NXP LPC1100 Scalable Entry Level 32-bit Microcontroller (MCU) based on Arm Cortex-M0 Cores Data Sheet

PDF

Dokument

Reklama

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB

SRAM

Rev. 7 — 26 September 2013 Product data sheet

The LPC1102/1104 are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures.

The LPC1102/1104 operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC1102/1104 includes 32 kB of flash memory, 8 kB of data memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four general purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.

Remark: The LPC1104 has a revised pinout and contains several features not found in the LPC1102:

• Two extra GPIO pins (PIO0_1 and PIO0_6).

• Extra match output (CT32B0_MAT2).

• CLKOUT feature.

• Easier re-entry to ISP via PIO0_1.

• SSP0_CLK available on two pins (A1 and A2) to support debugging of SSP communication.

• Better positioning of the XTALIN pin for easier PCB layout.

2. Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Serial Wire Debug.

 System tick timer.

 Memory:

 32 kB on-chip flash programming memory.

 8 kB SRAM.

 In-Application Programming (IAP) and In-System Programming (ISP) support via on-chip bootloader software.

 Digital peripherals:

 11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors and programmable open-drain mode.

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

 GPIO pins can be used as edge and level sensitive interrupt sources.

 Four general purpose counter/timers with a total of one capture input and 10 match outputs.

 Programmable windowed WatchDog Timer (WDT).

 Analog peripherals:

 10-bit ADC with input multiplexing among five pins.

 Serial interfaces:

 UART with fractional baud rate generation, internal FIFO, and RS-485 support.

 One SPI controller with SSP features and with FIFO and multi-protocol capabilities

(see Section 7.16

 Clock generation:

 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.

 Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.

 PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from an external clock or the internal RC oscillator.

 Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock (LPC1104 only).

 Power control:

 Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep and Deep-sleep modes.

 Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call.

 Two reduced power modes: Sleep and Deep-sleep modes.

 Processor wake-up from Deep-sleep mode via a dedicated start logic using up to six of the functional pins.

 Power-On Reset (POR).

 Brownout detect with up to four separate thresholds for interrupt and forced reset.

 Unique device serial number for identification.

 Single 3.3 V power supply (1.8 V to 3.6 V).

 Available as WLCSP16 package.

3. Applications

 Mobile devices

 Consumer peripherals

 Lighting

 8-/16-bit applications

 Portable devices

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

2 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

Table 1.

Ordering information

Type number Package

Name

LPC1102UK

LPC1104UK

WLCSP16

Description wafer level chip-size package; 16 bumps; 2.17

 2.32  0.6 mm wafer level chip-size package; 16 bumps; 2.17

 2.32  0.6 mm

4.1 Ordering options

Table 2.

Ordering options

Type number Flash

LPC1102UK

LPC1104UK

32 kB

Total

SRAM

8 kB

UART

RS-485

SPI

ADC channels

Version

Package

WLCSP16

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

3 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

GPIO port

PIO0/1

RXD

TXD

CT32B0_MAT[3,2

(1)

,1,0]

CT32B1_MAT[2:0]

CT32B1_CAP0

CT16B0_MAT[2:0]

SWD

XTALIN

RESET

LPC1102/1104

TEST/DEBUG

INTERFACE

ARM

CORTEX-M0 system bus

HIGH-SPEED

GPIO slave

UART

32-bit COUNTER/TIMER 0

32-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

16-bit COUNTER/TIMER 1

FLASH

32 kB slave

AHB-LITE BUS

IRC

POR

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS clocks and controls slave

SRAM

8 kB slave

ROM slave

AHB TO APB

BRIDGE

10-bit ADC

SPI

WDT

IOCONFIG

SYSTEM CONTROL

PMU

002aaf524

CLKOUT

(1)

AD[4:0]

SCK0,

MISO0,

MOSI0

(1) LPC1104 only.

(2) CT32B0_MAT2 LPC1104 only.

Fig 1.

LPC1102/1104 block diagram

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

4 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

6.1 Pinning

LPC1102/1104UK

B ball A1 index area

Fig 2.

Pin configuration WLCSP16 package

2 3 4

002aaf525

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

5 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

6.2 Pin description

Table 3.

LPC1102/1104 pin description table

Symbol

RESET/PIO0_0

LPC1102 LPC1104 Start

C1 [2] B2 [2]

logic input yes I

Type Reset state

[1]

Description

PIO0_1/CLKOUT/

CT32B0_MAT2

PIO0_6/SCK0

PIO0_8/MISO/

CT16B0_MAT0

PIO0_9/MOSI/

CT16B0_MAT1

SWCLK/

PIO0_10/

SCK0/CT16B0_MAT2

R/PIO0_11/

AD0/CT32B0_MAT3

R/PIO1_0/

AD1/CT32B1_CAP0

R/PIO1_1/

AD2/CT32B1_MAT0

yes yes yes yes yes yes yes no

I/O

I; PU RESET — External reset input with 20 ns glitch filter. A LOW -going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.

PIO0_0 — General purpose digital input/output pin.

I; PU PIO0_1 — General purpose digital input/output pin.

A LOW level on this pin during reset starts the ISP command handler.

I;PU

CLKOUT — Clockout pin.

CT32B0_MAT2 — Match output 2 for 32-bit timer 0.

PIO0_6 — General purpose digital input/output pin.

SCK0 — Serial clock for SPI0.

I; PU PIO0_8 — General purpose digital input/output pin.

MISO0 — Master In Slave Out for SPI.

CT16B0_MAT0 — Match output 0 for 16-bit timer 0.

I; PU PIO0_9 — General purpose digital input/output pin.

MOSI0 — Master Out Slave In for SPI.

CT16B0_MAT1 — Match output 1 for 16-bit timer 0.

I; PU SWCLK — Serial wire clock.

PIO0_10 — General purpose digital input/output pin.

SCK0 — Serial clock for SPI0.

CT16B0_MAT2 — Match output 2 for 16-bit timer 0.

I; PU R — Reserved.

PIO0_11 — General purpose digital input/output pin.

AD0 — A/D converter, input 0.

CT32B0_MAT3 — Match output 3 for 32-bit timer 0.

I; PU R — Reserved.

PIO1_0 — General purpose digital input/output pin.

AD1 — A/D converter, input 1.

CT32B1_CAP0 — Capture input 0 for 32-bit timer

I; PU R — Reserved.

PIO1_1 — General purpose digital input/output pin.

AD2 — A/D converter, input 2.

CT32B1_MAT0 — Match output 0 for 32-bit timer 1.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

6 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

Table 3.

LPC1102/1104 pin description table …continued

Symbol

R/PIO1_2/

AD3/CT32B1_MAT1

LPC1102 LPC1104 Start

C3 [4] C3 [4]

logic input no -

Type

I/O -

Reset state [1]

I; PU

Description

R — Reserved.

PIO1_2 — General purpose digital input/output pin.

SWDIO/PIO1_3/AD4/

CT32B1_MAT2

D4 [4] D4 [4]

I/O

I; PU

AD3 — A/D converter, input 3.

CT32B1_MAT1 — Match output 1 for 32-bit timer 1.

SWDIO — Serial wire debug input/output.

PIO1_3 — General purpose digital input/output pin.

PIO1_6/RXD/

CT32B0_MAT0

PIO1_7/TXD/

CT32B0_MAT1

XTALIN

D2; A1

D3; B1

no no

I/O

I; PU

AD4 — A/D converter, input 4.

CT32B1_MAT2 — Match output 2 for 32-bit timer 1.

PIO1_6 — General purpose digital input/output pin.

RXD — Receiver input for UART.

CT32B0_MAT0 — Match output 0 for 32-bit timer 0.

I; PU PIO1_7 — General purpose digital input/output pin.

TXD — Transmitter output for UART.

CT32B0_MAT1 — Match output 1 for 32-bit timer 0.

3.3 V supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage.

External clock input and input to internal clock generator circuits. Input voltage must not exceed

1.8 V.

Ground.

[1] Pin state at reset for default function: I = Input; PU = internal pull-up enabled (pins pulled up to full V

level (V

= 3.3 V)).

[2] 5 V tolerant pad. See

Figure 22 for the reset pad configuration.

[3]

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 21 ).

[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see

Figure 21

[5] When the external clock is not used, connect XTALIN as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise).

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

7 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

7.1 ARM Cortex-M0 processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption.

7.2 On-chip flash program memory

The LPC1102/1104 contain 32 kB of on-chip flash memory.

Remark: The LPC1102 supports In-Application Programming (IAP) and In-System

Programming (ISP). For ISP, since there is no dedicated ISP entry pin, user code is required to invoke ISP functionality. Unprogrammed parts will automatically boot into ISP mode.

7.3 On-chip SRAM

The LPC1102/1104 contain 8 kB on-chip static RAM memory.

7.4 Memory map

The LPC1102/1104 incorporate several distinct memory regions, shown in the following

figures. Figure 3

shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.

The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

8 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

LPC1102/1104 reserved private peripheral bus reserved

AHB peripherals

0x5020 0000

4 GB

1 GB

0.5 GB

0 GB

AHB peripherals reserved

APB peripherals reserved reserved

16 kB boot ROM reserved

8 kB SRAM reserved

32 kB on-chip flash

0xFFFF FFFF

0xE010 0000

0xE000 0000

0x5020 0000

0x5000 0000

0x4008 0000

0x4000 0000

0x2000 0000

0x1FFF 4000

0x1FFF 0000

0x1000 2000

0x1000 0000

0x0000 8000

0x0000 0000

127 - 16 reserved

15-12

11-8

7-4

3-0 reserved reserved

GPIO PIO1

GPIO PIO0

0x5004 0000

0x5003 0000

0x5002 0000

0x5001 0000

0x5000 0000

APB peripherals

31 - 23 reserved reserved

21 - 19 reserved system control

IOCONFIG

SPI flash controller

PMU

0x4008 0000

0x4005 C000

0x4005 8000

0x4004 C000

0x4004 8000

0x4004 4000

0x4004 0000

0x4003 C000

0x4003 8000

13 - 10 reserved reserved reserved

ADC

32-bit counter/timer 1

32-bit counter/timer 0

16-bit counter/timer 1

16-bit counter/timer 0

UART

WDT reserved

0x4002 8000

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000 active interrupt vectors

0x0000 00C0

0x0000 0000

002aaf526

Fig 3.

LPC1102/1104 memory map

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

7.5.1 Features

LPC1102_1104

Product data sheet

• Controls system exceptions and peripheral interrupts.

• In the LPC1102/1104, the NVIC supports 19 vectored interrupts including up to 6 inputs to the start logic from individual GPIO pins.

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

9 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

• Four programmable interrupt priority levels, with hardware priority level masking.

• Software interrupt generation.

7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Any GPIO pin (total of up to 11 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both.

7.6 IOCONFIG block

The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

7.7 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation.

The LPC1102/1104 use accelerated GPIO functions:

• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved.

• Entire port value can be written in one instruction.

Additionally, any GPIO pin (total of 11 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both.

7.7.1 Features

• Bit level port registers allow a single instruction to set or clear any number of bits in one write operation.

• Direction control of individual bits.

• All I/O default to inputs with pull-ups enabled after reset.

• Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin.

• All GPIO pins are pulled up to 3.3 V (V

= 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block.

• Programmable open-drain mode.

7.8 UART

The LPC1102/1104 contain one UART.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

10 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode.

The UART includes a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.8.1 Features

• Maximum UART data bit rate of 3.125 Mbit/s.

• 16 Byte Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.

• FIFO control mechanism that enables software flow control implementation.

• Support for RS-485/9-bit mode.

7.9 SPI serial I/O controller

The LPC1102/1104 contain one SPI controller and fully supports SSP features.

The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.

Remark: Care must be taken when using the SPI because the SPI clock SCK and the serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the

SPI is enabled, the serial wire debugger is no longer available (LPC1102 only).

7.9.1 Features

• Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

7.10 10-bit ADC

The LPC1102/1104 contain one ADC. It is a single 10-bit successive approximation ADC with five channels.

7.10.1 Features

• 10-bit successive approximation ADC.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

11 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

• Input multiplexing among 5 pins.

• Power-down mode.

• Measurement range 0 V to V

• 10-bit conversion time

 2.44 s (up to 400 kSamples/s).

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or timer match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

7.11 General purpose external event counter/timers

The LPC1102/1104 include two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.

7.11.1 Features

• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.

• Counter or timer operation.

• One capture channel that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt.

• Four match registers per timer that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

7.12 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).

7.13 Windowed WatchDog Timer

The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window.

7.13.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out period.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

12 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

• Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.

• Selectable time period from (T cy(WDCLK) multiples of T cy(WDCLK)

 4.

 256  4) to (T cy(WDCLK)

 2 24  4) in

• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated watchdog oscillator (WDO). This gives a wide range of potential timing choices of watchdog operation under different power conditions.

7.14 Clocking and power control

7.14.1 Crystal oscillators

The LPC1102/1104 include two independent oscillators. These are the Internal RC oscillator (IRC) and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application.

Following reset, the LPC1102/1104 operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.

See

Figure 4 for an overview of the LPC1102/1104 clock generation.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

13 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

AHB clock 0

(system)

SYSTEM CLOCK

DIVIDER system clock

AHBCLKCTRL[1:18]

(AHB clock enable)

AHB clocks 1 to 18

(memories and peripherals)

IRC oscillator watchdog oscillator main clock

SPI0 PERIPHERAL

CLOCK DIVIDER

UART PERIPHERAL

CLOCK DIVIDER

SPI0

UART

MAINCLKSEL

(main clock select)

IRC oscillator external clock

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM PLL

IRC oscillator watchdog oscillator

WDTUEN

(WDT clock update enable)

WDT CLOCK

DIVIDER

WDT

IRC oscillator system oscillator watchdog oscillator

CLKOUT PIN CLOCK

DIVIDER

CLKOUT pin

CLKOUTUEN

(CLKOUT update enable)

002aaf527

Fig 4.

LPC1102/1104 clock generation block diagram

7.14.1.1

Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC1102/1104 use the IRC as the clock source.

Software may later switch to one of the other available clock sources.

7.14.1.2

Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU or the watchdog timer. The watchdog oscillator nominal frequency is programmable between

9.4 kHz to 2.3 MHz. The frequency spread over processing and temperature is

40 %.

7.14.2 System PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

14 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller its frequency range while the PLL is providing the desired output frequency. The PLL output frequency must be lower than 100 MHz. The output divider may be set to divide by

2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.

The PLL settling time is 100

s.

7.14.3 Clock output (LPC1104 only)

The LPC1104 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.14.4 Wake-up process

The LPC1102/1104 begin operation at power-up by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If an external clock or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.

7.14.5 Power control

The LPC1102/1104 support a variety of power control features. There are two special modes of processor power reduction: Sleep mode and Deep-sleep mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control.

7.14.5.1

Power profiles

The power consumption in Active and Sleep modes can be optimized for the application through a simple call to the power profiles. The power configuration routine configures the

LPC1102/1104 for one of the following power modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profiles includes a routine to select the optimal PLL settings for a given system clock and PLL input clock.

7.14.5.2

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

15 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.

7.14.5.3

Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down except for the watchdog oscillator and the BOD circuit, which can be configured to remain running in Deep-sleep mode to allow a reset initiated by a timer or BOD event.

Deep-sleep mode allows for additional power savings.

Six of the GPIO pins (see Table 3 ) serve as external wake-up pins to a dedicated start

logic to wake up the chip from Deep-sleep mode.

The clock source should be switched to IRC before entering Deep-sleep mode unless the watchdog oscillator remains running in Deep-sleep mode. The IRC can be switched on and off glitch-free and provides a clean clock signal after start-up.

7.15 System control

7.15.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in

Table 3

as input to the start logic has an individual interrupt in the NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC before being used.

7.15.2 Reset

Reset has four sources on the LPC1102/1104: the RESET pin, the Watchdog reset,

Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. In addition, there is an ARM software reset. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

7.15.3 Brownout detection

The LPC1102/1104 include up to four levels for monitoring the voltage on the V

pin. If this voltage falls below one of the three selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable

Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

16 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

CAUTION

7.15.4 Code security (Code Read Protection - CRP)

This feature of the LPC1102/1104 allow user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0). This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update.

3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins.

Remark: The LPC1102 does not provide an ISP entry pin to be monitored at reset. For all three CRP levels, the user’s application code must provide a flash update mechanism which reinvokes ISP by defining a user-selected PIOn pin for ISP entry.

If Code Read Protection of any level (CRP1, CRP2 or CRP3) is selected, no future factory testing can be performed on the device.

7.15.5 APB interface

The APB peripherals are located on one APB bus.

7.15.6 AHBLite

The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM.

7.15.7 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as external interrupts (see Section 7.15.1

7.16 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported.

Remark: Care must be taken when using the SPI because the SPI clock SCK and the serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the

SPI is enabled, the serial wire debugger is no longer available (LPC1102 only).

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

17 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol

Parameter supply voltage (core and external rail) input voltage

Conditions

IA analog input voltage

5 V tolerant I/O pins; V

 1.8 V

= 0 V pin configured as analog input

[2]

[2][3]

Min

0.5

Max

+4.6

+5.5

[2][4]

0.5

+3.6

0.5 +4.6

Unit

SS latch supply current ground current

I/O latch-up current per supply pin per ground pin

(0.5V

) < V

(1.5V

);

T j

< 125

C non-operating

[5]

100

100 mA mA mA

T stg

T j(max)

P tot(pack) storage temperature maximum junction temperature total power dissipation (per package)

[6]

65

+150

150

1.5

C

ESD electrostatic discharge voltage based on package heat transfer, not device power consumption human body model; all pins

[7]

6500 V

[1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise noted.

c) The limiting values are stress ratings only. Operating the part at these values is not recommended and proper operation is not

guaranteed. The conditions for functional operation are specified in Table 5 .

[2]

Maximum/minimum voltage above the maximum operating voltage (see Table 5

) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] Including voltage on outputs in 3-state mode.

[4] See

Table 6 for maximum operating voltage.

[5] The peak current is limited to 25 times the corresponding maximum current.

[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k

 series resistor.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

18 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

Table 5.

Static characteristics

T amb





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions

DD supply voltage (core and external rail)

DD supply current Active mode; code while(1){} executed from flash

I system clock = 12 MHz

= 3.3 V system clock = 50 MHz

= 3.3 V

Sleep mode; system clock = 12 MHz

= 3.3 V

Deep-sleep mode;

= 3.3 V

Standard port pins, RESET

LOW-level input current V

= 0 V; on-chip pull-up resistor disabled

IL hys

HIGH-level input current

OFF-state output current input voltage output voltage

HIGH-level input voltage

LOW-level input voltage pin configured to provide a digital function;

 1.8 V; 5 V tolerant pins

= 0 V output active hysteresis voltage

HIGH-level output voltage

= V

; on-chip pull-down resistor disabled

= 0 V; V

= V

; on-chip pull-up/down resistors disabled

LOW-level output voltage

2.5 V

 V

4 mA

 3.6 V;

1.8 V

 V

3 mA

< 2.5 V;

2.5 V

 V

 3.6 V;

= 4 mA

1.8 V

 V

< 2.5 V;

= 3 mA

Min

1.8

[9]

0.7V

Typ

[1]

3.3

0.5

 0.4

0.4

 0.4

Max

3.6

5.0

Unit

A nA nA nA

0.4

3.6

0.3V

V mA mA mA

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

19 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

Table 5.

Static characteristics …continued

T amb





C to +85



C, unless otherwise specified.

Symbol Parameter

OHS

HIGH-level output current

LOW-level output current

HIGH-level short-circuit output current

Conditions

= V

 0.4 V;

2.5 V

 V

 3.6 V

1.8 V

 V

< 2.5 V

= 0.4 V

2.5 V

 V

 3.6 V

1.8 V

 V

< 2.5 V

= 0 V

OLS

= V

I pd

I pu

LOW-level short-circuit output current pull-down current pull-up current

= 5 V

= 0 V;

2.0 V

 V

 3.6 V

1.8 V

 V

< 2.0 V

< V

< 5 V

External clock input

V i(xtal) crystal input voltage

[11]

Min

4

3

15

10

Typ [1]

50

Max

45

150

85

Unit mA mA mA mA mA mA

A

0.5

1.8

1.95

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

[2] T amb

= 25

C.

[3] I

measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.

[4] IRC enabled; external clock disabled; system PLL disabled.

[5] BOD disabled.

[6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[7] IRC disabled; system oscillator enabled; system PLL enabled.

[8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. Before entering deep-sleep mode, you must write a 0 to bit 4 and bit 5 of the GPIO0DATA register at location 0x5000 3FFC and a 1 to bit 4 and bit 5 of the

GPIO0DIR register at location 0x5000 8000.

[9] Including voltage on outputs in 3-state mode.

[10] V

supply voltage must be present.

[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

20 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

Table 6.

ADC static characteristics

T amb





C to +85



C unless otherwise specified; ADC frequency 4.5 MHz, V

= 2.5 V to 3.6 V.

Symbol Parameter Conditions Min Typ

R vsi

C ia

L(adj) analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error

R i voltage source interface resistance input resistance

[7][8]

Max

1

1.5

3.5

0.6

4

2.5



[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (E

) is the difference between the actual step width and the ideal step width. See

Figure 5 .

[3] The integral non-linearity (E

L(adj)

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See

Figure 5 .

[4] The offset error (E

) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 5

[5] The gain error (E

) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 5

[6] The absolute error (E

) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

ADC and the ideal transfer curve. See Figure 5

[7] T amb

= 25

C; maximum sampling frequency f s

= 400 kSamples/s and analog input capacitance C ia

= 1 pF.

[8] Input resistance R i

depends on the sampling frequency f s

: R i

= 1 / (f s

 C ia

Unit

V pF

LSB

LSB k



LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

21 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller offset error

O gain error

1020

1019

1018

1023

1022

1021

(2) code out

1 offset error

2 3

(4)

(5)

(3)

1 LSB

(ideal)

5 6 7

(LSB ideal

)

(1)

1018 1019 1020 1021 1022 1023 1024

1 LSB =

− V

1024

002aaf426

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (E

(4) Integral non-linearity (E

L(adj)

(5) Center of a step of the actual transfer curve.

Fig 5.

ADC characteristics

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

22 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

9.1 BOD static characteristics

Table 7.

BOD static characteristics

T amb

= 25



[1]

Symbol Parameter Conditions

V th threshold voltage interrupt level 1 assertion de-assertion interrupt level 2 assertion de-assertion interrupt level 3 assertion de-assertion reset level 0 assertion de-assertion reset level 1 assertion de-assertion reset level 2 assertion de-assertion reset level 3 assertion de-assertion

Min Typ

2.22

2.35

2.52

2.66

2.80

2.90

1.46

1.63

2.06

2.15

2.35

2.43

2.63

2.71

Max Unit

[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see User

manual UM10429.

9.2 Power consumption

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see user manual UM10429):

• All digital pins configured as GPIO with pull-up resistor disabled in the IOCONFIG block.

• GPIO pins configured as outputs using the GPIOnDIR registers.

• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

• Write a 1 to bit 4 and bit 5 of the GPIO0DIR register at location 0x5000 8000 and a 0 to bit 4 and bit 5 of the GPIO0DATA register at location 0x5000 3FFC. This ensures that not-bonded out pins are in a well-defined state.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

23 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

48 MHz

(2)

36 MHz

(2)

24 MHz

(2)

12 MHz

(1)

002aaf980

(mA)

1.8

2.4

3.0

3.6

(V)

Conditions: T amb

= 25

C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

(1) System PLL disabled; IRC enabled.

(2) System PLL enabled; IRC disabled.

Fig 6.

Active mode: Typical supply current I

versus supply voltage V

for different system clock frequencies

002aaf981

(mA)

48 MHz

(2)

36 MHz

(2)

24 MHz

(2)

12 MHz

(1)

−

15 10 35 60 temperature ( ° C)

Conditions: V

= 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

(1) System PLL disabled; IRC enabled.

(2) System PLL enabled; IRC disabled.

Fig 7.

Active mode: Typical supply current I

versus temperature for different system clock frequencies

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

24 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

002aaf982

(mA)

48 MHz

(2)

36 MHz

(2)

24 MHz

(2)

12 MHz

(1)

− 40 − 15 10 35 60 temperature ( ° C)

Conditions: V

= 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

(1) System PLL disabled; IRC enabled.

(2) System PLL enabled; IRC disabled.

Fig 8.

Sleep mode: Typical supply current I

versus temperature for different system clock frequencies

002aaf977

5.5

( μ A)

4.5

3.5

2.5

= 3.3 V, 3.6 V

1.8 V

1.5

−

15 10 35 60 temperature (

Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register

(PDSLEEPCFG = 0x0000 18FF).

Remark: Before entering deep-sleep mode, you must write a 0 to bit 4 and bit 5 of the GPIO0DATA register at location 0x5000 3FFC and a 1 to bit 4 and bit 5 of the GPIO0DIR register at location

0x5000 8000.

Fig 9.

Deep-sleep mode: Typical supply current I

versus temperature for different supply voltages V

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

25 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

9.3 CoreMark data

(mA)

11.2

8.4

5.6

2.8

mode 0 mode 1 mode 2 mode 3

002aah163

0 10 20 30 40 50 frequency (MHz)

External signal generator providing 1 MHz to 20 MHz signal drives the XTALIN input; when testing

1 MHz to 19 MHz the system PLL is OFF, SYSAHBCLKDIV = 1; when testing 20 MHz to 50 MHz the system PLL is configured so that SYSAHBCLKDIV = 1.

Fig 10. CoreMark current consumption for power modes 0, 1, 2, and 3

9.4 Electrical pin characteristics

(mA)

T = 85 ° C

−

002aae991

0 0.2

0.4

0.6

(V)

Conditions: V

= 3.3 V; standard port pins.

Fig 11. Typical LOW-level output current I

versus LOW-level output voltage V

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

26 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

T = 85

25 ° C

− 40 ° C

002aae992

3.6

(V)

3.2

2.8

2.4

0 8 16 24

(mA)

Conditions: V

= 3.3 V; standard port pins.

Fig 12. Typical HIGH-level output voltage V

versus HIGH-level output source current

002aae988

I pu

( μ A)

−

T = 85 ° C

−

0 1 2 3

Conditions: V

= 3.3 V; standard port pins.

Fig 13. Typical pull-up current I pu

versus input voltage V

(V)

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

27 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

T = 85 ° C

25 ° C

− 40 ° C

002aae989

I pd

(

0 1 2 3

Conditions: V

= 3.3 V; standard port pins.

Fig 14. Typical pull-down current I pd

versus input voltage V

(V)

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

28 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

10. Dynamic characteristics

10.1 Power-up ramp conditions

Table 8.

Power-up characteristics

T amb

40 C to +85 C. t

Symbol Parameter r rise time

Conditions at t = t

: 0 < V

 400 mV t wait wait time

I input voltage at t = t

on pin V

[1]

Min

[1][2]

0 -

Typ

Max

500

Unit ms

s

400 mV

[1] See

Figure 15 .

[2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up.

t r

400 mV

0 t = t

Condition: 0 < V

 400 mV at start of power-up (t = t

)

Fig 15. Power-up ramp t wait

002aag001

LPC1102_1104

Product data sheet

10.2 Flash memory

Table 9.

Flash characteristics

T amb





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions

N endu t ret endurance retention time t er erase time powered unpowered sector or multiple consecutive sectors t prog programming time

Min

[1]

10000

[2]

0.95

Typ

100 000 -

Max

100

105

1 1.05

Unit cycles years years ms ms

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

29 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

10.3 External clock

Table 10.

Dynamic characteristic: external clock

T amb





C to +85



C; V

over specified ranges.

[1]

Symbol Parameter Conditions Min f osc

T cy(clk) t

CHCX t

CLCX t

CLCH t

CHCL oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time -

T cy(clk)

 0.4

T cy(clk)

 0.4

Typ

[2]

Max

1000

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

ns ns ns ns

Unit

MHz ns t

CHCL t

CLCX

T cy(clk) t

CHCX t

CLCH

002aaa907

Fig 16. External clock timing (with an amplitude of at least V i(RMS)

= 200 mV)

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

30 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

10.4 Internal oscillators

Table 11.

Dynamic characteristic: internal oscillators

T amb





C to +85



C; 2.7 V



3.6 V.

[1]

Symbol Parameter Conditions f osc(RC) internal RC oscillator frequency -

Min

11.88

Typ [2]

Max

12.12

Unit

MHz

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

002aaf403

12.15

(MHz)

12.05

VDD = 3.6 V

3.3 V

3.0 V

2.7 V

2.4 V

2.0 V

11.95

11.85

−

15 10 35 60 temperature ( ° C)

Conditions: Frequency values are typical values. 12 MHz

 1 % accuracy is guaranteed for

2.7 V

 V

 3.6 V and T amb

40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz

 1 % accuracy specification for voltages below 2.7 V.

Fig 17. Internal RC oscillator frequency versus temperature

Table 12.

Dynamic characteristics: Watchdog oscillator

Symbol Parameter f osc(int) internal oscillator frequency

Conditions

DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register;

DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register

[2][3]

Min Typ

[1]

9.4

[2][3]

2300

Max Unit kHz kHz

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

[2] The typical frequency spread over processing and temperature (T amb

40 C to +85 C) is 40 %.

[3] See user manual UM10429.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

31 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

10.5 I/O pins

Table 13.

Dynamic characteristic: I/O pins [1]

T amb





C to +85



C; 3.0 V



3.6 V.

Symbol Parameter Conditions t r rise time t f fall time pin configured as output pin configured as output

[1] Applies to standard port pins and RESET pin.

Min

3.0

2.5

Typ Max

5.0

Unit ns ns

10.6 SPI interfaces

Table 14.

Dynamic characteristics of SPI pins in SPI mode

Symbol Parameter Conditions

SPI master (in SPI mode) t t t

T cy(clk)

DH v(Q) clock cycle time when only receiving

[1]

data set-up time data hold time when only transmitting data output valid time in SPI mode

[1]

in SPI mode

2.4 V

 V

 3.6 V

[2]

2.0 V

 V

< 2.4 V

[2]

1.8 V

 V

< 2.0 V

[2]

in SPI mode

[2]

t h(Q) data output hold time in SPI mode

SPI slave (in SPI mode) t

T cy(PCLK)

PCLK cycle time

DS data set-up time data hold time t

DH t v(Q) t h(Q) in SPI mode in SPI mode data output valid time in SPI mode data output hold time in SPI mode

[3][4]

Min

 T cy(PCLK)

+ 4 -

Typ

Max

 T cy(PCLK)

+ 11

 T cy(PCLK)

+ 5

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns

[1] T cy(clk)

= (SSPCLKDIV

 (1 + SCR)  CPSDVSR) / f main

. The clock cycle time derived from the SPI bit rate T cy(clk)

is a function of the main clock frequency f main

, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2] T amb

40 C to 85 C.

[3] T cy(clk)

= 12

 T cy(PCLK)

[4] T amb

= 25

C; for normal voltage supply range: V

= 3.3 V.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

32 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

T cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

MISO t v(Q)

DATA VALID

DATA VALID t

DS t

DATA VALID t h(Q)

CPHA = 1

MOSI t v(Q)

DATA VALID

DATA VALID t

DS t

DATA VALID t h(Q)

MISO

Fig 18. SPI master timing in SPI mode

CPHA = 0

002aae829

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

33 of 43

NXP Semiconductors

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

MISO

T cy(clk)

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

DATA VALID t v(Q)

DATA VALID t

DS t

DATA VALID

DATA VALID t h(Q) CPHA = 1

MOSI

MISO

DATA VALID t v(Q)

DATA VALID t

DS t

DATA VALID

DATA VALID t h(Q)

Fig 19. SPI slave timing in SPI mode

CPHA = 0

002aae830

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

34 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

11. Application information

11.1 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in

Table 6

• The ADC input trace must be short and as close as possible to the LPC1102/1104 chip.

• The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines.

• Because the ADC and the digital core share the same power supply, the power supply line must be adequately filtered.

• To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion.

11.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with

C i

= 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground C g

which attenuates the input voltage by a factor C i

/(C i

+ C g

). In slave mode, a minimum of 200 mV (RMS) is needed.

LPC1xxx

XTALIN

100 pF

002aae788

Fig 20. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

( Figure 20

), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

LPC1102_1104

Product data sheet

11.3 Standard I/O pad configuration

Figure 21

shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver

• Digital input: Pull-up enabled/disabled

• Digital input: Pull-down enabled/disabled

• Digital input: Repeater mode enabled/disabled

• Analog input

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

35 of 43

NXP Semiconductors

pin configured as digital output driver pin configured as digital input

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller open-drain enable output enable data output repeater mode enable pull-up enable pull-down enable

DD strong pull-up strong pull-down

ESD

DD weak pull-up weak pull-down

PIN data input pin configured as analog input analog input

Fig 21. Standard I/O pad configuration

11.4 Reset pad configuration

select analog input

Rpu

DD reset

20 ns RC

GLITCH FILTER

002aah159

ESD

002aaf274

LPC1102_1104

Product data sheet

Fig 22. Reset pad configuration

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

36 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

11.5 ADC effective input impedance

A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See

Figure 23

ADC Block

Source

ADC

COMPARATOR

Rmux

<2 k Ω

Rsw

<1.3 k Ω

Cia

Cio

Rin

VEXT

002aah615

Fig 23. ADC input channel

The effective input impedance, R in

, seen by the external voltage source, V

EXT

, is the parallel impedance of ((1/f s

x C ia

) + R mux

+ R sw

) and (1/f s

x C io

), and can be calculated

using Equation 1 with

f s

= sampling frequency

C ia

= ADC analog input capacitance

R mux

= analog mux resistance

R sw

= switch resistance

C io

= pin capacitance

R in

= f s



C ia

+ mux

+ R sw

  f

-----------------s



C io

 (1)

Under nominal operating condition V

= 3.3 V and with the maximum sampling frequency fs = 400 kHz, the parameters assume the following values:

C ia

= 1 pF (max)

R mux

= 2 k Ω (max)

R sw

= 1.3 k Ω (max)

C io

= 7.1 pF (max)

The effective input impedance with these parameters is R in

= 308 k Ω.

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

37 of 43

NXP Semiconductors

12. Package outline

WLCSP16: wafer level chip-size package; 16 bumps; body 2.17 x 2.32 x 0.6 mm

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

LPC1102UK

D B A ball A1 index area

E A

1 detail X e e

1/2 e b

∅ v

∅ w

A B

A ball A1 index area

1 2 3 4 e

1/2 e e

0 1 scale

Dimensions mm

Unit A A

2 b max nom min

0.65

0.60

0.55

0.27

0.24

0.21

0.38

0.36

0.34

0.35

0.32

0.29

D E

2.21

2.17

2.13

2.36

2.32

2.28

0.5

1.5

2 v w y

1.5

0.15

0.05

2 mm

Outline version

LPC1102UK

IEC

- - -

JEDEC

References

JEITA

- - - - -

Fig 24. Package outline LPC1102UK (WLCSP16)

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

European projection

C y

X lpc1102uk_po

Issue date

10-10-15

10-10-18

38 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

13. Abbreviations

Table 15.

Abbreviations

Acronym

ADC

Description

Analog-to-Digital Converter

AHB

APB

BOD

GPIO

Advanced High-performance Bus

Advanced Peripheral Bus

BrownOut Detection

General Purpose Input/Output

PLL

SPI

SSI

SSP

UART

Phase-Locked Loop

Resistor-Capacitor

Serial Peripheral Interface

Serial Synchronous Interface

Synchronous Serial Port

Universal Asynchronous Receiver/Transmitter

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

39 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

14. Revision history

Table 16.

Revision history

Document ID

LPC1102_1104 v.7

Modifications:

LPC1102_1104 v.6

Modifications:

LPC1102_1104 v.5

Modifications:

LPC1102 v.4

Modifications:

LPC1102 v.3

Modifications:

LPC1102 v.2

Modifications:

LPC1102 v.1

Release date Data sheet status Change notice Supersedes

20130926 Product data sheet LPC1102_1104 v.6

•

Parameter V

updated in Table 4

and Table 5 . Condition V

= 0 added.

•

Section 11.5 “ADC effective input impedance” added.

•

Removed t clk(H)

and t clk(L)

from

Figure 18 “SPI master timing in SPI mode” and

Figure

19 “SPI slave timing in SPI mode” ; spec not characterized.

20121231 Product data sheet LPC1102_1104 v.5

•

Added Section 9.3 “CoreMark data”.

•

Conditions for power consumption in Deep-sleep mode updated in Table 5, Table note 8 and Section 9.2.

•

Table 4 “Limiting values” expanded for clarity.

•

BOD reset level 0 added in Table 7.

20120727 Product data sheet LPC1102 v.4

•

Added LPC1104UK.

•

Removed footnote “The peak current is limited to 25 times the corresponding maximum current.” from Table 4.

•

For parameters I

 V

, V

, I

 3.6 V in Table 5).

, V

, changed conditions to 1.8 V

 V

< 2.5 V and 2.5

•

WDOSc frequency range corrected.

•

BOD level 0 removed in Table 7.

20110624 Product data sheet LPC1102 v.3

•

ADC sampling frequency corrected in Table 6 (Table note 7).

•

Parameter T cy(clk)

corrected on Table 14.

•

Windowed WDT features added (Section 7.13).

•

Programmable open-drain mode added to GPIO pins (Section 7.7).

•

Pull-up level specified in Table 3, Table note 1 and Section 7.7.

•

Condition for parameter T stg

in Table 4 updated.

•

Table note 4 of Table 4 updated.

20110418 Product data sheet LPC1102 v.2

•

Changed data sheet status to Product.

•

Power consumption data added (see Figure 6 to Figure 9).

•

Section 10.1 “Power-up ramp conditions” added.

•

Reset pad description updated (5 V tolerant) in Table 3.

•

IRC frequency data added (see Figure 16 “Internal RC oscillator frequency versus temperature”.

•

Clock output removed from feature list.

LPC1102 v.1

20101126 Preliminary data sheet -

•

Changed data sheet status to Preliminary.

20101116 Objective data sheet -

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

40 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

15. Legal information

Document status

[1][2]

Objective [short] data sheet

Product status

[3]

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

15.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

LPC1102_1104

Product data sheet

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

41 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

16. Contact information

product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

LPC1102_1104

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 26 September 2013

42 of 43

NXP Semiconductors

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller

17. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4.1

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.1

6.2

Pinning information . . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Functional description . . . . . . . . . . . . . . . . . . . 8

ARM Cortex-M0 processor . . . . . . . . . . . . . . . . 8

On-chip flash program memory . . . . . . . . . . . . 8

On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . 8

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Nested Vectored Interrupt Controller (NVIC) . . 9

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 10

IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 10

Fast general purpose parallel I/O . . . . . . . . . . 10

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.9

7.9.1

SPI serial I/O controller. . . . . . . . . . . . . . . . . . 11

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.10 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.11 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.12 System tick timer . . . . . . . . . . . . . . . . . . . . . . 12

7.13 Windowed WatchDog Timer . . . . . . . . . . . . . . 12

7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.14 Clocking and power control . . . . . . . . . . . . . . 13

7.14.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 13

7.14.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 14

7.14.1.2 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 14

7.14.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7.14.3 Clock output (LPC1104 only) . . . . . . . . . . . . . 15

7.14.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 15

7.14.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.14.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 15

7.14.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.14.5.3 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 16

7.15 System control . . . . . . . . . . . . . . . . . . . . . . . . 16

7.15.1 Start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.15.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.15.3 Brownout detection . . . . . . . . . . . . . . . . . . . . . 16

7.15.4 Code security (Code Read Protection - CRP) 17

7.15.5 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.15.6 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.1

Emulation and debugging . . . . . . . . . . . . . . . 17

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 18

Static characteristics . . . . . . . . . . . . . . . . . . . 19

BOD static characteristics . . . . . . . . . . . . . . . 23

Power consumption . . . . . . . . . . . . . . . . . . . 23

CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 26

Electrical pin characteristics. . . . . . . . . . . . . . 26

Dynamic characteristics. . . . . . . . . . . . . . . . . 29

Power-up ramp conditions . . . . . . . . . . . . . . . 29

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 29

External clock. . . . . . . . . . . . . . . . . . . . . . . . . 30

Internal oscillators . . . . . . . . . . . . . . . . . . . . . 31

I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 32

Application information . . . . . . . . . . . . . . . . . 35

ADC usage notes . . . . . . . . . . . . . . . . . . . . . . 35

XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Standard I/O pad configuration . . . . . . . . . . . 35

Reset pad configuration . . . . . . . . . . . . . . . . . 36

ADC effective input impedance . . . . . . . . . . . 37

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 38

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39

Revision history . . . . . . . . . . . . . . . . . . . . . . . 40

Legal information . . . . . . . . . . . . . . . . . . . . . . 41

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Contact information . . . . . . . . . . . . . . . . . . . . 42

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 26 September 2013

Document identifier: LPC1102_1104

Witaj! Jestem chatbotem AI specjalnie przeszkolonym, aby pomóc Ci w obsłudze NXP LPC1100 Scalable Entry Level 32-bit Microcontroller (MCU) based on Arm Cortex-M0 Cores Data Sheet. Dokładnie przejrzałem dokument i mogę pomóc Ci zlokalizować dokładne informacje, których potrzebujesz, lub wyjaśnić treść w jasny i prosty sposób. Niezależnie od tego, czy szukasz wskazówek dotyczących konkretnych funkcji, kroków rozwiązywania problemów, czy ogólnego użytkowania, możesz zadawać pytania. Im więcej szczegółów podasz na temat swoich obaw lub potrzeb, tym dokładniej i skuteczniej mogę Ci pomóc!

Asystent pisze

Asystent jest niedostępny. Spróbuj ponownie później.

Reklama