NXP i.MX31 Applications Processors - Integrated Image Processing Unit (IPU), Connectivity , Arm11™ Core Data Sheet

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Dokument

Oglas

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCIMX31_5

Rev. 4.3, 12/2009

MCIMX31 and

MCIMX31L

MCIMX31 and

MCIMX31L

Multimedia Applications

Processors

Package Information

Plastic Package

Case 1581 14 x 14 mm, 0.5 mm Pitch

Case 1931 19 x 19 mm, 0.8 mm Pitch

Ordering Information

See Table 1 on page 3

for ordering information.

1 Introduction

The MCIMX31 and MCIMX31L multimedia applications processors represent the next step in low-power, high-performance application processors.

Unless otherwise specified, the material in this data sheet is applicable to both the MCIMX31 and MCIMX31L processors and referred to singularly throughout this document as MCIMX31. The MCIMX31L does not include a graphics processing unit (GPU).

Based on an ARM11™ microprocessor core, the

MCIMX31 provides the performance with low power consumption required by modern digital devices.

The MCIMX31 takes advantage of the

ARM1136JF-S™ core running at up to 532 MHz, and is optimized for minimal power consumption using the most advanced techniques for power saving (DPTC,

DVFS, power gating, clock gating). With 90 nm technology and dual-Vt transistors (two threshold voltages), the MCIMX31 provides the optimal performance versus leakage current balance.

The performance of the MCIMX31 is boosted by a multi-level cache system, and features peripheral devices

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering Information . . . . . . . . . . . . . . . . . . . . 3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional Description and Application

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

ARM11 Microprocessor Core . . . . . . . . . . . . . . 4

Module Inventory. . . . . . . . . . . . . . . . . . . . . . . . 6

Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . 9

Electrical Characteristics . . . . . . . . . . . . . . . . 10

Chip-Level Conditions . . . . . . . . . . . . . . . . . . 10

Supply Power-Up/Power-Down Requirements and

Restrictions . . . . . . . . . . . . . . . . . . . . . . . 18

Module-Level Electrical Specifications . . . . . . 20

Package Information and Pinout . . . . . . . . . 103

MAPBGA Production Package—457 14 x 14 mm,

0.5 mm Pitch . . . . . . . . . . . . . . . . . . . . . 103

MAPBGA Production Package—473 19 x 19 mm,

0.8 mm Pitch . . . . . . . . . . . . . . . . . . . . . 109

Ball Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Product Documentation . . . . . . . . . . . . . . . . 117

Revision History . . . . . . . . . . . . . . . . . . . . . . . 117

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Introduction such as an MPEG-4 Hardware Encoder (VGA, 30 fps), an Autonomous Image Processing Unit, a Vector

Floating Point (VFP11) co-processor, and a RISC-based SDMA controller.

The MCIMX31 supports connections to various types of external memories, such as DDR, NAND Flash,

NOR Flash, SDRAM, and SRAM. The MCIMX31 can be connected to a variety of external devices using technology, such as high-speed USB2.0 OTG, ATA, MMC/SDIO, and compact flash.

1.1

Features

The MCIMX31 is designed for the high-tier, mid-tier smartphone markets, and portable media players.

They provide low-power solutions for high-performance demanding multimedia and graphics applications.

The MCIMX31 is built around the ARM11 MCU core and implemented in the 90 nm technology.

The systems include the following features:

• Multimedia and floating-point hardware acceleration supporting:

— MPEG-4 real-time encode of up to VGA at 30 fps

— MPEG-4 real-time video post-processing of up to VGA at 30 fps

— Video conference call of up to QCIF-30 fps (decoder in software), 128 kbps

— Video streaming (playback) of up to VGA-30 fps, 384 kbps

— 3D graphics and other applications acceleration with the ARM

tightly-coupled Vector

Floating Point co-processor

— On-the-fly video processing that reduces system memory load (for example, the power-efficient viewfinder application with no involvement of either the memory system or the

ARM CPU)

• Advanced power management

— Dynamic voltage and frequency scaling

— Multiple clock and power domains

— Independent gating of power domains

• Multiple communication and expansion ports including a fast parallel interface to an external graphic accelerator (supporting major graphic accelerator vendors)

• Security

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Introduction

1.2

Ordering Information

Table 1

provides the ordering information for the MCIMX31.

Table 1. Ordering Information

Part Number Silicon Revision

2, 3, 4,5

Device Mask

Operating Temperature

Range (

Package

MCIMX31DVKN5D !

MCIMX31LDVKN5D !

MCIMX31CVKN5D !

MCIMX31LCVKN5D !

2.0.1

M91E

–20 to 70

–40 to 85

14 x 14 mm,

0.5 mm pitch,

MAPBGA-457,

Case 1581

MCIMX31DVMN5D

MCIMX31LDVMN5D

2.0.1

M91E

–20 to 70

19 x 19 mm,

0.8 mm pitch,

Case 1931

MCIMX31CJKN5D

MCIMX31LCJKN5D

2.0.1

M91E

–40 to 85

14 x 14 mm,

0.5 mm pitch,

MAPBGA-457,

Case 1581

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010:

Indicated by the Icon ( !

)

Information on reading the silicon revision register can be found in the IC Identification (IIM) chapter of the Reference Manual, see

Section 6, “Product Documentation

.”

Errata and fix information of the various mask sets can be found in the standard MCIMX31 Chip Errata, see Section 6, “Product

Documentation .”

Changes in output buffer characteristics can be found in the I/O Setting Exceptions and Special Pad Descriptions table in the

Reference Manual, see

Section 6, “Product Documentation .”

JTAG functionality is not tested nor guaranteed at -40°C.

Case 1581 and 1931 are RoHS compliant, lead-free, MSL = 3.

1.2.1 Feature Differences Between Mask Sets

There are no silicon differences between revisions 2.0 and 2.0.1. The main difference is an updated iROM code which supports USB-HS, SD/MMC boot modes and corrects some boot mode related erratas.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Functional Description and Application Information

1.3

Block Diagram

Figure 1

shows the MCIMX31 simplified interface block diagram.

SRAM, PSRAM, SDRAM NAND Flash,

NOR Flash

DDR

SmartMedia

Camera

Sensor (2)

Parallel

Display (2)

Serial

LCD Tamper

Detection

External Memory

Interface (EMI)

SDMA

Internal

Memory

ARM11

Platform

ARM1136JF-S

I-Cache

D-Cache

L2-Cache

MAX

ROMPATCH

VFP

ETM

MPEG-4

Video Encoder

Image Processing Unit (IPU)

Inversion and Rotation

Camera Interface

Blending

Display/TV Ctl

Pre and Post Processing

Expansion

SDHC (2)

PCMCIA/CF

Mem Stick (2)

SIM

ATA

Timers

RTC

WDOG

GPT

EPIT (2)

Debug

ECT

SJC

Security

SCC

RTIC

RNGA

* GPU unavailable for i.MX31L

AP Peripherals

AUDMUX

SSI (2)

UART (5)

C (3)

FIR

CSPI (3)

PWM

USB Host (2)

USB-OTG

KPP

GPIO

CCM

1-WIRE ®

IIM

GPU*

Mouse

Keyboard

Power

Management

8 x 8

Keypad

Serial

EPROM

GPS

ATA

Hard Drive

Fast

IrDA

Bluetooth Baseband WLAN

Card

USB

Host/Device

Figure 1. MCIMX31 Simplified Interface Block Diagram

2 Functional Description and Application Information

2.1

ARM11 Microprocessor Core

The CPU of the MCIMX31 is the ARM1136JF-S core based on the ARM v6 architecture. It supports the

ARM Thumb

instruction sets, features Jazelle

technology (which enables direct execution of Java byte codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.

The ARM1136JF-S processor core features:

• Integer unit with integral EmbeddedICE

™

logic

• Eight-stage pipeline

• Branch prediction with return stack

• Low-interrupt latency

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Functional Description and Application Information

• Instruction and data memory management units (MMUs), managed using micro TLB structures backed by a unified main TLB

• Instruction and data L1 caches, including a non-blocking data cache with Hit-Under-Miss

• Virtually indexed/physically addressed L1 caches

• 64-bit interface to both L1 caches

• Write buffer (bypassable)

• High-speed Advanced Micro Bus Architecture (AMBA)

™

L2 interface

• Vector Floating Point co-processor (VFP) for 3D graphics and other floating-point applications hardware acceleration

• ETM

™

and JTAG-based debug support

2.1.1 Memory System

The ARM1136JF-S complex includes 16 KB Instruction and 16 KB Data L1 caches. It connects to the

MCIMX31 L2 unified cache through 64-bit instruction (read-only), 64-bit data read/write (bi-directional), and 64-bit data write interfaces.

The embedded 16K SRAM can be used for audio streaming data to avoid external memory accesses for the low-power audio playback, for security, or for other applications. There is also a 32-KB ROM for bootstrap code and other frequently-used code and data.

A ROM patch module provides the ability to patch the internal ROM. It can also initiate an external boot by overriding the boot reset sequence by a jump to a configurable address.

Table 2

shows information about the MCIMX31 core in tabular form.

Table 2. MCIMX31 Core

Core

Acronym

Core

Name

Brief Description

Integrated Memory

Includes

ARM11 or

ARM1136

Platform

The ARM1136™ Platform consists of the ARM1136JF-S core, the ETM real-time debug modules, a 6 x 5 multi-layer AHB crossbar switch (MAX), and a Vector Floating Processor (VFP).

The MCIMX31 provides a high-performance ARM11 microprocessor core and highly integrated system functions. The ARM Application Processor (AP) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities.

• 16 Kbyte Instruction

Cache

• 16 Kbyte Data

Cache

• 128 Kbyte L2 Cache

• 32 Kbyte ROM

• 16 Kbyte RAM

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Functional Description and Application Information

2.2

Module Inventory

Table 3

shows an alphabetical listing of the modules in the multimedia applications processor. For extended descriptions of the modules, see the reference manual. A cross-reference is provided to the electrical specifications and timing information for each module with external signal connections.

Table 3. Digital and Analog Modules

Block

Mnemonic

Block Name

Functional

Grouping

Brief Description

Section/

Page

1-Wire® 1-Wire Interface Connectivity

Peripheral

The 1-Wire module provides bi-directional communication between the ARM11 core and external 1-Wire devices.

ATA Advanced

Technology (AT)

Attachment

Connectivity

Peripheral

The ATA block is an AT attachment host interface. It is designed to interface with IDE hard disc drives and ATAPI optical disc drives.

AUDMUX Digital Audio

Multiplexer

Multimedia

Peripheral

The AUDMUX interconnections allow multiple, simultaneous audio/voice/data flows between the ports in point-to-point or point-to-multipoint configurations.

4.3.4/24

4.3.5/25

4.3.6/34

CAMP

CCM

CSPI

DPLL

Clock Amplifier

Module

Clock Control

Module

Clock

The CAMP converts a square wave/sinusoidal input into a rail-to-rail square wave. The output of CAMP feeds the predivider.

The CCM provides clock, reset, and power management control for the MCIMX31.

Configurable

Serial Peripheral

Interface (x 3)

Connectivity

Peripheral

The CSPI is equipped with data FIFOs and is a master/slave configurable serial peripheral interface module, capable of interfacing to both SPI master and slave devices.

Digital Phase

Lock Loop

Clock

ECT Embedded

Cross Trigger

Debug

The DPLLs produce high-frequency on-chip clocks with low frequency and phase jitters.

Note: External clock sources provide the reference frequencies.

The ECT is composed of three CTIs (Cross Trigger Interface) and one CTM (Cross Trigger Matrix—key in the multi-core and multi-peripheral debug strategy.

EMI

EPIT

ETM

FIR

4.3.3/23

—

4.3.7/34

4.3.8/35

—

External

Memory

Interface

Memory

Interface

(EMI)

The EMI includes

• Multi-Master Memory Interface (M3IF)

• Enhanced SDRAM Controller (ESDCTL)

• NAND Flash Controller (NFC)

• Wireless External Interface Module (WEIM)

The EPIT is a 32-bit “set and forget” timer which starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention.

—

4.3.9.3/44 ,

4.3.9.1/36 ,

4.3.9.2/39

— Enhanced

Periodic

Interrupt Timer

Embedded

Trace Macrocell

Debug/Trace The ETM (from ARM, Ltd.) supports real-time instruction and data tracing by way of ETM auxiliary I/O port.

Fast InfraRed

Interface

Timer

Peripheral

Connectivity

Peripheral

This FIR is capable of establishing a 0.576 Mbit/s, 1.152 Mbit/s or 4

Mbit/s half duplex link via a LED and IR detector. It supports 0.576

Mbit/s, 1.152 Mbit/s medium infrared (MIR) physical layer protocol and 4Mbit/s fast infrared (FIR) physical layer protocol defined by

IrDA, Rev. 1.4.

4.3.10/52

4.3.11/53

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Functional Description and Application Information

Table 3. Digital and Analog Modules (continued)

Block

Mnemonic

Block Name

Functional

Grouping

Brief Description

Section/

Page

Fusebox

GPIO

GPT

GPU

IIM

Fusebox ROM The Fusebox is a ROM that is factory configured by Freescale.

The GPIO provides several groups of 32-bit bidirectional, general purpose I/O. This peripheral provides dedicated general-purpose signals that can be configured as either inputs or outputs.

The GPT is a multipurpose module used to measure intervals or generate periodic output.

4.3.12/53

3 Signal Descriptions

Signal descriptions are in the reference manual. Special signal considerations are listed following this paragraph. The BGA ball assignment is in

Section 5, “Package Information and Pinout .”

Special Signal Considerations:

• Tamper detect (GPIO1_6)

Tamper detect logic is used to issue a security violation. This logic is activated if the tamper detect input is asserted.

The tamper detect logic is disabled after reset. After enabling the logic, it is impossible to disable it until the next reset. The GPR[16] bit functions as the tamper detect enable bit.

GPIO1_6 functions similarly to other I/O with GPIO capabilities regardless of the status of the tamper detect enable bit. (For example, the GPIO1_6 can function as an input with GPIO capabilities, such as sampling through PSR or generating interrupts.)

• Power ready (GPIO1_5)

The power ready input, GPIO1_5, should be connected to an external power management IC power ready output signal. If not used, GPIO1_5 must either be (a) externally pulled-up to NVCC1 or (b) a no connect, internally pulled-up by enabling the on-chip pull-up resistor. GPIO1_5 is a dedicated input and cannot be used as a general-purpose input/output.

• SJC_MOD

SJC_MOD must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 k

Ω) is allowed, but the value should be much smaller than the on-chip 100 k

Ω pull-up.

• CE_CONTROL

CE_CONTROL is a reserved input and must be externally tied to GND through a 1 k

Ω resistor.

• TTM_PAD

This is for Freescale factory use only. Control bits indicate that the pull-up/down is disabled.

However, the TTM_PAD is actually connected to an on-chip pull-down device. Users must either float this signal or tie it to GND.

• M_REQUEST and M_GRANT

These two signals are not utilized internally. The user should make no connection to these signals.

• Clock Source Select (CLKSS)

The CLKSS is the input that selects the default reference clock source providing input to the DPLL.

To select CKIH, tie CLKSS to NVCC1. To select CKIL, tie CLKSS to ground. After initialization, the reference clock source can be changed (initial setting is overwritten) by programming the

PRCS bits in the CCMR.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4 Electrical Characteristics

This section provides the device-level and module-level electrical characteristics for the MCIMX31.

4.1

Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See

Table 4

for a quick reference to the individual tables and sections.

Table 4. MCIMX31 Chip-Level Conditions

For these characteristics, …

Table 5, “Absolute Maximum Ratings”

Table 7 , “Thermal Resistance Data—19

19 mm Package”

Table 8, “Operating Ranges”

Table 9

“Specific Operating Ranges for Silicon Revision 2.0.1”

Table 10, “Interface Frequency”

Section 4.1.1, “Supply Current Specifications”

Section 4.2, “Supply Power-Up/Power-Down Requirements and Restrictions”

Topic appears …

on page 10

on page 11

on page 13

on page 14 on page 14

on page 16

on page 18

CAUTION

Stresses beyond those listed under Table 5 may cause permanent damage to

the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under

Table 8,

"Operating Ranges," on page 13

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Table 5. Absolute Maximum Ratings

Parameter Symbol Min Max

Supply Voltage (Core)

Supply Voltage (I/O)

Input Voltage Range

Storage Temperature

ESD Damage Immunity:

Human Body Model (HBM)

Machine Model (MM)

Charge Device Model (CDM)

Offset voltage allowed in run mode between core supplies.

QVCC

NVCC

V storage

V max max

Imax esd

V core_offset

–0.5

–40

—

1.65

3.3

NVCC +0.3

125

1500

200

500

The offset is the difference between all core voltage pair combinations of QVCC, QVCC1, and QVCC4.

Units

V o

V mV

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 6

provides the thermal resistance data for the 14

× 14 mm, 0.5 mm pitch package.

Table 6. Thermal Resistance Data—14

14 mm Package

Rating

Junction to Ambient (natural convection)

Junction to Ambient (@200 ft/min)

Junction to Board

Junction to Case

Junction to Package Top (natural convection)

Board

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

Symbol Value Unit

θ JA

JMA

Notes

°C/W 1, 2, 3

°C/W 1, 3

°C/W 1, 2, 3

°C/W 1, 3

°C/W

1, 4

1, 5

1, 6

NOTES

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 7

provides the thermal resistance data for the 19

× 19 mm, 0.8 mm pitch package.

Table 7. Thermal Resistance Data—19

19 mm Package

Rating

Junction to Ambient (natural convection)

Junction to Ambient (@200 ft/min)

Junction to Board

Junction to Case (Top)

Junction to Package Top (natural convection)

Board

Single layer board (1s)

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

—

Symbol

R θ

θ JMA

R θ

JMA

θ JB

JCtop

Value

Unit

°C/W

Notes

1, 2, 3

1, 3

1, 4

1, 5

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

NOTES

2. Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6.

Thermal test board meets JEDEC specification for this package.

3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.

4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

5. Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 8

provides the operating ranges.

NOTE

The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter of the reference manual.

CAUTION

NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity.

Table 8. Operating Ranges

Symbol

QVCC,

QVCC1,

QVCC4

Parameter

Core Operating Voltage

1,2,3

≤ f

ARM

≤ f

ARM

≤ f

ARM

≤

400 MHz, non-overdrive

≤

532 MHz, non-overdrive

≤

532 MHz, overdrive

State Retention Voltage

I/O Supply Voltage, except DDR

6 non-overdrive overdrive

NVCC1,

NVCC3–10

NVCC2,

NVCC21,

NVCC22

I/O Supply Voltage, DDR only

FVCC, MVCC,

SVCC, UVCC

PLL (Phase-Locked Loop) and FPM (Frequency Pre-multiplier) Supply Voltage

8 non-overdrive overdrive

IOQVDD

FUSE_VDD

On-device Level Shifter Supply Voltage

Fusebox read Supply Voltage

9, 10

Fusebox write (program) Supply Voltage

Operating Ambient Temperature Range

Min

1.22

1.38

1.52

0.95

1.75

>3.1

1.75

1.3

>1.47

1.6

1.65

3.0

–20

Max

1.47

1.52

1.65

—

3.1

3.3

1.95

1.47

1.6

1.9

1.95

3.3

Units o

Measured at package balls, including peripherals, ARM, and L2 cache supplies (QVCC, QVCC1, QVCC4, respectively).

The core voltage must be higher than 1.38V to avoid corrupted data during transfers from the USB HS. Please refer to Errata file ENGcm02610 ID.

If the Core voltage is supplied by the MC13738, it will be 1.6 ± 0.05 V during the power-up sequence and this is allowed. After power-up the voltage should be reduced to avoid operation in overdrive mode.

Supply voltage is considered “overdrive” for voltages above 1.52 V. Operation time in overdrive—whether switching or not—must be limited to a cumulative duration of 1.25 years (10,950 hours) or less to sustain the maximum operating voltage without significant device degradation—for example, 25% (average 6 hours out of 24 yours per day) duty cycle for 5-year rated equipment. To tolerate the maximum operating overdrive voltage for 10 years, the device must have a duty cycle of 12.5% or less in overdrive (for example 3 out of 24 hours per day). Below 1.52 V, duty cycle restrictions may apply for equipment rated above 5 years.

The SR voltage is applied to QVCC, QVCC1, and QVCC4 after the device is placed in SR mode. The Real-Time Clock (RTC) is operational in State Retention (SR) mode.

Overshoot and undershoot conditions (transitions above NVCC and below GND) on I/O must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Supply voltage is considered “overdrive” for voltages above 3.1 V. Operation time in overdrive—whether switching or not—must be limited to a cumulative duration of 1 year (8,760 hours) or less to sustain the maximum operating voltage without significant device degradation—for example, 20% (average 4.8 hours out of 24 hours per day) duty cycle for 5-year rated equipment. Operation at 3.3 V that exceeds a cumulative 3,504 hours may cause non-operation whenever supply voltage is reduced to 1.8 V; degradation may render the device too slow or inoperable. Below 3.1 V, duty cycle restrictions may apply for equipment rated above 5 years.

For normal operating conditions, PLLs’ and core supplies must maintain the following relation: PLL

≥

Core – 100 mV. In other words, for a 1.6 V core supply, PLL supplies must be set to 1.5 V or higher. This restriction is no longer necessary on mask set M91E. PLL supplies may be set independently of core supply. PLL voltage must not be altered after power up, otherwise the PLL will be unstable and lose lock. To minimize inducing noise on the PLL supply line, source the voltage from a low-noise,

dedicated supply. PLL parameters in Table 30, "DPLL Specifications," on page 35

, are guaranteed over the entire specified voltage range.

Fusebox read supply voltage applies to silicon Revisions 1.2 and previous.

In read mode, FUSE_VDD can be floated or grounded for mask set M91E (silicon Revision 2.0.1).

Fuses might be inadvertently blown if written to while the voltage is below this minimum.

The temperature range given is for the consumer version. Please refer to

Table 1 for extended temperature range offerings

and the associated part numbers.

Table 9. Specific Operating Ranges for Silicon Revision 2.0.1

Symbol

FUSE_VDD

Parameter

Fusebox read Supply Voltage

Fusebox write (program) Supply Voltage

In read mode, FUSE_VDD should be floated or grounded.

Fuses might be inadvertently blown if written to while the voltage is below the minimum.

Min

—

3.0

Max

—

3.3

Units

Table 10

provides information for interface frequency limits. For more details about clocks characteristics,

see Section 4.3.8, “DPLL Electrical Specifications

,” and Section 4.3.3, “Clock Amplifier Module

(CAMP) Electrical Characteristics .”

Table 10. Interface Frequency

ID Parameter Symbol Min Typ Max Units

JTAG TCK Frequency

CKIL Frequency

CKIH Frequency

2 f

JTAG f

CKIL f

CKIH

32.768

38.4

MHz kHz

MHz

CKIL must be driven by an external clock source to ensure proper start-up and operation of the device. CKIL is needed to clock the internal reset synchronizer, the watchdog, and the real-time clock.

DPTC functionality, specifically the voltage/frequency relation table, is dependent on CKIH frequency. At the time of publication, standard tables used by Freescale OSs provided for a CKIH frequency of 26 MHz only. Any deviation from this frequency requires an update to the OS. For more details, refer to the particular OS user's guide documentation.

Table 11 shows the fusebox supply current parameters.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 11. Fusebox Supply Current Parameters

Ref. Num

Description eFuse Program Current.

Current to program one eFuse bit: efuse_pgm = 3.0 V eFuse Read Current

Current to read an 8-bit eFuse word vdd_fusebox = 1.875 V

Symbol

I program

I read

Minimum

—

Typical

Maximum

Units mA mA

The current I program

is during program time (t program

The current I read and previous.

is present for approximately 50 ns of the read access to the 8-bit word, and only applies to Silicon Rev. 1.2

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.1.1 Supply Current Specifications

Table 12

shows the core current consumption for –40

°C to 85°C for Silicon Revision 2.0.1 for the

MCIMX31.

Table 12. Current Consumption for –40 ° C to 85 ° C

1, 2

for Silicon Revision 2.0.1

Mode Conditions

QVCC

(Peripheral)

QVCC1

(ARM)

QVCC4

(L2)

FVCC + MVCC

+ SVCC + UVCC

(PLL) Unit

Typ Max Typ Max Typ Max Typ

0.16

5.50

— — — — 0.02

Max

0.10

mA Deep

Sleep

• QVCC = 0.95 V

• ARM and L2 caches are power gated

(QVCC1 = QVCC4 = 0 V)

• All PLLs are off, VCC = 1.4 V

• ARM is in well bias

• FPM is off

• 32 kHz input is on

• CKIH input is off

• CAMP is off

• TCK input is off

• All modules are off

• No external resistive loads

• RNGA oscillator is off

State

Retention

• QVCC and QVCC1 = 0.95 V

• L2 caches are power gated (QVCC4 = 0 V)

• All PLLs are off, VCC = 1.4 V

• ARM is in well bias

• FPM is off

• 32 kHz input is on

• CKIH input is off

• CAMP is off

• TCK input is off

• All modules are off

• No external resistive loads

• RNGA oscillator is off

Wait • QVCC,QVCC1, and QVCC4 = 1.22 V

• ARM is in wait for interrupt mode

• MAX is active

• L2 cache is stopped but powered

• MCU PLL is on (532 MHz), VCC = 1.4 V

• USB PLL and SPLL are off, VCC = 1.4 V

• FPM is on

• CKIH input is on

• CAMP is on

• 32 kHz input is on

• All clocks are gated off

• All modules are off

(by programming CGR[2:0] registers)

• RNGA oscillator is off

• No external resistive loads

Typical column: TA = 25

Maximum column: TA = 85

0.16

5.50

0.07

2.20

— — 0.02

6.00

15.00

2.20

25.00

0.03

0.29

3.60

0.10

4.40

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 13

shows the core current consumption for –20

°C to 70°C for Silicon Revision 2.0.1 for the

MCIMX31.

Table 13. Current Consumption for –20 ° C to 70 ° C

1, 2

for Silicon Revision 2.0.1

Mode Conditions

QVCC

(Peripheral)

QVCC1

(ARM)

QVCC4

(L2)

FVCC, +MVCC,

+SVCC, +UVCC

Typ Max Typ Max Typ Max Typ

0.16

— — — — — 0.02

(PLL)

Max

—

Unit mA Deep

Sleep

• QVCC = 0.95 V

• ARM and L2 caches are power gated

(QVCC1 2= QVCC4 = 0 V)

• All PLLs are off, VCC = 1.4 V

• ARM is in well bias

• FPM is off

• 32 kHz input is on

• CKIH input is off

• CAMP is off

• TCK input is off

• All modules are off

• No external resistive loads

• RNGA oscillator is off

State

Retention

• QVCC and QVCC1 = 0.95 V

• L2 caches are power gated (QVCC4 = 0 V)

• All PLLs are off, VCC = 1.4 V

• ARM is in well bias

• FPM is off

• 32 kHz input is on

• CKIH input is off

• CAMP is off

• TCK input is off

• All modules are off

• No external resistive loads

• RNGA oscillator is off

Wait • QVCC,QVCC1, and QVCC4 = 1.22 V

• ARM is in wait for interrupt mode

• MAX is active

• L2 cache is stopped but powered

• MCU PLL is on (532 MHz), VCC = 1.4 V

• USB PLL and SPLL are off, VCC = 1.4 V

• FPM is on

• CKIH input is on

• CAMP is on

• 32 kHz input is on

• All clocks are gated off

• All modules are off

(by programming CGR[2:0] registers)

• RNGA oscillator is off

• No external resistive loads

Typical column: TA = 25

Maximum column: TA = 70

0.16

6.00

— 0.07

— — —

— 2.20

— 0.03

—

0.02

3.60

—

— mA mA

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.2

Supply Power-Up/Power-Down Requirements and Restrictions

Any MCIMX31 board design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences may result in any or all of the following situations:

• Cause excessive current during power up phase

• Prevent the device from booting

• Cause irreversible damage to the MCIMX31 (worst-case scenario)

4.2.1 Powering Up

The Power On Reset (POR) pin must be kept asserted (low) throughout the power up sequence. Power up logic must guarantee that all power sources reach their target values prior to the release (de-assertion) of

POR.

Figure 2 and Figure 3 show the power-up sequence for silicon Revision 2.0.1.

NOTE

Stages need to be performed in the order shown; however, within each stage, supplies can be powered up in any order. For example, supplies IOQVDD,

NVCC1, and NVCC3 through NVCC10 do not need to be powered up in the order shown.

CAUTION

NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

4.2.1.1

Power-Up Sequence for Silicon Revision 2.0.1

Hold POR Asserted

QVCC, QVCC1, QVCC4

NVCC2, NVCC21, NVCC22

1, 3, 5

IOQVDD, NVCC1, NVCC3–10

1, 2

FVCC, MVCC, SVCC, UVCC

1,3

Notes:

The board design must guarantee that supplies reach

90% level before transition to the next state, using Power

Management IC or other means.

The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions.

The parallel paths in the flow indicate that supply group

NVCC2, NVCC21, and NVCC22, and supply group

FVCC, MVCC, SVCC, and UVCC ramp-ups are independent.

FUSE_VDD should not be driven on power-up for Silicon

Revision 2.0.1. This supply is dedicated for fuse burning

(programming), and should not be driven upon boot-up.

Raising IOQVDD before NVCC21 produces a slight increase in current drain on IOQVDD of approximately

3–5 mA. The current increase will not damage the IC.

Refer to Errata ID TLSbo91750 for details.

Release POR

Figure 2. Option 1 Power-Up Sequence (Silicon Revision 2.0.1)

Hold POR Asserted

QVCC, QVCC1, QVCC4

IOQVDD, NVCC1, NVCC3–10, NVCC2, NVCC21, NVCC22

1, 2,3

Notes:

The board design must guarantee that supplies reach

90% level before transition to the next state, using Power

Management IC or other means.

The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions.

Raising NVCC2, NVCC21, and NVCC22 at the same time as IOQVDD does not produce the slight increase in current drain on IOQVDD (as described in

Figure 2 ,

Note 5).

FUSE_VDD should not be driven on power-up for Silicon

Revision 2.0.1. This supply is dedicated for fuse burning

(programming), and should not be driven upon boot-up.

FVCC, MVCC, SVCC, UVCC

Release POR

Figure 3. Option 2 Power-Up Sequence (Silicon Revision 2.0.1)

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.2.2 Powering Down

For silicon revisions beginning with Revision 2.0.1 there is no special requirements for the power down sequence.

4.3

Module-Level Electrical Specifications

This section contains the MCIMX31 electrical information including timing specifications, arranged in alphabetical order by module name.

4.3.1 I/O Pad (PADIO) Electrical Specifications

This section specifies the AC/DC characterization of functional I/O of the MCIMX31. There are two main types of I/O: regular and DDR. In this document, the “Regular” type is referred to as GPIO.

4.3.1.1

DC Electrical Characteristics

The MCIMX31 I/O parameters appear in

Table 14 for GPIO. See

Table 8

for temperature and supply voltage ranges.

NOTE

The term NVCC in this section refers to the associated supply rail of an input or output. The association is shown in the Signal Multiplexing chapter

of the reference manual. NVCC for Table 14

refers to NVCC1 and

NVCC3–10; QVCC refers to QVCC, QVCC1, and QVCC4.

Table 14. GPIO DC Electrical Parameters

Parameter

High-level output voltage

Low-level output voltage

High-level output current, slow slew rate

High-level output current, fast slew rate

Low-level output current, slow slew rate

Symbol

OH_S

OH_F

OL_S

Test Conditions Min

= –1 mA

= 1 mA

NVCC –0.15

= specified Drive 0.8*NVCC

—

— I

= specified Drive

=0.8*NVCC

Std Drive

High Drive

Max Drive

–2

–4

–8

=0.8*NVCC

Std Drive

High Drive

Max Drive

=0.2*NVCC

Std Drive

High Drive

Max Drive

–4

–6

–8

Typ

—

Max

—

0.15

0.2*NVCC

—

Units

V mA

—

— mA mA

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

High-Level DC input voltage

Low-Level DC input voltage

Input Hysteresis

Schmitt trigger VT+

Schmitt trigger VT–

Pull-up resistor (100 k

PU)

Pull-down resistor (100 k

PD)

Input current (no PU/PD)

Input current (100 k

PU)

Table 14. GPIO DC Electrical Parameters (continued)

Min Parameter

Low-level output current, fast slew rate

Input current (100 k

PD)

Tri-state leakage current

Symbol

OL_F

–

HYS

Test Conditions

=0.2*NVCC

Std Drive

High Drive

Max Drive

—

Hysteresis enabled

—

= NVCC or GND

= 0

= NVCC

= 0

= NVCC

= NVCC or GND

I/O = High Z

—

0.7*NVCC

0.25

0.5*QVCC

—

Typ

—

100

—

Max

—

NVCC

0.3*QVCC

—

0.5*QVCC

—

0.1

0.25

Units mA

V k

The MCIMX31 I/O parameters appear in Table 15 for DDR (Double Data Rate). See

Table 8, "Operating

Ranges," on page 13

for temperature and supply voltage ranges.

NOTE

NVCC for

Table 15 refers to NVCC2, NVCC21, and NVCC22.

Table 15. DDR (Double Data Rate) I/O DC Electrical Parameters

Parameter

High-level output voltage

Low-level output voltage

High-level output current

Low-level output current

Symbol Test Conditions

= –1 mA

= 1 mA

= specified Drive

=0.8*NVCC

Std Drive

High Drive

Max Drive

DDR Drive

=0.2*NVCC

Std Drive

High Drive

Max Drive

DDR Drive

Min

NVCC –0.12

= specified Drive 0.8*NVCC

—

–3.6

–7.2

–10.8

–14.4

3.6

7.2

10.8

14.4

Typ

—

Max

—

0.08

0.2*NVCC

—

Units

V mA

— mA

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 15. DDR (Double Data Rate) I/O DC Electrical Parameters (continued)

Parameter

High-Level DC input voltage

Low-Level DC input voltage

Tri-state leakage current

Symbol Test Conditions

—

= NVCC or GND

I/O = High Z

Use of DDR Drive can result in excessive overshoot and ringing.

Min Typ Max Units

0.7*NVCC NVCC NVCC+0.3

–0.3

—

0.3*NVCC

4.3.2 AC Electrical Characteristics

Figure 4

depicts the load circuit for outputs.

Figure 5 depicts the output transition time waveform. The

range of operating conditions appears in

Table 16

for slow general I/O, Table 17 for fast general I/O, and

Table 18

for DDR I/O (unless otherwise noted).

From Output

Under Test

Test Point

CL includes package, probe and fixture capacitance

Figure 4. Load Circuit for Output

Output (at I/O)

80% 80%

NVCC

20%

PA1 PA1

Figure 5. Output Transition Time Waveform

20%

Table 16. AC Electrical Characteristics of Slow

General I/O

PA1

Parameter

Output Transition Times (Max Drive)

Output Transition Times (High Drive)

Output Transition Times (Std Drive)

Symbol tpr tpr tpr

Test

Condition

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

Min

0.92

1.5

1.52

2.75

2.79

5.39

Typ

1.95

2.98

—

Max

3.17

4.75

4.81

8.42

8.56

16.43

Fast/slow characteristic is selected per GPIO (where available) by “slew rate” control. See reference manual.

Units ns ns ns

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 17. AC Electrical Characteristics of Fast

General I/O

Parameter

PA1 Output Transition Times (Max Drive)

Output Transition Times (High Drive)

Output Transition Times (Std Drive)

Symbol tpr tpr tpr

Test

Condition

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

Min

0.68

1.34

.91

1.79

1.36

2.68

Typ

1.33

2.6

1.77

3.47

2.64

5.19

Fast/slow characteristic is selected per GPIO (where available) by “slew rate” control. See reference manual.

Use of GPIO in fast mode with the associated NVCC > 1.95 V can result in excessive overshoot and ringing.

Max

2.07

4.06

2.74

5.41

4.12

8.11

Units ns ns ns

Table 18. AC Electrical Characteristics of DDR I/O

Parameter

PA1 Output Transition Times (DDR Drive)

Output Transition Times (Max Drive)

Output Transition Times (High Drive)

Output Transition Times (Std Drive)

Symbol tpr tpr tpr tpr

Test

Condition

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

Min

0.51

0.97

0.67

1.29

.99

1.93

1.96

3.82

Use of DDR Drive can result in excessive overshoot and ringing.

Typ

0.82

1.58

1.08

2.1

1.61

3.13

3.19

6.24

Max

1.28

2.46

1.69

3.27

2.51

4.89

4.99

9.73

Units ns ns ns ns

4.3.3 Clock Amplifier Module (CAMP) Electrical Characteristics

This section outlines the Clock Amplifier Module (CAMP) specific electrical characteristics.

Table 19

shows clock amplifier electrical characteristics.

Table 19. Clock Amplifier Electrical Characteristics for CKIH Input

Parameter

Input Frequency

VIL (for square wave input)

VIH (for square wave input)

Sinusoidal Input Amplitude

Duty Cycle

Min

(VDD

– 0.25)

0.4

Typ

—

Max

0.3

VDD

Units

MHz

Vp-p

VDD is the supply voltage of CAMP. See reference manual.

This value of the sinusoidal input will be measured through characterization.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.3.4 1-Wire Electrical Specifications

Figure 6

depicts the RPP timing, and

Table 20 lists the RPP timing parameters.

1-Wire bus

(BATT_LINE)

OWIRE Tx

“Reset Pulse”

DS2502 Tx

“Presence Pulse”

OW2

OW1 OW3

OW4

Figure 6. Reset and Presence Pulses (RPP) Timing Diagram

OW1

OW2

OW3

OW4

Table 20. RPP Sequence Delay Comparisons Timing Parameters

Parameters

Reset Time Low

Presence Detect High

Presence Detect Low

Reset Time High

Symbol t

RSTL t

PDH t

PDL t

RSTH

Min

480

Typ

511

—

512

Max

—

240

—

Figure 7 depicts Write 0 Sequence timing, and Table 21 lists the timing parameters.

OW6

1-Wire bus

(BATT_LINE)

Units

µs

OW5

Figure 7. Write 0 Sequence Timing Diagram

OW5

OW6

Table 21. WR0 Sequence Timing Parameters

Parameter

Write 0 Low Time

Transmission Time Slot

Symbol t

WR0_low t

SLOT

Min

OW5

Typ

100

117

Max

120

Units

µs

Figure 8

depicts Write 1 Sequence timing,

Figure 9

depicts the Read Sequence timing, and

Table 22

lists the timing parameters.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

OW8

1-Wire bus

(BATT_LINE)

OW7

Figure 8. Write 1 Sequence Timing Diagram

OW8

1-Wire bus

(BATT_LINE)

OW7

OW8

OW9

OW7

OW9

Figure 9. Read Sequence Timing Diagram

Table 22. WR1/RD Timing Parameters

Parameter

Write 1 / Read Low Time

Transmission Time Slot

Release Time

Symbol t

LOW1 t

SLOT t

RELEASE

Min

Typ

117

—

Max

120

Units

µs

4.3.5 ATA Electrical Specifications (ATA Bus, Bus Buffers)

This section discusses ATA parameters. For a detailed description, refer to the ATA specification.

The user needs to use level shifters for 3.3 Volt or 5.0 Volt compatibility on the ATA interface.

The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast

UDMA mode operation is needed, this may not be compatible with bus buffers.

Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.

According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.

When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.3.5.1

Timing Parameters

In the timing equations, some timing parameters are used. These parameters depend on the implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.

Table 23 shows ATA

timing parameters.

Table 23. ATA Timing Parameters

Name

T Bus clock period (ipg_clk_ata)

Description

Value/

Contributing Factor

1 peripheral clock frequency ti_ds ti_dh tco

Set-up time ata_data to ata_iordy edge (UDMA-in only)

UDMA0

UDMA1

UDMA2, UDMA3

UDMA4

UDMA5

Hold time ata_iordy edge to ata_data (UDMA-in only)

UDMA0, UDMA1, UDMA2, UDMA3, UDMA4

UDMA5

Propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en tsu tsui

Set-up time ata_data to bus clock L-to-H

Set-up time ata_iordy to bus clock H-to-L thi Hold time ata_iordy to bus clock H to L tskew1 Max difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data

(write), ata_buffer_en tskew2 Max difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data

(write), ata_buffer_en tskew3 Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data

(read) tbuf Max buffer propagation delay tcable1 Cable propagation delay for ata_data tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack tskew4 Max difference in cable propagation delay between ata_iordy and ata_data (read) tskew5 Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) tskew6 Max difference in cable propagation delay without accounting for ground bounce

Values provided where applicable.

15 ns

10 ns

7 ns

5 ns

4 ns

5.0 ns

4.6 ns

12.0 ns

8.5 ns

2.5 ns

7 ns transceiver transceiver transceiver cable cable cable cable cable

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

4.3.5.2

PIO Mode Timing

Figure 10 shows timing for PIO read, and Table 24 lists the timing parameters for PIO read.

Figure 10. PIO Read Timing Diagram

Table 24. PIO Read Timing Parameters

ATA

Parameter

from Figure 10

t9 t5 t1 t2 t1 t2r t9 t5 t6 tA trd t0 t6 tA trd1

—

Value

Controlling

Variable t1 (min) = time_1 * T – (tskew1 + tskew2 + tskew5) t2 min) = time_2r * T – (tskew1 + tskew2 + tskew5) t9 (min) = time_9 * T – (tskew1 + tskew2 + tskew6) t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

0 tA (min) = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf) trd1 (max) = (–trd) + (tskew3 + tskew4) trd1 (min) = (time_pio_rdx – 0.5)*T – (tsu + thi)

(time_pio_rdx – 0.5) * T > tsu + thi + tskew3 + tskew4 t0 (min) = (time_1 + time_2 + time_9) * T

time_1 time_2r time_3

If not met, increase time_2

— time_ax time_pio_rdx time_1, time_2r, time_9

Figure 11 shows timing for PIO write, and Table 25 lists the timing parameters for PIO write.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Figure 11. Multiword DMA (MDMA) Timing

Table 25. PIO Write Timing Parameters

ATA

Parameter

Parameter from

Figure 11

t9 t3 t1 t2 t1 t2w t9

— t4 tA t0

—

— t4 tA

—

Value

Controlling

Variable t1 (min) = time_1 * T – (tskew1 + tskew2 + tskew5) t2 (min) = time_2w * T – (tskew1 + tskew2 + tskew5) t9 (min) = time_9 * T – (tskew1 + tskew2 + tskew6) t3 (min) = (time_2w – time_on)* T – (tskew1 + tskew2 +tskew5) t4 (min) = time_4 * T – tskew1 tA = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf) t0(min) = (time_1 + time_2 + time_9) * T

Avoid bus contention when switching buffer on by making ton long enough.

Avoid bus contention when switching buffer off by making toff long enough.

time_1 time_2w time_9

If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9

—

Figure 12

shows timing for MDMA read,

Figure 13 shows timing for MDMA write, and Table 26

lists the timing parameters for MDMA read and write.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Figure 12. MDMA Read Timing Diagram

ATA

Parameter tm, ti td tk t0 tg(read) tf(read) tg(write) tf(write) tL tn, tj

—

Figure 13. MDMA Write Timing Diagram

Table 26. MDMA Read and Write Timing Parameters tfr

—

— tkjn ton toff

Parameter from

Figure 12 ,

Figure 13

tm td, td1 tk

— tgr

Value tm (min) = ti (min) = time_m * T – (tskew1 + tskew2 + tskew5) td1.(min) = td (min) = time_d * T – (tskew1 + tskew2 + tskew6) tk.(min) = time_k * T – (tskew1 + tskew2 + tskew6) t0 (min) = (time_d + time_k) * T tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min-drive) = td – te(drive) tfr (min-drive) = 0 tg (min-write) = time_d * T – (tskew1 + tskew2 + tskew5) tf (min-write) = time_k * T – (tskew1 + tskew2 + tskew6) tL (max) = (time_d + time_k–2)*T – (tsu + tco + 2*tbuf + 2*tcable2) tn= tj= tkjn = (max(time_k,. time_jn) * T – (tskew1 + tskew2 + tskew6) ton = time_on * T – tskew1 toff = time_off * T – tskew1

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Controlling

Variable time_m time_d time_k time_d, time_k time_d

— time_d time_k time_d, time_k time_jn

—

Electrical Characteristics

4.3.5.3

UDMA In Timing

Figure 14 shows timing when the UDMA in transfer starts, Figure 15 shows timing when the UDMA in

host terminates transfer, Figure 16 shows timing when the UDMA in device terminates transfer, and

Table 27

lists the timing parameters for UDMA in burst.

Figure 14. UDMA In Transfer Starts Timing Diagram

Figure 15. UDMA In Host Terminates Transfer Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Figure 16. UDMA In Device Terminates Transfer Timing Diagram

Table 27. UDMA In Burst Timing Parameters

ATA

Parameter tack tenv

— tmli tzah tdzfs tds tdh tcyc trp tcvh

— tds1 tdh1 tc1 trp tx1

1 tmli1 tzah tdzfs tcvh ton toff

Parameter from

Figure 14

Figure 15

Figure 16

tack tenv

Description tack (min) = (time_ack * T) – (tskew1 + tskew2) tenv (min) = (time_env * T) – (tskew1 + tskew2) tenv (max) = (time_env * T) + (tskew1 + tskew2) tds – (tskew3) – ti_ds > 0 tdh – (tskew3) – ti_dh > 0

(tcyc – tskew) > T trp (min) = time_rp * T – (tskew1 + tskew2 + tskew6)

(time_rp * T) – (tco + tsu + 3T + 2 *tbuf + 2*tcable2) > trfs (drive) tmli1 (min) = (time_mlix + 0.4) * T tzah (min) = (time_zah + 0.4) * T tdzfs = (time_dzfs * T) – (tskew1 + tskew2) tcvh = (time_cvh *T) – (tskew1 + tskew2) ton = time_on * T – tskew1 toff = time_off * T – tskew1

Controlling Variable time_ack time_env tskew3, ti_ds, ti_dh should be low enough

T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh

—

There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

2. Make ton and toff big enough to avoid bus contention

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.3.5.4

UDMA Out Timing

Figure 17

shows timing when the UDMA out transfer starts,

Figure 18 shows timing when the UDMA out

host terminates transfer, Figure 19 shows timing when the UDMA out device terminates transfer, and

Table 28

lists the timing parameters for UDMA out burst.

Figure 17. UDMA Out Transfer Starts Timing Diagram

Figure 18. UDMA Out Host Terminates Transfer Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics tack tenv tdvs tdvh tcyc t2cyc trfs1

— tss tmli tli tli tli tcvh

—

ATA

Parameter

Figure 19. UDMA Out Device Terminates Transfer Timing Diagram

Table 28. UDMA Out Burst Timing Parameters tdvs tdvh tcyc

— trfs tdzfs tss tdzfs_mli tli1 tli2 tli3 tcvh ton toff

Parameter from

Figure 17

Figure 18

Figure 19

tack tenv

Value tack (min) = (time_ack * T) – (tskew1 + tskew2) tenv (min) = (time_env * T) – (tskew1 + tskew2) tenv (max) = (time_env * T) + (tskew1 + tskew2) tdvs = (time_dvs * T) – (tskew1 + tskew2) tdvs = (time_dvh * T) – (tskew1 + tskew2) tcyc = time_cyc * T – (tskew1 + tskew2) t2cyc = time_cyc * 2 * T trfs = 1.6 * T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs * T – (tskew1) tss = time_ss * T – (tskew1 + tskew2) tdzfs_mli =max (time_dzfs, time_mli) * T – (tskew1 + tskew2) tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh *T) – (tskew1 + tskew2) ton = time_on * T – tskew1 toff = time_off * T – tskew1

Controlling

Variable time_ack time_env time_dvs time_dvh time_cyc time_cyc

— time_dzfs time_ss

—

— time_cvh

—

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.3.6 AUDMUX Electrical Specifications

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSI) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is hence governed by the SSI module. Please refer to their respective electrical specifications.

4.3.7 CSPI Electrical Specifications

This section describes the electrical information of the CSPI.

4.3.7.1

CSPI Timing

Figure 20 and Figure 21 depict the master mode and slave mode timings of CSPI, and

Table 29

lists the timing parameters.

SPI_RDY

CS11

SSx

SCLK

MOSI

MISO

CS9

CS1

CS7 CS8

CS10

CS3

CS2

CS6

CS4

CS5

Figure 20. CSPI Master Mode Timing Diagram

SSx

SCLK

MISO

MOSI

CS9

CS1

CS7 CS8

CS10

CS3

CS2

CS6

CS4

CS5

Figure 21. CSPI Slave Mode Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 29. CSPI Interface Timing Parameters

ID Parameter Symbol Min

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

SCLK Cycle Time

SCLK High or Low Time

SCLK Rise or Fall

SSx pulse width

SSx Lead Time (CS setup time)

SSx Lag Time (CS hold time)

Data Out Setup Time

Data Out Hold Time t clk t

SW t

RISE/FALL t

CSLH t

SCS t

HCS t

Smosi t

Hmosi

—

CS9 Data In Setup Time t

Smiso

CS10 Data In Hold Time t

Hmiso

CS11 SPI_RDY Setup Time

1 t

SRDY

—

SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

Max

—

7.6

—

4.3.8 DPLL Electrical Specifications

The three PLL’s of the MCIMX31 (MCU, USB, and Serial PLL) are all based on same DPLL design. The characteristics provided herein apply to all of them, except where noted explicitly. The PLL characteristics are provided based on measurements done for both sources—external clock source (CKIH), and FPM

(Frequency Pre-Multiplier) source.

4.3.8.1

Electrical Specifications

Table 30

lists the DPLL specification.

Table 30. DPLL Specifications

Parameter

CKIH frequency

CKIL frequency

(Frequency Pre-multiplier (FPM) enable mode)

Predivision factor (PD bits)

PLL reference frequency range after Predivider

Min Typ Max Unit Comments

15 26

MHz —

— 32; 32.768, 38.4

— kHz FPM lock time

≈

480 µs.

—

16 — —

35 MHz 15

≤

CKIH frequency/PD

≤

35 MHz

≤

FPM output/PD

≤

35 MHz

PLL output frequency range:

Maximum allowed reference clock phase noise.

Frequency lock time

(FOL mode or non-integer MF)

MPLL and SPLL

UPLL

190

—

532

240

MHz

100 ps

—

398 — Cycles of divided reference clock.

Units ns ns ns ns ns ns ns ns ns ns ns

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 30. DPLL Specifications (continued)

Parameter

Phase lock time

Maximum allowed PLL supply voltage ripple

PLL output clock phase jitter

PLL output clock period jitter

Min

—

Typ

—

Max Unit Comments

100 µs In addition to the frequency

5.2

mV F modulation

< 50 kHz mV 50 kHz < F modulation

< 300 kHz mV F modulation

> 300 kHz ns Measured on CLKO pin

420 ps Measured on CLKO pin

The user or board designer must take into account that the use of a frequency other than 26 MHz would require adjustment to the DPTC–DVFS table, which is incorporated into operating system code.

The PLL reference frequency must be

≤

35 MHz. Therefore, for frequencies between 35 MHz and 70 MHz, program the predivider to divide by 2 or more. If the CKIH frequency is above 70 MHz, program the predivider to 3 or more. For PD bit description, see the reference manual.

4.3.9 EMI Electrical Specifications

This section provides electrical parametrics and timings for EMI module.

4.3.9.1

NAND Flash Controller Interface (NFC)

The NFC supports normal timing mode, using two flash clock cycles for one access of RE and WE. AC timings are provided as multiplications of the clock cycle and fixed delay.

Figure 22

, Figure 23 , Figure 24

and Figure 25

depict the relative timing requirements among different signals of the NFC at module level,

for normal mode, and Table 31

lists the timing parameters.

NFCLE

NF2

NF1

NF3 NF4

NFCE

NF5

NFWE

NF6 NF7

NFALE

NFIO[7:0]

NF8

NF9

Command

Figure 22. Command Latch Cycle Timing DIagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

NFCLE

NF1

NF3 NF4

NFCE

NF5

NF10

NF11

NFWE

NF6 NF7

NFALE

NFIO[7:0]

NF8

NF9

Address

Figure 23. Address Latch Cycle Timing DIagram

NFCLE

NF1

NF3

NFCE

NF10

NF11

NF5

NFWE

NF6 NF7

NFALE

NFIO[15:0]

NF8

NF9

Data to NF

Figure 24. Write Data Latch Cycle Timing DIagram

Electrical Characteristics

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

NFCLE

NFCE

NF14

NF13

NF15

NFRE

NF16 NF17

NFRB

NFIO[15:0]

NF12

Data from NF

Figure 25. Read Data Latch Cycle Timing DIagram

Table 31. NFC Timing Parameters

ID Parameter Symbol

Timing

T = NFC Clock Cycle

Example Timing for

NFC Clock

≈

33 MHz

T = 30 ns Unit

Min

T–1.0 ns

T–2.0 ns

T–1.0 ns

T–2.0 ns

T–1.5 ns

—

T–3.0 ns

T–5.0 ns

1.5T

T–2.5 ns

—

0.5T–2.5 ns

—

N/A

Max

NF1 NFCLE Setup Time

NF2 NFCLE Hold Time

NF3 NFCE Setup Time

NF4 NFCE Hold Time

NF5 NF_WP Pulse Width

NF6 NFALE Setup Time

NF7 NFALE Hold Time

NF8 Data Setup Time

NF9 Data Hold Time

NF10 Write Cycle Time

NF11 NFWE Hold Time

NF12 Ready to NFRE Low

NF13 NFRE Pulse Width

NF14 READ Cycle Time

NF15 NFRE High Hold Time

NF16 Data Setup on READ

NF17 Data Hold on READ tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR

The flash clock maximum frequency is 50 MHz.

Subject to DPLL jitter specification on Table 30, "DPLL Specifications," on page 35 .

Min

28.5

180

12.5

27.5

Max

—

— ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

NOTE

High is defined as 80% of signal value and low is defined as 20% of signal value.

Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is approximately 33 MHz (30 ns). All timings are listed according to this NFC clock frequency (multiples of NFC clock phases), except NF16 and NF17, which are not NFC clock related.

4.3.9.2

Wireless External Interface Module (WEIM)

All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising edge or falling edge according to corresponding assertion/negation control fields. Address always begins related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according to control register configuration. Output data begins related to BCLK rising edge except in muxed mode where both rising and falling edge may be used according to control register configuration. Input data,

ECB and DTACK all captured according to BCLK rising edge time. Figure 26 depicts the timing of the

WEIM module, and

Table 32

lists the timing parameters.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

BCLK

Address

CS[x]

WEIM Outputs Timing

WE21

WE22

WE23

...

WE1

WE2

WE3 WE4

WE5 WE6

WE7 WE8

EB[x]

WE9 WE10

WE11 WE12

LBA

WE13 WE14

Output Data

WEIM Inputs Timing

BCLK

WE16

Input Data

WE15

WE18

ECB

WE17

WE20

DTACK

WE19

Figure 26. WEIM Bus Timing Diagram

Table 32. WEIM Bus Timing Parameters

ID Parameter

WE1 Clock fall to Address Valid

WE2 Clock rise/fall to Address Invalid

WE3 Clock rise/fall to CS[x] Valid

WE4 Clock rise/fall to CS[x] Invalid

WE5 Clock rise/fall to RW Valid

WE6 Clock rise/fall to RW Invalid

WE7 Clock rise/fall to OE Valid

Min

–0.5

–3

Max

2.5

Unit ns ns ns ns ns ns ns

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 32. WEIM Bus Timing Parameters (continued)

ID Parameter

WE8 Clock rise/fall to OE Invalid

WE9 Clock rise/fall to EB[x] Valid

WE10 Clock rise/fall to EB[x] Invalid

WE11 Clock rise/fall to LBA Valid

WE12 Clock rise/fall to LBA Invalid

WE13 Clock rise/fall to Output Data Valid

WE14 Clock rise to Output Data Invalid

WE15 Input Data Valid to Clock rise, FCE=0

FCE=1

WE16 Clock rise to Input Data Invalid, FCE=0

FCE=1

WE17 ECB setup time, FCE=0

FCE=1

WE18 ECB hold time, FCE=0

FCE=1

WE19 DTACK setup time

WE20 DTACK hold time

WE21 BCLK High Level Width

2, 3

WE22 BCLK Low Level Width

2, 3

WE23 BCLK Cycle time

Applies to rising edge timing

BCLK parameters are being measured from the 50% VDD.

The actual cycle time is derived from the AHB bus clock frequency.

Min

–2

4.5

–2

6.5

3.5

—

–3

–2.5

2.5

–3

Max

—

T/2 – 3

— ns ns

NOTE

High is defined as 80% of signal value and low is defined as 20% of signal value.

Test conditions: load capacitance, 25 pF. Recommended drive strength for all controls, address, and BCLK is Max drive.

Figure 27 , Figure 28 ,

Figure 29 , Figure 30

, Figure 31 , and Figure 32 depict some examples of

basic WEIM accesses to external memory devices with the timing parameters mentioned in

Table 32

for specific control parameter settings.

ns ns ns ns ns ns

Unit ns ns ns ns ns ns ns ns

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

BCLK

ADDR

CS[x]

Last Valid Address

WE1

WE3

WE2

Next Address

WE4

WE11

WE12

LBA

WE7 WE8

WE9 WE10

EB[y]

DATA

WE16

WE15

Figure 27. Asynchronous Memory Timing Diagram for Read Access—WSC=1

BCLK

ADDR

CS[x]

LBA

Last Valid Address

WE1

WE3

WE5

WE11

WE12

WE2

WE4

WE6

Next Address

WE9 WE10

EB[y]

DATA

WE14

WE13

Figure 28. Asynchronous Memory Timing Diagram for Write Access—

WSC=1, EBWA=1, EBWN=1, LBN=1

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

BCLK

WE1

ADDR Last Valid Addr

WE3

CS[x]

Address V1

WE2

Address V2

WE4

WE11 WE12

LBA

WE7

WE8

EB[y]

WE9 WE10

WE18 WE18

ECB

DATA

WE17 WE17

WE16

Halfword

V1+2

Halfword

WE16

Halfword

V2+2

Halfword

WE15

Figure 29. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses—

WSC=2, SYNC=1, DOL=0

BCLK

ADDR

WE1

Last Valid Addr

CS[x]

WE3

WE5

WE11

LBA

WE12

Address V1

WE2

WE4

WE6

EB[y]

WE9 WE10

WE18

ECB

WE17

WE14

V1+4 V1+8 V1+12 DATA V1

WE13 WE13

Figure 30. Synchronous Memory TIming Diagram for Burst Write Access—

BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor 43

Electrical Characteristics

BCLK

WE1

ADDR/

M_DATA

Last Valid Addr

CS[x]

WE3

WE5

WE11

LBA

EB[y]

WE9

Address V1

WE12

WE2

WE13

Write Data

Write

WE14

WE4

WE6

WE10

Figure 31. Muxed A/D Mode Timing Diagram for Asynchronous Write Access—

WSC=7, LBA=1, LBN=1, LAH=1

BCLK

WE1

ADDR/

M_DATA

CS[x]

Last Valid Addr

WE3

LBA

EB[y]

WE9

Address V1

WE2

WE11

WE12

WE7

WE16

Read Data

WE15

WE4

WE8

WE10

Figure 32. Muxed A/D Mode Timing Diagram for Asynchronous Read Access—

WSC=7, LBA=1, LBN=1, LAH=1, OEA=7

4.3.9.3

ESDCTL Electrical Specifications

, and

depict the timings pertaining to the

ESDCTL module, which interfaces Mobile DDR or SDR SDRAM.

, and

Table 38 list the timing parameters.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

SDCLK

SD4

SD5

RAS

SD4

SD5

SD4

CAS

SD4

SD5

ADDR

SD6

ROW/BA

SD7

COL/BA

SD10

SD1

SD2

SD3

SD8

SD9

Data

SD5

SD6

SD7

SD8

SD1

SD2

SD3

SD4

DQM

Note: CKE is high during the read/write cycle.

SD5

Figure 33. SDRAM Read Cycle Timing Diagram

Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters

Parameter

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

CS, RAS, CAS, WE, DQM, CKE setup time

CS, RAS, CAS, WE, DQM, CKE hold time

Address setup time

Address hold time

SDRAM access time

Symbol tCH tCL tCK tCMS tCMH tAS tAH tAC

Min

1.8

2.0

1.8

—

3.4

7.5

2.0

Max

—

6.47

4.1

—

Unit ns ns ns ns ns ns ns ns

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)

SD9

SD10

Parameter

Data out hold time

Active to read/write command period

Symbol tOH tRC

Min

1.8

Max

—

Unit ns clock

Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see

Table 37 and

Table 38 .

NOTE

SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.

The timing parameters are similar to the ones used in SDRAM data sheets—that is,

Table 33 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

SD1

SDCLK

SD3

SD2

SD4

SD5

RAS

SD11

SD4

CAS

SD5

SD4 SD4

ADDR

SD6

SD5

SD7

ROW / BA

SD5

SD12

SD13

COL/BA

DATA

SD14

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD11

SD12

DQM

Figure 34. SDR SDRAM Write Cycle Timing Diagram

Table 34. SDR SDRAM Write Timing Parameters

Parameter

SDRAM clock high-level width

SDRAM clock low-level width

SDRAM clock cycle time

CS, RAS, CAS, WE, DQM, CKE setup time

CS, RAS, CAS, WE, DQM, CKE hold time

Address setup time

Address hold time

Precharge cycle period

Active to read/write command delay

Symbol tCH tCL tCK tCMS tCMH tAS tAH tRP tRCD

Min

1.8

2.0

1.8

3.4

7.5

2.0

Max

—

4.1

—

Unit ns ns ns clock clock ns ns ns ns

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 34. SDR SDRAM Write Timing Parameters (continued)

SD13

SD14

Data setup time

Data hold time

Parameter

SD11 and SD12 are determined by SDRAM controller register settings.

Symbol tDS tDH

Min

2.0

1.3

NOTE

SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value.

The timing parameters are similar to the ones used in SDRAM data sheets—that is,

Table 34 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.

Max

—

SD1

SDCLK

SD2

SD3

Unit ns ns

RAS

SD11

CAS

SD10 SD10

SD7

SD1

SD2

ADDR

SD6

Figure 35. SDRAM Refresh Timing Diagram

Table 35. SDRAM Refresh Timing Parameters

Parameter Symbol

SDRAM clock high-level width tCH

SDRAM clock low-level width tCL

Min

3.4

ROW/BA

Max

4.1

Unit ns ns

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 35. SDRAM Refresh Timing Parameters (continued)

SD3

SD6

SD7

SD10

SD11

Parameter

SDRAM clock cycle time

Address setup time

Address hold time

Precharge cycle period

Auto precharge command period

SD10 and SD11 are determined by SDRAM controller register settings.

Symbol tCK tAS tAH tRP tRC

Min

7.5

1.8

NOTE

SDR SDRAM CLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal value and low is defined as

50% of signal value.

The timing parameters are similar to the ones used in SDRAM data sheets—that is,

Table 35 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.

Max

—

Unit ns ns ns clock clock

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

SDCLK

RAS

CAS

ADDR

CKE

SD16 SD16

SD16

Don’t care

Figure 36. SDRAM Self-Refresh Cycle Timing Diagram

NOTE

The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state.

Table 36. SDRAM Self-Refresh Cycle Timing Parameters

Parameter

CKE output delay time

Symbol tCKS

Min

1.8

Max

—

Unit ns

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

SDCLK

DQS (output)

DQ (output)

SD19 SD20

SD17

Data

SD18

Data

SD17

Data Data

SD18

Data Data Data Data

DQM (output) DM

DM DM DM DM DM

SD17 SD17

SD18 SD18

Figure 37. Mobile DDR SDRAM Write Cycle Timing Diagram

Table 37. Mobile DDR SDRAM Write Cycle Timing Parameters

DM DM

ID Parameter

SD17 DQ and DQM setup time to DQS

SD18 DQ and DQM hold time to DQS

SD19 Write cycle DQS falling edge to SDCLK output delay time.

SD20 Write cycle DQS falling edge to SDCLK output hold time.

Symbol tDS tDH tDSS tDSH

Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.

Min

0.95

1.8

Max

—

Unit ns ns ns ns

NOTE

SDRAM CLK and DQS related parameters are being measured from the

50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value.

The timing parameters are similar to the ones used in SDRAM data sheets—that is,

Table 37 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

SDCLK

SD23

DQS (input)

SD22

DQ (input)

SD21

Data Data Data Data Data Data Data Data

Figure 38. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

Table 38. Mobile DDR SDRAM Read Cycle Timing Parameters

ID Parameter

SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS).

SD22 DQS DQ HOLD time from DQS

SD23 DQS output access time from SDCLK posedge

Symbol Min Max Unit tDQSQ — 0.85

ns tQH 2.3

— ns tDQSCK — 6.7

NOTE

SDRAM CLK and DQS related parameters are being measured from the

50% point—that is, high is defined as 50% of signal value and low is defined as 50% of signal value.

The timing parameters are similar to the ones used in SDRAM data sheets—that is,

Table 38 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency.

4.3.10 ETM Electrical Specifications

ETM is an ARM protocol. The timing specifications in this section are given as a guide for a TPA that supports TRACECLK frequencies up to 133 MHz.

Figure 39

depicts the TRACECLK timings of ETM, and

Table 39

lists the timing parameters.

Figure 39. ETM TRACECLK Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

T cyc

T wl

T wh

T r

T f

Table 39. ETM TRACECLK Timing Parameters

Parameter

Clock period

Low pulse width

High pulse width

Clock and data rise time

Clock and data fall time

Min

Frequency dependent

—

Max

—

Unit ns ns ns ns ns

Figure 40

depicts the setup and hold requirements of the trace data pins with respect to TRACECLK, and

Table 40

lists the timing parameters.

T s

T h

Figure 40. Trace Data Timing Diagram

Table 40. ETM Trace Data Timing Parameters

Parameter

Data setup

Data hold

Min

Max

—

Unit ns ns

4.3.10.1

Half-Rate Clocking Mode

When half-rate clocking is used, the trace data signals are sampled by the TPA on both the rising and falling edges of TRACECLK, where TRACECLK is half the frequency of the clock shown in

Figure 40

4.3.11 FIR Electrical Specifications

FIR implements asynchronous infrared protocols (FIR, MIR) that are defined by IrDA

(Infrared Data

Association). Refer to http://www.IrDA.org for details on FIR and MIR protocols.

4.3.12 Fusebox Electrical Specifications

Table 41. Fusebox Timing Characteristics

Ref. Num Description

Program time for eFuse

Symbol Minimum Typical Maximum Units

1 t program

125 — — µs

The program length is defined by the value defined in the epm_pgm_length[2:0] bits of the IIM module. The value to program is based on a 32 kHz clock source (4 * 1/32 kHz = 125 µs).

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.3.13 I

C Electrical Specifications

This section describes the electrical information of the I

C Module.

4.3.13.1

C Module Timing

Figure 41

depicts the timing of I

C module. Table 42 lists the I

C module timing parameters where the I/O supply is 2.7 V. 1

IC11

IC10 IC9

I2DAT

IC2

IC8

IC4 IC7

IC3

I2CLK

START IC10

IC6

IC11 START STOP

IC5

IC1

Figure 41. I

C Bus Timing Diagram

Table 42. I

C Module Timing Parameters—I

C Pin I/O Supply=2.7 V

START

Standard Mode Fast Mode

ID Parameter Unit

IC1 I2CLK cycle time

IC2 Hold time (repeated) START condition

IC3 Set-up time for STOP condition

IC4 Data hold time

IC5 HIGH Period of I2CLK Clock

IC6 LOW Period of the I2CLK Clock

IC7 Set-up time for a repeated START condition

IC8 Data set-up time

IC9 Bus free time between a STOP and START condition

IC10 Rise time of both I2DAT and I2CLK signals

IC11 Fall time of both I2DAT and I2CLK signals

IC12 Capacitive load for each bus line (C b

)

Min

4.0

4.7

250

4.0

4.7

—

Max

—

3.45

—

1000

300

400

Min

2.5

0.6

1.3

0.6

100

1.3

20+0.1C

—

Max

—

0.9

—

300

400

A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK.

The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.

A Fast-mode I

C-bus device can be used in a standard-mode I

C-bus system, but the requirement of set-up time (ID IC7) of

250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time

(ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I

C-bus specification) before the I2CLK line is released.

C b

= total capacitance of one bus line in pF.

μ s

μ s ns

μ s ns ns pF

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

4.3.14 IPU—Sensor Interfaces

4.3.14.1

Supported Camera Sensors

Table 43

lists the known supported camera sensors at the time of publication.

Table 43. Supported Camera Sensors

Conexant

Agilant

Toshiba

ICMedia iMagic

Transchip

Fujitsu

Micron

Vendor

Matsushita

STMicro

OmniVision

Sharp

Motorola

National Semiconductor

CX11646, CX20490

, CX20450

HDCP–2010, ADCS–1021

, ADCS–1021

Model

TC90A70

ICM202A, ICM102

IM8801

TC5600, TC5600J, TC5640, TC5700, TC6000

MB86S02A

MI–SOC–0133

MN39980

OV7620, OV6630

LZ0P3714 (CCD)

MC30300 (Python)

, SCM20014

, SCM20114

, SCM22114

, SCM20027

LM9618

Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers.

These sensors not validated at time of publication.

4.3.14.2

Functional Description

There are three timing modes supported by the IPU.

4.3.14.2.1

Pseudo BT.656 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656 standard.

This operation mode follows the recommendations of ITU BT.656 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.3.14.2.2

Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 42

Active Line

Start of Frame nth frame n+1th frame

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

SENSB_DATA[9:0] invalid invalid

1st byte 1st byte

Figure 42. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the

SENSB_VSYNC timing repeats.

4.3.14.2.3

Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.3.14.2.2, “Gated Clock Mode

”), except for the SENSB_HSYNC signal, which is not used. See

Figure 43

. All incoming pixel clocks are valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus.

Start of Frame nth frame n+1th frame

SENSB_VSYNC

SENSB_PIX_CLK

SENSB_DATA[7:0] invalid invalid

1st byte 1st byte

Figure 43. Non-Gated Clock Mode Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

The timing described in

Figure 43 is that of a Motorola sensor. Some other sensors may have a slightly

different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

4.3.14.3

Electrical Characteristics

Figure 44

depicts the sensor interface timing, and

Table 44

lists the timing parameters.

1/IP1

SENSB_MCLK

(Sensor Input)

SENSB_PIX_CLK

(Sensor Output)

IP3 IP2 1/IP4

SENSB_DATA,

SENSB_VSYNC,

SENSB_HSYNC

Figure 44. Sensor Interface Timing Diagram

Table 44. Sensor Interface Timing Parameters

ID Parameter Symbol Min.

Max.

Units

IP1

IP2

Sensor input clock frequency

Data and control setup time

Fmck

Tsu

0.01

133

—

MHz ns

IP3 Data and control holdup time Thd 3 — ns

IP4 Sensor output (pixel) clock frequency Fpck 0.01

133 MHz

The timing specifications for

Figure 44

are referenced to the rising edge of SENS_PIX_CLK when the

SENS_PIX_CLK_POL bit in the CSI_SENS_CONF register is cleared. When the SENS_PIX_CLK_POL is set, the clock is inverted and all timing specifications will remain the same but are referenced to the falling edge of the clock.

4.3.15 IPU

—

Display Interfaces

4.3.15.1

Supported Display Components

Table 45

lists the known supported display components at the time of publication.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 45. Supported Display Components

Type

TFT displays

(memory-less)

Vendor

Sharp (HR-TFT Super

Mobile LCD family)

Samsung (QCIF and

QVGA TFT modules for mobile phones)

Toshiba (LTM series)

Model

LQ035Q7 DB02, LM019LC1Sxx

LTS180S1-HF1, LTS180S3-HF1, LTS350Q1-PE1,

LTS350Q1-PD1, LTS220Q1-HE1

Display controllers

Smart display modules

Digital video encoders

(for TV)

NEC

Epson

Solomon Systech

Hitachi

ATI

Epson

Hitachi

Densitron Europe LTD

Sharp

Sony

Analog Devices

Crystal (Cirrus Logic)

Focus

LTM018A02A

NL6448BC20-08E, NL8060BC31-27

S1D15xxx series, S1D19xxx series, S1D13713, S1D13715

SSD1301 (OLED), SSD1828 (LDCD)

HD66766, HD66772

W2300

L1F10043 T

, L1F10044 T

120 160 65K/4096 C-STN (#3284 LTD-1398-2) based on HD 66766 controller

All displays with MPU 80/68K series interface and serial peripheral interface

LM019LC1Sxx

ACX506AKM

ADV7174/7179

CS49xx series

FS453/4

Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only display component suppliers.

These display components not validated at time of publication.

4.3.15.2

Synchronous Interfaces

4.3.15.2.1

Interface to Active Matrix TFT LCD Panels, Functional Description

Figure 45

depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

• DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, DISPB_D3_CLK runs continuously.

• DISPB_D3_HSYNC causes the panel to start a new line.

• DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one

HSYNC pulse.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

• DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off.

DISPB_D3_VSYNC

DISPB_D3_HSYNC

LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n

DISPB_D3_HSYNC

DISPB_D3_DRDY

1 2 3 m-1 m

DISPB_D3_CLK

DISPB_D3_DATA

Figure 45. Interface Timing Diagram for TFT (Active Matrix) Panels

4.3.15.2.2

Interface to Active Matrix TFT LCD Panels, Electrical Characteristics

Figure 46

depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals.

IP7

IP9 IP6 IP10

Start of line

IP5

IP8

DISPB_D3_CLK

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_DATA

Figure 46. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 47

depicts the vertical timing (timing of one frame). All figure parameters shown are programmable.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Start of frame

End of frame

IP13

DISPB_D3_VSYNC

DISPB_D3_HSYNC

DISPB_D3_DRDY

IP11 IP14 IP15

IP12

Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse

Table 46

shows timing parameters of signals presented in

Figure 46

and Figure 47 .

Table 46. Synchronous Display Interface Timing Parameters—Pixel Level

IP5

IP6

IP7

IP8

IP9

IP10

IP11

IP12

IP13

Parameter

Display interface clock period

Display pixel clock period

Screen width

HSYNC width

Horizontal blank interval 1

Horizontal blank interval 2

HSYNC delay

Screen height

VSYNC width

IP14

IP15

Vertical blank interval 1

Vertical blank interval 2

Display interface clock period immediate value.

Symbol

Tdicp

Tdpcp

Tsw

Thsw

Thbi1

Thbi2

Thsd

Tsh

Tvsw

Tvbi1

Tvbi2

Value

Tdicp

(DISP3_IF_CLK_CNT_D+1) * Tdicp

(SCREEN_WIDTH+1) * Tdpcp

(H_SYNC_WIDTH+1) * Tdpcp

BGXP * Tdpcp

(SCREEN_WIDTH – BGXP – FW) * Tdpcp

H_SYNC_DELAY * Tdpcp

(SCREEN_HEIGHT+1) * Tsw if V_SYNC_WIDTH_L = 0 than

(V_SYNC_WIDTH+1) * Tdpcp else

(V_SYNC_WIDTH+1) * Tsw

BGYP * Tsw

(SCREEN_HEIGHT – BGYP – FH) * Tsw

Tdicp =

⎧

⎪

⎨

⎪

⎩

HSP_CLK

⋅

⎛

⎝

⋅ -----------------------------------------------------------------floor

HSP_CLK_PERIOD

for integer

DISP3_IF_CLK_PER_WR

HSP_CLK_PERIOD

+ 0.5

0.5

⎞

⎠

for fractional

HSP_CLK_PERIOD

DISP3_IF_CLK_PER_WR

HSP_CLK_PERIOD

Display interface clock period average value.

Units ns ns ns ns ns ns ns ns ns ns ns

Tdicp = T

HSP_CLK

⋅

HSP_CLK_PERIOD

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

NOTE

HSP_CLK is the High-Speed Port Clock, which is the input to the Image

Processing Unit (IPU). Its frequency is controlled by the Clock Control

Module (CCM) settings. The HSP_CLK frequency must be greater than or equal to the AHB clock frequency.

The SCREEN_WIDTH, SCREEN_HEIGHT, H_SYNC_WIDTH, V_SYNC_WIDTH, BGXP, BGYP and

V_SYNC_WIDTH_L parameters are programmed via the SDC_HOR_CONF, SDC_VER_CONF,

SDC_BG_POS Registers. The FW and FH parameters are programmed for the corresponding DMA channel. The DISP3_IF_CLK_PER_WR, HSP_CLK_PERIOD and DISP3_IF_CLK_CNT_D parameters are programmed via the DI_DISP3_TIME_CONF, DI_HSP_CLK_PER and DI_DISP_ACC_CC

Registers.

Figure 48

depicts the synchronous display interface timing for access level, and

Table 47

lists the timing parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the

DI_DISP3_TIME_CONF Register.

IP20

DISPB_D3_VSYNC

DISPB_D3_HSYNC

DISPB_D3_DRDY other controls

DISPB_D3_CLK

IP16 IP17 IP19 IP18

DISPB_DATA

Figure 48. Synchronous Display Interface Timing Diagram—Access Level

Table 47. Synchronous Display Interface Timing Parameters—Access Level

ID Parameter Symbol Min Typ

Max Units

IP16 Display interface clock low time Tckl Tdicd–Tdicu–1.5

IP17 Display interface clock high time

Tdicd

–Tdicu

Tdicd–Tdicu+1.5

Tckh Tdicp–Tdicd+Tdicu–1.5

Tdicp–Tdicd+Tdicu Tdicp–Tdicd+Tdicu+1.5

IP18 Data setup time

IP19 Data holdup time

IP20 Control signals setup time to display interface clock

Tdsu

Tdhd

Tcsu

Tdicd–3.5

Tdicp–Tdicd–3.5

Tdicd–3.5

Tdicu

Tdicp–Tdicu

Tdicu

—

— ns ns ns

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Display interface clock down time

Tdicd =

2 HSP_CLK

⋅ ceil

HSP_CLK_PERIOD

Display interface clock up time

Tdicu =

2 HSP_CLK

⋅ ceil

HSP_CLK_PERIOD where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

4.3.15.3

Interface to Sharp HR-TFT Panels

Figure 49

depicts the Sharp HR-TFT panel interface timing, and

Table 48

lists the timing parameters. The

CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,

REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and

SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to

Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics

” The timing images correspond to straight polarity of the Sharp signals.

Horizontal timing

DISPB_D3_CLK

DISPB_D3_DATA D1 D2 D320

DISPB_D3_SPL

DISPB_D3_HSYNC

IP21 1 DISPB_D3_CLK period

IP23

IP22

DISPB_D3_CLS

IP24

DISPB_D3_PS

IP25

IP26

DISPB_D3_REV

Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.

SPL pulse width is fixed and aligned to the first data of the line.

REV toggles every HSYNC period.

Figure 49. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 48. Sharp Synchronous Display Interface Timing Parameters—Pixel Level

ID Parameter

IP21 SPL rise time

IP22 CLS rise time

IP23 CLS fall time

IP24 CLS rise and PS fall time

IP25 PS rise time

IP26 REV toggle time

Symbol

Tsplr

Tclsr

Tclsf

Tpsf

Tpsr

Trev

Value

(BGXP – 1) * Tdpcp

CLS_RISE_DELAY * Tdpcp

CLS_FALL_DELAY * Tdpcp

PS_FALL_DELAY * Tdpcp

PS_RISE_DELAY * Tdpcp

REV_TOGGLE_DELAY * Tdpcp

Units ns ns ns ns ns ns

4.3.15.4

Synchronous Interface to Dual-Port Smart Displays

Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are identical to parameters of the synchronous interface. See

Section 4.3.15.2.2, “Interface to Active Matrix

TFT LCD Panels, Electrical Characteristics

.”

4.3.15.4.1

Interface to a TV Encoder, Functional Description

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits

D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively. Figure 50 depicts the

interface timing,

• The frequency of the clock DISPB_D3_CLK is 27 MHz (within 10%).

• The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.

• The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal.

It remains low for a single clock cycle.

• The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC signal. It remains low for at least one clock cycle.

— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC and DISPB_D3_HSYNC coincide.

— At a transition to an even field (of the same frame), they do not coincide.

• The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

DISPB_D3_CLK

DISPB_D3_HSYNC

DISPB_D3_VSYNC

DISPB_D3_DRDY

DISPB_DATA

Cb Y Cr Y

523 524 525

Pixel Data Timing

1 2 3

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Cb Y

5 6

261

Even Field

262 263 264 265 266 267 268

Odd Field

269

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Odd Field

621 622 623

Line and Field Timing - NTSC

624 625 1 2 3

Even Field

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

Even Field Odd Field

308 309 310 311 312 313 314 315 316

DISPB_D3_HSYNC

DISPB_D3_DRDY

DISPB_D3_VSYNC

273

336

Odd Field Even Field

Line and Field Timing - PAL

Figure 50. TV Encoder Interface Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

4.3.15.4.2

Interface to a TV Encoder, Electrical Characteristics

The timing characteristics of the TV encoder interface are identical to the synchronous display

characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical

Characteristics .”

4.3.15.5

Asynchronous Interfaces

4.3.15.5.1

Parallel Interfaces, Functional Description

The IPU supports the following asynchronous parallel interfaces:

• System 80 interface

— Type 1 (sampling with the chip select signal) with and without byte enable signals.

— Type 2 (sampling with the read and write signals) with and without byte enable signals.

• System 68k interface

— Type 1 (sampling with the chip select signal) with or without byte enable signals.

— Type 2 (sampling with the read and write signals) with or without byte enable signals.

For each of four system interfaces, there are three burst modes:

1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters of the IDMAC (when data is transferred from the system memory) of by the HBURST signal

(when the MCU directly accesses the display via the slave AHB bus). For system 80 and system

68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD signals (system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during the whole burst.

2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the

DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are changed simultaneously with data when the bus state (read, write or wait) is altered. The CS signals and other controls move to non-active state after burst has been completed.

3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The data is sampled with CS or other controls according the interface type as described above. All controls (including CS) become non-active for one display interface clock after each access. This mode corresponds to the ATI single access mode.

Both system 80 and system 68k interfaces are supported for all described modes as depicted in

Figure 51

Figure 52

, Figure 53

, and Figure 54 . These timing images correspond to active-low DISPB_D#_CS,

DISPB_D#_WR and DISPB_D#_RD signals.

Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the

HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by CS signal

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 51. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by WR/RD signals

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

DISPB_RD

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 52. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by CS signal

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 53. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by ENABLE signal

DISPB_BCLK

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Burst access mode with sampling by separate burst clock (BCLK)

DISPB_D#_CS

DISPB_PAR_RS

DISPB_WR

(READ/WRITE)

DISPB_RD

(ENABLE)

DISPB_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 54. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram

Display read operation can be performed with wait states when each read access takes up to four display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the

DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers.

Figure 55

shows timing of the parallel interface with read wait states.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

WRITE OPERATION

DISP0_RD_WAIT_ST=00

READ OPERATION

DISPB_D#_CS

DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

DISP0_RD_WAIT_ST=01

DISPB_D#_CS

DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

DISP0_RD_WAIT_ST=10

DISPB_D#_CS

DISPB_RD

DISPB_WR

DISPB_PAR_RS

DISPB_DATA

Figure 55. Parallel Interface Timing Diagram—Read Wait States

4.3.15.5.2

Parallel Interfaces , Electrical Characteristics

Figure 56

, Figure 58

, Figure 57

, and

Figure 59 depict timing of asynchronous parallel interfaces based on

the system 80 and system 68k interfaces.

Table 49 lists the timing parameters at display access level. All

timing images are based on active low control signals (signals polarity is controlled via the

DI_DISP_SIG_POL Register).

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

IP28, IP27

DISPB_PAR_RS

DISPB_RD (READ_L)

DISPB_DATA[17]

(READ_H)

DISPB_D#_CS

DISPB_WR (WRITE_L)

DISPB_DATA[16]

(WRITE_H)

IP35, IP33 IP36, IP34

DISPB_DATA

(Input)

IP37

IP39

IP31, IP29 read point

Read Data

IP38

IP32, IP30

IP40

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 56. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

IP28, IP27

DISPB_PAR_RS

DISPB_D#_CS

IP35, IP33

IP36, IP34

DISPB_RD (READ_L)

DISPB_DATA[17]

(READ_H)

DISPB_WR (WRITE_L)

DISPB_DATA[16]

(WRITE_H)

DISPB_DATA

(Input)

IP37

IP31, IP29 read point

Read Data

IP38

IP39

IP32, IP30

IP40

DISPB_DATA

(Output)

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 57. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

IP28, IP27

DISPB_PAR_RS

DISPB_RD (ENABLE_L)

DISPB_DATA[17]

(ENABLE_H)

DISPB_D#_CS

DISPB_WR

(READ/WRITE)

IP35,IP33 IP36, IP34

DISPB_DATA

(Input)

DISPB_DATA

(Output)

IP37

IP31, IP29 read point

Read Data

IP38

IP39

IP32, IP30

IP40

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 58. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

IP28, IP27

DISPB_PAR_RS

DISPB_D#_CS

DISPB_RD (ENABLE_L)

DISPB_DATA[17]

(ENABLE_H)

DISPB_WR

(READ/WRITE)

IP35,IP33 IP36, IP34

DISPB_DATA

(Input)

DISPB_DATA

(Output)

IP37

IP31, IP29 read point

Read Data

IP38

IP39

IP32, IP30

IP40

IP46,IP44

IP47

IP45, IP43

IP42, IP41

Figure 59. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram

Table 49. Asynchronous Parallel Interface Timing Parameters—Access Level

ID Parameter

IP27 Read system cycle time

IP28 Write system cycle time

IP29 Read low pulse width

IP30 Read high pulse width

IP31 Write low pulse width

IP32 Write high pulse width

Symbol Min.

Typ.

Tcycr

Tcycw

Tdicpr–1.5

Tdicpw–1.5

Tdicpr

Tdicpw

Tdicdr

–Tdicur

Trl Tdicdr–Tdicur–1.5

Trh Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+

Tdicur

Twl Tdicdw–Tdicuw–1.5

Tdicdw

–Tdicuw

Twh Tdicpw–Tdicdw+

Tdicuw–1.5

Tdicpw–Tdicdw+

Tdicuw

IP33 Controls setup time for read Tdcsr Tdicur–1.5

IP34 Controls hold time for read Tdchr Tdicpr–Tdicdr–1.5

IP35 Controls setup time for write Tdcsw Tdicuw–1.5

Tdicur

Tdicpr–Tdicdr

Tdicuw

Max.

Tdicpr+1.5

Tdicpw+1.5

ns ns

Tdicdr–Tdicur+1.5

Tdicpr–Tdicdr+Tdicur+1.5

Tdicdw–Tdicuw+1.5

Tdicpw–Tdicdw+

Tdicuw+1.5

—

Units ns ns ns ns ns

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 49. Asynchronous Parallel Interface Timing Parameters—Access Level (continued)

ID Parameter

IP36 Controls hold time for write

IP37 Slave device data delay

IP38 Slave device data hold time

IP39 Write data setup time

IP40 Write data hold time

IP41 Read period

IP42 Write period

IP43 Read down time

IP44 Read up time

IP45 Write down time

IP46 Write up time

IP47 Read time point

Symbol Min.

Tdchw Tdicpw–Tdicdw–1.5

Tracc 0

Troh Tdrp–Tlbd–Tdicdr+1.5

Tds Tdicdw–1.5

Tdh Tdicpw–Tdicdw–1.5

Tdicpr Tdicpr–1.5

Tdicpw Tdicpw–1.5

Tdicdr Tdicdr–1.5

Tdicur Tdicur–1.5

Tdicdw Tdicdw–1.5

Tdicuw Tdicuw–1.5

Tdrp Tdrp–1.5

Typ.

Tdicpw–Tdicdw

—

Tdicdw

Tdicpw–Tdicdw

Tdicpr

Tdicpw

Tdicdr

Tdicur

Tdicdw

Tdicuw

Tdrp

Max.

—

Tdrp

–Tlbd

–Tdicur–1.5

Tdicpr–Tdicdr–1.5

—

Tdicpr+1.5

Tdicpw+1.5

Tdicdr+1.5

Tdicur+1.5

Tdicdw+1.5

Tdicuw+1.5

Tdrp+1.5

Units ns ns ns ns ns ns ns ns ns ns ns ns

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific.

Display interface clock period value for read:

Tdicpr = T

HSP_CLK

⋅ cei l

HSP_CLK_PERIOD

Display interface clock period value for write:

Tdicpw = T

HSP_CLK

⋅ ceil

HSP_CLK_PERIOD

Display interface clock down time for read:

Tdicdr =

HSP_CLK

⋅ cei l

HSP_CLK_PERIOD

Display interface clock up time for read:

Tdicur =

HSP_CLK

⋅ ce il

HSP_CLK_PERIOD

Display interface clock down time for write:

Tdicdw =

HSP_CLK

⋅ ceil

HSP_CLK_PERIOD

Display interface clock up time for write:

Tdi cuw =

HSP_CLK

⋅ cei l

HSP_CLK_PERIOD

This parameter is a requirement to the display connected to the IPU

Data read point

Tdrp = T

HSP_CLK

⋅ ceil

HSP_CLK_PERIOD

Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,

DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,

DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the

DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.

4.3.15.5.3

Serial Interfaces , Functional Description

The IPU supports the following types of asynchronous serial interfaces:

• 3-wire (with bidirectional data line)

• 4-wire (with separate data input and output lines)

• 5-wire type 1 (with sampling RS by the serial clock)

• 5-wire type 2 (with sampling RS by the chip select signal)

Figure 60

depicts timing of the 3-wire serial interface. The timing images correspond to active-low

DISPB_D#_CS signal and the straight polarity of the DISPB_SD_D_CLK signal.

For this interface, a bidirectional data line is used outside the device. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU.

Each data transfer can be preceded by an optional preamble with programmable length and contents. The preamble is followed by read/write (RW) and address (RS) bits. The order of the these bits is programmable. The RW bit can be disabled. The following data can consist of one word or of a whole burst. The interface parameters are controlled by the DI_SER_DISP1_CONF and DI_SER_DISP2_CONF

Registers.

DISPB_D#_CS

1 display IF clock cycle

DISPB_SD_D_CLK

DISPB_SD_D RW RS D7 D6 D5 D4 D3 D2 D1 D0

Preamble Input or output data

Figure 60. 3-Wire Serial Interface Timing Diagram

Figure 61

depicts timing of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the device.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Write

DISPB_D#_CS 1 display IF clock cycle

1 display IF clock cycle

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

DISPB_SD_D

(Input)

Preamble

RW RS D7 D6 D5 D4 D3 D2 D1 D0

Output data

Read

DISPB_D#_CS 1 display IF clock cycle

1 display IF clock cycle

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

RW RS

Preamble

DISPB_SD_D

(Input)

D7 D6 D5 D4 D3 D2 D1 D0

Input data

Figure 61. 4-Wire Serial Interface Timing Diagram

Figure 62

depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

DISPB_SD_D

(Input)

DISPB_SER_RS

1 display IF clock cycle

Preamble

Write

1 display IF clock cycle

RW D7 D6 D5 D4 D3 D2 D1 D0

Output data

Read

DISPB_D#_CS

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

DISPB_SD_D

(Input)

DISPB_SER_RS

1 display IF clock cycle

Preamble

D7 D6 D5 D4 D3 D2 D1 D0

Input data

Figure 62. 5-Wire Serial Interface (Type 1) Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Figure 63

depicts timing of the 5-wire serial interface (Type 2). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words.

Write

DISPB_D#_CS

1 display IF clock cycle

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

Preamble

RW D7 D6 D5 D4 D3 D2 D1 D0

Output data

DISPB_SD_D

(Input)

DISPB_SER_RS

1 display IF clock cycle

Read

DISPB_D#_CS

1 display IF clock cycle

DISPB_SD_D_CLK

DISPB_SD_D

(Output)

DISPB_SD_D

(Input)

DISPB_SER_RS

Preamble

D7 D6 D5 D4 D3 D2 D1 D0

1 display IF clock cycle

Input data

Figure 63. 5-Wire Serial Interface (Type 2) Timing Diagram

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.3.15.5.4

Serial Interfaces, Electrical Characteristics

Figure 64

depicts timing of the serial interface.

Table 50 lists the timing parameters at display access level.

IP49, IP48

DISPB_SER_RS

IP56,IP54 IP57, IP55

DISPB_SD_D_CLK

DISPB_DATA

(Input)

IP58

IP50, IP52 read point

Read Data

IP59

IP60

IP51, IP53

IP61

DISPB_DATA

(Output)

IP67,IP65

IP47

IP64, IP66

IP62, IP63

Figure 64. Asynchronous Serial Interface Timing Diagram

Table 50. Asynchronous Serial Interface Timing Parameters—Access Level

ID Parameter

IP48 Read system cycle time

IP49 Write system cycle time

IP50 Read clock low pulse width

IP51 Read clock high pulse width

IP52 Write clock low pulse width

IP53 Write clock high pulse width

Symbol Min.

Typ.

Tcycr

Tcycw

Tdicpr–1.5

Tdicpw–1.5

Tdicpr

Tdicpw

Tdicdr

–Tdicur

Trl Tdicdr–Tdicur–1.5

Trh Tdicpr–Tdicdr+Tdicur–1.5

Tdicpr–Tdicdr+

Tdicur

Twl Tdicdw–Tdicuw–1.5

Tdicdw

–Tdicuw

Twh Tdicpw–Tdicdw+

Tdicuw–1.5

Tdicpw–Tdicdw+

Tdicuw

IP54 Controls setup time for read Tdcsr Tdicur–1.5

IP55 Controls hold time for read Tdchr Tdicpr–Tdicdr–1.5

Tdicur

Tdicpr–Tdicdr

Max.

Tdicpr+1.5

Tdicpw+1.5

ns ns

Tdicdr–Tdicur+1.5

Tdicpr–Tdicdr+Tdicur+1.5

Tdicdw–Tdicuw+1.5

Tdicpw–Tdicdw+

Tdicuw+1.5

—

Units ns ns ns ns

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

Table 50. Asynchronous Serial Interface Timing Parameters—Access Level (continued)

ID Parameter Symbol Min.

IP56 Controls setup time for write Tdcsw Tdicuw–1.5

IP57 Controls hold time for write

IP58 Slave device data delay

IP59 Slave device data hold time

Tdchw Tdicpw–Tdicdw–1.5

Tracc

Troh

Tdrp–Tlbd–Tdicdr+1.5

Tds Tdicdw–1.5

Tdh Tdicpw–Tdicdw–1.5

IP60 Write data setup time

IP61 Write data hold time

IP66 Write down time

IP67 Write up time

IP68 Read time point

Tdicpr

Tdicpw

Tdicdr

Tdicur

Tdicdw

Tdicuw

Tdrp

Tdicpr–1.5

Tdicpw–1.5

Tdicdr–1.5

Tdicur–1.5

Tdicdw–1.5

Tdicuw–1.5

Tdrp–1.5

Typ.

Tdicuw

Tdicpw–Tdicdw

—

Tdicdw

Tdicpw–Tdicdw

Tdicpr

Tdicpw

Tdicdr

Tdicur

Tdicdw

Tdicuw

Tdrp

Max.

—

Tdrp

–Tlbd

–Tdicur–1.5

Tdicpr–Tdicdr–1.5

—

Tdicpr+1.5

Tdicpw+1.5

Tdicdr+1.5

Tdicur+1.5

Tdicdw+1.5

Tdicuw+1.5

Tdrp+1.5

Units ns ns ns ns ns ns ns ns ns ns ns ns ns

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific.

Display interface clock period value for read:

Tdicpr = T

HSP_CLK

⋅ c eil

HSP_CLK_PERIOD

Display interface clock period value for write:

Tdi cpw = T

HSP_CLK

⋅ ce il

HSP_CLK_PERIOD

Display interface clock down time for read:

Tdicdr =

HSP_CLK

⋅ cei l

HSP_CLK_PERIOD

Display interface clock up time for read:

Tdi cur =

HSP_CLK

⋅ cei l

HSP_CLK_PERIOD

Display interface clock down time for write:

Tdi cdw =

HSP_CLK

⋅ cei l

HSP_CLK_PERIOD

Display interface clock up time for write:

Tdi cuw =

HSP_CLK

⋅ ce il

HSP_CLK_PERIOD

This parameter is a requirement to the display connected to the IPU.

Data read point:

Tdrp = T

HSP_CLK

⋅ cei l

HSP_CLK_PERIOD

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

The DISP#_IF_CLK_PER_WR, DISP#_IF_CLK_PER_RD, HSP_CLK_PERIOD,

DISP#_IF_CLK_DOWN_WR, DISP#_IF_CLK_UP_WR, DISP#_IF_CLK_DOWN_RD,

DISP#_IF_CLK_UP_RD and DISP#_READ_EN parameters are programmed via the

DI_DISP#_TIME_CONF_1, DI_DISP#_TIME_CONF_2 and DI_HSP_CLK_PER Registers.

4.3.16 Memory Stick Host Controller (MSHC)

Figure 65 , Figure 66

, and Figure 67 depict the MSHC timings, and Table 51 and

Table 52 list the timing

parameters.

tSCLKc tSCLKwh tSCLKwl

MSHC_SCLK tSCLKr tSCLKf

Figure 65. MSHC_CLK Timing Diagram tSCLKc

MSHC_SCLK tBSsu tBSh

MSHC_BS tDsu tDh

MSHC_DATA

(Output) tDd

MSHC_DATA

(Intput)

Figure 66. Transfer Operation Timing Diagram (Serial)

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics tSCLKc

MSHC_SCLK tBSsu tBSh

MSHC_BS tDsu tDh

MSHC_DATA

(Output) tDd

MSHC_DATA

(Intput)

Figure 67. Transfer Operation Timing Diagram (Parallel)

NOTE

The Memory Stick Host Controller is designed to meet the timing requirements per Sony's Memory Stick Pro Format Specifications document. Tables in this section details the specifications requirements for parallel and serial modes, and not the MCIMX31 timing.

Table 51. Serial Interface Timing Parameters

Standards

Signal Parameter Symbol Unit

MSHC_SCLK

MSHC_BS

MSHC_DATA

Cycle

H pulse length

L pulse length

Rise time

Fall time

Setup time

Hold time

Setup time

Hold time

Output delay time tSCLKc tSCLKwh tSCLKwl tSCLKr tSCLKf tBSsu tBSh tDsu tDh tDd

Min.

—

Max.

—

15 ns ns ns ns ns ns ns ns ns ns

Timing is guaranteed for NVCC from 2.7 through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See

NVCC restrictions described in

Table 8, "Operating Ranges," on page 13

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 52. Parallel Interface Timing Parameters

Standards

Signal Parameter Symbol Unit

MSHC_SCLK

MSHC_BS

MSHC_DATA

Cycle

H pulse length

L pulse length

Rise time

Fall time

Setup time

Hold time

Setup time

Hold time

Output delay time tSCLKc tSCLKwh tSCLKwl tSCLKr tSCLKf tBSsu tBSh tDsu tDh tDd

Min

—

Max

—

15 ns ns ns ns ns ns ns ns ns ns

Timing is guaranteed for NVCC from 2.7 through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See NVCC restrictions

described in Table 8, "Operating Ranges," on page 13 .

4.3.17 Personal Computer Memory Card International Association

(PCMCIA)

Figure 68

and Figure 69 depict the timings pertaining to the PCMCIA module, each of which is an

example of one clock of strobe set-up time and one clock of strobe hold time.

Table 53 lists the timing

parameters.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

D[15:0]

WAIT

REG

OE/WE/IORD/IOWR

CE1/CE2

POE

HCLK

HADDR

CONTROL

HWDATA

HREADY

HRESP

A[25:0]

ADDR 1

CONTROL 1

DATA write 1

OKAY

ADDR 1

DATA write 1

OKAY OKAY

REG

PSST PSL

Figure 68. Write Accesses Timing Diagram—PSHT=1, PSST=1

PSHT

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

HCLK

HADDR

CONTROL

RWDATA

HREADY

HRESP

A[25:0]

D[15:0]

WAIT

REG

OE/WE/IORD/IOWR

CE1/CE2

POE

ADDR 1

CONTROL 1

OKAY

ADDR 1

OKAY

DATA read 1

OKAY

REG

Symbol

PSHT

PSST

PSL

PSST PSL

Figure 69. Read Accesses Timing Diagram—PSHT=1, PSST=1

Table 53. PCMCIA Write and Read Timing Parameters

Parameter

PCMCIA strobe hold time

PCMCIA strobe set up time

PCMCIA strobe length

Min

Max

128

PSHT

Unit clock clock clock

4.3.18 PWM Electrical Specifications

This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

4.3.18.1

PWM Timing

Figure 70

depicts the timing of the PWM, and

Table 54

lists the PWM timing characteristics.

System Clock

PWM Output

Figure 70. PWM Timing

Table 54. PWM Output Timing Parameters

Parameter

System CLK frequency

Clock high time

Clock low time

Clock fall time

Clock rise time

Output delay time

Output setup time

CL of PWMO = 30 pF

Min

12.29

9.91

—

8.71

Max ipg_clk

—

0.5

9.37

—

4.3.19 SDHC Electrical Specifications

This section describes the electrical information of the SDHC.

4.3.19.1

SDHC Timing

Figure 71 depicts the timings of the SDHC, and Table 55

lists the timing parameters.

Unit

MHz ns ns ns ns ns ns

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

SD4

SD3 SD2

SD1

CLK

SD5

SD6

CMD

DATA[3:0]

Output from SDHC to card

SD7

CMD

DATA[3:0]

Input to SDHC

SD8

Figure 71. SDHC Timing Diagram

Table 55. SDHC Interface Timing Parameters

ID Parameter Symbol Min Max

Card Input Clock

SD1 Clock Frequency (Low Speed)

Clock Frequency (SD/SDIO Full Speed)

Clock Frequency (MMC Full Speed)

Clock Frequency (Identification Mode)

SD2 Clock Low Time

SD3 Clock High Time

SD4 Clock Rise Time

SD5 Clock Fall Time

SDHC Output/Card Inputs CMD, DAT (Reference to CLK)

SD6 SDHC output delay

SDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD7 SDHC input setup

SD8 SDHC input hold t f

1 f

2 f

3 f

4 t t t t

TLH

THL

ODL

100

—

–6.5

3 t

IS t

—

18.5

–11.5

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 V–3.3 V.

In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 MHz–25 MHz.

In normal data transfer mode for MMC card, clock frequency can be any value between 0 MHz–20 MHz.

In card identification mode, card clock must be 100 kHz–400 kHz, voltage ranges from 2.7 V–3.3 V.

400

—

Unit ns ns ns

4.3.20 SIM Electrical Specifications

Each SIM card interface consist of a total of 12 pins (for 2 separate ports of 6 pins each. Mostly one port with 5 pins is used).

kHz

MHz

MHz kHz ns ns ns ns

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

The interface is meant to be used with synchronous SIM cards. This means that the SIM module provides a clock for the SIM card to use. The frequency of this clock is normally 372 times the data rate on the

TX/RX pins, however SIM module can work with CLK equal to 16 times the data rate on TX/RX pins.

There is no timing relationship between the clock and the data. The clock that the SIM module provides to the aim card will be used by the SIM card to recover the clock from the data much like a standard UART.

All six (or 5 in case bi-directional TXRX is used) of the pins for each half of the SIM module are asynchronous to each other.

There are no required timing relationships between the signals in normal mode, but there are some in two specific cases: reset and power down sequences.

4.3.20.1

General Timing Requirements

Figure 72

shows the timing of the SIM module, and

Figure 56 lists the timing parameters.

1/Sfreq

CLK

Sfall Srise

Figure 72. SIM Clock Timing Diagram

Table 56. SIM Timing Specification—High Drive Strength

Num

Description

SIM Clock Frequency (CLK)

SIM CLK Rise Time

SIM CLK Fall Time

SIM Input Transition Time (RX, SIMPD)

50% duty cycle clock

With C = 50pF

Symbol

S freq

S rise

S fall

S trans

Min

0.01

—

Max

5 (Some new cards may reach 10)

Unit

MHz ns ns ns

4.3.20.2

Reset Sequence

4.3.20.2.1

Cards with Internal Reset

The sequence of reset for this kind of SIM Cards is as follows (see Figure 73 ):

• After powerup, the clock signal is enabled on SGCLK (time T0)

• After 200 clock cycles, RX must be high.

• The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles after T0.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

RX response

< 200 clock cycles

400 clock cycles <

Figure 73. Internal-Reset Card Reset Sequence

2 < 40000 clock cycles

4.3.20.2.2

Cards with Active Low Reset

The sequence of reset for this kind of card is as follows (see Figure 74

1. After powerup, the clock signal is enabled on CLK (time T0)

2. After 200 clock cycles, RX must be high.

3. RST must remain Low for at least 40000 clock cycles after T0 (no response is to be received on

RX during those 40000 clock cycles)

4. RST is set High (time T1)

5. RST must remain High for at least 40000 clock cycles after T1 and a response must be received on RX between 400 and 40000 clock cycles after T1.

SVEN

RST

CLK

SVEN

CLK

1 response

3 3

400 clock cycles <

400000 clock cycles <

Figure 74. Active-Low-Reset Card Reset Sequence

< 200 clock cycles

2 < 40000 clock cycles

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

4.3.20.3

Power Down Sequence

Power down sequence for SIM interface is as follows:

1. SIMPD port detects the removal of the SIM Card

2. RST goes Low

3. CLK goes Low

4. TX goes Low

5. VEN goes Low

Each of this steps is done in one CKIL period (usually 32 kHz). Power down can be started because of a

SIM Card removal detection or launched by the processor.

Figure 75 and Table 57

show the usual timing requirements for this sequence, with Fckil = CKIL frequency value.

Spd2rst

SIMPD

RST

Srst2clk

CLK

Srst2dat

DATA_TX

Srst2ven

SVEN

Figure 75. SmartCard Interface Power Down AC Timing

Table 57. Timing Requirements for Power Down Sequence

Num

Description

SIM reset to SIM clock stop

SIM reset to SIM TX data low

SIM reset to SIM Voltage Enable Low

SIM Presence Detect to SIM reset Low

Symbol

S rst2clk

S rst2dat

S rst2ven

S pd2rst

Min

0.9*1/FCKIL

1.8*1/FCKIL

2.7*1/FCKIL

0.9*1/FCKIL

Max

0.8

1.2

1.8

Unit

µs

µs ns

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

4.3.21 SJC Electrical Specifications

This section details the electrical characteristics for the SJC module.

Figure 76

depicts the SJC test clock input timing.

Figure 77

depicts the SJC boundary scan timing, Figure 78

depicts the SJC test access port,

Figure 79 depicts the SJC TRST timing, and Table 58 lists the SJC timing parameters.

TCK

(Input)

TCK

(Input)

Data

Inputs

Data

Outputs

SJ1

SJ2

VM VIH

VIL

SJ3 SJ3

Figure 76. Test Clock Input Timing Diagram

VIL

VIH

SJ4

Input Data Valid

SJ5

SJ6

Output Data Valid

SJ7

Data

Outputs

Data

Outputs

SJ6

Output Data Valid

Figure 77. Boundary Scan (JTAG) Timing Diagram

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

TCK

(Input)

TDI

TMS

(Input)

TDO

(Output)

VIL

SJ10

SJ8

Input Data Valid

VIH

SJ9

Output Data Valid

SJ11

TDO

(Output)

TDO

(Output)

SJ10

Output Data Valid

Figure 78. Test Access Port Timing Diagram

TCK

(Input)

SJ13

TRST

(Input)

SJ12

Figure 79. TRST Timing Diagram

Table 58. SJC Timing Parameters

ID Parameter

SJ1 TCK cycle time

SJ2 TCK clock pulse width measured at V

SJ3 TCK rise and fall times

SJ4 Boundary scan input data set-up time

SJ5 Boundary scan input data hold time

SJ6 TCK low to output data valid

SJ7 TCK low to output high impedance

SJ8 TMS, TDI data set-up time

SJ9 TMS, TDI data hold time

SJ10 TCK low to TDO data valid

All Frequencies

—

Min Max

100

—

Unit ns ns ns ns ns ns ns ns ns ns

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 58. SJC Timing Parameters (continued)

All Frequencies

ID Parameter Unit

SJ11 TCK low to TDO high impedance

SJ12 TRST assert time

SJ13 TRST set-up time to TCK low

Min Max

—

100

—

— ns ns ns

On cases where SDMA TAP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.

M - mid point voltage

4.3.22 SSI Electrical Specifications

This section describes the electrical information of SSI. Note the following pertaining to timing information:

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on AUDMUX signals when SSI is being used for data transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx

Data (for example, during AC97 mode of operation).

4.3.22.1

SSI Transmitter Timing with Internal Clock

Figure 80

depicts the SSI transmitter timing with internal clock, and

Table 59 lists the timing parameters.

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

SS2

SS1

SS5

SS4

AD1_TXC

(Output)

SS6 SS8

AD1_TXFS (bl)

(Output)

SS10

AD1_TXFS (wl)

(Output)

SS16

AD1_TXD

(Output)

AD1_RXD

(Input)

Note: SRXD Input in Synchronous mode only

SS43

SS42

SS1

SS2

SS5

SS4

SS14

SS17

SS3

SS15

SS18

SS12

SS3

SS19

DAM1_T_CLK

(Output)

SS6 SS8

DAM1_T_FS (bl)

(Output)

SS10

DAM1_T_FS (wl)

(Output)

SS16

SS14

SS17

SS15

DAM1_TXD

(Output)

SS43

SS42

SS19

DAM1_RXD

(Input)

Note: SRXD Input in Synchronous mode only

Figure 80. SSI Transmitter with Internal Clock Timing Diagram

SS18

SS12

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 59. SSI Transmitter with Internal Clock Timing Parameters

Max ID Parameter Min

Internal Clock Operation

SS1 (Tx/Rx) CK clock period

SS2

SS3

SS4

SS5

SS6

SS8

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

SS10

SS12

SS14

SS15

SS16

SS17

SS18

SS19

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Tx/Rx) Internal FS rise time

(Tx/Rx) Internal FS fall time

(Tx) CK high to STXD valid from high impedance

(Tx) CK high to STXD high/low

(Tx) CK high to STXD high impedance

STXD rise/fall time

—

Synchronous Internal Clock Operation

SS42

SS43

SS52

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

10.0

Loading —

—

81.4

36.0

—

36.0

—

15.0

—

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

4.3.22.2

SSI Receiver Timing with Internal Clock

Figure 81

depicts the SSI receiver timing with internal clock, and

Table 60 lists the timing parameters.

SS1

SS2

AD1_TXC

(Output)

AD1_TXFS (bl)

(Output)

SS7

AD1_TXFS (wl)

(Output)

SS9

SS11

SS5

SS4

SS3

SS20

SS21

AD1_RXD

(Input)

AD1_RXC

(Output)

SS48

SS47 SS51

SS50

SS49

SS2

SS1

SS5

SS4

SS3

DAM1_T_CLK

(Output)

SS7 SS9

DAM1_T_FS (bl)

(Output)

SS11

DAM1_T_FS (wl)

(Output)

SS20

SS21

DAM1_RXD

(Input)

SS47

SS48

SS51

SS50

SS49

DAM1_R_CLK

(Output)

Figure 81. SSI Receiver with Internal Clock Timing Diagram

SS13

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 60. SSI Receiver with Internal Clock Timing Parameters

Min Max ID Parameter

Internal Clock Operation

SS1 (Tx/Rx) CK clock period

SS2 (Tx/Rx) CK clock high period

SS3 (Tx/Rx) CK clock rise time

SS4 (Tx/Rx) CK clock low period

SS5 (Tx/Rx) CK clock fall time

SS7 (Rx) CK high to FS (bl) high

SS9 (Rx) CK high to FS (bl) low

SS11 (Rx) CK high to FS (wl) high

SS13 (Rx) CK high to FS (wl) low

SS20 SRXD setup time before (Rx) CK low

SS21 SRXD hold time after (Rx) CK low

Oversampling Clock Operation

SS47 Oversampling clock period

SS48 Oversampling clock high period

SS49 Oversampling clock rise time

SS50 Oversampling clock low period

SS51 Oversampling clock fall time

—

81.4

36.0

—

36.0

—

10.0

15.04

—

15.0

—

15.0

—

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

4.3.22.3

SSI Transmitter Timing with External Clock

Figure 82

depicts the SSI transmitter timing with external clock, and Table 61 lists the timing parameters.

SS22

SS23 SS25

SS26 SS24

AD1_TXC

(Input)

SS27

AD1_TXFS (bl)

(Input)

AD1_TXFS (wl)

(Input)

AD1_TXD

(Output)

SS29

SS31

SS37 SS38

SS39

SS33

SS45

SS44

AD1_RXD

(Input)

Note: SRXD Input in Synchronous mode only

SS46

SS22

SS23

SS26

SS25

SS24

DAM1_T_CLK

(Input)

SS27 SS29

DAM1_T_FS (bl)

(Input)

SS31

DAM1_T_FS (wl)

(Input)

SS37 SS38

DAM1_TXD

(Output)

SS45

SS44

DAM1_RXD

(Input)

SS46

Note: SRXD Input in Synchronous mode only

Figure 82. SSI Transmitter with External Clock Timing Diagram

SS39

SS33

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Electrical Characteristics

Table 61. SSI Transmitter with External Clock Timing Parameters

Min Max ID Parameter

External Clock Operation

SS22 (Tx/Rx) CK clock period

SS23 (Tx/Rx) CK clock high period

SS24 (Tx/Rx) CK clock rise time

SS25 (Tx/Rx) CK clock low period

SS26 (Tx/Rx) CK clock fall time

SS27 (Tx) CK high to FS (bl) high

SS29 (Tx) CK high to FS (bl) low

SS31 (Tx) CK high to FS (wl) high

SS33 (Tx) CK high to FS (wl) low

SS37 (Tx) CK high to STXD valid from high impedance

SS38 (Tx) CK high to STXD high/low

SS39 (Tx) CK high to STXD high impedance

Synchronous External Clock Operation

SS44 SRXD setup before (Tx) CK falling

SS45 SRXD hold after (Tx) CK falling

SS46 SRXD rise/fall time

81.4

36.0

—

36.0

—

–10.0

10.0

–10.0

10.0

—

10.0

2.0

—

6.0

15.0

—

15.0

—

6.0

—

15.0

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

100

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Electrical Characteristics

4.3.22.4

SSI Receiver Timing with External Clock

Figure 83

depicts the SSI receiver timing with external clock, and

Table 62 lists the timing parameters.

SS22

SS23

SS26

SS25

SS24

AD1_TXC

(Input)

SS28

AD1_TXFS (bl)

(Input)

AD1_TXFS (wl)

(Input)

AD1_RXD

(Input)

SS30

SS32

SS35

SS40

SS41

SS36

SS34

SS22

SS23

SS26

SS25

SS24

DAM1_T_CLK

(Input)

SS28 SS30

DAM1_T_FS (bl)

(Input)

SS32

DAM1_T_FS (wl)

(Input)

SS35

SS41 SS36

SS40

DAM1_RXD

(Input)

Figure 83. SSI Receiver with External Clock Timing Diagram

SS34

Table 62. SSI Receiver with External Clock Timing Parameters

Min Max ID Parameter

External Clock Operation

SS22 (Tx/Rx) CK clock period

SS23 (Tx/Rx) CK clock high period

SS24 (Tx/Rx) CK clock rise time

SS25 (Tx/Rx) CK clock low period

SS26 (Tx/Rx) CK clock fall time

81.4

36.0

—

36.0

—

6.0

—

6.0

Unit ns ns ns ns ns

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

101

Electrical Characteristics

Table 62. SSI Receiver with External Clock Timing Parameters (continued)

ID Parameter

SS28 (Rx) CK high to FS (bl) high

SS30 (Rx) CK high to FS (bl) low

SS32 (Rx) CK high to FS (wl) high

SS34 (Rx) CK high to FS (wl) low

SS35 (Tx/Rx) External FS rise time

SS36 (Tx/Rx) External FS fall time

SS40 SRXD setup time before (Rx) CK low

SS41 SRXD hold time after (Rx) CK low

Min

–10.0

10.0

–10.0

10.0

—

10.0

2.0

Max

6.0

—

15.0

—

15.0

—

Unit ns ns ns ns ns ns ns ns

4.3.23 USB Electrical Specifications

This section describes the electrical information of the USBOTG port. The OTG port supports both serial and parallel interfaces.

The high speed (HS) interface is supported via the ULPI (Ultra Low Pin Count Interface).

Figure 84

depicts the USB ULPI timing diagram, and

Table 63 lists the timing parameters.

Clock

Control out (stp)

Data out

Control in (dir, nxt)

Data in

Figure 84. USB ULPI Interface Timing Diagram

Table 63. USB ULPI Interface Timing Specification

102

Setup time (control in, 8-bit data in)

Hold time (control in, 8-bit data in)

Output delay (control out, 8-bit data out)

Timing parameters are given as viewed by transceiver side.

, T

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

6 —

0 —

— 9 ns ns ns

Freescale Semiconductor

Package Information and Pinout

5 Package Information and Pinout

This section includes the contact assignment information and mechanical package drawing for the

MCIMX31.

5.1

MAPBGA Production Package—457 14 x 14 mm, 0.5 mm Pitch

This section contains the outline drawing, signal assignment map (see Section 7, “Revision History

,”

Table 69

for the 0.5 mm 14

14 MAPBGA signal assignments), and MAPBGA ground/power ID by ball grid location for the 457 14 x 14 mm, 0.5 mm pitch package.

5.1.1 Production Package Outline Drawing–

14 x 14 mm 0.5 mm

Freescale Semiconductor

Figure 85. Production Package: Case 1581—0.5 mm Pitch

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

103

Package Information and Pinout

5.1.2 MAPBGA Signal Assignment–14

14 mm 0.5 mm

See

Section 7, “Revision History

,” Figure 69 for the 0.5 mm 14

14 MAPBGA signal assignments.

5.1.3 Connection Tables–

14 x 14 mm 0.5 mm

Table 64

shows the device connection list for power and ground, alpha-sorted. Table 65 shows the device

connection list for signals.

5.1.3.1

Ground and Power ID Locations– 14 x 14 mm 0.5 mm

Table 64. 14 x 14 MAPBGA Ground/Power ID by Ball Grid Location

GND/PWR ID Ball Location

NVCC10

NVCC21

NVCC22

QVCC

QVCC1

QVCC4

SGND

SVCC

UVCC

UGND

FGND AB24

FUSE_VDD AC24

FVCC AA24

GND

IOQVDD

A1, A2, A25, A26, B1, B2, B25, B26, C1, C2, C24, C25, C26, D1, D25, E22, E24, F21, L12, M11, M12, M13, M14,

M15, M16, N12, N13, N14, N15, N16, P12, P13, P14, P15, P16, R12, R13, R14, R15, R16, T12, T13, V17, AC2,

AC26, AD1, AD2, AD24, AD25, AD26, AE1, AE2, AE24, AE25, AE26, AF1, AF2, AF25, AF26

MGND

MVCC

NVCC1

NVCC2

T15

V15

G19, G21, K18

Y17, Y18, Y19, Y20

NVCC3

NVCC4

NVCC5

NVCC6

NVCC7

NVCC8

NVCC9

L9, M9, N11

L18, L19

E5, F6, G7

J15, J16, K15

N18, P18, R18, T18

J12, J13

J17

P9, P11, R11, T11

Y14, Y15, Y16

W7, Y7, Y8, Y9, Y10, Y11, Y12, Y13, AA6

J14, L13, L14, L15, L16, M18, U18, V10, V11, V12, V13

J10, J11, K9, L11

N9, R9, T9, U9

T14

V14

V16

T16

104

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Package Information and Pinout

5.1.3.2

BGA Signal ID by Ball Grid Location–14 x 14 0.5 mm

Table 65

shows the device connection list for signals only, alpha-sorted by signal identification.

Table 65. 14 x 14 BGA Signal ID by Ball Grid Location

Signal ID

A22

A23

A24

A25

ATA_CS0

ATA_CS1

ATA_DIOR

ATA_DIOW

ATA_DMACK

ATA_RESET

BATT_LINE

BCLK

BOOT_MODE0

BOOT_MODE1

BOOT_MODE2

BOOT_MODE3

BOOT_MODE4

CAPTURE

CAS

CE_CONTROL

CKIH

A15

A16

A17

A18

A19

A20

A21

A10

A11

A12

A13

A14

Ball Location

AE3

AD5

AF3

AF9

AF8

AF7

AF6

AE4

AA3

AF4

AB3

AB26

F20

C21

D24

C22

D26

A22

AD20

A14

F24

AF16

AF15

AF14

AF13

AF12

AB5

AF11

AF10

AD6

AF5

AF18

AC3

AD3

AD4

AF17

Signal ID

CKIL

CLKO

CLKSS

COMPARE

CONTRAST

CS0

CS1

CS2

CS3

CS4

CS5

CSI_D10

CSI_D11

CSI_D12

CSI_D13

CSI_D14

CSI_D15

CSI_D4

CSI_D5

CSI_D6

CSI_D7

CSI_D8

CSI_D9

CSI_HSYNC

CSI_MCLK

CSI_PIXCLK

CSI_VSYNC

CSPI1_MISO

CSPI1_MOSI

CSPI1_SCLK

CSPI1_SPI_RDY

CSPI1_SS0

CSPI1_SS1

CSPI1_SS2

CSPI2_MISO

CSPI2_MOSI

CSPI2_SCLK

CSPI2_SPI_RDY

CSPI2_SS0

CSPI2_SS1

CSPI2_SS2

CSPI3_MISO

CSPI3_MOSI

Ball Location

K20

K24

J26

J25

M20

M26

L21

K25

L24

K26

L20

L25

AE21

AD22

AF24

AF22

M24

L26

M21

M25

H21

C23

G26

G18

R24

AE23

AF23

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

105

Package Information and Pinout

Ball Location

B12

B13

C18

AE19

AD19

AA20

AE18

N26

A11

A12

T26

U25

AA2

AA1

AB1

R20

B11

G13

AB2

Y24

AD23

N21

F18

B23

C20

W25

C11

F12

C12

E25

G24

W21

Table 65. 14 x 14 BGA Signal ID by Ball Grid Location (continued)

Signal ID

CSPI3_SCLK

CSPI3_SPI_RDY

CTS1

CTS2

D10

D11

D12

D13

D14

D15

D3_CLS

D3_REV

D3_SPL

DCD_DCE1

DCD_DTE1

DQM0

DQM1

DQM2

DQM3

DRDY0

DSR_DCE1

DSR_DTE1

DTR_DCE1

DTR_DCE2

DTR_DTE1

DVFS0

DVFS1

EB0

EB1

ECB

FPSHIFT

GPIO1_0

GPIO1_1

GPIO1_2

LD7

Signal ID

GPIO1_3

GPIO1_4

GPIO1_5 (PWR RDY)

GPIO1_6

GPIO3_0

GPIO3_1

HSYNC

I2C_CLK

I2C_DAT

IOIS16

KEY_COL0

KEY_COL1

KEY_COL2

KEY_COL3

KEY_COL4

KEY_COL5

KEY_COL6

KEY_COL7

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW4

KEY_ROW5

KEY_ROW6

KEY_ROW7

L2PG

LBA

LCS0

LCS1

LD0

LD1

LD10

LD11

LD12

LD13

LD14

LD15

LD16

LD17

LD2

LD3

LD4

LD5

LD6

SCK6

Ball Location

B16

F14

A16

See VPG1

AE22

P26

P21

T24

U26

V24

B18

F15

A18

F13

B15

C14

A15

G14

J24

H25

C15

B17

G15

A17

C16

F25

F19

B24

A23

K21

H26

N25

V20

T21

V25

T20

V26

U24

Y25

Y26

V21

AA25

W24

AA26

106

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Package Information and Pinout

Ball Location

H24

E26

AF19

P20

J21

U21

W26

Y21

AC25

AC1

See VPG0

AB25

R21

F11

G12

C17

G11

B14

AB22

A10

A13

AD21

AF21

Table 65. 14 x 14 BGA Signal ID by Ball Grid Location (continued)

Signal ID

PC_BVD1

PC_BVD2

PC_CD1

PC_CD2

PC_POE

PC_PWRON

PC_READY

PC_RST

PC_RW

PC_VS1

PC_VS2

PC_WAIT

POR

POWER_FAIL

PWMO

RAS

READ

RESET_IN

LD8

LD9

M_GRANT

M_REQUEST

MA10

MCUPG

NFALE

NFCE

NFCLE

NFRB

NFRE

NFWE

NFWP

PAR_RS

RI_DCE1

RI_DTE1

RTCK

RTS1

RTS2

RXD1

RXD2

SCK3

SCK4

SCK5

SDCKE0

SDCKE1

Signal ID

SD20

SD21

SD22

SD23

SD24

SD25

SD26

SD27

SD28

SD29

SD13

SD14

SD15

SD16

SD17

SD18

SD19

SD2

SCLK0

SD_D_CLK

SD_D_I

SD_D_IO

SD0

SD1

SD1_CLK

SD1_CMD

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

SD10

SD11

SD12

SD3

SD30

SD31

SD4

SD5

SD6

SD7

SD8

SD9

SDBA0

SDBA1

TRSTB

TTM_PAD

Ball Location

AE10

AA11

AE9

AA10

AE8

AD10

AE7

AA9

AA8

AD9

AA14

AE13

AD13

AA13

AD12

AA12

AE11

AA19

AE15

AE14

AD14

B22

P24

N20

P25

AD18

AE17

AA18

AE6

AA7

AD17

AA17

AE16

AA16

AD15

AA15

AD7

AE5

B20

U20

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

107

Package Information and Pinout

Table 65. 14 x 14 BGA Signal ID by Ball Grid Location (continued)

Signal ID

SRX0

SRXD3

SRXD4

SRXD5

SRXD6

STX0

STXD3

STXD4

STXD5

STXD6

SVEN0

TCK

TDI

TDO

TMS

SDCLK

SDQS0

SDQS1

SDQS2

SDQS3

SDWE

SER_RS

SFS3

SFS4

SFS5

SFS6

SIMPD0

SJC_MOD

SRST0

Ball Location

A21

B19

F16

A19

G16

B21

F17

T25

G17

A20

C19

AA21

AE20

AD16

AE12

AD11

AD8

AF20

Signal ID

TXD1

TXD2

USB_BYP

USB_OC

USB_PWR

USBH2_CLK

USBH2_DATA0

USBH2_DATA1

USBH2_DIR

USBH2_NXT

USBH2_STP

USBOTG_CLK

USBOTG_DATA0

USBOTG_DATA1

USBOTG_DATA2

USBOTG_DATA3

USBOTG_DATA4

USBOTG_DATA5

USBOTG_DATA6

USBOTG_DATA7

USBOTG_DIR

USBOTG_NXT

USBOTG_STP

VPG0

VPG1

VSTBY

VSYNC0

VSYNC3

WATCHDOG_RST

WRITE

Ball Location

G25

J20

F26

N24

R26

A24

R25

G10

F10

C13

C10

B10

108

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Package Information and Pinout

5.2

MAPBGA Production Package—473 19 x 19 mm, 0.8 mm Pitch

This section contains the outline drawing, signal assignment map (see

Section 7, “Revision History

,”

Table 70

for the 19 x 19 mm, 0.8 mm pitch signal assignments), and MAPBGA ground/power ID by ball grid location for the 473 19 x 19 mm, 0.8 mm pitch package.

5.2.1 Production Package Outline Drawing–19 x 19 mm 0.8 mm

Freescale Semiconductor

Figure 86. Production Package: Case 1931—0.8 mm Pitch

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

109

Package Information and Pinout

5.2.2 MAPBGA Signal Assignment–19

19 mm 0.8 mm

See

Table 70 for the 19

19 mm, 0.8 mm pitch signal assignments/ball map.

5.2.3 Connection Tables–

19 x 19 mm 0.8 mm

Table 66

shows the device connection list for power and ground, alpha-sorted followed by

Table 67 , which

shows the no-connects.

Table 68 shows the device connection list for signals.

5.2.3.1

Ground and Power ID Locations— 19 x 19 mm 0.8 mm

Table 66. 19 x 19 BGA Ground/Power ID by Ball Grid Location

GND/PWR ID Ball Location

NVCC10

NVCC21

NVCC22

QVCC

QVCC1

QVCC4

SGND

SVCC

UVCC

UGND

FGND U16

FUSE_VDD T15

FVCC T16

GND

IOQVDD

A1, A2, A3, A21, A22, A23, B1, B2, B22, B23, C1, C2, C22, C23, D22, D23, J12, J13, K10, K11, K12, K13, K14,

L10, L11, L12, L13, L14, M9, M10, M11, M12, M13, M14, N10, N11, N12, N13, N14, P10, P11, P12, P13, P14,

R12, Y1, Y23, AA1, AA2, AA22, AA23, AB1, AB2, AB21, AB22, AB23, AC1, AC2, AC21, AC22, AC23

MGND

MVCC

NVCC1

NVCC2

U14

U15

G15, G16, H16, J17

N16, P16, R15, R16, T14

NVCC3

NVCC4

NVCC5

NVCC6

NVCC7

NVCC8

NVCC9

K7, K8, L7, L8

H14, J15, K15

G9, G10, H8, H9

G11, G12, G13, H12

H15, J16, K16, L16, M16

H10, H11, J11

G14

P8, R7, R8, R9, T9

T11, T12, T13, U11

T10, U7, U8, U9, U10, V6, V7, V8, V9, V10

H13, J14, L15, M15, N9, N15, P9, P15, R10, R11, R13, R14

J8, J9, J10, K9

L9, M7, M8, N8

U13

U12

P18

P17

110

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Package Information and Pinout

Table 67. 19 x 19 BGA No Connects

Signal Ball Location

U21

These contacts are not used and must be floated by the user.

5.2.3.2

BGA Signal ID by Ball Grid Location—19 x 19 0.8 mm

Table 68. 19 x 19 BGA Signal ID by Ball Grid Location

Signal ID

A24

A25

A19

A20

A21

A22

A23

A13

A14

A15

A16

A17

A18

A10

A11

A12

ATA_CS0

ATA_CS1

ATA_DIOR

ATA_DIOW

ATA_DMACK

ATA_RESET

BATT_LINE

BCLK

Ball Location

AA5

AC4

AB4

AA4

Y12

AB5

V12

Y11

V11

Y10

AC3

W20

Y15

Y14

V14

Y13

V13

AC5

V15

AB3

AA3

Signal ID

CKIL

CLKO

CLKSS

COMPARE

CONTRAST

CS0

CS1

CS2

CS3

CS4

CS5

CSI_D10

CSI_D11

CSI_D12

CSI_D13

CSI_D14

CSI_D15

CSI_D4

CSI_D5

CSI_D6

CSI_D7

CSI_D8

CSI_D9

CSI_HSYNC

CSI_MCLK

CSI_PIXCLK

CSI_VSYNC

CSPI1_MISO

CSPI1_MOSI

CSPI1_SCLK

CSPI1_SPI_RDY

CSPI1_SS0

CSPI1_SS1

CSPI1_SS2

Ball Location

J20

J21

L17

J22

J23

K20

H22

H20

K21

K22

K23

L20

L18

L21

H23

H21

E21

C20

H17

A20

N21

U17

Y22

Y18

Y19

Y20

AA21

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

111

Package Information and Pinout

Ball Location

P20

P21

N17

D12

F23

C12

F17

C21

D20

F18

E20

D18

AA20

M17

B10

A11

F10

C11

A10

E22

C10

D11

D16

AB19

Y16

AA18

AB18

Table 68. 19 x 19 BGA Signal ID by Ball Grid Location (continued)

Signal ID

D3_CLS

D3_REV

D3_SPL

D10

D11

D12

D13

D14

D15

BOOT_MODE0

BOOT_MODE1

BOOT_MODE2

BOOT_MODE3

BOOT_MODE4

CAPTURE

CAS

CE_CONTROL

CKIH

CSPI3_SCLK

CSPI3_SPI_RDY

CTS1

CTS2

DCD_DCE1

DCD_DTE1

DQM0

DQM1

DQM2

DQM3

DRDY0

DSR_DCE1

DSR_DTE1

DTR_DCE1

DTR_DCE2

DTR_DTE1

DVFS0

Signal ID

CSPI2_MISO

CSPI2_MOSI

CSPI2_SCLK

CSPI2_SPI_RDY

CSPI2_SS0

CSPI2_SS1

CSPI2_SS2

CSPI3_MISO

CSPI3_MOSI

GPIO1_3

GPIO1_4

GPIO1_5 (PWR RDY)

GPIO1_6

GPIO3_0

GPIO3_1

HSYNC

I2C_CLK

I2C_DAT

IOIS16

KEY_COL0

KEY_COL1

KEY_COL2

KEY_COL3

KEY_COL4

KEY_COL5

KEY_COL6

KEY_COL7

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW4

KEY_ROW5

KEY_ROW6

KEY_ROW7

L2PG

LBA

LCS0

LCS1

LD0

LD1

LD10

LD11

LD12

LD13

LD14

Ball Location

F13

A16

B16

A17

A13

B13

C13

A14

L23

J18

K18

A15

B15

D14

C15

G20

D21

D19

G18

G23

K17

F12

D13

B14

C14

See VPG1

V17

M22

N23

R23

R22

U22

R18

U20

V23

V22

112

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

Package Information and Pinout

Ball Location

P22

T18

E23

W22

W21

Y21

M23

C19

G17

B20

T20

R17

U23

U18

T17

See VPG0

AA19

N18

F22

D10

B11

D15

F21

F20

Table 68. 19 x 19 BGA Signal ID by Ball Grid Location (continued)

Signal ID

NFALE

NFCE

NFCLE

NFRB

NFRE

NFWE

NFWP

PAR_RS

PC_BVD1

PC_BVD2

PC_CD1

PC_CD2

PC_POE

PC_PWRON

PC_READY

PC_RST

PC_RW

DVFS1

EB0

EB1

ECB

FPSHIFT

GPIO1_0

GPIO1_1

GPIO1_2

LD7

LD8

LD9

M_GRANT

M_REQUEST

MA10

MCUPG

PC_VS1

PC_VS2

PC_WAIT

POR

POWER_FAIL

PWMO

RAS

READ

RESET_IN

RI_DCE1

RI_DTE1

RTCK

RTS1

Signal ID

SD1_CLK

SD1_CMD

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

SD10

SD11

SD12

SD13

SD14

SD15

SD16

SD17

SD18

SD19

SD2

SD20

LD15

LD16

LD17

LD2

LD3

LD4

LD5

LD6

SCK6

SCLK0

SD_D_CLK

SD_D_I

SD_D_IO

SD0

SD1

SD21

SD22

SD23

SD24

SD25

SD26

SD27

SD28

SD29

SD3

SD30

SD31

SD4

Ball Location

AA13

AB13

AC13

AA12

AC12

AA11

AB11

AC11

AB17

AA10

AB14

AC14

T21

B19

M21

M20

M18

AC18

AA17

V21

V20

W23

R21

R20

T23

T22

AB10

AC10

AC9

AA9

AC8

AB8

AC7

AA8

AB7

AC17

AA7

AC6

AA16

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

113

Package Information and Pinout

Ball Location

C18

A19

F16

AB20

P23

B18

C17

D17

F14

A18

B17

C16

Y17

V16

AC20

AC19

AB16

AB12

AB9

AB6

B12

V18

A12

Table 68. 19 x 19 BGA Signal ID by Ball Grid Location (continued)

Signal ID

SDWE

SER_RS

SFS3

SFS4

SFS5

SFS6

SIMPD0

SJC_MOD

SRST0

SRX0

SRXD3

SRXD4

SRXD5

SRXD6

STX0

STXD3

RTS2

RXD1

RXD2

SCK3

SCK4

SCK5

SDCKE0

SDCKE1

SDCLK

SDQS0

SDQS1

SDQS2

SDQS3

STXD4

STXD5

STXD6

SVEN0

TCK

TDI

TDO

TMS

Signal ID

SD5

SD6

SD7

SD8

SD9

SDBA0

SDBA1

TRSTB

TXD1

TXD2

USB_BYP

USB_OC

USB_PWR

USBH2_CLK

USBH2_DATA0

USBH2_DATA1

USBH2_DIR

USBH2_NXT

USBH2_STP

USBOTG_CLK

USBOTG_DATA0

USBOTG_DATA1

USBOTG_DATA2

USBOTG_DATA3

USBOTG_DATA4

USBOTG_DATA5

USBOTG_DATA6

USBOTG_DATA7

USBOTG_DIR

USBOTG_NXT

USBOTG_STP

VPG0

VPG1

VSTBY

VSYNC0

VSYNC3

WATCHDOG_RST

WRITE

Ball Location

G21

G22

H18

L22

N20

B21

N22

F15

F11

AC16

AA15

AB15

AC15

AA14

AA6

114

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

Freescale Semiconductor

5.3 Ball Maps

Table 69. Ball Map—14 x 14 0.5 mm Pitch

GND

3 4 5 6 7 8 9

SFS5 CSPI2

_MISO

CSPI2_

SS2

USBOT

G_DAT

USBOT

G_DAT

USBOT

G_NXT

USB_

BYP

STXD4 SRXD

10 12 13 14 15

RXD1 DSR_D

CE1

DSR_D

TE1

RXD2 CE_CO

NTROL

KEY_R

OW3

CSPI2_

SS0

CSPI2_

SPI_R

USBOT

G_DAT

USBOT

G_DAT

USBOT

G_DIR

USB_P

CTS1 DCD_D

CE1

DCD_D

TE1

RTS2 KEY_R

OW1

KEY_R

OW7

KEY_C

OL3

KEY_R

OW5

KEY_C

OL1

18 19

KEY_C

OL7

TDO

KEY_C

OL5

TCK

SJC_M

21 22

SVEN0 CAPTU

23 24

GPIO1_

WATCH

DOG_R

GND

TRSTB SRX0 SCLK0 GPIO1_

GPIO1_

GND

CSPI3_

MOSI

SCK5

E CSPI3_

SCLK

ATA_DI

SRXD4 SCK4 STXD5 CSPI2_

SS1

CSPI2_

SCLK

USBOT

G_DAT

CSPI2_

MOSI

NVCC5

USBOT

G_STP

USB_O

DTR_D

CE1

DTR_D

TE1

TXD2 KEY_R

OW2

KEY_C

OL0

F ATA_D

MACK

ATA_C

SFS4

KEY_C

OL4

RTCK DE

M USBH2

N USBH2

_CLK

PC_BV

PC_RE

ADY

SD1_D

ATA3

SD1_C

USBH2

_STP

MISO

ATA_R

ESET

IOIS16

PC_PW

RON

SD1_D

ATA2

USBH2

_DATA1

CSPI1_

SCLK

CSPI1_

SPI_RD

P CSPI1_

SS1

CSPI1_

MOSI

CSPI1_

SS0

R STXD3 SCK3 SRXD3

PWMO PC_RW CSPI3_

PC_RS

PC_VS

PC_CD

SD1_D

ATA1

_DATA0

STXD6 SCK6

NFRB NFWP

SFS6

NFCLE

NVCC1

GND

SGND

GND

MGND UGND

SRST0 GPIO1

BOOT_

MODE1

NVCC5 BATT_L

INE

USBOT

G_DAT

USBOT

G_DAT

TXD1 RI_DC

CSPI3_

SPI_R

ATA_DI

ATA_C

PC_BV

PC_WA

SD1_D

ATA0

NVCC5

PC_PO

PC_VS

PC_CD

SD1_C

USBH2

_NXT

USBH2

_DIR

USBOT

G_DAT

USBOT

G_CLK

RTS1 RI_DT

QVCC1

NVCC3

QVCC4

DTR_D

CE2

KEY_R

OW0

CTS2

KEY_R

OW6

KEY_C

OL6

KEY_R

OW4

QVCC1 QVCC1 NVCC8 NVCC8 QVCC

QVCC1 GND

GND GND

NVCC3 GND

QVCC

GND

QVCC

GND

KEY_C

OL2

TDI

TMS

STX0

SIMPD

NVCC6 NVCC6 NVCC9

NVCC6

QVCC

GND

QVCC

GND

GPIO1

COMP

ARE

NVCC1 CSI_H

SYNC

GPIO3_

NVCC4 NVCC4 CSI_D8 CSI_D4

QVCC

NVCC7

GPIO1

NVCC1

BOOT_

MODE

GND

NVCC1

VPG1 RESET_

CSI_D1

CKIL

CSI_D1

SD_D_I FPSHIF

CSPI1_

SS2

SFS3

NFCE

CSPI1_

MISO

SRXD6

NFWE

NVCC1

QVCC4

NVCC7

READ

D3_CL

LD4

LCS1

PAR_RS

LD2

BOOT_

MODE3

GND

CLKO GND

BOOT_

MODE2

GND

CKIH

DVFS1

POR

I2C_CL

SD_D_

CLK

CONTR

AST

LD0

LD6

GND

GPIO1_

VPG0

I2C_DA

CSI_VS

YNC

GPIO3_

CSI_PIX

CLK

CSI_MC

CSI_D5 CSI_D7 K

L CSI_D6 CSI_D9 CSI_D1

CSI_D1

VSYNC

HSYNC DRDY0 N

SD_D_I

GND

BOOT_

MODE4

DVFS0 POWER

_FAIL

VSTBY

CLKSS

LCS0

WRITE VSYNC

SER_R

D3_REV

D3_SPL LD1

W D14

NFALE NFRE

D10

AA D6

D12

D13

D15

D11

QVCC4

QVCC QVCC QVCC QVCC SVCC MVCC UVCC GND

QVCC TTM_P

LD8

LD17 LD13

IOQVD

NVCC2

SD31 SD28 SD27 SD23 SD21 SD18 SD16 SD13 SD9

EB0

NVCC2

NVCC2 NVCC2 NVCC2 NVCC2 M_GRA

SD7 SD5 SD3 SD2 DQM2 SDCLK

LD10

LD15

EB1

FVCC

LD3

LD7

LD11

LD14

LD5

LD9

LD12

LD16

AB D2 D0

AC MA10 GND

AD GND GND

A11

A12 A13

A8 A0 SDBA0 SDQS3 SD29 SD25 SDQS2 SD17 SD15 SD12 SD8 SDQS0 SD4

CS3 ECB

FGND OE

FUSE_V

M_REQ

UEST

GND GND

BCLK

GND

AE GND

AF GND

GND

SDBA1 SD30

A25

SD26

A24

SD24

A23

SD22

A22

SD20

A21

SD19

A20

SDQS1 SD14

A19

A18

SD11

A17

SD10

A16

SD6

A15

SD1

A14

SD0 DQM1 CAS SDCKE

DQM3 DQM0 SDCLK CS2

A10 RAS SDWE SDCKE

18 19 20 21

LBA

CS5

CS0

CS1

GND

CS4

GND

Table 70. Ball Map—19 x 19 0.8 mm Pitch

GND

ATA_

CS0

PC_

RST

SD1_

DATA1

USBH2_

DATA1

CSPI1_

MOSI

GND

STXD4

SRXD4

4 5 6

CSPI2_

SS1

USBOTG_

DATA6

USBOTG

_DATA2

CSPI2_

MISO

SRXD5

CSPI2_

SCLK

CSPI2_

SS0

USBOTG_

DATA5

USBOTG_

DATA7

USBOTG

_DIR

USBOTG_

NXT

USBOTG_

DATA1

D STXD5

CSPI3_

MISO

ATA_

DMACK

PWMO

G PC_VS2

PC_

BVD1

H PC_CD2

PC_

READY

SD1_

DATA2

SD1_

CLK

SFS4

ATA_

DIOR

ATA_

RESET

PC_

VS1

PC_

CD1

SD1_

CMD

SCK5

CSPI3_

MOSI

CSPI3_

SPI_RDY

ATA_

CS1

PC_

BVD2

PC_

WAIT

SD1_

DATA0

USBH2_

CLK

USBH2_

DIR

USBH2_

STP

USBH2_

NXT

CSPI1_S

PI_RDY

CSPI1_

SS0

CSPI1_

SS2

CSPI1_

SCLK

CSPI1_

MISO

SRXD3 STXD3

USB_

PWR

USB_

BYP

CTS1

RTS1

RXD1

CSPI2_

MOSI

CSPI2_SPI USBOTG_ USBOTG_

_RDY DATA4 CLK

TXD1

DTR_

DTE1

DSR_

DCE1

DCD_

DCE1

RI_

DCE1

DSR_

DTE1

RI_

DTE1

DTR_

DCE2

DCD_

DTE1

RXD2

RTS2

CTS2

KEY_

ROW0

KEY_

ROW1

KEY_

ROW2

CE_

CONTROL

KEY_

ROW5

KEY_

ROW3

KEY_

ROW6

KEY_

ROW7

KEY_

COL2

KEY_

COL0

KEY_

COL1

KEY_

COL3

RTCK

KEY_

COL5

KEY_

COL6

TMS

KEY_

COL7

TDI

SRX0

COMPARE

GND

TDO

SJC_

MOD

WATCH

SIMPD0 SCLK0 GPIO1_2

DOG_RST

SRST0

GPIO1

CLKO

SVEN0 CAPTURE

GPIO1

BOOT_

MODE2

BOOT_

MODE1

GPIO1_4

GND

BOOT_

MODE4

POWER_

FAIL

CKIL

POR

DVFS0

RESET_

GND

DVFS1

CKIH

BATT_

LINE

SCK4

ATA_

DIOW

PC_POE

PC_

PWRON

SD1_

DATA3

USBH2_

DATA0

CSPI1_

SS1

CSPI2_

SS2

SFS5

USBOTG_

DATA3

USBOT

G_STP

DTR_

DCE1

TXD2

KEY_

ROW4

KEY_

COL4

TCK TRSTB STX0

BOOT_

MODE0

BOOT_

MODE3

USBOTG_

DATA0

NVCC5 NVCC5 NVCC6 NVCC6 NVCC6 NVCC9 NVCC1 NVCC1 GPIO1_1 GPIO1_6

CSPI3_

SCLK

NVCC5 NVCC5 NVCC8 NVCC8 NVCC6 QVCC NVCC4 NVCC7 NVCC1 CLKSS VSTBY

IOIS16

NVCC3

QVCC4

QVCC1

NVCC3

QVCC4

QVCC1 QVCC1 NVCC8

QVCC1

QVCC4

GND

QVCC

GND

QVCC

GND

NVCC4 NVCC7

QVCC

NVCC7

NVCC2

NVCC1

GPIO3_1

CSI_D6

DRDY0

D3_

SPL

I2C_

CLK

I2C_

DAT

CSI_

D14

SD_D_

READ

GPIO1_3

CSI_

MCLK

CSI_D4

CSI_D9

VPG0

CSI_

VSYNC

CSI_D5

CSI_

D10

SD_D_

CLK

VPG1 GPIO3_0 G

CSI_HSY CSI_PIX

NC CLK

CSI_D7 CSI_D8 J

CSI_

D11

CSI_

D12

CSI_D13 CSI_D15 VSYNC0 HSYNC L

SD_D_I

VSYNC3 CONTRAST

LCS0

WRITE

FPSHIFT M

LCS1 N

P SCK3 SFS3 STXD6 SFS6 NFWP

NVCC10 QVCC GND GND GND GND GND QVCC NVCC2 UGND UVCC D3_CLS

D3_

REV

PAR_

SER_

R SRXD6

T NFCLE

SCK6

NFALE

NFRB

NFWE

NFCE

NFRE

D13

NVCC10 NVCC10

NVCC1

QVCC QVCC

GND QVCC QVCC

IOQVDD

NVCC1

NVCC22 NVCC21 NVCC21 NVCC21 NVCC2

NVCC2 NVCC2

FUSE_

VDD

FVCC

LD8

REQUEST

LD11

LD3

LD7

LD2

LD6

LD1

LD5

LD0

LD4

D15

D10

D14

D12

D11

D0 NVCC22 NVCC22

NVCC2

NVCC22 NVCC21 SVCC

NVCC22 NVCC22 NVCC22

NVCC2

NVCC22 A22 A20

SGND

A18

MGND

A16

MVCC

A10

FGND

SDCKE1

CS0

LBA

GRANT

LD12

LD16

LD15

LD10

LD14

LD9

LD13

W D7 D5 D2 D1 BCLK EB1 EB0 LD17 W

Y GND MA10 A13

AA GND GND

AB GND GND

A12

A11

AC GND GND A9

SDBA0

SDBA1

SD30

SDQS3 SD29

SD31 SD27

A25

SD28

A24 A23

SD24 SD20

A21

SD17

A19

SD15

A17

SD12

A15

SD9

SD26 SDQS2 SD21 SD18 SDQS1 SD13 SD10

A14 DQM1 SDCKE0

SD6

SD7

SD4

SDQS0

SD1

SD2

CS2 CS3 CS4

DQM2 RAS CAS

DQM3 DQM0 SDWE

SD25 SD23 SD22

10 1 2 3 4 5 6 7 8 9

These contacts are not used and must be floated by the user.

SD19

SD16

SD14

SD11

SD8

SD5

SD3

ECB

CS5

GND

SD0 SDCLK SDCLK

18 19 20

GND

CS1 GND Y

GND GND AA

GND GND AB

GND

GND AC

Product Documentation

6 Product Documentation

This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data.

Definitions of these types are available at: http://www.freescale.com.

MCIMX31 Product Brief (order number MCIMX31PB)

MCIMX31 Reference Manual (order number MCIMX31RM)

MCIMX31 Chip Errata (order number MCIMX31CE)

The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web

site, or printed versions may be ordered. ARM Ltd. documentation is available from http://www.arm.com.

7 Revision History

Table 71

summarizes revisions to this document since the release of Rev. 4.1.

Table 71. Revision History

Rev.

Location Revision

4.3

Table 1, "Ordering Information," on page 3

Added a footnote and new part numbers for silicon revision 2.0.1.

4.2

Global Replaced all references to silicon 2.0 with silicon revision 2.0.1.

4.2

Table 1, "Ordering Information," on page 3

Added new part numbers for revision 2.0.1.

4.2

Section 1.2.1, “Feature Differences

Between Mask Sets

Updated for revision 2.0.1.

4.2

Table 8, "Operating Ranges," on page 13

Updated Core Operating voltage ranges and respective footnotes.

4.2

Table 12, "Current Consumption for

–40×C to 85×C, for Silicon Revision

2.0.1," on page 16

Updated for silicon revision 2.0.1.

Updated values for silicon revision 2.0.1.

4.2

Table 13, "Current Consumption for

–20×C to 70×C, for Silicon Revision

2.0.1," on page 17

4.2

Section 3, “Signal Descriptions

Removed reference to the TTM_PAD as it is no longer connected.

Freescale Semiconductor

MCIMX31/MCIMX31L Technical Data, Rev. 4.3

117

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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ARM, ARM

Thumb, Jazelle, and the ARM Powered logo are registered trademarks of ARM Limited.

ARM1136JF-S, ARM11, Embedded Trace Kit, Embedded Trace Macrocell, ETM, Embedded Trace

Buffer, and ETB are trademarks of ARM Limited. All other product or service names are the property of their respective owners. Java and all other Java-based marks are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. France Telecom – TDF –

Groupe des ecoles des telecommunications Turbo codes patents license.

Document Number: MCIMX31_5

Rev. 4.3

12/2009

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