NXP i.MX31 Applications Processors - Integrated Image Processing Unit (IPU), Connectivity , Arm11™ Core Reference Manual

MCIMX31 and MCIMX31L
Applications Processors
Reference Manual
MCIMX31RM
Rev. 2.4
12/2008
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Contents
Paragraph
Number
Title
Page
Number
Contents
Contents
About This Book
Audience ......................................................................................................................cxxvii
Organization.................................................................................................................cxxvii
Book I, i.MX31 and i.MX31L Integration and Description ...................................... cxxviii
Device Introduction and Memory Map ................................................................. cxxviii
Clocks, Power Management and Reset.................................................................. cxxviii
Pins......................................................................................................................... cxxviii
Debug..................................................................................................................... cxxviii
Boot........................................................................................................................ cxxviii
Book II, Applications Processors’ Core and Peripherals........................................... cxxviii
ARM11 Core and Interrupts .................................................................................. cxxviii
Security .................................................................................................................. cxxviii
Memory Systems ......................................................................................................cxxix
External Interfaces ....................................................................................................cxxix
Connectivity Peripherals...........................................................................................cxxix
Timer Peripherals......................................................................................................cxxix
System Control Peripherals .......................................................................................cxxx
Multimedia Peripherals..............................................................................................cxxx
Suggested Reading.........................................................................................................cxxx
Conventions .................................................................................................................cxxxii
Definitions, Acronyms, and Abbreviations .................................................................cxxxii
USBOTG References...................................................................................................cxli
Glossary of Terms and Abbreviations............................................................................ cxlii
Chapter 1
Introduction to the i.MX31 and i.MX31L Multimedia Applications Processors
1.1
1.1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
Architectural Overview.................................................................................................... 1-1
High-Level Block Diagram ......................................................................................... 1-2
Hardware Modules........................................................................................................... 1-4
System Control ............................................................................................................ 1-5
ARM11 Platform ......................................................................................................... 1-5
Standard System Functional Elements ........................................................................ 1-5
Multimedia and Human Interface ................................................................................ 1-5
Peripherals ................................................................................................................... 1-6
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Paragraph
Number
1.2.6
1.2.7
1.2.8
1.2.8.1
1.2.8.1.1
1.2.8.1.2
1.2.8.1.3
1.2.9
1.2.9.1
1.2.10
1.2.11
1.2.11.1
1.2.11.2
1.2.11.3
1.2.12
1.2.12.1
1.2.13
1.2.14
1.2.14.1
1.2.14.1.1
1.2.14.2
1.2.14.2.1
1.2.14.2.2
1.2.14.2.3
1.2.14.3
1.2.14.4
1.2.14.4.1
1.2.14.4.2
1.2.14.4.3
1.2.15
1.2.15.1
1.2.15.2
1.2.16
1.2.16.1
1.2.16.2
1.2.16.3
1.2.17
1.2.17.1
1.2.17.2
1.2.17.2.1
1.2.17.2.2
Page
Number
Title
Special Functional Blocks ........................................................................................... 1-7
Detailed Block Diagram .............................................................................................. 1-7
Applications Processor Core (ARM11 Core) .............................................................. 1-8
Memory System....................................................................................................... 1-8
Internal RAM....................................................................................................... 1-8
Internal ROM....................................................................................................... 1-8
Internal Registers ................................................................................................. 1-9
Interrupts...................................................................................................................... 1-9
ARM11 Platform Vectored Interrupt Controller (AVIC)......................................... 1-9
External Memory Interface (EMI) ............................................................................. 1-10
Clock Power Management and Reset ........................................................................ 1-10
Clocking and Synchronization............................................................................... 1-10
Power Management ............................................................................................... 1-11
Reset Module ......................................................................................................... 1-12
Pins............................................................................................................................. 1-12
Multiplexing, GPIO, and Pad Control Architecture .............................................. 1-12
Security ...................................................................................................................... 1-13
Connectivity............................................................................................................... 1-13
Wired Connectivity................................................................................................ 1-13
UART x 5........................................................................................................... 1-13
USB Module .......................................................................................................... 1-13
USB Host Port 1 ................................................................................................ 1-13
USB Host Port 2 ................................................................................................ 1-13
USBOTG Port.................................................................................................... 1-14
PCMCIA Port ........................................................................................................ 1-14
Wireless Connectivity............................................................................................ 1-14
Fast Infrared Interface (FIR).............................................................................. 1-14
Bluetooth ........................................................................................................... 1-14
Wireless LAN 802.11a/b ................................................................................... 1-14
Timers ........................................................................................................................ 1-15
General Timers ...................................................................................................... 1-15
Watchdog Timer (WDOG) .................................................................................... 1-15
System Resources ...................................................................................................... 1-15
AIPS....................................................................................................................... 1-15
Smart Direct Memory Access Controller (SDMA) ............................................... 1-16
ATA Controller ...................................................................................................... 1-17
Image, Video and Graphics........................................................................................ 1-17
Video Processing ................................................................................................... 1-17
Graphics Processing Unit ...................................................................................... 1-18
Graphics Processing Unit Overview.................................................................. 1-19
Graphics Processing Unit Features.................................................................... 1-20
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Number
1.2.17.3
1.2.17.4
1.2.17.4.1
1.2.17.4.2
1.2.17.4.3
1.2.17.4.4
1.2.17.4.5
1.2.17.4.6
1.2.17.4.7
1.2.17.4.8
1.2.17.4.9
1.2.17.4.10
1.2.17.5
1.2.18
1.2.18.1
1.2.18.2
1.2.19
1.2.19.1
1.2.20
1.2.20.1
Title
Page
Number
Display Management ............................................................................................. 1-20
Image Processing Unit ........................................................................................... 1-21
External Ports .................................................................................................... 1-22
Connectivity to Displays ................................................................................... 1-23
Synchronous Interface ....................................................................................... 1-23
Asynchronous Interface ..................................................................................... 1-23
Simultaneous Connectivity................................................................................ 1-24
IPU Processing .................................................................................................. 1-25
Post-Processing.................................................................................................. 1-25
Video Capturing................................................................................................. 1-25
Processing Stages............................................................................................... 1-26
Automatic Procedures........................................................................................ 1-26
MPEG-4 Video Encoder ........................................................................................ 1-27
Audio Interfaces......................................................................................................... 1-27
Synchronous Serial Interface or Inter-IC Sound (SSI/I2S) Module ...................... 1-27
Digital Audio MUX............................................................................................... 1-28
Debug Features .......................................................................................................... 1-28
Features.................................................................................................................. 1-29
Boot............................................................................................................................ 1-29
Boot Features ......................................................................................................... 1-30
Chapter 2
System Memory Map, Interrupts, and SDMA Events
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.2
2.2.1
2.2.2
2.3
Memory Map ................................................................................................................... 2-1
Internal RAM............................................................................................................... 2-4
Internal ROM............................................................................................................... 2-4
Internal Register Space ................................................................................................ 2-5
Peripheral Access Types .............................................................................................. 2-5
External Memory ......................................................................................................... 2-6
Misaligned Accesses.................................................................................................... 2-6
Interrupts .......................................................................................................................... 2-6
Interrupt Operation ...................................................................................................... 2-6
Interrupt Summary Table ............................................................................................. 2-7
Smart Direct Memory Access (SDMA) Events............................................................... 2-9
Chapter 3
Clocks, Power Management and Reset (AP Clock Controller Module)
3.1
3.2
Overview.......................................................................................................................... 3-1
PLLs................................................................................................................................. 3-1
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Paragraph
Number
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.2
3.3
3.3.1
3.3.2
3.4
3.4.1
3.4.2
3.4.3
3.4.3.1
3.4.3.2
3.4.3.3
3.4.3.4
3.4.3.5
3.4.3.5.1
3.4.3.6
3.4.3.6.1
3.4.3.7
3.4.3.7.1
3.4.3.8
3.4.3.9
3.4.3.10
3.4.3.11
3.4.3.12
3.4.3.13
3.4.3.14
3.4.3.15
3.4.3.16
3.4.3.17
3.4.3.18
3.4.3.19
3.4.3.20
3.4.3.21
3.4.4
3.4.4.1
3.4.4.1.1
3.4.4.2
3.4.4.2.1
Page
Number
Title
PLL Reference Clock Sources.................................................................................... 3-1
External High Frequency Clock—CKIH................................................................. 3-1
Frequency Pre-Multiplier (FPM) ............................................................................. 3-2
PLL Reference Clock Switch Unit .......................................................................... 3-2
High Frequency Clock Source..................................................................................... 3-2
CCM................................................................................................................................. 3-3
Features........................................................................................................................ 3-3
External Signal Description ......................................................................................... 3-3
Register Definition and Memory Map............................................................................. 3-3
Memory Map ............................................................................................................... 3-3
Register Summary........................................................................................................ 3-5
Register Descriptions................................................................................................... 3-9
Control Register (CCMR)........................................................................................ 3-9
Post Divider Register 0 (PDR0) ............................................................................ 3-12
Post Divider Register 1 (PDR1) ............................................................................ 3-14
Reset Control and Source Register (RCSR) .......................................................... 3-15
MCU PLL Control Register (MPCTL).................................................................. 3-17
Calculating MPLL’s Output Frequency............................................................. 3-18
USB PLL Control Register (UPCTL).................................................................... 3-19
Calculating USB PLL Output Frequency .......................................................... 3-20
SR PLL Control Register (SPCTL) ....................................................................... 3-21
Calculating SRPLL Output Frequency.............................................................. 3-22
Clock Out Source Register (COSR) ...................................................................... 3-23
Clock Gating Registers (CGR0–CGR2)................................................................ 3-24
Wake-Up Interrupt Mask Register (WIMR0)........................................................ 3-27
Latch Divergence Counter Register (LDC) ........................................................... 3-27
DPTC Comparator Value Registers (DCVR0–DCVR3) ....................................... 3-28
Load Tracking Register (LTR0)............................................................................. 3-29
Load Tracking Register (LTR1)............................................................................. 3-30
Load Tracking Register (LTR2)............................................................................. 3-31
Load Tracking Register (LTR3)............................................................................. 3-32
Load Tracking Buffer Register (LTBR0)............................................................... 3-33
Load Tracking Buffer Register (LTBR1)............................................................... 3-34
Power Management Control Register 0 (PMCR0)................................................ 3-35
Power Management Control Register 1 (PMCR1)................................................ 3-38
Post Divider Register 2 (PDR2) ............................................................................ 3-39
Functional Description............................................................................................... 3-40
Clock Sources ........................................................................................................ 3-41
External Low Frequency Clock—CKIL............................................................ 3-41
MCU Clock Domain Clocks.................................................................................. 3-42
MCU Clock Domain Clock Source Switch Unit............................................... 3-42
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Paragraph
Number
3.4.4.2.2
3.4.4.2.3
3.4.4.3
3.4.4.3.1
3.4.4.3.2
3.4.4.3.3
3.4.4.3.4
3.4.4.3.5
3.4.4.3.6
3.4.4.3.7
3.4.4.3.8
3.4.4.3.9
3.4.4.3.10
3.4.4.4
3.4.4.4.1
3.4.4.5
3.4.4.6
3.4.4.7
3.4.4.8
3.5
3.5.1
3.5.2
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4
3.5.2.5
3.5.2.6
3.5.3
3.5.4
3.5.4.1
3.5.4.1.1
3.5.5
3.5.5.1
3.5.5.1.1
3.5.5.1.2
3.5.5.1.3
3.5.5.1.4
3.5.5.1.5
3.5.6
3.5.7
Title
Page
Number
MCU Clock Domain Clocks.............................................................................. 3-42
Clock Generation—ipg_ckil_sync Clock .......................................................... 3-43
USB Clock Domain ............................................................................................... 3-44
USB Clock Domain Switch Unit....................................................................... 3-44
USB Clock Domain Clocks ............................................................................... 3-44
Clock Generation—ipg_clk_firi_baud .............................................................. 3-44
Clock Generation—ipg_clk_ssi1_baud ............................................................. 3-45
Clock Generation—ipg_clk_ssi2_baud ............................................................. 3-45
Clock Generation—ipg_sim_baud .................................................................... 3-45
Clock Generation—ipg_per_baud ..................................................................... 3-45
Clock Generation—ipg_clk_csi_baud............................................................... 3-45
Clock Generation—ipg_clk_mstick1_baud ...................................................... 3-45
Clock Generation—ipg_clk_mstick2_baud ...................................................... 3-45
SR Clock Domain .................................................................................................. 3-46
SR Clock Switch Unit........................................................................................ 3-46
Clock Cleaner ........................................................................................................ 3-46
Low Power Clock Gating (LPCG) ........................................................................ 3-46
SDRAM Controller Handshake Mechanism ......................................................... 3-46
Power Fail .............................................................................................................. 3-46
Power Management ....................................................................................................... 3-47
Power Domains.......................................................................................................... 3-47
Power Modes ............................................................................................................. 3-47
Run Mode .............................................................................................................. 3-47
Wait Mode.............................................................................................................. 3-47
Doze Mode............................................................................................................. 3-47
State Retention Mode ............................................................................................ 3-48
Deep Sleep Mode................................................................................................... 3-49
Hibernate Mode ..................................................................................................... 3-50
Power Management Techniques Overview ............................................................... 3-51
DVFS Support............................................................................................................ 3-52
DVFS Load Tracking Block ................................................................................. 3-55
Load Tracking Buffer Register .......................................................................... 3-56
DPTC support ............................................................................................................ 3-56
Blocks Description................................................................................................. 3-57
FSM Block......................................................................................................... 3-57
Ref_clk_counter Block ...................................................................................... 3-63
Comp_logic Blocks ........................................................................................... 3-63
Ref_cir Blocks ................................................................................................... 3-64
Initialization Information................................................................................... 3-64
Synchronization Between DVFS and DPTC ............................................................. 3-64
Well-Bias Support...................................................................................................... 3-65
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Paragraph
Number
3.5.7.1
3.5.7.2
3.5.8
3.5.9
3.5.10
3.5.11
3.5.11.1
3.5.11.2
3.5.11.3
3.5.11.4
3.5.11.5
3.5.11.6
3.5.11.7
3.5.11.8
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.5.1
3.6.6
3.6.7
3.7
Page
Number
Title
ARM Platform Well-Bias Activating .................................................................... 3-65
ARM Platform Well-Bias Deactivating................................................................. 3-65
State Retention Voltage Support ................................................................................ 3-65
L2 Cache Power Gating Support ............................................................................... 3-65
ARM Platform Power Gating Support....................................................................... 3-65
DFT Support .............................................................................................................. 3-66
Overview................................................................................................................ 3-66
Deterministic Reset................................................................................................ 3-66
Clocks in Scan Divergence Mode.......................................................................... 3-66
Clocks in Long Chain Mode.................................................................................. 3-66
Clocks in SAF Scan Test Mode ............................................................................ 3-66
Clocks in Transition Mode .................................................................................... 3-67
Clocks in Transition Last Shift Mode.................................................................... 3-68
Clocks in Standalone Scan Mode .......................................................................... 3-69
Reset Controller ............................................................................................................. 3-70
Functional Description of the Reset Module ............................................................. 3-70
Reset Negation Sequence........................................................................................... 3-70
Global Reset............................................................................................................... 3-70
MCU Reset ................................................................................................................ 3-71
Watchdog Resets........................................................................................................ 3-71
The Reset Negation Sequence on a Watchdog Event ............................................ 3-71
S/W Peripheral Reset ................................................................................................. 3-72
JTAG S/W Reset ........................................................................................................ 3-72
Power On Reset (Boot) .................................................................................................. 3-72
Chapter 4
Signal Multiplexing
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.5.1
4.3.5.2
4.3.5.3
Overview.......................................................................................................................... 4-1
IOMUX Controller (IOMUXC)....................................................................................... 4-2
Software Multiplexor Control (SW_MUX_CTL) ....................................................... 4-3
Software Pad Control (SW_PAD_CTL)...................................................................... 4-4
Memory Map and Register Definition............................................................................. 4-4
Register Summary........................................................................................................ 4-4
General Purpose Register (GPR) ................................................................................. 4-5
Software Multiplexor Control Register (SW_MUX_CTL)....................................... 4-10
Register Descriptions for SW MUX Control (SW_MUX_CTL) .............................. 4-11
Functional Multiplexing Modes................................................................................. 4-39
Hardware Mode ..................................................................................................... 4-39
Functional Mode.................................................................................................... 4-39
Alternate Modes..................................................................................................... 4-40
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Paragraph
Number
4.3.5.4
4.3.6
4.3.7
4.3.8
4.3.8.1
4.3.8.2
4.4
4.4.1
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
Title
Page
Number
GPIO Mode............................................................................................................ 4-40
ATA Routing Options ................................................................................................ 4-40
Software Pad Control Register (SW_PAD_CTL)...................................................... 4-42
Register Descriptions for SW Pad Control (SW_PAD_CTL) ................................... 4-43
Software-Controllable Signals Register 0 (SCS0)................................................. 4-80
Software-Controllable Signals Registers 1–3 (SCS1–SCS3) ................................ 4-80
I/O Settings and Signal Multiplexing Scheme............................................................... 4-84
EMI Signal Multiplexing ........................................................................................... 4-84
Special I/O Signal Considerations ................................................................................. 4-88
Power Ready Input (GPIO1_5).................................................................................. 4-88
SJC_MOD.................................................................................................................. 4-89
CE_CONTROL ......................................................................................................... 4-89
TTM_PAD ................................................................................................................. 4-89
M_REQUEST and M_GRANT................................................................................. 4-89
External DMA Signals (EXTDMA) .......................................................................... 4-89
Tamper Detect Logic ................................................................................................. 4-89
Clock Source Select (CLKSS)................................................................................... 4-90
Chapter 5
General Purpose Input/Output (GPIO)
5.1
5.1.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.3.4
5.3.3.5
5.3.3.6
5.3.3.7
5.4
5.4.1
5.4.2
5.4.2.1
5.4.2.2
5.4.3
Overview.......................................................................................................................... 5-1
Features........................................................................................................................ 5-3
External Signal Description ............................................................................................. 5-3
Memory Map and Register Definition............................................................................. 5-3
Memory Map ............................................................................................................... 5-3
Register Summary........................................................................................................ 5-4
Register Descriptions................................................................................................... 5-6
GPIO Data Register (DR)........................................................................................ 5-6
GPIO Direction Register (GDIR) ............................................................................ 5-7
GPIO Pad Status Register (PSR) ............................................................................. 5-8
GPIO Interrupt Configuration Register1 (ICR1) ..................................................... 5-9
GPIO Interrupt Configuration Register2 (ICR2) ................................................... 5-10
GPIO Interrupt Mask Register (IMR).................................................................... 5-10
GPIO Interrupt Status Register (ISR) .................................................................... 5-11
Functional Description................................................................................................... 5-12
GPIO Function........................................................................................................... 5-12
GPIO Programming ................................................................................................... 5-12
Read Value from Pad ............................................................................................. 5-12
Write Value to Pad ................................................................................................. 5-13
Interrupt Control Unit ................................................................................................ 5-13
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Title
Chapter 6
Debugging the i.MX31 and i.MX31L
6.1
6.1.1
6.2
6.2.1
6.2.1.1
6.2.1.2
6.2.2
6.2.2.1
6.2.3
6.2.4
6.2.4.1
6.2.5
6.2.6
6.2.7
6.2.8
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.1.4
6.3.2
6.3.2.1
6.3.3
6.3.3.1
6.3.3.2
6.3.3.3
6.3.3.4
6.3.4
6.3.4.1
6.3.4.2
6.3.4.3
6.3.4.4
6.4
6.4.1
6.4.2
6.4.3
6.4.4
Overview.......................................................................................................................... 6-1
Features........................................................................................................................ 6-2
AP Debug Support ........................................................................................................... 6-3
ARM1136JF-S ............................................................................................................. 6-4
PMU, L1 Caches, MMU, and TLB Debug Support via CP15 Registers ................ 6-5
Performance Metrics Unit (PMU) ........................................................................... 6-5
Embedded Trace Macrocell (ETM11) ......................................................................... 6-7
ETM11 Trace Port ................................................................................................... 6-7
Embedded Trace Buffer (ETB11)................................................................................ 6-9
L2CC Debug Support .................................................................................................. 6-9
ARM11 L2CC Event Monitor (EVTMON) ............................................................ 6-9
Embedded Cross Trigger Interface (ECTCTI) .......................................................... 6-10
Debug Support Via Critical Signal Visibility ............................................................ 6-10
Interrupts.................................................................................................................... 6-10
General Purpose Timer (GPT) ................................................................................... 6-11
Embedded Cross Trigger (ECT) .................................................................................... 6-11
ECT Overview ........................................................................................................... 6-11
Cross Trigger Interface (CTI) ................................................................................ 6-14
Wrapper On CTI .................................................................................................... 6-15
Cross Trigger Matrix (CTM) ................................................................................. 6-15
Clock Considerations............................................................................................. 6-16
ECT Integration in the i.MX31 and i.MX31L ........................................................... 6-17
CTI SJC Connectivity............................................................................................ 6-18
Cross Trigger Input and Output Signals .................................................................... 6-19
ARM Cross Trigger Interface (CTI) Signal Assignments ..................................... 6-19
SDMA Cross Trigger Signals (ECT CTI ‘0’)........................................................ 6-20
MCU Cross Trigger Signals (ECT CTI ‘1’) .......................................................... 6-21
Loopback of IOMUX Observability Signals to ECT ............................................ 6-22
Examples Of Debug Use Cases Using ECT Scheme ................................................ 6-23
Debug Request/Debug Acknowledge.................................................................... 6-23
SDMA Debug ........................................................................................................ 6-23
IO Triggers............................................................................................................. 6-24
Reconfiguration of the ECT................................................................................... 6-24
System JTAG Controller (SJC)...................................................................................... 6-25
SJC Main Features ..................................................................................................... 6-26
SJC TAP Port ............................................................................................................. 6-27
Return-TCK (RTCK) Pin Support ............................................................................. 6-27
OnCE/ICE Accesses .................................................................................................. 6-27
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Paragraph
Number
6.4.5
6.4.6
6.4.7
6.4.8
Title
Page
Number
TAP Connectivity Scheme......................................................................................... 6-27
SDMA TAP Bypass Mechanism ............................................................................... 6-28
Out Of Reset Modes Of Operation ............................................................................ 6-28
Bottom Connector/CE Bus Support........................................................................... 6-29
Chapter 7
i.MX31 and i.MX31L Boot
7.1
7.1.1
7.2
7.2.1
7.3
7.4
7.4.1
7.4.1.1
7.4.1.2
7.5
7.6
Overview.......................................................................................................................... 7-1
Features........................................................................................................................ 7-1
System Boot-Up Flow in i.MX31.................................................................................... 7-2
Supported Boot Modes ................................................................................................ 7-2
Endian Boot Mode ........................................................................................................... 7-3
Special Boot Cases........................................................................................................... 7-4
Development Parts....................................................................................................... 7-4
Use of RAM Loader to Download Flash Image onto System Flash ....................... 7-4
iROM System Flash Bootup.................................................................................... 7-4
High Assurance Boot (HAB) ........................................................................................... 7-5
MMC/SD Card................................................................................................................. 7-5
Chapter 8
ARM11 Platform
8.1
8.1.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.4.1
8.2.4.2
8.2.4.3
8.2.4.4
8.2.5
8.3
8.4
8.5
8.5.1
8.5.2
8.5.3
Overview.......................................................................................................................... 8-2
Features........................................................................................................................ 8-3
ARM11 Interfaces............................................................................................................ 8-3
Debug/JTAG ................................................................................................................ 8-3
ETM ............................................................................................................................. 8-3
Vectored Interrupt Controller (VIC) ............................................................................ 8-4
Level Two Interface ..................................................................................................... 8-4
Instruction Fetch Interface....................................................................................... 8-4
Data Read Interface ................................................................................................. 8-4
Data Write Interface................................................................................................. 8-5
Peripheral Interface.................................................................................................. 8-5
ARM11 Symbol ........................................................................................................... 8-5
ARM11 Platform Block Diagram .................................................................................... 8-5
Overview of Platform Submodules.................................................................................. 8-6
Configuration of ARM1136JF-S in the ARM11 Platform .............................................. 8-7
VFP11—Vector Floating Point Coprocessor ............................................................... 8-7
ARM11 Instruction and Data Caches (L1) .................................................................. 8-8
L2 Interface (IF_AHB, DR_AHB, DW_AHB) ........................................................... 8-8
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Paragraph
Number
8.5.4
8.5.5
8.5.6
8.5.6.1
8.5.7
8.5.8
8.5.9
8.5.10
8.5.10.1
8.5.11
8.5.12
8.5.13
8.5.13.1
8.5.13.2
8.5.13.3
8.5.14
8.5.15
8.5.16
8.5.17
8.5.18
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
8.6.9
Page
Number
Title
Vectored Interrupt Controller Interface (VIC Interface).............................................. 8-8
JTAG Interface............................................................................................................. 8-8
Level Two Cache Controller (L2CC) .......................................................................... 8-8
L2CC Configuration on the ARM11 Platform ........................................................ 8-9
L2CC Performance ...................................................................................................... 8-9
Level Two AHB MUX (L2MUX) ............................................................................... 8-9
AHB Downsizer (AHBDIV2) ................................................................................... 8-10
Multi-Layer 6 X 5 AHB Crossbar Switch (MAX) .................................................... 8-10
Peripheral Bus Timeout Monitors.......................................................................... 8-10
ARM11 Vectored Interrupt Controller (AVIC).......................................................... 8-11
Clock Control Module (CLKCTL) ............................................................................ 8-11
CLKCTL Registers .................................................................................................... 8-12
GP_CTRL, GP_SER, and GP_CER Registers ...................................................... 8-12
GP_STAT Register................................................................................................. 8-13
L2_MEM_VAL Register ....................................................................................... 8-13
JTAG Synchronization Module (JSYNC) ................................................................. 8-13
ARM1136JF-S Embedded Trace Macrocell (ETM11).............................................. 8-14
Embedded Trace Buffer (ETB11).............................................................................. 8-15
Embedded Cross-Trigger (ECT)................................................................................ 8-15
ECT Implementation in the ARM11 Platform........................................................... 8-16
Security Summary.......................................................................................................... 8-18
ARM1136JF-S MMU ................................................................................................ 8-18
AIPS Access Control Registers ................................................................................. 8-18
AIPS Master Privilege Registers ............................................................................... 8-18
AIPS Peripheral Access Control Registers................................................................ 8-18
ipsa_cacheable, ipsb_cacheable................................................................................. 8-18
hmaster[3:0] Encodings ............................................................................................. 8-19
Secure JTAG .............................................................................................................. 8-19
disable_trace .............................................................................................................. 8-20
Security Controller Module (SCC) ............................................................................ 8-20
Chapter 9
ARM1136JF-S Vectored Interrupt Controller (AVIC)
9.1
9.1.1
9.1.2
9.2
9.2.1
9.2.2
9.2.3
Overview.......................................................................................................................... 9-1
Features........................................................................................................................ 9-1
Modes of Operation ..................................................................................................... 9-2
Memory Map and Register Definition............................................................................. 9-3
Memory Map ............................................................................................................... 9-3
Register Summary........................................................................................................ 9-5
Register Descriptions................................................................................................... 9-9
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Paragraph
Number
9.2.3.1
9.2.3.2
9.2.3.3
9.2.3.4
9.2.3.5
9.2.3.6
9.2.3.7
9.2.3.8
9.2.3.9
9.2.3.10
9.2.3.11
9.2.3.12
9.2.3.13
9.2.3.14
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.2
9.4.3
9.4.4
Title
Page
Number
Interrupt Control Register...................................................................................... 9-10
Normal Interrupt Mask Register............................................................................ 9-11
Interrupt Enable Number Register......................................................................... 9-12
Interrupt Disable Number Register........................................................................ 9-13
Interrupt Enable Registers ..................................................................................... 9-14
Interrupt Type Registers ........................................................................................ 9-15
Normal Interrupt Priority Level Registers ............................................................. 9-16
Normal Interrupt Vector and Status Register......................................................... 9-24
Fast Interrupt Vector and Status Register .............................................................. 9-25
Interrupt Source Registers ..................................................................................... 9-26
Interrupt Force Registers ....................................................................................... 9-27
Normal Interrupt Pending Register........................................................................ 9-28
Fast Interrupt Pending Register ............................................................................. 9-29
AVIC Vector Registers........................................................................................... 9-31
ARM1136JF-S Interrupt Controller Operation.............................................................. 9-31
ARM1136JF-S Prioritization of Exception Sources.................................................. 9-31
AVIC Prioritization of Interrupt Sources ................................................................... 9-32
Controlling Bus Arbitration With AVIC.................................................................... 9-32
The AVIC Interface To The ARM1136JF-S Core ..................................................... 9-32
AVIC Interface and Fast Interrupts ............................................................................ 9-32
Writing Reentrant Normal Interrupt Routines ........................................................... 9-33
Interrupt Usage .............................................................................................................. 9-33
Simple Steps to Enable Interrupts.............................................................................. 9-33
Normal or Fast Interrupt ........................................................................................ 9-34
Accelerated Normal Interrupt ................................................................................ 9-34
Enabling Interrupts, Code Examples ......................................................................... 9-34
Normal Interrupt Mechanism..................................................................................... 9-35
Vector Accelerated Normal Interrupt Mechanism ..................................................... 9-35
Chapter 10
Security Controller (SCC)
10.1
10.2
Overview........................................................................................................................ 10-2
External Signal Description ........................................................................................... 10-2
Chapter 11
Security Random Number Generator Accelerator (RNGA)
11.1
11.2
11.3
Overview........................................................................................................................ 11-1
Features .......................................................................................................................... 11-2
External Signal Description ........................................................................................... 11-2
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Title
Chapter 12
Run-Time Integrity Checker (RTIC)
12.1
12.1.1
12.2
12.2.1
Features .......................................................................................................................... 12-1
Modes of Operation ................................................................................................... 12-2
Initialization/Application Information ........................................................................... 12-2
System Application.................................................................................................... 12-2
Chapter 13
IC Identification (IIM)
13.1
13.1.1
Overview........................................................................................................................ 13-1
Features...................................................................................................................... 13-1
Chapter 14
L2 Cache Controller (L2CC)
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
14.3
14.3.1
14.3.1.1
14.3.1.2
14.3.2
14.3.3
Overview........................................................................................................................ 15-1
L2CC Feature Set....................................................................................................... 15-2
L2CC Configuration .................................................................................................. 15-3
AHB Slave Port ......................................................................................................... 15-5
AHB Master Port ....................................................................................................... 15-5
Write Buffer (WB) ..................................................................................................... 15-6
Write-Allocation Buffer............................................................................................. 15-7
Eviction Buffer (EB).................................................................................................. 15-7
Line Read Buffer (LRB) ............................................................................................ 15-7
Linefill Buffer (LFB) ................................................................................................. 15-7
The ARM11 Event Monitor....................................................................................... 15-7
Modes of Operation ....................................................................................................... 15-8
L2CC Clocking .......................................................................................................... 15-8
L2CC Idle .................................................................................................................. 15-8
L2CC Disabled ........................................................................................................ 15-11
L2CC Target Speed.................................................................................................. 15-11
L2CC Power Management....................................................................................... 15-11
L2CC Performance .................................................................................................. 15-12
L2CC Memories .......................................................................................................... 15-12
Latency Configuration ............................................................................................. 15-12
L2 TAG/VALID and DIRTY Memories .............................................................. 15-12
L2 DATA Memory and Clock Stretch Circuit ..................................................... 15-13
Mega Bit rval/wval Programmable Control Bits ..................................................... 15-13
L2CC Clock-Gating Logic....................................................................................... 15-13
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Paragraph
Number
14.4
14.4.1
14.4.1.1
14.4.1.2
14.4.1.3
14.4.1.4
14.4.1.5
14.4.1.5.1
14.4.1.5.2
14.4.1.5.3
14.4.1.5.4
14.4.1.6
14.4.1.6.1
14.4.1.6.2
14.4.1.6.3
14.4.1.7
14.4.1.8
14.4.1.8.1
14.4.1.9
14.4.1.10
14.4.2
14.4.2.1
14.5
14.5.1
14.5.1.1
Title
Page
Number
Configuration and Control Registers ........................................................................... 15-14
Register Descriptions............................................................................................... 15-17
Register 0: L2CC Cache ID Register................................................................... 15-17
Register 0: L2CC Cache Type Register............................................................... 15-18
Register 1: L2CC Control Register...................................................................... 15-19
Register 1: L2CC Auxiliary Control register....................................................... 15-20
Register 7: L2CC Cache Maintenance Operations.............................................. 15-23
Atomic Operations........................................................................................... 15-24
Background Operations ................................................................................... 15-24
Line Based Operations..................................................................................... 15-25
Way-Based Operations .................................................................................... 15-25
Register 9: L2CC Cache Lockdown .................................................................... 15-25
Uses of Lockdown Format C........................................................................... 15-26
Preventing or Reducing Cache Pollution......................................................... 15-26
Using Lockdown Format C for Processing Frame Buffers ............................. 15-26
L2CC Replacement Strategy ............................................................................... 15-27
Register 15: Test and Debug................................................................................ 15-27
Test registers .................................................................................................... 15-27
L2 Line Tag Register ........................................................................................... 15-28
L2CC Debug Control Register ............................................................................ 15-29
Forcing Write-Through Behavior ............................................................................ 15-30
L2CC Auxiliary Control Register 2 (L2CCAUXCR) ......................................... 15-30
L2 Initialization/Application Information ................................................................... 15-33
Configuring the ARM11P L2CC ............................................................................. 15-33
Invalidating the L2CC Cache Memory................................................................ 15-34
Chapter 15
ARM11 Event Monitor (EVTMON)
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.3.3.1
15.3.3.2
15.3.3.3
15.3.3.4
15.4
15.5
Overview........................................................................................................................ 16-1
Features .......................................................................................................................... 16-1
Memory Map and Register Definition........................................................................... 16-1
Memory Map ............................................................................................................. 16-2
Register Summary...................................................................................................... 16-2
Register Descriptions................................................................................................. 16-4
Monitor Control Register (EMMC)....................................................................... 16-4
Counter Status Register (EMCS)........................................................................... 16-5
Counter Configuration Registers (EMCCx) .......................................................... 16-6
Counter Registers (EMCx) .................................................................................... 16-8
EVTMON Interrupts...................................................................................................... 16-9
Clock Gating .................................................................................................................. 16-9
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Paragraph
Number
Page
Number
Title
Chapter 16
External Memory Interface (EMI)
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.4
16.5
16.5.1
16.5.2
16.6
16.7
16.7.1
16.8
16.8.1
16.8.2
16.9
Overview........................................................................................................................ 17-3
Features .......................................................................................................................... 17-3
PCMCIA Host Adaptor ................................................................................................. 17-4
Interrupt Generation................................................................................................... 17-4
Card Extraction.......................................................................................................... 17-5
TrueIDE Support........................................................................................................ 17-5
NAND Flash Controller................................................................................................. 17-6
Operation ....................................................................................................................... 17-7
Internal and External Communications ..................................................................... 17-7
Sharing of I/O Pins .................................................................................................... 17-8
The Enhanced SDRAM Controller (ESDCTL) ............................................................. 17-8
EMI AHB MUX .......................................................................................................... 17-10
Overview of EMI AHB MUX Operation ................................................................ 17-10
EMI I/O MUX ............................................................................................................. 17-12
Overview of EMI I/O MUX Operation ................................................................... 17-13
EMI Input/Output Signals........................................................................................ 17-27
Memory Map/Register Definition ............................................................................... 17-34
Chapter 17
Multi-Master Memory Interface (M3IF)
17.1
17.1.1
17.1.2
17.2
17.2.1
17.2.2
17.2.3
17.2.3.1
17.2.3.2
17.2.3.3
17.2.3.4
17.2.3.5
17.2.3.6
17.2.3.7
17.3
17.3.1
17.3.1.1
Overview........................................................................................................................ 18-3
M3IF Interfaces.......................................................................................................... 18-3
Features...................................................................................................................... 18-4
Memory Map and Register Definition........................................................................... 18-5
Memory Map ............................................................................................................. 18-5
Register Summary...................................................................................................... 18-6
Register Descriptions................................................................................................. 18-9
M3IF Control Register (M3IFCTL) ...................................................................... 18-9
M3IF Snooping Configuration Register 0 (M3IFSCFG0) .................................. 18-11
M3IF Snooping Configuration Register 1 (M3IFSCFG1) .................................. 18-13
M3IF Snooping Configuration Register 2 (M3IFSCFG2) .................................. 18-14
M3IF Snooping Status Register 0 (M3IFSSR0) .................................................. 18-14
M3IF Snooping Status Register 1 (M3IFSSR1) .................................................. 18-15
M3IF Master Lock WEIM CSx Register (M3IFMLWEx).................................. 18-16
Functional Description................................................................................................. 18-18
Snooping Logic........................................................................................................ 18-18
Snooping Overview ............................................................................................. 18-18
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Number
17.4
17.4.1
17.4.1.1
17.4.1.2
Title
Page
Number
Initialization/Application Information ......................................................................... 18-19
M3IF in a System..................................................................................................... 18-19
Snooping Window Settings ................................................................................. 18-19
Snooping Window Settings ................................................................................. 18-21
Chapter 18
Wireless External Interface Module (WEIM)
18.1
18.1.1
18.1.2
18.2
18.2.1
18.3
18.4
18.4.1
18.4.2
18.4.3
18.4.3.1
18.4.3.2
18.4.3.3
18.4.3.4
18.5
18.5.1
18.5.2
18.5.3
18.5.4
18.5.5
18.5.6
18.5.7
18.5.8
18.5.9
18.5.10
18.5.11
18.5.12
18.6
18.7
18.7.1
18.7.1.1
18.7.1.2
18.7.2
Overview........................................................................................................................ 19-2
Features...................................................................................................................... 19-3
Modes of Operation ................................................................................................... 19-3
External Signal Description ........................................................................................... 19-4
Overview.................................................................................................................... 19-4
Detailed Signal Descriptions ......................................................................................... 19-4
Memory Map and Register Definition........................................................................... 19-8
Memory Map ............................................................................................................. 19-8
Register Summary.................................................................................................... 19-10
Register Descriptions............................................................................................... 19-11
Chip Select x Upper Control Register (CSCRxU) .............................................. 19-13
Chip Select x Lower Control Register (CSCRxL) .............................................. 19-17
Chip Select x Additional Control Register (CSCRxA) ....................................... 19-21
WEIM Configuration Register (WCR)................................................................ 19-24
Functional Description................................................................................................. 19-25
Configurable Bus Sizing.......................................................................................... 19-25
WEIM Operational Modes....................................................................................... 19-25
Burst Mode Memory Operation............................................................................... 19-26
Burst Clock Divisor ................................................................................................. 19-27
Burst Clock Start...................................................................................................... 19-27
Page Mode Emulation.............................................................................................. 19-27
PSRAM Mode Operation......................................................................................... 19-28
Mixed AHB/Memory Burst Modes Support ........................................................... 19-28
AHB Bus Cycles Support ........................................................................................ 19-28
DTACK Mode.......................................................................................................... 19-30
Internal Input Data Capture ..................................................................................... 19-30
Error Conditions ...................................................................................................... 19-31
Initialization/Application Information ......................................................................... 19-31
External Bus Timing Diagrams.................................................................................... 19-31
Asynchronous Memory Accesses Timing Diagrams............................................... 19-32
AHB Halfword Access to Halfword Width Memory .......................................... 19-32
AHB Word Access to Halfword Width Memory................................................. 19-39
Page Mode Timing Diagrams .................................................................................. 19-51
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Paragraph
Number
18.7.2.1
18.7.3
18.7.3.1
18.7.4
18.7.4.1
18.7.4.2
18.7.5
18.7.5.1
18.7.5.2
18.7.6
18.7.6.1
18.7.6.2
Page
Number
Title
AHB Word Accesses to Halfword Width Memory ............................................. 19-51
DTACK Mode Memory Accesses Timing Diagrams .............................................. 19-52
AHB Word Accesses to Word-Width Memory.................................................... 19-52
Burst Memory Accesses Timing Diagrams ............................................................. 19-55
AHB Word Accesses to Halfword Width Memory ............................................. 19-55
AHB Accesses to Word-Width Burst Memory.................................................... 19-58
Synchronous Accesses Timing Diagrams with PSRAM ......................................... 19-66
AHB Sequential Accesses to Halfword Width PSRAM Memory....................... 19-66
AHB Sequential Accesses to Word-width PSRAM Memory.............................. 19-68
Muxed A/D Mode.................................................................................................... 19-69
Asynchronous Word Accesses to Word-Width Memory ..................................... 19-69
Synchronous Accesses with Word-width Memory.............................................. 19-71
Chapter 19
Enhanced SDRAM Controller (ESDCTL)
19.1
19.1.1
19.1.2
19.1.3
19.1.4
19.1.5
19.1.6
19.1.7
19.1.8
19.1.8.1
19.1.9
19.1.10
19.2
19.2.1
19.3
19.3.1
19.3.2
19.3.3
19.3.3.1
19.3.3.2
19.3.3.3
19.3.3.4
19.3.3.5
19.3.3.6
19.3.3.7
Overview........................................................................................................................ 20-3
SDRAM Command Controller .................................................................................. 20-3
Bank Model................................................................................................................ 20-3
Decoder and Address MUX....................................................................................... 20-3
ESDCTL Control and Configuration Registers ......................................................... 20-3
Refresh Sequencer ..................................................................................................... 20-3
Command Sequencer ................................................................................................. 20-3
Size Logic .................................................................................................................. 20-4
Mobile/Low Power DDR (LPDDR) Interface........................................................... 20-4
Power Down Timer................................................................................................ 20-4
Features...................................................................................................................... 20-4
Modes of Operation ................................................................................................... 20-6
External Signal Description ........................................................................................... 20-7
Detailed Signal Descriptions ..................................................................................... 20-8
Memory Map and Register Definition......................................................................... 20-10
Memory Map ........................................................................................................... 20-10
Register Summary.................................................................................................... 20-11
Register Descriptions............................................................................................... 20-14
ESDCTL0 and ESDCTL1 Control Registers ...................................................... 20-15
ESDCTL Configuration Registers (ESDCFG0/ESDCFG1) ............................... 20-20
ESDMISC Miscellaneous Register (ESDMISC)................................................. 20-33
MDDR Delay Line 1 Configuration Debug Register .......................................... 20-35
MDDR Delay Line 2 Configuration Debug Register .......................................... 20-36
MDDR Delay Line 3 Configuration Debug Register .......................................... 20-37
MDDR Delay Line 4 Configuration Debug Register .......................................... 20-38
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Paragraph
Number
19.3.3.8
19.3.3.9
19.4
19.4.1
19.4.1.1
19.4.1.2
19.4.1.3
19.4.2
19.4.2.1
19.4.2.2
19.4.3
19.4.4
19.4.5
19.4.5.1
19.4.5.2
19.4.5.3
19.4.5.3.1
19.4.5.4
19.4.5.4.1
19.4.5.5
19.4.5.6
19.4.6
19.4.6.1
19.4.7
19.4.7.1
19.4.7.1.1
19.4.7.1.2
19.4.7.1.3
19.4.7.2
19.4.7.2.1
19.4.7.3
19.4.8
19.4.9
19.4.10
19.4.11
19.5
19.5.1
19.5.2
19.5.3
19.5.4
19.5.4.1
Title
Page
Number
MDDR Delay Line 5 Configuration Debug Register .......................................... 20-39
MDDR Delay Line Cycle Length Debug Register.............................................. 20-40
Functional Description................................................................................................. 20-41
Enhanced SDRAM Controller Optimization Strategy............................................. 20-42
MIF1—No Optimization/Sequential Accesses.................................................... 20-45
MIF2—Medium Level Optimization/Command Anticipation............................ 20-45
Latency Hiding .................................................................................................... 20-45
Address Multiplexing .............................................................................................. 20-48
Multiplexed Address Bus .................................................................................... 20-48
Bank Addresses ................................................................................................... 20-50
Multiplexed Address Bus—During “Special” Mode (SMODE 1 or 3)................... 20-51
Refresh ..................................................................................................................... 20-51
Low Power Operating Modes .................................................................................. 20-53
Self Refresh Mode for SDRAM/LPDDR Devices .............................................. 20-54
Manual Self Refresh Mode for SDRAM/LPDDR Devices ................................. 20-56
Precharge Power Down Mode ............................................................................. 20-58
SDRAM Precharge Power Down Mode.......................................................... 20-58
Active Power Down Mode .................................................................................. 20-63
SDRAM/LPDDR Active Power Down Mode................................................. 20-63
Precharge bank(s)—Low Power Mode................................................................ 20-66
LPDDR Frequency Change ................................................................................. 20-66
SDRAM (SDR and LPDDR) Command Encoding................................................. 20-66
Reset .................................................................................................................... 20-67
Normal READ/WRITE Mode ................................................................................. 20-68
SDR Cycle Accurate Enhanced SDRAM Controller Accesses........................... 20-91
Single Read Word Access to 16-Bit Memory.................................................. 20-91
Misaligned INCR4 Burst Read Access to 16-Bit Memory ............................. 20-92
Misaligned WRAP8 Burst Read Access to 32-Bit Memory ........................... 20-94
Single Write Word Access to 32-Bit Memory ..................................................... 20-96
INCR4 Burst Write Word Access to 32-Bit Memory...................................... 20-96
SDRAM Command Sequence for Burst Accesses .............................................. 20-97
Precharge Command Mode ..................................................................................... 20-98
Auto-Refresh Mode ............................................................................................... 20-100
Manual Self Refresh Mode .................................................................................... 20-101
Set Mode Register Mode ....................................................................................... 20-101
Initialization/Application Information ....................................................................... 20-103
Memory Device Selection ..................................................................................... 20-104
Configuring Controller for SDRAM Memory Array ............................................ 20-104
CAS Latency.......................................................................................................... 20-104
SDRAM/LPDDR Initialization Sequence ............................................................. 20-104
SDRAM Initialization........................................................................................ 20-105
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
19.5.4.1.1
19.5.4.1.2
19.5.4.2
19.5.4.3
19.5.4.3.1
19.5.4.3.2
19.5.4.3.3
19.5.4.3.4
19.5.4.3.5
19.5.4.3.6
19.5.4.3.7
19.5.4.3.8
19.5.4.3.9
19.5.4.3.10
19.5.4.3.11
19.5.4.3.12
19.5.4.3.13
19.5.4.3.14
19.5.4.3.15
19.5.4.3.16
Page
Number
Title
SDR SDRAM Initialization........................................................................... 20-105
LPDDR SDRAM Initialization ..................................................................... 20-107
SDR SDRAM Load Mode Register .................................................................. 20-108
SDRAM Memory Configuration Examples ...................................................... 20-110
Single 64 Mbit (4Mx16) SDRAM Configuration ......................................... 20-110
Single 128 Mbit (8Mx16) SDRAM Configuration ........................................20-111
Single 256 Mbit (16Mx16) SDRAM Configuration ..................................... 20-112
Single 512 Mbit (32Mx16) SDRAM Configuration ..................................... 20-113
Single 1-Gbit (64Mx16) SDRAM Configuration.......................................... 20-114
Dual 64 Mbit (4Mx16) SDRAM Configuration............................................ 20-115
Dual 128 Mbit (8Mx16) SDRAM Configuration.......................................... 20-116
Dual 256 Mbit (16Mx16) SDRAM Configuration........................................ 20-117
Single 64-Mbit (2Mx32) SDRAM Configuration ......................................... 20-118
Single 128-Mbit (4Mx32) SDRAM Configuration ....................................... 20-119
Single 256-Mbit (8Mx32) SDRAM Configuration ....................................... 20-120
Single 512-Mbit (16Mx32) SDRAM Configuration ..................................... 20-121
Single 1-Gbit (32Mx32) SDRAM Configuration.......................................... 20-122
Single 2-Gbit (64Mx32) SDRAM Configuration.......................................... 20-123
Single 512-Mbit (16Mx32) Mobile DDR SDRAM Configuration ............... 20-124
Single 512-Mbit (32Mx16) Mobile DDR SDRAM Configuration ............... 20-125
Chapter 20
NAND Flash Controller (NANDFC)
20.1
20.2
20.3
20.4
20.4.1
20.4.2
20.5
20.5.1
20.6
20.6.1
20.6.2
20.7
20.7.1
20.7.1.1
20.7.2
20.7.3
20.7.4
Overview........................................................................................................................ 21-2
Operation ....................................................................................................................... 21-2
Features .......................................................................................................................... 21-3
External Signal Description ........................................................................................... 21-4
Overview.................................................................................................................... 21-4
Detailed Signal Descriptions ..................................................................................... 21-4
NANDFC Buffer Memory Space .................................................................................. 21-6
Main and Spare Area Buffers .................................................................................... 21-7
Memory Map and Register Definition........................................................................... 21-9
Memory Map ............................................................................................................. 21-9
Register Summary.................................................................................................... 21-10
Register Descriptions ................................................................................................... 21-12
Internal SRAM SIZE (NFC_BUFSIZE).................................................................. 21-12
Buffer Number for Page Data Transfer (RAM_BUFFER_ADDRESS) ............. 21-12
NAND Flash Address (NAND_FLASH_ADD)...................................................... 21-13
NAND Flash Command (NAND_FLASH_CMD).................................................. 21-13
NANDFC Internal Buffer Lock Control (NFC_CONFIGURATION).................... 21-14
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
20.7.5
20.7.6
20.7.7
20.7.8
20.7.8.1
20.7.9
20.7.10
20.7.11
20.7.12
20.7.13
20.7.14
20.8
20.8.1
20.8.2
20.8.3
20.8.4
20.8.5
20.8.6
20.8.7
20.8.8
20.8.9
20.8.10
20.8.11
20.8.11.1
20.8.11.2
20.8.12
20.9
20.9.1
20.9.1.1
20.9.1.1.1
20.9.1.1.2
20.9.1.1.3
20.9.1.1.4
20.9.1.1.5
20.9.1.2
Title
Page
Number
Controller Status and Result of Flash Operation (ECC_STATUS_RESULT)......... 21-14
ECC Error Position of Main Area Data Error x8
(ECC_RSLT_MAIN_AREA) .............................................................................. 21-15
ECC Error Position of Main Area Data Error x16
(ECC_RSLT_MAIN_AREA) .............................................................................. 21-16
ECC Error Position of Spare Area Data Error x8
(ECC_RSLT_SPARE_AREA) ............................................................................ 21-16
ECC Error Position of Spare Area Data Error x16
(ECC_RSLT_SPARE_AREA) ........................................................................ 21-17
NAND Flash Write Protection (NF_WR_PROT) ................................................... 21-18
Address to Unlock in Write Protection Mode—
Start (UNLOCK_START_BLK_ADD)............................................................... 21-18
Address to Unlock in Write Protection Mode—
End (UNLOCK_END_BLK_ADD).................................................................... 21-19
NAND Flash Write Protection Status (NAND_FLASH_WR_PR_ST) .................. 21-19
NAND Flash Operation Configuration (NAND_FLASH_CONFIG1) ................... 21-20
NAND Flash Operation Configuration 2 (NAND_FLASH_CONFIG2) ................ 21-21
Functional Description................................................................................................. 21-22
Modes of Operation ................................................................................................. 21-22
Booting From a NAND Flash Device...................................................................... 21-23
NAND Flash Control ............................................................................................... 21-24
ECC Control ............................................................................................................ 21-27
Address Control ....................................................................................................... 21-27
RAM Buffer (SRAM) .............................................................................................. 21-27
Registers (Command, Address, Status, and Others.) ............................................... 21-27
Read and Write Control ........................................................................................... 21-28
Data Output Control................................................................................................. 21-28
Host Control............................................................................................................. 21-28
AHB Bus Interface................................................................................................... 21-28
Big/Little Endian ................................................................................................. 21-28
Burst Access Support........................................................................................... 21-28
I/O Pins Sharing....................................................................................................... 21-29
Initialization/Application Information ......................................................................... 21-29
Normal Operation .................................................................................................... 21-30
Fundamental Building Block Operations ............................................................ 21-30
Preset Operation .............................................................................................. 21-30
NAND Flash Command Input Operation........................................................ 21-30
NAND Flash Address Input Operation ........................................................... 21-31
NAND Flash Data Input Operation ................................................................. 21-32
NAND Flash Data Output Operation .............................................................. 21-33
Read NAND Flash ID Operation......................................................................... 21-34
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Paragraph
Number
20.9.1.2.1
20.9.1.3
20.9.1.3.1
20.9.1.4
20.9.1.5
20.9.1.6
20.9.1.7
20.9.2
20.9.2.1
20.9.2.2
20.9.2.3
20.9.3
20.9.3.1
20.9.3.2
20.9.3.3
20.9.3.4
20.9.3.4.1
20.9.3.4.2
20.9.3.4.3
20.9.4
Page
Number
Title
NAND Flash ID Data Formats ........................................................................ 21-35
NAND Flash Status Read Operation ................................................................... 21-37
NAND Flash Status Data Format .................................................................... 21-37
Read NAND Flash Data Operation ..................................................................... 21-38
Program NAND Flash Data Operation................................................................ 21-39
Erase NAND Flash Data Operation..................................................................... 21-40
HOT Reset (Controller and NAND Flash Reset) ................................................ 21-41
ECC Operation......................................................................................................... 21-42
ECC Normal Operation ....................................................................................... 21-42
ECC Bypass Operation ........................................................................................ 21-42
How to Operate the ECC ..................................................................................... 21-43
Write Protection Operation ...................................................................................... 21-43
Write Protection for RAM Buffer (LSB 1 Kbyte) ............................................... 21-43
Write Protection Modes ....................................................................................... 21-44
Write Protection Commands................................................................................ 21-44
Write Protection Status ........................................................................................ 21-45
Lock Sequence................................................................................................. 21-46
Unlock Sequence ............................................................................................. 21-46
Lock-Tight Sequence....................................................................................... 21-46
Memory Configuration Examples ........................................................................... 21-46
Chapter 21
Personal Computer Memory Card International Association (PCMCIA) Controller
21.1
21.2
21.3
21.3.1
21.4
21.4.1
21.4.1.1
21.4.1.2
21.4.1.3
21.4.1.4
21.4.1.5
21.4.1.6
21.4.1.7
21.4.1.8
21.5
21.5.1
21.5.2
Overview........................................................................................................................ 22-1
Features .......................................................................................................................... 22-3
External Signal Description ........................................................................................... 22-3
Detailed Signal Descriptions ..................................................................................... 22-3
Memory Map and Register Definition........................................................................... 22-6
Register Summary...................................................................................................... 22-7
PCMCIA Input Pins Register (PIPR) .................................................................... 22-9
PCMCIA Status Change Register (PSCR) .......................................................... 22-11
PCMCIA Enable Register (PER)......................................................................... 22-12
PCMCIA Base Registers 0–4 (PBR0–PBR4)...................................................... 22-14
PCMCIA Option Registers 0–4 (POR0–POR4).................................................. 22-15
PCMCIA Offset Registers 0–4 (POFR0–POFR4) .............................................. 22-19
PCMCIA General Control Register (PGCR)....................................................... 22-20
PCMCIA General Status Register (PGSR).......................................................... 22-21
Functional Description................................................................................................. 22-22
Modes of Operation ................................................................................................. 22-22
Windowing Capabilities........................................................................................... 22-22
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Contents
Paragraph
Number
21.5.2.1
21.5.3
21.5.4
21.5.4.1
21.5.5
21.5.6
21.5.7
21.5.8
21.5.9
21.5.10
21.5.11
21.5.12
21.5.13
21.6
Title
Page
Number
Window Overlapping........................................................................................... 22-22
WAIT Signal ............................................................................................................ 22-22
Interrupts.................................................................................................................. 22-22
Error Interrupt Conditions ................................................................................... 22-23
Power Control .......................................................................................................... 22-24
Reset and Three-Score Control................................................................................ 22-24
Write Protect ............................................................................................................ 22-24
16-Bit/8-Bit Support ................................................................................................ 22-25
Data and Control Signals Relations ......................................................................... 22-25
True IDE Mode Access............................................................................................ 22-26
Card Extraction ........................................................................................................ 22-26
TrueIDE Support...................................................................................................... 22-27
Endianness Support.................................................................................................. 22-28
Timing Diagrams ......................................................................................................... 22-28
Chapter 22
1-Wire Interface (1-Wire)
22.1
22.2
22.3
22.4
22.4.1
22.4.2
22.4.3
22.4.3.1
22.4.3.2
22.4.3.3
22.5
22.5.1
22.5.2
22.5.3
22.5.4
22.5.5
Overview........................................................................................................................ 23-1
Features .......................................................................................................................... 23-1
External Signal Descriptions ......................................................................................... 23-2
Memory Map and Register Definition........................................................................... 23-2
Memory Map ............................................................................................................. 23-2
Register Summary...................................................................................................... 23-2
Register Descriptions................................................................................................. 23-4
Control Register (CONTROL) .............................................................................. 23-4
Time Divider Register (TIME_DIVIDER)............................................................ 23-5
Reset Register (RESET) ........................................................................................ 23-7
Functional Description................................................................................................... 23-7
Low Power Modes ..................................................................................................... 23-7
Reset Sequence with Reset Pulse Presence Pulse...................................................... 23-8
Write 0 ....................................................................................................................... 23-8
Write 1/Read Data...................................................................................................... 23-9
1-Wire Clock Path...................................................................................................... 23-9
Chapter 23
Advanced Technology Attachment (ATA)
23.1
23.1.1
23.1.2
Overview........................................................................................................................ 24-1
Features...................................................................................................................... 24-3
Modes of Operation ................................................................................................... 24-3
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Paragraph
Number
23.2
23.2.1
23.2.1.1
23.2.1.2
23.2.1.3
23.2.1.4
23.2.1.5
23.2.1.6
23.2.1.7
23.2.1.8
23.2.1.9
23.2.1.10
23.2.2
23.2.2.1
23.2.2.2
23.2.2.3
23.2.2.4
23.2.2.5
23.3
23.3.1
23.3.2
23.3.3
23.3.3.1
23.3.3.2
23.3.3.2.1
23.3.3.2.2
23.3.3.2.3
23.3.3.2.4
23.3.3.2.5
23.3.3.2.6
23.3.3.2.7
23.3.3.2.8
23.3.3.2.9
23.3.3.2.10
23.3.3.2.11
23.3.3.2.12
23.3.3.2.13
23.3.3.2.14
23.3.3.2.15
23.3.3.2.16
23.3.3.2.17
Page
Number
Title
External Signal Description ........................................................................................... 24-4
Detailed Signal Descriptions ..................................................................................... 24-4
ata_reset (out) ........................................................................................................ 24-4
ata_dior (out) ......................................................................................................... 24-5
ata_diow (out)........................................................................................................ 24-5
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0 (out) ................................................. 24-5
ata_dmarq (in)........................................................................................................ 24-5
ata_dmack (out) ..................................................................................................... 24-5
ata_intrq (in) .......................................................................................................... 24-5
ata_iordy (in) ......................................................................................................... 24-5
ata_data[15:0] (in/out-tristate) ............................................................................... 24-5
ata_buffer_en ......................................................................................................... 24-5
Timing on ATA Bus ................................................................................................... 24-6
Timing Parameters ................................................................................................. 24-6
PIO Mode Timing .................................................................................................. 24-7
Timing in Multiword DMA Mode......................................................................... 24-8
UDMA In Timing Diagrams................................................................................ 24-10
UDMA Out Timing Diagrams ............................................................................. 24-12
Memory Map and Register Definition......................................................................... 24-14
Memory Map ........................................................................................................... 24-14
Register Summary.................................................................................................... 24-16
Register Descriptions............................................................................................... 24-19
Endianness in ATA............................................................................................... 24-19
Timing Registers.................................................................................................. 24-20
TIME_OFF Register........................................................................................ 24-20
TIME_ON Register ......................................................................................... 24-20
TIME_1 Register ............................................................................................. 24-21
TIME_2W Register ......................................................................................... 24-21
TIME_2R Register .......................................................................................... 24-21
TIME_AX Register ......................................................................................... 24-21
TIME_PIO_RDX Register .............................................................................. 24-22
TIME_4 Register ............................................................................................. 24-22
TIME_9 Register ............................................................................................. 24-22
TIME_M Register............................................................................................ 24-22
TIME_JN Register........................................................................................... 24-23
TIME_D Register ............................................................................................ 24-23
TIME_K Register ............................................................................................ 24-23
TIME_ACK Register....................................................................................... 24-23
TIME_ENV Register ....................................................................................... 24-24
TIME_RPX Register ....................................................................................... 24-24
TIME_ZAH Register ....................................................................................... 24-24
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Paragraph
Number
23.3.3.2.18
23.3.3.2.19
23.3.3.2.20
23.3.3.2.21
23.3.3.2.22
23.3.3.2.23
23.3.3.2.24
23.3.3.3
23.3.3.3.1
23.3.3.3.2
23.3.3.3.3
23.3.3.4
23.3.3.5
23.3.3.5.1
23.3.3.5.2
23.3.3.5.3
23.3.3.6
23.3.3.7
23.4
23.4.1
23.4.2
23.4.3
23.4.4
23.4.5
Title
Page
Number
TIME_MLIX Register ..................................................................................... 24-24
TIME_DVH Register ...................................................................................... 24-25
TIME_DZFS Register ..................................................................................... 24-25
TIME_DVS Register ....................................................................................... 24-25
Time_CVH Register ........................................................................................ 24-25
TIME_SS Register........................................................................................... 24-26
TIME_CYC Register ....................................................................................... 24-26
FIFO Data Registers ............................................................................................ 24-26
FIFO_DATA Register in 16-Bit Mode ............................................................ 24-26
FIFO_DATA Register in 32-Bit Mode ............................................................ 24-27
FIFO_FILL Register........................................................................................ 24-27
ATA_CONTROL Register................................................................................... 24-27
Interrupt Registers ............................................................................................... 24-28
INTERRUPT_PENDING Register.................................................................. 24-29
INTERRUPT_ENABLE Register ................................................................... 24-30
INTERRUPT_CLEAR Register ...................................................................... 24-31
FIFO_ALARM Register...................................................................................... 24-31
Drive Registers Connected to ATA Bus .............................................................. 24-32
Functional Description................................................................................................. 24-33
Resetting ATA Bus................................................................................................... 24-33
Programming ATA Bus Timing and iordy_en ......................................................... 24-33
Access to ATA Bus in PIO Mode ............................................................................ 24-33
Using DMA Mode to Receive Data from ATA Bus ................................................ 24-34
Using DMA Mode to Transmit Data to ATA Bus ................................................... 24-35
Chapter 24
Configurable Serial Peripheral Interface (CSPI)
24.1
24.1.1
24.2
24.3
24.3.1
24.3.2
24.3.3
24.3.3.1
24.3.3.2
24.3.3.3
24.3.3.4
24.3.3.5
24.3.3.6
Features .......................................................................................................................... 25-1
Modes of Operation ................................................................................................... 25-2
External Signal Description ........................................................................................... 25-2
Memory Map and Register Definition........................................................................... 25-2
Memory Map ............................................................................................................. 25-2
Register Summary...................................................................................................... 25-3
Register Descriptions................................................................................................. 25-5
Receive Data Register (RXDATA) ........................................................................ 25-5
Transmit Data Register (TXDATA)....................................................................... 25-6
Control Register (CONREG)................................................................................. 25-7
Interrupt Control Register (INTREG) ................................................................. 25-10
DMA Control Register (DMAREG) ................................................................... 25-12
Status Register (STATREG) ................................................................................ 25-13
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
24.3.3.7
24.3.3.8
24.4
24.4.1
24.4.2
24.4.2.1
24.4.2.2
24.4.2.3
24.4.2.4
24.4.3
24.4.4
24.4.5
24.5
24.6
24.7
24.8
Page
Number
Title
Sample Period Control Register (PERIODREG) ................................................ 25-14
Test Control Register (TESTREG) ...................................................................... 25-15
Functional Description................................................................................................. 25-17
Phase and Polarity Configurations........................................................................... 25-17
Master Mode ............................................................................................................ 25-18
Master Mode with SPI_RDY............................................................................... 25-18
Master Mode with Wait States............................................................................. 25-19
Master Mode with SSCTL Control...................................................................... 25-20
Master Mode with PHA Control.......................................................................... 25-21
Slave Mode .............................................................................................................. 25-22
Interrupt Control ...................................................................................................... 25-23
DMA Control........................................................................................................... 25-24
Initialization/Application Information ......................................................................... 25-25
CSPI Signal Multiplexing............................................................................................ 25-26
CSPI Pin Configuration ............................................................................................... 25-27
Recommended Signal Pad Configuration.................................................................... 25-28
Chapter 25
Fast Infrared Interface (FIR)
25.1
25.1.1
25.1.1.1
25.1.1.2
25.1.1.3
25.1.1.4
25.1.1.5
25.1.1.6
25.1.2
25.1.3
25.2
25.2.1
25.2.1.1
25.2.1.2
25.3
25.3.1
25.3.2
25.3.3
25.3.3.1
25.3.3.2
25.3.3.3
Overview........................................................................................................................ 26-1
Overview of IrDA Medium Infrared and Fast Infrared Standards ............................ 26-3
MIR Packet Structure............................................................................................. 26-3
FIR Packet Structure.............................................................................................. 26-4
MIR CRC............................................................................................................... 26-4
FIR CRC ................................................................................................................ 26-5
MIR Modulation .................................................................................................... 26-5
FIR Modulation ..................................................................................................... 26-5
Features...................................................................................................................... 26-6
Modes of Operation ................................................................................................... 26-6
External Signal Description ........................................................................................... 26-6
Detailed Signal Descriptions ..................................................................................... 26-7
IPP_DO_FIRI_TXD .............................................................................................. 26-7
IPP_IND_FIRI_RXD ............................................................................................ 26-7
Memory Map and Register Definition........................................................................... 26-7
FIR Memory Map ...................................................................................................... 26-7
Register Summary...................................................................................................... 26-8
Register Descriptions................................................................................................. 26-9
FIR Transmitter Control Register (FIRITCR) ....................................................... 26-9
FIR Transmitter Count Register (FIRITCTR) ..................................................... 26-11
FIR Receiver Control Register (FIRIRCR) ......................................................... 26-12
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Paragraph
Number
25.3.3.4
25.3.3.5
25.3.3.6
25.4
25.4.1
25.4.1.1
25.4.1.2
25.4.1.3
25.4.1.4
25.4.2
25.4.3
25.4.3.1
25.4.3.2
25.4.3.3
25.4.4
25.5
25.5.1
25.5.2
25.5.2.1
25.5.2.2
Title
Page
Number
FIR Transmit Status Register (FIRITSR) ............................................................ 26-14
FIR Receive Status Register (FIRIRSR) ............................................................. 26-15
FIR Control Register (FIRICR) ........................................................................... 26-16
Functional Description................................................................................................. 26-17
Transmitter Overview .............................................................................................. 26-17
MIR Mode ........................................................................................................... 26-18
FIR Mode............................................................................................................. 26-18
Serial Infrared Interaction Pulse .......................................................................... 26-18
Software Packet Assembly Mode........................................................................ 26-18
Transmitter FIFO ..................................................................................................... 26-18
Receiver Overview .................................................................................................. 26-19
MIR Mode ........................................................................................................... 26-19
FIR Mode............................................................................................................. 26-19
Software Packet Disassembly Mode ................................................................... 26-20
Receiver FIFO.......................................................................................................... 26-20
Initialization/Application Information ......................................................................... 26-20
FIRI Clock Path ....................................................................................................... 26-20
Examples of FIR Programming ............................................................................... 26-20
Transmitter Programming Scenario..................................................................... 26-20
Receiver Programming Scenario ......................................................................... 26-21
Chapter 26
Inter-Integrated Circuit (I2C)
26.1
26.1.1
26.2
26.2.1
26.3
26.3.1
26.3.2
26.3.3
26.3.3.1
26.3.3.2
26.3.3.3
26.3.3.4
26.3.3.5
26.4
26.4.1
26.4.2
26.4.2.1
Overview........................................................................................................................ 27-2
Features...................................................................................................................... 27-2
External Signal Description ........................................................................................... 27-3
Detailed External Signal Descriptions....................................................................... 27-3
Memory Map and Register Definition........................................................................... 27-4
I2C Memory Map....................................................................................................... 27-4
Register Summary...................................................................................................... 27-4
Register Descriptions................................................................................................. 27-6
I2C Address Register (IADR)................................................................................ 27-6
I2C Frequency Register (IFDR)............................................................................. 27-7
I2C Control Register (I2CR).................................................................................. 27-8
I2C Status Register (I2SR)................................................................................... 27-10
I2C Data Register (I2DR) .................................................................................... 27-11
Functional Description................................................................................................. 27-12
I2C System Configuration........................................................................................ 27-12
I2C Protocol ............................................................................................................. 27-12
START Signal ...................................................................................................... 27-13
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
26.4.2.2
26.4.2.3
26.4.2.4
26.4.2.5
26.4.3
26.4.4
26.4.5
26.4.6
26.4.7
26.4.8
26.5
26.5.1
26.5.2
26.5.3
26.5.4
26.5.5
26.5.6
26.5.7
26.5.8
Page
Number
Title
Slave Address Transmission................................................................................ 27-13
Data Transfer ....................................................................................................... 27-13
STOP Signal ........................................................................................................ 27-13
Repeat Start.......................................................................................................... 27-13
Arbitration Procedure .............................................................................................. 27-14
Clock Synchronization............................................................................................. 27-14
Handshaking ............................................................................................................ 27-15
Clock Stretching ...................................................................................................... 27-15
IP Bus Accesses ....................................................................................................... 27-15
Generation of Transfer Error on IP Bus................................................................... 27-15
Initialization/Application Information ......................................................................... 27-15
Initialization Sequence............................................................................................. 27-15
Generation of START .............................................................................................. 27-16
Post-Transfer Software Response ............................................................................ 27-16
Generation of STOP................................................................................................. 27-16
Generation of Repeated START .............................................................................. 27-17
Slave Mode .............................................................................................................. 27-17
Arbitration Lost........................................................................................................ 27-17
Timing Section......................................................................................................... 27-19
Chapter 27
Keypad Port (KPP)
27.1
27.1.1
27.1.2
27.2
27.2.1
27.2.1.1
27.2.1.2
27.3
27.3.1
27.3.2
27.3.3
27.3.3.1
27.3.3.2
27.3.3.3
27.3.3.4
27.4
27.4.1
27.4.2
Overview........................................................................................................................ 28-1
Features...................................................................................................................... 28-2
Modes of Operation ................................................................................................... 28-2
External Signal Description ........................................................................................... 28-2
Overview.................................................................................................................... 28-2
Input Pins ............................................................................................................... 28-2
Output Pins ............................................................................................................ 28-2
Memory Map and Register Definition........................................................................... 28-3
KPP Memory Map ..................................................................................................... 28-3
Register Summary...................................................................................................... 28-3
Register Descriptions................................................................................................. 28-4
Keypad Control Register (KPCR) ......................................................................... 28-5
Keypad Status Register (KPSR) ............................................................................ 28-5
Keypad Data Direction Register (KDDR) ............................................................. 28-7
Keypad Data Register (KPDR).............................................................................. 28-8
Functional Description................................................................................................... 28-9
Keypad Matrix Construction ..................................................................................... 28-9
Keypad Port Configuration........................................................................................ 28-9
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Contents
Paragraph
Number
27.4.3
27.4.4
27.4.5
27.4.6
27.4.6.1
27.4.7
27.5
27.5.1
27.5.2
27.5.3
Title
Page
Number
Keypad Matrix Scanning ........................................................................................... 28-9
Keypad Standby........................................................................................................ 28-9
Glitch Suppression on Keypad Inputs ..................................................................... 28-10
Multiple Key Closures ............................................................................................. 28-11
Ghost Key Problem and Correction..................................................................... 28-13
3-Point Contact Keys Support ................................................................................. 28-14
Initialization/Application Information ......................................................................... 28-15
Typical Keypad Configuration and Scanning Sequence.......................................... 28-15
Key Press Interrupt Scanning Sequence .................................................................. 28-15
Additional Comments .............................................................................................. 28-16
Chapter 28
Memory Stick Host Controller (MSHC)
28.1
28.1.1
28.1.2
28.1.3
28.2
28.2.1
28.2.2
28.2.3
28.2.3.1
28.2.3.2
28.2.3.2.1
28.2.3.2.2
28.2.3.2.3
28.3
28.3.1
28.3.2
28.3.2.1
28.3.2.2
Overview........................................................................................................................ 29-1
Overview.................................................................................................................... 29-2
Features...................................................................................................................... 29-3
Modes of Operation ................................................................................................... 29-3
Memory Map and Register Definition........................................................................... 29-3
Memory Map ............................................................................................................. 29-4
Register Summary...................................................................................................... 29-4
Register Descriptions................................................................................................. 29-5
SMSC Registers..................................................................................................... 29-5
Gasket Registers .................................................................................................... 29-6
Gasket Timeout Register ................................................................................... 29-6
Gasket Interrupt Status/Clear Register .............................................................. 29-7
Gasket Interrupt Enable Register....................................................................... 29-8
Functional Description................................................................................................... 29-9
Sony Memory Stick Controller (SMSC) ................................................................... 29-9
MSHC Gasket ............................................................................................................ 29-9
Resetting and Clocking.......................................................................................... 29-9
Memory Stick Interface ....................................................................................... 29-10
Chapter 29
Secured Digital Host Controller (SDHC)
29.1
29.1.1
29.2
29.3
29.3.1
Overview........................................................................................................................ 30-2
Features...................................................................................................................... 30-2
External Signal Description ........................................................................................... 30-3
Memory Map and Register Definition........................................................................... 30-4
Memory Map ............................................................................................................. 30-4
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
29.3.2
29.3.3
29.3.3.1
29.3.3.2
29.3.3.3
29.3.3.4
29.3.3.5
29.3.3.6
29.3.3.7
29.3.3.8
29.3.3.9
29.3.3.10
29.3.3.11
29.3.3.12
29.3.3.13
29.3.3.14
29.4
29.4.1
29.4.1.1
29.4.1.2
29.4.1.3
29.4.1.4
29.4.1.5
29.4.2
29.4.2.1
29.4.3
29.4.4
29.4.4.1
29.4.4.2
29.4.4.3
29.4.5
29.4.6
29.4.6.1
29.4.6.2
29.4.7
29.4.8
29.4.9
29.5
29.5.1
29.5.2
29.5.2.1
Page
Number
Title
Register Summary...................................................................................................... 30-5
Register Descriptions................................................................................................. 30-8
SDHC Clock Control Register (STR_STP_CLK)................................................. 30-8
SDHC Status Register (STATUS)........................................................................ 30-10
SDHC Clock Rate Register (CLK_RATE).......................................................... 30-14
SDHC Command and Data Control Register (CMD_DAT_CONT)................... 30-15
SDHC Response Time Out Register (RES_TO) ................................................. 30-17
SDHC Read Time Out Register (READ_TO) ..................................................... 30-18
SDHC Block Length Register (BLK_LEN) ........................................................ 30-19
SDHC Number of Blocks Register (NOB).......................................................... 30-20
SDHC Revision Number Register (REV_NO).................................................... 30-22
SDHC Interrupt Control Register (INT_CNTR) ................................................. 30-22
SDHC Command Number Register (CMD)........................................................ 30-26
SDHC CMD Argument Register (ARG) ............................................................. 30-27
SDHC Response FIFO Access Register (RES_FIFO) ........................................ 30-28
SDHC Data Buffer Access Register (BUFFER_ACCESS) ................................ 30-29
Functional Description................................................................................................. 30-30
Data Buffers ............................................................................................................. 30-30
Data Buffer Access .............................................................................................. 30-31
Write Operation Sequence ................................................................................... 30-32
Read Operation Sequence.................................................................................... 30-32
Data Buffer Size................................................................................................... 30-32
Dividing Large Data Transfer.............................................................................. 30-33
DMA Interface......................................................................................................... 30-34
DMA Request ...................................................................................................... 30-35
Memory Controller .................................................................................................. 30-35
SDIO Card Interrupt ................................................................................................ 30-36
Interrupts in 1-Bit Mode ...................................................................................... 30-36
Interrupt in 4-Bit Mode........................................................................................ 30-36
Card Interrupt Handling....................................................................................... 30-37
Card Insertion and Removal Detection.................................................................... 30-38
Power Management and Wake-Up Events .............................................................. 30-39
Dynamic Voltage/Frequency Scaling (DVFS) Operation.................................... 30-40
Setting Wake-Up Events...................................................................................... 30-40
Command/Data Interpreter ...................................................................................... 30-40
System Clock Controller.......................................................................................... 30-42
DAT/CMD Transceiver............................................................................................ 30-43
Initialization/Application of SDHC ............................................................................. 30-43
Command Submit—Response Receive Basic Operation ........................................ 30-44
Card Identification Mode......................................................................................... 30-45
Card Detect .......................................................................................................... 30-45
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
29.5.2.2
29.5.2.3
29.5.2.4
29.5.3
29.5.3.1
29.5.3.1.1
29.5.3.1.2
29.6
Title
Page
Number
Reset .................................................................................................................... 30-46
Voltage Validation................................................................................................ 30-47
Card Registry ....................................................................................................... 30-48
Card Access ............................................................................................................. 30-50
Block Access—Block Write and Block Read ..................................................... 30-50
Block Write...................................................................................................... 30-50
Block Read ...................................................................................................... 30-51
Commands for MMC/SD/SDIO .................................................................................. 30-52
Chapter 30
Subscriber Identification Module (SIM)
30.1
30.1.1
30.1.2
30.1.3
30.1.4
30.1.5
30.1.6
30.1.7
30.1.8
30.1.9
30.1.10
30.2
30.2.1
30.2.2
30.2.2.1
30.2.2.2
30.2.2.3
30.2.2.4
30.2.2.5
30.2.2.6
30.2.2.7
30.2.2.8
30.2.2.9
30.2.2.10
30.2.2.11
30.3
30.3.1
30.3.2
30.3.3
Introduction.................................................................................................................... 31-1
SIM Features.............................................................................................................. 31-1
SIM Modes of Operation ........................................................................................... 31-2
SIM Bus Interface Overview ..................................................................................... 31-2
SIM Clock Generator Overview ................................................................................ 31-3
SIM Transmitter Overview ........................................................................................ 31-3
SIM Receiver Overview ............................................................................................ 31-3
SIM Port Control Overview....................................................................................... 31-4
SIM General Purpose Counter Overview .................................................................. 31-4
SIM LRC Block Overview ........................................................................................ 31-5
SIM CRC Block Overview ........................................................................................ 31-5
External Signal Description ........................................................................................... 31-5
Overview.................................................................................................................... 31-5
SIM Detailed Signal Descriptions ............................................................................. 31-6
SIM_PIN_SCLK0.................................................................................................. 31-6
SIM_PIN_SRST0 .................................................................................................. 31-6
SIM_PIN_SVEN0 ................................................................................................. 31-6
SIM_PIN_DATA0_TX_OUT................................................................................ 31-6
SIM_PIN_RCVD0_IN .......................................................................................... 31-6
SIM_PIN_SIMPD0................................................................................................ 31-6
SIM_PIN__SRST1 ................................................................................................ 31-7
SIM_PIN__SVEN1 ............................................................................................... 31-7
SIM_PIN_DATA1_TX_OUT................................................................................ 31-7
SIM_PIN_RCVD_IN ............................................................................................ 31-7
SIM_PIN_SIMPD1................................................................................................ 31-7
SIM Memory Map and Register Definition................................................................... 31-7
Memory Map ............................................................................................................. 31-7
SIM Register Summary ............................................................................................. 31-8
SIM Register Descriptions....................................................................................... 31-12
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
30.3.3.1
30.3.3.2
30.3.3.3
30.3.3.4
30.3.3.5
30.3.3.6
30.3.3.7
30.3.3.8
30.3.3.9
30.3.3.10
30.3.3.11
30.3.3.12
30.3.3.13
30.3.3.14
30.3.3.15
30.3.3.16
30.3.3.17
30.3.3.18
30.3.3.19
30.3.3.20
30.3.3.21
30.3.3.22
30.3.3.23
30.3.3.24
30.3.3.25
30.3.3.26
30.3.3.27
30.4
30.4.1
30.4.2
30.4.3
30.4.3.1
30.4.3.2
30.4.3.3
30.4.3.4
30.4.3.5
30.4.3.6
30.4.3.7
30.4.4
30.4.4.1
30.4.4.2
Page
Number
Title
SIM Port1 Control Register (PORT1_CNTL) ..................................................... 31-12
SIM Setup Register (SETUP).............................................................................. 31-13
SIM Port1 Detect Register (PORT1_DETECT).................................................. 31-14
SIM Port1 Transmit Buffer Register (PORT1_XMT_BUF) ............................... 31-15
SIM Port1 Receive Buffer Register (PORT1_RCV_BUF) ................................. 31-16
SIM Port0 Control Register (PORT0_CNTL) ..................................................... 31-17
SIM Control Register (CNTL)............................................................................. 31-18
SIM Clock Select Register (CLOCK_SELECT)................................................. 31-20
SIM Receive Threshold Register (RCV_THRESHOLD) ................................... 31-21
SIM Enable Register (ENABLE) ........................................................................ 31-22
SIM Transmit Status Register (XMT_STATUS) ................................................. 31-23
SIM Receive Status Register (RCV_STATUS) ................................................... 31-25
SIM Interrupt Mask Register (INT_MASK) ....................................................... 31-27
SIM Port0 Transmit Buffer Register (PORT0_XMT_BUF) ............................... 31-29
SIM Port0 Receive Buffer Register (PORT0_RCV_BUF) ................................. 31-30
SIM Port0 Detect Register (PORT0_DETECT).................................................. 31-31
SIM Data Format Register (DATA_FORMAT)................................................... 31-32
SIM Transmit Threshold Register (XMT_THRESHOLD) ................................. 31-33
SIM Transmit Guard Control Register (GUARD_CNTL) .................................. 31-34
SIM Open Drain Configuration Control Register (OD_CONFIG) ..................... 31-35
SIM Reset Control Register (RESET_CNTL) .................................................... 31-36
SIM Character Wait Time Register (CHAR_WAIT)........................................... 31-37
SIM General Purpose Counter Register (GPCNT).............................................. 31-38
SIM Divisor Register (DIVISOR) ....................................................................... 31-39
SIM Block Wait Time Register (BWT) ............................................................... 31-39
SIM Block Guard Time Register (BGT).............................................................. 31-40
SIM Block Wait Time Register HIGH (BWT_H) ............................................... 31-41
SIM Functional Description......................................................................................... 31-42
Detailed SIM Block Diagram .................................................................................. 31-42
SIM Bus Interface.................................................................................................... 31-44
SIM Clock Generator............................................................................................... 31-46
Clock Tree Synthesis ........................................................................................... 31-46
Scan Test .............................................................................................................. 31-47
Baud Clock Generation........................................................................................ 31-47
Transmitter Clock Generation ............................................................................. 31-47
Receiver Clock Generation.................................................................................. 31-47
Port Control Clock Generation ............................................................................ 31-47
Low Power Mode Clock Control......................................................................... 31-48
SIM Transmitter....................................................................................................... 31-48
Transmit State Machine ....................................................................................... 31-48
Transmit Shift Register........................................................................................ 31-50
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
30.4.4.3
30.4.4.4
30.4.4.5
30.4.4.6
30.4.5
30.4.5.1
30.4.5.2
30.4.5.3
30.4.5.4
30.4.5.5
30.4.5.6
30.4.5.7
30.4.5.8
30.4.5.9
30.4.5.10
30.4.6
30.4.6.1
30.4.6.2
30.4.6.3
30.4.7
30.4.8
30.4.9
30.4.10
30.5
30.5.1
30.5.1.1
30.5.1.2
30.5.1.3
30.5.1.4
30.5.1.5
30.5.1.6
30.5.1.7
30.5.2
30.5.2.1
30.5.2.2
30.5.2.3
30.5.2.4
30.5.2.5
30.5.2.6
30.5.2.7
Title
Page
Number
Transmit FIFO ..................................................................................................... 31-50
Transmit Guard Time Generator.......................................................................... 31-50
Transmit NACK Generator.................................................................................. 31-51
Transmit Data Convention Logic ........................................................................ 31-52
SIM Receiver ........................................................................................................... 31-52
Receive State Machine......................................................................................... 31-52
Data Sampling/Voting.......................................................................................... 31-54
Start Bit Detection ............................................................................................... 31-54
Parity Error Detection.......................................................................................... 31-55
Framing Error Detection...................................................................................... 31-55
NACK Detection ................................................................................................. 31-56
Initial Character Detection................................................................................... 31-56
Receive FIFO....................................................................................................... 31-57
Overrun Detection ............................................................................................... 31-57
Character Wait Time Counter .............................................................................. 31-58
SIM Port Control ..................................................................................................... 31-58
SIM Card Interface .............................................................................................. 31-58
SIM Card Presence Detect................................................................................... 31-59
SIM Card Automatic Power Down...................................................................... 31-59
SIM General Purpose Counter................................................................................. 31-60
SIM LRC Block ....................................................................................................... 31-61
SIM CRC Block....................................................................................................... 31-61
SIM Interrupts.......................................................................................................... 31-63
Initialization and Application Information .................................................................. 31-63
Configuring SIM for Operation ............................................................................... 31-63
Configuring the SIM Receiver............................................................................. 31-64
Configuring the SIM Transmitter ........................................................................ 31-65
Configuring SIM General Purpose Counter ........................................................ 31-65
Configuring SIM to Measure WWT (Work Wait Time) for
type=0 SmartCards .......................................................................................... 31-66
Configuring SIM to measure CWT, BWT, BGT for type=1 SmartCards............ 31-66
Configuring SIM Linear Redundancy Check (LRC) Block ................................ 31-67
Configuring SIM Cyclic Redundancy Check (CRC) Block................................ 31-68
Using the SIM Receiver........................................................................................... 31-68
Receive Parity Errors and Parity NACK Generation .......................................... 31-69
Receive Frame Errors .......................................................................................... 31-69
Receive Overrun Errors and Overrun NACK Generation ................................... 31-70
Using Initial Character Mode and Resulting Receive Data Formats................... 31-70
Initial Character Mode Programming Notes........................................................ 31-71
Automatic Receiver Mode................................................................................... 31-71
Using the SIM Receiver with “T=1” SIM Cards................................................. 31-71
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
30.5.3
30.5.3.1
30.5.3.2
30.5.3.3
30.5.3.4
30.5.4
30.5.4.1
30.5.4.2
30.5.4.3
30.5.4.4
Page
Number
Title
Using the SIM Transmitter ...................................................................................... 31-72
Transmit Data Formats ........................................................................................ 31-73
Transmit NACK................................................................................................... 31-73
Transmit Guard Time........................................................................................... 31-73
Using SIM Transmit with “T=1” SIM Cards....................................................... 31-74
Suggested T=1 Compliant Programming Model ..................................................... 31-75
Answer To Reset (ATR) Detection ...................................................................... 31-75
Programming Considerations for Geldkarte Cards.............................................. 31-76
Programming Considerations for T=0 SIM Cards............................................... 31-77
Programming Considerations for T=1 SIM Cards............................................... 31-78
Chapter 31
Universal Asynchronous Receiver/Transmitter (UART)
31.1
31.1.1
31.2
31.2.1
31.2.2
31.2.2.1
31.2.2.1.1
31.2.2.1.2
31.2.2.2
31.2.2.2.1
31.2.2.2.2
31.2.2.3
31.2.2.3.1
31.2.2.3.2
31.2.2.3.3
31.2.2.3.4
31.2.2.3.5
31.2.2.3.6
31.2.2.3.7
31.2.2.3.8
31.2.2.3.9
31.2.2.3.10
31.3
31.3.1
31.3.2
31.3.3
31.3.3.1
Features .......................................................................................................................... 32-2
Modes of Operation ................................................................................................... 32-3
External Signal Description ........................................................................................... 32-3
Overview.................................................................................................................... 32-3
Detailed Signal Descriptions ..................................................................................... 32-4
Interrupt Signals..................................................................................................... 32-4
IPI_UART_RX—Receiver Interrupt ................................................................. 32-4
IPI_UART_TX—Transmitter Interrupt............................................................. 32-4
Serial/IrDA Signals................................................................................................ 32-4
IPP_UART_RXD—Serial Data Receive........................................................... 32-4
IPP_UART_TXD—Serial Data Transmit ......................................................... 32-4
Modem Control Signals......................................................................................... 32-4
IPP_UART_CTS—Clear To Send..................................................................... 32-4
IPP_UART_RTS—Request To Send................................................................. 32-4
IPP_UART_DSR_DTE_I—Data Set Ready (DTE Mode) ............................... 32-4
IPP_UART_DSR_DCE_O—Data Set Ready (DCE Mode) ............................. 32-5
IPP_UART_DCD_DTE_I—Data Carrier Detected (DTE Mode) .................... 32-5
IPP_UART_DCD_DCE_O—Data Carrier Detected (DCE Mode) .................. 32-5
IPP_UART_DTR_DCE_I—Data Terminal Ready (DCE Mode) ..................... 32-5
IPP_UART_DTR_DTE_O—Data Terminal Ready (DTE Mode) .................... 32-5
IPP_UART_RI_DTE_I—Ring Indicator (DTE Mode)..................................... 32-5
IPP_UART_RI_DCE_O—Ring Indicator (DCE Mode)................................... 32-5
Memory Map and Register Definition........................................................................... 32-5
UART Memory Map.................................................................................................. 32-5
Register Summary...................................................................................................... 32-7
Register Descriptions............................................................................................... 32-12
UART Receiver Register (URXD) ...................................................................... 32-12
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
31.3.3.2
31.3.3.3
31.3.3.4
31.3.3.5
31.3.3.6
31.3.3.7
31.3.3.8
31.3.3.9
31.3.3.10
31.3.3.11
31.3.3.12
31.3.3.13
31.3.3.14
31.3.3.15
31.3.3.16
31.4
31.4.1
31.4.1.1
31.4.1.2
31.4.1.3
31.4.1.4
31.4.2
31.4.3
31.4.3.1
31.4.3.2
31.4.4
31.4.4.1
31.4.4.2
31.4.4.3
31.4.4.4
31.4.4.5
31.4.4.6
31.4.4.7
31.4.4.8
31.4.4.9
31.4.4.10
31.4.4.10.1
31.4.5
31.4.5.1
31.4.5.1.1
31.4.5.1.2
Title
Page
Number
UART Transmitter Register (UTXD) .................................................................. 32-14
UART Control Register 1 (UCR1) ...................................................................... 32-15
UART Control Register 2 (UCR2) ...................................................................... 32-17
UART Control Register 3 (UCR3) ...................................................................... 32-19
UART Control Register 4 (UCR4) ...................................................................... 32-22
UART FIFO Control Register (UFCR) ............................................................... 32-23
UART Status Register 1 (USR1) ......................................................................... 32-25
UART Status Register 2 (USR2) ......................................................................... 32-27
UART Escape Character Register (UESC).......................................................... 32-29
UART Escape Timer Register (UTIM) ............................................................... 32-30
UART BRM Incremental Register (UBIR) ......................................................... 32-31
UART BRM Modulator Register (UBMR) ......................................................... 32-32
UART Baud Rate Count Register (UBRC) ......................................................... 32-33
UART One Millisecond Register (ONEMS) ....................................................... 32-34
UART Test Register (UTS).................................................................................. 32-35
Functional Description................................................................................................. 32-37
Integration Guide ..................................................................................................... 32-37
Connections of Signals Used During Serial and Infrared Transfer ..................... 32-37
Special Multiplexing at IC Top Level ................................................................. 32-38
Special Case of 4-Wire Mode.............................................................................. 32-40
Special Case of IrDA Mode (2-Wire Connection) .............................................. 32-41
Interrupts and DMA Requests ................................................................................. 32-42
Clocking Considerations.......................................................................................... 32-43
Min/Max Clock Frequency.................................................................................. 32-43
Clocking in Low-Power Modes........................................................................... 32-44
General UART Definitions ...................................................................................... 32-45
RTS—UART Request To Send............................................................................ 32-46
RTS Edge-Triggered Interrupt ............................................................................. 32-46
DTR—Data Terminal Ready ............................................................................... 32-47
DSR—Data Set Ready......................................................................................... 32-47
DTR/DSR Edge Triggered Interrupt.................................................................... 32-47
DCD—Data Carrier Detect.................................................................................. 32-48
RI—Ring Indicator .............................................................................................. 32-48
CTS—Clear To Send ........................................................................................... 32-48
Programmable CTS Deassertion.......................................................................... 32-48
TXD—UART Transmit ....................................................................................... 32-48
RXD—UART Receive .................................................................................... 32-49
Sub-Block Description............................................................................................. 32-50
Transmitter........................................................................................................... 32-50
Transmitter FIFO Empty Interrupt Suppression.............................................. 32-51
Transmitting a Break Condition ...................................................................... 32-52
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Paragraph
Number
31.4.5.2
31.4.5.2.1
31.4.5.2.2
31.4.5.2.3
31.4.5.2.4
31.4.5.2.5
31.4.5.2.6
31.4.6
31.4.7
31.4.7.1
31.4.7.2
31.4.7.2.1
31.4.7.2.2
31.4.8
31.4.9
31.4.9.1
31.4.9.2
31.4.9.3
31.4.9.4
31.4.9.5
31.4.10
31.4.11
31.5
31.5.1
31.5.2
Page
Number
Title
Receiver ............................................................................................................... 32-53
Idle Line Detect ............................................................................................... 32-54
Idle Condition Detect Configuration ............................................................... 32-55
Aging Character Detect ................................................................................... 32-55
Receiver Wake ................................................................................................. 32-55
Receiving a BREAK Condition....................................................................... 32-56
Vote Logic........................................................................................................ 32-56
Binary Rate Multiplier (BRM) ................................................................................ 32-58
Baud Rate Automatic Detection Logic.................................................................... 32-59
Baud Rate Automatic Detection Protocol............................................................ 32-60
Baud Rate Automatic Detection Protocol Improved ........................................... 32-61
New Baud Rate Determination........................................................................ 32-61
New Autobaud Counter Stopped Bit and Interrupt ......................................... 32-61
Escape Sequence Detection ..................................................................................... 32-61
Infrared Interface ..................................................................................................... 32-63
Generalities .......................................................................................................... 32-63
Inverted Transmission and Reception Bits (INVT and INVR) ........................... 32-63
Infrared Special Case (IRSC) Bit ........................................................................ 32-64
IrDA Interrupt...................................................................................................... 32-65
Conclusion about IrDA........................................................................................ 32-65
UART Operation in Low-Power System States ...................................................... 32-66
UART Operation in System Debug State ................................................................ 32-67
Programming the IrDA Interface ................................................................................. 32-67
High Speed............................................................................................................... 32-67
Low Speed ............................................................................................................... 32-68
Chapter 32
Universal Serial Bus, On-The-Go (USBOTG)
32.1
32.1.1
32.1.1.1
32.1.1.1.1
32.1.1.1.2
32.1.1.1.3
32.2
32.2.1
32.2.1.1
32.2.1.2
32.3
32.3.1
Overview........................................................................................................................ 33-2
Modes of Operation ................................................................................................... 33-2
Operational Modes................................................................................................. 33-2
Normal Mode..................................................................................................... 33-2
Bypass Mode ..................................................................................................... 33-3
Low Power Mode .............................................................................................. 33-3
Memory Map and Register Definition........................................................................... 33-4
Register Descriptions................................................................................................. 33-9
USBCONTROL—USB Control Register ............................................................. 33-9
OTGMIRROR—OTG Port Mirror Register ....................................................... 33-12
Functional Description................................................................................................. 33-13
USB HOST Controller 1.......................................................................................... 33-13
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
32.3.1.1
32.3.2
32.3.3
32.3.3.1
32.3.3.2
32.3.3.3
32.3.4
32.3.4.1
32.3.4.2
32.3.4.2.1
32.3.4.2.2
32.3.5
32.3.5.1
32.3.5.2
32.3.5.3
32.3.6
32.3.6.1
32.3.6.2
32.3.7
32.3.8
32.3.8.1
32.3.8.2
32.4
32.5
32.5.1
32.5.2
32.6
32.7
32.8
32.8.1
32.8.2
32.9
32.9.1
32.9.2
32.9.3
32.9.3.1
32.9.3.2
32.9.3.3
32.9.3.4
32.9.3.5
32.9.3.6
Title
Page
Number
Host Controller 1 to Host Port 1 Interface........................................................... 33-13
Host Controller 2 ..................................................................................................... 33-13
OTG Controller........................................................................................................ 33-14
Host Mode ........................................................................................................... 33-14
Peripheral (Device) Mode.................................................................................... 33-14
Special Considerations......................................................................................... 33-15
USB Power Control Module.................................................................................... 33-15
Entering Suspend Mode....................................................................................... 33-15
Wake-Up Events .................................................................................................. 33-15
Host Mode Events ........................................................................................... 33-15
Device Mode Events........................................................................................ 33-16
TLL Mode................................................................................................................ 33-16
TLL Functional Description ................................................................................ 33-16
Host Port 1 ........................................................................................................... 33-17
Host Port 2 ........................................................................................................... 33-17
USB Bypass Mode................................................................................................... 33-18
Bypass Mode Operation ...................................................................................... 33-18
OTG and Host 1 Pin Functions............................................................................ 33-19
ULPI/Serial MUX.................................................................................................... 33-20
Interrupts.................................................................................................................. 33-20
USB Core Interrupts ............................................................................................ 33-20
USB Wake-Up Interrupts..................................................................................... 33-20
USB Interface .............................................................................................................. 33-21
Overview...................................................................................................................... 33-21
USB 2.0.................................................................................................................... 33-21
USB On-The-Go ...................................................................................................... 33-22
USBOTG Block Diagram ............................................................................................ 33-23
USBOTG Core Features .............................................................................................. 33-23
Functional Description................................................................................................. 33-24
Device Data Structure.............................................................................................. 33-24
Host Data Structure.................................................................................................. 33-24
Register Interface ......................................................................................................... 33-25
Configuration, Control, and Status Register Set...................................................... 33-26
Summary of Register Layouts ................................................................................. 33-28
Identification Registers ............................................................................................ 33-32
ID Register........................................................................................................... 33-32
HWGENERAL .................................................................................................... 33-32
HWHOST ............................................................................................................ 33-33
HWDEVICE ........................................................................................................ 33-34
HWTXBUF.......................................................................................................... 33-35
HWRXBUF ......................................................................................................... 33-36
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
32.9.4
32.9.4.1
32.9.4.2
32.9.4.3
32.9.4.4
32.9.4.5
32.9.5
32.9.5.1
32.9.5.2
32.9.5.3
32.9.5.4
32.9.5.5
32.9.5.5.1
32.9.5.5.2
32.9.5.6
32.9.5.6.1
32.9.5.6.2
32.9.5.7
32.9.5.8
32.9.5.9
32.9.5.9.1
32.9.5.9.2
32.9.5.10
32.9.5.10.1
32.9.5.11
32.9.5.12
32.9.5.13
32.9.5.14
32.9.5.15
32.9.5.16
32.9.5.17
32.9.5.18
32.9.6
32.9.6.1
32.10
32.10.1
32.10.2
32.10.3
32.10.3.1
32.10.3.2
32.10.3.3
Page
Number
Title
Device/Host Capability Registers............................................................................ 33-37
CAPLENGTH—EHCI Compliant....................................................................... 33-37
HCIVERSION—EHCI Compliant...................................................................... 33-37
HCSPARAMS—EHCI Compliant with Extensions............................................ 33-37
HCCPARAMS—EHCI Compliant...................................................................... 33-39
DCCPARAMS (Non-EHCI)................................................................................ 33-41
Device/Host Operational Registers.......................................................................... 33-42
USB Command Register (USBCMD) ................................................................. 33-42
USBSTS............................................................................................................... 33-46
USBINTR ............................................................................................................ 33-49
FRINDEX ............................................................................................................ 33-51
PERIODICLISTBASE; DEVICEADDR ............................................................ 33-52
Host Controller (PERIODICLISTBASE) ....................................................... 33-52
Device Controller (USB DEVICEADDR) ...................................................... 33-53
ASYNCLISTADDR and ENDPOINTLISTADDR ............................................. 33-54
Host Controller (ASYNCLISTADDR)............................................................ 33-54
Device Controller (ENDPOINTLISTADDR) ................................................. 33-55
BURSTSIZE ........................................................................................................ 33-56
TXFILLTUNING................................................................................................. 33-57
ULPI VIEWPORT (Optional) ............................................................................. 33-58
Host Controller ................................................................................................ 33-60
Device Controller ............................................................................................ 33-60
OTGSC ................................................................................................................ 33-67
Host Controller ................................................................................................ 33-67
USBMODE.......................................................................................................... 33-70
ENDPTSETUPSTAT ........................................................................................... 33-71
ENDPTPRIME .................................................................................................... 33-72
ENDPTFLUSH .................................................................................................... 33-73
ENDPTSTAT ....................................................................................................... 33-74
ENDPTCOMPLETE............................................................................................ 33-75
ENDPTCTRL0 .................................................................................................... 33-76
ENDPTCTRL0—ENDPTCTRL15...................................................................... 33-77
OTG Operations....................................................................................................... 33-80
Register Bits......................................................................................................... 33-80
Host Data Structures .................................................................................................... 33-81
Periodic Frame List.................................................................................................. 33-81
Asynchronous List Queue Head Pointer.................................................................. 33-83
Isochronous (High-Speed) Transfer Descriptor (iTD)............................................. 33-83
Next Link Pointer ................................................................................................ 33-84
iTD Transaction Status and Control List ............................................................. 33-85
iTD Buffer Page Pointer List (Plus) .................................................................... 33-86
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Contents
Paragraph
Number
32.10.4
32.10.4.1
32.10.4.2
32.10.4.3
32.10.4.4
32.10.4.5
32.10.5
32.10.5.1
32.10.5.2
32.10.5.3
32.10.5.4
32.10.6
32.10.7
32.10.7.1
32.10.7.2
32.10.8
32.10.8.1
32.10.8.2
32.11
32.11.1
32.11.2
32.11.2.1
32.11.2.2
32.11.2.3
32.11.2.3.1
32.11.2.3.2
32.11.2.4
32.11.2.5
32.11.3
32.11.3.1
32.11.4
32.11.4.1
32.11.5
32.11.6
32.11.7
32.11.7.1
32.11.7.2
32.11.8
32.11.9
32.11.10
32.11.10.1
Title
Page
Number
Split Transaction Isochronous Transfer Descriptor (siTD)...................................... 33-88
Next Link Pointer ................................................................................................ 33-88
siTD Endpoint Capabilities/Characteristics......................................................... 33-89
siTD Transfer State .............................................................................................. 33-90
siTD Buffer Pointer List (Plus)............................................................................ 33-91
siTD Back Link Pointer ....................................................................................... 33-92
Queue Element Transfer Descriptor (qTD) ............................................................. 33-92
Next qTD Pointer................................................................................................. 33-93
Alternate Next qTD Pointer................................................................................. 33-94
qTD Token ........................................................................................................... 33-94
qTD Buffer Page Pointer List .............................................................................. 33-97
Queue Head.............................................................................................................. 33-98
Queue Head Horizontal Link Pointer ...................................................................... 33-99
Endpoint Capabilities/Characteristics.................................................................. 33-99
Transfer Overlay ................................................................................................ 33-102
Periodic Frame Span Traversal Node (FSTN) ...................................................... 33-103
FSTN Normal Path Pointer................................................................................ 33-104
FSTN Back Path Link Pointer .......................................................................... 33-104
Host Operational Model............................................................................................. 33-105
Host Controller Initialization ................................................................................. 33-105
Port Routing and Control ...................................................................................... 33-106
Port Routing Control via EHCI Configured Flag (CF) Bit ............................... 33-108
Port Routing Control via PortOwner and Disconnect Event ............................ 33-109
Example Port Routing State Machine................................................................ 33-110
EHCI HC Owner .......................................................................................... 33-110
Companion HC Owner ................................................................................. 33-110
Port Power .........................................................................................................33-111
Port Reporting Over-Current ............................................................................ 33-112
Suspend/Resume ................................................................................................... 33-113
Port Suspend/Resume ....................................................................................... 33-114
Schedule Traversal Rules ...................................................................................... 33-116
Example: Preserving Micro-Frame Integrity..................................................... 33-117
Periodic Schedule Frame Boundaries Versus Bus Frame Boundaries .................. 33-120
Periodic Schedule .................................................................................................. 33-122
Managing Isochronous Transfers Using iTDs ...................................................... 33-123
Host Controller Operational Model for iTDs ................................................... 33-124
Software Operational Model for iTDs .............................................................. 33-125
Periodic Scheduling Threshold ............................................................................. 33-126
Asynchronous Schedule ........................................................................................ 33-127
Adding Queue Heads to Asynchronous Schedule ................................................ 33-129
Removing Queue Heads from Asynchronous Schedule ................................... 33-129
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
32.11.10.2
32.11.10.3
32.11.10.4
32.11.10.5
32.11.11
32.11.11.1
32.11.12
32.11.12.1
32.11.12.2
32.11.12.3
32.11.12.3.1
32.11.12.3.2
32.11.12.3.3
32.11.12.3.4
32.11.12.4
32.11.12.5
32.11.12.6
32.11.12.7
32.11.12.8
32.11.13
32.11.14
32.11.14.1
32.11.14.1.1
32.11.14.1.2
32.11.14.2
32.11.14.2.1
32.11.14.2.2
32.11.14.3
32.11.14.3.1
32.11.14.3.2
32.11.14.3.3
32.11.14.4
32.11.14.4.1
32.11.14.4.2
32.11.15
32.11.16
32.11.17
32.11.17.1
32.11.17.1.1
32.11.17.1.2
32.11.17.1.3
Page
Number
Title
Empty Asynchronous Schedule Detection ........................................................ 33-131
Restarting Asynchronous Schedule Before EOF............................................... 33-132
Asynchronous Schedule Traversal: Start Event................................................. 33-135
Reclamation Status Bit (USBSTS Register)...................................................... 33-135
Operational Model for NAK Counter.................................................................... 33-135
NAK Count Reload Control ............................................................................. 33-136
Managing Control/Bulk/Interrupt Transfers via Queue Heads.............................. 33-137
Fetch Queue Head.............................................................................................. 33-139
Advance Queue.................................................................................................. 33-140
Execute Transaction........................................................................................... 33-141
Interrupt Transfer Pre-condition Criteria....................................................... 33-141
Asynchronous Transfer Pre-Operations and Pre-Condition Criteria............. 33-141
Transfer Type Independent Pre-Operations ................................................... 33-142
Halting a Queue Head ................................................................................... 33-144
Write Back qTD ................................................................................................ 33-146
Follow Queue Head Horizontal Pointer ........................................................... 33-146
Buffer Pointer List Use for Data Streaming with qTDs .................................... 33-147
Adding Interrupt Queue Heads to the Periodic Schedule ................................. 33-148
Managing Transfer Complete Interrupts from Queue Heads ............................ 33-149
Ping Control........................................................................................................... 33-149
Split Transactions .................................................................................................. 33-150
Split Transactions for Asynchronous Transfers ................................................ 33-151
Asynchronous—Do Start Split ...................................................................... 33-152
Asynchronous—Do Complete Split ............................................................. 33-152
Split Transaction Interrupt ................................................................................ 33-153
Split Transaction Scheduling Mechanisms for Interrupt .............................. 33-153
Host Controller Operational Model for FSTNs ............................................ 33-156
Software Operational Model for FSTNs............................................................ 33-158
Tracking Split Transaction Progress for Interrupt Transfers ......................... 33-159
Split Transaction Execution State Machine for Interrupt ............................. 33-159
Rebalancing the Periodic Schedule .............................................................. 33-165
Split Transaction Isochronous ........................................................................... 33-166
Split Transaction Scheduling Mechanisms for Isochronous ......................... 33-166
Tracking Split Transaction Progress for Isochronous Transfers ................... 33-169
Host Controller Pause ............................................................................................ 33-179
Port Test Modes ..................................................................................................... 33-180
Interrupts ............................................................................................................... 33-180
Transfer/Transaction Based Interrupts............................................................... 33-181
Transaction Error ........................................................................................... 33-181
Serial Bus Babble .......................................................................................... 33-182
Data Buffer Error .......................................................................................... 33-183
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
32.11.17.1.4
32.11.17.1.5
32.11.17.2
32.11.17.2.1
32.11.17.2.2
32.11.17.2.3
32.11.17.2.4
32.12
32.12.1
32.12.1.1
32.12.1.2
32.12.1.3
32.12.1.4
32.12.1.5
32.12.1.5.1
32.12.1.5.2
32.12.1.5.3
32.12.1.5.4
32.12.1.5.5
32.12.2
32.12.2.1
32.12.2.2
32.12.2.3
32.12.3
32.12.3.1
32.12.4
32.12.4.1
32.12.4.2
32.12.4.2.1
32.12.4.2.2
32.12.4.3
32.13
32.13.1
32.13.1.1
32.13.1.2
32.13.1.3
32.13.1.4
32.13.2
32.14
32.14.1
32.14.2
Title
Page
Number
USB Interrupt (Interrupt on Completion (IOC)............................................. 33-183
Short Packet ................................................................................................... 33-183
Host Controller Event Interrupts ....................................................................... 33-184
Port Change Events ...................................................................................... 33-184
Frame List Rollover....................................................................................... 33-184
Interrupt on Async Advance.......................................................................... 33-184
Host System Error ......................................................................................... 33-184
EHCI Deviation ......................................................................................................... 33-185
Embedded Transaction Translator Function .......................................................... 33-186
Capability Registers........................................................................................... 33-186
Operational Registers......................................................................................... 33-186
Discovery ........................................................................................................... 33-186
Data Structures................................................................................................... 33-187
Operational Model ............................................................................................. 33-188
Micro-Frame Pipeline.................................................................................... 33-188
Split State Machines ...................................................................................... 33-188
Asynchronous Transaction Scheduling and Buffer Management ................. 33-189
Periodic Transaction Scheduling and Buffer Management ........................... 33-189
Multiple Transaction Translators................................................................... 33-190
Device Operation ................................................................................................... 33-190
USBMODE Register ......................................................................................... 33-190
Non-Zero Fields in the Register File ................................................................. 33-190
SOF Interrupt ..................................................................................................... 33-191
Embedded Design Interface................................................................................... 33-191
Frame Adjust Register ....................................................................................... 33-191
Miscellaneous variations from EHCI .................................................................... 33-191
Programmable Physical Interface Behavior ...................................................... 33-191
Discovery ........................................................................................................... 33-191
Port Reset....................................................................................................... 33-191
Port Speed Detection ..................................................................................... 33-192
Port Test Mode................................................................................................... 33-192
Device Data Structures .............................................................................................. 33-192
Endpoint Queue Head (dQH) ................................................................................ 33-193
Endpoint Capabilities/Characteristics................................................................ 33-194
Transfer Overlay ................................................................................................ 33-195
Current dTD Pointer .......................................................................................... 33-195
Set-up Buffer...................................................................................................... 33-195
Endpoint Transfer Descriptor (dTD) ..................................................................... 33-196
Device Operational Model......................................................................................... 33-198
Device Controller Initialization ............................................................................. 33-198
Port State and Control............................................................................................ 33-199
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
32.14.2.1
32.14.2.2
32.14.2.2.1
32.14.2.2.2
32.14.2.2.3
32.14.2.3
32.14.2.4
32.14.2.5
32.14.2.6
32.14.2.6.1
32.14.2.6.2
32.14.3
32.14.3.0.1
32.14.3.0.2
32.14.3.1
32.14.3.1.1
32.14.3.2
32.14.3.2.1
32.14.3.2.2
32.14.3.2.3
32.14.3.2.4
32.14.3.3
32.14.3.3.1
32.14.3.3.2
32.14.4
32.14.4.1
32.14.4.2
32.14.5
32.14.5.1
32.14.5.2
32.14.5.3
32.14.5.4
32.14.5.5
32.14.5.6
32.14.6
32.14.6.1
32.14.6.2
32.14.6.3
Page
Number
Title
Bus Reset ........................................................................................................... 33-201
Suspend/Resume................................................................................................ 33-202
Suspend.......................................................................................................... 33-202
Resume .......................................................................................................... 33-202
Port Test Modes ............................................................................................. 33-203
Managing Endpoints.......................................................................................... 33-203
Endpoint Initialization ....................................................................................... 33-203
Stalling ............................................................................................................... 33-204
Data Toggle........................................................................................................ 33-205
Data Toggle Reset.......................................................................................... 33-205
Data Toggle Inhibit ........................................................................................ 33-205
Operational Model For Packet Transfers ............................................................... 33-205
Priming Transmit Endpoints.......................................................................... 33-206
Priming Receive Endpoints ........................................................................... 33-206
Interrupt/Bulk Endpoint Operational Model ..................................................... 33-206
Interrupt/Bulk Endpoint Bus Response Matrix ............................................. 33-208
Control Endpoint Operation Model ................................................................... 33-208
Setup Phase.................................................................................................... 33-208
Data Phase ..................................................................................................... 33-210
Status Phase ................................................................................................... 33-210
Control Endpoint Bus Response Matrix........................................................ 33-210
Isochronous Endpoint Operational Model......................................................... 33-211
Isochronous Pipe Synchronization ................................................................ 33-212
Isochronous Endpoint Bus Response Matrix................................................. 33-213
Managing Queue Heads......................................................................................... 33-213
Queue Head Initialization .................................................................................. 33-214
Operational Model For Setup Transfers ............................................................ 33-214
Managing Transfers with Transfer Descriptors ..................................................... 33-215
Software Link Pointers ...................................................................................... 33-215
Building a Transfer Descriptor .......................................................................... 33-215
Executing A Transfer Descriptor ....................................................................... 33-216
Transfer Completion .......................................................................................... 33-216
Flushing/De-priming an Endpoint ..................................................................... 33-217
Device Error Matrix........................................................................................... 33-217
Servicing Interrupts................................................................................................ 33-218
High-Frequency Interrupts................................................................................. 33-218
Low-Frequency Interrupts ................................................................................. 33-219
Error Interrupts .................................................................................................. 33-219
Chapter 33
Enhanced Periodic Interrupt Timer (EPIT 1, 2)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
33.1
33.1.1
33.1.2
33.2
33.2.1
33.3
33.4
33.5
33.5.1
33.5.2
33.5.2.1
33.5.2.2
33.5.2.3
33.5.2.4
33.5.2.5
33.6
33.6.1
33.6.1.1
33.6.1.2
33.6.1.3
33.6.1.4
Title
Page
Number
Overview........................................................................................................................ 34-2
Features...................................................................................................................... 34-2
Modes of Operation ................................................................................................... 34-2
Signal Description.......................................................................................................... 34-2
Overview.................................................................................................................... 34-2
External Signals ............................................................................................................. 34-3
EPIT Module Signals..................................................................................................... 34-4
Memory Map and Register Definition........................................................................... 34-5
Memory Map ............................................................................................................. 34-5
Register Summary...................................................................................................... 34-6
EPIT Control Register (EPITCR).......................................................................... 34-8
EPIT Status Register (EPITSR)........................................................................... 34-10
EPIT Load Register (EPITLR) ............................................................................ 34-11
EPIT Compare Register (EPITCMPR)................................................................ 34-11
EPIT Counter Register (EPITCNT)..................................................................... 34-12
Functional Description................................................................................................. 34-13
Operation ................................................................................................................. 34-13
Clocks .................................................................................................................. 34-13
Overwriting the Counter Value............................................................................ 34-15
Low-Power Mode Behavior ................................................................................ 34-15
Debug Mode Behavior......................................................................................... 34-15
Chapter 34
General Purpose Timer (GPT)
34.1
34.1.1
34.1.2
34.2
34.2.1
34.2.2
34.2.2.1
34.2.2.2
34.2.2.3
34.2.3
34.3
34.3.1
34.3.2
34.3.3
34.3.3.1
Overview........................................................................................................................ 35-2
Features...................................................................................................................... 35-2
Modes of Operation ................................................................................................... 35-2
Signal Description.......................................................................................................... 35-3
Overview.................................................................................................................... 35-3
External Signals ......................................................................................................... 35-4
External Clock Input (ipp_ind_clkin).................................................................... 35-5
Input Capture Trigger Signals (ipp_ind_capin1, ipp_ind_capin2) ........................ 35-5
Output Compare Signals (ipp_do_cmpout1, ipp_do_cmpout2,
ipp_do_cmpout3)............................................................................................... 35-5
GPT Module Internal Signals .................................................................................... 35-5
Register Definition and Memory Map........................................................................... 35-7
Memory Map ............................................................................................................. 35-7
Register Summary...................................................................................................... 35-8
Register Descriptions............................................................................................... 35-10
GPT Control Register (GPTCR) .......................................................................... 35-10
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
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Contents
Paragraph
Number
34.3.3.2
34.3.3.3
34.3.3.4
34.3.3.5
34.3.3.6
34.3.3.7
34.3.3.8
34.3.3.9
34.3.3.10
34.4
34.4.1
34.4.1.1
34.4.1.2
34.4.1.3
34.4.1.4
34.4.1.5
34.4.1.6
Page
Number
Title
GPT Prescaler Register (GPTPR) ........................................................................ 35-14
GPT Status Register (GPTSR) ............................................................................. 35-14
GPT Interrupt Register (GPTIR).......................................................................... 35-15
GPT Output Compare Register 1 (GPTOCR1).................................................... 35-16
GPT Output Compare Register 2 (GPTOCR2).................................................... 35-17
GPT Output Compare Register 3 (GPTOCR3).................................................... 35-18
GPT Input Capture Register 1 (GPTICR1) .......................................................... 35-18
GPT Input Capture Register 2 (GPTICR2) .......................................................... 35-19
GPT Counter Register (GPTCNT)....................................................................... 35-20
Functional Description................................................................................................. 35-20
Operation ................................................................................................................. 35-20
Clocks .................................................................................................................. 35-21
Input Capture ....................................................................................................... 35-22
Output Compare................................................................................................... 35-22
Interrupts.............................................................................................................. 35-23
Low-Power Mode Behavior ................................................................................ 35-24
Debug Mode Behavior......................................................................................... 35-24
Chapter 35
Pulse-Width Modulator (PWM)
35.1
35.2
35.2.1
35.2.1.1
35.2.2
35.3
35.3.1
35.3.2
35.3.2.1
35.3.2.2
35.3.2.3
35.3.2.4
35.3.2.5
35.3.2.6
35.4
35.4.1
35.4.1.1
35.4.1.2
35.4.1.3
35.4.1.4
Overview........................................................................................................................ 36-1
Signal Description.......................................................................................................... 36-2
External Signals ......................................................................................................... 36-3
ipp_do_pwmo ........................................................................................................ 36-4
PWM Module Boundary Signals............................................................................... 36-4
Memory Map and Register Definition........................................................................... 36-5
Register Summary...................................................................................................... 36-6
Register Descriptions................................................................................................. 36-7
PWM Control Register (PWMCR)........................................................................ 36-8
PWM Status Register (PWMSR)........................................................................... 36-9
PWM Interrupt Register (PWMIR) ..................................................................... 36-11
PWM Sample Register (PWMSAR) ................................................................... 36-11
PWM Period Register (PWMPR)........................................................................ 36-12
PWM Counter Register (PWMCNR) .................................................................. 36-13
Functional Description................................................................................................. 36-14
Operation ................................................................................................................. 36-14
Clocks .................................................................................................................. 36-14
FIFO..................................................................................................................... 36-15
Rollover and Compare Event............................................................................... 36-15
Low Power Mode Behavior................................................................................. 36-16
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
35.4.1.5
35.5
35.5.1
35.5.2
Title
Page
Number
Debug Mode Behavior......................................................................................... 36-16
PWM Clocking ............................................................................................................ 36-16
PWM Clock Inputs .................................................................................................. 36-16
ipg_enable_clk Generation ...................................................................................... 36-18
Chapter 36
Real Time Clock (RTC)
36.1
36.1.1
36.1.2
36.2
36.2.1
36.3
36.3.1
36.3.2
36.3.3
36.3.3.1
36.3.3.2
36.3.3.3
36.3.3.4
36.3.3.5
36.3.3.6
36.3.3.7
36.3.3.8
36.3.3.9
36.3.3.10
36.4
36.4.1
36.4.2
36.4.3
36.4.4
36.5
36.5.1
36.5.2
Overview........................................................................................................................ 37-2
Features...................................................................................................................... 37-2
Modes of Operation ................................................................................................... 37-2
External Signal Description ........................................................................................... 37-3
Overview.................................................................................................................... 37-3
Memory Map and Register Definition........................................................................... 37-3
Memory Map ............................................................................................................. 37-3
Register Summary...................................................................................................... 37-3
Register Descriptions................................................................................................. 37-6
RTC Hours and Minutes Counter Register (HOURMIN) ..................................... 37-6
RTC Seconds Counter Register (SECONDS) ....................................................... 37-7
RTC Hours and Minutes Alarm Register (ALRM_HM) ....................................... 37-7
RTC Seconds Alarm Register (ALRM_SEC) ....................................................... 37-8
RTC Control Register (RTCCTL) ......................................................................... 37-9
RTC Interrupt Status Register (RTCISR) ............................................................ 37-10
RTC Interrupt Enable Register (RTCIENR)........................................................ 37-12
RTC Stopwatch Minutes Register (STPWCH).................................................... 37-14
RTC Days Counter Register (DAYR).................................................................. 37-15
RTC Day Alarm Register (DAYALARM)........................................................... 37-16
Functional Description................................................................................................. 37-17
Prescaler and Counter .............................................................................................. 37-17
Alarm ....................................................................................................................... 37-17
Sampling Timer ....................................................................................................... 37-18
Minute Stopwatch .................................................................................................... 37-18
Initialization/Application Information ......................................................................... 37-19
Flowchart of RTC Operation ................................................................................... 37-19
Code Example of ARM Instruction ......................................................................... 37-19
Chapter 37
Watchdog Timer (WDOG)
37.1
37.1.1
Overview........................................................................................................................ 38-1
Features...................................................................................................................... 38-2
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
37.2
37.2.1
37.2.1.1
37.2.2
37.3
37.3.1
37.3.2
37.4
37.4.1
37.4.2
37.4.2.1
37.5
37.5.1
37.5.2
37.5.3
37.5.3.1
37.5.3.2
37.5.3.3
37.5.3.4
37.5.4
37.5.5
37.5.5.1
37.5.5.2
37.5.6
37.5.7
37.5.8
37.6
37.6.1
Page
Number
Title
External Signal Description ........................................................................................... 38-2
Detailed External Signal Descriptions....................................................................... 38-2
IPP_WDOG, IPP_WDOG_OE .............................................................................. 38-2
Internal Port Signals................................................................................................... 38-2
Memory Map and Register Definitions ......................................................................... 38-4
Watchdog Timer Memory Map.................................................................................. 38-4
Register Summary...................................................................................................... 38-4
Register Descriptions ..................................................................................................... 38-5
Watchdog Control Register (WCR) ........................................................................... 38-5
Watchdog Service Register (WSR)............................................................................ 38-6
Watchdog Reset Status Register (WRSR) ............................................................. 38-7
Functional Description................................................................................................... 38-8
Timing Specifications ................................................................................................ 38-8
Watchdog During Reset ............................................................................................. 38-8
Watchdog After Reset ................................................................................................ 38-9
Initial Load............................................................................................................. 38-9
Timer Countdown .................................................................................................. 38-9
Reloading the Counter ........................................................................................... 38-9
Time-Out................................................................................................................ 38-9
Generation of Transfer Error on the IP Bus............................................................... 38-9
Low-Power and DEBUG Modes ............................................................................. 38-10
Low-Power Mode (WAIT, DOZE, STOP) .......................................................... 38-10
DEBUG Mode ..................................................................................................... 38-10
Watchdog Reset Control .......................................................................................... 38-10
WDOG Operation.................................................................................................... 38-11
Clock Monitor.......................................................................................................... 38-11
Initialization/Application Information ......................................................................... 38-12
State Machine .......................................................................................................... 38-12
Chapter 38
AHB-Lite 2.v6 to IP Bus Interface (AIPS)
38.1
38.1.1
38.1.2
38.2
38.2.1
38.2.2
38.2.2.1
38.2.2.1.1
38.2.2.1.2
Overview........................................................................................................................ 39-1
Features...................................................................................................................... 39-1
General Operation...................................................................................................... 39-2
AIPS Interface Signals................................................................................................... 39-7
AIPS Signal Overview............................................................................................... 39-7
AIPS Signal Descriptions .......................................................................................... 39-9
AHB Interface Signals......................................................................................... 39-10
System Clock—hclk ........................................................................................ 39-10
System Reset—hreset ...................................................................................... 39-10
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
38.2.2.1.3
38.2.2.1.4
38.2.2.1.5
38.2.2.1.6
38.2.2.1.7
38.2.2.1.8
38.2.2.1.9
38.2.2.1.10
38.2.2.1.11
38.2.2.1.12
38.2.2.1.13
38.2.2.1.14
38.2.2.1.15
38.2.2.1.16
38.2.2.1.17
38.2.2.1.18
38.2.2.1.19
38.2.2.1.20
38.2.2.1.21
38.2.2.2
38.2.2.2.1
38.2.2.2.2
38.2.2.2.3
38.2.2.2.4
38.2.2.2.5
38.2.2.2.6
38.2.2.2.7
38.2.2.2.8
38.2.2.2.9
38.2.2.2.10
38.2.2.2.11
38.2.2.3
38.2.2.3.1
38.2.2.3.2
38.2.2.4
38.2.2.4.1
38.2.2.4.2
38.2.2.4.3
38.2.2.4.4
38.2.2.4.5
Title
Page
Number
AIPS Select Signal—hsel_aips........................................................................ 39-10
AHB Master—hmaster[3:0] ............................................................................ 39-10
AIPS Sideband Inputs—hsideband_in_aips[3:0] ............................................ 39-10
Address Bus—haddr[25:0] .............................................................................. 39-10
Write Data Bus—hwdata[63:0] (hwdata[31:0]) .............................................. 39-10
Read Data Bus—aips_hrdata[63:0] (aips_hrdata[31:0]) ................................. 39-10
Transfer Type—htrans[1:0] ............................................................................. 39-10
Burst Type—hburst[2:0].................................................................................. 39-11
Transfer Direction—hwrite ............................................................................. 39-11
Protection Control—hprot[5,1:0] .................................................................... 39-11
Transfer Size—hsize[1:0] ................................................................................ 39-12
Transfer Unaligned—hunalign ........................................................................ 39-12
Transfer Byte Strobes—hbstrb[7:0] (hbstrb[3:0]) ........................................... 39-12
AIPS Transfer Done—aips_hready_out .......................................................... 39-13
Transfer Done In—hready_in.......................................................................... 39-13
Transfer Response—aips_hresp[2:0]............................................................... 39-13
Byte Ordering Configuration—aips_byte_config[1:0] ................................... 39-13
Disable Multi-access for Data—aips_disable_macc ....................................... 39-13
AIPS Idle—aips_idle....................................................................................... 39-13
Off-Platform IPS V3.0 Interface Signals............................................................. 39-14
IP Address Bus—ips_addr[25:0]..................................................................... 39-14
IP Read Data Bus—ips_rdata[31:0] ................................................................ 39-14
IP Write Data Bus ............................................................................................ 39-14
ips_module_en[31:0], ips_module_en_glbl[1:0], ips_module_en_nonglbl .... 39-14
ips_rwb ............................................................................................................ 39-15
ips_byte_31_24, ips_byte_23_16, ips_byte_15_8, ips_byte_7_0 ................... 39-16
ips_byte_15_8_16bit, ips_byte_7_0_16bit...................................................... 39-16
ips_xfr_wait ..................................................................................................... 39-16
ips_xfr_err ....................................................................................................... 39-16
ips_supervisor_access...................................................................................... 39-16
ips_seq_access ................................................................................................. 39-16
Off-Platform IPS Sideband Signals ..................................................................... 39-17
aips_master[3:0] .............................................................................................. 39-17
aips_sideband[3:0]........................................................................................... 39-17
On-Platform IPS V3.0 Interface Signals ............................................................. 39-17
IP Address Bus—onpf_ips_addr[18:0] ........................................................... 39-17
IP Read Data Buses—onpf_ips_rdata[31:1][31:0].......................................... 39-17
IP Write Data Bus—onpf_ips_wdata[31:0]..................................................... 39-17
onpf_ips_module_en[31:1].............................................................................. 39-18
onpf_ips_rwb ................................................................................................... 39-19
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
38.2.2.4.6
38.2.2.4.7
38.2.2.4.8
38.2.2.4.9
38.2.2.4.10
38.2.2.4.11
38.2.2.5
38.2.2.5.1
38.2.2.5.2
38.3
38.3.1
38.3.2
38.3.3
38.3.3.1
38.3.3.2
38.3.3.3
38.4
38.4.1
38.4.1.1
38.4.1.2
38.4.1.3
38.4.1.4
38.4.1.5
38.4.1.6
38.4.2
38.4.3
38.4.4
38.4.4.1
38.4.4.2
38.4.4.3
38.4.5
38.4.6
38.4.7
38.4.8
38.4.9
38.4.10
38.5
38.5.1
Page
Number
Title
onpf_ips_byte_31_24, onpf_ips_byte_23_16, onpf_ips_byte_15_8,
onpf_ips_byte_7_0 ...................................................................................... 39-19
onpf_ips_byte_15_8_16bit, onpf_ips_byte_7_0_16bit ................................... 39-19
onpf_ips_xfr_wait[31:1] .................................................................................. 39-19
onpf_ips_xfr_err[31:1] .................................................................................... 39-19
onpf_ips_supervisor_access ............................................................................ 39-20
onpf_ips_seq_access........................................................................................ 39-20
AIPS Configuration Signals ................................................................................ 39-20
aips_rstcfg[63:0].............................................................................................. 39-20
aips_psize1[33:0], aips_psize0[33:0] .............................................................. 39-20
Memory Map and Register Definition......................................................................... 39-21
AIPS A and AIPS B Memory Map.......................................................................... 39-21
Register Summary.................................................................................................... 39-22
Register Descriptions............................................................................................... 39-24
Master Privilege Registers (MPR_1 and MPR_2)............................................... 39-24
Peripheral Access Control Registers (PACR_1, PACR_2, PACR_3,
and PACR_4) ................................................................................................... 39-26
Off-Platform Peripheral Access Control Registers (OPACR_1, OPACR_2,
OPACR_3, OPACR_4, and OPACR_5) .......................................................... 39-29
Functional Description................................................................................................. 39-33
AIPS Scalability....................................................................................................... 39-33
Master Presence ................................................................................................... 39-35
Peripheral Presence.............................................................................................. 39-35
AHB Data Port Width.......................................................................................... 39-36
Memory Map ....................................................................................................... 39-36
Registers .............................................................................................................. 39-36
Read Cycle and Buffered Write Delay Control ................................................... 39-36
Access Protections ................................................................................................... 39-36
Peripheral Write Buffering....................................................................................... 39-37
Data Byte Lane and Byte Strobe Mapping .............................................................. 39-37
32-Bit Peripherals ................................................................................................ 39-38
16-Bit Peripherals ................................................................................................ 39-42
8-Bit Peripherals .................................................................................................. 39-50
Access Support ........................................................................................................ 39-52
Read Cycles ............................................................................................................. 39-53
Write Cycles............................................................................................................. 39-54
Buffered Write Cycles ............................................................................................. 39-54
Aborted Cycles ........................................................................................................ 39-55
Timing Diagrams ..................................................................................................... 39-55
Initialization/Application Information ......................................................................... 39-73
Software Restrictions............................................................................................... 39-73
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
Title
Page
Number
Chapter 39
Multi-Layer AHB Crossbar Switch (MAX)
39.1
39.1.1
39.1.2
39.2
39.2.1
39.2.2
39.2.2.1
39.2.2.2
39.3
39.3.1
39.3.2
39.3.3
39.3.3.1
39.3.3.2
39.3.3.3
39.3.4
39.4
39.4.1
39.4.1.1
39.4.1.2
39.4.1.3
39.4.2
39.4.3
39.4.3.1
39.4.3.2
39.4.3.3
39.4.3.4
39.4.3.5
39.4.3.5.1
39.4.3.5.2
39.4.4
39.4.4.1
39.4.4.2
39.4.4.3
39.4.4.4
39.4.4.4.1
39.4.4.4.2
39.4.4.4.3
Features .......................................................................................................................... 40-3
Limitations ................................................................................................................. 40-3
General Operation...................................................................................................... 40-3
MAX Interface Signals .................................................................................................. 40-4
MAX Signal Overview .............................................................................................. 40-4
MAX Signal Descriptions.......................................................................................... 40-9
max_halt_request ................................................................................................... 40-9
max_halted............................................................................................................. 40-9
Memory Map and Register Definition......................................................................... 40-10
Memory Map ........................................................................................................... 40-10
Register Summary.................................................................................................... 40-11
MAX Register Descriptions..................................................................................... 40-14
Master Priority Register (MPR0–MPR4) ............................................................ 40-14
Slave General Purpose Control Register (SGPCR0–SGPCR4) .......................... 40-15
Master General Purpose Control Register ........................................................... 40-17
Coherency ................................................................................................................ 40-18
Detailed Functional Description .................................................................................. 40-19
Arbitration................................................................................................................ 40-19
Arbitration During Undefined Length Bursts...................................................... 40-19
Fixed Priority Operation ...................................................................................... 40-19
Round-Robin Priority Operation ......................................................................... 40-20
Priority Assignment ................................................................................................. 40-20
Master Port Functionality ........................................................................................ 40-21
General................................................................................................................. 40-21
Master Port Decoders .......................................................................................... 40-23
Master Port Capture Unit..................................................................................... 40-23
Master Port Registers........................................................................................... 40-23
Master Port State Machine................................................................................... 40-23
Master Port State Machine States .................................................................... 40-23
Master Port State Machine Slave Swapping.................................................... 40-24
Slave Port Functionality........................................................................................... 40-24
General................................................................................................................. 40-24
Slave Port Muxes................................................................................................. 40-25
Slave Port Registers............................................................................................. 40-26
Slave Port State Machine..................................................................................... 40-26
Slave Port State Machine States ...................................................................... 40-26
Slave Port State Machine Arbitration .............................................................. 40-26
Slave Port State Machine Master Handoff ...................................................... 40-27
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
39.4.4.4.4
39.4.4.4.5
39.5
39.6
39.6.1
39.6.2
39.6.2.1
39.6.2.2
39.6.2.3
39.6.2.4
39.6.3
39.7
39.7.1
39.7.2
39.7.3
39.7.4
Page
Number
Title
Slave Port State Machine Parking ................................................................... 40-29
Slave Port State Machine Halt Mode............................................................... 40-31
Initialization/Application Information ......................................................................... 40-31
MAX Interface ............................................................................................................. 40-31
Overview.................................................................................................................. 40-32
Master Ports ............................................................................................................. 40-32
Terminated Accesses ........................................................................................... 40-32
Taken Accesses .................................................................................................... 40-32
Stalled Accesses................................................................................................... 40-32
Error Response Terminated Accesses.................................................................. 40-32
Slave Ports ............................................................................................................... 40-33
Integration .................................................................................................................... 40-33
Address Map ............................................................................................................ 40-33
Master Ports ............................................................................................................. 40-34
Slave Ports ............................................................................................................... 40-35
Registers................................................................................................................... 40-35
Chapter 40
Smart Direct Memory Access (SDMA)
40.1
40.2
40.3
40.4
40.4.1
40.4.2
40.4.3
40.4.3.1
40.4.3.2
40.4.4
40.5
40.5.1
40.5.2
40.5.2.1
40.5.2.2
40.5.2.3
40.5.3
40.5.3.1
40.5.3.2
40.5.3.3
40.5.3.4
Overview........................................................................................................................ 41-1
Features .......................................................................................................................... 41-3
Functional Description................................................................................................... 41-5
SDMA Core ................................................................................................................... 41-5
Attributes ................................................................................................................... 41-6
Structure..................................................................................................................... 41-6
Program Control Unit (PCU)..................................................................................... 41-8
Instruction Types ................................................................................................... 41-9
PCU States ............................................................................................................. 41-9
SDMA Core Memory .............................................................................................. 41-12
Scheduler ..................................................................................................................... 41-12
Primary Functions.................................................................................................... 41-12
Channels and DMA Requests .................................................................................. 41-12
Channels .............................................................................................................. 41-12
DMA Requests..................................................................................................... 41-12
Mapping from DMA Requests to Channels and Priorities.................................. 41-13
Scheduler Functional Description............................................................................ 41-13
Scheduler Overview............................................................................................. 41-13
DMA Requests Scanning..................................................................................... 41-14
Mapping DMA Requests to Pending Channels ................................................... 41-15
Channel Overflow................................................................................................ 41-17
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
40.5.3.5
40.5.3.6
40.5.3.7
40.5.3.8
40.5.3.9
40.5.3.10
40.5.4
40.5.4.1
40.5.4.2
40.5.4.3
40.6
40.6.1
40.6.1.1
40.6.1.2
40.6.1.3
40.6.1.4
40.6.2
40.6.2.1
40.6.2.2
40.6.2.3
40.6.2.3.1
40.6.2.3.2
40.6.2.3.3
40.6.3
40.6.3.1
40.6.3.2
40.6.3.3
40.6.3.3.1
40.6.3.3.2
40.6.3.3.3
40.7
40.8
40.8.1
40.8.2
40.8.2.1
40.8.2.2
40.8.2.3
40.8.2.3.1
40.8.2.3.2
40.8.2.3.3
40.8.2.4
Title
Page
Number
Runnable Channels Evaluation............................................................................ 41-17
Next Channel Decision Tree................................................................................ 41-18
Scheduler State Diagram ..................................................................................... 41-20
Scheduler Pipeline Timing Diagram.................................................................... 41-22
Channel-DMA Request Mapping ........................................................................ 41-22
Examples: How to Start a Channel ...................................................................... 41-22
Context Switching.................................................................................................... 41-23
Context Switch Modes......................................................................................... 41-23
Context Switch Procedure ................................................................................... 41-23
Context Map in Memory ..................................................................................... 41-24
Functional Units........................................................................................................... 41-24
CRC Calculation Unit.............................................................................................. 41-25
CRC Structure...................................................................................................... 41-25
CRC Data Processing .......................................................................................... 41-25
CRC Registers ..................................................................................................... 41-26
CRC Summary..................................................................................................... 41-26
Burst DMA Unit ...................................................................................................... 41-27
Burst DMA Structure........................................................................................... 41-27
Burst DMA Registers .......................................................................................... 41-28
Data Transfers...................................................................................................... 41-29
Data Retrieval from the AP Memory .............................................................. 41-29
Storing Data Into the AP Memory................................................................... 41-29
Transferring Data Between Two AP Memory Locations ................................ 41-29
Peripheral DMA Unit............................................................................................... 41-30
Peripheral DMA Structure ................................................................................... 41-30
Peripheral DMA Registers................................................................................... 41-31
Peripheral DMA Data Transfers .......................................................................... 41-31
Data Retrieval from the AP Memory or Peripheral......................................... 41-32
Storing Data into the AP Memory or Peripheral ............................................. 41-32
Transferring Data Between Two AP Memory Locations ................................ 41-32
OnCE and PCU Debug States...................................................................................... 41-32
SDMA Clocks and Low Power Modes........................................................................ 41-33
Root and Derived Clocks......................................................................................... 41-33
Clock Gating and Low Power Modes...................................................................... 41-34
Coarse Clock Gating............................................................................................ 41-34
Refined Clock Gating .......................................................................................... 41-35
Low Power Modes and User Control .................................................................. 41-35
SLEEP Mode ................................................................................................... 41-36
RUN Mode ...................................................................................................... 41-36
DEBUG Mode ................................................................................................. 41-36
Stop Mode Response ........................................................................................... 41-37
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
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Contents
Paragraph
Number
40.8.3
40.9
40.10
40.10.1
40.10.2
40.10.3
40.10.3.1
40.10.3.2
40.10.3.3
40.10.3.4
40.10.3.5
40.10.3.6
40.10.3.7
40.10.3.8
40.10.3.9
40.10.3.10
40.10.3.11
40.10.3.12
40.10.3.13
40.10.3.14
40.10.3.15
40.10.3.16
40.10.3.17
40.10.3.18
40.10.3.19
40.10.3.20
40.10.3.21
40.10.3.22
40.10.3.23
40.10.3.24
40.10.3.25
40.11
40.11.1
40.11.2
40.11.3
40.11.3.1
40.11.3.2
40.11.3.3
40.11.3.4
40.11.3.5
Page
Number
Title
Reset......................................................................................................................... 41-37
Software Interface........................................................................................................ 41-37
AP Memory Map and Control Register Definitions .................................................... 41-37
AP Memory Map ..................................................................................................... 41-37
Register Summary.................................................................................................... 41-38
Register Descriptions............................................................................................... 41-43
AP Channel 0 Pointer (MC0PTR) ....................................................................... 41-43
Channel Interrupts (INTR) .................................................................................. 41-44
Channel Stop/Channel Status (STOP_STAT) ...................................................... 41-44
Channel Start (HSTART)..................................................................................... 41-45
Channel Event Override (EVTOVR)................................................................... 41-46
Channel DSP Override (DSPOVR) ..................................................................... 41-46
Channel AP Override (HOSTOVR) .................................................................... 41-47
Channel Event Pending (EVTPEND).................................................................. 41-48
Reset Register (RESET) ...................................................................................... 41-48
DMA Request Error Register (EVTERR) ........................................................... 41-49
Channel AP Interrupt Mask Flags (INTRMASK)............................................... 41-50
Schedule Status (PSW) ........................................................................................ 41-51
DMA Request Error Register for Debug (EVTERRDBG) ................................. 41-52
Configuration Register (CONFIG) ...................................................................... 41-53
OnCE Enable (ONCE_ENB)............................................................................... 41-54
OnCE Data Register (ONCE_DATA).................................................................. 41-54
OnCE Instruction Register (ONCE_INSTR)....................................................... 41-55
OnCE Status Register (ONCE_STAT) ................................................................ 41-56
OnCE Command Register (ONCE_CMD).......................................................... 41-58
Illegal Instruction Trap Address (ILLINSTADDR) ............................................ 41-59
Channel 0 Boot Address (CHN0ADDR)............................................................. 41-59
DMA Requests (EVT_MIRROR) ....................................................................... 41-60
Cross-Trigger Events Configuration Register (1) and (2) (XTRIG_CONF1 and
XTRIG_CONF2) ............................................................................................. 41-61
Channel Priority Registers (CHNPRIn)............................................................... 41-64
Channel Enable RAM (CHNENBLn) ................................................................. 41-65
SDMA Programming Model ....................................................................................... 41-66
State and Registers Per Channel .............................................................................. 41-66
General Purpose Registers ....................................................................................... 41-66
Functional Unit State ............................................................................................... 41-66
Program Counter Register (PC)........................................................................... 41-66
Flags..................................................................................................................... 41-67
Return Program Counter (RPC)........................................................................... 41-67
Loop Mode Start Program Counter (SPC)........................................................... 41-67
Loop Mode End Program Counter (EPC) ........................................................... 41-67
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
40.11.4
40.11.5
40.11.5.1
40.11.5.2
40.12
40.12.1
40.12.2
40.12.3
40.12.3.1
40.12.3.2
40.12.3.3
40.12.3.4
40.12.3.5
40.12.3.6
40.12.3.7
40.12.3.8
40.12.3.9
40.12.3.10
40.12.3.11
40.12.3.12
40.12.3.13
40.12.3.14
40.12.3.15
40.12.3.16
40.12.3.17
40.12.3.18
40.12.3.19
40.13
40.14
40.14.1
40.14.2
40.14.3
40.14.4
40.15
40.15.1
40.15.2
40.15.3
40.15.4
40.15.5
40.15.6
40.15.7
Title
Page
Number
Context Switching.................................................................................................... 41-68
Address Space.......................................................................................................... 41-69
Instruction Memory Map..................................................................................... 41-70
Data Memory Map............................................................................................... 41-70
SDMA Internal (Core) Memory Map and Internal Register Definitions .................... 41-72
SDMA Internal (Core) Registers Memory Map ...................................................... 41-72
Register Summary.................................................................................................... 41-72
SDMA Core Register Descriptions.......................................................................... 41-76
AP (MCU) Channel 0 Pointer (MC0PTR)........................................................... 41-76
Current Channel Pointer (CCPTR) ...................................................................... 41-77
Current Channel Register (CCR)......................................................................... 41-77
Highest Pending Channel Register (NCR) .......................................................... 41-78
External DMA Requests Mirror (EVENTS) ....................................................... 41-79
Current Channel Priority (CCPRI) ...................................................................... 41-80
Next Channel Priority (NCPRI)........................................................................... 41-81
OnCE Event Cell Counter (ECOUNT)................................................................ 41-81
OnCE Event Cell Control Register (ECTL) ........................................................ 41-82
OnCE Event Address Register A (EAA)............................................................. 41-83
OnCE Event Cell Address Register B (EAB)...................................................... 41-84
OnCE Event Cell Address Mask (EAM)............................................................. 41-85
OnCE Event Cell Data Register (ED) ................................................................. 41-85
OnCE Event Cell Data Mask (EDM) .................................................................. 41-86
OnCE Real-Time Buffer (RTB)........................................................................... 41-87
OnCE Trace Buffer (TB) ..................................................................................... 41-87
OnCE Status (OSTAT)......................................................................................... 41-88
Channel 0 Boot Address (MCHN0ADDR) ......................................................... 41-91
ENDIAN Mode Status Register (ENDIANESS)................................................. 41-92
SDMA Peripheral Registers......................................................................................... 41-93
SDMA Initialization .................................................................................................... 41-93
Hardware Reset........................................................................................................ 41-93
Standard Boot Sequence .......................................................................................... 41-93
User-Defined Boot Sequence................................................................................... 41-94
Script Loading and Context Initialization................................................................ 41-94
Instruction Description ................................................................................................ 41-94
Scheduling Instructions............................................................................................ 41-94
Conditional Branch Instructions .............................................................................. 41-95
Unconditional Jump Instructions ............................................................................. 41-95
Subroutine Return Instructions ................................................................................ 41-95
Loop Instruction....................................................................................................... 41-95
Miscellaneous Instructions ...................................................................................... 41-96
Logic Instructions .................................................................................................... 41-96
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
40.15.8
40.15.9
40.15.10
40.15.11
40.15.12
40.15.13
40.15.14
40.15.15
40.15.16
40.15.17
40.16
40.16.1
40.16.1.1
40.16.1.2
40.16.1.3
40.16.1.4
40.16.1.5
40.16.1.6
40.16.1.7
40.16.1.8
40.16.1.8.1
40.16.1.8.2
40.16.1.8.3
40.16.1.9
40.16.1.10
40.16.1.11
40.16.2
40.16.2.1
40.16.2.2
40.16.2.3
40.16.2.4
40.16.2.5
40.16.2.6
40.16.2.7
40.16.2.8
40.16.2.8.1
40.16.2.8.2
40.16.2.8.3
40.16.2.8.4
40.16.2.8.5
40.16.2.8.6
Page
Number
Title
Arithmetic Instructions ............................................................................................ 41-96
Compare Instructions............................................................................................... 41-97
Test Instructions ....................................................................................................... 41-97
Byte Permutation Instructions ................................................................................. 41-97
Bit Shift Instructions................................................................................................ 41-97
Bit Manipulation Instructions .................................................................................. 41-98
SDMA Memory Access Instructions....................................................................... 41-98
Functional Unit Instructions .................................................................................... 41-98
Illegal Instructions ................................................................................................... 41-98
Debug Instructions................................................................................................... 41-99
Functional Units Programming Model ........................................................................ 41-99
Burst DMA Unit .................................................................................................... 41-100
Memory Source Address Register (MSA)......................................................... 41-100
Memory Destination Address Register (MDA)................................................. 41-100
Memory Data Buffer Register (MD) ................................................................. 41-101
State Register (MS)............................................................................................ 41-101
Burst DMA Write (stf)....................................................................................... 41-103
Burst DMA Read (ldf) ....................................................................................... 41-105
Prefetch/Flush and Auto-Flush Management .................................................... 41-106
Data Alignment and Endianness........................................................................ 41-108
Burst DMA in Read Mode............................................................................. 41-108
Burst DMA in Write Mode............................................................................ 41-108
Endianness ..................................................................................................... 41-110
Copy Mode ........................................................................................................ 41-110
Error Management ..............................................................................................41-111
Conditional Yielding.......................................................................................... 41-112
Peripheral DMA Unit............................................................................................. 41-113
Peripheral Source Address Register (PSA) ....................................................... 41-113
Peripheral Destination Address Register (PDA) ............................................... 41-114
Peripheral Data Register (PD) ........................................................................... 41-114
Peripheral State Register (PS)............................................................................ 41-115
Peripheral DMA Write (stf)—Write Mode........................................................ 41-116
Peripheral DMA Read (ldf)—Read Mode......................................................... 41-119
Copy Mode ........................................................................................................ 41-120
Error Management ............................................................................................. 41-120
Immediate Errors ........................................................................................... 41-120
Data Transfer Errors ...................................................................................... 41-121
Read Error (First Phase) ................................................................................ 41-121
Write Error and Read Error (Second Phase).................................................. 41-122
Copy Mode Errors ......................................................................................... 41-122
Error Check Example .................................................................................... 41-123
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
40.16.2.9
40.16.3
40.16.4
40.16.4.1
40.16.4.2
40.16.4.3
40.16.4.4
40.16.4.5
40.16.5
40.16.5.1
40.16.5.2
40.16.5.3
40.16.5.4
40.16.5.5
40.17
40.17.1
40.17.2
40.17.2.1
40.17.2.2
40.17.2.3
40.17.3
40.17.3.1
40.17.3.2
40.17.3.3
40.17.4
40.17.4.1
40.17.4.2
40.17.4.3
40.17.4.4
40.17.4.5
40.17.4.6
40.17.4.7
40.17.4.8
40.17.4.9
40.17.5
40.17.5.1
40.17.5.2
40.17.5.3
40.18
40.18.1
40.18.2
Title
Page
Number
Prefetch/Flush Management .............................................................................. 41-123
BP DMA Unit ........................................................................................................ 41-123
CRC Unit ............................................................................................................... 41-124
Polynomial Register (CA) ................................................................................. 41-124
Accumulator Register (CS)................................................................................ 41-125
Write Instruction (stf) ........................................................................................ 41-125
Read Instruction (ldf)......................................................................................... 41-126
Operating Mode ................................................................................................. 41-126
OnCE and Real-Time Debug ................................................................................. 41-127
Memory and Register Access ............................................................................ 41-127
Hardware Breakpoints ....................................................................................... 41-127
Watchpoints ....................................................................................................... 41-127
Software Breakpoints......................................................................................... 41-127
Core Control ...................................................................................................... 41-128
The OnCE Controller................................................................................................. 41-128
OnCE Commands .................................................................................................. 41-128
Sending Commands to the OnCE Controller......................................................... 41-129
Using the JTAG Interface .................................................................................. 41-129
Using the AP...................................................................................................... 41-129
Conflicts Between the JTAG and the AP Accesses ........................................... 41-130
Executing a Command from the OnCE ................................................................. 41-131
Nature of the Commands ................................................................................... 41-131
Execution Request ............................................................................................. 41-131
Command Execution ......................................................................................... 41-131
Registers Descriptions ........................................................................................... 41-133
Event Cell Counter Register (ECOUNT) .......................................................... 41-133
Event Cell Address Registers (EAA or EAB) ................................................... 41-133
Event Cell Address Mask Register (EAM) ....................................................... 41-134
Event Cell Data Register (ED) .......................................................................... 41-134
Event Cell Data Mask Register (EDM) ............................................................. 41-134
Real Time Buffer Register (RTB)...................................................................... 41-134
Event Control Register (ECTL)......................................................................... 41-134
Trace Buffer (TB) .............................................................................................. 41-134
OnCE Status Register (OSTAT) ........................................................................ 41-134
JTAG Interface Requirements................................................................................ 41-135
TCK Speed Limitation....................................................................................... 41-135
Synchronization Implementation....................................................................... 41-135
JTAG Controller Start-Up Recommended Procedure ....................................... 41-137
Using the OnCE ......................................................................................................... 41-137
Activating Clocks in Debug Mode ........................................................................ 41-137
Getting the Current Status...................................................................................... 41-138
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
40.18.3
40.18.3.1
40.18.3.2
40.18.3.3
40.18.3.4
40.18.4
40.18.5
40.18.5.1
40.18.5.2
40.18.5.3
40.18.5.4
40.18.5.5
40.18.5.6
40.18.5.7
40.18.6
40.18.7
40.18.7.1
40.18.7.2
40.18.8
40.18.8.1
40.18.8.2
40.18.8.3
40.18.8.4
40.19
40.19.1
40.19.2
40.20
40.21
40.21.1
40.22
40.22.1
40.22.1.1
40.22.1.2
40.22.1.2.1
40.22.1.2.2
40.22.1.3
40.22.1.3.1
40.22.1.3.2
40.22.1.4
40.22.1.4.1
40.22.1.4.2
Page
Number
Title
Methods of Entering Debug Mode ........................................................................ 41-138
External Debug Request During Reset .............................................................. 41-138
Debug Request During Normal Activity ........................................................... 41-138
Software Breakpoint Instruction........................................................................ 41-138
Event Detection Unit Matching Condition ........................................................ 41-138
Executing Instructions in Debug Mode ................................................................. 41-139
Command Sequences Examples ............................................................................ 41-139
Getting the SDMA Status .................................................................................. 41-139
Saving the Context............................................................................................. 41-140
Restoring the Context ........................................................................................ 41-141
Accessing the Memory ...................................................................................... 41-142
Resuming Program Execution ........................................................................... 41-142
Single Stepping in RAM.................................................................................... 41-142
Single Stepping in ROM.................................................................................... 41-143
OnCE Event Detection Unit .................................................................................. 41-143
Clock Gating and Reset ......................................................................................... 41-144
Clocks ................................................................................................................ 41-144
Resets................................................................................................................. 41-145
Real Time Features ................................................................................................ 41-145
Trace Buffer ....................................................................................................... 41-145
Real Time Buffer ............................................................................................... 41-146
Emulation Pin .................................................................................................... 41-146
Real-Time Debug Outputs ................................................................................. 41-146
Instruction Set ............................................................................................................ 41-149
Instruction Encoding.............................................................................................. 41-149
SDMA Instruction Set ........................................................................................... 41-151
Reference Clocks ....................................................................................................... 41-212
Software Restrictions ................................................................................................. 41-213
Unsupported Burst DMA Access Sequence .......................................................... 41-213
Application Notes ...................................................................................................... 41-213
Typical Data Transfer Supported by SDMA DMA Units ..................................... 41-213
External Memory to External Memory.............................................................. 41-214
Peripheral to Peripheral Transfer ....................................................................... 41-215
Source and Destination Target Have the Same Data Path Width .................. 41-215
Source and Destination Target Have a Different Data Path Width................ 41-216
Transfer Between Peripheral and External Memory ......................................... 41-216
Peripheral to External Memory Transfer ....................................................... 41-216
External Memory to Peripheral Transfer ....................................................... 41-218
Transfer Between External Memory and Internal Memory............................... 41-219
Internal Memory to Internal Memory............................................................ 41-219
Transfer Between Peripheral and Internal Memory ...................................... 41-219
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
Title
Page
Number
Chapter 41
Shared Peripheral Bus Arbiter (SPBA)
41.1
41.1.1
41.1.2
41.2
41.2.1
41.2.1.1
41.3
41.3.1
41.3.2
41.4
41.5
41.5.1
41.6
41.7
41.8
41.8.1
41.8.1.1
41.8.1.2
41.8.2
41.8.3
41.8.3.1
41.8.3.2
41.8.4
41.9
41.10
41.10.1
41.10.2
41.11
Overview........................................................................................................................ 42-3
Features...................................................................................................................... 42-4
Modes of Operation ................................................................................................... 42-4
Signal Description.......................................................................................................... 42-5
Out-of-Band Steering Control ................................................................................... 42-5
obsc(n)[4:0]............................................................................................................ 42-5
Memory Map and Register Definition........................................................................... 42-5
Memory Map ............................................................................................................. 42-5
Register Summary...................................................................................................... 42-7
SPBA Register Definition.............................................................................................. 42-8
Register Descriptions ................................................................................................... 42-10
Peripheral Right Register (PRRn)............................................................................ 42-10
Functional Description................................................................................................. 42-12
Masters Arbitration ...................................................................................................... 42-12
Resource Ownership Control....................................................................................... 42-14
Access Control......................................................................................................... 42-15
Peripheral Access................................................................................................. 42-15
Peripheral Right Register Access ........................................................................ 42-15
Owner Election ........................................................................................................ 42-15
Ending Ownership ................................................................................................... 42-16
Hardware Controlled Ownership Ending ............................................................ 42-16
Software Controlled Ownership Ending.............................................................. 42-16
The Un-Owned State ............................................................................................... 42-16
IP-Multiplexing............................................................................................................ 42-16
Clock Usage ................................................................................................................. 42-17
SPBA Clocks ........................................................................................................... 42-17
SPBA and Synchronization ..................................................................................... 42-17
Reset Usage.................................................................................................................. 42-18
Chapter 42
Digital Audio Multiplexer (AUDMUX)
42.1
42.1.1
42.1.2
42.1.3
42.1.3.1
42.1.3.1.1
Overview........................................................................................................................ 43-1
Features...................................................................................................................... 43-4
Port Descriptions........................................................................................................ 43-4
Network Modes.......................................................................................................... 43-4
Port Receive Data Modes ...................................................................................... 43-5
Normal Mode..................................................................................................... 43-6
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
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Contents
Paragraph
Number
42.1.3.1.2
42.1.3.1.3
42.1.3.1.4
42.1.3.2
42.1.3.3
42.1.3.3.1
42.1.3.3.2
42.1.4
42.1.4.1
42.1.4.2
42.1.4.3
42.1.4.4
42.2
42.3
42.3.1
42.3.2
42.3.2.1
42.3.2.2
42.3.2.3
42.3.2.4
42.3.2.5
42.3.2.6
42.3.2.7
42.3.2.8
42.3.2.9
42.3.2.10
42.3.2.11
42.3.2.12
42.3.2.13
42.3.2.14
42.3.2.15
42.3.2.15.1
42.3.3
42.3.3.1
42.3.3.2
42.4
42.4.1
42.4.2
42.4.3
Page
Number
Title
Internal Network Mode ..................................................................................... 43-6
Bottom Connector Network Mode .................................................................. 43-12
Transmit Data Output Enable Assertion.......................................................... 43-15
Tx/Rx Switch and External Network Mode ........................................................ 43-15
Timing Modes...................................................................................................... 43-16
Synchronous Mode (4-Wire Interface) ............................................................ 43-16
Asynchronous Mode (6-Wire Interface).......................................................... 43-17
Connectivity Between Ports..................................................................................... 43-20
Internal Port to External Port Connectivity ......................................................... 43-21
External Port to External Port Connectivity ........................................................ 43-23
Internal Port to Internal Port Connectivity .......................................................... 43-23
Loopback Connectivity........................................................................................ 43-23
External Signal Description ......................................................................................... 43-24
Memory Map and Register Definition......................................................................... 43-24
Register Summary.................................................................................................... 43-25
Register Descriptions............................................................................................... 43-28
Port Timing Control Register 1 (PTCR1) ............................................................ 43-28
Port Data Control Register 1 (PDCR1) ............................................................... 43-31
Port Timing Control Register 2 (PTCR2) ............................................................ 43-32
Port Data Control Register 2 (PDCR2) ............................................................... 43-34
Port Timing Control Register 3 (PTCR3) ............................................................ 43-36
Port Data Control Register 3 (PDCR3) ............................................................... 43-38
Port Timing Control Register 4 (PTCR4) ............................................................ 43-39
Port Data Control Register 4 (PDCR4) ............................................................... 43-41
Port Timing Control Register 5 (PTCR5) ............................................................ 43-43
Port Data Control Register 5 (PDCR5) ............................................................... 43-45
Port Timing Control Register 6 (PTCR6) ............................................................ 43-46
Port Data Control Register 6 (PDCR6) ............................................................... 43-48
Port Timing Control Register 7 (PTCR7) ............................................................ 43-50
Port Data Control Register 7 (PDCR7) ............................................................... 43-52
Bottom Connector Network Mode Control Register (CNMCR)......................... 43-53
Limitations of bc_bus_dis Signal Generation ................................................. 43-55
AUDMUX Default Configuration ........................................................................... 43-56
Default Port Configuration .................................................................................. 43-56
Default Bottom Connector Configuration ........................................................... 43-56
AUDMUX Clocking.................................................................................................... 43-57
AUDMUX Clock Inputs.......................................................................................... 43-57
AUDMUX Clock Diagram...................................................................................... 43-57
Clocking Restrictions............................................................................................... 43-58
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
Title
Page
Number
Chapter 43
Moving Pictures Experts Group-4 (MPEG-4) Encoder
43.1
43.2
43.3
Overview........................................................................................................................ 44-1
MPEG-4 Video Encoder ................................................................................................ 44-1
Functional Description................................................................................................... 44-2
Chapter 44
Image Processing Unit (IPU)
44.1
44.1.1
44.1.1.1
44.1.1.2
44.1.1.3
44.1.1.4
44.1.1.4.1
44.1.1.4.2
44.1.1.4.3
44.1.2
44.1.3
44.2
44.2.1
44.2.2
44.2.2.1
44.2.2.1.1
44.2.2.1.2
44.2.2.1.3
44.2.2.1.4
44.2.2.1.5
44.2.2.1.6
44.2.2.2
44.2.2.2.1
44.2.2.2.2
44.2.2.2.3
44.2.2.2.4
44.2.2.2.5
44.2.2.2.6
44.2.2.2.7
44.2.2.2.8
44.2.2.2.9
Introduction.................................................................................................................... 45-1
Overview.................................................................................................................... 45-2
Performed Functions.............................................................................................. 45-2
External Interfaces ................................................................................................. 45-3
Data Flows and Formats ........................................................................................ 45-3
Clocking Scheme ................................................................................................... 45-6
General............................................................................................................... 45-6
Changing Clock Rates and Disabling Clocks.................................................... 45-9
Clocking Microarchitecture ............................................................................. 45-10
IPU Features ............................................................................................................ 45-12
Modes of Operation ................................................................................................. 45-21
External Signal Description ......................................................................................... 45-25
Overview.................................................................................................................. 45-25
Detailed Signal Descriptions ................................................................................... 45-27
Sensor Interface ................................................................................................... 45-27
IPP_IND_SENSB_DATA[15:1]...................................................................... 45-27
IPP_IND_SENSB_PIX_CLK ......................................................................... 45-27
IPP_IND_SENSB_HSYNC ............................................................................ 45-27
IPP_IND_SENSB_VSYNC ............................................................................ 45-28
SENSB_SENS_CLK ....................................................................................... 45-28
IPP_DO_SENSB_MCLK................................................................................ 45-28
Display Interface.................................................................................................. 45-28
IPP_IND_DISPB_DATA[17:0] ....................................................................... 45-28
IPP_DO_DISPB_DATA[17:0] ........................................................................ 45-28
IPP_OBE_DISPB_DATA................................................................................ 45-28
IPP_OBE_DISPB_DATA16_17...................................................................... 45-28
IPP_DO_DISPB_D3_VSYNC........................................................................ 45-28
IPP_DO_DISPB_D3_HSYNC........................................................................ 45-28
IPP_DO_DISPB_D3_CLK ............................................................................. 45-29
IPP_IND_DISPB_D3_DRDY......................................................................... 45-29
IPP_DO_DISPB_D3_SPL............................................................................... 45-29
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
44.2.2.2.10
44.2.2.2.11
44.2.2.2.12
44.2.2.2.13
44.2.2.2.14
44.2.2.2.15
44.2.2.2.16
44.2.2.2.17
44.2.2.2.18
44.2.2.2.19
44.2.2.2.20
44.2.2.2.21
44.2.2.2.22
44.2.2.2.23
44.2.2.2.24
44.2.2.2.25
44.2.2.2.26
44.2.2.2.27
44.2.2.2.28
44.2.2.2.29
44.2.2.2.30
44.2.2.2.31
44.3
44.3.1
44.3.2
44.3.3
44.3.3.1
44.3.3.1.1
44.3.3.1.2
44.3.3.1.3
44.3.3.1.4
44.3.3.1.5
44.3.3.1.6
44.3.3.1.7
44.3.3.1.8
44.3.3.1.9
44.3.3.1.10
Page
Number
Title
IPP_DO_DISPB_D3_CLS .............................................................................. 45-29
IPP_DO_DISPB_D3_REV ............................................................................. 45-29
IPP_IND_DISPB_D0_VSYNC....................................................................... 45-29
IPP_DO_DISPB_D0_VSYNC........................................................................ 45-29
IPP_OBE_DISPB_D0_VSYNC...................................................................... 45-29
IPP_DO_DISPB_D0_CS................................................................................. 45-29
IPP_DO_DISPB_D1_CS................................................................................. 45-29
IPP_DO_DISPB_D2_CS................................................................................. 45-30
IPP_DO_DISPB_PAR_RS .............................................................................. 45-30
IPP_DO_DISPB_SER_RS .............................................................................. 45-30
IPP_DO_DISPB_WR...................................................................................... 45-30
IPP_DO_DISPB_RD....................................................................................... 45-30
IPP_IND_DISPB_SD_D ................................................................................. 45-30
IPP_DO_DISPB_SD_D .................................................................................. 45-30
IPP_OBE_DISPB_SD_D ................................................................................ 45-30
IPP_DO_DISPB_SD_D_CLK ........................................................................ 45-30
IPP_IND_DISPB_D12_VSYNC..................................................................... 45-30
IPP_DO_DISPB_D12_VSYNC...................................................................... 45-30
IPP_OBE_DISPB_D12_VSYNC.................................................................... 45-31
IPP_DO_DISPB_CONTRAST ....................................................................... 45-31
IPP_DO_DISPB_BCLK.................................................................................. 45-31
Usage of the Display Interface Signals............................................................ 45-31
Memory Map and Register Definition......................................................................... 45-32
Memory Map ........................................................................................................... 45-32
Register Summary.................................................................................................... 45-37
Register Descriptions............................................................................................... 45-65
IPU Common Registers ....................................................................................... 45-65
IPU Configuration Register (IPU_CONF) ...................................................... 45-65
IPU Channels Buffer 0 Ready Register (IPU_CHA_BUF0_RDY) ................ 45-67
IPU Channels Buffer 1 Ready Register (IPU_CHA_BUF1_RDY) ................ 45-68
IPU Channel Double Buffer Mode Select Register
(IPU_CHA_DB_MODE_SEL) ................................................................... 45-69
IPU Channel Current Buffer Register (IPU_CHA_CUR_BUF) ..................... 45-70
IPU Frame Synchronization Processing Flow Register
(IPU_FS_PROC_FLOW)............................................................................ 45-71
IPU Frame Synchronization Displaying Flow Register
(IPU_FS_DISP_FLOW).............................................................................. 45-74
IPU Tasks Status Register (IPU_TASKS_STAT) ............................................ 45-75
IPU Internal Memory Access Address and Data Registers
(IPU_IMA_ADDR and IPU_IMA_DATA)................................................. 45-79
IPU Interrupt Control Register 1 (IPU_INT_CTRL_1) ................................ 45-102
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
44.3.3.1.11
44.3.3.1.12
44.3.3.1.13
44.3.3.1.14
44.3.3.1.15
44.3.3.1.16
44.3.3.1.17
44.3.3.1.18
44.3.3.1.19
44.3.3.1.20
44.3.3.1.21
44.3.3.1.22
44.3.3.1.23
44.3.3.2
44.3.3.2.1
44.3.3.2.2
44.3.3.2.3
44.3.3.2.4
44.3.3.2.5
44.3.3.2.6
44.3.3.2.7
44.3.3.2.8
44.3.3.2.9
44.3.3.2.10
44.3.3.3
44.3.3.3.1
44.3.3.3.2
44.3.3.3.3
44.3.3.3.4
44.3.3.3.5
44.3.3.3.6
44.3.3.4
44.3.3.4.1
44.3.3.5
44.3.3.5.1
44.3.3.5.2
44.3.3.5.3
44.3.3.5.4
44.3.3.6
Title
Page
Number
IPU Interrupt Control Register 2 (IPU_INT_CTRL_2) ................................ 45-103
IPU Interrupt Control Register 3 (IPU_INT_CTRL_3) ................................ 45-104
IPU Interrupt Control Register 4 (IPU_INT_CTRL_4) ................................ 45-107
IPU Interrupt Control Register 5 (IPU_INT_CTRL_5) ................................ 45-108
IPU Interrupt Status Register 1 (IPU_INT_STAT_1).....................................45-111
IPU Interrupt Status Register 2 (IPU_INT_STAT_2).................................... 45-112
IPU Interrupt Status Register 3 (IPU_INT_STAT_3).................................... 45-113
IPU Interrupt Status Register 4 (IPU_INT_STAT_4).................................... 45-117
IPU Interrupt Status Register 5 (IPU_INT_STAT_5).................................... 45-118
IPU Break Control Register 1 (IPU_BRK_CTRL_1) ................................... 45-120
IPU Break Control Register 2 (IPU_BRK_CTRL_2) ................................... 45-122
IPU Break Status Register (IPU_BRK_STAT).............................................. 45-124
IPU Diagnostic Bus Control Register (IPU_DIAGB_CTRL)....................... 45-124
CSI Registers ..................................................................................................... 45-137
CSI Sensor Configuration Register (CSI_SENS_CONF) ............................. 45-137
CSI Sensor Frame Size Register (CSI_SENS_FRM_SIZE) ......................... 45-138
CSI Actual Frame Size Register (CSI_ACT_FRM_SIZE) ........................... 45-139
CSI Output Frame Control Register (CSI_OUT_FRM_CTRL) ................... 45-140
CSI Test Control Register (CSI_TST_CTRL)............................................... 45-141
CSI CCIR Code Register 1 (CSI_CCIR_CODE_1)...................................... 45-142
CSI CCIR Code Register 2 (CSI_CCIR_CODE_2)...................................... 45-143
CSI CCIR Code Register 3 (CSI_CCIR_CODE_3)...................................... 45-144
CSI Flash Strobe Register 1 (CSI_FLASH_STROBE_1)............................. 45-144
CSI Flash Strobe Register 2 (CSI_FLASH_STROBE_2)............................. 45-145
IC Registers ....................................................................................................... 45-146
IC Configuration Register (IC_CONF) ......................................................... 45-146
IC Preprocessing Encoder Resizing Coefficients Register
(IC_PRP_ENC_RSC)................................................................................ 45-149
IC Preprocessing View-Finder Resizing Coefficients Register
(IC_PRP_VF_RSC)................................................................................... 45-150
IC Post-Processing Resizing Coefficients Register (IC_PP_RSC) ............... 45-151
IC Combining Parameters Register 1 (IC_CMBP_1) ................................... 45-152
IC Combining Parameters Register 2 (IC_CMBP_2) ................................... 45-153
Post Filter (PF) Registers................................................................................... 45-153
Post Filter (PF) Configuration Register (PF_CONF) .................................... 45-153
IDMAC Registers .............................................................................................. 45-154
IDMAC Configuration Register (IDMAC_CONF) ...................................... 45-154
IDMAC Channel Enable Register (IDMAC_CHA_EN) .............................. 45-156
IDMAC Channel Priority Register (IDMAC_CHA_PRI) ............................ 45-156
IDMAC Channel Busy Register (IDMAC_CHA_BUSY) ............................ 45-158
SDC Registers.................................................................................................... 45-158
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
44.3.3.6.1
44.3.3.6.2
44.3.3.6.3
44.3.3.6.4
44.3.3.6.5
44.3.3.6.6
44.3.3.6.7
44.3.3.6.8
44.3.3.6.9
44.3.3.6.10
44.3.3.6.11
44.3.3.7
44.3.3.7.1
44.3.3.7.2
44.3.3.7.3
44.3.3.7.4
44.3.3.7.5
44.3.3.7.6
44.3.3.7.7
44.3.3.7.8
44.3.3.7.9
44.3.3.7.10
44.3.3.7.11
44.3.3.7.12
44.3.3.7.13
44.3.3.7.14
44.3.3.7.15
44.3.3.7.16
44.3.3.7.17
44.3.3.8
44.3.3.8.1
Page
Number
Title
SDC Common Configuration Register (SDC_COM_CONF)....................... 45-158
SDC Graphic Window Control Register
(SDC_GRAPH_WIND_CTRL) ................................................................ 45-160
SDC Foreground Window Position Register (SDC_FG_POS)..................... 45-162
SDC Background Window Position Register (SDC_BG_POS) ................... 45-163
SDC Cursor Position Register (SDC_CUR_POS) ........................................ 45-163
SDC Cursor Blinking and PWM Contrast Control Register
(SDC_CUR_BLINK_PWM_CTRL) ........................................................ 45-164
SDC Color Cursor Mapping Register (SDC_CUR_MAP) ........................... 45-165
SDC Horizontal Configuration Register (SDC_HOR_CONF) ..................... 45-166
SDC Vertical Configuration Register (SDC_VER_CONF) .......................... 45-167
SDC Sharp Configuration Register 1 (SDC_SHARP_CONF_1) ................. 45-169
SDC Sharp Configuration Register 2 (SDC_SHARP_CONF_2) ................. 45-170
ADC Registers ................................................................................................... 45-170
ADC Configuration Register (ADC_CONF) ................................................ 45-170
ADC System Channel 1 Start Address Register
(ADC_SYSCHA1_SA) ............................................................................. 45-174
ADC System Channel 2 Start Address Register
(ADC_SYSCHA2_SA) ............................................................................. 45-175
ADC Preprocessing Channel Start Address Register
(ADC_PRPCHAN_SA) ............................................................................ 45-175
ADC Post-Processing Channel Start Address Register
(ADC_PPCHAN_SA) ............................................................................... 45-176
ADC Display 0 Configuration Register (ADC_DISP0_CONF) ................... 45-177
ADC Display 0 Read Acknowledge Pattern Register
(ADC_DISP0_RD_AP)............................................................................. 45-178
ADC Display 0 Read Mask Register (ADC_DISP0_RDM) ......................... 45-179
ADC Display 0 Screen Size Register (ADC_DISP0_SS) ............................. 45-179
ADC Display 1 Configuration Register (ADC_DISP1_CONF) ................... 45-180
ADC Display 1 Read Acknowledge Pattern Register
(ADC_DISP1_RD_AP)............................................................................. 45-182
ADC Display 1 Read Mask Register (ADC_DISP1_RDM) ......................... 45-182
ADC Displays 1 or 2 Screen Size Register (ADC_DISP12_SS) .................. 45-183
ADC Display 2 Configuration Register (ADC_DISP2_CONF) ................... 45-184
ADC Display 2 Read Acknowledge Pattern Register
(ADC_DISP2_RD_AP)............................................................................. 45-185
ADC Display 2 Read Mask Register (ADC_DISP2_RDM) ......................... 45-186
ADC Displays Vertical Synchronization Register
(ADC_DISP_VSYNC).............................................................................. 45-187
DI Registers ....................................................................................................... 45-189
DI Display Interface Configuration Register (DI_DISP_IF_CONF)............ 45-189
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
Title
44.3.3.8.2
44.3.3.8.3
44.3.3.8.4
44.3.3.8.5
44.3.3.8.6
Page
Number
DI Display Signals Polarity Register (DI_DISP_SIG_POL) ........................ 45-192
DI Serial Display 1 Configuration Register (DI_SER_DISP1_CONF) ........ 45-195
DI Serial Display 2 Configuration Register (DI_SER_DISP2_CONF) ........ 45-197
DI HSP_CLK Period Register (DI_HSP_CLK_PER) .................................. 45-199
DI Display 0 Time Configuration Register 1
(DI_DISP0_TIME_CONF_1) ................................................................... 45-200
DI Display 0 Time Configuration Register 2
(DI_DISP0_TIME_CONF_2) ................................................................... 45-202
DI Display 0 Time Configuration Register 3
(DI_DISP0_TIME_CONF_3) ................................................................... 45-203
DI Display 1 Time Configuration Register 1
(DI_DISP1_TIME_CONF_1) ................................................................... 45-205
DI Display 1 Time Configuration Register 2
(DI_DISP1_TIME_CONF_2) ................................................................... 45-206
DI Display 1 Time Configuration Register 3
(DI_DISP1_TIME_CONF_3) ................................................................... 45-208
DI Display 2 Time Configuration Register 1
(DI_DISP2_TIME_CONF_1) ................................................................... 45-209
DI Display 2 Time Configuration Register 2
(DI_DISP2_TIME_CONF_2) ................................................................... 45-210
DI Display 2 Time Configuration Register 3
(DI_DISP2_TIME_CONF_3) ................................................................... 45-212
DI Display 3 Time Configuration Register (DI_DISP3_TIME_CONF) ...... 45-213
DI Display 0 Data Byte 0 Mapping Register (DI_DISP0_DB0_MAP) ........ 45-215
DI Display 0 Data Byte 1 Mapping Register (DI_DISP0_DB1_MAP) ........ 45-216
DI Display 0 Data Byte 2 Mapping Register (DI_DISP0_DB2_MAP) ........ 45-217
DI Display 0 Command Byte 0 Mapping Register
(DI_DISP0_CB0_MAP)............................................................................ 45-219
DI Display 0 Command Byte 1 Mapping Register
(DI_DISP0_CB1_MAP)............................................................................ 45-220
DI Display 0 Command Byte 2 Mapping Register
(DI_DISP0_CB2_MAP)............................................................................ 45-221
DI Display 1 Data Byte 0 Mapping Register (DI_DISP1_DB0_MAP) ........ 45-222
DI Display 1 Data Byte 1 Mapping Register (DI_DISP1_DB1_MAP) ........ 45-224
DI Display 1 Data Byte 2 Mapping Register (DI_DISP1_DB2_MAP) ........ 45-225
DI Display 1 Command Byte 0 Mapping Register
(DI_DISP1_CB0_MAP)............................................................................ 45-226
DI Display 1 Command Byte 1 Mapping Register
(DI_DISP1_CB1_MAP)............................................................................ 45-227
DI Display 1 Command Byte 2 Mapping Register
(DI_DISP1_CB2_MAP)............................................................................ 45-229
44.3.3.8.7
44.3.3.8.8
44.3.3.8.9
44.3.3.8.10
44.3.3.8.11
44.3.3.8.12
44.3.3.8.13
44.3.3.8.14
44.3.3.8.15
44.3.3.8.16
44.3.3.8.17
44.3.3.8.18
44.3.3.8.19
44.3.3.8.20
44.3.3.8.21
44.3.3.8.22
44.3.3.8.23
44.3.3.8.24
44.3.3.8.25
44.3.3.8.26
44.3.3.8.27
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
44.3.3.8.28
44.3.3.8.29
44.3.3.8.30
44.3.3.8.31
44.3.3.8.32
44.3.3.8.33
44.3.3.8.34
44.3.3.8.35
44.3.3.8.36
44.3.3.8.37
44.3.3.8.38
44.3.3.8.39
44.4
44.4.1
44.4.1.1
44.4.1.2
44.4.1.3
44.4.1.4
44.4.1.5
44.4.1.6
44.4.1.7
44.4.1.8
44.4.2
44.4.2.1
44.4.2.2
44.4.2.3
44.4.2.4
44.4.2.5
44.4.3
44.4.3.1
44.4.3.2
44.4.3.2.1
44.4.3.2.2
44.4.3.3
44.4.3.4
44.4.3.5
44.4.4
Page
Number
Title
DI Display 2 Data Byte 0 Mapping Register (DI_DISP2_DB0_MAP) ........ 45-230
DI Display 2 Data Byte 1 Mapping Register (DI_DISP2_DB1_MAP) ........ 45-231
DI Display 2 Data Byte 2 Mapping Register (DI_DISP2_DB2_MAP) ........ 45-232
DI Display 2 Command Byte 0 Mapping Register
(DI_DISP2_CB0_MAP)............................................................................ 45-234
DI Display 2 Command Byte 1 Mapping Register
(DI_DISP2_CB1_MAP)............................................................................ 45-235
DI Display 2 Command Byte 2 Mapping Register
(DI_DISP2_CB2_MAP)............................................................................ 45-236
MDI Display 3 Byte 0 Mapping Register (DI_DISP3_B0_MAP)................ 45-237
DI Display 3 Byte 1 Mapping Register (DI_DISP3_B1_MAP) ................... 45-239
DI Display 3 Byte 2 Mapping Register (DI_DISP3_B2_MAP) ................... 45-240
DI Display Access Cycles Count Register (DI_DISP_ACC_CC) ................ 45-241
DI Display Low Level Access Configuration Register
(DI_DISP_LLA_CONF) ........................................................................... 45-243
DI Display Low Level Access Data Register (DI_DISP_LLA_DATA) ....... 45-245
Functional Description............................................................................................... 45-246
Camera Sensor Interface (CSI) .............................................................................. 45-246
Block Diagram................................................................................................... 45-246
Sensor Image Frame Relations .......................................................................... 45-246
Interface Logic................................................................................................... 45-247
Data Packing Unit.............................................................................................. 45-248
Sensor Interface Control .................................................................................... 45-248
Non-contiguous Memory Buffers Support ........................................................ 45-249
Flash Strobe Generation..................................................................................... 45-249
Interlaced Sensor Format Support ..................................................................... 45-250
Image Converter (IC)............................................................................................. 45-250
Block Diagram................................................................................................... 45-250
Processing tasks ................................................................................................. 45-251
Downsizing Section ........................................................................................... 45-252
Main Processing Section.................................................................................... 45-253
Rotation Section................................................................................................. 45-256
Post-Filter (PF) ...................................................................................................... 45-257
Block Diagram................................................................................................... 45-257
Filter Algorithms ............................................................................................... 45-258
MPEG-4 Mode .............................................................................................. 45-261
H.264 Mode ................................................................................................... 45-266
Mode Decision Unit........................................................................................... 45-273
Filter Arithmetic Unit ........................................................................................ 45-273
Postfilter Flow Control ...................................................................................... 45-273
Synchronous Display Controller (SDC) ................................................................ 45-273
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
44.4.4.1
44.4.4.2
44.4.4.3
44.4.4.4
44.4.4.5
44.4.4.6
44.4.5
44.4.5.1
44.4.5.2
44.4.5.3
44.4.5.4
44.4.5.5
44.4.5.6
44.4.5.7
44.4.5.8
44.4.5.8.1
44.4.5.8.2
44.4.5.8.3
44.4.5.8.4
44.4.5.8.5
44.4.5.8.6
44.4.5.9
44.4.5.10
44.4.5.10.1
44.4.5.10.2
44.4.5.11
44.4.6
44.4.6.1
44.4.6.2
44.4.6.2.1
44.4.6.2.2
44.4.6.2.3
44.4.6.3
44.4.6.4
44.4.6.5
44.4.6.6
44.4.7
44.4.7.1
44.4.7.2
44.4.7.3
44.4.7.4
Title
Page
Number
Block Diagram................................................................................................... 45-273
Input Data Formats ............................................................................................ 45-274
Displayed Planes................................................................................................ 45-275
Combining Unit ................................................................................................. 45-276
Cursor Generator ............................................................................................... 45-276
Display Refresh Rate ......................................................................................... 45-276
Asynchronous Display Controller (ADC) ............................................................. 45-277
Block Diagram................................................................................................... 45-277
Display Access Modes....................................................................................... 45-278
Control Sequence Generation Modes ................................................................ 45-290
Byte Enable Support .......................................................................................... 45-291
Windows Displayed on a Smart Display ........................................................... 45-292
AHB Slave Interface.......................................................................................... 45-293
Asynchronous Display Buffer Memory............................................................. 45-293
Access Control................................................................................................... 45-294
Access Priorities ............................................................................................ 45-294
Tearing Elimination ....................................................................................... 45-294
Snooping ........................................................................................................ 45-294
Automatic Window Refresh .......................................................................... 45-295
Sequential Addressing Access....................................................................... 45-295
MCU Direct Access to Display/Graphic Accelerator Memory..................... 45-295
Data and Command Combiner .......................................................................... 45-296
Template Command Generator.......................................................................... 45-296
Template Functions and Structure ................................................................. 45-296
Format of Template Commands .................................................................... 45-297
Asynchronous Display Adapter ......................................................................... 45-302
Display Interface (DI)............................................................................................ 45-302
Block Diagram................................................................................................... 45-302
Supported Display Interface Types.................................................................... 45-302
Synchronous Interfaces.................................................................................. 45-302
Asynchronous Parallel Interfaces .................................................................. 45-303
Asynchronous Serial Interfaces ..................................................................... 45-303
Display Access Priorities................................................................................... 45-304
Bus Mapping Unit.............................................................................................. 45-305
Timing Control .................................................................................................. 45-308
Bus Controls Converter ..................................................................................... 45-308
Image DMA Controller (IDMAC)......................................................................... 45-309
Block Diagram................................................................................................... 45-309
DMA channels ................................................................................................... 45-309
Address Calculation........................................................................................... 45-311
Format Converter............................................................................................... 45-312
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
44.4.7.5
44.4.7.6
44.4.7.7
44.4.8
44.4.8.1
44.4.8.2
44.4.8.2.1
44.4.8.2.2
44.4.8.2.3
44.4.8.3
44.4.8.4
44.4.8.5
44.4.8.6
44.5
44.5.1
44.5.2
44.5.3
44.5.4
44.5.5
44.5.6
44.5.7
44.5.7.1
44.5.7.2
44.5.7.3
44.5.7.4
44.5.7.5
44.5.7.6
44.5.7.7
44.5.7.8
44.5.8
44.5.9
44.5.10
44.5.11
44.5.12
44.5.13
44.5.14
44.5.15
44.5.16
44.5.17
44.6
44.6.1
Page
Number
Title
Internal Bus Interface ........................................................................................ 45-315
Dual Port FIFOs................................................................................................. 45-316
AHB Master Interface........................................................................................ 45-316
Control Module (CM)............................................................................................ 45-316
Block Diagram................................................................................................... 45-316
Frame Synchronization Unit.............................................................................. 45-317
General Description....................................................................................... 45-317
Frame Synchronization Flow......................................................................... 45-334
Frame Synchronization Example................................................................... 45-335
Interrupt Generator (IG) .................................................................................... 45-339
Debug Unit......................................................................................................... 45-344
General Configuration Registers ....................................................................... 45-345
Smart BIST ........................................................................................................ 45-345
Initialization/Application Information ....................................................................... 45-345
IPU Management Flow.......................................................................................... 45-346
System Configuration ............................................................................................ 45-347
Configuring Common Parameters ......................................................................... 45-347
Configuring Sensor Interface................................................................................. 45-347
Configuring Display Interface ............................................................................... 45-347
Tasks Configuration and Initialization................................................................... 45-348
Configuring and Initializing Submodules.............................................................. 45-348
CSI Configuring................................................................................................. 45-348
IC Configuring................................................................................................... 45-348
PF Configuring .................................................................................................. 45-348
ADC Configuring .............................................................................................. 45-349
SDC Configuring ............................................................................................... 45-349
DI Configuring................................................................................................... 45-349
IDMAC Configuring ......................................................................................... 45-349
CM Configuring................................................................................................. 45-349
Initializing Sensors ................................................................................................ 45-350
Initializing Displays............................................................................................... 45-350
Normal Operation .................................................................................................. 45-350
Enabling Tasks ....................................................................................................... 45-350
Resuming Tasks ..................................................................................................... 45-351
Reconfiguring and Resuming Tasks ...................................................................... 45-351
Disabling Tasks...................................................................................................... 45-351
Disabling Sensors .................................................................................................. 45-351
Disabling Displays................................................................................................. 45-352
Disabling Submodules ........................................................................................... 45-352
Internal Memories Mapping ...................................................................................... 45-352
IC Memories .......................................................................................................... 45-352
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Contents
Paragraph
Number
44.6.1.1
44.6.1.2
44.6.1.3
44.6.1.4
44.6.1.5
44.6.1.6
44.6.2
44.6.2.1
44.6.2.2
44.6.3
44.6.4
44.6.4.1
44.6.4.2
44.6.5
44.6.5.1
44.6.5.2
44.6.5.3
44.6.5.4
Title
Page
Number
Input Buffer Memory......................................................................................... 45-352
Downsizing Temporary Memory....................................................................... 45-356
Downsizing Output Memory ............................................................................. 45-356
Task Parameter Memory Mapping .................................................................... 45-357
Main Processing Memory.................................................................................. 45-358
Rotation Memory............................................................................................... 45-360
Post Filter (PF) Memories...................................................................................... 45-361
Memory for MPEG-4 ........................................................................................ 45-361
Memory for H264 .............................................................................................. 45-362
Synchronous Display Controller (SDC) Memories ............................................... 45-363
Asynchronous Display Controller (ADC) Memories ............................................ 45-364
Buffer Memory .................................................................................................. 45-364
Template Memory.............................................................................................. 45-368
Image DMA Controller (IDMAC) Memories ....................................................... 45-369
IDMAC Channel Parameter Memory................................................................ 45-369
IDMAC Y Dual-Port FIFO................................................................................ 45-370
IDMAC U/V Dual-Port FIFO............................................................................ 45-370
IDCMA Decoding Look-Up Table Memory ..................................................... 45-371
Chapter 45
Synchronous Serial Interface (SSI)
45.1
45.1.1
45.1.2
45.1.2.1
45.1.2.1.1
45.1.2.1.2
45.1.2.2
45.1.2.2.1
45.1.2.2.2
45.1.2.3
45.1.2.4
45.1.2.5
45.1.2.5.1
45.1.2.5.2
45.1.2.6
45.1.2.7
45.2
45.3
45.3.1
Overview........................................................................................................................ 46-2
Features...................................................................................................................... 46-3
Modes of Operation ................................................................................................... 46-3
Normal Mode......................................................................................................... 46-5
Normal Mode Transmit ..................................................................................... 46-5
Normal Mode Receive....................................................................................... 46-6
Network Mode ....................................................................................................... 46-8
Network Mode Transmit.................................................................................... 46-9
Network Mode Receive ................................................................................... 46-10
Gated Clock Mode............................................................................................... 46-13
I2S Mode.............................................................................................................. 46-14
AC97 Mode ......................................................................................................... 46-16
AC97 Fixed Mode (SACNT[1]=0).................................................................. 46-18
AC97 Variable Mode (SACNT[1]=1) ............................................................. 46-18
External Frame and Clock Operation .................................................................. 46-18
Data Alignment Formats Supported .................................................................... 46-18
External Signal Description ......................................................................................... 46-20
Memory Map and Register Definition......................................................................... 46-20
SSI Memory Map..................................................................................................... 46-20
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Number
45.3.2
45.3.3
45.3.3.1
45.3.3.2
45.3.3.3
45.3.3.4
45.3.3.5
45.3.3.6
45.3.3.7
45.3.3.8
45.3.3.9
45.3.3.10
45.3.3.11
45.3.3.12
45.3.3.13
45.3.3.14
45.3.3.15
45.3.3.16
45.3.3.17
45.3.3.18
45.3.3.19
45.4
45.4.1
45.4.2
45.4.2.1
45.4.2.2
45.4.3
45.4.4
45.4.5
45.4.5.1
45.4.5.2
45.4.5.3
45.5
Page
Number
Title
Register Summary.................................................................................................... 46-21
Register Descriptions............................................................................................... 46-25
SSI Transmit Data Registers 0 and 1 (STX0/1)................................................... 46-25
SSI Transmit FIFO 0 and FIF0 1 Registers ......................................................... 46-27
SSI Transmit Shift Register (TXSR) ................................................................... 46-27
SSI Receive Data Registers 0 and 1 (SRX0/1).................................................... 46-29
SSI Receive FIFO 0 and FIFO 1 Registers.......................................................... 46-30
SSI Receive Shift Register (RXSR) .................................................................... 46-30
SSI Control Register (SCR)................................................................................. 46-32
SSI Interrupt Status Register (SISR) ................................................................... 46-34
SSI Interrupt Enable Register (SIER).................................................................. 46-38
SSI Transmit Configuration Register (STCR)..................................................... 46-40
SSI Receive Configuration Register (SRCR) ...................................................... 46-42
SSI Transmit and Receive Clock Control Registers (STCCR and SRCCR)....... 46-44
SSI FIFO Control/Status Register (SFCSR)........................................................ 46-47
SSI AC97 Control Register (SACNT)................................................................. 46-50
SSI AC97 Command Address Register (SACADD)........................................... 46-51
SSI AC97 Command Data Register (SACDAT) ................................................. 46-52
SSI AC97 Tag Register (SATAG) ....................................................................... 46-52
SSI Transmit Time Slot Mask Register (STMSK) .............................................. 46-53
SSI Receive Time Slot Mask Register (SRMSK) ............................................... 46-54
Functional Description................................................................................................. 46-55
SSI Architecture....................................................................................................... 46-55
SSI Clocking ............................................................................................................ 46-55
SSI Clock and Frame Sync Generation ............................................................... 46-56
DIV2, PSR, and PM Bit Description ................................................................... 46-57
Receive Interrupt Enable Bit Description................................................................ 46-59
Transmit Interrupt Enable Bit Description .............................................................. 46-60
IP Bus Interface ....................................................................................................... 46-61
Transfer Lengths Supported................................................................................. 46-61
Transfer Bus Errors.............................................................................................. 46-61
Clock Rate ........................................................................................................... 46-61
Initialization/Application Information ......................................................................... 46-61
Chapter 46 Graphics Accelerator (MBX R-S)
46.1
46.2
46.3
46.3.1
46.3.2
About the MBX R-S 3D Graphics Core ........................................................................ 47-1
Features of the MBX R-S 3D Graphics Core ................................................................ 47-2
MBX R-S Functional Description ................................................................................. 47-3
Functional Overview.................................................................................................. 47-3
Memory Map ............................................................................................................. 47-4
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Paragraph
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46.3.2.2
Title
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AHB Slave Interface.............................................................................................. 47-4
GX Port Memory Interface.................................................................................... 47-4
Appendix A
i.MX31/31L Multiplexing and I/O Settings
A.1
A.2
A.2.1
A.2.2
A.2.3
A.2.4
GPIO Mode..................................................................................................................... A-1
I/O Settings Table ......................................................................................................... A-37
Special I/O and Exceptions for SW_PAD_CTL....................................................... A-37
Special I/O and Exceptions for SW_PAD_CTL for IC Rev 2.0............................... A-39
Table Headings ......................................................................................................... A-40
Table Subheadings .................................................................................................... A-41
Appendix B
Revision History
B.1
B.2
Changes From Revision 2.3 to Revision 2.4 ...................................................................B-1
Changes From Revision 0 to Revision 2.3 ......................................................................B-1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
i.MX31 and i.MX31L Simplified Block Diagram .................................................................. 1-3
i.MX31 External Connections Diagram.................................................................................. 1-4
i.MX31 and i.MX31L Detailed Block Diagram ..................................................................... 1-7
Video Processing Chain in the i.MX31 ................................................................................ 1-18
GPU Block Diagram ............................................................................................................. 1-19
Image Processing Unit .......................................................................................................... 1-22
Digital Audio MUX (AUDMUX)......................................................................................... 1-28
i.MX31 and i.MX31L Debug Port Scheme .......................................................................... 1-29
Boot Components.................................................................................................................. 1-30
PLL Reference Clock Switch Unit.......................................................................................... 3-2
Key to Register Fields............................................................................................................. 3-5
Control Register (CCMR) ..................................................................................................... 3-10
Post Divider Register 0 (PDR0)............................................................................................ 3-13
Post Divider Register 1 (PDR1)............................................................................................ 3-14
Reset Control and Source Register (RCSR) ......................................................................... 3-16
MCU PLL Control Register (MPCTL) ................................................................................. 3-17
USB PLL Control Register—UPCTL................................................................................... 3-19
SR PLL Control Register (SPCTL) ...................................................................................... 3-21
Clock Out Source Register (COSR)...................................................................................... 3-23
Clock Gating Registers (CGR0–CGR2) ............................................................................... 3-24
Wake-up Interrupt Mask Register 0 (WIMR0) ..................................................................... 3-27
Latch Divergence Counter Register (LDC) .......................................................................... 3-28
DPTC Comparator Value Register 0:3 (DCVR0:3) .............................................................. 3-28
Load Tracking Register—LTR0............................................................................................ 3-29
Load Tracking Register (LTR1) ............................................................................................ 3-30
Load Tracking Register (LTR2) ............................................................................................ 3-31
Load Tracking Register—LTR3............................................................................................ 3-32
Load Tracking Register—LTBR0 ......................................................................................... 3-33
Load Tracking Register (LTBR1) ......................................................................................... 3-34
Power Management Control Register 0 (PMCR0) ............................................................... 3-35
Power Management Control Register 1 (PMCR1) ............................................................... 3-38
Post Divider Register 2 (PDR2)............................................................................................ 3-39
i.MX31 Clock Generation Scheme ....................................................................................... 3-41
MCU Clock Switch Unit....................................................................................................... 3-42
ckil_mcu_sync_ipg Clock Generation .................................................................................. 3-43
USB Clock Switch Unit ........................................................................................................ 3-44
SR Clock Switch Unit ........................................................................................................... 3-46
Well-Bias Activating and Deactivating and ARM Core Power Gating................................ 3-50
L2 Cache Power Gating ........................................................................................................ 3-50
Low Power Modes State Machine ........................................................................................ 3-51
Frequency/Voltage Switching Procedure .............................................................................. 3-53
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Title
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DVFS State Machine............................................................................................................. 3-54
DVFS Load Tracking Module Block Diagram ..................................................................... 3-56
DPTC Block Diagram ........................................................................................................... 3-57
FSM Control Loop ................................................................................................................ 3-62
FSM Control Signals Waveforms ......................................................................................... 3-63
DVFS—DPTC Synchronization ........................................................................................... 3-64
“Stuck-At Fault” (SAF) mode Launch and Capture Timing Diagram.................................. 3-67
Transition Mode Launch and Capture Timing Diagram ....................................................... 3-68
Transition Last Shift Mode Launch and Capture Timing Diagram ...................................... 3-69
Watchdog Software Reset Diagram ...................................................................................... 3-71
Watchdog Timeout Event Reset Diagram ............................................................................. 3-72
I/O Signal Multiplexing Block Diagram................................................................................. 4-2
IOMUXC Registers................................................................................................................. 4-3
Key to Register Fields............................................................................................................. 4-4
General Purpose Register (GPR) ............................................................................................ 4-6
SW_MUX_CTL Register ..................................................................................................... 4-10
Register Description sw_mux_ctl_cspi3_miso_cspi3_sclk_cspi3_spi_rdy_ttm_pad .......... 4-12
Register Description sw_mux_ctl_ata_reset_b_ce_control_clkss_cspi3_mosi.................... 4-12
Register Description sw_mux_ctl_ata_cs1_ata_dior_ata_diow_ata_dmack ........................ 4-12
Register Description sw_mux_ctl_sd1_data1_sd1_data2_sd1_data3_ata_cs0 .................... 4-13
Register Description sw_mux_ctl_d3_spl_sd1_cmd_sd1_clk_sd1_data0 ........................... 4-13
Register Description sw_mux_ctl_vsync3_contrast_d3_rev_d3_cls.................................... 4-13
Register Description sw_mux_ctl_ser_rs_par_rs_write_read .............................................. 4-14
Register Description sw_mux_ctl_sd_d_io_sd_d_clk_lcs0_lcs1 ......................................... 4-14
Register Description sw_mux_ctl_hsync_fpshift_drdy0_sd_d_i ......................................... 4-14
Register Description sw_mux_ctl_ld15_ld16_ld17_vsync0 ................................................ 4-15
Register Description sw_mux_ctl_ld11_ld12_ld13_ld14..................................................... 4-15
Register Description sw_mux_ctl_ld7_ld8_ld9_ld10........................................................... 4-15
Register Description sw_mux_ctl_ld3_ld4_ld5_ld6............................................................. 4-16
Register Description sw_mux_ctl_usbh2_data1_ld0_ld1_ld2.............................................. 4-16
Register Description sw_mux_ctl_usbh2_dir_usbh2_stp_usbh2_nxt_usbh2_data0 ............ 4-16
Register Description sw_mux_ctl_usbotg_data5_usbotg_data6_usbotg_
data7_usbh2_clk............................................................................................................... 4-17
Register Description sw_mux_ctl_usbotg_data1_usbotg_data2_usbotg_data3_
usbotg_data4..................................................................................................................... 4-17
Register Description sw_mux_ctl_usbotg_dir_usbotg_stp_usbotg_nxt_usbotg_data0........ 4-17
Register Description sw_mux_ctl_usb_pwr_usb_oc_usb_byp_usbotg_clk......................... 4-18
Register Description sw_mux_ctl_tdo_trstb_de_b_sjc_mod................................................ 4-18
Register Description sw_mux_ctl_rtck_tck_tms_tdi ............................................................ 4-18
Register Description sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 ...................... 4-19
Register Description sw_mux_ctl_key_col0_key_col1_key_col2_key_col3 ...................... 4-19
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
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Figures
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Title
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Register Description sw_mux_ctl_key_row4_key_row5_key_row6_key_row7 ................. 4-19
Register Description sw_mux_ctl_key_row0_key_row1_key_row2_key_row3 ................. 4-20
Register Description sw_mux_ctl_txd2_rts2_cts2_batt_line................................................ 4-20
Register Description sw_mux_ctl_ri_dte1_dcd_dte1_dtr_dce2_rxd2.................................. 4-20
Register Description sw_mux_ctl_ri_dce1_dcd_dce1_dtr_dte1_dsr_dte1........................... 4-21
Register Description sw_mux_ctl_rts1_cts1_dtr_dce1_dsr_dce1 ........................................ 4-21
Register Description sw_mux_ctl_cspi2_sclk_cspi2_spi_rdy_rxd1_txd1 ........................... 4-21
Register Description sw_mux_ctl_cspi2_miso_cspi2_ss0_cspi2_ss1_cspi2_ss2 ................ 4-22
Register Description sw_mux_ctl_cspi1_ss2_cspi1_sclk_cspi1_spi_rdy_cspi2_mosi ........ 4-22
Register Description sw_mux_ctl_cspi1_mosi_cspi1_miso_cspi1_ss0_cspi1_ss1.............. 4-22
Register Description sw_mux_ctl_stxd6_srxd6_sck6_sfs6.................................................. 4-23
Register Description sw_mux_ctl_stxd5_srxd5_sck5_sfs5.................................................. 4-23
Register Description sw_mux_ctl_stxd4_srxd4_sck4_sfs4.................................................. 4-23
Register Description sw_mux_ctl_stxd3_srxd3_sck3_sfs3.................................................. 4-24
Register Description sw_mux_ctl_csi_hsync_csi_pixclk_i2c_clk_i2c_dat ......................... 4-24
Register Description sw_mux_ctl_csi_d14_csi_d15_csi_mclk_csi_vsync .......................... 4-24
Register Description sw_mux_ctl_csi_d10_csi_d11_csi_d12_csi_d13................................ 4-25
Register Description sw_mux_ctl_csi_d6_csi_d7_csi_d8_csi_d9 ....................................... 4-25
Register Description sw_mux_ctl_m_request_m_grant_csi_d4_csi_d5 .............................. 4-25
Register Description sw_mux_ctl_pc_rst_iois16_pc_rw_b_pc_poe .................................... 4-26
Register Description sw_mux_ctl_pc_vs1_pc_vs2_pc_bvd1_pc_bvd2 ............................... 4-26
Register Description sw_mux_ctl_pc_cd2_b_pc_wait_b_pc_ready_pc_pwron .................. 4-26
Register Description sw_mux_ctl_d2_d1_d0_pc_cd1_b...................................................... 4-27
Register Description sw_mux_ctl_d6_d5_d4_d3 ................................................................. 4-27
Register Description sw_mux_ctl_d10_d9_d8_d7 ............................................................... 4-27
Register Description sw_mux_ctl_d14_d13_d12_d11 ......................................................... 4-28
Register Description sw_mux_ctl_nfwp_b_nfce_b_nfrb_d15 ............................................. 4-28
Register Description sw_mux_ctl_nfwe_b_nfre_b_nfale_nfcle........................................... 4-28
Register Description sw_mux_ctl_sdqs0_sdqs1_sdqs2_sdqs3............................................. 4-29
Register Description sw_mux_ctl_sdcke0_sdcke1_sdclk_sdclk_b ...................................... 4-29
Register Description sw_mux_ctl_rw_ras_cas_sdwe ........................................................... 4-29
Register Description sw_mux_ctl_cs5_ecb_lba_bclk .......................................................... 4-30
Register Description sw_mux_ctl_cs1_cs2_cs3_cs4............................................................ 4-30
Register Description sw_mux_ctl_eb0_eb1_oe_cs0 ............................................................ 4-30
Register Description sw_mux_ctl_dqm0_dqm1_dqm2_dqm3............................................. 4-31
Register Description sw_mux_ctl_sd28_sd29_sd30_sd31 ................................................... 4-31
Register Description sw_mux_ctl_sd24_sd25_sd26_sd27 ................................................... 4-31
Register Description sw_mux_ctl_sd20_sd21_sd22_sd23 ................................................... 4-32
Register Description sw_mux_ctl_sd16_sd17_sd18_sd19 ................................................... 4-32
Register Description sw_mux_ctl_sd12_sd13_sd14_sd15 ................................................... 4-32
Register Description sw_mux_ctl_sd8_sd9_sd10_sd11 ....................................................... 4-33
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
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Register Description sw_mux_ctl_sd4_sd5_sd6_sd7 ........................................................... 4-33
Register Description sw_mux_ctl_sd0_sd1_sd2_sd3 ........................................................... 4-33
Register Description sw_mux_ctl_a24_a25_sdba1_sdba0 ................................................... 4-34
Register Description sw_mux_ctl_a20_a21_a22_a23 .......................................................... 4-34
Register Description sw_mux_ctl_a16_a17_a18_a19 .......................................................... 4-34
Register Description sw_mux_ctl_a12_a13_a14_a15 .......................................................... 4-35
Register Description sw_mux_ctl_a9_a10_ma10_a11 ......................................................... 4-35
Register Description sw_mux_ctl_a5_a6_a7_a8 .................................................................. 4-35
Register Description sw_mux_ctl_a1_a2_a3_a4 .................................................................. 4-36
Register Description sw_mux_ctl_dvfs1_vpg0_vpg1_a0 .................................................... 4-36
Register Description sw_mux_ctl_ckil_power_fail_vstby_dvfs0 ........................................ 4-36
Register Description sw_mux_ctl_boot_mode1_boot_mode2_boot_mode3_
boot_mode4...................................................................................................................... 4-37
Register Description sw_mux_ctl_reset_in_b_por_b_clko_boot_mode0 ............................ 4-37
Register Description sw_mux_ctl_stx0_srx0_simpd0_ckih ................................................. 4-37
Register Description sw_mux_ctl_gpio3_1_sclk0_srst0_sven0........................................... 4-38
Register Description sw_mux_ctl_gpio1_4_gpio1_5_gpio1_6_gpio3_0............................. 4-38
Register Description sw_mux_ctl_gpio1_0_gpio1_1_gpio1_2_gpio1_3............................. 4-38
Register Description sw_mux_ctl_capture_compare_watchdog_rst_pwmo ........................ 4-39
SW_PAD_CTL ..................................................................................................................... 4-42
Register Description sw_pad_ctl_ttm_pad__x__x ............................................................... 4-43
Register Description sw_pad_ctl_cspi3_miso_cspi3_sclk_cspi3_spi_rdy........................... 4-44
Register Description sw_pad_ctl_ce_control_clkss_cspi3_mosi ......................................... 4-44
Register Description sw_pad_ctl_ata_diow_ata_dmack_ata_reset_b .................................. 4-44
Register Description sw_pad_ctl_ata_cs0_ata_cs1_ata_dior ............................................... 4-45
Register Description sw_pad_ctl_sd1_data1_sd1_data2_sd1_data3.................................... 4-45
Register Description sw_pad_ctl_sd1_cmd_sd1_clk_sd1_data0 ......................................... 4-45
Register Description sw_pad_ctl_d3_rev_d3_cls_d3_spl .................................................... 4-46
Register Description sw_pad_ctl_read_vsync3_contrast...................................................... 4-46
Register Description sw_pad_ctl_ser_rs_par_rs_write......................................................... 4-46
Register Description sw_pad_ctl_sd_d_clk_lcs0_lcs1 ......................................................... 4-47
Register Description sw_pad_ctl_drdy0_sd_d_i_sd_d_io.................................................... 4-47
Register Description sw_pad_ctl_vsync0_hsync_fpshift ..................................................... 4-47
Register Description sw_pad_ctl_ld15_ld16_ld17 ............................................................... 4-48
Register Description sw_pad_ctl_ld12_ld13_ld14 ............................................................... 4-48
Register Description sw_pad_ctl_ld9_ld10_ld11 ................................................................. 4-48
Register Description sw_pad_ctl_ld6_ld7_ld8 ..................................................................... 4-49
Register Description sw_pad_ctl_ld3_ld4_ld5 ..................................................................... 4-49
Register Description sw_pad_ctl_ld0_ld1_ld2 ..................................................................... 4-49
Register Description sw_pad_ctl_usbh2_nxt_usbh2_data0_usbh2_data1 ........................... 4-50
Register Description sw_pad_ctl_usbh2_clk_usbh2_dir_usbh2_stp.................................... 4-50
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
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Register Description sw_pad_ctl_usbotg_data5_usbotg_data6_usbotg_data7 .................... 4-50
Register Description sw_pad_ctl_usbotg_data2_usbotg_data3_usbotg_data4 .................... 4-51
Register Description sw_pad_ctl_usbotg_nxt_usbotg_data0_usbotg_data1 ........................ 4-51
Register Description sw_pad_ctl_usbotg_clk_usbotg_dir_usbotg_stp ................................ 4-51
Register Description sw_pad_ctl_usb_pwr_usb_oc_usb_byp.............................................. 4-52
Register Description sw_pad_ctl_trstb_de_b_sjc_mod ........................................................ 4-52
Register Description sw_pad_ctl_tms_tdi_tdo ..................................................................... 4-52
Register Description sw_pad_ctl_key_col7_rtck_tck........................................................... 4-53
Register Description sw_pad_ctl_key_col4_key_col5_key_col6 ........................................ 4-53
Register Description sw_pad_ctl_key_col1_key_col2_key_col3 ........................................ 4-53
Register Description sw_pad_ctl_key_row6_key_row7_key_col0...................................... 4-54
Register Description sw_pad_ctl_key_row3_key_row4_key_row5 .................................... 4-54
Register Description sw_pad_ctl_key_row0_key_row1_key_row2 .................................... 4-54
Register Description sw_pad_ctl_rts2_cts2_batt_line .......................................................... 4-55
Register Description sw_pad_ctl_dtr_dce2_rxd2_txd2 ........................................................ 4-55
Register Description sw_pad_ctl_dsr_dte1_ri_dte1_dcd_dte1............................................. 4-55
Register Description sw_pad_ctl_ri_dce1_dcd_dce1_dtr_dte1............................................ 4-56
Register Description sw_pad_ctl_cts1_dtr_dce1_dsr_dce1.................................................. 4-56
Register Description sw_pad_ctl_rxd1_txd1_rts1 ................................................................ 4-56
Register Description sw_pad_ctl_cspi2_ss2_cspi2_sclk_cspi2_spi_rdy.............................. 4-57
Register Description sw_pad_ctl_cspi2_miso_cspi2_ss0_cspi2_ss1 ................................... 4-57
Register Description sw_pad_ctl_cspi1_sclk_cspi1_spi_rdy_cspi2_mosi ........................... 4-57
Register Description sw_pad_ctl_cspi1_ss0_cspi1_ss1_cspi1_ss2...................................... 4-58
Register Description sw_pad_ctl_sfs6_cspi1_mosi_cspi1_miso.......................................... 4-58
Register Description sw_pad_ctl_stxd6_srxd6_sck6............................................................ 4-58
Register Description sw_pad_ctl_srxd5_sck5_sfs5.............................................................. 4-59
Register Description sw_pad_ctl_sck4_sfs4_stxd5 .............................................................. 4-59
Register Description sw_pad_ctl_sfs3_stxd4_srxd4 ............................................................ 4-59
Register Description sw_pad_ctl_stxd3_srxd3_sck3............................................................ 4-60
Register Description sw_pad_ctl_csi_pixclk_i2c_clk_i2c_dat ............................................ 4-60
Register Description sw_pad_ctl_csi_mclk_csi_vsync_csi_hsync ...................................... 4-60
Register Description sw_pad_ctl_csi_d13_csi_d14_csi_d15 ............................................... 4-61
Register Description sw_pad_ctl_csi_d10_csi_d11_csi_d12 ............................................... 4-61
Register Description sw_pad_ctl_csi_d7_csi_d8_csi_d9 ..................................................... 4-61
Register Description sw_pad_ctl_csi_d4_csi_d5_csi_d6 ..................................................... 4-62
Register Description sw_pad_ctl_pc_poe_m_request_m_grant ........................................... 4-62
Register Description sw_pad_ctl_pc_rst_iois16_pc_rw_b ................................................... 4-62
Register Description sw_pad_ctl_pc_vs2_pc_bvd1_pc_bvd2.............................................. 4-63
Register Description sw_pad_ctl_pc_ready_pc_pwron_pc_vs1 .......................................... 4-63
Register Description sw_pad_ctl_pc_cd1_b_pc_cd2_b_pc_wait_b..................................... 4-63
Register Description sw_pad_ctl_d2_d1_d0 ........................................................................ 4-64
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
lxxiii
Figures
Figure
Number
4-151
4-152
4-153
4-154
4-155
4-156
4-157
4-158
4-159
4-160
4-161
4-162
4-163
4-164
4-165
4-166
4-167
4-168
4-169
4-170
4-171
4-172
4-173
4-174
4-175
4-176
4-177
4-178
4-179
4-180
4-181
4-182
4-183
4-184
4-185
4-186
4-187
4-188
4-189
4-190
4-191
Title
Page
Number
Register Description sw_pad_ctl_d5_d4_d3 ........................................................................ 4-64
Register Description sw_pad_ctl_d8_d7_d6 ........................................................................ 4-64
Register Description sw_pad_ctl_d11_d10_d9..................................................................... 4-65
Register Description sw_pad_ctl_d14_d13_d12 .................................................................. 4-65
Register Description sw_pad_ctl_nfce_b_nfrb_d15 ............................................................. 4-65
Register Description sw_pad_ctl_nfale_nfcle_nfwp_b ........................................................ 4-66
Register Description sw_pad_ctl_sdqs3_nfwe_b_nfre_b ..................................................... 4-66
Register Description sw_pad_ctl_sdqs0_sdqs1_sdqs2 ......................................................... 4-66
Register Description sw_pad_ctl_sdcke1_sdclk_sdclk_b .................................................... 4-67
Register Description sw_pad_ctl_cas_sdwe_sdcke0 ............................................................ 4-67
Register Description sw_pad_ctl_bclk_rw_ras..................................................................... 4-67
Register Description sw_pad_ctl_cs5_ecb_lba..................................................................... 4-68
Register Description sw_pad_ctl_cs2_cs3_cs4 .................................................................... 4-68
Register Description sw_pad_ctl_oe_cs0_cs1 ...................................................................... 4-68
Register Description sw_pad_ctl_dqm3_eb0_eb1................................................................ 4-69
Register description sw_pad_ctl_dqm0_dqm1_dqm2 .......................................................... 4-69
Register Description sw_pad_ctl_sd29_sd30_sd31.............................................................. 4-69
Register Description sw_pad_ctl_sd26_sd27_sd28.............................................................. 4-70
Register Description sw_pad_ctl_sd23_sd24_sd25.............................................................. 4-70
Register Description sw_pad_ctl_sd20_sd21_sd22.............................................................. 4-70
Register Description sw_pad_ctl_sd17_sd18_sd19.............................................................. 4-71
Register Description sw_pad_ctl_sd14_sd15_sd16.............................................................. 4-71
Register Description sw_pad_ctl_sd11_sd12_sd13 .............................................................. 4-71
Register Description sw_pad_ctl_sd8_sd9_sd10.................................................................. 4-72
Register Description sw_pad_ctl_sd5_sd6_sd7.................................................................... 4-72
Register Description sw_pad_ctl_sd2_sd3_sd4.................................................................... 4-72
Register Description sw_pad_ctl_sdba0_sd0_sd1 ................................................................ 4-73
Register Description sw_pad_ctl_a24_a25_sdba1................................................................ 4-73
Register Description sw_pad_ctl_a21_a22_a23 ................................................................... 4-73
Register Description sw_pad_ctl_a18_a19_a20 ................................................................... 4-74
Register Description sw_pad_ctl_a15_a16_a17 ................................................................... 4-74
Register Description sw_pad_ctl_a12_a13_a14 ................................................................... 4-74
Register Description sw_pad_ctl_a10_ma10_a11 ................................................................ 4-75
Register Description sw_pad_ctl_a7_a8_a9 ......................................................................... 4-75
Register Description sw_pad_ctl_a4_a5_a6 ......................................................................... 4-75
Register Description sw_pad_ctl_a1_a2_a3 ......................................................................... 4-76
Register Description sw_pad_ctl_vpg0_vpg1_a0................................................................. 4-76
Register Description sw_pad_ctl_vstby_dvfs0_dvfs1 .......................................................... 4-76
Register Description sw_pad_ctl_boot_mode4_ckil_power_fail ......................................... 4-77
Register Description sw_pad_ctl_boot_mode1_boot_mode2_boot_mode3 ........................ 4-77
Register Description sw_pad_ctl_por_b_clko_boot_mode0 ................................................ 4-77
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
lxxiv
Freescale Semiconductor
Figures
Figure
Number
4-192
4-193
4-194
4-195
4-196
4-197
4-198
4-199
4-200
4-201
4-202
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
7-1
7-2
7-3
7-4
Title
Page
Number
Register Description sw_pad_ctl_simpd0_ckih_reset_in_b ................................................. 4-78
Register Description sw_pad_ctl_sven0_stx0_srx0.............................................................. 4-78
Register Description sw_pad_ctl_gpio3_1_sclk0_srst0 ....................................................... 4-78
Register Description sw_pad_ctl_gpio1_5_gpio1_6_gpio3_0 ............................................. 4-79
Register Description sw_pad_ctl_gpio1_2_gpio1_3_gpio1_4 ............................................. 4-79
Register Description sw_pad_ctl_pwmo_gpio1_0_gpio1_1 ................................................ 4-79
Register Description sw_pad_ctl_capture_compare_watchdog_rst ..................................... 4-80
Software Controllable Signals Register 0 ............................................................................. 4-80
Software Controllable Signals Register 1 ............................................................................. 4-81
Software Controllable Signals Register 2 ............................................................................. 4-81
Software Controllable Signals Register 3 ............................................................................. 4-83
GPIO Block Diagram.............................................................................................................. 5-1
SoC IOMUX Scheme ............................................................................................................. 5-2
Key to Register Fields............................................................................................................. 5-4
GPIO Data Register (DR) ....................................................................................................... 5-7
GPIO Direction Register (GDIR) ........................................................................................... 5-8
GPIO Pad Status Register (PSR)............................................................................................. 5-9
GPIO Interrupt Configuration Register1 (ICR1) .................................................................... 5-9
GPIO Interrupt Configuration Register2 (ICR2) .................................................................. 5-10
GPIO Interrupt Mask Register (IMR) ................................................................................... 5-11
GPIO Interrupt Status Register (ISR) ................................................................................... 5-12
i.MX31 and i.MX31L Debug Port Scheme ............................................................................ 6-2
ARM11 Platform Debug Features (Highlighted in Blue) ....................................................... 6-4
1:2 Port Mode.......................................................................................................................... 6-8
1:4 Port Mode.......................................................................................................................... 6-8
ECT Block Diagram.............................................................................................................. 6-13
CTI Block Diagram............................................................................................................... 6-14
CTM Logic Bit Diagram....................................................................................................... 6-16
CTM Detailed Implementation for Channel 0 ...................................................................... 6-17
ECT in the i.MX31 and i.MX31L......................................................................................... 6-18
CTI-SJC Connectivity........................................................................................................... 6-19
IOMUXC Observability To ECT Loopback Logic............................................................... 6-23
IO Triggers ............................................................................................................................ 6-24
System JTAG Controller Block Diagram ............................................................................. 6-26
The i.MX31 and i.MX31L JTAG Default TAP Daisy Chain................................................ 6-28
SJC Mode Selection Through Pin Sampling......................................................................... 6-29
Bottom Connector/CE Supports............................................................................................ 6-30
Boot Components.................................................................................................................... 7-1
External Boot Endian Mode Logic ......................................................................................... 7-4
SD Boot Flow (including HighCapacity) Starting from MMC/SD Boot Entry Point ............ 7-6
MMC Boot Flow (Including HighCapacity)........................................................................... 7-7
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
lxxv
Figures
Figure
Number
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
10-1
11-1
Title
Page
Number
The ARM1136JF-S Block Diagram........................................................................................ 8-2
Instruction Fetch Interface ...................................................................................................... 8-4
A Simplified ARM11 Symbol ................................................................................................ 8-5
ARM11 Platform Block Diagram ........................................................................................... 8-6
The AVIC Module Connected to the ARM1136................................................................... 8-11
ETM11 Functional Block Diagram....................................................................................... 8-14
ETB11 Functional Block Diagram........................................................................................ 8-15
ECT Functional Block Diagram ........................................................................................... 8-17
AVIC Block Diagram .............................................................................................................. 9-1
Key to Register Fields............................................................................................................. 9-5
INTCNTL Register ............................................................................................................... 9-10
Normal Interrupt Mask Register ........................................................................................... 9-12
Interrupt Enable Number Register ........................................................................................ 9-13
Interrupt Disable Number Register ....................................................................................... 9-14
Interrupt Enable Register High ............................................................................................. 9-15
Interrupt Enable Register Low.............................................................................................. 9-15
Interrupt Type Register High ................................................................................................ 9-16
Interrupt Type Register Low ................................................................................................. 9-16
Normal Interrupt Priority Level 7 Register........................................................................... 9-17
Normal Interrupt Priority Level 6 Register........................................................................... 9-18
Normal Interrupt Priority Level 5 Register........................................................................... 9-18
Normal Interrupt Priority Level 4 Register........................................................................... 9-19
Normal Interrupt Priority Level 4 Register........................................................................... 9-20
Normal Interrupt Priority Level 2 Register........................................................................... 9-21
Normal Interrupt Priority Level 1 Register........................................................................... 9-22
Normal Interrupt Priority Level 0 Register........................................................................... 9-23
Normal Interrupt Vector and Status Register ........................................................................ 9-24
Fast Interrupt Vector and Status Register.............................................................................. 9-25
INTSRCH Register ............................................................................................................... 9-26
INTSRCL Register................................................................................................................ 9-27
INTFRCH Register ............................................................................................................... 9-28
INTFRCL Register................................................................................................................ 9-28
NIPNDH Register ................................................................................................................. 9-29
NIPNDL Register.................................................................................................................. 9-29
FIPNDH Register .................................................................................................................. 9-30
FIPNDL Register .................................................................................................................. 9-30
AVIC Vector Registers .......................................................................................................... 9-31
Normal Interrupt Mechanism................................................................................................ 9-35
Vector Accelerated Normal Interrupt Mechanism ................................................................ 9-36
Security Controller Block Diagram ...................................................................................... 10-1
RNGA Block Diagram.......................................................................................................... 11-1
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
lxxvi
Freescale Semiconductor
Figures
Figure
Number
12-1
12-2
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
15-1
15-2
15-3
15-4
15-5
16-1
16-2
16-3
16-4
16-5
16-6
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
Title
Page
Number
RTIC Block Diagram ............................................................................................................ 12-1
System Diagram .................................................................................................................... 12-2
Tightly Coupled ARM11 and L2CC ..................................................................................... 15-2
Top Level L2CC Architecture............................................................................................... 15-4
CLKENAHB Usage .............................................................................................................. 15-8
L2CC Clock Gating and ipg_stop_ack Function ................................................................ 15-10
ipg_stop_ack Timing Diagrams .......................................................................................... 15-11
Key to Register Fields......................................................................................................... 15-14
ID Register .......................................................................................................................... 15-18
Cache Type Register ........................................................................................................... 15-19
L2CC Control Register 1 .................................................................................................... 15-20
L2CC Control Register ....................................................................................................... 15-21
PA Format ........................................................................................................................... 15-25
Index/Way Format............................................................................................................... 15-25
Format C Format ................................................................................................................. 15-25
Index/Way Format of Test Operation Register, 0xF00 ....................................................... 15-28
Word Order of L2 Cache Lines in Line Data Registers ...................................................... 15-28
Line TAG Register .............................................................................................................. 15-29
L2CC Debug Control Register............................................................................................ 15-30
L2CC Auxiliary Control Register 2 (L2CCAUXCR)......................................................... 15-31
Key to Register Field ............................................................................................................ 16-2
EMMC Register .................................................................................................................... 16-4
EMCS Register ..................................................................................................................... 16-6
EMCCx Registers ................................................................................................................. 16-7
EMCx Registers .................................................................................................................... 16-8
EMI System Block Diagram ................................................................................................. 17-2
PCMCIA Host Adapter Simplified Block Diagram ............................................................. 17-6
NAND Flash Controller Simplified Block Diagram............................................................. 17-7
Enhanced SDR/LPDDR SDRAM Controller Block Diagram.............................................. 17-9
EMI AHB MUX Interface Diagram ................................................................................... 17-11
EMI I/O MUX Interface Diagram ...................................................................................... 17-13
M3IF Block Diagram ............................................................................................................ 18-2
Key to Register Fields........................................................................................................... 18-6
M3IF Control Register ........................................................................................................ 18-10
M3IF Snooping Configuration Register 0 (M3IFSCFG0).................................................. 18-12
M3IF Snooping Configuration Register 1 (M3IFSCFG1).................................................. 18-13
M3IF Snooping Configuration Register 2 (M3IFSCFG2).................................................. 18-14
M3IF Snooping Status Register 0 (M3IFSSR0) ................................................................. 18-15
M3IF Snooping Status Register 1 (M3IFSSR1) ................................................................. 18-16
M3IF Lock General Register (M3IFMLGE) ...................................................................... 18-17
M3IF Integration ................................................................................................................. 18-20
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
lxxvii
Figures
Figure
Number
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
18-16
18-17
18-18
18-19
18-20
18-21
18-22
18-23
18-24
18-25
18-26
18-27
18-28
18-29
18-30
18-31
18-32
18-33
18-34
18-35
18-36
18-37
18-38
18-39
Title
Page
Number
WEIM Block Diagram .......................................................................................................... 19-2
Key to Register Fields......................................................................................................... 19-10
Chip Select x Upper Control Register................................................................................. 19-14
Chip Select x Lower Control Register ................................................................................ 19-18
Chip Select x Addition Control Register ............................................................................ 19-21
WCR Register ..................................................................................................................... 19-24
Read Access, WSC=1 ......................................................................................................... 19-33
Write Access, WSC=1, EBWA=1, EBWN=1, LBN=1....................................................... 19-34
Read and Write Accesses, WSC=2, WWS=2, EBWA=1, EBWN=2.................................. 19-35
Read and Write Accesses, WSC=2, WWS=1, EBWA=1, EBWN=2, EDC=1 ................... 19-36
Read and Write Accesses, WSC=3, CSA=1, CSN=1, LBA=1, LBN=1............................. 19-37
Read Accesses, WSC=2, OEA=2, CNC=2, BCM=1, EBRA=2......................................... 19-38
Read and Write Accesses, WSC=2, OEA=2, EBWA=1, EBWN=2,
CNC=2, EBRA=2 .......................................................................................................... 19-39
Read Access, WSC=1, OEA=1, EBRA=1.......................................................................... 19-40
Write Access, WSC=1, EBWA=1, EBWN=1 ..................................................................... 19-41
Read Access, WSC=3, OEA=2, EBRA=2.......................................................................... 19-42
Write Access, WSC=3, EBWA=1, EBWN=3 ..................................................................... 19-43
Read Access, WSC=3, OEA=4, EBRA=4.......................................................................... 19-44
Write Access, WSC=3, EBWA2, EBWN=3 ....................................................................... 19-45
Read Access, WSC=3, OEN=2, EBRN=2.......................................................................... 19-46
Read Access, WSC=3, OEA=2, OEN=2, EBRA=2, EBRN=2 .......................................... 19-47
Write Access, WSC=2, WWS=1, EBWA=1, EBWN=2 ..................................................... 19-48
Write Access, WSC=1, WWS=2, EBWA=1, EBWN=2 ..................................................... 19-49
Write Access, WSC=2, CSA=1, WWS=1, CSN=1 ............................................................ 19-50
Sequential Read Access, WSC=7, OEA=8, PME=1, SYNC=1, DOL=1, EBRA=8 .......... 19-51
Read Access, WSC=3F, OEA=8, OEN=5, EBRA=8, EBRN=5......................................... 19-52
Sequential Read Accesses, WSC=1, EW=1, DCT=1 ......................................................... 19-53
Sequential Write Accesses, WSC=1, EW=1, RWA=1, RWN=1 ........................................ 19-54
Non-Sequential Read Accesses, WSC=2, SYNC=1, DOL=0 ............................................ 19-55
Sequential Read Access, WSC=7, OEA=8, SYNC=1, DOL=1, BCD=1,
BCS=1, EBRA=8 ........................................................................................................... 19-56
Non-Sequential Read Accesses, WSC=3, SYNC=1, DOL=1 ............................................ 19-57
Increment 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=0 .......................... 19-58
Increment 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=0 .......................... 19-59
Increment 4 AHB Read Access, WSC=3, SYNC=1, DOL=1, WRAP=0, EW=0.............. 19-60
Increment 4 AHB Read Access, WSC=3, SYNC=1, DOL=1, WRAP=0, EW=1.............. 19-61
Increment 4 AHB Read Access, WSC=3, SYNC=1, WRAP=0, EW=1 ............................ 19-62
Increment 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=1, PSZ=0 ............. 19-63
Wrap 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=0.................................. 19-64
Wrap 4 AHB Read Access, WSC=2, SYNC=1, DOL=1, WRAP=1, PSZ=0..................... 19-65
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
lxxviii
Freescale Semiconductor
Figures
Figure
Number
18-40
18-41
18-42
18-43
18-44
18-45
18-46
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
19-25
19-26
19-27
19-28
19-29
19-30
19-31
19-32
19-33
19-34
Title
Page
Number
Write Access, BCD=1, BCS=1, WSC=3, SYNC=1, DOL=1, EW=1, PSR=1................... 19-66
Read Access, BCD=1, BCS=1, WSC=3, SYNC=1, DOL=1, EW=1, PSR=1.................... 19-67
Write Access, BCS=1, WSC=4, SYNC=1, PSR=1 ............................................................ 19-68
Read Access, WSC=7, LBA=1, LBN=1, LAH=1, OEA=7................................................ 19-69
Write Access, WSC=7, LBA=1, LBN=1, LAH=1 ............................................................. 19-70
Read Access, BCD=1, SYNC=1, WCS=4, DOL=1, LBN=2, LAH=1, PSR=1 ................. 19-71
Write Access, BCD=1, SYNC=1, WCS=5, DOL=1, LBN=2, LAH=1, PSR=1 ................ 19-72
Enhanced SDR/LPDDR SDRAM Controller Block Diagram.............................................. 20-2
Key to Register Fields......................................................................................................... 20-11
Data Organization in Memory ............................................................................................ 20-15
Enhanced SDRAM Control Register (ESDCTL0) ............................................................. 20-15
Enhanced SDRAM Control Register (ESDCTL1) ............................................................. 20-16
Enhanced SDRAM Configuration Register 0 (ESDCFG0) ................................................ 20-20
Enhanced SDRAM Configuration Register 1 (ESDCFG1) ................................................ 20-20
tWTRtRP Bit Field Encoding ............................................................................................. 20-24
tRP—Precharge Delay Timing............................................................................................ 20-25
tMRD—SDRAM Load Mode Register to Active Command Timing Diagram ................. 20-26
tWR—WRITE to PRECHARGE Timing Diagram ............................................................ 20-27
tRAS—SDRAM ACTIVE to PRECHARGE Command Timing Diagram........................ 20-27
tRAS—SELF REFRESH Mode Minimum Time Period.................................................... 20-28
tRRD—Alternating Bank Read Access .............................................................................. 20-28
SDR CAS Latency Timing.................................................................................................. 20-29
Mobile LPDDR CAS Latency Timing................................................................................ 20-30
tRCD—Row to Column Delay Timing............................................................................... 20-31
tRC—Row Cycle Timing.................................................................................................... 20-32
tXP—New Command After Power Down Exit (4 Cycles)................................................. 20-33
ESDMISC Miscellaneous Register (ESDMISC) ................................................................ 20-34
MDDR Delay Line 1 Configuration Debug Register ......................................................... 20-35
MDDR Delay Line 2 Configuration Debug Register ......................................................... 20-36
MDDR Delay Line 3 Configuration Debug Register ......................................................... 20-37
MDDR Delay Line 4 Configuration Debug Register ......................................................... 20-38
MDDR Delay Line 5 Configuration Debug Register ......................................................... 20-39
MDDR Delay Line Cycle Length Debug Register ............................................................. 20-40
SDR SDRAM Read Burst Command Sequence Example.................................................. 20-42
LPDDR SDRAM Read Burst Command Sequence Example ............................................ 20-43
SDR SDRAM Optimization Strategies—MIF1 and MIF2 Examples ................................ 20-44
Mobile LPDDR SDRAM Optimization Strategies—MIF1 and MIF2 Examples .............. 20-44
SDR Simple Read after Read Latency Hiding Timing Diagram ........................................ 20-46
Mobile DDR Simple Read after Read Latency Hiding Timing Diagram ........................... 20-46
SDR Miss Write to CSD1 After Read from CSD0 ............................................................. 20-47
Mobile DDR Miss Write to CSD1 After Read from CSD0................................................ 20-47
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
lxxix
Figures
Figure
Number
19-35
19-36
19-37
19-38
19-39
19-40
19-41
19-42
19-43
19-44
19-45
19-46
19-47
19-48
19-49
19-50
19-51
19-52
19-53
19-54
19-55
19-56
19-57
19-58
19-59
19-60
19-61
19-62
19-63
Title
Page
Number
Hardware Refresh Timing Diagram.................................................................................... 20-52
Hardware Refresh with Pending Bus Cycle Timing Diagram ............................................ 20-53
SDRAM/LPDDR Enter Self Refresh Mode During System STOP Mode ......................... 20-55
SDRAM/LPDDR Exit Self Refresh Mode During System STOP Mode ........................... 20-56
Manual Self Refresh Entry Timing Diagram ...................................................................... 20-57
Manual Self Refresh Exit Timing Diagram ........................................................................ 20-58
SDR SDRAM Precharge Power Down Mode Entry Timing Diagram ............................... 20-60
SDR SDRAM Precharge Power Down Mode Exit Timing Diagram ................................. 20-61
Mobile DDR SDRAM Precharge Power Down Mode Entry Timing Diagram.................. 20-62
Mobile DDR SDRAM Precharge Power Down Mode Exit Timing Diagram .................... 20-63
SDR SDRAM Active Power Down Mode Timing Diagram .............................................. 20-64
Mobile DDR SDRAM Active Power Down Mode Timing Diagram ................................. 20-65
Simplified Enhanced SDRAM Controller State Diagram .................................................. 20-68
SDR and LPDDR Off-Page Single Read Timing Diagram (32-Bit Memory
for SDR and 16-Bit for LPDDR) ................................................................................... 20-71
SDR and LPDDR On-Page Single Read Timing Diagram (32-Bit Memory
for SDR, 16-Bit for LPDDR) ......................................................................................... 20-72
SDR and LPDDR Off-Page Burst Read Timing Diagram (32-Bit Memory for SDR or 16-Bit for
LPDDR) ......................................................................................................................... 20-73
AHB 32-Bit Read from a LPDDR: Off-Page Burst Read Timing Diagram (32-Bit) ......... 20-74
AHB 64-Bit Read from a LPDDR: Off-Page Burst Read Timing Diagram (32-Bit) ......... 20-75
SDR and LPDDR On-Page Burst Read Timing Diagram (32-Bit Memory
for SDR and 16-Bit for LPDDR) ................................................................................... 20-76
On-Page Burst Read Timing Diagram (16-Bit Memory for SDR, LPDDR 8-Bit is Not
Supported) ...................................................................................................................... 20-77
Off-Page Burst Read Timing Diagram (16-Bit Memory, LPDDR
8-Bit is Not Supported) .................................................................................................. 20-77
SDR Off-Page Write Followed by On-Page Write Timing Diagram.................................. 20-78
LPDDR Off-Page Write Followed by On-Page Write Timing Diagram ............................ 20-79
Off-Page Burst Write Timing Diagram (32-Bit Memory for SDR and
16-Bit for LPDDR)......................................................................................................... 20-80
AHB 64-Bit Write to LPDDR: Off-Page Burst Write Timing Diagram
(32-Bit Memory) ............................................................................................................ 20-81
AHB 32-Bit Write to LPDDR: Off-Page Burst Write Timing Diagram
(32-Bit Memory) ............................................................................................................ 20-82
On-Page Burst Write Timing Diagram (32-Bit Memory for SDR and
16-Bit for LPDDR)......................................................................................................... 20-83
Off-Page Burst Write Timing Diagram (SDR 16-bit Memory, LPDDR
8-Bit is Not Supported) .................................................................................................. 20-84
On-Page Burst Write Timing Diagram (SDR 16-Bit Memory, LPDDR
8-Bit Memory is Not Supported) ................................................................................... 20-85
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
lxxx
Freescale Semiconductor
Figures
Figure
Number
19-64
19-65
19-66
19-67
19-68
19-69
19-70
19-71
19-72
19-73
19-74
19-75
19-76
19-77
19-78
19-79
19-80
19-81
19-82
19-83
19-84
19-85
19-86
19-87
19-88
19-89
19-90
19-91
19-92
19-93
19-94
19-95
19-96
19-97
19-98
20-1
20-2
20-3
20-4
20-5
20-6
Title
Page
Number
SDR Single Write Followed by On-Page Read Timing Diagram....................................... 20-86
LPDDR Single Write Followed by On-Page Read Timing Diagram ................................. 20-87
SDR Single Read Followed by On-Page Write Timing Diagram....................................... 20-88
LPDDR Single Read Followed by On-Page Write Timing Diagram ................................. 20-89
SDR Burst Read Followed by On-Page Write Timing Diagram ........................................ 20-90
LPDDR Burst Read Followed by On-Page Write Timing Diagram ................................... 20-91
Single on Page Read-Word Access to 16-Bit Memory (Cycle Accurate) .......................... 20-92
Misaligned on Page INCR4 Burst Read Access to 16-Bit Memory ................................... 20-93
Misaligned WRAP8 Burst Read Access to 32-Bit Memory............................................... 20-95
Single on Page Write-Word Access to 32-Bit Memory (Cycle Accurate).......................... 20-96
INCR4 burst on Page Write-Word Access to 32-Bit Memory (Cycle Accurate) ............... 20-97
Precharge Specific Bank Timing Diagram.......................................................................... 20-99
Precharge All Banks Timing Diagram .............................................................................. 20-100
Software Initiated Auto-Refresh Timing Diagram............................................................ 20-101
Set Mode Register State Diagram ..................................................................................... 20-102
SDR and LPDDR Set Mode Register Timing Diagram.................................................... 20-103
SDR SDRAM Initialization and Load Mode Register Sequence ..................................... 20-106
Simplified LPDDR SDRAM Initialization and Load Mode Register Sequence .............. 20-108
128 Mbit SDR SDRAM Mode Register ........................................................................... 20-109
Single 64 Mbit (4M x 16) SDRAM Connection Diagram.................................................20-111
Single 128 Mbit (8M x 16) SDRAM Connection Diagram.............................................. 20-112
Single 256 Mbit (16M x 16) Connection Diagram ........................................................... 20-113
Single 512 Mbit (32M x 16) SDRAM Connection Diagram............................................ 20-114
Single 1-Gbit (64M x 16) SDRAM Connection Diagram ................................................ 20-115
Dual 64 Mbit (4M x 16 x 2) SDRAM Connection Diagram ............................................ 20-116
Dual 128 Mbit (8M x 16 x 2) SDRAM Connection Diagram .......................................... 20-117
Dual 256-Mbit (16M x 16 x 2) SDRAM Connection Diagram ........................................ 20-118
Single 64-Mbit (2Mx32) SDRAM Connection Diagram ................................................. 20-119
Single 128-Mbit (4Mx32) SDRAM Connection Diagram ............................................... 20-120
Single 256-MB (8Mx32) SDRAM Connection Diagram ................................................. 20-121
Single 512-Mbit (16Mx32) SDRAM Connection Diagram ............................................. 20-122
Single 1-Gbit (32Mx32) SDRAM Connection Diagram .................................................. 20-123
Single 2-Gbit (64Mx32) SDRAM Connection Diagram .................................................. 20-124
Single 512-Mbit (16Mx32) LPDDR SDRAM Connection Diagram ............................... 20-125
Single 512-Mbit (32Mx16) LPDDR SDRAM Connection Diagram ............................... 20-126
NAND Flash Controller Block Diagram .............................................................................. 21-2
Warm Reset Operation .......................................................................................................... 21-6
Key to Register Fields......................................................................................................... 21-10
NFC_BUFSIZE Register .................................................................................................... 21-12
RAM Buffer Address Register............................................................................................ 21-13
NAND Flash Address Register ........................................................................................... 21-13
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
lxxxi
Figures
Figure
Number
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
20-21
20-22
20-23
20-24
20-25
20-26
20-27
20-28
20-29
20-30
20-31
20-32
20-33
20-34
20-35
20-36
20-37
20-38
20-39
20-40
20-41
21-1
21-2
21-3
21-4
21-5
21-6
Title
Page
Number
NAND_Flash_CMD Register ............................................................................................. 21-14
NFC_Configuration Register .............................................................................................. 21-14
ECC_Status_Result ............................................................................................................. 21-15
ECC_RSLT_MAIN_AREA Register.................................................................................. 21-15
ECC_RSLT_MAIN_AREA Register.................................................................................. 21-16
ECC_Rslt_Spare_Area Register ......................................................................................... 21-17
ECC_Rslt_Spare_Area Register ......................................................................................... 21-17
NAND Flash Write Protection Register.............................................................................. 21-18
Unlock_Start_Blk_Add Register ........................................................................................ 21-18
UNLOCK_END_BLK_ADD Register............................................................................... 21-19
NAND_FLASH_WR_PR_ST Register .............................................................................. 21-19
NAND_FLASH_CONFIG1 Register ................................................................................. 21-20
NAND_FLASH_CONFIG2 Register ................................................................................. 21-21
Boot Mode Operation.......................................................................................................... 21-24
Read Operation ................................................................................................................... 21-25
Program Operation .............................................................................................................. 21-26
Erase Operation................................................................................................................... 21-26
Flowchart of Preset Operation ............................................................................................ 21-30
Flowchart of NAND Flash Command Input Operation...................................................... 21-31
Flowchart of NAND Flash Address Input Operation ......................................................... 21-32
Flowchart of NAND Flash Data Input Operation ............................................................... 21-33
Flowchart of NAND Flash Data Output Operation ............................................................ 21-34
Flowchart of Read NAND Flash ID Operation .................................................................. 21-35
NAND Flash ID Data Format (x8) ..................................................................................... 21-36
NAND Flash ID Data Format (x16) ................................................................................... 21-36
Flowchart of Read NAND Flash Status Operation ............................................................. 21-37
NAND Flash Status Data Format........................................................................................ 21-38
Flowchart of Read NAND Flash Data Operation ............................................................... 21-39
Flowchart of Program NAND Flash Data Operation.......................................................... 21-40
Flowchart of Erase NAND Flash Operation ....................................................................... 21-41
Flowchart of a Hot Reset Operation ................................................................................... 21-42
State Diagram of RAM Buffer Write Protection................................................................. 21-44
State Diagram of NAND Flash Write Protection................................................................ 21-45
256 Mbit (32 M x 8 Bit) NAND Flash Connection Diagram ............................................. 21-47
256 Mbit (16 M x 16 Bit) NAND Flash Connection Diagram ........................................... 21-48
PCMCIA Controller Interface Block Diagram ..................................................................... 22-2
Key to Register Fields........................................................................................................... 22-7
PCMCIA Input Pins Register (PIPR).................................................................................. 22-10
PCMCIA Status Change Register (PSCR).......................................................................... 22-11
PCMCIA Enable Register (PER) ........................................................................................ 22-13
PCMCIA Base Registers 0–4 (PBR0–PBR4) ..................................................................... 22-15
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
lxxxii
Freescale Semiconductor
Figures
Figure
Number
21-7
21-8
21-9
21-10
21-11
21-12
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
22-10
22-11
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
23-22
23-23
23-24
Title
Page
Number
PCMCIA Option Registers 0–4 (POR0–POR4) ................................................................. 22-16
PCMCIA Offset Registers 0–4 (POFR0–POFR4).............................................................. 22-19
PCMCIA General Control Register (PGCR) ...................................................................... 22-20
PCMCIA General Status Register (PGSR) ......................................................................... 22-21
Write Accesses PSHT=1, PSST =1..................................................................................... 22-28
Read Cycle PSHT=1, PSST =1........................................................................................... 22-29
1-Wire Block Diagram .......................................................................................................... 23-1
1-Wire Connections............................................................................................................... 23-2
Key to Register Fields........................................................................................................... 23-3
Control Register .................................................................................................................... 23-4
Time Divider Register........................................................................................................... 23-5
Time Precision for Reset and Presence, Write0, and Read Pulses........................................ 23-6
Reset Register ....................................................................................................................... 23-7
1-Wire Initialization .............................................................................................................. 23-8
Write 0 Timing ...................................................................................................................... 23-8
Write 1 Timing ...................................................................................................................... 23-9
Read Timing .......................................................................................................................... 23-9
ATA interface Block Diagram............................................................................................... 24-1
PIO Read Mode Timing ........................................................................................................ 24-7
PIO Write Mode Timing ...................................................................................................... 24-8
MDMA Read Timing ............................................................................................................ 24-9
MDMA Write Timing ........................................................................................................... 24-9
UDMA in Transfer Start ..................................................................................................... 24-10
UDMA in Host Terminates Transfer................................................................................... 24-11
UDMA in Device Terminates Transfer ............................................................................... 24-11
UDMA Out Transfer Start................................................................................................... 24-12
UDMA Out Host Terminates Transfer................................................................................ 24-13
UDMA Out Device Terminates Transfer ............................................................................ 24-13
Key to Register Fields......................................................................................................... 24-16
TIME_OFF Register ........................................................................................................... 24-20
TIME_ON Register............................................................................................................. 24-21
TIME_1 Register................................................................................................................. 24-21
TIME_2W Register............................................................................................................. 24-21
TIME_2R Register .............................................................................................................. 24-21
TIME_AX Register............................................................................................................. 24-22
TIME_PIO_RDX Register.................................................................................................. 24-22
TIME_4 Register................................................................................................................. 24-22
TIME_9 Register................................................................................................................. 24-22
TIME_M Register ............................................................................................................... 24-23
TIME_JN Register .............................................................................................................. 24-23
TIME_D Register................................................................................................................ 24-23
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
lxxxiii
Figures
Figure
Number
23-25
23-26
23-27
23-28
23-29
23-30
23-31
23-32
23-33
23-34
23-35
23-36
23-37
23-38
23-39
23-40
23-41
23-42
23-43
23-44
24-1
24-2
24-3
24-4
24-5
24-6
24-7
24-8
24-9
24-10
24-11
24-12
24-13
24-14
24-15
24-16
24-17
24-18
24-19
24-20
24-21
Title
Page
Number
TIME_K Register................................................................................................................ 24-23
TIME_ACK Register .......................................................................................................... 24-24
TIME_ENV Register .......................................................................................................... 24-24
TIME_RPX Register........................................................................................................... 24-24
TIME_ZAH Register .......................................................................................................... 24-24
TIME_MLIX Register ........................................................................................................ 24-25
TIME_DVH Register .......................................................................................................... 24-25
TIME_DZFS Register......................................................................................................... 24-25
TIME_DVS Register........................................................................................................... 24-25
TIME_CVH Register .......................................................................................................... 24-26
TIME_SS Register .............................................................................................................. 24-26
TIME_CYC Register .......................................................................................................... 24-26
FIFO_DATA Register In 16-bit Mode ................................................................................ 24-26
FIFO_DATA Register in 32-Bit Mode................................................................................ 24-27
FIFO_FILL Register ........................................................................................................... 24-27
ATA_CONTROL Register .................................................................................................. 24-28
INTERRUPT_PENDING Register ..................................................................................... 24-29
INTERRUPT_ENABLE Register....................................................................................... 24-30
INTERRUPT_CLEAR Register ......................................................................................... 24-31
FIFO_ALARM Register ..................................................................................................... 24-32
CSPI Block Diagram............................................................................................................. 25-1
Key to Register Fields........................................................................................................... 25-3
RXDATA Register Diagram ................................................................................................. 25-6
TXDATA Register Diagram.................................................................................................. 25-7
CSPI Control Register........................................................................................................... 25-8
Interrupt Control Register Diagram .................................................................................... 25-11
DMA Control Register Diagram......................................................................................... 25-12
Status Register Diagram...................................................................................................... 25-13
Sample Period Control Register Diagram........................................................................... 25-15
Test Control Register Diagram............................................................................................ 25-16
CSPI Generic Timing .......................................................................................................... 25-17
Typical SPI Burst (8-bit transfer)........................................................................................ 25-18
Relationship Between a SPI Burst and the Falling Edge of SPI_RDY .............................. 25-19
Relationship Between a SPI Burst and SPI_RDY .............................................................. 25-19
SPI Bursts with Wait States................................................................................................. 25-20
SPI Burst While SSCTL is Clear ........................................................................................ 25-20
SPI Bursts while SSCTL is Set ........................................................................................... 25-21
SPI Burst with Different POL and PHA Configuration...................................................... 25-22
Increment Data FIFO by SS Rising Edge ........................................................................... 25-23
Program Sequence of SPI Burst Using Interrupt ................................................................ 25-24
Program Sequence of SPI Burst Using DMA ..................................................................... 25-24
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
lxxxiv
Freescale Semiconductor
Figures
Figure
Number
24-22
25-1
25-2
25-3
25-4
25-5
25-6
25-7
25-8
25-9
26-1
26-2
26-3
26-6
26-7
26-8
26-9
26-10
26-11
26-12
26-13
26-14
26-15
27-1
27-2
27-3
27-4
27-5
27-6
27-7
27-8
27-9
27-10
27-11
27-12
28-1
28-2
28-3
28-4
28-5
28-6
Title
Page
Number
Flowchart of CSPI Operation.............................................................................................. 25-25
FIR Integration Diagram ....................................................................................................... 26-1
FIR Block Diagram ............................................................................................................... 26-2
Key to Register Fields........................................................................................................... 26-8
FIR Transmitter Control Register ....................................................................................... 26-10
FIR Transmitter Count Register.......................................................................................... 26-12
FIR Receiver Control Register............................................................................................ 26-12
FIR Transmit Status Register .............................................................................................. 26-14
FIR Receive Status Register................................................................................................ 26-15
FIR Control Register ........................................................................................................... 26-16
I2C Block Diagram................................................................................................................ 27-1
Connection of Devices to I2C Bus ........................................................................................ 27-2
Key to Register Fields........................................................................................................... 27-4
I2C Address Register............................................................................................................. 27-7
I2C Frequency Register......................................................................................................... 27-7
I2C Control Register.............................................................................................................. 27-9
I2C Status Register .............................................................................................................. 27-10
I2C Data Register ................................................................................................................ 27-11
I2C Standard Communication Protocol............................................................................... 27-12
Repeated START................................................................................................................. 27-14
Synchronized Clock SCL.................................................................................................... 27-15
Flowchart of Typical I2C Interrupt Routine........................................................................ 27-18
Definition of Timing for Devices on I2C Bus ..................................................................... 27-19
KPP Peripheral Block Diagram ............................................................................................ 28-1
Key to Register Fields........................................................................................................... 28-3
KPCR Register ...................................................................................................................... 28-5
KPSR Register ...................................................................................................................... 28-6
KDDR Register ..................................................................................................................... 28-7
KPDR Register...................................................................................................................... 28-8
Keypad Synchronizer Functional Diagram......................................................................... 28-11
Multiple Key Presses on Same Column Line (Simplified View) ....................................... 28-12
Multiple Key Presses on Same Row Line (Simplified View)............................................. 28-12
Decoding Wrong Three-Key Presses .................................................................................. 28-13
Matrix with “Ghost” Key Protections ................................................................................. 28-14
KPP Interface with 3-Point Contact Key Matrix (Simplified View) .................................. 28-15
Applications Processor Memory Stick Controller Block Diagram....................................... 29-2
Key to Register Fields........................................................................................................... 29-4
Timeout Register ................................................................................................................... 29-6
Gasket Interrupt Status/Clear Register.................................................................................. 29-7
Gasket Interrupt Enable Register .......................................................................................... 29-8
MSHC Clock Structure ....................................................................................................... 29-10
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
lxxxv
Figures
Figure
Number
28-7
29-1
29-2
29-3
29-4
29-5
29-6
29-7
29-8
29-9
29-10
29-11
29-12
29-13
29-14
29-15
29-16
29-17
29-18
29-19
29-20
29-21
29-22
29-23
29-24
29-25
29-26
29-27
29-28
30-1
30-2
30-3
30-4
30-5
30-6
30-7
30-8
30-9
30-10
30-11
30-12
Title
Page
Number
Gasket Memory Interface Logic ......................................................................................... 29-11
Secure Digital Host Controller Block Diagram .................................................................... 30-2
System Interconnection with the Secure Digital Host Controller......................................... 30-2
Key to Register Fields........................................................................................................... 30-5
SDHC Clock Control Register.............................................................................................. 30-9
SDHC Status Register ......................................................................................................... 30-10
SDHC Clock Rate Register................................................................................................. 30-14
SDHC Command and Data Control Register ..................................................................... 30-16
MMC/SD Response Time Out Register.............................................................................. 30-18
SDHC Read Time Out Register .......................................................................................... 30-19
SDHC Block Length Register............................................................................................. 30-20
SDHC Number of Blocks Register ..................................................................................... 30-21
SDHC Revision Number Register ...................................................................................... 30-22
SDHC Interrupt Control Register ....................................................................................... 30-23
SDHC Command Number Register .................................................................................... 30-27
SDHC Command Argument Register ................................................................................. 30-28
SDHC Response FIFO Register.......................................................................................... 30-28
SDHC Buffer Access Register ............................................................................................ 30-30
SDHC Buffer Scheme ......................................................................................................... 30-31
Byte Lanes Relationship Between System IP Bus and SD Card Bus ................................. 30-32
Example for Dividing Large Data Transfer ........................................................................ 30-34
DMA Interface Block.......................................................................................................... 30-35
Memory Controller Block Diagram .................................................................................... 30-36
a) Card Interrupt Scheme, b) Card Interrupt Detection and Handling Procedure............... 30-38
Block diagram for Command Interpreter............................................................................ 30-41
Command CRC Shift Register (DATs Have a Similar Structure)....................................... 30-41
Clock used in SDHC ........................................................................................................... 30-42
Flow Diagram for Card Detection ...................................................................................... 30-46
Flowchart for Reset of SDHC and SD I/O Card ................................................................. 30-47
SIM Block Diagram .............................................................................................................. 31-1
Key to Register Fields........................................................................................................... 31-8
SIM Port1 Control Register ................................................................................................ 31-12
SIM Setup Register ............................................................................................................. 31-13
SIM Port 1 Detect Register ................................................................................................. 31-14
SIM Port1 Transmit Buffer Register ................................................................................... 31-15
SIM Port 1 Receive Buffer Register ................................................................................... 31-16
SIM Port0 Control Register ................................................................................................ 31-17
SIM Control Register .......................................................................................................... 31-18
SIM Clock Select Register.................................................................................................. 31-20
SIM Receive Threshold Register ........................................................................................ 31-21
SIM Enable Register ........................................................................................................... 31-22
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
lxxxvi
Freescale Semiconductor
Figures
Figure
Number
30-13
30-14
30-15
30-16
30-17
30-18
30-19
30-20
30-21
30-22
30-23
30-24
30-25
30-26
30-27
30-28
30-29
30-30
30-31
30-32
30-33
30-34
30-35
30-36
30-37
30-38
30-39
30-40
30-41
30-42
30-43
30-44
30-45
30-46
30-47
30-48
30-49
31-1
31-2
31-3
31-4
Title
Page
Number
SIM Transmit Status Register ............................................................................................. 31-23
SIM Receive Status Register............................................................................................... 31-25
SIM Interrupt Mask Register .............................................................................................. 31-27
SIM Port0 Transmit Buffer Register ................................................................................... 31-29
SIM Port0 Receive Buffer Register .................................................................................... 31-30
SIM Port0 Detect Register .................................................................................................. 31-31
SIM Data Format Register .................................................................................................. 31-32
SIM Transmit Threshold Register....................................................................................... 31-33
SIM Transmit Guard Control Register................................................................................ 31-34
SIM Open Drain Configuration Control Register............................................................... 31-35
SIM Reset Control Register ................................................................................................ 31-36
SIM Character Wait Time Register ..................................................................................... 31-37
SIM General Purpose Counter Register.............................................................................. 31-38
SIM Divisor Register .......................................................................................................... 31-39
SIM Block Wait Time Register ........................................................................................... 31-39
SIM Block Guard Time Register ........................................................................................ 31-40
SIM Block Wait Time Register HIGH................................................................................ 31-41
Block Diagram for SIM Module ......................................................................................... 31-42
SIM Detailed Block Diagram ............................................................................................. 31-43
SIM Bus Interface ............................................................................................................... 31-44
SIM Read Registers ............................................................................................................ 31-45
Register Bit Diagram .......................................................................................................... 31-45
SIM Clock Generator .......................................................................................................... 31-46
Transmit State Machine ...................................................................................................... 31-48
Transmit Guard Time .......................................................................................................... 31-51
Transmit NACK Generator ................................................................................................. 31-51
SIM Data Conventions........................................................................................................ 31-52
Receive State Machine........................................................................................................ 31-53
Start Bit Diagram ................................................................................................................ 31-55
Parity Bit Diagram .............................................................................................................. 31-55
Framing Error Diagram....................................................................................................... 31-56
Valid Initial Characters........................................................................................................ 31-57
Inverse Convention Versus Direct Convention ................................................................... 31-57
SIM Card Hookup............................................................................................................... 31-59
Auto Power Down Sequence .............................................................................................. 31-60
CRC Block Diagram ........................................................................................................... 31-62
Suggested T=1, EMV, Geldkarte Compliant SIM Initialization ......................................... 31-77
UART Block Diagram .......................................................................................................... 32-2
Key to Register Fields........................................................................................................... 32-8
UART Receiver Register .................................................................................................... 32-13
UART Transmitter Register ................................................................................................ 32-14
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
lxxxvii
Figures
Figure
Number
31-5
31-6
31-7
31-8
31-9
31-10
31-11
31-12
31-13
31-14
31-15
31-16
31-17
31-18
31-19
31-20
31-21
31-22
31-23
31-24
31-25
31-26
32-1
32-2
32-3
32-4
32-5
32-6
32-7
32-8
32-9
32-10
32-11
32-12
32-13
32-14
32-15
32-16
32-17
32-18
32-19
Title
Page
Number
UART Control Register 1 ................................................................................................... 32-15
UART Control Register 2 ................................................................................................... 32-17
UART Control Register 3 ................................................................................................... 32-20
UART Control Register 4 ................................................................................................... 32-22
UART FIFO Control Register............................................................................................. 32-24
UART Status Register 1 ...................................................................................................... 32-25
UART Status Register 2 ...................................................................................................... 32-27
UART Escape Character Register....................................................................................... 32-30
UART Escape Timer Register............................................................................................. 32-31
UART BRM Incremental Register...................................................................................... 32-32
UART BRM Modulator Register ........................................................................................ 32-33
UART Baud Rate Count Register ....................................................................................... 32-34
UART One Millisecond Register ........................................................................................ 32-35
UART Test Register ............................................................................................................ 32-36
UART in DCE Mode........................................................................................................... 32-39
UART in DTE Mode........................................................................................................... 32-40
Examples of Working Relations Between ipg_clk and ipg_perclk..................................... 32-44
UART Simplified Block and Clock Generation Diagrams ................................................. 32-50
Transmitter FIFO Empty Interrupt Suppression Flowchart ................................................ 32-52
Receiver Flowchart ............................................................................................................. 32-54
Majority Vote Results.......................................................................................................... 32-57
Baud Rate Detection Protocol Diagram.............................................................................. 32-60
USBOTG Block Diagram ..................................................................................................... 33-1
Key to Register Fields........................................................................................................... 33-4
USB Control Register ........................................................................................................... 33-9
OTG Mirror Register (OTGMIRROR)............................................................................... 33-12
TLL MUX Functional Diagram .......................................................................................... 33-17
USB Bypass MUX Functional Diagram ............................................................................. 33-19
Example USB 2.0 System Configuration ........................................................................... 33-22
USBOTG Block Diagram ................................................................................................... 33-23
End Point Queue Head Organization .................................................................................. 33-24
Periodic Schedule Organization.......................................................................................... 33-25
Asynchronous Schedule Organization ................................................................................ 33-25
ID—Identification Register................................................................................................. 33-32
HWGENERAL—General Hardware Parameters ............................................................... 33-33
HWHOST—Host Hardware Parameters ............................................................................ 33-34
HWDEVICE—Device Hardware Parameters .................................................................... 33-35
HWTXBUF—TX Buffer Hardware Parameters................................................................. 33-35
HWRXBUF—RX Buffer Hardware Parameters ................................................................ 33-36
CAPLENGTH—Capability Register Length ...................................................................... 33-37
HCIVERSION—Host Interface Version Number .............................................................. 33-37
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
lxxxviii
Freescale Semiconductor
Figures
Figure
Number
32-20
32-21
32-22
32-23
32-24
32-25
32-26
32-27
32-28
32-29
32-30
32-31
32-32
32-33
32-34
32-35
32-36
32-37
32-38
32-39
32-40
32-41
32-42
32-43
32-44
32-45
32-46
32-47
32-48
32-49
32-50
32-51
32-52
32-53
32-54
32-55
32-56
32-57
32-58
32-59
32-60
Title
Page
Number
HCSPARAMS—Host Control Structural Parameters......................................................... 33-38
HCCPARAMS—Host Control Capability Parameters ....................................................... 33-40
DCIVERSION—Device Interface Version Number........................................................... 33-41
DCCPARAMS—Device Controller Capability Parameters ............................................... 33-42
USB Command Register (USBCMD) ................................................................................ 33-43
USBSTS—USB Status........................................................................................................ 33-47
USBINTR—USB Interrupt Enable..................................................................................... 33-50
FRINDEX—USB Frame Index .......................................................................................... 33-52
PERIODICLISTBASE—Host Controller Frame List Base Address ................................. 33-53
DEVICEADDR—Device Controller USB Device Address............................................... 33-54
ASYNCLISTADDR—Host Controller Next Asynchronous Address................................ 33-55
ENDPOINTLISTADDR—Device Controller Endpoint List Address ............................... 33-56
BURSTSIZE—Host Controller Embedded TT Async. Buffer Status ................................ 33-56
TXFILLTUNING Register.................................................................................................. 33-57
ULPI VIEWPORT .............................................................................................................. 33-59
PORTSCx—Port Status Control[1:8] ................................................................................. 33-60
OTGSC—OTG Status Control ........................................................................................... 33-68
USBMODE—USB Device Mode....................................................................................... 33-70
ENDPTSETUPSTAT—Endpoint Setup Status ................................................................... 33-71
ENDPTPRIME—Endpoint Initialization............................................................................ 33-72
ENDPTFLUSH—Endpoint De-Initialize ........................................................................... 33-73
ENDPTSTAT—Endpoint Status ......................................................................................... 33-74
ENDPTCOMPLETE—Endpoint Compete......................................................................... 33-75
ENDPTCTRL0—Endpoint Control 0 ................................................................................. 33-76
ENDPTCTRL1–ENDPTCTRL15—Endpoint Control 1 to 15 ........................................... 33-78
Controller Mode .................................................................................................................. 33-80
Periodic Schedule Organization.......................................................................................... 33-82
Format of Frame List Element Pointer ............................................................................... 33-82
Asynchronous Schedule Organization ................................................................................ 33-83
Isochronous Transaction Descriptor (iTD) ......................................................................... 33-84
Split-transaction Isochronous Transaction Descriptor (siTD) ............................................ 33-88
Queue Element Transfer Descriptor Block Diagram .......................................................... 33-93
Queue Head Structure Layout ............................................................................................. 33-99
FSTN Register................................................................................................................... 33-104
Frame Span Traversal Node Structure Layout .................................................................. 33-104
Example USB 2.0 Host Controller Port Routing Block Diagram..................................... 33-107
Port Owner Handoff State Machine .................................................................................. 33-110
Derivation of Pointer into Frame List Array..................................................................... 33-116
General Format of Asynchronous Schedule List .............................................................. 33-117
Best Fit Approximation..................................................................................................... 33-119
Frame Boundary Relationship Between HS bus and FS/LS Bus...................................... 33-120
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
lxxxix
Figures
Figure
Number
32-61
32-62
32-63
32-64
32-65
32-66
32-67
32-68
32-69
32-70
32-71
32-72
32-73
32-74
32-75
32-76
32-77
32-78
32-79
32-80
32-81
32-82
32-83
32-84
33-1
33-2
33-3
33-4
33-5
33-6
33-7
33-8
33-9
33-10
34-1
34-2
34-3
34-4
34-5
34-6
34-7
Title
Page
Number
Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries ............ 33-121
Example Periodic Schedule .............................................................................................. 33-123
Example Association of iTDs to Client Request Buffer ................................................... 33-126
Generic Queue Head Unlink Scenario .............................................................................. 33-131
Asynchronous Schedule List w/Annotation to Mark Head of List ................................... 33-132
Example State Machine for Managing Asynchronous Schedule Traversal ...................... 33-133
Example HC State Machine for Controlling NAK Counter Reloads ............................... 33-137
Host Controller Queue Head Traversal State Machine ..................................................... 33-139
Example Mapping of qTD Buffer Pointers to Buffer Pages ............................................. 33-148
Host Controller Asynchronous Schedule Split-Transaction State Machine ..................... 33-151
Split Transaction, Interrupt Scheduling Boundary Conditions ......................................... 33-154
General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading .................. 33-155
Example Host Controller Traversal of Recovery Path via FSTNs.................................... 33-157
Split Transaction State Machine for Interrupt................................................................... 33-160
Split Transaction, Isochronous Scheduling Boundary Conditions ................................... 33-167
siTD Scheduling Boundary Examples .............................................................................. 33-169
Split Transaction State Machine for Isochronous ............................................................. 33-172
End Point Queue Head Organization ................................................................................ 33-193
Endpoint Queue Head (dQH)............................................................................................ 33-194
dTD Register Examples .................................................................................................... 33-196
Endpoint Transfer Descriptor (dTD)................................................................................. 33-196
Device State Diagram ....................................................................................................... 33-200
End Point Queue Head Diagram ....................................................................................... 33-213
Software Link Pointers ..................................................................................................... 33-215
Enhanced Periodic Interrupt Timer (EPIT) Block Diagram ................................................. 34-1
EPIT Module Signals ............................................................................................................ 34-3
Key to Register Fields........................................................................................................... 34-6
EPIT Control Register........................................................................................................... 34-8
EPIT Status Register ........................................................................................................... 34-10
EPITLR Load Register........................................................................................................ 34-11
EPITC Compare Register (EPTICCMPR) .......................................................................... 34-12
EPIT Counter Register ........................................................................................................ 34-12
Prescaler Value Change Timing Diagram ........................................................................... 34-14
Compare Event and Interrupt Timing Diagram .................................................................. 34-14
General Purpose Timer (GPT) Block Diagram ..................................................................... 35-1
GPT Counter Clocks Diagram .............................................................................................. 35-2
GPT Module Signals ............................................................................................................. 35-4
Key to Register Fields........................................................................................................... 35-8
GPT Control Register (GPTCR) ......................................................................................... 35-11
GPT Prescaler Register ....................................................................................................... 35-14
GPT Status Register ............................................................................................................ 35-15
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
xc
Freescale Semiconductor
Figures
Figure
Number
34-8
34-9
34-10
34-11
34-12
34-13
34-14
34-15
34-16
34-17
35-1
35-2
35-3
35-4
35-5
35-6
35-7
35-8
35-9
35-10
35-11
35-12
35-13
36-1
36-2
36-3
36-4
36-5
36-6
36-7
36-8
36-9
36-10
36-11
36-12
36-13
37-1
37-2
37-3
37-4
37-5
Title
Page
Number
GPT Interrupt Register ........................................................................................................ 35-16
GPT Output Compare Register 1 ........................................................................................ 35-17
GPT Output Compare Register 2 ........................................................................................ 35-17
GPT Output Compare Register 3 ........................................................................................ 35-18
GPT Input Capture Register 1 ............................................................................................. 35-19
GPT Input Capture Register 2 ............................................................................................. 35-19
GPT Counter Register ......................................................................................................... 35-20
Prescaler Value Change Timing Diagram ........................................................................... 35-22
Input Capture Event Timing Diagram................................................................................. 35-22
Output Compare and Interrupt Timing Diagram ................................................................ 35-23
Pulse-Width Modulator Block Diagram ............................................................................... 36-1
PWM Module Signals ........................................................................................................... 36-3
Key to Register Fields........................................................................................................... 36-6
PWM Control Register (PWMCR) ....................................................................................... 36-8
PWM Status Register (PWMSR) ........................................................................................ 36-10
PWM Interrupt Register (PWMIR)..................................................................................... 36-11
PWM Sample Register (PWMSAR)................................................................................... 36-12
PWM Period Register (PWMPR) ....................................................................................... 36-13
PWM Counter Register (PWMCNR) ................................................................................. 36-13
PWM Clocking ................................................................................................................... 36-16
Clock Distribution Inside PWM ......................................................................................... 36-17
Clock Selection and Division Unit...................................................................................... 36-18
ipg_enable_clk Generation Logic ....................................................................................... 36-18
Real Time Clock Block Diagram .......................................................................................... 37-1
Key to Register Fields........................................................................................................... 37-4
RTC Hours and Minutes Counter Register ........................................................................... 37-6
RTC Seconds Counter Register............................................................................................. 37-7
RTC Hours and Minutes Alarm Register .............................................................................. 37-8
RTC Seconds Alarm Register ............................................................................................... 37-9
RTC Control Register............................................................................................................ 37-9
RTC Interrupt Status Register ............................................................................................. 37-10
RTC Interrupt Enable Register............................................................................................ 37-13
RTC Stopwatch Minutes Register ....................................................................................... 37-15
RTC Days Counter Register................................................................................................ 37-16
RTC Day Alarm Register .................................................................................................... 37-16
Flowchart of RTC Operation............................................................................................... 37-19
WDOG Block Diagram......................................................................................................... 38-1
Key to Register Fields........................................................................................................... 38-4
Watchdog Control Register ................................................................................................... 38-5
Watchdog Service Register (WSR) ....................................................................................... 38-7
Watchdog Reset Status Register (WRSR)............................................................................. 38-7
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
xci
Figures
Figure
Number
37-6
37-7
38-1
38-2
38-3
38-4
38-5
38-6
38-7
38-8
38-9
38-10
38-11
38-12
38-13
38-14
38-15
38-16
38-17
38-18
38-19
38-20
38-21
38-22
38-23
38-24
38-25
38-26
38-27
38-28
38-29
Title
Page
Number
Clock Monitor Signals ........................................................................................................ 38-12
Counter State Machine........................................................................................................ 38-14
AIPS Interface....................................................................................................................... 39-3
AIPS Memory Map #1.......................................................................................................... 39-5
AIPS Memory Map #2.......................................................................................................... 39-6
Key to Register Fields......................................................................................................... 39-22
Master Privilege Register 1................................................................................................. 39-25
Master Privilege Register 2................................................................................................. 39-25
Peripheral Access Control Register 1 ................................................................................. 39-27
Peripheral Access Control Register 2 ................................................................................. 39-27
Peripheral Access Control Register 3 ................................................................................. 39-28
Peripheral Access Control Register 4 ................................................................................. 39-28
Off-Platform Peripheral Access Control Register 1............................................................ 39-30
Off-Platform Peripheral Access Control Register 2............................................................ 39-30
Off-Platform Peripheral Access Control Register 3............................................................ 39-31
Off-Platform Peripheral Access Control Register 4............................................................ 39-31
Off-Platform Peripheral Access Control Register 5............................................................ 39-32
Data Bus Byte Lane Mapping
for 32-Bit Peripherals, 64-Bit System, aips_byte_config[1:0] = 00 .............................. 39-38
Data Bus Byte Lane Mapping
for 32-Bit Peripherals, 64-Bit System, aips_byte_config[1:0] = 01, 11......................... 39-39
Data Bus Byte Lane Mapping
for 32-Bit Peripherals, 32-Bit System, aips_byte_config[1:0] = 00 .............................. 39-39
Data Bus Byte Lane Mapping
for 32-Bit Peripherals, 32-Bit System, aips_byte_config[1:0] = 01, 11......................... 39-40
Mapping of 32-Bit Byte Strobes, 64-Bit System ................................................................ 39-41
Mapping of 32-Bit Byte Strobes, 32-Bit System ................................................................ 39-42
Data Bus Byte Lane Mapping
for 16-Bit Peripherals, 64-Bit System, aips_byte_config[1:0] = 00 .............................. 39-43
Data Bus Byte Lane Mapping
for 16-Bit Peripherals, 64-Bit System, aips_byte_config[1:0] = 01 .............................. 39-43
Data Bus Byte Lane Mapping
for 16-Bit Peripherals, 64-Bit System, aips_byte_config[1:0] = 11............................... 39-44
Data Bus Byte Lane Mapping
for 16-Bit Peripherals, 32-Bit System, aips_byte_config[1:0] = 00 .............................. 39-44
Data Bus Byte Lane Mapping
for 16-Bit Peripherals, 32-Bit System, aips_byte_config[1:0] = 01 .............................. 39-45
Data Bus Byte Lane Mapping
for 16-Bit Peripherals, 32-Bit System, aips_byte_config[1:0] = 11............................... 39-45
Mapping of 16-Bit Byte Strobes, 64-Bit System, aips_byte_config[1:0]= 00.................... 39-46
Mapping of 16-Bit Byte Strobes, 64-Bit System, aips_byte_config[1:0]=01..................... 39-47
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
xcii
Freescale Semiconductor
Figures
Figure
Number
38-30
38-31
38-32
38-33
38-34
38-35
38-36
38-37
38-38
38-39
38-40
38-41
38-42
38-43
38-44
38-45
38-46
38-47
38-48
38-49
38-50
38-51
38-52
38-53
38-54
39-1
39-2
39-3
39-4
39-5
39-6
39-7
39-8
39-9
39-10
39-11
39-12
Title
Page
Number
Mapping of 16-Bit Byte Strobes, 64-Bit System, aips_byte_config[1:0]= 11.................... 39-48
Mapping of 16-Bit Byte Strobes, 32-Bit System, aips_byte_config[1:0]= 00.................... 39-49
Mapping of 16-Bit Byte Strobes, 32-Bit System, aips_byte_config[1:0]= 01.................... 39-49
Mapping of 16-Bit Byte Strobes, 32-Bit System, aips_byte_config[1:0]= 11.................... 39-50
Data Bus Byte Lane Mapping
for 8-Bit Peripherals, 64-Bit System, aips_byte_config[1:0] = 00, 01 .......................... 39-51
Data Bus Byte Lane Mapping for 8-Bit Peripherals, 64-Bit System,
aips_byte_config[1:0] = 11 ............................................................................................ 39-51
Data Bus Byte Lane Mapping
for 8-Bit Peripherals, 32-Bit System, aips_byte_config[1:0] = 00, 01 .......................... 39-52
Data Bus Byte Lane Mapping
for 8-Bit Peripherals, 32-Bit System, aips_byte_config[1:0] = 11................................. 39-52
Read Access, 32-Bit Peripheral, 2 Cycle AIPS Delay ........................................................ 39-56
Read Access, 16-Bit Peripheral, 2 Cycle AIPS Delay ........................................................ 39-57
Read Access, Delayed hready_in........................................................................................ 39-58
Read Access with One IPS Wait-State, Three-Cycle AIPS Delay...................................... 39-59
Doubleword Read Access, Three-Cycle AIPS Delay ......................................................... 39-60
Misaligned Read Access (Word Access to Byte Offset 1) Three-Cycle AIPS Delay......... 39-61
Read Access with Delayed Initiation, Three-Cycle AIPS Delay........................................ 39-62
Write Access, Three-Cycle AIPS Delay ............................................................................. 39-63
Write Access, 16-Bit Peripheral, Three-Cycle AIPS Delay................................................ 39-64
Doubleword Write Access, Four-Cycle AIPS Delay .......................................................... 39-65
Misaligned Write Access (Word Write to Byte Offset 1) Four-Cycle AIPS Delay ............ 39-66
Buffered Write Access, Single-Cycle AIPS Delay ............................................................. 39-67
Buffered Write Access, Delayed (AIPS_DLY_CYCLE = 1), Two-Cycle AIPS Delay ..... 39-68
Read With Error .................................................................................................................. 39-69
Read With Error, One IPS Waitstate ................................................................................... 39-70
Permission Violation Error.................................................................................................. 39-71
Permission Violation Error, AIPS_DLY_CYCLE = 1........................................................ 39-72
MAX Block Diagram............................................................................................................ 40-2
Key to Register Fields......................................................................................................... 40-11
Slave General Purpose Control Register n.......................................................................... 40-16
Master General Purpose Control Register n ....................................................................... 40-18
MAX Master Port Block Diagram ...................................................................................... 40-22
MAX Slave Port Block Diagram ........................................................................................ 40-25
Low to High Priority Mastership Change ........................................................................... 40-27
High to Low Priority Mastership Change ........................................................................... 40-28
Round-Robin Mastership Change ....................................................................................... 40-29
Parking on a Specific Master .............................................................................................. 40-30
Parking on Last Master ....................................................................................................... 40-31
Multiple Master Configuration ........................................................................................... 40-34
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
xciii
Figures
Figure
Number
39-13
40-1
40-2
40-3
40-4
40-5
40-6
40-7
40-8
40-9
40-10
40-11
40-12
40-13
40-14
40-15
40-16
40-17
40-18
40-19
40-20
40-21
40-22
40-23
40-24
40-25
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40-27
40-28
40-29
40-30
40-31
40-32
40-33
40-34
40-35
40-36
40-37
40-38
40-39
40-40
Title
Page
Number
Single Master Configuration ............................................................................................... 40-35
SDMA Block Diagram.......................................................................................................... 41-2
SDMA Connections .............................................................................................................. 41-5
SDMA Core .......................................................................................................................... 41-7
PCU State Diagram ............................................................................................................. 41-11
SDMA Hardware Scheduler ............................................................................................... 41-14
Examples of Valid DMA Requests ..................................................................................... 41-15
Scheduler State Diagram..................................................................................................... 41-21
Scheduler Timing Diagram ................................................................................................. 41-22
CRC Structure ..................................................................................................................... 41-25
Burst DMA Structure .......................................................................................................... 41-28
Peripheral DMA structure ................................................................................................... 41-31
Key to Register Fields......................................................................................................... 41-38
AP Channel 0 Pointer (MC0PTR)....................................................................................... 41-43
Channel Interrupts (INTR) Register ................................................................................... 41-44
Channel Stop/Channel Status (STOP_STAT) Register ....................................................... 41-45
Channel Start (HSTART) Register...................................................................................... 41-45
Channel Event Override (EVTOVR) Register.................................................................... 41-46
Channel DSP Override (DSPOVR) Register ...................................................................... 41-47
Channel AP Override (HOSTOVR) Register ..................................................................... 41-47
Channel Event Pending (EVTPEND) Register................................................................... 41-48
Reset Register ..................................................................................................................... 41-49
DMA Request Error (EVTERR) Register .......................................................................... 41-50
Channel AP Interrupt Mask Flags (INTRMASK) Register................................................ 41-51
Schedule Status (PSW) Register ......................................................................................... 41-51
DMA Request Error for Debug (EVTERRDBG) Register................................................. 41-52
Configuration Register (CONFIG) ..................................................................................... 41-53
OnCE Enable (ONCE_ENB) Register................................................................................ 41-54
OnCE Data Register (ONCE_DATA) ................................................................................. 41-55
OnCE Instruction Register (ONCE_INSTR) ...................................................................... 41-55
OnCE Status Register (ONCE_STAT)................................................................................ 41-56
OnCE Command Register (ONCE_CMD) ......................................................................... 41-58
Illegal Instruction Trap Address (ILLINSTADDR)............................................................ 41-59
Channel 0 Boot Address (CHN0ADDR) Register.............................................................. 41-60
DMA Requests (EVT_MIRROR)....................................................................................... 41-61
Cross-Trigger Events Configuration Register (1) (XTRIG_CONF1)................................. 41-61
Cross-Trigger Events Configuration Register (2) (XTRIG_CONF2)................................. 41-63
Channel Priority Registers (CHNPRIn) .............................................................................. 41-65
Channel Enable RAM (CHNENBLn) Register .................................................................. 41-65
GRegn to DMBUS Address Mapping ................................................................................ 41-71
Key to Register Fields......................................................................................................... 41-72
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
xciv
Freescale Semiconductor
Figures
Figure
Number
40-41
40-42
40-43
40-44
40-45
40-46
40-47
40-48
40-49
40-50
40-51
40-52
40-53
40-54
40-55
40-56
40-57
40-58
40-59
40-60
40-61
40-62
40-63
40-64
40-65
40-66
40-67
40-68
40-69
40-70
40-71
40-72
40-73
40-74
41-1
41-2
41-3
41-4
41-6
41-7
41-8
Title
Page
Number
AP (MCU) Channel 0 Pointer (MC0PTR) Register............................................................ 41-76
Current Channel Pointer (CCPTR) Register ....................................................................... 41-77
Current Channel Register (CCR) ........................................................................................ 41-78
Highest Pending Channel Register (NCR).......................................................................... 41-78
External DMA Requests Mirror (EVENTS)....................................................................... 41-79
Current Channel Priority (CCPRI) Register ....................................................................... 41-80
Next Channel Priority (NCPRI) Register............................................................................ 41-81
OnCE Event Cell Counter (ECOUNT) Register................................................................. 41-81
OnCE Event Cell Control Register (ECTL) ....................................................................... 41-82
OnCE Event Address Register A (EAA) ............................................................................ 41-84
OnCE Event Cell Address Register B................................................................................. 41-84
OnCE Event Cell Address Mask (EAM) ............................................................................ 41-85
OnCE Event Cell Data (ED) Register................................................................................. 41-86
OnCE Event Cell Data Mask (EDM) Register ................................................................... 41-86
OnCE Real-Time Buffer (RTB) Register............................................................................ 41-87
OnCE Trace Buffer (TB) Register ...................................................................................... 41-88
OnCE Status (OSTAT) Register.......................................................................................... 41-89
Channel 0 Boot Address (MCHN0ADDR) Register .......................................................... 41-91
Endian Mode Status Register (ENDIANESS) Register...................................................... 41-92
MS Structure ..................................................................................................................... 41-102
STF Code Bits ................................................................................................................... 41-103
LDF Code Bits .................................................................................................................. 41-105
PS Structure....................................................................................................................... 41-115
STF Code Bits ................................................................................................................... 41-116
LDF Code Bits .................................................................................................................. 41-119
CA Structure...................................................................................................................... 41-124
OnCE Status Register (OnCE) .......................................................................................... 41-135
OnCE Synchronization Layer ........................................................................................... 41-136
Synchronization Timings .................................................................................................. 41-137
Event Detection Unit......................................................................................................... 41-143
Event Cell Architecture..................................................................................................... 41-144
Trace Buffer ...................................................................................................................... 41-145
Peripheral to External Memory Example (1) .................................................................... 41-217
Peripheral to External Memory Example (2) .................................................................... 41-218
i.MX31 and i.MX31L SPBA Connectivity........................................................................... 42-2
SPBA Block Diagram ........................................................................................................... 42-3
Key to Register Fields........................................................................................................... 42-7
Peripheral Right Register Diagram ..................................................................................... 42-11
Example of One Master Request: No Module Arbitration ................................................. 42-13
ExamplE Of Three Master Requests: Masters Already Granted Are “Waited” ................. 42-14
Example of One Master B Gaining Ownership Of Peripheral 2......................................... 42-15
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
xcv
Figures
Figure
Number
41-9
42-1
42-2
42-3
42-4
42-5
42-6
42-7
42-8
42-9
42-10
42-11
42-12
42-13
42-14
42-15
42-16
42-17
42-18
42-19
42-20
42-21
42-22
42-23
42-24
42-25
42-26
42-27
42-28
42-29
42-30
42-31
42-32
42-33
42-34
42-35
42-36
43-1
44-1
44-2
44-3
Title
Page
Number
High-Level Block Diagram of the SPBA Clocking............................................................ 42-17
AUDMUX Block Diagram A ............................................................................................... 43-2
AUDMUX Block Diagram B ............................................................................................... 43-3
Receive Data Logic for Port x............................................................................................... 43-6
Block Diagram For Example 1 ............................................................................................. 43-7
Example Using All Internal Ports For Transmit Data........................................................... 43-8
Block Diagram For Example 2 ............................................................................................. 43-9
Example Using External Ports for Transmit Data in Consecutive Timeslots ..................... 43-10
Block Diagram For Example 3 ........................................................................................... 43-11
Example Using External Ports For Transmit Data In Non-Consecutive Timeslots............ 43-12
FSPOL-0, CLKPOL-0, CNTLOW-3, CNTHI-0................................................................. 43-13
FSPOL-0, CLKPOL-1, CNTLOW-3, CNTHI-3................................................................. 43-14
FSPOL-1, CLKPOL-0, CNTLOW-3, CNTHI-0................................................................. 43-14
FSPOL-1, CLKPOL- 1, CNTLOW-3, CNTHI-3................................................................ 43-14
FSPOL-1, CLKPOL-1, CNTLOW-6, CNTHI-0................................................................. 43-15
Tx/Rx Switch ...................................................................................................................... 43-16
Frame Sync and Clock Routing When External Port Is 4-Wire ......................................... 43-17
Frame Sync Routing When External Port Is 6-Wire........................................................... 43-19
Clock Routing When External Port Is 6-Wire .................................................................... 43-20
Internal to External Port Interconnection............................................................................ 43-22
Key to Register Fields......................................................................................................... 43-25
Port Timing Control Register for Port 1 (PTCR1) .............................................................. 43-29
Port Data Control Register for Port 1 (PDCR1) ................................................................. 43-31
Port Timing Control Register 2 (PTCR2) ........................................................................... 43-32
Port Data Control Register 2 (PDCR2)............................................................................... 43-34
Port Timing Control Register 3 (PTCR3) ........................................................................... 43-36
Port Data Control Register 3 (PDCR3)............................................................................... 43-38
Port Timing Control Register 4 (PTCR4) ........................................................................... 43-39
Port Data Control Register 4 (PDCR4)............................................................................... 43-41
Port Timing Control Register 5 (PTCR5) ........................................................................... 43-43
Port Data Control Register 5 (PDCR5)............................................................................... 43-45
Port Timing Control Register 6 (PTCR6) ........................................................................... 43-46
Port Data Control Register 6 (PDCR6)............................................................................... 43-48
Port Timing Control Register 7 (PTCR7) ........................................................................... 43-50
Port Data Control Register 7 (PDCR7)............................................................................... 43-52
Bottom Connector Network Mode Control Register (CNMCR) ........................................ 43-53
AUDMUX Clocking Scheme ............................................................................................. 43-58
MPEG-4 SP Video Capturing—Data Flow .......................................................................... 44-1
IPU Block Diagram............................................................................................................... 45-1
High Level Block Diagram of the IPU Clocking.................................................................. 45-9
Relationship Between HSP_CLK, HCLK and IPG_CLK .................................................... 45-9
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
xcvi
Freescale Semiconductor
Figures
Figure
Number
44-4
44-5
44-6
44-7
44-8
44-9
44-10
44-11
44-12
44-13
44-14
44-15
44-16
44-17
44-18
44-19
44-20
44-21
44-22
44-23
44-24
44-25
44-26
44-27
44-28
44-29
44-30
44-31
44-32
44-33
44-34
44-35
44-36
44-37
44-38
44-39
44-40
44-41
44-42
44-43
44-44
Title
Page
Number
Operation Sequence of Clock Rate Change........................................................................ 45-10
Entering and Exiting Standby Mode ................................................................................... 45-10
Clocking Microarchitecture in the IPU ............................................................................... 45-11
Key to Register Fields......................................................................................................... 45-37
IPU Configuration Register (IPU_CONF).......................................................................... 45-66
IPU Channels Buffer 0 Ready Register (IPU_CHA_BUF0_RDY).................................... 45-67
IPU Channels Buffer 1 Ready Register (IPU_CHA_BUF1_RDY).................................... 45-68
IPU Channel Double Buffer Mode Select Register (IPU_CHA_DB_MODE_SEL) ......... 45-69
IPU Channel Current Buffer Register (IPU_CHA_CUR_BUF) ........................................ 45-70
IPU Frame Synchronization Processing Flow Register (IPU_FS_PROC_FLOW)............ 45-71
IPU Frame Synchronization Displaying Flow Register (IPU_FS_DISP_FLOW) ............. 45-74
IPU Tasks Status Register (IPU_TASKS_STAT) ............................................................... 45-76
IPU Internal Memory Access Address Register (IPU_IMA_ADDR) ................................ 45-79
IPU Internal Memory Access Data Register (IPU_IMA_DATA)....................................... 45-80
IPU Interrupt Control Register 1 (IPU_INT_CTRL_1).................................................... 45-103
IPU Interrupt Control Register 2 (IPU_INT_CTRL_2).................................................... 45-104
IPU Interrupt Control Register 3 (IPU_INT_CTRL_3).................................................... 45-105
IPU Interrupt Control Register 4 (IPU_INT_CTRL_4).................................................... 45-108
IPU Interrupt Control Register 5 (IPU_INT_CTRL_5).................................................... 45-109
IPU Interrupt Status Register 1 (IPU_INT_STAT_1) ....................................................... 45-112
IPU Interrupt Status Register 2 (IPU_INT_STAT_2) ....................................................... 45-113
IPU Interrupt Status Register 3 (IPU_INT_STAT_3) ....................................................... 45-114
IPU Interrupt Status Register 4 (IPU_INT_STAT_4) ....................................................... 45-117
IPU Interrupt Status Register 5 (IPU_INT_STAT_5) ....................................................... 45-118
IPU Break Control Register 1 (IPU_BRK_CTRL_1)....................................................... 45-121
IPU Break Control Register 2 (IPU_BRK_CTRL_2)....................................................... 45-123
IPU Break Status Register (IPU_BRK_STAT) ................................................................. 45-124
IPU Diagnostic Bus Control Register (IPU_DIAGB_CTRL) .......................................... 45-125
CSI Sensor Configuration Register (CSI_SENS_CONF) ................................................ 45-137
CSI Sensor Frame Size Register (CSI_SENS_FRM_SIZE)............................................. 45-139
CSI Actual Frame Size Register (CSI_ACT_FRM_SIZE)............................................... 45-139
CSI Output Frame Control Register (CSI_OUT_FRM_CTRL)....................................... 45-140
CSI Test Control Register (CSI_TST_CTRL) .................................................................. 45-141
CSI CCIR Code Register 1 (CSI_CCIR_CODE_1) ......................................................... 45-142
CSI CCIR Code Register 2 (CSI_CCIR_CODE_2) ......................................................... 45-143
CSI CCIR Code Register 3 (CSI_CCIR_CODE_3) ......................................................... 45-144
CSI Flash Strobe Register 1 (CSI_FLASH_STROBE_1) ................................................ 45-145
CSI Flash Strobe Register 2 (CSI_FLASH_STROBE_2) ................................................ 45-146
IC Configuration Register (IC_CONF)............................................................................. 45-147
IC Preprocessing Encoder Resizing Coefficients Register (IC_PRP_ENC_RSC)........... 45-149
IC Preprocessing View-Finder Resizing Coefficients Register (IC_PRP_VF_RSC)....... 45-150
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
xcvii
Figures
Figure
Number
44-45
44-46
44-47
44-48
44-49
44-50
44-51
44-52
44-53
44-54
44-55
44-56
44-57
44-58
44-59
44-60
44-61
44-62
44-63
44-64
44-65
44-66
44-67
44-68
44-69
44-70
44-71
44-72
44-73
44-74
44-75
44-76
44-77
44-78
44-79
44-80
44-81
44-82
44-83
44-84
Title
Page
Number
IC Post-Processing Resizing Coefficients Register (IC_PP_RSC)................................... 45-151
IC Combining Parameters Register 1 (IC_CMBP_1)....................................................... 45-152
IC Combining Parameters Register 2 (IC_CMBP_2)....................................................... 45-153
PF Configuration Register (PF_CONF)............................................................................ 45-154
IDMAC Configuration Register (IDMAC_CONF) .......................................................... 45-155
IDMAC Channel Enable Register (IDMAC_CHA_EN).................................................. 45-156
IDMAC Channel Priority Register (IDMAC_CHA_PRI)................................................ 45-157
IDMAC Channel Busy Register (IDMAC_CHA_BUSY) ............................................... 45-158
SDC Common Configuration Register (SDC_COM_CONF) .......................................... 45-159
SDC Graphic Window Control Register (SDC_GRAPH_WIND_CTRL)....................... 45-161
SDC Foreground Window Position Register (SDC_FG_POS) ........................................ 45-162
SDC Background Window Position Register (SDC_BG_POS) ....................................... 45-163
SDC Cursor Position Register (SDC_CUR_POS)............................................................ 45-164
SDC Cursor Blinking and PWM Contrast Control Register
(SDC_CUR_BLINK_PWM_CTRL) ........................................................................... 45-165
SDC Color Cursor Mapping Register (SDC_CUR_MAP)............................................... 45-166
SDC Horizontal Configuration Register (SDC_HOR_CONF) ........................................ 45-167
SDC Vertical Configuration Register (SDC_VER_CONF).............................................. 45-168
SDC Sharp Configuration Register 1 (SDC_SHARP_CONF_1)..................................... 45-169
SDC Sharp Configuration Register 2 (SDC_SHARP_CONF_2)..................................... 45-170
ADC Configuration Register (ADC_CONF).................................................................... 45-171
ADC System Channel 1 Start Address Register (ADC_SYSCHA1_SA) ........................ 45-174
ADC System Channel 2 Start Address Register (ADC_SYSCHA2_SA) ........................ 45-175
ADC Preprocessing Channel Start Address Register (ADC_PRP_CHAN_SA) .............. 45-176
ADC Post-Processing Channel Start Address Register (ADC_PPCHAN_SA) ............... 45-176
ADC Display 0 Configuration Register (ADC_DISP0_CONF)....................................... 45-177
ADC Display 0 Read Acknowledge Pattern Register (ADC_DISP0_RD_AP) ............... 45-178
ADC Display 0 Read Mask Register (ADC_DISP0_RDM) ............................................ 45-179
ADC Display 0 Screen Size Register (ADC_DISP0_SS) ................................................ 45-180
ADC Display 1 Configuration Register (ADC_DISP1_CONF)....................................... 45-181
ADC Display 1 Read Acknowledge Pattern Register (ADC_DISP1_RD_AP) ............... 45-182
ADC Display 1 Read Mask Register (ADC_DISP1_RDM) ............................................ 45-183
ADC Displays 1 or 2 Screen Size Register (ADC_DISP12_SS)...................................... 45-183
ADC Display 2 Configuration Register (ADC_DISP2_CONF)....................................... 45-184
ADC Display 2 Read Acknowledge Pattern Register (ADC_DISP2_RD_AP) ............... 45-185
ADC Display 2 Read Mask Register (ADC_DISP2_RDM) ............................................ 45-186
ADC Displays Vertical Synchronization Register (ADC_DISP_VSYNC) ...................... 45-187
DI Display Interface Configuration Register (DI_DISP_IF_CONF) ............................... 45-189
DI Display Signals Polarity Register (DI_DISP_SIG_POL)............................................ 45-192
DI Serial Display 1 Configuration Register (DI_SER_DISP1_CONF) ........................... 45-196
DI Serial Display 2 Configuration Register (DI_SER_DISP2_CONF) ........................... 45-198
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
xcviii
Freescale Semiconductor
Figures
Figure
Number
44-85
44-86
44-87
44-88
44-89
44-90
44-91
44-92
44-93
44-94
44-95
44-96
44-97
44-98
44-99
44-100
44-101
44-102
44-103
44-104
44-105
44-106
44-107
44-108
44-109
44-110
44-111
44-112
44-113
44-114
44-115
44-116
44-117
44-118
44-119
44-120
44-121
44-122
44-123
44-124
44-125
Title
Page
Number
DI HSP_CLK Period Register (DI_HSP_CLK_PER)...................................................... 45-200
DI Display 0 Time Configuration Register 1 (DI_DISP0_TIME_CONF_1) ................... 45-201
DI Display 0 Time Configuration Register 2 (DI_DISP0_TIME_CONF_2) ................... 45-202
DI Display 0 Time Configuration Register 3 (DI_DISP0_TIME_CONF_3) ................... 45-204
DI Display 1 Time Configuration Register 1 (DI_DISP1_TIME_CONF_1) ................... 45-205
DI Display 1 Time Configuration Register 2 (DI_DISP1_TIME_CONF_2) ................... 45-206
DI Display 1 Time Configuration Register 3 (DI_DISP1_TIME_CONF_3) ................... 45-208
DI Display 2 Time Configuration Register 1 (DI_DISP2_TIME_CONF_1) ................... 45-209
DI Display 2 Time Configuration Register 2 (DI_DISP2_TIME_CONF_2) ................... 45-211
DI Display 2 Time Configuration Register 3 (DI_DISP2_TIME_CONF_3) ................... 45-212
DI Display 3 Time Configuration Register (DI_DISP3_TIME_CONF) .......................... 45-214
DI Display 3 Data Byte 0 Mapping Register (DI_DISP0_DB0_MAP) ........................... 45-215
DI Display 0 Data Byte 1 Mapping Register (DI_DISP0_DB1_MAP) ........................... 45-216
DI Display 0 Data Byte 2 Mapping Register (DI_DISP0_DB2_MAP) ........................... 45-218
DI Display 0 Command Byte 0 Mapping Register (DI_DISP0_CB0_MAP) .................. 45-219
DI Display 0 Command Byte 1 Mapping Register (DI_DISP0_CB1_MAP) .................. 45-220
DI Display 0 Command Byte 2 Mapping Register (DI_DISP0_CB2_MAP) .................. 45-221
DI Display 1 Data Byte 0 Mapping Register (DI_DISP1_DB0_MAP) ........................... 45-223
DI Display 1 Data Byte 1 Mapping Register (DI_DISP1_DB1_MAP) ........................... 45-224
DI Display 1 Data Byte 2 Mapping Register (DI_DISP1_DB2_MAP) ........................... 45-225
DI Display 1 Command Byte 0 Mapping Register (DI_DISP1_CB0_MAP) .................. 45-226
DI Display 1 Command Byte 1 Mapping Register (DI_DISP1_CB1_MAP) .................. 45-228
DI Display 1 Command Byte 2 Mapping Register (DI_DISP1_CB2_MAP) .................. 45-229
DI Display 2 Data Byte 0 Mapping Register (DI_DISP2_DB0_MAP) ........................... 45-230
DI Display 2 Data Byte 1 Mapping Register (DI_DISP2_DB1_MAP) ........................... 45-231
DI Display 2 Data Byte 2 Mapping Register (DI_DISP2_DB2_MAP) ........................... 45-233
DI Display 2 Command Byte 0 Mapping Register (DI_DISP2_CB0_MAP) .................. 45-234
DI Display 2 Command Byte 1 Mapping Register (DI_DISP2_CB1_MAP) .................. 45-235
DI Display 2 Command Byte 2 Mapping Register (DI_DISP2_CB2_MAP) .................. 45-236
DI Display 3 Byte 0 Mapping Register (DI_DISP3_B0_MAP)....................................... 45-238
DI Display 3 Byte 1 Mapping Register (DI_DISP3_B1_MAP)....................................... 45-239
DI Display 3 Byte 2 Mapping Register (DI_DISP3_B2_MAP)....................................... 45-240
DI Display Access Cycles Count Register (DI_DISP_ACC_CC).................................... 45-242
DI Display Low Level Access Configuration Register (DI_DISP_LLA_CONF) ........... 45-244
DI Display Low Level Access Data (DI_DISP_LLA_DATA) ......................................... 45-245
CSI Block Diagram ........................................................................................................... 45-246
Sensor Image Frames ........................................................................................................ 45-247
IC Block Diagram ............................................................................................................. 45-251
PF Block Diagram............................................................................................................. 45-258
Allocation of Y Input and Output Frame Buffer in Memory (Little Endian) ................... 45-259
Allocation of U Input and Output Frame Buffer in Memory (Little Endian) ................... 45-260
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
xcix
Figures
Figure
Number
44-126
44-127
44-128
44-129
44-130
44-131
44-132
44-133
44-134
44-135
44-136
44-137
44-138
44-139
44-140
44-141
44-142
44-143
44-144
44-145
44-146
44-147
44-148
44-149
44-150
44-151
44-152
44-153
45-1
45-2
45-3
45-4
45-5
45-6
45-7
45-8
45-9
45-10
45-11
45-12
45-13
Title
Page
Number
Allocation of V Input and Output Frame Buffer in Memory (Little Endian) ................... 45-261
QP Parameters Allocation in the System Memory ........................................................... 45-263
Processing Flow for Y Component in MPEG-4 Mode (Part 1) ........................................ 45-265
Processing Flow for Y Component in MPEG-4 Mode (Part 2) ........................................ 45-266
QP, QPC, FOA, FOB Parameters Allocation in the System Memory (Little Endian)...... 45-268
BSB Parameter Definition ................................................................................................ 45-269
BSB Parameters Allocation in the System Memory (Little Endian) ................................ 45-270
Processing Flow for H.264 (First Line of Frame)............................................................. 45-271
Processing Flow for H.264 (All Lines of the Frame Excluding the First)........................ 45-272
SDC Block Diagram ......................................................................................................... 45-274
Displayed Planes ............................................................................................................... 45-275
ADC Block Diagram......................................................................................................... 45-277
Data and Command Buffers in the System Memory ........................................................ 45-291
Windows on a Smart Display............................................................................................ 45-293
DI Block Diagram ............................................................................................................. 45-302
Example of Data Packing for Writing Data to the Display............................................... 45-306
Example of Data Unpacking for Reading Data from the Display .................................... 45-307
IDMAC Block Diagram.................................................................................................... 45-309
Addressing Parameters and Image Frame......................................................................... 45-312
Example of Packing .......................................................................................................... 45-314
Example of Unpacking...................................................................................................... 45-315
CM Block Diagram ........................................................................................................... 45-316
Initialization and Enabling Steps ...................................................................................... 45-335
Triggering Step.................................................................................................................. 45-336
Operating Step—First Input Data Fetching ...................................................................... 45-337
Operating Step—First Input Graphics Fetching ............................................................... 45-338
Operating Step—First Output Data Writing to the System Memory................................ 45-339
IPU Management Flow ..................................................................................................... 45-346
SSI Block Diagram ............................................................................................................... 46-2
Normal Mode Timing—Continuous Clock .......................................................................... 46-7
Normal Mode Timing—Internal Gated Clock...................................................................... 46-8
Normal Mode Timing—External Gated Clock..................................................................... 46-8
Network Mode Timing—Continuous Clock....................................................................... 46-12
Internal Gated Mode Timing—Rising Edge Clocking/Falling Edge Latching .................. 46-13
Internal Gated Mode Timing—Falling Edge Clocking/Rising Edge Latching .................. 46-13
External Gated Mode Timing—Rising Edge Clocking/Falling Edge Latching ................. 46-14
External Gated Mode Timing—Falling Edge clocking/Rising Edge Latching .................. 46-14
I2S Mode Timing—Serial Clock, Frame Sync, and Serial Data......................................... 46-14
Key to Register Fields......................................................................................................... 46-21
SSI0 Transmit Data Register............................................................................................... 46-26
SSI1 Transmit Data Register............................................................................................... 46-26
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
c
Freescale Semiconductor
Figures
Figure
Number
45-14
45-15
45-16
45-17
45-18
45-19
45-20
45-21
45-22
45-23
45-24
45-25
45-26
45-27
45-28
45-29
45-30
45-31
45-32
45-33
45-34
45-35
45-36
45-37
45-38
45-39
45-40
45-41
45-42
46-1
46-2
46-3
Title
Page
Number
Transmit Data Path (TXBIT0=0, TSHFD=0) (MSB Alignment) ....................................... 46-27
Transmit Data Path (TXBIT0=0, TSHFD=1) (MSB Alignment) ....................................... 46-28
Transmit Data Path (TXBIT0=1, TSHFD=0) (LSB Alignment) ........................................ 46-28
Transmit Data Path (TXBIT0=1, TSHFD=1) (LSB Alignment) ........................................ 46-28
SSI0 Receive Data Register ................................................................................................ 46-29
SSI1 Receive Data Register ................................................................................................ 46-29
Receive Data Path (RXBIT0=0, RSHFD=0) (MSB Alignment)........................................ 46-30
Receive Data Path (RXBIT0=0, RSHFD=1) (MSB Alignment)........................................ 46-31
Receive Data Path (RXBIT0=1, RSHFD=0) (LSB Alignment) ......................................... 46-31
Receive Data Path (RXBIT0=1, RSHFD=1) (LSB Alignment) ......................................... 46-32
SSI Control Register ........................................................................................................... 46-32
SSI Interrupts ...................................................................................................................... 46-34
SSI Interrupt Status Register............................................................................................... 46-35
SSI Interrupt Enable Register ............................................................................................. 46-39
SSI Transmit Configuration Register.................................................................................. 46-40
SSI Receive Configuration Register ................................................................................... 46-42
SSI Transmit Clock Control Register ................................................................................. 46-45
SSI Receive Clock Control Register ................................................................................... 46-45
SSI FIFO Control/Status Register....................................................................................... 46-47
SSI AC97 Control Register................................................................................................. 46-50
SSI AC97 Command Address Register .............................................................................. 46-51
SSI AC97 Command Data Register.................................................................................... 46-52
SSI AC97 Tag Register ....................................................................................................... 46-53
SSI Transmit Time Slot Mask Register............................................................................... 46-53
SSI Receive Time Slot Mask Register ................................................................................ 46-54
SSI Clocking ....................................................................................................................... 46-56
SSI Transmit Clock Generator Block Diagram .................................................................. 46-56
SSI Transmit Frame Sync Generator Block Diagram ......................................................... 46-57
SSI Bit Clock Equation ....................................................................................................... 46-57
MBX R-S 3D Graphics Core Top-level Block Diagram ...................................................... 47-1
MBX R-S Block Diagram..................................................................................................... 47-3
MMU Address Translation ................................................................................................... 47-6
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
ci
Figures
Figure
Number
Title
Page
Number
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
cii
Freescale Semiconductor
Tables
Table
Number
Title
Page
Number
Tables
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
4-1
Frequency Domains .............................................................................................................. 1-11
Refresh Rates and Pixel Formats .......................................................................................... 1-21
Display Types Supported by the Synchronous Interface ...................................................... 1-23
Simultaneous Functionality in the Dedicated Port................................................................ 1-24
Memory Map........................................................................................................................... 2-1
Peripheral Access Type ........................................................................................................... 2-5
Interrupt Summary .................................................................................................................. 2-7
Interrupt Sources ..................................................................................................................... 2-8
SDMA Events Summary....................................................................................................... 2-10
CCM Memory Map................................................................................................................. 3-3
Register Figure Conventions................................................................................................... 3-5
CCM Register Summary ......................................................................................................... 3-6
CCMR Field Descriptions..................................................................................................... 3-10
PDR0 Field Descriptions ...................................................................................................... 3-13
PDR1 Field Descriptions ...................................................................................................... 3-15
RCSR Field Descriptions ...................................................................................................... 3-16
MPCTL Field Descriptions ................................................................................................... 3-18
UPCTL Field Descriptions.................................................................................................... 3-19
SPCTL Field Descriptions .................................................................................................... 3-21
COSR Field Descriptions...................................................................................................... 3-23
GR0–CGR2 Field Descriptions ............................................................................................ 3-25
CGR0 Register Mapping....................................................................................................... 3-25
CGR1 Register Mapping....................................................................................................... 3-26
CGR2 Register Mapping....................................................................................................... 3-26
WIMR0 Field Descriptions ................................................................................................... 3-27
LDC Field Descriptions ........................................................................................................ 3-28
DPTC Field Descriptions ...................................................................................................... 3-29
LTR0 Field Descriptions ....................................................................................................... 3-29
LTR1 Field Descriptions ....................................................................................................... 3-30
LTR Field Descriptions ......................................................................................................... 3-32
LTR3 Field Descriptions ....................................................................................................... 3-33
LTBR0 Field Descriptions .................................................................................................... 3-34
LTBR1 Field Descriptions .................................................................................................... 3-35
PMCR0 Field Descriptions ................................................................................................... 3-36
PMCR1 Field Descriptions ................................................................................................... 3-39
PDR2 Field Descriptions ...................................................................................................... 3-40
DVFS Transition Descriptions .............................................................................................. 3-54
dvfs_w_sigs Connectivity ..................................................................................................... 3-55
Low Power FSM Transition Descriptions............................................................................. 3-58
FSM Control Loop Stages..................................................................................................... 3-62
IOMUX Memory Map ............................................................................................................ 4-4
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
ciii
Tables
Table
Number
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
7-1
8-1
8-2
8-3
8-4
Title
Page
Number
Register Figure Conventions................................................................................................... 4-4
IOMUXC Register Summary.................................................................................................. 4-5
GPR Register Field Description.............................................................................................. 4-6
Hardware Mode Definitions by GPR Bit Position.................................................................. 4-6
SW_MUX_CTL Register Field Descriptions ....................................................................... 4-10
Multiplexing Priorities .......................................................................................................... 4-39
ATA Signal Routing Options using Hardware Modes .......................................................... 4-40
SW_PAD_CTL Bit Descriptions .......................................................................................... 4-42
Software Controllable Signals Register 0 Field Descriptions............................................... 4-80
Software Controllable Signals Registers 1............................................................................ 4-81
Software Controllable Signals Registers 2............................................................................ 4-82
Software Controllable Signals Registers 3............................................................................ 4-83
EMI Signal Multiplexing ...................................................................................................... 4-84
GPIO Memory Map ................................................................................................................ 5-4
Register Conventions .............................................................................................................. 5-4
GPIO Register Summary ........................................................................................................ 5-5
DR Field Descriptions............................................................................................................. 5-7
GDIR Field Descriptions ........................................................................................................ 5-8
PSR Field Descriptions ........................................................................................................... 5-9
ICR1 Field Descriptions........................................................................................................ 5-10
ICR2 Field Descriptions........................................................................................................ 5-10
IMR Field Descriptions......................................................................................................... 5-11
ISR Field Descriptions .......................................................................................................... 5-12
EVNTBUS Signals Used For Performance Modeling............................................................ 6-5
Trace Signals Decode.............................................................................................................. 6-8
ARM11 L2 Cache Events To EVTMON ................................................................................ 6-9
ARM11 Platform Debug Centric Signal Visibility ............................................................... 6-10
Interrupt Source Of Debug Signals ....................................................................................... 6-11
ECT Functionality Depending on the i.MX31 and i.MX31L Security Mode ...................... 6-12
ARM CTI Signal Input Assignments.................................................................................... 6-20
ARM CTI Signal Output Assignments ................................................................................. 6-20
SDMA Cross Trigger Input Assignments ............................................................................. 6-20
SDMA Cross Trigger Output Assignments .......................................................................... 6-21
MCU Cross Trigger Input Assignments ............................................................................... 6-21
MCU Cross Trigger Output Assignments............................................................................. 6-22
SJC Out Of Reset Modes ..................................................................................................... 6-29
System Boot Mode Selection.................................................................................................. 7-2
VFP11 Instruction Throughput and Latency Cycle Counts .................................................... 8-7
L2CC Burst Read Access Time .............................................................................................. 8-9
MAX Port Connections......................................................................................................... 8-10
CLKCTL Registers ............................................................................................................... 8-12
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
civ
Freescale Semiconductor
Tables
Table
Number
8-5
8-6
8-7
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
13-1
13-2
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
Title
Page
Number
CLKCTL General Purpose Control Bit (GP_CTRL) Usage ................................................ 8-12
L2_MEM_VAL Register Bit Assignments ........................................................................... 8-13
HMASTER Encodings.......................................................................................................... 8-19
AVIC Memory Map ................................................................................................................ 9-3
Register Figure Conventions................................................................................................... 9-5
AVIC Detailed Register Summary .......................................................................................... 9-6
INTCNTL Field Descriptions ............................................................................................... 9-10
NIMASK Descriptions.......................................................................................................... 9-12
INTENNUM Field Descriptions ........................................................................................... 9-13
INTDISNUM Field Descriptions.......................................................................................... 9-14
INTENABLEH/L Field Descriptions ................................................................................... 9-15
INTTYPEH/INTTYPEL Field Descriptions ........................................................................ 9-16
NIPRIORITY7 Register Field Descriptions ......................................................................... 9-17
NIPRIORITY6 Register Field Descriptions ......................................................................... 9-18
NIPRIORITY5 Register Field Descriptions ......................................................................... 9-19
NIPRIORITY4 Register Field Descriptions ......................................................................... 9-20
NIPRIORITY3 Register Field Descriptions ......................................................................... 9-21
NIPRIORITY2 Register Field Descriptions ......................................................................... 9-22
NIPRIORITY1 Register Field Descriptions ......................................................................... 9-23
NIPRIORITY0 Register Field Descriptions ......................................................................... 9-24
NIVECSR Register Field Descriptions................................................................................. 9-25
FIVECSR Register Field Descriptions ................................................................................. 9-26
INTSRCH/INTSRCL Field Descriptions ............................................................................. 9-27
INTFRCH/INTFRCL Field Descriptions ............................................................................. 9-28
NIPNDH/NIPNDL Field Descriptions ................................................................................. 9-29
FIPNDH/FIPNDL Field Descriptions................................................................................... 9-30
VECTOR0–VECTOR63 Field Descriptions ........................................................................ 9-31
IIM Fuse Definition for i.MX31 ........................................................................................... 13-2
SILICON_REV Settings ....................................................................................................... 13-4
L2CC Master Port Transactions for 2 Master Port System................................................... 15-4
L2CC Burst Read Access Time .......................................................................................... 15-12
Register Figure Conventions............................................................................................... 15-14
L2CC Memory Map............................................................................................................ 15-15
L2CC Register Summary .................................................................................................... 15-16
ID Register Field Descriptions............................................................................................ 15-18
Cache Type Register Field Descriptions ............................................................................. 15-19
L2CC Control Register Field Descriptions ......................................................................... 15-20
Aux Ctrl Configuration Examples ...................................................................................... 15-20
L2CC Auxiliary Control Register Field Descriptions......................................................... 15-21
L2CC Cache Maintenance Operations................................................................................ 15-23
Line Tag Register Field Descriptions.................................................................................. 15-29
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
cv
Tables
Table
Number
14-13
14-14
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
16-1
16-2
16-3
16-4
16-5
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
Title
Page
Number
L2CC Debug Control Register............................................................................................ 15-30
L2CC Auxiliary Control Register Field Descriptions......................................................... 15-31
EVTMON Memory Map ...................................................................................................... 16-2
Register Figure Conventions................................................................................................. 16-2
EVTMON Register Summary............................................................................................... 16-3
EMMC Register Field Descriptions...................................................................................... 16-5
EMCS Field Descriptions ..................................................................................................... 16-6
EMCCx Field Descriptions ................................................................................................... 16-7
EVTMON Event Descriptions .............................................................................................. 16-7
EMCx Descriptions............................................................................................................... 16-8
CHOOSEN_SLAVE Encoding ........................................................................................... 17-14
EMI Output Summary......................................................................................................... 17-14
EMI Signal Properties ......................................................................................................... 17-27
EMI Registers Definition .................................................................................................... 17-35
EMI Memory Map .............................................................................................................. 17-35
M3IF Memory Map .............................................................................................................. 18-5
M3IF Memory Space Summary............................................................................................ 18-6
Register Figure Conventions................................................................................................. 18-7
M3IF Register Summary....................................................................................................... 18-7
M3IF Control Register Field Descriptions.......................................................................... 18-10
M3IF Snooping Configuration Register 0 Field Descriptions ............................................ 18-12
SWSZ Field Descriptions.................................................................................................... 18-12
M3IF Snooping Configuration Register 1 Field Descriptions ............................................ 18-13
M3IF Snooping Configuration Register 2 Field Descriptions ............................................ 18-14
M3IF Snooping Status Register 0 Field Descriptions......................................................... 18-15
M3IF Snooping Status Register 0 Field Descriptions......................................................... 18-16
M3IF Lock General Register Field Descriptions ................................................................ 18-17
WEIM Signal Properties ....................................................................................................... 19-4
WEIM Detailed Signal Descriptions..................................................................................... 19-5
Boot Configuration Settings.................................................................................................. 19-7
WEIM Out/in Data in Case AHB Out/in Data is 0xB3B2B1B0 .......................................... 19-7
WEIM Memory Map ............................................................................................................ 19-9
WEIM Chip Selection Memory Map.................................................................................. 19-10
Register Figure Conventions............................................................................................... 19-10
WEIM Register Summary................................................................................................... 19-11
Chip Select x Upper Control Register Field Descriptions .................................................. 19-14
PSZ Bit Field Values ........................................................................................................... 19-16
WSC Bit Field Values ......................................................................................................... 19-17
Chip Select x Lower Control Register Field Descriptions.................................................. 19-18
DSZ Bit Field Values .......................................................................................................... 19-20
Chip Select x Addition Control Register Field Descriptions .............................................. 19-22
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
cvi
Freescale Semiconductor
Tables
Table
Number
18-15
18-16
18-17
18-18
18-19
18-20
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
19-25
19-26
19-27
19-28
19-29
19-30
19-31
19-32
19-33
19-34
Title
Page
Number
LBN Bit Field Values .......................................................................................................... 19-23
CNC/CNC2 Bit Values........................................................................................................ 19-24
WEIM Control Register Field Descriptions........................................................................ 19-25
WEIM Operation Modes Field Settings.............................................................................. 19-26
AHB Burst Cycles Supported ............................................................................................. 19-29
External Memory Bursts Start Addresses for Some AHB Burst Accesses........................ 19-29
ESDCTL Signal Properties ................................................................................................... 20-7
ESDCTL Detailed Signal Description .................................................................................. 20-8
ESDCTL Memory Map Overview...................................................................................... 20-10
ESDCTL Memory Map ...................................................................................................... 20-11
Register Figure Conventions............................................................................................... 20-11
ESDCTL Register Summary............................................................................................... 20-12
Enhanced SDRAM Control Register (ESDCTL0/1) Field Descriptions............................ 20-16
COL Bit Field Encoding ..................................................................................................... 20-18
SREFR Bit Field Encoding ................................................................................................. 20-18
PWDT Bit Field Encoding.................................................................................................. 20-19
Burst Length Bit Field Encoding ........................................................................................ 20-19
PRCT Bit Field Encoding ................................................................................................... 20-19
ESDCFG0/ESDCFG1 Field Descriptions .......................................................................... 20-21
tWR Bit Field Encoding...................................................................................................... 20-23
Configurable SDRAM/LPDDR Timing Parameters........................................................... 20-24
tRC Bit Field Encoding....................................................................................................... 20-31
Enhanced SDRAM Control Register (ESDCTL0/1) Field Descriptions............................ 20-34
Enhanced MDDR Delay Line 1 Control Register (ESDCDLY1) Field Descriptions ........ 20-36
Enhanced MDDR Delay Line 2 Control Register (ESDCDLY2) Field Descriptions ........ 20-37
Enhanced MDDR Delay Line 3 Control Register (ESDCDLY3) Field Descriptions ........ 20-38
Enhanced MDDR Delay Line 4 Control Register (ESDCDLY4) Field Descriptions ........ 20-39
Enhanced MDDR Delay Line 5 Control Register (ESDCDLY5) Field Descriptions ........ 20-40
Enhanced MDDR Delay Line Cycle Length Debug Register (ESDCDLY1)
Field Descriptions .......................................................................................................... 20-41
JEDEC Standard Single/Double Data Rate SDRAMs........................................................ 20-41
Possibilities for Latency Hiding.......................................................................................... 20-43
CPU to SDRAM/LPDDR Translation ................................................................................ 20-48
Address Multiplexing by Column/Row Width for 16-Bit Devices..................................... 20-49
Address Multiplexing by Column/Row Width for 32-Bit Devices..................................... 20-50
Bank Address Bit Assignment ............................................................................................ 20-51
ESDCTL Low Power Operating Modes ............................................................................. 20-53
SDRAM (SDR and LPDDR) Command Encoding ............................................................ 20-66
SDRAM/LPDDR Burst Access Support............................................................................. 20-69
SDRAM Command Sequence for Burst Accesses ............................................................. 20-98
SDRAM Mode Register Description ................................................................................ 20-109
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
cvii
Tables
Table
Number
19-35
19-36
19-37
19-38
19-39
19-40
19-41
19-42
19-43
19-44
19-45
19-46
19-47
19-48
19-49
19-50
19-51
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
20-21
20-22
20-23
20-24
Title
Page
Number
Example Address Calculation for Mode Register............................................................. 20-110
Single 4Mx16 Control Register Value .............................................................................. 20-110
Single 8Mx16 Control Register Value ...............................................................................20-111
Single 16Mx16 Control Register Value ............................................................................ 20-112
Single 32Mx16 Control Register Value ............................................................................ 20-113
Single 64Mx16 Control Register Value ............................................................................ 20-114
Dual 4Mx16 Control Register Value................................................................................. 20-115
Dual 8Mx16 Control Register Value................................................................................. 20-116
Dual 16Mx16 Control Register Value............................................................................... 20-117
Single 2Mx32 Control Register Value .............................................................................. 20-118
Single 4Mx32 Control Register Value .............................................................................. 20-119
Single 8Mx32 Control Register Value .............................................................................. 20-120
Single 16Mx32 Control Register Value ............................................................................ 20-121
Single 32Mx32 Control Register Value ............................................................................ 20-122
Single 64Mx32 Control Register Value ............................................................................ 20-123
Single 16Mx32 Control Register Value ............................................................................ 20-124
Single 32Mx16 Control Register Value ............................................................................ 20-125
NANDFC Signal Properties.................................................................................................. 21-4
NANDFC Detailed Signal Descriptions ............................................................................... 21-5
Data (Buffer) Organization in Memory ................................................................................ 21-6
Spare Area Buffer (with X8 I/O Bus) ................................................................................... 21-7
Spare Area Buffer (with X16 I/O Bus) ................................................................................. 21-8
NANDFC Register Memory Map......................................................................................... 21-9
Register Figure Conventions............................................................................................... 21-10
NANDFC Register Summary ............................................................................................. 21-11
NFC_BUFSIZE Register Field Descriptions...................................................................... 21-12
RAM Buffer Address Field Descriptions............................................................................ 21-13
NAND Flash Address Register Field Descriptions............................................................. 21-13
NAND_Flash_CMD Register Field Descriptions............................................................... 21-14
NFC_Configuration Register Field Descriptions................................................................ 21-14
ECC_STATUS_RESULT Register Field Descriptions ....................................................... 21-15
ECC_RSLT_MAIN_AREA Register Field Descriptions ................................................... 21-16
ECC_RSLT_MAIN_AREA Register Field Descriptions ................................................... 21-16
ECC_Rslt_Spare_Area Descriptions .................................................................................. 21-17
ECC_Rslt_Spare_Area Descriptions .................................................................................. 21-17
NAND Flash Write Protection Register Field Descriptions ............................................... 21-18
Unlock_Start_Blk_Add Register Field Descriptions .......................................................... 21-18
UNLOCK_END_BLK_ADD Register Field Descriptions ................................................ 21-19
NAND_FLASH_WR_PR_ST Register Field Descriptions................................................ 21-19
NAND_FLASH_CONFIG1 Register Field Descriptions................................................... 21-20
NAND_FLASH_CONFIG2 Register Field Descriptions................................................... 21-21
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
cviii
Freescale Semiconductor
Tables
Table
Number
20-25
20-26
20-27
20-28
20-29
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
21-14
21-15
21-16
21-17
21-18
21-19
21-20
21-21
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
23-1
23-2
23-3
23-4
23-5
23-6
23-7
Title
Page
Number
NAND FLASH Controller Operating Modes ..................................................................... 21-22
NAND Flash Burst Access Support.................................................................................... 21-29
ECC Code/Result Readability............................................................................................. 21-43
Write Protection for Main/Spare RAM Buffer ................................................................... 21-44
Examples for NANDFC Pin Configuration for Selected Memory Devices ....................... 21-48
PCMCIA Signal Descriptions ............................................................................................... 22-3
BVD1 and BVD2 Descriptions............................................................................................. 22-6
PCMCIA Controller Memory Map...................................................................................... 22-6
Register Figure Conventions................................................................................................. 22-7
PCMCIA Controller Register Summary ............................................................................... 22-8
PIPR Field Descriptions...................................................................................................... 22-10
PSCR Field Descriptions .................................................................................................... 22-12
PER Field Descriptions ....................................................................................................... 22-13
PBR0–PBR4 Field Descriptions ......................................................................................... 22-15
POR0–POR4 Field Descriptions......................................................................................... 22-16
BSIZE Values ...................................................................................................................... 22-17
BSIZE Mask........................................................................................................................ 22-18
POFR0–POFR4 Field Descriptions .................................................................................... 22-19
PGCR Field Descriptions.................................................................................................... 22-20
PGSR Field Descriptions .................................................................................................... 22-21
PCMCIA I/F Interrupt Sources ........................................................................................... 22-22
Write Protect ....................................................................................................................... 22-24
IOIS16 and PPS Bit Relations ............................................................................................ 22-25
Data and Control Signal Relations...................................................................................... 22-25
Data, Control and Address Relations in TrueIDE Mode .................................................... 22-26
PCMCIA Card TrueIDE Signal Names and Assignments.................................................. 22-27
1-Wire Memory Map ............................................................................................................ 23-2
Register Figure Conventions Key to Register Fields............................................................ 23-3
1-Wire Register Summary..................................................................................................... 23-3
Control Register Field Descriptions...................................................................................... 23-4
Time Divider Register Field Descriptions ............................................................................ 23-5
System Timing Requirements ............................................................................................... 23-5
Examples of Relative Time Imprecision............................................................................... 23-7
Reset Register Field Descriptions ......................................................................................... 23-7
Signal Properties ................................................................................................................... 24-4
Timing Parameters ................................................................................................................ 24-6
Timing Parameters PIO Read................................................................................................ 24-7
Timing Parameters PIO Write............................................................................................... 24-8
Timing Parameters MDMA Read and Write ........................................................................ 24-9
Timing Parameters for UDMA in Burst.............................................................................. 24-11
Timing Parameters UDMA Out Burst ................................................................................ 24-13
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
cix
Tables
Table
Number
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
24-1
24-2
24-3
24-4
24-5
24-6
24-7
24-8
24-9
24-10
24-11
24-12
24-13
24-14
24-15
25-1
25-2
25-3
25-4
25-5
25-6
25-7
25-8
25-9
25-10
25-11
25-12
25-13
25-14
26-3
26-4
26-5
26-6
Title
Page
Number
ATA Memory Map .............................................................................................................. 24-14
Register Figure Conventions............................................................................................... 24-17
ATA Register Summary ...................................................................................................... 24-17
ATA_CONTROL Register Field Descriptions.................................................................... 24-28
INTERRUPT_PENDING Register Field Descriptions....................................................... 24-29
INTERRUPT_ENABLE Register Field Descriptions ........................................................ 24-30
INTERRUPT_CLEAR Register Field Descriptions ........................................................... 24-31
Drive Registers Connected to ATA Bus.............................................................................. 24-32
CSPI–Detailed Signal Descriptions ...................................................................................... 25-2
CSPI Memory Map ............................................................................................................... 25-3
Register Figure Conventions................................................................................................. 25-3
CSPI Register Summary ....................................................................................................... 25-4
RXDATA Register Field Descriptions .................................................................................. 25-6
TXDATA Register Field Descriptions .................................................................................. 25-7
CONREG Register Field Descriptions ................................................................................. 25-8
INTREG Register Field Descriptions ................................................................................. 25-11
DMAREG Register Field Descriptions............................................................................... 25-12
STATREG Register Field Descriptions............................................................................... 25-13
PERIODREG Register Field Descriptions ......................................................................... 25-15
TESTREG Register Field Descriptions .............................................................................. 25-16
CSPI Signal Primary and Alternative Pin Assignments ..................................................... 25-26
CSPI Pin Configuration ...................................................................................................... 25-27
Recommended CSPI Signal Pad Configuration.................................................................. 25-28
MIR Packet Structure............................................................................................................ 26-3
FIR Packet Structure ............................................................................................................. 26-4
MIR Modulation ................................................................................................................... 26-5
4 PPM Mapping .................................................................................................................... 26-5
Signal Properties ................................................................................................................... 26-6
FIR Memory Map ................................................................................................................. 26-7
Register Figure Conventions................................................................................................. 26-8
FIR Register Summary.......................................................................................................... 26-9
FIR Transmitter Control Register Field Descriptions ......................................................... 26-10
FIR Transmitter Count Register Field Descriptions ........................................................... 26-12
FIR Receiver Control Register Field Descriptions ............................................................. 26-13
FIR Transmit Status Register Descriptions ......................................................................... 26-14
FIR Receive Status Register Field Descriptions ................................................................. 26-15
FIR Control Register Field Descriptions ............................................................................ 26-17
I2C Memory Map .................................................................................................................. 27-4
I2C Register Summary .......................................................................................................... 27-6
I2C Address Register Field Descriptions .............................................................................. 27-7
I2C Frequency Register Field Descriptions .......................................................................... 27-8
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
cx
Freescale Semiconductor
Tables
Table
Number
26-7
26-8
26-9
26-10
26-11
27-1
27-2
27-3
27-4
27-5
27-6
27-7
27-8
28-1
28-2
28-3
28-4
28-5
28-6
28-7
29-1
29-2
29-3
29-4
29-5
29-6
29-7
29-8
29-9
29-10
29-11
29-12
29-13
29-14
29-15
29-16
29-17
29-18
29-19
29-20
30-1
Title
Page
Number
IFDR Register Field Values .................................................................................................. 27-8
I2C Control Register Field Descriptions ............................................................................... 27-9
I2C Status Register Field Descriptions................................................................................ 27-10
I2C Data Register Field Descriptions.................................................................................. 27-11
I2C Bus Timing Parameters ................................................................................................ 27-19
Keypad Port Column Modes................................................................................................. 28-3
KPP Memory Map ................................................................................................................ 28-3
Register Figure Conventions................................................................................................. 28-4
KPP Register Summary ........................................................................................................ 28-4
Keypad Control Register Field Descriptions ........................................................................ 28-5
Keypad Status Register Field Descriptions........................................................................... 28-6
Keypad Data Direction Register Field Descriptions............................................................. 28-8
Keypad Data Register Field Descriptions ............................................................................. 28-8
MSHC Memory Map ............................................................................................................ 29-4
Register Figure Conventions................................................................................................. 29-4
MSHC Register Summary .................................................................................................... 29-5
MSHC Data Endianness and Connection to IP Bus ............................................................. 29-5
Timeout Register Field Descriptions .................................................................................... 29-7
Gasket Interrupt Status/Clear Register Field Descriptions ................................................... 29-7
Gasket Interrupt Enable Register Field Descriptions............................................................ 29-9
Signal Properties ................................................................................................................... 30-3
SDHC Memory Map............................................................................................................. 30-4
Register Figure Conventions................................................................................................. 30-5
SDHC Register Summary ..................................................................................................... 30-6
SDHC Clock Control Register Field Descriptions ............................................................... 30-9
SDHC Status Register Field Descriptions........................................................................... 30-11
SDHC Clock Rate Register Field Descriptions .................................................................. 30-15
SDHC Command and Data Control Register Field Descriptions ....................................... 30-16
MMC/SD Response Time Out Register Field Descriptions ............................................... 30-18
SDHC Read Time Out Register Field Descriptions............................................................ 30-19
SDHC Block Length Register Field Descriptions .............................................................. 30-20
SDHC Number of Blocks Register Field Descriptions....................................................... 30-21
SDHC Revision Number Register Field Descriptions ........................................................ 30-22
SDHC Interrupt Control Register Field Descriptions ......................................................... 30-23
Interrupt Mechanisms ......................................................................................................... 30-25
SDHC Command Number Register Field Descriptions ..................................................... 30-27
SDHC Command Argument Register Field Descriptions .................................................. 30-28
SDHC Response FIFO Register Field Descriptions ........................................................... 30-29
SDHC Buffer Access Register Field Descriptions.............................................................. 30-30
Commands for MMC/SD/SDIO ......................................................................................... 30-53
SIM Top Level Interrupt Summary....................................................................................... 31-2
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
cxi
Tables
Table
Number
30-2
30-3
30-4
30-5
30-6
30-7
30-8
30-9
30-10
30-11
30-12
30-13
30-14
30-15
30-16
30-17
30-18
30-19
30-20
30-21
30-22
30-23
30-24
30-25
30-26
30-27
30-28
30-29
30-30
30-31
30-32
30-33
30-34
30-35
30-36
30-37
31-1
31-2
31-3
31-4
31-5
Title
Page
Number
SIM Transmitter Interrupt Summary .................................................................................... 31-3
SIM Receiver Interrupt Summary......................................................................................... 31-4
SIM Card Detect Interrupts................................................................................................... 31-4
SIM General Purpose Counter Interrupts.............................................................................. 31-5
Signal Properties ................................................................................................................... 31-5
SIM Memory Map ................................................................................................................ 31-7
Register Figure Conventions................................................................................................. 31-8
SIM Register Summary......................................................................................................... 31-9
SIM Port1 Control Register Field Descriptions.................................................................. 31-12
SIM Setup Register Field Descriptions............................................................................... 31-14
SIM Port 1 Detect Register Field Descriptions................................................................... 31-14
SIM Port1 Transmit Buffer Register Field Descriptions .................................................... 31-15
SIM Port 1 Receive Buffer Register Field Descriptions ..................................................... 31-16
SIM Port0 Control Register Field Descriptions.................................................................. 31-17
SIM Control Register Field Descriptions............................................................................ 31-18
SIM Clock Select Register Field Descriptions ................................................................... 31-21
SIM Receive Threshold Register Field Descriptions.......................................................... 31-22
SIM Enable Register Field Descriptions............................................................................. 31-22
SIM Transmit Status Register Field Descriptions............................................................... 31-23
SIM Receive Status Register Field Descriptions ................................................................ 31-25
SIM Interrupt Mask Register Field Descriptions ................................................................ 31-27
SIM Port0 Transmit Buffer Register Field Descriptions .................................................... 31-29
SIM Port0 Receive Buffer Register Field Descriptions...................................................... 31-30
SIM Port0 Detect Register Field Descriptions.................................................................... 31-31
SIM Data Format Register Field Descriptions.................................................................... 31-32
SIM Transmit Threshold Register Field Descriptions ........................................................ 31-33
SIM Transmit Guard Control Register Field Descriptions ................................................. 31-34
SIM Open Drain Configuration Control Register Field Descriptions ................................ 31-35
SIM Reset Control Register Field Descriptions.................................................................. 31-36
SIM Character Wait Time Register Field Descriptions ...................................................... 31-37
SIM General Purpose Counter Register Field Descriptions ............................................... 31-38
SIM Divisor Register Field Descriptions............................................................................ 31-39
SIM Block Wait Time Register Field Descriptions ............................................................ 31-40
SIM Block Guard Time Register Field Descriptions .......................................................... 31-40
SIM Block Wait Time Register HIGH Field Descriptions ................................................. 31-41
SIM Module Interrupts........................................................................................................ 31-63
Interface Signals.................................................................................................................... 32-3
UART Memory Map ............................................................................................................. 32-6
Register Figure Convention .................................................................................................. 32-8
UART Register Summary ..................................................................................................... 32-8
UART Receiver Register Field Descriptions ...................................................................... 32-13
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
cxii
Freescale Semiconductor
Tables
Table
Number
31-6
31-7
31-8
31-9
31-10
31-11
31-12
31-13
31-14
31-15
31-16
31-17
31-18
31-19
31-20
31-21
31-22
31-23
31-24
31-25
31-26
31-27
31-28
31-29
31-30
31-31
31-32
32-1
32-2
32-3
32-4
32-5
32-6
32-7
32-8
32-9
32-10
32-11
32-12
32-13
32-14
Title
Page
Number
UART Transmitter Register Field Descriptions.................................................................. 32-15
UART Control Register 1 Field Descriptions ..................................................................... 32-15
UART Control Register 2 Field Descriptions ..................................................................... 32-18
UART Control Register 3 Field Descriptions ..................................................................... 32-20
UART Control Register 4 Field Descriptions ..................................................................... 32-22
UART FIFO Control Register Field Descriptions .............................................................. 32-24
UART Status Register 1 Field Descriptions........................................................................ 32-26
UART Status Register 2 Field Descriptions........................................................................ 32-28
UART Escape Character Register Field Descriptions ........................................................ 32-30
UART Escape Timer Register Field Descriptions .............................................................. 32-31
UART BRM Incremental Register Field Descriptions ....................................................... 32-32
UART BRM Modulator Register Field Descriptions ......................................................... 32-33
UART Baud Rate Count Register Field Descriptions......................................................... 32-34
UART One Millisecond Register Field Descriptions ......................................................... 32-35
UART Test Register Field Descriptions.............................................................................. 32-36
Usage of Serial/Infrared Signal in DCE/DTE..................................................................... 32-37
Multiplexing at IC Top Level.............................................................................................. 32-38
4-Wire Connections in DCE Mode and with No IrDA....................................................... 32-40
2-Wire Connections in IrDA Mode Only............................................................................ 32-41
Interrupts and DMA ............................................................................................................ 32-42
RTS Edge Triggered Interrupt Truth Table ......................................................................... 32-46
DTR/DSR Edge Triggered Interrupt Truth Table ............................................................... 32-47
Detection Truth Table.......................................................................................................... 32-55
Majority Vote Results.......................................................................................................... 32-57
Baud Rate Automatic Detection ......................................................................................... 32-59
Escape Timer Scaling.......................................................................................................... 32-62
UART Low Power State Operation..................................................................................... 32-66
Register Conventions ............................................................................................................ 33-4
USB Module Memory Map .................................................................................................. 33-5
USB Control Register Field Descriptions ............................................................................. 33-9
OTGMIRROR Field Descriptions ...................................................................................... 33-12
Host Port 1 Pin Functions ................................................................................................... 33-13
ULPI/Serial Multiplexing for Host 2 .................................................................................. 33-14
Multiplexing for Host OTG ................................................................................................ 33-14
Port 1 TLL and PHY Mode Pin Connections ..................................................................... 33-17
Port 2 TLL and PHY Mode Pin Connections ..................................................................... 33-18
HOST1 Bypass Mode Pin Functions .................................................................................. 33-19
Interface Register Sets ........................................................................................................ 33-26
Device/Host Capability Registers ....................................................................................... 33-26
USBOTG Register Summary.............................................................................................. 33-28
ID Field Descriptions .......................................................................................................... 33-32
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
cxiii
Tables
Table
Number
32-15
32-16
32-17
32-18
32-19
32-20
32-21
32-22
32-23
32-24
32-25
32-26
32-27
32-28
32-29
32-30
32-31
32-32
32-33
32-34
32-35
32-36
32-37
32-38
32-39
32-40
32-41
32-42
32-43
32-44
32-45
32-46
32-47
32-48
32-49
32-50
32-51
32-52
32-53
32-54
32-55
Title
Page
Number
HWGENERAL Field Descriptions ..................................................................................... 33-33
HWHOST Field Descriptions ............................................................................................. 33-34
HWDEVICE Field Descriptions ......................................................................................... 33-35
HWTXBUF Field Descriptions .......................................................................................... 33-36
HWRXBUF Field Descriptions .......................................................................................... 33-36
HCSPARAMS Field Descriptions ...................................................................................... 33-38
HCCPARAMS Field Descriptions ...................................................................................... 33-40
DCCPARAMS Field Descriptions ...................................................................................... 33-42
USBCMD Field Descriptions ............................................................................................. 33-43
USBSTS Field Descriptions................................................................................................ 33-47
USBINTR Field Descriptions ............................................................................................. 33-50
FRINDEX Field Descriptions ............................................................................................. 33-52
PERIODICLISTBASE Field Descriptions ......................................................................... 33-53
DEVICEADDR Field Descriptions .................................................................................... 33-54
ASYNCLISTADDR Field Descriptions ............................................................................. 33-55
BURSTSIZE Field Descriptions ......................................................................................... 33-56
ULPI Field Descriptions ..................................................................................................... 33-59
PORTSCx Field Descriptions ............................................................................................. 33-61
OTGSC Field Descriptions ................................................................................................. 33-68
USBMODE Field Descriptions........................................................................................... 33-70
ENDPTSETUPSTAT Field Descriptions ............................................................................ 33-72
ENDPTPRIM Field Descriptions........................................................................................ 33-73
ENDPTFLUSH Field Descriptions ..................................................................................... 33-74
ENDPTSTAT Field Descriptions ........................................................................................ 33-75
ENDPTCOMPLETE Field Descriptions ............................................................................ 33-76
ENDPTCTRL0 Field Descriptions ..................................................................................... 33-76
ENDPTCTRL1–ENDPTCTRL15 Field Descriptions ........................................................ 33-78
Typ Field Value Definitions ................................................................................................ 33-83
iTD Register Summary ....................................................................................................... 33-83
Next Schedule Element Pointer .......................................................................................... 33-85
iTD Transaction Status and Control.................................................................................... 33-85
iTD Buffer Pointer Page 0 (Plus) ........................................................................................ 33-87
iTD Buffer Pointer Page 1 (Plus) ........................................................................................ 33-87
iTD Buffer Pointer Page 2 (Plus) ........................................................................................ 33-87
iTD Buffer Pointer Pages 3–6 ............................................................................................. 33-87
siTD Register Summary...................................................................................................... 33-88
Next Link Pointer................................................................................................................ 33-88
Endpoint and Transaction Translator Characteristics ......................................................... 33-89
Micro-frame Schedule Control ........................................................................................... 33-89
siTD Transfer Status and Control........................................................................................ 33-90
Buffer Page Pointer List (Plus) ........................................................................................... 33-91
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
cxiv
Freescale Semiconductor
Tables
Table
Number
32-56
32-57
32-58
32-59
32-60
32-61
32-62
32-63
32-64
32-65
32-66
32-67
32-68
32-69
32-70
32-71
32-72
32-73
32-74
32-75
32-76
32-77
32-78
32-79
32-80
32-81
32-82
32-83
32-84
32-85
32-86
32-87
32-88
32-89
32-90
32-91
32-92
32-93
32-94
32-95
32-96
Title
Page
Number
siTD Back Link Pointer ...................................................................................................... 33-92
qTD Register Summary ...................................................................................................... 33-93
D Next Element Transfer Pointer (DWord 0) ..................................................................... 33-93
TD Alternate Next Element Transfer Pointer (DWord 1) ................................................... 33-94
qTD Token (DWord 2) ........................................................................................................ 33-94
qTD Buffer Pointer(s) (DWords 3–7) ................................................................................. 33-98
Queue Head Register Summary .......................................................................................... 33-98
Queue Head DWord 0 ......................................................................................................... 33-99
Endpoint Characteristics: Queue Head DWord 1.............................................................. 33-100
Endpoint Capabilities: Queue Head DWord 2 .................................................................. 33-101
Current qTD Link Pointer ................................................................................................. 33-103
Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8, and 9) ................................. 33-103
FSTN Normal Path Pointer Field Descriptions................................................................. 33-104
FSTN Back Path Link Pointer Field Descriptions ............................................................ 33-105
Default Values of Operational Register Space.................................................................. 33-105
Default Port Routing Depending on EHCI HC CF Bit ..................................................... 33-108
Port Power Enable Control Rules ..................................................................................... 33-112
Behavior During Wake-up Events .................................................................................... 33-115
Example Worse-case Transaction Timing Components.................................................... 33-119
Operation of FRINDEX and SOFV (SOF Value Register)............................................... 33-122
Asynchronous Schedule SM Transition Actions .............................................................. 33-133
Typical Low-/Full-speed Transaction Times .................................................................... 33-134
NakCnt Field Adjustment Rules ....................................................................................... 33-136
Actions for Park Mode, Based on Endpoint Response and Residual Transfer State ........ 33-145
Example Periodic Reference Patterns for Interrupt Transfers with 2ms Poll Rate........... 33-149
Ping Control State Transition Table .................................................................................. 33-150
Ping State Encoding .......................................................................................................... 33-150
Interrupt IN/OUT Do Complete Split State Execution Criteria........................................ 33-164
Table 38 Initial Conditions for OUT siTD's TP and T-count Fields ................................. 33-173
Transaction Position (TP)/Transaction Count (T-Count) Transition Table....................... 33-173
Table 40 Summary siTD Split Transaction State .............................................................. 33-176
Example Case 2a—Software Scheduling siTDs for an IN Endpoint................................ 33-178
Summary of Transaction Errors ........................................................................................ 33-182
Table 43 Summary Behavior of EHCI Host Controller on Host System Errors............... 33-185
Speed Detection Translation ............................................................................................. 33-187
Split State Handshake Conditions..................................................................................... 33-188
dQH Register Summary .................................................................................................... 33-193
Endpoint Capabilities/Characteristics ............................................................................... 33-194
Next dTD Pointer .............................................................................................................. 33-195
Multiple Mode Control (HCCPARAMS) ......................................................................... 33-196
Next dTD Pointer .............................................................................................................. 33-196
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
cxv
Tables
Table
Number
32-97
32-98
32-99
32-100
32-101
32-102
32-103
32-104
32-105
32-106
32-107
32-108
32-109
32-110
32-111
33-1
33-2
33-3
33-4
33-5
33-6
33-7
33-8
33-9
33-10
34-1
34-2
34-3
34-4
34-5
34-6
34-7
34-8
34-9
34-10
34-11
34-12
34-13
34-14
34-15
35-1
Title
Page
Number
dTD Token ........................................................................................................................ 33-197
Table 49 dTD Buffer Page Pointer List............................................................................. 33-198
Device Controller State Information Bits ......................................................................... 33-200
Device Controller Endpoint Initialization......................................................................... 33-204
Device Controller Stall Response Matrix ......................................................................... 33-204
Variable Length Transfer Protocol Example (ZLT = 0) .................................................... 33-207
Variable Length Transfer Protocol Example (ZLT = 1) .................................................... 33-207
Interrupt/Bulk Endpoint Bus Response Matrix................................................................. 33-208
Control Endpoint Bus Response Matrix ........................................................................... 33-210
Isochronous Endpoint Bus Response Matrix .................................................................... 33-213
Device Error Matrix .......................................................................................................... 33-218
Error Descriptions ............................................................................................................. 33-218
High Frequency Interrupt Events...................................................................................... 33-218
Low Frequency Interrupt Events....................................................................................... 33-219
Error Interrupt Events ....................................................................................................... 33-219
External EPIT Signals ........................................................................................................... 34-3
Module Signal Description ................................................................................................... 34-4
EPIT Memory Map ............................................................................................................... 34-5
Register Figure Conventions................................................................................................. 34-6
EPIT Register Summary ....................................................................................................... 34-6
EPITCR Register Field Descriptions .................................................................................... 34-8
EPTISR Register Field Descriptions................................................................................... 34-10
EPITLR Register Field Descriptions .................................................................................. 34-11
EPITCMPR Register Field Descriptions ............................................................................ 34-12
EPITCNT Register Field Descriptions ............................................................................... 34-13
External Signal Description .................................................................................................. 35-5
Module Signal Description ................................................................................................... 35-6
GPT Memory Map ................................................................................................................ 35-8
Register Figure Conventions................................................................................................. 35-8
GPT Register Summary ........................................................................................................ 35-9
GPT Control Register Field Descriptions ........................................................................... 35-11
GPT Prescaler Register Field Descriptions ......................................................................... 35-14
GPT Status Register Field Descriptions.............................................................................. 35-15
GPT Interrupt Register Field Descriptions.......................................................................... 35-16
GPT Output Compare Register 1 Field Descriptions.......................................................... 35-17
GPT Output Compare Register 2 Field Descriptions.......................................................... 35-18
GPT Output Compare Register 3 Field Descriptions.......................................................... 35-18
GPT Input Capture Register 1 Field Descriptions .............................................................. 35-19
GPT Input Capture Register 2 Field Descriptions .............................................................. 35-20
GPT Counter Register Field Descriptions........................................................................... 35-20
External Signals .................................................................................................................... 36-3
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
cxvi
Freescale Semiconductor
Tables
Table
Number
35-2
35-3
35-4
35-5
35-6
35-7
35-8
35-9
35-10
35-11
36-1
36-2
36-3
36-4
36-5
36-6
36-7
36-8
36-9
36-10
36-11
36-12
36-13
36-14
37-1
37-2
37-3
37-4
37-5
37-6
37-7
37-8
38-1
38-2
38-3
38-4
38-5
38-6
38-7
38-8
38-9
Title
Page
Number
Module Boundary Signal Description................................................................................... 36-4
PWM Memory Map .............................................................................................................. 36-5
Register Figure Conventions................................................................................................. 36-6
PWM Register Summary ...................................................................................................... 36-7
PWMCR Field Descriptions ................................................................................................. 36-8
PWMSR Field Descriptions................................................................................................ 36-10
PWMIR Field Descriptions................................................................................................. 36-11
PWMSAR Field Descriptions ............................................................................................. 36-12
PWMPR Field Descriptions................................................................................................ 36-13
PWMCNR Field Descriptions ............................................................................................ 36-14
RTC Register Memory Map.................................................................................................. 37-3
Register Figure Conventions................................................................................................. 37-4
RTC Register Summary ........................................................................................................ 37-4
RTC Hours and Minutes Counter Register Field Descriptions............................................. 37-6
RTC Seconds Counter Register Field Descriptions .............................................................. 37-7
RTC Hours and Minutes Alarm Register Field Descriptions ............................................... 37-8
RTC Seconds Alarm Register Field Descriptions................................................................. 37-9
RTC Control Register Field Descriptions ........................................................................... 37-10
RTC Interrupt Status Register Field Descriptions............................................................... 37-11
RTC Interrupt Enable Register Field Descriptions ............................................................. 37-13
RTC Stopwatch Minutes Register Field Descriptions ........................................................ 37-15
RTC Days Counter Register Field Descriptions ................................................................. 37-16
RTC Day Alarm Register Field Descriptions ..................................................................... 37-17
Sampling Timer Frequencies .............................................................................................. 37-18
Signal Properties ................................................................................................................... 38-2
WDOG Module Port List ...................................................................................................... 38-3
WDOG Memory Map ........................................................................................................... 38-4
Register Figure Conventions................................................................................................. 38-4
WDOG Register Summary ................................................................................................... 38-5
WCR Register Descriptions .................................................................................................. 38-6
Watchdog Service Register Description................................................................................ 38-7
WRSR Descriptions .............................................................................................................. 38-8
AIPS Signals ......................................................................................................................... 39-8
Transfer Type Encoding ...................................................................................................... 39-11
hburst[2:0] Burst Type Encoding ........................................................................................ 39-11
Transfer Size Encoding ....................................................................................................... 39-12
hbstrb[7:0] to Byte Address Mappings, 64-bit AHB .......................................................... 39-12
hbstrb[3:0] to Byte Address Mappings, 32-bit AHB .......................................................... 39-12
Off-Platform IPS Peripheral Location Decoder for AIPS MAP #1.................................... 39-14
Off-Platform IPS Peripheral Location Decoder for AIPS MAP #2.................................... 39-15
On-Platform IPS Peripheral Location Decoder for AIPS MAP #1 .................................... 39-18
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
cxvii
Tables
Table
Number
38-10
38-11
38-12
38-13
38-14
38-15
38-16
38-17
38-18
38-19
38-20
39-1
39-2
39-3
39-4
39-5
39-6
39-7
39-8
39-9
40-1
40-2
40-3
40-4
40-5
40-6
40-7
40-8
40-9
40-10
40-11
40-12
40-14
40-13
40-15
40-17
40-16
40-18
40-20
40-19
40-21
Title
Page
Number
On-Platform IPS Peripheral Location Decoder for AIPS MAP #2 .................................... 39-18
Off-Platform Peripheral Size Control ................................................................................. 39-20
AIPS A and AIPS B Memory Map..................................................................................... 39-21
Register Figure Conventions............................................................................................... 39-22
AIPS Register Summary ..................................................................................................... 39-23
Master Protection Field Descriptions.................................................................................. 39-25
Peripheral Access Control Register Field Descriptions ...................................................... 39-29
Off-Platform Peripheral Access Control Register Field Descriptions ................................ 39-32
AIPS Parameters and Defaults............................................................................................ 39-33
Read Access Delay Through AIPS ..................................................................................... 39-53
Write Access Delay Through AIPS .................................................................................... 39-53
MAX Signals......................................................................................................................... 40-4
MAX Memory Map ............................................................................................................ 40-10
Register Figure Conventions............................................................................................... 40-11
MAX Detailed Register Summary...................................................................................... 40-12
Master Priority Register (MPR0–MPR4) ........................................................................... 40-14
Master Priority Register Descriptions................................................................................. 40-14
Slave General Purpose Control Register Descriptions ....................................................... 40-16
Master General Purpose Control Register Descriptions ..................................................... 40-18
MAX Address Map............................................................................................................. 40-33
PCU States ............................................................................................................................ 41-9
Channel Enable RAM Programming Example ................................................................... 41-16
Runnable Channel Selection Control .................................................................................. 41-18
Channel Switching Decision with a Yield, Yield(ge), or Done .......................................... 41-19
CRC Processing Summary.................................................................................................. 41-26
SDMA in Debug Mode ....................................................................................................... 41-33
Clocking Scheme ................................................................................................................ 41-34
Submodules Clocks............................................................................................................. 41-34
Power Modes....................................................................................................................... 41-36
AP Memory Map ................................................................................................................ 41-37
Register Figure Conventions............................................................................................... 41-39
AP SDMA Register Summary ............................................................................................ 41-39
INTR Field Descriptions ..................................................................................................... 41-44
MC0PTR Field Descriptions ............................................................................................... 41-44
STOP_STAT Field Descriptions ......................................................................................... 41-45
EVTOVR Field Descriptions .............................................................................................. 41-46
HSTART Field Descriptions ............................................................................................... 41-46
DSPOVR Field Descriptions .............................................................................................. 41-47
EVTPEND Field Descriptions ............................................................................................ 41-48
HOSTOVR Field Descriptions ........................................................................................... 41-48
RESET Field Descriptions .................................................................................................. 41-49
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
cxviii
Freescale Semiconductor
Tables
Table
Number
40-22
40-23
40-25
40-24
40-26
40-27
40-28
40-29
40-30
40-32
40-31
40-33
40-34
40-35
40-36
40-37
40-38
40-39
40-40
40-41
40-42
40-43
40-44
40-46
40-45
40-47
40-49
40-48
40-50
40-51
40-53
40-52
40-54
40-56
40-55
40-57
40-59
40-58
40-60
40-61
40-63
Title
Page
Number
EVTERR Field Descriptions............................................................................................... 41-50
INTRMASK Field Description ........................................................................................... 41-51
EVTERRDBG Field Descriptions ...................................................................................... 41-52
PSW Field Descriptions ...................................................................................................... 41-52
CONFIG Register Field Descriptions ................................................................................. 41-53
ONCE_ENB Field Descriptions ......................................................................................... 41-54
ONCE_DATA Field Descriptions ....................................................................................... 41-55
ONCE_INSTR Field Descriptions...................................................................................... 41-56
ONCE_STAT Field Descriptions ........................................................................................ 41-57
ILLINSTADDR Field Descriptions .................................................................................... 41-59
ONCE_CMD Field Descriptions ........................................................................................ 41-59
CHN0ADDR Register Field Descriptions .......................................................................... 41-60
EVT_MIRROR Field Descriptions..................................................................................... 41-61
XTRIG_CONF1 Field Descriptions ................................................................................... 41-62
XTRIG_CONF2 Field Descriptions ................................................................................... 41-63
CHNPRIn Field Descriptions.............................................................................................. 41-65
CHNENBLn Field Descriptions ......................................................................................... 41-66
Layout of a Channel Context in Memory for SDMA ......................................................... 41-68
SDMA Instruction Memory Space ..................................................................................... 41-70
SDMA Data Memory Space ............................................................................................... 41-71
SDMA Internal Registers Memory Map............................................................................. 41-72
Register Figure Conventions............................................................................................... 41-73
SDMA Internal Registers Summary ................................................................................... 41-73
CCPTR Field Descriptions.................................................................................................. 41-77
MC0PTR Field Descriptions ............................................................................................... 41-77
CCR Field Descriptions ...................................................................................................... 41-78
EVENTS Field Descriptions ............................................................................................... 41-79
NCR Field Descriptions ...................................................................................................... 41-79
CCPRI Field Descriptions................................................................................................... 41-80
NCPRI Field Descriptions .................................................................................................. 41-81
ECTL Field Descriptions .................................................................................................... 41-82
ECOUNT Field Descriptions .............................................................................................. 41-82
EAA Field Descriptions ...................................................................................................... 41-84
EAM Field Descriptions ..................................................................................................... 41-85
EAB Field Descriptions ...................................................................................................... 41-85
ED Field Descriptions ......................................................................................................... 41-86
RTB Field Descriptions....................................................................................................... 41-87
EDM Field Descriptions ..................................................................................................... 41-87
TB Field Descriptions ......................................................................................................... 41-88
OSTAT Field Descriptions .................................................................................................. 41-90
ENDIANESS Field Descriptions ........................................................................................ 41-92
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
cxix
Tables
Table
Number
40-62
40-64
40-65
40-66
40-67
40-68
40-69
40-70
40-71
40-72
40-73
40-74
40-75
40-76
40-77
40-78
40-79
40-80
40-81
40-82
40-83
40-84
40-85
40-86
40-87
40-88
40-89
41-1
41-2
41-3
41-4
41-5
41-6
41-5
42-1
42-2
42-3
42-4
42-5
42-6
42-7
Title
Page
Number
MCHN0ADDR Field Descriptions ..................................................................................... 41-92
Functional Unit Registers.................................................................................................... 41-99
MS Field Descriptions ...................................................................................................... 41-102
STF Code Bit Field Descriptions ...................................................................................... 41-103
Burst DMA STF Instruction List ...................................................................................... 41-104
LDF Code Bit Field Descriptions ..................................................................................... 41-105
Burst DMA LDF Instruction List...................................................................................... 41-106
FIFO Read Configuration ................................................................................................. 41-108
FIFO Write Configuration................................................................................................. 41-109
Possibilities in ERROR READ BURST Mode..................................................................41-111
Possibilities in ERROR Mode........................................................................................... 41-112
PS Field Descriptions........................................................................................................ 41-115
STF Code Bits Field Descriptions .................................................................................... 41-116
Peripheral DMA STF Instruction List .............................................................................. 41-117
LDF Code Bits Descriptions ............................................................................................. 41-119
Peripheral DMA LDF Instruction List.............................................................................. 41-119
Immediate Errors with Peripheral DMA........................................................................... 41-120
Possibilities in ERROR READ Mode............................................................................... 41-121
Possibilities in ERROR Mode........................................................................................... 41-122
CA Descriptions ................................................................................................................ 41-124
Stf Instructions for CRC.................................................................................................... 41-126
ldf Instructions for CRC.................................................................................................... 41-126
OnCE Command Opcode Values...................................................................................... 41-128
Real-Time Debug Output Pins .......................................................................................... 41-147
SDMA Instruction List...................................................................................................... 41-151
AP/SDMA Clocks Configuration ..................................................................................... 41-212
Typical Data Transfers Summary...................................................................................... 41-213
Out-Of Band Steering Control Signals -obsc(n)[4:0] ........................................................... 42-5
SPBA Memory Map.............................................................................................................. 42-5
Peripherals Absolute Address ............................................................................................... 42-6
Register Figure Conventions................................................................................................. 42-7
SPBA PRR Register Summary ............................................................................................. 42-8
PRR Addresses...................................................................................................................... 42-8
Peripheral Right Register Field Descriptions...................................................................... 42-11
AUDMUX External Signals and Port Numbers ................................................................. 43-24
AUDMUX Memory Map.................................................................................................... 43-24
Register Figure Conventions............................................................................................... 43-25
AUDMUX Register Summary............................................................................................ 43-26
PTCR1 Field Descriptions .................................................................................................. 43-29
PDCR (Port 1) Field Descriptions ...................................................................................... 43-31
PTCR2 Field Descriptions .................................................................................................. 43-33
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
cxx
Freescale Semiconductor
Tables
Table
Number
42-8
42-9
42-10
42-11
42-12
42-13
42-14
42-15
42-16
42-17
42-18
42-19
44-1
44-2
44-3
44-4
44-5
44-6
44-7
44-8
44-9
44-10
44-11
44-12
44-13
44-14
44-15
44-16
44-17
44-18
44-19
44-20
44-21
44-22
44-23
44-24
44-25
44-26
44-27
44-28
44-29
Title
Page
Number
PDCR2 Field Descriptions.................................................................................................. 43-35
PTCR3 Field Descriptions .................................................................................................. 43-36
PDCR3 Field Descriptions.................................................................................................. 43-38
PTCR4 Field Descriptions .................................................................................................. 43-40
PDCR4 Field Descriptions.................................................................................................. 43-42
PTCR5 Field Descriptions .................................................................................................. 43-43
PDCR5 Field Descriptions.................................................................................................. 43-45
PTCR6 Field Descriptions .................................................................................................. 43-47
PDCR6 Field Descriptions.................................................................................................. 43-49
PTCR7 Field Descriptions .................................................................................................. 43-50
PDCR7 Field Descriptions.................................................................................................. 43-52
CNMCR Field Descriptions................................................................................................ 43-54
IPU Clocks ............................................................................................................................ 45-7
Manual Clock Gating Conditions ....................................................................................... 45-12
Basic IPU Features.............................................................................................................. 45-12
Sensor Interface Features .................................................................................................... 45-14
Preprocessing Features........................................................................................................ 45-15
Postprocessing Features ...................................................................................................... 45-16
Post-filtering Features ......................................................................................................... 45-17
Synchronous Display Interface Features............................................................................. 45-18
Asynchronous Display Interface Features .......................................................................... 45-19
Video from the System Memory on a VGA Synchronous Display .................................... 45-22
Video from the System Memory on a QVGA Synchronous Display ................................. 45-24
Signal Properties ................................................................................................................. 45-25
Display Interface Signals Usage ......................................................................................... 45-31
IPU Memory Map ............................................................................................................... 45-33
Register Figure Conventions............................................................................................... 45-37
IPU Register Summary ....................................................................................................... 45-38
IPU_CONF Field Descriptions ........................................................................................... 45-66
IPU_CHA_BUF0_RDY...................................................................................................... 45-68
IPU_CHA_BUF1_RDY Field Descriptions ....................................................................... 45-69
IPU_CHA_DB_MODE_SEL Field Descriptions ............................................................... 45-69
IPU_CHA_CUR_BUF Field Descriptions ......................................................................... 45-71
IPU_FS_PROC_FLOW Field Descriptions........................................................................ 45-72
IPU_FS_DISP_FLOW Field Descriptions ......................................................................... 45-74
IPU_TASKS_STAT Field Descriptions .............................................................................. 45-76
IPU_IMA_ADDR Field Descriptions................................................................................. 45-79
MEM_NU, ROW_NU, and WORD_NU Values............................................................... 45-79
IPU_IMA_DATA Field Description ................................................................................... 45-80
IC Parameters ...................................................................................................................... 45-82
Variable Channel Parameters for RGB/YUV Non-Interleaved Configuration................... 45-86
MCIMX31 and MCIMX31L Applications Processors, Rev. 2.4
Freescale Semiconductor
cxxi
Tables
Table
Number
44-30
44-31
44-32
44-33
44-34
44-35
44-36
44-37
44-38
44-39
44-40
44-41
44-42
44-43
44-44
44-45
44-46
44-47
44-48
44-49
44-50
44-51
44-52
44-53
44-54
44-55
44-56
44-57
44-58
44-59
44-60
44-61
44-62
44-63
44-64
44-65
44-66
44-67
44-68
44-69
44-70
Title
Page
Number
Constant Channel Parameters for RGB/YUV Non-Interleaved Configuration .................. 45-86
Variable Channel for Parameters for RGB/YUV Interleaved Configuration ..................... 45-89
Constant Channel Addressing Parameters for RGB/YUV Interleaved Configuration ....... 45-89
Constant Channel Formatting Parameters for YUV/RGB Interleaved Configuration ....... 45-93
Look-Up Table Memory Structure...................................................................................... 45-96
ADC Template Memory Structure ...................................................................................... 45-97
IPU_INT_CTRL_1 Field Descriptions ............................................................................. 45-103
IPU_INT_CTRL_2 Field Descriptions ............................................................................. 45-104
IPU_INT_CTRL_3 Field Descriptions ............................................................................. 45-105
IPU_INT_CTRL_4 Field Descriptions ............................................................................. 45-108
IPU_INT_CTRL_5 Field Descriptions ............................................................................. 45-109
IPU_INT_STAT_1 Field Descriptions.............................................................................. 45-112
IPU_INT_STAT_2 Field Descriptions.............................................................................. 45-113
IPU_INT_STAT_3 Field Descriptions.............................................................................. 45-114
IPU_INT_STAT_4 Field Descriptions.............................................................................. 45-117
IPU_INT_STAT_5 Field Descriptions.............................................................................. 45-118
IPU_BRK_CTRL_1 Field Descriptions ........................................................................... 45-121
IPU_BRK_CTRL_2 Field Descriptions ........................................................................... 45-123
IPU_BRK_STAT Field Descriptions ................................................................................ 45-124
IPU_DIAGB_CTRL Field Descriptions ........................................................................... 45-125
Diagnostic Bus Groups ..................................................................................................... 45-126
CSI_SENS_CONF Field Descriptions.............................................................................. 45-137
CSI_SENS_FRM_SIZE Field Descriptions ..................................................................... 45-139
CSI_ACT_FRM_SIZE Field Descriptions ....................................................................... 45-140
CSI_OUT_FRM_CTRL Field Descriptions ..................................................................... 45-140
CSI_TST_CTRL Field Descriptions................................................................................. 45-142
CSI_CCIR_CODE_1 Field Descriptions.......................................................................... 45-142
CSI_CCIR_CODE_2 Field Descriptions.......................................................................... 45-143
CSI_CCIR_CODE_3 Field Descriptions.......................................................................... 45-144
CSI_FLASH_STROBE_1 Field Descriptions .................................................................. 45-145
CSI_FLASH_STROBE_2 Field Descriptions .................................................................. 45-146
IC_CONF Field Descriptions............................................................................................ 45-147
IC_PRP_ENC_RSC Field Descriptions............................................................................ 45-149
IC_PRP_VF_RSC Field Descriptions .............................................................................. 45-150
IC_PP_RSC Field Descriptions ........................................................................................ 45-151
IC_CMBP_1 Field Descriptions ....................................................................................... 45-152
IC_CMBP_2 Field Descriptions ....................................................................................... 45-153
PF_CONF Field Descriptions ........................................................................................... 45-154
IDMAC_CONF Field Descriptions .................................................................................. 45-155
IDMAC_CHA_EN Field Descriptions ............................................................................. 45-156
IDMAC_CHA_PRI Field Descriptions ............................................................................ 45-157
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Tables
Table
Number
44-71
44-72
44-73
44-74
44-75
44-76
44-77
44-78
44-79
44-80
44-81
44-82
44-83
44-84
44-85
44-86
44-87
44-88
44-89
44-90
44-91
44-92
44-93
44-94
44-95
44-96
44-97
44-98
44-99
44-100
44-101
44-102
44-103
44-104
44-105
44-106
44-107
44-108
44-109
44-110
44-111
Title
Page
Number
IDMAC_CHA_BUSY Field Descriptions........................................................................ 45-158
SDC_COM_CONF Field Descriptions............................................................................. 45-159
SDC_GRAPH_WIND_CTRL Field Descriptions............................................................ 45-161
SDC_ALPHA_V Values ................................................................................................... 45-162
SDC_FG_POS Field Descriptions .................................................................................... 45-162
SDC_BG_POS Field Descriptions.................................................................................... 45-163
SDC_CUR_POS Field Descriptions ................................................................................. 45-164
SDC_CUR_POS Field Descriptions ................................................................................. 45-165
SDC_CUR_MAP Field Descriptions................................................................................ 45-166
SDC_HOR_CONF Field Descriptions ............................................................................. 45-167
SDC_VER_CONF Field Descriptions.............................................................................. 45-168
SDC_SHARP_CONF_1 Field Descriptions ..................................................................... 45-169
SDC_SHARP_CONF_2 Field Descriptions ..................................................................... 45-170
ADC_CONF Field Descriptions ....................................................................................... 45-171
ADC_SYSCHA1_SA Field Descriptions ......................................................................... 45-174
ADC_SYSCHA2_SA Field Descriptions ......................................................................... 45-175
ADC_PRP_CHAN_SA Field Descriptions ...................................................................... 45-176
ADC_PPCHAN_SA Field Descriptions ........................................................................... 45-177
ADC_DISP0_CONF Field Descriptions .......................................................................... 45-178
ADC_DISP0_RD_AP Field Descriptions ........................................................................ 45-179
ADC_PRCHAN_SA Field Descriptions .......................................................................... 45-179
ADC_DISP0_SS Field Descriptions................................................................................. 45-180
ADC_DISP1_CONF Field Descriptions .......................................................................... 45-181
ADC_DISP1_RD_AP Field Descriptions ........................................................................ 45-182
ADC_DISP1_RDM Field Descriptions ............................................................................ 45-183
ADC_DISP12_SS Field Descriptions............................................................................... 45-184
ADC_DISP2_CONF Field Descriptions .......................................................................... 45-185
ADC_DISP1_RD_AP Field Descriptions ........................................................................ 45-186
ADC_DISP2_RDM Field Descriptions ............................................................................ 45-186
ADC_DISP_VSYNC Field Descriptions.......................................................................... 45-187
DI_DISP_IF_CONF Field Descriptions ........................................................................... 45-189
DI_DISP_SIG_POL Field Descriptions ........................................................................... 45-192
DI_SER_DISP1_CONF Field Descriptions ..................................................................... 45-196
DI_SER_DISP2_CONF Field Descriptions ..................................................................... 45-198
DI_HSP_CLK_PER Field Descriptions ........................................................................... 45-200
DI_DISP0_TIME_CONF_1 Field Descriptions ............................................................... 45-201
DI_DISP0_TIME_CONF_2 Field Descriptions ............................................................... 45-203
DI_DISP0_TIME_CONF_3 Field Descriptions ............................................................... 45-204
DI_DISP1_TIME_CONF_1 Field Descriptions ............................................................... 45-205
DI_DISP1_TIME_CONF_2 Field Descriptions ............................................................... 45-207
DI_DISP1_TIME_CONF_3 Field Descriptions ............................................................... 45-208
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Tables
Table
Number
44-112
44-113
44-114
44-115
44-116
44-117
44-118
44-119
44-120
44-121
44-122
44-123
44-124
44-125
44-126
44-127
44-128
44-129
44-130
44-131
44-132
44-133
44-134
44-135
44-136
44-137
44-138
44-139
44-140
44-141
44-142
44-143
44-144
44-145
44-146
44-147
44-148
44-149
44-150
44-151
Title
Page
Number
DI_DISP2_TIME_CONF_1 Field Descriptions ............................................................... 45-210
DI_DISP2_TIME_CONF_2 Field Descriptions ............................................................... 45-211
DI_DISP2_TIME_CONF_3 Field Descriptions ............................................................... 45-213
DI_DISP3_TIME_CONF Field Descriptions ................................................................... 45-214
DI_DISP0_DB0_MAP Field Descriptions ....................................................................... 45-215
DI_DISP0_DB1_MAP Field Descriptions ....................................................................... 45-217
DI_DISP0_DB2_MAP Field Descriptions ....................................................................... 45-218
DI_DISP0_CB0_MAP Field Descriptions ....................................................................... 45-219
DI_DISP0_CB1_MAP Field Descriptions ....................................................................... 45-220
DI_DISP0_CB2_MAP Field Descriptions ....................................................................... 45-222
DI_DISP1_DB0_MAP Field Descriptions ....................................................................... 45-223
DI_DISP1_DB1_MAP Field Descriptions ....................................................................... 45-224
DI_DISP1_DB2_MAP Field Descriptions ....................................................................... 45-225
DI_DISP1_CB0_MAP Field Descriptions ....................................................................... 45-227
DI_DISP1_CB1_MAP Field Descriptions ....................................................................... 45-228
DI_DISP1_CB2_MAP Field Descriptions ....................................................................... 45-229
DI_DISP2_DB0_MAP Field Descriptions ....................................................................... 45-230
DI_DISP2_DB1_MAP Field Descriptions ....................................................................... 45-232
DI_DISP2_DB2_MAP Field Descriptions ....................................................................... 45-233
DI_DISP2_CB0_MAP Field Descriptions ....................................................................... 45-234
DI_DISP2_CB1_MAP Field Descriptions ....................................................................... 45-235
DI_DISP2_CB2_MAP Field Descriptions ....................................................................... 45-237
DI_DISP3_B0_MAP Field Descriptions .......................................................................... 45-238
DI_DISP3_B1_MAP Field Descriptions .......................................................................... 45-239
DI_DISP3_B2_MAP Field Descriptions .......................................................................... 45-240
DI_DISP_ACC_CC Field Descriptions............................................................................ 45-242
DI_DISP_LLA_CONF Field Descriptions ....................................................................... 45-244
DI_DISP_LLA_DATA...................................................................................................... 45-246
Task Commands ................................................................................................................ 45-252
Rotation and Flip Options ................................................................................................. 45-256
QP Parameter Format........................................................................................................ 45-264
QP, QPC, FOA, FOB Parameters Format
in the External Memory (Little Endian) ....................................................................... 45-267
BSB Parameter Format ..................................................................................................... 45-269
Supported Pixel Formats and Bursts ................................................................................. 45-274
Asynchronous Display Access Modes.............................................................................. 45-279
16-bits Display Command Format .................................................................................... 45-290
24-bits Display Command Format .................................................................................... 45-290
Template Flow Control ..................................................................................................... 45-297
Command Opcode............................................................................................................. 45-297
RD_DATA Command Format........................................................................................... 45-298
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Tables
Table
Number
44-152
44-153
44-154
44-155
44-156
44-157
44-158
44-159
44-160
44-161
44-162
44-163
44-164
44-165
44-166
44-167
44-168
44-169
44-170
44-171
44-172
44-173
44-174
44-175
44-176
44-177
44-178
44-179
44-180
44-181
44-182
44-183
44-184
45-1
45-2
45-3
45-4
45-5
45-6
45-7
45-8
Title
Page
Number
RD_ACK Command Format ............................................................................................ 45-298
RD_WAIT Command Format ........................................................................................... 45-298
WR_XADDR Command Format...................................................................................... 45-298
XCodedWidth Values......................................................................................................... 45-299
WR_YADDR Command Format ...................................................................................... 45-299
YCodedWidth Values........................................................................................................ 45-300
WR_ADDR Command Format......................................................................................... 45-301
WR_CMND Command Format A .................................................................................... 45-301
WR_CMND Command Format B .................................................................................... 45-301
WR_DATA Command Format.......................................................................................... 45-301
Display Interfaces and Access Priorities........................................................................... 45-304
IDMAC Channels ............................................................................................................. 45-309
Use Cases of Chaining the IPU Tasks............................................................................... 45-317
Programming IPU Flows and Tasks.................................................................................. 45-321
Functional Interrupts Summary ........................................................................................ 45-340
Error Interrupts Summary ................................................................................................. 45-343
Input Buffer Memory Mapping for 8-Bit YUV or Generic Sensor Output ...................... 45-352
Input Buffer Memory Mapping for 16-Bit Generic Sensor Output .................................. 45-354
Input Buffer Memory Mapping for 10-bit RGB Sensor Output ....................................... 45-355
Downsizing Temporary Memory Mapping....................................................................... 45-356
Downsizing Output Memory Mapping ............................................................................. 45-356
Task Parameter Memory Mapping.................................................................................... 45-357
Main Processing Memory Mapping.................................................................................. 45-359
Rotation Memory Mapping............................................................................................... 45-360
Post-filter Memory Mapping for MPEG-4 ....................................................................... 45-361
Post-filter Memory Mapping for H264 ............................................................................. 45-363
SDC Buffer Memory Mapping ......................................................................................... 45-364
ADC Buffer Memory Mapping......................................................................................... 45-365
ADC Template Memory Mapping .................................................................................... 45-368
Channel Parameter Memory Mapping.............................................................................. 45-370
Y Dual-Port FIFO Mapping.............................................................................................. 45-370
U/V Dual Port FIFO Mapping ......................................................................................... 45-371
Decoding Look-Up-Table Memory Mapping ................................................................... 45-371
SSI Operating Modes ............................................................................................................ 46-4
I2S Mode Selection ............................................................................................................. 46-15
Data Alignment ................................................................................................................... 46-19
SSI Memory Map................................................................................................................ 46-20
Register Figure Conventions............................................................................................... 46-21
SSI Register Summary ........................................................................................................ 46-23
SSI Transmit Data Register Field Descriptions .................................................................. 46-26
SSI_1 Receive Data Register Field Descriptions................................................................ 46-29
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Tables
Table
Number
45-9
45-10
45-11
45-12
45-13
45-14
45-15
45-16
45-17
45-18
45-19
45-20
45-21
45-22
45-23
45-24
45-25
45-26
45-27
45-28
45-29
45-30
Title
Page
Number
SSI Control Register Field Descriptions ............................................................................. 46-33
SSI Interrupt Status Register Field Descriptions ................................................................ 46-35
SSI Interrupt Enable Register Field Descriptions ............................................................... 46-39
SSI Transmit Configuration Register Field Descriptions ................................................... 46-40
SSI Receive Configuration Register Field Descriptions..................................................... 46-43
SSI Transmit and Receive Clock Control Register Field Descriptions .............................. 46-45
SSI Data Length .................................................................................................................. 46-46
SSI FIFO Control/Status Register Field Descriptions ........................................................ 46-47
Status of Transmit FIFO Empty Flag .................................................................................. 46-50
SSI AC97 Control Register Field Descriptions .................................................................. 46-50
SSI AC97 Command Address Register Field Descriptions................................................ 46-52
SSI AC97 Command Data Register.................................................................................... 46-52
SSI AC97 Tag Register Field Descriptions......................................................................... 46-53
SSI Transmit Time Slot Mask Register Field Descriptions ................................................ 46-54
SSI Receive Time Slot Mask Register Field Descriptions.................................................. 46-54
SSI Bit Clock and Frame Rate as a Function of PSR, PM, and DIV2................................ 46-58
SSI System Clock, Bit Clock, Frame Clock in Master Mode............................................. 46-59
SSI Receive Data 1 Interrupts ............................................................................................. 46-60
SSI Receive Data 0 Interrupts ............................................................................................. 46-60
SSI Transmit Data 1 Interrupts ........................................................................................... 46-60
SSI Transmit Data 0 Interrupts ........................................................................................... 46-61
SSI Control Bits Requiring SSI To Be Disabled Before Change........................................ 46-62
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About This Book
The MCIMX31 and MCIMX31L Multimedia Applications Processors Reference Manual describes the
features and operation of the i.MX31 and i.MX31L Multimedia Applications Processors. This manual
provides details on how to initialize, configure, and program the ICs. It is assumed that the reader has a
good working knowledge of the ARM1136JF-S architecture. For programming information about the
ARM1136JF-S processor, see the documents listed in the Suggested Reading section of this preface.
Audience
The MCIMX31 and MCIMX31L Multimedia Applications Processors Reference Manual provides to the
design engineer the necessary data to successfully integrate the applications processor ICs into a wide
variety of applications.
The intended audience for this document includes system architects, system modeling teams, IC designers,
software architects/designers, and the platform integration and testing teams. The level of detail in this
document is intended to provide the reader with sufficient information to validate the capabilities of the
applications processor ICs in the targeted applications. This document is supplemented with users’
manuals for hardware design and software development.
Organization
This reference manual is organized into chapters that describe the operation and programming of the
i.MX31 and i.MX31L processors. It includes brief summaries of the major components of the i.MX31 and
i.MX31L, as well as a complete listing of the memory maps for the applications processor ICs and shared
memories. This book also describes the generation and distribution of clocks.
A brief summary of the ARM11 Platform and its operational features is covered in this document, as well
as an extensive overview of the components including the features, addressing, and operational modes of
the ARM11 Platform. This manual also provides detailed information about the ARM11 core and the
relationship and prioritization of the interrupts, and describes how the Security Controller provides a way
to securely store sensitive information in on-chip RAM, as well as in off-chip non-volatile memory to
prevent un-authorized access. It also describes how data is stored in encrypted form, using an encryption
key that is unique to each device and accessible only to the Secure RAM module.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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cxxvii
This reference manual contains chapters that describe the operations and configuration of all of the
peripherals, including the modules that provide security, memory, and connectivity. The chapters in this
book are as follows.
Book I, i.MX31 and i.MX31L Integration and Description
Device Introduction and Memory Map
Chapter 1, “Introduction to the i.MX31 and i.MX31L Multimedia Applications Processors,” on page 1-1
Chapter 2, “System Memory Map, Interrupts, and SDMA Events,” on page 2-1
Clocks, Power Management and Reset
Chapter 3, “Clocks, Power Management and Reset (AP Clock Controller Module),” on page 3-1
Pins
Chapter 4, “Signal Multiplexing,” on page 4-1
Chapter 5, “General Purpose Input/Output (GPIO),” on page 5-1
Debug
Chapter 6, “Debugging the i.MX31 and i.MX31L,” on page 6-1
Boot
Chapter 7, “i.MX31 and i.MX31L Boot,” on page 7-1
Book II, Applications Processors’ Core and Peripherals
ARM11 Core and Interrupts
Chapter 8, “ARM11 Platform,” on page 8-1
Chapter 9, “ARM1136JF-S Vectored Interrupt Controller (AVIC),” on page 9-1
Security
Chapter 10, “Security Controller (SCC),” on page 10-1
Chapter 11, “Security Random Number Generator Accelerator (RNGA),” on page 11-1
Chapter 12, “Run-Time Integrity Checker (RTIC),” on page 12-1
Chapter 13, “IC Identification (IIM),” on page 13-1
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Memory Systems
Chapter 14, “L2 Cache Controller (L2CC),” on page 14-1
Chapter 15, “ARM11 Event Monitor (EVTMON),” on page 15-1
External Interfaces
Chapter 16, “External Memory Interface (EMI),” on page 16-1
Chapter 17, “Multi-Master Memory Interface (M3IF),” on page 17-1
Chapter 18, “Wireless External Interface Module (WEIM),” on page 18-1
Chapter 19, “Enhanced SDRAM Controller (ESDCTL),” on page 19-1
Chapter 20, “NAND Flash Controller (NANDFC),” on page 20-1
Chapter 21, “Personal Computer Memory Card International Association (PCMCIA) Controller,”
on page 21-1
Connectivity Peripherals
Chapter 22, “1-Wire Interface (1-Wire),” on page 22-1
Chapter 23, “Advanced Technology Attachment (ATA),” on page 23-1
Chapter 24, “Configurable Serial Peripheral Interface (CSPI),” on page 24-1
Chapter 25, “Fast Infrared Interface (FIR),” on page 25-1
Chapter 26, “Inter-Integrated Circuit (I2C),” on page 26-1
Chapter 27, “Keypad Port (KPP),” on page 27-1
Chapter 28, “Memory Stick Host Controller (MSHC),” on page 28-1
Chapter 29, “Secured Digital Host Controller (SDHC),” on page 29-1
Chapter 30, “Subscriber Identification Module (SIM),” on page 30-1
Chapter 31, “Universal Asynchronous Receiver/Transmitter (UART),” on page 31-1
Chapter 32, “Universal Serial Bus, On-The-Go (USBOTG),” on page 32-1
Timer Peripherals
Chapter 33, “Enhanced Periodic Interrupt Timer (EPIT 1, 2),” on page 33-1
Chapter 34, “General Purpose Timer (GPT),” on page 34-1
Chapter 35, “Pulse-Width Modulator (PWM),” on page 35-1
Chapter 36, “Real Time Clock (RTC),” on page 36-1
Chapter 37, “Watchdog Timer (WDOG),” on page 37-1
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System Control Peripherals
Chapter 38, “AHB-Lite 2.v6 to IP Bus Interface (AIPS),” on page 38-1
Chapter 39, “Multi-Layer AHB Crossbar Switch (MAX),” on page 39-1
Chapter 40, “Smart Direct Memory Access (SDMA),” on page 40-1
Chapter 41, “Shared Peripheral Bus Arbiter (SPBA),” on page 41-1
Multimedia Peripherals
Chapter 42, “Digital Audio Multiplexer (AUDMUX),” on page 42-1
Chapter 43, “Moving Pictures Experts Group-4 (MPEG-4) Encoder,” on page 43-1
Chapter 44, “Image Processing Unit (IPU),” on page 44-1
Chapter 45, “Synchronous Serial Interface (SSI),” on page 45-1
Chapter 46, “Graphics Accelerator (MBX R-S),” on page 46-1
Suggested Reading
The following documents are suggested for a complete description of the i.MX31 and i.MX31L, and are
necessary to design with the device. Especially for those not familiar with the ARM1136JF-S processor,
these manuals and documents will be helpful when used in conjunction with this reference manual.
These manuals can be found at the ARM Ltd. World Wide Web site at http://www.arm.com, and at the
Freescale Semiconductor, Inc. World Wide Web site at http://www.freescale.com. They can be
downloaded directly from the Web sites, or printed versions can be ordered.
1. AMBA AHB specifications
2. ARMv6 AMBA Extensions
3. ARM1136JF-S Platform specifications
4. Hip7a KiloBit Single Port HP SRAM Compiler
5. Hip7A SAMI ROM Compiler
6. Hip7A KiloBit HD VIA ROM Compiler
7. ARM1136JF-S Platform Test Guide
8. ARM Architecture Reference Manual
9. ARM11DT1 Data Sheet Manual
10. ARM Technical Reference Manual
11. IP Interface, Semiconductor Reuse Standard, Freescale Semiconductor
12. ARM1136 Technical Reference Manual
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Conventions
This reference manual uses the following conventions:
• OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
• Logic level one is a voltage that corresponds to Boolean true (1) state.
• Logic level zero is a voltage that corresponds to Boolean false (0) state.
• To set a bit or bits means to establish logic level one.
• To clear a bit or bits means to establish logic level zero.
• A signal is an electronic construct whose state conveys or changes in state convey information.
• A pin is an external physical connection. The same pin can be used to connect a number of signals.
• Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
• Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
• LSB means least significant bit or bits, and MSB means most significant bit or bits. References to
low and high bytes or words are spelled out.
• Numbers preceded by a percent sign (%) are binary. Numbers preceded by a 0x are hexadecimal.
• Courier monospaced type indicate commands, command parameters, code examples, expressions,
data types, and directives.
• Italic type indicates replaceable command parameters.
• All source code examples are in C.
Definitions, Acronyms, and Abbreviations
Table i defines the acronyms and abbreviations used in this document.
Table i. Definitions, Acronyms, and Abbreviations
Term
Definition
1-Wire
An interface providing a single serial communication line to a 1 K-bit EPROM.
ABIST
Array built-in self test —A hardware unit that autonomously performs memory array testing when in test
mode.
ADC
Analog-to-digital converter
ADC
Asynchronous display controller
address
translation
Address conversion from virtual domain to physical domain
AFE
Analog front end
AHB
AMBA high-performance bus
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Table i. Definitions, Acronyms, and Abbreviations (continued)
Term
Definition
AIPS
AHB-Lite 2.v6 to IP bus interface
AMBA
AMBA is an open standard, on-chip bus specification that details a strategy for the interconnection and
management of functional blocks that makes up a System-on-Chip (SoC).
API
ARM
associativity
Application programming interface
Advanced RISC machines processor architecture
Refers to the number of sets in the cache.
atomic operation An ARM11 operation in which the processor reads data from a memory location, modifies it and immediately
writes it back. A successful operation means that there was no other write operation to the same location by
another bus master between the read and the write.
AUDMUX
BCD
BDMA
Digital audio MUX—provides a programmable interconnection for voice, audio, and synchronous data routing
between host serial interfaces and peripheral serial interfaces.
Binary coded decimal
Baseband direct memory access—the BDMA controls the DMA accesses of StarCore peripherals to the
DMA bus shared by the DMA channels, and the DMA channels’ accesses to M1 memory and MAX slaves
(M2 memory, external memory and AIPS peripherals) through the AHB bus.
be/le
Big Endian/Little Endian
beat
A bus transaction that is part of a burst.
BER
Bit error ratio
BIST
Built in self-test
burst
A sequence of transactions (beats) on the bus that the bus controller cannot interrupt.
bus
A path between several devices via data lines.
bus load
The percentage of time a bus is busy.
cache
coherency
A state where data images in a cache match the data in other memories or caches.
cache hit
A request for data that is in the cache, which the cache can fulfill with minimum latency.
cache miss
A request for data from the cache that cannot be fulfilled without some latency because the data is not
present in the cache.
cache
A procedure to reach cache coherency by writing back to the L2/M2 data that was written only to the cache.
synchronization
CCM
Clock control module
CF
CompactFlash—a small form factor card standard that encompasses CF data storage cards, magnetic disk
cards and I/O cards.
channel
Refers to a defined path for flow of data between a source and sink. A channel is uni-directional. Example
source and sink nodes are AP Processor or Peripherals. Up to 32 channels can be defined and operating at
any one time.
CMOS
Complimentary metal-oxide semiconductor
CODEC
Coder/decoder or compression/decompression algorithm—Used to encode and decode (or compress and
decompress) various types of data.
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Table i. Definitions, Acronyms, and Abbreviations (continued)
Term
contention
context switch
Definition
A situation in which multiple simultaneous accesses cannot be served by memory in the same cycle.
Saving micro RISC (for example, SDMA core) registers by copying their contents into internal SRAM space
followed by a load of the registers from a different channel. Essentially, a context switch means that the
current state of the SDMA micro-RISC engine is saved, and the new state of the core is determined by
loading the core registers with the state of a different channel.
CPU
Central processing unit—generic term used to describe a processing core.
CRC
Cyclic redundancy check—Bit error protection method for data communication.
CSF
Command sequence file—a script loaded together with an application to direct HAB verification
CSI
Camera sensor interface
CSIC
Complex instruction set computer
CTL
Control
DAC
Digital-to-analog converter
DDR RAM
Double data rate RAM
degradation
Refers to the increase of execution time of an a program due to the use of cache. The reference execution
time is that obtained by running the program with infinite M1 memory (without cache). The degradation is
measured in percentage.
DFD
Digital frequency doubler—produces an output clock that is twice the frequency of the input clock.
dirty
An attribute of a VBR indicating that its content was modified without being updated in M2 memory.
DMA
Direct memory access—an independent block that can initiate memory-to-memory data transfers.
DPLL
Digital phase locked loop—provides clock generation in digital and mixed analog/digital chips designed for
wireless communication and other applications. The DPLL produces a high-frequency chip clock with a low
frequency and phase jitter.
DRAM
Dynamic random access memory
DRM
Data read messaging
DSM
Deep sleep module—handles the transition to and from Deep Sleep power saving mode.
DSP
Digital signal processor—a special-purpose CPU used for digital signal processing. It provides ultra-fast
instruction sequences, such as shift and add, and multiply and add, which are commonly used in
math-intensive signal processing applications.
DWM
Data write messaging
EDIO
External interrupt module—recognizes external (to the IC) asynchronous signals as interrupt sources.
EDO RAM
Extended data out DRAM
e-Fuse
Electrically-programmable poly fuses—a fusible element that may be blown under software or JTAG control
during IC final test, at the customer factory or in the field.
EMI
External memory interface—controls all IC external memory accesses (read/write/erase/program) from all
the masters in the system.
Endian
Refers to byte ordering of data in memory. Little Endian means that the least significant byte of the data is
stored in a lower address than the most significant byte. In Big Endian, the order of the bytes is reversed.
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Table i. Definitions, Acronyms, and Abbreviations (continued)
Term
EOnCE
Definition
Enhanced on-chip emulation—a unit that supports core-level debugging and profiling.
EPIT
enhanced periodic interrupt timer—a 32-bit set and forget timer capable of providing precise interrupts at
regular intervals with minimal processor intervention.
FCS
Frame checker sequence
FEC
Forward error correction
fetch
The process of retrieving information (program and data) initiated by a miss in the cache. The process is
comprised of a mandatory fetch and a speculated fetch.
FIFO
First in first out
FIPS
Federal information processing standards—United States Government technical standards published by the
National Institute of Standards and Technology (NIST). NIST develops FIPS when there are compelling
Federal government requirements such as for security and interoperability but no acceptable industry
standards or solutions
FIPS-140
Security requirements for cryptographic modules—Federal Information Processing Standard 140-2(FIPS
140-2) is a standard that describes US Federal government requirements that IT products should meet for
Sensitive, but Unclassified (SBU) use.
FIR
Fast infrared—high speed IrDA protocol that supports speeds up to 4M baud.
FIR
See FIR.
Flash
Flash path
A non-volatile storage device similar to EEPROM, but where erasing can only be done in blocks or the entire
chip.
Path within ROM bootstrap pointing to an executable Flash application.
Flush
A procedure to reach cache coherency. Refers to removing a data line from cache. This process includes
cleaning the line, invalidating its VBR and resetting the tag valid indicator. The flush is triggered by a software
command.
FPM
Full port mode
GEM
GPRS encryption module—The module is a hardware accelerator that assists in the processing of general
packet radio service (GPRS) data packets.
GPCR
Global peripheral control registry
GPIO
General purpose input/output
GPS
Global positioning system—GPS module within BP domain that can process satellite signals and compute
position coordinates.
H.264
A high compression digital video codec standard
HAB
High assurance boot—Used to prevent hackers from bypassing device security during the boot process. The
high assurance boot permits flashed code to be verified for integrity before being loaded by a mobile device.
HAC
Hash accelerator controller—a security hardware module that is also called HACC
hash
Hash values are produced to access secure data. A hash value (or simply hash), also called a message
digest, is a number generated from a string of text. The hash is substantially smaller than the text itself, and
is generated by a formula in such a way that it is extremely unlikely that some other text will produce the same
hash value.
hit
See cache hit.
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Table i. Definitions, Acronyms, and Abbreviations (continued)
Term
Definition
hw
Hardware
i/o
Input/output
ICACHE
ICE
IEEE 1149.1
IIM
Indigo
IP
IPU
Instruction cache—A cache memory dedicated to program only; a component in the SC140e Platform 2002
In-circuit emulation
The IEEE standard defining JTAG, see JTAG
IC identification module
An IP interrupt request standard based on the SRS standard.
intellectual property
Image Processing Unit —supports video and graphics processing functions and provides an interface to
video/still image sensors and displays.
iRAM
Processor-internal RAM
IrDa
Infrared Data Association—A nonprofit organization whose goal is to develop globally adopted specifications
for infrared wireless communication.
iROM
Processor-internal ROM
ISR
Interrupt service routine
JTAG
Kill
KPP
JTAG (IEEE Standard 1149.1) A standard specifying how to control and monitor the pins of compliant devices
on a printed circuit board.
To stop a memory access
Keypad port—a 16-bit peripheral that can be used as a keypad matrix interface or as general purpose
input/output (I/O).
l1 memory
Level 1 cache memory—It is closest to the core and serves the core directly.
l2 memory
Level 2 cache memory—a cache memory that serves the Level 1 cache
L-Fuse
Laser fuse—a fusible connection that can only be during chip manufacturing (at the wafer level).
line
Refers to a unit of information in the cache that is associated with a tag.
lock
The state of a line or group of lines in the cache that prevents them from being replaced in case of a miss.
LRU
Least recently used—a policy for line replacement in the cache
LSP
Least significant part.
LV
LWB
Low voltage
Late-write buffer
m1 memory
Level 1 RAM connected directly to the core.
m2 memory
Level 2 RAM connected to the core via L1 cache memory.
MAP
MAPBGA
MCTL
Mold array process
Mold array process ball grid array
Memory controller
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Table i. Definitions, Acronyms, and Abbreviations (continued)
Term
MDO
Definition
Message data out
MEMCTC
Embedded Memory Core Technology Center (Freescale, Austin, TX)
memory
mapping
Translation of address referenced by the core to a physical memory address
MIPS
Million instructions-per-second
MISO
Master in slave out—supplies the output data from a slave to the input of the master. There can be no more
than one slave that is transmitting data during any particular transfer. See SPI.
miss
See cache miss.
miss rate
The ratio between the number of memory misses and the total memory accesses.
MMC
MultiMedia card—a memory storage card. See SD.
MMU
Memory management unit—a component responsible for memory protection and address translation.
MOSI
Master out slave in—supplies the output data from the master to the inputs of the slaves. See SPI
MPEG
Moving Picture Experts Group—an ISO committee that generates standards for digital video compression
and audio. It is also the name of the algorithms used to compress moving pictures and video.
MPEG
standards
There are several standards of compression for moving pictures and video.
• MPEG-1 is optimized for CD-ROM and is the basis for MP3.
• MPEG-2 is defined for broadcast quality video in applications such as digital television set-top boxes and
DVD.
• MPEG-3 was merged into MPEG-2.
• MPEG-4 is a standard for low-bandwidth video telephony and multimedia on the World-Wide Web.
MQSPI
Multiple queue serial peripheral interface—used to perform serial programming operations necessary to
configure radio subsystems and selected peripherals.
MSHC
Memory stick host controller
MSP
Most significant part
MUX
Multiplexing
NAND Flash
NANDFC
NC
Nexus
NOR Flash
Flash ROM technology—NAND Flash architecture is one of two flash technologies (the other being NOR)
used in memory cards such as the CompactFlash cards. NAND is best suited to flash devices requiring high
capacity data storage. NAND flash devices offer storage space up to 512-Mbyte and offers faster erase, write,
and read capabilities over NOR architecture.
NAND flash controller—Provides a glueless interface to a Flash memory device.
Not connected—designates unassigned connections in connection diagrams.
A standard providing real-time trace capabilities in compliance with the IEEE-ISTO 5001-2003 standard. The
Nexus standard defines an Auxiliary port used in conjunction with the IEEE 1149.1 JTAG port to provide
development support capabilities without requiring address and data pins for internal visibility.
See NAND Flash.
O-Wire
See 1-Wire.
OnCE™
On-Chip Emulation—circuitry that provides convenient and inexpensive debug facilities normally available
only using expensive external hardware.
One-wire
See 1-Wire.
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Table i. Definitions, Acronyms, and Abbreviations (continued)
Term
OS
Definition
operating system.
OWire
See 1-Wire.
P2002
Platform 2002–The platform of a StarCore and other modules that provide the BP portion of the IC, see also
DSP, SC140e and StarCore.
Parity
Check bit for detection of errors during data transfers
PC card
See PCMCIA.
PCMCIA
Personal Computer Memory Card International Association—a multi-company organization that has
developed a standard for small, credit card-sized devices, called PC Cards. There are three types of PCMCIA
cards that have the same rectangular size (85.6 by 54 millimeters), but different widths.
physical
address
The address by which the memory in the system is physically accessed.
PLL
Phase locked loop—an electronic circuit controlling an oscillator so that it maintains a constant phase angle
(a lock) on the frequency of an input, or reference, signal.
POR
Power on reset
pre-fetch
Refers to the speculated fetch process, up to the end of the cache line (see fetch).
pre-fetch hit
A match between the required address and a speculated access before it is written to the cache.
pre-fetch line
A pre-fetch mode supported by the caches, where pre-fetching is done up to the end of the cache line.
privileged mode Core mode that enables execution of certain instructions, usually used by the operating system. user
application is executed in non-privileged (User) mode.
PWM
R-AHB bus
RAM
RAMC
RAM path
RGB
Pulse-width modulator—Using a PWM waveforms are synthesized by a sequence of pulses with a
progressive width adjustment to produce a range of frequencies.
Reduced advanced high-performance bus (AHB), related to ARM bus architecture
Random access memory
Random Access Memory (RAM) Controller
Path within ROM bootstrap leading to the downloading and the execution of a RAM application
The RGB color model is based on the additive model in which red, green, and blue light are combined in
various ways to create other colors. The abbreviation RGB come from the three primary colors in additive
light models.
RGBA
RGBA color space stands for red green blue alpha. The alpha channel is the transparency channel, and is
unique to this color space. RGBA, like RGB, is an additive color space, so the more of a color you place, the
lighter the picture gets. PNG is the best known image format that uses the RGBA color space.
RNGA
Random number generator accelerator—a security hardware module that produces 32-bit pseudo random
numbers as part of the security module.
ROM
Read-only memory
ROMC
Read-only memory (ROM) controller
ROM bootstrap Internal boot code encompassing main boot flow as well as exception vectors.
RPM
Reduced port mode
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Table i. Definitions, Acronyms, and Abbreviations (continued)
Term
Definition
RTC
Real-time clock
RTIC
Real-time integrity checker—a security hardware module
RTOS
Real-time operating system—any operating system where interrupts are guaranteed to be handled within a
certain specified maximum time, thereby making it suitable for control of hardware in embedded systems and
other time-critical applications. RTOS is not a specific product but a class of operating systems.
sample
The result of measuring the amplitude of an analog signal at a specified time. In digital signal processing a
sample is a signed or unsigned number and the number of samples per second is called the sample rate.
SCC
Security controller—a security hardware module
SCLK
Serial clock—a control line driven by the master, regulating the flow of data bits. See SPI.
script
An assembly language program executed by the SDMA core. Scripts reside in the ROM or may be pre-loaded
into the SDMA SRAM.
SD
Secure digital card—based on the MMC specification, the SD is a highly secure small flash memory card
that measures 32 x 24 x 2.1 millimeters that provide high-capacity memory storage in capacities between 16
Megabytes to beyond 1 Gigabyte. SD cards provide encryption capabilities for protected content to ensure
secure distribution of copyrighted material.
SDC
SDMA
SDRAM
SHA-1
shared
peripherals
Synchronous display controller
Smart direct memory access
Synchronous dynamic random access memory
The Secure Hash Algorithm (SHA-1), National Institute of Standards and Technology, NIST FIPS PUB 180-1,
“Secure Hash Standard,” U.S. Department of Commerce, April 1995
Shared peripherals domain—one of three major domains of the IC
SHW
Security hardware
SHWI
Security hardware interface
SIM
Subscriber identification module—This module is designed to facilitate communication between the IC and
SIM cards or Eurochip pre-paid phone cards.
SMIF
StarCore memory interface
SoC
System on a chip
SPBA
SPI
SRAM
SRS
Shared peripheral bus arbiter—a three-to-one IP bus arbiter, with a resource-locking mechanism.
Serial peripheral interface—a full-duplex synchronous serial interface for connecting low-/medium-bandwidth
external devices using four wires. SPI devices communicate using a master/slave relationship over two data
lines and two control lines: Also see SS, SCLK, MISO, and MOSI.
Static random access memory
Semiconductor Reuse Standards
SS
Slave select—a control line that enables slaves to be turned on and off with hardware control. See SPI.
SSI
Synchronous-serial interface—standardized interface for serial data transfer
Supervisor
Level
A core privilege level that enables the execution of all instructions and access to all registers (as opposed to
user level).
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Table i. Definitions, Acronyms, and Abbreviations (continued)
Term
Sync Flash
Definition
An obsolete Flash ROM technology that was discontinued in 2003.
Task
A program unit with a set of attributes that is controlled by the operating system. Task attributes can include
such elements as the execution priority, data area protection, program protection, and so on.
TBD
To be determined
TQFP
Thin quad flat pack
tristate
Input control that switches outputs either to active or to high impedance.
true IDE
A CompactFlash (CF) storage card mode of operation. When the CF card runs in True IDE mode it is
electrically compatible with an IDE disk drive.
TWB
Trace write buffer—a component of the SC140e that temporarily holds trace data before the debugging and
profiling unit (DPU) saves it into main memory.
TYPE
Identifier that distinguishes a production, engineering, or HAB-disabled device.
UART
Universal asynchronous receiver/transmitter—this module provides asynchronous serial communication to
external devices.
UID
Unique ID–a field in the processor and CSF identifying a device or group of devices
USB
Universal serial bus—an external bus standard that supports high speed data transfers. The USB 1.1
specification supports data transfer rates of up to 12Mb/s and USB 2.0 has a maximum transfer rate of
480 Mbps. A single USB port can be used to connect up to 127 peripheral devices, such as mice, modems,
and keyboards. USB also supports Plug-and-Play installation and hot plugging.
USBOTG
USB on the go—an extension of the USB 2.0 specification for connecting peripheral devices to each other.
USBOTG devices, also known as dual-role peripherals, can act as limited hosts or peripherals themselves
depending on how the cables are connected to the devices, and they also can connect to a host PC.
user level
A core privilege level with restricted access to some core registers and no access to some instructions. It is
also called user mode.
valid bit
VBR
VBR miss
VC
VDD
Virtual DMA
An attribute of a VBR, indicating its contents is valid, and can be used.
Valid bit resolution—a unit of data that is treated as a whole regarding its validity.
A miss reported when the Tag of the data is in the cache, but the VBR is not.
Virtual component.
Virtual data descriptor.
DMA function executed as observed from the outside. However, the function is actually executed by a script
in the micro-RISC core.
WBB
Write back buffer
word
A group of bits comprising 32 bits
write miss
write-allocate
write-back
A miss caused when trying to write data that is not in the cache (either the entire line is missing, or the specific
VBR is not valid).
A writing scheme in which a write miss first reads the data from the L2/M2 before executing a write in the
cache.
A write scheme in which data is written only to the cache. The main memory is updated when the data in the
cache is replaced.
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Table i. Definitions, Acronyms, and Abbreviations (continued)
Term
write-through
Definition
A write scheme in which the data is written simultaneously to the cache and to memory.
WTB
Write-through buffer—buffer that temporarily saves the data written into main memory in a write-through
mode.
WTLS
Wireless transport layer security—a part of the wireless application protocol
XTAL
Crystal
YUV
YUV is the color space used in the PAL system of television broadcasting that is the standard in most of
Europe and other areas of the world. Y stands for the luminance component (the brightness) and U and V
are the chrominance (color) components.
YUV 4:2:2
YUV 4:2:2 is a specific encoding for digital representation of the YUV color space. In YUV 4:2:2, the basic
unit is composed of two pixels, and occupies four bytes of space. Each pixel has an individual 8 bit Y channel.
Then, the first pixel specifies an 8 bit U channel, and the second pixel an 8 bit V channel. Both pixels use the
same U and V channels.
YUV 4:4:4
A specific encoding for digital representation of the YUV color space. Each of the Y,U and V channels are
expressed with 8 bits, and have therefore 256 (28) possible levels. It is in this respect similar to RGB 24-bit,
and uses the same amount of space (3 bytes per pixel). YUV 4:4:4 is the highest-quality digital YUV standard
available.
Glossary of Terms and Abbreviations
Table ii lists and defines terms and abbreviations used in Chapter 32, “Universal Serial Bus, On-The-Go
(USBOTG).”
Table ii. Glossary of Terms and Abbreviations
Term
Definition
ACK
Handshake packet indicating a positive acknowledgment.
Active Device
A device that is powered and is not in the Suspend state.
Asynchronous Data Data transferred at irregular intervals with relaxed latency requirements.
Asynchronous RA
The incoming data rate, Fsi, and the outgoing data rate, Fso, of the RA process are independent (for
example, there is no shared master clock). See also rate adaptation.
Asynchronous SRC The incoming sample rate, Fsi, and outgoing sample rate, Fso, of the SRC process are independent (for
example,, there is no shared master clock). See also sample rate conversion.
Audio Device
AWG#
A device that sources or sinks sampled analog data.
The measurement of a wire’s cross-section, as defined by the American Wire Gauge standard.
b/s
Transmission rate expressed in bits per second.
B/s
Transmission rate expressed in bytes per second.
Babble
Unexpected bus activity that persists beyond a specified point in a (micro) frame.
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Table ii. Glossary of Terms and Abbreviations
Term
Definition
Bandwidth
The amount of data transmitted per unit of time, typically bits per second (b/s) or bytes per second (B/s).
Big Endian
A method of storing data that places the most significant byte of multiple-byte values at a lower storage
address. For example, a 16-bit integer stored in Big Endian format places the least significant byte at the
higher address and the most significant byte at the lower address. See also Little Endian.
Bit
A unit of information used by digital computers. Represents the smallest piece of addressable memory
within a computer. A bit expresses the choice between two possibilities and is typically represented by a
logical one (1) or zero (0).
Bit Stuffing
Insertion of a “0” bit into a data stream to cause an electrical transition on the data wires, enabling a PLL
to remain locked.
Buffer
Bulk Transfer
Storage used to compensate for a difference in data rates or time of occurrence of events, when
transmitting data from one device to another.
One of the four USB transfer types. Bulk transfers are non-periodic, large burst communication typically
used for a transfer that can use any available bandwidth and can be delayed until bandwidth is available.
See also transfer type.
Bus Enumeration
Detecting and identifying USB devices.
Byte
A data element that is eight bits in size.
Capabilities
Characteristics
Those attributes of a USB device that are administrated by the host.
Those qualities of a USB device that are unchangeable; for example, the device class is a device
characteristic.
Client
Software resident on the host that interacts with the USB System Software to arrange data transfer
between a function and the host. The client is often the data provider and consumer for transferred data.
Configuring
Software
Software resident on the host software that is responsible for configuring a USB device. This may be a
system configuration or software specific to the device.
Control Endpoint
Control Pipe
Control Transfer
A pair of device endpoints with the same endpoint number that are used by a control pipe. Control
endpoints transfer data in both directions and, therefore, use both endpoint directions of a device
address and endpoint number combination. Thus, each control endpoint consumes two endpoint
addresses.
Same as a message pipe.
One of the four USB transfer types. Control transfers support configuration/command/status type
communications between client and function. See also transfer type.
CRC
See Cyclic Redundancy Check.
CTI
Computer Telephony Integration.
Cyclic Redundancy
Check (CRC)
A check performed on data to see if an error has occurred in transmitting, reading, or writing the data.
The result of a CRC is typically stored or transmitted with the checked data. The stored or transmitted
result is compared to a CRC calculated for the data to determine if an error has occurred.
Default Address
An address defined by the USB Specification and used by a USB device when it is first powered or reset.
The default address is 00H.
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Table ii. Glossary of Terms and Abbreviations
Term
Definition
Default Pipe
The message pipe created by the USB System Software to pass control and status information between
the host and a USB device’s endpoint zero.
Device
A logical or physical entity that performs a function. The actual entity described depends on the context
of the reference. At the lowest level, device may refer to a single hardware component, as in a memory
device. At a higher level, it may refer to a collection of hardware components that perform a particular
function, such as a USB interface device. At an even higher level, device may refer to the function
performed by an entity attached to the USB; for example, a data/FAX modem device. Devices may be
physical, electrical, addressable, and logical. When used as a non-specific reference, a USB device is
either a hub or a function.
Device Address
A seven-bit value representing the address of a device on the USB. The device address is the default
address (00H) when the USB device is first powered or the device is reset. Devices are assigned a
unique device address by the USB System Software.
Device Endpoint
A uniquely addressable portion of a USB device that is the source or sink of information in a
communication flow between the host and device. See also endpoint address.
Device Resources
Resources provided by USB devices, such as buffer space and endpoints. See also Host Resources and
Universal Serial Bus Resources.
Device Software
Software that is responsible for using a USB device. This software may or may not also be responsible
for configuring the device for use.
Downstream
The direction of data flow from the host or away from the host. A downstream port is the port on a hub
electrically farthest from the host that generates downstream data traffic from the hub. Downstream ports
receive upstream data traffic.
Driver
When referring to hardware, an I/O pad that drives an external load. When referring to software, a
program responsible for interfacing to a hardware device, that is, a device driver.
DWord
Double word. A data element that is two words (for example, four bytes or 32 bits) in size.
Dynamic Insertion
and Removal
The ability to attach and remove devices while the host is in operation.
E2PROM
See Electrically Erasable Programmable Read Only Memory.
EEPROM
See Electrically Erasable Programmable Read Only Memory.
Electrically Erasable Non-volatile re-writeable memory storage technology
Programmable Read
Only Memory
(EEPROM)
End User
The user of a host.
Endpoint
See device endpoint.
Endpoint Address
The combination of an endpoint number and an endpoint direction on a USB device. Each endpoint
address supports data transfer in one direction.
Endpoint Direction
The direction of data transfer on the USB. The direction can be either IN or OUT. IN refers to transfers
to the host; OUT refers to transfers from the host.
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Table ii. Glossary of Terms and Abbreviations
Term
Definition
Endpoint Number
A four-bit value between 0H and FH, inclusive, associated with an endpoint on a USB device.
Envelope detector
An electronic circuit inside a USB device that monitors the USB data lines and detects certain voltage
related signal characteristics.
EOF
End-of- (micro) Frame.
EOP
End-of-Packet.
External Port
See port.
Eye pattern
A representation of USB signaling that provides minimum and maximum voltage levels as well as signal
jitter.
False EOP
A spurious, usually noise-induced event that is interpreted by a packet receiver as an EOP.
Flush (Endpoint)
Frame
Frame Pattern
Fs
A term used in this device controller implementation to describe the action of clearing an endpoint ready
status.
A 1-millisecond time base established on full-/low-speed buses.
A sequence of frames that exhibit a repeating pattern in the number of samples transmitted per frame.
For a 44.1 kHz audio transfer, the frame pattern could be nine frames containing 44 samples followed by
one-frame containing 45 samples.
See sample rate.
Full-duplex
Computer data transmission occurring in both directions simultaneously.
Full-speed
USB operation at 12 Mb/s. See also low-speed and high-speed
Function
Handshake Packet
High-bandwidth
endpoint
High-speed
Host
A USB device that provides a capability to the host, such as an ISDN connection, a digital microphone,
or speakers.
A packet that acknowledges or rejects a specific condition. For example, see ACK and NAK.
A high-speed device endpoint that transfers more than 1024 bytes and less than3073 bytes per
microframe.
USB operation at 480 Mb/s. See also low-speed and full-speed
The host computer system where the USB Host Controller is installed. This includes the host hardware
platform (CPU, bus, among others) and the operating system in use.
Host Controller
The host’s USB interface.
Host Controller
Driver (HCD)
The USB software layer that abstracts the Host Controller hardware. The Host Controller Driver provides
an SPI for interaction with a Host Controller. The Host Controller Driver hides the specifics of the Host
Controller hardware implementation.
Host Resources
Resources provided by the host, such as buffer space and interrupts. See also Device Resources and
Universal Serial Bus Resources.
Hub
Hub Tier
A USB device that provides additional connections to the USB.
One plus the number of USB links in a communication path between the host and a function.
I/O Request Packet
An identifiable request by a software client to move data between itself (on the host) and an endpoint of
a device in an appropriate direction.
Interrupt Request
(IRQ)
A hardware signal that enables a device to request attention from a host. The host typically invokes an
interrupt service routine to handle the condition that caused the request.
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Table ii. Glossary of Terms and Abbreviations
Term
Definition
Interrupt Transfer
One of the four USB transfer types. Interrupt transfer characteristics are small data, non-periodic, low
frequency, and bounded-latency. Interrupt transfers are typically used to handle service needs. See also
transfer type.
IRP
See I/O Request Packet.
IRQ
See Interrupt Request.
Isochronous Data
A stream of data whose timing is implied by its delivery rate
Isochronous Device An entity with isochronous endpoints, as defined in the USB Specification, that sources or sinks sampled
analog streams or synchronous data streams.
Isochronous Sink
Endpoint
An endpoint that is capable of consuming an isochronous data stream that is sent by the host.
Isochronous Source An endpoint that is capable of producing an isochronous data stream and sending it to the host.
Endpoint
Isochronous Transfer One of the four USB transfer types. Isochronous transfers are used when working with isochronous data.
Isochronous transfers provide periodic, continuous communication between host and device. See also
transfer type.
Jitter
A tendency toward lack of synchronization caused by mechanical or electrical changes. More
specifically, the phase shift of digital pulses over a transmission medium.
kb/s
Transmission rate expressed in kilobits per second.
kB/s
Transmission rate expressed in kilobytes per second.
Little Endian
LOA
Low-speed
Method of storing data that places the least significant byte of multiple-byte values at lower storage
addresses. For example, a 16-bit integer stored in Little Endian format places the least significant byte
at the lower address and the most significant byte at the next address. See also Big Endian.
Loss of bus activity characterized by an SOP without a corresponding EOP.
USB operation at 1.5 Mb/s. See also full-speed and high-speed.
LSb
Least significant bit.
LSB
Least significant byte.
Mb/s
Transmission rate expressed in megabits per second.
MB/s
Transmission rate expressed in megabytes per second.
Message Pipe
Microframe
A bidirectional pipe that transfers data using a request/data/status paradigm. The data has an imposed
structure that enables requests to be reliably identified and communicated.
A 125-microsecond time base established on high-speed buses.
MSB
Most significant byte.
NAK
Handshake packet indicating a negative acknowledgment.
Non Return to Zero
Invert (NRZI)
A method of encoding serial data in which ones and zeroes are represented by opposite and alternating
high and low voltages where there is no return to zero (reference) voltage between encoded bits.
Eliminates the need for clock pulses.
NRZI
See Non Return to Zero Invert.
Object
Host software or data structure representing a USB entity.
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Table ii. Glossary of Terms and Abbreviations
Term
Definition
Packet
A bundle of data organized in a group for transmission. Packets typically contain three elements: control
information (for example, source, destination, and length), the data to be transferred, and error detection
and correction bits.
Packet Buffer
The logical buffer used by a USB device for sending or receiving a single packet. This determines the
maximum packet size the device can send or receive.
Packet ID (PID)
A field in a USB packet that indicates the type of packet and by inference, the format of the packet and
the type of error detection applied to the packet.
Phase
A token, data, or handshake packet. A transaction has three phases
Phase Locked Loop A circuit that acts as a phase detector to keep an oscillator in phase with an incoming frequency.
(PLL)
Physical Device
A device that has a physical implementation; for example, speakers, microphones, and CD players.
PID
See Packet ID.
Pipe
A logical abstraction representing the association between an endpoint on a device and software on the
host. A pipe has several attributes; for example, a pipe may transfer data as streams (stream pipe) or
messages (message pipe) See also stream pipe and message pipe.
PLL
See Phase Locked Loop.
Polling
Asking multiple devices, one at a time, if they have any data to transmit.
POR
See Power On Reset.
Port
Point of access to or from a system or circuit. For the USB, the point where a USB device is attached.
Power On Reset
(POR)
Restoring a storage device, register, or memory to a predetermined state when power is applied.
Prime (Endpoint)
A term used in this device controller implementation to describe the action of readying an endpoint to
transmit or receive data.
Programmable Data A fixed data rate (single-frequency endpoints), a limited number of data rates (32 kHz, 44.1 kHz, 48 kHz,
Rate
…), or a continuously programmable data rate. The exact programming capabilities of an endpoint must
be reported in the appropriate class-specific endpoint descriptors.
Protocol
RA
Rate Adaptation
Request
Retire
A specific set of rules, procedures, or conventions relating to format and timing of data transmission
between two devices.
See rate adaptation.
The process by which an incoming data stream, sampled at Fsi, is converted to an outgoing data stream,
sampled at Fso, with a certain loss of quality, determined by the rate adaptation algorithm. Error control
mechanisms are required for the process. Fsi and Fso can be different and asynchronous. Fsi is the input
data rate of the RA; Fso is the output data rate of the RA.
A request made to a USB device contained within the data portion of a SETUP packet.
The action of completing service for a transfer and notifying the appropriate software client of the
completion.
Root Hub
A USB hub directly attached to the Host Controller. This hub (tier 1) is attached to the host.
Root Port
The downstream port on a Root Hub.
Sample
The smallest unit of data on which an endpoint operates; a property of an endpoint.
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Table ii. Glossary of Terms and Abbreviations
Term
Definition
Sample Rate (Fs)
The number of samples per second, expressed in Hertz (Hz).
Sample Rate
Conversion (SRC)
A dedicated implementation of the RA process for use on sampled analog data streams. The error
control mechanism is replaced by interpolating techniques.
Service
Service Interval
A procedure provided by a System Programming Interface (SPI).
The period between consecutive requests to a USB endpoint to send or receive data.
Service Jitter
The deviation of service delivery from its scheduled delivery time.
Service Rate
The number of services to a given endpoint per unit time.
SOF
See Start-of-Frame.
SOP
Start-of-Packet
SPI
See System Programming Interface.
Split transaction
A transaction type supported by host controllers and hubs. This transaction type enables full- and
low-speed devices to be attached to hubs operating at high-speed.
SRC
See Sample Rate Conversion.
Stage
One part of the sequence composing a control transfer; stages include the Setup stage, the Data stage,
and the Status stage.
Start-of-Frame
(SOF)
The first transaction in each (micro) frame. An SOF enables endpoints to identify the start of the (micro)
frame and synchronize internal endpoint clocks to the host.
Stream Pipe
A pipe that transfers data as a stream of samples with no defined USB structure.
Synchronization
Type
A classification that characterizes an isochronous endpoint’s capability to connect to other isochronous
endpoints.
Synchronous RA
The incoming data rate, Fsi, and the outgoing data rate, Fso, of the RA process, are derived from the
same master clock. There is a fixed relation between Fsi and Fso.
Synchronous SRC
System
Programming
Interface (SPI)
The incoming sample rate, Fsi, and outgoing sample rate, Fso, of the SRC process are derived from the
same master clock. There is a fixed relation between Fsi and Fso.
A defined interface to services provided by system software.
TDM
See Time Division Multiplexing.
TDR
See Time Domain Reflectometer.
Termination
Time Division
Multiplexing (TDM)
Passive components attached at the end of cables to prevent signals from being reflected or echoed.
A method of transmitting multiple signals (data, voice, and/or video) simultaneously over one
communications medium by interleaving a piece of each signal one after another.
Time Domain
An instrument capable of measuring impedance characteristics of the USB signal lines.
Reflectometer (TDR)
Timeout
Token Packet
The detection of a lack of bus activity for some predetermined interval.
A type of packet that identifies what transaction is to be performed on the bus.
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Table ii. Glossary of Terms and Abbreviations
Term
Definition
Transaction
The delivery of service to an endpoint; consists of a token packet, optional data packet, and optional
handshake packet. Specific packets are enabled/required based on the transaction type.
Companion
Controller
A functional component of a USB hub. The Companion Controller responds to special high-speed
transactions and translates them to full/low-speed transactions with full/low-speed devices attached on
downstream facing ports.
Transfer
One or more bus transactions to move information between a software client and its function.
Transfer Type
Determines the characteristics of the data flow between a software client and its function. Four standard
transfer types are defined: control, interrupt, bulk, and isochronous.
Turn-around Time
The time a device needs to wait to begin transmitting a packet after a packet has been received to prevent
collisions on the USB. This time is based on the length and propagation delay characteristics of the cable
and the location of the transmitting device in relation to other devices on the USB.
Universal Serial Bus The host resident software entity responsible for providing common services to clients that are
Driver (USBD)
manipulating one or more functions on one or more Host Controllers.
Universal Serial Bus Resources provided by the USB, such as bandwidth and power. See also Device Resources and Host
Resources
Resources.
Upstream
The direction of data flow towards the host. An upstream port is the port on a device electrically closest
to the host that generates upstream data traffic from the hub. Upstream ports receive downstream data
traffic.
USBD
See Universal Serial Bus Driver.
USB-IF
USB Implementers Forum, Inc. is a nonprofit corporation formed to facilitate the development of USB
compliant products and promote the technology.
Virtual Device
Word
A device that is represented by a software interface layer. An example of a virtual device is a hard disk
with its associated device driver and client software that makes it able to reproduce an audio .WAV file.
A data element that is two bytes (16 bits) in size.
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Book I:
i.MX31 and i.MX31L Integration and Description
Introduction
Book I comprises detailed descriptions and information on the integration of the i.MX31 and i.MX31L
ICs. Book I includes the following chapters.
Device Introduction and Memory Map
Chapter 1, “Introduction to the i.MX31 and i.MX31L Multimedia Applications Processors,” on page 1-1
Chapter 2, “System Memory Map, Interrupts, and SDMA Events,” on page 2-1
Clocks, Power Management and Reset
Chapter 3, “Clocks, Power Management and Reset (AP Clock Controller Module),” on page 3-1
Pins
Chapter 4, “Signal Multiplexing,” on page 4-1
Chapter 5, “General Purpose Input/Output (GPIO),” on page 5-1
Debug
Chapter 6, “Debugging the i.MX31 and i.MX31L,” on page 6-1
Boot
Chapter 7, “i.MX31 and i.MX31L Boot,” on page 7-1
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Chapter 1
Introduction to the i.MX31 and i.MX31L Multimedia
Applications Processors
The i.MX31 and i.MX31L Multimedia Applications Processors are designed for high-tier and mid-tier
smart phone markets. They are a model solution for multimedia and graphics applications that require low
power combined with high performance.
The i.MX31 and i.MX31L processors are built around an ARM1136JF-S™ processor core and are
implemented using 90 nm technology.
NOTE
The MBX R-S graphics accelerator is not available in the i.MX31L
Multimedia Applications Processor.
The system includes the following features:
• Multimedia and floating point hardware acceleration that supports:
— MPEG-4 real-time encoding of up to 30 fps VGA
— MPEG-4 real-time video post processing of up to 30 fps VGA
— Video conference call of up to 30 fps QCIF (decoder in software), 128 Kbps
— Video streaming playback of up to 30 fps VGA, 384 Kbps
— 3D graphics and other application acceleration with the ARM tightly coupled Vector Floating
Point (VFP) coprocessor
— On-the-fly video processing reducing system memory load (for example, power-efficient
Viewfinder application with no involvement of either the memory system or the ARM CPU)
• Advanced power management that includes:
— Dynamic voltage and frequency scaling
— Multiple clock and power domains
— Independent gating of power domains
• Multiple communication and expansion ports, including a fast parallel interface to an external
graphic accelerator (with support for major graphic accelerator vendors)
1.1
Architectural Overview
With their ARM11 microprocessor core, the i.MX31 and i.MX31L processors provide new milestones in
applications processors, delivering the high performance and low-power consumption demanded by
modern digital devices, such as the following:
• Feature-rich cellular phones
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•
•
•
•
Portable media players and mobile gaming machines
Personal digital assistants (PDAs) and wireless PDAs
Portable DVD players
Digital cameras
The heart of the i.MX31 and i.MX31L is an ARM1136JF-S core, which can run at speeds up to 665 MHz
and is optimized for minimal power consumption, using the most advanced techniques for power saving
(including DPTC, DVFS, power gating, and clock gating). With 90 nm technology and dual VT, the
i.MX31 and i.MX31L offer an optimum balance of performance versus current leakage.
Performance is boosted by a multi-level cache system, and the i.MX31 and i.MX31L feature peripheral
devices, such as an MPEG-4 Hardware Encoder (VGA, 30 fps), an autonomous Image Processing Unit, a
Vector Floating Point (VFP11) coprocessor, and a Smart Direct Memory Access (SDMA)/RISC-based
DMA controller.
The i.MX31 and i.MX31L support connections to various types of external memory, such as 266 MHz
DDR, NAND Flash, NOR Flash, SDRAM, and SRAM.
The i.MX31 and i.MX31L can be connected to a variety of external devices using technologies, such as
Universal Serial Bus, On-The-Go, High-Speed (USB 2.0, OTG), ATA-4, MMC/SDIO, and
CompactFlash.
1.1.1
High-Level Block Diagram
Figure 1-1 is a high-level block diagram of the i.MX31 and i.MX31L Multimedia Applications Processors.
Figure 1.2 shows an example scenario of external connections for the i.MX31.
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Introduction to the i.MX31 and i.MX31L Multimedia Applications Processors
i.MX31/i.MX31L
Connectivity
System Control
ARM11 Platform
MSHC x 2
JTAG, Debug
ARM1136JF-S
System Boot
GPIO x 3
VFP
FIR
D Cache
I Cache
PLL and Power
Management
ETM
L2 Cache
SIM
MMC/SD x 2
AVIC
KPP
System Reset
CSPI x 3
UART x 5
System Functions
1-WIRE
Multimedia Peripherals
EPIT x 2
I2C x 3
MPEG-4 Encoder
USBOTG, HS
PWM
USB Host x 2
IPU
WDOG
Sensor
Interface
RTC
ATA
Resize/CSC
Deblock/Dering
GPT x 3
IOMUXC
Blending
External
Memory
Display/TV Control
RAM, ROM
System Control
SSI x 2/
I2S
AIPS x 2
MAX
M3IF
MBX R-S
Graphics
Accelerator*
WEIM
ESDCTL
SDMA
AUDMUX
SPBA
NANDFC
PCMCIA
Security
SCC
RNGA
RTIC
IIM
* The MBX R-S Graphics
Accelerator
is not available in the i.MX31L.
Figure 1-1. i.MX31 and i.MX31L Simplified Block Diagram
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Analog Joystick
Touch-screen
Accessory bus connector
IPC
WLAN
Data
SSI1
Touch
Screen
Power Ctrl
Tamper
Detection
GPIO
1-Wire
UART 5
External
Memory
Interface
(EMI)
i.MX31
SSI2
USB
Host 1
USB
Host2
MMC
SDIO 0/1
133 MHz
16/32
8/16
Keypad
PCMCIA
Data
Data
UART 2
UART 3
FIRI
UART 1
SIM
Image Processing Unit
I2C
Sensor 1
2
18-bit
Base
Band
SPI 1
UART 4
100 MHz
Data
USB
OTG
Fast
IrDA
GPS
60 MHz
12-bit
Voice
SSI
Audio
MUX
Data
Audio
SSI
BT
WB Audio
SSI
Transceiver
USB Phy
NB Audio
SSI
Power Management IC
ATA-6
SPI 2
Serial
LCD
DDR
NAND
Flash
8x8
MIDI
Fingerprint
Parallel
Displ. 1 2
TV
Encoder
Figure 1-2. i.MX31 External Connections Diagram
1.2
Hardware Modules
The hardware modules for the i.MX31 and i.MX31L can be divided into six areas:
• System control
• ARM11 Platform
• Standard system functional elements
• Multimedia and human interface
• Peripherals
• Special functional blocks
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The specific modules that make up each of these areas are listed in the following subsections.
1.2.1
System Control
System control modules provide features such as clocks, debugging, and a wake-up sequence:
• System JTAG Controller (SJC)
• Debug features
• Bootstrap
• Clocks, power management, and reset (AP clock controller module)
• System reset
1.2.2
ARM11 Platform
The ARM11 Platform is based on the ARM11 core, and provides basic processing for the device, as
follows:
• ARM11 core
• VFP
• I-Cache
• D-Cache
• L2 Cache
• ETM
• MAX
1.2.3
Standard System Functional Elements
The modules in this area provide resources and services for the operating system:
• Timers
• PWM
• Watchdog
• RTC
• GPIOs
• RAM and ROM
• Smart Direct Memory Access (SDMA)
1.2.4
Multimedia and Human Interface
The modules in this area provide state-of-the-art multimedia and human interface capabilities:
• MPEG-4 Encoder
• GPU (Graphics Processing Unit, based on the MBX R-S)
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NOTE
The MBX R-S graphics accelerator is not available in the i.MX31L.
•
•
•
•
1.2.5
IPU:
— Sensor interface
— Resize/CSC
— Deblock/Dering
— Blending
— Display and TV control
Keypad
Audio MUX
SSI/I2S
Peripherals
The peripheral devices provide connection capabilities to standard interfaces:
• Fast IrDA
• MMC/SD units
• CSPI units
• UARTs
• 1-Wire
• USBOTG, High-Speed
• USB host units
• SIM
• ATA
• PCMCIA/CF
• External Memory Interface (EMI):
— SDRAM/DDR
— PSRAM
— NAND/NOR Flash
— SmartMedia
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1.2.6
Special Functional Blocks
The special functional blocks are a group of modules and features that provide a complete solution for
system security, including security hardware.
1.2.7
Detailed Block Diagram
Figure 1-3 is a detailed block diagram of the i.MX31 and i.MX31L.
CCM, LPCG,
PLLs
EPIT1
EPIT2
GPT
WDOG
PWM
GPIO1
GPI02
GPI03
RTC
Memory
Stick
Memory
MBX R-S
Graphics
Core
(GPU) (not
available in the
i.MX31L)
Stick
ECT
SJC
CSPI3
GXI master bus
RNGA
EMI
USBOTG
USB
ARM11 Platform
SIM
ETM
SCC
FPU
16 Kbyte L1
16 Kbyte L1
Icache MM Dcache
RTIC
ARM1136JF-
0
1
2
L2-Cache
128
3
4
L2CC0
L2CC
5
6
7
L2CC1
SDRAM
DDR
PCMCIA/CF
NAND
SmartMedia
allp_clk_off
MPEG-4
Encoder
sync_jtag
JSYNC
gated_clocks
IP Bus
CLKCTL
EVTMON
eventmon_int
ETB
INTs
SD/MMC1
int[63:0]
AVIC
ROM PATCH
ALT_BM0
ALT_BM1
SDMA
I2C(x3)
MAX0
M0
M1
M2
MU
CTI
SD/MMC2
gp_control
ALT_BM2
MAX1
16 Kbyte
S0
S1
S2
S3 M3
S4
S5 M4
IP BusA
AIPS A
ROMC
AIPS B
IP BusB
RAMC
SPBA
SSI1
CSPI1
32-Kbyte ROM
boot_ext
over_ride, patch_data[31:0]
IPU
extboot_adr [31:2]
1-WIRE
Audio MUX
ATA
IIM
FIR
COLOR
LEGEND
UART1
UART2
UART3
UART4
UART5
SDMA-DP MemoryMapped Module
MCU MemoryMapped Module
Other Modules like test, PLLs or
memories (all sizes in Kbytes)
CSPI2
DMA
LEGEND
SSI2
Keypad
IOMUXC
Module
without DMA
Module with
DMA-req. to SDMA-DP
Figure 1-3. i.MX31 and i.MX31L Detailed Block Diagram
NOTE
The MBX R-S graphics accelerator is not available in the i.MX31L.
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1.2.8
Applications Processor Core (ARM11 Core)
The core of the i.MX31 and i.MX31L Multimedia Applications Processors is the ARM1136JF-S, which
is based on the innovative ARM v6 architecture. It supports ARM Thumb® instruction sets, and features
Jazelle® technology (which enables direct execution of Java™ bytecodes), as well as a range of SIMD
DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
The ARM1136JF-S processor core features:
• Integer unit with integral EmbeddedICE® logic
• Eight-stage pipeline
• Branch prediction with return stack
• Low-interrupt latency
• Instruction and Data Memory Management units (MMUs), managed by using micro TLB
structures backed by a unified main TLB
• Instruction and Data L1 Caches, including a non-blocking Data cache with Hit-Under-Miss
• Virtually indexed/physically addressed L1 caches
• 64-bit interface to both L1 caches
• Write buffer (bypassable)
• High-Speed Advanced Micro Bus architecture (AMBA) L2 interface
• Vector Floating Point coprocessor (VFP) for hardware acceleration of 3D graphics and other
floating-point applications
• ETM™ and JTAG-based debug support
1.2.8.1
Memory System
The ARM1136JF-S complex includes a 16-Kbyte instruction cache and a 16-Kbyte data L1 cache. The
complex connects to the i.MX31 128 Kbyte L2 unified cache through a read-only 64-bit instruction
interface, a bidirectional 64-bit data read/write interface, and a 64-bit data write interface.
The embedded SRAM (16 Kbyte) can be used for Audio Streaming data to avoid external memory
accesses for applications such as low-power audio playback, security, or other applications. There is also
a ROM (32 Kbyte) for bootstrap code and other frequently used code and data.
1.2.8.1.1
Internal RAM
There are 16 Kbytes of internal SRAM.
1.2.8.1.2
Internal ROM
The ROM is partitioned into two parts (ROM is not aliased):
• The location of the first 16 Kbytes of Secure ROM starts at the lowest part of the memory map, at
address 0×0. After reset, the ARM processor starts running code from this location.
• The remaining 16 Kbytes are mapped at the starting address 0×00404000 (4 Mbytes +16 Kbytes).
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1.2.8.1.3
Internal Registers
The various categories of internal registers are all decoded by the two AIPS modules—AIPS A and
AIPS B. Many registers belong to the ARM11 Platform; others belong to the various off-platform
modules.
• Any write access by the ARM1136JF-S core to off-platform modules encounters two wait states;
that is, any write access lasts for three cycles.
• Any read access by the ARM1136JF-S core from off-platform modules has one wait state; that is,
any read access lasts for two cycles.
• Any number of architected registers can be defined in each peripheral space. Software must
explicitly address the registers without making assumptions regarding multiple mapping.
1.2.9
Interrupts
The i.MX31 and i.MX31L have a dedicated Programmable Interrupt controller for the AP. The controller
handles interrupts generated by associated peripherals and can handle multiple interrupts with varying
priority levels. These characteristics make the controller an excellent solution for administering interrupt
requirements at both the RTOS and SoC level. The controller also has advanced features to reduce module
power consumption.
1.2.9.1
ARM11 Platform Vectored Interrupt Controller (AVIC)
The ARM11 Platform Vectored Interrupt controller (AVIC) provides interrupt support for the ARM-based
peripherals.
The AVIC is a 32-bit peripheral that collects interrupt requests from a maximum of 64 sources and
provides an interface to the ARM1136JF-S core. The AVIC includes hardware acceleration and
software-controlled priority levels for normal interrupts.
The AVIC has hardware for prioritizing interrupts, and it can supply the interrupt vector address of the
highest priority interrupt to the ARM1136JF-S core automatically via an interrupt sideband bus. The
module has an AHB-Lite interface, and can be programmed by the ARM1136JF-S peripheral Advanced
High-Performance Bus (AHB). The AVIC contains a 30×64 memory array to store the vector table.
The following list summarizes AVIC features:
• Supports a maximum of 64 interrupt sources
• Handles fast and normal interrupts
• Selects normal or fast interrupt request for any interrupt source
• Supports hardware accelerated vectoring to service routines for all normal interrupts
• Indicates pending interrupt sources via a register for normal and fast interrupts
• Identifies the highest priority interrupt number via a register, which can be used as a table index
• Can independently enable or disable any interrupt source
• Provides a mechanism for software to schedule an interrupt
• Has an integrated vector table for hardware acceleration of normal interrupt service routine entries
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•
•
Supports a maximum of 16 software-controlled priority levels for normal interrupts and priority
masking
Supports single bit disabling
1.2.10
External Memory Interface (EMI)
The following list describes the main features of the External Memory Interface (EMI):
• Programmable 16-bit or 32-bit wide external data bus
• Address interleaving
• Four input ports with arbitration
• External Bus Alternative Master support (for example, external graphics accelerator IC)
• External Memory Sharing (for example, with a cellular baseband IC)
• Support for standard SRAM and Flash device
• SDRAM controller (up to 133 MHz)
• PSRAM support (up to 133 MHz)
• DDR support with a data rate up to 266 MHz
• NAND Flash support
— Address space to a maximum of 64Gbits.
— One Chip Select
— Support for 8-bit and 16-bit devices, with dedicated IO pins for the 8-bit interface
— Little Endian addressing
— Internal buffer of 2 Kbyte RAM for boot (at start-up) and as a transfer buffer during normal
operation
— Internal automatic Bootloader
— Data protection for buffer RAM and NAND Flash
• SmartMedia card support
• PCMCIA release 2.1 support
— PC Card
— Compact Flash
— TrueIDE mode
• Memory snooping mechanism for minimizing memory traffic when using Smart Displays (For
details, see Section 1.2.17.4, “Image Processing Unit.”)
1.2.11
1.2.11.1
Clock Power Management and Reset
Clocking and Synchronization
The i.MX31 and i.MX31L have several frequency domains. The frequency ratios and absolute values are
flexible, and provide the performance needed to run applications while keeping the operating frequency
as low as possible to save power. Table 1-1 shows some of the fixed frequency ratios.
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Table 1-1. Frequency Domains
FARM
FSL2
FML2
FXBAR
FMEM
F
F
F/2 or F/4
F/2 or F/4
F/4
532
532
133
133
133
432
432
108
108
108
266
266
133
133
133
134
134
67
67
67
1.2.11.2
Power Management
The i.MX31 and i.MX31L use the following advanced power management features:
• Dynamic frequency and voltage scaling (DVFS) with one voltage domain
• Active Well-Biasing (AWB)
• Power gating in standby
• Three power domains (for power gating)
• Independent low power modes for different power domains
The i.MX31’s and i.MX31L’s power domains and their operating modes are as follows:
• ARM11 Platform domain (ARM11 Core + MMU + Caches)
— ARM_Active mode:
The ARM clock frequency can vary between fmax and fmin. The voltage can vary between
Vmax and Vmin.
— ARM_Stop mode:
The mode is a result of STANDBY instruction execution. In this mode, the supply voltage can
be reduced to Vccmin.
— ARM_Standby mode:
This mode is similar to ARM_Stop mode, except the supply voltage is reduced to a minimum
value for data retention and well-biasing is on. ARM is not functional in this mode. Before
attempting to perform any function, increase the supply voltage and disable well-biasing.
— ARM_Shut-down mode:
The ARM power domain supply is off. If ARM state retention is required, save the data from
critical registers before entering Standby mode.
• Peripheral Domain, which includes all the peripherals except the DPLL
— Peripheral_On mode:
Supply of the domain is on.
— Peripheral_Standby mode:
Supply voltage is reduced to minimum for data retention. Well-biasing is on.
— Peripheral_Off mode:
Supply of the domain is off.
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DPLL, included in a separate domain because an unknown influence on operating frequency can
occur while changing voltage in DVFS modes
— DPLL_On mode:
Supply of the domain is on.
— DPLL_Standby mode:
DPLL is in reset. Supply voltage can be reduced to minimum. Well-biasing is on. Restart DPLL
to get the generated output clock.
DPLL_Off mode:
Supply of the domain is off.
1.2.11.3
Reset Module
The reset module controls or distributes all of the system reset signals used by the i.MX31. The reset
module generates seven distinct events—a global reset and a processor reset.
• mcu_reset_out signal is connected to ARM11P and RTIC.
• reset_fuse signal is connected to laser fuses in L2 cache data array.
• ccm_por_reset signal is connected to JTAG.
• periph_reset_out signal is connected to all peripherals except IIM, EMI, WDOG.
• ccm_pll_reset signal is connected to three PLLs and FPM.
• global_reset signal is connected to modules engaged in boot and security (IIM, EMI, MGA, RTC).
• ect_reset signal is connected to ECT module.
1.2.12
Pins
The external pins in the i.MX31 and i.MX31L can be configured for various functions, according to system
use. The memory interface pins are controlled by the EMI, but the rest of the pins are controlled by I/O
MUX (IOMUX) units.
1.2.12.1
Multiplexing, GPIO, and Pad Control Architecture
Peripheral signals are mapped (or multiplexed) to give the end user a great deal of flexibility for
determining the external connections planned for the i.MX31 and i.MX31L implementation. The user can
use software to configure the signals associated with each pin.
The muxing hardware is composed of the following:
• IOMUX—Combinational logic that does the muxing
• IOMUX Controller (IOMUXC)—An IP that consists of memory-mapped registers designed to:
— Control the IOMUX
— Handle interrupt observation
— Control pad settings, for example pull-up, pull-down, hysteresis, and keeper.
• GPIO—An IP that consists of memory-mapped registers used for handling GPIO capabilities—for
example, using software to apply a value on a pad, capturing a value from a pad, or generating
interrupts from pads.
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1.2.13
Security
Tamper detect logic is used to issue a security violation. This logic is activated if the tamper detect pin is
asserted. The tamper detect logic is disabled after reset. After enabling the logic, it is impossible to disable
it until the next reset. For a schematic diagram of the tamper detect logic, refer to Chapter 4, “Signal
Multiplexing.”
1.2.14
1.2.14.1
1.2.14.1.1
Connectivity
Wired Connectivity
UART x 5
Five UART modules in the i.MX31 and i.MX31L support the following serial data transmit/receive
protocols and configurations:
•
•
•
•
Data words of 7-bit or 8-bit length, 1 or 2 stop bits, programmable parity (even, odd, or none)
Programmable baud rates to a maximum of 1.875 Mbit/s
32-byte FIFO on Tx and 32 halfword FIFO on Rx supporting auto-baud
IrDA 1.0 support (to a maximum SIR speed of 115200 bps)
1.2.14.2
USB Module
The USB module in the i.MX31 and i.MX31L is used for inter-processor communication with the
onboard Cellular Modem baseband processor (Host Port #1), for connection to a WLAN/Bluetooth and
other onboard peripherals (Host Port #2), and for communication with external USB devices (OTG
host/device port) via a transceiver IC.
The USB has the following main features:
• EHCI compatibility
• Power-Saving mode for hosts and Suspend mode for other functions
• Transaction scheduling and transfer level protocol implemented in hardware
1.2.14.2.1
USB Host Port 1
USB Host 1 has the following capabilities and features:
• Is compliant with USB 2.0 specification for operation at full speed (12 Mbit/s) and low speed
(1.5 Mbit/s)
• Is designed to support transceiver-less connection to the Cellular Modem baseband processor
1.2.14.2.2
USB Host Port 2
USB Host 2 has the following capabilities and features:
• Is compliant with USB 2.0 specification for operation at high speed (480 Mbit/s), full speed
(12 Mbit/s), and low speed (1.5 Mbit/s).
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Features built-in switching logic to support bypass mode, so an external host can communicate
directly with the Cellular Modem baseband processor.
Is designed to support transceiver-less connection to the onboard peripherals in low speed and full
speed mode, and connection to ULPI (UTMI+ low pin count) and legacy full speed transceivers.
1.2.14.2.3
USBOTG Port
The USBOTG port has the following capabilities and features:
• Is compliant with the OTG Supplement to the USB 2.0 specification
• As a host, operates at high speed, full speed, and low speed; as a device, operates at high speed and
full speed
• Includes Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) implemented in
the hardware with software support. (These protocols are also full controllable by software.)
• Includes built-in switching logic to support bypass mode, so an external host can communicate
directly to the Cellular Modem baseband processor in full speed or low speed
• Is designed to interface with ULPI transceivers (Low Pin Count Supplement to the UTMI+
specification), and legacy full speed transceivers
1.2.14.3
PCMCIA Port
The i.MX31 and i.MX31L PCMCIA Rel.2.1 port is part of the EMI module (described in Section 1.2.10,
“External Memory Interface (EMI)”). The PCMCIA port provides a high data rate interface to external
peripherals (such as WLAN 802.11b) and Compact Flash cards.
1.2.14.4
1.2.14.4.1
Wireless Connectivity
Fast Infrared Interface (FIR)
The Fast Infrared interface (FIR) module supports infrared communication, including the following
features:
• Is compliant with IrDA 1.1 for MIR and FIR. (The IrDA 1.0 Serial Infrared (SIR) protocol can be
supported by one of the UART modules.)
• Has a full physical layer implementation
• Supports 0.56 Mbit/s and 1.152 Mbit/s Medium Infrared (MIR) physical layer protocol
• Supports 4 Mbit/s FIR physical layer protocol defined by IrDA version 1.4
• Generates 16-bit and 32-bit CRC for error detection
1.2.14.4.2
Bluetooth
Connection to high-bit rate communication devices that use Bluetooth wireless technology is supported.
1.2.14.4.3
Wireless LAN 802.11a/b
Connection to high-bit rate communication devices that use WLAN 802.11 a/b technology is supported.
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1.2.15
1.2.15.1
Timers
General Timers
The i.MX31 and i.MX31L include several timers:
• One General Purpose Timer (GPT) for Operating System Real-Time scheduling and waveform
sampling/generation functions. (This timer measures intervals or generates periodic outputs.)
• Two Enhanced Periodic Interrupt Timers (EPIT1,EPIT2) for Operating System Real-Time
scheduling. (This timer provides precise interrupts at regular intervals with minimal processor
intervention.)
1.2.15.2
Watchdog Timer (WDOG)
The Watchdog Timer provides a time-out notification if the system ceases activity for a user-specified
period of time. Both the period of time and the time-out action are programmable.
The Watchdog Timer has the following features:
• Time-out, which is programmable to a value between 0.5–64 s
• Resolution of 0.5 s
In case of a time-out, the following actions can be taken:
• Interrupt to the MPU, which is programmed in software
• Internal reset, which is programmed in software and can follow the interrupt after a predefined
time-out
• External pin toggle for resetting external devices, issued together with the internal reset
1.2.16
1.2.16.1
System Resources
AIPS
The AIPS acts as an interface between the system bus (AHB-Lite 2.v6) and lower bandwidth peripherals
that conform to the IP Bus Specification Rev 3.0 Skyblue line interface (IPS).1
The following list summarizes the key features of the AIPS:
• Supports the IPS slave bus (Skyblue) signals. This interface is only meant for slave mode
peripherals.
• Supports 32-bit IPS peripherals. (AIPS supports byte, halfword, word, and double-word read and
write operations for each peripheral.)
• Supports two global external IPS peripheral spaces (32 Mbyte and 31 Mbyte each)
• Supports a pair of IPS accesses for 64-bit transfers and certain misaligned AHB transfers
• AIPS A directly supports a maximum of 16 on-platform IPS peripherals, with 16 Kbytes of address
space for each one
1. To acquire a copy of this specification, contact Freescale Semiconductors, Inc.
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•
•
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AIPS B directly supports a maximum of 32 on-platform IPS peripherals, with 16 Kbytes of address
space for each one
Supports configurable per-module write buffering
Provides configurable per-module and per-master access protections
Handles peripheral read transactions that require a minimum of two HCLK clocks, and unbuffered
write transactions that require a minimum of three HCLK clocks
Uses one single asynchronous reset and one global clock
Provides Secure Restricted Access Control for different masters to selected peripherals
1.2.16.2
Smart Direct Memory Access Controller (SDMA)
The Smart Direct Memory Access (SDMA) controller maximizes system performance by relieving the
ARM core of the task of the bulk transfer of data from memory to memory or between memory and on-chip
peripherals. The advantage of the SDMA is its dynamic routing capability and its ability to perform
numerous tasks simultaneously based on the DMA channel’s descriptors. Application processor OS
software drivers can make extensive use of DMA channels to minimize software overhead and transfer
latencies.
Each of the 32 DMA channels support linear memory, 2D memory, buffer chaining, FIFO, and Enable
FIFO for both source and destination.
The SDMA controller has the following features:
• Three independent AHB buses, typically used for transferring data between the applications
processor, DSP, and EMI domains
• Dedicated IP Skyblue peripheral bus
• Daisy chain
• Multi-channel DMA with virtual support of up to 32 simultaneous DMA channels
• Very fast context-switching with two-level priority-based preemptive multi-tasking
• DMA units with flush and pre-fetch capability, flexible Endianness, and word sizes that range from
8, 16, or 32 bits in length
• Flexible address management for DMA transfers (increment, decrement, and no address changes
on source and destination address)
• Support for byte swapping
• Buffer for configurable burst transfer (buffer size is a maximum of 16 words long)
• Capacity to be configured to respond to any of the 32 DMA request signals
• Bus utilization control that can be handled by script if needed
• Burst time-out error for terminating the DMA cycle if the burst cannot be completed in the
user-specified length of time
• Buffer overflow—SDMA stops reading if FIFO is full (64 bytes of data)
• Transfer error to terminate the DMA cycle if a transfer error is detected during the DMA burst
• Interrupts provided to interrupt handler, then to the core for bulk data transfer completion or
transfer error events
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Capability for each peripheral that supports DMA transfer to generate a request signal to the DMA
controller. Each FIFO has a unique system address and can generate a dedicated request signal to
the DMA.
Support for single interface peripheral
Small footprint and power-efficient architecture
Power supplied by a 16-bit Instruction Set microRISC engine
Access to a library of scripts and API
1.2.16.3
ATA Controller
The ATA block is an AT attachment host interface. Its main function is to interface with IDE hard disc
drives and ATAPI optical disc drives. It interfaces with the ATA device over a number of ATA signals.
The ATA interface is compliant to the ATA-6 standard, and supports the following protocols:
• PIO mode 0, 1, 2, 3, and 4
• Multiword DMA mode 0, 1, and 2
• Ultra DMA modes 0, 1, 2, 3, and 4 with bus clock of 50 MHz or higher
• Ultra DMA modes 5 with bus clock of 80 MHz or higher
1.2.17
Image, Video and Graphics
Visual data—video and graphics—is handled in the i.MX31 and i.MX31L with the aid of the Image
Processing Unit (IPU), the MPEG-4 Video Encoder module, and software.
1.2.17.1
Video Processing
The i.MX31 processor supports the following video-related activities:
• Capturing video input from an image sensor (support for a maximum of two sensors, no
concurrency)
• Displaying a still image or moving video from a stored file
• A video call
The video processing chain is illustrated in Figure 1-4. The IPU performs the steps displayed in the purple
box. The remaining steps are performed as follows:
• The camera typically performs format conversion and quality enhancement operations after the
image is captured. (This processing chain is typically called post-image processing or
pre-processing.) Any processing the camera does not perform can be handled by ARM processor
software.
• Any controls the camera requires from the applications processor are performed by ARM software.
These controls are transferred to the sensor through an I2C interface, so the IPU is not involved in
the transfer. (The I2C interface is a two-wire, bidirectional serial bus that provides a simple
standard interface to peripherals.)
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ARM software performs other processing. The software implementation provides the flexibility
needed to support a variety of compression algorithms and to adapt as compression standards
evolve.
Image Sensor
Display
Bayer
Combining with
Graphics
Format
Conversion
IPU
YUV
RGB
Format
Conversion
Quality
Enhancement
Resolution
Adjustment
Viewfinder Window
Resolution
Adjustment
Post Filtering
YUV
Compression
Video
Encoder
De-compression
Memory
Combining with
Audio
Separation from
Audio
Communication
Network
Performed By:
Camera (or ARM11 software)
Hardware Module (IPU)
ARM11 Software
Figure 1-4. Video Processing Chain in the i.MX31
1.2.17.2
Graphics Processing Unit
NOTE
The MBX R-S graphics accelerator is not available in the i.MX31L.
The Graphics Processing Unit (GPU) provides hardware acceleration for 2D and 3D graphics algorithms.
GPU acceleration is sufficient to run desktop-quality interactive graphic applications on displays with a
screen resolution equivalent to VGA and above and with color representation up to 32 bits per pixel. The
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i.MX31 GPU uses an ARM MBX R-S graphics accelerator. Figure 1-5 shows the GPU high-level block
diagram.
AHB
Geometry data
AHB
Slave
Interface
Tile
Accelerator
HSR
Engine
Texture
Shading
Unit
Pixel
Blender
Texture
Cache
Display
List
Parser
Event
Manager
Display list
write/read
External
Z-buffer
Display
list read
Texture
Frame
Buffer
Write
Memory Interface Arbiter
Memory Management Unit and Memory
GXI 64-bit * 133 MHz maximum
Figure 1-5. GPU Block Diagram
1.2.17.2.1
Graphics Processing Unit Overview
The GPU consists of the following modules:
• Tile Accelerator (TA)
• Event Manager
• Vertex Geometry processor (VGP)
• Display List Parser
• Hidden Surface Removal (HSR) engine
• Texture Shading unit
• Texture cache
• Pixel Blender
• Memory Interface Arbiter
• Memory Management unit
• GPI (Graphics Port interface) to MBX—master gasket
The GPU operates on 3D scene data, sent as batches of triangles, then transformed and lit by the VGP.
Triangles are written directly to the TA on a First In First Out (FIFO) basis so the CPU does not stall. The
SDMA can also be used to perform batch transfers with minimal CPU involvement.
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The TA performs advanced culling of the triangle data by writing the tiled non-culled triangles to external
memory.
The Event Manager uses SmartBuffer technology for control, so any amount of scene complexity is
handled in a fixed display list buffer size.
The HSR engine reads the tiled data and implements per-pixel HSR with full Z-accuracy. The resulting
visible pixels are textured and shaded in 24 bit Internal True Color (ITC) before the final image is rendered
for the display buffer.
1.2.17.2.2
Graphics Processing Unit Features
The GPU includes the following features:
• Deferred texturing
• Screen tiling
• Flat and Gouraud shading
• Perspective-correct texturing
• Specular highlights
• Floating-point Z-buffer
• 32-bit ARGB internal rendering and layer buffering
• Full tile blend buffer
• Z-load and store mode
• Per-vertex fog
• 16-bit RGB textures, 1555, 565, 4444, 8332, 88
• 32-bit RGB textures, 8888
• YUV 422 textures
• PVR-TC compressed textures
• One-bit textures for text acceleration
• Point, bilinear, trilinear, and anisotropic filtering
• Full range of OpenGL and Direct3D (D3D) blend modes
• Dot3 bump mapping
• Alpha test
• Zero-cost full-scene anti-aliasing
• 2D-via-3D 2D graphics acceleration.
1.2.17.3
Display Management
The i.MX31 controls the transfer of visual data (video and graphics) to the display. The transfer is
performed in the following way:
• Before it is sent to the screen, the data is arranged and stored in a memory buffer called a display
buffer. The data sources update the display buffer whenever required.
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Some applications generate content in a separate background buffer and the data is transferred
periodically to the display buffer. This is necessary, for example, to avoid visual tearing while
displaying frequently changing data. The IPU handles this type of block transfer.
The data from the display buffer is transferred to the display screen at a rate determined by the
display’s needs (as described in Table 1-2). This process is called screen refresh. Screen refresh is
performed by a dedicated controller on the device in which the i.MX31 is installed, typically called
a display controller.
Table 1-2. Refresh Rates and Pixel Formats
Resolution [pixels]
Refresh Rate
Format
Display
up to 640 × 480 (VGA)
up to 100 Hz (typically 70)
RGB, up to 18 BPP
progressive
TV–PAL
704 × 576
25 Hz
TV–NTSC
704 × 480
30 Hz
YCC 4:2:2
8 bit color component
progressive or interlaced
Some display devices, called smart displays, refresh the screen internally. To do this, they include an
integrated controller and memory for the display buffer. The advantage of such an implementation is low
power consumption. However, the data access rate from the applications processor to the display memory
is typically limited by the smart display’s data port bandwidth.
Other display devices, called memory-less displays, have no control capabilities. For such displays, the
screen refresh is performed from a display buffer in the i.MX31’s system memory and is controlled by a
display controller in the i.MX31’s IPU. A TV screen driven by a Digital Video Encoder or DVE also
belongs to this category.
The display devices are typically connected to the i.MX31 through a dedicated display port, controlled by
the IPU.
Smart displays can also be connected to the host through the External Memory Interface (EMI) port. In
this case, they are managed directly by the processor, without involving the IPU.
1.2.17.4
Image Processing Unit
The role of the Image Processing Unit (IPU) is to provide hardware acceleration and control for processing
and displaying visual data (video and graphics) in the i.MX31 and i.MX31L. A schematic description of
the IPU internal structure is illustrated in Figure 1-6.
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External
connections
Image
Sensors
Image Sensor
Interface
Post-Filtering
Resizing
Color
Conversion
Combining
On-chip
connections
Display Interface
AHB
AHB Interface
Displays
Asynchronous
Synchronous
AHB Slave Interface
IP Interface
AHB
IP
Figure 1-6. Image Processing Unit
1.2.17.4.1
External Ports
The IPU receives input from the following sources:
• An image sensor (support for two image sensors, no concurrency)
• System memory
IPU output can be sent to the following destinations:
• System memory
• External display controller or graphics accelerator
• A screen—either an LCD or a TV via a digital video encoder
The IPU also provides a communication channel between the processor and an external display controller
or graphics accelerator. The IPU uses the following ports for communication:
• Image sensor port connected to one or two sensors
• Display port connected to one or two display devices and, optionally, also to a digital video encoder
shared with the External Graphics Accelerator port
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AHB master and slave ports connected to the ARM cross-bar switch
IP port
1.2.17.4.2
Connectivity to Displays
To handle the diversity of displays supported, the IPU uses two types of display interface: synchronous
and asynchronous.
1.2.17.4.3
Synchronous Interface
The synchronous interface is used to transfer a two-dimensional block of pixels to the display, either to
display memory or directly to the screen. When the IPU uses this interface, it also sends the display vertical
and horizontal synchronization signals to make sure the screen refresh cycle and block transfers are
synchronized.
• For a memory-less display (to an LCD device or TV screen), the synchronous interface is used to
perform screen refreshes from a display buffer in system memory.
• For a smart display with an integrated controller, the synchronous interface provides a high-speed
channel to transfer a rectangular block of pixels to the display and still avoid tearing effects.
• The supported display types are summarized in Table 1-3.
Table 1-3. Display Types Supported by the Synchronous Interface
Display Type
Bus Width [Bits]
Monochrome/Color Mode
Notes
TFT LCD
(or smart)
8
up to 256 colors in gray scale
1 bus cycle per pixel
9
up to 512 colors
12
up to 4096 colors
16
up to 64 Kbyte colors
18
up to 256 Kbyte colors
6
up to 256 Kbyte colors
8
up to 16M colors
8
up to 16M colors
TV encoder
1.2.17.4.4
3 bus cycles per pixel
Format: YUV 4:2:2
Encoder is synchronized as a slave.
Asynchronous Interface
The asynchronous interface is used to communicate with the integrated controller of a smart display or a
graphics accelerator. Communication includes updating the on-display buffer. Unlike the synchronous
interface, the asynchronous interface handles these updates without synchronizing them with the screen
refresh cycle.
The main features of the asynchronous interface are as follows:
• Interfaces: parallel (18-bit data) and serial
• Operation modes:
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— Data transfer (DMA)—Read and write operations between the host system’s memory and the
external device. These operations can be performed while either the host or the device are bus
masters.
— Direct access—Read and write operations of the processor to the external device. The IPU
provides the processor with an emulation of the device as a memory-mapped peripheral.
The serial interface pins can be set to tri-state mode to enable the sharing the display device control
with the cellular baseband IC.
1.2.17.4.5
Simultaneous Connectivity
The display port can provide simultaneous connectivity to the following display devices:
• Primary display device—smart or memory-less display or a graphics accelerator
• Secondary display device—a smart display
• Digital video encoder
These devices share most of the port pins as well as parts of the internal interface, so simultaneous use of
the devices is limited. Table 1-4 describes availability for each device.
Table 1-4. Simultaneous Functionality in the Dedicated Port
Secondary Display Type
Smart Display
Serial Interface
Smart Display
Asynchronous Parallel
Interface
TV Screen
Smart Display
Serial Interface
Yes
Yes
Yes
Smart Display
Asynchronous
Parallel Interface
Yes
Yes
Yes, but access to the smart
display is restricted to blanking
intervals.
Graphics Accelerator
Yes
Yes, if the accelerator supports
a chip select functionality.
NA
Dual Port Smart Display
Synchronous + Asynchronous
Parallel Interface
Yes
Yes
NA
TV Screen
Yes
(No Vsync for smart
display)
Yes, but access to the smart
display is restricted to blanking
intervals.
NA
TFT Memory-Less Display
Generic
Yes
Yes, but access to the smart
display is restricted to blanking
intervals.
NA
TFT Memory-Less Display
Sharp HR
NA
Yes, but access to the smart
display is restricted to blanking
intervals.
NA
Primary Display Type
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1.2.17.4.6
IPU Processing
The IPU processes rectangular blocks of pixels. The block must be part of a progressive (non-interlaced)
video or graphics stream. Its format can be either RGB or YUV. The IPU has two processing chains:
post-processing and video capturing.
1.2.17.4.7
•
•
•
•
Input from system memory:
— Frame size is a maximum of 1024 × 1024 pixels.
— Input rate is a maximum of 9M pixels/s (for example, VGA at 30 fps).
Processing:
— Post-filtering
— Resizing
— Color space conversion
— Combining with a graphics plane
— Inversion and rotation
Outputs:
— For a reference frame in H.264 decoding, output is after post-filtering.
— For display, output is after combining.
Post-processing is mainly used for a video stream after decompression. Post-processing can also
be applied without post-filtering to a graphics block, however.
1.2.17.4.8
•
•
•
Post-Processing
Video Capturing
Input is from an image sensor. (The i.MX31 supports a maximum of two sensors.)
— Frame size is a maximum of 4096 × 4096 pixels.
— Input rate is a maximum of 30M pixels/s (for example, UXGA at 15 fps).
Processing:
— Resizing
— Color space conversion
— Combining with a graphics plane
— Inversion and rotation
Outputs:
— For encoding, output is in YUV format and occurs after resizing.
— For display, output is in RGB format and occurs after combining, with independent resizing.
The display output is sent either to system memory through the AHB master port or to display memory by
using the asynchronous display interface. The preferred destination is display memory, which produces
minimal power consumption.
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1.2.17.4.9
Processing Stages
The processing stages have the following features:
Post-Filtering
• De-blocking and de-ringing for YUV 4:2:0 format
Resizing
• Fully flexible resizing ratio that is independent for horizontal and vertical resizing
• Maximum downsizing is 16:1 during video recapturing and 8:1 during post-processing.
• Subject to this limitation, any N->M resizing can be performed
Color Space Conversion
• Flexible conversion using a configurable conversion matrix and offsets, in particular the following
conversions:
— YUV <-> RGB, YUV<->YUV conversions
— Color adjustment
Combining
• Two planes can be combined: for example, you can add a graphics plane on top of a video plane.
• You can specify the transparency of the upper (graphics) plane by using either a key color, a global
alpha parameter, or an individual alpha parameter for each pixel.
Inversion and Rotation
• Horizontal and vertical rotation
• Rotation at a 90 degree angle
— Rotation performed during post-processing, by reading and writing 2D blocks and rotating
them internally.
— If a video frame is received from the sensor, rotation can be performed by first writing it to
external memory, then reading it in back in blocks.
1.2.17.4.10
Automatic Procedures
The IPU is equipped with all the control capabilities needed to perform its tasks with minimal ARM
involvement and minimal memory use. In particular, the IPU uses the following controls:
• A master AHB port and DMA control functionality and enable the IPU to access system memory
autonomously.
• An integrated display controller enables the IPU to synchronize the screen refresh cycle with the
internal processing chains and to transfer processed video and graphics data directly to the display.
This synchronization helps avoid tearing effects.
• The IPU also features internal synchronization between sensor input and display output.
• The EMI sends the IPU direct indications about changes in system memory buffers (snooping).
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Introduction to the i.MX31 and i.MX31L Multimedia Applications Processors
The IPU can perform complex procedures automatically without involving the processor—thus saving
power. The following list describes some important examples of this type of procedure:
• Screen refresh for memory-less displays.
• Periodic update of the display buffer in a smart display. This can be done conditionally (only when
needed) by using the snooping mechanism mentioned previously.
• Viewfinder (a video stream from the image sensor to the display).
• Video capturing (a video stream from the image sensor to memory, for compression).
1.2.17.5
MPEG-4 Video Encoder
The MPEG-4 encoder accelerates video compression, following the MPEG-4 standard.
The encoder has the following main features:
• Compression formats: MPEG-4 simple profile (all levels), H.263 baseline
• Pixel rate: a maximum of VGA at 30 fps
• Compressed bit-rate: a maximum of 4 Mbps
• Essentially performs the complete video processing chain, generating a Huffman-coded stream.
Only the formation of the final MPEG-4 stream is performed by the processor.
• Additional processing:
— Picture smoothening (low-pass filter)
— Camera movement stabilization
— Enhanced conference call format, which inserts additional information in the MPEG stream.
An MPEG-4 decoder uses the additional information to improve performance.
1.2.18
Audio Interfaces
The i.MX31 and i.MX31L processors have a flexible audio architecture with multiple possibilities for
routing narrowband audio (voice) and wideband audio (Hi-Fi).
1.2.18.1
Synchronous Serial Interface or Inter-IC Sound (SSI/I2S) Module
Depending on system programming, the same module can provide Synchronous Serial interface or
Inter-IC Sound (SSI/I2S) capabilities.
The SSI/I2S features:
•
•
•
•
•
•
Generic SSI interface support for an external audio processor
Support for Philips standard Inter-IC Sound (I2S) bus for external digital audio processor interface
Non-integer clock divider for bit rate generation
Independent transmit and receive sections that operate in master or slave mode
Operation in normal and network mode
Support for AC-97 standard
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Introduction to the i.MX31 and i.MX31L Multimedia Applications Processors
1.2.18.2
Digital Audio MUX
The Digital Audio MUX (AUDMUX) supports various audio applications. The Digital Audio MUX is
configured by software. Figure 1-7 shows a schematic diagram of the AUDMUX.
WB
NB
BB
SSI1
SSI2
Audio1
BT
Audio2
WB
Audio3
NB
Audio4
CE bus
SAP
Figure 1-7. Digital Audio MUX (AUDMUX)
1.2.19
Debug Features
The i.MX31 and i.MX31L debug features handle hardware and software debugging and silicon validation,
either on evaluation boards, on customer application boards, or even on a closed or opened radio device.
Debugging helps identify and isolate causes of failure when you run hardware and software in real
applications. The failure source could be in the software or hardware (for example, a race condition).
The i.MX31 and i.MX31L debug hardware also supports system profiling. You can use system profiling
to improve overall system performance by identifying optimal system configurations.
Because of the multi-core nature of the i.MX31 and i.MX31L, all internal cores have their own dedicated
debug features and ports so you can perform parallel debugging on the processor (ARM11) core and
peripherals along with the Smart Direct Memory Access (SDMA) core. The debug architecture of the
i.MX31 and i.MX31L encompasses the individual cores’ debug components and shared debug
components. The individual cores share the following resources:
• The JTAG controller port, which is used to communicate with each of the multiple cores
• The ECT module, which is used to control cross trigger events among the multiple cores
In addition, secure JTAG options are provided to protect debug resources from attacks by unauthorized
users. The secure JTAG design prevents the debug architecture from compromising security.
Figure 1-8 shows a block diagram of the i.MX31 and i.MX31L along with the debug-related I/O.
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JTAG
port
DE
pin
ETM
ATP
GPIO
signals
i.MX31 and i.MX31L
Figure 1-8. i.MX31 and i.MX31L Debug Port Scheme
1.2.19.1
Features
The i.MX31 and i.MX31L provide a full set of features for multi-core debugging. The overall debug
system for the i.MX31 and i.MX31L consists of the following elements and features:
• Multi-core debug support is provided by multi-core debuggers via the System JTAG Controller
(SJC) and the extensive cross trigger support of the Embedded Cross Trigger (ECT) module.
• Static debug support is provided via the System JTAG Controller (SJC) and appropriate accesses
to ICE/OnCE resources on the cores. Support is provided for debug start, stop, single-step, break
points, and access to CPU and system resources.
• Non-intrusive real-time instruction and data tracing is supported on the (ETM11) processor.
• ROM patching is supported on the processor. Patching is used to effectively replace data in a ROM
memory location. Patching can also enable the software to execute different instructions from the
instructions that reside in ROM.
• It is possible to MUX internal signals by using the IOMUX to processor IOs. Critical signals can
be routed to the top level SoC pads for external visibility.
• Limited time stamping support in the processor domain is facilitated by using three counters in the
PMU of the ARM11 processor, in conjunction with other resources such as the ETM and the ECT
module.
• Performance profiling is supported for processor domains: for example, it is possible to count the
number of processor stalls, L1 cache hits, L2 cache misses, or external memory accesses that have
occurred. Profiling data is accessible by the software and can be used to optimize system
configurations for optimal performance.
1.2.20
Boot
The i.MX31 and i.MX31L system boot up is designed according to the configuration of the boot fuses in
the IIM and the external BOOT pins. The sequence is therefore divided into Boot-external, Boot-internal,
Bootloader, and In-Factory security test modes.
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Introduction to the i.MX31 and i.MX31L Multimedia Applications Processors
The system boot flow is defined in the i.MX31 processor. The boot flow controls booting, ensures that the
system boots up in a predefined secure path, and ensures that the software in the Flash ROM runs on the
correct system. This process helps prevent unauthorized modifications to the trusted OS. The process also
turns the Flash ROM into tamper-evident memory, protecting it against unauthorized key extraction,
hacking program downloads, and viruses.
ARM
core
HAB procedure
High Assurance Boot
SCC
Security Monitor
RTIC
SHA-1 algorithm accelerator
Run-Time Integrity Check
The boot flow uses security hardware and software components to protect the Flash image and to create a
well-bonded secure-based platform for the core and other functional modules. The boot components are
shown in Figure 1-9.
Flash
Volatile
Memory
Figure 1-9. Boot Components
The ARM core interfaces with the SCC and operates the HAB procedure. The HAB procedure is stored in
Flash memory and uses volatile memory for its operation. During boot, the RTIC is in operation and
performs its tasks.
1.2.20.1
Boot Features
The boot flow has the following features:
• The system boots up in a predefined secure path.
• The boot flow prevents unauthorized modifications to the trusted OS by ensuring that software in
Flash ROM runs on the correct system.
• Boot action effectively makes Flash ROM tamper-evident memory.
• The boot flow protects against unauthorized access, hacking, and viruses.
• Boot modes are divided into Boot-external, Boot-internal, Bootloader, and In-Factory security test
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Chapter 2
System Memory Map, Interrupts, and SDMA Events
This chapter provides information on the memory map, internal ROM and RAM, internal register space,
peripheral access types, external memory, interrupts, and SDMA events for the i.MX31 and i.MX31L
applications processors.
2.1
Memory Map
The ARM1136JF-S processor’s physical memory is mapped according to the addresses shown in
Table 2-1.
Table 2-1. Memory Map
Start Address
End Address
Size
Name
0x000 00000
0x0000 3FFF
16 Kbyte
Secure ROM
0x0000 0000
0x0040 3FFF
4 Mbyte–16 Kbyte
Reserved
0x0040 4000
0x0040 7FFF
16 Kbyte
ROM
0x0040 8000
0x0FFF FFFF
252 Mbyte–32 Kbyte
Reserved
0x1000 0000
0x1FFF BFFF
256 Mbyte–16 Kbyte
Reserved for RAM aliasing
0x1FFF C000
0x1FFF FFFF
16 Kbyte
RAM
0x2000 0000
0x2FFF FFFF
256 Mbyte
Reserved
0x3000 0000
0x3FFF FFFF
256 Mbyte
L2CC configuration Registers
0x4000 0000
0x41FF FFFF
32 Mbyte
AIPS A off platform global module enable #0
0x4200 0000
0x43EF FFFF
31 Mbyte
AIPS B off platform global module enable #1
0x43F0 0000
0x43F0 3FFF
16 Kbyte
AIPS A Control registers on platform slot 0
0x43F0 4000
0x43F0 7FFF
16 Kbyte
AIPS A MAX on platform slot 1
0x43F0 8000
0x43F 0BFFF
16 Kbyte
AIPS A EVTMON on platform slot 2
0x43F0 C000
0x43F0 FFFF
16 Kbyte
AIPS A CLKCTL on platform slot 3
0x43F1 0000
0x43F1 3FFF
16 Kbyte
AIPS A ETB registers on platform slot 4
0x43F1 4000
0x43F1 7FFF
16 Kbyte
AIPS A ETB Memory on platform slot 5
0x43F1 8000
0x43F1 BFFF
16 Kbyte
AIPS A ECT CTIO on platform slot 6
0x43F1 C000
0x43F7 FFFF
400 Kbyte
Reserved AIPS A on platform slots
0x43F8 0000
0x43F8 3FFF
16 Kbyte
I2C
0x43F8 4000
0x43F8 7FFF
16 Kbyte
I2C3
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Table 2-1. Memory Map (continued)
Start Address
End Address
Size
Name
0x43F8 8000
0x43F8 BFFF
16 Kbyte
USBOTG
0x43F8 C000
0x43F8 FFFF
16 Kbyte
ATA (control port)
0x43F9 0000
0x43F9 3FFF
16 Kbyte
UART1
0x43F9 4000
0x43F9 7FFF
16 Kbyte
UART2
0x43F9 8000
0x43F9 BFFF
16 Kbyte
I2C2
0x43F9 C000
0x43F9 FFFF
16 Kbyte
1-WIRE
0x43FA 0000
0x43FA 3FFF
16 Kbyte
SSI1
0x43FA 4000
0x43FA 7FFF
16 Kbyte
CSPI1
0x43FA 8000
0x43FA BFFF
16 Kbyte
KPP
0x43FA C000
0x43FA FFFF
16 Kbyte
IOMUXC
0x43FB 0000
0x43FB 3FFF
16 Kbyte
UART4
0x43FB 4000
0x43FB 7FFF
16 Kbyte
UART5
0x43FB 8000
0x43FBBFFF
16 Kbyte
ECT (IP BUS 1)
0x43FB C000
0x43FBFFFF
16 Kbyte
ECT (IP BUS 2)
0x43FC 0000
0x43FFFFFF
256 Kbyte
Reserved AIPS A off platform slots
0x44000 000
0x4FFFFFFF
192 Mbyte
Reserved (aliased AIPS A slots)
0x5000 0000
0x5000 3FFF
16 Kbyte
SPBA base address
0x5000 4000
0x5000 7FFF
16 Kbyte
MMC/SDHC1
0x5000 8000
0x5000 BFFF
16 Kbyte
MMC/SDHC2
0x5000 C000
0x5000 FFFF
16 Kbyte
UART3
0x5001 0000
0x500 13FFF
16 Kbyte
CSPI2
0x5001 4000
0x500 17FFF
16 Kbyte
SSI2
0x5001 8000
0x500 1BFFF
16 Kbyte
SIM
0x5001 C000
0x500 1FFFF
16 Kbyte
IIM
0x5002 0000
0x5002 3FFF
16 Kbyte
ATA (DMA port)
0x5002 4000
0x5002 7FFF
16 Kbyte
MSHC1
0x5002 8000
0x5002 BFFF
16 Kbyte
MSHC2
0x5002 C000
0x5002 FFFF
16 Kbyte
Reserved
0x5003 0000
0x5003 3FFF
16 Kbyte
Reserved
0x5003 4000
0x5003 7FFF
16 Kbyte
Reserved
0x5003 8000
0x5003 BFFF
16 Kbyte
Reserved
0x5003 C000
0x5003 FFFF
16 Kbyte
SPBA Registers
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Table 2-1. Memory Map (continued)
Start Address
End Address
Size
Name
0x5004 0000
0x51FF FFFF
32 Mbyte-256 Kbyte
Reserved AIPS B off platform global module
enable #0
0x5200 0000
0x53EF FFFF
31 Mbyte
AIPS B off platform global module enable #1
0x53F0 0000
0x53F0 3FFF
16 Kbyte
AIPS B Control registers on platform slot 0
0x53F0 4000
0x53F7 FFFF
496 Kbyte
Reserved AIPS B on platform slots
0x53F8 0000
0x53F8 3FFF
16 Kbyte
CCM
0x53F8 4000
0x53F8 7FFF
16 Kbyte
CSPI3
0x53F8 8000
0x53F8 BFFF
16 Kbyte
Reserved
0x53F8 C000
0x53F8 FFFF
16 Kbyte
FIR
0x53F9 0000
0x53F9 3FFF
16 Kbyte
GPT
0x53F9 4000
0x53F9 7FFF
16 Kbyte
EPIT1
0x53F9 8000
0x53F9 BFFF
16 Kbyte
EPIT2
0x53F9 C000
0x53F9 FFFF
16 Kbyte
Reserved
0x53F A0000
0x53FA 3FFF
16 Kbyte
Reserved
0x53FA 4000
0x53FA 7FFF
16 Kbyte
GPIO3
0x53FA 8000
0x53FA BFFF
16 Kbyte
Reserved
0x53FA C000
0x53FA FFFF
16 Kbyte
SCC
0x53FB 0000
0x53FB 3FFF
16 Kbyte
RNGA
0x53FB 4000
0x53FB 7FFF
16 Kbyte
Reserved
0x53FB 8000
0x53FB BFFF
16 Kbyte
Reserved
0x53FB C000
0x53FB FFFF
16 Kbyte
Reserved
0x53FC 0000
0x53FC 3FFF
16 Kbyte
IPU
0x53FC 4000
0x53FC 7FFF
16 Kbyte
AUDMUX
0x53FC 8000
0x53FC BFFF
16 Kbyte
MPEG4_Encoder
0x53FC C000
0x53FC FFFF
16 Kbyte
GPIO1
0x53FD 0000
0x53FD 3FFF
16 Kbyte
GPIO2
0x53FD 4000
0x53FD 7FFF
16 Kbyte
SDMA
0x53FD 8000
0x53FD BFFF
16 Kbyte
RTC
0x53FD C000
0x53FD FFFF
16 Kbyte
WDOG
0x53FE 0000
0x53FE 3FFF
16 Kbyte
PWM
0x53FE 4000
0x53FE 7FFF
16 Kbyte
Reserved
0x53FE 8000
0x53FE BFFF
16 Kbyte
Reserved
0x53FE C000
0x53FE FFFF
16 Kbyte
RTIC
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Table 2-1. Memory Map (continued)
Start Address
2.1.1
End Address
Size
Name
0x53FF 0000
0x53FF 3FFF
16 Kbyte
Reserved
0x53FF 4000
0x53FF 7FFF
16 Kbyte
Reserved
0x53FF 8000
0x53FF BFFF
16 Kbyte
Reserved
0x53FF C000
0x53FF FFFF
16 Kbyte
Reserved
0x5400 0000
0x5FFF FFFF
192 Mbyte
Reserved (aliased AIPS B slots)
0x6000 0000
0x67FF FFFF
128 Mbyte
ROMPATCH
0x6800 0000
0x6BFF FFFF
128 Mbyte
AVIC
0x7000 0000
0x7FFF FFFF
256 Mbyte
IPU (MAX M2)
0x8000 0000
0x8FFF FFFF
256 Mbyte
CSD0 SDRAM/DDR
0x9000 0000
0x9FFF FFFF
256 Mbyte
CSD1 SDRAM/DDR
0xA000 0000
0xA7FF FFFF
128 Mbyte
CS0 (Flash) 128 Mbyte
0xA800 0000
0xAFFF FFFF
128 Mbyte
CS1 (Flash) 64 Mbyte
0xB000 0000
0xB1FF FFFF
32 Mbyte
CS2 (SRAM)
0xB200 0000
0xB3FF FFFF
32 Mbyte
CS3 (Spare)
0xB400 0000
0xB5FF FFFF
32 Mbyte
CS4 (Spare)
0xB600 0000
0xB7FF FFFF
32 Mbyte
CS5 (spare)
0xB800 0000
0xB800 0FFF
4 Kbyte
NAND Flash
0xB800 1000
0xB800 1FFF
4 Kbyte
ESDCTL registers
0xB800 2000
0xB800 2FFF
4 Kbyte
WEIM registers
0xB800 3000
0xB800 3FFF
4 Kbyte
M3IF Registers
0xB800 4000
0xB800 4FFF
4 Kbyte
PCMCIA_IF registers
0xB800 5000
0xBBFF 5FFF
64 Mbyte–20 Kbyte
Reserved
0xBC00 0000
0xBFFF FFFF
64 Mbyte
PCMCIA/CF
0xC000 0000
0xC3FF FFFF
64 Mbyte
GACC
0xC400 0000
0xFFFF FFFF
960 Mbyte
Reserved
Internal RAM
The Internal RAM base address is 0x1FFF C000.
2.1.2
Internal ROM
The Internal ROM is partitioned into two parts, as follows (ROM is not aliased):
• The first 16 Kbytes of Secure ROM is located starting at the lowest part of the memory map, from
address 0x0. As such, the ARM processor will start running code from this location after reset.
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•
2.1.3
The remaining 16 Kbytes are mapped starting at 0x00404000 (4 Mbyte +16 Kbyte).
Internal Register Space
There are various categories of internal registers, all of which are decoded by the two AIPS modules,
AIPS A and AIPS B (see Chapter 38, “AHB-Lite 2.v6 to IP Bus Interface (AIPS)”).
• Many registers belong to the ARM11 Platform, and others belong to the various off-platform
modules.
• Any ARM1136JF-S core write access to off-platform modules will experience two wait states (any
write access will last for three cycles).
• Any ARM1136JF-S core read access from these modules will have one wait state (any read access
will last for two cycles).
Within each peripheral space, any number of architected registers may be defined (as outlined in the
chapter for each peripheral), and software should explicitly address them making no assumptions
regarding multiple mapping.
2.1.4
Peripheral Access Types
Table 2-2 shows how different types of accesses are treated by each module.
• Y—The module can be accessed in that access type
• N—The module cannot be accessed in that access type
• O—It is possible to access the peripheral in that access type but there may be unwanted side affects.
So, it should be treated as unsupported.
For example, the 1-Wire module has Read/Write 8-bit capability, but does not have Read/Write 16-bit
capability; the SSI module has capability for all of these types, but there may be unwanted results.
Table 2-2. Peripheral Access Type
Access
Type ->
8 Bit-Access 8 Bit-Access
16-Bit
Access
16-Bit
Access
Name
Access
Width \/
Read
Write
Read
Write
I2C
16-bit
Y
Y
Y
Y
SIM
16-bit
Y
N
Y
N
UART
32-bit
O
O
Y
Y
1-WIRE
8-bit
Y
Y
N
N
SSI
32-bit
O
O
O
O
CSPI
32-bit
O
O
O
O
FIR
32-bit
N
N
N
N
GPT
32-bit
O
O
O
O
SCC
32-bit
N
N
N
N
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System Memory Map, Interrupts, and SDMA Events
Table 2-2. Peripheral Access Type (continued)
Access
Type ->
8 Bit-Access 8 Bit-Access
16-Bit
Access
16-Bit
Access
Name
2.1.5
Access
Width \/
Read
Write
Read
Write
RNGA
32-bit
N
N
N
N
IPU
32-bit
Y
Y
Y
Y
Digital Audio MUX
32-bit
O
O
O
O
GPIO
32-bit
O
O
O
O
RTC
32-bit
Y
Y
Y
Y
Watchdog
16-bit
Y
Y
Y
Y
PWM
32-bit
O
O
O
O
Keypad
16-bit
Y
Y
O
O
USBOTG
32-bit
N
N
N
N
External Memory
There are 896 Mbytes of the memory map allocated for external chip access.
There are nine external chip selects, which are allocated as follows:
• 256 Mbyte for each CSD1–CSD0
• 32 Mbyte for each CS5–CS2
• 128 Mbyte for each CS1–CS2 and
• 64 Mbyte for the PCMCIA/CF
2.1.6
•
•
•
•
2.2
2.2.1
Misaligned Accesses
The i.MX31supports misaligned accesses to external memories supported by the ESDCTL and
WEIM modules.
The i.MX31 does not support misaligned accesses to NAND Flash and PCMCIA_IF.
The i.MX31 does not support misaligned access to peripherals residing on the AIPS buses.
The IPU slave AHB bus supports misaligned accesses.
Interrupts
Interrupt Operation
The description of the ARM11 Platform Vectored Interrupt Controller can be found in Chapter 9,
“ARM1136JF-S Vectored Interrupt Controller (AVIC).”
Each module will send one or more interrupt request to the AVIC.
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The existence of an interrupt is reflected in the value of a bit in the Interrupt Pending register. It is the
responsibility of the software to determine the underlying reason of the interrupt when servicing it. This is
done by reading the status register of the module whose interrupt is being serviced. Once the interrupt has
been serviced, and at the end of the interrupt service routine, software explicitly clears the interrupt in
accordance with the appropriate value in the status register of the module in question.
2.2.2
Interrupt Summary Table
Table 2-3 shows the interrupts in the i.MX31 and i.MX31L Multimedia Applications Processors.
Each module can send one or more interrupt requests to the ARM11 Platform Vectored Interrupt Controller
(AVIC).
While servicing an interrupt, it is the software’s responsibility to read the peripheral module’s
status/interrupt register and determine which event from the peripheral module generated the interrupt.
Table 2-3. Interrupt Summary
Interrupt
Source
Description
Interrupt
Source
Description
0
Reserved
—
32
UART2
OR’ed (rx,tx,mint)
1
Reserved
—
33
NANDFC
NAND Flash Controller
2
Reserved
—
34
SDMA
Smart Direct Memory
Access
3
I2C3
Inter-Integrated Circuit 3
35
USB
Host 1
4
I2C2
Inter-Integrated Circuit 2
36
USB
Host2
5
MPEG4_Encoder
MPEG-4 Encoder
37
USB
OTG
6
RTIC
Depending on the mode an
Interrupt indicates that a
HASH error has occurred, or
the RTIC has completed
hashing.
38
Reserved
—
7
FIR
Fast Infrared Controller
39
MSHC1
Memory Stick Host
Controller 1
8
MMC/SDHC2
module
MultiMedia/Secure Data
Host Controller 2
40
MSHC2
Memory Stick Host
Controller 2
9
MMC/SDHC1
MultiMedia/Secure Data
Host Controller 1
41
IPU
Image Processing Unit error
10
I2C module
MultiMedia/Secure Data
Host Controller
42
IPU
IPU general interrupt
11
SSI2 module
Synchronous Serial Interface
1
43
Reserved
12
SSI1 module
Synchronous Serial Interface
2
44
Reserved
13
CSPI2 module
Configurable Serial
Peripheral Interface 2
45
UART1 Module
OR’ed (rx,tx,mint)
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Table 2-3. Interrupt Summary (continued)
Interrupt
Source
Description
Interrupt
Source
Description
14
CSPI1 module
Configurable Serial
Peripheral Interface 1
46
UART4 module
OR’ed (rx,tx,mint)
15
ATA controller
HArd Drive (ATA) Controller
47
UART5 module
OR’ed (rx,tx,mint)
16
MBX R-S
Graphic accelerator
48
ect_irq
AND of oct_irq_b[1:0]
17
CSPI3 module
Configurable Serial
Peripheral Interface 3
49
SCC module
SCM interrupt
18
UART3 module
OR’ed (rx,tx,mint)
50
SCC module
SMN interrupt
19
IIM module
IC Identification
51
GPIO2 module
General Purpose I/O 2
20
SIM module
Subscriber Identification
Module
52
GPIO1 module
General Purpose I/O 1
21
SIM module
Subscriber Identification
Module
53
CCM
Clock controller
22
RNGA module
Random Number Generator
Accelerator
54
PCMCIA module
23
EVTMON module
OR of evtmon_interrupt,
pmu_irq
55
WDOG module
Watch Dog Timer
24
KPP module
Keyboard Pad Port
56
GPIO3 module
General Purpose I/O 3
25
RTC module
Real Time Clock
57
Reserved
26
PWM module
Pulse Width Modulator
58
External (power
management)
27
EPIT2 module
Enhanced Periodic Timer 2
59
External (Temper)
28
EPIT1 module
Enhanced Periodic Timer 1
60
External (sensor)
29
GPT module
General Purpose Timer
61
External (sensor)
30
Power fail
62
External (WDOG)
31
CCM (DVFS)
63
External (TV)
Table 2-4 lists the interrupt sources that connect directly to the CCM (dsm_wakeup_int[31:0] input).
These sources are used to wakeup the i.MX31 and i.MX31L from DSM mode. Sources can be masked in
the Wake-Up Interrupt Mask Register (WIMR0) shown on page 3-27.
If the WAMO (bit 10) in CCM Control Register (CCMR) shown on page 3-9 is set, then this mechanism
is also used for State Retention (SR) mode. When enabled, interrupts from ARM are ignored.
Table 2-4. Interrupt Sources
Mask bit in WIMRO
Interrupt Source
WIM0
GPIO 3
WIM1
GPIO 2
WIM2
GPIO 1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
2-8
Freescale Semiconductor
System Memory Map, Interrupts, and SDMA Events
Table 2-4. Interrupt Sources (continued)
Mask bit in WIMRO
2.3
Interrupt Source
WIM3
PCMCIA
WIM4
Watch Dog Timer
WIM5
USB On the Go
WIM6
ipi_int_uh2
WIM7
ipi_int_uh1
WIM8
ipi_int_uart5_anded
WIM9
ipi_int_uart4_anded
WIM10
ipi_int_uart3_anded
WIM11
ipi_int_uart2_anded
WIM12
ipi_int_uart1_anded
WIM13
ipi_int_sim_data_irq
WIM14
ipi_int_sdhc2
WIM15
ipi_int_sdhc1
WIM16
ipi_int_rtc
WIM17
ipi_int_pwm
WIM18
ipi_int_kpp
WIM19
ipi_int_iim
WIM20
ipi_int_gpt
WIM21
ipi_int_firi
WIM22
ipi_int_epit2
WIM23
ipi_int_epit1
WIM24
ipi_int_cspi2
WIM25
ipi_int_cspi1
WIM26
ipp_ind_power_fail
WIM27
ipi_int_cspi3
WIM28
Reserved
WIM29
Reserved
WIM30
Reserved
WIM31
Reserved
Smart Direct Memory Access (SDMA) Events
Table 2-5 provides a summary of the Smart Direct Memory Access (SDMA) events.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
2-9
System Memory Map, Interrupts, and SDMA Events
Table 2-5. SDMA Events Summary
Event Number
Module
Description
31
IPU OR ECT
IPU or ECT sources, defaults to IPU at reset.
30
NAND Flash
29
SSI1 Module
SSI #1 transmit 1 DMA request
28
SSI1 Module
SSI #1 receive 1 DMA request
27
SSI1 Module
SSI #1 transmit 2 DMA request
26
SSI1 Module
SSI #1 receive 2 DMA request
25
SSI2 Module
SSI #2 transmit 1 DMA request
24
SSI2 Module
SSI #2 receive 1 DMA request
23
SSI2 Module
SSI #2 transmit 2 DMA request
22
SSI2 Module
SSI #2 receive 2 DMA request
21
MMC/SDHC2/MSHC
2
MMC/SDHC2 DMA request OR MSHC2
20
MMC/SDHC1/MSHC
1
MMC/SDHC1 DMA request OR MSHC1
19
UART1 Module
TxFIFO
18
UART1 Module
RxFIFO
17
UART2/FIR
TxFIFO of UART2 or DMA request of FIR’s
transmitter FIFO controlled by the pgp_firi signal
from the IOMUXC PGP register.
16
UART2/FIR
RxFIFO of UART2 or DMA request of FIR’s
receiver FIFO controlled by the pgp_firi signal from
the IOMUXC PGP register.
15
EXTDMAREQ1
External DMA request from GPIO1_1
14
EXTDMAREQ2
External DMA request from GPIO1_2 or from MBX
(Graphic accelerator)
13
UART4 Module
TxFIFO
12
UART4 Module
RxFIFO
11
UART5
Module/CSPI3
TxFIFO or CSPI3 Tx request
10
UART5
Module/CSPI3
RxFIFOor CSPI3 Rx request
9
CSPI1
Module/UART3
Module
DMA Tx request of CSPI/TxFIFO of UART3
8
CSPI1
Module/UART3
Module
DMA Rx request of CSPI/RxFIFO of UART3
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
2-10
Freescale Semiconductor
System Memory Map, Interrupts, and SDMA Events
Table 2-5. SDMA Events Summary (continued)
Event Number
Module
Description
7
CSPI2 Module
DMA Tx request
6
CSPI2 Module
DMA Rx request
5
SIM module
4
ATA
ata_rcv_fifo_alarm
3
ATA
ata_tx_fifo_alarm
2
ATA
ata_txfer_end_alarm
1
CCM
DVFS/DPTC event (ccm_dvfs_sdma_int)
0
EXTDMAREQ0
External DMA request from GPIO1_0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
2-11
System Memory Map, Interrupts, and SDMA Events
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
2-12
Freescale Semiconductor
Chapter 3
Clocks, Power Management and Reset (AP Clock Controller
Module)
The Clock Controller Module (CCM) controls the system frequency, distributes clocks to various parts of
the chip, controls the reset mechanism of the chip, and provides an advanced low-power management
capability for the i.MX31 and i.MX31L processors.
3.1
Overview
The CCM includes these distinctive features:
• Frequency Pre-Multiplier (FPM) and PLLs control
• Clock distributions—division of PLLs output clock and clock source selectors
• Reset Controller—generate reset signals to the core and to the peripherals
• CCM registers are accessible via IP bus
• Power manager controls power modes and special techniques, such as AWB, power gating, DPTC.
3.2
PLLs
The i.MX31 and i.MX31L processors have three Digital PLLs (DPLLs) in the system that generate three
separate clock frequencies from the PLL reference clock. The PLL reference clock, in turn, can be
generated either from an external high frequency source (CKIH), or from a low frequency source that has
been passed through a Frequency Pre-Multiplier (FPM).
The DPLLs and the choice of specific clock source is accomplished by programming the PLL registers,
which are part of the CCM registers.
3.2.1
PLL Reference Clock Sources
The PLL can have one of two clock sources: an external high frequency source (CKIH), or a low frequency
source that is passed through a Frequency Pre-Multiplier (FPM).
3.2.1.1
External High Frequency Clock—CKIH
One of the potential input clocks to the CCM is an external high frequency clock that can be connected to
the CKIH pin. It can be used as one of sources for the PLL reference clock.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-1
Clocks, Power Management and Reset (AP Clock Controller Module)
3.2.1.2
Frequency Pre-Multiplier (FPM)
In case of a low-frequency input clock, the required Multiplication Factor (MF) becomes extremely large
(~3000). Such requirement is non-trivial for the PLL and the modern Digital PLL does not support it.
Configuring the Analog PLL with such a large MF may result in unstable output clocks, very large
frequency jitters (up to 5–10%), and very long lock time (~2000 CKIL clock periods).
The Digital PLL will be used with an additional fully digital Pre-Multiplier (FPM). The FPM creates a
relatively stable output clock with constant frequency that equals 1024*(CKIL frequency).
The FPM therefore can be used as one of the sources for the PLL reference clock.
3.2.1.3
PLL Reference Clock Switch Unit
The PLL reference clock is pll_ref_clk and is generated by the PLL reference clock switch unit. See
Figure 3-1 for a schematic diagram of this unit. Section 3.2.1.1, “External High Frequency Clock—CKIH”
and Section 3.2.1.2, “Frequency Pre-Multiplier (FPM)” provide information on two clocks (CKIH and
FPM) that function as possible clock sources. CKIH is always the selected clock source in PLL bypass test
mode. Selection is accomplished between CKIH and FPM by external pin signal ipp_clkss during reset.
Selection between the two sources can be done in S/W by setting the PRCS bits in the Control Register
(CCMR). When a different clock source is selected, the new clock source will be automatically enabled.
Only after it becomes available will switching be done. If CKIH is selected, the value of the OSCNT bits
may be updated with the delay time that CKIH will be available. After switching is done, the previously
selected clock source will be automatically disabled.
(ipt_ckih_sel&ipt_pll_bypass_en)
|| ipt_scan_mode_ccm || ipt_scan_mode_clocks
fpm_ckil512_clk
0
1
pll_ref_clk
clk_cleaner
prcs [1:0]
fpm_ready_flag
select
ctl
ckih_receiver_en
ipp_clkss
ckih
Figure 3-1. PLL Reference Clock Switch Unit
3.2.2
High Frequency Clock Source
There are three DPLLs in the system that generate three separate clock frequencies from the PLL reference
clock.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-2
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
The MCU PLL, configured by the MPCTL register, produces the mcu_main _clk clock. The MCU clock
sub-domain is generated from that clock.
The USB PLL, configured by the UPCTL register, produces the clock for the USB circuitry (60 MHz).
This clock can be used for FIR. When the clock is used for FIR it can be programmed to be 46 MHz (MIR
mode) or 60 MHz (FIR mode). Since the USB requires a 60-MHz clock and FIR (when in MIR mode)
requires a 46 MHz clock, it is impossible to use the USB_PLL for MIR and the USB at the same time.
3.3
CCM
The CCM controls the system frequency, distributes clocks to various parts of the chip, controls the reset
mechanism of the chip, and provides an advanced low-power management capability for the i.MX31 and
i.MX31L.
3.3.1
Features
The CCM includes the following distinctive features:
• Frequency Pre-Multiplier (FPM) and PLLs control
• Clocks’ distributions—Division of PLLs output clock and clock source selectors
• Reset Controller—Generate reset signals to the core and to the peripherals
• CCM registers are accessible via the IP bus.
• Power manager controls power modes and special techniques, such as AWB, power gating, DPTC.
3.3.2
External Signal Description
The CKO pin can be used to output internal clock signals. It is controlled by the COSR register in the
CCM. See Table 3-11 for a detailed description of the COSR settings.
3.4
Register Definition and Memory Map
The CCM has 28 user accessible 32-bit registers used to configure, operate and monitor the state of the
CCM. Section 3.4.3, “Register Descriptions” provides the detailed descriptions for all of the CCM
registers.
3.4.1
Memory Map
Table 3-1 shows the CCM memory map.
Table 3-1. CCM Memory Map
Address
Register
Access
Reset Value
Section/Page
0x53F8_0000
(CCMR)
Control Register (CCMR)
R/W
0x074B_0B7B1
0x074B_0B7D1
3.4.3.1/3-9
0x53F8_0004
(PDR0)
Post Divider Register 0 (PDR0)
R/W
0xFF87_0B48
3.4.3.2/3-12
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-3
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-1. CCM Memory Map (continued)
Address
Register
Access
Reset Value
Section/Page
0x53F8_0008
(PDR1)
Post Divider Register 1 (PDR1)
R/W
0x49FC_FE7F
3.4.3.3/3-14
0x53F8_ 000C
(RCSR)
Reset Control and Source Register (RCSR)
R/W
0x007F_0000
3.4.3.4/3-15
0x53F8_ 0010
(MPCTL)
MCU PLL Control Register (MPCTL)
R/W
0x0400_1800
3.4.3.5/3-17
0x53F8_ 0014
(UPCTL)
USB PLL Control Register (UPCTL)
R/W
0x0405_1C03
3.4.3.6/3-19
0x53F8_ 0018
(SPCTL)
Serial PLL Control Register (SPCTL)
R/W
0x0404_3001
3.4.3.7/3-21
0x53F8_ 001C
(COSR)
Clock Out Source Register (COSR)
R/W
0x0000_0280
3.4.3.8/3-23
0x53F8_ 0020
(CGR0)
Clock Gating Register 0 (CGR0)
R/W
0xFFFF_FFFF
3.4.3.9/3-24
0x53F8_ 0024
(CGR1)
Clock Gating Register 1 (CGR1)
R/W
0xFFFF_FFFF
3.4.3.9/3-24
0x53F8_ 0028
(CGR2)
Clock Gating Register 2 (CGR2)
R/W
0xFFFF_FFFF
3.4.3.9/3-24
0x53F8_ 002C
(WIMR0)
Wake-up Interrupt Mask Register (WIMR)
R/W
0xFFFF_FFFF
3.4.3.10/3-27
0x53F8_ 0030
(LDC)
Latch Divergence Counter Register (LDC)
R/W
0x0000_0000
3.4.3.11/3-27
0x53F8_ 0034
(DCVR0)
DPTC Comparator Value Register 0 (DCVR0)
R/W
0x0000_0000
3.4.3.12/3-28
0x53F8_ 0038
(DCVR1)
DPTC Comparator Value Register 1 (DCVR1)
R/W
0x0000_0000
3.4.3.12/3-28
0x53F8_ 003C
(DCVR2)
DPTC Comparator Value Register 2 (DCVR2)
R/W
0x0000_0000
3.4.3.12/3-28
0x53F8_ 0040
(DCVR3)
DPTC Comparator Value Register 3 (DCVR3)
R/W
0x0000_0000
3.4.3.12/3-28
0x53F8_ 0044
(LTR0)
Load Tracking Register 0 (LTR0)
R/W
0x0000_0000
3.4.3.13/3-29
0x53F8_ 0048
(LTR1)
Load Tracking Register 1 (LTR1)
R/W
0x0000_4040
3.4.3.14/3-30
0x53F8_ 004C
(LTR2)
Load Tracking Register 2 (LTR2)
R/W
0x0000_0000
3.4.3.15/3-31
0x53F8_ 0050
(LTR3)
Load Tracking Register 3 (LTR3)
R/W
0x0000_0000
3.4.3.16/3-32
0x53F8_ 0054
(LTBR0)
Load Tracking Buffer Register 0 (LTBR0)
R
0x0000_0000
3.4.3.17/3-33
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-4
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-1. CCM Memory Map (continued)
1
Address
Register
Access
Reset Value
Section/Page
0x53F8_ 0058
(LTBR1)
Load Tracking Buffer Register 1 (LTBR1)
R
0x0000_0000
3.4.3.18/3-34
0x53F8_ 005C
(PMCR0)
Power Management Control Register 0 (PMCR0)
R/W
0x8020_9828
3.4.3.19/3-35
0x53F8_ 0060
(PMCR1)
Power Management Control Register 1 (PMCR1)
R/W
0x00AA_0000
3.4.3.20/3-38
0x53F8_ 0064
(PDR2)
Post Divider Register 2 (PDR2)
R/W
0x0000_0285
3.4.3.21/3-39
Default value of CCMR depends on the setting of the external signal CLKSS as this effects default setting of PRCS.
3.4.2
Register Summary
Figure 3-2 shows the key to the register fields and Table 3-2 shows the register figure conventions.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT
bit
only bit
Write-only
bit
BIT
Write 1 BIT Self-clear 0
to clear
bit
w1c
BIT
N/A
Figure 3-2. Key to Register Fields
Table 3-2. Register Figure Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
r
Read only. Writing this bit has no effect.
w
Write only.
rw
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing
bit
Writing a one has some effect on the module, but it always reads as zero.
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-5
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-2. Register Figure Conventions (continued)
Convention
Description
u
Unaffected by reset.
[signal_name] Reset value is determined by polarity of indicated signal.
Table 3-3 shows the CCM register summary.
Table 3-3. CCM Register Summary
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0x53F8_0000
(CCMR)
L2P
G
VST WBE
BY
N
FPM
CSC PER
F
S
CS
0
0
SSI2S
W
R
0
LPM
WA
MO
FIRS
W
UPE SPE MDS
R
SBY
MPE
CS
ROMW
0
PRCS
FPM
E
0
CSI_PODF
0x53F8_0004
(PDR0)
RAMW
SSI1S
PER_PODF
W
R
0
0
HSP_PODF
NFC_PODF
IPG_PODF
USB_PODF
FIRI_PRE_PODF
MAX_PODF
MCU_PODF
W
R
USB_PRDF
SSI2_PRE
_PODF[2:1]
FIRI_PODF
W
0x53F8_0008
(PDR1)
0x53F8_ 000C
(RCSR)
0x53F8_ 0010
(MPCTL)
R SSI2
_PR
E_P
W ODF[
0]
SSI2_PODF
R NF16 NFM
B
S
W
R PER
W ES
0
R BRM
W O
0
R
0
0
0
0
SSI1_PRE_PODF
BTP
4
BTP
3
BTP
2
BTP
1
0
0
0
0
SDM
SSI1_PODF
BTP
0
OSCNT
GPF
WFI
S
PD
MFD
MFI
MFN
0
REST
W
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-6
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-3. CCM Register Summary (continued)
Name
0x53F8_ 0014
(UPCTL)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R BRM
W O
0
R
0
0
PD
MFD
MFI
MFN
PD
MFD
MFI
MFN
W
0x53F8_ 0018
(SPCTL)
R BRM
W O
0
R
0
0
W
R
0x53F8_ 001C
(COSR)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLK
OEN
0
0
0
W
R
W
CLKOUTDIV
CLKOSEL
R
0x53F8_ 0020
(CGR0)
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
R
W
R
0x53F8_ 0024
(CGR1)
W
R
W
R
0x53F8_ 0028
(CGR2)
W
R
W
0x53F8_ 002C
(WIMR0)
0x53F8_ 0030
(LDC)
R WIM
W 31
WIM
30
WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R WIM
W 15
WIM
14
WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM WIM
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R LDC
W 31
LDC
30
LDC
29
LDC
28
LDC
27
LDC
26
LDC
25
LDC LDC LDC
24
23
22
LDC
21
LDC
20
LDC
19
LDC
18
LDC
17
LDC
16
R LDC
W 15
LDC
14
LDC
13
LDC
12
LDC
11
LDC
10
LDC
9
LDC LDC LDC
8
7
6
LDC
5
LDC
4
LDC
3
LDC
2
LDC
1
LDC
0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-7
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-3. CCM Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ULV
0x53F8_ 0034
(DCVR0)
LLV
W
R
LLV
ELV
W
R
ULV
0x53F8_ 0038
(DCVR1)
LLV
W
R
LLV
ELV
W
R
ULV
0x53F8_ 003C
(DCVR2)
LLV
W
R
LLV
ELV
W
R
ULV
0x53F8_ 0040
(DCVR3)
LLV
W
R
LLV
ELV
W
0x53F8_ 0044
(LTR0)
0x53F8_ 0048
(LTR1)
0x53F8_ 004C
(LTR2)
0x53F8_ 0050
(LTR3)
R SIGD SIGD SIG
14
D13
W 15
0
R SIGD SIGD SIG
11
D10
W 12
SIG
D9
R SIGD SIGD SIG
14
D13
W 15
0
R SIGD SIGD SIG
11
D10
W 12
SIG
D9
R SIGD SIGD SIG
14
D13
W 15
0
R SIGD SIGD SIG
11
D10
W 12
SIG
D9
R SIGD SIGD SIG
14
D13
W 15
0
R SIGD SIGD SIG
11
D10
W 12
SIG
D9
UPTHR
SIG
D8
SIG
D7
SIG
D6
SIG
D5
DNTHR
SIG
D4
SIG
D3
SIG
D2
SIG
D1
UPTHR
SIG
D8
SIG
D7
SIG
D6
SIG
D5
SIG
D7
SIG
D6
SIG
D5
SIG
D4
SIG
D3
SIG
D2
SIG
D1
SIG
D7
SIG
D6
SIG
D5
SIG
D0
0
DIV3CK
DNTHR
SIG
D4
SIG
D3
SIG
D2
SIG
D1
UPTHR
SIG
D8
0
DIV3CK
DNTHR
UPTHR
SIG
D8
SIG
D0
SIG
D0
0
DIV3CK
DNTHR
SIG
D4
SIG
D3
SIG
D2
SIG
D1
SIG
D0
0
DIV3CK
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-8
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-3. CCM Register Summary (continued)
Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0x53F8_ 0054
(LTBR0)
LTS7
LTS6
LTS5
LTS4
LTS3
LTS2
LTS1
LTS0
LTS15
LTS14
LTS13
LTS12
LTS11
LTS10
LTS9
LTS8
W
R
W
R
0x53F8_ 0058
(LTBR1)
W
R
W
R
DFSUP
0x53F8_ 005C
(PMCR0)
DVSUP
UDS
C
DVF DVFI LBM
EV
S
I
VSCNT
LBF
L
UPD
PTVI TEN
S
LBCF
W
R FSV
W AIM
R
0
FSVAI
0
0
DPV DPV
CR
V
0
0
WFI
M
0
DRC DRC DRC DRC DCR DVF
E3
E2
E1
E0
EN
0
PTV
AIM
PTVAI
DPT
EN
0
WBCN
0x53F8_ 0060
(PMCR1)
W
R
0
0
0
PWT NWT CPF
S
S
A
CPSPA
W
R
0x53F8_ 0064
(PDR2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DVGP
0
0
0
0
0
0
W
R
MST2_PDF
MST1_PDF
W
3.4.3
Register Descriptions
This section contains the detailed register descriptions for the CCM registers.
3.4.3.1
Control Register (CCMR)
Figure 3-3 shows the register; Table 3-4 provides the register’s field descriptions.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-9
Clocks, Power Management and Reset (AP Clock Controller Module)
0x53F8_0000 (CCMR)
31
30
29
R
L2PG
W
Reset
Access: User Read/Write
28
27
25
24
VSTB WBE FPMF
PERC
CSCS
Y
N
S
23
22
21
0
20
19
18
17
0
SSI2S
16
RAMW
SSI1S
0
0
0
0
0
1
1
1
0
1
0
0
1
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WAM
O
UPE
SPE
MDS
0
1
1
0
R
0
LPM
FIRS
W
Reset
26
0
0
0
0
1
ROMW
1
1
SBYC
MPE
S
1
1
PRCS1
0
0
FPME
1
Figure 3-3. Control Register (CCMR)
1
Default value of PRCS depends on the setting of the external signal CLKSS. Refer to bit definition of the PRCS bits for more
details.
Table 3-4. CCMR Field Descriptions
Field
Description
31–30
Reserved
29
L2PG
L2 cache power gating enable. The MCU writes to this bit to indicate that supply of L2 cache should be disabled
when the MCU enters State Retention mode.
0 L2 cache supply is not to be shutdown when MCU enters State Retention mode.
1 L2 cache supply is to be shutdown when MCU enters State Retention mode.
28
VSTBY
Supply regulator standby mode enable. The MCU writes to this bit to indicate that the supply regulator should be
placed in Standby mode when the MCU enters State Retention or Deep Sleep modes.
0 Supply regulator will not be put in standby mode when the MCU enters State Retention or Deep Sleep modes.
1 Supply regulator will be put in Standby mode when the MCU enters State Retention or Deep Sleep modes.
27
WBEN
ARM domain well-bias enable bit. This bit enables the well-biasing of modules in the ARM11P. Well-biasing can be
activated only after the MCU has entered Standby mode and max_halted signal is asserted. If the MCU entered
Standby mode and this bit is set, the well-biasing mechanism is enabled.
0 Well-bias is disabled.
1 Well-bias is enabled.
26
FPMF
FPM multiplying factor.
1 = 1024
25
CSCS
ipg_clk_csi_baud clock generation source. This clock can be generated from SRPLL or USB clock domain sources
0 USB clock domain source is selected
1 SRPLL clock domain source is selected
24
PERCS
23
ipg_per_clk clock generation source. This clock can be generated from ipg_clk or USB clock domain source
0 USB clock domain source is selected
1 ipg_clk is selected
Reserved
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-10
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-4. CCMR Field Descriptions (continued)
Field
22–21
SSI2S
20
Description
SSI2 post divider clock source select
00 MCU CLK
01 usb_clk
10 serial_clk (default)
11 reserved
Reserved
19–18
SSI1S
SSI1 post divider clock source select
00 mcu clk
01 usb_clk
10 serial_clk (default)
11 Reserved
17–16
RAMW
wait state control bits for ARM RAM
00 0 Wait states for both ARM and alternate masters
01 0 Wait states and 1 wait state for alternate masters—not recommended for i.MX31 uses.
10 1 Wait state for ARM and 0 wait states for alternate masters—not recommended for the i.MX31 and i.MX31L
uses.
11 1 Wait state for both ARM and alternate masters.
15–14
LPM
These bits define which Low Power Mode the i.MX31 and i.MX31L will enter when the WFI command is next
executed by the MCU.
00 Wait mode
01 Doze mode
10 State retention mode
11 Deep sleep mode
13
Reserved
12–11
FIRS
FIR post divider clock source select
00 mcu clk
01 usb_clk
10 serial_clk
11 Reserved
10
WAMO
Wakeup interrupt mask.
0 Masked in all modes but DSM
1 Masked in all modes but SR or DSM
9
UPE
USB PLL enable bit. This bit enables/disables the USB PLL. This bit cannot be set when selected clock source is
disabled.
0 USB PLL disabled.
1 USB PLL enabled.
8
SPE
Serial PLL enable bit. This bit enables/disables the Serial PLL. This bit cannot be set when selected clock source
is disabled.
0 Serial PLL disabled.
1 Serial PLL enabled.
7
MDS
MCU clock Domain source select. This bit selects the source of the MCU domain post divider. If the MCU PLL is
disabled in run mode, the MCU PLL cannot be the MCU clock domain source. The default MCU clock domain
source is MCU PLL.
0 MCU PLL is the MCU clock domain source
1 Reference clock is the MCU clock domain source (bypass)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-11
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-4. CCMR Field Descriptions (continued)
Field
Description
6–5
ROMW
Wait state control bit from ARM ROM
00 0 Wait states for both ARM and alternate masters
01 0 Wait states and 1 wait state for alternate masters—not recommended for the i.MX31 and i.MX31L uses.
10 1 Wait state for ARM and 0 wait states for alternate masters—not recommended for the i.MX31 and i.MX31L
uses.
11 1 Wait state for both ARM and alternate masters.
4
SBYCS
Clock source enable in Standby mode. This bit determines whether or not the selected clock source for the MCU
clock domain will be disabled in Standby mode. This is applied to all reference clocks involved in the specific clock
generation. To enter Deep Sleep Mode (see Section 3.5.2, “Power Modes”), all other clock sources should be
disabled by software before the system enters Standby mode. This ensures proper interrupt command execution.
0 Clock source is disabled in Standby mode.
1 Clock source is enabled in Standby mode.
3
MPE
MCU PLL enable. This bit enables/disables the MCU PLL. If MCU PLL is disabled, MCU clock domain source will
be automatically switched to pll_ref_clk. When MCU PLL is re-enabled, the MCU clock domain source will be
automatically switched to the MCU PLL output, after which MCU PLL will be re-locked.
0 MCU PLL is disabled
1 MCU PLL is enabled.
2–1
PRCS
PLL reference clock select bits. These bits select the reference clock of all PLLs. This bit can be modified only when
the MCU PLL is disabled. When a reference clock source is changed, the relevant clock source will be automatically
enabled, and only after it is available, clock sources will be switched to the new source. After that the other source
will be disabled. The default value of these bits is defined by external signal ipp_clkss (CLKSS).
00 Reserved
01 FPM
10 CKIH
11 Reserved
0
FPME
FPM enable bit. This bit defines if the FPM will be enabled. This applies even if it was not selected as reference
clock source.
0 FPM is disabled.
1 FPM is enabled.
3.4.3.2
Post Divider Register 0 (PDR0)
Figure 3-4 shows the register; Table 3-5 provides the register’s field descriptions.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-12
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
0x53F8_0004 (PDR0)
31
30
29
Access: User Read/Write
28
27
26
25
24
23
R
22
21
0
0
20
19
CSI_PODF
18
17
16
PER_PODF
W
Reset
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
HSP_PODF
NFC_PODF
IPG_PODF
MAX_PODF
MCU_PODF
W
Reset
0
0
0
0
1
0
1
1
0
1
0
0
1
0
0
0
Figure 3-4. Post Divider Register 0 (PDR0)
Table 3-5. PDR0 Field Descriptions
Field
Description
31–23
CSI_PODF
These bits control the CSI post divider. See Figure 3-24, which shows a diagram of the role the CSI post
divider plays.
000000000 Divide by 1
000000001 Divide by 2
——
111111111 Divide by 512
22–21
Reserved
20–16
These bits control the per post-divider. See Figure 3-24, which shows a diagram of the role the per post
PER_PODF divider plays
00000Divide by 1
00001Divide by 2
——
11111Divide by 32
15–14
Reserved
13–11
These bits control the hsp post divider, which plays a part in generating the IPU high speed clock. See
HSP_PODF Figure 3-24.
Warning: Before changing the post divider of the IPU high speed clock, first ensure that the IPU itself has
been enabled because the Clock Controller Module waits for an acknowledge from the IPU. To enable the
IPU, simply set the DI_EN bit (bit 6) in the IPU_CONF register. Refer to Chapter 44, “Image Processing
Unit (IPU) for more details.
000 Divide by 1
001 Divide by 2
——
111 Divide by 8
10–8
These bits control the NFC post divider of the nfc_clk (nfc divider). See Figure 3-24.
NFC_PODF 000 Divide by 1
001 Divide by 2
——
111 Divide by 8
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-13
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-5. PDR0 Field Descriptions (continued)
Field
Description
7–6
IPG_PODF
These bits control the peripheral clock post divider. See Figure 3-24.
00 Divide by 1
01 Divide by 2
10 Divide by 3
11 Divide by 4
5–3
These bits control the hclk post divider. See Figure 3-24.
MAX_PODF 000 Divide by 1
001 Divide by 2
——
111 Divide by 8
2–0
These bits control the MCU post divider. See Figure 3-24.
MCU_PODF 000 Divide by 1
001 Divide by 2
——
111 Divide by 8
3.4.3.3
Post Divider Register 1 (PDR1)
Figure 3-5 shows the register; Table 3-6 provides the register’s field descriptions.
0x53F8_0008 (PDR1)
31
30
29
Access: User Read/Write
28
27
26
25
24
23
22
21
20
19
18
R
USB_PRDF
USB_PODF
FIRI_PRE_PODF
0
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
R SSI2_
PRE_
W POD
F[0]
Reset
16
SSI2_PRE_
PODF[2:1]
FIRI_PODF
W
Reset
17
1
SSI2_PODF
1
1
1
1
SSI1_PRE_PODF
1
1
0
0
1
SSI1_PODF
1
1
1
1
Figure 3-5. Post Divider Register 1 (PDR1)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-14
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-6. PDR1 Field Descriptions
Field
Description
31–30
USB_PRDF
These bits control the USB pre divider. See Figure 3-24.
00 Divide by 1
——
11 Divide by 4
29–27
USB_PODF
These bits control the USB post divider. See Figure 3-24.
000 Divide by 1
——
111 Divide by 8
26–24
FIRI_PRE_PODF
These bits control the FIR pre divider. See Figure 3-24.
000 Divide by 1
——
111 Divide by 8
23–18
FIRI_PODF
These bits control the FIR post divider. See Figure 3-24.
000000 Divide by 1
——
111111 Divide by 64
17–15
SSI2_PRE_PODF
These bits control the SSI2 pre divider. See Figure 3-24.
000 Divide by 1
——
111 Divide by 8
14–9
SSI2_PODF
These bits control the SSI2 post divider. See Figure 3-24.
000000 Divide by 1
——
111111 Divide by 64
8–6
SSI1_PRE_PODF
These bits control the SSI1 pre divider. See Figure 3-24.
000 Divide by 1
——
111 Divide by 8
5–0
SSI1_PODF
These bits control the SSI2 post divider. See Figure 3-24.
000000 Divide by 1
——
111111 Divide by 64
3.4.3.4
Reset Control and Source Register (RCSR)
Figure 3-6 shows the register; Table 3-7 provides the register’s field descriptions.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-15
Clocks, Power Management and Reset (AP Clock Controller Module)
0x53F8_ 000C (RCSR)
31
30
R NF16 NFM
B
S
W
Reset
29
28
0
0
27
26
25
24
23
22
21
20
19
18
17
16
BTP4 BTP3 BTP2 BTP1 BTP0
OSCNT
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R PERE
S
W
Reset
Access: User Read/Write
0
0
0
SDM
0
0
GPF
0
0
0
0
0
0
0
REST
WFIS
0
0
0
0
0
0
Figure 3-6. Reset Control and Source Register (RCSR)
Table 3-7. RCSR Field Descriptions
Field
Description
31
NF16B
This bit defines bit select for NAND Flash device on the EMI.
0 8 bit
1 16 bit
30
NFMS
This bit defines page size for NAND Flash device. Its default (reset) value is defined by decoding the boot mode
pins.
0 512-byte page size
1 2 Kbyte page size
29–28
Reserved
27–23
BTPn
[4–0]
These read only bits reflect the value of the boot pins, and are sampled upon reset negation.
See Chapter 7, “i.MX31 and i.MX31L Boot.”
22–16
OSCNT
Oscillator ready counter value. These bits define the value of 32 KHz counter. This counter serves as the counter
for the external high speed clock oscillator lock time.
0000000Count 1 cycle
——
1111111Count 128 cycles
15
PERES
Peripheral S/W reset bit. Writing “1” to this bit will result in a reset of all peripherals on MCU side, except CCM
and PLLs.
0 MCU peripherals are not in the process of being reset.
1 MCU peripherals are in the process of being reset.
14
13–12
SDM
Reserved
Scan divergence mode bits.
00 Disable scan divergence mode
01 Clocks to the MCU will be stopped one cycle after the counter finishes counting. The LDC register value will
not change
10 Clocks to the MCU will be stopped after counter finishes counting and value of LDC register will be
decremented by 1.
11 Clocks to the MCU will be stopped two cycles after the counter finishes counting and value of LDC register
will be incremented by 1.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-16
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-7. RCSR Field Descriptions (continued)
Field
Description
11–8
Reserved
7–5
GPF
General purpose Flag Bits. This bits are reset by the reset_in_por input pin. This bits can be used as warm start
parameters or for debug purposes. For example, the user can write a value to these bits before turning off the
voltage. This value can then be used by the wake up routine for the wake up scenario purposes.
4
WFIS
WFI Pending SW control bit
0 No software control
1 SW control to emulate WFI pending behavior.
3
Reserved
2–0
REST
Reset status bits. Shows what caused the most recent reset to the system. If several sources’ signals overlap
and if the signals are released during the same CLK32 cycle (which also causes the assertion of the
RESET_OUT signal), only the highest–priority event is registered by the REST using the following priority order:
• POR external reset signal
• Qualified external reset signal
• Watchdog signal
• S/W reset
Otherwise, the last signal that is released is honored.
000 POR external reset
001 Qualified external reset
010 Watchdog timeout
011 Reserved
100 Reserved
101 Reserved
110 JTAG (s/w or IEEE) reset
111 ARM11P power gating
3.4.3.5
MCU PLL Control Register (MPCTL)
Figure 3-7 shows the register; Table 3-8 provides the register’s field descriptions.
0x53F8_ 0010 (MPCTL)
31
R BRM
W O
Reset
R
30
Access: User Read/Write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
PD
MFD
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
MFI
MFN
W
Reset
0
0
0
1
1
0
0
0
0
0
0
Figure 3-7. MCU PLL Control Register (MPCTL)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-17
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-8. MPCTL Field Descriptions
Field
Description
31
BRMO
BRM Order bit. Determines if the BRM order is first order or second order. The first order BRM is used if
a MF fractional part is both more than 1/10 and less than 9/10. In other cases, the second order BRM is
used. The BRMO bit is cleared by a hardware reset.
0 BRM order is first order.
1 BRM order is second order.
30
Reserved
29–26
PD
Pre-divider Factor bits define the pre-divider factor (PD) applied to the PLL input frequency. See
Equation 3-1. PD is an integer between 1and 16 (inclusive). PD is chosen to ensure that the resulting
output frequency remains within the specified range. When a new value is written into PD bits, the PLL
loses its lock; after a freq. lock time delay (see DPLL specification), the PLL re-locks.
0000 = 1
0001 = 2
——
1111 = 16
25–16
MFD
Multiplication Factor (Denominator Part). Defines the denominator part of the BRM value for the MF. See
Equation 3-1. When a new value is written into the MFD bits, the PLL loses its lock; after a freq. lock time
delay, the PLL re-locks.
0000000000 = 1
0000000001 = 2
——
1111111111 = 1024
15–14
Reserved
13–10
MFI
Multiplication Factor (Integer part). Defines the integer part of the BRM value for the MF. See
Equation 3-1. The MFI is encoded so that MFI < 5 results in MFI = 5. When a new value is written into
the MFI bits, the PLL loses its lock: after a freq. lock time delay, the PLL re-locks.
0000–0101 = 5
0110 = 6
——
1111 = 15
9–0
MFN
Multiplication Factor (Numerator part). Defines the numerator of the BRM value for the MF. See
Equation 3-1. When a new value is written into the MFN bits, the PLL loses its lock; after a freq. lock time
delay, the PLL re-locks. This value is a 2’s complements number.
0000000000 = 0
0000000001 = 1
——
0111111111 = 511
1000000000 = -512
——
1111111111 = -1
Restriction: The absolute value of MFn/MFd must be smaller than 1.
3.4.3.5.1
Calculating MPLL’s Output Frequency
The MPLL’s output frequency (FVCO) oscillates at a value determined by Equation 3-1, where:
Fref =Reference clock (input frequency) of MPLL
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-18
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
MFx =Various multiplication factors, whose value is set using the MPCTL register (see bit descriptions
below)
PD =Pre-Divider factor, whose value is also set in the MPCTL register
MF N
MFI + -----------MF D
----------------------------- = Fvco
F ref × 2
PD
Eqn. 3-1
MPLL Output Frequency
3.4.3.6
USB PLL Control Register (UPCTL)
Figure 3-8 shows the register; Table 3-9 provides the register’s field descriptions.
0x53F8_ 0014 (UPCTL)
31
R BRM
W O
Reset
R
30
Access: User Read/Write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
PD
MFD
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
MFI
MFN
W
Reset
0
0
0
1
1
1
0
0
0
0
0
Figure 3-8. USB PLL Control Register—UPCTL
Table 3-9. UPCTL Field Descriptions
Field
Description
31
BRMO
BRM Order bit. Determines if the BRM order is first order or second order. The first order BRM is used if a MF
fractional part is both more than 1/10 and less than 9/10. In other cases, the second order BRM is used. The
BRMO bit is cleared by a hardware reset.
0 BRM order is first order.
1 BRM order is second order.
30
Reserved
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-19
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-9. UPCTL Field Descriptions (continued)
Field
Description
29–26
PD
Pre-divider Factor bits define the pre-divider factor (PD) applied to the PLL input frequency. See Equation 3-1.
PD is an integer between 1and 16 (inclusive). PD is chosen to ensure that the resulting output frequency remains
within the specified range. When a new value is written into PD bits, the PLL loses its lock; after a freq. lock time
delay (see DPLL specification), the PLL re-locks.
0000 = 1
0001 = 2
——
1111 = 16
25–16
MFD
Multiplication Factor (Denominator Part). Defines the denominator part of the BRM value for the MF. See
Equation 3-1. When a new value is written into the MFD bits, the PLL loses its lock; after a freq. lock time delay,
the PLL re-locks.
000000000 = 1
000000001 = 2
——
1111111111 = 1024
15–14
Reserved
13–10
MFI
Multiplication Factor (Integer part). Defines the integer part of the BRM value for the MF. See Equation 3-1. The
MFI is encoded so that MFI < 5 results in MFI = 5. When a new value is written into the MFI bits, the PLL loses
its lock: after a freq. lock time delay, the PLL re-locks.
0000–0101 = 5
0110 = 6
——
1111 = 15
9–0
MFN
Multiplication Factor (Numerator part). Defines the numerator of the BRM value for the MF. See Equation 3-2.
When a new value is written into the MFN bits, the PLL loses its lock; after a freq. lock time delay, the PLL re-locks.
This value is a 2’s complements number.
0000000000 = 0
0000000001 = 1
——
0111111111 = 511
1000000000 = –512
——
1111111111 = –1
Restriction: The absolute value of MFn/MFd must be smaller than 1.
3.4.3.6.1
Calculating USB PLL Output Frequency
The UPLL’s output frequency (FVCO) oscillates at a value determined by Equation 3-2, where:
Fref =Reference clock (input frequency) of UPLL
MFx =Various multiplication factors, whose value is set using the UPCTL register (see bit descriptions)
PD =Pre-Divider factor, whose value is also set in the UPCTL register
Eqn. 3-2
UPLL Output Frequency
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-20
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
MF N
MFI + -----------MF D
F ref × 2 ------------------------------ = Fvco
PD
3.4.3.7
SR PLL Control Register (SPCTL)
Figure 3-9 shows the register; Table 3-10 provides the register’s field descriptions.
0x53F8_ 0018 (SPCTL)
31
R
30
Access: User Read/Write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
BRMO
PD
MFD
W
Reset
R
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
MFI
MFN
W
Reset
0
0
1
1
0
0
0
0
0
0
0
Figure 3-9. SR PLL Control Register (SPCTL)
Table 3-10. SPCTL Field Descriptions
Field
Description
31
BRMO
BRM Order bit. Determines if the BRM order is first order or second order. The first order BRM is used if a MF
fractional part is both more than 1/10 and less than 9/10. In other cases, the second order BRM is used. The
BRMO bit is cleared by a hardware reset.
0 BRM order is first order.
1 BRM order is second order.
30
29–26
PD
Reserved
Pre-divider Factor bits define the pre-divider factor (PD) applied to the PLL input frequency. See Equation 3-1.
PD is an integer between 1and 16 (inclusive). PD is chosen to ensure that the resulting output frequency remains
within the specified range. When a new value is written into PD bits, the PLL loses its lock; after a freq. lock time
delay (see DPLL specification), the PLL re-locks.
0000 = 1
0001 = 2
——
1111 = 16
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-21
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-10. SPCTL Field Descriptions (continued)
Field
Description
25–16
MFD
Multiplication Factor (Denominator Part). Defines the denominator part of the BRM value for the MF. See
Equation 3-1. When a new value is written into the MFD bits, the PLL loses its lock; after a freq. lock time delay,
the PLL re-locks.
0000000000 = 1
0000000001 = 2
——
1111111111 = 1024
15–14
Reserved
13–10
MFI
Multiplication Factor (Integer part). Defines the integer part of the BRM value for the MF. See Equation 3-1. The
MFI is encoded so that MFI < 5 results in MFI = 5. When a new value is written into the MFI bits, the PLL loses
its lock: after a freq. lock time delay, the PLL re-locks.
0000–0101 = 5
0110 = 6
——
1111 = 15
9–0
MFN
Multiplication Factor (Numerator part). Defines the numerator of the BRM value for the MF. See Equation 3-1.
When a new value is written into the MFN bits, the PLL loses its lock; after a freq. lock time delay, the PLL re-locks.
This value is a 2’s complements number.
0000000000 = 0
0000000001 = 1
——
0111111111 = 511
1000000000 = -512
——
1111111111 = -1
Restriction: The absolute value of MFn/MFd must be smaller than 1.
3.4.3.7.1
Calculating SRPLL Output Frequency
The SRPLL’s output frequency (FVCO) Oscillates at a value determined by Equation 3-3,
Where:
Fref = Reference clock (input frequency) of SRPLL
MFx = Various multiplication factors, whose value is set using the SPCTL register (see bit descriptions
below)
PD = Pre-Divider factor, whose value is also set in the SPCTL register
MF N
MFI + -----------MF D
F ref × 2 ------------------------------ = Fvco
PDF
Eqn. 3-3
SRPLL Output Frequency
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-22
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
3.4.3.8
Clock Out Source Register (COSR)
Figure 3-10 shows the register; Table 3-11 provides the register’s field descriptions.
0x53F8_ 001C (COSR)
R
Access: User read-write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
CLK
OEN
0
0
W
Reset
R
W
Reset
0
0
0
0
0
0
1
CLKOUTDIV
0
1
CLKOSEL
0
0
0
0
0
0
0
Figure 3-10. Clock Out Source Register (COSR)
Table 3-11. COSR Field Descriptions
Field
31–10
9
CLKOEN
8–6
CLKOUTDIV
Description
Reserved
Clock output enable bit
1 clock output IO pin is enabled
0 clock output IO pin disabled
Clock output divide factor
000 20
001 21
010 22
011 23
100 24
101 Reserved
110 Reserved
111 Reserved
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-23
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-11. COSR Field Descriptions (continued)
Field
Description
5–4
Reserved
3–0
CLKOSEL
3.4.3.9
These bits select which clock is to be reflected on the clock output CKO:
0000 mpl_dpdgck_clk
0001 ipg_clk_ccm
0010 upl_dpdgck_clk
0011 pll_ref_clk
0100 fpm_ckil512_clk
0101 ipg_clk_ahb_arm
0110 ipg_clk_arm
0111 spl_dpdgck_clk
1000 ckih
1001 ipg_clk_ahb _emi_clk
1010 ipg_clk_ipu_hsp
1011 ipg_clk_nfc_20m
1100 ipg_clk_perclk_uart1
1101 ref_cir1 (ref_cir_gateload)
1110 ref_cir2 (ref_cir_intrcload)
1111 ref_cir3 (ref_cir_path)
Clock Gating Registers (CGR0–CGR2)
Figure 3-11 shows the register; Table 3-12 provides the register’s field descriptions.
Access: User Read/Write
0x53F8_ 0020 (CGR0)
0x53F8_ 0024 (CGR1)
0x53F8_ 0028 (CGR2)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CG15
CG14
CG13
CG12
CG11
CG10
CG9
CG8
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CG7
CG6
CG5
CG4
CG3
CG2
CG1
CG0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 3-11. Clock Gating Registers (CGR0–CGR2)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-24
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-12. GR0–CGR2 Field Descriptions
Field
Description
31–30
CG15
The clock gating registers define the clock gating for power reduction of each clock
(CG(i) bits). There are n CGR registers. The number of registers required is according to the number of
peripherals (n) in the system.
CG(i) bits
These bits are used to turn on/off the clock to each module independently. The following list details the
possible clock activity conditions for each module.
00 clock is off during all modes.
01 clock is on in run mode, but off in wait and doze modes
10 clock is on in run and wait modes, but off in doze mode
11 clock is on during all modes, except when PLL clock is off.
Note: Before writing 00 to these bits (thus shutting off the clock to the module), the module to which it is
connected must first be stopped. If this is not done, the module’s behavior can be adversely
affected.
RTIC, SDMA, IPU, and EMI clock gating is not possible during run mode.
——
——
(2i+1)–2i
CG(i)
Table 3-13, Table 3-14, and Table 3-15 provide information on the mapping of i.MX31 modules and the
CGR registers bits.
Table 3-13. CGR0 Register Mapping
Module Name
CG(i) Bits Index
sd_mmc1
0
sd_mmc2
1
GPT
2
EPIT1
3
EPIT2
4
IIM
5
ATA
6
SDMA
7
CSPI3
8
RNG
9
UART1
10
UART2
11
SSI1
12
I2C1
13
I2C2
14
I2C3
15
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-25
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-14. CGR1 Register Mapping
Module Name
CG(i) Bits Index
HANTRO
0
MEMSTICK1
1
MEMSTICK2
2
CSI
3
RTC
4
WDOG
5
PWM
6
SIM
7
ECT
8
USBOTG
9
KPP
10
IPU
11
UART3
12
UART4
13
UART5
14
1-WIRE
15
Table 3-15. CGR2 Register Mapping
Module or Clock
Name
CG Bits Index
SSI2
0
CSPI1
1
CSPI2
2
GACC
3
EMI
4
RTIC
5
FIR
6
Reserved
7
Reserved
8
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-26
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-15. CGR2 Register Mapping (continued)
3.4.3.10
Module or Clock
Name
CG Bits Index
Reserved
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Wake-Up Interrupt Mask Register (WIMR0)
Figure 3-12 shows the register; Table 3-16 provides the register’s field descriptions.
0x53F8_ 002C (WIMR0)
31
30
Access: User Read/Write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R WIM3 WIM3 WIM2 WIM2 WIM2 WIM2 WIM2 WIM2 WIM2 WIM2 WIM2 WIM2 WIM1 WIM1 WIM1 WIM1
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R WIM1 WIM1 WIM1 WIM1 WIM1 WIM1
WIM9 WIM8 WIM7 WIM6 WIM5 WIM4 WIM3 WIM2 WIM1 WIM0
5
4
3
2
1
0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 3-12. Wake-up Interrupt Mask Register 0 (WIMR0)
Table 3-16. WIMR0 Field Descriptions
Field
Description
31–0
WIMn
WIM[31:0]. These bits are interrupt mask bits. They are applicable for all interrupts that can be connected to the
CCM interrupt controller, and can be used, for instance, for wake-up interrupt generation in MCU power gating
mode.
0 Interrupt is enabled.
1 Interrupt is masked.
3.4.3.11
Latch Divergence Counter Register (LDC)
Figure 3-13 shows the register; Table 3-17 provides the register’s field descriptions.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-27
Clocks, Power Management and Reset (AP Clock Controller Module)
0x53F8_ 0030 (LDC)
31
Access: User Read/Write
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R LDC3 LDC3 LDC2 LDC2 LDC2 LDC2 LDC2 LDC2 LDC2 LDC2 LDC2 LDC2 LDC1 LDC1 LDC1 LDC1
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R LDC1 LDC1 LDC1 LDC1 LDC1 LDC1
LDC9 LDC8 LDC7 LDC6 LDC5 LDC4 LDC3 LDC2 LDC1 LDC0
5
4
3
2
1
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Figure 3-13. Latch Divergence Counter Register (LDC)
Table 3-17. LDC Field Descriptions
Field
Description
31–0
LDCn
LDC[31:0]. These bits contain the latch divergence counter value. Returns to default value only after POR_B‘ef.
3.4.3.12
DPTC Comparator Value Registers (DCVR0–DCVR3)
Figure 3-14 shows the register; Table 3-18 provides the register’s field descriptions.
Access: User Read/Write
0x53F8_ 0034 (DCVR0)
0x53F8_ 0038 (DCVR1)
0x53F8_ 003C (DCVR2)
0x53F8_ 0040 (DCVR3)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ULV
LLV
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
LLV
ELV
W
Reset
0
0
0
0
0
0
0
0
0
Figure 3-14. DPTC Comparator Value Register 0:3 (DCVR0:3)
These registers contain relevant DPTC look-up table values.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-28
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-18. DPTC Field Descriptions
Field
Description
31–22
ULV
Upper Limit-value for the upper performance limit of the reference circuit clock counter.
21–12
LLV
Lower Limit-value for the lower performance limit of the reference circuit clock counter.
11–2
ELV
Emergency Limit -value for the lower performance limit of the reference circuit clock counter. This serves
as an “emergency” lower limit, which indicates a critical value.
1–0
Reserved
3.4.3.13
Load Tracking Register (LTR0)
Figure 3-15 shows the register; Table 3-19 provides the register’s field descriptions.
0x53F8_ 0044 (LTR0)
31
30
Access: User Read/Write
29
R SIGD1 SIGD1 SIGD1
5
4
3
W
Reset
28
27
26
25
24
23
22
21
20
19
17
16
0
UPTHR
DNTHR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R SIGD1 SIGD1 SIGD1 SIGD SIGD SIGD SIGD SIGD SIGD SIGD SIGD SIGD SIGD
2
1
0
9
8
7
6
5
4
3
2
1
0
W
Reset
18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIV3CK
0
0
0
Figure 3-15. Load Tracking Register—LTR0
Table 3-19. LTR0 Field Descriptions
Field
31–29
Description
SIGD15–13. These bits define whether the dvfs_w_sig[15:0] signals are detected using level or edge
detection.
0 Level detection
1 Edge detection
27–22
UPTHR
Upper threshold for load tracking
21–16
Lower threshold for load tracking
15–3
SIGDn
SIGD12–0. These bits define whether the dvfs_w_sig[15:0] signals are detected using level or edge
detection.
0 Level detection
1 Edge detection
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-29
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-19. LTR0 Field Descriptions (continued)
Field
Description
2–1
DIV3CK
0
Defines the division value of div_3_clk
Reserved
3.4.3.14
Load Tracking Register (LTR1)
Figure 3-16 shows the register; Table 3-20 provides the register’s field descriptions.
0x53F8_ 0048 (LTR1)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
W
Reset
23
22
21
20
LTBR LTBR
SH
SR
19
18
17
16
DNCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
DNCNT
UPCNT
PNCTHR
W
Reset
0
1
0
0
0
0
0
0
0
1
0
0
0
0
Figure 3-16. Load Tracking Register (LTR1)
Table 3-20. LTR1 Field Descriptions
Field
31–22
Description
Reserved
23
LTBRSH
Load tracking buffer shift
0 takes the original MSB of ld_add–ld_add[5:2]
1 takes a shift of ld_add–ld_add[4:1]
22
LTBRSR
Load tracking buffer source
0 pre_ld_add
1 ld_add
21–14
DNCNT
These bits define the number of consecutive times the lower frequency threshold is undershot (that is, the
effective frequency is lower than this threshold) to generate a dvfs_fdw signal. This signal causes a decrease of
the system frequency.
00000001=2
00000010=3
——
Note:
The value 00000000 is not enabled.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-30
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-20. LTR1 Field Descriptions (continued)
Field
Description
13–6
UPCNT
These bits define the number of consecutive times the upper frequency threshold must be exceeded (threshold
overcomes) to generate a dvfs_fup signal. This signal causes an increase of the system frequency.
00000001=2
00000010=3
——
Note:
5–0
PNCTHR
The value 00000000 is not enabled.
These bits define panic mode level threshold for load tracking
3.4.3.15
Load Tracking Register (LTR2)
Figure 3-17 shows the register; Table 3-21 provides the register’s field descriptions.
0x53F8_ 004C (LTR2)
31
30
Access: User Read/Write
29
28
27
26
25
24
23
22
21
20
19
18
17
R
WSW15
WSW14
WSW13
WSW12
WSW
10
WSW11
W
Reset
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
WSW10
WSW9
EMAC
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-17. Load Tracking Register (LTR2)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-31
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-21. LTR Field Descriptions
Field
31–29
WSW15
Description
These bits define the general purpose load tracking signals dvfs_w_sig[15:9]. For
more details about how these values are defined, see Table 3-29.
28–26
WSW14
25–23
WSW13
22–20
WSW12
19–17
WSW11
16–14
WSW10
13–11
WSW9
10–9
8–0
EMAC
3.4.3.16
Reserved
These bits define the EMA configuration.
Load Tracking Register (LTR3)
Figure 3-18 shows the register; Table 3-22 provides the register’s field descriptions.
0x53F8_ 0050 (LTR3)
31
30
Access: User Read/Write
29
28
27
26
25
24
23
22
21
20
19
18
17
R
WSW8
WSW7
WSW6
WSW5
WSW
3
WSW4
W
Reset
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
R
WSW3
WSW2
WSW1
WSW0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
Figure 3-18. Load Tracking Register—LTR3
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
3-32
Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-22. LTR3 Field Descriptions
Field
Description
31–29
WSW8
These bit fields (each one in turn) define the weight of each of the general purpose load tracking signals
(dvfs_w_sig[8:0]). The total CPU load as a result of the dvfs_w_sig signal is defined as a sum of each of the
individual signal’s dvfs_w_sig[n] value multiplied by its weight, as defined by the corresponding WSWn bit field.
28–26
WSW7
25–23
WSW6
22–20
WSW5
19–17
WSW4
16–14
WSW3
13–11
WSW2
10–8
WSW1
7–5
WSW0
3.4.3.17
Load Tracking Buffer Register (LTBR0)
Figure 3-19 shows the register; Table 3-23 provides the register’s field descriptions.
0x53F8_ 0054 (LTBR0)
31
30
R
Access: User Read
29
28
27
26
LTS7
25
24
23
22
LTS6
21
20
19
18
LTS5
17
16
LTS4
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
LTS3
LTS2
LTS1
LTS0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-19. Load Tracking Register—LTBR0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-23. LTBR0 Field Descriptions
Field
Description
31–28
LTS7
These bits contain data of the last eight samples of load tracking.
27–24
LTS6
23–20
LTS5
19–16
LTS4
15–12
LTS3
11–8
LTS2
7–4
LTS1
3–0
LTS0
3.4.3.18
Load Tracking Buffer Register (LTBR1)
Figure 3-20 shows the register; Table 3-24 provides the register’s field descriptions.
0x53F8_ 0058 (LTBR1)
31
R
30
Access: User Read
29
28
27
LTS15
26
25
24
23
LTS14
22
21
20
19
LTS13
18
17
16
LTS12
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
LTS11
LTS10
LTS9
LTS8
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-20. Load Tracking Register (LTBR1)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-24. LTBR1 Field Descriptions
Field
Description
31–28
LTS15
These bits contain data of the first eight samples of load tracking.
27–24
LTS14
23–20
LTS13
19–16
LTS12
15–12
LTS11
11–8
LTS10
7–4
LTS9
3–0
LTS8
3.4.3.19
Power Management Control Register 0 (PMCR0)
Figure 3-21 shows the register; Table 3-25 provides the register’s field descriptions.
0x53F8_ 005C (PMCR0)
31
30
Access: User Read/Write
29
28
27
26
25
24
23
22
21
20
19
18
17
R
UDS
C
DVFE DVFI
LBMI LBFL
V
S
VSCNT
PTVI
S
LBCF
16
UPDT
EN
DFSUP
DVSUP
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DRC
E2
DRC
E1
DRC
E0
0
0
0
W
Reset
R FSVA
W IM
Reset
1
FSVAI
0
0
DPVC
DRC
DPVV WFIM
R
E3
1
1
0
0
DCR DVFE PTVA
N
IM
1
0
1
PTVAI
0
0
DPTE
N
0
Figure 3-21. Power Management Control Register 0 (PMCR0)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-25. PMCR0 Field Descriptions
Field
Description
31
DFSUP[1]
DFS update. These bits define which aspect of the MCU frequency will be updated, as follows:
0 SRPLL update
1 MCUPLL update
30
DFSUP[0]
DFS update. These bits define which aspect of the MCU frequency will be updated, as follows:
0 pll and post-dividers update
1 post-dividers update only
29–28
DVSUP
DVS update. These bits, connected to external I/O pins, define in what manner the DVS0 and DVS1 voltages are
updated, if at all.
Note: These bits merely set a value, and it is incumbent upon software external to the i.MX31 and i.MX31L to
use this information and act upon it.
00 DVS1=0 DVS0=0—highest frequency/voltage level
01 DVS1=0 DVS0=1
10 DVS1=1 DVS0=0
11 DVS1=1 DVS0=1—lowest frequency/voltage level
27
UDSC
Up-down scaling. This bit indicates the direction of frequency scaling.
0 Frequency is decreased.
1 Frequency is increased.
26–24
VSCNT
Voltage scaling counter. These bits define the number of CKIL cycles required to carry out voltage scaling. This
counter is initialized when the UDSC bit is set to “1”. After the counter arrives at the value indicated in the VSCNT
bits, the frequency is then scaled.
(No. of CKIL cycles)
000 No delay
001 1-0 CKIL cycle delay
010 2-1 CKIL cycle delay (1 CKIL cycle guaranteed).
011 3-2 CKIL cycle delay (1 CKIL cycle guaranteed).
...
111 7-6 CKIL cycle delay
Note: The value 0x2 should be used to ensure a minimal delay of one CKIL cycle. (Higher values can be used
where needed, depending on system requirement).
23
DVFEV
Always give a DVFS event.
0 Do not give an event always.
1 Always give event.
22
DVFIS
DVFS Interrupt select. These bits define destination of DVFS interrupts.
0 SDMA interrupt will be generated for DVFS events.
1 MCU interrupt will be generated for DVFS events.
21
LBMI
Load buffer full mask interrupt. This bit masks the generation of this interrupt.
0 Load buffer full interrupt is enabled.
1 Load buffer full interrupt is masked.
20
LBFL
Load buffer full status bit. This bit indicates that log buffer registers are full. An interrupt will be generated if LBMI
bit is set to “0”.
0 Load buffer is not full.
1 Load buffer is full.
Note:
SW can write only “0” into this bit.
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Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-25. PMCR0 Field Descriptions (continued)
Field
Description
19–18
LBCF
DVFS load buffer programmable size
00 Load buffer size is 4.
01 Load buffer size is 8.
10 Load buffer size is 12.
11 Load buffer size is 16.
17
PTVIS
DPTC Interrupt select. These bits define destination of DPTC interrupts.
0 SDMA interrupts will be generated for DPTC events.
1 MCU interrupts will be generated for DPTC events
16
UPDTEN
DVFS update enable of new value
0 SW is not enabled to write new setting of frequency change (Not able to update DFSUP, DVSUP, UDSC,
VSCNT) because PLL is not locked yet.
1 SW is enabled to write new setting of frequency change.
15
FSVAIM
DVFS Frequency adjustment interrupt mask. This bit masks the DVFS frequency adjustment interrupt. FSVAI
status bits will be still asserted in relevant cases.
0 Interrupt is enabled.
1 Interrupt is masked.
14–13
FSVAI[1:0]
12
DPVCR
11
DPVV
DVFS Frequency adjustment interrupt. These status bits indicate that the system frequency should be changed.
00 no interrupt
01 frequency should be increased. Low priority interrupt. Interrupt is asserted, if FSVAIM=0. Interrupt is masked
if DVSUP = 00 (highest frequency).
10 frequency should be decreased. Interrupt is asserted, if FSVAIM=0. Interrupt is masked if DVSUP = 11 (lowest
frequency).
11 frequency should be increased immediately. High priority interrupt. Interrupt is asserted, if FSVAIM=0.
Interrupt is masked if DVSUP = 00 (highest frequency).
DPTC voltage change request
0 Disabled
1 Enabled
DPTC voltage valid edge detect. Can be updated by SW.
0 Voltage is not valid
1 Received a voltage valid acknowledge
Note:
10
WFIM
If written by SW, it is possible to assert it only after DPVCR is asserted.
DVFS Wait for Interrupt mask bit
0 Wait for interrupt is not masked.
1 Wait for interrupt is masked.
9
DRCE3
DPTC reference circuit3 enable bit. This bit defines if reference circuit3 is enabled during DPTC operation.
0 DPTC reference circuit3 is disabled.
1 DPTC reference circuit3 is enabled.
8
DRCE2
DPTC reference circuit2 enable bit. This bit defines if reference circuit2 is enabled during DPTC operation.
0 DPTC reference circuit2 is disabled.
1 DPTC reference circuit2 is enabled.
7
DRCE1
DPTC reference circuit1 enable bit. This bit defines if reference circuit1 is enabled during DPTC operation.
0 DPTC reference circuit1 is disabled.
1 DPTC reference circuit1 is enabled.
6
DRCE0
DPTC reference circuit0 enable bits. This bit defines if reference circuit0 is enabled during DPTC operation.
0 DPTC reference circuit0 is disabled.
1 DPTC reference circuit0 is enabled.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-25. PMCR0 Field Descriptions (continued)
Field
Description
5
DCR
DPTC counting range. This bit sets how many times the system clock may increment and the reference circuits
remain active (and their output signals will be counted). Value of “1” causes 512 system clock count. Value of “0”
causes 256 system clock count.
0 256 system clock count
1 512 system clock count
4
DVFEN
DVFS enable. This bit enables the DVFS block.
1 DVFS is enabled.
0 DVFS is disabled.
Note: Between disable and enable there has to be at least 3 cycles of div_3_clk.
3
PTVAIM
DPTC Voltage adjustment interrupt mask. This bit masks the DPTC voltage adjustment interrupt. PTVAI status
bits will be still asserted in relevant case.
0 Interrupt is enabled.
1 Interrupt is masked.
2–1
PTVAI[1:0]
0
DPTEN
DPTC Voltage adjustment interrupt. These status bits indicate that the supply voltage should be changed.
00 no interrupt
01 voltage should be decreased. Interrupt is asserted, if PTVAIM=0
10 voltage should be increased. Low priority interrupt. Interrupt is asserted, if PTVAIM=0
11 voltage should be increased immediately. High priority interrupt. Interrupt is asserted, if PTVAIM=0
DPTC enable. This bit enables the DPTC block and starts the reference circuit clock counting and compares this
to look-up table values.
0 DPTC is disabled.
1 DPTC is enabled.
3.4.3.20
Power Management Control Register 1 (PMCR1)
Figure 3-22 shows the register; Table 3-26 provides the register’s field descriptions.
0x53F8_ 0060 (PMCR1)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
WBCN
W
Reset
R
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PWT NWT
CPFA
S
S
CPSPA
W
Reset
0
0
0
0
0
0
0
0
0
0
DVGP
0
0
0
0
Figure 3-22. Power Management Control Register 1 (PMCR1)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-26. PMCR1 Field Descriptions
Field
Description
31–24
Reserved
23–16
WBCN
8 bit programmable well-bias counter configuration bits
15–13
Reserved
12–9
CPSPA
WBCP adjustment. These signals enable adjustment of well-bias function parameters.
The value of CPSPA will be inverted to match the WBCP expectation as stated in the WBCP specification.
8
PWTS
WBCP pwell pump test. This signal enables the pwell charge pump in test mode.
0 pwell charge pump is disabled.
1 pwell charge pump is enabled.
7
NWTS
WBCP nwell pump test. This signal enables the nwell charge pump in test mode.
0 nwell charge pump is disabled.
1 nwell charge pump is enabled.
6
CPFA
WBCP Frequency Adjustment. This bit changes the frequency of the internal ring oscillator in the well-bias
charge pump block.
0 Normal frequency set
1 Lower frequency set
5–4
3–0
DVGP
Reserved
DVFS general purpose registers.
3.4.3.21
Post Divider Register 2 (PDR2)
Figure 3-23 shows the register; Table 3-27 provides the register’s field descriptions.
0x53F8_ 0064 (PDR2)
R
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
W
Reset
R
MST2_PDF
MST1_PDF
W
Reset
0
0
0
0
0
0
1
0
1
0
0
0
0
1
Figure 3-23. Post Divider Register 2 (PDR2)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
3-39
Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-27. PDR2 Field Descriptions
Field
31–13
Description
Reserved
12–7
These bits control the M-stick2 post divider. See Figure 3-24.
MST2_PDF 000001 Divide by 2
——
111111 Divide by 64
6
Reserved
5–0
These bits control the M-stick1 post divider. See Figure 3-24.
MST1_PDF 000001 Divide by 2
——
111111 Divide by 64
3.4.4
Functional Description
The general clock generation scheme is shown in Figure 3-24 which is shown without scan mux and clock
gating. The sections that immediately in this chapter describe in more detail how the individual clocks are
generated.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Freescale Semiconductor
Clocks, Power Management and Reset (AP Clock Controller Module)
Clock Controller Module
ckil_sync
CKIL
sync unit
CKIL
mcu_clk
mcu div.
hsp_clk
hsp divider
pll_ref_clk
CKIH
hclk_clk
hclk divider
ipg_clk
ipg divider
nfc_clk
Pre
Multiplier
nfc divider
MCU PLL
mpl-dpdgck-clk
Serial PLL
gacc_mbx_clk
1/2
MCU
Clock mcu_main_clk
Switch
Unit
ssi1_clk
ssi1 prediv.
ssi1_clk_sel
ssi1 div
ssi2 prediv.
ssi2_clk_sel
ssi2 div
spl_dpdgck_clk
Serial
Clock
Switch
Unit
ipt_clk_sr_bypass
ssi2_clk
firi_clk
firi prediv.
firi div
sim_baud_clk
firi_clk_sel
USB
PLL
ipg_clk
upl-dpdgck-clk
USB
Clock
Switch
Unit
perclk_out_clk
sync
per div
per_clk_sel
ipg_clk_ahb
csi_clk
ipt_clk_usb_bypass
csi div. - pre div.
csi_clk_sel.
csi div - post div
usb_clk
usb pre div
usb post div.
mstick1_clk
mstick1 div
mstick2_clk
mstick2 div
Figure 3-24. i.MX31 Clock Generation Scheme
3.4.4.1
3.4.4.1.1
Clock Sources
External Low Frequency Clock—CKIL
The i.MX31 and i.MX31L processors can use either a 32 kHz, 32.768 kHz or a 38.4 kHz crystal as the
external low frequency source. Throughout this chapter, the low frequency crystal is referred to as the
32 kHz crystal, even though this can refer to the 32.768 or 38.4 kHz values.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
The signal from the external 32 kHz crystal is the source of the CKIL signal that is sent to the real time
clock (RTC). The output of the 32 kHz crystal is also input to the pre-multiplier PLL to produce the PLL
reference clock by multiplying CKIL by a factor of 1024.
3.4.4.2
MCU Clock Domain Clocks
The CCM provides a large number of clock outputs used to supply clocks to the MCU and the peripherals.
Each of the i.MX31 processors are partitioned into two asynchronous clock domains: MCU and USB, as
there are different functionality and frequency requirements from the clocks (detailed in this section).
3.4.4.2.1
MCU Clock Domain Clock Source Switch Unit
The main clock of the MCU clock domain is mcu_main_clk and is generated by MCU clock switch unit.
The following signals are possible clock sources for the MCU clock switch unit: pll_ref_clk,
mpl_dpdgck_clk (MCU PLL output), and spl_dpdgck_clk (SRPLL output). Whether the functional mode
clock uses ref_pll_clk or the mpl_dpdgck_clk signal is determined in S/W via enabling/disabling the MCU
PLL by writing MPE bit in the CCMR register, and by choosing the MCU clock domain source by writing
the MDS bit in the CCMR register. The selection between a reference clock from the MCU PLL or the
SRPLL can only be done when the DVFS is enabled. The ref_pll_clk signal will be selected automatically
when the MCU enters the test mode to bypass the PLL.
DVSF
State Machine
pll_ref_clk
0
1
mds
mpe
mpl_dpdgck_clk
mcu_pll_byp
mcu_main_clk
0
spl_gpdgck_clk
ipt_pll_bypass
and ipt_pll_bypass_en
1
Figure 3-25. MCU Clock Switch Unit
3.4.4.2.2
MCU Clock Domain Clocks
The MCU clock domain is partitioned into four synchronous clocks and two sub-domains. These are
described below. The main clock of this domain is called mcu_main_clk, and it is the output of the MCU
clock switch unit.
• mcu_clk (ipg_clk_arm) is the clock of the ARM platform. The target frequency of this clock is 532
MHz. This clock is generated from MCU BRM with a division factor as defined by the BRMM
bits in PDR0.
• max_clk sub-domain (ipg_clk_ahb) is the clock domain of the internal ARM platform peripherals
like the cross bar switch and chip modules. Clocks in this domain are generated from the max
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Clocks, Power Management and Reset (AP Clock Controller Module)
•
•
•
•
•
post-divider with a division factor as defined by the MAX_PDF bits in PDR0 register. These clocks
should be an integer multiple (value of between 1 and 8) of the mcu_main_clk. Maximum target
frequency of these clocks is 133 MHz.
hsp_clk is the clock for the IPU. This clock is generated from the hsp post-divider with a division
factor as defined by the HSP_PDF bits in PDR0 register. These clocks should be an integer
multiple (value of between 1 and 8) of the mcu_main_clk. Maximum target frequency of this clock
is 133 MHz for 1.2 V supply.
ipg_clk sub-domain is the clock domain of certain parts of the IP peripherals. These clocks are
generated from the ipg post-divider with a division factor defined by the IPG_PDF bits in the PDR0
register. These clocks should be an integer multiple (either 1 or 2) of the max_clk. Maximum target
frequency of these clocks is 62.5 MHz.
nfc_clk (ipg_clk_nfc_20m) is the clock for NAND Flash Controller. This clock is generated from
the nfc post-divider with a division factor as defined by the NFC_PDF bits in the PDR0 register.
ckil_mcu_sync_ipg is the clock for the peripheral modules. They require a 32-kHz clock
ipg_clk_gacc_mbx_clk is the clock for the MBX module. It is 1/2 of the ipg_ahb_clk, which is
66 MHz.
NOTE
The MBX R-S graphics accelerator is not available in the i.MX31L.
The phases between mcu_clk, hsp_clk, ckil_mcu_sync_ipg, ipg_clk_gacc_mbx_clk and clocks from
max_clk and per_clk subdomains are synchronized with the MCU domain master clock frequency
(mcu_main_clk), but the frequencies can be different.
Each MCU clock sub-domain has a dedicated post-divider that can be programmed to generate the divided
clock from the mcu_main_clk. The division factor is always an integer. Each clock port from the MCU
domain is connected to a specific sub-domain.
All clocks in the MCU clock domain are balanced. Posedge (the edge at which point the voltage increases)
of max_clk sub-domain clocks is always aligned with mcu_clk posedge. Posedge of ipg_clk sub-domain
clocks is always aligned with posedge of max_clk sub-domain clocks.
3.4.4.2.3
Clock Generation—ipg_ckil_sync Clock
This clock is generated by synchronization of CKIL clock to ipg_clk, when the system is not in Deep Sleep
mode or reset. When the system is in Deep Sleep mode and by default in reset, the synchronizer is
bypassed.
ckil
1
ipg_ckil_sync
0
ungated_ipg_clk
Deep Sleep mode
mux_ctl
All resets
Figure 3-26. ckil_mcu_sync_ipg Clock Generation
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
3.4.4.3
3.4.4.3.1
USB Clock Domain
USB Clock Domain Switch Unit
The main clock of the USB clock domain is usb_main_clk. This signal is generated by the USB clock
switch unit. The following signals are possible clock sources of the USB switch unit: USB DPLL output
(upl_dpdgck_clk) and bypass clock (ipp_clk_usb_bypass - bypass clock).
Selection between functional mode clock upl_dpdgck_clk and test mode clock: ipt_clk_usb_bypass is
done automatically, when the systems enters test mode.
ipp_clk_usb_bypass
1
0
upl_dpdgck_clk
ipt_upll_bypass
and ipt_pll_bypass_en
Figure 3-27. USB Clock Switch Unit
3.4.4.3.2
USB Clock Domain Clocks
The USB clock domain is partitioned into several asynchronous clocks.
• ipg_clk_usb_baud is the clock for the USBOTG module. This clock is generated from the usb
post-divider with division factor, defined by the USB_PDF bits in the MPDR1 register.
• ipg_clk_firi_baud is the clock of the FIR module.
• ipg_clk_ssi1_baud is the clock for the SSI1 module.
• ipg_clk_ssi2_baud is the clocks for the SSI2 module.
• ipg_sim_baud is the clock for the SIM module.
• ipg_per_baud is the clock for the peripherals that will not be affected by the DVFS changes.
• ipg_clk_csi_baud is the clock for the IPU, used for the camera sensor chip. This clock is generated
from the CSI post-divider with a division factor as defined by the CSI_PDF bits in the PDR0
register.
• ipg_clk_mstick1_baud is the clock for memstick1 module.
• ipg_clk_mstick2_baud is the clock for the memstick2 module.
USB domain clocks are not synchronized or balanced with each other.
3.4.4.3.3
Clock Generation—ipg_clk_firi_baud
The ipg_clk_firi_baud clock is generated as follows: First a source between MCU, USB or Serial PLL’s
outputs is chosen, according to the value of the FIRS bits in the CCMR register. Then, this source is passed
through two post dividers, connected in series. The division factors of the post dividers are defined by
defined by the FIRI_PRE_PDF and FIRI_PDF bits in the MPDR1 register.
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Clocks, Power Management and Reset (AP Clock Controller Module)
3.4.4.3.4
Clock Generation—ipg_clk_ssi1_baud
The ipg_clk_ssi1_baud clock is generated as follows: First a source between MCU, USB or Serial PLL’s
outputs is chosen, according to the value of the SSI1S bits in the CCMR register. Then, this source is
passed through two post dividers, connected in series. The division factors of the post dividers are defined
by defined by the SSI1_PRE_PDF and SSI1_PDF bits in the MPDR1 register.
3.4.4.3.5
Clock Generation—ipg_clk_ssi2_baud
The ipg_clk_ssi2_baud clock is generated as follows: First a source between MCU, USB or Serial PLL’s
outputs is chosen, according to the value of the SSI2S bits in the CCMR register. Then, this source is
passed through two post dividers, connected in series. The division factors of the post dividers are defined
by defined by the SSI2_PRE_PDF and SSI2_PDF bits in the MPDR1 register.
3.4.4.3.6
Clock Generation—ipg_sim_baud
The ipg_sim_baud clock is generated as follows: The a source between USB PLL’s output and ipg_clk is
chosen according to the value of PERCS bit in the CCMR register. This source is passed though the
peripheral divider that is defined in the PER_PODF bits in the PDR0 register.
3.4.4.3.7
Clock Generation—ipg_per_baud
The ipg_per_baud clock is generated as follows: A source between the synchronized USB PLL’s output
and ipg_clk is chosen according to the value of PERCS bit in CCMR register. The USB PLL’s output is
synchronized with ipg_clk_ahb after being divided by the peripheral post-divider using the PER_PODF
bit in PDR0. There is a restriction on the value of the post divider bits, the created clock must be slower
than the synchronizing clock ipg_clk_ahb by at least a half.
3.4.4.3.8
Clock Generation—ipg_clk_csi_baud
The ipg_clk_csi_baud clock is generated as follows: First a source between the MCU and USB PLL’s
output is chosen according to CSCS bit in CCMR register. Then, this source is passed throughout the CSI
post-divider that is defined in CSI_PODF bits in the PDR0 register.
3.4.4.3.9
Clock Generation—ipg_clk_mstick1_baud
This clock is generated as follows: The USB PLL’s output is passed though the memstick1 post-divider
that is defined in the MST1_PDF bits in PDR2 register.
3.4.4.3.10
Clock Generation—ipg_clk_mstick2_baud
This clock is generated as follows: The USB PLL’s output is passed though the memstick1 post-divider
that is defined in the MST2_PDF bits in PDR2 register.
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Clocks, Power Management and Reset (AP Clock Controller Module)
3.4.4.4
3.4.4.4.1
SR Clock Domain
SR Clock Switch Unit
The man clock of the SR clock domain in the sr_main_clk and is generated by the SR clock switch unit.
The following signals are possible clock sources SRPLL output clock—spl_dpdgck_clk, bypass clock
ipp_clk_sr_clk.
ipp_clk_sr_bypass
spl_dpdgck_clk
1
0
ipt_spll_bypass
and ipt_pll_bypass_en
Figure 3-28. SR Clock Switch Unit
3.4.4.5
Clock Cleaner
The clock cleaner is connected to the ipp_ckih clock after the CAMP cell. Clock cleaner is actually a clock
gating cell, that gates off PLL clocks until the output of CAMP is stable. ckih_osc_rdy signal controls the
CKIH clock cleaner.
3.4.4.6
Low Power Clock Gating (LPCG)
The LPCG block distributes clocks to all modules from the subdomain clocks and gates off clocks in low
power mode. Clock gating for each module is carried out based on the specific low power mode and the
relevant bits in the MCGR register.
3.4.4.7
SDRAM Controller Handshake Mechanism
The SDRAM controller requires high frequency clock (more than 1 MHz) to work properly with the
external memories. If for some reason the clock controller will not provide such a clock to the SDRAM
controller (software disable of SDRAM controller clock or entering the STOP mode), then before
disabling the SDRAM controller clock, the handshake mechanism is activated, which causes the SDRAM
controller to place the external memories in power down mode. CCM will then assert the ccm_sd_lpmd
signal, which indicates that a request to place the SDRAM in self-refresh mode was made. After the EMI
places the SDRAM in self refresh mode, the emi_sd_lpack signal will be asserted and the CCM will gate
the clock to the EMI.
3.4.4.8
Power Fail
The power_fail IO port is connected to the CCM and generates a power fail interrupt for the MCU. The
interrupt can be generated only if the MCU is not in State Retention or Deep Sleep mode. The goal of the
interrupt routine is to enter Deep Sleep mode with minimum energy consumption.
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Clocks, Power Management and Reset (AP Clock Controller Module)
3.5
3.5.1
Power Management
Power Domains
The i.MX31 and i.MX31L are partitioned into four power domains:
• MCU domain—includes the ARM11 Core, the MMU, and the Caches
• L2 cache domain—includes L2 cache data array
• Peripheral domain—includes all the peripherals except the MCU–PLL, USB-PLL, SR-PLL, and
the FPM
• PLL domain—includes the MCU-PLL, USB-PLL, SR-PLL, and the FPM
3.5.2
Power Modes
The i.MX31 and i.MX31L processors support a versatile definition of power modes, including power and
clock domains status and applied power techniques. The power modes described in the following sections
were defined taking into account static and dynamic power consumption of blocks in different operational
modes, the power consumption of clock sources, and the time required to exit low power modes.
3.5.2.1
Run Mode
This is the normal/functional operating mode of ARM11. The ARM clock frequency can vary between
fmax and fmin, and the voltage between Vmax and Vmin.
3.5.2.2
Wait Mode
In this mode, the MCU clock is gated, but ARM11P MAX and all peripherals clocks are available. This
mode is entered by the MCU executing a STANDBY FOR INTERRUPT command. The arm_clk_off
output of ARM11P is asserted and the clock to the MCU arm_clk is gated by the CCM. The MCU exits
the wait mode and enters the run mode by receiving of any interrupt (depend on mask bits) and negation
of arm_clk_off signal. Clocks for specific modules can be gated off automatically in wait mode by
programming MCGR registers.
3.5.2.3
Doze Mode
MCU and MAX clocks are gated. Clock source is available and peripherals that do not require MAX and
MCU functionality can be active.
Doze mode is entered by programming the LPM bits in the MCR register. The next time the MCU executes
the STANDBY FOR INTERRUPT command, a signal for MAX clock halt request will be asserted by the
CCM and the clock to MAX will be gated off upon acknowledgement of the signal assertion. If WBEN bit
is set to “1”, the ccm_wben signal will be asserted.
The MCU exits Doze mode to Run mode by receiving any enabled interrupt and negation of the
arm_clk_off signal. If WBEN bit is set to “1”, PLL reference clock well-bias counter will be started and
upon completion of its counting, the ccm_wben signal will be negated and clocks will then be provided to
the MCU and peripherals. LPM bits in MCR register are cleared by exiting Doze mode.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
Clocks for specific modules can be gated off automatically in Doze mode by programming the MCRG
register.
3.5.2.4
State Retention Mode
This mode has the same functionality as Doze mode, except that the addition of clocks to peripherals are
gated off, and MCU domain PLLs are disabled. SDRAM is put in Self-refresh mode.
State Retention mode is entered by programming the LPM bits in the MCR register the next time the
STANDBY FOR INTERRUPT command is issued.
The sequence below is implemented by the CCM upon entering the State Retention mode:
1. Asserts ccm_sd_lpmd signal to EMI to put SDRAM in self refresh mode
2. Upon emi_sd_lpack assertion, stops clocks to the MCU and peripherals and then stops the PLLs,
if any were enabled
3. If the SBYCS bit in the MCR register is set to “1”, disables selected clock source generator as
follows:
a) If an external oscillator is selected, disables CKIH receiver
b) If FPM is selected, disables FPM
4. If the WBEN bit in the MCR register is set to “1”, assert the ccm_mcu_wb_en signal.
5. If the VSTBY bit was set to “1”, assert the ccm_vstby_pmic signal. This in turn will assert the
pmic_stby output pin, which places the PMIC regulators in standby mode. If the L2PG bit is set to
“1”, asserts the ccm_l2pg_pmic signal, which asserts the l2pg_pmic output pin.
The i.MX31 and i.MX31L exit State Retention mode by any internal or external interrupt.
The sequence below is implemented by the CCM to exit the State Retention mode:
1. If the VSTBY bit was set to “1”, negates the ccm_vstby_pmic signal, which negates the pmic_stby
output pin. If the L2PG bit was set to “1”, negates the ccm_l2pg_pmic signal. A flash of the L2
cache should be performed before the MCU executes the WFI command.
2. If SBYCS bit is set to “1”, enables the clock source generator as follows:
a) If external oscillator is selected, enables CKIH receiver
b) If FPM is selected, enables FPM
c) If the oscillator is selected as a clock source, starts the 32-KHz counter to count the time as
defined by the OSCNT bits
d) If WBEN bit is set to “1”, disables the well-bias
3. After reaching the value defined by the OSCNT bits in MCR register, and if the oscillator is
selected as the clock source, the clock cleaner will be enabled. Indication on the FPM that the clock
output is ready, if is selected, is the assertion of the lock-ready flag.
The time required to disable the well-bias is significantly less than the settling time of the external
oscillator. Indication that the voltage from the PMIC is valid is a PMIC interrupt, which is sent to
the CCM.
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Clocks, Power Management and Reset (AP Clock Controller Module)
4. After the selected clock source is ready and the voltage is valid, then if MPE, UPE or SPE bits are
set to “1”, the relevant PLL’s will be started. If the WBEN bit is set to “1” and SBYCS to “0”, the
well-bias will be disabled, and well-bias counter will be started, running on PLL reference clock.
5. With the MCU, USB, the Serial port (if enabled), and the PLL’s lock ready flag1, negate the
ccm_sd_lpmd signal to the EMI to remove the SDRAM from Self Refresh mode. Then start the
ccm_emi_ahb_clk clock, and input this to the EMI.
6. Upon emi_sd_wack signal assertion, and when the well-bias disabled counter completes, if the
SBYCS is set to “0”, the clocks to the ARM and peripherals will be restored. LPM bits in MCR
register will be cleared by exiting Deep Sleep mode.
3.5.2.5
Deep Sleep Mode
This mode is similar to State retention mode, but supply of the ARM platform is shut down. If ARM State
Retention is required, critical registers data should be saved before entering Deep Sleep mode (executing
WFI instruction).
Entering the Deep Sleep mode follows the same steps as entering State Retention mode with the next
addition to Step 5:
deassert ccm_pgen, ccm_reset_mcu, and ccm_mcupg_pmic signals, which will in turn assert the
mcupg_pmic output pin.
Interrupts in this mode will be managed by a simplified interrupt controller unit in CCM and output of this
unit will place the i.MX31 and i.MX31L processors in Run mode.
Exiting Deep Sleep mode is the same as exiting State Retention mode with the following additions:
Step 1: negate ccm_mcupg_pmic signal.
Step 2: negate mcu_power_gate_en and mcu_reset_out.
1. If MPE bit is set to “0”, skip PLL lock ready flag requirement.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
T
mcu_wb_en
wbcp_fbd
ccm_mcu_mem_pwrdn
ccm_mcu_mem_on
Figure 3-29. Well-Bias Activating and Deactivating and ARM Core Power Gating
T-In Doze mode, this is the WB counter.
In Deep Sleep Mode or State Retention Mode, and if SBYCS = 0, T is the OSCNT (if CKIH is the source)
or FPM lock time (if FPM is the source). If SBYCS = 1 T is the WB counter.
T > 2 ipg_clk_mcu
ipg_clk_arm
ccm_mcu_l2d_sfen
ccm_mcu_l2d_oe
ccm_l2pg_pmic
Figure 3-30. L2 Cache Power Gating
3.5.2.6
Hibernate Mode
The supply of the IC is shut down. The i.MX31 and i.MX31L processors can enter Run mode by external
interrupt only with warm boot operation.
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Clocks, Power Management and Reset (AP Clock Controller Module)
DOZE
MODE
4
WAIT 2
MODE
SR OR DSM
EMI req. if
CG=01||10
11
8
Well-Bias
EXIT 5
Hibernate
9
EMI req. if
CG=01 10
Issue EMI
req.
7
Issue req.
3
Issue req.
1
Issue req.
6
RUN
MODE
0
Figure 3-31. Low Power Modes State Machine
3.5.3
Power Management Techniques Overview
The CCM supports several power management techniques that reduce active and static power
consumption:
Dynamic Voltage Frequency Scaling (DVFS)
Reduces active power consumption by scaling voltage and frequency accordingly
to required MIPs.
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Clocks, Power Management and Reset (AP Clock Controller Module)
Dynamic Process Temperature Compensation (DPTC)
Reduces active power consumption by adjusting supply voltage accordingly
specific process cases, the manner in which the chip was fabricated, and the
ambient temperature.
State Retention Voltage (SRV)
Reduces static power consumption by decreasing supply voltage to minimum
State Retention level. Chip is not functional in this mode.
Active Well-Bias (AWB)
Reduces static power consumption by applying back bias on transistors. AWB can
be applied on ARM11P. ARM11P is not functional when AWB is applied.
L2 Cache Power Gating
Reduces static power consumption by eliminating L2 Cache leakage.
ARM11P Power Gating
Reduces static power consumption by eliminating ARM11P leakage.
3.5.4
DVFS Support
The CCM enables simple S/W dynamic voltage frequency scaling. The frequency of the MCU clock
domain and the voltage of the chip can be changed on the fly while all modules (including the MCU)
continue their normal operation. The voltage of the chip can be changed by setting the DVS0 and DVS1
pins (connected to PMIC). The frequency of the MCU clock domain can be changed by switching to an
alternate PLL clock (MCU or SR PLLs), already locked at a specific frequency, or by merely changing the
post dividers division factors. Figure 3-32 shows the flow of frequency/voltage scaling.
The DVFS load tracking block enables hardware tracking on the MCU load and a generation of an
interrupt when a frequency change is requested. Figure 3-33 shows the DVFS state machine.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
DVFS start
Check LBFL
==1
read LBCF
==0
UPDTEN==0
read LBTR0 and LBTR1 and
write their values to mem buffer
according to LBCF register
write 0 to LBFL
Check UPDTEN
UPDTEN==1
FSVAI==00
check FSVAI
dvsup_val = DVSUP
(up_val=0 && DVSUP==11) ||
check DVSUP
(up_val==1 && DVSUP==00)
FSVAI==10
up_val = 0
vscnt_val = 1
FSVAI==01||10
up_val = 1,
vscnt_val = table[i].vscnt
write 0 to DPVCR
write up_val to UDSC
==0
==1
check up_val
i = dvsup_val+1
write i to DVSUP
pll_switch = table[dvsup_val].pll_sw_down
pll_val = table[dvsup_val].pll_down
pdr0_val = table[dvsup_val].pdr0_down
pdr0_switch = table[dvsup_val].pdr0_sw_down
i = 00
write i to DVSUP
pll_switch = table[dvsup_val].pll_up
pll_val = table[dvsup_val].pll_up
pdr0_val = table[dvsup_val].pdr0_up
pdr0_switch = table[dvsup_val].pdr0_sw_up
write vscnt_val to VSCNT register
read DFSUP register
==1
check pll_switch
==0
dfsup_val[0] = 0
dfsup_val[1] =!DFSUP[1]
Write dfsup_val to DFSUP
dfsup_val[0] = 1
write pdr0_val to PDR0 if pdr0_switch set
Write dfsup_val[0] to DFSUP[0]
write pll_val to current PLL
write pdr0_val to PDR0 if pdr0_switch set
(current pll according to dfsup.val[1])
write dcvr[i][j] values
to DCVR
write 1 to DPVCR
End
Figure 3-32. Frequency/Voltage Switching Procedure
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
0
0
wait_new_freq
1
2
1
wait_pll
_ready
6
3
7
4
3
switch_done
2
wait_for_
finish_switch
5
Figure 3-33. DVFS State Machine
Table 3-28. DVFS Transition Descriptions
Transition
Transition Condition
0
not (1)
1
new pll reg values written, pll restarted and pll
change required
or post-dividers only updated (if dfsup[0] ==1)
2
not (3)
3
(pll lock finished | postdiv only update) and
(voltage ready {voltage counter ended} in case
of freq up)
4
not (5)
5
(switch to pll finished) | (postdiv only updated)
6
1 clk delay in state
7
always
Output
volt_count disabled
dvfs_cnt_rst negated
UPDTEN set to 0
if freq_up => voltage_count enabled and DVSUP values written to
PMIC pins
volt_count disabled
Note: plls are switching at all_counters_in_zero of post-divider
if freq_dw => DVSUP values are written to PMIC pins
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Clocks, Power Management and Reset (AP Clock Controller Module)
3.5.4.1
DVFS Load Tracking Block
The DVFS load tracking block includes the following features:
• Configurable include/exclude of input signals:
— ARM standby signal (idle/non-idle)
— 16 general purpose load tracking signals
• Configurable weight and edge/level detection of each input signal/set of signals.
• Configurable generated clocks and averaging time slicing (respond time).
• Configurable panic mode respond logic (for frequency up).
• Programmable buffer for last 4,8,12, or 16 load tracking samples. Based on value in LBCF in
PMCR0. There is also a buffer full signal—LBFL.
The general purpose load tracking signals are (dvfs_w_sigs[15:0]) are connected at the device level to the
signals in Table 3-29. Figure 3-34 shows the DVFS load tracking module block diagram.
Table 3-29. dvfs_w_sigs Connectivity
Bit #
Signal
Functionality
15:12
ccm_dvgp
Software controllable general purpose bits from the CCM
11
ipi_int_ipu_func
Interrupt line from IPU
10
ipi_gpio1_int0
Interrupt line from GPIO
9
arm11p_fiq_b_rbt_gated
ARM fast interrupt
8
arm11p_irq_b_rbt_gated
ARM normal interrupt
7
m3if_hready_m7
Hready signal of M3IF’s master #7 (IPU)
6
m3if_hready_m6
Hready signal of M3IF’s master #6 (IPU)
5
m3if_hready_m5
Hready signal of M3IF’s master #5 (mpeg4_vga_encoder)
4
m3if_hready_m4
Hready signal of M3IF’s master #4 (SDMA)
3
m3if_hready_m3
Hready signal of M3IF’s master #3 (MAX)
2
mbx_mbxclkgate
Hready signal of M3IF’s master #2 (MBX)
1
m3if_hready_m1
Hready signal of M3IF’s master #1 (L2 Cache)
0
m3if_hready_m0_buf
Hready signal of M3IF’s master #0 (L2 Cache)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Clocks, Power Management and Reset (AP Clock Controller Module)
dvfs_cnt_rst
dvfs_
sig_wt
dvfs_w_sig
extr_w_ld
16
1
0
5
s
h
i
f
t
LTBR[0:1]
DVFEV
freq_pa
ld_add
dvfs_
thresh_
cmp
6
~wfi_pendingdvfs_
stdb_
smpl
stdb_smpl
dvfs_
pre_
avg
pre_avg_ld dvfs_
ld_add
5
dvfs_
ema_
avg
ema_ld
6
up_th_res
freq_up
dvfs_
thresh_
dw_th_res count
freq_dw
div_3_clk
ipg_clk_arm
reset
LTR0 reg
32
LTR1 reg
32
FSVAI
PMCR0 reg
32
Figure 3-34. DVFS Load Tracking Module Block Diagram
3.5.4.1.1
Load Tracking Buffer Register
The purpose of the load tracking buffer register is to save last 16 samples of the tracked load (before EMA
operation). Hence, the upper four bits of ld_add signal (ld_add[5:2]) are saved continuously, overwriting
each time the last sample. Each save is carried upon detecting an edge of the div_3_clk signal.
3.5.5
DPTC support
The DPTC (Dynamic Process and Temperature Compensation) module is a power management module.
The purpose of the DPTC module is to detect the minimum operation voltage for the IC, taking into
account the extreme of processing activity and ambient temperature for a given frequency. It inputs
predefined values for process speed performance measurement and generates an interrupt if the value of
the supply voltage must be updated.
Figure 3-35 is a block diagram of the DPTC module.
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Clocks, Power Management and Reset (AP Clock Controller Module)
placed on chip level
ref_cir_0
ref_cir_1
ref_cir_2
4
count [3.0]
DPTC
ref_cir_3
ref_clk_[3.0]
comp_logic
blocks
sys_clk
_counter
control bits PMCR
ref_clk
reset
ipg_clk
_counter
up. limit
low. limit
FSM
reset
read_clk
ref_cir
register
upper
limit
emg. limit
DPTC en (synced with DVFS)
lower
limit
emerg.
limit
counter_out
(11 bit)
compare_clk
3*10
DCVR0:3
4*32
div_3_clk
1
1
env_dptc_out
0
0
ipi_dptc_out
DVFEN&!DVFIS
!PTVIS
Figure 3-35. DPTC Block Diagram
3.5.5.1
3.5.5.1.1
Blocks Description
FSM Block
The FSM block is responsible for the internal control signals generation. For this purpose it includes a
sys_clk_counter sub-block that creates a long-interval count enable signal, based on the system clock
signal, and received from the sys_clk input pin. Table 3-30 provides the low-power FSM transition
descriptions.
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Clocks, Power Management and Reset (AP Clock Controller Module)
Table 3-30. Low Power FSM Transition Descriptions
Transition
0
Input
ARM not in standby mode—arm_clk_off
asserted||(WIMRandWAMO=11), reset, voltage valid
interrupt (ccm_int_pmic) and valid clocks
Output
* Enable clocks to ARM and peripherals.
* Deassert stop, wait, and doze
signals—ccm_ipg_stop, ccm_ipg_doze,
ccm_ipg_wait.
* Enable interrupts: deassert ccm_int_holdoff.
* Clear LPM bits.
* SDRAM (EMI) not in self refresh
mode—deassert ccm_sd_lpmd
* No request to stop MAX clock—deassert
max_halt_req
* No request for voltage change—deassert
ccm_vstby_pmic
* Well-Bias disabled—deassert ccm_wb_en,
wbcp_fbd.
* No ARM mem I/F power down—deassert
ccm_mcu_mem_pwrdn
* ARM mem. I/F enabled—ccm_mcu_mem_on
* Enable ARM L2 cache memories—assert
ccm_mcu_l2d_oe, deassert
ccm_mcu_l2d_sfen.
* No power down of L2 cache—deassert
ccm_l2pg_pmic
* Disable power gating of ARM—deassert
mcu_power_gate_en
* No reset to ARM—deassert mcu_reset_out
* No power down to ARM domain—deassert
ccm_mcupg_pmic
* According to the clock source—
If CKIH then enable clock amplifier and disable
FPM: deassert ccm_ckih_camp_off,
ccm_fpm_enable
IF FPM then disable clock amplifier and enable
FPM: assert ccm_ckih_camp_off,
ccm_fpm_enable
* Assert requests to IPU if the right glock gating
is selected—assert ccm_ipu_stby_req
CG(11)=00 in CGR1. Only after receiving
ipu_stby_ack the IPU clock is stopped.
* Assert request to SDMA if the right glock
gating is selected—assert
ccm_sdma_stby_req if CG(7)=00 in CGR0.
Only after receiving sdma_stby_ack the SDMA
clock is stopped
* Assert request to EMI if the right clock gating
is chosen—assert ccm_sd_lpmd if CG(4)=00 in
CGR2. Only after receiving emi_sd_lpack with
the EMI clocks be stopped.
* No requests to rtic will be given since RTIC
cannot be stopped at run mode—deassert
ccm_rtic_stby_req.
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Table 3-30. Low Power FSM Transition Descriptions (continued)
Transition
Input
Output
1
ARM in standby mode and LPM in
WAIT—!arm_clk_off&LPM=WAIT
* Disable interrupts—assert ccm_int_holdoff.
* Issue requests to IPU, SDMA, RTIC, and EMI
if the clock gating is chosen for WAIT—assert
ccm_ipu_stby_req if CG(11)=01 in CGR1,
ccm_sdma_stby_req if CG(7)=01 in CGR0,
ccm_rtic_stby_req if CG(5)=01 in CGR2.
* Wait for acknowledges.
2
Received EMI acknowledges if needed (depending on
clock gating)—emi_sd_lpack&(CG(4)=01 in
CGR2)||~emi_sd_lpack&(CG(4)!=01)
* Assert the wait signal to peripherals—assert
ccm_ipg_wait.
* Wait 8 cycles.
* Stop the clocks according to the CGR
registers.
* Enable interrupt—deassert ccm_int_holdoff.
3
ARM in standby mode and LPM in
DOZE—!arm_clk_off&LPM=DOZE
* Disable interrupts—assert ccm_int_holdoff.
* Issue requests to IPU, SDMA, RTIC, EMI and
MAX if the clock gating is chosen for
DOZE—assert ccm_ipu_stby_req if
CG(11)=01||10 in CGR1, ccm_sdma_stby_req
if CG(7)=01||10 in CGR0, ccm_rtic_stby_req if
CG(5)=01||10 in CGR2, max_halt_request.
4
Received EMI acknowledges if needed (depending on
clock gating)—emi_sd_lpack&(CG(4)=01||10 in
CGR2)||~emi_sd_lpack&(CG(4)!=01||10)
* Assert doze signal to peripheral—assert
ccm_ipg_doze.
* Wait 8 cycles.
* Stop the clock according to the CGR registers.
* IF WBEN bit is enabled then well-bias will be
enabled and ARM memory I/F will be powered
down—assert mcu_wb_en, wbcp_fbd,
ccm_mcu_mem_pwrdn, deassert
ccm_mcu_mem_on.
* Enable interrupts—deassert ccm_int_holdoff.
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Table 3-30. Low Power FSM Transition Descriptions (continued)
Transition
Input
Output
5
ARM not in standby mode or wakeup
interrupt—arm_clk_off|| WIMR&(WAMO=00||01||10)
** If LPM=DOZE then well-bias counter starts
according to WBCN value.
* Then well-bias will be disabled and ARM
memory I/F will be enabled—deassert
mcu_wb_en, ccm_mcu_mem_pwrdn, after WB
counter (WBCN) deassert wbcp_fbd, assert
ccm_mcu_mem_on.
** IF LPM=DSM||SR
* If VSTBY bit set remove PMIC regulator from
standby—deassert ccm_vstby_pmic.
* If L2PG is set the power up L2 cache, a flash
should be performed by MCU executing WFI
command—deassert ccm_l2pg_pmic.
ccm_mcu_l2d_sfen will be asserted and
ccm_mcu_l2d_oe will be deasserted.
* If LPM = DSM request to power up
ARM—deassert ccm_mcupg_pmic.
* Then if SBYCS is not set enable clock
generator—IF CKIH deassert
ccm_ckih_camp_off if FPM assert
ccm_fpm_enable.
* If WBEN is set disable well-bias and ARM
mem I/F will be powered up—deassert
mcu_wb_en, ccm_mcu_mem_pwrdn.
* After OSCNT is over (if CKIH) or FPM lock (if
FPM) MPE, UPE and SPE bits will be set, and
the relevant PLLs will start.
* If LPM = DSM release the ARM power gating
in the chip, release ARM reset—deassert
mcu_power_gate_en, assert mcu_reset_out.
* If WBEN is set and
—If SBYCS is set then well-bias counter starts
according to value in WBCN
—If SBYCS is not set then continue. After either
OSCNT is complete (if CKIH is chosen) or FPM
is enabled (if FPM is chosen).
* Then the final stages of releasing the well-bias
and enabling the power of the ARM mem I/F
occur—deassert wbcp_fbd, assert
ccm_mcu_mem_on.
* After PLLs are set and the pll_lock_ready flag
is set (disregard if MPE is set to “0”) remove
SDRAM (EMI) from self refresh mode and start
EMI lock—deassert ccm_sd_lpmd.
6
ARM is standby and LPM in DSM||SR
—arm_clk_off&LPM=DSM||SR
* Disable interrupts—assert ccm_int_holdoff.
* Issue requests to IPU, SDMA, RTIC, and
MAX—assert ccm_ipu_stby_req,
ccm_sdma_stby_req, ccm_rtic_stby_req,
max_halt_request.
7
Received acknowledges—ipu_stby_ack,
sdma_stby_ack, rtic_stby_ack, max_halted
* Issue request to EMI for self refresh
mode—assert ccm_sd_lpmd.
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Table 3-30. Low Power FSM Transition Descriptions (continued)
Transition
Input
Output
8
Received EMI acknowledge—emi_sd_lpack
* Assert stop signal—assert ccm_ipg_stop.
* Wait 8 cycles.
* Stop clocks to MCU and peripherals.
* Stop PLL’s if any where enabled after there
clock is held high—deassert ccm_mpl_cpen,
ccm_spl_cpen, ccm_upl_cpen after
mpl_dpdgck_clk, upl_dpdgck_clk,
spl_dpdgck_clk are high respectively.
* If SBYCS bit is set to “0” disable clock source
generator—IF CKIH then assert
ccm_ckih_camp_off, IF FPM deassert
ccm_fpm_enable.
* If WBEN bit is enabled then well-bias will be
enabled—assert mcu_wb_en, wbcp_fbd.
* If VSTBY bit is enabled then PMIC regulators
are placed in standby—assert
ccm_vstby_pmic.
* If L2PG is set L2 cache memory will be shut
down by deasserting ccm_mcu_l2d_oe and at
least 2 cycles later ccm_mcu_l2d_sfen and
then assert ccm_l2pg_pmic.
* If LPM = DSM reset the ARM, turn on ARM
power gating in the chip and power down the
ARM mem I/F—deassert
ccm_mcu_mem_pwrdn and then assert
ccm_mcu_mem_on, assert
mcu_power_gate_en, ccm_mcupg_pmic,
deassert mcu_reset_out
9
Software request
No change from DSM||SR
10
Received acknowledges—ipu_stby_ack&(CG(11)=01 in
CGR1), sdma_stby_ack&(CG(7)=01 in CGR0),
rtic_stby_ack&(CG(5)=01 in CGR2)
* If EMI clock gating issue request—assert
ccm_sd_lpmd if CG(4)=01 in CGR2.
* If EMI not clock gated continue to next stage.
11
Received acknowledges—ipu_stby_ack&(CG(11)
=01||10 in CGR1), sdma_stby_ack&(CG(7)=01||10 in
CGR0), rtic_stby_ack&(CG(5)=01||10 in CGR2),
max_halted
* If EMI clock gating issue request—assert
ccm_sd_lpmd if CG(4)=01||10 in CGR2.
* If EMI not clock gated continue to next stage.
Figure 3-36 shows the FSM loop.
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next reference
circuit select:
ref_clk_counter
A reference circuit
is enabled by count
0
1
2
3
signal
Comparison between
ref_clk_counter
external performance
result is stored in
limits and measured
ref_cir register
Figure 3-36. FSM Control Loop
Table 3-31 presents the FSM Control Loop stages.
Table 3-31. FSM Control Loop Stages
Operation
Explanation
Active Signals
Level
Reference circuit select
Reference circuit 0–3 is selected
ref_circuit_select
2 bits value
ref_clk_counter reset
Previous reference circuit counting
result is deleted from
ref_circuit_counter
ref_count_reset
low
Reference circuit
performance evaluation
Amount of ref circuit clock cycles is
counted by ref_clk_counter during
defined number of sys clock
count
high
Read reference circuit
count result
Value of ref_circuit_counter is read
to register
read_enable_clk
posedge
Performance comparison:
measured to limits
Reference circuit performance is
compared to the limits from input
register
comp_enable_clk
posedge
Misc.
counter_out
value is reset
counter_out
value is valid
Figure 3-37 shows the FSM control signals waveforms.
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ref_cir_select
00
01
ref_count_reset
count
read_enable_clk
comp_enable_clk
single reference circuit cycle
Figure 3-37. FSM Control Signals Waveforms
All signals are generated based on sys_clk. To create a long “count” signal, a sub-block sys_clk_counter
is used. The sys_clk_counter counts the system clock and stops when the max value is reached. The max
value for sys_clk_counter is set by the SCR bit in the status control register: ‘1’ is equivalent for 512
system clocks and ‘0’ is equivalent for 256 system clocks.
3.5.5.1.2
Ref_clk_counter Block
The ref_clk_counter block acts as a counter for the reference clocks. These clocks are generated by ref_cir
blocks and includes the ref_cir_register (11 bit) for storing the last valid value of the counter.
Ref_cir_counter receives the following signals: ref_clk_reset, read_enable_clk, ref_clk_0, ref_clk_1,
ref_clk_2, ref_clk_3. The output (11 bits) is sent to the counter_out bus.
As long as the ref_clk_counter is not in the reset state (defined by ref_clk_reset active low signal),
counting is enabled. Counter is an 11 bit counter, stored in the ref_cir_register.
3.5.5.1.3
Comp_logic Blocks
The comparison blocks are responsible for the comparison between performance values from performance
limit registers and the actual performance as measured by the ref_clk_counter block. Each one of the
compared signals are 11 bits (due to the fact that the input performance limits are extended by a “0” as the
MSB).
The Comp_logic block inputs the following:
• Performance limit value (10 bits) (the desired performance limit value)
• Actual performance limit value (11 bits) (the measured performance limit value)
• ref_cir_select (2 bits)—index of currently active reference circuit
• RCSE (reference circuits selective enable) (4 bits) from status control register—to get information
about enabled/disabled reference circuits.
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•
•
comp_enable_clk—clock of comparison enable.
Limit type (1 bit)—hard config bit, connected to ground or supply.
The RCSE data is essential for taking/not taking in the account the result of comparison of the currently
active reference circuit. For the disabled reference circuit, the comparison result should be considered as
“right.” A critical situation can occur when all reference circuits are disabled (no real result—all
artificial)—in this case all the outputs should be reset to “0” and the “error” bit in the control status register
must be set.
Comp_logic includes FFs (one for single reference circuit), saving the comparison result for each
reference circuit. The FFs data is used to generate the output signal of the comp_logic block. The data in
the FF is continuously renewed so long as the appropriate reference circuit has completed its cycle and the
data is valid. The FFs data is reset when the DPTC block is disabled or the external reset signal is activated.
Comp_logic blocks can be operated as “high_limit” type and “low_limit” type. For the “high_limit” type
active output, the comparison of ALL reference circuits should exceed the high performance limit. For the
“low_limit” type active output, one or more reference circuit comparison should exceed the low_limit
/emergency_limit value.
3.5.5.1.4
Ref_cir Blocks
The ref_cir blocks are “reference circuit” units, constructed using a ring oscillator with an integrated clock
gating cell. The inverting stages components and their values vary according to the type of ring oscillator.
Ref_cir blocks are built to optimize speed and performance of the most critical paths in the chip for a given
process/temperature.
3.5.5.1.5
Initialization Information
In the control status register, at least one of the RCSE bits should be set (to 1). Otherwise, the error bit will
be activated and the output “limit” signals will be atrophied.
3.5.6
Synchronization Between DVFS and DPTC
To avoid a situation of DPTC trying to update events during voltage update done by DVFS a
synchronization scheme has been created.
The DPTC machine can work in case the DPTC is enabled and the voltage is valid (DPVV = 1) and there
is no voltage change request (DPVCR = 1).
Figure 3-38 shows the DVFS—DPTC synchronization.
DVFS Event
div_3_clk
SDMA Event
Figure 3-38. DVFS—DPTC Synchronization
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3.5.7
Well-Bias Support
Well-bias is implemented with an on-chip charge pump. When well-bias is activated, the voltage of wells
will be pumped to optimal values to enable minimum leakage. Parameters of the charge pump can be
controlled in S/W by setting configuration bits in the PMCR register.
3.5.7.1
ARM Platform Well-Bias Activating
Well-bias of the ARM domain can be activated in Doze or State Retention modes by asserting the
mcu_wb_en signal. The ARM Platform contains memory blocks with stdVt transistors in its interface
sector. Well-Bias eliminates the leakage from these transistors by power gating of this interface—there is,
therefore, no need for any data saving/restoring. Memories interface is power gated by asserting the
ccm_mcu_mem_pwdn signal and negating the ccm_mcu_mem_on signal.
3.5.7.2
ARM Platform Well-Bias Deactivating
When ARM deasserts the arm_clk_off signal, the CCM deasserts mcu_wb_en signal. Clock will be
provided to ARM11P after the time counted by the well-bias counter has elapsed (threshold is defined in
the WBCN bits), or after any other event that lasts longer than 10µs. ARM11P memories interface power
supply is restored by negation of the ccm_mcu_mem_pwdn signal together with mcu_wb_en negation and
assertion of the ccm_mcu_mem_on signal upon clock restoration.
3.5.8
State Retention Voltage Support
In State Retention and Deep Sleep modes, the supply voltage of the i.MX31 and i.MX31L processors, if
not power-gated, can be reduced to a State Retention value, which enables a reduction of chip leakage
current while embedded memory state is dormant. Cores and modules using embedded memory are not
functional in this mode. Voltage will be reduced by PMIC after assertion of the ccm_vstby_pmic signal,
which in turn asserts the VSTBY I/O pin. Voltage will be restored to previous value upon negation of this
signal. Valid voltage is indicated when the PMIC interrupt is asserted.
3.5.9
L2 Cache Power Gating Support
L2 cache power gating can be applied in State Retention and Deep Sleep modes. L2 cache power gating
is implemented by negation of the ccm_l2d_oe signal and assertion of the ccm_l2d_sfen signal (after two
cycles of the mcu_clk have passed). Supply of L2 cache is power gated by assertion of the ccm_l2pg_pmic
signal, which in turn asserts the L2PG I/O pin. Upon exiting low power mode, the L2 cache supply is
restored by negation of the ccm_l2pg_pmic signal and after voltage is valid and clocks are restored,
negation of the ccm_l2d_sfen signal and assertion of the ccm_l2d_oe signal.
3.5.10
ARM Platform Power Gating Support
To provide interrupt monitoring during ARM11P power gating, the CCM contains a simplified interrupt
controller—this consists of an “OR” between all interrupts with “enable” bit for each interrupt. Special
power gasket cells are tied to all outputs of ARM11P to avoid contention during supply powering down
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and restoring. ARM11P supply is power gated by assertion of the ccm_mcupg_pmic signal, which in turn
asserts the MCUPG I/O pin. The reset_mcu signal is asserted during ARM11P power gating.
3.5.11
3.5.11.1
DFT Support
Overview
The CCM supports the following features to provide DFT support:
• Deterministic reset
• CCM Scan Div Mode
• CCM Long Chain Mode
• CCM SAF Scan Test Mode
• CCM Trans. System Mode
• CCM Trans. Last Shift Mode
• CCM Standalone Scan Mode
• Functional Mode
3.5.11.2
Deterministic Reset
The i.MX31 and i.MX31L processors support a deterministic reset test mode to enable synchronization
between the tester clock and the EMI I/O port during test.
In this mode, the MCU PLL is applied in its phase lock mode and an equivalence path will be applied to
get a minimum phase difference between the CKIH clock and the EMI BCLK IO pin. In this mode, system
clocks will be frozen after the arm_active output of ARM is asserted, thus indicating that the first fetch has
been executed by ARM. Clocks will be restored after the ipp_mcu_handshake signal assertion.
3.5.11.3
Clocks in Scan Divergence Mode
This mode is a failure analysis mode. In this mode all clocks are fetched from one source (mcu_pll). The
CCM freezes all clocks after the scan divergence counter reaches the value defined by the
ipt_scan_div_mcu_cnt[9:0] input signals. All the flops values then are shifted out.
3.5.11.4
Clocks in Long Chain Mode
In this mode, all the sequential elements except the BISTs are toggled in by the TCK clock. The BISTs are
in Functional Mode and run on the functional clock frequency.
3.5.11.5
Clocks in SAF Scan Test Mode
In this mode, the CCM shunts test clocks that normally go to I/O pads directly (dividers and post-dividers
in bypass state) to the operational clocks. See Figure 3-39 for its timing diagram.
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Clocks, Power Management and Reset (AP Clock Controller Module)
Launch cycle
Capture cycle
Capture 2 cycle
Shift Clock (Load)
Shift Clock (Unload)
Clock
AHB clock
AHB clock
AHB clk
ipt_iomux_se
ipt_se
divider bypass
(internal signal)
ipt_se_2dft_chop
ipt_launch_clk_start
ipt_
chop_mode
xxyyzz
Don’t Care
Don’t Care
xxyyzz
Figure 3-39. “Stuck-At Fault” (SAF) mode Launch and Capture Timing Diagram
3.5.11.6
Clocks in Transition Mode
In Transition mode, launch and capture clock cycles are generated at the functional frequency. See
Figure 3-40 for its timing diagram.
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Clocks, Power Management and Reset (AP Clock Controller Module)
Dummy cycles Launch cycle
Capture cycle
Capture 2 cycle
Dummy
cycles
CLOCK
AHB clock
AHB clock
AHB clk
ipt_iomux_se
ipt_se
divider bypass
(internal signal)
ipt_se_2dft_chop
ipt_launch_clk_start
ipt_
chop_mode
xxyyzz
xxyyzz
10_10_10
Figure 3-40. Transition Mode Launch and Capture Timing Diagram
3.5.11.7
Clocks in Transition Last Shift Mode
In the Transition Last Shift mode, launch and capture clock cycles are generated at the functional
frequency (like Transition mode), but the scan enable signal is asserted after launching the clock cycle. See
Figure 3-41 for its timing diagram.
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Clocks, Power Management and Reset (AP Clock Controller Module)
Dummy Cycles Launch Cycle
Capture Cycle Capture 2 Cycle
Dummy
Cycles
CLOCK
AHB clock
AHB clock
AHB clk
ipt_launch_clk_start
ipt_iomux_se
ipt_se
divider bypass
(internal signal)
ipt_se_2dft_chop
ipt_
chop_mode
xxyyzz
10_10_10
xxyyzz
Figure 3-41. Transition Last Shift Mode Launch and Capture Timing Diagram
3.5.11.8
Clocks in Standalone Scan Mode
This is a unique test mode that was created to check the Clock Control Module (CCM). During this mode,
no provided clocks are needed, and as such the clocks can be checked in various configurations regardless
of the clock output form. A safe mode ability can be achieved by blocking all CCM output clocks to avoid
or cancel any spike issues.
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3.6
3.6.1
Reset Controller
Functional Description of the Reset Module
The reset module controls or distributes all of the system reset signals used by the i.MX31 and i.MX31L.
The reset module generates eight distinct events.
• mcu_reset_out signal is connected to ARM11P, RTIC, and SCC.
• reset_fuse signal is connected to laser fuses in L2 cache data array through the FSH module.
• ccm_por_reset signal is connected to TCU and WDOG modules.
• periph_reset_out signal is connected to all peripherals except EMI.
• ccm_pll_reset1 signal is connected to three PLLs and FPM.
• ccm_pll_reset2 signal is connected to modules engaged in boot and security (IIM, RNGA, RTC).
• emi_reset_ signal is connected to EMI.
• ect_reset signal is connected to the ECT module.
3.6.2
Reset Negation Sequence
The reset exit sequence is as follows:
1. Fuse reset is generated (after por reset only) and then follows:
a) FPM will be enabled
b) Boot mode pins value will be sampled
c) Reset to PLLs, peripherals including IIM and JTAG will be negated. The negation is
synchronized to CKIL.
2. After FPM lock ready flag is asserted, and if ipp_clkss=0 or the oscillator counter has completed
counting, and if ipp_clkss=1, all three PLLs will be restarted.
3. After the MCU PLL lock ready flag is asserted, a clock to the CCM and IIM is provided as follows:
a) Generate NFC boot signals, if boot is done from NF
4. After the counter has completed counting, provide clocks to peripherals and MCU as follows:
a) After 16 mcu_clk cycles, negate the mcu_reset_out. The negation is synchronized to CKIL.
b) ARM11 processor begins fetching code from the internal bootstrap ROM, sync flash or CS0
space. The memory location of the fetch depends on the configuration of the BOOT pins and
the value of the TEST pin on the rising edge of the reset.
3.6.3
Global Reset
Global reset will reset cores and all peripherals. Any one of the following events or conditions can cause
a global reset:
• An external qualified low condition on the por pin
• An external qualified low condition on the reset_in pin
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•
•
A low condition on wdog_mcu_reset
A JTAG command
3.6.4
MCU Reset
Any qualified global reset signal resets the ARM11 Platform and all related peripherals to their default
state. After the internal reset is deasserted, the ARM11 processor begins fetching code from the internal
bootstrap ROM, sync flash or CS0 space. The memory location of the fetch depends on the configuration
of the BOOT pins and the value of the TEST pin on the rising edge of the hreset.
3.6.5
Watchdog Resets
There are two different watchdog reset events that can occur: a time-out event or a software reset. A
watchdog module reset causes a reset of the chip, and the CCM thereby generates a reset pulse. All
registers in the CCM—except those that can be reset by por_reset signal only—will be reset to their default
values. When the MCU comes out of reset it can check the “reset source” bits in the CCM module and
execute a different power mode transition routine accordingly.
3.6.5.1
The Reset Negation Sequence on a Watchdog Event
The following defines the reset negation sequence on a watchdog event (see Figure 3-42 and Figure 3-43):
1. A reset that is received from the watchdog is synchronized by CKIL.
2. The exit of the reset is also synchronized by CKIL.
3. After the two samples of the reset, the reset is given to the PLLs and peripheral, causing the
watchdog to release the reset.
4. After 1 CKIL, the reset given to the peripherals and PLLs will be released.
ipg_clk
wdog_reset
2 CKILs
ccm_pll_reset1
ccm_pll_reset2
periph_reset_out
1–2 CKILs
Figure 3-42. Watchdog Software Reset Diagram
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Delay inside WDOG
wdog_reset
CKIL
ccm_pll_reset1
ccm_pll_reset2
periph_reset_out
1–2 CKILs
Figure 3-43. Watchdog Timeout Event Reset Diagram
3.6.6
S/W Peripheral Reset
MCU peripherals (except CCM and PLLs) can be reset by writing the PERES bit in the PCSR register.
3.6.7
JTAG S/W Reset
The i.MX31 and i.MX31L processors can be reset via S/W from a JTAG module, either by a signal or by
a general purpose bit.
3.7
Power On Reset (Boot)
For more information, see Chapter 7, “i.MX31 and i.MX31L Boot.”
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Signal Multiplexing
Chapter 4
Signal Multiplexing
This chapter identifies and describes the I/O module, which configures and controls the multiplexing of
signals going to and from the i.MX31 or i.MX31L IC. This chapter also provides information about the
I/O needed to configure and operate the I/O module.
NOTE
In previous versions of this manual, this chapter was named “Signal
Descriptions and Pin Assignments.”
4.1
Overview
This section provides an overview of the configuration and operation of the I/O MUX Controller
(IOMUXC) module. The IOMUXC module, shown in Figure 4-1, is composed of three hardware blocks:
•
•
•
MUX—Routes signals to and from the I/O
Buffers—Logic level converters and drivers for interfacing the signals to the external contacts of
the IC. I/O characteristics of each line are determined by these buffers.
Control Registers
— Software MUX Control (SW_MUX_CTL)—These register control the configuration of the
signal lines connecting the On-chip peripherals to the contacts. See SW_MUX_CTL registers.
— I/O Line Characteristics (SW_PAD_CTL)—These registers configure features such as
pull-ups, drive strength, and hysteresis. See SW_PAD_CTL registers.
While there is interaction between the GPIO and the IOMUXC, the operation of the GPIO is described in
Chapter 5, “General Purpose Input/Output (GPIO).”
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Signal Multiplexing
I/O MUX Controller Module
One channel shown
Hardware Mode 1
Hardware Mode 2
Functional Mode
Alternate Mode 1
Buffers
Alternate Mode 2
On-chip
Peripherals
MUX
I/O
Alternate Mode 3
Alternate Mode 4
Alternate Mode 5
Alternate Mode 6
GPIO
GPIO Mode
Control Registers
GPR: Hardware Modes
SW_MUX_CTL: Functional, Alternate
or GPIO Modes
SW_PAD_CTL: I/O Characteristics
Figure 4-1. I/O Signal Multiplexing Block Diagram
4.2
IOMUX Controller (IOMUXC)
The IOMUXC registers control features in the IOMUXC. These registers perform the following tasks:
• Controls the IOMUX input and output paths.
• Controls I/O line properties such as pull-up, pull-down, and hysteresis.
• Monitors off-chip interrupts.
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Signal Multiplexing
Figure 4-2 shows the registers that control the IOMUXC.
Multiplexer Control
SW_MUX_CTLn[7:0]
0
7
SW_MUX_CTL0[7:0]
0
7
IP Bus I/F
Input MUX
Control
Reserved
Output MUX
Control
gpr[31:0]
GPR[31:0]
I/O Characteristics Control
SW_PAD_CTLn[9:0]
0
9
SW_PAD_CTL0[9:0]
9
0
ipp_sre
ipp_dse0
ipp_dse1
ipp_ode
ipp_hys
ipp_pus1
ipp_pus0
ipp_pue
ipp_pke
ipp__loopback
Figure 4-2. IOMUXC Registers
4.2.1
Software Multiplexor Control (SW_MUX_CTL)
The SW_MUX_CTL block consists of registers that control each IOMUX on an individual I/O line basis.
The SW_MUX_CTL registers are partitioned into 4 × 8 bit fields. Each field is mapped to a specific I/O
line and is partitioned as follows: four bits to control the input path, three bits to control the output path,
and one reserved bit.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-3
Signal Multiplexing
4.2.2
Software Pad Control (SW_PAD_CTL)
The SW_PAD_CTL block consists of registers that control the characteristics of each I/O line. The
SW_PAD_CTL registers are partitioned into 3×9 bit fields, with each field mapped to a specific I/O line.
Each field in the register controls several parameters of the I/O characteristics (for example,
pull-up/pull-down, keeper, max drive, hysteresis, and open-drain).
4.3
Memory Map and Register Definition
Table 4-1 shows the IOMUXC memory map.
Table 4-1. IOMUX Memory Map
Address
Register
Access
Reset Value
Section/Page
0x43FA_C008
General Purpose Register (GPR)
R/W
0x0000_0000
4.3.2/4-5
0x43FA_C00C
to
0x43FA_C150
Software MUX Control Register (SW_MUX_CTL)
R/W
See register
descriptions.
4.3.3/4-10
0x43FA_C154
to
0x43FA_C308
Software Pad Control Register (SW_PAD_CTL)
R/W
See register
descriptions.
4.3.7/4-42
4.3.1
Register Summary
Figure 4-3 shows the key to the register fields and Table 4-2 shows the register figure conventions.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0
bit
only bit
only bit BIT to clear w1c
bit BIT
N/A
Figure 4-3. Key to Register Fields
Table 4-2. Register Figure Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
r
Read only. Writing this bit has no effect.
w
Write only.
rw
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Self-clearing
bit
Writing a one has some effect on the module, but it always reads as zero.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-4
Freescale Semiconductor
Signal Multiplexing
Table 4-2. Register Figure Conventions (continued)
Convention
Description
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name] Reset value is determined by polarity of indicated signal.
Table 4-3. IOMUXC Register Summary
Field
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
0x43FA_C008
GPR[31:0]
R
W
R
0x43FA_C00C
to
0x43FA_C150
W
SW_MUX_CTLx[31:0]
R
W
R
0x43FA_C154
to
0x43FA_C308
W
SW_PAD_CTLx[31:0]
R
W
4.3.2
General Purpose Register (GPR)
The General Purpose Register (GPR) is used to configure the IOMUXC. Bits in the GPR control
combinations of predefined I/O type signals in the IOMUXC which are prioritized as Hardware modes 1
and 2 (HW1 and HW2). The priority of these hardware modes is shown in Table 4-7. Figure 4-4 shows the
GPR register; Table 4-4 provides its field descriptions, and the bit definitions. Each bit controls a
combination of I/O lines, functions or modes. The operation of each bit is defined in Table 4-5.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-5
Signal Multiplexing
0x43FA_C008
Access: User Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
GPR[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
GPR[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 4-4. General Purpose Register (GPR)
Table 4-4. GPR Register Field Description
Name
Description
31–0
GPR[31:0]
Each bit in this register controls a combination of I/O Type signals or selection/modes. The signals are
routed through the IOMUXC, providing 32 combinations of settings.
Table 4-5 shows which signals or hardware modes are controlled by each GPR bit. The multiplexing data
about the signals being controlled is listed in Table 0-1 on page Special.
Table 4-5. Hardware Mode Definitions by GPR Bit Position
Bit
Definition
HW
Mode
GPR bit = 0
GPR bit = 1
GPR[0]
Selects FIR or UART2 SDMA events
—
UART2 DMA requests FIR DMA requests are
are selected for DMA selected for DMA events 16
and 17.
events 16 and 17.
GPR[1]
Forces all DDR type contacts to DDR Drive
Strength setting.
—
Inactive
(recommended)
Forces DDR type I/O contacts
to DDR mode1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-6
Freescale Semiconductor
Signal Multiplexing
Table 4-5. Hardware Mode Definitions by GPR Bit Position (continued)
Bit
GPR[2]
Definition
Overrides the Full UART group default
signals on page A-1 with CSPI1.
HW
Mode
GPR bit = 0
HW1
Inactive
Replaces Full UART Group
with CSPI1 signals.
GPR bit = 1
UART1 signals DSR_DCE1, RI_DCE1,
and DCD_DCE1 are multiplexed with HW1
mode JTAG signals. These signals are not
controlled by GPR[2], they are controlled
via the test signal CE_CONTROL which
should be tied to GND to prevent
multiplexing with the JTAG signals
To multiplexing of the CSPI1 signals,
is controlled by the SW_MUX_CTL
registers. The steps are as follows:
• Ensure CE_CONTROL is tied to GND
• To output CSPI1 MOSI, MISO, SS0,
SS1, and SS2 set GPR[2]
• To output signals CSPI1 SCLK,
SPI_RDY, SS3 on DSR_DCE1,
RI_DCE1, and DCD_DCE1 configure
SW_MUX_CTL registers for alt mode 1
for CSPI1
GPR[3]
Overrides the PWMO default signal with
the ATA IORDY signal
HW1
Inactive
Enable ATA IORDY signal on
PWMO contact.
GPR[4]
Overrides the USBH2 default signals with
the following ATA signals
• DA[2:0]
• DMARQ
• BUFFER_EN
• INTRQ
HW1
Inactive
Enable ATA signals on USBH2
contacts
GPR[5]
Overrides the EMI Group NANDF default
signals with ATA Data[13:7]
HW1
Inactive
Enable ATA DATA7-13 on
NANDF contacts.
GPR[6]
Overrides the default EMI Group signals
with the following ATA signals:
• DA[2:0]
• DMARQ
• BUFFER_EN
• INTRQ
HW2
Inactive
Enable ATA signals on NANDF
contacts
GPR[7]
Override the default IPU (CSI) /I2C Group
signals with the ATA Data.
HW1
Inactive
Enable DATA0-13 signals of
ATA on IPU (CSI) and
DATA14-15 on I2C
GPR[8]
Overrides the default AudioPort 3 and
AudioPort6 Group signals with the ATA
Data signals.
HW1
Inactive
Enable DATA7-10 signals of
ATA on AudioPort3 and
DATA11-13 on AudioPort6
GPR[9]
Overrides the default Timer/CSPI1 Group
signals with ATA Data signals.
HW1
Inactive
Enable ATA DATA14-15 on
Timer Group contacts and
DATA0-6 on CSPI1 Group
contacts.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-7
Signal Multiplexing
Table 4-5. Hardware Mode Definitions by GPR Bit Position (continued)
Bit
Definition
HW
Mode
GPR bit = 0
GPR bit = 1
GPR[10]
Overrides the default CSPI1 signals with
the following ATA signals
• DA[2:0]
• DMARQ
• BUFFER_EN
• INTRQ
HW2
Inactive
Enable ATA signals on CSPI1
Group contacts
GPR[11]
Overrides the default AudioPort 3 and
AudioPort6 Group signals with USBH2
signals.
HW2
Inactive
Enable USBH2 signals on
AudioPort 3 and AudioPort6
GPR[12]
Selects either CSD0 or WEIM on EMI CS2
contact.
—
CSD0 is selected for
EMI CS2
WEIM is selected for EMI CS2
GPR[13]
Selects either CSD1 or WEIM on EMI CS3
contact.
—
CSD1 is selected for
EMI CS3
WEIM is selected for EMI CS3
GPR[14]
Selects either CSPI1 or UART3 DMA
requests.
—
CSPI1 DMA request
is selected for events
8 and 9.
UART3 DMA request is
selected for events 8 and 9.
GPR[15]
Selects either External or MBX DMA
requests.
—
External DMA
Request2 is selected
for event 14
MBX DMA request is selected
for event 14.
GPR[16]
Enables Tamper Detect Logic.
—
Inactive
Tamper detect logic is
enabled.
GPR[17]
Overrides default DSR_DCE1 signal with
the USBOTG_DATA4 signal.
HW2
Inactive
Enable USBOTG_DATA4 on
DSR_DCE1 contact.
GPR[18]
Overrides the default Full UART Group
signals DCD_DCE1, DSR_DCE1 and
RI_DCE1 with USBOTG_DATA[5:3].
HW2
Inactive
Enable USBOTG_DATA[5:3]
on Full UART Group contacts
GPR[19]
Selects either SDHC1 or MSHC1 DMA
requests.
—
SDHC1 DMA
Request Is Selected
for event 20
MSHC1 DMA request is
selected for event 20.
GPR[20]
Selects either SDHC2 or MSHC2 DMA
requests.
—
SDHC2 DMA
Request Is Selected
for event 21
MSHC2 DMA request is
selected for event 21.
GPR[21]
Selects GPIO3_0 or SPLL_BYPASS_CLK.
Note: SPLL_BYPASS_CLK is intended for
testing purposes.
HW1
Inactive
Enable SPLL clock bypass
through GPIO3_0 contact.
GPR[22]
Selects GPIO3_1 or UPLL_BYPASS_CLK.
Note: UPLL_BYPASS_CLK is intended for
manufacturing testing.
HW1
Inactive
Enable UPLL clock bypass
through GPIO3_1 contact.
GPR[23]
When MSHC2 clock is selected using
Alternate Mode 2, this bit controls the drive
strength on PC_CD1_B as either a
standard/high or maximum drive strength.
—
Standard or high drive Maximum drive strength
strength
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-8
Freescale Semiconductor
Signal Multiplexing
Table 4-5. Hardware Mode Definitions by GPR Bit Position (continued)
Bit
1
Definition
HW
Mode
GPR bit = 0
GPR bit = 1
GPR[24]
When MSHC2 clock is selected using
Alternate Mode 2, this bit controls the
output on PC_CD1_B as either a slow or
fast slew rate signal
—
Slow slew rate
Fast slew rate
GPR[25]
Selects either CSPI3 or UART5 DMA
requests.
—
CSPI3 DMA requests UART5 DMA requests are
selected for events 10 and 11.
are selected for
events 10 and 11.
GPR[26]
Overrides the default Keypad Group
signals with the following ATA signals
• DA[2:0]
• DMARQ
• BUFFER_EN
• INTRQ
HW1
Inactive
Enable ATA signals on Keypad
Group contacts
GPR[27]
Overrides the default signal SFS6 with
USBH1_SUSPEND.
HW1
Inactive
Enable USBH1_SUSPEND
signal on SFS6 contact.
GPR[28]
Enables USBOTG loopback
Note: This is intended for manufacturing
testing.
—
Inactive
Turn on sw_input_on
(loopback) on some USBOTG
contacts
GPR[29]
Enables USBH1 loopback
Note: This is intended for manufacturing
testing.
—
Inactive
Turn on sw_input_on
(loopback) on some USBH1
contacts
GPR[30]
Enables USBH2 loopback
Note: This is intended for manufacturing
testing.
—
Inactive
Turn on sw_input_on
(loopback) on some USBH2
contacts
GPR[31]
Enables DDR Drive Strength setting on the
CLKO contact.
—
Inactive
Enable DDR mode on CLKO
contact
Setting this bit is not recommended as it may produce excessive overshoot.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-9
Signal Multiplexing
4.3.3
Software Multiplexor Control Register (SW_MUX_CTL)
The SW_MUX_CTL register controls the IOMUX. Figure 4-5 describes an example generic
SW_MUX_CTL register. Table 4-6 provides the register’s field descriptions; Table 4-7 lists its priorities.
0x43FA_C00C
to
0x43FA_C150
30
28
27
26
25
22
21
20
19
18
17
16
MUX1_IN
FUNC_IN
GPIO_PSR/ISR
MUX2_IN
MUX1_IN
FUNC_IN
SW_MUX_CTL_SIGNAL 3
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
SW_MUX_OUT_
EN
7
6
5
4
3
2
1
GPIO_PSR/ISR
FUNC_IN
7
MUX1_IN
SW_MUX_OUT_EN
MUX2_IN
W
FUNC_IN
SW_MUX_CTL_SIGNAL 1
MUX1_IN
SW_MUX_CTL_SIGNAL 2
GPIO_PSR/ISR
R
SW_MUX_OUT_
EN
MUX2_IN
SW_MUX_OUT_EN
Field Bits
23
SW_MUX_CTL_SIGNAL 4
W
Field Bits
24
MUX2_IN
R
29
GPIO_PSR/ISR
31
Access: User Read/Write
0
Figure 4-5. SW_MUX_CTL Register
Table 4-6. SW_MUX_CTL Register Field Descriptions
Register Bit
SW_MUX_CTL[31]
SW_MUX_CTL[23]
SW_MUX_CTL[15]
SW_MUX_CTL[7]
Bit Name
Setting
—
Reserved
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-10
Freescale Semiconductor
Signal Multiplexing
Table 4-6. SW_MUX_CTL Register Field Descriptions (continued)
Register Bit
Bit Name
SW_MUX_CTL[30:28]
SW_MUX_CTL[22:20]
SW_MUX_CTL[14:12]
SW_MUX_CTL[6:4]
sw_mux_out_en
SW_MUX_CTL[27:24]
SW_MUX_CTL[19:16]
SW_MUX_CTL[11:8]
SW_MUX_CTL[3:0]
mux2_in, mux1_in, func_in,
gpio_psr/isr
Setting
000
001
010
011
100
101
110
111
MUX Output Selection
GPIO DR (data register) output
Functional output
Alternate mode 1 output
Alternate mode 2 output
Alternate mode 3 output
Alternate mode 4 output
Alternate mode 5 output
Alternate mode 6 output
MUX Input Selection
0000 No inputs selected
0001 GPIO PSR/ISR input
0010 Functional input
0100 Alternate Mode 1 input
1000 Alternate Mode 2 input
0011 Not recommended
0101 Not recommended
0110 Not recommended
0111 Not recommended
1001 Not recommended
1010 Not recommended
1011 Not recommended
1100 Not recommended
1101 Not recommended
1110 Not recommended
1111 Not recommended
4.3.4
Register Descriptions for SW MUX Control (SW_MUX_CTL)
Figure 4-6 through Figure 4-87 show the sw_mux_ctl registers. The functional multiplexing information
shown in Table A-1 of the Appendix A, “i.MX31/31L Multiplexing and I/O Settings” enables the user to
select the function of each I/O line by configuring the GPR or appropriate SW_MUX_CTL registers. The
data in the table applies to any I/O that is multiplexed to provide different functions.
Additional information about EMI Multiplexing is shown in Table A-2 in Appendix A, “i.MX31/31L
Multiplexing and I/O Settings.”
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-11
Signal Multiplexing
Absolute:
0x43FA_C00C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_cspi3_miso
20
19
18
17
16
sw_mux_ctl_cspi3_sclk
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_cspi3_spi_rdy
sw_mux_ctl_ttm_pad
W
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Figure 4-6. Register Description sw_mux_ctl_cspi3_miso_cspi3_sclk_cspi3_spi_rdy_ttm_pad
Absolute:
0x43FA_C010
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ata_reset_b
20
19
18
17
16
sw_mux_ctl_ce_control
W
Reset
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_clkss
sw_mux_ctl_cspi3_mosi
W
Reset
0
0
0
1
0
0
1
0
0
0
0
0
0
0
Figure 4-7. Register Description sw_mux_ctl_ata_reset_b_ce_control_clkss_cspi3_mosi
Absolute:
0x43FA_C014
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ata_cs1
20
19
18
17
16
sw_mux_ctl_ata_dior
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_ata_diow
sw_mux_ctl_ata_dmack
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-8. Register Description sw_mux_ctl_ata_cs1_ata_dior_ata_diow_ata_dmack
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-12
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C018
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd1_data1
20
19
18
17
16
sw_mux_ctl_sd1_data2
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_sd1_data3
sw_mux_ctl_ata_cs0
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-9. Register Description sw_mux_ctl_sd1_data1_sd1_data2_sd1_data3_ata_cs0
Absolute:
0x43FA_C01C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_d3_spl
20
19
18
17
16
sw_mux_ctl_sd1_cmd
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_sd1_clk
sw_mux_ctl_sd1_data0
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-10. Register Description sw_mux_ctl_d3_spl_sd1_cmd_sd1_clk_sd1_data0
Absolute:
0x43FA_C020
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_vsync3
20
19
18
17
16
sw_mux_ctl_contrast
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_d3_rev
sw_mux_ctl_d3_cls
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-11. Register Description sw_mux_ctl_vsync3_contrast_d3_rev_d3_cls
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-13
Signal Multiplexing
Absolute:
0x43FA_C024
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ser_rs
20
19
18
17
16
sw_mux_ctl_par_rs
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_write
sw_mux_ctl_read
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-12. Register Description sw_mux_ctl_ser_rs_par_rs_write_read
Absolute:
0x43FA_C028
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd_d_io
20
19
18
17
16
sw_mux_ctl_sd_d_clk
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_lcs0
sw_mux_ctl_lcs1
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-13. Register Description sw_mux_ctl_sd_d_io_sd_d_clk_lcs0_lcs1
Absolute:
0x43FA_C02C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_hsync
20
19
18
17
16
sw_mux_ctl_fpshift
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_drdy0
sw_mux_ctl_sd_d_i
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-14. Register Description sw_mux_ctl_hsync_fpshift_drdy0_sd_d_i
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-14
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C030
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ld15
20
19
18
17
16
sw_mux_ctl_ld16
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_ld17
sw_mux_ctl_vsync0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-15. Register Description sw_mux_ctl_ld15_ld16_ld17_vsync0
Absolute:
0x43FA_C034
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ld11
20
19
18
17
16
sw_mux_ctl_ld12
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_ld13
sw_mux_ctl_ld14
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-16. Register Description sw_mux_ctl_ld11_ld12_ld13_ld14
Absolute:
0x43FA_C038
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ld7
20
19
18
17
16
sw_mux_ctl_ld8
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_ld9
sw_mux_ctl_ld10
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-17. Register Description sw_mux_ctl_ld7_ld8_ld9_ld10
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-15
Signal Multiplexing
Absolute:
0x43FA_C03C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ld3
20
19
18
17
16
sw_mux_ctl_ld4
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_ld5
sw_mux_ctl_ld6
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-18. Register Description sw_mux_ctl_ld3_ld4_ld5_ld6
Absolute:
0x43FA_C040
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_usbh2_data1
20
19
18
17
16
sw_mux_ctl_ld0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_ld1
sw_mux_ctl_ld2
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-19. Register Description sw_mux_ctl_usbh2_data1_ld0_ld1_ld2
Absolute:
0x43FA_C044
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_usbh2_dir
20
19
18
17
16
sw_mux_ctl_usbh2_stp
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_usbh2_nxt
sw_mux_ctl_usbh2_data0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-20. Register Description sw_mux_ctl_usbh2_dir_usbh2_stp_usbh2_nxt_usbh2_data0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-16
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C048
31
30
R
Access: User Read/Write
29
28
27
26
25
24
23
22
21
sw_mux_ctl_usbotg_data5
20
19
18
17
16
sw_mux_ctl_usbotg_data6
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_usbotg_data7
sw_mux_ctl_usbh2_clk
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-21. Register Description sw_mux_ctl_usbotg_data5_usbotg_data6_usbotg_data7_usbh2_clk
Absolute:
0x43FA_C04C
31
30
R
Access: User Read/Write
29
28
27
26
25
24
23
22
21
sw_mux_ctl_usbotg_data1
20
19
18
17
16
sw_mux_ctl_usbotg_data2
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_usbotg_data3
sw_mux_ctl_usbotg_data4
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-22. Register Description sw_mux_ctl_usbotg_data1_usbotg_data2_usbotg_data3_usbotg_data4
Absolute:
0x43FA_C050
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_usbotg_dir
20
19
18
17
16
sw_mux_ctl_usbotg_stp
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_usbotg_nxt
sw_mux_ctl_usbotg_data0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-23. Register Description sw_mux_ctl_usbotg_dir_usbotg_stp_usbotg_nxt_usbotg_data0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-17
Signal Multiplexing
Absolute:
0x43FA_C054
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_usb_pwr
20
19
18
17
16
sw_mux_ctl_usb_oc
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_usb_byp
sw_mux_ctl_usbotg_clk
W
Reset
0
0
0
1
0
0
1
0
0
0
0
0
0
0
Figure 4-24. Register Description sw_mux_ctl_usb_pwr_usb_oc_usb_byp_usbotg_clk
Absolute:
0x43FA_C058
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_tdo
20
19
18
17
16
sw_mux_ctl_trstb
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_de
sw_mux_ctl_sjc_mod
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-25. Register Description sw_mux_ctl_tdo_trstb_de_b_sjc_mod
Absolute:
0x43FA_C05C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_rtck
20
19
18
17
16
sw_mux_ctl_tck
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_tms
sw_mux_ctl_tdi
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-26. Register Description sw_mux_ctl_rtck_tck_tms_tdi
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-18
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C060
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_key_col4
20
19
18
17
16
sw_mux_ctl_key_col5
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_key_col6
sw_mux_ctl_key_col7
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-27. Register Description sw_mux_ctl_key_col4_key_col5_key_col6_key_col7
Absolute:
0x43FA_C064
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_key_col0
20
19
18
17
16
sw_mux_ctl_key_col1
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_key_col2
sw_mux_ctl_key_col3
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-28. Register Description sw_mux_ctl_key_col0_key_col1_key_col2_key_col3
Absolute:
0x43FA_C068
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_key_row4
20
19
18
17
16
sw_mux_ctl_key_row5
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_key_row6
sw_mux_ctl_key_row7
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-29. Register Description sw_mux_ctl_key_row4_key_row5_key_row6_key_row7
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-19
Signal Multiplexing
Absolute:
0x43FA_C06C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_key_row0
20
19
18
17
16
sw_mux_ctl_key_row1
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_key_row2
sw_mux_ctl_key_row3
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-30. Register Description sw_mux_ctl_key_row0_key_row1_key_row2_key_row3
Absolute:
0x43FA_C070
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_txd2
20
19
18
17
16
sw_mux_ctl_rts2
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_cts2
sw_mux_ctl_batt_line
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-31. Register Description sw_mux_ctl_txd2_rts2_cts2_batt_line
Absolute:
0x43FA_C074
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ri_dte1
20
19
18
17
16
sw_mux_ctl_dcd_dte1
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_dtr_dce2
sw_mux_ctl_rxd2
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-32. Register Description sw_mux_ctl_ri_dte1_dcd_dte1_dtr_dce2_rxd2
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-20
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C078
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ri_dce1
20
19
18
17
16
sw_mux_ctl_dcd_dce1
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_dtr_dte1
sw_mux_ctl_dsr_dte1
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-33. Register Description sw_mux_ctl_ri_dce1_dcd_dce1_dtr_dte1_dsr_dte1
Absolute:
0x43FA_C07C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_rts1
20
19
18
17
16
sw_mux_ctl_cts1
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_dtr_dce1
sw_mux_ctl_dsr_dce1
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-34. Register Description sw_mux_ctl_rts1_cts1_dtr_dce1_dsr_dce1
Absolute:
0x43FA_C080
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_cspi2_sclk
20
19
18
17
16
sw_mux_ctl_cspi2_spi_rdy
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_rxd1
sw_mux_ctl_txd1
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-35. Register Description sw_mux_ctl_cspi2_sclk_cspi2_spi_rdy_rxd1_txd1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-21
Signal Multiplexing
Absolute:
0x43FA_C084
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_cspi2_miso
20
19
18
17
16
sw_mux_ctl_cspi2_ss0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_cspi2_ss1
sw_mux_ctl_cspi2_ss2
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-36. Register Description sw_mux_ctl_cspi2_miso_cspi2_ss0_cspi2_ss1_cspi2_ss2
Absolute:
0x43FA_C088
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_cspi1_ss2
20
19
18
17
16
sw_mux_ctl_cspi1_sclk
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_cspi1_spi_rdy
sw_mux_ctl_cspi2_mosi
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-37. Register Description sw_mux_ctl_cspi1_ss2_cspi1_sclk_cspi1_spi_rdy_cspi2_mosi
Absolute:
0x43FA_C08C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_cspi1_mosi
20
19
18
17
16
sw_mux_ctl_cspi1_miso
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_cspi1_ss0
sw_mux_ctl_cspi1_ss1
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-38. Register Description sw_mux_ctl_cspi1_mosi_cspi1_miso_cspi1_ss0_cspi1_ss1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-22
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C090
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_stxd6
20
19
18
17
16
sw_mux_ctl_srxd6
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_sck6
sw_mux_ctl_sfs6
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-39. Register Description sw_mux_ctl_stxd6_srxd6_sck6_sfs6
Absolute:
0x43FA_C094
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_stxd5
20
19
18
17
16
sw_mux_ctl_srxd5
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_sck5
sw_mux_ctl_sfs5
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-40. Register Description sw_mux_ctl_stxd5_srxd5_sck5_sfs5
Absolute:
0x43FA_C098
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_stxd4
20
19
18
17
16
sw_mux_ctl_srxd4
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_sck4
sw_mux_ctl_sfs4
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-41. Register Description sw_mux_ctl_stxd4_srxd4_sck4_sfs4
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-23
Signal Multiplexing
Absolute:
0x43FA_C09C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_stxd3
20
19
18
17
16
sw_mux_ctl_srxd3
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_sck3
sw_mux_ctl_sfs3
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-42. Register Description sw_mux_ctl_stxd3_srxd3_sck3_sfs3
Absolute:
0x43FA_C0A0
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_csi_hsync
20
19
18
17
16
sw_mux_ctl_csi_pixclk
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_i2c_clk
sw_mux_ctl_i2c_dat
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-43. Register Description sw_mux_ctl_csi_hsync_csi_pixclk_i2c_clk_i2c_dat
Absolute:
0x43FA_C0A4
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_csi_d14
20
19
18
17
16
sw_mux_ctl_csi_d15
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_csi_mclk
sw_mux_ctl_csi_vsync
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-44. Register Description sw_mux_ctl_csi_d14_csi_d15_csi_mclk_csi_vsync
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-24
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C0A8
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_csi_d10
20
19
18
17
16
sw_mux_ctl_csi_d11
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_csi_d12
sw_mux_ctl_csi_d13
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-45. Register Description sw_mux_ctl_csi_d10_csi_d11_csi_d12_csi_d13
Absolute:
0x43FA_C0AC
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_csi_d6
20
19
18
17
16
sw_mux_ctl_csi_d7
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_csi_d8
sw_mux_ctl_csi_d9
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-46. Register Description sw_mux_ctl_csi_d6_csi_d7_csi_d8_csi_d9
Absolute:
0x43FA_C0B0
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_m_request
20
19
18
17
16
sw_mux_ctl_m_grant
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_csi_d4
sw_mux_ctl_csi_d5
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-47. Register Description sw_mux_ctl_m_request_m_grant_csi_d4_csi_d5
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-25
Signal Multiplexing
Absolute:
0x43FA_C0B4
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_pc_rst
20
19
18
17
16
sw_mux_ctl_iois16
W
Reset
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_pc_rw_b
sw_mux_ctl_pc_poe
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-48. Register Description sw_mux_ctl_pc_rst_iois16_pc_rw_b_pc_poe
Absolute:
0x43FA_C0B8
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_pc_vs1
20
19
18
17
16
sw_mux_ctl_pc_vs2
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_pc_bvd1
sw_mux_ctl_pc_bvd2
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-49. Register Description sw_mux_ctl_pc_vs1_pc_vs2_pc_bvd1_pc_bvd2
Absolute:
0x43FA_C0BC
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_pc_cd2_b
20
19
18
17
16
sw_mux_ctl_pc_wait_b
W
Reset
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R
sw_mux_ctl_pc_ready
sw_mux_ctl_pc_pwron
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-50. Register Description sw_mux_ctl_pc_cd2_b_pc_wait_b_pc_ready_pc_pwron
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-26
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C0C0
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_d2
20
19
18
17
16
sw_mux_ctl_d1
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_d0
sw_mux_ctl_pc_cd1_b
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-51. Register Description sw_mux_ctl_d2_d1_d0_pc_cd1_b
Absolute:
0x43FA_C0C4
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_d6
20
19
18
17
16
sw_mux_ctl_d5
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_d4
sw_mux_ctl_d3
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-52. Register Description sw_mux_ctl_d6_d5_d4_d3
Absolute:
0x43FA_C0C8
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_d10
20
19
18
17
16
sw_mux_ctl_d9
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_d8
sw_mux_ctl_d7
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-53. Register Description sw_mux_ctl_d10_d9_d8_d7
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-27
Signal Multiplexing
Absolute:
0x43FA_C0CC
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_d14
20
19
18
17
16
sw_mux_ctl_d13
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_d12
sw_mux_ctl_d11
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-54. Register Description sw_mux_ctl_d14_d13_d12_d11
Absolute:
0x43FA_C0D0
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_nfwp_b
20
19
18
17
16
sw_mux_ctl_nfce_b
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_nfrb
sw_mux_ctl_d15
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-55. Register Description sw_mux_ctl_nfwp_b_nfce_b_nfrb_d15
Absolute:
0x43FA_C0D4
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_nfwe_b
20
19
18
17
16
sw_mux_ctl_nfre_b
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_nfale
sw_mux_ctl_nfcle
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-56. Register Description sw_mux_ctl_nfwe_b_nfre_b_nfale_nfcle
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-28
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C0D8
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sdqs0
20
19
18
17
16
sw_mux_ctl_sdqs1
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sdqs2
sw_mux_ctl_sdqs3
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-57. Register Description sw_mux_ctl_sdqs0_sdqs1_sdqs2_sdqs3
Absolute:
0x43FA_C0DC
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sdcke0
20
19
18
17
16
sw_mux_ctl_sdcke1
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
R
sw_mux_ctl_sdclk*
Reserved
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
Figure 4-58. Register Description sw_mux_ctl_sdcke0_sdcke1_sdclk_sdclk_b
*Bits 8–14 control the differential output pair SDCLK and SDCLK.
Absolute:
0x43FA_C0E0
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_rw
20
19
18
17
16
sw_mux_ctl_ras
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_cas
sw_mux_ctl_sdwe
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-59. Register Description sw_mux_ctl_rw_ras_cas_sdwe
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-29
Signal Multiplexing
Absolute:
0x43FA_C0E4
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_cs5
20
19
18
17
16
sw_mux_ctl_ecb
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_lba
sw_mux_ctl_bclk
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-60. Register Description sw_mux_ctl_cs5_ecb_lba_bclk
Absolute:
0x43FA_C0E8
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_cs1
20
19
18
17
16
sw_mux_ctl_cs2
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_cs3
sw_mux_ctl_cs4
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-61. Register Description sw_mux_ctl_cs1_cs2_cs3_cs4
Absolute:
0x43FA_C0EC
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_eb0
20
19
18
17
16
sw_mux_ctl_eb1
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_oe
sw_mux_ctl_cs0
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-62. Register Description sw_mux_ctl_eb0_eb1_oe_cs0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-30
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C0F0
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_dqm0
20
19
18
17
16
sw_mux_ctl_dqm1
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_dqm2
sw_mux_ctl_dqm3
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-63. Register Description sw_mux_ctl_dqm0_dqm1_dqm2_dqm3
Absolute:
0x43FA_C0F4
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd28
20
19
18
17
16
sw_mux_ctl_sd29
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sd30
sw_mux_ctl_sd31
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-64. Register Description sw_mux_ctl_sd28_sd29_sd30_sd31
Absolute:
0x43FA_C0F8
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd24
20
19
18
17
16
sw_mux_ctl_sd25
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sd26
sw_mux_ctl_sd27
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-65. Register Description sw_mux_ctl_sd24_sd25_sd26_sd27
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-31
Signal Multiplexing
Absolute:
0x43FA_C0FC
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd20
20
19
18
17
16
sw_mux_ctl_sd21
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sd22
sw_mux_ctl_sd23
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-66. Register Description sw_mux_ctl_sd20_sd21_sd22_sd23
Absolute:
0x43FA_C100
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd16
20
19
18
17
16
sw_mux_ctl_sd17
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sd18
sw_mux_ctl_sd19
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-67. Register Description sw_mux_ctl_sd16_sd17_sd18_sd19
Absolute:
0x43FA_C104
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd12
20
19
18
17
16
sw_mux_ctl_sd13
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sd14
sw_mux_ctl_sd15
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-68. Register Description sw_mux_ctl_sd12_sd13_sd14_sd15
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-32
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C108
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd8
20
19
18
17
16
sw_mux_ctl_sd9
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sd10
sw_mux_ctl_sd11
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-69. Register Description sw_mux_ctl_sd8_sd9_sd10_sd11
Absolute:
0x43FA_C10C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd4
20
19
18
17
16
sw_mux_ctl_sd5
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sd6
sw_mux_ctl_sd7
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-70. Register Description sw_mux_ctl_sd4_sd5_sd6_sd7
Absolute:
0x43FA_C110
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_sd0
20
19
18
17
16
sw_mux_ctl_sd1
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sd2
sw_mux_ctl_sd3
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-71. Register Description sw_mux_ctl_sd0_sd1_sd2_sd3
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-33
Signal Multiplexing
Absolute:
0x43FA_C114
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_a24
20
19
18
17
16
sw_mux_ctl_a25
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_sdba1
sw_mux_ctl_sdba0
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-72. Register Description sw_mux_ctl_a24_a25_sdba1_sdba0
Absolute:
0x43FA_C118
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_a20
20
19
18
17
16
sw_mux_ctl_a21
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_a22
sw_mux_ctl_a23
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-73. Register Description sw_mux_ctl_a20_a21_a22_a23
Absolute:
0x43FA_C11C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_a16
20
19
18
17
16
sw_mux_ctl_a17
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_a18
sw_mux_ctl_a19
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-74. Register Description sw_mux_ctl_a16_a17_a18_a19
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-34
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C120
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_a12
20
19
18
17
16
sw_mux_ctl_a13
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_a14
sw_mux_ctl_a15
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-75. Register Description sw_mux_ctl_a12_a13_a14_a15
Absolute:
0x43FA_C124
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_a9
20
19
18
17
16
sw_mux_ctl_a10
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_ma10
sw_mux_ctl_a11
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-76. Register Description sw_mux_ctl_a9_a10_ma10_a11
Absolute:
0x43FA_C128
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_a5
20
19
18
17
16
sw_mux_ctl_a6
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_a7
sw_mux_ctl_a8
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-77. Register Description sw_mux_ctl_a5_a6_a7_a8
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-35
Signal Multiplexing
Absolute:
0x43FA_C12C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_a1
20
19
18
17
16
sw_mux_ctl_a2
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_a3
sw_mux_ctl_a4
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-78. Register Description sw_mux_ctl_a1_a2_a3_a4
Absolute:
0x43FA_C130
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_dvfs1
20
19
18
17
16
sw_mux_ctl_vpg0
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_vpg1
sw_mux_ctl_a0
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-79. Register Description sw_mux_ctl_dvfs1_vpg0_vpg1_a0
Absolute:
0x43FA_C134
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_ckil
20
19
18
17
16
sw_mux_ctl_power_fail
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_vstby
sw_mux_ctl_dvfs0
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-80. Register Description sw_mux_ctl_ckil_power_fail_vstby_dvfs0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-36
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C138
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_boot_mode1
20
19
18
17
16
sw_mux_ctl_boot_mode2
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_boot_mode3
sw_mux_ctl_boot_mode4
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-81. Register Description sw_mux_ctl_boot_mode1_boot_mode2_boot_mode3_boot_mode4
Absolute:
0x43FA_C13C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_reset_in_b
20
19
18
17
16
sw_mux_ctl_por_b
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_clko
sw_mux_ctl_boot_mode0
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
Figure 4-82. Register Description sw_mux_ctl_reset_in_b_por_b_clko_boot_mode0
Absolute:
0x43FA_C140
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_stx0
20
19
18
17
16
sw_mux_ctl_srx0
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
R
sw_mux_ctl_simpd0
sw_mux_ctl_ckih
W
Reset
0
0
0
0
0
0
0
1
0
0
0
1
0
0
Figure 4-83. Register Description sw_mux_ctl_stx0_srx0_simpd0_ckih
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-37
Signal Multiplexing
Absolute:
0x43FA_C144
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_gpio3_1
20
19
18
17
16
sw_mux_ctl_sclk0
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_srst0
sw_mux_ctl_sven0
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-84. Register Description sw_mux_ctl_gpio3_1_sclk0_srst0_sven0
Absolute:
0x43FA_C148
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_gpio1_4
20
19
18
17
16
sw_mux_ctl_gpio1_5
W
Reset
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_gpio1_6
sw_mux_ctl_gpio3_0
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-85. Register Description sw_mux_ctl_gpio1_4_gpio1_5_gpio1_6_gpio3_0
Absolute:
0x43FA_C14C
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_gpio1_0
20
19
18
17
16
sw_mux_ctl_gpio1_1
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_gpio1_2
sw_mux_ctl_gpio1_3
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Figure 4-86. Register Description sw_mux_ctl_gpio1_0_gpio1_1_gpio1_2_gpio1_3
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-38
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C150
31
30
Access: User Read/Write
29
R
28
27
26
25
24
23
22
21
sw_mux_ctl_capture
20
19
18
17
16
sw_mux_ctl_compare
W
Reset
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
R
sw_mux_ctl_watchdog_rst
sw_mux_ctl_pwmo
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-87. Register Description sw_mux_ctl_capture_compare_watchdog_rst_pwmo
4.3.5
Functional Multiplexing Modes
The IOMUX has four configurable modes: Hardware, Functional, Alternate, and GPIO. Each mode has a
priority. Setting an I/O with a higher priority overrides the previous mode setting. Likewise, if a priority
setting being applied is a lower priority than the priority of the current mode, the new mode setting is
ignored. Table 4-7 shows the priority for each of the modes.
Table 4-7. Multiplexing Priorities
Priority
Mode
1
Hardware mode 2
2
Hardware mode 1
3
Alternate mode 2
4
Alternate mode 1
5
Functional mode
The four multiplexing modes are defined in the following sections.
4.3.5.1
Hardware Mode
This mode is used to set multiple sets of I/O signals by setting or clearing a single bit in the General
Purpose Register (GPR).
4.3.5.2
Functional Mode
This is the primary mode of the I/O line. Like a default setting, the primary mode routes the signals for
which it is named. For example, the functional mode of the RXD1 I/O line routes the RXD signal of
UART1 to the external contact of the IC.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-39
Signal Multiplexing
4.3.5.3
Alternate Modes
Each I/O has software-programmable bits that can select between the functional mode and other I/O
muxing options. Each I/O signal has the potential of six alternate modes which are individually defined by
software. For example, using an alternate mode allows the RXD signal to be routed to RI_DCE1 I/O. The
six alternate mode options are as follows:
• Alternate Mode 1–2 (I/O)
• Alternate Modes 3–6 (output only)
4.3.5.4
GPIO Mode
In GPIO mode, configuration of the I/O is controlled by the GPIO module. For example, in the GPIO
column of Table A-1, MCU indicates MCU1_7, which is associated with GPIO1 bit 7.
4.3.6
ATA Routing Options
Table 4-8 lists seven signal routing options for the ATA signals. The primary purpose of this table is to
provide a summary of the seven most commonly used routing scenarios of the ATA signals that are
controlled by the hardware modes.
Table 4-8. ATA Signal Routing Options using Hardware Modes
Scenario A
Scenario B
Scenario C
Scenario D
Scenario E
Scenario F
Scenario G
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
PWM
HW1;
GPR[3];
IORDY
HW1;
GPR[3];
IORDY
HW1;
GPR[3];
IORDY
HW1;
GPR[3];
IORDY
HW1;
GPR[3];
IORDY
HW1;
GPR[3];
IORDY
HW1;
GPR[3];
IORDY
HW1;
GPR[9];
DATA[14,15]
HW1;
GPR[9];
DATA[14,15]
–
–
–
Timer
HW1;
GPR[9];
DATA[14,15]
HW1;
GPR[9];
DATA[14,15]
HW1;
GPR[5];
DATA[7:13]
–
–
–
HW2;
GPR[6];
DA0-2,
DMARQ,
INTRQ,
BUFFER_EN
HW2;
GPR[6];
DA0-2,
DMARQ,
INTRQ,
BUFFER_EN
–
IPU
(CSI)
HW1;
GPR[7];
DATA[0:13]
HW1;
GPR[7];
DATA[0:13]
–
–
HW1;
GPR[7];
DATA[0:13]
–
–
–
–
–
HW1;
GPR[8];
DATA[7:10]
–
AudioPort3
HW1;
GPR[8];
DATA[7:10]
HW1;
GPR[8];
DATA[7:10]
–
–
–
HW1;
GPR[8];
DATA[11:13]
–
AudioPort6
HW1;
GPR[8];
DATA[11:13]
HW1;
GPR[8];
DATA[11:13]
Group
EMI
(NANDFC)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-40
Freescale Semiconductor
Signal Multiplexing
Table 4-8. ATA Signal Routing Options using Hardware Modes (continued)
Group
Scenario A
Scenario B
Scenario C
Scenario D
Scenario E
Scenario F
Scenario G
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
MUX Mode;
GPR Bit;
ATA Signals
HW1;
GPR[26];
DA0-2,
DMARQ,
INTRQ,
BUFFER_EN
–
–
–
–
–
HW1;
GPR[9];
DATA[0:6]
–
HW2;
GPR[10];
DA0-2,
DMARQ,
INTRQ,
BUFFER_EN
–
HW1;
GPR[9];
DATA[0:6]
HW1;
GPR[9];
DATA[0:6]
HW1;
GPR[4];
DA0-2,
DMARQ,
INTRQ,
BUFFER_EN
–
–
–
HW1;
GPR[4];
DA0-2,
DMARQ,
INTRQ,
BUFFER_EN
–
Keypad
CSPI1
USBH2
HW1;
GPR[9];
DATA[0:6]
HW1;
GPR[4];
DA0-2,
DMARQ,
INTRQ,
BUFFER_EN
–
–
–
HW1;
GPR[7];
DATA[14,15]
HW1;
GPR[7];
DATA[14,15]
HW1;
GPR[7];
DATA[14,15]
–
–
Functional;
(no GPR bit);
DIOR, DIOW,
CS0, CS1,
RESET_B,
DMACK
Functional;
(no GPR bit);
DIOR, DIOW,
CS0, CS1,
RESET_B,
DMACK
Functional;
(no GPR bit);
DIOR, DIOW,
CS0, CS1,
RESET_B,
DMACK
Functional;
(no GPR bit);
DIOR, DIOW,
CS0, CS1,
RESET_B,
DMACK
Functional;
(no GPR bit);
DIOR, DIOW,
CS0, CS1,
RESET_B,
DMACK
Functional;
(no GPR bit);
DIOR, DIOW,
CS0, CS1,
RESET_B,
DMACK
Functional;
(no GPR bit);
DIOR, DIOW,
CS0, CS1,
RESET_B,
DMACK
I2C
ATA
See Table 4-8 for (Contact) Group, (Functional) MUX Modes, and associated Contact Signal list. See Table 4-5 for GPR bit and MUX Mode
information.
A dash indicates that a Contact Group is not used for a particular Scenario. Therefore, the Group may be used for other signal multiplexing.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-41
Signal Multiplexing
4.3.7
Software Pad Control Register (SW_PAD_CTL)
The SW_PAD_CTL registers control the characteristics of the I/O lines. Figure 4-88 provides the
register’s field descriptions; Table 4-9 lists the control by bit.
31
30
0
0
ipp_pke
ipp_pue
ipp_pus0
ipp_pus1
ipp_hys
ipp_ode
ipp_dse1
ipp_dse0
ipp_sre
loopback
ipp_pke
ipp_pue
ipp_pus0
R
Access: User Read/Write
loopback
0x43FA_C154
to
0x43FA_C308
29
—
—
9
8
7
6
5
4
3
2
1
0
9
8
7
6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
26
25
24
23
22
21
20
19
18
17
16
SW_PAD_CTL_IO2
W
ipp_ode
ipp_dse1
ipp_dse0
ipp_sre
loopback
ipp_pke
ipp_pue
ipp_pus0
ipp_pus1
ipp_hys
ipp_ode
ipp_dse1
ipp_dse0
ipp_sre
SW_PAD_CTL_IO1
ipp_hys
SW_PAD_CTL_IO2
ipp_pus1
R
27
SW_PAD_CTL_IO3
W
Field bits
28
Field bits
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
Figure 4-88. SW_PAD_CTL
Table 4-9. SW_PAD_CTL Bit Descriptions
Register Bit
Bit Name
Description
SW_PAD_CTL[31:30]
—
Unused
SW_PAD_CTL[29]
SW_PAD_CTL[19]
SW_PAD_CTL[9]
Loopback
Used to loop back the logic level at the BGA ball to a module input. Used when
programming an output value to verify the value is achieved at I/O
0 Disable
1 Enable
SW_PAD_CTL[28:27]
SW_PAD_CTL[18:17]
SW_PAD_CTL[8:7]
ipp_pke
ipp_pue
Pull-up, pull-down, and keeper
00 Disable pull-up/down, and keeper
01 Disable pull-up/down, and keeper
10 Enable keeper
11 Enable pull-up or pull-down
SW_PAD_CTL[26:25]
SW_PAD_CTL[16:15]
SW_PAD_CTL[6:5]
ipp_pus0
ipp_pus1
Size of pull resistor and up/down control
00 100 kΩ pull-down
01 100 kΩ pull-up
10 47 kΩ pull-up (Not used in i.MX31 and i.MX31L.)
11 22 kΩ pull-up (Not used in i.MX31 and i.MX31L.)
SW_PAD_CTL[24]
SW_PAD_CTL[14]
SW_PAD_CTL[4]
ipp_hys
Hysteresis control
0 Standard input
1 Input with hysteresis, Schmitt trigger engaged
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-42
Freescale Semiconductor
Signal Multiplexing
Table 4-9. SW_PAD_CTL Bit Descriptions (continued)
Register Bit
Bit Name
Description
SW_PAD_CTL[23]
SW_PAD_CTL[13]
SW_PAD_CTL[3]
ipp_ode
Open-drain control
0 Standard CMOS output, push-pull
1 Output is open-drain (requires pull-up)
SW_PAD_CTL[22:21]
SW_PAD_CTL[12:11]
SW_PAD_CTL[2:1]
ipp_dse1
ipp_dse0
Output drive strength
00 Standard (std)
01 High
10 Max
11 Max
SW_PAD_CTL[20]
SW_PAD_CTL[10]
SW_PAD_CTL[0]
ipp_sre
Slew rate control
0 Slow
1 Fast
4.3.8
Register Descriptions for SW Pad Control (SW_PAD_CTL)
Figure 4-89 through Figure 4-198 show the sw_pad_ctl registers. The I/O settings shown in Table A-2
enable the user to select the characteristics of each I/O line by configuring the appropriate SW_PAD_CTL
registers.
Absolute:
0x43FA_C154
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_ttm_pad
18
17
16
Reserved
W
Reset
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
Reserved
Reserved
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-89. Register Description sw_pad_ctl_ttm_pad__x__x
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-43
Signal Multiplexing
Absolute:
0x43FA_C158
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_cspi3_miso
19
18
17
16
sw_pad_ctl_cspi3_sclk
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_cspi3_sclk
sw_pad_ctl_cspi3_spi_rdy
W
Reset
1
1
0
0
0
0
0
1
1
0
1
0
0
Figure 4-90. Register Description sw_pad_ctl_cspi3_miso_cspi3_sclk_cspi3_spi_rdy
Absolute:
0x43FA_C15C
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_ce_control
18
17
16
sw_pad_ctl_clkss
W
Reset
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_clkss
sw_pad_ctl_cspi3_mosi
W
Reset
1
0
0
0
0
1
0
1
1
0
1
0
0
Figure 4-91. Register Description sw_pad_ctl_ce_control_clkss_cspi3_mosi
Absolute:
0x43FA_C160
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_ata_diow
19
18
17
16
sw_pad_ctl_ata_dmack
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_ata_dmack
sw_pad_ctl_ata_reset_b
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-92. Register Description sw_pad_ctl_ata_diow_ata_dmack_ata_reset_b
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-44
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C164
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_ata_cs0
18
17
16
sw_pad_ctl_ata_cs1
W
Reset
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_ata_cs1
sw_pad_ctl_ata_dior
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-93. Register Description sw_pad_ctl_ata_cs0_ata_cs1_ata_dior
Absolute:
0x43FA_C168
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_sd1_data1
19
18
17
16
sw_pad_ctl_sd1_data2
W
Reset
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
R
sw_pad_ctl_sd1_data2
sw_pad_ctl_sd1_data3
W
Reset
1
0
0
0
0
1
0
0
1
0
0
0
0
Figure 4-94. Register Description sw_pad_ctl_sd1_data1_sd1_data2_sd1_data3
Absolute:
0x43FA_C16C
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_sd1_cmd
19
18
17
16
sw_pad_ctl_sd1_clk
W
Reset
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
R
sw_pad_ctl_sd1_clk
sw_pad_ctl_sd1_data0
W
Reset
1
0
0
0
0
1
0
0
1
0
1
0
0
Figure 4-95. Register Description sw_pad_ctl_sd1_cmd_sd1_clk_sd1_data0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-45
Signal Multiplexing
Absolute:
0x43FA_C170
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_d3_rev
18
17
16
sw_pad_ctl_d3_cls
W
Reset
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_d3_cls
sw_pad_ctl_d3_spl
W
Reset
1
0
0
0
1
1
0
0
1
0
1
0
Figure 4-96. Register Description sw_pad_ctl_d3_rev_d3_cls_d3_spl
Absolute:
0x43FA_C174
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_read
18
17
16
sw_pad_ctl_vsync3
W
Reset
0
0
0
0
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
R
sw_pad_ctl_vsync3
sw_pad_ctl_contrast
W
Reset
1
0
0
0
1
1
0
0
1
0
1
0
0
Figure 4-97. Register Description sw_pad_ctl_read_vsync3_contrast
Absolute:
0x43FA_C178
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_ser_rs
18
17
16
sw_pad_ctl_par_rs
W
Reset
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_par_rs
sw_pad_ctl_write
W
Reset
1
0
0
0
1
1
0
0
1
0
1
0
Figure 4-98. Register Description sw_pad_ctl_ser_rs_par_rs_write
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-46
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C17C
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
18
sw_pad_ctl_sd_d_clk
17
16
sw_pad_ctl_lcs0
W
Reset
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_lcs0
sw_pad_ctl_lcs1
W
Reset
1
0
0
0
1
1
0
0
1
0
1
0
Figure 4-99. Register Description sw_pad_ctl_sd_d_clk_lcs0_lcs1
Absolute:
0x43FA_C180
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_drdy0
18
17
16
sw_pad_ctl_sd_d_i
W
Reset
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
R
sw_pad_ctl_sd_d_i
sw_pad_ctl_sd_d_io
W
Reset
1
0
0
0
1
1
0
0
1
0
1
0
0
Figure 4-100. Register Description sw_pad_ctl_drdy0_sd_d_i_sd_d_io
Absolute:
0x43FA_C184
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_vsync0
18
17
16
sw_pad_ctl_hsync
W
Reset
0
0
0
1
1
0
1
0
0
0
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_hsync
sw_pad_ctl_fpshift
W
Reset
1
0
0
0
1
1
0
0
1
0
1
0
Figure 4-101. Register Description sw_pad_ctl_vsync0_hsync_fpshift
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-47
Signal Multiplexing
Absolute:
0x43FA_C188
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_ld15
18
17
16
sw_pad_ctl_ld16
W
Reset
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_ld16
sw_pad_ctl_ld17
W
Reset
1
0
0
0
1
1
0
1
1
0
1
0
Figure 4-102. Register Description sw_pad_ctl_ld15_ld16_ld17
Absolute:
0x43FA_C18C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_ld12
18
17
16
sw_pad_ctl_ld13
W
Reset
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_ld13
sw_pad_ctl_ld14
W
Reset
1
0
0
0
1
1
0
1
1
0
1
0
Figure 4-103. Register Description sw_pad_ctl_ld12_ld13_ld14
Absolute:
0x43FA_C190
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_ld9
18
17
16
sw_pad_ctl_ld10
W
Reset
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_ld10
sw_pad_ctl_ld11
W
Reset
1
0
0
0
1
1
0
1
1
0
1
0
Figure 4-104. Register Description sw_pad_ctl_ld9_ld10_ld11
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-48
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C194
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_ld6
18
17
16
sw_pad_ctl_ld7
W
Reset
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_ld7
sw_pad_ctl_ld8
W
Reset
1
0
0
0
1
1
0
1
1
0
1
0
Figure 4-105. Register Description sw_pad_ctl_ld6_ld7_ld8
Absolute:
0x43FA_C198
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_ld3
18
17
16
sw_pad_ctl_ld4
W
Reset
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_ld4
sw_pad_ctl_ld5
W
Reset
1
0
0
0
1
1
0
1
1
0
1
0
Figure 4-106. Register Description sw_pad_ctl_ld3_ld4_ld5
Absolute:
0x43FA_C19C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_ld0
18
17
16
sw_pad_ctl_ld1
W
Reset
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_ld1
sw_pad_ctl_ld2
W
Reset
1
0
0
0
1
1
0
1
1
0
1
0
Figure 4-107. Register Description sw_pad_ctl_ld0_ld1_ld2
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-49
Signal Multiplexing
Absolute:
0x43FA_C1A0
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_usbh2_nxt
19
18
17
16
sw_pad_ctl_usbh2_data0
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_usbh2_data0
sw_pad_ctl_usbh2_data1
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-108. Register Description sw_pad_ctl_usbh2_nxt_usbh2_data0_usbh2_data1
Absolute:
0x43FA_C1A4
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_usbh2_clk
19
18
17
16
sw_pad_ctl_usbh2_dir
W
Reset
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_usbh2_dir
sw_pad_ctl_usbh2_stp
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-109. Register Description sw_pad_ctl_usbh2_clk_usbh2_dir_usbh2_stp
Absolute:
0x43FA_C1A8
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_usbotg_data5
19
18
17
16
sw_pad_ctl_usbotg_data6
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_usbotg_data6
sw_pad_ctl_usbotg_data7
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-110. Register Description sw_pad_ctl_usbotg_data5_usbotg_data6_usbotg_data7
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-50
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C1AC
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_usbotg_data2
19
18
17
16
sw_pad_ctl_usbotg_data3
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_usbotg_data3
sw_pad_ctl_usbotg_data4
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-111. Register Description sw_pad_ctl_usbotg_data2_usbotg_data3_usbotg_data4
Absolute:
0x43FA_C1B0
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_usbotg_nxt
19
18
17
16
sw_pad_ctl_usbotg_data0
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_usbotg_data0
sw_pad_ctl_usbotg_data1
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-112. Register Description sw_pad_ctl_usbotg_nxt_usbotg_data0_usbotg_data1
Absolute:
0x43FA_C1B4
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_usbotg_clk
19
18
17
16
sw_pad_ctl_usbotg_dir
W
Reset
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_usbotg_dir
sw_pad_ctl_usbotg_stp
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-113. Register Description sw_pad_ctl_usbotg_clk_usbotg_dir_usbotg_stp
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-51
Signal Multiplexing
Absolute:
0x43FA_C1B8
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_usb_pwr
18
17
16
sw_pad_ctl_usb_oc
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_usb_oc
sw_pad_ctl_usb_byp
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-114. Register Description sw_pad_ctl_usb_pwr_usb_oc_usb_byp
Absolute:
0x43FA_C1BC
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_trstb
18
17
16
sw_pad_ctl_de_b
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_de_b
sw_pad_ctl_sjc_mod
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-115. Register Description sw_pad_ctl_trstb_de_b_sjc_mod
Absolute:
0x43FA_C1C0
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_tms
18
17
16
sw_pad_ctl_tdi
W
Reset
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_tdi
sw_pad_ctl_tdo
W
Reset
1
1
0
0
0
0
0
0
1
0
1
0
Figure 4-116. Register Description sw_pad_ctl_tms_tdi_tdo
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-52
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C1C4
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_key_col7
18
17
16
sw_pad_ctl_rtck
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_rtck
sw_pad_ctl_tck
W
Reset
0
0
0
0
1
1
0
1
1
0
0
1
Figure 4-117. Register Description sw_pad_ctl_key_col7_rtck_tck
Absolute:
0x43FA_C1C8
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_key_col4
19
18
17
16
sw_pad_ctl_key_col5
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_key_col5
sw_pad_ctl_key_col6
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-118. Register Description sw_pad_ctl_key_col4_key_col5_key_col6
Absolute:
0x43FA_C1CC
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_key_col1
19
18
17
16
sw_pad_ctl_key_col2
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_key_col2
sw_pad_ctl_key_col3
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-119. Register Description sw_pad_ctl_key_col1_key_col2_key_col3
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-53
Signal Multiplexing
Absolute:
0x43FA_C1D0
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_key_row6
19
18
17
16
sw_pad_ctl_key_row7
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_key_row7
sw_pad_ctl_key_col0
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-120. Register Description sw_pad_ctl_key_row6_key_row7_key_col0
Absolute:
0x43FA_C1D4
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_key_row3
19
18
17
16
sw_pad_ctl_key_row4
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_key_row4
sw_pad_ctl_key_row5
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-121. Register Description sw_pad_ctl_key_row3_key_row4_key_row5
Absolute:
0x43FA_C1D8
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_key_row0
19
18
17
16
sw_pad_ctl_key_row1
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_key_row1
sw_pad_ctl_key_row2
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-122. Register Description sw_pad_ctl_key_row0_key_row1_key_row2
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-54
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C1DC
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_rts2
18
17
16
sw_pad_ctl_cts2
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_cts2
sw_pad_ctl_batt_line
W
Reset
1
0
0
0
0
0
1
1
1
0
1
0
1
Figure 4-123. Register Description sw_pad_ctl_rts2_cts2_batt_line
Absolute:
0x43FA_C1E0
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_dtr_dce2
18
17
16
sw_pad_ctl_rxd2
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_rxd2
sw_pad_ctl_txd2
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
Figure 4-124. Register Description sw_pad_ctl_dtr_dce2_rxd2_txd2
Absolute:
0x43FA_C1E4
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_dsr_dte1
18
17
16
sw_pad_ctl_ri_dte1
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_ri_dte1
sw_pad_ctl_dcd_dte1
W
Reset
1
1
0
0
0
0
0
1
1
0
1
0
0
Figure 4-125. Register Description sw_pad_ctl_dsr_dte1_ri_dte1_dcd_dte1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-55
Signal Multiplexing
Absolute:
0x43FA_C1E8
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_ri_dce1
19
18
17
16
sw_pad_ctl_dcd_dce1
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_dcd_dce1
sw_pad_ctl_dtr_dte1
W
Reset
1
0
0
0
0
0
0
1
1
0
1
1
0
Figure 4-126. Register Description sw_pad_ctl_ri_dce1_dcd_dce1_dtr_dte1
Absolute:
0x43FA_C1EC
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_cts1
18
17
16
sw_pad_ctl_dtr_dce1
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_dtr_dce1
sw_pad_ctl_dsr_dce1
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-127. Register Description sw_pad_ctl_cts1_dtr_dce1_dsr_dce1
Absolute:
0x43FA_C1F0
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_rxd1
18
17
16
sw_pad_ctl_txd1
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_txd1
sw_pad_ctl_rts1
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
Figure 4-128. Register Description sw_pad_ctl_rxd1_txd1_rts1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-56
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C1F4
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_cspi2_ss2
19
18
17
16
sw_pad_ctl_cspi2_sclk
W
Reset
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_cspi2_sclk
sw_pad_ctl_cspi2_spi_rdy
W
Reset
1
1
0
0
0
0
0
1
1
0
1
0
0
Figure 4-129. Register Description sw_pad_ctl_cspi2_ss2_cspi2_sclk_cspi2_spi_rdy
Absolute:
0x43FA_C1F8
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_cspi2_miso
19
18
17
16
sw_pad_ctl_cspi2_ss0
W
Reset
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_cspi2_ss0
sw_pad_ctl_cspi2_ss1
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-130. Register Description sw_pad_ctl_cspi2_miso_cspi2_ss0_cspi2_ss1
Absolute:
0x43FA_C1FC
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_cspi1_sclk
19
18
17
16
sw_pad_ctl_cspi1_spi_rdy
W
Reset
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_cspi1_spi_rdy
sw_pad_ctl_cspi2_mosi
W
Reset
1
0
0
0
0
0
0
1
1
0
1
1
0
Figure 4-131. Register Description sw_pad_ctl_cspi1_sclk_cspi1_spi_rdy_cspi2_mosi
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-57
Signal Multiplexing
Absolute:
0x43FA_C200
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_cspi1_ss0
19
18
17
16
sw_pad_ctl_cspi1_ss1
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_cspi1_ss1
sw_pad_ctl_cspi1_ss2
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-132. Register Description sw_pad_ctl_cspi1_ss0_cspi1_ss1_cspi1_ss2
Absolute:
0x43FA_C204
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
sw_pad_ctl_sfs6
19
18
17
16
sw_pad_ctl_cspi1_mosi
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_cspi1_mosi
sw_pad_ctl_cspi1_miso
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-133. Register Description sw_pad_ctl_sfs6_cspi1_mosi_cspi1_miso
Absolute:
0x43FA_C208
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_stxd6
18
17
16
sw_pad_ctl_srxd6
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_srxd6
sw_pad_ctl_sck6
W
Reset
1
0
0
0
0
0
0
1
1
0
1
1
Figure 4-134. Register Description sw_pad_ctl_stxd6_srxd6_sck6
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-58
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C20C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_srxd5
18
17
16
sw_pad_ctl_sck5
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_sck5
sw_pad_ctl_sfs5
W
Reset
1
1
0
0
0
0
0
1
1
0
1
0
Figure 4-135. Register Description sw_pad_ctl_srxd5_sck5_sfs5
Absolute:
0x43FA_C210
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sck4
18
17
16
sw_pad_ctl_sfs4
W
Reset
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_sfs4
sw_pad_ctl_stxd5
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
Figure 4-136. Register Description sw_pad_ctl_sck4_sfs4_stxd5
Absolute:
0x43FA_C214
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sfs3
18
17
16
sw_pad_ctl_stxd4
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_stxd4
sw_pad_ctl_srxd4
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
Figure 4-137. Register Description sw_pad_ctl_sfs3_stxd4_srxd4
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-59
Signal Multiplexing
Absolute:
0x43FA_C218
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_stxd3
18
17
16
sw_pad_ctl_srxd3
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_srxd3
sw_pad_ctl_sck3
W
Reset
1
0
0
0
0
0
0
1
1
0
1
1
Figure 4-138. Register Description sw_pad_ctl_stxd3_srxd3_sck3
Absolute:
0x43FA_C21C
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_csi_pixclk
18
17
16
sw_pad_ctl_i2c_clk
W
Reset
0
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_i2c_clk
sw_pad_ctl_i2c_dat
W
Reset
1
1
0
0
0
0
0
1
1
0
1
1
0
Figure 4-139. Register Description sw_pad_ctl_csi_pixclk_i2c_clk_i2c_dat
Absolute:
0x43FA_C220
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_csi_mclk
19
18
17
16
sw_pad_ctl_csi_vsync
W
Reset
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
R
sw_pad_ctl_csi_vsync
sw_pad_ctl_csi_hsync
W
Reset
1
0
0
0
1
1
0
1
0
0
1
0
0
Figure 4-140. Register Description sw_pad_ctl_csi_mclk_csi_vsync_csi_hsync
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-60
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C224
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_csi_d13
18
17
16
sw_pad_ctl_csi_d14
W
Reset
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
R
sw_pad_ctl_csi_d14
sw_pad_ctl_csi_d15
W
Reset
1
0
0
0
1
1
0
1
0
0
1
0
0
Figure 4-141. Register Description sw_pad_ctl_csi_d13_csi_d14_csi_d15
Absolute:
0x43FA_C228
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_csi_d10
18
17
16
sw_pad_ctl_csi_d11
W
Reset
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
R
sw_pad_ctl_csi_d11
sw_pad_ctl_csi_d12
W
Reset
1
0
0
0
1
1
0
1
0
0
1
0
0
Figure 4-142. Register Description sw_pad_ctl_csi_d10_csi_d11_csi_d12
Absolute:
0x43FA_C22C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_csi_d7
18
17
16
sw_pad_ctl_csi_d8
W
Reset
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_csi_d8
sw_pad_ctl_csi_d9
W
Reset
1
0
0
0
1
1
0
1
0
0
1
0
Figure 4-143. Register Description sw_pad_ctl_csi_d7_csi_d8_csi_d9
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-61
Signal Multiplexing
Absolute:
0x43FA_C230
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_csi_d4
18
17
16
sw_pad_ctl_csi_d5
W
Reset
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_csi_d5
sw_pad_ctl_csi_d6
W
Reset
1
0
0
0
1
1
0
1
0
0
1
0
Figure 4-144. Register Description sw_pad_ctl_csi_d4_csi_d5_csi_d6
Absolute:
0x43FA_C234
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_pc_poe
19
18
17
16
sw_pad_ctl_m_request
W
Reset
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_m_request
sw_pad_ctl_m_grant
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-145. Register Description sw_pad_ctl_pc_poe_m_request_m_grant
Absolute:
0x43FA_C238
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_pc_rst
18
17
16
sw_pad_ctl_iois16
W
Reset
0
0
0
1
1
0
1
0
0
0
1
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
R
sw_pad_ctl_iois16
sw_pad_ctl_pc_rw_b
W
Reset
1
0
0
0
1
0
0
1
1
0
1
0
0
Figure 4-146. Register Description sw_pad_ctl_pc_rst_iois16_pc_rw_b
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-62
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C23C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_pc_vs2
18
17
16
sw_pad_ctl_pc_bvd1
W
Reset
0
0
0
1
1
0
1
0
0
0
1
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
R
sw_pad_ctl_pc_bvd1
sw_pad_ctl_pc_bvd2
W
Reset
1
0
0
0
1
0
0
1
1
0
1
0
0
Figure 4-147. Register Description sw_pad_ctl_pc_vs2_pc_bvd1_pc_bvd2
Absolute:
0x43FA_C240
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_pc_ready
19
18
17
16
sw_pad_ctl_pc_pwron
W
Reset
0
0
0
1
1
0
1
0
0
0
1
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
R
sw_pad_ctl_pc_pwron
sw_pad_ctl_pc_vs1
W
Reset
0
0
0
0
1
0
0
1
1
0
1
0
Figure 4-148. Register Description sw_pad_ctl_pc_ready_pc_pwron_pc_vs1
Absolute:
0x43FA_C244
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_pc_cd1_b
19
18
17
16
sw_pad_ctl_pc_cd2_b
W
Reset
0
0
0
1
1
0
1
0
0
0
1
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
R
sw_pad_ctl_pc_cd2_b
sw_pad_ctl_pc_wait_b
W
Reset
1
0
0
0
1
0
0
1
1
0
1
0
0
Figure 4-149. Register Description sw_pad_ctl_pc_cd1_b_pc_cd2_b_pc_wait_b
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-63
Signal Multiplexing
Absolute:
0x43FA_C248
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_d2
18
17
16
sw_pad_ctl_d1
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_d1
sw_pad_ctl_d0
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-150. Register Description sw_pad_ctl_d2_d1_d0
Absolute:
0x43FA_C24C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_d5
18
17
16
sw_pad_ctl_d4
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_d4
sw_pad_ctl_d3
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-151. Register Description sw_pad_ctl_d5_d4_d3
Absolute:
0x43FA_C250
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_d8
18
17
16
sw_pad_ctl_d7
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_d7
sw_pad_ctl_d6
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-152. Register Description sw_pad_ctl_d8_d7_d6
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-64
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C254
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_d11
18
17
16
sw_pad_ctl_d10
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_d10
sw_pad_ctl_d9
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-153. Register Description sw_pad_ctl_d11_d10_d9
Absolute:
0x43FA_C258
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_d14
18
17
16
sw_pad_ctl_d13
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_d13
sw_pad_ctl_d12
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-154. Register Description sw_pad_ctl_d14_d13_d12
Absolute:
0x43FA_C25C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_nfce_b
18
17
16
sw_pad_ctl_nfrb
W
Reset
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_nfrb
sw_pad_ctl_d15
W
Reset
1
0
0
0
1
1
0
1
0
0
1
0
Figure 4-155. Register Description sw_pad_ctl_nfce_b_nfrb_d15
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-65
Signal Multiplexing
Absolute:
0x43FA_C260
31
30
Access: User Read/Write
29
28
27
26
25
R
24
23
22
21
20
19
sw_pad_ctl_nfale
18
17
16
sw_pad_ctl_nfcle
W
Reset
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_nfcle
sw_pad_ctl_nfwp_b
W
Reset
1
0
0
0
1
1
0
1
1
0
1
0
Figure 4-156. Register Description sw_pad_ctl_nfale_nfcle_nfwp_b
Absolute:
0x43FA_C264
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sdqs3
18
17
16
sw_pad_ctl_nfwe_b
W
Reset
0
0
0
1
1
0
0
0
0
0
0
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_nfwe_b
sw_pad_ctl_nfre_b
W
Reset
0
0
0
0
1
1
0
1
1
0
1
0
Figure 4-157. Register Description sw_pad_ctl_sdqs3_nfwe_b_nfre_b
Absolute:
0x43FA_C268
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sdqs0
18
17
16
sw_pad_ctl_sdqs1
W
Reset
0
0
0
1
1
0
0
0
0
0
0
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
R
sw_pad_ctl_sdqs1
sw_pad_ctl_sdqs2
W
Reset
0
0
0
0
0
1
0
1
1
0
0
0
Figure 4-158. Register Description sw_pad_ctl_sdqs0_sdqs1_sdqs2
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-66
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C26C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sdcke1
18
17
16
sw_pad_ctl_sdclk*
W
Reset
0
0
0
1
0
0
1
0
0
0
0
1
1
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_sdclk*
Reserved
W
Reset
1
0
0
1
1
1
0
1
1
0
1
0
Figure 4-159. Register Description sw_pad_ctl_sdcke1_sdclk_sdclk_b
*Bits 10–19 control the differential output pair SDCLK and SDCLK.
Absolute:
0x43FA_C270
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_cas
18
17
16
sw_pad_ctl_sdwe
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
R
sw_pad_ctl_sdwe
sw_pad_ctl_sdcke0
W
Reset
1
0
0
0
0
1
0
1
0
0
1
0
Figure 4-160. Register Description sw_pad_ctl_cas_sdwe_sdcke0
Absolute:
0x43FA_C274
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_bclk
18
17
16
sw_pad_ctl_rw
W
Reset
0
0
1
0
1
0
1
0
0
0
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_rw
sw_pad_ctl_ras
W
Reset
1
0
0
0
1
1
0
1
0
0
1
0
Figure 4-161. Register Description sw_pad_ctl_bclk_rw_ras
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-67
Signal Multiplexing
Absolute:
0x43FA_C278
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_cs5
18
17
16
sw_pad_ctl_ecb
W
Reset
0
0
0
0
1
0
1
0
0
0
1
1
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_ecb
sw_pad_ctl_lba
W
Reset
1
0
0
0
1
1
0
0
1
0
1
0
Figure 4-162. Register Description sw_pad_ctl_cs5_ecb_lba
Absolute:
0x43FA_C27C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_cs2
18
17
16
sw_pad_ctl_cs3
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_cs3
sw_pad_ctl_cs4
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-163. Register Description sw_pad_ctl_cs2_cs3_cs4
Absolute:
0x43FA_C280
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_oe
18
17
16
sw_pad_ctl_cs0
W
Reset
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_cs0
sw_pad_ctl_cs1
W
Reset
1
0
0
0
1
1
0
0
1
0
1
0
Figure 4-164. Register Description sw_pad_ctl_oe_cs0_cs1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-68
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C284
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
18
sw_pad_ctl_dqm3
17
16
sw_pad_ctl_eb0
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
1
R
sw_pad_ctl_eb0
sw_pad_ctl_eb1
W
Reset
1
0
0
0
1
1
0
0
1
0
1
0
Figure 4-165. Register Description sw_pad_ctl_dqm3_eb0_eb1
Absolute:
0x43FA_C288
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_dqm0
18
17
16
sw_pad_ctl_dqm1
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_dqm1
sw_pad_ctl_dqm2
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-166. Register description sw_pad_ctl_dqm0_dqm1_dqm2
Absolute:
0x43FA_C28C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd29
18
17
16
sw_pad_ctl_sd30
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd30
sw_pad_ctl_sd31
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-167. Register Description sw_pad_ctl_sd29_sd30_sd31
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-69
Signal Multiplexing
Absolute:
0x43FA_C290
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd26
18
17
16
sw_pad_ctl_sd27
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd27
sw_pad_ctl_sd28
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-168. Register Description sw_pad_ctl_sd26_sd27_sd28
Absolute:
0x43FA_C294
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd23
18
17
16
sw_pad_ctl_sd24
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd24
sw_pad_ctl_sd25
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-169. Register Description sw_pad_ctl_sd23_sd24_sd25
Table 1:
Absolute:
0x43FA_C298
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd20
18
17
16
sw_pad_ctl_sd21
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd21
sw_pad_ctl_sd22
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-170. Register Description sw_pad_ctl_sd20_sd21_sd22
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-70
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C29C
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd17
18
17
16
sw_pad_ctl_sd18
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd18
sw_pad_ctl_sd19
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-171. Register Description sw_pad_ctl_sd17_sd18_sd19
Absolute:
0x43FA_C2A0
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd14
18
17
16
sw_pad_ctl_sd15
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd15
sw_pad_ctl_sd16
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-172. Register Description sw_pad_ctl_sd14_sd15_sd16
Absolute:
0x43FA_C2A4
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd11
18
17
16
sw_pad_ctl_sd12
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd12
sw_pad_ctl_sd13
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-173. Register Description sw_pad_ctl_sd11_sd12_sd13
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-71
Signal Multiplexing
Absolute:
0x43FA_C2A8
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd8
18
17
16
sw_pad_ctl_sd9
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd9
sw_pad_ctl_sd10
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-174. Register Description sw_pad_ctl_sd8_sd9_sd10
Absolute:
0x43FA_C2AC
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd5
18
17
16
sw_pad_ctl_sd6
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd6
sw_pad_ctl_sd7
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-175. Register Description sw_pad_ctl_sd5_sd6_sd7
Absolute:
0x43FA_C2B0
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sd2
18
17
16
sw_pad_ctl_sd3
W
Reset
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd3
sw_pad_ctl_sd4
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-176. Register Description sw_pad_ctl_sd2_sd3_sd4
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-72
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C2B4
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sdba0
18
17
16
sw_pad_ctl_sd0
W
Reset
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_sd0
sw_pad_ctl_sd1
W
Reset
1
0
0
1
1
1
0
1
0
0
1
0
Figure 4-177. Register Description sw_pad_ctl_sdba0_sd0_sd1
Absolute:
0x43FA_C2B8
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_a24
18
17
16
sw_pad_ctl_a25
W
Reset
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
R
sw_pad_ctl_a25
sw_pad_ctl_sdba1
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-178. Register Description sw_pad_ctl_a24_a25_sdba1
Absolute:
0x43FA_C2BC
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_a21
18
17
16
sw_pad_ctl_a22
W
Reset
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_a22
sw_pad_ctl_a23
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-179. Register Description sw_pad_ctl_a21_a22_a23
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-73
Signal Multiplexing
Absolute:
0x43FA_C2C0
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_a18
18
17
16
sw_pad_ctl_a19
W
Reset
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_a19
sw_pad_ctl_a20
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-180. Register Description sw_pad_ctl_a18_a19_a20
Absolute:
0x43FA_C2C4
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_a15
18
17
16
sw_pad_ctl_a16
W
Reset
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_a16
sw_pad_ctl_a17
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-181. Register Description sw_pad_ctl_a15_a16_a17
Absolute:
0x43FA_C2C8
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_a12
18
17
16
sw_pad_ctl_a13
W
Reset
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_a13
sw_pad_ctl_a14
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-182. Register Description sw_pad_ctl_a12_a13_a14
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-74
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C2CC
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_a10
18
17
16
sw_pad_ctl_ma10
W
Reset
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_ma10
sw_pad_ctl_a11
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-183. Register Description sw_pad_ctl_a10_ma10_a11
Absolute:
0x43FA_C2D0
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_a7
18
17
16
sw_pad_ctl_a8
W
Reset
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_a8
sw_pad_ctl_a9
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-184. Register Description sw_pad_ctl_a7_a8_a9
Absolute:
0x43FA_C2D4
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_a4
18
17
16
sw_pad_ctl_a5
W
Reset
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_a5
sw_pad_ctl_a6
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-185. Register Description sw_pad_ctl_a4_a5_a6
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-75
Signal Multiplexing
Absolute:
0x43FA_C2D8
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
18
sw_pad_ctl_a1
17
16
sw_pad_ctl_a2
W
Reset
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_a2
sw_pad_ctl_a3
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
Figure 4-186. Register Description sw_pad_ctl_a1_a2_a3
Absolute:
0x43FA_C2DC
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
18
sw_pad_ctl_vpg0
17
16
sw_pad_ctl_vpg1
W
Reset
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
R
sw_pad_ctl_vpg1
sw_pad_ctl_a0
W
Reset
1
0
0
0
0
0
0
0
1
0
1
0
Figure 4-187. Register Description sw_pad_ctl_vpg0_vpg1_a0
Absolute:
0x43FA_C2E0
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_vstby
18
17
16
sw_pad_ctl_dvfs0
W
Reset
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_dvfs0
sw_pad_ctl_dvfs1
W
Reset
1
0
0
0
0
0
0
0
1
0
1
0
Figure 4-188. Register Description sw_pad_ctl_vstby_dvfs0_dvfs1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-76
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C2E4
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_boot_mode4
18
17
16
sw_pad_ctl_ckil
W
Reset
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_ckil
sw_pad_ctl_power_fail
W
Reset
1
1
0
0
0
0
0
1
1
0
0
0
0
Figure 4-189. Register Description sw_pad_ctl_boot_mode4_ckil_power_fail
Absolute:
0x43FA_C2E8
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
sw_pad_ctl_boot_mode1
19
18
17
16
sw_pad_ctl_boot_mode2
W
Reset
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_boot_mode2
sw_pad_ctl_boot_mode3
W
Reset
1
0
0
0
0
0
0
0
1
0
1
0
0
Figure 4-190. Register Description sw_pad_ctl_boot_mode1_boot_mode2_boot_mode3
Absolute:
0x43FA_C2EC
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_por_b
18
17
16
sw_pad_ctl_clko
W
Reset
0
0
0
1
1
0
1
1
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_clko
sw_pad_ctl_boot_mode0
W
Reset
1
0
0
1
1
1
0
0
1
0
1
0
0
Figure 4-191. Register Description sw_pad_ctl_por_b_clko_boot_mode0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-77
Signal Multiplexing
Absolute:
0x43FA_C2F0
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_simpd0
18
17
16
sw_pad_ctl_ckih
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_ckih
sw_pad_ctl_reset_in_b
W
Reset
1
1
0
0
0
0
0
1
1
0
1
1
0
Figure 4-192. Register Description sw_pad_ctl_simpd0_ckih_reset_in_b
Absolute:
0x43FA_C2F4
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_sven0
18
17
16
sw_pad_ctl_stx0
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_stx0
sw_pad_ctl_srx0
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
Figure 4-193. Register Description sw_pad_ctl_sven0_stx0_srx0
Absolute:
0x43FA_C2F8
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_gpio3_1
18
17
16
sw_pad_ctl_sclk0
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
R
sw_pad_ctl_sclk0
sw_pad_ctl_srst0
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
Figure 4-194. Register Description sw_pad_ctl_gpio3_1_sclk0_srst0
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-78
Freescale Semiconductor
Signal Multiplexing
Absolute:
0x43FA_C2FC
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_gpio1_5
18
17
16
sw_pad_ctl_gpio1_6
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_gpio1_6
sw_pad_ctl_gpio3_0
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-195. Register Description sw_pad_ctl_gpio1_5_gpio1_6_gpio3_0
Absolute:
0x43FA_C300
31
30
Access: User Read/Write
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_gpio1_2
18
17
16
sw_pad_ctl_gpio1_3
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_gpio1_3
sw_pad_ctl_gpio1_4
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-196. Register Description sw_pad_ctl_gpio1_2_gpio1_3_gpio1_4
Absolute:
0x43FA_C304
31
30
Access: User Read/Write
29
28
27
26
R
25
24
23
22
21
20
19
sw_pad_ctl_pwmo
18
17
16
sw_pad_ctl_gpio1_0
W
Reset
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_gpio1_0
sw_pad_ctl_gpio1_1
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-197. Register Description sw_pad_ctl_pwmo_gpio1_0_gpio1_1
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-79
Signal Multiplexing
Absolute:
0x43FA_C308
31
Access: User Read/Write
30
29
28
27
R
26
25
24
23
22
21
20
19
sw_pad_ctl_capture
18
17
16
sw_pad_ctl_compare
W
Reset
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R
sw_pad_ctl_compare
sw_pad_ctl_watchdog_rst
W
Reset
1
0
0
0
0
0
0
1
1
0
1
0
0
Figure 4-198. Register Description sw_pad_ctl_capture_compare_watchdog_rst
4.3.8.1
Software-Controllable Signals Register 0 (SCS0)
See Figure 4-199 for an illustration of valid bits in the Software-Controllable Signals Register 0 and
Table 4-10 for its field descriptions.
0x5001_C02C (SCS0)
Access: Supervisor read/write
7
R
0
W
LOCK
Reset
6
5
4
3
2
1
0
SCS[27]
SCS[26]
SCS[25]
SCS[24]
SCS[23]
SCS[22]
SCS[21]
0
0
0
0
0
0
0
0
Figure 4-199. Software Controllable Signals Register 0
Table 4-10. Software Controllable Signals Register 0 Field Descriptions
Field
7
LOCK
Description
Lock this register. This bit is used to lock the contents of this register until the next reset. The
intended usage is to have trusted software program the register as desired and lock it before
allowing distrusted software to run. This bit is write only; reading this bit returns a zero.
0 The register is not locked; it may be modified.
1 The register is locked; all attempts to modify it are ignored.
6
SCS[27]
Reserved
5
SCS[26]
IPU/ECT DMA Event Source Select. Selects either the IPU or ECT as the DMA event source.
0 IPU (default)
1 ECT
4–0
SCS[24:21]
4.3.8.2
Reserved
Software-Controllable Signals Registers 1–3 (SCS1–SCS3)
See Figure 4-200 through Figure 4-202 for illustrations of valid bits in the Software-Controllable Signals
Registers 1–3, and Table 4-11 through Table 4-13 for their field descriptions.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-80
Freescale Semiconductor
Signal Multiplexing
0x5001_C030 (SCS1)
Access: Supervisor read/write
7
R
0
W
LOCK
Reset
6
5
4
3
2
1
0
SCS[20]
SCS[19]
SCS[18]
SCS[17]
SCS[16]
SCS[15]
SCS[14]
0
0
0
0
0
0
0
0
Figure 4-200. Software Controllable Signals Register 1
Table 4-11. Software Controllable Signals Registers 1
Field
Description
7
LOCK
Lock this register. This bit is used to lock the contents of this register until the next reset. The
intended usage is to have trusted software program the register as desired and lock it before
allowing distrusted software to run. This bit is write-only; reading this bit returns a zero.
0 The register is not locked; it may be modified.
1 The register is locked; all attempts to modify it are ignored.
6–2
SCS[20:16]
Reserved
1
SCS[15]
Drive strength control ipp_des0 for SDCLK and SDCLK. This bit is used in conjunction with
ipp_des1(sw_pad_ctl_sdclk[2] in the sw_pad_ctl_sdcke1_sdclk_sdclk register) to determine the
drive strength capability of these signals as follows:
Note: The settings of ipp_des0 is the reverse of the standard settings used in the sw_pad__ctl
registers.
ipp_dse1* ipp_dse0** Drive Strength
0
1
Standard
0
0
High (default)
1
x
Max
*sw_pad_ctl_sdclk[2]
**SCS[15]
0
SCS[14]
(For revision 2.0 and 2.0.1 silicon) Drive strength control ipp_des0 for SDBA1 and SDBA0. This bit
is used in conjunction with SCS[7] in the SCS2 register (functions as ipp_dse1) to determine the
drive strength capability of these signals as follows:
Note: The settings of ipp_des0 is the reverse of the standard settings used in the sw_pad__ctl
registers.
ipp_dse1* ipp_dse0** Drive Strength
0
1
Standard
0
0
High (default)
1
x
Max
*SCS[7]
**SCS[14]
0x5001_C034 (SCS2)
7
R
0
W
LOCK
Reset
0
Access: Supervisor read/write
6
5
4
3
2
1
0
SCS[13]
SCS[12]
SCS[11]
SCS[10]
SCS[9]
SCS[8]
SCS[7]
0
0
0
0
0
0
0
Figure 4-201. Software Controllable Signals Register 2
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-81
Signal Multiplexing
Table 4-12. Software Controllable Signals Registers 2
Field
Description
7
LOCK
Lock this register. This bit is used by the HAB to enable JTAG debugging, assuming that a properly
signed command to do so is found and validated by the HAB. The HAB must lock the register
before passing control to the OS whether or not JTAG debugging has been enabled.
0 The register is not locked; it may be modified.
1 The register is locked; all attempts to modify it are ignored.
6
SCS[13]
Reserved for future use.
5
SCS[12]
(For revision 2.0 and 2.0.1 silicon) Drive strength control ipp_dse1 for SDQS[3:0]. This bit is used
in conjunction with SCS[8] in the SCS2 register (functions as ipp_dse0) to determine the drive
strength capability of these signals as follows (note that the definition of ipp_dse0 is reversed from
the standard description in the sw_pad_ctl registers):
ipp_dse1 (SCS[12])
ipp_dse0 (SCS[8]) drive strength
4
SCS[11]
0
1
standard
0
1
0
x
high (default)
max
(For revision 2.0 and 2.0.1 silicon) Drive strength control ipp_dse0 for SDCKE1 and SDCKE0. This
bit is used to determine the drive strength capability of these signals as follows (note that the
definition of ipp_dse0 is reversed from the standard description in the sw_pad_ctl registers and
note that max drive strength is not an option for these signals):
ipp_dse0 (SCS[11])
drive strength
1
0
standard
high (default)
3
SCS[10]
Reserved for future use.
2
SCS[9]
(For revision 2.0 and 2.0.1 silicon) Drive strength control ipp_dse0 for SDWE. This bit is used to
determine the drive strength capability of these signals as follows (note that the definition of
ipp_dse0 is reversed from the standard description in the sw_pad_ctl registers and note that max
drive strength is not an option for these signals):
ipp_dse0 (SCS[9])
1
0
drive strength
standard
high(default)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
4-82
Freescale Semiconductor
Signal Multiplexing
Table 4-12. Software Controllable Signals Registers 2 (continued)
Field
Description
1
SCS[8]
(For revision 2.0 and 2.0.1 silicon) Drive strength control ipp_dse0 for SDQS[3:0]. This bit is used
in conjunction with SCS[12] in the SCS2 register (functions as ipp_dse1) to determine the drive
strength capability of these signals as follows (note that the definition of ipp_dse0 is reversed from
the standard description in the sw_pad_ctl registers):
ipp_dse1 (SCS[12])
0
SCS[7]
ipp_dse0 (SCS[8])
drive strength
0
1
standard
0
1
0
x
high (default)
max
(For revision 2.0 and 2.0.1 silicon) Drive strength control ipp_dse1 for SDBA1 and SDBA0. This bit
is used in conjunction with SCS[14] in the SCS1 register (functions as ipp_dse0) to determine the
drive strength capability of these signals as follows (note that the definition of ipp_dse0 is reversed
from the standard description in the sw_pad_ctl registers):
ipp_dse1 (SCS[7]) ipp_dse0 (SCS[14])
drive strength
0
1
standard
0
1
0
x
high (default)
max
0x5001_C038 (SCS3)
7
R
Access: Supervisor read/write
6
5
4
3
2
1
0
SCS[6]
SCS[5]
SCS[4]
SCS[3]
SCS[2]
SCS[1]
SCS[0]
0
0
0
0
0
0
0
0
W
Reset
0
Figure 4-202. Software Controllable Signals Register 3
Table 4-13. Software Controllable Signals Registers 3
Field
Description
7
LOCK
Lock this register. This bit is used by the HAB to enable JTAG debugging, assuming that a properly
signed command to do so is found and validated by the HAB. The HAB must lock the register
before passing control to the OS whether or not JTAG debugging has been enabled.
0 The register is not locked; it may be modified.
1 The register is locked; all attempts to modify it are ignored.
6
SCS[6]
MPEG4-EMI throughput improvement
0 INCR bus operation (INCR4 off)
1 INCR4 bus operation on AHB enabled
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-83
Signal Multiplexing
Table 4-13. Software Controllable Signals Registers 3 (continued)
Field
Description
5–3
SCS[5]–SCS[3]
MSHC2 Programmable Delay Control – These bits determine the amount of delay added in the
MSHC2 module between the internal SCLK to the external MSHC2_SCLK pin.
SCS[5] SCS[4] SCS[3]
0
0
0
0
0
1
0
1
0
1
1
1
2–0
SCS[2]–SCS[0]
MSHC1 Programmable Delay Control – These bits determine the amount of delay added in the
MSHC1 module between the internal SCLK to the external MSHC1_SCLK pin.
SCS[2] SCS[1] SCS[0]
delay
0
0
0
1
4.4
delay
0
1 ns
2 ns
7 ns
0
0
1
1
0
1
0
1
0
1 ns
2 ns
7 ns
I/O Settings and Signal Multiplexing Scheme
Appendix A, “i.MX31/31L Multiplexing and I/O Settings,” contains detailed information about the
settings for each I/O line and the functional multiplexing scheme. Table A-1 through Table A-4 describe
the pin settings and the functional multiplexing between I/O and signals.
4.4.1
EMI Signal Multiplexing
The EMI signal multiplexing described in this section deals with multiplexing that is performed in the
EMI. This type of multiplexing is performed automatically whenever the processor accesses a particular
memory space that is controlled by one of the four memory controllers: EIM, ESDCTL (SDRAM-SDR or
SDRAM-DDR), PCMCIA, or NFC. See Table 4-14 for details.
Table 4-14. EMI Signal Multiplexing
Contact Name
I/O Type
EIM
SDRAM
SDR
PCMCIA
SDRAM
DDR
NFC
A0
regular
A0
MA0
A0
MA0
—
A1
regular
A1
MA1
A1
MA1
—
A2
regular
A2
MA2
A2
MA2
—
A3
regular
A3
MA3
A3
MA3
—
A4
regular
A4
MA4
A4
MA4
—
A5
regular
A5
MA5
A5
MA5
—
A6
regular
A6
MA6
A6
MA6
—
A7
regular
A7
MA7
A7
MA7
—
A8
regular
A8
MA8
A8
MA8
—
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Signal Multiplexing
Table 4-14. EMI Signal Multiplexing (continued)
Contact Name
I/O Type
EIM
SDRAM
SDR
PCMCIA
SDRAM
DDR
NFC
A9
regular
A9
MA9
A9
MA9
—
A10
regular
A10
—
A10
—
—
MA10
regular
—
MA10
—
MA10
—
A11
regular
A11
MA11
A11
MA11
—
A12
regular
A12
MA12
A12
MA12
—
A13
regular
A13
MA13
A13
MA13
—
A14
regular
A14
—
A14
—
—
A15
regular
A15
—
A15
—
—
A16
regular
A16
—
A16
—
—
A17
regular
A17
—
A17
—
—
A18
regular
A18
—
A18
—
—
A19
regular
A19
—
A19
—
—
A20
regular
A20
—
A20
—
—
A21
regular
A21
—
A21
—
—
A22
regular
A22
—
A22
—
—
A23
regular
A23
—
A23
—
—
A24
regular
A24
—
A24
—
—
A25
regular
A25
—
A25
—
—
SDBA1
regular
—
SDBA1
CE1
SDBA1
—
SDBA0
regular
—
SDBA0
CE2
SDBA0
—
SD0
ddr
—
SD0
—
SD0
—
SD1
ddr
—
SD1
—
SD1
—
SD2
ddr
—
SD2
—
SD2
—
SD3
ddr
—
SD3
—
SD3
—
SD4
ddr
—
SD4
—
SD4
—
SD5
ddr
—
SD5
—
SD5
—
SD6
ddr
—
SD6
—
SD6
—
SD7
ddr
—
SD7
—
SD7
—
SD8
ddr
—
SD8
—
SD8
—
SD9
ddr
—
SD9
—
SD9
—
SD10
ddr
—
SD10
—
SD10
—
SD11
ddr
—
SD11
—
SD11
—
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-85
Signal Multiplexing
Table 4-14. EMI Signal Multiplexing (continued)
Contact Name
I/O Type
EIM
SDRAM
SDR
PCMCIA
SDRAM
DDR
NFC
SD12
ddr
—
SD12
—
SD12
—
SD13
ddr
—
SD13
—
SD13
—
SD14
ddr
—
SD14
—
SD14
—
SD15
ddr
—
SD15
—
SD15
—
SD16
ddr
—
SD16
—
SD16
—
SD17
ddr
—
SD17
—
SD17
—
SD18
ddr
—
SD18
—
SD18
—
SD19
ddr
—
SD19
—
SD19
—
SD20
ddr
—
SD20
—
SD20
—
SD21
ddr
—
SD21
—
SD21
—
SD22
ddr
—
SD22
—
SD22
—
SD23
ddr
—
SD23
—
SD23
—
SD24
ddr
—
SD24
—
SD24
—
SD25
ddr
—
SD25
—
SD25
—
SD26
ddr
—
SD26
—
SD26
—
SD27
ddr
—
SD27
—
SD27
—
SD28
ddr
—
SD28
—
SD28
—
SD29
ddr
—
SD29
—
SD29
—
SD30
ddr
—
SD30
—
SD30
—
SD31
ddr
—
SD31
—
SD31
—
DQM0
ddr
—
DQM0
—
DQM0
—
DQM1
ddr
—
DQM1
—
DQM1
—
DQM2
ddr
—
DQM2
—
DQM2
—
DQM3
ddr
—
DQM3
—
DQM3
—
EB0
regular
EB0
—
REG
—
—
EB1
regular
EB1
—
IORD
—
—
OE
regular
OE
—
IOWR
—
—
CS0
regular
CS0
—
—
—
—
CS1
regular
CS1
—
—
—
—
CS2
regular
CS2
CSD0
—
CSD0
—
CS3
regular
CS3
CSD1
—
CSD1
—
CS4
regular
CS4
—
—
—
—
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Freescale Semiconductor
Signal Multiplexing
Table 4-14. EMI Signal Multiplexing (continued)
Contact Name
I/O Type
EIM
SDRAM
SDR
PCMCIA
SDRAM
DDR
NFC
CS5
regular
CS5
—
—
—
—
ECB
regular
ECB
—
—
—
—
LBA
regular
LBA
—
OE
—
—
BCLK
regular
BCLK
—
—
—
—
RW
regular
RW
—
WE
—
—
RAS
regular
—
RAS
—
RAS
—
CAS
regular
—
CAS
—
CAS
—
SDWE
regular
—
SDWE
—
SDWE
—
SDCKE0
regular
—
SDCKE0
—
SDCKE0
—
SDCKE1
regular
—
SDCKE1
—
SDCKE1
—
SDCLK
regular
—
SDCLK
—
SDCLK
—
SDCLK
regular
—
—
—
SDCLK
—
SDQS0
ddr
—
—
—
SDQS0
—
SDQS1
ddr
—
—
—
SDQS1
—
SDQS2
ddr
—
—
—
SDQS2
—
SDQS3
ddr
—
—
—
SDQS3
—
NFWE
regular
—
—
—
—
WE
NFRE
regular
—
—
—
—
RE
NFALE
regular
—
—
—
—
ALE
NFCLE
regular
—
—
—
—
CLE
NFWP
regular
—
—
—
—
WP
NFCE
regular
—
—
—
—
CE
NFRB
regular
—
—
—
—
R/B
D15
regular
D15
—
D15
—
D15
D14
regular
D14
—
D14
—
D14
D13
regular
D13
—
D13
—
D13
D12
regular
D12
—
D12
—
D12
D11
regular
D11
—
D11
—
D11
D10
regular
D10
—
D10
—
D10
D9
regular
D9
—
D9
—
D9
D8
regular
D8
—
D8
—
D8
D7
regular
D7
—
D7
—
D7
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-87
Signal Multiplexing
Table 4-14. EMI Signal Multiplexing (continued)
Contact Name
I/O Type
EIM
SDRAM
SDR
PCMCIA
SDRAM
DDR
NFC
D6
regular
D6
—
D6
—
D6
D5
regular
D5
—
D5
—
D5
D4
regular
D4
—
D4
—
D4
D3
regular
D3
—
D3
—
D3
D2
regular
D2
—
D2
—
D2
D1
regular
D1
—
D1
—
D1
D0
regular
D0
—
D0
—
D0
PC_CD1
regular
—
—
CD1_B
—
—
PC_CD2
regular
—
—
CD2_B
—
—
PC_WAIT
regular
—
—
WAIT_B
—
—
PC_READY
regular
—
—
READY
—
—
PC_PWRON
regular
—
—
PC_PWRON
—
—
PC_VS1
regular
—
—
VS1
—
—
PC_VS2
regular
—
—
VS2
—
—
PC_BVD1
regular
—
—
BVD1
—
—
PC_BVD2
regular
—
—
BVD2
—
—
PC_RST
regular
—
—
RST
—
—
IOIS16
regular
—
—
IOIS16/WP
—
—
PC_RW
regular
—
—
RW_B
—
—
PC_POE
regular
—
—
POE
—
—
4.5
Special I/O Signal Considerations
The following I/O lines should be connected as described in the following sections.
4.5.1
Power Ready Input (GPIO1_5)
The i.MX31/31L uses the Power Ready input as a qualifier when exiting state retention mode. The power
ready input, GPIO1_5, should be connected to an external power management IC power ready output
signal. If not used, GPIO1_5 must either be (a) externally pulled-up to NVCC1 or (b) a no connect,
internally pulled-up by enabling the on-chip pull-up resistor. GPIO1_5 is a dedicated input and cannot be
used as a general-purpose input/output.
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Signal Multiplexing
4.5.2
SJC_MOD
SJC_MOD must be externally connected to GND for normal operation. Termination to GND through an
external pull-down resistor (such as 1 kΩ) is allowed, but the value should be much smaller than the
on-chip 100 kΩ pull-up.
4.5.3
CE_CONTROL
CE_CONTROL is a reserved input and must be externally tied to GND through a 1 kΩ resistor.
4.5.4
TTM_PAD
TTM_PAD is for Freescale factory use only. Control bits indicate pull-up/down disabled. However,
TTM_PAD is actually connected to an on-chip pull-down device. Users must either float this signal or tie
it to GND.
4.5.5
M_REQUEST and M_GRANT
These two signals are not utilized internally. The user should make no connection to these signals.
4.5.6
External DMA Signals (EXTDMA)
Input signals EXTDMA_0, EXTDMA_1, and EXTDMA_2 (also called EXTDMAREQ1,
EXTDMAREQ2, and EXTDMAREQ3) are used as external DMA request event signals and are designed
to trigger internal DMA transactions. This type of functionality is analogous to interrupt requests. These
signals should not be used to trigger memory-to-memory DMA transactions. The SDMA script for
memory-to-memory transfers is not designed to clear the SDMA request event when the DMA transaction
is complete.
To trigger SDMA transfers to/from the WEIM, ESDCTL, or NAND Flash Controller, the external DMA
request signals should be configured as a GPIO interrupt, where the interrupt service routine initiates the
memory-to-memory DMA transfer. The i.MX31/31L do not provide external bus mastership. DMA-style
transactions on the external bus (those requiring both a DMA request and DMA grant or acknowledge) are
not supported. These external request signals are accessed by invoking Alternate Mode 1 on GPIO1_0,
GPIO1_1, and GPIO1_2.
4.5.7
Tamper Detect Logic
Tamper detect logic is used to issue a security violation. This logic is activated if the tamper detect input
is asserted.
The tamper detect logic is disabled after reset. After enabling the logic, it is impossible to disable it until
the next reset. The GPR[16] bit functions as the tamper detect enable bit.
GPIO1_6 functions similarly to other I/O with GPIO capabilities regardless of the status of the tamper
detect enable bit. (For example, the GPIO1_6 can function as an input with GPIO capabilities, such as
sampling through PSR or generating interrupts.)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
4-89
Signal Multiplexing
4.5.8
Clock Source Select (CLKSS)
The CLKSS is the input that selects the default reference clock source providing input to the DPLL. To
select CKIH, tie CLKSS to NVCC1. To select CKIL, tie CLKSS to ground. After initialization, the
reference clock source can be changed (initial setting is overwritten) by programming the PRCS bits in the
CCMR.
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Chapter 5
General Purpose Input/Output (GPIO)
The General Purpose Input/Output (GPIO) module provides 32 bits of bidirectional, general-purpose input
and output signals. Figure 5-1 presents a block diagram of the GPIO.
GDIR
DR
IP Bus I/F
gdir
gpio_dr
gpio_in
PSR
ICR0
ICR1
Interrupt
Control
Unit
IMR
ISR
int_31_16
int_15_0
int_31_0
Figure 5-1. GPIO Block Diagram
5.1
Overview
The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or
outputs. When configured as an output, you can write to an internal register to control the state driven on
the output pin. When configured as an input, you can detect the state of the input by reading the state of
an internal register.
The GPIO module is one of the modules controlling the IOMUX of the System on a Chip (SoC).
Figure 5-2 shows the SoC muxing scheme.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
5-1
General Purpose Input/Output (GPIO)
IP MODULE
GPIO
IOMUX
input_on
DR
GDIR
PSR
Dir
Data_out
Data_in
PAD1
ICR1 ICR2
IMR
ISR
alternate input
IO_CTL
IOMUXC
MUX_OUT_EN
MUX_IN_EN
PAD_SW_CTL
SW_INPUT_ON
SW_PAD_CFG
SW_PUPD_CFG
IOMUX
input_on
Dir
Data_out
Data_in
PAD2
Figure 5-2. SoC IOMUX Scheme
The functionality is provided through seven registers, an edge-detect circuit, and an interrupt generation
logic.
The seven registers include:
• DR—Data Register (32-Bit)
• GDIR—Data Direction Register (32-Bit)
• PSR—Pad Sample Register (32-Bit)
• ICR (ICR1, ICR2)—Two Interrupt Control Registers (2x32Bit)
• IMR—An Interrupt Mask Register (32-Bit)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
5-2
Freescale Semiconductor
General Purpose Input/Output (GPIO)
•
ISR—An Interrupt Status Register (32-Bit)
The data register is used to drive data from this register to I/O pins. Read access to the data register returns
the value stored in the register or the value of the pad depending on the corresponding GDIR bit.
The data direction register controls the direction of the pin through the I/O multiplexer. Writing one to this
register configures the pin as an output, while a zero configures it as an input.
Each GPIO input has a dedicated edge-detect circuit that can be configured through software to detect
rising edges, falling edges, a logic low-level or a logic high-level on the input pin. Thirty two interrupts
are supported. Two registers are used for this configuration, the interrupt configuration register (ICR1 and
ICR2). Two bits are assigned to each GPIO pin, selecting one of the four possible detection methods.
The outputs of the edge detect circuits are optionally masked by setting the corresponding bit in the
interrupt mask register (IMR). These qualified outputs are OR’ed together to generate three interrupt lines:
• interrupt_or_31_16 : 1 Bit Int OR of 16 High Int
• interrupt_or_15_0 : 1 Bit Int OR of 16 Low Int
• ipi_gpio_int : 1 Bit Int OR of 32
• ipi_gpio_int32 : 32 bit All Interrupt Out
5.1.1
Features
The GPIO includes the following features:
• General purpose input/output logic:
— Provides the ability to drive specific data to the pad using the DR register
— Provides the ability to control the direction of the pad using the GDIR register
— Enables the core to have the ability to sample the status of the corresponding pads by reading
the PSR register
• GPIO interrupts:
— Provides the ability to support up to 32 interrupts
— Enables the ability to identify interrupt edges
— Generates three active high interrupts to the SoC interrupt controller
5.2
External Signal Description
This module has no usable external signals.
5.3
Memory Map and Register Definition
There are seven GPIO registers. All registers are byte-addressable and accessible from the IP interface.
5.3.1
Memory Map
Table 5-1 shows the GPIO memory map.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
5-3
General Purpose Input/Output (GPIO)
Table 5-1. GPIO Memory Map
Address
Register
Access
Reset Value
Section/Page
GPIO Data
R/W
0X0000_0000
5.3.3.1/5-6
0x53FC_C004 GPIO1 (GDIR)
0x53FD_0004 GPIO2 (GDIR)
0x53FA_4004 GPIO3 (GDIR)
GPIO Direction
R/W
0X0000_0000
5.3.3.2/5-7
0x53FC_C008 GPIOP1 (PSR)
0x53FD_0008 GPIOP2 (PSR)
0x53FA_4008 GPIOP3 (PSR)
GPIO Pad Status
R
0X0000_0000
5.3.3.3/5-8
0x53FC_C00C GPIO1 (ICR1)
0x53FD_000C GPIO2 (ICR1)
0x53FA_400C GPIO3 (ICR1)
GPIO Interrupt Configuration
Register1
R/W
0X0000_0000
5.3.3.4/5-9
0x53FC_C010 GPIO1 (ICR2)
0x53FD_0010 GPIO2 (ICR2)
0x53FA_4010 GPIO3 (ICR2)
GPIO Interrupt Configuration
Register2
R/W
0X0000_0000
5.3.3.5/5-10
0x53FC_C014 GPIO1(IMR)
0x53FD_0014 GPIO2 (IMR)
0x53FA_4014 GPIO3 (IMR)
GPIO Interrupt Mask Register
R/W
0X0000_0000
5.3.3.6/5-10
0x53FC_C018 GPIO1 (ISR)
0x53FD_0018 GPIO2 (ISR)
0x53FA_4018 GPIO3 (ISR)
GPIO Interrupt Status Register
R/W
0X0000_0000
5.3.3.7/5-11
0x53FC_C000 GPIO1 (DR)
0x53FD_0000 GPIO2 (DR)
0x53FA_4000 GPIO3 (DR)
5.3.2
Register Summary
The following definitions serve as a key for the GPIO register summary and individual register diagrams.
Always
reads 1
1
Always
reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0
bit
only bit
only bit BIT to clear w1c
bit BIT
N/A
Figure 5-3. Key to Register Fields
Table 5-2 provides a key for register figures and the register summary table.
Table 5-2. Register Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable.
FIELDNAME
Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
R
Read only. Writing this bit has no effect.
W
Write only.
R/W
Standard read/write bit. Only software can change the bit’s value (other than a hardware reset).
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
5-4
Freescale Semiconductor
General Purpose Input/Output (GPIO)
Table 5-2. Register Conventions (continued)
Convention
w1c
Self-clearing bit
Description
Write one to clear. A status bit that can be read, and is cleared by writing a one.
Writing a one has some effect on the module, but it always reads as zero (previously labeled slfclr).
Reset Values
0
Resets to zero.
1
Resets to one.
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
Reset value is determined by polarity of indicated signal.
Table 5-3 shows the GPIO register summary.
Table 5-3. GPIO Register Summary
Name
0x53FC_C000
GPIO1 (DR)
0x53FD_0000
GPIO2 (DR)
0x53FA_4000
GPIO3 (DR)
0x53FC_C004
GPIO1 (GDIR)
0x53FD_0004
GPIO2 (GDIR)
0x53FA_4004
GPIO3 (GDIR)
0x53FC_C008
GPIOP1 (PSR)
0x53FD_0008
GPIOP2 (PSR)
0x53FA_4008
GPIOP3 (PSR)
0x53FC_C00C
GPIO1 (ICR1)
0x53FD_000C
GPIO2 (ICR1)
0x53FA_400C
GPIO3 (ICR1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
DR[31:16]
W
R
DR[15:0]
W
R
GDIR[31:16]
W
R
GDIR[15:0]
W
R
PSR[31:16]
W
R
PSR[15:0]
W
R
ICR1[31:16]
W
R
ICR1[15:0]
W
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
5-5
General Purpose Input/Output (GPIO)
Table 5-3. GPIO Register Summary (continued)
Name
0x53FC_C010
GPIO1 (ICR2)
0x53FD_0010
GPIO2 (ICR2)
0x53FA_4010
GPIO3 (ICR2)
0x53FC_C014
GPIO1(IMR)
0x53FD_0014
GPIO2 (IMR)
0x53FA_4014
GPIO3 (IMR)
0x53FC_C018
GPIO1 (ISR)
0x53FD_0018
GPIO2 (ISR)
0x53FA_4018
GPIO3 (ISR)
5.3.3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
R
ICR2[31:16]
W
R
ICR2[15:0]
W
R
IMR[31:16]
W
R
IMR[15:0]
W
R
W
ISR[31:16]
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R
W
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ISR[15:0]
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Register Descriptions
This section contains the detailed register descriptions for the GPIO registers.
5.3.3.1
GPIO Data Register (DR)
The GPIO DR register is a 32-bit register. Each bit stores a data to be driven to the pad at all times. If the
IOMUX is in GPIO mode and the direction is output, this data will be driven there. If the direction is input,
then a read action to DR bit reflects the value on the corresponded pad. Two wait states are required in read
access for synchronization.
Reading of DR:
The data returned when reading the DR register is a function of the IOMUX input mode settings and the
corresponding GDIR bit.
If GDIR == 1 && IOMUX input mode == GPIO: reading DR will return the content of the DR register
If GDIR == 0 && IOMUX input mode == GPIO: reading DR will return the pad’s value
If GDIR == 1 && IOMUX input mode != GPIO: reading DR will return the content of the DR register
If GDIR == 0 && IOMUX input mode != GPIO: reading DR will return zero.
Figure 5-4 shows the DR register, and Table 5-4 shows the register’s field descriptions.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
5-6
Freescale Semiconductor
General Purpose Input/Output (GPIO)
Access: User read/write
0x53FC_C000 GPIO1 (DR)
0x53FD_0000 GPIO2 (DR)
0x53FA_4000 GPIO3 (DR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
DR[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
DR[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 5-4. GPIO Data Register (DR)
Table 5-4. DR Field Descriptions
Field
31–0
DR
5.3.3.2
Description
Data bits. This register defines the value of the GPIO output when the pin is configured as an output (GDIR[n]=1).
Writes to this register are stored in a register. Reading DR returns the value stored in the register if the pin is
configured as an output (GDIR=1), or the state of the I/O pin if configured as an input (GDIR[n]=0).
Settings:
The I/O multiplexer associated with each bit must be configured for GPIO for the function to affect the state of the
pin. Reading the data register with the input path disabled will always return a zero value.
GPIO Direction Register (GDIR)
The GPIO GDIR register is a 32-bit register that functions as direction control when the IOMUX direction
is controlled by this bit. Each bit specifies the direction of a specific pad. The mapping of each DIR bit to
a corresponding pad is determined on the SoC’s pin assignment and IOMUX table. Figure 5-5 shows the
GDIR register, and Table 5-5 shows the register’s field descriptions.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
5-7
General Purpose Input/Output (GPIO)
Access: User read/write
0x53FC_C004 GPIO1 (GDIR)
0x53FD_0004 GPIO2 (GDIR)
0x53FA_4004 GPIO3 (GDIR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
GDIR[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
GDIR[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 5-5. GPIO Direction Register (GDIR)
Table 5-5. GDIR Field Descriptions
Field
Description
31–0
GDIR
GPIO Direction bits. Bit i of this register defines the direction of the GPIO[i] signal.
0 GPIO is configured as input.
1 GPIO is configured as output.
Note: GDIR affects only the direction of the I/O pin when the corresponding bit in the I/O MUX is configured for GPIO.
5.3.3.3
GPIO Pad Status Register (PSR)
The GPIO PSR register is a 32-bit read-only register. Each bit stores the value of the corresponding pad.
This register is clocked with the ipg_clk_s clock, meaning that the value on the pad is sampled only when
accessing this location. Two wait states are required any time this register is accessed for synchronization.
Figure 5-6 shows the PSR register, and Table 5-6 shows the register’s field descriptions.
NOTE
PSR[i]—pad sample register [i]
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
5-8
Freescale Semiconductor
General Purpose Input/Output (GPIO)
Access: User read
0x53FC_C008 GPIOP1 (PSR)
0x53FD_0008 GPIOP2 (PSR)
0x53FA_4008 GPIOP3 (PSR)
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
PSR[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
PSR[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 5-6. GPIO Pad Status Register (PSR)
Table 5-6. PSR Field Descriptions
Field
Description
31–0
PSR
GPIO Pad Status bits (status bits). Reading PSR returns the state of the corresponding pad.
Settings:
The I/O multiplexer associated with each bit must be configured for GPIO for the function to affect the state of the pin.
5.3.3.4
GPIO Interrupt Configuration Register1 (ICR1)
The GPIO ICR1 register is a 32-bit register. Each set of 2 bits specifies the interrupt configuration for each
corresponding interrupt line. There is total support for 16 interrupts. Figure 5-7 shows the ICR1 register,
and Table 5-7 shows the register’s field descriptions.
Access: User read/write
0x53FC_C00C GPIO1 (ICR1)
0x53FD_000C GPIO2 (ICR1)
0x53FA_400C GPIO3 (ICR1)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ICR1[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
ICR1[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 5-7. GPIO Interrupt Configuration Register1 (ICR1)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
5-9
General Purpose Input/Output (GPIO)
Table 5-7. ICR1 Field Descriptions
Field
31–0
ICR1
Description
Interrupt Configuration 1 bits. This register controls the active condition of the interrupt function for lines 15 to 0.
Settings:
interrupts (i) 0 to 15, when bits {ICR1[2*i+1],ICR1[2*i]} are as follows:
00 The interrupt i is low-level sensitive.
01 The interrupt i is high-level sensitive.
10 The interrupt i is rise-edge sensitive.
11 The interrupt i is fall-edge sensitive.
5.3.3.5
GPIO Interrupt Configuration Register2 (ICR2)
The GPIO ICR2 register is a 32-bit register. Each set of 2 bits specifies the interrupt configuration for each
corresponding interrupt line. There is total support for 16 interrupts. Figure 5-8 shows the ICR2 register,
and Table 5-8 shows the register’s field descriptions.
Access: User read/write
0x53FC_C010 GPIO1 (ICR2)
0x53FD_0010 GPIO2 (ICR2)
0x53FA_4010 GPIO3 (ICR2)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ICR2[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
ICR2[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 5-8. GPIO Interrupt Configuration Register2 (ICR2)
Table 5-8. ICR2 Field Descriptions
Field
31–0
ICR2
5.3.3.6
Description
Interrupt Configuration 2 bits. This register controls the active condition of the interrupt function for lines 31 to 15.
Settings:
interrupts (i) 0 to 15, when bits {ICR2[2*i+1],ICR2[2*i]} are as follows:
00 The interrupt i+16 is low-level sensitive.
01 The interrupt i+16 is high-level sensitive.
10 The interrupt i+16 is rise-edge sensitive.
11 The interrupt i+16 is fall-edge sensitive.
GPIO Interrupt Mask Register (IMR)
The GPIO IMR is a 32 bit register. Each bit is the interrupt masking bit for each interrupt line. Figure 5-9
shows the IMR register, and Table 5-9 shows the register’s field descriptions.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
5-10
Freescale Semiconductor
General Purpose Input/Output (GPIO)
Access: User read/write
0x53FC_C014 GPIO1(IMR)
0x53FD_0014 GPIO2 (IMR)
0x53FA_4014 GPIO3 (IMR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
IMR[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
IMR[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 5-9. GPIO Interrupt Mask Register (IMR)
Table 5-9. IMR Field Descriptions
Field
31–0
IMR
5.3.3.7
Description
Interrupt Mask bits. This register is used to enable/disable the interrupt function on each of the 32 GPIO pins.
Settings:
For i from 0 to 31, when IMR[i] is as follows:
0 The interrupt i is disabled.
1 The interrupt i is enabled.
GPIO Interrupt Status Register (ISR)
The GPIO ISR is a 32- bit register that functions as interrupt. Each bit indicates whether an interrupt has
occurred. When an interrupt event occurs, the bit in this register is set. The condition for setting of the bit
is determined by the Interrupt Configuration Register (ICR) and the input that satisfies the configuration.
Two wait states are required in read access for synchronization. One wait state is required for reset.
Figure 5-10 shows the ISR register, and Table 5-10 shows the register’s field descriptions.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
5-11
General Purpose Input/Output (GPIO)
Access: User read/write
0x53FC_C018 GPIO1 (ISR)
0x53FD_0018 GPIO2 (ISR)
0x53FA_4018 GPIO3 (ISR)
31
30
29
28
27
26
25
R
22
21
20
19
18
17
16
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w1c
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w1c
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w1c
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ISR[15:0]
W w1c
Reset
23
ISR[31:16]
W w1c
Reset
24
0
w1c
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w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-10. GPIO Interrupt Status Register (ISR)
Table 5-10. ISR Field Descriptions
Field
Description
31–0
IMR
Interrupt Status bits. Bit i of this register is asserted (active high) when the active condition is detected on the GPIO
input and is waiting for service. The value of this register is independent of the value in the IMR register. When the
active condition has been detected, the corresponding bit remains set until cleared by software. Status flags are
cleared by writing a 1 to the corresponding bit position.
5.4
5.4.1
Functional Description
GPIO Function
A GPIO pin can operate as a general-purpose input/output when the IOMUX functions in GPIO mode.
You can independently configure each GPIO pin as either an input or an output using the GPIO Direction
Register (GDIR). When configured as an output (GDIR bit = 1), the value in the data bit in the GPIO Data
Register (DR) is driven on the corresponding GPn pin. When configured as an input (GDIR bit = 0), the
state of the input can be read from the corresponding PSR bit.
5.4.2
5.4.2.1
GPIO Programming
Read Value from Pad
Programming sequence should be as follows:
1. Configure IOMUXC to select GPIO mode.
2. Configure GPIO Direction Register to input.
3. Read value from Data register/Pad Status register.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
5-12
Freescale Semiconductor
General Purpose Input/Output (GPIO)
Pseudo code Description To Read [pad3:pad0] Values:
write sw_mux_ctl_<pad0>_<pad1>_<pad2>_<pad3> , 32’h0x01010101 // SET PADS TO GPIO MODE.
write GDIR[31:4,pad3_bit,pad2_bit, pad1_bit, pad0_bit,] 32’hxxxxxxx0 // SET GDIR TO INPUT.
read DR
// READ PAD VALUE FROM DR.
read PSR
// READ PAD VALUE FROM PSR.
NOTE
While GPIO direction is set to input (GDIR = 0), a read access to DR does
not return DR data. Instead, it returns the PSR data, which is the
corresponding pad value.
5.4.2.2
Write Value to Pad
Programming sequence should be as follows:
1. Configure IOMUXC to select GPIO mode.
2. Configure GPIO Direction Register to output.
3. Write value to Data Register (DR).
Pseudo code Description To Drive 4’b0101 on [pad3:pad0]:
write sw_mux_ctl_<pad0>_<pad1>_<pad2>_<pad3> , 32’h00000000
// SET PADS TO GPIO MODE.
write GDIR[31:4,pad3_bit,pad2_bit, pad1_bit, pad0_bit,] 32’hxxxxxxxF // SET GDIR TO OUTPUT.
write DR, 32’hxxxxxxx5
// WRITE PAD VALUE TO DR.
read_cmp PSR, 32’hxxxxxxx5
// READ PAD VALUE FROM PSR ONLY.
NOTE
While GPIO direction is set to output, you can verify real pad value only
through PSR.
5.4.3
Interrupt Control Unit
In addition to the general-purpose input/output function, the edge-detect logic in the GPIO peripheral
reflects whether a transition has occurred on a given GPIO signal that is configured as an input (GDIR bit
= 0). The GPIO signal transition is reflected in the GPIO ICR registers. The GPIO ICR registers enables
to configure each interrupt input to its sensitivity case (low-to-high transition; high-to-low transition; low;
high).
The interrupt control unit is built of 32 interrupt control sub units. Each sub unit handles a single interrupt
line.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
5-13
General Purpose Input/Output (GPIO)
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
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Freescale Semiconductor
Chapter 6
Debugging the i.MX31 and i.MX31L
The i.MX31 and i.MX31L debug features are the enablers for hardware/software (HW/SW) debug and
validation of the silicon, either on an evaluation board, customer application board, or even a closed or
opened radio device.
6.1
Overview
Debugging is used to identify and isolate causes of failure when running HW and SW in real applications.
The source of failure could be the SW or HW (a race condition, for example).
The i.MX31 and i.MX31L debug hardware also supports system profiling. System profiling is used to
improve overall system performance by identifying optimal system configurations.
Because of the multi-core nature of the i.MX31 and i.MX31L applications processors, all internal cores
have their own dedicated debug features and ports to enable parallel debug of the MCU (ARM11) core and
peripherals, the Smart Direct Memory Access (SDMA) core. The debug architecture of the i.MX31 and
i.MX31L is therefore composed of the individual cores’ debug components as well as shared debug
components.
The aspects with which the individual cores share resources are as follows:
• The JTAG controller port, which is used to communicate with each of the multiple cores.
• The ECT module, which is used to control cross trigger events among the multiple cores.
In addition, secure JTAG options will be provided to protect debug resources from attacks by unauthorized
users. The secure JTAG design will prevent the debug architecture from compromising security.
Figure 6-1 shows a block diagram of the i.MX31 and i.MX31L, along with the debug-related I/O.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
6-1
Debugging the i.MX31 and i.MX31L
JTAG
Port
DE
pin
ETM
ATP
GPIO
Signals
i.MX31/i.MX31L
Figure 6-1. i.MX31 and i.MX31L Debug Port Scheme
6.1.1
Features
The i.MX31 and i.MX31L microprocessors provide a full set of features for multi-core debug. This section
gives an overview of these features and the interconnections between different modules.
The overall debug system for the i.MX31 and i.MX31L is divided as follows:
• Multi-core debug support is provided by multi-core debuggers via the System JTAG Controller
(SJC) and the extensive cross trigger support of the Embedded Cross Trigger (ECT) module.
• Static debug support is provided via the System JTAG Controller (SJC) and appropriate accesses
to ICE/OnCE resources on the cores. Support is provided for debug start/stop, single-step, break
points, access to CPU and system resources.
• Non-intrusive real-time instruction and data tracing is supported on the MCU (ETM11) processor.
• ROM patching is supported on the MCU processor. Patching provides the means to effectively
replace data in a ROM memory location. It can also enable the SW to execute different instructions
from those residing in ROM.
• Multiplexing of internal signals is possible using the IOMUX to chip IOs. Critical signals can be
routed to the top-level SoC pads for external visibility.
• Limited time stamping support in the MCU domain is facilitated by use of three counters within
the PMU of the ARM11 processor, used in conjunction with other resources such as the ETM and
the ECT module.
• Performance profiling is supported for the MCU domain. For example, it is possible to count the
number of processor stalls, L1 cache hits, L2 cache misses, or external memory accesses that have
occurred. Profiling data is accessible by the SW and can be used to optimize system configurations
for optimal performance.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
6-2
Freescale Semiconductor
Debugging the i.MX31 and i.MX31L
The remainder of this chapter presents more details of the various debug partitions within the i.MX31 and
i.MX31L:
• MCU domain (ARM11)
• SDMA domain
• System JTAG Controller
• I/O muxing scheme
• Embedded Cross Trigger configuration
6.2
AP Debug Support
This section describes the debug features specific to the applications processor ICs.
Figure 6-2 is a block diagram of the ARM11 Platform. Debug and performance profiling related
components are indicated in blue dashed lines.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
6-3
Debugging the i.MX31 and i.MX31L
Embedded Trace Module (ETM11)
and ETM Trace Port
ARM1136JF-S: ICE,
CP15, PMU
L2 CACHE
DATA MEMORY
128 (256) Kbyte
L2 Test and Debug
Register
l2cc_max_only
FPU
ETM11
16k I$
MMU
256
16k D$
L2MUX (2)
ARM1136JF-S
ETM
64-bit
IF_AHB
DR_AHB
S0
L2CC
M0
S1
TAG
M1
DW-AHB
S2
L2CC0
L2CC1
VALID
AVIC
P_AHB
DIRTY
JTAG
sync_jtag
M2
64-bit
HSELRS1/S2
EVENTS
AHBDIV2 (2)
L2 Cache
Profiling
JSYNC
JTAG/SYNC
CLKS & RST
JTAG
Resets
a11p_clk_off
evtmon_int
EVTMON
CLOCK OFF
32-bit
ETB11
4 Kbyte
Trace
Buffer
ETM
Trace
Port
INT’s
AVIC
int[63:0]
gated_clocks
IPBus
CLKCTL
4 Kbyte Embedded
Trace Buffer
gp_control
MAX0
MAX1
S0
S1
Misc. Debug
I/O
MAX
CTI0
Embedded X-trigger
6 x 5 (x32)
M0
M3_HADDR
S3
M1
M2
ROMPATCH
Alternate
Bus
Masters
MAX2
S2
PAHBMUX
ALT_BM0
ALT_BM1
ALT_BM2
M3
M4
MAXMUX(2)
IPBusA
AIPS A
ROM
ROMC
S4
Peripherals
IPBusB
AIPS B
Peripherals
M5
RAMC
boot_ext
SRAM
IPBus
ext_boot_addr[31:2]
(x32)
Multi-Core Cross Trigger
over_ride, patch_data[31:0]
MCU ROM Patch
Figure 6-2. ARM11 Platform Debug Features (Highlighted in Blue)
All of the debug components shown can be accessed via JTAG or software running on the ARM11 core.
The ETM is accessed through the coprocessor interface, and the ETB, ECT, and EVTMON modules reside
on the IP Bus as memory mapped peripherals. The ROM Patch module resides on the peripheral AHB bus.
6.2.1
ARM1136JF-S
The ARM1136JF-S processor has robust support for debug and performance profiling, including:
• Dedicated ARM11 core, including ICE logic support by debuggers
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
6-4
Freescale Semiconductor
Debugging the i.MX31 and i.MX31L
•
•
•
•
•
•
ICE-enabled ARM11 processor resource access; speeds system memory access
Control of breakpoints and watchpoints
Data communication channel between ARM core and host debugger via JTAG
Control of debug status
CP15 register for debugging the MMU, I, and D L1 cache, and TLB
Performance Metrics Unit (PMU) used for system profiling and debug
6.2.1.1
PMU, L1 Caches, MMU, and TLB Debug Support via CP15 Registers
One of the first resources software programmers often use for debugging an ARM1136JF-S system are the
processor’s CP15 registers. The CP15 registers and associated logic have been designed specifically to
support Memory Management Unit (MMU) debug, Translation Lookaside Buffer (TLB) debug and L1
instruction and data cache debug.
6.2.1.2
Performance Metrics Unit (PMU)
The Performance Metrics Unit (PMU) is part of the ARM1136JF-S processor. It includes four registers,
which are implemented as part of the CP15 register:
• Performance Monitor Control Register (PMNC)
• Count Register 0, PMN0
• Count Register 1, PMN1
• Cycle Count Register, CCNT
The Performance Monitor Control Register controls the operation of all three counter registers. The PMN0
and PMN1 registers are 32-bit counters that can be programmed to count selected EVNTBUS (Table 6-1)
occurrences. The cycle count register (CCNT) is a 32-bit counter used to count core clock cycles. All three
counters can be enabled to generate interrupts on overflow.
System performance monitoring uses a series of system events to profile system performance. These
events are described in Table 6-1.
Table 6-1. EVNTBUS Signals Used For Performance Modeling
Event Signal
Description
EVNTBUS[0]
Instruction cache miss to a cacheable location. This requires a fetch
from external memory.
EVNTBUS[1]
Stall because instruction buffer cannot deliver an instruction.
This could indicate an Instruction Cache miss or an Instruction
MicroTLB miss. This event occurs every cycle in which the condition is
present.
EVNTBUS[2]
Stall because of a data dependency. This event occurs every cycle in
which the condition is present.
EVNTBUS[3]
Instruction MicroTLB miss.
EVNTBUS[4]
Data MicroTLB miss.
MCIMX31 and MCIMX31L Applications Processors Reference Manual, Rev. 2.4
Freescale Semiconductor
6-5
Debugging the i.MX31 and i.MX31L
Table 6-1. EVNTBUS Signals Used For Performance Modeling (continued)
Event Signal
EVNTBUS[5]
Description
Branch instruction executed.
Note: The branching action may or may not have changed program
flow.
EVNTBUS[6]
Fixed at 0 in the current RTL revision.
EVNTBUS[7]
Branch miss-predicted.
EVNTBUS[8]
A valid instruction was executed (including either a branch phantom or
a non-phantom instruction)
EVNTBUS[9]
Both a branch phantom and non-phantom instruction were executed in
this cycle (for example, 2 instructions were executed).
EVNTBUS[10]
Data cache was accessed, not including internal cache operations.
This event occurs for each non-sequential access to a cache line, for
cacheable locations.
EVNTBUS[11]
Data cache access, not including cache operations.
This event occurs for each non-sequential access to a cache line,
regardless of whether or not the location is cacheable.
EVNTBUS[12]
Data cache miss, not including cache operations.
EVNTBUS[13]
Data cache Write-Back.
This event occurs once for each half line of four words that are written
back from the cache.
EVNTBUS[14]
Software changed the PC.
This event occurs any time the PC is changed by software and there is
not a mode change. For example, a MOV instruction with PC as the
destination triggers this event. Executing an SWI from User mode does
not trigger this event, because it incurs a mode change.
EVNTBUS[15]
Same as bit 14, but this bit indicates if it was an executed branch
phantom
EVNTBUS[16]
Main TLB miss.
EVNTBUS[17]
External memory request (Cache Refill, Non-cacheable,
Write-Through, Write-Back).
EVNTBUS[18]
Stall because the Load Store Unit request queue is full.
This event takes place each clock cycle in which the condition is met.
A high incidence of this event indicates the BCU is often waiting for
transactions to complete on the external bus.
EVNTBUS[19]
The number of times the Write Buffer was drained because of a Drain
Write Buffer command or Strongly Ordered operation.
This signal will go high each time the write buffer needs to be drained.
The PMU counters can be used to generate an interrupt (pmu_irq). The PMU resources can then be
accessed through an interrupt handler, and the resulting register reads can be made visible on the ETM11
trace port. One can also get periodic interrupts by using the cycle counter register of the PMU. When
entering the interrupt routine, the core can read the counters, and using the address comparator, an ETM
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packet can be generated that includes the PMU counter value. See Section 6.2.7, “Interrupts” for more
details.
6.2.2
Embedded Trace Macrocell (ETM11)
The ARM1136 platform includes the ETM11 module, which supports real-time instruction and data
tracing via ETM version 3.1. The ARM11 Platform enables access to the ETM registers via software, in
addition to using the JTAG.
Tracing is controlled by specifying the exact set of triggering and filtering resources required for a
particular application. Resources include four pairs of address comparators, two data comparators, eight
address decoders and two counters, a three-stage sequencer, and four external inputs EXT_INT[3:0].
Three of those external triggers comes from the ECT/ARM Cross Trigger Interface (CTI) and one is
accessible at the chip-level pads through IOMUX programing (for example, muxed with other signals on
the pad).
The EXTIN inputs of ETM are connected to the CTI of the ARM11 Platform, but one can use an IO pad
via the IOMUX to trigger the input of ECT and then trigger the CTI -> ETM through EXTIN.
The ETM includes two FIFOs (each holding 69 bytes) to store the compressed trace information. To
prevent overflow, the user can program a FIFO full level register to behave as follows: When the FIFO is
nearly full, the data trace is suppressed but instruction tracing is permitted to continue.
Two counters are located inside the ETM and their values can be traced. The counters can count events,
including the EXTIN signals. The debugger tool can then reconstruct the global timing information. ETM
can generate a debug request upon triggers.
ETM also has two outputs (EXTOUT) that are asserted to echo a trigger; those go to the CTI to activate
or deactivate other debug functions in the i.MX31 and i.MX31L. These two bits are connected to the
ARM11 core through the ECT to be monitored by the PMU.
The ETM also supports JAVA debug. The trace tool indicates when the core enters or exits JAVA state. The
ARM tool then uses this information to calculate the percentage of time or cycles spent in and out of JAVA
state, which enables one to quantify JAVA efficiency. In addition, the ARM11 “java_mode” signal can be
muxed out to a chip pin for monitoring.
6.2.2.1
ETM11 Trace Port
The ETM11 module provides trace information to an external debugger through the ETM Trace Port
interface at the SoC level.
The following signals are part of the ETM trace port interface:
• TRACECLK: clock signal, running at ARM_CLK/4 or ARM_CLK/8. Clock division is controlled
by programming a register in the ETM.
NOTE
When ARM_CLK:TRACE_CLK ration is 1:1, TRACECLK is not used and
the trace information automatically goes to the ETB.
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•
•
TRACEDATA[n-1:0]: data bus, bus width (n) is configurable by a programming register in the
ETM. The maximum value of n in the i.MX31 and i.MX31L is 23.
TRACECTL: control signal used in conjunction with TRACEDATA[0] to signal the debugger that
a valid trace is available. See Table 6-2 for the decode information.
Table 6-2. Trace Signals Decode
TRACECTL
TRACEDATA[0]
Status
1
0
Trigger
1
1
Valid data trace
0
X
Do not capture current info
With ETM V3.1, data and control are updated on the rising and the falling edges of the TraceCLK signal
so there is no real difference in terms of frequency of the CLK, DATA, and CTL signals; DDR is always
enabled.
The ETM11 supports 3 port modes: dynamic, 1:2, and 1:4.
Dynamic mode is used for on-chip trace capture using the 4 Kbyte embedded trace buffer. When it is used,
TRACECLK does NOT toggle, and the ETB11 should be setup to capture the trace data. The ETB11
captures the data on the rising edge of the ARM processor clock.
1:2 and 1:4 mode refer to the trace-port to arm clock ratio, not the TRACECLK to ARM clock ratio.
Because the trace-port uses double data rate (clocking on both edges of TRACECLK) the TRACECLK
ratio is actually twice the trace-port ratio (for example, 1:2 uses a 1:4 TRACECLK and 1:4 uses a 1:8
TRACECLK).
See Figure 6-3 and Figure 6-4 for trace port timing in 1:2 and 1:4 modes.
ARMCLK
TRACECLK
TRACEDATA
Figure 6-3. 1:2 Port Mode
ARMCLK
TRACECLK
TRACEDATA
Figure 6-4. 1:4 Port Mode
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6.2.3
Embedded Trace Buffer (ETB11)
The ARM11 Platform includes a 4-Kbyte embedded trace buffer (ETB11) to internally store the real-time
trace data generated by the ETM11 module. The ETM writes 32 bits to the ETB at ARM11 processor clock
speed. The ETB is memory mapped (IP Bus), but can also be accessed via JTAG. The memory array of the
ETB is a compiled RAM. The ETB11 memory may be used by software as general purpose scratch
memory when the ETM11 is not using it for debug. However, to prevent Endianness issues, only word
accesses are enabled. Accesses to the ETB over the IP bus takes 7 hclk (‘per_clk’) clock cycles for write
and read.
6.2.4
L2CC Debug Support
The L2CC design includes Register 15 for test and debug. This register enables the contents of the L2
cache to be read/written and forces specific behavior required for debug. The register supports
mechanisms to force all cacheable accesses to be treated as write-through (no write-allocate) as well as
preventing the cache from updating when performing a linefill on a miss.
6.2.4.1
ARM11 L2CC Event Monitor (EVTMON)
The L2CC event monitor (EVTMON) has profiling capabilities for the L2 cache. It is memory-mapped on
IP Bus interface. It includes four 32-bit counters and 9 different events from the L2 cache are supported,
as shown in Table 6-3. For more details, see Chapter 14, “L2 Cache Controller (L2CC).”
Table 6-3. ARM11 L2 Cache Events To EVTMON
Event Name
Description
BWABT
Buffered write abort
CO
Castout of a line from the L2 cache
DRHIT
Data read hit
DRREQ
Data read request
DWHIT
Data write hit
DWREQ
Data write request
IRHIT
Instruction read hit
IRREQ
Instruction read request
WA
Write allocate (write caused a linefill to the L2 cache)
An interrupt (evntmon_interrupt) can be generated on counter overflow conditions or on an increment. See
Section 6.2.7, “Interrupts” for details.
There is no direct link from EVTMON counters to ETM but one can access the counter values through
ETM by using interrupt routines. Refer to Section 6.2.1.2, “Performance Metrics Unit (PMU)” for more
details.
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6.2.5
Embedded Cross Trigger Interface (ECTCTI)
For details on the ECT module, see Section 6.3, “Embedded Cross Trigger (ECT).”
6.2.6
Debug Support Via Critical Signal Visibility
In addition to I/O signals required for functionality, several internal signals have been brought to the
top-level of the ARM11 Platform specifically to support debug. These signals, along with any signal on
the ARM11 Platform top-level, can be used by external logic or muxed out to an SoC pad, to gain visibility
and assist in debugging the system. These signals are summarized in Table 6-4.
Table 6-4. ARM11 Platform Debug Centric Signal Visibility
Signal Name
Description
Visibility Details
standbywfi
ARM1136JF-S is in standby mode, waiting for an
interrupt.
Visible on pads via OBS_INT register
of IOMUXC
wfipending
ARM1136JF-S output to ETM on execution of
Wait-for-Interrupt instruction. ETM must drain FIFO
before shutting off clocks. standbywfi asserts after
FIFO is drained.
java_mode
Internal ARM1136JF-S J-bit (flopped by arm_clk)
thumb_mode
Internal ARM1136JF-S T-bit (flopped by arm_clk)
fiq
AVIC fast interrupt to ARM1136JF-S
Not connected in the i.MX31 and
i.MX31L
irq
AVIC normal interrupt to ARM1136JF-S
Not connected in the i.MX31 and
i.MX31L
evtmon_interrupt
L2CC Event Monitor Interrupt
Visible on pads via OBS_INT register
of IOMUXC
etb_acqcomp
Embedded Trace Buffer Acquisition Complete
etb_full
Embedded Trace Buffer Full
pmu_irq
System Metrics Module Interrupt
Connected to ECT, can be visible on
pads via programming of ECT to
either display ctm_lines or via
cti_trig_out_1[5:2] connected to
IOMUX.
evntbus[19:0]
6.2.7
System Metrics Module Event Bus
Visible on pads via alternate mode
(refer to ARM1136JF-S Technical Reference Manual) settings of IOMUX.
Interrupts
The ARM11 Platform has several interrupt outputs:
• pmu_irq
• evtmon_interrupt
• ect_irq[1:0]
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Each of these interrupts are directly or indirectly tied to one or more of the a11p_int[63:0] inputs at the
SoC level. In the i.MX31 and i.MX31L, the assignments are as follows:
Table 6-5. Interrupt Source Of Debug Signals
Interrupt Source
Signal Source
i.MX31/i.MX31L
pmu_irq and evtmon_interrupt
ect_irq[0]& ect_irq[1]
6.2.8
General Purpose Timer (GPT)
The i.MX31 and i.MX31L SoC includes the General Purpose Timer (GPT) module mapped to the MCU
peripheral space. The GPT 32bit timer can be used during debug and profiling sessions according to
debug/profiling specific needs. Programming of the GPT is done in debug session by executing ARM
commands via JTAG interface.
6.3
Embedded Cross Trigger (ECT)
This section provides a summary of the Embedded Cross Trigger (ECT) debug scheme. An overview of
the IP is given first, followed by specific i.MX31 and i.MX31L integration details. The Cross Trigger
Interface (CTI) trigger signals are listed for the each CTI. Finally, some debug use cases using the ECT
are presented.
6.3.1
ECT Overview
The ECT scheme is based on the ECT debugging hardware from ARM Ltd. The ECT is composed of
three Cross Trigger Interfaces (CTIs) and one Cross Trigger Matrix (CTM). The ECT is key in the
multi-core and multi-IP debug strategy. The outcome is a SW-controlled debug signal matrix that receives
many signals from various sources (for example, cores and peripherals) and propagates/routes them to the
different debug resources of the SoC. As seen in previous sections, those debug resources can include
profiling capabilities, real-time trace (trace enabled or disabled), triggers, Soc level multiplexing, and
debug interrupts.
The main advantages of using the ECT are as follows:
• Standardized debug scheme, in line with ARM RealView debugger, simplifies integration with
ARM debug tools.
• Within a single debug domain, all the IPs can share the same debug resources. There is no need to
duplicates counters or real-time trace resources. One trace port can be used with one tool to track
the activity of the core and its peripherals.
As the ECT should only be used during debug sessions, it is off (disabled) by default.
The ECT features are enabled by enabling the individual CTIs. It is only allowed in supervisor mode, after
having presented a suitable key to the CTI’s CTILOCK register (by writing 0x0ACCE550). Hardware
input from the SJC module prevents use of the all CTIs based on the security mode of the IC. See Table 6-6
for details.
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Table 6-6. ECT Functionality Depending on the i.MX31 and i.MX31L Security Mode
Security Mode
Security level
ECT Functionality
No Debug
Maximal
Use of ECT scheme is prevented by hardware.
Secure JTAG
High
Proper authentication of challenge-response sequence must be
carried, prior to enabling the ECT.
JTAG Enable
Low
ECT is enabled by SW activation.
SCC JTAG
Un-secure
ECT is enabled by SW activation.
Figure 6-5 illustrates the construction of the ECT and how it interfaces with the CTI embedded in the
ARM11 Platform.
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Trigger
outputs
Trigger
inputs
IPS
interface
8
8
ECT
AHB IF
OR
EXTENDED_CTI 1
4
control reg
mapping
8 ECT_CTI
8
IPS to AHB
WRAPPER
4
Channel interface 1
CTM
IPS to AHB
IPS to AHB
WRAPPER
Trigger 8
outputs
8
4
ECT_CTI
8
mapping
OR
Channel interface 2
control reg
8
Channel interface 0
Trigger
inputs
IPS
interface
AHB IF
AHB IF
4
control reg
8 Trigger
4
8
ECT_CTI
4
OR
mapping
8
WRAPPER
IPS
interface
EXTENDED_CTI 2
inputs
8 Trigger
outputs
EXTENDED_CTI 0
Channel interface 3
4
4
ARM11 Platform
WRAPPER
Trigger
outputs
8
Trigger
inputs
8
IPS to AHB
8 ECT_CTI
AHB IF
mapping
8
control reg
OR
ARM_CTI
IPS
interface
Figure 6-5. ECT Block Diagram
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6.3.1.1
Cross Trigger Interface (CTI)
The CTI has eight inputs (trigger inputs) and eight outputs (trigger outputs) to the IC and four inputs and
outputs to the CTM (channel triggers). The eight trigger inputs can come from a wrapper or from an IP or
a core directly. Figure 6-6 shows the block diagram of a single CTI.
8 trigger inputs
CTI
8 trigger outputs
4
8
4
HS
From IP/Cores/wrapper
HS
path1
To CTM
4 channel triggers
APPTRIG
path2
path3
AND
4
OR
HS
HS
8
To IP/Cores
From CTM
Figure 6-6. CTI Block Diagram
Each trigger input can be connected to any of the channel triggers to the CTM (path1) and/or propagate
back to the eight trigger outputs (path2). The four channel triggers of the CTM to the CTI can be mapped
to any of the eight trigger outputs of the CTI (path3). All of this is fully programmable using
memory-mapped registers.
The muxing with APPTRIG shown on the input path is for software triggering support; by writing to some
of the CTI registers, one can generate a trigger by software/assert one of the four channel triggers to CTM
or/and one of the eight trigger outputs. A pulse can be generated by writing to the APPPULSE register or
one can assert by writing to APPSET and then de-assert by writing to APPCLEAR.
The CTI supports four classes of trigger inputs:
• Conditioned—Keeps the output active until an acknowledge is received.
• Level/pulse—Used when the trigger destination is level-sensitive, the signal is active for only one
clock cycle.
• Sticky—Trigger is active until the source is cleared.
• NOACK—Used when the output follows the input trigger and does not require an acknowledge.
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The CTI includes handshaking/synchronization mechanism (represented as HS in Figure 6-6) on the eight
trigger inputs/eight trigger outputs and 4 + 4 channel input and output triggers. This handshake mechanism
is enabled at integration level to support the various classes of signals, clock domains, and frequencies.
6.3.1.2
Wrapper On CTI
The wrapper placed in front of the CTI is optional, depending on the nature of the signals connected to the
input of CTI. The event signals in the ECT are all transmitted as a binary level, with “one” being active,
and “zero” inactive.
The wrapper is used as a handshaking mechanism as well as for synchronization when necessary,
especially in the case of multiple clock domains on trigger inputs or outputs or when timing is difficult to
meet.
6.3.1.3
Cross Trigger Matrix (CTM)
The CTM logic serves as router logic between the system CTIs. The CTM consists of four interfaces of
four inputs and four outputs each, referred to as the channel triggers.
Figure 6-7 presents the high-level CTM block diagram, while Figure 6-8 provides the logic details for the
lower bit of the channel trigger signals.
The CTM includes handshake hardware (similar to the one used in the CTI) on its inputs and outputs to
manage various clock domains, clock frequencies, and types of signals.
One can assign any trigger input to any trigger channel and to any trigger output. However, there are some
timing and signal class considerations to take into account. For that reasons connectivity of ECT should
follow the ECT design specifications. The ECT module provides additional visibility to the internal CTM
logic. To track activity on each line, an OR4 function of the all four channel inputs is performed. These
four system lines are available at the ECT boundaries for silicon debugging.
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From CTI or other CTM
bit3
bit3
interface #2
4
To CTI or other CTM
bit3
To CTI or other CTM
4
4
To CTI or other CTM
interface #1
bit3
interface #3
4
From CTI or other CTM
CTM
interface #0
From CTI or other CTM
4
4
4
To CTI or other CTM
4
From CTI or other CTM
Figure 6-7. CTM Logic Bit Diagram
6.3.1.4
Clock Considerations
Each CTI has its own clock for its bus interface and memory-mapped registers but it also has its own clock
for all the triggering. The CTM also has its own clock for handshaking logic (synchronization and flip-flop
acknowledgement). Obviously one needs to properly use the wrapper/HS logic to manage the signals
crossing those clock domains (including wrappers for CTI inputs and outputs).
When a processor clock is stopped (for example, waiting for an interrupt), the corresponding CTI can
receive an event from the CTM. When the CTI clock is the same domain as the subsystem and the
handshaking logic is not bypassed, the CTM keeps the signal active until an acknowledge is received
(which only occurs when the clock is started again). In this situation, out-of-date events on the core can
occur. This does not prevent the channel from being used by other processors.
However, if the CTI clock differs from the local processor clock (for example, gated differently), it is
possible for the CTI to raise an event to the core using a trigger output while the processor clock is off.
This generates a debug interrupt and wakes the core so the debug features connected to the CTI trigger
outputs are available again.
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