Hewlett-Packard 10342B Bus Preprocessor User Manual

HP 10342B Bus Preprocessor
(H?1650A/51A and HP16510A)
Operating Manual
7) Paciano
2e
Bus Preprocessor
Operating Manual
HP 10342B
Bus Preprocessor
for the HP 1650A, HP 1651A,
and HP 16510A Logic Analyzers
Гл HEWLETT
PACKARD
O Copyright Hewlett Packard Company 1987
Manual Set Part Number 10342-90912
Microfiche Part Number 10342-90812 Printed in U.S.A November 1987
Printing History First Edition - November 1987 Printed in U.S.A,
Product Warranty
Limitation of
Warranty
This Hewlett-Packard product has a warranty against defects in
material and workmanship for a period of 1 year from date of
shipment. During warranty period, Hewlett-Packard Company will, at
its option, either repair or replace products that prove to be defective.
For warranty service or repair, this product must be returned to a
service facility designated by Hewlett-Packard. However, warranty
service for products installed by Hewlett-Packard and certain other
products designated by Hewlett-Packard will be performed at Buyer's
facility at no charge within the Hewlett-Packard service travel area.
Outside Hewlett-Packard service travel areas, warranty service will be
performed at Buyer's facility only upon Hewlett-Packard's prior
agreement and Buyer shall pay Hewlett-Packard's round trip travel
expenses.
For products returned to Hewlett-Packard for warranty service, the
Buyer shall prepay shipping charges to Hewlett-Packard and
Hewlett-Packard shall pay shipping charges to return the product to
the Buyer. However, the Buyer shall pay all shipping charges, duties,
and taxes for products returned to Hewlett-Packard from another
country.
Hewlett-Packard warrants that its software and firmware designated by
Hewlett-Packard for use with an instrument will execute its
programming instructions when properly installed on that instrument.
Hewlett-Packard does not warrant that the operation of the instrument,
software, or firmware will be uninterrupted or error-free.
The foregoing warranty shall not apply to defects resulting from
improper or inadequate maintenance by the Buyer, Buyer-supplied
software or interfacing, unauthorized modification or misuse, operation
outside of the environmental specifications for the product, or improper
site preparation or maintenance.
NO OTHER WARRANTY IS EXPRESSED OR IMPLIED.
HEWLETT-PACKARD SPECIFICALLY DISCLAIMS THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Exclusive
Remedies
Assistance
Certification
Safety
THE REMEDIES PROVIDED HEREIN ARE BUYER'S SOLE AND
EXCLUSIVE REMEDIES. HEWLETT-PACKARD SHALL NOT BE LIABLE
FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, WHETHER BASED ON CONTRACT,
TORT, OR ANY OTHER LEGAL THEORY.
Product maintenance agreements and other customer assistance
agreements are available for Hewlett-Packard products.
For assistance, contact your nearest Hewlett-Packard Sales and
Service Office. Addresses are provided at the back of this operating
manual,
Hewlett-Packard Company certifies that this product met its published
specifications at the time of shipment from the factory.
Hewlett-Packard further certifies that its calibration measurements are
traceable to the United States National Bureau of Standards, to the
extent allowed by the Bureau's calibration facility, and to the calibration
facilities of other International Standards Organization members.
This product has been designed and tested according to International
Safety Requirements. To ensure safe operation and to keep the
product safe, the information, cautions, and warnings in this operating
manual must be heeded.
Table of Contents
E
Introduction
Ci T———.L Lo
Chapter 1: General Information ................e.errrrrricienee e IIA 1-1
Introduction ............eoeeeeeceerdorecsco crecer rear caer en ene 1-1
HP-IB RAS 1-1
RS-232-C/CCITT V.24 ............ 00000000000 eee 1-1
RS-449 eee ea 1-2
Operating Characteristics ............... iil 1-2
Equipment Supplied .........co ii KR eee een ee 1-6
Minimum Equipment Required ............... iin 1-6
E
Chapter 2: Hardware Information .................... BU 2-1
Introduction ...........eoreeerírerrreriereerenr recae a rer0irce 6 2-1
Initial Inspection .... ree 2-1
Power Requirements .............._e.eeceecreoerorcsrereernerer 2-1
Operator Maintenance ..............eceeererecerreoccorereer e. 2-2
Testing and Troubleshooting ................eoeerrerrerererre. 2-2
Replaceable Parts .................eeereccessrioererrorerrrereec0 2-3
бспетанНс$ ............... ee eee ea 2-3
Serial Input Circuits .............._eeeeeerecercocerrrerer e 2-4
Serial Timing Connections ........... cco viii, 2-5
E
Chapter 3: Software Information ...................eeerriirerriie IZ 3-1
Introduction ooo eeere Aer 3-1
Copying Files ...........000400 01e aa aa aa ana a eee a aa a ae a aan 3-2
HP 1650A/51A ee 3-2
HP 16510A ea 3-2
Table of Contents (Continued)
р
Chapter 4: HP-IB Bus Preprocessing ............oeeeeeeenenneaeeeiniameennes 4-1
Introduction ........e..e_eeoéeeeccceorcerarerrecererr ear rearrec— 4-1
Preprocessor Function ............ coin e 4-1
Equipment Required ...........cooiiii A. 4-1
Setting Up the HP 10342B ........... coon 4-2
Connecting the HP 10342B to the HP 102696 ..................... 4-3
Setting Up the HP 10342B Front Panel ..................ee.rm..... 4-5
Connecting to the HP 10269C .......0.000000001 ae aan nas e sens 4-5
Setting Up the System ............ ooo канал лннннеоо 4-6
Setting Up the Analyzer fromthe Disc ................... cons 4-6
Accumulating Data ....... coo KK eee 4-7
Signal Connections ........... coi KK ea ae see ere ea et 4-7
Clocks LL LL a aa aa ae 49
DAV ..................., ee eee a a a ae A 4e 88 1 ss ee a ea Na 00e 4-9
Parallel Poll... eae 4-9
Status (STAT) LINES .... oo NEE 4-10
Cycle LINES... oii EHER a se ee aa aa ee 4-10
Address (ADDR) o.oo ee 4-10
Setting Up the Analyzer for Timing Analysis ...................... 4-11
E
Chapter 5: RS-232-C/V.24 Bus Preprocessing ................oooiveieieeeiens 5-1
Introduction .......020200100 00 ae Ad A A ea 5-1
Preprocessor FUNCtion ............. o.oo ere 5-1
Equipment Required .............cooiii 5-2
Setting Up the HP 10342B .............. oii EEK 5-2
Connecting the HP 10342B to the HP 102696 ..................... 5-4
Setting Up the HP 10342B Front Panel ........................00n. 5-6
Connecting to the HP 10269C ............. cc oii t, 5-7
Setting Up the System ........ iii EHE 5-7
Setting Up the Analyzer from the Disc ..... PE 5-8
Accumulating Data ..............eéeesresirrerirerrerrer re 5-8
Signal Connections ...............r.rieevererevrererrnre E 5-8
Clock oot a aa 5-10
Table of Contents (Continued)
E
Status Byte ..........e_eeccoreeriereererrereiereerr e ere ree 5-10
Address (ADDR) ................eeer02rreerireerrreeeerr ere A 5-11
Mnemonics ............oeeerrrresererrerverenrerecrerar recaen 9-11
Sync Characters ................eee_erecerrececererrrore cres 5-12
Block Check Characters ......... cco iii iii, 5-14
Setting Up the HP 1650A or HP 16510A for Timing Analysis ....... 9-14
Setting Up the HP 1651A for Timing Analysis ..................... 5-15
Timing Signals Lo ee 5-16
E
Chapter 6: RS-449 Bus Preprocessing ..............e......rrecereriiermeAs 6-1
Introduction ........... o. oeeererireorerrarer erre enero 6-1
Preprocessor Function ................oereecerereerreerrer A 6-1
Equipment Required .....................ee...ererrerrerererrrAA A 6-2
Setting Up the HP 10342B ..........00000000 0e ane se ae ea aa eee 00 6-2
Connecting the HP 10342B to the HP 10269G ..................... 6-4
Setting Up the HP 10342B Front Panel ................... coon 6-6
Connecting tothe HP 10269C ............... coin, 6-7
Setting Up the System ................ RAA renoecracene, 6-7
Setting Up the Analyzer from the Disc ..............e..exreserevao 6-8
Accumulating Data ...........o EE 6-8
Signal Connections ......... coo ee 6-8
Glock ovine FUTUR OS 6-10
Data A AS 6-10
Status Byte ....... ee 6-10
Address (ADDR)... coi eee sea a a ae a a ee eee a eee 6-11
Sync Characters ..........00200000 0e ea ane see eee ae eee a eee eue 6-11 _
Block Check Characters .......... ccm iii, 6-13
Setting Up the HP 1650A or HP 16510A for Timing Analysis ....... 6-14
Setting Up the HP 1651A for Timing Analysis ..................... 6-15
TIMING Signals .......o i A 6-16
Table of Contents (Continued)
E
Appendix A: HP-IB Overview .............eeeeeecerrreriicareereer mentre. A-1
Introduction ..............ocJecer2eerrerericer aer rre Tee A A-1
The HP-I1B ...............es0s0rerverreorrrecreraroreresrre rre. A-1
Interface Management LINES... Herrn A-3
Handshake Lines . o.oo viii iii ieee ieee A-4
I
Appendix B: Serial Interface Comparisons ..................es.rrerreeeeeee.s B-1
Introduction ..........eeoeoee.eecrccecrerier rene RRA B-1
E
Appendix C: RS-232-C/CCITT V.24 Overview .................r-iiriiiieecerees C-1
Introduction .......... JU i, C-1
The RS-232-C/CCITT V.24 ................0000e000erere AA C-i
Mechanical +. teeter C-2
Electrical 110012200004 see a ee eee ae ee a eee С-4
rr
Appendix D: RS-449 and RS-422 Overview ...................0000000000ererre D-1
Introduction 000000004055 sea ea se sa eee eee ee ere D-1
The RS-449/RS-422 LL. 0200 aan na eee D-1
Mechanical and Functional ...........00+00000 5 sea eee ananas eee D-2
Electrical votre erre D-2
E
Appendix E: Using the HP 10342B with other CPU Interfaces .................. E-1
Introduction
The HP 10342B Bus Preprocessor, with the HP 10269C General
Purpose Probe Interface, provides an easy connection between the HP
1650A/51A or HP 16510A Logic Analyzers and three popular data
buses, HP-IB (Hewlett-Packard's implementation of IEEE 488- 1978),
RS-232-C/CCITT V.24, and RS-449.
The HP 10342B software provides inverse assembly of activity on the
buses, and configurations for the logic analyzers. Any information in
this manual about the usage of the HP 1650A/51A or HP 16510A Logic
Analyzers is supplementary to that provided in the logic analyzer
operation and programming manuals.
The appendices contain abbreviated versions of the standards for the
buses. Additional information should be obtained from the appropriate
standards organization for each bus.
The manual is organized into six chapters.
Chapter 1 covers general information such as product description and
accessories.
Chapter 2 covers general hardware information, such as inspection,
power requirements, maintenance, and troubleshooting.
Chapter 3 covers general information about the software supplied.
Chapter 4 covers use of the HP 10342B for preprocessing the HP-IB.
It includes installation and other information specific to using the HP
10342B on this bus.
Chapter 5 covers the use of the HP 10342B for preprocessing the
RS-232-C/CCITT V.24 bus. It includes installation and other information
specific to using the HP 10342B on this bus.
Chapter 6 covers use of the HP 10342B for preprocessing the RS-449
bus. It includes installation and other information specific to using the
HP 10342B on this bus.
The appendices provide some of the basic specifications of the three
buses handled by the HP 10342B.
1
Introduction
HP-IB
RS-232-C/CCITT
v.24
General Information
The HP 10342B Bus Preprocessor combines in one instrument the
capability for analyzing three popular buses. The HP 10342B consists
of an interface module which plugs into the HP 10269C General
Purpose Probe Interface. Three connectors on the front panel of the
interface module accept cables which connect with the bus being
tested. Switches on the front panel are set up to match the
parameters of the signals on the bus.
The inverse assembler and configuration files loaded into the logic
analyzer from the disc set up the basic analysis parameters. The
operator can further set up the analyzer to make and process the
measurements in other ways. The exact measurement capabilities
depend on the logic analyzer being used.
The HP-IB input to the HP 10342B provides one HP-IB defined load to
the bus being monitored. The data and handshake lines of the bus are
buffered and run directly to the probe connectors of the HP 10269C.
The RS-232-C input to the HP 10342B provides one RS-232-C defined
load on the bus being monitored. The lines of the bus under test are
buffered and applied to circuitry that takes the serial data stream and
converts it back into original data and status. The HP 10342B monitors
five handshake lines and their status is stored with each character
received. Four switches set up the protocol and data rates. À
microprocessor controls the functions in the preprocessor.
1-1
RS-449 The RS-449 input to the HP 10342B provides one RS-449 defined load
on the bus being monitored. The lines of the bus are buffered and
ORed with the buffered lines from the RS-232-C connector. From that
point, RS-449 uses the same circuitry to capture the serial data as
used by RS-232-C. RS-449 inverse assembler and configuration files
are provided for the logic analyzer.
Operating Table 1-1 gives operating characteristics of the HP 10342B.
Characteristics
Table 1-1. HP 10342B Specifications and Operating Characteristics
RS-232C and RS-449*
Asynchronous Data
Data Transfer Rates 50, 75, 110, 134.5, 150, 300, 600, 1200,
(bits/second) 1800, 2000, 2400, 3600, 4800, 7200, 9600,
19200
Bits per Character 6, 7, or 8
Data Format 6-bit transcode, 7 or 8-bit ASCII,
8-bit EBCDIC
Odd, even, or no parity
1, 1.5, or 2 stop bits
* Note: The HP 10342B supports both RS-422A (balanced) and RS-423A (unbalanced) electrical
implementation of RS-449.
Table 1-1. HP 10342B Specifications and Operating Characteristics
(Continued)
Synchronous Data
Data Transfer Rates
(bits/second)
To 72 k bits/second
Bits per Character
6, 7, or 8
Data Format
Captures characters transmitted in
character-oriented protocols (COP) with
data transmission in one of the following
formats:
6-bit transcode using sync
character 3AH |
7 or 8-bit ASCII using sync
character 16H
8-bit EBCDID using sync
character 32H
Odd, even, or no parity
Captures bytes transmitted in
bit-oriented protocols (BOP) with data
transmitted as 8-bit ASCII or 8-bit
EBCDIC.
Table 1-1. HP 10342B Specifications and Operating Characteristics
(Continued)
General Characteristics
RS-232C/V.24 RS-449 HP-IB
Signals Monitored TX (BA) (SD) DIO1-8
RX (BB) (RD) IFC
RTS (CA) (RS) ATN
CTS (CB) (CS) SRQ
DSR (CC) (DW) REN
DTR (CD) (TR) EOI
CD (CF) (RR) DAV
NRFD
NDAC
Signal Loading One Standard | One Standard|1 LS TTL load
Load
Maximum Power
0.65 A at +5 VDC, supplied by the logic
Required analyzer.
Accessories RS-232C/V.24 ribbon cable 1-0.75 m (2.48 ft).
Supplied ;
RS-446 ribbon cable 1-0.75 m (2.48 ft)
HP-IB ribbon cable 1-0.75 m (2.48 ft)
Accessories HP 103428 and HP 10269C
Required
Logic Analyzer
Required
HP 1650A, HP 1651A, or HP 16510A
Number of
Probes Required
Two probes for state analysis and/or two
probes for timing analysis.
Table 1-1. HP 10342B Specifications and Operating Characteristics
(Continued)
General Information
Three provided: RS-232C/(V.24), RS-449, and
Inputs
HP-IB.
Outputs: Three mini-probe sockets can be connected
internally to any of the input lines via
jumper wires.
Environmental
Temperature:
Operating 0 to 55 degrees C (+32 to +131 degrees F)
Non-operating
-40 to +75 degrees C (-40 to +167 degrees F)
Altitude:
Operating
up to 4600 m (15,000 ft).
Non-operating
up to 15,300 m (50,000 ft).
Humidity:
90% non-condensing. Avoid sudden, extreme
temperature changes that could cause
condensation within the instrument.
1-5
mr
Equipment Equipment supplied with the HP 10342B consists of the following:
Supplied |
* One HP 10342B Preprocessor Module
* One 0.75 meter (2.5 ft) HP-IB ribbon cable
* One 0.75 meter (2.5 ft) RS-232C/V.24 ribbon cable
* One 0.75 meter (2.5 ft) RS-449 ribbon cable
* One 16-pin jumper cable
* 20 jumper wires
* HP 10269B Overlay
* This operating manual
E
Minimum The following is a list of the minimum equipment required for a system
Equipment using the HP 10342B Bus preprocessor.
Required
* HP 1650A, HP 1651A, or HP 16510A Logic Analyzer
* HP 10269C General Purpose Probe Interface
* HP 10342B Bus Preprocessor
1-6
2 Hardware Information
Introduction This chapter contains information about the hardware supplied with the
HP 103428 Bus Preprocessor. inspection, power requirements,
maintenance, and setup of the logic analyzer system are some of the
subjects covered.
|
Initial Inspect the shipping container for damage. If the shipping container or
Inspection cushioning material is damaged, it should be kept until the contents of
the shipment have been inspected mechanically and electrically. If the
contents are incomplete, if there is mechanical damage or a defect, or
if the instrument does not operate, notify your nearest Hewlett-Packard
Sales and Service Office. If the shipping container is damaged, or the
cushioning materials show signs of stress, notify the carrier as well as
Hewlett-Packard. Keep the shipping materials for inspection by the
carrier.
|
Power The HP 10342B draws power (t5 V) through the analyzer cables of the
Requirements HP 1650A/51A or HP 16510A Logic Analyzer. It draws approximately
0.65 amps.
2-1
Operator
Maintainance
The only instrument maintenance an operator needs to perform is to
keep the instrument clean. Caution must be used in the selection of
cleaning agents. Use a mild soap and water solution. Harsh soaps and
solvents could damage the painted finish.
PAIN NN RIU
Sell
{ CAUTION $
ns ie sn A Ad a AP Ph PP
WANN NNN ON EN
Be careful when cleaning the panel of the instrument.
Soap and solvents could damage parts or contaminate
circuitry. It is better to apply cleaning solutions to a
cloth and wipe the panel, than to wet the surface directly.
POPC OO TOOT OOO YY
§ CAUTION $
he Pn Peat AP An A A A
"A ONO NEY
Do not use chemical cleaning agents or abrasive cleaners
that could damage plastic parts. Recommended cleaning
agents are isopropyl! alcohol or a 1% solution of mild
detergent in water.
Testing and
Troubleshooting
There are no established field testing procedures for the HP 10342B.
The HP 10342B is part of the Blue-Stripe Exchange program. This
allows you to exchange a faulty assembly with one that has been
repaired, calibrated, and performance verified by the factory. If your
instrument is inoperative contact the nearest Hewlett-Packard Sales
and Service Office for assistance.
Replaceable Parts
Since the HP 10342B is part of the Blue Stripe board exchange
program, the only replaceable parts are the major parts and cabling.
These are listed in table 2-1.
Table 2-1. Replaceable Parts
Quantity Description HP Part Number
1 HP 163X Software Disc 10342-13012
1 HP 165X Software Disc 10342-13017
1 HP-IB Cable 10342-61603
1 RS-232-C Cable 10342-61601
1 RS-449 Cable 10342-61602
1 Probe Interface Overlay 10342-94301
1 16-pin Jumper Cable 10342-61604
20 Jumper wire 8120-4665
1 PC Board 10342-66501
1 Top cover 10342-04104
1 Bottom plate 10342-04102
12 4-40 Flathead screw 2200-0512
2 Captive screw 1390-0393
2 Retaining ring 0510-0952
E
Schematics The following information is supplied to help the user understand how
{пе НР 103428 impacts timing measurements of serial bus signals and
is not intended for troubleshooting an inoperative instrument.
2-3
Serial Input The input circuitry for one signal from each of the RS-232 and RS-449
Circuits buses is shown in figure 2-1. The inputs for the other signals are
identical. Both inputs are buffered and supplied to open-collector
drivers. The output of an RS-232 driver is wire-ORed with the output
of the corresponding RS-449 driver and the line is pulled up to *5 V.
The RS-232 line receiver has a threshold connection which is connected
to ground through 470 pF. This supplies noise immunity for RS-232
signals.
Probing for timing analysis for RS-232 and RS-449 is done after the line
receivers. These receivers invert the input signals.
+5V
A
A --
P70 MC1488 4700
P/O 7407
RS232 | y PS 1
NPUT LL ---
THRESHOLD INPUT
478
P/O 26L532
Бу
1
1
P/O 7487
>
RS443
INPUT
Figure 2-1. Serial Input Circuitry
Serial Timing
Connections
EACH +5V
LINE 47003
An overall view of the timing connections is shown in figure 2-2. The
RS-232 and RS-449 input circuitry (previously covered) are represented
by their respective blocks.
The three synchronous clocks from the buses are multiplexed with the
two asynchronous clocks generated in the HP 10342B in order to
provide one transmit and one receive clock. Clock selection depends
on the internal and front-panel switch settings. The two selected
clocks are used by the SIO and also sent to J6 where they join the
buffered and inverted serial signals for connection to the logic analyzer
timing inputs.
ASYNC SELECT
+5V — aE,
TX ASYNC CLK
ASYNC
CLOCK
GEN
RX ASYNC CLK
BITS/SEC
p———)
RS-232C ‘ A de TIMING OUTPUT
MEER ERT
2 2 18 NN 3 2
4 4 € 3 3
6 6 € 3 8
8 8 < 3 9
18 19 € 3 11
12 12 € <> 3 12
14 14 € N 3 13
16 16 — 3 14
1 1 € 3 15
a 3 € 5 8
5 5 € 5 9
7 7 € > 5 19
9 9 € 5 11
11 11 € 5 12
13 13 € 5 13
15 15 |5 14
A
MISC/SCG9
Figure 2-2. Serial Timing Circuitry
2-5
3
Introduction
Software Information
This chapter contains information about the software on the disc
labeled "HP-IB, RS-232C, and RS-449 Inverse Assemblers for use with
the HP 1650A, HP 1651A, and HP 16510A." Two types of files are
supplied on this disc, configuration files and inverse assembler files.
The configuration files set up the logic analyzer to capture the
information from the bus, and load the inverse assembler file. The
inverse assembler file is the software routine that decodes the
operations of the bus.
Table 3-1 is a list of the files provided with the HP 10342B for use with
the HP 1650A, HP 1651A, and HP 16510A Logic Analyzers.
Table 3-1. Software File List
Filename
Filetype
File Description
CHPIB 51
CHPIB I
CRS232 51
CRS232 1
CRS449 51
CRS449 I
IHPIB I
IRS232 I
IRS449 I
1650/1 config
1650/1 config
1650/1 config
1650/1 config
1650/1 config
1650/1 config
inverse assem
inverse assem
inverse assem
HPIB CONFIG FOR HP 1651A
HPIB CONFIG FOR 1650A/510A
RS232 CONFIG FOR HP 1651А
RS232 CONFIG FOR 1650A/510A
RS449 CONFIG FOR HP 1651A
RS449 CONFIG FOR 1650A/510A
HPIB IA FOR INTERFACE
RS232 IA FOR INTERFACE
RS449 IA FOR INTERFACE
3-1
Copying Files
HP 1650A/51A
HP 16510A
3-2
As soon as possible after receiving your instrument, you should copy
your disc. Use the copy and keep the original as a backup.
On HP 1650A/51A logic analyzers files are copied with the 1/0 Disc
Operations menu. You can copy HP 1650A/51A executable programs,
configuration files, and inverse assemblers from one disc to another.
To use the 1/0 Operations menu to "Copy" files or "Duplicate Discs,"
configure the menu with the same disc procedures described in the HP
1650A/51A Front-Panel Operation Reference manual.
Once the disc operation has been configured, press EXECUTE to copy
a file or duplicate a disc. When the operation has been completed, the
logic analyzer will display the filename, file type, and description of all
files transferred to the new disc.
For the HP 16510A Logic Analyzer, files are copied with the Front or
Rear Disc menu. You can copy HP 16510A executable programs,
configuration files, and inverse assemblers from one disc to another.
To use the Front or Rear disc menu to "Copy" files or "Duplicate
Discs," configure the menu with the same disc procedures described in
the HP 16500A Logic Analysis System Reference manual.
Once the disc operation has been configured, press EXECUTE to copy
a file or duplicate a disc. When the operation has been completed, the
logic analyzer will display the filename, file type, and description of all
files transferred to the new disc.
4
Introduction
Preprocessor
Function
Equipment
Required
HP-1B Bus Preprocessing
The HP-IB is the Hewlett-Packard implementation of IEEE Standard
488-1978. The HP-IB is a parallel bus with eight data lines, three
handshake lines and five control lines. A brief overview of HP-IB is
given in appendix A. |
The function of the HP 10342B when monitoring the HP-IB is to
connect onto the bus, buffer the lines, provide easy connection to the
logic analyzer, set up the logic analyzer menus, and inverse assemble
captured data. The HP 10342B can monitor the state of all the HP-IB
signal lines. On the HP 1650A and HP 16510A all 16 status and control
lines can be monitored for timing information. On the HP 1651A, eight
status and control lines can be monitored.
The HP 10342B allows you to either mass-connect the HP-IB lines up
to timing channels or individually connect the lines with jumper wires
provided. Timing channels are connected directly to the HP-IB without
buffering.
Additionally, any HP-IB line can be connected, unbuffered, to one of the
three HP 10342B front-panel outputs provided. These can be used for
connecting to an oscilloscope.
The minimum equipment necessary to use the HP 10342B Bus
Preprocessor is as follows:
* HP 1650A, HP 1651A, or HP 16510A Logic Analyzer
* HP 10269C Probe Interface
* HP 10342B Bus Preprocessor
4-1
Setting Up Note
the HP 10342B
The HP 10342B comes from the factory set up for
processing HP-IB, therefore some of the following
instructions may be redundant if the HP 10342B is being
used for the first time.
1. On the HP 10342B, connect the ribbon jumper cable from J7 to
J9. All 16 possible timing channels are connected when the
jumper cable is used (see figure 4-1).
If you use the single jumper wires to connect the timing signals,
be sure to connect them to corresponding pins of J7 and J9 or
the data captured will not match the HP 1650A/51A or HP 16510A
setup provided on disc. You will then need to change the HP
1650A/51A or HP 16510A Timing Format Specification menu to
match your hookup.
J4
J3
J6 J10 TIMING PODS J7 J9
CAR | 00 | TCK oloo| looloa D1| 00 ATN
00 |CTS 1|00| |00|1 D2 | 00 | SRQ
00 | DTR 2/00! loo|2 D3| 00 | IFC
00 | TX 3{00| lools D4 | 00 | NDAC
00 | DSR aloo| looja D5| 00 |NRFD
00 | RX s|00| lools D6 | 00 | DAV
00 | RTS seloo| loole D7 | 00 | REN
00 | RCK 7100| |00|7 ps | 00 | EOI
01 01
J5
ol,
1 2 3 U
т
Figure 4-1. HP-IB Timing Connector Locations
4-2
2.
If you want to connect any data or control lines to the
front-panel outputs, use the small jumper wires to connect the
pins from J10 to the pins of J5 (see figure 4-1). When the
mass-connect jumper cable is used, the signals at J10 correspond
to the mnemonics at J9.
For example, connect ATN to front-panel Output 1 by connecting
a jumper between J10 pod 1 pin 0 (top right) and J5 pin 1.
Connecting
the HP 10342B
to the HP 10269C
. Once all the connections are made, install the HP 10342B on the
bottom of the HP 10269C (see figure 4-2).
Insert the free end of the HP 10342B in the slots of the HP
10269C.
Connect the two 60-pin cables from the HP 10269C to the
connectors on the HP 103428.
Fold the HP 10342B into the bottom of the HP 10269C and fasten
the HP 10342B to the HP 10269C with the two captive screws.
4-3
INTERFACE POD
(HP 10269C)
SLOT
CABLE
cv
Pa)
>
us
x
a
la)
=
HP 103428
Figure 4-2. Installing the HP 103428 in the HP 10269C
4-4
Setting Up
the HP 10342B
Front Panel
The front-panel switches are used for serial data preprocessing and
have no function in preprocessing the HP-IB.
Connecting to
When using the HP 1650A or HP 16510A connect the logic analyzer
the HP 10269C
probes as follows:
HP 1650A and HP 16510A (into) HP 10269C
Probes Connector
2 2
3 3
5 5
Since the HP 1651A only has two probes, these probes must be hooked
up differently than shown above. To use the HP 10342B with the HP
1651A, connect up the probes as follows.
HP 1651A (into) HP 10269C
Probes Connector
1 2
2 3
Timing analysis on HP-IB with the HP 1651A is limited to the 8 status
and handshake lines.
Setting Up
the System
. Connect the HP-IB ribbon cable between the HP-1B bus to be
monitored and the HP-IB connector on the HP 10342B.
. Turn on power for all equipment involved. The logic analyzer will
come up in the System Configuration menu.
DAN
Setting Up
the Analyzer
from the Disc
4-6
. Install the flexible disc labeled "HP-IB, RS-232C, and RS-449
Inverse Assembler for use with HP 1650A, HP 1651A, and HP
16510A" in the front disc drive of the logic analyzer.
. Select one of the following menus:
* For the HP 1650A/51A, select the Disc Operations menu;
* For the HP 16510A, select the System Front Disc menu.
. Configure the menu to "Load" the analyzer with the configuration
file "CHPIB_1I" for the HP 1650A or HP 16510A. If you are using an
HP 1651A, load the configuration file "CHPIB_51."
. Execute the load operation to load the file into the HP 1650A, HP
1651A, or HP 16510A.
Accumulating
Data
Press RUN and, as soon as a clock is available on the bus, the logic
analyzer will begin to accumulate data.
Note
The logic analyzer will flash "Warning Slow Clock" when
data is no longer being transmitted across the bus. If you
press STOP at this point, the end of the data stream will
be displayed.
Signal
Connections
The HP 10342B monitors all HP-IB lines for state information. Eight or
16 lines (depending on the logic analyzer) can be monitored for timing
information. Table 4-1 lists the HP-IB signals and connections for the
HP 1650A/51A and HP 16510A Logic Analyzers.
4-7
4-8
Table 4-1. Logic Analyzer to HP-IB Signal Connections
for the HP 1650A/51A and HP 16510A
State Timing
HP 10269C HP 10269C
HP-IB Line Pod Pin Pod Pin
DAV 2 CLK - -
DIO1 2 9 3 15
DIO2 2 10 5 8
DIO3 2 11 5 9
DIO4 2 12 5 10
DIOS 2 13 5 11
DIO6 2 14 5 12
DIO7 2 15 5 13
DIOS 3 0 5 14
PAR POLL** 3 CLK - -
ATN 2 0 3 2
EOI 2 1 3 14
REN 2 2 3 13
IFC 2 3 . 3 8
SRQ 2 4 3 3
NDAC 2 5 3 9
DAV 2 6 3 12
NRFD 2 7 3 11
** Parallel Poll is available but not activated (see "Clocks" on
page 4-9).
Clocks
DAV
Parallel Poll
Two clocks are provided to the logic analyzer. These clocks can be
ORed to clock data.
DAV, Data Valid, is brought out at HP 10269C pod connector 2. iogic
analyzer POD 2 is connected there, providing DAV as the K Clock. The
logic analyzer clocks data on the negative edge of the K Clock.
The Parallel Poll clock is brought out at HP 10269C pod connector 3.
This is the Clock at logic analyzer POD 3. The PAR POLL clock is
ANDed from the EOI and ATN lines of the HP-IB.
The IEEE Standard 488 defines the Parallel Poll as requiring the EOI and
ATN lines to be true for 2 Ls to be valid. This timing function is not
implemented in the HP 103428.
The configuration file on the disc does not automatically set up the
logic analyzer to clock data on parallel polls. To clock data using the
ANDed function of EO! and ATN, go to the State Format Specification
menu of the logic analyzer. Add an active low L Clock to the clock
field. Remember that only data clocked after the 2 Us specification is a
valid paralle! poll.
Note
Since the HP 1651A does not have 3 pods, the clock
signals are setup as follows:
Signal Clock Used
DAV JJ
PPOLL 1K
4-9
Status The State Listing monitors the HP-IB interface management (ATN, EOI,
(STAT) Lines REN, IFC, and SRQ) and handshake (NDAC, DAV, and NRFD) lines
under the Status label. Only the interface management lines are used
in the inverse assembler. Table 4-2 shows which HP-IB line
corresponds to which Status line.
Table 4-2. Status Lines
Status Line | HP-IB Line Status Line | HP-IB Line
STAT 0 ATN STAT 4 SRQ
STAT 1 EOI STAT 5 NDAC
STAT 2 REN STAT 6 DAV
STAT 3 IFC STAT 7 NRFD
E
Cycle Lines The cycle lines are the HP-IB ATN and EOI lines and are the same as
the first two STAT lines. They are displayed in the State Display in
their symbol format.
Address (ADDR) There is an Address (ADDR) label set up in the State Format
Specification with no bits assigned to the label. This label must be
present when you are using an inverse assembler. If the ADDR label
appears on screen, you can go to the State Display menu and move
this label off the screen. This label is moved off the screen by the
configuration file when the software is loaded.
4-10
Setting Up
the Analyzer for
Timing Analysis
The HP 10342B software automatically configures the logic analyzer
for state analysis. The logic analyzer can also perform timing analysis
on the HP-IB lines. To set up the logic analyzer for timing analysis,
you will need to do the following:
1. In the System menu of the logic analyzer, configure Analyzer 2 to
be a Timing Analyzer.
2. For the HP 1650A or HP 16510A, assign pods 3 and 5 to Analyzer
2. You should see a display as shown in figure 4-3.
3. For the HP 1651A, assign pod 2 to Analyzer 2. You should see a
display as shown in figure 4-4.
The Format menu will provide a label for each signal.
System Configuration
Analyzer | Analyzer 2
Name: [HPIB STATE Neme: [HPIB TIME | Unassigned Pods
Type: Type:
(Rutoscale
Figure 4-3. Configuration Menu for Timing Analysis
with the HP 1650A or HP 16510A
System Configuration
Analyzer | Analyzer 2
Neme: [HPIB STATE Name: [HPIB TIME | Unassigned Pods
Type: Type:
Figure 4-4. Configuration Menu for Timing Analysis with the HP T651A
9
introduction
Preprocessor
Function
RS-232-C/V.24
Bus Preprocessing
The RS-232-C/V.24 is a serial interface with unbalanced data and
control lines. A brief overview of RS-232-C/V.24 is given in Appendix C.
Several of the serial interfaces are compared in Appendix B. Further
references to RS-232-C should be assumed to include CCITT V.24.
The primary function of the HP 10342B is to convert serial data stream
to parallel data and status. The HP 10342B monitors five handshake
lines and stores their states for each character. Four of the handshake
lines are synchronous with the serial controller and one line (carrier
detect) is asynchronous but sampled each time a character is output to
the logic analyzer.
All lines are buffered at the input to the HP 10342B. The buffers
provide one RS-232-C standard load to the bus. Signals are inverted
by the buffer circuitry.
The HP 10342B can mass-connect the bus lines to timing channels, or
the lines can be individually connected with the jumper wires provided.
Timing connections are made to the buffered and inverted signals.
Additionally, any buffered line can be connected to one of the three HP
10342B front-panel outputs provided. These can be used for
connecting to an oscilloscope.
5-1
Equipment The minimum equipment necessary to use the HP 103428 Bus
Required Preprocessor is as follows:
* HP 1650A, HP 1651A, or HP 16510A Logic Analyzer
* HP 10269C Probe Interface
* HP 10342B Bus Preprocessor
Setting Up
the HP 10342B Note
The HP 10342B comes from the factory set up for
processing HP-IB.
1. On the HP 10342B, connect the ribbon jumper cable to the
appropriate pins. All 16 possible timing channels are connected
when the jumper cable is connected from J6 to J10. Only nine
channels are used with RS-232-C processing (see figure 5-1).
If you use the single jumper wires to connect the timing signals
be sure to connect them to corresponding pins of J6 and J10 or
the data captured will not match the HP 1650A/51A or HP 16510A
setup provided on disc. You would then need to change the HP
1650A/51A or HP 16510A Timing Format Specification menu to
match your hook-up.
5-2
J4
J3
J6 J10 TIMING PODS J7 J9
CAR | 00 | TCK 0 |100 00| 0 011 00 | АТМ
00| ст$ 1/00 OO | 1 D2 | CO | SRG
OO |DTR 2 100 00| 2 D3{ 00 | IFC
00 | TX 3100 00| 3 D4 | OO | NDAC
00 | DSR 4/00 00| 4 D5{ 00 | NRFD
00 | RX 5 |100 00 | 5 06 100 | DAV
OO | RTS 6 100 OO | 6 D7 | 00 | REN
00 | ВСК 7 |100 00 | 7 D8 | OO | EOI
0 1 0 1
J5
000],
12 3 vu
т
Figure 5-1. RS-232-C Timing Connector Locations
2. If you want to connect any data or control lines to the
front-panel outputs, use the single jumper wires to connect pins
of J7 to pins of J5 (see figure 5-1). When you are using the
mass-connect jumper cable, the signals at J7 correspond to the
mnemonics at Jb.
For example, connect TCK to front-panel Output 1 by connecting
a jumper between J7 pod 1 pin 0 (top right) and J5 pin 1.
5-3
3. Set the DTE/DCE switch (see figure 5-2) to the position
corresponding to the desired sync transmit clock. If the transmit
clock from the terminal (computer) is desired, use DTE and, if the
transmit clock from the modem is desired, use DCE.
MISC/EX60
Figure 5-2. DTE/DCE Switch Location
E
Connecting 1. Once all the connections are made, install the HP 103428 on the
the HP 10342B bottom of the HP 10269C (see figure 5-3).
to the HP 10269C
2 Insert the free end of the HP 10342B in the slots of the HP
10269C.
3. Connect the two 60-pin cables from the HP 10269C to the
connectors on the HP 10342B.
4. Fold the HP 10342B into the bottom of the HP 10269C and fasten
the HP 10342B to the HP 10269C with the two captive screws.
5-4
INTERFACE POD
(HP 10265C)
SLOT
CABLE
MISC/EX53
HP 103428
Figure 5-3. Installing the HP 10342B in the HP 10269C
5-5
Setting Up Set the front-panel switches according to the protocol, parity, etc. of
the HP 10342B the bus you are working with. The HP 10342B needs the proper
Front Panel protocol settings to disassemble the data on the bus.
* In BIT PROTOCOL (BOP, bit oriented synchronous protocol), the
only other switch setting that must be made is 8 ASCII or 8 EBCDIC
in BITS/CHAR. No other switch settings are relevant because the
rest of the protocol is predefined. Clock comes from the external
source, either terminal (DTE) or modem (DCE).
* In CHAR PROTOCOL (BCP, byte control synchronous protocol), the
PARITY and BITS/CHAR switches must be set so that the HP
10342B knows which characters to sync on. These sync characters
are not displayed due to internal processing in the HP 10342B. The
clock comes from an external source, either terminal (DTE) or
modem (DCE).
* When ASYNChronous is selected, the settings of all other front
pane! switches are relevant. The clock source is from an internal!
source ASYNC BITS/SEC. |
1. Set the PARITY to the proper setting.
2. Set the BITS/CHAR.
3. Set the ASYNC BITS/SEC.
Note
When transmit or receive data is present a state will be
stored. Lack of data, or improper sync characters, results
in a slow clock indication from the logic analyzer.
Connecting to
the HP 10269C
When using the HP 1650A or HP 16510A, connect the logic analyzer
probes as follows:
HP 1650A and 16510A (into) HP 10269C
Probes Connector
1 | 1
4 4
Since the HP 1651A only has two probes, this logic analyzer must be
hooked up differently than shown above. When you use the HP 1651A
with the HP 10342B, connect the logic analyzer probes as follows:
HP 1651A (into) HP 10269C
Probes Connector
1 1
2 4
1. Connect the RS-232 ribbon cable between the bus to be monitored
Setting Up
and the RS-232C/V.24 connector on the HP 103428.
the System
2. Turn on power for all equipment involved. The logic analyzer will
come up in the System Configuration menu.
Setting Up
the Analyzer
from the Disc
1. Install the flexible disc labeled "HP-IB, RS-232C, and RS-449
"Inverse Assembler for use with HP 1650A, HP 1651A, and HP
16510A" in the front disc drive of the logic analyzer.
2. Select one of the following menus:
* For the HP 1650A/51A, select the Disc Operations menu,
* For the HP 16510A, select the System Front Disc menu.
3. Configure the menu to "Load" the analyzer with the configuration
file "CRS232_I" for the HP 1650A or HP 16510A. If you are using
an HP 1651A, load the configuration file "CRS232_51."
4. Execute the load operation to load the file into the HP 1650A, HP
1651A, or HP 16510A.
E
Accumulating Press RUN and, as soon as a clock is available on the bus, the logic
Data analyzer will begin to accumulate data.
Note
The logic analyzer will flash "Warning Slow Clock" when
data is no longer being transmitted across the bus. If you
press STOP at this point, the end of the data stream will
be displayed.
E
Signal The HP 10342B provides processed data and status to the logic
Connections analyzer state inputs. The timing inputs are buffered from the
5-8
RS-232-C bus except for TX CLK and RX CLK, which are selected in
the HP 103428.
Table 5-1. Logic Analyzer to RS-232-C Signal Connections
(HP 1650A/51A and HP 165710A)
State* Timing
HP 10269C HP 10269C
Signal Connector Pin Signal Connector | Pin
Clock 4 CLK TX CLK** 3 2
CTS*** 3 3
1 0 DTR*** 3 8
1 1 TX*** 3 9
Serial 1 2
Data 1 3 DSR*** 3 11
Converted RX*** 3 12
to 1 4 RTS*** 3 13
Parallel 1 5 RX CLK** 3 14
: 1 6
1 7 CAR*** 3 15
TX/RX 1 8
CC LSB 1 9
CC MSB 1 10
CTS 1 11
DSR 1 12
RTS 1 13
DTR 1 14
CD 1 15
* Processed through S10 in HP 10342B.
** Clock selected in HP 10342B.
*** Signal from buffered RS-232-C lines.
Clock
One clock is supplied to the logic analyzer from the processor in the
HP 10342B. For the HP 1650A and HP 16510A, this clock is provided to
pod 4 an is the M Clock. For the HP 1651A, this clock is provided to
pod 2 and is the K Clock. The logic analyzer clocks data on the
negative edge of the clock.
Data
The Data, at HP 10269C connector 1 (logic analyzer POD 1), is the
parallel format of the serial data byte. It has been processed in the
SIO (Serial IN/OUT Interface) and microprocessor of the HP 10342B.
Status Byte
5-10
The Status Byte, at Connector 1 of the HP 10269C, is provided by the
microprocessor in the HP 103428.
Bit 0 represents whether the data is transmitted (1) or received (0)
and is used by the inverse assembler.
Bits 1 and 2, CC LSB and CC MSB, represent front panel settings
for BITS/CHAR and are used by the inverse assembler to interpret
data.
00 = Normal Character
01 = EBCDIC Character Set
10 = 6-bit Transcode Character Set
11 = Not Used
Bits 3-7 are the handshake signals. They have been processed in
the SIO of the HP 10342B and represent the status of the
handshake lines for each serial data byte.
Address (ADDR)
There is an Address (ADDR) label set up in the State Format
Specification with no bits pod assigned to the label. There is no
RS-232-C information in this label. This label must be present when
you are using an inverse assembler. If the ADDR label appears on
screen you can go to the State Display menu and move it off the
— ws vw we
screen. This is done automatically by the configuration file when the
software is loaded. |
Mnemonics
The HP 10342B inverse assembler for RS-232-C uses common
mnemonics rather than the mnemonics specified in the ElA Standard.
Table 5-2 provides a cross reference.
Table 5-2. RS-232-C Mnemonic Cross Reference
Mnemonic
Pin Common RS-232-C
2 TX | BA
3 RX BB
4 RTS CA
5 CTS CB
6 DSR CC
8 CD CF
15 DCE CLK DB
17 REC CLK DD
20 DTR CD
24 DTE CLK DA
Sync Characters
5-12
The HP 10342B must receive the proper sync characters in order to
process data. The SIO is programmed to recognize the standard sync
characters for the selected character code. If some other sync
characters are being sent to the HP 10342B, the logic analyzer will
display "Slow Clock."
The transmitted sync character can be seen in only the timing display.
The HP 10342B does not provide the sync characters to the state
display. Table 5-3 shows the expected sync characters for given
character codes.
Table 5-3. Standard Sync Characters
CHAR CODE SYNC CHAR
6 BIT TRANS 3A3A HEX
7 BIT ASCII 1616 HEX
8 BIT ASCII 1616 HEX
8 BIT EBCDIC 3232 HEX
The SIO recognizes a 16-bit "character word.” When observing the
sync character data string, take into account the relationship of this
word to the idle characteristics of the data line and the parity of the
transmitted data.
For example, when observing bit strings on the timing channels of the
logic analyzer, note that data is clocked on the rising edge of TX CLK
or RX CLK.
As can be seen in figure 5-4, the SIO uses two "bits" from the idle bus
to fill out the two "missing" bits of the character. It then uses 2C5BH
as a comparison to recognize the sync characters. If the bus does not
idle high (idle high is standard), the sync characters will not be
recognized. |
i |
(no parity) DATA FLOW >
| SYNC | SYNC | LINE IDLE——
/
00101 10/00 101 10/1 1|1 11 11 \
16H | 16H |
—— 2C5BH 16-bit "sync word"
Start sending |
data to analyzer
Figure 5-4. 7-Bit ASCII Sync Sequence
In figure 5-5 the sync characters with parity have a longer bit string
than the "sync word." The two least significant bits are dropped and
the SIO uses 994CH as a comparison to recognize the sync characters.
8-BIT EBCDIC
(even parity) DATA FLOW >
Чар
| SYNC | SYNC | —LINE IDLE— >
/
1/001 10010f1j001100f20{1111111\
/
| 32H 4 32H |
parity
— 994CH 16-bit "sync word"
Start sending |
data to analyzer
Figure 5-5. 8-Bit EBCDIC Sync Sequence
5-13
Block Check Tha last two characters of the data stream are Block Check
Characters
Characters (BCC). These characters are actually CRCs and are passed
on to the logic analyzer as data. However, they have been altered by
the SIO and their value is no longer significant.
Setting Up The HP 10342B software automatically configures the logic analyzer
the HP1650A or for state analysis. The logic analyzer can also perform timing analysis
HP 16510A for on the RS-232 lines. To set up the logic analyzer for timing analysis,
Timing Analysis you will need to do the following:
5-14
. In the Configuration menu of the logic analyzer, configure Analyzer
2 to be a timing analyzer.
2. Assign pod 3 to Analyzer 2. You should see a display as shown in
figure 5-6.
3. Connect probe 3 from the logic analyzer to POD 3 on the HP
10269C.
System Configuration
Analyzer 1 Analyzer 2
Name: | RS232 ST Name: |RS232 TIME Unassigned Pods
Type: Type:
Figure 5-6. Configuration Menu for Timing Analysis
with the HP 1650A or HP T6510A
Setting Up
the HP 1651A for
Timing Analysis
The Format menu will provide a label for each signal.
The following signals are turned off in the Format menu:
RX CLK, TX CLK, RX, TX
To capture these signals with the timing analyzer, turn on the
appropriate labels in the Format menu.
Refer to page 5-16 for more information on the timing signals.
The HP 10342B software automatically configures the HP 1651A for
state analysis. The logic analyzer can also perform timing analysis on
the RS-232C lines. To set up the HP 1651A for timing analysis, you will
need to do the following:
1. In the logic analyzer System menu configure Analyzer 2 to be a
Timing Analyzer.
2. Assign pod 2 to Analyzer 2. You should see the display as shown
in figure 5-7. |
3. Move pod 2 from connector 4 to connector 3 on the HP 10269C.
The Format menu of the HP 1651A will provide a label for each signal.
5-15
Timing Signals
5-16
System Configuration
Analyzer 1 Analyzer 2
Neme: [ RS232 ST Neme: |RS232 TIME Unassigned Pods
Type: Type:
1
Figure 5-7. Configuration Menu for Timing Analysis
with the HP T651A
For further information about the timing signals see the "Schematics”
section in Chapter 2.
Most timing signals are buffered directly from the RS-232-C bus. The
TXCLK and RXCLK are clocks selected in the HP 10342B by the
DTE/DCE switch and front-panel setup.
On asynchronous buses, the RX CLK and TX CLK are generated by the
НР 103428 circuitry and are not signals sent across RS-232-C.
On synchronous buses, the RX CLK is the REC CLK signal (DD, pin 17).
The TX CLK is either the DTE CLK signal (DA, pin 24) or the DCE CLK
signal (DB, pin 15), depending on the setting of the DTE/DCE switch on
the HP 103428.
The Carrier Detect (CAR) is also buffered directly from the RS-232-C
bus.
The timing signals supplied to the logic analyzer are of the opposite
sense to the mark/space definition in the RS-232-C standard (see figure
5-8). The line receivers buffer, invert, and convert the RS-232 signals
to TTL. The logic analyzer timing inputs are not designed to handle the
+25 V signals specified by RS-232-C, so they are connected to the
buffered signals.
Though the timing signals are of the opposite sense to that defined by
the RS-232-C specification, they are of the same sense as the signals
supplied to the RS-232 line drivers in the DCE. This makes it easier to
compare the output (TTL) of the asynchronous receiver/transmitter in
the DCE to the TTL signal applied to the SIO in the DTE.
103428
| STATE
DCE
TO
CPU
1026896
SERÍAL | ET
LINE BUS LINE 10 J 7 { LR Ÿ
-- RCVRS ” = —
| TIMING
— Jr pu — | mu
SIGNAL SENSE
Figure 5-8. Signal Sense Diagram
6
Introduction
Preprocessor
Function
RS-449 Bus
Preprocessing
The RS-449 is a serial interface with balanced data and control lines. A
brief overview of RS-449 is given in Appendix D. Several of the serial
interfaces are compared in Appendix B.
The RS-449 has two categories of interchange circuits, Category | and
Category Il. Category 1 circuits are balanced high-speed circuits.
Category ll circuits are low-speed, unbalanced circuits used for
secondary functions. The HP 10342B processes only the Category |
circuits. |
The primary function of the HP 10342B is to convert the serial data
stream into parallel data and status. The HP 10342B monitors five
handshake lines and stores their states for each character. Four of the
handshake lines are synchronous with the serial controller and one line
(carrier detect) is asynchronous but sampled each time a character is
output to the logic analyzer.
All lines are buffered at the input to the HP 10342B. The buffers
provide one RS-449 standard load to the bus. Signals are inverted by
the buffer circuitry.
The HP 10342B can mass-connect the bus lines to timing channels, or
the lines can be individually connected with the jumper wires provided.
Timing connections are made to the buffered and inverted signals.
Additionally, any buffered line can be connected to one of the three HP
10342B front-panel outputs provided. These can be used for
connection to an oscilloscope.
Equipment The minimum equipment necessary to use the HP 10342B Bus
Required "Preprocessor is as follows:
* HP 1650A, HP 1651A, or HP 16510A Logic Analyzer
* HP 10269C Probe interface
* HP 10342B Bus Preprocessor
Setting Up Note
the HP 10342B
The HP 10342B comes from the factory set up for
processing HP-IB.
1. On the HP 10342B, connect the ribbon jumper cable to the
appropriate pins. All 16 possible timing channels are connected
when the jumper cable is connected from J6 to J10. Only nine
channels are used with RS-449 processing (see figure 6-1).
If you use the single jumper wires to connect the timing signals,
be sure to connect them to corresponding pins of J6 and J10 or
the data captured will not match the HP 1650A/51A or HP 16510A
setup provided on disc. You will need to change the HP
1650A/51A or HP 16510A Timing Format Specification menu to
match your hook-up.
6-2
J4
J3
RS-449 Jb J6 J10 TIMING PODS J7 J9
RR TCK CAR | OO | TCK 0 100 00 | 0 Di COTATN
CS 00 | CTS 1/00 001} 1 D2 | 00 | SRQ
TR 00 | DTR 2100 00 | 2 D3 | OO |IFC
SD 00 | Tx 3:00 00 | 3 D4 | OO | NDAC
DM 00 | psr 4 100 00|4 D5 | OO | NRFD
RD 00 | RX 5 100 ОО | 5 D6 | OO | DAV
RS OO | RTS 6 100 OO | 6 D7 | OO ! REN
RCK 00 | RCK 7100 00 | 7 D8 | 00 | EOI
0 1 0 1
J5 19 00
[0 0 of,
1 2 3 u
T
Figure 6-1. Timing Connector Locations
2. If you want to connect any data or control lines to the
front-panel outputs, use the single jumper wires to connect pins
of J7 to pins of J5 (see figure 6-1). When you're using the
mass-connect jumper cable, the signals at J7 correspond to the
mnemonics at J6.
For example, connect TCK to front-panel Output 1 by connecting
a jumper between J7 pod 1 pin 0 (top right) and J5 pin 1.
6-3
DTE/DCE
SWITCH
3. Set the DTE/DCE switch (left side of PC board) to the position
corresponding to the desired sync transmit clock. If the transmit
clock from the terminal (computer) is desired, use DTE and, if the
transmit clock from the modem is desired, use DCE.
M1SC/EX88
Figure 6-2. DTE/DCE Switch Location
E
Connecting
the HP 10342B
to the HP 10269C
6-4
. Once all the connections are made, install the HP 10342B on the
bottom of the HP 10269C (see figure 6-3).
. Insert the free end of the HP 10342B in the slots of the HP
10269C.
. Connect the two 60-pin cables from the HP 10269C to the
connectors on the HP 103428.
. Fold the HP 10342B into the bottom of the HP 10269C and fasten
the HP 10342B to the HP 10269C with the two captive screws.
INTERFACE POD
(HP 10269C)
MISC/EXS3
SLOT
LJ
—
a
<q
O
NS
HP 103428
Figure 6-3. Installing the HP 103428 in the HP 10269C
6-5
Setting Up Set the front-panel switches according to the protocol, parity, etc. of
the HP 10342B the bus you are working with. The protocol must be set correctly for
Front Panel the HP 10342B to disassemble the data on the bus.
* In BIT PROTOCOL (BOP, bit oriented synchronous protocol), the
only other switch that must be set is 8 ASCII or 8 EBCDIC in
BITS/CHAR. No other switch settings are relevant because the rest
of the protocol is predefined. Clock comes from the external
source, either terminal (DTE) or modem (DCE).
* In CHAR PROTOCOL (BCP, byte control synchronous protocol), the
PARITY and BITS/CHAR switch settings must be set so that the HP
10342B knows which characters to sync on. These characters are
not displayed due to internal processing in the HP 10342B. Clock
comes from the external source, either terminal (DTE) or modem
(DCE).
* When ASYNChronous is selected, the settings of all other
front-panel switches are relevant. The clock source is from the
internal source, ASYNG BITS/SEG. To select ASYNChronous:
1. Set the PARITY to the proper setting.
2. Set the BITS/CHAR.
3. Set the ASYNC BITS/SEC.
Note
When transmit or receive data is present a state will be
stored. Lack of data resuits in a slow clock indication
from the logic analyzer.
6-6
Connecting to
the HP 10269C
When using the HP 1650A or HP 16510A connect the logic analyzer
probes as follows:
HP 1050A and HP 16510A (into) HP 10269C
Probes Connector
1 1
4 4
Since the HP 1651A only has two probes, this logic analyzer must be
hooked up differently than shown above. To use the HP 10342B with
the HP 1651A, connect up the probes as follows.
HP 1651A (into) HP 10269C
Probes Connector
1 1
2 4
|]
Setting Up 1. Connect the RS-449 ribbon cable between the bus to be monitored
the System and the RS-449 connector on the HP 10342B.
2. Turn on power for all equipment involved. The logic analyzer will
come up in the System Configuration menu.
6-7
Setting Up | 1. Install the flexible disc labeled "HP-IB, RS-232C, and RS-449
the Analyzer Inverse Assembler for use with HP 1650A, HP 1651A, and HP
from the Disc 16510A" in the front disc drive of the logic analyzer.
2. Select one of the following menus:
* For the HP 1650A/51A, select the Disc Operations menu;
* For the HP 16510A, select the System Front Disc menu.
3. Configure the menu to "Load" the analyzer with the configuration
file "CRS449 |" for the HP 1650A or HP 16510A. If you are using
an HP 1651A, load the configuration file "CRS449_51."
4. Execute the load operation to load the file into the HP 1650A, HP
1651A, or HP 16510A.
Accumulating Press RUN and, as soon as a clock is available on the bus, the logic
Data analyzer will begin to accumulate data.
Note
The logic analyzer will flash “Warning Slow Clock” when
data is no longer being transmitted across the bus. If you
press STOP at this point, the end of the data stream will
be displayed.
I
Signal The HP 10342B provides processed data and status to the logic
Connections analyzer state inputs.
6-8
Table 6-1. Logic Analyzer to RS-449 Signal Connections
(HP 1650A/51A and HP 16510A)
State* Timing
HP 10269C HP 10269C
Signal Connector Pin Signal Connector Pin
Clock 4 CLK TX CLK** 3 2
CS*** 3 3
1 0 TR*** 3 8
1 1 SD*** 3 9
Serial 1 2
Data 1 3 DM*** 3 11
Converted RD*** 3 12
to 1 4 RS*** 3 13
Parallel 1 5 RX CLK** 3 14
1 6
1 7 RR*** 3 15
TX/ RX 1 8
CC LSB 1 9
CC MSB 1 10
CS 1 11
DM 1 12
RS 1 13
TR 1 14
RR 1 15
* Processed through SIO in HP 10342B.
** Clock selected in HP 10342B.
*** Signal from buffered RS-449 lines.
6-9
Clock One clock is supplied to the logic analyzer from the microprocessor in
the HP 10342B. For the HP 1650A and HP 16510A, this clock is
provided to pod 4 and is the M Clock. For the HP 1651A, this clock is
provided to pod 2 and is the K Clock. The logic analyzer clocks data
on the negative edge of the clock. |
Data The Data, at HP 10269C connector 1 (logic analyzer POD 1), is the
parallel format of the serial data byte. It has been processed in the
SIO (Serial IN/OUT interface) and microprocessor of the HP 10342B.
Status Byte The Status Byte, at connector 1 of the HP 10269C, is provided by the
microprocessor in the HP 10342B.
Bit 0 represents whether the data is transmitted (1) or received (0)
and is used by the inverse assembler.
Bits 1 and 2, CC LSB and CC MSB, represent front-panel settings
for BITS/CHAR and are used by the inverse assembler to interpret
data.
00 = Normal Character
01 = EBCDIC Character Set
10 = 6-bit Transcode Character Set
11 = Not Used
Bits 3-7 are the handshake signals. They have been processed in
the SIO of the HP 10342B and represent the status of the
handshake lines for each serial data byte.
Address (ADDR)
Sync Characters
There is an Address (ADDR) label set up in the State Format
Specification with no bits from a pod assigned to the label. There is no
RS-449 information in this label. This label must be present when you
are using an inverse assembier. If the ADDR label appears on screen,
you can go to the State Display menu and move it off the screen. This
is done: automatically by the configuration file when the software is
loaded.
The HP 10342B must receive the proper sync characters in order to
process data. The SIO is programmed to recognize the standard sync
characters for the selected character code. If some other sync
characters are being sent to the HP 10342B, the logic analyzer will
display "Slow Clock".
The transmitted sync character can be seen in only the timing display.
The HP 10342B does not provide the sync characters to the state
display. Table 6-2 shows the expected sync characters for given
character codes.
Table 6-2. Standard Sync Characters
CHAR CODE SYNC CHAR
6 BIT TRANS 3A3A HEX
7 BIT ASCII 1616 HEX
8 BIT ASCII 1616 HEX
8 BIT EBCDIC 3232 HEX
The SIO recognizes a 16-bit "character word". When observing the
sync character data string, take into account the relationship of this
word to the idle characteristics of the data line and the parity of the
transmitted data.
For example, when observing bit strings on the timing channels of the
logic analyzer, note that data is clocked on the rising edge of TX CLK
or RX CLK.
As can be seen in figure 6-4, the SIO uses two "bits" from the idle bus
to fill out the two "missing" bits of the character. № then uses 2C5BH
as a comparison to recognize the sync characters. If the bus does not
idie high (idle high is standard), the sync characters will not be
recognized.
7-BIT ASCII
(no parity) DATA FLOW >
| SYNC | SYNC | —LINE IDLE— —>
/
0010110j0010110/1 1/1 1 1 11 \
/
16H | 16H |
— 2C5BH 16-bit "sync word"
Start sending |
data to analyzer
Figure 6-4. 7-Bit ASCII Sync Sequence
In figure 6-5 the sync characters with parity have a longer bit string
than the "sync word." The two least significant bits are dropped and
the SIO uses 994CH as a comparison to recognize the sync characters.
8-BIT EBCDIC
(even parity) DATA FLOW >
| SYNC | SYNC |—LINE IDLE—
/
1100110010(1{001100J10f1111111\
/
| 32H a
party a
— 994CH 16-bit "sync word"
Start sending |
data to analyzer
Figure 6-5. 8-Bit EBCDIC Sync Sequence
|
Block Check Tha last two characters of the data stream are Block Check
Characters Characters (BBC). These characters are actually CRCs and are passed
on to the logic analyzer as data. However, they have been altered by
the SIO and their value is no longer significant.
6-13
Setting Up
the HP1650A or
HP 16510A for
Timing Analysis
6-14
The HP 10342B software automatically configures the logic analyzer
for state analysis. The logic analyzer can also perform timing analysis
on the RS-449 lines. To set up the logic analyzer for timing analysis,
you will need to do the following:
1. In the Configuration menu of the logic analyzer, configure Analyzer
2 to be a timing analyzer.
2. Assign pod 3 to Analyzer 2. You should see a display as shown in
figure 6-6.
3. Connect probe 3 from the logic analyzer to POD 3 on the HP
10269C.
System Configuration
Analyzer 1 Analyzer 2
Name: | RS449 ST Name: |RS449 TIME Unassigned Pods
Type: Type: Fer)
Von
| ( Pod 5 y
{ Pod I Y ( Pod 3 ` || ‘—==============- )
[ Pod 4 ]
Figure 6-6. Configuration Menu for Timing Analysis
with the HP 1650A or HP 16510A
The Format menu will provide a label for each signal.
The following signals are turned off in the Format menu:
RX CLK, TX CLK, RX, TX
To capture these signals with the timing analyzer, turn on the
appropriate labels in the Format menu.
Refer to page 6-16 for more information on the timing signals.
|
Setting Up The HP 10342B software automatically configures the HP 1651A for
the HP 1651A for state analysis. The logic analyzer can also perform timing analysis on
Timing Analysis the RS-449 lines. To set up the HP 1651A for timing analysis, you will
need to do the following:
1. In the logic analyzer System menu configure Analyzer 2 to be a
Timing Analyzer.
2. Assign pod 2 to Analyzer 2. You should see the display as shown
in figure 6-7.
3. Move pod 2 from connector 4 to connector 3 on the HP 10269C.
The Format menu of the HP 1651A will provide a label for each signal.
Timing Signals
6-16
System Configuration
Analyzer 1 Analyzer 2
Neme: | RS449 ST Name: [RS449 TIME Unassigned Pods
Type: Type:
Figure 6-7. Configuration Menu for Timing Analysis with the HP 1651A
For more information about the timing signals see the "Schematics”
section in Chapter 2.
Most timing signals are buffered directly from the RS-449 bus. The
TXCLK and RXCLK are clocks selected in the HP 10342B by the
DTE/DCE switch and front-panel setup.
On asynchronous buses, the RX CLK and TX CLK are generated by the
HP 10342B circuitry and are not signals sent across RS-449.
On synchronous buses, the RX CLK is the REC CLK signal (RT, pins 8
and 26). The TX CLK is either the DTE CLK signal (TT, pins 17 and 35)
or the DCE CLK signal (ST, pins 5 and 23), depending on the setting of
the DTE/DCE switch on the HP 103428.
The Receiver Ready (RR) is also buffered directly from the RS-449 bus.
The timing signais supplied to the logic anaiyzer are of the opposite
sense to the mark/space definition in the RS-449 standard (see figure
6-8). The line receivers buffer, invert, and convert the RS-449 signals
to TTL.
Though the timing signais are of the opposite sense to that defined by
the RS-449 specification, they are of the same sense as the signals
supplied to the RS-449 line drivers in the DCE. This makes it easier to
compare the output (TTL) of the asynchronous receiver/transmitter in
the DCE to the TTL signal applied to the SIO in the DTE.
193428
STATE |)
L
PROCESSOR
TO
102696
SERIAL 3 2 JUMPER
LINE | | BUS | LINE 10 7 9 Y |
—l DR VR/ H RCVRS ple pls pi >
RCVR
TIMING
— т pe MISC/BL23
SIGNAL SENSE
Figure 6-8. Signal Sense Diagram
A
HP-IB Overview
Introduction HP-IB is the Hewlett-Packard implementation of IEEE Standard
488-1978. The following is a brief overview of HP-IB. If additional
information is needed obtain the standard from the appropriate source.
|
The HP-1B The HP-IB empioys a 16-line bus to interconnect up to 15 instruments.
Each instrument on the bus is connected in parallel to the 16 lines of
the bus. Eight of the lines are used to transmit data and the remaining
eight are used for data transfer control (handshake) and bus
management. Data is transferred by means of an interlocked
"handshake," permitting asynchronous communication over a wide
range of data rates.
The HP-IB structure is diagrammed in figure A-1. Four types of
devices may be used on the bus based on their functions:
(1) devices only able to talk;
(2) devices only able to listen;
(3) devices able to talk and listen;
(4) devices able to talk, listen, and control.
The simplest instrument is one that only talks. When signaled this
device enters its output on the data bus lines in a fixed configuration.
The configuration may be altered only by front-panel control.
Devices that only listen respond to data from the HP-IB data lines. In
the case of a signal generator, this data could cause the instrument to
output signals of different amplitude and frequency, external to the bus.
Printers are frequently listen-only instruments.
A digital multimeter is a device that listens and talks. The multimeter is
configured by signals from the controller, takes the requested reading,
and returns the results on the bus.
The controller, along with talk and listen capabilities, controls all
operations on the interface bus.
A-1
As shown in figure A-1, the 16 lines of the HP-IB form three functional
groups: five lines for interface management, three lines for handshake
(data byte transfer) control, and eight bidirectional lines for carrying
HE EZ
DEVICE A <
ABLE TO
TALK, LISTEN,
AND CONTROL
(e.g.calculator) a DATA
> 8 LINES
DEVICE B
ABLE TO
TALK AND
LISTEN
(e.g.digitol DATA BYTE
multimeter) TRANSFER
(D CONTROL
3 LINES
DEVICE C <
ONLY ABLE
TO LISTEN
(e.g.signal GENERAL
generator) A INTERFACE
( N MANAGEMENT
y 5 LINES .
DEVICE D <
ONLY ABLE
TO TALK
(e.g.counter) =) oA INPUT/
81034201 — - OUTPUT
— DATA VALID
NOT READY FOR DATA
La NOT DATA ACCEPTED
INTERFACE CLEAR
ATTENTION
SERVICE REQUEST
REMOTE ENABLE
END-OR-IDENTIFY
Figure A-1. HP-IB Interface Capabilities and Bus Structure
A-2
Interface
Management
Lines
1. Attention (ATN) specifies how and by which devices data on the
data input/output (DIO) lines is to be interpreted. ATN is pulled
low for commands (Command Mode) and released for data by
the controller.
In command mode the controller is active and all other devices
are waiting for instructions. Command Mode instructions which
can be issued by the controller fall into five groups:
a. Talker Address Group (TAG) commands enable a specific
device to talk. Only one device at a time may act as the
talker. When the controller addresses one device to talk, the
previous talker is automatically unaddressed and ceases to be
a talker.
b. Listener Address Group (LAG) commands enable a specific
device to listen. Up to 14 devices at a time may be listeners.
c. Universal Command Group (UCG) commands cause all bus
devices capable of responding to these commands from the
controller. to do so at any time regardiess of whether they are
addressed.
d. Addressed Command Group (ACG) commands are similar to
universal commands except that they are recognized only by
devices that are addressed as listeners only.
e. Secondary Command Group (SCG) commands are used when
addressing extended listeners and talkers, or enabling the
parallel poll.
. Interface Clear (IFC) puts the entire system into a predefined
quiescent state.
. Service Request (SRQ) is used by a device to indicate a need for
attention and to request an interruption of the current sequence
of events.
. Remote Enable (REN), in conjunction with other messages,
selects between alternate sources of device programming data
(typically HP-IB vs front panel).
5. End or Identify (EOI) indicates the end of a multiple-byte transfer
sequence, or, with ATN executes a polling sequence.
The Unlisten Address Command (UNL) unaddresses all listeners that
have been previously addressed to listen. The Untalk Address
Command (UNT) unaddresses any talker that has been previously
addressed to talk.
Handshake Lines 1. Data Valid (DAV) indicates the availability and validity of
information on the data lines.
2. Not Ready For Data (NRFD) indicates the state of readiness of
devices to accept data.
3. Not Data Accepted (NDAC) indicates the condition of acceptance
of data by device(s).
The DAV, NRFD, and NDAC lines operate in a three-wire interlocked
handshake process to transfer each data byte across an interface (see
figure A-2).
DAV
! |
| !
CDATA VALID) | |
= = === =
|
| |
| |
|
|
| some Г” Г АЦ.
NRFD | | READY | READY
(NOT READY FOR DATA) | | | | |
== | | | |
. SOME | ALL | | | |
NDAC ACCEPTED ACCEPTED : | |
CNOT DATA ACCEPTED) | | | | |
LOGIC STATES
(NEGATIVE
LOGIC) DAV1 1. 1. 9 © 29 29 1 1
NRFD1 1 1 4 1 1 e e 1
NDAC1 1 e eo! 1 41 4
B1034202
Figure A-2. HP-IB Handshake Sequence
A-4
A handshake sequence is entered with the listener-controlled NRFD and
NDAG both low. Line DAV is high. As each listener is ready to accept
data, it releases its Not Ready For Data (NRFD) line. When all listeners
have released their NRFD line, pull-up resistors on the line pull NRFD
high. The talker signals new Data Valid by pulling the DAV line low.
Listeners respond by pulling their NRFD outputs low. During the period
that listeners accept data, they release the Not Data Accepted (NDAC)
line. When data has been accepted by all the listeners, the NDAC line
goes high. Acknowledgment by the talker releases the DAV line, and
the handshake is completed by the listeners by pulling the NDAC low.
A legal handshake must proceed in the manner shown in figure A-2.
Note that the NRFD and NDAC lines may never go high (logic 0)
together.
A-5
B Serial Interface
Comparisons
introduction The following tabies show comparisons between seriai interfaces
covered in this document and interfaces not directly covered. Those
not directly covered in this document are shown here for reference
purposes.
Table B-1. Serial Interface Standards Comparison
Mechanical Electrical Functional
Interface Name Standard Standard Standard
RS-232-C RS-232-C RS-232-C RS-232-C
CCITT V.24 150-2110 CCITT \.28- CCITT v.24
MIL-188C RS-232-C MIL-188C RS-232-C
RS-449 (balanced) RS-449 RS-442 RS-449
RS-449 (unbalanced) RS-449 RS-423 RS-449
CCITT V.35 (balanced) 150-2593 CCITT V.11.(X.27)| CCITT V.24
CCITT V.35 (unbalanced) 150-2593 CCITT V.10(X.26) CCITT v.24
MIL-188-114 (balanced) MIL-188-114 MIL-188-114 MIL-188-114
CCITT X.20 (no clocks) -- -- --
CCITT X.21 (clocks) 150-4903 CCITT V.11 CCITT X.27
CCITT X.21-bis RS-232-C CCITT V.10 CCITT X.26
B-1
Table B-2. Serial Interface Characteristics Comparison
Interface Electrical
Interface Type Connector Speed Maximum Threshold
RS-232-C 25 pin <20Kbps +25 V +3 V
RS-449 | 37 pin -- -- --
RS-422 (balanced) -- <10Mbps +6 V +0.2 V
RS-423 (unbalanced) -- <100Kbps -- --
CCITT V.35 34 pin 56Kbps (bipolar current)
CCITT X.20/X.21 15 pin -- +10 V +0.3 V
CCITT V.10 (unbalanced) -- <100Kbps -- --
CCITT V.11 (balanced) -- <10Mbps -- --
Table B-3. Serial Interface Interchange Circuit Comparison
DTE/DCE EIA RS-232-C CCITT V.24 EIA RS-449
-- AB Signal Ground |102 Signal Ground |SG Signal Ground
DTE to DCE 102a DTE Common SC Send Common
DCE to DTE 102b DCE Common RC Receive Common
DTE to DCE IS Terminal in
Service
DCE to DTE|CE Ring Indicator|125 Calling IC Incoming Call
Indicator
DTE to DCE|CD Data Terminal (¡108.2 Data Terminal |TR Terminal Read
Ready Ready
DCE to DTE|CC Data Set Ready|107 Data Set Ready |DM Data Mode
DTE to DCE|BA Transmitted 103 Transmitted SD Send Data
Data Data .
DCE to DTE|BB Received Data |104 Received Data RD Receive Data
B-2
Table B-3. Serial Interface Interchange Circuit Comparison
(Continued)
DTE/DCE EIA RS-232-C CCITT V.24 EIA RS-449
DTE to DCE|DA Transmitter 113 Transmitter TI Terminal
Signal Signal Element Timing
Element Timing Timing
(DTE Source) (DTE Source)
DCE to DTE|DB Transmitter 114 Transmitter ST Send Timing
Signal Element Signal Element
Timing Timing
(DCE Source) (DCE Source)
DCE to DTE|DD Receiver 115 Receiver Signal [RT Receive Timing
Signal Element Element Timing
Timing (DCE Source)
DTE to DCE|CA Request to 105 Request to RS Request to
Send Send Send
DCE to DTE|CB Clear to Send |106 Ready for CS Clear to Send
Sending
DCE to DTE|CF Received Line |109 Data Channel RR Receiver Ready
Signal Received Line
Detector Signal Detector
DCE to DTE|CG Signal Quality|110 Data Signal SQ Signal Quality
Detector Quality
Detector
DTE to DCE NS New Signal
DTE to DCE 126 Select Transmit|SF Select
Frequency Frequency
DTE to DCE|CH Data Signal 111 Data Signaling |SR Signaling Rate
Rate Selector Rate Selector Selector
(DTE Source) (DTE Source)
DCE to DTE CI Data Signal 112 Data Signaling |SI Signaling Rate
Rate Selector Rate Selector Indicator
(DCE Source) (DCE Source)
Table B-3. Serial Interface Interchange Circuit Comparison
(Continued)
DTE/DCE EIA RS-232-C CCITT V.24 EIA RS-449
DTE to DCE|SBA Secondary 118 Transmitted SSD Secondary
Transmitted Backward Send Data
Data Channel Data
DCE to DTE|SBB Secondary 119 Received SRD Secondary
Received Data Backward Receive Data
Channel Data
DTE to DCE|SCA Secondary 120 Transmit SRS Secondary
Request to Backward Request to
Send Channel Line Send
Signal
DCE to DTE|SCB Secondary 121 Backward SCS Secondary
| Clear to Send Channel Ready Clear to Send
DCE to DTE|SCF Secondary 122 Backward SRR Secondary
Received Line Channel Receiver
Signal Received Ready
Detector Line Signal
Detector
DTE to DCE 141 Local Loopback [LL Local Loopback
DTE to DCE 140 Remote Loopback|RL Remote Loopback
DCE to DTE 142 Test Indicator [TM Test Mode
DTE to DCE 116 Select Standby |SS Select Standby
DCE to DTE 117 Standby SB Standby
Indicator Indicator
B-4
C
Introduction
The
RS-232-C/CCITT
V.24
RS-232-C/CCITT V.24
Overview
The RS-232-G/CCITT V.24 is a serial interface standard that has
predominated for many years. It originated with the requirements for
teletype interface, which accounts for the large voltage specifications in
the standard. it is still being designed into new equipment though it is
being replaced by the RS-449 standard, due to the much higher data
speeds of RS-449. The RS-232-C is the EIA standard conforming to
the international standard CCITT V.24. It expands on the international
standard to include the connector type, pin assignments, and electrical
standards.
The following information is intended to cover the main points of
RS-232-C. If you need more comprehensive information about the
standard, obtain the related documents from the ElA.
Most voltage interfaces in North America conform to ElA RS-232-C.
This standard specifies a 25-pin connector as the standard interface in
datacom networks. The connector is shown in figure C-1. The
interchange circuitry with pin assignments and CCITT V.24 equivalents
is shown in table C-1. In addition to the mechanical and electrical
requirements, the standard specifies an operating range of 0 to 20k bps
in bit-serial, synchronous, and asynchronous operation.
C-1.
Mechanical
The signal interface between the Data Communications Equipment
(DCE), usually a modem, and the Data Terminal Equipment (DTE), the
remote terminal or data processor, is located at the RS-232-C specified
connector between two equipments. The female is connected to the
DCE and the male to the DTE. Short cables of less than 15 metres (50
feet) are recommended, but longer cables may be used if the load
capacitance is suitable. The pin assignments shown in table C-1 must
be used, and unassigned pins may carry additional circuits determined
by mutual agreement between the communicating parties.
While RS-232-C designates 23 circuits, the number actually used in a
given application depends on the requirements of the application. In
some modems only nine of the 23 are used.
(TX)
(RX)
(RTS)
(CTS)
(DSR)
(CD)
DCE
AA AA
SBA
BA BA
DB(DCE CLK)
вв BB
see
CA | СА
DD(REC CLK)
cB CB
сс cc
SCA |
AB AB
CD (DTR)
CF CF
сс
СЕ
CH/CI
DA (DTE CLK)
SCF SCF
SCB SCB
M1034202/11JUNBS
Figure C-1. RS-232-C Connector with Pin Assignments
C-2
Table C-1. Interchange Circuits for RS-232-C and CCITT V.24 Equivalents
Direction |RS-232-C|CCITT V.24
Pin DTE/DCE Circuit Circuit RS-232-C Description
1 -- AA 101 Protective Ground
2 DTE to DCE BÂ 103 Transmitted Data
3 DCE to DTE BB 104 Received Data
4 DTE to DCE CA 105 Request to Send
5 DCE to DTE CB 106 Clear to Send
6 DCE to DTE CC 107 Data Set Ready
7 -- AB 102 Signal Ground (Common Return)
8 DCE to DTE CF 109 Received Line Signal Detector
9 -- -- -- (Reserved for Data Set
Testing)
10 -- -- -- (Reserved for Data Set
Testing)
11 -- -- -- Unassigned
12 DCE to DTE SCF 122 Secondary Received Line
Signal Detector
13 DCE to DTE SCB 121 Secondary Clear to Send
14 DTE to DCE SBA 118 Secondary Transmitted Data
15 DCE to DTE DB 114 Transmitter Signal Element
Timing (DCE Source)
16 DCE to DTE SBB 119 Secondary Received Data
17 DCE to DTE DD 115 Receiver Signal Element
| Timing (DCE Source)
18 -- -- -- Unassigned
19 DTE to DCE SCA 120 Secondary Request to Send
20 DTE to DCE CD 108.2 | Data Terminal Ready
21 DCE to DTE CG 110 Signal Quality Detector
22 DCE to DTE CE 125 Ring Indicator
23 DTE to DCE| CH/CI 111/112 | Data Signal Rate Detector
(DTE/DCE Source)
24 DTE to DCE DA 113 Transmitter Signal Element
Timing (DTE Source)
25 - - -- -- Unassigned
Electrical
Except for protective and signal grounds, all circuits carry bi-polar
low-voltage signals that are suitable for electronic circuits. All voltages
are measured at the connector with respect to Signal Ground (AB) and
cannot exceed £25 V. The electrical specifications are shown in table
C-2.
Control circuits can be designated as fail safe. This means that when
power is lost at the transmitter the receiver interprets the signal
condition as off.
Table C-2. Condensed Electrical Specifications for EIA RS-232-C
Driver output levels with
3 kohm to 7 kohm load
Driver output voltage with open circuit
Driver output impedance with power off
Output short circuit current
Driver slew rate
Receiver input impedance
Receiver input voltage
Receiver output with open circuit input
Receiver output with +3 V input
Receiver output with -3 V input
15 V > VoH > 5 V
-5 V > VOL
Vo] < 25 V
Ro > 300 ohms
|Io| < 0.5 A
dv/dt < 30 V/us
7 kohm > Rin > 3 kohm
+15 V compatible
with driver
MARK
SPACE
MARK
LOGIC -0- = SPACE = CONTROL ON
Noise Margin
Transition Region
Noise Margin
LOGIC -1- = MARK = CONTROL OFF
+5 V to +15 V
+3 V to +5 V
-3 V to +3 V
-3 V to -5V
-5 V to -15 V
C-5
D
Introduction
RS-449 AND RS-422
Overview
In 1975 uniform standards were established governing the electrical
parameters and interface between both high-speed and low-speed data
communications. These standards, RS-422 and RS-423 respectively,
specify characteristics without defining the mechanical interface.
RS-422 establishes characteristics of balanced voltage interface
circuits, while RS-423 establishes characteristics for unbalanced
circuits.
The standard for defining the mechanical and functional characteristics
of the RS-422 and RS-423 standards is RS-449. This standard was
released in 1977. ‘Only the RS-422 standard will be explained in this
appendix.
The RS-449/RS-422 The main differences between the RS-449 standard and the RS-232-C
standard are the following:
1. Two connectors, a 37-pin and a 9-pin, replace the 25-pin
connector used in RS-232-C applications. The 37-pin connector
accommodates the normal interchange circuits while the 9-pin
connector is used for secondary channel circuits. Both
connectors are from the same family as the RS-232-C connector.
2. Depending on the signaling rate, the cable distance between
equipments has been extended to 60 metres (200 feet) from the
RS-232-C distance of 15 metres (50 feet).
3. Ten interchange circuits not previously included in RS-232-C have
been defined in RS-449.
D-1
Mechanical
and Functional
EE ——
Electrical
4. The electrical characteristics (RS-422 and RS-423) in the
interface have been completely re-defined. Both balanced and
unbalanced circuits may be used within one interface connection.
Two categories of circuits are defined: Category | circuits, which
may be balanced or unbalanced depending on data rate, and
Category ll circuits, which are always unbalanced.
With a few additional provisions, equipment conforming to this standard
can be used with equipment conforming to RS-232-C standards.
The basic functional characteristic of the standard (RS-449) is to
operate up to a nominal limit of 2M bps in synchronous or
non-synchronous communication. The connector is shown in figure
D-1 on the next page. Table D-1 shows the interchange circuits with
pins, circuit names and mnemonics.
The balanced electrical standard (RS-422) for the new interface is too
involved to explain here without explaining virtually the entire standard.
This is because the higher data rates used with these standards
requires more involved specifications. The primary points are:
1. The signal voltage levels are less than |6V| open circuit and less
than |3V] at nominal load.
. The receiver requires a maximum differential voltage of 200 mV
to ensure the intended state over the common mode voltage
range of -7 V to +7 V. The receiver should operate with a
maximum differential input of 12 V.
. The nominal impedance is 100 ohms and the minimum load
impedance is not less than 90 ohms.
. The input impedance of the receivers should be greater than 4
kohms.
5. The short circuit current is 150 mA.
6. The risetime of the data pulses is less than 0.1(bit period) when
the bit period is greater than 200 ns and less than 20 ns when the
bit period is less than 200 ns.
The unbalanced electrical standard (RS-423) is also too involved to
explain in this document and is only mentioned because many of the
lines (Category Il) are operated unbalanced at all times. The
characteristics for the unbalanced signals are much the same as for
the balanced signals once the lack of the differential characteristic is
taken into account. Consult the EIA Standard for further information.
DCE DTE
O
SHIELD SHIELD
1
RC 20
51 2 SI
SPARE 21
SPARE - 3 SPARE
SD 22
SD 4 SD
ST 23
ST 5 ST
RD 24
RD 6
RS 25 RD
RS 7 RS
RT RT 26
8
cs or RT
cs 9 ;
LL IS es
DM LL
DM
TR DM
TR
RR TR
RR
ss RR
RL RL
IC a
i NS IC
SF/S SF /SR
TT
TT TT
58
™ ™
SC
SG SG
M1034201/13JUN85
Figure D-1. RS-449 Connector with Pin Assignments
D-3
Table D-1. Interchange Circuits for RS-449
Direction
Pins DTE/DCE Circuit|{Category Description
1 -- SHIELD -- --
2 DCE to DTE Si II Signaling Rate Indicator
20| DCE to DIE RC II Receive Common
3 -- SPARE -- --
21 -- SPARE -- --
4 22| DTE to DCE SD I Send Data
5 23| DCE to DTE ST I Send Timing
6 24| DCE to DTE RD I Receive Data
7 25| DTE to DCE RS I Request to Send
8 26| DCE to DTE RT I Receive Timing
9 27| DCE to DTE CS I Clear to Send
10 DTE to DCE LL II Local Loopback
28| DTE to DCE IS II Terminal in Service
11 29| DCE to DTE DM I Data Mode
12 30| DTE to DCE TR I Terminal Ready
13 31| DCE to DTE RR I Receiver Ready
14 DTE to DCE RL 11 Remote Loopback
32} DTE to DCE SS II Select Standby
15 DCE to DTE IC Il Incoming Call
33| DCE to DTE SQ II Signal Quality
16 DTE to DCE| SF/SR II Select Frequency/
Signaling Rate Selector
34| DTE to DCE NS Il New Signal
17 35| DTE to DCE TT I Terminal Timing
18 DCE to DTE TM II Test Mode
36| DCE to DTE SB II Standby Indicator
19 DTE to DCE SG 11 Signal Ground
37| DTE to DCE SC II Send Common
Using the HP 10342B
with other CPU Interfaces
The HP 1650A and HP 16510A logic analyzers can be configured as
two state analyzers. This configuration can be used to monitor a
microprocessor and a bus simultaneously. This allows you to analyze
the interaction between a microprocessor and a port.
To do this you must have an HP 10342B Bus Preprocessor, two HP
10269C General Purpose probe Interfaces, and a preprocessor for the
microprocessor that you're using.
The following example will show you how to configure your logic
analyzer to monitor an RS-232C port and a microprocessor
simultaneously. Although the example uses a 68000 microprocessor,
this technique will work with any microprocessor that can be analyzed
with three logic analyze probes or less.
1. Set all the switches on the 68000 Preprocessor (HP 10311B) to
the correct position and install the HP 10311B in the HP 10269C
General Purpose Probe Interface.
2. Connect the 68000 Preprocessor cables to the target system.
3. Install the RS-232C Preprocessor (HP 10342B) in the second HP
10269C General Purpose Probe Interface.
4. Connect the RS-232C Preprocessor cables to the R8-232C port
and set the front-panel switches on the HP 10342B to match the
setup of the port.
E-1
5. Plug the logic analyzer probes into the HP 10269C as follows:
HP 1650A and 16510A (into) HP 10269C
Pod connector
HP 10269C-1*
1 1
2 2
3 3
HP 10269C-2**
4 1
5 4
* HP 10269C-1 represents the HP 10269C
with the 68000 Preprocessor.
* HP 10269C-2 represents the HP 10269C
with the RS-232C Preprocessor.
6. Load the 68000 configuration and inverse assembler from the
disc provided with the 68000 Preprocessor.
7. Bring up the logic analyzer System menu and perform the
following:
a. Configure Analyzer 2 of the logic analyzer to be a state
analyzer.
b. Assign pods 4 and 5 to Analyzer 2 of the logic analyzer.
8. Bring up the Format menu of Analyzer 2 and set up the labels
and configuration for pods 4 and 5 as shown in figure E-1.
RS232 ST |- State Format Specification ( Specify Symbols )
Clock
Pod 5 Pod
| TTL TIL |
| Clock Cloc |
—
Activity >
TU
o
na
CITE AE
р ор но
[j++] +[+]+]+]0 [+]
Figure E-1. Format menu for Analyzer 2
9. Assign the following edge of the N clock to pods 4 and 5 as
shown in figure E-1.
10. Load IRS232_1 (inverse assembler file) into Analyzer 2 of the logic
analyzer.
11. Go to the Display menu for Analyzer 2 and change the base of
the data labei from hexadecimal (HEX) to "Invasm.”
E-3
E-4
12. This configuration allows you to view the microprocessor's and
13.
the port's activity individually, or simultaneously using a
"mixed-mode" display. Select the display that is most useful for
your application.
When you have finished configuring the logic analyzer, bring up
the Disc menu of the logic analyzer and store this configuration in
a separate file for later use. If both the 68000 inverse assembler
and the RS-232C inverse assembler are on the same disc as this
configuration file, the inverse assemblers will be automatically
loaded when the configuration is loaded.
2 Pacicano
10342-90912 PRINTED IN U.S.A.
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