Hewlett-Packard HP 59310B Bus Interface Kit Operating and Service Manual

 Ш
HEWLETT (hp; PACKARD
OPERATING AND SERVICE MANUAL
HP 59310B
BUS INPUT/OUTPUT
INTERFACE KIT
Manual Part No. 59310-90068
Printed: MAR 1979
Card Assembly: 59310-60101
Date Code: 1826
HEWLETT-PACKARD COMPANY
ROSEVILLE NETWORKS DIVISION
8000 FOOTHILLS BOULEVARD
ROSEVILLE, CALIFORNIA 95678
PRINTING HISTORY
The Printing History below identifies the Edition of this Manual and any Updates that are included. Periodically, update
packages are distributed which contain replacement pages to be merged into the manual, including an updated copy of
this Printing History page. Also, the update may contain write-in instructions.
Each reprinting of this manual will incorporate all past updates; however, no new information will be added. Thus, the
reprinted copy will be identical in content to prior printings of the same edition with its user-inserted update information.
New editions of this manual will contain new information, as well as all updates.
To determine what manual edition and update is compatible with your current software revision code, refer to the appro-
priate Software Numbering Catalog, Software Product Catalog, or Diagnostic Configurator Manual.
First edition . . . LL LL LL A AAA AAA RAS March 1979
Update |... вн нн вне аН нон е НН НннННеННеНноо August 1982
Reprint (incorporating update 1) ..... ooo August 1982
NOTICE
The information contained in this document is subject to change without notice.
HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard shall
not be liable for errors contained herein or for incidental or consequential damages in connection with
the furnishing, performance or use of this material.
Hewlett-Packard assumes no responsibility for the use of its software on equipment that is not furnished
by Hewlett-Packard.
This document contains proprietary information which is protected by copyright. All rights are
reserved. No part of this document may be photocopied, reproduced or translated to another program
language without the prior written consent of Hewlett-Packard Company.
Copyright © 1979 by HEWLETT-PACKARD COMPANY
li
CONTENTS
Section 1 Page
GENERAL INFORMATION
Introduction .............. eee e aerea. 1-1
Description ............. eerrieeoeooadon 1-1
Identification ..................................... 1-2
Equipment Supplied .............................. 1-2
Specifications .................... eee. 1-2
Software Available. ............................... 1-2
Hewlett-Packard Interface Bus Capabilities ........ 1-4
Program Code ....................... ou. ... 1-4
Addressing-Talking-Listening-Handshaking ........ 1-4
Functions of Instruments on the Bus............... 1-4
HP-IB Bus Lines ................................. 1-5
Control Lines ........................ ci... 1-5
Data Lines (DIO1-8) .............................. 1-6
Transfer Lines .................. i. .... 1-6
Data Transfer .................................... 1-7
HP-IB Electrical Characteristics ................... 1-9
HP-IB Physical Characteristics .................... 1-9
Section II Page
INSTALLATION
Introduction ............... aa aan aa aa 2-1
Unpacking and Inspection ......................... 2-1
Storage and Shipment ............................ 2-1
Environment ................................... 2-1
Installation................................. ...... 2-1
Power Requirements ........................... 2-1
Programming of Hardwired Options ............. 2-1
DIP Switches ............. i. 2-2
Standard Mode of Operation ....................... 2-3
Installing Printed Circuit Board
in Computer ...................................23
Performance Check ............................... 2-3
Interconnecting Cables ............................ 2-3
Cabling Length Restrictions .................... 2-3
Cabling Configurations ......................... 2-3
Section III Page
OPERATION AND PROGRAMMING
Introduction ................ 2. aa aa nee 3-1
HP Interface (HP-IB) Bus Lines ................... 3-1
Bus Functions Available to Computer .............. 3-1
Listen Functions ............................... 3-1
Talk Functions ................................. 3-1
Controller Functions ........................... 3-1
System Controller Functions .................... 3-2
Communication Forms Between I/O PCA and
Computer ............ aa aa aa ea aa a aa aan 3-2
Control Word ..................................... 3-2
Functions and Modes ........................... 3-2
Outputting the Control Word ................... 3-4
Control Word Group 1 Coding .................. 3-4
Control Word Group 2 Coding .................. 3-5
Control Word Group 3 Coding .................. 3-6
Status Word ............. redee aaaece., 3-6
Status Word Function .......................... 3-6
Inputting the Status Word ...................... 3-6
Status Word Coding ............................ 3-7
Data Output...................................... 3-9
Data Transfer Capabilities ...................... 3-9
Output Data Types ......................c...... 3-9
Output Data Registers .......................... 3-9
To Output Data ................................ 3-9
Output Data Format ........................... 3-9
Datalnput ................ i. 3-10
Data Transfer Capabilities ..................... 3-10
Input Data Type ................ cc. co... 3-10
Input Word Register .......................... 3-10
ToInput Data ................................ 3-11
Input Data Format ............................ 3-11
Flags eee Aa A a de na dan 3-12
Flag Organization ....................... Cee. 3-12
Main Flag ......... e. aa e area. 3-12
End of Record Flag (EOR) ..................... 3-12
Output Register Accepted Flag (ORA) .......... 3-12
Input Register Loaded Flag IRL) .............. 3-12
Interface Clear Flag (IFC) ............... aa 3-12
Service Request Flag (SRQ).............. RARE 3-12
Serial Poll Mode Flag (SPM)................... 3-12
DCPC Output Request Flag ................... 3-13
Machine I/O Instructions Operation ......... Ce 3-13
Difference in Use of I/O Instructions ..... Cee 3-13
STF Instruction ......................... Cee 3-13
OTA and OTB Instructions .................... 3-13
LIA, LIB, MIA and MIB Instructions ........... 3-13
SFS and SFC Instructions ..................... 3-13
STC and CLC Instructions ..................... 3-13
CLF Instructions ........................ RS 3-13
ASCI Mode ........... 2... ed. e 3-14
Enabling the ASCII Mode ..................... 3-14
Operation When Outputting ................... 3-14
Operation When Inputting ............... Cee 3-14
Section IV Page
THEORY OF OPERATION
Introduction ............. 2.0.2... eee. 4-1
General Theory ............... 02. eee. 4-1
Control Word Processing. ....................... 4-1
Bus Data Output............................... 4-1
Computer Data Input........................... 4-2
Status Information Input ....................... 4-2
Detailed Theory ............ iii... 4-2
Data Input/Output Control ...................... 4-2
Control Word Processing ........................ 4-2
Computer DataInput........................... 4-3
Status Information Input .......................... 4-5
Section V Page
MAINTENANCE
Introduction .............. aora 5-1
Troubleshooting .................................. 5-1
CONTENTS (continued)
Section VI Page Section VII Page
REPLACEABLE PARTS SCHEMATIC DIAGRAMS
Introduction ................... e. 6-1 Introduction ................. ae nana 7-1
Ordering Information ............................. 6-1 Schematic Diagram Notes ......................... 7-1
HP Part Number Organization .................... 6-3 Identification Markings on PC Boards ............. 7-1
Component Parts and Materials ................. 6-3 Component Locators .............................. 7-1
ILLUSTRATIONS
Title Page Title Page
59310B Bus Input/Output Kit ..................... 1-1 Output Data Formats ............................ 3-10
HP-IB Bus Structure .............................. 1-5 Input Data Formats ............................. 3-11
Transfer Timing .................................. 1-8 Simplified Block Diagram ......................... 4-1
Pin Connections of the HP-IB Cables ............. 1-10 Schematic Diagram Notes ......................... 7-2
Installation Information ........................... 2-2 59310B Block Diagram ............................ 7-3
Control Word Format ............................. 3-3 59310D Simplified Logic Diagram ................. 7-5
Status Word Format .............................. 3-7 59310B Component Locator ....................... 7-9
59310B Schematic Diagram ....................... 7-9
TABLES
Title Page Title Page
59310B Equipment Supplied....................... 1-2 Bus Cables ........ Ce 4 A 4 aa ea ae sa Aa aa ea an + 2-3
Specifications ...................... i. 1-3 Bus Line Nomenclature ........................... 3-1
Available Software. ............................... 1-4 ASCII Modes Codes ...................00000 0... 3-14
Relation of ATN and Transfer (Handshake) Reference Designations and
Lines (NRFD, NDAC and DAV)................. 1-6 Abbreviations .......... aa aa aa aa 6-1
Summary of Bus Timing .......................... 1-7 Replaceable Parts ................................. 6-4
Power Requirements .............................. 2-1 Manufacturer Code List ........................... 6-7
iv
GENERAL INFORMATION
SECTION
1-1. INTRODUCTION
This section provides general information on the
Hewlett-Packard Model 59310B Bus Input/Output Inter-
face Kit shown in figure 1-1. Included in this section are a
description of the computer interface, card identification,
equipment supplied, specifications and a description of the
Hewlett-Packard Interface Bus.
1-2. DESCRIPTION
The HP 59310B Bus Input/Output Interface Kit interfaces
the HP 1000 family of computers to the HP Interface Bus
(HP-IB). The HP-IB provides a two-way digital communi-
cations structure for one or more instruments with
ASCII-compatible interface. Hardware connection of com-
patible instruments is a matter of plugging them together
with the bus cables. Writing software programs for input/
output operations to/from the computer is made easier by
hardware features on the interface such as packing.
Driver and utility subroutines for BCS and RTE (Real-
Time Executive) are furnished as options to the 59310B.
The interface Printed Circuit Assembly (PCA) makes bus
functions available to the computer: listen and talk func-
tions, serial poll identification, controller clearing and
7700-175
Figure 1-1. 59310B Bus Input/Output Kit
1-1
HP 59310B
four types of interrupt flagging. The 59310B also has
parallel poll identification. Data transfers are byte-serial
and bit parallel (8-bit bytes) and packing is available.
Dual Channel Port Controller (DCPC) can be used for data
transfers.
1-3. IDENTIFICATION
Printed-circuit assembly revisions are identified by a let-
ter and a series code marked beneath the part number on
the PCA. The letter identifies the revision of the etched-
trace pattern on the unloaded PCA. The four-digit series
code pertains to the electrical characteristics of the loaded
PCA and component positions. If the series number does
not correspond exactly with the series number on the title
page of this manual, the PCA differs from the one de-
scribed in this manual. These differences are covered in
manual supplements available at the nearest HP Sales
and Service Office listed at the back of this manual. In
addition, there may be a suffix letter, e.g., (a), to indicate a
minor circuit change which enhances operation.
1-4. EQUIPMENT SUPPLIED
Table 1-1 lists the equipment supplied with the Model
59310B Bus Input/Output Kit. The kit is shown in figure
1-1.
1-2
Table 1-1. 59310B Equipment Supplied
STANDARD
/
DESCRIPTION
—
59310-60101
59310-60005
59310-90068
Bus I/O PCA (Printed Circuit Assembly)
Cable Assembly
Operating and Service Manual
Note: Diagnostic and Diagnostic Manual supplied with
Diagnostic Library. User's Guide supplied with RTE
Drivers Package.
1-5. SPECIFICATIONS
Specifications for the 59310B Bus Input/Output card are
provided in table 1-2.
1-6. SOFTWARE AVAILABLE
Software available for use with the 59310B is listed in
table 1-3.
General Information
Table 1-2. Specifications
ELECTRICAL CHARACTERISTICS
Bus Signal Lines: The Bus consists of 16 signal lines as follows:
DIO1 Data input/Output 1
DIOS Data Input/Output 8
DAV Data Valid
NRFD Not Ready for Data
NDAC Not Data Accepted
IFC Interface Clear
ATN Attention
SRQ Service Request
REN Remote Enable
FOI End or Identify
Logic Levels: High = 2.4V
Low =< 0.4V
All signals are Low = True except NRFD and NDAC.
Line Termination: Each of the 16 Bus signal lines is terminated with 3K) to Vcc and 6.2KQ to logic common. The value of Vcc depends on
the particular 2100 series model in which the card is installed. It varies between 4.5 to 5.0V.
Line Drivers: The signal lines DIO1 through DIOS, DAV, ATN and EOI are drivers with a circuit having the following characteristics:
Type: Tri-State
Output Voltage Low State: < 0.4V @ 48 mA
Output Voltage High State: = 2.4V @ —40 mA
The signal lines NRFD, NDAC, IFC, REN and SRQ are drivers having the following characteristics:
Type: Open Collector
Output Voltage Low State: < 0.4V @ 48 mA
Output Voltage High State: Determined by resistor termination
Leakage Current High State: < 0.250 mA @ 5.5V
Line Receivers: Each of the 16 Bus signal lines is received with a circuit having the following characteristics:
Type: Schmitt Trigger
Threshold Positive Transition: 1.5V
Threshold Negative Transition: 1.1V
Input Current Low State: —1.6 mA @ 0.4V
Input Current High State: 0.04 mA @ 2.4V
Maximum Cable Length: 2 metres per device connected, 20 metres total.
Operating Temperature: 0-55" Celsius
Power Requirements: The card requires the following amounts of power from the computer's power supply:
Supply Maximum Current Acquired
+30 None
+12 None
+ 5% 3.0A
—2 100 mA
—12 None
*Value of supply varies from 4.5 to 5.0V depending on model of computer.
PHYSICAL CHARACTERISTICS
Card Dimensions:
Width: 7-3/4 in. (196,8 mm)
Height: 8-11/16 in. (220,7 mm)
Weight:
Net Weight, card and cable: 4 Ib. (1,81 kg)
Shipping weight: 5 Ib (1,94 kg)
Connector: 48-pin printed circuit board edge connector (cable supplied has standard bus connector on outboard end.)
1-3
HP 59310B
Table 1-3. Available Software
MANUALS
PART NO.
DESCRIPTION
59310-90022
59310-90050
59310-90061
59310-90063
59310-90064
59310-90068
Driver Program Procedure (BCS, D.37A/B)
BCS Bus Utility Subroutine
Diagnostic Program Procedure
Real-Time Executive System Driver
(DVR37) Programming and Operating
Users Guide
Bus I/O Kit Operating and Service
SOFTWARE, BINARY PUNCHED PAPER TAPES
59310-60020
59310-60021
59310-60050
59310-16001
59310-16002
59310-16003
59310-16004
BCS Bus 1/0 Card Driver, non DCPC
(D.37A)
BCS Bus I/O Card Driver, DCPC (D.37B)
BCS Bus Utility Library (BLIB)
Bus I/O Card Diagnostic
RTE Bus I/O Card Driver, non-SRQ
(DVR37)
RTE Bus I/O Card Driver, SRQ (DVR37)
RTE Bus Utility Library
1-7. HEWLETT-PACKARD INTERFACE
BUS CAPABILITIES
HP-IB provides the capability of connecting from one to 14
compatible devices to the computer via one interface PCA.
Data is transferred over the Bus bidirectionally in 8-bit
bytes. Data can be transferred from a device to the com-
puter or from the computer to one or more devices simul-
taneously or from one to other devices under the direction
of the computer.
Some bus features must be used while others are optional.
For example, all instruments must be capable of being
addressed, but they may or may not be capable of being
operated by remote control. A system may have some
instruments operating under remote control while other
instruments obey their front and rear panel controls
(LOCAL). The same pins of all bus connectors of all in-
struments are connected in parallel making a parallel
communication network. This permits information to flow
in any direction on the bus and allows any instrument to
talk directly with another without going through a central
control unit.
1-4
1-8. PROGRAM CODE
Once a system has been assembled, programming is
simplified since almost all HP instruments use the same
code set. The seven-bit ASCII code set was selected be-
cause of its wide acceptance in the communications and
data handling fields. The HP-IB itself can transmit full
eight-bit binary data however. All of these features make
the job of interconnecting instruments into a system sim-
ple. The job has been reduced primarily to programming.
1-9. ADDRESSING-TALKING-
LISTENING-HANDSHAKING
A technique of addressing is used to determine which
instrument is to “talk” and those instruments that are to
“listen”. Data is sent from one instrument to another one
character (byte) at a time using an interlocked “Hand-
shake” technique. This technique assures that the sender
does not remove data before the receiver has finished
using the data. It also insures that data is not lost when
instruments having inherently different speeds communi-
cate on the same bus.
1-10. FUNCTIONS OF INSTRUMENTS ON
THE BUS
Instruments connected to the bus may function in one or
more of the following ways: (They function only after
being addressed.)
TALKER—Any instrument that is capable of sending or
transmitting information on the bus. There can be only
one talker at a time on the bus.
LISTENER—Any instrument that is capable of receiving
or accepting information on the bus is a listener. There
may be up to 14 listeners at the same time on the bus.
TALKER-LISTENER—AnN instrument has the capability
of both sending and receiving information on the bus as
defined above is both a talker and a listener. For example:
a counter is a talker when sending data to a recorder and
it is a listener when it is being programmed.
CONTROLLER —Any device that has been programmed
to have the responsiblility of managing the flow of infor-
mation between instruments connected to the bus is a
controller. It is capable of addressing one of the instru-
ments as a talker and one or more as a listener. It is a
talker and may be a listener. The HP interface bus permits
a system to have more than one controller, but only one
may be active at any time. (A controller can be contained
within the System Controller.)
SYSTEM-CONTROLLER—The system designer must de-
signate one instrument as the System Controller at the
time the system is configured. This instrument performs
all the functions of a Controller plus it has the ability to
gain absolute control of the Bus for programming instru-
ment modes, collecting and processing data, ete.
1-11. HP-IB BUS LINES
The HP-IB Bus structure consisting of 16 signal lines is
shown in figure 1-2. There are eight additional bus con-
ductors: one ground, one cable shield and six twisted pair
commons for six of the signal lines.
All sixteen signal bus lines have been given names and
mnemonic acronyms that describe the message being car-
ried on that line. There are three types of lines: Data (8),
Transfer (handshake) (3), and Control (management) (5).
NOTE
All instruments connected to the bus,
including the controller, must conform
to these descriptions.
DEVICE A
ABLE TO N
TALK, LISTEN,
AND CONTROLE
E
(e.9., calculator) À
db DATA
8 fines
DEVICE B
ABLE TO N
TALK AND E р
LISTEN E
{e.g., digital x
multimeter) DATA BYTE
TRANSFER
dro CONTROL
и 3 ines
DEVICE C
ONLY ABLE 3
TO LISTEN i
le.g., signal
gene ator GENERAL
| INTERFACE
q TN MANAGEMENT
va 5 lines
DEVICED
ONLY ABLE ,
TO TALK Ё
| |
{e.g., counter) i — | DATA
INPUT/OUTPUT
DATA VALID
NOT READY FOR DATA
NOT DATA ACCEPTED
INTERFACE CLEAR
ATTENTION
- SERVICE REQUEST
REMOTE ENABLE
|
END-OR-IDENTIFY
Figure 1-2. HP-IB Bus Structure
General Information
1-12. CONTROL LINES
The five control lines are used to manage the flow of
information over the data and transfer lines. They com-
municate control and status information between the ac-
tive controller and instruments connected to the bus. All
instruments must use ATN and IFC. An instrument may
or may not use REN, SRQ and EOI.
ATN (Attention) is driven by the active controller to place
the bus in either the COMMAND (Low) or DATA (High)
mode. All other instruments must monitor ATN at all
times.
When the controller sets ATN to its low state, the bus is in
the Command Mode. The primary purpose of the Com-
mand Mode is to permit the controller to send commands
or address those instruments that are to communicate
when the bus is placed in the Data Mode. Also, the control-
ler may send “universal commands” while the bus is in the
Command Mode.
When the controller puts ATN to its high state, the bus is
in Data Mode. The instrument that was addressed to talk
and those that were addressed to listen will now communi-
cate on the Data Lines.
ATN may be set low or high at any time by a controller,
however, it is usually changed at the end of a transfer
(handshake) cycle so that data information is not lost.
Timing of the transfer lines with respect to ATN is given
below under Transfer Lines.
IFC (Interface Clear) is used by the system controller to
initialize the bus. Only the system controller can drive
IFC and it must be monitored by all other units on the bus.
When the system controller sets IFC low for at least 100
usec the following takes place: all talkers and listeners
are stopped, serial poll mode is disabled, and control is
returned to the bus controller. When IFC is high it has no
effect on the bus operation. The system controller may set
IFC low at any time.
REN (Remote Enable) is one of the conditions for operat-
ing instruments under Remote Control. Only instruments
capable of Remote operation use REN and they monitor it
at all times. Instruments that do not use REN terminate
the line in a resistor load. The system controller driver
REN may change its state at any time.
SRQ (Service Request) is driven to its low state by an
instrument to indicate that it wants the attention of the
controller. SRQ may be set low by an instrument at any
time except when IFC is in the low state. Only the control-
ler senses SRQ. Some instruments do not use SRQ but
terminate it in a resistor load.
EOI (End or Identify) may be used to indicate the end of an
instruments character string. When the bus is in the Data
Mode (ATN is high), the addressed talker may indicate the
end of its data setting EOI low at the same time it places
the last byte on the Data Lines.
1-5
HP 59310B
1-13. DATA LINES (DIO1-8)
The data lines are used to communicate all data including
input, output and program codes, addresses control and
status information between instruments connected to the
bus. These data are passed one character (byte) at a time
(1.e., byte serial and bit parallel) under control of the
Transfer Lines. In most instruments these data are based
on the 7-bit ASCII code set. Unused data lines terminate
in a resistor load.
1-14. TRANSFER LINES
The three transfer (handshake) lines are used to execute
the transfer of each byte of information on the data lines.
All instruments use these lines and employ an interlocked
“handshake” technique to pass information. This allows
asynchronous data transfer without timing restrictions
being placed on any instrument connected to the bus.
Transfer of each byte is accomplished at the speed of the
slowest instrument. The three transfer lines are: NRFD,
NDAC, and DAV.
NRFD (Not Ready for Data) is the transfer (handshake)
line that indicates all listeners are ready to accept infor-
mation on the data lines. NRFD is driven by all listeners
(all instruments when ATN is low and only by those in-
struments addressed to listen when ATN is high). It is
sensed by talkers: the controller when ATN is low, and the
instrument addressed to talk when ATN is high.
When NRFD is high, all listeners are unconditionally
ready for data. The talker may, at its own time, put a byte
of information on the data lines and set DAV low. When
NRFD is low, one or more listeners are not ready for data.
When the controller sets ATN low, all instruments must
set NRFD to its high state within 200 nanoseconds, i.e., if
an instrument is “Ready for Data” it places NRFD to its
high state and if it is “Not Ready for Data” it sets NRFD to
its low state. When the controller sets ATN high, all
instruments that have not been addressed to listen will
not drive NRFD, those addressed to Listen will set NRFD
to its high state within 200 ns.
A listener must not set NRFD low until it senses DAV is
low. It may do so before or at the same time that it sets
Table 1-4. Relation of ATN and Transfer (Handshake) Lines (NRFD, NDAC and DAYV)
NRFD NDAC DAV
MODE ATN
LOW HIGH LOW HIGH LOW HIGH
One or All units One or All units Controller Controllers
A more units ready for more units have has valid data 1s
D not ready data have not accepted data on not valid
D L for data accepted data DIO lines
R O data
E W
с 1. Driven by all units except controller 1. Driven by controller
с 2. Sensed by controller 2. Sensed by listeners
3. All units set NRFD and NDAC to valid state within 3. See DAV above for
200 nanoseconds after ATN goes LOW timing
One or All One or All The The
more addressed more addressed addressed addressed
listeners listeners listeners listeners talker talker
not ready ready for have not have has valid data is
D H for data data accepted accepted data on not valid
A | data the data lines
T G
A H 1. Driven by all units addressed to listen. 1. Driven by the instru-
2. Sensed by the unit addressed to talk. ments addressed to
3. All units not addressed will not drive. TALK
4. All addressed listeners set both NRFD and NDAC to valid 2. Sensed by all instru-
within 200 nanoseconds after ATN goes HIGH. ments addressed to
LISTEN
3. See DAV above for
timing.
NDAC high. It must not return NRFD high until it senses
DAV is high and may do so after, or at the same time that
it sets NDAC low.
NDAC (Not Data Accepted) is the transfer line that indi-
cates the acceptance of information on the data lines.
NDAC is driven by all listeners. That is, all instruments
when ATN is low and only those instruments addressed to
listen when ATN is high. It is sensed by talker and the
controller when ATN is low and by the instrument ad-
dressed to talk when ATN is high.
When NDAC is high, all listeners have unconditionally
accepted the byte of information that is on the data lines
and no longer need it. The talker may, at its own time set
DAY high, remove that byte of information and continue.
When NDAC is low, one or more listeners has not accepted
the information on the data lines.
When the controller sets ATN low, each instrument must
set NDAC to its high state within 200 nanoseconds. When
the controller sets ATN high, the instruments that have
not been addressed to listen will not drive NDAC, those
addressed to listen will set NDAC to its true state within
200 nanoseconds.
A listener must not set NDAC low until it senses DAV is
high. It may do so before or at the same time that it sets
NRFD high. It must not return NDAC high until it senses
DAV is low and it may do so after or at the same time that
1t sets NRFD low.
DAV (Data Valid) is the transfer line that indicates the
validity of information on the data lines.
DAV is driven by talkers: the controller when ATN is low
and by the instrument addressed to talk when ATN is
high. It is sensed by listeners and by all instruments if
ATN is low and by those instruments addressed to listen
when ATN is high.
When DAV is low, the states of data lines DIO1 through
DIO7 are unconditionally valid and may be accepted by all
listeners at their own time. DAV can only be driven low if
NRFD and IFC are high. When DAV is high, the informa-
tion on the data lines is not valid. DAV cannot be set high
unless NDAC is high and NRFD is low.
The talker has the responsibility of allowing enough time
for cable rise time and ringing. It does this with DAV. The
controller after placing the bus in the Address Mode (sets
ATN low) must wait at least one microsecond before set-
ting DAV low. Of course it must not do so unless NRFD is
high. In either the Address or Data Mode, a talker de-
signed with open-collector circuits must not set DAV low
for at least two microseconds after placing valid data at its
output connector. Those designed with tri-state integrated
circuits must wait at least 500 nanoseconds.
General Information
Table 1-5. Summary of Bus Timing
IFC INTERFACE CLEAR | The System Controller must
set IFC low for at least 100
microseconds to clear the
bus.
TRANSFER LINES WITH | When sending an Address or
RESPECT TO ATN a Universal Command the
controller may set DAV low
only after sensing that NRFD
IS high, and ATN has been
low for at least one micro-
second.
When a controller changes
ATN from its high to the low
state or from low to high, all
Listeners (all instruments
when ATN is low and those
addressed to Listen when
ATN is high) put both NRFD
and NDAC to their high state
in less than 200 nanoseconds.
TRANSFER LINES WITH | After changing the informa-
RESPECT TO THE DATA] tion on one or more Data
Lines, the ta/ker (the Con-
troller when ATN is low or the
instrument addressed to talk
when ATN is high) must wait
before setting DAV low. It
waits 2 +sec if designed with
open-collector circuits and
0.5 microsecond if designed
with tri-state integrated
Circuits.
1-15. DATA TRANSFER
Transfer of data on the bus is asynchronous. It places no
restrictions on the data rates of instruments connected to
the bus. The timing and levels required to transfer a byte
of information on the data lines are shown in figure 1-3.
Transfer is under the control of three lines DAV, NRFD
and NDAC. The talker (sender of data) drives the Data
Lines and DAV (Data Valid) and the listeners (acceptors of
data) drive both NRFD (Not Ready for Data) and NDAC
(Not Data Accepted).
The transfer of a byte or data is initiated by all listeners
signifying they are ready for data by setting NRFD high.
When the talker recognizes NRFD is high and has placed
valid data on the data lines it sets DAV low. When the
listener senses that DAV is low and have finished using
the data, they set NDAC high. Notice that the assertive or
action state of both NRFD and NDAC is high. Since all
1-7
HP 59310B
SEQUENTIAL REQUIREMENTS OF THE THREE WIRE TRANSFER
ty — — tg
?2777777777777777777772772722777777?
DATA* do |
DAV +
(TALKER)
NRED Fr
(LISTENER)
NDAC
(LISTENER)
ton toy to Lo to to ta
EVENTS
to : Listener becomes ready to accept data.
ty : Talker has put data on the lines.
to : Indicates data is valid.
ty : Listener has accepted the data and no longer requires it held valid.
to : Talker indicates the data is no longer valid and may change it.
ta : Listener indicates it is ready for new data.
ty : A new cycle begins (equivalent to to).
t_, tot, : Time that data is put on lines before DAV is set low.
*A composite of the DIO1 through DIO7 lines for illustrative purposes.
(The curved lines indicate interlocked signal sequence.)
Figure 1-3. Transfer Timing
1-8
instruments on the bus have their corresponding lines
connected together (e.g. NRFD), all listeners must be in a
high state before that line goes high. This wire-AND situ-
ation allows a talker to recognize when the slowest lis-
tener has accepted a byte of data and is ready for the next
byte.
Figure 1-3 also shows the timing of the transition to the
non-assertive state of these lines. A listener may set
NRFD low as soon as it recognizes that DAV has been set
low and must do so before or at the same time it puts
NDAC high. The talker may return DAV to its high state
after it detects that NDAC is high. A listener may set
NDAC low as soon as it recognizes that DAV is high and
must do so before or at the same time it places NRFD in its
high state.
1-16. HP-IB ELECTRICAL
CHARACTERISTICS
All 16 bus lines are designed to be compatible with TTL or
DTL integrated circuits. Because wire-ANDING is used
on some lines the line drivers must be either open collector
or tri-state. Each line in every instrument is terminated
in a resistor divider consisting of a 3KQ connected to 5V
and a 6.2K0 connected to ground. Typically receivers are
hex inverters and the drivers are open collector NAND
gates. These may be put into four groups:
a. Receivers only: They require —3.2 mA max. at 0.4V
drive (A Standard Load).
b. Senders only: They are capable of sinking 45 mA at
+0.4V (A Standard Driver).
General Information
c. Bi-directional Lines: They are a combination of the
above, i.e., when a talker, capable of sinking 45 mA at
0.4V. When a listener, requires —3.2 mA at 0.4V to
drive. Examples are the Data Lines (DIO1 through
DIO7 for instruments using the ASCII code) and the
handshake lines (NRFD, NDAC and DAV).
d. Lines not used by an instrument are connected to a
3.0KQ resistor to +5V, and 6.2K(} resistor to signal
ground (a Standard Termination). For example, DIO8
for instruments using the ASCII code or those not
using REN, SRQ or EOL
E a
BUS < e NC
6.2K
1-17. HP-IB PHYSICAL
CHARACTERISTICS
Bus cables are available for connecting instruments into a
system. These have one overall shield to reduce suscepti-
bility to external noise. The cables use a mixture of indi-
vidual wires and twisted pairs to reduce crosstalk. Both
ends are identical. They are terminated in two 24-pin
piggy back connectors; one male and one female. Pin con-
nections of these connectors are shown in figure 1-4.
1-9
HP 59310B
DIO1
DIO?
DIO3
DI04
ЕО!
DAV
NRFD
NDAC
IFC
SRQ
ATN
GROUND ONLY AT ——m= SHIELD
SYSTEM CONTROLLER
1 13
2 14
3 15
4 16
5 17
6 18
7 19
8 20
9 21
10 22
11 23
12 24
D105
D106
DI07
DIOS
REN
P/O TWISTED PAIR WITH 6 >
P/O TWISTED PAIR WITH 7
P/O TWISTED PAIR WITH 8
P/O TWISTED PAIR WITH 9
P/O TWISTED PAIR WITH 10
P/O TWISTED PAIR WITH 11 J
SIGNAL GROUND
SHOULD BE GROUNDED
NEAR TERMINATION
OF OTHER WIRE
OF TWISTED PAIR
> TYPE 57 MICRORIBBON CONNECTOR
1-10
Figure 1-4. Pin Connections of the HP-IB Cables
SECTION
INSTALLATION т
2-1. INTRODUCTION
This section contains information for unpacking, inspec-
tion, repacking, storage, and installation. Information on
the performance check and interconnecting cables is also
included.
2-2. UNPACKING AND INSPECTION
If the shipping carton is damaged, ask that the carrier's
agent be present when the carton is opened. Inspect the
components for damage. If there is physical damage or the
interface fails to meet electrical specifications, notify the
carrier and the nearest Hewlett-Packard Sales and Ser-
vice Office immediately (offices are listed at the back of
this manual). Retain the shipping carton and padding
material for the carrier's inspection. The sales and service
office will arrange for the repair or replacement of your
Bus I/O Interface Kit without waiting for the claim
against the carrier to be settled.
2-3. STORAGE AND SHIPMENT
To protect the Bus Input/Output PCA (Printed Circuit
Assembly) during storage or shipment, good commerical
packing methods should be used. Reliable commercial
packing and shipping companies have the facilities and
materials to adequately repack an instrument.
NOTE
Before returning any product or compo-
nent to Hewlett-Packard, contact the
nearest Hewlett-Packard Sales and Ser-
vice Office for instructions
2-4. ENVIRONMENT
Conditions during storage and shipment should normally
be limited as follows:
a. Maximum altitude: 25,000 feet.
b. Minimum temperature: —40°F (~40°C).
c. Maximum temperature: +167°F (+75°C).
2-5. INSTALLATION
The following steps are suggested for preparing and in-
stalling the Bus Input/Output PCA into the computer:
a. Determine that the computer has sufficient power to
support the addition of the Bus Input/Output PCA.
(Refer to paragraph 2-6.)
b. Set up the hardwired options on the PCA using
switches or jumpers for desired system functions.
(Refer to paragraph 2-7.)
c. Install printed circuit board assembly in computer.
(Refer to paragraph 2-10.)
d. Verify proper operation using the Diagnostic Pro-
gram. (Refer to paragraph 2-11.)
e. Interconnect system observing cabling restrictions.
(Refer to paragraph 2-13.)
2-6. POWER REQUIREMENTS
Before installing the Bus Input/Output PCA in the com-
puter, determine that the additional power consumed will
not overload the computer power supply. The power re-
quired by the PCA is given in table 2-1.
Table 2-1. Power Requirements
SUPPLY VOLTAGE | MAX. CURRENT REQUIRED
+30 None
+12 None
+ 5% 3.0 A
—2 100 mA
—12 None
*Nominal value of voltage can vary between 4.5 to
5.0 volts depending on the computer model.
2-7. PROGRAMMING OF HARDWIRED
OPTIONS
Before installing the Bus YO PCA in the computer, sev-
eral “options” must be programmed for the desired user
application and system function by use of DIP switches.
2-1
HP 59310B
The DIP switches allow easy changing of the card's func-
tion to accommodate changing system requirements.
The hardwired programmable functions of the PCA are as
follows:
a. BUS ADDRESS, 5 4 3 2 1: Defines the lower five
bits of the Talk and Listen addresses that the PCA
will recognize as its own. The value set on the
switches of DIP switch 2 must be between 00 000 (0,)
and 11 110 (36,5). Address 37; 1s reserved for the Unlis-
ten and Untalk addresses. (Located on DIP switch 2.)
b. REN: When ON (switch open), enables the PCA to
drive the BUS signal line REN. When OFF, disables
the PCA from driving the BUS signal line REN. (Lo-
cated on DIP switch 2.)
с. IFC: When the switch is set to ON (switch open),
enables the PCA to drive the BUS signal line IFC.
When the switch is set to OFF, disables the PCA from
driving the BUS signal line IFC. (Located on DIP
switch 2.)
d. SHIELD: When the switch is set to CNX, connects
the shield in the bus cable to the logic circuit common.
When the switch is set to DNX, disconnects the shield
in the bus cable from the PCA’s common. It should be
set to CNX (closed). (Located on DIP switch 2.)
e. PP ID CODE: Defines the code that the PCA will
send in response to a Parallel Poll. Setting the switch
to ON will cause the PCA to use the DIO signal line
specified to be used. (Located on DIP switch 1.)
2-8. DIP SWITCHES
There are two DIP switches located in the upper left and
lower left of the printed circuit board. See figure 2-1.
The upper left hand location (SW1) defines the identifica-
tion code to be used by the card in response to a parallel
poll. The lower left hand location (SW2) defines the BUS
ADDRESS, REN and IFC enables, and the SHIELD
connection.
SW1
SW2
PE PTE me y NA
EEE EEE
7700-174
Figure 2-1. Installation Information
2-2
Select the switch positions of each DIP switch according to
the functions desired as described in paragraph 2-7. The
arfows associated with the labeling on the printed circuit
board indicate which side of the rocker is to be depressed
to cause the indicated effect. A closed switch is logical 0
and an open switch is logical 1.
2-9. STANDARD MODE OF OPERATION
The normal use of the Bus I/O PCA is the System Control-
ler function. This requires the switches to be set.
Set DIP switch 1 (upper left) as follows:
a. PP ID CODE: to all OFF (all open)
Set DIP switch 2 (lower left) as follows:
a. BUS ADDRESS: sw no. 54 3 21
state 0000 0 (005) (all closed)
b. REN (sw. no. 6): to ON (open)
c. IFC (sw. no. 7): to ON (open)
d. SHIELD (sw. no. 8): to CNX (closed)
NOTE
The BUS Address may be set to any
value between 00 000 (0g) and 11 110
(365). The value 00 is the preferred ad-
dress for the computer when it is used as
the system controller.
2-10. INSTALLING PRINTED CIRCUIT
BOARD IN THE COMPUTER
After having selected hardwired options, the BUS I/O
PCA may then be installed in the computer as follows:
a. Set the computer’s power to OFF.
b. Insert the PCA into one of the available I/O slots of
the computer. (Since the location and position will
vary depending on the model of computer, refer to the
computer manual for details.)
2-11. PERFORMANCE CHECK
To verify proper operation of the BUS I/O Interface run
the diagnostic program as described in the 59310A/B Bus
Input/Output Card Diagnostic Manual (part no. 59310-
90061).
2-12. INTERCONNECTING CABLES
Supplied with the BUS 1/О Kit is a 4 metre cable (59310-
60005) which contains a printed circuit board edge con-
Installation
nector at one end and a piggy-back connector at the other
end. The printed circuit board edge connector end is con-
nected to the BUS I/O PCA J1. The end of the connector
opposite from the cable must be installed so it is closest to
the extractor labeled “BUS INPUT/OUTPUT.
The piggy-back connector end is connected to the
peripheral device. Other devices may be added to the bus
by use of the standard bus cable (not supplied), listed in
table 2-2.
Table 2-2. Bus Cables
LENGTH ACCESSORY NUMBER
1 metre 10833A
2 metres 10833B
4 metres 10833C
0.5 metres 10833D
2-13. CABLING LENGTH RESTRICTIONS
In order to ensure proper operation of the bus, two rules
must be observed regarding the total length of bus cables
when they are connected together. These are:
a. The total length of cable permitted to be used with
one Bus I/O PCA must be less than or equal to two
metres times the number of devices connected to-
gether. (The Bus I/O PCA is counted as one device.)
b. The total maximum length of cable must not exceed
20 metres.
Rule (a.) implies that there may be up to 4 metres of cable
between the first two devices (2 units x 2 m./device = 4
m.). Additional units may be added using 2 metre cables
up to a total of 10 units (10 units X 2 m./device = 20
metres); e.g., using one 4-metre and eight 2-metre cables
(4 + (8 x 2) = 20). If more than ten devices are to be con-
nected together, cables shorter than two metres must be
used between some of the devices. For example, 15 devices
can be connected together using one 4-metre and thirteen
one-metre cables 4 + (13 x 1) = 17. Other combinations
may be used as long as both of the requirements of rule (a.)
and (b.) are met. In making calculations, remember to
count the Bus I/O PCA as one device.
2-14. CABLING CONFIGURATIONS
There are no restrictions to the ways cables may be con-
nected together. However, it is recommended that no more
than 3 to 4 piggy-back connectors be stacked together on
one device. The resulting structure can exert great force
on the panels of the device where the connector is mounted
and could cause mechanical damage.
The configuration may be linear (all cables connected end
to end) or in a star (all cables branching out from a central
point) or any combination of the above.
2-3 /2-4
OPERATION AND PROGRAMMING
SECTION
3-1. INTRODUCTION
This section explains the operation and programming of
the 59310B Bus I/O PCA (Printed Circuit Assembly) in
table 3-1.
3-2. HP INTERFACE (HP-IB) BUS LINES
The HP-1B has 24 lines with 16 signals. The bus lines and
changes are listed in table 3-1.
Table 3-1. Bus Line Nomenclature
ABBREVIATION NAME ABBREVIATION NAME
DIO1 NRFD Not Ready
DIO? for Data
DIO3 Data Input
DIO4 Output NDAC Not Data
DIOS 1 thru 8 Accepted
DIO6
DIO7 IFC interface
DIOS Clear
DAV Data SRQ Service
Valid Request
ATN Attention
EIO End or
Identify
REN Remote
Enable
Common
(Ground)
3-3. BUS FUNCTIONS AVAILABLE TO
THE COMPUTER
Several functions on the HP-IB are usable by the compu-
ter. These functions are described in the following parag-
raphs.
3-4. LISTEN FUNCTIONS
The computer can input data from the bus when ad-
dressed. The listen functions include the following
capabilities.
Addressable Listen: The PCA becomes addressed to
Listen when a controller sends its Listen Address.
Programmable Listen: The PCA becomes addressed to
Listen by the computer via software control.
End of Record Detection: An End of Record (EOR) Flag
will be set if the card is addressed to Listen and is
receiving data and the EOI line goes “low”. In addition,
if enabled by software control, an ASCII Line Feed
(0125) on the data lines will also set the EOR Flag. The
EOR Flag can be tested by software or used to generate
an interrupt.
Service Requesting: If enabled by software control and
not addressed to Listen and ready to receive data, the
PCA will generate a Service Request (SRQ).
3-5. TALK FUNCTIONS
The computer can output data to the bus when addressed.
The talk functions include the following capabilities:
Addressable Talk: The PCA becomes addressed to Talk
when a controller sends its Talk Address.
Programmable Talk: The PCA becomes addressed to
Talk by the computer via software control.
End of Record Signaling: The computer can set EOI
Low with the last byte or after the last byte indicating
that End of Record has occurred. If enabled by program
control, EOI will be set Low if an ASCII Line Feed (0123)
is output.
Service Requesting: If enabled by software control and
not addressed to talk and ready to send data, the Bus I/O
PCA will generate a Service Request (SRQ).
Serial Poll Identification: Allows the computer to re-
spond to a controller making a serial poll. The controller
sending the “serial poll enable” command will set the
“serial poll mode” flag which may be tested via software
or used to cause an interrupt. The computer may then
send its status byte to the controller when addressed to
Talk.
3-6. CONTROLLER FUNCTIONS
The computer can manage the activities on the bus by
sending addresses and universal commands. The comput-
er can only perform this role if its active status is set. (A
controller becomes “active” if designated by another con-
troller or if a system controller and it activates itself.) The
controller functions include the following capabilities:
3-1
HP 59310B
Addressing and Universal Commands: The computer
sets ATN Low via program control and sends address or
commands to devices in the bus.
Service Request Processing: The computer can
monitor for the Service Request (SRQ) line or enable it
to cause an interrupt to determine if a device on the bus
1s requesting service.
Serial Polling: Allows the computer to determine the
device(s) that have caused a Service Request. A serial
poll is executed via software by sending universal com-
mands and addresses and using the Listen Mode.
Parallel Polling: Allows the computer to determine the
device(s) needing service by sending one universal
command to all devices and reading the status bits re-
turned on the data lines. If jumper W1 is installed a
Parallel Poll response causes a computer interrupt.
3-7. SYSTEM CONTROLLER FUNCTIONS
The PCA as a System Controller performs all of the func-
tions of a controller including the following additional
capabilities:
Interface Clear: Allows the computer to utilize the bus
or regain control by setting the bus signal line Interface
Clear (IFC) “low”.
Remote Enable Control: Allows the computer to enable
programmable devices to switch from local to remote
control by setting the bus signal line Remote Enable
(REN) “low”.
Automatic Activation of Controller Functions: The
Bus VO PCA automatically becomes the Active Control-
ler when powered up or if it sets IFC “low”.
3-8. COMMUNICATION FORMS
BETWEEN THE 1/0 PCA AND
COMPUTER
The information that can be transferred between the com-
puter and the Bus I/O PCA under program control takes
five forms. These include four data types which can be
passed between the A/B registers and the PCA’s registers.
They are: (1) the Control Word, which establishes the I/O
card’s operating mode, (2) the Status Word which provides
information about the condition of the card and the Bus,
(3) Output Data, which is transmitted from the computer
to the bus and (4) Input Data which is received from the
bus. Input Data and Output Data may also be transferred
under DCPC control. These are discussed in detail in
paragraphs 3-19 to 3-30.
3-2
The fifth type of communication from the PCA is the flags.
There are eight flags, of which seven can be tested by
program instructions and one is used with DCPC. Opera-
tion of the flags is discussed in paragraphs 3-31 to 3-40.
Operations under program control are controlled by use of
the various computer I/O instructions.
3-9. CONTROL WORD
The control word is a 16 bit word (see figure 3-1) which is
output to the I/O PCA under program control. It is divided
into three parts referred to as Group 1, 2 and 3. Group 2 is
further divided into two sub-groups, Group 2A and 2B.
The effect on the I/O PCA of each group is independent
from the other groups. Each group may be used individ-
ually or in combinations.
3-10. FUNCTIONS AND MODES
The control word is used to select the operating modes and
bus functions that the PCA is to perform.
The operating modes controllable with the control word
are as follows:
1. Flag selection for interrupt or by testing with the
SES or SFC instructions
2. Packaging enable/disable
3. DCPC input or output flag selection
4. Service Request enable/disable
5. ASCII Mode enable/disable
6. Forced input of data (without a handshake cycle)
7. Initialize flags
The Bus functions controllable with the Control Word are
as follows:
1. Remote/Local
2. Active/Inactive Controller Function
3. Enable talker functior/disable
4. Enable listener function/disable
5. Controller functions
a. Data Mode/Command Mode Select
b. Parallel Poll
Operation and Programming
GROUP 1
GROUP 2
BUS FUNCTION CONTROL
GROUP 3
MODE CONTROL
MICS
10
11
12
13
14
INTERFACE (BUS) CLEAR COMMAND
LOCAL COMMAND
REMOTE ENABLE COMMAND
NOP
0
1
0
1
1:ENABLE
1:ENABLE
1:ENABLE
0:OUTPUT
1: INPUT
1: ENABLE
1:ENABLE
1:ENABLE
1:ENABLE
DEACTIVATE CONTROLLER FUNCTION COMMAND
0
0:DISABLE
0:DISABLE
O:DISABLE
O:DISABLE
0:DISABLE
EE —
O:DISABLE
O:DISABLE
o
zZ
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2 23.2
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c9z0 05% те
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© = «< отр «Е о <
HU 54 Fu9 z
td oui«= £a
ar SE y 8% = ©
бош ь Я Q ©
rer Zona no O0
O:DISABLE
с xx о - © — со TALK m
1:ENABLE
+ xoo-- + O:DISABLE LISTEN <
1:ENABLE
NES - = = = = = = = —
© ooo oo — —
GROUP 3 SELECT
ASCII MODE
GROUP {
/
GROUP 2B (
GENERATE SERVICE REQUEST
DMA FLAG SELECT
PACKING
END OF RECORD FLAG
OUTPUT REGISTER ACCEPTED FLAG
INPUT REGISTER LOADED FLAG
15
IF INACTIVE CONTROLLER
1:ENABLE SPM FLAG
IF ACTIVE CONTROLLER
1:ENABLE IFC AND SRQ FLAGS
0: DISABLE
Figure 3-1. Control Word Format
HP 59310B
3-11. OUTPUTTING THE CONTROL WORD
The control word is output to Bus I/O Interface PCA by the
following sequence of instructions:
LDA CTLWD
STF SC
OTA SC
CTLWD OCT <value>
SC EQU <select code of BUS I/O card>
Do not include a NOP instruction in this program se-
quence as this will cause errors on the I/O bus. The value
of the control word is a function of the desired operating
mode of the I/O PCA and bus functions.
3-12. CONTROL WORD GROUP 1 CODING
Group 1 of the control word consists of seven coded com-
mands using bits 0 thru 2. The commands of group 1
control the following: IFC one-shot, remote enable flip-
flop, and active flip-flop. The active flip-flop forces an
input cycle and initializes certain I/O control and flag
flip-flops. The coding and function of each of the com-
mands is as follows:
B B
I I
T T
2 1 0 FUNCTION/OPERATION
0 0 0 NO OPERATION (NOP)
Does not affect the ГО PCA or the bus.
B B
I I
T T
2 1 0 FUNCTION/OPERATION
0 0 1 INTERFACE CLEAR (IFC)
COMMAND
Causes the IFC one-shot to be triggered.
This sets the bus signal line IFC (Inter-
face Clear) “low” for 100 usec which un-
addresses all Talkers and Listeners,
clears the Serial Poll Mode and deacti-
vates all other controllers.
0 1 0 LOCAL COMMAND
Causes the remote enable flip-flop to be
cleared which causes the bus signal line
Remote Enable (REN) to be set high.
3-4
This causes all devices, with the pos-
sible exception of source devices (i.e.,
power supplies), to switch to local con-
trol, and the local lock out state to be
cleared.
0 1 1 REMOTE ENABLE COMMAND
Causes the remote enable flip-flop to be
set which causes the bus signal line Re-
mote Enable (REN) to be set “low”. This
enables all devices on the bus to switch
to remote control when addressed to
Listen to their remote programming
codes.
1 0 0 DEACTIVATE CONTROLLER
FUNCTION COMMAND
Causes the active flip-flop to be cleared.
In this state, the I/O PCA (and thus
the computer) can not perform any of
the functions of a controller.
1 0 1 ACTIVATE CONTROLLER
FUNCTION COMMAND
Causes the active flip-flop to be set.
Only if the I/O PCA is in this state may
it perform the bus functions of a
controller.
1 1 0 STROBE INPUT DATA COMMAND
Causes the contents of the bus data lines
at the time of execution to be strobed
into the input data register irrespective
of the state of the handshake lines or
whether the card is addressed to Listen
or not. The data will go into the upper
or lower half of the input data register
as a function of the state of the input
byte counter. The input byte counter
will be toggled and the input register
loaded FF set if appropriate.
1 1 1 INITIALIZE FLAGS COMMAND
Affects several flags associated with the transfer of data in
and out as follows:
1. Causes the flip-flop for Output Register Loaded and
Output Byte Register Loaded (ORA FF) to be cleared.
This initializes the output handshake logic for subse-
quent output operations and/or terminates an output
cycle in progress.
2. Initialized the output byte counter to byte 0 (upper
half) so that data output using packing always starts
with the upper half word.
3. Causes the DCPC output request flip-flop to be set
so that the first DCPC Output cycle will be requested
when DCPC is enabled.
Causes the “ready for data” flip-flop to be cleared
which will set the bus signal line NRFD (Not Ready
for Data) “low” if the card is addressed to Listen. This
indicates to the Talker device that the card is not able
to accept data yet.
3-13.
CONTROL WORD GROUP 2 CODING
Group 2 of the Control Word consists of two sub-groups
which control two functions each using bits 3 through 6.
Group 2A is used to control the controller functions and
Group 2B to control the talker/listener functions. The two
sub-groups may be used independently or in combination.
Bits 4 and 5 are used to select Groups 2A and 2B respec-
tively and bits 3 and 4 to control the functions of each
sub-group. Group 2 coding and functions are as follows:
IU
©
0
Ww — 0
Pa
FUNCTION/OPERATION
NO OPERATION (NOP)
Does not affect the I/O PCA or the
bus.
GROUP 2A FUNCTIONS
Accesses ATN and EOI FFs.
SET DATA MODE
Causes the ATN (Attention) and
the EOI (End of Identify) Flip-
Flops to be cleared which puts the
bus into the data mode so that the
Talker and Listener(s) may
transmit data.
SIGNAL END OF RECORD
Clears the ATN and sets the EOI
Flip-Flops which sets the bus
signal line EOI (End or Identify)
“low” if addressed to Talk. This
indicates that the next byte sent
as a Talker is the last in the string.
SET COMMAND MODE
Sets the ATN and clears the EOI
Flip-Flops which sets the Bus sig-
nal line ATN “low” and EOI
“high”. This puts the bus into the
command mode which enables the
computer to send commands and
addresses.
OH + СО
ji
CO = — 0
Operation and Programming
PARALLEL POLL COMMAND
Sets the ATN and EOI flip-flops
which sets the bus signal lines
ATN and EOI “low”. This initiates
a parallel poll. Devices so equipped,
respond on a preassigned data
line.
FUNCTION/OPERATION
GROUP 2B FUNCTIONS
Accesses Talk and Listen flip-
flops. All Group 2B codes cause
the data mode to be set simul-
taneously (i.e., the ATN FF is
cleared).
DISABLE LISTEN AND
DISABLE TALK FUNCTIONS
Clears both the Talk and Listen
flip-flops which prevents the VO
PCA from transmitting or re-
ceiving data.
DISABLE LISTEN AND
ENABLE TALK FUNCTIONS
Clears the Listen flip-flop and sets
the Talk flip-flop, thereby en-
abling the PCA to send data to the
bus.
ENABLE LISTEN AND
DISABLE TALK FUNCTIONS
Sets the Listen flip-flop and clears
the Talk flip-flop, thereby en-
abling the PCA to receive data
from the bus.
ENABLE LISTEN AND
ENABLE TALK
Sets both the Talk and Listen
flip-flops, allowing the PCA to
send data to itself. This is gen-
erally useful only for diagnostic
purposes.
COMBINED ACTION OF
GROUPS 2A & 2B
Both the functions indicated by bit
3 and 4 in Groups 2A and 2B will
be performed.
3-5
HP 59310B
3-14. CONTROL WORD GROUP 3 CODING
Group 3 of the control word consists of eight mode control
functions coded with one bit per function using bits 8
through 15. Bit 7 enables or disables the effect of the other
bits in the group. Group 3 coding and functions are as
follows:
Bit 7 GROUP 3 SELECT
When Bit 7 = 1, enables bits 8
through 15 to control their speci-
fied functions.
When Bit 7 = 0, disables bits 8
through 15 from having any effect
in controlling their designated
functions.
Bit 8 ASCII MODE ENABLE
When Bit 7 = 1, enables the ASCII
mode logic (see paragraph 3-122
for details of the operation of the
ASCII Mode.)
When Bit 7 = 0, disables the
ASCII Mode.
Bit 9 GENERATE SERVICE
REQUEST ENABLE
When Bit 9 = 1, enables the bus
I/O PCA to generate a Service Re-
quest (set the Bus signal line SRQ
“low” if:
1(a). The Talk flip-flop is clear and
(b) the Output Byte Register flip-
flop is set.
2(b). The Listen flip-flop is clear
and (b) the NRFD flip-flop is set.
When bit 9 = 0, the PCA is dis-
abled from driving the SRQ line
(it is set to OFF).
Bit 10 DCPC FLAG SELECT
Selects which flag is to be used to
request a DCPC cycle.
When Bit 10 = 0, the DCPC out-
put request flag is selected.
When Bit 10 = 1, the input regis-
ter loaded flag is selected.
3-6
Bit 11 PACKING ENABLE
When Bit 11 = 1, enables the
packing and unpacking logic for
both input and output.
When Bit 11 = 0, disables the
packing logic.
Bits 12-15 FLAG SOURCE SELECT
Selects which flags can be tested
bv the SFS or SFC instructions or
can be used to cause an interrupt.
Bit 12 Enables the end-of-record flag.
Bit 13 Enables the output register ac-
cepted flag.
Bit 14 Enables the input register loaded
flag.
Bit 15 If the active flip-flop is set, enables
the bus clear as Service Request
Flag (SRQ).
If the active flip-flop is clear, en-
ables Serial Poll Mode Flag.
3-15. STATUS WORD
The status word is a 16 bit word (see figure 3-2) which is
input under program control to obtain information about
the operating conditions of the Bus I/O Interface PCA and
the bus.
3-16. STATUS WORD FUNCTION
With the status word, the following can be determined:
1. Which one or more of the six flags have occurred
(EOR, ORA, IRC, IFC, SRQ, SPM).
2. The states of five of the bus signal lines (REN, ATN,
DAV, NRFD and NDAC).
3. Which of the three bus interface functions the I/O
card is currently enabled to perform (Talk, Listen,
Active Controller).
4. The highest priority response to a parallel poll.
3-17. INPUTTING THE STATUS WORD
The status word is transferred to the A or B registers of
the computer using the following sequence of machine
instructions:
STF SC
LIA SC
or
STF SC
LIB SC
SC EQU <select code of BUS I/O card>
NOTE
A OTA/B instruction may not be exe-
cuted between the STF and LIA/B or in-
putting of data will result.
3.
18.
Operation and Programming
STATUS WORD CODING
The coding of each of the bits of the status word is as
follows:
Bits 0-3
Bit
4
PARALLEL POLL PRIORITY
ENCODED IDENTIFICATION
Indicates the highest priority re-
sponse to a parallel poll or the oc-
currence a “bus clear” command.
Highest priority is assigned to IFC
followed by DIOS, etc.
The priority encoding scheme is
shown in Figure 3-2.
ACTIVE FLIP-FLOP STATUS
Indicates the state of the ACTIVE
Flip-Flop.
BUS FUNCTION PARALLEL POLL
FLAGS STATUS BUS SIGNAL LINE STATES STATUS PRIORITY ENCODE ID
AN AN Ne
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C 8 7 6 5 4 3 2 1 3 2 1 @
H H H H H H H H H 0 0 0 0
H H H H H H H H L 0 0 0 1
H H H H H H H L X 0 0 1 0
H H H H H H L X X 0 0 1 1
H H H H H L X X X 0 1 0 0
H H H H L X X X X 0 1 0 1
H H H L X X X X X 0 1 1 0
H H L X X X X X X 0 1 1 1
H L X X X X X X X 1 0 0 0
L X X X X X X X X 1 0 0 1
Figure 3-2. Status Word Format
3-7
HP 59310B
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
3-8
If Bit 4 = 1, the ACTIVE Flip-
Flop is set.
If Bit 4 = 0, the ACTIVE Flip-
Flop is reset.
TALK F STATUS
Indicates the state of the TALK
Flip-Flop.
If Bit 5 = 1, the TALK Flip-Flop
1s set (i.e., the PCA is addressed to
talk).
If Bit 5 = 0, the TALK Flip-Flop
1s reset (i.e., the PCA has not been
addressed to talk).
LISTEN FLIP-FLOP STATUS
Indicates the state of the LISTEN
Flip-Flop.
If Bit 6 = 1, the LISTEN Flip-
Flop is set (i.e., the PCA is ad-
dressed to listen).
If Bit 6 = 0, the LISTEN Flip-
Flop is reset (i.e., the PCA has not
been addressed to listen).
ATN LINE STATUS
Indicates the state of the bus
signal line ATN.
If Bit 7 = 1, ATN is “low”. (bus in
Command Mode).
If Bit 7 = 0, ATN is “high”. (bus in
Data Mode)
REN LINE STATUS
Indicates the state of the bus
signal line REN.
If Bit 8 = 1, REN is “low”. (bus is
Remote Enabled).
If Bit 8 = 9, REN is “high”. (bus is
in Local).
NDAC LINE STATUS
Indicates the state of the bus sig-
nal line NDAC.
NRFD LINE STATUS
Indicates the state of the bus sig-
nal line NFRD.
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
If Bit 10
||
1, NRFD is “high”.
If Bit 10
0, NRFD is “low”.
DAV LINE STATUS
Indicates the state of the bus
signal line DAV.
If Bit 11
1, DAV is “low”.
If Bit 11 = 0, DAV is “high”.
END OF RECORD (EOR)
FLAG STATUS
Indicates the state of the End of
Record Flag.
If Bit 12 = 1, EOR FLG has been
set.
If Bit 12 = 0, EOR FLG has not
been set.
OUTPUT REGISTER ACCEPT
(ORA) FLAG
Indicates the state of the ORA
Flag.
If Bit 13 = 1, the ORA Flag has
been set.
If Bit 13 = 0, the ORA Flag is
clear.
INPUT REGISTER LOADED
(IRL) FLAG
Indicates the state of the IRL Flag.
If Bit 14 = 1, the IRL Flag has
been set.
If Bit 14 = 0, the IRL Flag is
clear.
INTERFACE CLEAR (IFC),
SERVICE REQUEST (SRQ) AND
SERIAL POLL MODE (SPM)
FLAG STATUS
If Active (Bit 4 = 1), Bit 15 = 1 in-
dicates that either the IFC or SRQ
Flags have been set and Bit 15 = 0
indicates that both the IFC and
SRQ Flags are clear.
If Inactive (Bit 4 = 0), Bit 15 = 1
indicates that the SPM Flag has
been set and Bit 15 = 1 indicates
that the SPM Flag is clear.
3-19. DATA OUTPUT
3-20. DATA TRANSFER CAPABILITIES
Data can be transferred from the computer to the bus via
the A or B registers under program control or via memory
under DCPC (Dual Channel Port Controller) control.
Either whole (16 bits) or half words (8 bits) can be output
from the computer. If whole words are to be used, the ГО
PCA's packing feature must be enabled by outputting a
control word.
3-21. OUTPUT DATA TYPES
Data that is outputted can be classified into three types.
They are distinguished by the affect they have on the
devices on the bus and the I/O card. Each is output in the
same manner, only their affect is different. All data type
can be output with or without packing.
The function of the three data types are:
1. To send information (device data) from the computer
to a device(s) on the bus while the computer is acting
as the Talker. Coding and Formatting is a function of -
the devices.
2. To send Addresses and coded Commands to the bus
while the computer is acting as the Controller. Codes
are defined by bus.
3. To send ASCII data, control codes, Addresses and
Commands when the I/O Card is in the ASCII Mode.
Some codes are defined by I/O Card.
3-22. OUTPUT DATA REGISTERS
There are two registers on the PCA which store data
received from the computer prior to being sent over the
bus. These are the Output Word Register (OWR) and the
Output Byte Register (OBR). The OWR is a 16 bit (2 bytes)
register which stores the data received from the A or B
registers or memory. The OBR is an 8 bit (1 byte) register
which stores the data which is being sent via the bus.
The OWR is loaded when an OTA/B instruction is exe-
cuted or simulated by DCPC. Its contents are transferred
to the OBR by the I/O Card in 8 bit bytes. If packing has
been enabled by outputting a control word with Bit 11 = 1,
then two bytes are transferred from the OWR to the OBR
for each OTA/B. If packing is disabled, only one byte is
transferred for each OTA/B.
The contents of the OBR are transferred via the bus in
accordance with the bus handshake lines. Each time a
byte is accepted by the device(s) on the bus, a new byte is
transferred from the OWR to the OBR until all the data in
the OWR (one byte without packing, two with) has been
accepted.
When data is being transferred under program control
(using OTA/B instructions) only one or two bytes can be
Operation and Programming
stored at a time in the two registers. The acceptance of all
bytes is indicated by a flag* that can be tested or used to
generate an interrupt. When data is being transferred by
DCPC, up to three bytes can be stored. A special flag*
indicates when the OWR is empty and requests the next
DCPC output cycle. This allows DCPC and bus cycles to
overlap.
3-23. TO OUTPUT DATA
Data may be transferred from the A or B register of the
computer to a device on the bus under program control by
using the following instruction sequence:
LDA DATA
OTA sc, C
or
LDB DATA
OTB sc, C
NOTE
A STF SC instruction may not precede
the LDA/B and OTA/B instructions or
the data will be interpreted as a control
word by the I/O card.
Data may also be transferred from the computer’s memory
to a device on the bus by using the DCPC option.
3-24. OUTPUT DATA FORMAT
The correspondence between the way the data appears in
the A/B registers or memory and the way it appears when
transferred to the bus is shown in figure 3-3.
With packing disabled, only the lower half of the machine
word is transferred (bits 0-7) to the bus. The upper half
(bits 8-15) is ignored. Bit 0 of the machine word corre-
sponds to DIO1 of the bus, Bit 1 to DIO2, etc.
With packing enabled, both the upper and lower half of
the machine word are transferred to the bus. The upper
half is output as the first bus byte, the lower half second.
Bits 0 and 7 correspond to DIO! of the bus, Bits 1 and 8 to
DIO?, etc.
*See paragraphs 3-31 to 3-38.
3-9
HP 59310B
3-25. DATA INPUT
3-26. DATA TRANSFER CAPABILITIES
Data can be transferred from the bus to the computer's A
or B registers under program control or to the computers’
memory under Dual Channel Port Controller (DCPC) con-
trol. One or two bus bytes may be packed into one comput-
er word by the I/O card, as selected by outputting a control
word.
NOTE
Devices transferring data bytes to the
computer under DCPC control must
complete the 3-wire Handshake in less
than three microseconds; otherwise each
data byte will be duplicated.
3-27. INPUT DATA TYPE
The only type of data that can be input is data received
from a device on the bus while the computer is addressed
to listen and the device to talk. The coding and formatting
of the data is a function of the two devices.
3-28. INPUT WORD REGISTER
The Input Word Register (IWR) is a 16 bit register on the
1O card which can store one or two bytes of data received
from a device on the Bus.
One byte is loaded into the IWR each time a bus hand-
shake cycle occurs. It will be loaded with one byte if
packing is disabled and two bytes if packing is enabled.
When the IWR is full (1 byte without packing, 2 with) a
flag* will be set which can be tested, used to cause an
interrupt, or used to request a DCPC input cycle. The
contents of IWR is transferred to the A or B registers when
a LIA/B or MIA/B instruction is executed or to memory
when a DCPC cycle simulates a LIA/B.
*See paragraphs 3-31 to 3-40.
WITH PACKING DISABLED
DATA AS IT APPEARS
IN A/B REGISTERS 15 g | 7 0 + BIT #
OR MEMORY | |
tr nn
NOT USED
(DON'T CARE)
1
DATA AS IT APPEARS WHEN
OUTPUT TO THE BUS 8 1 <— DIO LINE #
WITH PACKING ENABLED
DATA AS IT APPEARS IN A/B 15 a | 5 р BIT #
REGISTERS OR MEMORY '
FIRST
BYTE 8 1 7 DIO LINE £
DATA AS IT
APPEARS WHEN
OUTPUT TO THE
BUS IN SEQUENCE y
SECOND [ ,
BYTE
Figure 3-3. Output Data Formats
3-10
3-29. TO INPUT DATA
Data may be transferred to the A or B register under
program control by the following sequence of instructions:
LIA sc, C
STA DATA
or
LIB sc, C
STB DATA
Operation and Programming
NOTE
A STF sc instruction may not precede
the LIA/B instruction or the inputting of
a status word will result.
Data may also be transferred to the computer's memory
using the DCPC option. See paragraph 3-101.
3-30. INPUT DATA FORMAT
The correspondence between the way the data appears on
the bus data lines and the way it appears when it is
transferred to the A/B register or memory is shown in
figure 3-4.
With packing disabled only the lower half (bits 0-7) of the
computer word contains a bus byte. The upper half (bits
8-15) will contain all zeroes. The bus signal line DIO1
corresponds to Bit 0, DIO2 to Bit 1, etc.
With packing enabled both the upper and lower halves of
the computer word will contain Bus bytes. The upper half
will contain the first byte received, the lower the second.
The bus signal line DIO1 corresponds to Bit 0 and Bit 8,
DIO2 to Bits 1 and 9, etc.
WITH PACKING DISABLED
DATA AS IT APPEARS
DATA AS IT APPEARS ON THE BUS }
«— DIO LINE +
WHEN INPUT INTO
THE A/B REGISTER
<< BIT #
OR MEMORY
WITH PACKING ENABLED
FIRST
BYTE
DATA AS IT APPEARS
WHEN INPUT TO THE
BUS IN SEQUENCE
SECOND
BYTE
DATA AS IT APPEARS /
“4— DIO LINE #
WHEN INPUT TO THE 15
A/B REGISTERS
«+—— BIT #
OR MEMORY
Figure 3-4. Input Data Formats
3-11
HP 59310B
3-31.
3-32.
FLAGS
FLAG ORGANIZATION
There are eight flags associated with various aspects of
the cards’ and the bus’ operation. Six of the flags (EOR,
ORA, IRL, IFC, SRQ and SPM Flags) can be selectable
combined to set a seventh flag (Main Flag) which can be
tested by the program or used to cause an interrupt. The
six flags may also be tested by inputting a status word.
The eighth flag is used in conjunction with outputting
data under DCPC control.
3-33. MAIN FLAG
The main flag indicates that at least one auxiliary flag
has been set. It is set if any one of the auxiliary flags
selected by the control word occurs. It is cleared by a CLF
instruction if the control flip-flop is clear.
The state of the main flag can be tested by the SFS or SFC
instructions. It may also be used to cause an interrupt if it
is set and the control flip-flop is set and the interrupt
system has been turned on (by a STF 0 instruction).
3-34. END OF RECORD FLAG (EOR)
The End of Record (EOR) Flag indicates that the byte of
data received is the last in the string. The EOR Flag is set
only if the bus I/O PCA is addressed to Listen and the
talker signals “END” (EOI is low) or an ASCII linefeed
character (012;) is received and the ASCII Mode has been
enabled by the control word. The EOR Flag is cleared by a
CLF instruction if the control flip-flop has been cleared.
The EOR Flag may be tested by inputting a status word. If
Bit 12 = 1, the EOR flag is set. The EOR flag may be
enabled to set the main flag by outputting a control word
with Bit 12 = 1.
3-35. OUTPUT REGISTER ACCEPTED
FLAG (ORA)
The Output Register Accepted (ORA) flag indicates when
set that all data in the output word and output byte regis-
ter has been accepted by the device(s) on the bus. The
ORA Flag will be set if:
1. The bus I/O PCA is addressed to Talk and the bus is
in the Data Mode or
2. If the bus I/O PCA is the Active Controller and the
bus is in the command mode and the last byte in the
OWR and OBR has been accepted.
The ORA Flag is cleared by a OTA/B instruction. It can be
initially cleared by outputting a Control Word =
XXXXX7;.
3-12
INPUT REGISTER LOADED FLAG
(IRL)
3-36.
The Input Register Loaded (IRL) flag indicates when set
that data has been loaded into the input register and is
ready to be input into the computer.
The TRL Flag will be set if the I/O card is addressed to
Listen and the bus is in the data mode and a handshake
cycle occurs. If the packing mode is disabled, the IRL Flag
will be set each time a handshake cycle occurs. If the
packing mode is enabled, the IRL flag will only be set
every other time a‘handshake cycle occurs. The IRL flag is
cleared by a LIA/B or MIA/B instruction.
The IRL flag can be tested by inputting the status word
and testing bit 14 or it can be used to set the main flag by
outputting a control word with bit 14 = 1 or it can be
selected to request DCPC cycles by outputting a control
word with bit 10 = 0.
3-37. INTERFACE CLEAR FLAG (FC)
The Interface Clear Flag (IFC) indicates when set that an
interface clear command has occurred on the bus (it may
or may not have been generated by the bus I/O PCA). The
IFC flag is cleared by a CLF instruction if the control
flip-flop is clear.
The IFC Flag can be tested by inputting a Status Word. If
the Status word = X XXX XXX XXX XX1 (0001), then
the IFC Flag is set. It may also be enabled to set the Main
Flag if the I/O card is Active by outputting a Control Word
with Bit 15 = 1.
NOTE
This will also enable the SRQ Flag to set
the Main Flag.
3-38. SERVICE REQUEST FLAG (SRQ)
The Service Request (SRQ) flag indicates that some device
on the bus wants service from the controller. The SRQ flag
1s set when the first device requests service. It will remain
set as long as at least one device still requires service. The
SRQ flag is cleared by executing a serial poll to all devices.
The SRQ flag may be tested only if the PCA is active by
inputting a status word. If Bit 15 = 1 (and Bit 4 = 1) and
Bits 0-3 = 11,, then the SRQ flag is set. If the computer is
the system controller and is not executing an interface
clear command, then Bits 0 — 3 need not be tested. The
SRQ flag may also be enabled to set the main flag if the
PCA is active and a control word with Bit 15 = 1 is output.
(Note: This also enables the IFC Flag to set the main flag.)
3-39. SERIAL POLL MODE FLAG (SPM)
The Serial Poll Mode (SPM) flag indicates when set that
another controller has entered the serial poll mode to
determine the source of a service request. The SPM flag
will be set when the controller sends the serial poll mode
enable command. It will be cleared by the controller send-
ing the serial poll disable command or the interface clear
command.
The SPM flag may be tested only if the PCA is inactive as
a controller and a status word is input. If Bit 15 = 1 (and
Bit 4 = 0)*, the SPM flag is set. The SPM flag can also be
used to set the main flag if the PCA is inactive by output-
ting a control word with Bit 15 = 1.
3-40. DCPC OUTPUT REQUEST FLAG
The DCPC output request flag indicates when set that all
the data in the output word register has been transferred
to the output byte register. It is set at the same time the
last byte is loaded into the OBR. This occurs when the
previous byte has been accepted from the OBR by the
device(s) on the bus. If packing is used, the DCPC output
request flag will be set as the second byte is loaded. If
packing is not enabled, it will be set for each byte trans-
ferred. The DCPC output request flag is cleared by a CLF
instruction (during DCPC operation, it is issued by
DCPC).
The DCPC output request flag can only be used to request
DCPC cycles. It must be enabled to do so by outputting a
control word with Bit 10 = 1. Furthermore, DCPC must be
initialized with various parameters to operate properly.
3-41. MACHINE I/O INSTRUCTIONS
OPERATION
This section describes the operation of each of the comput-
ers I/O instructions with respect to the bus I/O PCA. It
should be noted that some of them operate somewhat
differently than the normal description of each indicates.
3-42. DIFFERENCE IN USE OF I/O
INSTRUCTIONS
Specifically, the STF instruction is used differently to set
a data type flip-flop, the OTA/B, LIA/B, MIA/B do more
(STC’s are not used with them), STC does less (only en-
abling interrupts) and the CLF instruction is qualified by
the control flip-flop.
3-43. STF INSTRUCTION
A STF sc instruction prepares the bus I/O PCA indicated
by sc to receive a control word or input a status word.
Execution of a STF instruction changes the operation of
the next OTA/B, LIA/B, MIA/B instruction on the PCA.
Execution of a OTA/B, LIA/B, MIA/B instruction returns
them to their normal operation.
*Optional
Operation and Programming
3-44. OTA AND OTB INSTRUCTIONS
An OTA sc or OTB sc loads the contents of the A or B
registers into the output word register and clears the ORA
Flag if preceded by a STF sc instruction, outputs a control
word to the PCA indicated by sc.
3-45. LIA, LIB, MIA AND MIB
INSTRUCTIONS
A LIA sc or LIB sc instruction transfers the contents of the
input register or, if preceded by a STF sc instruction, the
status word of the bus I/O PCA indicated by sc to the A or
B registers. The MIA sc and MIB sc instructions operate
the same except they merge (inclusion “or”) the contents
into A and B.
A LIA/B, MIA/B instruction clears the input register
loaded flag, presets the input byte counter to byte 0 (first
input) and sets the not ready for data (NRFD) flip-flop.
3-46. SFS AND SFC INSTRUCTIONS
А SFS sc (SFC sc) instruction causes the next instruction
to be skipped (i.e., P + 2 is executed) if the main flag of the
PCA indicated by sc is set (clear).
3-47. STC AND CLC INSTRUCTIONS
A STC sc instruction enables the bus I/O PCA by setting
the control flip-flop. This causes an interrupt if the inter-
rupt system is turned on, and any one of the six flags
selected by the control word occurs. In addition, a STC sc
prevents any subsequent CLF sc instructions from clear-
ing all but the DCPC Output Request Flag.
A CLC sc instruction clears the control flip-flop and pre-
vents the PCA from causing an interrupt. The cleared
control flip-flop will enable CLF sc to clear main flag, EOR
flag and IFC flag.
3-48. CLF INSTRUCTION
A CLF sc instruction clears the DCPC output request flag
and if the control flip-flop is clear, it will also clear the
main flag, the EOR flag and the IFC flag.
NOTE 1
A stand alone CLF sc instruction does
not operate the same as a ,C appended to
another I/O instruction. The stand alone
CLF sc instruction executes as though it
were STF sc ,C; thus, it prepares the VO
to receive a control word or send a status
word. To effectively execute a stand
alone CLF, use a CLC sc, C instruction.
3-13
HP 59310B
NOTE 2
If the PCA has been placed in the
control/status mode (via an STF instruc-
tion), execution of the CLC,C instruction
will clear the main flag but not the EOR
and IFC flags. A “dummy” LIA instruc-
tion should then be executed to return
the PCA to the data mode.
3-49. ASCII MODE
The ASCII Mode is a special operating mode of the bus I/O
PCA in which six of the functions of the control word may
be controlled by outputting reserved data codes. These are
listed in table 3-1. It also enables an ASCII Linefeed (0125)
character to set the End-of-Record (EOR) flag when re-
ceiving data while addressed to listen.
Table 3-1. ASCII Mode Codes
DATA CODE
FUNCTION OCTAL ASCII TTY
INTERFACE CLEAR 033 ESC ESC
COMMAND
LOCAL COMMAND 002 STX CTRL and B
REMOTE ENABLE 003 ETX CTRL and C
COMMAND
SET COMMAND 016 SO CTRL and N
MODE
SET DATA MODE 017 Si CTRL and O
SIGNAL END OF 012 LF LINE FEED
RECORD
3-14
3-50. ENABLING THE ASCII MODE
The ASCII mode is enabled by outputting a control word
with Bit 8 = 1 when Group 3 is enabled.
3-51. OPERATION WHEN OUTPUTTING
When the ASCII mode is enabled, any one of the functions
shown in table 3-1 may be executed by outputting the
indicated data code. The effect of each on the I/O on the
bus is the same as outputting a control word for the same
function.
When in the ASCII mode, all codes which have control
functions defined (per table 3-1) will not be transmitted
except for linefeed (012;). Linefeed causes End-of-Record
to be signaled and is transmitted to the Listener(s). (The
PCA must be addressed to Talk.) The other ASCII mode
codes cause an internal handshake to occur which oper-
ates the same as if a device had accepted the data. That is
the ORA flag will be set, etc.
An ASCII mode code (except LF) can be output whether or
not the card is addressed to Talk or in the command mode.
All other codes must be output when appropriate, 1.e.,
device data only when addressed to talk, address, etc. only
when in the command mode.
The ASCII mode operates the same with or without pack-
ing enabled and under program or DCPC data transfer or
any combination thereof.
3-52. OPERATION WHEN INPUTTING
If the I/O PCA is addressed to Listen and the ASCII mode
has been enabled, an ASCII Linefeed (012;) will cause the
End-of-Record (EOR) flag to be set. The linefeed character
will also be loaded into the input register. If packing 15
disabled, the receipt of the linefeed character will also set
the Input Register Loaded (IRL) flag. If packing is en-
abled, the IRL flag will only be set if the linefeed was the
second byte received.
THEORY OF OPERATION
SECTION
IV
4-1. INTRODUCTION
This section explains the theory of operation of the Bus
Input/Output Interface. The circuit analysis presented in
this section is limited to a description of a simplified block
diagram and a detailed block diagram.
4-2. GENERAL THEORY
The purpose of the Bus I/O Interface is to interface the HP
computer I/O backplane to the HP Interface Bus (HP-IB).
This requires translation of the computer backplane logic
levels to the TTL logic level used by the HP-IB. The HP
Interface Bus uses 8-bit words which requires the conver-
sion of the computer 16-bit word to two 8-bit words.
The Bus Input/Output PCA (Printed circuit Assembly)
performs four major functions; computer control word pro-
cessing, bus data output, computer data input, and status
information input to the computer. These four functions
are controlled by the control signals applied from the
computer through the I/O backplane to the control logic,
see figure 4-1.
4-3. CONTROL WORD PROCESSING
The computer control word output, which is applied
through the BP data receivers to the control logic, de-
termines the operating mode of the Bus Input/Output
PCA. When the control word processing function is in-
itiated, the control logic, in response to the computer
backplane signals, inhibits the computer data converter
logic and the bus data converter logic. The control logic, in
conjunction with the computer control word output, de-
termines if the PCA is either a listener or talker; the state
of the ASCII logic; and the logic state of the flag outputs to
the computer.
4-4, BUS DATA OUTPUT
The PCA applies data to the bus lines (DIO1 through
DIOS) when the computer data converter logic is enabled
COMPUTER
> FLAGS
BACKPLANE CONTROL |
CONTROL LOGIC <
SIGNALS et,
À
ASCII
LOGIC -
1 Y y Y
COMPUTER BUS
DATA Xx _ DATA DATA -—+ 1081
(10BO) UT | CONVERTER _,| CONVERTER
LOGIC LOGIC
Di01 ATN NRFD
to REN NDAC
DIOS IFC DAV
O O
ЕО!
SRQ
NRFD
NDAC
DAV
Figure 4-1. Simplified Block Diagram
4-1
HP 59310B
by the control logic. The computer data converter logic
stores the 16-bit computer word and, after the handshake
sequence 1s completed, transfers eight bits to the bus data
lines. The handshake cycle is repeated and the second
eight bits are applied to the bus data lines. The data
output of the computer data converter logic is continuously
monitored by the ASCII logic. If the ASCII logic is enabled
by the control logic and the data output is a special ASCII
character, the appropriate ASCII command output is
activated.
4-5. COMPUTER DATA INPUT
The Bus Input/Output card applies data to the computer
when the control logic enables the bus data converter logic.
The bus data converter logic converts two eight bit words
into one 16-bit word before outputting to the computer.
This is accomplished in the following manner. After the
completion of the handshake cycle, the first eight bits are
transferred from the bus data lines and stored in the bus
data converter logic. The handshake cycle is repeated and
the second eight bits are clocked into the appropriate
output register of the bus data converter logic. Two eight
bit words, now one 16-bit word, are clocked into the
computer.
4-6. STATUS INFORMATION INPUT
The fourth major function of the PCA is the outputting of
card status information to the computer. The bus data
converter logic applies status information to the computer
when the control logic inhibits the data output and en-
ables the status word output. The status word output is
used by the computer to monitor card operation to deter-
mine which flag caused an interrupt; to determine the
state of the input/output handshake cycle; and to deter-
mine the state of the ASCII commands.
4-7. DETAILED THEORY
4-8. DATA INPUT/OUTPUT CONTROL
The four major functions of the PCA are controlled by the
data input/output control, see figure 7-2. The data input/
output control generates four outputs from the ТОТ, 100,
and STF inputs. These outputs are the IOI SC status,
which puts the PCA in the computer status information
function; the IOI SC data, which puts the PCA in the
computer data input function; the IOO SC control, which
puts the PCA in the control word processing function; and
the IOO SC data, which puts the PCA in the bus data
output function.
4-9, CONTROL WORD PROCESSING
4-10. WORD REGISTER AND DECODER. The
computer control word determines the PCA operating
mode and is processed by the word register and decoder.
When the PCA is in the control word processing function,
the transfer of data from the card to either the bus (lines
4-2
DIO1 through DIOS) or the computer is inhibited by the
data input/output control. The control word is a 16-bit
word which is divided into three functional groups; groups
one, two, and three. Group one consists of bits seven
through fifteen. Group two consists of bits three through
six and group three consists of bits zero through two.
These three groups can be used independently or in com-
bination with each other.
The group one portion of the control word is loaded into
the word register and decoder whenever bit seven of the
control word is set high. These eight bits control the selec-
tion of which flags will cause an interrupt to be tested by a
skip flag set or skip flag clear instruction. Group one also
sets the ASCII mode in either the address or data mode
and sets the DCPC in an input or output operation. In
addition, these bits determine if the service request (SRQ)
1s generated on the bus with an input/output operation
and if packing is enabled or disabled.
The group two portion of the control word consists of bits
three through six and is subdivided into two groups:
groups 2a and 2b. Group 2a controls the ATN and EOI
flip-flops and is selected whenever bit five of the control
word is set high. Group 2b controls the talk and listen
flip-flops and is selected whenever bit six of the control
word is set high. Groups 2a and 2b can be used indepen-
dently or in conjunction with each other.
The third group of the control word consists of bits zero
through two and is decoded by the word register and de-
coder into six control lines. These six control lines, in
addition to controlling the REN and active flip-flops and
the IFC single-shot, also sets the output data control and
the input data control to their initial state (byte one).
4-11. EOI. The EOI flip-flop, set by the control word,
determines the state of the EOI signal output line. The
EOI flip-flop is reset by either the control word, an IFC
signal from the bus, computer turn on, or when the com-
puter preset push button is engaged.
4-12. REN. The REN flip-flop output is enabled when
switch SW2 (position 6) is set to REN on. When enabled,
the REN flip-flop sets the REN output line low when
triggered by either the control word or the ASCII mode
logic.
4-13. ACTIVE. The output state of the active flip-flop
is controlled by the control word and the IFC single-shot.
When the active flip-flop is set, the PCA becomes the bus
controller. The bus controller is a device that can send out
addresses and universal commands to instruments con-
nected to the HP-IB. The active flip-flop is reset by the
control word or when some other device on the bus sets
IFC low.
4-14. ATN. When the active flip-flop is set, the ATN
driver is enabled. This allows the ATN flip-flop to control
the ATN output line. The ATN flip-flop is set by either the
control word or the ASCII mode logic. It is reset by the
following: the control word, ASCII mode logic, triggering
of the IFC single-shot, computer turn on, and when the
computer preset button is pushed if the PCA is the system
controller.
4-15. IFC. The IFC single-shot output is enabled
when switch SW2 (position 7) is set to IFC on. In this
position, the IFC single-shot produces a 100 microsecond
pulse output when triggered by one of the following: an
octal one in the lower octal digit of the control word, the
ASCII mode logic, computer turn-on, or when the com-
puter preset push button is pushed.
4-16. IFC BUFFER AND FILTER. The IFC buffer
and filter, in addition to buffering the IFC signal line from
the bus, also filters the IFC line. Filtering is required to
eliminate fast transient noise spikes on the bus IFC line to
prevent falsely clearing of various flip-flops.
4-17. IFC OFF. The IFC off flip-flop, set whenever the
IFC bus signal line goes low, is used to generate an inter-
rupt output to the computer. It can be tested by either a
skip flag set instruction or by loading the status word into
the computer. A clear flag instruction resets the IFC flip-
flop.
4-18. BUS DATA OUTPUT.
The transfer of data from the computer to the PCA to the
bus data lines uses a series of circuits on the PCA. These
circuits are the BP data receivers, the data input/output
control, the output word register, the output data control,
the output handshake logic, the output byte register, and
the DIO drivers.
4-19. BP DATA RECEIVERS. The BP data receivers
provide signal buffering from the computer IOBO data bus
to the PCA internal bus. In addition, the BP data receivers
translate the computer backplane logic level to the TTL
logic level required by the Bus Input/Output card. The
output of the BP data receivers is applied to the word
register and decoder and to the output word register.
4-20. OUTPUT WORD REGISTER. The output
word register is a 16-bit register which is used to store the
input data because the computer applies data to the IOBO
lines for only 400 nanoseconds. Data is strobed into the
output word register by the IOO SC data signal output of
the data input/output control. The transfer of information
from the output word register to the output byte register is
controlled by the output data control and the output hand-
shake logic.
4-21. OUTPUT BYTE REGISTER. The output byte
register 1s an eight bit register used to transfer the data
from the output word register to the DIO drivers in eight
bit segments. This operation is controlled by two inputs
applied from the output data control. One input is the word
shift (ws), determining which eight bits of the output word
register are applied to the DIO drivers. The remaining
input is the clock and is used to transfer data into the
output byte register.
Theory of Operation
4-22. OUTPUT DATA CONTROL. The output data
control consists of a series of flip-flops. These flip-flops are
used to control the output byte register, to generate a
DCPC flag output, to enable the output handshake logic,
and to inform the computer of the output byte register
operating state. The 100 SC data signal input sets the
output word register loaded flag (ORA FLG) low and,
after a 100 nanosecond delay, clocks data into the output
byte register. If packing is enabled, which is the ability to
convert the computer 16-bit word into two eight bit words,
and the output data control is in byte one, bits zero
through seven are transferred to the output byte register.
After the handshake cycle, the DCPC flag output is set
high and the output data control is set to byte two. The
DCPC flag output requests the next DCPC cycle of the
computer. The second eight bits of the computer word, bits
eight through fifteen, are clocked into the output byte
register and applied through the DIO drivers to the bus
output lines. After the handshake cycle, the ORA FLG
output is set high, indicating to the computer that the
device on the bus has accepted both eight bit words. The
output data control is reset to byte one.
4-23. OUTPUT HANDSHAKE LOGIC. The output
handshake logic consists of a combination of logic func-
tions that are used to control the inputting of data to the
required handshake sequence. There is a 500 nanosecond
delay incorporated in the output handshake logic. After an
initial 200 nanosecond delay, an enable is applied to the
ASCII mode logic. An additional 300 nanoseconds later, if
the NRFD on the bus is high, the DAV bus output line is
set low. When the device on the bus has accepted the data,
the DAC bus input is set high which resets the DAV
output to high.
4-24, ASCII MODE LOGIC. The data output of the
output byte register is also applied to the ASCII mode logic.
If the ASCII mode logic is enabled, bit-8 of the control
word set high, and the data is a reserved ASCII character,
a low output is applied to the output handshake logic. This
ends the handshake cycle, giving the appearance that the
device on the bus has accepted the data. In addition, the
reserved ASCII characters are decoded by the ASCII mode
logic, determining the state of the REN flip-flop, the ATN
flip-flop, or the triggering of the IFC single-shot.
4-25. DIO DRIVERS. The output of the output byte
register 1s applied to the DIO drivers. The DIO drivers
provide the drive for the bus data lines. These are tristate
drivers and they are enabled only when the PCA is either
addressed to talk or is an active controller with ATN set
low.
4-26. COMPUTER DATA INPUT
The third major function of the PCA is the transferring of
data from the input data and status word multiplexer to
the computer. This is controlled by the input handshake
logic, the input data control, and the input data/word re-
gister. The input data is applied through the DIO receivers
to the input data/word register. The strobing of data into
the input data/word register is controlled by the hand-
4-3
HP 59310B
shake lines (DAV, NDAC, and NRFD) and the listen flip-
flop. The listen flip-flop is part of the bus communicator
logic. If the listen flip-flop is set and DAV goes low, the
card can accept data into the input data/word register.
This is conrolled by the input handshake logic.
4-27. INPUT HANDSHAKE LOGIC. The input
handshake logic consists of a combination of logic func-
tions that are used to control the strobing of data into the
input data/word register. There is a 200 nanosecond delay
incorporated into the input handshake logic. After an ini-
tial 100 nanosecond delay, the DAV input from the bus is
applied to the input data control and the NRFD bus output
line is set high. After an additional 100 nanosecond delay,
the NDAC output line is set high.
4-28. INPUT DATA CONTROL. The input data con-
trol, consisting of a series of flip-flops and other logic
elements, provides a clock output to both the ZOR flag
logic and the upper and lower half of the input data/word
register. Also, an input register loaded flag (IRL FLG)
output is applied to the computer.
If packing is enabled, the IOI SC data output signal from
the data input/output control sets the input data control to
byte one. The DAV input, applied from the input hand-
shake logic, results in a clock applied to the lower half of
the input data/word register, transferring the contents of
the DIO receivers into the input data/word register. The
clock is also applied to the FOR flag logic and the input
data control is set to byte two. The next DAV input clocks
the contents of the DIO receivers into the upper half of the
input data/word register. In addition, a IRL FLG is applied
to the computer, indicating that the card has accepted
both words of data and is ready to output.
If packing is not enabled, data is clocked into only the
upper half of the input data/word register. The input data
control 1s continuously set to byte two.
4-29, EOR FLAG LOGIC. The EOR flag logic will
respond to the clock output from the input data control if
enabled by either the ASCII mode LF detector or the EOI
flip-flop. The EOR flag can be used to generate an inter-
rupt and be tested by either a skip flag set instruction or
by the control word.
4-30. ASCII MODE LF DETECTOR. If the ASCII
mode LF detector is enabled by the bus communicator
logic, it monitors the data output of the DIO drivers. If an
octal 12 is applied to the bus data lines (DIO1 through
DIO7), the ASCII mode LF detector will enable the EOR
flag logic. The EOR flag logic, when clocked, will indicate
end of record in the ASCII mode.
4-31. BUS COMMUNICATOR LOGIC. The bus
communicator logic, in conjunction with the computer
control word or with a bus controller, enables the PCA as
either a talker or listener. The listen flip-flop, contained in
the bus communicator logic, is set or reset by either the
computer control word or if a controller applies the ap-
propriate Bus Input/Output listen or un-listen address to
4-4
the data lines. Similarly, the talk flip-flop is set or reset by
either the computer control word or if a controller applies
the correct Bus Input/Output talk address to the data
lines.
An additional function in the bus communicator logic is
the status poll flip-flop. The status poll flip-flop is set when
a controller applies a status poll command to the bus data
lines. It is used to cause an interrupt and is tested by the
skip flag set instruction. The status poll flip-flop enables
the computer to output a status byte to the controller on
request. The status poll flip-flop is reset by either the
status poll disable command, generated by the controller,
or when IFC is set low.
4-32. ADDRESS COMPARATOR AND ADDRESS
SWITCH. Switch SW2 consists of eight, two position
switches. Five of these switches, labeled bus address on
the PCA, correspond to the address switch. The position of
these switches determine the address of the card. The
output of the address switch is applied to the address
comparator. The address comparator, by comparing the
output of the address switch to the data applied to the bus
input data lines, determines if the PCA is addressed.
When the card is addressed, the address comparator
applies an output to the bus communicator logic.
4-33. SRQ REQUEST LOGIC. The SRQ request
logic 1s used to generate an SRQ output, if enabled by the
computer, whenever data is to be outputted or received.
When enabled, an SRQ output is generated if the card is
not addressed to talk and the output byte register loaded
flip-flop (part of the output data control) is set. Also, an
SRQ output is generated if the card is not addressed to
listen and the ready for data flip-flop (part of the input
handshake logic) is set.
4-34. PARALLEL POLL LD. If a SRQ is pending,
the controller may execute a parallel service request I.D.
sequence by setting both ATN and EOI low. In response,
the Parallel Poll I.D. will set the DIO line assigned to the
card, line assignment is determined by the PP I.D. code
switch SW11, low. This identifies the PCA as one of the
sources of a SRQ.
4-35. PP PRIORITY AND ENCODER. The PP
priority and encoder is used to execute a Parallel Poll I.D.
cycle by encoding the data lines (DIO1 through DI08) to
the octal equivalent of the eight line code. Line DI08 has
the highest priority of the data lines, octal code eight is
generated if line DIOS is low. If DIOS is high, line DIO7 has
the highest priority. This sequence is repeated through
line DIO1. The IFC flip-flop generates the highest priority
code, octal 11. Octal code 11 can be used to distinguish a
service request from an IFC interrupt.
4-36. FLAG MULTIPLEXER and FLAGS. The flag
multiplexer selects one of seven flag inputs that can be
used as a source of interrupt. Any combination of these
flags, which are enabled, will set the flags. The output of
the flags is used in conjunction with the SFS/SFC logic,
enabling testing by these machine instructions. In addi-
tion, the flags output is used with the interrupt logic to
cause an interrupt if the computer uses the interrupt
system.
4-37. INTERRUPT LOGIC. The interrupt logic gen-
erates an interrupt output to the computer if the interrupt
system in the computer is enabled and a high priority
interrupt from another I/O card is not pending. If the flags
is set, any other interrupt is locked out until the interrupt
from the PCA is processed.
4-38. DCPC FLAG MULTIPLEXER. The DCPC
flag multiplexer selects which flag, the IRL flag or the
Theory of Operation
DMA output request flag, is used to generate a DCPC
service request. The control word determines flag
selection.
4-39. STATUS INFORMATION INPUT
The fourth major function of the Bus Input/Output card is
the transfer of the status word from the input data and
status word multiplexer to the computer. The data input/
output control 101 SC status output inhibits bus data
transfer and enables the outputting of the status word.
The status word is used by the computer to monitor card
operation to determine which flag caused an interrupt; to
determine the state of the handshake cycle; and to deter-
mine the state of the ASCII commands.
4-5/4-6
MAINTENANCE
SECTION
V
5-1. INTRODUCTION
This section contains troubleshooting information.
5-3. TROUBLESHOOTING
Refer to the 59310B Bus Input/Output Card Diagnostic
manual, part number 59310-90061; for diagnostic pro-
gram use part number 59310-16001. The program is de-
signed to rapidly confirm proper operation of the Bus I/O
PCA and to assist in troubleshooting defective cards.
9-1/5-2
REPLACEABLE PARTS
SECTION
VI
6-1. INTRODUCTION
This section contains information for ordering replaceable
parts. Table 6-1 gives the meanings of the abbreviations
and reference designations used in the table of replaceable
parts. Table 6-2 is the list of replaceable parts and is
organized as follows:
1. Components in alpha-numerical order by reference
designation.
2. Miscellaneous parts.
The information given for each part consists of:
1. the Hewlett-Packard part number,
2. total quantity (Qty),
ad
description of the part,
a
typical manufacturer of the part in a 5-digit code, and
5. the manufacturers number for the part.
Total quantity for each part is given only once—at the
first appearance of the part number.
Table 6-3 contains the names and addresses that corre-
spond to the manufacturers” code numbers.
6-2. ORDERING INFORMATION
To order a part listed in the Replaceable Parts table,
provide the nearest Hewlett-Packard office with the fol-
lowing information:
1. The Hewlett-Packard part number from the Replace-
able Parts table.
2. The quantity required.
To order a part not listed in the Replaceable Parts table,
provide the nearest Hewlett-Packard office with the fol-
lowing information:
1. Model number.
Table 6-1. Reference Designations and Abbreviations
REFERENCE DESIGNATIONS
A = assembly E = miscellaneous elec- P = electrical connector U = integrated circuit:
AT = attenuator; isolator; trical part {movable portion); microcircuit
termination F = fuse plug V = electron tube
R = fan: motor FI, = filter Q = transistor; SCR; VR = voltage regulator;
BT = battery H = hardware triode thyristor hreakdown dinde
С = capacitor HY = circulator R = resistor W = cable; transmission
CP = coupler J = electrical connector RT = thermistor path: wire
CR = diode; diode (stationary portion), 5 = switch X = socket
thyristor; varactor jack T = transformer Y = crystal unit -piezo-
DC = directional coupler K = relay TR = terminal hoard electric
DI, = delay line |. = coil; inductor TC = thermocouple 7. = tuned cavity: tuned
DS = annunciator; signal- M = meter TP = test point circuit
ing device (audible MP = miscellaneous
or visual), lamp: mechanical part
LED
ABBREVIATIONS
A = ampere avg = average CHAN = channel de = direct current
ac = alternating current AWG = American wire cm = centimeter deg = degree (temperature
ACCESS = accessory gauge CMO = cabinet mount only interval or
ADJ = adjustment ВАТ. = balance COAX = coaxial difference)
AD = analog-to-digital BCD = binary coded COFF = coefficient © = degree (plane angle)
AF = audio frequency decimal COM = common °C = degree Celsius
AFC = automatic fre- BD = board COMP = composition (centigrade)
quency control BE CU = beryllium copper COMPI. = complete °F = degree Fahrenheit
AGC = automatic gain BFO = beat frequency CONN = connector °К = degree Kelvin
control oscillator CP = cadmium plate DEPC = deposited carbon
AI. = aluminum RH = hinder head CRT = cathode-ray tube DET = detector
ALC = automatic level RKDN = breakdown CTI. = complementary diam = diameter
control BP = bandpass transistor logic DIA = diameter (used in
AM = amplitude modula- BPF = bandpass filter CW - continuous wave parts list)
tion BRS = brass cw = clockwise DIFF
AMPI. = amplifier BWO = hackward-wave em = centimeter AMPI. = differential amplifier
APC = automatic phase oscillator DA = digital-to-analog div = division
control CAL = calibrate dB = decibel DPDT = double-pale, double-
ASSY = assembly Cow = counterclockwise dBm = decibel referred to throw
AUX = auxiliary CER = ceramic I mW DR - drive
6-1
HP 59310B
Table 6-1. Reference Designations and Abbreviations (Continued)
DSR
DT!
DVM
КОТ.
EMP
EDP
ELECT
ENCAP
EXT
FET
FF
FH
FIT. H
FM
HPF
HV
Hz
Ke
ID
IF
IMPG
In
INCD
МСТ.
INP
INS
INT
kyr
kHz
ко
kV
Ih
Le
tog
IPF
IV
m
mA
MAX
MC
MEG
MET FIM
MET OX
MH
= double sideband
= diode transistor logic
= digital voltmeter
= emitter coupled logic
= electromotive force
= electronic data
processing
= electrolytic
= encapsulated
= external
= farad
= field-effect tran-
sistor
= flip-flop
= flat head
= fillister head
= frequency modula-
tion
= front panel
= frequency
= fixed
- gram
germanium
gigahertz
- glass
grounded)
henry
Four
= Бе!етойупе
= hexagonal
= head
= hardware
= high frequency
- Mercury
= high
= Hewlett-Packard
= high pass filter
= hour fused in parts
list)
= high voltage
= Hertz
- integrated circuit
= inside diameter
= intermediate fre-
quency
= impregnated
= inch
= incandescent
= includeis)
- input
= insulation
- internal
= kilogram
= kilohertz
= kilohm
= kilovolt
= pound
= inductance-
capacitance
= light-emitting diode
= low frequency
= long
= left hand
limit
= linear taper (used in
parts list)
= linear
= lock washer
= low: local oscillator
= logarithmic taper
tused in parte list
= logarthmiio
= low pass filter
= low voltage
= meter (distance)
= milliampere
= maximum
= megohm
= meg (10) used in
parts list)
= metal film
metal oxide
= medium frequency:
microfarad tused in
parts list)
MFR
mg
МН?
mH
mho
MIN
min
MINAT
mm
MOD
MOM
MOS
ms
MTG
MTR
mV
т\ас
mVdc
mV pk
mV pp
mVrms
mW
MUX
MY
HA
MH
Нло
HS
pVie
нУдс
uVpk
нУр-р
uVrms
NC
NRFR
NSR
ns
nw
ORD
on
OH
OP AMPI.
OPT
Osc
OX
07
Q
P
PAM
PC
PCM
PDM
pr
PH RR
PHI,
PIN
ABBREVIATIONS
manufarturer
milligram
megahertz
millihenry
то
minimum
minute time)
minute plane angle)
miniature
1
1
I
1H
H
и
H
Ш
n
1
millimeter
modulator
momentary
metal-oxide semi-
conductor
millisecond
mounting
meter (indicating
device)
millivolt
millivalt, ac
millivolt, de
millivolt, peak
millivelt, peak-to-
peak
mitlivolt. rms
milliwatt
multiplex
mylar
microampere
microfarad
microhenry
micromho
microsecond
microvolt
microvolt,
microvolt,
microvolt,
microvolt,
ac
de
peak
peak-to-
peak
microvolt, rms
microwatt
nanoampere
no connection
normally closed
neon
negative
nanofarad
nickel plate
normallv open
nominal
normal
negative-pasitive-
negative
negative-positive
zero (zero tempera-
ture coefficient)
not recommended
for field replacement
not separately
replaceable
nanosecond
nanowatt
order by description
outside diameter
oval head
operational amplifier
option
oscillator
oxide
ounce
ohm
peak (used in parts
list)
pulse-amplitude
modulation
printed circuit
pulse-code modula-
tion; pulse-count
modulation
pulse-duration
modulation
picofarad
phosphor bronze
Phillips
positive-Instrinsic-
negative
PO
POLY
PORC
POS
POSN
POT
PP
PP
PPM
PREAMPL,
PRE
PRR
ps
PT
PTM
PWM
PWV
RE
RECT
REF
REG
REPLI.
RF
RFI
RH
RIC
RMO
rms
RND
ROM
R&P
RWV
S-B
SCR
sE
SECT
SEMICON
SHF
Si
SIT,
ST.
SNR
SPDT
SPG
SR
SPST
SSB
SST
STI,
SQ
SWR
SYNC
T
TA
TC
TH
TERM
1
H
peak inverse voltage
peak
phase lock
phase lock oscillator
phase modulation
positive-negative-
positive
part af
polystyrene
porcelain
positive; position(s)
{used in parts list)
position
potentiometer
peak-to-peak
peak-to-peak (used
in parts list)
pulse-position
modulatinn
preamplifier
pulse-repetition
frequency
pulse repetition rate
picosecond
paint
pulse-time modula-
tion
pulse-width
modulation
peak working voltage
resistance
capacitance
rectifier
reference
regulated
replaceable
radio frequency
radio frequency
interference
round head: right
hand
resistance-
inductance-
capacitance
rack mount only
root-mean-square
round
read-only memory
rack and panel
reverse working
voltage
scattering parameter
second (time)
second (plane angle)
slow-hlow (fuse)
(used in parts list)
silicon controlled
rectifier; screw
selenium
sections
semiconductor
superhigh fre-
quency
silicon
silver
slide
signal-to-noise ratio
single-pole, double-
throw.
spring
split ring
single-pole, single-
throw
single sideband
stainless steel
steel
square
standing-wave ratio
synchronize
timed (slow-hlow
fuse}
tantalum
temperature
compensating
time delay
terminal
TFT
TGI.
THD
THRU
TI
TOI,
TRIM
TSTR
TTI.
TV
TVI
TWT
U
UF
UHF
UNREG
V
VA
Vac
VAR
УСО
!
H
|
thin-film transistor
toggle
thread
through
titanium
tolerance
trimmer
transistor
transistor-transistor
logic
television
television interference
traveling wave tube
micro (10-5) {used
in parts list)
microfarad (used in
parts list)
ultrahigh frequency
unregulated
volt
voltampere
volts. ac
variable
voltage-controlled
oscillator
volts, de
volts, de. working
{used in parts list)
volts, filtered
variable-frequency
ascillator
very-high frequency
volts, peak
volts, peak-to-peak
volts, rms
voltage standing
wave ratin
voltage-tuned
oscillator
vacuum-tuhe
voltmeter
volts, switched
watt
with
working inverse
voltage
wirewound
without
vttrium-iron-garnet
charactenstic
impedance
NOTE
All abbreviations in the parts
list will be in upper case.
MULTIPLIERS
Abbreviation
== y IEYIS)LAF EOS
Prefix Multiple
tera 10'?
giga 109
mega 108
kilo 103
deka 10
deci 107
centi 10-2
milh 10-4
micro 10-75
nano tû-*
pico 10-12
femta 10-15
atto 1071»
6-2
2. Complete serial number, including prefix
3. Description and function of the part
4. Quantity required
6-3. HP PART NUMBER
ORGANIZATION
Replaceable Parts
6-4. COMPONENT PARTS AND
MATERIALS
Generally, the prefix of HP part numbers identifies the
type of device. Eight digit part numbers are used, where
the four digit prefix identifies the type of component, part,
or material and the four digit suffix indicates the specific
type. Following is a list of some of the more commonly
used prefixes for component parts. The list includes HP
manufactured parts and purchased parts.
For example, 1854-0037, 1854-0221, and 1851-0192 are all
Following is a general description of the HP part number NPN transistors. The first two are silicon and the last is
system.
germanium.
Commonly-Used Prefixes for Component Parts
Prefix
0121--
0122--
0140--
0150--
0160--
0180--
0330--
0340--
0370--
0380--
0410--
0470--
0490--
0510--
0674- thru 0778-
0811- thru 0831-
1200-
1205-
1250-
1251-
1410-
1420-
1820-
1826-
1850-
1851—
1853-
1854-
1855-
1900- thru 1912-
1920- thru 1952-
1990-
3100- thru 3106-
8120-
9100-
Component/Part/Material
Capacitors, Variable (mechanical)
Capacitors, Voltage Variable (semiconductor)
Capacitors, Fixed
Capacitors, Fixed Non-Electrolytic
Capacitors, Fixed
Capacitors, Fixed Electrolytic
Insulating Materials
Insulators, Formed
Knobs, Control
Spacers and Standoffs
Crystals
Adhesives
Relays
Fasteners
Resistors, Fixed (non wire wound)
Resistors (wire wound)
Sockets for components
Heat Sinks
Connectors (RF and related parts)
Connectors (non RF and replated parts)
Bearings and Bushings
Batteries
Monolithic Digital Integrated Circuits
Monolithic Linear Integrated Circuits
Transistors, Germanium PNP
Transistors, Germanium NPN
Transistors, Silicon PNP
Transistors, Silicon NPN
Field-Effect-Transistors
Diodes
Vacuum Tubes
Semiconductor Photosensitive and Light-Emitting Diodes
Switches
Cables
Transformers, Coils, Chokes, Inductors, and Filters
HP 59310B
Table 6-2. Replaceable Parts
REFERENCE HP MFR
DESIGNATION | PART NO. QTY DESCRIPTION CODE MFR PART NO.
59310-60101 1 BOARD ASSEMBLY, BUS I/O 28480 59310-60101
C1 0180-0374 2 CAPACITOR-FXD 10UF+—-10% 20VDC TA 56289 | 150D106X9020B2
C2 0180-0374 CAPACITOR-FXD 10UF+ —10% 20VDC TA 56289 150D106X9020B2
C3 0160-0153 2 CAPACITOR-FXD 1000PF +—10% 200WVDC POLYE | 56289 292P10292
C4 0160-0155 1 CAPACITOR-FXD 3300PF +-10% 200WVDC POLYE | 56289 292P33292
C5 0160-2640 1 CAPACITOR-FXD .O1UF +—20% 50WVDC СЕВ 28480 0160-2640
Сб 0160-0157 1 CAPACITOR-FXD 4700F +—10% 200WVDC POLYE 56289 29P47292
C7 0160-0153 CAPACITOR-FXD 1000PF +-10% 200WVDC POLYE | 56289 292P10292
C8 0160-0154 CAPACITOR-FXD 2200PF +—10% 200WVDC POLYE | 56289 292P22292
C9 0160-2197 1 CAPACITOR-FXD 10PF + —5% 300WVDC MICA 28480 0160-2197
C10 0160-0154 CAPACITOR-FXD 2200PF +—10% 200WVDC POLYE | 56289 292P2292
C11 0160-0945 1 CAPACITOR-FXD 910PF +—5% 100WVDC MICA 28480 0160-0945
C12 0160-2055 8 CAPACITOR-FXD .01UF +80—20% 100WVDC CER 28480 0160-2055
C13 0160-2055 CAPACITOR-FXD .01UF +80-20% 100WVDC CER 28480 0160-2055
C14 0160-2055 CAPACITOR-FXD .01UF +80—20% 100WVDC CER 28480 0160-2055
C15 0160-2055 CAPACITOR-FXD .01UF +80-20% 100WVDC CER 28480 0160-2055
C16 0160-2055 CAPACITOR-FXD .01UF +80-20% 100WVDC CER 28480 0160-2055
C17 0160-2055 CAPACITOR-FXD .01UF +80-20% 100WVDC CER 28480 0160-2055
C18 0160-2055 CAPACITOR-FXD .01UF +80-20% 100WVDC CER 28480 0160-2055
C19 0160-2055 CAPACITOR-FXD .01UF +80—-20% 100WVDC CER 28480 0160-2055
CR1 1901-0040 6 DIODE-SWITCHING 30V 50MA 2NS DO-35 28480 1901-0040
CR2 1901-0040 DIODE-SWITCHING 30V 50MA 2NS DO-35 28480 1901-0040
CR3 1901-0040 DIODE-SWITCHING 30V 50MA 2NS DO-35 28480 1901-0040
CR4 1901-0040 DIODE-SWITCHING 30V 50MA 2NS DO-35 28480 1901-0040
CR6 1901-0040 DIODE-SWITCHING 30V 50MA 2NS DO-35 28480 1901-0040
R1 0757-0403 7 RESISTOR 121 1% .125W F TC=0+-100 24546 C4-1/8-TO-121R-F
R2 0757-0403 RESISTOR 121 1% .125W F TC=+—100 24546 C4-1/8-TO-121R-F
R3 0698-3160 1 RESISTOR 31.6K 1% .125W F TC=0+ -100 24546 C4-1/8-TO-3161-F
R4 0757-0403 1 RESISTOR 121 1% .125W F TC=0+-100 24546 C4-1/8-TO-121R-F
R5 0757-0403 RESISTOR 121 1% .125W F TC%0+-100 24546 C4-1/8-TO-121R-F
R6 0757-0403 RESISTOR 121 1% .125W F TC=0+-100 24546 | C4-1/8-TO-121R-F
R7 0757-0438 1 RESISTOR 5.11K 1% .125W F TC=0+-100 24546 C4-1/8-TO-5111-F
R9 0757-0403 RESISTOR 121 1% .125W F TC=0+-100 24546 C4-1/8-TO-121R-F
R10 0757-0403 RESISTOR 121 1% .125W F TC=0+-100 24546 C4-1/8-TO-121R-F
R12 0683-1025 2 RESISTOR 1K 5% .25W FC TC=-400/+600 01121 CB1025
R13 0683-1025 RESISTOR 1K 5% .25W FC TC= —400/+600 01121 CB1025
R14 1810-0121 5 NETWORK-RES 9-PIN-SIP .15-PIN-SPCG 28480 1810-0121
R15 1810-0121 NETWORK-RES 9-PIN-SIP .15-PIN-SPCG 28480 1810-0121
R16 1810-0121 NETWORK-RES 9-PIN-SIP .15-PIN-SPCG 28480 1810-0121
R17 1810-0121 NETWORK-RES 9-PIN-SIP .15-PIN-SPCG 28480 1810-0121
R18 1810-0041 2 NETWORK-RES 9-PIN-SIP .15-PIN-SPCG 28480 1810-0041
R19 1810-0121 NETWORK-RES 9-PIN-SIP .15-PIN-SPCG 28480 1810-0121
R20 1810-0136 2 NETWORK-RES 10-PIN-SIP .1-PIN-SPCG 28480 1810-0136
R21 1810-0136 NETWORK-RES 10-PIN-SIP .1-PIN-SPCG 28480 1810-0136
R22 1810-0041 NETWORK-RES 9-PIN-SIP .15-PIN-SPCG 28480 1810-0041
51 3101-1983 2 SWITCH-TGL DIP ROCKER ASSEMBLY 8-1A NS 81073 76YY2078
S2 3101-1983 SWITCH-TGL DIP ROCKER ASSEMBLY 8-1A NS 81073 76YY2078
6-4
See introduction to this section for ordering information
Replaceable Parts
Table 6-2. Replaceable Parts (Continued)
REFERENCE HP MFR
DESIGNATION | PART NO. QTY DESCRIPTION CODE MFR PART NO.
U13 1820-0054 8 IC SN74 00 N GATE 01295 SN7400N
U14 1820-1112 7 IC SN74LS 74 N FLIP-FLOP 01295 SN74LS74N
U15 1820-1112 IC SN74LS 74 N FLIP-FLOP 01295 SN74LS74N
U16 1820-0054 IC SN74 00 N GATE 01295 SN7400N
U17 1820-0054 IC SN74 00 N GATE 01295 SN7400N
U18 1820-1080 11 | IC N8T13B DRIVER 18324 N8T138
U21 1820-1112 IC SN74LS 74 N FLIP-FLOP 01295 SN74LS74N
U22 1820-1112 IC SN74LS 74 N FLIP-FLOP 01295 SN74LS74N
U23 1820-1056 3 IC SN74 132 N SCHMITT 01295 SN74132N
U24 1820-1112 IC SN74LS 74 N FLIP-FLOP 01295 SN74LS74N
U25 1820-1112 IC SN74LS 74 N FLIP-FLOP 01295 SN74LS74N
U26 1820-0328 3 IC SN74 02 N GATE 01295 SN7402N
U27 1820-0068 7 IC SN74 10 N GATE 01295 SN7410N
U28 1820-1080 IC N8T13B DRIVER 18324 N8T13B
U31 1820-0511 6 IC SN74 08 N GATE 01295 SN7408N
U32 1820-0328 IC SN74 02 N GATE 01295 SN7402N
U33 1820-0174 2 IC SN74 04 N INV 01295 SN7404N
U34 1820-1112 IC SN74LS 74 N FLIP-FLOP 01295 SN74LS74N
U35 1820-0328 IC SN74 02 N GATE 01295 SN7402N
U36 1820-0068 IC SN74 10 N GATE 01295 SN7410N
U37 1820-1056 IC SN74 132 N SCHMITT 01295 SN74132N
U38 1820-0054 IC SN74 00 N GATE 01295 SN7400N
U41 1820-0515 1 IC MV 07263 9602PC
U42 1820-0537 1 IC SN74 13 N SCHMITT 01295 SN7413N
U43 1820-0068 IC SN74 10 N GATE 01295 SN7410N
U44 1820-0511 IC SN74 08 N GATE 01295 SN7408N
U45 1820-0539 1 IC SN74 37 N BUFFER 01295 SN7437N
U46 1820-0054 IC SN74 00 N GATE 01295 SN7400N
U47 1820-0511 IC SN74 08 N GATE 01295 SN7408N
U48 1820-0511 IC SN74 08 N GATE 01295 SN7408N
U51 1820-1084 3 IC N8T09B DRIVER 18324 N8T09B
Us2 1820-0054 IC SN74 00 N GATE 01295 SN7400N
U53 1820-0069 2 IC SN74 20 N GATE 01295 SN7420N
U54 1820-0214 2 IC:TTL BCD-TO-DECIMAL DECODER 01295 SN7442N
U55 1820-0069 IC SN74 20 N GATE 01295 SN7420N
U56 1820-1100 2 IC SN74 298 N MUXR 01295 SN74298N
U57 1820-1196 2 IC SN74LS 174 N FLIP-FLOP 01295 SN74LS174N
U58 1820-1049 3 IC DMBO 97N BUFFER 27014 DM8097N
U61 1820-0621 2 IC SN74 38 N BUFFER 01295 SN7438N
U6? 1820-0068 IC SN74 10 N GATE 01295 SN7410N
U63 1820-1084 IC N8TO9B DRIVER 18324 N8TO9B
U64 1816-0188 1 IC 256-BIT ROM TTL 28480 1816-0188
U65 1820-1195 7 IC SN74LS 175 N FLIP-FLOP 01295 SN74LS175N
U66 1820-1100 IC SN74 298 N MUXR 01295 SN74298N
U67 1820-1196 IC SN74 LS174N FLIP-FLOP 01295 SN74LS174N
U68 1820-1049 IC DMBO 97N BUFFER 27014 DM8097N
U71 1820-1056 IC SN74 132 N SCHMITT 01295 SN74132N
U72 1820-1053 5 IC SN74 14 N SCHMITT 01295 SN7414N
U73 1820-1084 IC N8TO9B DRIVER 18324 N8TO9B
U74 1820-1080 IC N8T138 DRIVER 18324 N8T13B
See introduction to this section for ordering information
6-5
HP 59310B
Table €-2. Replaceable Parts (Continued)
REFERENCE HP MFR
DESIGNATION | PART NO. QTY DESCRIPTION CODE MFR PART NO.
U75 1820-0084 1 IC SN74 53 N GATE 01295 SN7453N
U76 1820-1195 IC SN74LS 175 N FLIP-FLOP 01295 SN74LS175N
U77 1820-1195 IC SN74LS 175 N FLIP-FLOP 01295 SN74LS175N
U78 1820-1049 IC DMEO 97N BUFFER 27014 DM8097N
U81 1820-1053 IC SN74 14 N SCHMITT 01295 SN7414N
U82 1820-0068 IC SN74 10 N GATE 01295 SN7410N
U83 1820-1053 IC SN74 14 N SCHMITT 01295 SN7414N
U84 1820-0070 2 IC SN74 30 N GATE 01295 SN7430N
uss 1820-1082 1 IC SN74 147 N ENCODER 01295 SN74147N
U86 1820-1195 IC SN74LS 175 N FLIP-FLOP 01295 SN74LS175N
U87 1820-1080 IC N8T13B DRIVER 18324 N8T13B
uss 1820-1080 IC N8T13B DRIVER 18324 N8T13B
U91 1820-0621 IC SN74 38 N BUFFER 01295 SN7438N
U92 1820-0054 IC SN74 00 N GATE 01295 SN7400N
U93 1820-0214 IC:TTL BCD-TO-DECIMAL DECODER 01295 SN7442N
U94 1820-1053 IC SN74 14 N SCHMITT 01295 SN7414N
U95 1820-0174 IC SN74 04 N INV 01295 SN7404N
U96 1820-1195 IC SN74LS 175 N FLIP-FLOP 01295 SN74LS175N
U97 1820-1080 IC N8T13B DRIVER 18324 N8T13B
U98 1820-1080 IC N8T13B DRIVER 18324 N8T13B
U101 1820-0782 1 IC SN74 27 N GATE 01295 SN7427N
U102 1820-0511 IC SN74 08 N GATE 01295 SN7408N
U103 1820-0068 IC SN74 10 N GATE 01295 SN7410N
U104 1820-0068 IC SN74 10 N GATE 01295 SN7410N
U105 1820-1053 IC SN74 14 N SCHMITT 01295 SN7414N
U106 1820-1195 IC SN74LS 175 N FLIP-FLOP 01295 SN74LS175N
U107 1820-1080 IC N8T13B DRIVER 18324 N8T13B
U108 1820-1080 IC N8T138 DRIVER 18324 N8T13B
U112 1820-0054 IC SN74 00 N GATE 01295 SN7400N
U113 1820-0706 1 IC COMPTR 07263 9324DC
U114 1820-0070 IC SN74 30 N GATE 01295 SN7430N
U115 1820-0511 IC SN74 08 N GATE 01295 SN7408N
U116 1820-1195 IC SN74LS 175 N FLIP-FLOP 01295 SN74LS175N
U117 1820-1080 IC N8T13B DRIVER 18324 N8T13B
U118 1820-1080 IC N8T13B DRIVER 18324 N8T13B
W1 8159-0005 1 WIRE 22AWG W PVC 1X22 80C 0073G L-2007-1
MISCELLANEOUS PARTS
5040-6001 1 EXTRACTOR:PC BOARD 28480 5040-6001
1480-0116 2 EXTRACTOR PIN:1/16” DIA 73957 GP24-063X250-12
5040-6065 1 28480 5040-6065
1480-0116 EXTRACTOR PIN:1/16” DIA 73957 GP24-063X250-12
6-6
See introduction to this section for ordering information
Table 6-3. Manufacturers Code List
Replaceable Parts
MFR NO. MANUFACTURER NAME ADDRESS ZIP CODE
01121 ALLEN BRADLEY CO MILWAUKEE, WI 53212
01295 TEXAS INST3 INC SEMICONDUCTOR DALLAS, TX 75231
CMPNT DIV
07263 FAIRCHILD SEMICONDUCTOR DiV MOUNTAIN VIEW, CA 94040
16299 CORNING GL WK ELEC CMPNT DIV RALEIGH, NC 27604
18324 SIGNETICS CORP SUNNYVALE, CA 94086
22526 BERG ELECTRONIC INC CUMBERLAND PA 17070
24546 CORNING GLASS WORKS BRADFORD, PA 16701
(BRADFORD)
27014 NATIONAL SEMICONDUCTOR CORP SANTA CLARA, CA 95051
28480 HEWLETT-PACKARD CO PALO ALTO, CA 94304
CORPORATE HQ
56289 SPRAGUE ELECTRIC CO NORTH ADAMS, MA 01247
6-7/6-8
SCHEMATIC DIAGRAMS
SECTION
Vii
7-1. INTRODUCTION
This section contains information for schematic diagram
notes, reference designation system, identification mark-
ings on PC board, an overall block diagram, schematic
simplified logic ‘diagram and component locator.
7-2. SCHEMATIC DIAGRAM NOTES
Figure 7-1 shows the symbols used on the schematic dia-
grams. Notes are also included on each schematic diag-
ram.
7-3. IDENTIFICATION MARKINGS ON
PRINTED-CIRCUIT BOARDS
HP printed circuit boards (see figure 7-1) have four iden-
tification numbers; an assembly par: numbers, a date
code, a revision letter, and a production code.
The assembly part number has 10 digits (such as 59310-
60101) and is the primary identification. All assemblies
with the same part number are interchangeable. When a
production change is made on an assembly that makes it
incompatible with previous assemblies, a change in part
number is required. The date code (such: as 1812) is used to
document minor electrical changes. As changes are made,
the date code is incremented. When replacement boards
are ordered, you may receive a replacement with a differ-
ent date code. If there is a difference between the date code
marked on the board and the schematic in this manual, a
minor electrical difference exists. If it is a higher number,
refer to the loose leaf manual change sheets for this
manual. Ifthe manual change sheets are missing, contact
your local Hewlett-Packard Sales and Service Office. See
the listing on the back cover of this manual.
Revision letters (A, B, etc.) denote changes in printed
circuit layout. For example, if a capacitor type is changed
(electrical value may remain the same) and requires dif-
ferent spacing for its leads, the printed circuit board lay-
out is changed and the revision letter is incremented to
the next letter. The production code is the four digit, seven
segment number used for production purposes.
Symbols are used on PC boards to aid in identifying pin
numbers, diode elements etc. as follows:
AORO IDENTIFIES: Pin 1 of dip and flat-pack IC's.
Tab of TO cases.
+ side of electrolytic capacitors.
Pin 1 of resistor packs.
Cathode of diodes.
Section 1 of dip switches.
7-4. COMPONENT LOCATORS
Figure 7-4 component locator for the printed circuit
assembly is next to the schematic.
7-1
HP 59310B
SYMBOLS
MAIN SIGNAL PATH
[| FRONT PANEL
FEEDBACK PATH
r— —
REAR PANEL
| JA TEST POINT
INTERIOR AND PC BOARDS
"AND" GATE
WIPER MOVES TOWARD *"CW WHEN
COR GATE
POWER LINE GROUND
INVERTER
CIRCUIT COMMON GROUND
FLOATING GROUND
NAND GATE
CHASSIS GROUND
NOR GATE
KNOB CONTROL
EXCLUSIVE NOR
A)
CONTROL IS ROTATED CLOCKWISE
4
Y
rh
O
@
A
SCREWDRIVER ADJUST
PRINTED CIRCUIT BOARD IDENTIFICATION
PC REVISION LETTER | HP PART NO.
| 59310-60101 «—
C- 1826 _22= MANUFACTURING
2 ANUFACTU
2318 DIVISION CODE
PRODUCTION CODE Da
DATE CODE
(May Be Stamped
Elsewhere On The Board)
>
Figure 7-1. Schematic Diagram Notes
COMPUTER
BACKPLANE
CONTROL
PLANE
STC CONTROL LOGIC
IEN |
[ CLC | INTERRUPT PRL FLGL {RQ | N
LOGIC 1
SFS | | 10
SFC , SFS/SFC SKF | CARD
| LOGIC bo OUTPUT
| | SIGNALS
; DCPC SRQ =
| wor er
Je
| |
| 100 & |
101 DATA |
— | ° INPUT/OUTPUT
| CONTROL |
| EV, ELA | Г A
| > FLAGS MULTIPLEXER x ) | “x |
| | | ASCII LOGIC |
| | | IFC SURFER IFC PRIORITY 4 |
| | | Ba | нот X & FILTER ENCODER / A |
| | 54 |
| E
/ 3
| | J REN FF | a 7 7 a |
REGISTER +
— | 8 DECODER Ll |
| i | | STATUS |
PARALLEL WORD
L — TT TT — —— — = == == === == == == == =—= = — — | | ACTIVE FF — SRQ DATA |
| |
1
| 7 |
| |
| REQUEST
LOGIC BUS 2, |
> COMMUNICATOR 7 N |
X Lo
ATN EF ADDRESS |
Le x COMPARATOR ЭЙ
| ;
| Г MODE ЕО! ADDRESS FOR 14 |
| LOGIC nn EF SWITCH FLAG N |
À
L hm o— — _o— _—lo— — — —— CNT ED CU —_— — — — —][—o—;—]Ñ—Ñíúk — — —o — — kh — o E em et AMIS SEAL AMES WHA GEE CEE je eke ees ces EE oj—]. — J
[| — — — E == о PT EL — TT PT PI —
| COMPUTER DATA | | BUS DATA |
| CONVERTER LOGIC | Y | MOTOR CONVERTER LOGIC |
OUT OUTPUT |
| E ae + y 2D À
| |
| | | 7 | т HANDSHAKE в DATA 1 |
| Nn | | LOGIC CONTROL 7 |
8 4
‚и > | L |
1080 | Cy > ый ——— ’ 8 Ly | + ый 7 № 108!
> FE $ A ART on
1 /
BP OUTPUT OUTPUT — 29 / | 5 ! ET 8 /
Er 7 Tae TT êtes a | | | | ко | та won |
ATUS WOR
| | 0101 ATH ЧАР | RECEIVERS _ DATAMORD — MULTIPLEXER
TO ¿FC NDAC REGISTER |
L — — o a a o > e o a o o e o — J D108 EOI || —
46 — 32 23 /7 _/6_1/5_/4 73 0 8
x TP / dS OY ol | © « =
Ч Te" Si & © 5} «| = &
Q Q v x 2 Ol + ~ BUS INPUT OUTPUT
CLC PRL y
STC ELGL Y
2 С INTERRUPT CONTROL AND 7RQ >
25 SES FLAG ~SELECT LOGIC SKE >
> CLE SRQ
9 STE —
у FLAGS STATUS WORD/ DATA WORD SELECT
701 DÂTA (8)
24 — а Ko
INPUT - 7P2 o
го 199 — y OUTPUT | ®— BUS 2 SRA 70 CODE
CONTROL TALK lo SW I (7-8)
CONTROL ED |
~J 429
Si» t LOGIC
ELO S 703 |
SiS < Su LISTEN” Swe (7)
LJEG 3/20 (600 oJ REN
CONTROL CHAR. y 0, MY 7087 €
35 —080 € | RECOG. | % ADDRESS STATUS
38 | | 2, q 5 BUS |
41 220 DORESS
q ) A
PY | COMPUTER - Е ASCO ; a 1/0 CARD | Two |
5 CONVERTER LOGIC x 3 LOGIC я CONVERTER |
53
52 LOGIC IM A. @ LOGIC |
í ba)
54 | 7 ; 7 7 7 - 7 / = - oy - 7 > 7 |
se| | LIT ONE BUS (FF И Их вата вия [И
sa| | ПИ |
Se | TE TRANSFER BUS N CAT 7 TRANSFER BUS 7A |
57 2 |
6/ | ©) , y © SHIELD |
/ SW2(8
Sa |-7080/5 , A AA (8) 1081 15
amas QSIEN VAIO y
— — y Y y Y Y Y—Y Y Y-Y Y Y == у — Y — —
SPA RH 19) O7 | 0
inde sul wg SQ
Aaa Ey
NE NU ioe |] S32 ON
3999/9393 + Hula JAY 9 os
£I3/0-60002
4 METERS
1 1868688 avoress | REPRESENTATIVE 'BUS COMMUNICATOR
| J J d $ J SELECT SW | cocrc WITHIN A BUS COMPATIBLE DEVICE
| ENABLED 70 TALK хи ‚ «— 2707
— — ><. 2102
| CATA OUT \ | 3 < 2103
u ase DATA INPUT y + 2105
UI | Daran CONTROL & | AA 13 ———
2 ADDRESSING DATA IN
Eu ere LOGIC E
L $ мо CLEAR y
3 SX | COCA) — OTN "PIGGYBACK" CABLES
SIS ATA TO OTHER DEVICES (2)(3)
ых ès | MY REN €K_-— = — 10631A - 1 M. CABLE
K| EX | 2004 ZocaL IFC 106318 - 2M. CABLE
330 | RUT Zo 10631C - 4 M. CABLE
x 5 | LLO) 6 €——
3 SPE & SPL
&| © REMOTE
h | ENABLE ?
= LOGIC. |
> | leo 70 REMOTE INTERFACE
/FREN:L CLEAR о
| | AND THIS LOGIC CLEAR END SERVICE
LOCAL | DEVICE 15 ALL BUS oF REQUEST
7
RESET ADORESSEO| |COMMUNICATOR| | RECORD HANDSHAKE
GO T0 LOCAL CIRCUITS LOGIC LOGIC ogre
| | уе REN =H IE IEE =L
|
BUS SIGNAL LINE CONVENTIONS
MNEMONIC “TRUE" VOLTAGE
PREFIX LOGIC STATE LEYEL
NONE LOW <+0,4V
N HIGH +2, 4V
5 Na AU
~~,
26
29
30
64
’7
30
в,
84
27
28
3/7
&0
75
82
a3
TEST-POINTS
1/0 CARD | CONTROL TEST-POINT TO VERIFY ACTION
CONTROL WORD WORD ACCESS PT. |. CABLE PIN | STATUS
BIT 4's FUNCTION ON CARD © 7 1/0 T BUS WD. BIT
IFC (1004$) U41 (6) Al” 21 9 -
REN u43 (6) Г U 17 8
2-9 ACTIVE U21 (9) } 1 - - 4
FORCE INPUT usd (7) u |} - - -
CYCLE |
CLEAR 1/0 CARD | U54 (9) ur | - - -
ATN U21 (5) 23 ha 7
6-3 EOI U22 (6) | AD 57 -
TALK TP-2 1 - 5
LISTEN TP-3 | - - 6
ASCII MODE ues (10)! | - - -
SRO ENABLE UES (15): | 257) Y -
1! - В DMA R/W SELECT | U65 (2) | ' - - -
(BIT 7 PACKING/ Ue5 (7) Го - -
ENABLES) UNPACKING | I
1
15 - 12 EOR FLAG EN. U76 (15) Г - - 12
(BIT 7 ORA FLAG EN. U76 (10) Г - - 13
ENABLES) | IRL FLAG EN. ure (7) Г - - 14
SEP FLAG EN. U76 (2) Г - - 15
NOTES:
© The cable shield is grounded only once, and is done at the System Controller.
The maximum accumulated cable length (per bus) is 20 meters, total.
© ©
A bus cable network must not exceed an average of one “standard load" device
for each 2 meters of bus cable; i.e.:
TOTAL CABLE CER < 2 meters/davice
Remember that the I/O card must be counted as one of the devices.
The 1/0 card's circuitry has one "Standard Load" on each bus signal line,
Bus cable signal grounds are connected to I/0 card common at connector pins
V,W,X,Y,Z,AA and BB.
Use TP-1 (2100 time "t2") to sync 'scope for dynamic tests.
Oe OO
State of these signal lines is dependent on other 1/0 card functions that are programmed.
Figure 7-3. 59310B Simplified Logic Diagram
(Sheet 1 of 2)
7-5/7-6
1/0 CARD
ASCI1-MODE FUNCTIONS
| -— CODE —————
| ASCII
FUNCTION | (TTY KEY) OCTAL DECIMAL
IFC (100us) 1 — ESC 33 27.
: Esc) (8)
|
REN = L | STX 2 2.
1. (CTRL-8)
=H EX 3 3.
| {CTRL-C)
АТМ = | 50 16 14.
| (СТК -м)
= K ji SI 17 15.
j (CTRL-O) |
| i
| |
GENERAL BUS-CODE ALLOCATIONS WITHIN THE ASCII-CODE SET
DIC LINES UNIVERSAL BUS COMMANDS DEVICE LISTEN ADDRESS DEVICE TALK ADDRESS
8 ——- | x. x X x. x X
7 —— H Tho ko Hoy bo Lo
6 — HH LE Lo Lo OH) он,
о — — H L H L H L
|| ——
COLUMN 8 ] 2 3 4 5
—l — -— == |
4 3 2 «< =; <T = ‹ < æ Um < aw < awn
| { — = | _ = =<: — = Du — x Ow — = Du — x cu
! | << = x < — = x — me “I — me < € me I …— ou
| | + у — o VE — < NE) + [a] zo H oO EO — © zo — or FO
m uy oo cs Las = о — ad > 93 > wd > © < wd > a c J > ©
© ao aa < = за < = wv = < = u <= < a Ww) «< © a LA) <=
| |
i ' {
H H H H ' 0 в 0. :28 16. ¡49 32. SP (69 48. O |199 64. @112ß 80. Р
HH HL ] 1 0. 21 17, LLOJ41 33. *! |61 49, 1 (191 65. А 21 81. Q
H H L H 2 ; 2 2. 22 18, R*|42 34. " |62 50. 2 1192 66. B 122 82. R
H H LL 3 | 3 3. 23 19, R*:43 35. # |63 51. 3 [183 67. C |123 83. S
H L H H 4 | 2 4, :24 20, DCR 44 36. $ 164 52. 4 1184 68, 01124 84. T
H L HL 5 | 5 5. 25 21. 45 37. % |65 53. 5 11895 69. E [125 85. u
H L L H 6 | 6 6. 26 22, 46 138. & [66 54, 6 196 70. Е [126 86 \
H L LL 7 ; 7 7. '27 23. 47 39. ' 167 55. 7 1187 71. 6 |127 87. G
LH HM 8 18 8. 39 24. SPESA 40. ( 179 56. 8 |11ß 72. Н |139 88, X
L H HL 9 11 9. ‚31 25. SPCI51 41. ) 171 57. 9 1111 73. 11131 89. Y
L HL Hilo | 12 10. 32 26. 52 42, * 172 58. : {112 74, J 132 90, Z
Lo HL Lo, 11 (13 1. 133 27. 53 43. + [73 59. (11375. kh33 91. [
{ i .
L L H H | 12 ‘14 12. 34 28, R*|54 44. , |74 60. < |114 76. L [134 92. \
LL H L ; 13 1513. 35 29. R*|55 45, - 175 61, = [115 77. M135 93. ]
LL Là | 14 116 14, 36 30. 56 46. . |76 62. > |116 78. N {136 94. A
L LL L 5 Ш 15. 37 31. 57 47. / [77 63. 211117 79. of137 9. —
| | UNL ISTEN UNTALK |
| | COMMAND COMMAND y
H = High State. LLO = Local Lockout. SPE = Status Poll Enable.
L = Low State. DER = Device Clear. SPD = Status Poll Disable.
X = Unused when MRE is low. R* = Reserved or DIO = Data Input Output
_ future assignment ; |
à = Control Bits Signal Lines,
a. - NOTE THAT ASCII COLUMNS DIC1-8
6 AND 7 ARE NOT USED.
PAGE 8002 NEL AMD SO3IDAa OPIO QUBSYSTEM TOGOLE TEST PROGRAM
ne: ASMB,A,B,L
[-] 1. 00108 ORG 1888
ОВ»
00050 THIS TOGGLE PROGRAM PROVIDES FOR COMPLETE FUNCTION
06068 PROGRAMMING OF THE 59310-621801 BUS I/0 CARD, PLUS
00071 CONTROL OF INDIVIDUAL SIGNAL LINES WITHIN THE BUS
gosse CABLE, IT MAY BE RUN WITH OR WITHOUT INSTRUMENTS
00098 ON THE BUS,
00100
991 1+ SPECIFIC BIT PATTERNS ARE ENTERED VIA THE COMPUTER'S
08128 FRONT PANEL REGISTERS, BOTM AS CONTROL WORDS TO THE
901 3. 1/0 CARD AND AS DATA WORDS TO THE BUS DIO SIGNAL LINES,
08140
20150 TME PROGRAM RETURNS THE I/0 CARD'S STATUS WORD
90160 IN TME 8 REGISTER,
0817
9018. ACTION CAUSED BY SPECIFIC CONTROL WORDS CAN BE CHECKED
00191 AT ACCESS POINTS ON THE I/0 CARD, AT THE CABLE
0820. CONNECTORS AND/OR IN THE STATUS WORD RETURNED IN THE
2821 B REGISTER,
0022.
0023. TEST EQUIPMENT FOR CONVENIENCE IN LOGIC LEVEL TESTING!
ERA" LOGIC PROBE LOGIC CLIP FIXTURE FOR BUS CABLE
9825 HP 1895257 HP 105284 MP P/N BOSP=8124
96280
ace?
20280 TO USE THIS PROGRAM)
0020. L. LOAD THE PROGRAM BELOW, USING THE COMPUTER FRONT
80300 PANEL CONTROLS AND ENTERING TWE 1/0 CARD'S
Sorin SELECT CODE (CSC) WHERE REQUIRED,
9832 2. SET STARTING ADDRESS oe (86 OCTAL, AND PRESS
203d» BOTH PRESET BUTTONS,
90340 $, SET CONTENTS OF THE NEGIBTERS AS APPROPRIATE:
2835» DATA TO THE BUS DIC SIGNAL LINES = = u 8 REG,
2038» CONTROL WORQ TO THE BUS 1/0 CARD = = = A REG,
2037»
086300 NOTES! THE FIRST WORD OUTPUT TO THE 893188
0039» POLLONING A 'STC SC,C! INSTRUCTION IB
08400 ALWAYS CONSIDERED TO BE A CONTROL WORD,
0041 + ANY BUBSEQUENT WORDS ARE TREATED AS DATA
80491 UNTIL ANOTHER !87P SC? INSTRUCTION IS
00430 ENCOUNTERED,
8044s
баб. THE DATA IN THE SWITCH REG, IS OFFSET ONE
00480 PLACE FROM THE DIO LINES POR CONVENIENCE IN
6247. USING OCTAL PORMATI I,E,: BIT 8 OF TME
8040 8 REG, a DIO LINE 1, BIT ı OF 3 REG, = DIO 2,
90491 ETC,
dese
2051. 4, PRESS 'RUN', THE PROGRAM MALTS,
30520 OBSERVE 1/0 CARD'S STATUS WORD =» = = 8 REG,
9553. Y, NOTE THAT THE DIO LINES ARE SET ONLY IF THE 1/0
e 4u CARO 18 PROGRAMMED TO TTALK' OR '"MRE' 18 SET LON,
80580 6, OBSERVE OTHER RESULTS, AND REPEAT STEPS 3.6
воза» AS APPROPRIATE,
00870
geste
9650 GELES 064114 START LOB В? GET CLEAR CODE
0060 881061 162177 a7TF sc CLEAR 1/0 FOR USE W/0 MANDSMAKE
8861 09102 186677 ОТВ 8C
09962 82103 1986577 LIB SC SET STATUS/READY 1/0 CARD
0063 #164 182177? SF" 8“ RELEASE CARD FROM CLEAR MODE
6864 E2188 182077 OYA SC SEND A REG AS CONTROL WORD
0065 806106 186591 LIB 1 GET Sw REG
0866 30107 107877 OTB SC,C SEND DATA TO 1/0 LINES
9067 Celia 192177 SF SC
0068 81:1 1668577 LIB SE GET STATUS WD FROM 1/0 CARD
0069 08110 102000 HLT 28 {NOP FOR CONTINUOUS LOOPING)
R078 08113 824100 JMP START
00711.
0072 88114 0080087 В? OCT 7 CODE TO CLEAR 1/0 CARO
8073 66077 sc EQU 778 SELECT CODE OF 1/0 CARD
Ве? 4+
0878 END
жа NO ERRORBI AMD ASHMB, 251170400518
NOTES
(A) Data is put on the DIO Signal Lines only if the 1/0
card is programmed to TALK, or if the ATN line
is programmed LOW,
ESCAPE (ESC) Key on HP 2754B (ASR-35) is OCT
176: to get OCT 33, Press CTRL-SHIFT-K.
Figure 7-3. 59310B Simplified Logic Diagram
(Sheet 2 of 2)
7-7/7-8
HP 59310B
Schematic Diagrams
TO
FROM U48D (II)
FROM U268(4)
FROM
10800
IoBo!
10802
10803
10804
10805
10806
10807
10808
15809
1098010
I0B0 | |
108012
108013
108014
108015
U74(1,2)
26,15
a
UY5(13)
3H,13
TO U75t9)
3H,13
TO U75(3)
3H,13
TO UT5(4)
6,13
»
Coll
U4BA(3)
3F,14
—
35
38
41
45
42
51
BACKPLANE
DATA
4 |
CONTROL WORD
REGISTERADECODER
FROM
U44AC3)
38,10
OUTPUT
,— WORD
REGISTER
0 Q
TN
Г 7 | 8 | 9 | 10 |
BUS INPUT/OUTPUT CARD (59310-6010!) DATE CODE 1826
TO U23C(10)2E,13
TO U258<1032E, 14
—— ASCII] MODE LOGIC ——
TO U8641)3F,3 R2! 2700
TO U228(11}20Cj2
TO U74(14)3H,15
TO U74(12/13} 3H,15
TO US4A(12)2B,7
TO U62C(11)2B,3
TO UISA(1)2D,14
QUTPUT DATA CONTROL
FROM
UI7C (8)
3E,11
QUT REG FLG
TO U74
(10,11)
3H,15
¡ VIO2A
TO U75(10) 3H, 13
UFO7(15) 36,6
TO U62C( 10
OBRL
ST
cz 100ns
CRI „001
R9
E21
OUTPUT
— BYTE
STER
CRE
U33A
IFC
|-SHOT
R3 C5
OR IVER lA
UIB
TO UT2F(13) 2C,2
REN DRIVER
Usia —
TO UBIECIN2D,2
IB
!
(318 ACTIVE FF
TO U7 ICI9)3G,12
TO UI18{12,13)3C,6
TO US28(4)36,12
TO ATN (2E,2)
TO UN20 36,16
FROM USTA(3)2C,13
TO EOI (2F,2)
О
a
USIB
FROM U72E (10) 2C,4
OUTPUT HANDSHAKE
LOGIC TN
—
TO UB8(12,13)3F,6
U4 DAV FF
TO UBIB(S)ZE,6
TO U87(1,2)3E,6 IE
ST
ca 200ns FROM USID(I1) 2F
0022 ’ a
FROM USIC(8) 2F, 2
TO U94A(1} 2F, 2
TO U94B(3) 2F, 2
TO US4C(S5) 2F,2
TO U94E(I1) 26, 2
T
o
U83D(S) 26,2
T
La)
UB3E(IN 26, 2
TO UB3F(13) 26,2
TO U72D(9) 26,2
TO UISB(12)2D,12
TO U228(12)2D,!2
SHEET 1 OF 3 —
|| | 12 | 3 | 14 |
7700-174
Figure 7-4. 59310B Component Locator
Figure 7-5. 59310B Schematic Diagram
(Sheet 1 of 3)
7-9/7-10
34TTA
34778 Schematic Diagrams
2A
28
2C
2D
2E
2F
26
2H
FROM U62B(4)1D,10
FROM U65 (IS) IB,5
FROM USIB(6)
lA,13
,
FROM USIA (3)
18,13
FROM USIDC!1)
1С, 5
FROM USIA(3)
FE,t3
FROM USIC(8)
10,13
TO UBIALI)
IE,I3
UBIB(3)
1F,13
FROM U638(6)
16,13
FROM U63A(3)
IF,t3
FROM U63D(1 1)
IF,I3
FROM U63C(8)
16,13
FROM U73C(B)
16,13
FROM U73D4 11)
16,13
FROM U73A(3)
IH,13
FROM U738(6)
IH
P/O
R21
3000
$
Ji
SRG
2 3 | 4 | 5 | 6 | 7 | 8 9 10 | || 12 13 | 14 | |5 | 16 |
RED BUS INPUT/QUTPUT CARD (59310-60101) DATE CODE 1826
—
— "LF" DETECTOR — ENCODER
REQUEST LOGIC—
— IFC FF —
TO UY 1D
(12)36,12
A TO U97 (15)
3A,6
B
| TO U98(5)
FROM USSA(G) 3B,6
STATUS POLL FF
USD
TO U97(1,2)
uss C ov
USIC
UI38
TO U98(12,13) |
30,6
+
TO UTIDC13)
36,11
TO
528 (5)
36,12
00 — DUR GUN —
TO UNZ2(9)
3H,13
BUS
COMMUNICATOR
LOGIC
— INPUT DATA CONTROL
R7 ca
5100 lOPF
—— IFC BUFFER/FILTER ——
RA
UT2F 12] UT2E
TO U33E(11)
10,11
CR3 15
FROM
U45(6)
3F,15
ce
e
U4iB
T
q
ТР?
"TALK"
TO UIIB{5}3D,6
FROM
U22A(2)IC,12
UIO3A FROM
U44B
(5)iB,6
TO U3ID(B)10,13
+5 Y
4 | U1J4B
TO U87
(15) 3E,6
TO UN7(15)
3D6
UIED
FROM U22A(2)
Uloac —UlosF
SW Ill
3 2
ADDRESS
SWITCH
(OR PLUG)
PARALLEL SRQ I.D.——— ——
2
D q
41585
y33c U44C
TO U86(9),
UIO6(9) 36, 2
LOW HLF CLK
у1028
INPUT HANDSHAKE LOGIC
uti2a UII2B FROM U54(7)
IA, 5
UIOSE
DAV TI IRL FF
TO U7S (2)3H,13
Dyasa®
с
РВОМ у450(1) ЗЕ. 14
UP HLF CLK
U44D
U7 |A |
ST
ST TO UILT7(1,2)
3D,6
FROM U54(9)
TO U86(9),
Ulie(S) 3G,2
C7 300ns
OI
R
-0 FO FF
CB 1|00ns
„0022
-2V
RI9
1500
5 U74
Dose
2550
U76(15)
18,2
TO UBB(S)3F,6
TO DION3E,1)
TO DIOZ(3E,1)
TO DIOSB(3F,1)
TO DIO4(3F,1)
DIO RECEIVERS
TO DIOS(36,1)
TO DIOG(3G,1)
TO DIO7(3H,1)
To DIO8(3H,1)
EOR FLAG —
LOGIC
EOR FF
T
o
U75(1)3H,13
UENCIN)
D q
¿U348
+
9
CLR INT FLGS
» TOUI3B(5) 2B,5
TO ULO7CI,2)3H,6
0 UIOB(12,13)36G,6
FROM U46DG1)3D,12
FROM U34A(6)3F,i3
2A
2B
2C
2D
2E
2F
2G
2H
IFC
REN
DIO!
DIO?
ATN
DAY
EOI
COMMON BB
SHIELD 24
SHEET 2 OF 3
3 4 | 5 | 6 7 8 9 | 10 | |2 | 13 | 14 | 15 | 16
Figure 7-5. 59310B Schematic Diagram
(Sheet 2 of 3)
7-11/7-12
3A
3B
3C
3D
SE
SF
3G
3H
FROM U44C (LI)
2E,16
FROM U94A(2)
2F,7
FROM U94B(4)
2F,7
FROM US4C(6)
2F,7
FROM U94E(10)
AND U94D(9)
FROM UBS (7)
IC,5
FROM UB3D(8)
26,7
FROM US3E( 10)
26,7
FROM U44D(8)
2E
1
FROM UB3F (12)
G,7
FROM U720(8)
,— INPUT DATA/WORD—
REGISTER LOWER HALF
STATUS WD
DATA/WORD
ISTER UPPER HALF
FROM U45A(3) 3H,15
FROM U45B(6)3H,15
FROM U95D (8)
2A,I
FROM U9SC{6)
2B,ii
FROM USSE (10)
28,11
FROM U9SF (12)
2B,ll
+
FROM U2IB(9)
1C,14
FROM U22B(9)
2C,12
FROM UISB (9)
20,2
FROM UVIOS (+)
2
FROM UBIE (10)
2D, 3
FROM UBID (8)
1£,13
FROM UBID (12)
IE,I3
FROM DAV
(2F,10)
FROM U34B(9)
14
FROM UIO2 (3)
7
FROM U25A (5)
2E,14
FROM US2A (3)
36,12
5
INPUT DATA & STATUS WD
7
P/OT
26
23
30
64
TT
80
8 |
84
27
28
60
78
79
82
B3
,— COMPUTER
1/0 BACKPLANE
IGBIO
IOBI |
10BI?
10813
10BI4
10815
ТОВ 16
IoBIT
10618
I0BI9
108110
IOBINI
108112
IOBI13
ТОВ 14
ТОВ 15
8
_ _BUS INPUT/OUTPUT CARD
9
10
(59310-60101) DATE CODE 1826 _
SIR TS
IEN
STC
CLC
ENF T2
CRS
POPIO
IAK
CLF
101
100
LSCM
LSCL
106 8
32
22
21
46
25
24
20
7 |
P/O |
|p ‘а U288
С 15 TO UI6 (1)1A.4 |
| |P/0 RIE E 6 U44A y 9 S 3 PRL
y | | 15004 — L2 3 ?
No Cc 4 LL P/O RI4 |
| | 1500
| | 9 , V2TC 7/ _F Do
«Ц = VA |
y na TT | >
i |proRI4] 6 |e = 3 3 54 FLGL
71 | 15000 — | A A
Na
1,2
3,4 | 7
ı [Pro rRıel 6 |s : > 6 IRQ —
| [15604 [7 5 '
| | el] !
VAL .
NE YP/IORIS] A [2
| LL
| | 500 U26A и FLAGS € 3C
< 2,3 o
>| RS U268
1500 11,12 13
| TF1 U26B CRS POP 10
| 'T2' | 5 L 13, U3GA FLAG BUFFER || U37C FLAG FF |
N 1 6] Joi TO U76 9
| | ” IB,
| P/ORIS| F |7
, 1] 15000 pes N
NT -
| | D 5
É РС
< |
| y UNTB
<G 6 CLR INT FLES
| | ls == TOU35B(5,6)2H,15
С —_—
| P/ORIAL S18 UITC CLFSC UI6C 12 2460 ,— SFS/SFC LOGIC—
|, 1500 9 5 || —
N |
| D 5 4 U48B
VY TO Ut4B 4
| 6 6 U28A |
o | (10167 5 =
NT
| | | —
i | Pro RIS 5 1 4
FA 7 x 3E
ı | 1500 3 12 SKF
< i 2 „ 7
| |
y DATA INPUT/OUTPUT \
| P/O RI4 6 1о U48C CONTROL U45C U45A |
| | 15006 + 5 8 10 1,2 3 10ISC STATUS
+ } 9 | 3 æ- TO UIOB (6)3H,6 —_
| | jo U38C 100 DESKEW FF | u4TC Vaso Case TOISC DATA TO U418(11)2C,14
ı [P/0 Rıs |_LF.__ 17 i 8 100SCT5 13 las 6
| [1500 ME 12 T > = TO U108 (3,4)3H,6
1
a | _ vol, ba ¡3 U48D = TO U25A (1)2E.14
| { \ 1 |
»- TO и4ТА(1)1С
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|
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A lOPF DATA MODE
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y 1500 В 3 2 100 ns
x
mm— 9 + FLAG MULTIPLEXERÑÑ -
FROM USIC(8) SRA FLG |
|, ——® TO UI08 (5)3H,6 |
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, FROM U76 (2) Ale — —
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TD
urs
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|
FROM OR FLG 10
Pi ORA F >
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18,2
FROM U34B(9) —mEOR FLO !
2H,14 13
FROM U76 (15) _p, EOR FLG EN |
__ 18,2
DCPCRW SEL e FROM UBS (2)18,5
—DCPCRW SEL as FROM U5 (3)IB,5
DCPC OUT REQ FLG
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DCPC FLAG MPLXR À
10,11 U74 | 1500
12,13 | |
| |2 | 13
SHEET 3 OF 3
|5 | 16 |
SA
SRQ 3H
Figure 7-5. 59310B Schematic Diagram
(Sheet 3 of 3)
7-13/7-14
2) Packano
Manual Part No: 59310-90068 HEWLETT-PACKARD
Printed in U.S.A. Roseville Networks Division
August 1982 8000 Foothills Boulevard
Roseville, California 95678
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