NXP MCF527X ColdFire® V2 Integrated Microprocessor Data Sheet

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Document

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCF5271EC

Rev. 4, 08/2009

MCF5271 Integrated

Microprocessor

Hardware Specification

by: Microcontroller Solutions Group

The MCF5271 family is a highly integrated implementation of the ColdFire

family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent features and functions of the MCF5271 family. The MCF5271 family includes the

MCF5271 and MCF5270 microprocessors. The differences between these parts are summarized below in

Table 1

. This document is written from the perspective of the MCF5271 and unless otherwise noted, the information applies also to the MCF5270.

Contents

1 MCF5271 Family Configurations . . . . . . . . . . . . . . . . . . . 2

2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 8

6 Mechanicals/Pinouts and Part Numbers . . . . . . . . . . . . 12

7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9 Document Revision History . . . . . . . . . . . . . . . . . . . . . . 39

The MCF5271 family combines low cost with high integration on the popular version 2 ColdFire core with over 144 (Dhrystone 2.1) MIPS at 150 MHz. Positioned for applications requiring a cost-sensitive 32-bit solution, the MCF5271 family features a 10/100 Ethernet

MAC and optional hardware encryption to ensure the application can be connected and protected. In addition, the MCF5271 family features an enhanced multiply accumulate unit (eMAC), large on-chip memory (64

Kbytes SRAM, 8 Kbytes configurable cache), and a

32-bit SDR SDRAM memory controller.

MCF5271 Family Configurations

1 MCF5271 Family Configurations

Table 1. MCF5271 Family Configurations

Module MCF5270 MCF5271

ColdFire V2 Core with EMAC and

Hardware Divide

System Clock

Performance (Dhrystone/2.1 MIPS)

Instruction/Data Cache

Static RAM (SRAM)

Interrupt Controllers (INTC)

Edge Port Module (EPORT)

External Interface Module (EIM)

4-channel Direct-Memory Access (DMA)

SDRAM Controller

Fast Ethernet Controller (FEC)

Hardware Encryption

Watchdog Timer (WDT)

Four Periodic Interrupt Timers (PIT)

32-bit DMA Timers

QSPI

UART(s)

General Purpose I/O Module (GPIO)

JTAG - IEEE 1149.1 Test Access Port

Package x x x x

3 x

— x x x x x

2 x

150 MHz

144

8 Kbytes

64 Kbytes x x x x

3 x

4 x x x x x x

2 x x x

160 QFP,

196 MAPBGA

160 QFP,

196 MAPBGA

2 Block Diagram

The superset device in the MCF5271 family comes in a 196 mold array plastic ball grid array (MAPBGA) package.

Figure 1

shows a top-level block diagram of the MCF5271.

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

(To/From SRAM backdoor)

Arbiter INTC0 INTC1

EIM

CHIP

SELECTS

EBI

(To/From PADI)

FAST

ETHERNET

CONTROLLER

(FEC)

(To/From PADI)

(To/From

PADI)

4 CH DMA

DREQ[2:0] DACK[2:0]

JTAG_EN

UART

C QSPI

DTIM

SDRAMC

V2 ColdFire CPU

DIV EMAC

JTAG

TAP

Watchdog

Timer

64 Kbytes

SRAM

(8Kx16)x4

8 Kbytes

CACHE

(1Kx32)x2

(To/From Arbiter)

PORTS

(GPIO) CIM

Block Diagram

SDRAMC

QSPI

I2C_SDA

I2C_SCL

UnTXD

UnRXD

UnRTS

UnCTS

DTnOUT

DTnIN

FEC

D[31:0]

A[23:0]

R/W

CS[3:0]

TSIZ[1:0]

TEA

BS[3:0]

SKHA

RNGA

MDHA

Cryptography

Modules

PLL

CLKGEN

(To/From INTC)

PIT0

Edge

Port

PIT1 PIT2 PIT3

Figure 1. MCF5271 Block Diagram

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Features

3 Features

For a detailed feature list see the MCF5271 Reference Manual (MCF5271RM).

4 Signal Descriptions

This section describes signals that connect off chip, including a table of signal properties. For a more detailed discussion of the MCF5271 signals, consult the MCF5271 Reference Manual (MCF5271RM).

4.1 Signal Properties

Table 4 lists all of the signals grouped by function. The “Dir” column is the direction for the primary

function of the pin. Refer to Section 6, “Mechanicals/Pinouts and Part Numbers

,” for package diagrams.

NOTE

In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon.

NOTE

The primary functionality of a pin is not necessarily its default functionality.

Pins that are muxed with GPIO will default to their GPIO functionality.

Table 2. MCF5270 and MCF5271 Signal Information and Muxing

Signal Name GPIO Alternate 1 Alternate 2 Dir.

MCF5270

MCF5271

160 QFP

MCF5270

MCF5271

196 MAPBGA

RESET

RSTOUT

—

Reset

—

N13

P13

EXTAL

XTAL

CLKOUT

CLKMOD[1:0]

RCON

A[23:21]

—

PADDR[7:5]

—

Mode Selection

—

External Memory Interface and Ports

20,21

CS[6:4]

Clock

—

M14

N14

K14

G5,H5

K10

O 126, 125, 124 B11, C11, D11

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Signal Descriptions

Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)

Signal Name

A[20:0]

D[31:16]

D[15:8]

D[7:0]

BS[3:0]

TEA

R/W

TSIZ1

TSIZ0

TIP

CS[7:4]

CS[3:2]

CS1

CS0

SD_WE

SD_SCAS

SD_SRAS

GPIO

—

PDATAH[7:0]

PDATAL[7:0]

PBS[7:4]

PBUSCTL7

PBUSCTL6

PBUSCTL5

PBUSCTL4

PBUSCTL3

PBUSCTL2

PBUSCTL1

PBUSCTL0

PCS[7:4]

—

CAS[3:0]

—

DREQ1

—

DACK1

DACK0

DACK2

DREQ0

—

PCS[3:2] SD_CS[1:0]

PCS1

—

Chip Selects

— O

123:115,

112:106, 102:98

A12, B12, C12,

A13, B13, B14,

C13, C14, D12,

D13, D14, E11,

E12, E13, E14,

F12, F13, F14,

G11, G12, G13

22:30, 33:39 G1, G2, H1, H2,

H3, H4, J1, J2,

J3, J4, K1, K2,

K3, K4, L1, L2

42:49 M1, N1, M2, N2,

P2, L3, M3, N3

50:52, 56:60 P3, M4, N4, P4,

L5, M5, N5, P5

143:140 B6, C6, D7, C7

—

H11

J14

J13

—

H13

H12

—

132,131

130

129

B9, A10, C10,

A11

A9, C9

B10

D10

PSDRAM5

PSDRAM4

PSDRAM3

SD_CKE PSDRAM2

SD_CS[1:0] PSDRAM[1:0]

Alternate 1 Alternate 2 Dir.

—

SDRAM Controller

—

MCF5270

MCF5271

160 QFP

—

MCF5270

MCF5271

196 MAPBGA

K13

K12

K11

L12, L13

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Signal Descriptions

Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2 Dir.

MCF5270

MCF5271

160 QFP

MCF5270

MCF5271

196 MAPBGA

IRQ[7:3] PIRQ[7:3]

External Interrupts Port

— — I IRQ7=63

IRQ4=64

—

N7, M7, L7, P8,

IRQ2

IRQ1

EMDC

EMDIO

ECOL

ECRS

ERXCLK

ERXDV

ERXD[3:0]

ERXER

ETXCLK

ETXEN

ETXER

ETXD[3:0]

I2C_SDA

I2C_SCL

PIRQ2

PIRQ1

DREQ2

—

PFECI2C3 I2C_SCL

PFECI2C2 I2C_SDA

—

PFECI2C1

PFECI2C0

—

FEC

—

U2TXD O

U2RXD I/O

—

— I

—

DMA

I/O

DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads. Please refer to the following pins for muxing:

TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1,

TSIZ0 and DT0OUT for DACK0, IRQ2 and DT2IN for DREQ2,

TEA and DT1IN for DREQ1, and TIP and DT0IN for DREQ0.

QSPI

QSPI_CS1

QSPI_CS0

QSPI_CLK

QSPI_DIN

QSPI_DOUT

PQSPI4

PQSPI3

PQSPI2

PQSPI1

PQSPI0

SD_CKE

—

I2C_SCL

I2C_SDA

—

5:2

159

151

150

158

157

156

155:152

—

139

146

147

148

149

D3, C1, C2, B1

A3, A4, C4, B4

J12

J11

—

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Signal Descriptions

Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2 Dir.

MCF5270

MCF5271

160 QFP

MCF5270

MCF5271

196 MAPBGA

U2TXD

U2RXD

U1CTS

U1RTS

U1TXD

U1RXD

U0CTS

U0RTS

U0TXD

U0RXD

DT3IN

DT3OUT

DT2IN

DT2OUT

DT1IN

DT1OUT

DT0IN

DT0OUT

DSCLK

PSTCLK

BKPT

DSI

DSO

JTAG_EN

DDATA[3:0]

PST[3:0]

PUARTH1

PUARTH0

PUARTL7

PUARTL6

PUARTL5

PUARTL4

PUARTL3

PUARTL2

PUARTL1

PUARTL0

—

PTIMER7

PTIMER6

PTIMER5

PTIMER4

PTIMER3

PTIMER2

PTIMER1

PTIMER0

—

U2CTS

U2RTS

—

UARTs

—

DMA Timers

TRST

TCLK

TMS

TDI

TDO

—

U2CTS QSPI_CS2 I

U2RTS QSPI_CS3 O

DREQ2

DACK2

DT2OUT

—

DREQ1

DACK1

DREQ0

DACK0

DT1OUT

—

BDM/JTAG

—

— — O

—

136

135

133

134

—

77:74

H14

G14

P10

M10

N10

M12, N12, P12,

L11

M11, N11, P11,

L10

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Design Recommendations

Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2 Dir.

MCF5270

MCF5271

160 QFP

MCF5270

MCF5271

196 MAPBGA

TEST

PLL_TEST

—

Test

—

Power Supplies

I 19

—

VDDPLL

VSSPLL

OVDD

VSS

—

I 87

M13

L14

I 1, 18, 32, 41, 55,

69, 81, 94, 105,

114, 128, 138,

145

E5, E7, E10, F7,

F9, G6, G8, H7,

H8, H9, J6, J8,

J10, K5, K6, K8

17, 31, 40, 54,

67, 80, 88, 93,

104, 113, 127,

137, 144, 160

A1, A14, E6, E9,

F6, F8, F10, G7,

G9, H6, J5, J7,

J9, K7, P1, P14

VDD — — — I 16, 53, 103 D6, F11, G4, L4

Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.

5 Design Recommendations

5.1 Layout

• Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF5271.

• See application note AN1259, System Design and Layout Techniques for Noise Reduction in

Processor-Based Systems.

• Match the PC layout trace width and routing to match trace length to operating frequency and board impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the

PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace and separation. Clocks get extra separation and more precise balancing.

5.2 Power Supply

• 33

μF, 0.1 μF, and 0.01 μF across each power supply

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Design Recommendations

5.2.1 Supply Voltage Sequencing and Separation Cautions

Figure 2

shows situations in sequencing the I/O V

(OV

), PLL V

DDPLL

is specified relative to V

), and Core V

DD,

DDPLL 3.3V

2.5V

1.5V

Supplies Stable

Time

Notes:

VDD should not exceed OVDD or VDDPLL by more than 0.4 V

at any time, including power-up.

Recommended that VDD should track OVDD/VDDPLL up to

0.9 V, then separate for completion of ramps.

Input voltage must not be greater than the supply voltage (OVDD,

VDD, or VDDPLL) by more than 0.5 V at any time, including during power-up.

Use 1 ms or slower rise time for all supplies.

Figure 2. Supply Voltage Sequencing and Separation Cautions

5.2.1.1

Power Up Sequence

If OV

is powered up with V connected to the OV

at 0 V, then the sense circuits in the I/O pads cause all pad output drivers

to be in a high impedance state. There is no limit on how long after OV

powers up before V

must power up. V

should not lead the OV

or V

DDPLL

by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1

μs to avoid turning on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1 ms or slower rise time for all supplies.

2. V

and OV

DDPLL

should track up to 0.9 V, then separate for the completion of ramps with

going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.

5.2.1.2

Power Down Sequence

If V

is powered down first, then sense circuits in the I/O pads cause all output drivers to be in a high impedance state. There is no limit on how long after V

powers down before OV

DDPLL

must power down. V

should not lag OV

or V

DDPLL

going low by more than 0.4 V during power down or there

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Design Recommendations will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop V

to 0 V.

2. Drop OV

DDPLL

supplies.

5.3 Decoupling

• Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of the package.

• 0.1

μF and 0.01 μF at each supply input

5.4 Buffering

• Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses

when excessive loading is expected. See Section 7, “Electrical Characteristics

.”

5.5 Pull-up Recommendations

• Use external pull-up resistors on unused inputs. See pin table.

5.6 Clocking Recommendations

• Use a multi-layer board with a separate ground plane.

• Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator pins) as possible.

• Do not run a high frequency trace around crystal circuit.

• Ensure that the ground for the bypass capacitors is connected to a solid ground trace.

• Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents in the vicinity of the crystal.

• Tie the ground pin to the most solid ground in the system.

• Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable.

• Tie XTAL to ground when an external oscillator is clocking the device.

5.7 Interface Recommendations

5.7.1 SDRAM Controller

5.7.1.1

SDRAM Controller Signals in Synchronous Mode

Table 3

shows the behavior of SDRAM signals in synchronous mode.

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Design Recommendations

Table 3. Synchronous DRAM Signal Connections

Signal Description

SD_SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM

SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SD_CS[1:0], which should not be interfaced to the SDRAM SD_SRAS signals.

SD_SCAS Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled

SD_SCAS on the SDRAM.

DRAMW DRAM read/write. Asserted for write operations and negated for read operations.

SD_CS[1:0] Row address strobe. Select each memory block of SDRAMs connected to the MCF5271. One

SD_CS signal selects one SDRAM block and connects to the corresponding CS signals.

SD_CKE

BS[3:0]

CLKOUT

Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of

SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode.

SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SD_CKE to provide command-bit functionality.

Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the

SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.

Bus clock output. Connects to the CLK input of SDRAMs.

5.7.1.2

Address Multiplexing

See the SDRAM controller module chapter in the MCF5271 Reference Manual for details on address multiplexing.

5.7.2 Ethernet PHY Transceiver Connection

The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10

Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard defines and the FEC module supports 18 signals. These are shown in

Table 4 .

Table 4. MII Mode

Signal Description

Transmit clock

Transmit enable

Transmit data

Transmit error

Collision

Carrier sense

Receive clock

Receive enable

Receive data

MCF5271 Pin

ETXCLK

ETXEN

ETXD[3:0]

ETXER

ECOL

ECRS

ERXCLK

ERXDV

ERXD[3:0]

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Mechanicals/Pinouts and Part Numbers

Table 4. MII Mode (continued)

Signal Description

Receive error

Management channel clock

Management channel serial data

MCF5271 Pin

ERXER

EMDC

EMDIO

The serial mode interface operates in what is generally referred to as AMD mode. The MCF5271 configuration for seven-wire serial mode connections to the external transceiver are shown in

Table 5

Table 5. Seven-Wire Mode Configuration

Signal Description

Transmit clock

Transmit enable

Transmit data

Collision

Receive clock

Receive enable

Receive data

Unused, configure as PB14

Unused input, tie to ground

Unused, configure as PB[13:11]

Unused output, ignore

Unused, configure as PB[10:8]

Unused, configure as PB15

Input after reset, connect to ground

MCF5271 Pin

ETXCLK

ETXEN

ETXD[0]

ECOL

ERXCLK

ERXDV

ERXD[0]

ERXER

ECRS

ERXD[3:1]

ETXER

ETXD[3:1]

EMDC

EMDIO

Refer to the M5271EVB evaluation board user’s manual for an example of how to connect an external

PHY. Schematics for this board are accessible at the MCF5271 site by navigating to: http://www.freescale.com/coldfire .

5.7.3 BDM

Use the BDM interface as shown in the M5271EVB evaluation board user’s manual. The schematics for this board are accessible at the Freescale website at: http://www.freescale.com/coldfire .

6 Mechanicals/Pinouts and Part Numbers

This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5271 devices. See Table 4 for a list the signal names and pin locations for each device.

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Mechanicals/Pinouts and Part Numbers

6.1 Pinout—196 MAPBGA

The following figure shows a pinout of the MCF5270/71CVMxxx package.

1 2 3 4 8 9 10

VSS ETXCLK ETXD3 ETXD2

5 6 7

QSPI_

DOUT

QSPI_CS0 U2RXD U2TXD CS3 CS6

CS4

A20

A17

VSS A

B ERXD0 ERXER ETXER ETXD0 QSPI_DIN BS3 QSPI_CS1 U1CTS CS7 CS1 A23 A19 A16 A15 B

C ERXD2 ERXD1 ETXEN ETXD1 QSCK BS2 BS0 RTS1 CS2 CS5

D ERXCLK ERXDV ERXD3 EMDC EMDIO

Core

VDD_4

BS1 U1RXD1 U1TXD CS0

E ECRS ECOL NC TIN0 VDD VSS VDD SD_CKE VSS

F U0TXD U0RXD

D31

D29

J D25

U0CTS DTOUT0 TEST VSS

D30

D28

U0RTS

Core

VDD_1

D27 D26

CLK

MOD1

CLK

MOD0

VDD

VSS

D24 D23 D22 VSS VDD

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

A22

A21

VDD A9

VSS

Core

VDD_3

NC A2

VDD

I2C_SCL

A18

A12

TIP

I2C_SDA

A14

A11

R/W

A13

A10

DTOUT3 G

DTIN3

TEA

K D21

L D17

M D15

N D14

P VSS

D20

D16

D13

D12

D11

D19 D18

D10

Core

VDD_2

VDD

VDD VSS

DTIN1 IRQ5

VDD JTAG_EN RCON SD_ RAS SD_ CAS SD_ WE CLKOUT K

IRQ1 DTOUT2 PST0 DDATA0 SD_ CS1 SD_ CS0 VSSPLL L

D6 D2 DTOUT1 IRQ6 IRQ2 DTIN2 TDI/DSI PST3 DDATA3 VDDPLL EXTAL M

D5 D1 OE IRQ7 IRQ3

TRST/

DSCLK

TDO/DSO PST2

D0 TSIZ1 TSIZ0 IRQ4

TCLK/

PSTCLK

TMS/

BKPT

10 5 6 7 8

Figure 3. MCF5270/71CVMxxx Pinout (196 MAPBGA)

PST1

DDATA2 RESET XTAL N

DDATA1 RSTOUT VSS P

12 13 14

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Mechanicals/Pinouts and Part Numbers

6.2 Package Dimensions—196 MAPBGA

Figure 4

shows MCF5270/71CVMxxx package dimensions.

13X e

TOL

Laser mark for pin 1 identification in this area

14 13 12 11 10 9

NOTES:

Dimensions are in millimeters.

Interpret dimensions and tolerances per ASME Y14.5M, 1994.

Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z.

Datum Z (seating plane) is defined by the spherical crowns of the solder balls.

Parallelism measurement shall exclude any effect of mark on top surface of package.

13X e

5 4 3 2 1

Millimeters

DIM

Min Max

A2 b

1.25

0.27

1.16 REF

0.45

1.60

0.47

0.55

15.00 BSC

Metalized mark for pin 1 identification in this area

A2 e

1.00 BSC

0.50 BSC

Z 4 0.10 Z

196X

Detail K

Rotated 90

Clockwise

0.20 Z

196X b

0.15

Z X Y

0.08 Z

View M-M

Figure 4. 196 MAPBGA Package Dimensions (Case No. 1128A-01)

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

6.3 Pinout—160 QFP

Figure 5

shows a pinout of the MCF5271CABxxx package.

Mechanicals/Pinouts and Part Numbers

U0TXD

U0RTS

Core VDD_1

VSS

O-VDD

TEST

CLKMOD1

CLKMOD0

DATA31

DATA30

DATA29

DATA28

O-VDD

ERXD0

ERXD1

ERXD2

ERXD3

ERXDV

ERXCLK

ECRS

ECOL

U0TIN

U0TOUT

U0CTS

U0RXD

DATA27

DATA26

DATA25

DATA24

DATA23

VSS

O-VDD

DATA22

DATA21

DATA20

DATA19

DATA18

DATA17

DATA16

VSS

MCF5271

A17

A16

A15

A14

A13

A12

O-VDD

VSS

A11

A10

O-VDD

VSS

Core_Vdd_3

R/W

O-VDD

VSS

SD_WE

SD_SCAS

SD_SRAS

CLKOUT

VSS

VDDPLL

EXTAL

XTAL

VSSPLL

RESET

RSTOUT

O-VDD

104

103

102

101

100

112

111

110

109

108

107

106

105

121 120

119

118

117

116

115

114

113

Figure 5. MCF5270/71CABxxx Pinout (160 QFP)

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Mechanicals/Pinouts and Part Numbers

6.4 Package Dimensions—160 QFP

Figure 6

shows MCF5270/71CAB80 package dimensions.

Y L

–A–, –B–, –D–

–A– –B–

B B

DETAIL A

–C–

–H–

0.110 (0.004)

0.20 (0.008) M C

0.20 (0.008)

A-B

A-B S

S D S

D S

DETAIL C

BASE

METAL

DETAIL C

–H–

0.13 (0.005) M C A-B S D S

SECTION B–B

TOP &

BOTTOM

NOTES

1. DIMENSIONING AND TOLERINCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER

3. DATUM PLAN -H- IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD WHERE

THE LEAD EXITS THE PLASTIC BODY AT THE

BOTTOM OF THE PARTING LINE.

4. DATUMS -A-, -B-, AND -D- TO BE DETERMINED AT

DATUM PLANE -H-.

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE -C-.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25

(0.010) PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE DETERMINED

AT DATUM PLANE -H-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT.

Case 864A-03

Figure 6. 160 QFP Package Dimensions

MILLIMETERS INCHES

DIM MIN

27.90

0.22

3.20

MAX

28.10

0.38

3.50

MIN

1.098

27.90

28.10

1.098

1.106

3.85

0.132 1.106

0.009

MAX

1.106

0.015

0.126

0.138

0.22

0.33

0.009

0.013

0.65 BSC

0.25

0.11

0.35

0.23

0.026 REF

0.010

0.014

0.004

0.009

0.70

0.90

25.35 BSC

0.11

0.19

0.028

0.035

0.998 REF

0.004

0.007

0.325 BSC

0.013 REF

0.13

0.30

0.005 0.012

31.00

31.40

1.220

1.236

0.13

—

0.005

—

31.00

31.40

1.220

1.236

0.4

— 0.016

—

1.60 REF

1.33 REF

0.063 REF

0.052 REF

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

6.5 Ordering Information

Table 6. Orderable Part Numbers

Freescale Part

Number

MCF5270AB100

MCF5270CAB100

MCF5270VM100

MCF5270CVM150

MCF5271CAB100

MCF5271CVM100

MCF5271CVM150

Description

MCF5270 RISC Microprocessor

MCF5271 RISC Microprocessor

Package Speed

160 QFP

100MHz

196 MAPBGA 100MHz

196 MAPBGA 150MHz

160 QFP 100MHz

196 MAPBGA 100MHz

196 MAPBGA 150MHz

Yes

Lead-Free?

Temperature

to +70

-40

to +85

to +70

-40

to +85

-40

to +85

-40

to +85

-40

to +85

7 Electrical Characteristics

This chapter contains electrical specification tables and reference timing diagrams for the MCF5271 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5271.

NOTE

The parameters specified in this processor document supersede any values found in the module specifications.

7.1 Maximum Ratings

Table 7. Absolute Maximum Ratings

1, 2

Rating Symbol Value Unit

Core Supply Voltage

Pad Supply Voltage

PLL Supply Voltage

Digital Input Voltage

DDPLL

– 0.5 to +2.0

– 0.3 to +4.0

– 0.3 to + 4.0

Instantaneous Maximum Current

Single pin limit (applies to all pins)

3,4,5

25 mA

Operating Temperature Range (Packaged) T

- T

)

– 40 to 85

Storage Temperature Range T stg

– 65 to 150

Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum

Ratings are stress ratings only, and functional operation at the maxima is not guaranteed.

Continued operation at these levels may affect device reliability or cause permanent damage to the device.

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either V

or OV

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.

All functional non-supply pins are internally clamped to V

and OV

Power supply must maintain regulation within operating OV

range during instantaneous and operating maximum current conditions. If positive injection current (V in

> OV

) is greater than I

, the injection current may flow out of OV

DD and could result in external power supply going out of regulation. Insure external OV

load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power

(ex; no clock).Power supply must maintain regulation within operating OV

range during instantaneous and operating maximum current conditions.

7.2 Thermal Characteristics

The below table lists thermal resistance values.

Table 8. Thermal Characteristics

Characteristic Symbol

196

MAPBGA

160QFP Unit

Junction to ambient, natural convection Four layer board (2s2p)

JMA

1,2

1,2 °

C / W

Junction to ambient (@200 ft/min)

Junction to board

Junction to case

Junction to top of package

Four layer board (2s2p)

JMA

Ψ jt

1,2

1,5

1,2

1,5

C / W

Maximum operating junction temperature T j

104 105 o

JMA

and

Ψ jt

parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.

Motorola recommends the use of

JmA

and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices.

Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the

Ψ jt

EIA/JESD Standard 51-2.

parameter, the device power dissipation, and the method described in

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8.

Board temperature is measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.

The average chip-junction temperature (T

) in

°C can be obtained from:

= T

(

× Θ

JMA

)

(1)

Where:

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

= Ambient Temperature,

°C

JMA

= Package Thermal Resistance, Junction-to-Ambient,

°C/W

= P

INT

+ P

I/O

INT

= I

× V

, Watts - Chip Internal Power

I/O

= Power Dissipation on Input and Output Pins — User Determined

For most applications P

I/O

< P

INT

and can be ignored. An approximate relationship between P

D and T

(if P

I/O

is neglected) is:

= K

÷ (

+ 273

°C )

(2)

Solving equations 1 and 2 for K gives:

K = P

× (T

+ 273

°C) + Θ

JMA

× P

(3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring P

(at equilibrium) for a known T

. Using this value of K, the values of P

can be obtained by solving equations (1) and (2) iteratively for any value of T

and

7.3 DC Electrical Specifications

Table 9. DC Electrical Specifications

Characteristic

Core Supply Voltage

Pad Supply Voltage

PLL Supply Voltage

Input High Voltage

Input Low Voltage

Input Hysteresis

Input Leakage Current

V in

= V

or V

, Input-only pins

High Impedance (Off-State) Leakage Current

V in

= V

or V

, All input/output and output pins

Output High Voltage (All input/output and all output pins)

= –5.0 mA

Output Low Voltage (All input/output and all output pins)

= 5.0mA

Weak Internal Pull Up Device Current, tested at V

Max.

Input Capacitance

All input-only pins

All input/output (three-state) pins

Symbol

DDPLL

HYS

I in

Min

1.4

3.0

0.7

– 0.3

0.06

–1.0

APU

C in

–1.0

- 0.5

—

–10

—

Typical

—

Max

1.6

3.6

3.65

0.35

—

1.0

Unit

V mV

—

1.0

—

0.5

– 130

A pF

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

Table 9. DC Electrical Specifications

(continued)

Characteristic

Load Capacitance

Low drive strength

High drive strength

Core Operating Supply Current

Master Mode

Symbol

Min Typical

—

Max

Unit pF pF

— 135 150 mA

Pad Operating Supply Current

Master Mode

Low Power Modes

DC Injection Current

3, 6, 7, 8

NEGCLAMP

– 0.3 V, V

POSCLAMP

= V

+ 0.3

Single Pin Limit

Total processor Limit, Includes sum of all stressed pins

—

–1.0

–10

100

TBD

—

1.0

10 mA

A mA mA

Refer to Table 10 for additional PLL specifications.

Refer to the MCF5271 signals section for pins having weak internal pull-up devices.

This parameter is characterized before qualification rather than 100% tested.

pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive strength and termination. See High Speed Signal Propagation:

Advanced Black Magic by Howard W. Johnson for design guidelines.

Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load.

All functional non-supply pins are internally clamped to V

and their respective V

Power supply must maintain regulation within operating V

range during instantaneous and operating maximum current conditions. If positive injection current (V in

> V

) is greater than I

, the injection current may flow out of V

DD and could result in external power supply going out of regulation. Insure external V

load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not present during the power-up sequence until the PLL has attained lock.

7.4 Oscillator and PLLMRFM Electrical Characteristics

Table 10. HiP7 PLLMRFM Electrical Specifications

Num Characteristic Symbol

Min.

Value

Max.

Value

PLL Reference Frequency Range

Crystal reference

External reference

1:1 mode (NOTE: f sys/2

= 2

f ref_1:1

)

Core frequency

CLKOUT Frequency

External reference

On-Chip PLL Frequency

Loss of Reference Frequency

3, 5

Self Clocked Mode Frequency

4, 5

Crystal Start-up Time

5, 6 f ref_crystal f ref_ext f ref_1:1 f sys f sys/2

24 f ref

32 f

LOR

100 f

SCM

10.25

t cst

—

150

1000

15.25

Unit

MHz

MHz kHz

MHz ms

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 10. HiP7 PLLMRFM Electrical Specifications

(continued)

Num Characteristic Symbol

Min.

Value

Max.

Value

Unit

XTAL Load Capacitance

PLL Lock Time

5, 7,13

Power-up To Lock Time

5, 6,8

With Crystal Reference (includes 5 time)

Without Crystal Reference

9 t lpll t lplk

—

750 pF

μ s

—

750 ms

μ s

9 1:1 Mode Clock Skew (between CLKOUT and EXTAL)

Duty Cycle of reference

5 t skew

–1 1 ns

Frequency un-LOCK Range

Frequency LOCK Range

CLKOUT Period Jitter,

5, 6, 8,11, 12

Measured at f sys/2

Max

Peak-to-peak Jitter (Clock edge to clock edge)

Long Term Jitter (Averaged over 2 ms interval) f

C f t dc

–3.8

LCK jitter

–1.7

—

4.1

2.0

5.0

.01

% f

% sys/2 sys/2

14 Frequency Modulation Range Limit

13,14

(f sys/2

Max must not be exceeded)

C mod

0.8

2.2

%f sys/2

15 ICO Frequency. f ico

= f ref

(MFD+2)

15 f ico

48 150 MHz

All values given are initial design targets and subject to change.

All internal registers retain data at 0 Hz.

“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f

LOR

with default MFD/RFD settings.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Proper PC board layout procedures must be followed to achieve specifications.

This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR).

Assuming a reference is available at power up, lock time is measured from the time V

and V

DDSYN are valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the

10 crystal start up time must be added to the PLL lock time to determine the total start-up time.

t lpll

= (64

5 + 5

) T ref

, where T ref

= 1/F ref_crystal

= 1/F ref_ext

= 1/F ref_1:1

, and

= 1.57x10

-6

2(MFD +

2).

PLL is operating in 1:1 PLL mode.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys/2

. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via V

DDSYN

and V

SSSYN

and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval.

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of

Cjitter+Cmod.

Modulation percentage applies over an interval of 10

μ s, or equivalently the modulation rate is 100KHz.

Modulation rate selected must not result in f sys/2

value greater than the f sys/2

maximum specified value. f

Modulation range determined by hardware design.

sys/2

= f ico

/ (2

RFD

)

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

7.5 External Interface Timing Characteristics

Table 11

lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the CLKOUT output.

All other timing relationships can be derived from these values.

Table 11. Processor Bus Input Timing Specifications

Characteristic

Symbol Min Max Unit Name freq

System bus frequency

CLKOUT period f sys/2 t cyc

—

1/75

B1a Control input valid to CLKOUT high

B1b BKPT valid to CLKOUT high

B2a

B2b

CLKOUT high to control inputs invalid

Control Inputs

CLKOUT high to asynchronous control input BKPT invalid

3 t

CVCH t

BKVCH t

CHCII t

BKNCH

—

Data Inputs

Data input (D[31:0]) valid to CLKOUT high

CLKOUT high to data input (D[31:0]) invalid t

DIVCH t

CHDII

—

Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line environment..

TEA and TA pins are being referred to as control inputs.

Refer to figure A-19.

MHz ns ns ns ns ns ns ns

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Timings listed in

Table 11

are shown in Figure 7 .

* The timings are also valid for inputs sampled on the negative clock edge.

CLKOUT(75MHz)

1.5V

SETUP

HOLD

Input Setup And Hold Invalid 1.5V Valid 1.5V

Invalid trise

Input Rise Time

Input Fall Time

V h

= V

V l

= V

V h

= V

V l

= V

IL tfall

CLKOUT B4

Inputs

Figure 7. General Input Timing Requirements

7.6 Processor Bus Output Timing Specifications

Table 12

lists processor bus output timings.

Table 12. External Bus Output Timing Specifications

Name Characteristic Symbol Min

Control Outputs

B6a CLKOUT high to chip selects valid

1 t

CHCV

—

B6b CLKOUT high to byte enables (BS[3:0]) valid

2 t

CHBV

—

B6c CLKOUT high to output enable (OE) valid

3 t

CHOV

—

B7a

CLKOUT high to control output (BS[3:0], OE) invalid

CLKOUT high to chip selects invalid

Max

0.5t

CYC

0.5t

CYC

+5 t

CHCOI t

CHCI

0.5t

CYC

+1.5

0.5t

CYC

+1.5

0.5t

CYC

—

Unit ns ns ns ns ns

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

Table 12. External Bus Output Timing Specifications (continued)

Characteristic Symbol Min Max Name

Address and Attribute Outputs

CLKOUT high to address (A[23:0]) and control (TS,

TSIZ[1:0], TIP, R/W) valid

CLKOUT high to address (A[23:0]) and control (TS,

TSIZ[1:0], TIP, R/W) invalid t

CHAV t

CHAI

Data Outputs

B11

B12

CLKOUT high to data output (D[31:0]) valid

CLKOUT high to data output (D[31:0]) invalid t

CHDOV t

CHDOI

B13 CLKOUT high to data output (D[31:0]) high impedance t

CHDOZ

CS transitions after the falling edge of CLKOUT.

BS transitions after the falling edge of CLKOUT.

OE transitions after the falling edge of CLKOUT.

—

1.5

—

1.5

—

Unit ns ns ns ns ns

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Read/write bus timings listed in Table 12 are shown in

Figure 8 ,

Figure 9

, and

Figure 10

S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5

CLKOUT

CSn

B6a

B7a

B6a

B7a

A[23:0]

TSIZ[1:0]

B8 B9

TS B9

TIP B8

B6c B0

R/W

(H)

B6b

BS[3:0]

B11 B12

D[31:0]

B13

TA (H)

TEA (H)

Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

Figure 9

shows a bus cycle terminated by TA showing timings listed in

Table 12 .

S0 S1 S2 S3 S4 S5

CLKOUT

B6a

B7a

CSn

B8 B9

A[23:0]

TSIZ[1:0]

TS B9

TIP

B6c

OE B7

R/W (H)

B6b

BS[3:0]

D[31:0]

B2a

TEA (H)

B1a

Figure 9. SRAM Read Bus Cycle Terminated by TA

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Figure 10

shows an SRAM bus cycle terminated by TEA showing timings listed in

Table 12 .

S0 S1 S2 S3 S4 S5 S0 S1

CLKOUT

B6a

B7a

CSn

B8 B9

A[23:0]

TSIZ[1:0]

TS B9

TIP

B6c

R/W (H)

B6b

BS[3:0]

D[31:0]

TA (H)

TEA

B1a

B2a

Figure 10. SRAM Read Bus Cycle Terminated by TEA

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

Figure 11 shows an SDRAM read cycle.

0 1 2 3 4

SD_CKE

A[23:0]

Row

SD_SRAS

SD_CAS

5 6

SDWE

7 8 9 10 11 12 13 14 15

Column

D[31:0]

RAS[1:0]

CAS[3:0]

ACTV

DACR[CASL] = 2

NOP READ NOP NOP

Figure 11. SDRAM Read Cycle

Table 13. SDRAM Timing

NUM Characteristic

D1 CLKOUT high to SDRAM address valid

D2 CLKOUT high to SDRAM control valid

D3 CLKOUT high to SDRAM address invalid

D4 CLKOUT high to SDRAM control invalid

D5 SDRAM data valid to CLKOUT high

D6 CLKOUT high to SDRAM data invalid

CLKOUT high to SDRAM data valid

CLKOUT high to SDRAM data invalid

D7 and D8 are for write cycles only.

Symbol t

CHDAV t

CHDCV t

CHDAI t

CHDCI t

DDVCH t

CHDDI t

CHDDVW t

CHDDIW

PALL

Min

1.5

—

1.5

—

1.5

Max

—

Unit ns ns ns ns ns ns ns ns

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Figure 12

shows an SDRAM write cycle.

0 1 2 3 4 5 6 7 8 9 10 11 12

SD_CKE

A[23:0]

Row

Column

SD_SRAS

SD_SCAS

SD_WE

D[31:0]

RAS[1:0]

CAS[3:0]

ACTV

DACR[CASL] = 2

NOP WRITE NOP

Figure 12. SDRAM Write Cycle

PALL

7.7 General Purpose I/O Timing

Table 14. GPIO Timing

NUM Characteristic

G1 CLKOUT High to GPIO Output Valid

G2 CLKOUT High to GPIO Output Invalid

G3 GPIO Input Valid to CLKOUT High

G4 CLKOUT High to GPIO Input Invalid

GPIO pins include: INT, UART, Timer, DREQn and DACKn pins.

Symbol t

CHPOV t

CHPOI t

PVCH t

CHPI

Min

—

1.5

Max

—

Unit ns ns ns ns

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

CLKOUT

G1 G2

GPIO Outputs

G3 G4

GPIO Inputs

Figure 13. GPIO Timing

7.8 Reset and Configuration Override Timing

NUM

Table 15. Reset and Configuration Override Timing

= 2.7 to 3.6 V, V

= 0 V, T

= T

to T

)

Characteristic Symbol Min Max Unit

RESET Input valid to CLKOUT High

CLKOUT High to RESET Input invalid

R3 RESET Input valid Time

CLKOUT High to RSTOUT Valid t

RVCH t

CHRI t

RIVT t

CHROV

1.5

—

10 t ns ns

CYC ns

RSTOUT valid to Config. Overrides valid

Configuration Override Setup Time to RSTOUT invalid t

ROVCV t

COS

—

— ns t

CYC

Configuration Override Hold Time after RSTOUT invalid

RSTOUT invalid to Configuration Override High Impedance t t

COH

ROICZ

—

1 ns t

CYC

All AC timing is shown with respect to 50% V

levels unless otherwise noted.

During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.

CLKOUT

R1 R2

RESET

RSTOUT

Configuration Overrides*:

(RCON, Override pins])

Figure 14. RESET and Configuration Override Timing

Refer to the chip configuration module (CCM) chapter in the device’s reference manual for more information.

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

7.9 I

C Input/Output Timing Specifications

Table 16

lists specifications for the I

C input timing parameters shown in

Figure 15

Table 16. I

C Input Timing Specifications between I2C_SCL and I2C_SDA

Num Characteristic

I1 Start condition hold time

I2 Clock low period

I3 I2C_SCL/I2C_SDA rise time (V

= 0.5 V to V

= 2.4 V)

I4 Data hold time

I5 I2C_SCL/I2C_SDA fall time (V

= 2.4 V to V

= 0.5 V)

I6 Clock high time

I7 Data setup time

I8 Start condition setup time (for repeated start condition only)

I9 Stop condition setup time

Min

—

Max

—

Table 17

lists specifications for the I

C output timing parameters shown in

Figure 15

Table 17. I

C Output Timing Specifications between I2C_SCL and I2C_SDA

Units ms t cyc ns t cyc t cyc t cyc t cyc ms ns

Num Characteristic Min Max Units

Start condition hold time 6 — t cyc

Clock low period

I2C_SCL/I2C_SDA rise time (V

= 0.5 V to V

= 2.4 V)

Data hold time

I2C_SCL/I2C_SDA fall time (V

= 2.4 V to V

= 0.5 V)

Clock high time

Data setup time

Start condition setup time (for repeated start condition only)

Stop condition setup time

—

— t cyc

µs t cyc ns t cyc t cyc t cyc t cyc

Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in

Table 17

. The

C interface is designed to scale the actual data transition time to move it to the middle of the

I2C_SCL low period. The actual position is affected by the prescale and division values programmed

into the IFDR; however, the numbers given in Table 17 are minimum values.

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values.

Specified at a nominal 50-pF load.

Figure 15

shows timing for the values in

Table 16 and Table 17

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

I2C_SCL

I2 I6 I5

I1 I4 I8 I9

I2C_SDA

Figure 15. I

C Input/Output Timings

7.10 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

7.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and

ERXCLK)

The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the ERXCLK frequency.

Table 18

lists MII receive channel timings.

Table 18. MII Receive Signal Timing

Num

Characteristic

ERXD[3:0], ERXDV, ERXER to ERXCLK setup

ERXCLK to ERXD[3:0], ERXDV, ERXER hold

ERXCLK pulse width high

ERXCLK pulse width low

Min

35%

Max

—

65%

Unit ns ns

ERXCLK period

Figure 16 shows MII receive signal timings listed in Table 18

ERXCLK (input)

ERXD[3:0] (inputs)

ERXDV

ERXER

M1 M2

Figure 16. MII Receive Signal Timing Diagram

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

7.10.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)

Table 19

lists MII transmit channel timings.

The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the ETXCLK frequency.

Table 19. MII Transmit Signal Timing

Num

Characteristic

ETXCLK to ETXD[3:0], ETXEN, ETXER invalid

ETXCLK to ETXD[3:0], ETXEN, ETXER valid

ETXCLK pulse width high

ETXCLK pulse width low

Min

—

35%

Max

—

65%

Unit ns ns

ETXCLK period

Figure 17 shows MII transmit signal timings listed in Table 19

ETXCLK (input)

ETXD[3:0] (outputs)

ETXEN

ETXER

Figure 17. MII Transmit Signal Timing Diagram

7.10.3 MII Async Inputs Signal Timing (ECRS and ECOL)

Table 20

lists MII asynchronous inputs signal timing.

Table 20. MII Async Inputs Signal Timing

Num

Characteristic

ECRS, ECOL minimum pulse width

Min

1.5

Max

—

Figure 18 shows MII asynchronous input timings listed in Table 20

ECRS, ECOL

Figure 18. MII Async Inputs Timing Diagram

Unit

ETXCLK period

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

7.10.4 MII Serial Management Channel Timing (EMDIO and EMDC)

Table 21

lists MII serial management channel timings. The FEC functions correctly with a maximum

MDC frequency of 2.5 MHz.

Table 21. MII Serial Management Channel Timing

Num Characteristic

M10 EMDC falling edge to EMDIO output invalid (minimum propagation delay)

M11 EMDC falling edge to EMDIO output valid (max prop delay)

M12 EMDIO (input) to EMDC rising edge setup

M13 EMDIO (input) to EMDC rising edge hold

M14 EMDC pulse width high

M15 EMDC pulse width low

Min Max Unit

—

— ns ns ns

0 — ns

40% 60% MDC period

Figure 19

shows MII serial management channel timings listed in

Table 21 .

M14

M15

EMDC (output)

M10

EMDIO (output)

M11

EMDIO (input)

M12

M13

Figure 19. MII Serial Management Channel Timing Diagram

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

7.11 32-Bit Timer Module AC Timing Specifications

Table 22

lists timer module AC timings.

Table 22. Timer Module AC Timing Specifications

0–66 MHz

Name Characteristic

DT0IN / DT1IN / DT2IN / DT3IN cycle time

DT0IN / DT1IN / DT2IN / DT3IN pulse width

Min

Max

—

Unit t

CYC t

CYC

7.12 QSPI Electrical Specifications

Table 23

lists QSPI timings.

Table 23. QSPI Modules AC Timing Specifications

Name Characteristic Min

QS1 QSPI_CS[1:0] to QSPI_CLK

QS2 QSPI_CLK high to QSPI_DOUT valid.

QS3 QSPI_CLK high to QSPI_DOUT invalid. (Output hold)

QS4 QSPI_DIN to QSPI_CLK (Input setup)

QS5 QSPI_DIN to QSPI_CLK (Input hold)

—

The values in Table 23 correspond to Figure 20

Max

510

—

Unit tcyc ns ns ns ns

QS1

QSPI_CS[1:0]

QSPI_CLK

QSPI_DOUT

QSPI_DIN

QS3

QS2

QS4 QS5

Figure 20. QSPI Timing

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

7.13 JTAG and Boundary Scan Timing

Table 24. JTAG and Boundary Scan Timing

Num Characteristics

Symbol Min

J10

J11

TCLK Frequency of Operation

TCLK Cycle Period

TCLK Clock Pulse Width

TCLK Rise and Fall Times

Boundary Scan Input Data Setup Time to TCLK Rise

Boundary Scan Input Data Hold Time after TCLK Rise

TCLK Low to Boundary Scan Output Data Valid

TCLK Low to Boundary Scan Output High Z

TMS, TDI Input Data Setup Time to TCLK Rise

TMS, TDI Input Data Hold Time after TCLK Rise

TCLK Low to TDO Data Valid f

JCYC t

JCW t

JCRF t

BSDST t

BSDHT t

BSDV t

BSDZ t

TAPBST t

TAPBHT t

TDODV

J12

J13

TCLK Low to TDO High Z

TRST Assert Time t

TDODZ t

TRSTAT

100

J14 TRST Setup Time (Negation) to TCLK High t

TRSTST

JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

Max

—

1/4

—

Unit ns ns ns ns f sys/2 t

CYC ns ns ns ns ns ns ns ns

TCLK

(input)

Figure 21. Test Clock Input Timing

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

TCLK

TDI

TMS

TDO

TCLK

Data Inputs

Data Outputs

Input Data Valid

Output Data Valid

Figure 22. Boundary Scan (JTAG) Timing

J10 J9

Input Data Valid

J11

Output Data Valid

J12

J11

Output Data Valid

Figure 23. Test Access Port Timing

TCLK

TRST

J14

J13

Figure 24. TRST Timing

Electrical Characteristics

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Electrical Characteristics

7.14 Debug AC Timing Specifications

Table 25

lists specifications for the debug AC timing parameters shown in Figure 26 .

Table 25. Debug AC Timing Specification

150 MHz

Num Characteristic Units

Min Max

DE0 PSTCLK cycle time

DE1 PST valid to PSTCLK high

DE2 PSTCLK high to PST invalid

—

1.5

0.5

—

— t cyc ns ns

DE3 DSCLK cycle time

DE4

DE5

DE6

DSI valid to DSCLK high

DSCLK high to DSO invalid

BKPT input data setup time to CLKOUT rise

—

— t cyc t cyc t cyc ns

DE7 CLKOUT high to BKPT high Z 0 10 ns

DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT.

Figure 25

shows real-time trace timing for the values in

Table 25 .

PSTCLK

DE0

DE1 DE2

PST[3:0]

DDATA[3:0]

Figure 25. Real-Time Trace AC Timing

Figure 26

shows BDM serial port AC timing for the values in

Table 25 .

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Documentation

CLKOUT

BKPT

DE6

DE7

DE5

DSCLK

DE3

DSI

DSO

Current

DE4

Past

Figure 26. BDM Serial Port AC Timing

Current

8 Documentation

Documentation regarding the MCF5271 and their development support tools is available from a local

Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale web address at http://www.freescale.com

/coldfire .

9 Document Revision History

The below table provides a revision history for this document.

Table 26. MCF5271EC Revision History

Substantive Change(s) Rev. No.

0 Initial release

1.1

1.2

• Fixed several clock values.

• Updated Signal List table

• Removed duplicate information in the module description sections. The information is all in the

Signals Description Table.

• Removed detailed signal description section. This information can be found in the

MCF5271RM Chapter 2.

• Removed detailed feature list. This information can be found in the MCF5271RM Chapter 1.

• Changed instances of Motorola to Freescale

• Added values for ‘Maximum operating junction temperature’ in

Table 8 .

• Added typical values for ‘Core operating supply current (master mode)’ in

Table 9 .

• Added typical values for ‘Pad operating supply current (master mode)’ in Table 9

• Removed unnecessary PLL specifications, #6-9, in

Table 10 .

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Document Revision History

Rev. No.

1.3

1.4

Table 26. MCF5271EC Revision History (continued)

Substantive Change(s)

• Device is now available in 150 MHz versions. Updated specs where necessary to reflect this improvement.

• Added 2 new part numbers to Table 6 : MCF5270CVM150 and MCF5271CVM150.

• Removed features list. This information can be found in the MCF5271RM.

• Removed SDRAM address multiplexing section. This information can be found in the

MCF5271RM.

• Added

Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions .”

• Updated 196MAPBGA package dimensions, Figure 4 .

• Table 2 : Changed SD_CKE pin location from 139 to “—” for the 160QFP device.

• Table 2 : Changed QSPI_CS1 pin location from “—” to 139 for the 160QFP device.

• Table 2 : Changed DT3IN pin’s alternate 2 function from “—” to QSPI_CS2.

• Table 2 : Changed DT3OUT pin’s alternate 2 function from “—” to QSPI_CS3.

•

Figure 5

: Changed pin 139 label from “SD_CKE/QSPI_CS1” to “QSPI_CS1/SD_CKE”.

• Removed second sentence from Section 7.10.1, “MII Receive Signal Timing (ERXD[3:0],

ERXDV, ERXER, and ERXCLK) ,”

and Section 7.10.2, “MII Transmit Signal Timing (ETXD[3:0],

ETXEN, ETXER, ETXCLK) ,”

regarding no minimum frequency requirement for TXCLK.

• Removed third and fourth paragraphs from

Section 7.10.2, “MII Transmit Signal Timing

(ETXD[3:0], ETXEN, ETXER, ETXCLK) ,”

as this feature is not supported on this device.

•

Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions

” changed PLLV

DDPLL

to match rest of document.

•

Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions

” Changed V

DDPLL voltage level from 1.5V to 3.3V throughout section.

•

Section 5.2.1.1, “Power Up Sequence

” first bullet, changed “Use 1 µs” to “Use 1 ms”.

• Corrected position of spec D5 in Figure 11

•

Figure 3

: Corrected M4 ball location from DATA5 to DATA6, changed DATAn labels to Dn for consistency

•

Table 14

: Added DACKn and DREQn to footnote.

•

Table 9 , added PLL supply voltage row

• Added part number MCF5270CAB100 in

Table 6

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

Freescale Semiconductor

Document Revision History

Freescale Semiconductor

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4

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Document Number: MCF5271EC

Rev. 4

08/2009

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