NXP MCF527X ColdFire® V2 Integrated Microprocessor Reference Manual
Reklama
Reklama
MCF5271 Reference Manual
Devices Supported:
MCF5270
MCF5271
Document Number: MCF5271RM
Rev. 2
07/2006
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MCF5271RM
Rev. 2
07/2006
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
General Purpose I/O Module
Interrupt Controller Modules
DMA Controller Module
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Synchronous DRAM Controller
Fast Ethernet Controller (FEC)
Watchdog Timer Module
Programmable Interrupt Timers (PITs)
DMA Timers
Queued Serial Peripheral Interface (QSPI)
UART Modules
I
2
C interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Debug Support
Register Memory Map Quick Reference
Index
27
28
29
30
A
IND
21
22
23
24
25
26
16
17
18
19
20
9
10
11
12
13
14
15
6
7
8
1
2
3
4
5
15
16
17
18
19
20
21
10
11
12
13
14
7
8
9
5
6
3
4
1
2
22
23
24
25
26
27
28
29
30
A
IND
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
General Purpose I/O Module
Interrupt Controller Modules
DMA Controller Module
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Synchronous DRAM Controller
Fast Ethernet Controller (FEC)
Watchdog Timer Module
Programmable Interrupt Timers (PITs)
DMA Timers
Queued Serial Peripheral Interface (QSPI)
UART Modules
I
2
C interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Debug Support
Register Memory Map Quick Reference
Index
Contents
1.3.8
Paragraph
Number
Title
Page
Number
2
C Bus...................................................................................................................... 1-10
2.3.1
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor v
Contents
3.7.2
Paragraph
Number
Title
Page
Number
Supervisor/User Stack Pointers (A7 and OTHER_A7).......................................... 3-7
SRAM Base Address Register (RAMBAR)........................................................... 3-8
MCF5271 Reference Manual, Rev. 2 vi Freescale Semiconductor
Contents
4.5.3
Paragraph
Number
Title
Page
Number
Enhanced Multiply-Accumulate Unit (EMAC)
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2 vii
Contents
7.1.3.4
Paragraph
Number
Title
Page
Number
MCF5271 Reference Manual, Rev. 2 viii Freescale Semiconductor
Contents
Paragraph
Number
7.2.5
Title
Page
Number
8.2
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor ix
Contents
Paragraph
Number
Title
Page
Number
Low-Power Interrupt Control Register (LPICR).................................................... 8-2
UART Modules (UART0, UART1, and UART2) ................................................. 8-7
Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3) ............................ 8-10
Summary of Peripheral State During Low-Power Modes ........................................ 8-11
9.1.3
Chip Configuration Module (CCM)
MCF5271 Reference Manual, Rev. 2 x Freescale Semiconductor
Contents
Paragraph
Number
9.2.1
Title
Page
Number
10.2.2
10.4.2
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xi
Contents
Paragraph
Number
Title
Page
Number
Internal Peripheral System Base Address Register (IPSBAR)............................. 11-3
Memory Base Address Register (RAMBAR) ...................................................... 11-4
Peripheral Access Control Registers (PACR0–PACR8).................................... 11-15
Grouped Peripheral Access Control Register (GPACR) .................................... 11-17
12.1.2
MCF5271 Reference Manual, Rev. 2 xii Freescale Semiconductor
Contents
13.2.1.6
13.2.1.7
Paragraph
Number
12.3.1.1
12.3.1.2
12.3.1.3
12.3.1.4
12.3.1.5
12.3.1.7
Title
Page
Number
Port Pin Data/Set Data Registers (PPDSDR_x).................................................. 12-14
Port Clear Output Data Registers (PCLRR_x) ................................................... 12-16
Timer Pin Assignment Registers (PAR_TIMERH & PAR_TIMERL).............. 12-26
Interrupt Force Registers (INTFRCH, INTFRCL)............................................... 13-9
Interrupt Acknowledge Level and Priority Register (IACKLPR)...................... 13-11
Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)......... 13-14
14.1.1
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xiii
Contents
Paragraph
Number
Title
Page
Number
Byte Count Registers (BCR0–BCR3) and DMA Status Registers (DSR0–DSR3) . 14-8
Transfer Requests (Cycle-Steal and Continuous Modes) ....................................... 14-14
Programming the DMA Controller Module ....................................................... 14-15
External Request and Acknowledge Operation.................................................. 14-16
EPORT Pin Assignment Register (EPPAR)......................................................... 15-3
EPORT Data Direction Register (EPDDR).......................................................... 15-4
16.1
MCF5271 Reference Manual, Rev. 2 xiv Freescale Semiconductor
Contents
17.7
Paragraph
Number
16.2.1
16.2.2
16.2.3
Title
Page
Number
Chip Select Address Registers (CSAR0–CSAR7) ............................................... 16-7
Chip Select Mask Registers (CSMR0–CSMR7) .................................................. 16-8
Chip Select Control Registers (CSCR0–CSCR7)................................................. 16-9
External Interface Module (EIM)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xv
Contents
Paragraph
Number
Title
Page
Number
Synchronous DRAM Controller Module
DRAM Address and Control Registers (DACR0/DACR1) ..................................... 18-6
DRAM Controller Mask Registers (DMR0/DMR1) ................................................ 18-9
19.1.5.2
Fast Ethernet Controller (FEC)
MCF5271 Reference Manual, Rev. 2 xvi Freescale Semiconductor
Contents
Paragraph
Number
19.3.5
Title
Page
Number
Receive Descriptor Active Register (RDAR)..................................................... 19-11
Transmit Descriptor Active Register (TDAR) ................................................... 19-12
MII Management Frame Register (MMFR) ....................................................... 19-14
Descriptor Individual Upper Address Register (IAUR) ................................... 19-22
Descriptor Individual Lower Address Register (IALR) .................................... 19-23
Descriptor Group Upper Address Register (GAUR)......................................... 19-23
Descriptor Group Lower Address Register (GALR)......................................... 19-24
FIFO Transmit FIFO Watermark Register (TFWR) ......................................... 19-25
Receive Descriptor Ring Start Register (ERDSR) ............................................ 19-27
Transmit Buffer Descriptor Ring Start Registers (ETSDR) .............................. 19-27
Driver/DMA Operation with Buffer Descriptors ............................................... 19-29
User Initialization (Prior to Setting ECR[ETHER_EN])........................................ 19-35
User Initialization (After Asserting ECR[ETHER_EN]) ....................................... 19-37
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xvii
Contents
21.2.1.1
21.2.1.2
21.2.1.3
21.3.2
Paragraph
Number
Title
Page
Number
Programmable Interrupt Timer Modules (PIT0–PIT3)
MCF5271 Reference Manual, Rev. 2 xviii Freescale Semiconductor
Contents
23.2.2
22.2.6
22.2.7
22.2.8
22.2.9
22.2.10
22.2.11
Paragraph
Number
Title
Page
Number
DMA Timer Extended Mode Registers (DTXMRn)................................................ 22-5
Queued Serial Peripheral Interface (QSPI) Module
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xix
Contents
24.3.1
24.3.2
24.3.3
24.3.4
24.3.5
24.3.6
24.3.7
24.3.8
24.3.9
24.3.10
24.3.11
24.3.12
24.3.13
24.4.2.2
Paragraph
Number
Title
Page
Number
Command RAM Registers (QCR0–QCR15).......................................................... 23-14
UART Interrupt Status/Mask Registers (UISRn/UIMRn)...................................... 24-14
UART Baud Rate Generator Registers (UBG1n/UBG2n) ..................................... 24-15
UART Output Port Command Registers (UOP1n/UOP0n) ................................... 24-16
MCF5271 Reference Manual, Rev. 2 xx Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
25.5.1
25.5.2
25.5.3
25.4
25.5.4
25.5.5
25.6
25.6.6
2
C Interface
C System Configuration............................................................................................. 25-3
2
C Address Register (I2ADR)................................................................................. 25-8
2
2
C Frequency Divider Register (I2FDR)................................................................. 25-9
2
2
C Control Register (I2CR)................................................................................... 25-10
C Status Register (I2SR)...................................................................................... 25-11
C Data I/O Register (I2DR) ................................................................................. 25-12
C Programming Examples ....................................................................................... 25-13
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xxi
Contents
26.4.5
26.2.8
26.2.10
Paragraph
Number
Title
Page
Number
Message Digest Hardware Accelerator (MDHA)
MDHA Interrupt Status & Mask Registers (MDISR and MDIMR) ...................... 26-10
MDHA Message Data Size Register (MDMDS).................................................... 26-12
Performing a HMAC Operation Without the MACFULL Bit ............................... 26-15
Performing a MAC Operation With the MACFULL Bit ....................................... 26-18
MCF5271 Reference Manual, Rev. 2 xxii Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
28.2.1.11
Symmetric Key Hardware Accelerator (SKHA)
Data Ecryption Standard (DES & 3DES) Algorithm ........................................... 28-1
Advanced Encryption Standard (AES) Algorithm ............................................... 28-3
Cipher Block Chaining (CBC) Cipher Mode ....................................................... 28-4
SKHA Command Register (SKCMR).................................................................. 28-9
SKHA Error Status Mask Register (SKESMR) ................................................. 28-12
SKHA Key Data Registers (SKKDRn) ............................................................. 28-14
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xxiii
Contents
29.2.3
29.4.3.2
Paragraph
Number
28.2.1.12
Title
Page
Number
IEEE 1149.1 Test Access Port (JTAG)
Test Reset/Development Serial Clock (TRST/DSCLK) .......................................... 29-4
Test Data Output/Development Serial Output (TDO/DSO)..................................... 29-5
MCF5271 Reference Manual, Rev. 2 xxiv Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
30.7.2
Data Breakpoint/Mask Registers (DBR, DBMR)................................................... 30-12
Program Counter Breakpoint/Mask Registers (PBR, PBMR)................................ 30-13
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xxv
Contents
Paragraph
Number
Title
Page
Number
A.1
Register Memory Map Quick Reference
xxvi
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
About This Book
The primary objective of this reference manual is to define the functionality of the MCF5271 processor for use by software and hardware developers. In addition, this manual supports the
MCF5270. This book is written from the perspective of the MCF5271, and unless otherwise noted, the information applies also to the MCF5270. The MCF5270 has the same functionality as the
MCF5271 and any differences in data regarding bus timing, signal behavior, and AC, DC, and thermal characteristics are in the hardware specifications. Please refer to
to see a summary of the differences.
The information in this book is subject to change without notice, as described in the disclaimers on the title page. As with any technical documentation, it is the reader’s responsibility to be sure he is using the most recent version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at http://www.freescale.com/coldfire .
Audience
This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MCF5271. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the ColdFire
®
architecture.
Organization
Following is a summary and brief description of the major sections of this manual:
•
,” includes general descriptions of the modules and features incorporated in the MCF5271, focussing in particular on new features.
•
Chapter 2, “Signal Descriptions ,” describes MCF5271 signals. It includes a listing of
signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used.
•
Chapter 3, “ColdFire Core ,” provides an overview of the microprocessor core of the
MCF5271. The chapter describes the organization of the Version 2 (V2) ColdFire processor core and an overview of the program-visible registers (the programming model) as they are implemented on the MCF5271.
•
Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC) ,” describes the MCF5271
multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The EMAC is integrated into the operand execution pipeline (OEP).
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xxvii
About This Book
•
,” describes the MCF5271 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures.
•
Chapter 6, “Static RAM (SRAM) ,” describes the MCF5271 on-chip static RAM (SRAM)
implementation. It covers general operations, configuration, and initialization. It also provides information and examples of how to minimize power consumption when using the
SRAM.
•
Chapter 7, “Clock Module ,” describes the MCF5271’s different clocking methods. It also
describes clock module operation in low power modes.
•
Chapter 8, “Power Management ,” describes the low power operation of the MCF5271 and
peripheral behavior in low power modes.
•
Chapter 9, “Chip Configuration Module (CCM)
,” describes CCM functionality, detailing the two modes of chip operation: master mode and single-chip mode. This chapter provides a description of signals used by the CCM and a programming model.
•
Chapter 10, “Reset Controller Module
,” describes the operation of the reset controller module, detailing the different types of reset that can occur.
•
Chapter 11, “System Control Module (SCM) ,” describes the functionality of the SCM,
which provides the programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit Core Watchdog Timer (CWT), and the system control registers and logic.
•
Chapter 12, “General Purpose I/O Module ,” describes the operation and programming
model of the general purpose I/O (GPIO) ports on the MCF5271.
•
Chapter 13, “Interrupt Controller Modules
,” describes operation of the interrupt controller portion of the SCM. Includes descriptions of the registers in the interrupt controller memory map and the interrupt priority scheme.
•
Chapter 14, “DMA Controller Module
,” describes the MCF5271 Direct Memory Access
(DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail.
•
Chapter 15, “Edge Port Module (EPORT) ,” describes EPORT module functionality,
including operation in low power mode.
•
Chapter 16, “Chip Select Module
,” describes the MCF5271 chip-select implementation, including the operation and programming model, which includes the chip-select address, mask, and control registers.
•
Chapter 17, “External Interface Module (EIM) ,” describes data-transfer operations, error
conditions, bus arbitration, and reset operations.
•
Chapter 18, “Synchronous DRAM Controller Module ,” describes the configuration and
operation of the SDRAM controller. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the
MCF5271 Reference Manual, Rev. 2 xxviii Freescale Semiconductor
Organization chapter describes the programming model and signal timing, as well as the command set required for synchronous operations.
•
Chapter 19, “Fast Ethernet Controller (FEC)
,” provides a feature-set overview, a functional block diagram, and transceiver connection information for both MII (Media Independent
Interface) and 7-wire serial interfaces. It also provides describes operation and the programming model.
•
Chapter 20, “Watchdog Timer Module ,” describes Watchdog timer functionality, including
operation in low power mode.
•
Chapter 21, “Programmable Interrupt Timer Modules (PIT0–PIT3)
,” describes the functionality of the four PIT timers, including operation in low power mode.
•
Chapter 22, “DMA Timers (DTIM0–DTIM3) ,” describes the configuration and operation
of the four DMA timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or triggers. This chapter also provides programming examples.
•
Chapter 23, “Queued Serial Peripheral Interface (QSPI) Module ,” provides a feature-set
overview and a description of operation, including details of the QSPI’s internal storage organization. The chapter concludes with the programming model and a timing diagram.
•
,” describes the use of the universal asynchronous receiver/transmitters (UARTs) implemented on the MCF5271 and includes programming examples.
•
Chapter 25, “I2C Interface ,” describes the MCF5271 I
clock synchronization, and I
2
2
C module, including I
2
C protocol,
C programming model registers. It also provides extensive programming examples.
•
Chapter 26, “Message Digest Hardware Accelerator (MDHA) ,” describes implementation
of two of the world’s most popular cryptographic hash functions: SHA-1 and MD5.
Accelerators for either algorithm separately have been designed, however the MDHA combines similar functions of the two algorithms into one small, optimized area of silicon on the MCF5271 device.
•
Chapter 27, “Random Number Generator (RNG),”
describes the 32-bit Random Number
Generator (RNG), including a programming model, functional description, and application information.
•
Chapter 28, “Symmetric Key Hardware Accelerator (SKHA),” describes the cryptographic
hardware coprocessor designed to implement two widely used symmetric key block cipher algorithms, AES and DES.
•
Chapter 29, “IEEE 1149.1 Test Access Port (JTAG) ,” describes configuration and
operation of the MCF5271 Joint Test Action Group (JTAG) implementation. It describes those items required by the IEEE 1149.1 standard and provides additional information specific to the MCF5271. For internal details and sample applications, see the IEEE 1149.1 document.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xxix
About This Book
•
,” describes the Revision A enhanced hardware debug support in the MCF5271.
This manual includes the following appendix:
•
Appendix A, “Register Memory Map Quick Reference ,” provides the entire address-map
for MCF5271 memory-mapped registers.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture.
Hardware Specification
The MCF5271EC document contains the mechanical and electrical specifications of the
MCF5271. It can be found at http://www.freescale.com/coldfire .
General Information
The following documentation provides useful information about the ColdFire architecture and computer architecture in general:
• ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD)
• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray,
Ross Bannatyne, Joseph D. Greenfield
• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David A. Patterson.
• Computer Organization and Design: The Hardware/Software Interface, Second Edition,
David A. Patterson and John L. Hennessy.
ColdFire Documentation
ColdFire documentation is available from the sources listed on the back cover of this manual.
• Reference manuals (formerly called user’s manuals)—These books provide details about individual ColdFire implementations and are intended to be used in conjunction with The
ColdFire Programmers Reference Manual.
• Addenda/errata to reference manuals—Because some processors have follow-on parts, an addendum is provided that describes the additional features and functionality changes.
Also, if mistakes are found within a reference manual, an errata document will be issued before the next published release of the reference manual. These addenda/errata are intended for use with the corresponding reference manuals.
MCF5271 Reference Manual, Rev. 2 xxx Freescale Semiconductor
Conventions
• Hardware specifications—Hardware specifications provide specific data regarding bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations.
• Product briefs—Each device has a product brief that provides an overview of its features.
This document is roughly equivalent to the overview (Chapter 1) of an implementation’s reference manual.
• Application notes—These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors.
Additional literature is published as new processors become available. For a current list of
ColdFire documentation, refer to http://www.freescale.com/coldfire .
Conventions
|
~
& x n
This document uses the following notational conventions:
MNEMONICS In text, instruction mnemonics are shown in uppercase. mnemonics italics
0x0
0b0
REG[FIELD]
In code and tables, instruction mnemonics are shown in lowercase.
Italics indicate variable command parameters.
Book titles in text are set in italics.
Prefix to denote hexadecimal number
Prefix to denote binary number
Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifies the base address field in the RAM base address register.
A 4-bit data unit nibble byte word longword
An 8-bit data unit
A 16-bit data unit
A 32-bit data unit
1
In some contexts, such as signal encodings, x indicates a don’t care.
Used to express an undefined numerical value
NOT logical operator
AND logical operator
OR logical operator
1. The only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xxxi
About This Book
Acronyms and Abbreviations
lists acronyms and abbreviations used in this document.
Table i. Acronyms and Abbreviated Terms
Term lsb
MAC
MBAR
MSB msb
Mux
NOP
OEP
PC
IEEE
IFP
IPL
JEDEC
JTAG
LIFO
LRU
LSB
ADC
ALU
BDM
BIST
BSDL
CODEC
DAC
DMA
DSP
EA
FIFO
GPIO
I
2
C
Meaning
Analog-to-digital conversion
Arithmetic logic unit
Background debug mode
Built-in self test
Boundary-scan description language
Code/decode
Digital-to-analog conversion
Direct memory access
Digital signal processing
Effective address
First-in, first-out
General-purpose I/O
Inter-integrated circuit
Institute for Electrical and Electronics Engineers
Instruction fetch pipeline
Interrupt priority level
Joint Electron Device Engineering Council
Joint Test Action Group
Last-in, first-out
Least recently used
Least-significant byte
Least-significant bit
Multiply accumulate unit, also Media access controller
Memory base address register
Most-significant byte
Most-significant bit
Multiplex
No operation
Operand execution pipeline
Program counter
MCF5271 Reference Manual, Rev. 2 xxxii Freescale Semiconductor
Term
Rx
SIM
SOF
TAP
TTL
Tx
UART
USB
PCLK
PLIC
PLL
POR
PQFP
PWM
QSPI
RISC
Table i. Acronyms and Abbreviated Terms (Continued)
Meaning
Processor clock
Physical layer interface controller
Phase-locked loop
Power-on reset
Plastic quad flat pack
Pulse width modulation
Queued serial peripheral interface
Reduced instruction set computing
Receive
System integration module
Start of frame
Test access port
Transistor transistor logic
Transmit
Universal asynchronous/synchronous receiver transmitter
Universal serial bus
Terminology Conventions
Terminology Conventions
Table ii shows terminology conventions used throughout this document.
Table ii. Notational Conventions
Instruction cc
An
Ay,Ax
Dn
Dy,Dx
Rc
Operand Syntax
Opcode Wildcard
Logical condition (example: NE for not equal)
Register Specifications
Any address register n (example: A3 is address register 3)
Source and destination address registers, respectively
Any data register n (example: D5 is data register 5)
Source and destination data registers, respectively
Any control register (example VBR is the vector base register)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xxxiii
About This Book
Table ii. Notational Conventions (Continued)
Instruction
Rm
Rn
Rw
Ry,Rx
Xi
ACC
CCR
MACSR
MASK
PC
SR
Operand Syntax
MAC registers (ACC, MAC, MASK)
Any address or data register
Destination register w (used for MAC instructions only)
Any source and destination registers, respectively
Index register i (can be an address or data register: Ai, Di)
Register Names
MAC accumulator register
Condition code register (lower byte of SR)
MAC status register
MAC mask register
Program counter
Status register
Port Name
DDATA
PST
Debug data port
Processor status port
#<data>
<ea>
Miscellaneous Operands
Immediate data following the 16-bit operation word of the instruction
Effective address
<ea>y,<ea>x Source and destination effective addresses, respectively
<label>
<list>
<shift>
<size>
Assembly language program label
List of registers for MOVEM instruction (example: D3–D0)
Shift operation: shift left (<<), shift right (>>)
Operand data size: byte (B), word (W), longword (L) bc dc ic
# <vector>
<>
<xxx> dn
SF
Both instruction and data caches
Data cache
Instruction cache
Identifies the 4-bit vector number for trap instructions identifies an indirect data address referencing memory identifies an absolute address referencing memory
Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
MCF5271 Reference Manual, Rev. 2 xxxiv Freescale Semiconductor
Terminology Conventions
Table ii. Notational Conventions (Continued)
Instruction Operand Syntax
Operations
{}
() d n
Address
Bit lsb
LSB
LSW msb
MSB
MSW
^
|
~
& x
/
+
–
Arithmetic addition or postincrement indicator
Arithmetic subtraction or predecrement indicator
Arithmetic multiplication
Arithmetic division
Invert; operand is logically complemented
Logical AND
Logical OR
Logical exclusive OR
<<
If <condition> then
<operations> else
<operations>
Shift left (example: D0 << 3 is shift D0 left 3 bits)
>>
→
←→
Shift right (example: D0 >> 3 is shift D0 right 3 bits)
Source operand is moved to destination operand
Two operands are exchanged sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion
Test the condition. If true, the operations after ‘then’ are performed. If the condition is false and the optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example.
Subfields and Qualifiers
Optional operation
Identifies an indirect address
Displacement value, n-bits wide (example: d
16
is a 16-bit displacement)
Calculated effective address (pointer)
Bit selection (example: Bit 3 of D0)
Least significant bit (example: lsb of D0)
Least significant byte
Least significant word
Most significant bit
Most significant byte
Most significant word
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor xxxv
About This Book
Instruction
V
X
C
N
Z
Carry
Negative
Overflow
Extend
Zero
Table ii. Notational Conventions (Continued)
Operand Syntax
Condition Code Register Bit Names
Revision History
provides a revision history for this document.
Table iii. MCF5271RM Revision History
Location
—
—
—
—
Substantive Changes
Revision 0, 04/26/2004
Initial customer-release version.
Revision 1.0, 08/16/2004
Various updates and formatting changes.
Revision 1.1, 04/2005
Changes are noted in revision 1.3 or later of the MCF5271RMAD document.
Revision 2, 07/2006
Changes are noted in revision 1.6 or later of the MCF5271RMAD document.
xxxvi
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Chapter 1
Overview
The MCF5271 family is a highly integrated implementation of the ColdFire
®
family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent features and functions of the MCF5271 family. The MCF5271 family includes the MCF5271 and
MCF5270 microprocessors. The differences between these parts are summarized below in
Table 1-1 . This document is written from the perspective of the MCF5271 and unless otherwise
noted, the information applies also to the MCF5270.
The MCF5271 family delivers a new level of performance and integration on the popular version 2
ColdFire core with up to 144 (Dhrystone 2.1) MIPS at 150 MHz. Positioned for applications requiring a low cost, strong performance, 32-bit solution, the MCF5271 family features a 10/100
Ethernet MAC and optional hardware encryption to ensure the application can be connected and protected. In addition, the MCF5271 family features an Enhanced Multiply Accumulate Unit
(EMAC), large on-chip memory (64 Kbytes SRAM, 8 Kbytes configurable cache), and a 32-bit
SDR SDRAM memory controller.
To locate any published errata or updates for this document, refer to the ColdFire products website at http://www.freescale.com/coldfire .
1.1
MCF5271 Family Configurations
Table 1-1. MCF5271 Family Configurations
Module
ColdFire V2 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
System Clock
Performance (Dhrystone/2.1 MIPS)
Instruction/Data Cache
Static RAM (SRAM)
Interrupt Controllers (INTC)
Edge Port Module (EPORT)
External Interface Module (EIM)
4-channel Direct-Memory Access
(DMA)
SDRAM Controller
Fast Ethernet Controller (FEC)
Cryptography Hardware Accelerators
5270 x x x
—
5271 x x x
2 x up to 150 MHz up to 144
8 Kbytes
64 Kbytes x x
2 x x x x
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 1-1
Overview
Table 1-1. MCF5271 Family Configurations (Continued)
Module
Watchdog Timer (WDT)
Four Periodic Interrupt Timers (PIT)
32-bit DMA Timers
QSPI
UART(s)
I
2
C
General Purpose I/O Module (GPIO)
JTAG - IEEE 1149.1 Test Access Port
Package
5270 5271
4 x x x
4 x x x x x
3 x
3 x x x
160 QFP
196
MAPBGA
160 QFP
196
MAPBGA
1.2
Block Diagram
The superset device in the MCF5271 family comes in a 196 mold array process ball grid array
(MAPBGA) package.
shows a top-level block diagram of the MCF5271.
1-2
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
(To/From SRAM backdoor)
Arbiter INTC0 INTC1
EIM
CHIP
SELECTS
EBI
(To/From PADI)
FAST
ETHERNET
CONTROLLER
(FEC)
(To/From PADI)
(To/From
PADI)
4 CH DMA
DREQ[2:0]
DACK [2:0]
JTAG_EN
UART
0
UART
1
UART
2
I 2 C QSPI
DTIM
0
DTIM
1
DTIM
2
DTIM
3
SDRAMC
V2 ColdFire CPU
DIV EMAC
JTAG
TAP
Watchdog
Timer
64 Kbytes
SRAM
(8Kx16)x4
8 Kbytes
CACHE
(1Kx32)x2
(To/From Arbiter)
PORTS
(GPIO) CIM
Block Diagram
SDRAMC
QSPI
SDA
SCL
UnTXD
UnRXD
UnRTS
UnCTS
TnOUT
TnIN
FEC
D[31:0]
A[23:0]
R/W
CS[3:0]
TA
TSIZ[1:0]
TEA
BS[3:0]
SKHA
RNGA
MDHA
Cryptography
Modules
PLL
CLKGEN
(To/From INTC)
PIT0
Edge
Port
PIT1
Figure 1-1. MCF5271 Block Diagram
PIT2 PIT3
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 1-3
Overview
1.3
Features
1.3.1
Feature Overview
• Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data path on-chip
— Processor core runs at twice the internal bus frequency
— Sixteen general-purpose 32-bit data and address registers
— Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to support the user stack pointer register, and 4 new instructions for improved bit processing
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support
32-bit signal processing algorithms
— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with two user-visible hardware breakpoint registers (PC and address with optional data) that can be configured into a 1- or 2-level trigger
• On-chip memories
— 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC)
• Fast Ethernet Controller (FEC)
— 10 BaseT capability, half duplex or full duplex
— 100 BaseT capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
— Media independent interface (MII) to external transceiver (PHY)
• Three Universal Asynchronous Receiver Transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic
— Maskable interrupts
MCF5271 Reference Manual, Rev. 2
1-4 Freescale Semiconductor
Features
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (UnRTS) and clear-to-send (UnCTS) lines for two UARTs
— Transmit and receive FIFO buffers
• I 2 C Module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I 2 C bus
— Master or slave modes support multiple masters
— Automatic interrupt generation with programmable level
• Queued Serial Peripheral Interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable master bit rates
— Up to 16 pre-programmed transfers
• Four 32-bit DMA Timers
— 13-ns resolution at 75 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input-capture capability with programmable trigger edge on input pin
— Output-compare with programmable mode for the output pin
— Free run and restart modes
— Maskable interrupts on input capture or reference-compare
— DMA trigger capability on input capture or reference-compare
• Four Periodic Interrupt Timers (PITs)
— 16-bit counter
— Selectable as free running or count down
• Software Watchdog Timer
— 16-bit counter
— Low power mode support
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 1-5
Overview
• Phase Locked Loop (PLL)
— Crystal or external oscillator reference
— 8 to 25 MHz reference frequency for normal PLL mode
— 24 to 75 MHz oscillator reference frequency for 1:1 mode (input freq = core freq = 2 ×
CLKOUT)
— Separate clock output pins
• Interrupt Controllers (x2)
— Support for up to 110 interrupt sources per interrupt controller organized as follows:
– 103 fully-programmable interrupt sources
– 7 fixed-level interrupt sources
— Seven external interrupt signals
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
• DMA Controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16- and 32-bit data capability along with support for 16-byte (4 x 32-bit) burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable connections between the four DMA channels and the 14 DMA requesters in the UARTs (6), 32-bit timers (4), and external logic (4)
• External Bus Interface
— Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)
— SDRAM controller supports 8-, 16-, and 32-bit wide memory devices
— Support for n-1-1-1 burst fetches from page mode Flash
— Glueless interface to SRAM devices with or without byte strobe inputs
— Programmable wait state generator
— 32-bit bidirectional data bus
— 24-bit address bus
— Up to eight chip selects available
MCF5271 Reference Manual, Rev. 2
1-6 Freescale Semiconductor
Features
— Byte/write enables (byte strobes)
— Ability to boot from external memories that are 8,16, or 32 bits wide
• Chip Integration Module (CIM)
— System configuration during reset
— Selects one of four clock modes
— Sets boot device and its data port width
— Configures output pad drive strength
— Unique part identification number and part revision number
— Reset
– Separate reset in and reset out signals
– Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss of clock, PLL loss of lock
– Status flag indication of source of last reset
• General Purpose I/O interface
— Up to 142 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
1.3.2
V2 Core Overview
The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The
OEP includes two pipeline stages. The first stage decodes instructions and selects operands
(DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a separate user stack pointer register and four new instructions to assist in bit processing.
Additionally, the MCF5271 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands and a complete set of instructions to process these data types. The EMAC provides superb support for execution of DSP operations within the context of a single processor at a minimal hardware cost.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 1-7
Overview
1.3.3
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, users can access real-time trace and debug information. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface provided on the 683xx family of parts.
The on-chip breakpoint resources include a total of 8 programmable registers—a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), an address attribute register, a trigger definition register, and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU’s clock rate.
1.3.4
JTAG
The MCF5271 supports circuit board test strategies based on the Test Technology Committee of
IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 330-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic.
The MCF5271 implementation can do the following:
• Perform boundary-scan operations to test circuit board electrical continuity
• Sample MCF5271 system pins during operation and transparently shift out the result in the boundary scan register
• Bypass the MCF5271 for a given circuit board test by effectively reducing the boundary-scan register to a single bit
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
MCF5271 Reference Manual, Rev. 2
1-8 Freescale Semiconductor
Features
1.3.5
On-chip Memories
1.3.5.1
Cache
The 8-Kbyte cache can be configured into one of three possible organizations: an 8-Kbyte instruction cache, an 8-Kbyte data cache or a split 4-Kbyte instruction/4-Kbyte data cache. The configuration is software-programmable by control bits within the privileged Cache Configuration
Register (CACR). In all configurations, the cache is a direct-mapped single-cycle memory, organized as 512 lines, each containing 16 bytes of data. The memories consist of a 512-entry tag array (containing addresses and control bits) and a 8-Kbyte data array, organized as 2048 x 32 bits.
If the desired address is mapped into the cache memory, the output of the data array is driven onto the ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped into the tag memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch.
The cache module includes a 16-byte line fill buffer used as temporary storage during miss processing. For all data cache configurations, the memory operates in write-through mode and all operand writes generate an external bus cycle.
1.3.5.2
SRAM
The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the system stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module.
The SRAM module is also accessible by the DMA and FEC non-core bus masters. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance. As an example, system performance can be increased significantly if
Ethernet packets are moved from the FEC into the SRAM (rather than external memory) prior to any processing.
1.3.6
Fast Ethernet Controller (FEC)
The MCF5271’s integrated Fast Ethernet Controller (FEC) performs the full set of IEEE
802.3/Ethernet CSMA/CD media access control and channel interface functions. The FEC supports connection and functionality for the 10/100 Mbps 802.3 media independent interface
(MII). It requires an external transceiver (PHY) to complete the interface to the media.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 1-9
Overview
1.3.7
UARTs
The MCF5271 contains three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an externally supplied clock.
They can use DMA requests on transmit-ready and receive-ready as well as interrupt requests for servicing. Flow control via UnCTS and UnRTS pins is provided on all three UARTS.
1.3.8
I
2
C Bus
The I 2 C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices.
1.3.9
QSPI
The queued serial peripheral interface module provides a high-speed synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, eliminating CPU intervention between transfers.
1.3.10 Cryptography
The superset device, MCF5271, incorporates small, fast, dedicated hardware accelerators for random number generation, message digest and hashing, and the DES, 3DES, and AES block cipher functions allowing for the implementation of common Internet security protocol cryptography operations with performance well in excess of software-only algorithms.
1.3.11 DMA Timers (DTIM0-DTIM3)
There are four independent, DMA-transfer-generating 32-bit timers (DTIM[3:0]) on the
MCF5271. Each timer module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference compare mode. By configuring the internal registers, each timer may be configured to assert an external signal, generate an interrupt on a particular event or cause a DMA transfer.
1.3.12 Periodic Interrupt Timers (PIT0-PIT3)
The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at regular intervals with minimal processor intervention. Each timer can either count down from the value written in its PIT modulus register, or it can be a free-running down-counter.
MCF5271 Reference Manual, Rev. 2
1-10 Freescale Semiconductor
Features
1.3.13 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.
1.3.14 Clock Module and Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity, the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD, VSS, OVDD, and OVSS.
1.3.15 Interrupt Controllers (INTC0, INTC1)
There are two interrupt controllers on the MCF5271, each of which can support up to 63 interrupt sources each for a total of 126. Each interrupt controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7] and priority within the level.
1.3.16 DMA Controller
The Direct Memory Access (DMA) Controller Module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module provides four channels
(DMA0-DMA3) that allow byte, word, longword or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit. Other sources include the DMA timer, external sources via the DREQ signal, and UARTs. The DMA controller supports dual address to off-chip or on-chip devices.
1.3.17 External Interface Module (EIM)
The external bus interface handles the transfer of information between the core and memory, peripherals, or other processing elements in the external address space. Features have been added to support external Flash modules, for secondary wait states on reads and writes, and a signal to support Active-Low Address Valid (a signal on most Flash memories).
Programmable chip-select outputs provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting address must be on a boundary that is a multiple of the block size. Each chip select can be configured to provide read and write enable signals suitable for use with most popular static RAMs
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 1-11
Overview and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for protection from read-only access.
1.3.18 SDRAM Controller
The SDRAM controller provides all required signals for glueless interfacing to a variety of
JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software configurable for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the address and data buses, SD_SRAS, SD_SCAS, SD_WE, SD_CS[1:0] and
SD_CKE are dedicated SDRAM signals.
1.3.19 Reset
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and keep track of what caused the last reset. The power management registers for the internal low-voltage detect (LVD) circuit are implemented in the reset module. There are six sources of reset:
• External
• Power-on reset (POR)
• Watchdog timer
• Phase locked-loop (PLL) loss of lock
• PLL loss of clock
• Software
External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also software-readable status flags indicating the cause of the last reset.
1.3.20 GPIO
Like the MC68332, unused bus interface and peripheral pins on the MCF5271 can be used as discrete general-purpose inputs and outputs. These are managed by a dedicated GPIO module that logically groups all pins into ports located within a contiguous block of memory-mapped control registers.
All of the pins associated with the external bus interface may be used for several different functions. Their primary function is to provide an external memory interface to access off-chip resources. When not used for this, all of the pins may be used as general-purpose digital I/O pins.
In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.
The digital I/O pins on the MCF5271 are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins.
MCF5271 Reference Manual, Rev. 2
1-12 Freescale Semiconductor
Documentation
1.4
Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the
Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com
/coldfire .
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
1-13
Overview
1-14
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Chapter 2
Signal Descriptions
2.1 Introduction
This chapter describes MCF5271 signals. It includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a
pull-up resistor should be used. Chapter 17, “External Interface Module (EIM)
,” describes how these signals interact.
NOTE
The terms ‘assertion’ and ‘negation’ are used to avoid confusion when dealing with a mixture of active-low and active-high signals. The term
‘asserted’ indicates that a signal is active, independent of the voltage level. The term ‘negated’ indicates that a signal is inactive.
Active-low signals, such as SD_SRAS and TA, are indicated with an overbar.
2.1.1 Overview
Figure 2-1 shows the block diagram of the MCF5271 with the signal interface.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
2-1
Signal Descriptions
RCON
CLKMOD0
CLKMOD1
RESET
RSTOUT
TEA
TA
TS
BS[3:0]
OE
TSIZ[1:0]
R/ W
TIP
D[31:0]
4
2
32
24
A[23:0]
Chip
Configuration
Reset
Controller
External
Interface
Module
ETXCLK
ETXEN
ECOL
ERXCLK
ERXDV
ECRS
ETXD[3:0]
ETXER
ERXD[301]
ERXER
EMDIO
EMDC
CS[7:0]
8 Chip
Selects
IRQ[7:1]
SD_CS[1:0]
SD_WE
SD_SRAS
SD_SCAS
SD_CKE
CLKOUT
EXTAL
XTAL
2
Edgeport
SDRAM
Controller
Clock Module
(PLL)
Interrupt
Controller 0
Interrupt
Controller 1
FEC
Ports
Module
QSPI
UART
Serial I/O
Modules
(UART0–
UART2)
JTAG
Port
TDO/DSO
TCLK/PSTCLK
TMS/ BKPT
TDI/DSI
TRST/DSCLK
JTAG_EN
Debug Module
ColdFire V2 Core
64K
SRAM
DIV EMAC
8-Kbyte
D-Cache/I-Cache
4
Test
Controller
DDATA[3:0]
DMA
Timer
Modules
(DTIM0–
DTIM3)
I
2
C
Module
Watchdog
Timer
Prog.
Interrupt
Timers
(PIT0–
PIT3)
2-2
Figure 2-1. MCF5271 Block Diagram with Signal Interfaces
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Signal Properties Summary
2.2 Signal Properties Summary
Table 2-14 lists the MCF5271 signals grouped by functionality.
NOTE
In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e.,
A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their
GPIO functionality.
Table 2-1. MCF5270 and MCF5271 Signal Information and Muxing
Signal Name GPIO
Alternate
1
Alternate
2
Dir.
1
MCF5270
MCF5271
160 QFP
MCF5270
MCF5271
196 MAPBGA
RESET
RSTOUT
—
—
—
—
Reset
—
—
Clock
I
O
83
82
N13
P13
EXTAL
XTAL
CLKOUT
—
—
—
—
—
—
—
—
—
—
Mode Selection
— I
I
O
O
86
85
89
M14
N14
K14
CLKMOD[1:0
]
RCON
A[23:21]
A[20:0]
— 20,21 G5,H5
—
PADDR[7:5]
—
— — I
External Memory Interface and Ports
79
CS[6:4]
—
—
—
K10
O 126, 125, 124 B11, C11, D11
O 123:115,
112:106, 102:98
A12, B12, C12,
A13, B13, B14,
C13, C14, D12,
D13, D14, E11,
E12, E13, E14,
F12, F13, F14,
G11, G12, G13
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 2-3
Signal Descriptions
Table 2-1. MCF5270 and MCF5271 Signal Information and Muxing (Continued)
Signal Name
D[31:16]
D[15:8]
D[7:0]
BS[3:0]
OE
TA
TEA
R/W
TSIZ1
TSIZ0
TS
TIP
CS[7:4]
GPIO
—
PDATAH[7:0]
PDATAL[7:0]
PBS[7:4]
PBUSCTL7
PBUSCTL6
PBUSCTL5
PBUSCTL4
PBUSCTL3
PBUSCTL2
PBUSCTL1
PBUSCTL0
PCS[7:4]
Alternate
1
Alternate
2
Dir.
1
—
—
—
—
—
—
O
O
O
CAS[3:0]
—
—
DREQ1
—
DACK1
DACK0
DACK2
DREQ0
—
—
—
—
—
—
—
—
—
—
Chip Selects
— O
O
O
O
O
O
I
I
O
O
MCF5270
MCF5271
160 QFP
MCF5270
MCF5271
196 MAPBGA
22:30, 33:39 G1, G2, H1, H2,
H3, H4, J1, J2,
J3, J4, K1, K2,
K3, K4, L1, L2
42:49 M1, N1, M2, N2,
P2, L3, M3, N3
50:52, 56:60 P3, M4, N4, P4,
L5, M5, N5, P5
143:140
62
96
—
95
—
—
97
—
B6, C6, D7, C7
N6
H11
J14
J13
P6
P7
H13
H12
—
132,131
B9, A10, C10,
A11
A9, C9 CS[3:2]
CS1
CS0
PCS[3:2] SD_CS[1:0
]
PCS1
—
—
—
—
—
—
SDRAM Controller
O
O
O
SD_WE
SD_SCAS
SD_SRAS
SD_CKE
PSDRAM5
PSDRAM4
PSDRAM3
PSDRAM2
SD_CS[1:0] PSDRAM[1:0
]
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
IRQ[7:3] PIRQ[7:3]
External Interrupts Port
— — I
130
129
92
91
90
139
—
IRQ7=63
IRQ4=64
B10
D10
K13
K12
K11
E8
L12, L13
N7, M7, L7, P8,
N8
MCF5271 Reference Manual, Rev. 2
2-4 Freescale Semiconductor
Signal Properties Summary
Table 2-1. MCF5270 and MCF5271 Signal Information and Muxing (Continued)
Signal Name GPIO
Alternate
1
Alternate
2
Dir.
1
MCF5270
MCF5271
160 QFP
—
65
MCF5270
MCF5271
196 MAPBGA
M8
L8
IRQ2
IRQ1
EMDC
EMDIO
ECOL
ECRS
ERXCLK
ERXDV
ERXD[3:0]
ERXER
ETXCLK
ETXEN
ETXER
ETXD[3:0]
I2C_SDA
I2C_SCL
PIRQ2
PIRQ1
DREQ2
—
PFECI2C3 I2C_SCL
PFECI2C2 I2C_SDA
—
—
—
—
—
—
—
—
—
—
PFECI2C1
PFECI2C0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FEC
—
—
—
—
I
2
C
U2TXD O
U2RXD I/O
—
— I
I
—
—
—
—
I
O
I
I
O
O
I
I
—
—
DMA
I/O
I/O
I
I
DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads. Please refer to the following pins for muxing:
TS and DT2OUT for DACK2, TSIZ1and DT1OUT for
DACK1, TSIZ0 and DT0OUT for DACK0, IRQ2 and DT2IN for DREQ2, TEA and DT1IN for DREQ1, and TIP and DT0IN for DREQ0.
QSPI
QSPI_CS1
QSPI_CS0
QSPI_CLK
QSPI_DIN
QSPI_DOUT
PQSPI4
PQSPI3
PQSPI2
PQSPI1
PQSPI0
SD_CKE
—
I2C_SCL
I2C_SDA
—
—
—
—
—
—
UARTs
O
I
O
O
O
7
6
5:2
159
151
150
9
8
158
157
156
155:152
—
—
—
—
146
147
148
149
D4
D5
E2
E1
D1
D2
D3, C1, C2, B1
B2
A2
C3
B3
A3, A4, C4, B4
J12
J11
—
B7
A6
C5
B5
A5
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 2-5
Signal Descriptions
Table 2-1. MCF5270 and MCF5271 Signal Information and Muxing (Continued)
Signal Name
DT3IN
DT3OUT
DT2IN
DT2OUT
DT1IN
DT1OUT
DT0IN
DT0OUT
U2TXD
U2RXD
U1CTS
U1RTS
U1TXD
U1RXD
U0CTS
U0RTS
U0TXD
U0RXD
DSCLK
PSTCLK
BKPT
DSI
DSO
JTAG_EN
DDATA[3:0]
PST[3:0]
GPIO
—
—
—
—
—
—
—
PTIMER7
PTIMER6
PTIMER5
PTIMER4
PTIMER3
PTIMER2
PTIMER1
PTIMER0
PUARTH1
PUARTH0
PUARTL7
PUARTL6
PUARTL5
PUARTL4
PUARTL3
PUARTL2
PUARTL1
PUARTL0
—
Alternate
1
Alternate
2
Dir.
1
—
—
U2CTS
U2RTS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA Timers
TRST
TCLK
TMS
TDI
TDO
—
—
U2CTS
U2RTS
DREQ2
DACK2
—
—
DT2OUT
—
DREQ1
DACK1
DREQ0
DACK0
DT1OUT
—
—
—
BDM/JTAG
2
—
—
—
—
—
—
—
I
O
O
I
O
I
I
O
O
I
I
O
I
O
I
O
I
O
O
I
O
O
I
O
O
— — O
72
78
—
70
68
71
73
61
—
10
11
—
—
66
—
MCF5270
MCF5271
160 QFP
133
134
12
15
—
—
136
135
14
13
77:74
N9
P9
P10
M10
N10
K9
M12, N12, P12,
L11
M11, N11, P11,
L10
L6
M6
E4
F4
H14
G14
M9
L9
MCF5270
MCF5271
196 MAPBGA
D9
D8
F3
G3
A8
A7
B8
C8
F1
F2
MCF5271 Reference Manual, Rev. 2
2-6 Freescale Semiconductor
Signal Primary Functions
Table 2-1. MCF5270 and MCF5271 Signal Information and Muxing (Continued)
Signal Name GPIO
Alternate
1
Alternate
2
Dir.
1
MCF5270
MCF5271
160 QFP
MCF5270
MCF5271
196 MAPBGA
TEST
PLL_TEST
—
—
—
—
Test
—
—
Power Supplies
I
I 19
—
F5
VDDPLL
VSSPLL
OVDD
—
—
—
—
—
—
—
—
—
I
I
I
87
84
M13
L14
1, 18, 32, 41,
55, 69, 81, 94,
105, 114, 128,
138, 145
E5, E7, E10,
F7, F9, G6, G8,
H7, H8, H9, J6,
J8, J10, K5, K6,
K8
VSS — — — I 17, 31, 40, 54,
67, 80, 88, 93,
104, 113, 127,
137, 144, 160
A1, A14, E6,
E9, F6, F8, F10,
G7, G9, H6, J5,
J7, J9, K7, P1,
P14
VDD — — — I 16, 53, 103 D6, F11, G4, L4
1
2
Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS,
PSDRAM.
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
2.3 Signal Primary Functions
2.3.1 Reset Signals
Table 2-2 describes signals that are used to either reset the chip or as a reset indication.
Table 2-2. Reset Signals
Signal Name
Reset In
Reset Out
Abbreviation
RESET
RSTOUT
Function
Primary reset input to the device. Asserting RESET immediately resets the CPU and peripherals.
Driven low for 128 CPU clocks when the soft reset bit of the system configuration register (SCR[SOFTRST]) is set. It is driven low for 32K
CPU clocks when the software watchdog timer times out or when a low input level is applied to RESET.
I/O
I
O
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 2-7
Signal Descriptions
2.3.2 PLL and Clock Signals
Table 2-3 describes signals that are used to support the on-chip clock generation circuitry.
Table 2-3. PLL and Clock Signals
Signal Name
External Clock In
Crystal
Clock Out
Abbreviation
EXTAL
XTAL
CLKOUT
Function
Always driven by an external clock input except when used as a connection to the external crystal when the internal oscillator circuit is used. The clock source is configured during reset by CLKMOD[1:0].
Used as a connection to the external crystal when the internal oscillator circuit is used to drive the crystal.
This output signal reflects one-half the internal system clock. (f sys/2
)
I/O
I
O
O
2.3.3 Mode Selection
Table 2-4 describes signals used in mode selection.
Table 2-4. Mode Selection Signals
Signal Name Abbreviation Function
Clock Mode Selection CLKMOD[1:0] Configure the clock mode after reset.
Reset Configuration RCON Indicates whether the external D[31:16] pin states affect chip configuration at reset.
I/O
I
I
2.3.4 External Memory Interface Signals
Table 2-5 describes signals that are used for doing transactions on the external bus.
Table 2-5. External Memory Interface Signals
Signal Name
Address Bus
Data Bus
Abbreviation
A[23:0]
D[31:0]
Function
The 24 dedicated address signals define the address of external byte, word, and longword accesses. These three-state outputs are the 24 lsbs of the internal 32-bit address bus and multiplexed with the
SDRAM controller row and column addresses.
These three-state bidirectional signals provide the general purpose data path between the processor and all other devices.
The D[15:0] pins can be configured as GPIO when using a 16-bit bus.
I/O
O
I/O
2-8
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Signal Primary Functions
Table 2-5. External Memory Interface Signals (Continued)
Signal Name
Byte Strobes
Output Enable
Abbreviation
BS[3:0]
Function
Define the flow of data on the data bus. During SRAM and peripheral accesses, these output signals indicate that data is to be latched or driven onto a byte of the data when driven low. The BS[3:0] signals are asserted only to the memory bytes used during a read or write access.
BS0 controls access to the least significant byte lane of data, and BS3 controls access to the most significant byte lane of data.
I/O
O
OE
Transfer Acknowledge TA
Transfer Error
Acknowledge
Read/Write
Transfer Size
Transfer Start
Transfer in Progress
Chip Selects
TEA
R/W
TSIZ[1:0]
TS
TIP
CS[7:0]
The BS[3:0] signals are asserted during accesses to on-chip peripherals but not to on-chip SRAM, or cache. During SDRAM accesses, these signals act as the CAS[3:0] signals, which indicate a byte transfers between SDRAM and the chip when driven high.
For SRAM or Flash devices, the BS[3:0] outputs should be connected to individual byte strobe signals.
For SDRAM devices, the BS[3:0] should be connected to individual
SDRAM DQM signals. Note that most SDRAMs associate DQM3 with the MSB, in which case BS3 should be connected to the SDRAM's
DQM3 input.
Indicates when an external device can drive data during external read cycles.
Indicates that the external data transfer is complete. During a read cycle, when the processor recognizes TA, it latches the data and then terminates the bus cycle. During a write cycle, when the processor recognizes TA, the bus cycle is terminated.
Indicates an error condition exists for the bus transfer. The bus cycle is terminated and the CPU begins execution of the access error exception.
Indicates the direction of the data transfer on the bus for SRAM (R/W) and SDRAM (SD_WE) accesses. A logic 1 indicates a read from a slave device and a logic 0 indicates a write to a slave device
When the device is in normal mode, static bus sizing lets the programmer change data bus width between 8, 16, and 32 bits for each chip select. The initial width for the bootstrap program chip select, CS0, is determined by the state of TSIZ[1:0]. The program should select bus widths for the other chip selects before accessing the associated memory space. These pins arecxvvvvvvvvvvvvvvvvv output pins.
Bus control output signal indicating the start of a transfer.
Bus control output signal indicating bus transfer in progress.
These output signals select external devices for external bus transactions. The CS[3:2] can also be configured to function as
SDRAM chip selects SD_CS[1:0].
O
I
I
O
O
O
O
O
2.3.5 SDRAM Controller Signals
Table 2-6 describes signals that are used for SDRAM accesses.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 2-9
Signal Descriptions
Table 2-6. SDRAM Controller Signals
Signal Name Abbreviation Function
SDRAM Synchronous
Row Address Strobe
SD_SRAS
SDRAM Synchronous
Column Address Strobe
SD_SCAS
SDRAM synchronous row address strobe.
SDRAM synchronous column address strobe.
SDRAM Write Enable SD_WE SDRAM write enable.
SDRAM Chip Selects SD_CS[1:0] SDRAM chip select signals.
SDRAM Clock Enable SD_CKE SDRAM clock enable.
I/O
O
O
2.3.6 External Interrupt Signals
Table 2-7 describes the external interrupt signals.
Table 2-7. External Interrupt Signals
Signal Name
External Interrupts
Abbreviation
IRQ[7:1]
Function
External interrupt sources. IRQ2 can also be configured as DMA request signal DREQ2.
I/O
I
2.3.7 Ethernet Module (FEC) Signals
The following signals are used by the Ethernet module for data and clock signals.
Table 2-8. Ethernet Module (FEC) Signals
Signal Name
Management Data
Management Data
Clock
Transmit Clock
Transmit Enable
Transmit Data 0
Collision
Abbreviation
EMDIO
EMDC
ETXCLK
ETXEN
ETXD0
ECOL
Function
Transfers control information between the external PHY and the media-access controller. Data is synchronous to EMDC. Applies to MII mode operation. This signal is an input after reset. When the FEC is operated in 10Mbps 7-wire interface mode, this signal should be connected to VSS.
In Ethernet mode, EMDC is an output clock which provides a timing reference to the PHY for data transfers on the EMDIO signal. Applies to MII mode operation.
Input clock which provides a timing reference for ETXEN, ETXD[3:0] and ETXER
Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first ETXCLK following the final nibble of the frame.
ETXD0 is the serial output Ethernet data and is only valid during the assertion of ETXEN. This signal is used for 10-Mbps Ethernet data. It is also used for MII mode data in conjunction with ETXD[3:1].
Asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode.
I/O
I/O
O
I
I
O
O
O
O
O
MCF5271 Reference Manual, Rev. 2
2-10 Freescale Semiconductor
Signal Primary Functions
Table 2-8. Ethernet Module (FEC) Signals (Continued)
Signal Name
Receive Clock
Receive Data Valid
Receive Data 0
Transmit Data 1–3
Transmit Error
Receive Data 1–3
Receive Error
Abbreviation
ERXCLK
ERXDV
ERXD0
Carrier Receive Sense ECRS
ETXD[3:1]
ETXER
ERXD[3:1]
ERXER
Function
Provides a timing reference for ERXDV, ERXD[3:0], and ERXER.
Asserting the receive data valid (ERXDV) input indicates that the PHY has valid nibbles present on the MII. ERXDV should remain asserted from the first recovered nibble of the frame through to the last nibble.
Assertion of ERXDV must start no later than the SFD and exclude any
EOF.
ERXD0 is the Ethernet input data transferred from the PHY to the media-access controller when ERxDV is asserted. This signal is used for 10-Mbps Ethernet data. This signal is also used for MII mode
Ethernet data in conjunction with ERXD[3:1].
When asserted, indicates that transmit or receive medium is not idle.
Applies to MII mode operation.
In Ethernet mode, these pins contain the serial output Ethernet data and are valid only during assertion of ETXEN in MII mode.
In Ethernet mode, when ETXER is asserted for one or more clock cycles while ETXEN is also asserted, the PHY sends one or more illegal symbols. ETXER has no effect at 10 Mbps or when ETXEN is negated. Applies to MII mode operation.
In Ethernet mode, these pins contain the Ethernet input data transferred from the PHY to the Media Access Controller when
ERXDV is asserted in MII mode operation.
In Ethernet mode, ERXER—when asserted with ERXDV—indicates that the PHY has detected an error in the current frame. When
ERXDV is not asserted ERXER has no effect. Applies to MII mode operation.
I/O
I
I
I
I
I
I
O
O
2.3.8 I
2
C I/O Signals
2
C serial interface module signals.
Table 2-9. I
2
C I/O Signals
Signal Name
Serial Clock
Serial Data
Abbreviation
I2C_SCL
I2C_SDA
Function
Open-drain clock signal for the for the I by the I
2
2
C interface. Either it is driven
C module when the bus is in the master mode or it becomes the clock input when the I
2
C is in the slave mode.
Open-drain signal that serves as the data input/output for the I
2
C interface.
I/O
I/O
I/O
2.3.9 Queued Serial Peripheral Interface (QSPI)
Table 2-10 describes QSPI signals.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 2-11
Signal Descriptions
Table 2-10. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name Abbreviation Function
QSPI Syncrhonous
Serial Output
QSPI Synchronous
Serial Data Input
QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be driven on the rising or falling edge of QSPI_CLK. Each byte is sent msb first.
QSPI_DIN Provides the serial data to the QSPI and can be programmed to be sampled on the rising or falling edge of QSPI_CLK. Each byte is written to RAM lsb first.
QSPI Serial Clock QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable. The output frequency is programmed according to the following formula, in which n can be any value between 1 and 255:
SPI_CLK = f sys/2
÷ (2 × n)
Synchronous
Peripheral Chip Selects
QSPI_CS[1:0] Provide QSPI peripheral chip selects that can be programmed to be active high or low. QSPI_CS1 can also be configured as SDRAM clock enable signal SD_CKE.
I/O
O
I
O
O
2.3.10 UART Module Signals
The UART modules use the signals in this section for data. The baud rate clock inputs are not supported.
Table 2-11. UART Module Signals
Signal Name
Transmit Serial Data
Output
Abbreviation Function
U2TXD/U1TXD
/U0TXD
Transmitter serial data outputs for the UART modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, lsb first, on this pin at the falling edge of the serial clock source.
I/O
O
Receive Serial Data
Input
U2RXD/U1RX
D/U0RXD
Receiver serial data inputs for the UART modules. Data received on this pin is sampled on the rising edge of the serial clock source lsb first. When the UART clock is stopped for power-down mode, any transition on this pin restarts it.
I
Clear-to-Send
Request-to-Send
U1CTS/U0CTS Indicate to the UART modules that they can begin data transmission.
I
U1RTS/U0RTS Automatic request-to-send outputs from the UART modules.
U1RTS/U0RTS can also be configured to be asserted and negated as a function of the RxFIFO level.
O
2.3.11 DMA Timer Signals
Table 2-12 describes the signals of the four DMA timer modules.
MCF5271 Reference Manual, Rev. 2
2-12 Freescale Semiconductor
Signal Name
DMA Timer 0 Input
DMA Timer 0 Output
DMA Timer 1 Input
DMA Timer 1 Output
DMA Timer 2 Input
DMA Timer 2 Output
DMA Timer 3 Input
DMA Timer 3 Output
Signal Primary Functions
Table 2-12. DMA Timer Signals
Abbreviation
DT0IN
DT0OUT
DT1IN
DT1OUT
DT2IN
DT2OUT
DT3IN
DT3OUT
Function
Can be programmed to cause events to occur in first platform timer. It can either clock the event counter or provide a trigger to the timer value capture logic.
The output from first platform timer.
Can be programmed to cause events to occur in the second platform timer. This can either clock the event counter or provide a trigger to the timer value capture logic.
The output from the second platform timer.
Can be programmed to cause events to occur in the third platform timer. It can either clock the event counter or provide a trigger to the timer value capture logic.
The output from the third platform timer.
Can be programmed as an input that causes events to occur in the fourth platform timer. This can either clock the event counter or provide a trigger to the timer value capture logic.
The output from the fourth platform timer.
I/O
I
O
O
I
I
O
I
I
2.3.12 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the
BDM logic.
Table 2-13. Debug Support Signals
Signal Name
Test Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Development Serial
Clock
Breakpoint
Development Serial
Input
Abbreviation
TRST
TCLK
TMS
TDI
TDO
DSCLK
BKPT
DSI
Function
This active-low signal is used to initialize the JTAG logic asynchronously.
Used to synchronize the JTAG logic.
Used to sequence the JTAG state machine. TMS is sampled on the rising edge of TCLK.
Serial input for test instructions and data. TDI is sampled on the rising edge of TCLK.
Serial output for test instructions and data. TDO is three-stateable and is actively driven in the shift-IR and shift-DR controller states.
TDO changes on the falling edge of TCLK.
Clocks the serial communication port to the BDM module during packet transfers.
Used to request a manual breakpoint.
This internally-synchronized signal provides data input for the serial communication port to the BDM module.
I
I
I
I
I/O
I
I
I
O
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 2-13
Signal Descriptions
Table 2-13. Debug Support Signals (Continued)
Signal Name
Development Serial
Output
Debug Data
Processor Status
Outputs
Abbreviation
DSO
DDATA[3:0]
PST[3:0]
Processor Status Clock PSTCLK
Function
This internally-registered signal provides serial output communication for BDM module responses.
Display captured processor data and breakpoint status. The PSTCLK signal can be used by the development system to know when to sample DDATA[3:0].
Indicate core status, as shown in Table 2-14
. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. The PSTCLK signal can be used by the development system to know when to sample PST[3:0].
PSTCLK indicates when the development system should sample
PST and DDATA values.
I/O
O
O
O
O
PST[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Table 2-14. Processor Status
Processor Status
Continue execution
Begin execution of one instruction
Reserved
Entry into user mode
Begin execution of PULSE and WDDATA instructions
Begin execution of taken branch
Reserved
Begin execution of RTE instruction
Begin one-byte transfer on DDATA
Begin two-byte transfer on DDATA
Begin three-byte transfer on DDATA
Begin four-byte transfer on DDATA
Exception processing
Reserved
Processor is stopped
Processor is halted
2.3.13 Test Signals
Table 2-15 describes test signals.
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Test
Signal Name
PLL Test
External Boot Mode
Table 2-15. Test Signals
Abbreviation
TEST
PLL_TEST
Function
Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions.
Reserved for factory testing only and should be treated as a no-connect (NC).
I/O
I
I
2.3.14 Power and Ground Pins
The pins described in Table 2-16 provide system power and ground to the chip. Multiple pins are
provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression.
Table 2-16. Power and Ground Pins
Signal Name
PLL Analog Supply
I/O
I
Positive Supply
Positive Supply
Ground
Abbreviation
VDDPLL,
VSSPLL
VDDO
VDD
VSS
Function
Dedicated power supply signals to isolate the sensitive PLL analog circuitry from the normal levels of noise present on the digital power supply.
These pins supply positive power to the I/O pads .
These pins supply positive power to the core logic.
This pin is the negative supply (ground) to the chip.
I
I
2.4 External Boot Mode
When booting from external memory, the address bus, data bus, and bus control signals will default to their bus functionalities as shown in
. As in single-chip mode, the signals listed in
will operate as described above. All other signals will default to GPIO inputs.
Table 2-17. Default Signal Functions After System Reset (External Boot Mode)
Signal
A[23:0]
D[31:0]
BS[3:0]
OE
TA
TEA
R/W
TSIZ[1:0]
Reset
A[23:0]
—
High
High
—
—
High
High
I/O
O
O
I
I
O
I/O
O
O
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Signal Descriptions
Table 2-17. Default Signal Functions After System Reset (External Boot Mode) (Contin-
Signal
TS
TIP
CS[7:0]
Reset
High
High
High
I/O
O
O
O
2-16
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Chapter 3
ColdFire Core
This section describes the organization of the Version 2 (V2) ColdFire
®
processor core and an overview of the program-visible registers. For detailed information on instructions, see the
ColdFire Family Programmer’s Reference Manual.
3.1
Processor Pipelines
Figure 3-1 is a block diagram showing the processor pipelines of a V2 ColdFire core.
Instruction
Fetch
Pipeline
IAG
IC
Instruction
Address
Generation
Instruction
Fetch Cycle
IB
FIFO
Instruction Buffer
Address [31:0]
Operand
Execution
Pipeline
DSOC
Decode & Select,
Operand Fetch
AGEX
Address
Generation,
Execute
Read Data[31:0]
Write Data[31:0]
Figure 3-1. ColdFire Processor Core Pipelines
The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer.
The Instruction Fetch Pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage Operand Execution Pipeline (OEP),
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ColdFire Core which decodes the instruction, fetches the required operands and then executes the required function. Since the IFP and OEP pipelines are decoupled by an instruction buffer which serves as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.
The Instruction Fetch Pipeline consists of two stages with an instruction buffer stage:
• Instruction Address Generation (IAG Cycle)
• Instruction Fetch Cycle (IC Cycle)
• Instruction Buffer (IB Cycle)
When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the
Operand Execution Pipeline. If the buffer is not empty, the IFP stores the contents of the fetch cycle in the FIFO queue until it is required by the OEP. In the Version 2 implementation, the instruction buffer contains three 32-bit longwords of storage.
The Operand Execution Pipeline is implemented in a two-stage pipeline featuring a traditional
RISC datapath with a dual-read-ported register file (RGF) feeding an arithmetic/logic unit. In this design, the pipeline stages have multiple functions:
• Decode & Select/Operand Cycle (DSOC Cycle)
• Address Generation/Execute Cycle (AGEX Cycle)
3.2
Processor Register Description
The following paragraphs describe the processor registers in the user and supervisor programming models. The appropriate programming model is selected based on the privilege level (user mode or supervisor mode) of the processor as defined by the S bit of the status register (SR).
3.2.1
User Programming Model
Figure 3-2 illustrates the user programming model. The model is the same as the M68000 family
microprocessors, consisting of the following registers:
• 16 general-purpose 32-bit registers (D0–D7, A0–A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
3.2.1.1
Data Registers (D0–D7)
Registers D0–D7 are used as data registers for bit (1-bit), byte (8-bit), word (16-bit) and longword
(32-bit) operations; they can also be used as index registers.
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Processor Register Description
3.2.1.2
Address Registers (A0–A6)
These registers can be used as software stack pointers, index registers, or base address registers; they can also be used for word and longword operations.
3.2.1.3
Stack Pointer (A7)
Certain ColdFire implementations, including the MCF5271, support two unique stack pointer
(A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP). This support provides the required isolation between operating modes of the processor. The SSP is described in
Section 3.2.3.2, “Supervisor/User Stack Pointers (A7 and OTHER_A7)
.”
A subroutine call saves the PC on the stack and the return restores it from the stack. Both the PC and the SR are saved on the supervisor stack during the processing of exceptions and interrupts.
The return from exception (RTE) instruction restores the SR and PC values from the supervisor stack.
3.2.1.4
Program Counter (PC)
The PC contains the address of the currently executing instruction. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate. For some addressing modes, the PC is used as a base address for PC-relative operand addressing.
31 15 7 0
A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
Data
Registers
Address registers
A7
PC
USERStack
Pointer
Program
Counter
15 7 0
CCR
ConditionCode
Register
Figure 3-2. User Programming Model
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3.2.1.5
Condition Code Register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results generated by processor operations. Bit 4, the extend bit (X bit), is also used as an input operand during multiprecision arithmetic computations.
3
2
1
0
Bits
7–5
4
Field
Reset
7
0
0
6
0
0
5
0
0
4
X
0
3
N
0
2
Z
0
1
V
0
Address LSB of Status Register (SR)
Figure 3-3. Condition Code Register (CCR)
Name
—
X
N
Z
V
C
0
C
0
Table 3-1. CCR Field Descriptions
Description
Reserved, should be cleared
Extend condition code bit. Set to the value of the C-bit for arithmetic operations; otherwise not affected or set to a specified result.
Negative condition code bit. Set if the most significant bit of the result is set; otherwise cleared.
Zero condition code bit. Set if the result equals zero; otherwise cleared.
Overflow condition code bit. Set if an arithmetic overflow occurs implying that the result cannot be represented in the operand size; otherwise cleared.
Carry condition code bit. Set if a carry out of the operand msb occurs for an addition, or if a borrow occurs in a subtraction; otherwise cleared
Set to the value of the C bit for arithmetic operations; otherwise not affected.
3.2.2
EMAC Register Description
The registers in the EMAC portion of the user programming model, are described in
“Enhanced Multiply-Accumulate Unit (EMAC) ,” and include the following registers:
• Four 48-bit accumulator registers partitioned as follows:
— Four 32-bit accumulators (ACC0–ACC3)
— Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two 32-bit values for load and store operations (ACCEXT01 and ACCEXT23).
Accumulators and extension bytes can be loaded, copied, and stored, and results from
EMAC arithmetic operations generally affect the entire 48-bit destination.
• Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values for load and store operations (ACCext01 and ACCext23)
• One 16-bit mask register (MASK)
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Processor Register Description
• One 32-bit status register (MACSR) including four indicator bits signaling product or accumulation overflow (one for each accumulator: PAV0–PAV3)
These registers are shown in
.
Table 3-2. EMAC Register Set
31:24 7:0 23:16 15:8
MAC Status Register
MAC Accumulator 0
MAC Accumulator 1
MAC Accumulator 2
MAC Accumulator 3
Extensions for ACC0 and ACC1
Extensions for ACC2 and ACC3
MAC Mask Register
Mnemonic
MACSR
ACC0
ACC1
ACC2
ACC3
ACCext01
ACCext23
MASK
3.2.3
Supervisor Register Description
Only system control software is intended to use the supervisor programming model to implement restricted operating system functions, I/O control, and memory management. All accesses that affect the control features of ColdFire processors are in the supervisor programming model, which consists of registers available in user mode as well as the following control registers:
• 16-bit status register (SR)
• 32-bit supervisor stack pointer (SSP)
• 32-bit vector base register (VBR)
• 32-bit cache control register (CACR)
• Two 32-bit access control registers (ACR0, ACR1)
• Two 32-bit base address registers (RAMBAR)
Table 3-3. Supervisor Programming Model
31:24 23:16 15:8 7:0
— Status Register
Supervisor/User A7 Stack Pointer
User/Supervisor A7 Stack Pointer
Vector Base Register
Cache Control Register
Access Control Register 0
Mnemonic
SR
A7
OTHER_A7
VBR
CACR
ACR0
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31:24
Table 3-3. Supervisor Programming Model
7:0 23:16 15:8
Access Control Register 1
RAM Base Address Register
Mnemonic
ACR1
RAMBAR1
The following paragraphs describe the supervisor programming model registers.
3.2.3.1
Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control bits. In supervisor mode, software can access the entire SR. In user mode, only the lower
8 bits are accessible (CCR). The control bits indicate the following states for the processor: trace mode (T bit), supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access when in supervisor mode.
15
Field T
Reset 0
Address
Bits
15
14
13
12
11
10–8
7–5
4–0
System Byte Condition Code Register (CCR)
14
—
0
Name
T
—
S
M
—
I
—
CCR
13
S
0
12
M
0
11
—
0
10 9
I
0
8 7 6
—
0
5
0 0 0 0
CPU @ 0x80E
Figure 3-4. Status Register (SR)
4
X
0
3
N
0
2
Z
0
1
V
0
0
C
0
Table 3-4. SR Field Descriptions
Description
Trace enable. When set, the processor performs a trace exception after every instruction.
Reserved, should be cleared.
Supervisor/user state. Denotes whether the processor is in supervisor mode (S = 1) or user mode (S = 0).
Master/interrupt state. This bit is cleared by an interrupt exception, and can be set by software during execution of the RTE or move to SR instructions.
Reserved, should be cleared.
Interrupt level mask. Defines the current interrupt level. Interrupt requests are inhibited for all priority levels less than or equal to the current level, except the edge-sensitive level 7 request, which cannot be masked.
Reserved, should be cleared.
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Processor Register Description
3.2.3.2
Supervisor/User Stack Pointers (A7 and OTHER_A7)
The MCF5271 architecture supports two independent stack pointer (A7) registers
— the supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two programmable-visible 32-bit registers does not identify one as the SSP and the other as the USP.
Instead, the hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents are a function of the processor operation mode, as shown in the following: if SR[S] = 1 then A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer else A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the responsibility of the external development system to determine, based on the setting of SR[S], the mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP). This functionality is enabled by setting the enable user stack pointer bit, CACR[EUSP]. If this bit is cleared, only the stack pointer (A7), defined for previous ColdFire versions, is available. EUSP is zero at reset.
If EUSP is set, the appropriate stack pointer register (SSP or USP) is accessed as a function of the processor’s operating mode. To support dual stack pointers, the following two privileged M68000 instructions are added to the ColdFire instruction set architecture to load/store the USP: move.l Ay, USP; move to USP move.l USP, Ax; move from USP
These instructions are described in the ColdFire Family Programmer’s Reference Manual.
3.2.3.3
Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in memory. To access the vector table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are not implemented by ColdFire processors; they are assumed to be zero, forcing the table to be aligned on a 1 MByte boundary.
3.2.3.4
Cache Control Register (CACR)
The CACR controls operation of the instruction/data cache memories. It includes bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining the default cache mode
and write-protect fields. The CACR is described in Section 5.2.1.1, “Cache Control Register
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3.2.3.5
Access Control Registers (ACR0, ACR1)
The access control registers, ACR0 and ACR1, define attributes for two user-defined memory regions. These attributes include the definition of cache mode, write protect, and buffer write enables. The ACRs are described in
Section 5.2.1.2, “Access Control Registers (ACR0, ACR1) .”
3.2.3.6
SRAM Base Address Register (RAMBAR)
The RAMBAR register is used to specify the base address of the internal SRAM and indicate the types of references mapped to it. The base address register includes a base address, write-protect bit, address space mask bits, and an enable bit. For more information, refer to
“SRAM Base Address Register (RAMBAR)
”.
3.3
Memory Map/Register Definition
Table 3-5 lists register names, the CPU space location, and whether the register is written from the
processor using the MOVEC instruction.
Table 3-5. ColdFire CPU Registers
Name
CACR
ACR0, ACR1
D0–D7
A0–A7
OTHER_A7
VBR
MACSR
MASK
ACC0–ACC3
ACCext01
ACCext23
SR
PC
CPU Space (Rc)
Written with
MOVEC
Register Name
Memory Management Control Registers
0x002
0x004–0x005
Yes
Yes
Cache control register
Access control registers 0 and 1
Processor General-Purpose Registers
0x(0,1)80–0x(0,1)87
0x(0,1)88–0x(0,1)8F
No
No
Data registers 0-7 (0 = load, 1 = store)
Address registers 0-7 (0 = load, 1 = store)
A7 is user stack pointer
Processor Miscellaneous Registers
0x800
0x801
0x804
0x805
0x806, 0x809,
0x80A, 0x80B
0x807
0x808
0x80E
0x80F
No
Yes
No
No
No
No
No
No
Yes
Other stack pointer
Vector base register
MAC status register
MAC address mask register
MAC accumulators 0-3
MAC accumulator 0, 1 extension bytes
MAC accumulator 2, 3 extension bytes
Status register
Program counter
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Additions to the Instruction Set Architecture
Name
RAMBAR
Table 3-5. ColdFire CPU Registers (Continued)
CPU Space (Rc)
0xC05
Written with
MOVEC
Register Name
Local Memory Registers
Yes SRAM base address register
3.4
Additions to the Instruction Set Architecture
The original ColdFire instruction set architecture (ISA) was derived from the M68000-family opcodes based on extensive analysis of embedded application code. After the initial ColdFire compilers were created, developers identified ISA additions that would enhance both code density and overall performance. Additionally, as users implemented ColdFire-based designs into a wide range of embedded systems, they identified frequently used instruction sequences that could be improved by the creation of new instructions. This observation was especially prevalent in development environments that made use of substantial amounts of assembly language code.
Table 3-6 summarizes the new instructions added to Revision A+ ISA. For more details see
Section 3.14, “ColdFire Instruction Set Architecture Enhancements .”
Table 3-6. ISA Revision A+ New Instructions
Instruction
BITREV
BYTEREV
FF1
STLDSR
Description
The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0], new Dx[30] = old Dx[1], ..., new Dx[0] = old Dx[31].
The contents of the destination data register are byte-reversed; that is, new Dx[31:24] = old
Dx[7:0], ..., new Dx[7:0] = old Dx[31:24].
The data register, Dx, is scanned, beginning from the most-significant bit (Dx[31]) and ending with the least-significant bit (Dx[0]), searching for the first set bit. The data register is then loaded with the offset count from bit 31 where the first set bit appears.
Pushes the contents of the status register onto the stack and then reloads the status register with the immediate data value.
3.5
Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors differ from the M68000 family in that they include:
• A simplified exception vector table
• Reduced relocation capabilities using the vector base register
• A single exception stack frame format
• Use of a single self-aligning system stack
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ColdFire Core
All ColdFire processors use an instruction restart exception model, but certain microarchitectures
(V2 and V3) require more software support to recover from certain access errors. See
Section 3.7.1, “Access Error Exception ” for details.
Exception processing includes all actions from the detection of the fault condition to the initiation of fetch for the first handler instruction. Exception processing is comprised of four major steps
First, the processor makes an internal copy of the SR and then enters supervisor mode by asserting the S bit and disabling trace mode by negating the T bit. The occurrence of an interrupt exception also forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current interrupt request.
Second, the processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on the exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the interrupt controller. The IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address.
Third, the processor saves the current context by creating an exception stack frame on the supervisor system stack. As a result, the exception stack frame is created at a 0-modulo-4 address on the top of the current system stack. Additionally, the processor uses a simplified fixed-length stack frame for all exceptions. The exception type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next).
Fourth, the processor calculates the address of the first instruction of the exception handler. By definition, the exception vector table is aligned on a 1 Mbyte boundary. This instruction address is generated by fetching an exception vector from the table located at the address defined in the vector base register. The index into the exception table is calculated as (4 x vector number). Once the exception vector has been fetched, the contents of the vector determine the address of the first instruction of the desired handler. After the instruction fetch for the first opcode of the handler has been initiated, exception processing terminates and normal instruction processing continues in the handler.
All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see
Table 3-7 ). The table contains 256 exception vectors; the first 64 are defined by
Freescale and the remaining 192 are user-defined interrupt vectors.
Table 3-7. Exception Vector Assignments
Vector
Number(s)
0
1
2
Vector
Offset (Hex)
0x000
0x004
0x008
Stacked
Program
Counter
—
—
Fault
Assignment
Initial stack pointer
Initial program counter
Access error
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Exception Stack Frame Definition
Table 3-7. Exception Vector Assignments (Continued)
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
15–23
24
25–31
32–47
11
12
13
14
6–7
8
9
10
3
4
5
0x00C
0x010
0x014
0x018–0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C–0x05C
0x060
0x064–0x07C
0x080–0x0BC
Fault
Fault
Fault
—
Fault
Next
Fault
Fault
Next
—
Fault
—
Next
—
Next
Address error
Illegal instruction
Divide by zero
Reserved
Privilege violation
Trace
Unimplemented line-a opcode
Unimplemented line-f opcode
Debug interrupt
Reserved
Format error
Reserved
Spurious interrupt
Reserved
Trap # 0-15 instructions
48–63
64–255
0x0C0–0x0FC
0x100–0x3FC
—
Next
Reserved
User-defined interrupts
“Fault” refers to the PC of the instruction that caused the exception; “Next” refers to the
PC of the next instruction that follows the instruction that caused the fault.
All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register. In addition, the V2 core includes a new instruction (STLDSR) that stores the current interrupt mask level and loads a value into the SR.
This instruction is specifically intended for use as the first instruction of an interrupt service routine which services multiple interrupt requests with different interrupt levels. For more details see
Section 3.14, “ColdFire Instruction Set Architecture Enhancements
.”
3.6
Exception Stack Frame Definition
The exception stack frame is shown in Figure 3-5 . The first longword of the exception stack frame
contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the second longword contains the 32-bit program counter address.
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SSP
+ 0x4
31 27
FORMAT FS[3:2]
25
VECTOR[7:0]
17
FS[1:0]
15
Program Counter[31:0]
Status Register
0
Figure 3-5. Exception Stack Frame Form
The 16-bit format/vector word contains 3 unique fields:
• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by the processor indicating a two-longword frame format. See
Table 3-8. Format Field Encodings
Original SSP @ Time of Exception, Bits 1:0
00
01
10
11
SSP @ 1st
Instruction of
Handler
Original SSP - 8
Original SSP - 9
Original SSP - 10
Original SSP - 11
Format Field
6
7
4
5
• There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other types of exceptions. See
Table 3-9. Fault Status Encodings
FS[3:0]
00xx
0100
0101
011x
1000
1001
101x
1100
1101
111x
Definition
Reserved
Error on instruction fetch
Reserved
Reserved
Error on operand write
Attempted write to write-protected space
Reserved
Error on operand read
Reserved
Reserved
• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor for all internal faults and represents the value supplied by the interrupt controller
in the case of an interrupt. Refer to Table 3-7
.
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Processor Exceptions
3.7
Processor Exceptions
3.7.1
Access Error Exception
The exact processor response to an access error depends on the type of memory reference being performed. For an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an instruction for execution. Therefore, faults that occur during instruction prefetches that are then followed by a change of instruction flow do not generate an exception.
When the processor attempts to execute an instruction with a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For this type of exception, the programming model has not been altered by the instruction generating the access error.
If the access error occurs on an operand read, the processor immediately aborts the current instruction’s execution and initiates exception processing. In this situation, any address register updates attributable to the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming model contains the updated An value. In addition, if an access error occurs during the execution of a MOVEM instruction loading from memory, any registers already updated before the fault occurs contain the operands from memory.
The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes. Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. Accordingly, the PC contained in the exception stack frame merely represents the location in the program when the access error was signaled. All programming model updates associated with the write instruction are completed. The NOP instruction can collect access errors for writes. This instruction delays its execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.
3.7.2
Address Error Exception
Any attempted execution transferring control to an odd instruction address (that is, if bit 0 of the target address is set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of 8 on an indexed effective addressing mode generates an address error as does an attempted execution of a full-format indexed addressing mode.
3.7.3
Illegal Instruction Exception
Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an illegal instruction exception (vector 4). Additionally, any attempted execution of any non-MAC line-A and most line-F opcode generates their unique exception types, vector numbers
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10 and 11, respectively. The V2 core does not provide illegal instruction detection on the extension words on any instruction, including MOVEC.
3.7.4
Divide-By-Zero
Attempting to divide by zero causes an exception (vector 5, offset = 0x014).
3.7.5
Privilege Violation
The attempted execution of a supervisor mode instruction while in user mode generates a privilege violation exception. See the ColdFire Programmer’s Reference Manual for lists of supervisor- and user-mode instructions.
3.7.6
Trace Exception
To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing capability. While in trace mode, indicated by the assertion of the T-bit in the status register
(SR[15] = 1), the completion of an instruction execution (for all but the STOP instruction) signals a trace exception. This functionality allows a debugger to monitor program execution.
The STOP instruction has the following effects:
1. The instruction before the STOP executes and then generates a trace exception. In the exception stack frame, the PC points to the STOP opcode.
2. When the trace handler is exited, the STOP instruction is executed, loading the SR with the immediate operand from the instruction.
3. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after the STOP, and the SR reflects the value loaded in the previous step.
If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the STOP, and the SR reflects the value loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. As an example, consider the execution of a TRAP instruction while in trace mode. The processor will initiate the TRAP exception and then pass control to the corresponding handler. If the system requires that a trace exception be processed, it is the responsibility of the TRAP exception handler to check for this condition (SR[15] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception.
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Processor Exceptions
3.7.7
Unimplemented Line-A Opcode
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the attempted execution of an undefined line-A opcode.
3.7.8
Unimplemented Line-F Opcode
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated by attempted execution of an undefined line-F opcode.
3.7.9
Debug Interrupt
This special type of program interrupt is discussed in detail in Chapter 32, “Debug Support.” This exception is generated in response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle but rather calculates the vector number internally (vector number 12).
3.7.10 RTE and Format Error Exception
When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire core, any attempted RTE execution where the format is not equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code from
M68000 applications. On M68000 family processors, the SR was located at the top of the stack.
On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero.
Thus, if an RTE is attempted using this “old” format, it generates a format error on a ColdFire processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame.
3.7.11 TRAP Instruction Exception
The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls.
3.7.12 Interrupt Exception
Interrupt exception processing includes interrupt recognition and the fetch of the appropriate
vector from the interrupt controller using an IACK cycle. See Chapter 13, “Interrupt Controller
for details on the interrupt controller.
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3.7.13 Fault-on-Fault Halt
If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic “fault-on-fault” condition.
A reset is required to force the processor to exit this halted state.
3.7.14 Reset Exception
Asserting the reset input signal to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the S-bit and disables tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets the processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero
(0x00000000). The control registers specifying the operation of any memories (e.g., cache and/or
RAM modules) connected directly to the processor are disabled.
NOTE
Other implementation-specific supervisor registers are also affected.
Refer to each of the modules in this user’s manual for details on these registers.
Once the processor is granted the bus, it then performs two longword read bus cycles. The first longword at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault halted state.
ColdFire processors load hardware configuration information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated. This allows an emulator to read out the contents of these registers via BDM to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in Figure 3-6
.
3-16
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Processor Exceptions
31
R
W
Reset 1
30
1
29
0
28
PF
27
0 1
26
1
25
1
24
1
23
0
22
VER
21
0 1
20
0
19
0
18
REV
17
0 0
15 14 13 12 11
R MAC DIV EMAC FPU MMU
W
Reset 0 1 1
10 9
—
8 7 6
ISA
5 4
0 0 0 0 0 1 0 0 0
Figure 3-6. D0 Hardware Configuration Info
3
0 0
Table 3-10. D0 Hardware Configuration Info Field Description
2 1
DEBUG
0
Bits
31–24
23–20
19–16
15
14
13
12
11
10–8
Name
PF
VER
REV
MAC
DIV
EMAC
FPU
MMU
—
16
0
0
0
Description
Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.
ColdFire core version number. This field is fixed to a hex value of 0x2 indicating a Version
2 ColdFire core.
Processor revision number.
MAC execute engine status.
0 MAC execute engine not present in core. (This is the value used for MCF5271 .)
1 MAC execute engine is present in core.
Divide execute engine status.
0 Divide execute engine not present in core.
1 Divide execute engine is present in core. (This is the value used for MCF5271 .)
EMAC execute engine status.
0 EMAC execute engine not present in core.
1 EMAC execute engine is present in core. (This is the value used for MCF5271)
FPU execute engine status.
0 FPU execute engine not present in core. (This is the value used for MCF5271)
1 FPU execute engine is present in core.
Virtual memory management unit status.
0 MMU execute engine not present in core. (This is the value used for MCF5271)
1 MMU execute engine is present in core.
Reserved.
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ColdFire Core
Table 3-10. D0 Hardware Configuration Info Field Description (Continued)
Bits
7–4
3–0
Name Description
ISA Instruction set architecture (ISA) revision number.
0000 ISA_A
0001 ISA_B
0010 ISA_C
1000 ISA_A+ (ISA_A with the addition of the BYTEREV, BITREV, FF1, and STLDSR instructions. This is the value used for MCF5271.)
0011-1111 Reserved.
DEBUG Debug module revision number.
0000 DEBUG_A (This is the value used for MCF5271)
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
0101–1111 Reserved.
Information loaded into D1 defines the local memory hardware configuration as shown in
31 30
R
W
Reset 0
CL
0
15 14
R BUSW
W
Reset 0 0
29
ICA
28
0 1
13
DCA
12
27
0
11
26
ICSIZ
25
1 0
10
DCSIZ
9
24
1
8
23
0
7
22 21
0 0
6 5
RAM1SIZ
0
4
20
—
19
0
3
18 17
0 0
2 1
ROM1SIZ
16
0
0
0 1 0 0 0 0 1 0 0 0
Figure 3-7. D1 Hardware Configuration Info
0 0 0 0
Table 3-11. D1 Local Memory Hardware Configuration Information Field Description
Bits
31–30
29–28
27–24
23–16
15–14
Name
CL
ICA
ICSIZ
—
BUSW
Description
Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.
Instruction cache associativity.
00 Four-way.
01 Direct mapped. (This is the value used for MCF5271)
Instruction cache size.
0101 8KB instruction cache. (This is the value used for MCF5271)
All other values do not apply for MCF5271
Reserved for MCF5271
Encoded bus data width.
00 32-bit data bus (only configuration currently in use).
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Instruction Execution Timing
Table 3-11. D1 Local Memory Hardware Configuration Information Field Description
Bits
13–12
11–8
7–4
3–0
Name Description
DCA
DCSIZ
Data cache associativity.
00 Four-way.
01 Direct mapped. (This is the value used for MCF5271)
Data cache size.
0000 No data cache. (This is the value used for MCF5271)
All other values do not apply for MCF5271.
RAM1SIZ RAM bank 1 size.
1000 64KB RAM. (This is the value used for MCF5271)
All other values do not apply for MCF5271
ROM1SIZ ROM bank 1 size.
0x0–0x3 No ROM. (This is the value used for MCF5271)
All other values do not apply for MCF5271.
3.8
Instruction Execution Timing
This section presents V2 processor instruction execution times in terms of processor core clock cycles. The number of operand references for each instruction is enclosed in parentheses following the number of processor clock cycles. Each timing entry is presented as C(R/W) where:
• C is the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution.
• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing a read-modify-write function is denoted as (1/1).
This section includes the assumptions concerning the timing values and the execution time details.
3.8.1
Timing Assumptions
For the timing data presented in this section, the following assumptions apply:
1. The operand execution pipeline (OEP) is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the instruction fetch pipeline (IFP) to supply opwords and/or extension words.
2. The OEP does not experience any sequence-related pipeline stalls. For V2 ColdFire processors, the most common example of this type of stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE operations (except
MOVEM), certain hardware resources within the processor are marked as “busy” for two processor clock cycles after the final DSOC cycle of the store instruction. If a subsequent
STORE instruction is encountered within this 2-cycle window, it will be stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive STORE operations is 2 cycles. The MOVEM instruction uses a different set of resources and this stall does not apply.
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ColdFire Core
3. The OEP completes all memory accesses without any stall conditions caused by the memory itself. Thus, the timing details provided in this section assume that an infinite zero-wait state memory is attached to the processor core.
4. All operand data accesses are aligned on the same byte boundary as the operand size: that is, 16 bit operands aligned on 0-modulo-2 addresses and 32 bit operands aligned on
0-modulo-4 addresses.
If the operand alignment fails these guidelines, it is misaligned. The processor core decomposes the misaligned operand reference into a series of aligned accesses as shown in
.
Table 3-12. Misaligned Operand References
Address[1:0]
X1
X1
10
Size
Word
Long
Long
Kbus
Operations
Byte, Byte
Byte, Word,
Byte
Word, Word
Additional
C(R/W)
2(1/0) if read
1(0/1) if write
3(2/0) if read
2(0/2) if write
2(1/0) if read
1(0/1) if write
3.8.2
MOVE Instruction Execution Times
The execution times for the MOVE.{B,W} instructions are shown in
provides the timing for MOVE.L.
For all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode.
The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l.
Table 3-13. Move Byte and Word Execution Times
Source
Dn
An
(An)
(An)+
-(An)
(d
16
,An)
(d
8
,An,Xi)
(xxx).w
Rx
1(0/0)
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
(Ax)
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
(Ax)+
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
Destination
-(Ax)
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
(d
16
,Ax) (d
8
,Ax,Xi) (xxx).wl
1(0/1)
1(0/1)
2(0/1)
2(0/1)
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
—
—
4(1/1)
4(1/1)
4(1/1)
—
—
—
3(1/1)
3(1/1)
3(1/1)
—
—
—
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Source
Dn
An
(An)
(An)+
-(An)
(d
16
,An)
(d
8
,An,Xi)
(xxx).w
(xxx).l
(d
16
,PC)
(d
8
,PC,Xi)
#<xxx>
Standard One Operand Instruction Execution Times
Source
(xxx).l
(d
16
,PC)
(d
8
,PC,Xi)
#<xxx>
Table 3-13. Move Byte and Word Execution Times (Continued)
Rx
3(1/0)
3(1/0)
4(1/0)
1(0/0)
(Ax)
3(1/1)
3(1/1)
4(1/1)
3(0/1)
(Ax)+
3(1/1)
3(1/1)
4(1/1)
3(0/1)
Destination
-(Ax)
3(1/1)
3(1/1)
4(1/1)
3(0/1)
(d
16
,Ax) (d
8
,Ax,Xi) (xxx).wl
—
3(1/1)
—
—
—
—
—
—
—
—
—
—
Rx
1(0/0)
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
1(0/0)
Table 3-14. Move Long Execution Times
(Ax)
1(0/1)
1(0/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(0/1)
(Ax)+
1(0/1)
1(0/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(0/1)
Destination
-(Ax)
1(0/1)
1(0/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(0/1)
—
—
—
2(1/1)
—
—
(d
16
,Ax)
1(0/1)
1(0/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
—
—
—
—
(d
8
,Ax,Xi) (xxx).wl
2(0/1)
2(0/1)
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
—
2(1/1)
2(1/1)
2(1/1)
—
—
—
—
—
—
—
3.9
Standard One Operand Instruction Execution Times
Table 3-15. One Operand Instruction Execution Times
Opcode <EA> bitrev byterev clr.b
clr.w
clr.l
Dx
Dx
<ea>
<ea>
<ea>
Rn
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
(An)
—
—
1(0/1)
1(0/1)
1(0/1)
(An)+
—
—
1(0/1)
1(0/1)
1(0/1)
Effective Address
-(An)
—
—
1(0/1)
1(0/1)
1(0/1)
(d16,An) (d8,An,Xn*SF) xxx.wl
—
—
1(0/1)
1(0/1)
1(0/1)
—
—
2(0/1)
2(0/1)
2(0/1)
—
—
1(0/1)
1(0/1)
1(0/1)
#xxx
—
—
—
—
—
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ColdFire Core
Opcode <EA> ext.w
ext.l
extb.l
ff1 neg.l
negx.l
not.l
scc stldsr swap tst.b
tst.w
tst.l
Table 3-15. One Operand Instruction Execution Times (Continued)
(An)+
—
—
—
—
—
—
—
—
—
—
3(1/0)
3(1/0)
2(1/0)
(An)
—
—
—
—
—
—
—
—
—
—
3(1/0)
3(1/0)
2(1/0)
Rn
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
—
1(0/0)
1(0/0)
1(0/0)
1(0/0)
Dx
Dx
Dx
Dx
Dx
Dx
Dx
Dx
#imm
Dx
<ea>
<ea>
<ea>
Effective Address
-(An)
—
—
—
—
—
—
—
—
—
—
3(1/0)
3(1/0)
2(1/0)
(d16,An) (d8,An,Xn*SF) xxx.wl
—
—
—
—
—
—
—
—
—
—
3(1/0)
3(1/0)
2(1/0)
—
—
—
—
—
—
—
—
—
—
4(1/0)
4(1/0)
3(1/0)
—
—
—
—
—
—
—
—
—
—
3(1/0)
3(1/0)
2(1/0)
3.10 Standard Two Operand Instruction Execution Times
Table 3-16. Two Operand Instruction Execution Times
Opcode asl.l
asr.l
bchg bchg bclr bclr add.l
add.l
addi.l
addq.l
addx.l
and.l
and.l
andi.l
<EA>
Rn
<ea>,Rx
Dy,<ea>
1(0/0)
—
#imm,Dx 1(0/0)
#imm,<ea> 1(0/0)
Dy,Dx
<ea>,Rx
Dy,<ea>
#imm,Dx
1(0/0)
1(0/0)
—
1(0/0)
<ea>,Dx
<ea>,Dx
1(0/0)
1(0/0)
Dy,<ea> 2(0/0)
#imm,<ea> 2(0/0)
Dy,<ea> 2(0/0)
#imm,<ea> 2(0/0)
(An)
—
—
4(1/1)
4(1/1)
4(1/1)
4(1/1)
3(1/0)
3(1/1)
—
3(1/1)
—
3(1/0)
3(1/1)
—
—
—
4(1/1)
4(1/1)
4(1/1)
4(1/1)
3(1/0)
3(1/1)
—
3(1/1)
—
3(1/0)
3(1/1)
—
(An)+
—
—
4(1/1)
4(1/1)
4(1/1)
4(1/1)
3(1/0)
3(1/1)
—
3(1/1)
—
3(1/0)
3(1/1)
—
Effective Address
-(An)
(d16,An)
(d16,PC)
(d8,An,Xn*SF)
(d8,PC,Xn*SF)
—
—
4(1/1)
4(1/1)
4(1/1)
4(1/1)
3(1/0)
3(1/1)
—
3(1/1)
—
3(1/0)
3(1/1)
—
—
—
5(1/1)
—
5(1/1)
—
4(1/0)
4(1/1)
—
4(1/1)
—
4(1/0)
4(1/1)
— xxx.wl
—
—
4(1/1)
—
4(1/1)
—
3(1/0)
3(1/1)
—
3(1/1)
—
3(1/0)
3(1/1)
—
#xxx
1(0/0)
1(0/0)
—
—
—
—
1(0/0)
—
—
—
—
1(0/0)
—
—
#xxx
—
—
—
—
—
—
—
—
5(0/1)
—
1(0/0)
1(0/0)
1(0/0)
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Standard Two Operand Instruction Execution Times
Table 3-16. Two Operand Instruction Execution Times (Continued)
Effective Address
Opcode <EA>
Rn (An) (An)+ -(An)
(d16,An)
(d16,PC)
(d8,An,Xn*SF)
(d8,PC,Xn*SF) xxx.wl
#xxx bset bset btst btst
Dy,<ea> 2(0/0)
#imm,<ea> 2(0/0)
Dy,<ea> 2(0/0)
#imm,<ea> 1(0/0)
4(1/1)
4(1/1)
3(1/1)
3(1/1)
41/1)
4(1/1)
3(1/1)
3(1/1)
4(1/1)
4(1/1)
3(1/1)
3(1/1)
4(1/1)
4(1/1)
3(1/1)
3(1/1)
5(1/1)
—
4(1/1)
—
4(1/1)
—
3(1/1)
—
—
—
—
1(0/0) cmp.l
cmpi.l
divs.w
1
divs.l
divu.l
eor.l
eori.l
lea lsl.l
lsr.l
moveq muls.w
mulu.w
muls.l
mulu.l
or.l
or.l
<ea>,Rx
#imm,Dx
<ea>,Dx
<ea>,Dx
3(1/0)
—
<ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
<ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
Dy,<ea>
#imm,Dx
<ea>,Ax
<ea>,Dx
<ea>,Dx
#imm,Dx
<ea>y, Dx
<ea>y, Dx
<ea>y, Dx
1(0/0)
1(0/0)
1(0/0)
1(0/0)
—
1(0/0)
1(0/0)
—
4(0/0)
4(0/0)
4(0/0)
4(0/0)
1(0/0)
—
3(1/0)
—
3(1/1)
—
1(0/0)
—
—
—
6(1/0)
6(1/0)
6(1/0)
6(1/0)
3(1/0)
3(1/1)
3(1/0)
—
3(1/1)
—
—
—
—
—
6(1/0)
6(1/0)
6(1/0)
3(1/0)
—
20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0)
20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0)
3(1/1)
—
—
—
—
—
6(1/0)
6(1/0)
6(1/0)
6(1/0)
3(1/0)
6(1/0)
3(1/0)
3(1/1) 3(1/1)
3(1/1)
—
1(0/0)
—
—
—
6(1/0)
6(1/0)
6(1/0)
6(1/0)
3(1/0)
3(1/1)
4(1/0)
—
24(1/0)
24(1/0)
—
—
4(1/1)
—
2(0/0)
—
—
—
7(1/0)
7(1/0)
—
—
3(1/0)
—
23(1/0)
23(1/0)
—
—
3(1/1)
—
1(0/0)
—
—
—
6(1/0)
6(1/0)
—
—
1(0/0)
—
20(0/0)
20(0/0)
—
—
—
—
—
1(0/0)
1(0/0)
1(0/0)
4(1/0)
4(1/0)
—
— <ea>y, Dx
<ea>,Rx
Dy,<ea>
4(1/0)
4(1/1)
3(1/0)
3(1/1)
1(0/0)
— ori.l
rems.l
sub.l
sub.l
subi.l
subq.l
subx.l
#imm,Dx 1(0/0) — — — —
<ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
<ea>,Dx ≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
<ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0)
Dy,<ea>
#imm,Dx
—
1(0/0)
#imm,<ea> 1(0/0)
Dy,Dx 1(0/0)
3(1/1)
—
3(1/1)
—
3(1/1)
—
3(1/1)
—
3(1/1)
—
3(1/1)
—
3(1/1)
—
3(1/1)
—
—
—
—
4(1/0)
4(1/1)
—
4(1/1)
—
—
—
—
3(1/0)
3(1/1)
—
3(1/1)
—
—
—
—
1(0/0)
—
—
—
—
1
For divide and remainder instructions the times listed represent the worst-case timing. Depending on the operand values, the actual execution time may be less.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 3-23
ColdFire Core
3.11 Miscellaneous Instruction Execution Times
Table 3-17. Miscellaneous Instruction Execution Times
Effective Address
Opcode <EA>
Rn (An) (An)+ -(An) (d16,An)
(d8,An,Xn*SF
) xxx.wl
#xxx link.w
Ay,#imm move.w
CCR,Dx move.w
<ea>,CC
R move.w
SR,Dx move.w
<ea>,SR movec Ry,Rc movem.l
<ea>,&list
2(0/1)
1(0/0)
1(0/0)
1(0/0)
7(0/0)
9(0/1)
—
—
—
—
—
—
—
1+n(n/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1+n(n/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1(0/0)
—
7(0/0)
—
—
2 movem.l
&list,<ea> nop pea pulse stop trap trapf trapf.w
trapf.l
unlk wddata
<ea>
#imm
#imm
Ax
<ea>
—
3(0/0)
—
1(0/0)
—
—
1(0/0)
1(0/0)
1(0/0)
2(1/0)
—
1+n(0/n)
—
2(0/1)
—
—
—
—
—
—
—
3(1/0)
—
—
—
—
—
—
—
—
—
—
3(1/0)
—
—
—
—
—
—
—
—
—
—
3(1/0)
1+n(0/n)
—
2(0/1)
—
—
—
—
—
—
—
3(1/0)
4
—
—
3(0/1)
—
—
—
—
—
—
—
4(1/0)
5
—
—
2(0/1)
—
—
—
—
—
—
—
3(1/0) wdebug <ea> — 5(2/0) — — 5(2/0) — —
1 n is the number of registers moved by the MOVEM opcode.
2
If a MOVE.W #imm,SR instruction is executed and imm[13] = 1, the execution time is 1(0/0).
3 The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
4
PEA execution times are the same for (d16,PC).
5
PEA execution times are the same for (d8,PC,Xn*SF).
—
—
—
—
3(0/0)
3
15(1/2)
—
—
—
—
3(1/0)
—
3.12 EMAC Instruction Execution Times
Table 3-18. EMAC Instruction Execution Times
Opcode muls.w
mulu.w
<EA>
<ea>y, Dx
<ea>y, Dx
Rn
4(0/0)
4(0/0)
(An)
6(1/0)
6(1/0)
(An)+
6(1/0)
6(1/0)
Effective Address
-(An) (d16,An)
(d8,An,X n*SF)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
7(1/0)
7(1/0) xxx.wl
6(1/0)
6(1/0)
#xxx
4(1/0)
4(1/0)
MCF5271 Reference Manual, Rev. 2
3-24 Freescale Semiconductor
EMAC Instruction Execution Times
Table 3-18. EMAC Instruction Execution Times (Continued)
Effective Address
Opcode <EA>
Rn (An) (An)+ -(An) (d16,An)
(d8,An,X n*SF) xxx.wl
#xxx muls.l
mulu.l
mac.w
mac.l
<ea>y, Dx
<ea>y, Dx
Ry, Rx, Raccx
Ry, Rx, Raccx msac.w
msac.l
Ry, Rx, Raccx
Ry, Rx, Raccx mac.w
Ry, Rx, <ea>, Rw,
Raccx mac.l
Ry, Rx, <ea>, Rw,
Raccx msac.w
Ry, Rx, <ea>, Rw msac.l
Ry, Rx, <ea>, Rw,
Raccx
4(0/0)
4(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
—
—
—
—
6(1/0)
6(1/0)
—
—
—
—
2(1/0)
2(1/0)
2(1/0)
2(1/0)
6(1/0)
6(1/0)
—
—
—
—
2(1/0)
2(1/0)
2(1/0)
2(1/0)
6(1/0)
6(1/0)
—
—
—
—
2(1/0)
2(1/0)
2(1/0)
2(1/0)
6(1/0)
6(1/0)
—
—
—
—
2(1/0)
1
2(1/0)
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— mov.l
mov.l
mov.l
mov.l
<ea>y, Raccx
Raccy,Raccx
<ea>y, MACSR
<ea>y, Rmask
1(0/0)
1(0/0)
5(0/0)
4(0/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1(0/0)
—
5(0/0)
4(0/0) mov.l
mov.l
<ea>y,Raccext01 1(0/0)
<ea>y,Raccext23 1(0/0)
Raccx,<ea>x 1(0/0)
2
—
—
—
—
—
—
—
—
—
—
—
—
1(0/0)
1(0/0) mov.l
mov.l
mov.l
mov.l
MACSR,<ea>x
Rmask, <ea>x
1(0/0)
1(0/0)
Raccext01,<ea.x
1(0/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— mov.l
Raccext23,<ea>x 1(0/0) — — — — — —
1
2
Effective address of (d16,PC) not supported
Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] = 1---, -11-, --11)
—
—
—
—
—
—
—
—
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
3-25
ColdFire Core
NOTE
The execution times for moving the contents of the Racc,
Raccext[01,23], MACSR, or Rmask into a destination location <ea>x shown in this table represent the best-case scenario when the store instruction is executed and there are no load or M{S}AC instructions in the EMAC execution pipeline. In general, these store operations require only a single cycle for execution, but if preceded immediately by a load, MAC, or MSAC instruction, the depth of the EMAC pipeline is exposed and the execution time is four cycles.
3.13 Branch Instruction Execution Times
Table 3-19. General Branch Instruction Execution Times
Opcod e
<EA> bsr jmp jsr rte rts
<ea>
<ea>
Rn
—
—
—
—
—
(An)
—
3(0/0)
3(0/1)
—
—
(An)+
—
—
—
10(2/0)
5(1/0)
—
—
—
—
—
Effective Address
-(An)
(d16,An)
(d16,PC)
(d8,An,Xi*SF)
(d8,PC,Xi*SF)
3(0/1)
3(0/0)
3(0/1)
—
—
—
4(0/0)
4(0/1)
—
— xxx.wl
—
3(0/0)
3(0/1)
—
—
Table 3-20. BRA, Bcc Instruction Execution Times
Opcode bra bcc
Forward
Taken
2(0/0)
3(0/0)
Forward
Not Taken
—
1(0/0)
Backward
Taken
2(0/0)
2(0/0)
Backward
Not Taken
—
3(0/0)
#xxx
—
—
—
—
—
3.14 ColdFire Instruction Set Architecture Enhancements
This section describes the new opcodes implemented as part of the Revision A+ enhancements to the basic ColdFire ISA.
3-26
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
BITREV
ColdFire Instruction Set Architecture Enhancements
Bit Reverse Register
(Supported Starting with ISA A+)
BITREV
Operation: Bit Reversed Dx → Dx
Assembler Syntax: BITREV.L Dx
Attributes: Size = longword
Instruction
Format:
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
1
6
1
5
0
4
0
3
0
2 1
Register, Dx
0
The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0], new
Dx[30] = old Dx[1], ..., new Dx[0] = old Dx[31].
Condition Codes: Not affected
Instruction Field:
• Register field—Specifies the destination data register, Dx.
BITREV
Opcode present
Freescale Semiconductor
V2, V3 Core (ISA_A)
No
V4 Core (ISA_B)
No
V2 Core (ISA_A+)
Yes
MCF5271 Reference Manual, Rev. 2
3-27
ColdFire Core
BYTEREV
Byte Reverse Register
(Supported Starting with ISA A+)
Operation: Byte Reversed Dx → Dx
Assembler Syntax: BYTEREV.L Dx
Attributes: Size = longword
BYTEREV
Instruction
Format:
15
0
14
0
13
0
12
0
11
0
10
0
9
1
8
0
7
1
6
1
5
0
4
0
3
0
The contents of the destination data register are byte-reversed as defined below:
2 1
Register, Dx
0 new Dx[31:24] new Dx[23:16] new Dx[15:8] new Dx[7:0]
= old Dx[7:0]
= old Dx[15:8]
= old Dx[23:16]
= old Dx[31:24]
Condition Codes: Not affected
Instruction Field:
• Register field—Specifies the destination data register, Dx.
3-28
BYTEREV
Opcode present
V2, V3 Core (ISA_A)
No
V4 Core (ISA_B)
No
V2 Core (ISA_A+)
Yes
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
FF1
ColdFire Instruction Set Architecture Enhancements
Find First One in Register
(Supported Starting with ISA A+)
FF1
Operation: Bit Offset of the First Logical One in Register → Destination
Assembler Syntax: FF1.L Dx
Attributes: Size = longword
Instruction
Format:
15
0
14
0
13
0
12
0
11
0
10
1
9
0
8
0
7
1
6
1
5
0
4
0
3
0
2 1
Destination
Register, Dx
0
The data register, Dx, is scanned, beginning from the most-significant bit (Dx[31]) and ending with the least-significant bit (Dx[0]), searching for the first set bit. The data register is then loaded with the offset count from bit 31 where the first set bit appears, as shown below. If the source data is zero, then an offset of 32 is returned.
Old Dx[31:0]
0b1---- . . . ----
0b01--- . . . ----
0b001-- . . . ----
...
0b00000 . . . 0010
0b00000 . . . 0001
0b00000 . . . 0000
New Dx[31:0]
0x0000 0000
0x0000 0001
0x0000 0002
...
0x0000 001E
0x0000 001F
0x0000 0020
Condition
Codes:
X
—
N
∗
Z
∗
V
0 0 N Set if the msb of the source operand is set; cleared otherwise
Z Set if the source operand is zero; cleared otherwise
V Always cleared
C Always cleared
Instruction Field:
• Destination Register field—Specifies the destination data register, Dx.
FF1
Opcode present
Freescale Semiconductor
V2, V3 Core (ISA_A)
No
V4 Core (ISA_B)
No
V2 Core (ISA_A+)
Yes
MCF5271 Reference Manual, Rev. 2
3-29
ColdFire Core
STRLDSR
Store/Load Status Register
STRLDSR
(Supported Starting with ISA A+)
Operation: If Supervisor State
Then SP - 4 → SP; zero-filled SR → (SP); immediate data → SR
Else TRAP
Assembler Syntax:STRLDSR #<data>
Attributes: Size = word
Instruction
Format:
15
0
0
14
1
1
13
0
0
12
0
0
11
0
0
10
0
1
9
0
8
0
7
1
1 0 1
Immediate Data
1
6
1
5
1
1
4
0
1
3
0
1
2
1
1
1
1
0
0
1
0
Description: Pushes the contents of the Status Register onto the stack and then reloads the
Status Register with the immediate data value. This instruction is intended for use as the first instruction of an interrupt service routine shared across multiple interrupt request levels. It allows the level of the just-taken interrupt request to be stored in memory (using the SR[IML] field), and then masks interrupts by loading the SR[IML] field with 0x7 (if desired). If execution is attempted with bit 13 of the immediate data cleared (attempting to place the processor in user mode), a privilege violation exception is generated. The opcode for STRLDSR is 0x40E7 46FC.
Condition
Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X Set to the value of bit 4 of the immediate operand
N Set to the value of bit 3 of the immediate operand
Z Set to the value of bit 2 of the immediate operand
V Set to the value of bit 1 of the immediate operand
C Set to the value of bit 0 of the immediate operand
3-30
STRLDSR
Opcode present
V2, V3 Core (ISA_A)
No
V4 Core (ISA_B)
No
V2 Core (ISA_A+)
Yes
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
This chapter describes the functionality, microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors.
4.1
Multiply-Accumulate Unit
The MAC design provides a set of DSP operations which can be used to improve the performance of embedded code while supporting the integer multiply instructions of the baseline ColdFire architecture.
The MAC provides functionality in three related areas:
• Signed and unsigned integer multiplies
• Multiply-accumulate operations supporting signed and unsigned integer operands as well as signed, fixed-point, fractional operands
• Miscellaneous register operations
The ColdFire family supports two MAC implementations with different performance levels and capabilities. The original MAC uses a three-stage execution pipeline optimized for 16-bit operands and featuring a 16x16 multiply array with a single 32-bit accumulator. The EMAC features a four-stage pipeline optimized for 32-bit operands, with a fully pipelined 32 × 32 multiply array and four 48-bit accumulators.
The first ColdFire MAC supported signed and unsigned integer operands and was optimized for
16x16 operations, such as those found in a variety of applications including servo control and image compression. As ColdFire-based systems proliferated, the desire for more precision on input operands increased. The result was an improved ColdFire MAC with user-programmable control to optionally enable use of fractional input operands.
EMAC improvements target three primary areas:
• Improved performance of 32 × 32 multiply operations.
• Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges between the accumulator and the pipeline’s general-purpose registers.
• A 48-bit accumulation data path to allow the use of a 40-bit product plus the addition of 8 extension bits to increase the dynamic number range when implementing signal processing algorithms.
The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module, as shown in
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 4-1
Enhanced Multiply-Accumulate Unit (EMAC)
Operand Y Operand X
X
Shift 0,1,-1
+/-
Accumulator(s)
Figure 4-1. Multiply-Accumulate Functionality Diagram
4.2
Introduction to the MAC
The MAC is an extension of the basic multiplier found in most microprocessors. It is typically implemented in hardware within an architecture and supports rapid execution of signal processing algorithms in fewer cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements beyond the scope of any processor architecture and may require full DSP implementation.
To strike a balance between speed, size, and functionality, the ColdFire MAC is optimized for a small set of operations that involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for single-cycle pipelined operations with a possible accumulation after product generation. This functionality is common in many signal processing applications.
The ColdFire core architecture also has been modified to allow an operand to be fetched in parallel with a multiply, increasing overall performance for certain DSP operations.
Consider a typical filtering operation where the filter is defined as in
.
=
∑ k = 1 a ) +
∑ b k k = 0
)
Figure 4-2. Infinite Impulse Response (IIR) Filter
Here, the output y(i) is determined by past output values and past input values. This is the general form of an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies and product summing. To show this point, reduce the above equation to a simple, four-tap FIR filter, shown in
, in which the accumulated sum is a sum of past data values and coefficients.
MCF5271 Reference Manual, Rev. 2
4-2 Freescale Semiconductor
General Operation
=
3
∑
k = 0
( )x i k ) =
Figure 4-3. Four-Tap FIR Filter
)
4.3
General Operation
The MAC speeds execution of ColdFire integer multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations. By executing MULS and
MULU in the MAC, execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early termination that the OEP normally uses if no MAC hardware is present.
The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of the product to or from the value in an accumulator.
Optionally, the product may be shifted left or right by 1 bit before addition or subtraction.
Hardware support for saturation arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions. Multiply-accumulate operations support 16- or 32-bit input operands of the following formats:
• Signed integers
• Unsigned integers
• Signed, fixed-point, fractional numbers
The EMAC is optimized for single-cycle, pipelined 32 × 32 multiplications. For word- and longword-sized integer input operands, the low-order 40 bits of the product are formed and used with the destination accumulator. For fractional operands, the entire 64-bit product is calculated and either truncated or rounded to the most-significant 40-bit result using the round-to-nearest
(even) method before it is combined with the destination accumulator.
For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator.
show relative alignment of input operands, the full 64-bit product, the resulting 40-bit product used for accumulation, and 48-bit accumulator formats.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
4-3
Enhanced Multiply-Accumulate Unit (EMAC)
X
OperandY
OperandX
32
32
Product
40
23 “0”
Extended Product
+
Accumulator
8 40
8 40 8
Extension Byte Upper [7:0] Accumulator [31:0] Extension Byte Lower [7:0]
Figure 4-4. Fractional Alignment
X
OperandY
OperandX
32
32
Product
24 8 32
Extended Product
+
Accumulator
8 8 32
8 8 32
Extension Byte Upper [7:0] Accumulator [31:0]
Extension Byte Lower [7:0]
Figure 4-5. Signed and Unsigned Integer Alignment
Thus, the 48-bit accumulator definition is a function of the EMAC operating mode. Given that each 48-bit accumulator is the concatenation of 16-bit accumulator extension register (ACCextn) contents and 32-bit ACCn contents, the specific definitions are as follows: if MACSR[6:5] == 00/* signed integer mode */
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
MCF5271 Reference Manual, Rev. 2
4-4 Freescale Semiconductor
General Operation if MACSR[6:5] == -1/* signed fractional mode */
Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]} if MACSR[6:5] == 10/* unsigned integer mode */
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
The four accumulators are represented as an array, ACCn, where n selects the register.
Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC instructions have an effective issue rate of 1 cycle, regardless of input operand size or type.
All arithmetic operations use register-based input operands, and summed values are stored internally in an accumulator. Thus, an additional move instruction is needed to store data in a general-purpose register. One new feature found in EMAC instructions is the ability to choose the upper or lower word of a register as a 16-bit input operand. This is useful in filtering operations if one data register is loaded with the input data and another is loaded with the coefficient. Two 16-bit multiply accumulates can be performed without fetching additional operands between instructions by alternating the word choice during the calculations.
The EMAC has four accumulator registers versus the MAC’s single accumulator. The additional registers improve the performance of some algorithms by minimizing pipeline stalls needed to store an accumulator value back to general-purpose registers. Many algorithms require multiple calculations on a given data set. By applying different accumulators to these calculations, it is often possible to store one accumulator without any stalls while performing operations involving a different destination accumulator.
The need to move large amounts of data presents an obstacle to obtaining high throughput rates in
DSP engines. New and existing ColdFire instructions can accommodate these requirements. A
MOVEM instruction can move large blocks of data efficiently by generating line-sized burst references. The ability to simultaneously load an operand from memory into a register and execute a MAC instruction makes some DSP operations such as filtering and convolution more manageable.
The programming model includes a 16-bit mask register (MASK), which can optionally be used to generate an operand address during MAC + MOVE instructions. The application of this register with auto-increment addressing mode supports efficient implementation of circular data queues for memory operands.
The additional MAC status register (MACSR) contains a 4-bit operational mode field and condition flags. Operational mode bits control whether operands are signed or unsigned and whether they are treated as integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding is performed. Negative, zero, and multiple overflow condition flags are also provided.
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Enhanced Multiply-Accumulate Unit (EMAC)
4.4
Memory Map/Register Definition
The EMAC provides the following program-visible registers:
• Four 32-bit accumulators (ACCn = ACC0, ACC1, ACC2, and ACC3)
• Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values for load and store operations (ACCext01 and ACCext23)
• One 16-bit mask register (MASK)
• One 32-bit MAC status register (MACSR) including four indicator bits signaling product or accumulation overflow (one for each accumulator: PAV0–PAV3)
These registers are shown in
.
31 0
MACSR
ACC0
ACC1
ACC2
MAC status register
MAC accumulator 0
MAC accumulator 1
MAC accumulator 2
ACC3 MAC accumulator 3
ACCext01 Extensions for ACC0 and ACC1
ACCext23 Extensions for ACC2 and ACC3
MASK MAC mask register
Figure 4-6. EMAC Register Set
4.4.1
MAC Status Register (MACSR)
MACSR functionality is organized as follows:
• MACSR[11–8] contains one product/accumulation overflow flag per accumulator.
• MACSR[7–4] defines the operating configuration of the MAC unit.
• MACSR[3–0] contains indicator flags from the last MAC instruction execution.
Field
Reset
R/W
31
—
12 11–8
Prod/acc overflow flags
7 6 5
Operational Mode
4 3
PAVx OM
C
S/U F/I
0000_0000_0000_0000_0000_0000_0000_0000
R/T N
R/W
Figure 4-7. MAC Status Register (MACSR)
Table 4-1 describes MACSR fields.
2
Flags
1
Z
0
V EV
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Bits
31–12
11–8
7–4
7
6
5
Name
—
PAVx
OMC
S/U
F/I
Memory Map/Register Definition
Table 4-1. MACSR Field Descriptions
Description
Reserved, should be cleared.
Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a MAC or MSAC instruction is executed, the PAVx flag associated with the destination accumulator is used to form the general overflow flag,
MACSR[V]. Once set, each flag remains set until V is cleared by a MOV.L , MACSR instruction or the accumulator is loaded directly.
Operational Mode Fields
Overflow/saturation mode. Used to enable or disable saturation mode on overflow. If set, the accumulator is set to the appropriate constant on any operation which overflows the accumulator. Once saturated, the accumulator remains unaffected by any other MAC or
MSAC instructions until either the overflow bit is cleared or the accumulator is directly loaded.
Signed/unsigned operations.
In integer mode:
S/U determines whether operations performed are signed or unsigned. It also determines the accumulator value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, an accumulator saturates to the most positive (0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on both the instruction and the value of the product that overflowed.
1 Unsigned numbers. On overflow, if OMC is enabled, an accumulator saturates to the smallest value (0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.
In fractional mode:
S/U controls rounding while storing an accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose register as a 32-bit value.
1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method
when it is moved to a general-purpose register. See Section 4.4.1.1.1, “Rounding .” The
resulting 16-bit value is stored in the lower word of the destination register. The upper word is zero-filled. The accumulator value is not affected by this rounding procedure.
Fractional/integer mode Determines whether input operands are treated as fractions or integers.
0 Integers can be represented in either signed or unsigned notation, depending on the value of S/U.
1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to 1- 2
-15
for 16-bit fractions and -1 to 1 - 2
-31
for 32-bit fractions. See
Section 4.5.2, “Data Representation ."
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Enhanced Multiply-Accumulate Unit (EMAC)
Bits
4
3–0
3
2
1
0
Name
R/T
N
Z
V
EV
Table 4-1. MACSR Field Descriptions (Continued)
Description
Round/truncate mode. Controls the rounding procedure for MOV.L ACCx,Rx, or MSAC.L instructions when operating in fractional mode.
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator.
Additionally, when a store accumulator instruction is executed (MOV.L ACCx,Rx), the 8 lsbs of the 48-bit accumulator logic are simply truncated.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest 40-bit value. If the low-order 24 bits equal 0x80_0000, the upper
40 bits are rounded to the nearest even (lsb = 0) value. See Section 4.4.1.1.1,
.” Additionally, when a store accumulator instruction is executed (MOV.L
ACCx,Rx), the lsbs of the 48-bit accumulator logic are used to round the resulting 16- or
32-bit value. If MACSR[S/U] = 0 and MACSR[R/T] = 1, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] = 1, the low-order 24 bits are used to round the resulting 16-bit fraction.
Flags
Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC,
MSAC, and load operations; it is not affected by MULS and MULU instructions.
Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC,
MSAC, and load operations; it is not affected by MULS and MULU instructions.
Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that the result cannot be represented in the limited width of the EMAC. V is set only if a product overflow occurs or the accumulation overflows the 48-bit structure. V is evaluated on each
MAC or MSAC operation and uses the appropriate PAVx flag in the next-state V evaluation.
Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in integer mode or the 40 lsbs in fractional mode of the destination accumulator. However, the result is still accurately represented in the combined 48-bit accumulator structure.
Although an overflow has occurred, the correct result, sign, and magnitude are contained in the 48-bit accumulator. Subsequent MAC or MSAC operations may return the accumulator to a valid 32/40-bit result.
Table 4-2 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.
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Memory Map/Register Definition
Table 4-2. Summary of S/U, F/I, and R/T Control Bits
S/U F/I R/T
0
0
0
1
0
1
1
1
1
0
1
1
Operational Modes x Signed, integer
0 Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores
1 Signed, fractional
Round on MAC.L and MSAC.L
Round-to-32-bits on accumulator stores x Unsigned, integer
0 Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
1 Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
4.4.1.1
Fractional Operation Mode
This section describes behavior when the fractional mode is used (MACSR[F/I] is set).
4.4.1.1.1
Rounding
When the processor is in fractional mode, there are two operations during which rounding can occur.
• Execution of a store accumulator instruction (MOV.L ACCx,Rx). The lsbs of the 48-bit accumulator logic are used to round the resulting 16- or 32-bit value. If MACSR[S/U] is cleared, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit fraction.
• Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero, multiplying two 32-bit numbers creates a 64-bit product that is truncated to the upper 40 bits; otherwise, it is rounded using round-to-nearest (even) method.
To understand the round-to-nearest-even method, consider the following example involving the rounding of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest 16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L.
• If R0.L is less than 0x8000, the result is truncated to the value of R0.U.
• If R0.L is greater than 0x8000, the upper word is incremented (rounded up).
• If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is based on the lsb of R0.U, so the result is always even (lsb = 0).
— If the lsb of R0.U = 1 and R0.L = 0x8000, the number is rounded up.
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Enhanced Multiply-Accumulate Unit (EMAC)
— If the lsb of R0.U = 0 and R0.L =0x8000, the number is rounded down.
This method minimizes rounding bias and creates as statistically correct an answer as possible.
The rounding algorithm is summarized in the following pseudocode: if R0.L < 0x8000 then Result = R0.U
else if R0.L > 0x8000 then Result = R0.U + 1 else if lsb of R0.U = 0 then Result = R0.U
else Result = R0.U + 1
/* R0.L = 0x8000 */
The round-to-nearest-even technique is also known as convergent rounding.
4.4.1.1.2
Saving and Restoring the EMAC Programming Model
The presence of rounding logic in the output datapath of the EMAC requires that special care be taken during the EMAC’s save/restore process. In particular, any result rounding modes must be disabled during the save/restore process so the exact bit-wise contents of the EMAC registers are accessed. Consider the following memory structure containing the EMAC programming model: struct macState { int acc0; int acc1; int acc2; int acc3; int accext01; int accext02; int mask; int macsr;
} macState;
The following assembly language routine shows the proper sequence for a correct EMAC state save. This code assumes all Dn and An registers are available for use and the memory location of the state save is defined by A7.
EMAC_state_save: move.l macsr,d7 clr.l d0 move.l d0,macsr move.l acc0,d0 move.l acc1,d1 move.l acc2,d2 move.l acc3,d3 move.l accext01,d4 move.l accext23,d5 move.l mask,d6 movem.l #0x00ff,(a7)
; save the macsr
; zero the register to ...
; disable rounding in the macsr
; save the accumulators
; save the accumulator extensions
; save the address mask
; move the state to memory
The following code performs the EMAC state restore:
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Memory Map/Register Definition
EMAC_state_restore: movem.l (a7),#0x00ff move.l #0,macsr move.l d0,acc0 move.l d1,acc1 move.l d2,acc2 move.l d3,acc3 move.l d4,accext01 move.l d5,accext23 move.l d6,mask move.l d7,macsr
; restore the state from memory
; disable rounding in the macsr
; restore the accumulators
; restore the accumulator extensions
; restore the address mask
; restore the macsr
By executing this type of sequence, the exact state of the EMAC programming model can be correctly saved and restored.
4.4.1.1.3
MULS/MULU
MULS and MULU are unaffected by fractional mode operation; operands are still assumed to be integers.
4.4.1.1.4
Scale Factor in MAC or MSAC Instructions
The scale factor is ignored while the MAC is in fractional mode.
4.4.2
Mask Register (MASK)
The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones.
This register performs a simple AND with the operand address for MAC instructions. That is, the processor calculates the normal operand address and, if enabled, that address is then ANDed with
{0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address can be constrained to a certain memory region. This is used primarily to implement circular queues in conjunction with the (An)+ addressing mode.
This feature minimizes the addressing support required for filtering, convolution, or any routine that implements a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be included in all memory effective address calculations. The syntax is as follows:
MAC.sz Ry,RxSF,<ea>y&,Rw
The & operator enables the use of MASK and causes bit 5 of the extension word to be set. The exact algorithm for the use of MASK is as follows:
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Enhanced Multiply-Accumulate Unit (EMAC) if extension word, bit [5] = 1, the MASK bit, then if <ea> = (An) oa = An & {0xFFFF, MASK} if <ea> = (An)+ oa = An
An = (An + 4) & {0xFFFF, MASK} if <ea> =-(An) oa = (An - 4) & {0xFFFF, MASK}
An = (An - 4) & {0xFFFF, MASK} if <ea> = (d16,An) oa = (An + se_d16) & {0xFFFF0x, MASK}
Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For auto-addressing modes of post-increment and pre-decrement, the calculation of the updated An value is also shown.
Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue implementations.
4.5
EMAC Instruction Set Summary
Table 4-3 summarizes EMAC unit instructions.
Table 4-3. EMAC Instruction Summary
Command Mnemonic Description
Multiply Signed
Multiply Unsigned
Multiply Accumulate
Multiply Accumulate with Load
Load Accumulator
Store Accumulator
Copy Accumulator
Load MACSR
Store MACSR
Store MACSR to CCR
MULS <ea>y,Dx
MULU <ea>y,Dx
MAC Ry,RxSF,ACCx
MSAC Ry,RxSF,ACCx
MAC Ry,Rx,<ea>y,Rw,ACCx
MSAC Ry,Rx,<ea>y,Rw,ACCx
MOV.L {Ry,#imm},ACCx
MOV.L ACCx,Rx
MOV.L ACCy,ACCx
MOV.L {Ry,#imm},MACSR
MOV.L MACSR,Rx
MOV.L MACSR,CCR
Multiplies two signed operands yielding a signed result
Multiplies two unsigned operands yielding an unsigned result
Multiplies two operands and adds/subtracts the product to/from an accumulator
Multiplies two operands and combines the product to an accumulator while loading a register with the memory operand
Loads an accumulator with a 32-bit operand
Writes the contents of an accumulator to a CPU register
Copies a 48-bit accumulator
Writes a value to MACSR
Write the contents of MACSR to a CPU register
Write the contents of MACSR to the CCR
Load MAC Mask Reg MOV.L {Ry,#imm},MASK
Store MAC Mask Reg MOV.L MASK,Rx
Writes a value to the MASK register
Writes the contents of the MASK to a CPU register
Load AccExtensions01 MOV.L {Ry,#imm},ACCext01 Loads the accumulator 0,1 extension bytes with a 32-bit operand
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EMAC Instruction Set Summary
Table 4-3. EMAC Instruction Summary (Continued)
Command Mnemonic Description
Load AccExtensions23 MOV.L {Ry,#imm},ACCext23 Loads the accumulator 2,3 extension bytes with a 32-bit operand
Store AccExtensions01 MOV.L ACCext01,Rx Writes the contents of accumulator 0,1 extension bytes into a
CPU register
Store AccExtensions23 MOV.L ACCext23,Rx Writes the contents of accumulator 2,3 extension bytes into a
CPU register
4.5.1
EMAC Instruction Execution Times
The instruction execution times for the EMAC can be found in
Section 3.12, “EMAC Instruction
The EMAC execution pipeline overlaps the AGEX stage of the OEP; that is, the first stage of the
EMAC pipeline is the last stage of the basic OEP. EMAC units are designed for sustained, fully-pipelined operation on accumulator load, copy, and multiply-accumulate instructions.
However, instructions that store contents of the multiply-accumulate programming model can generate OEP stalls that expose the EMAC execution pipeline depth, as in the following: mac.w
Ry, Rx, Acc0 mov.l
Acc0, Rz
The mov.l instruction that stores the accumulator to an integer register (Rz) stalls until the program-visible copy of the accumulator is available.
DSOC
AGEX mac mac
Three-cycle regBusy stall mov mov mov
EMAC EX1
EMAC EX2
EMAC EX3
EMAC EX4
Accumulator 0 mac mac mac mac mov old
Figure 4-8. EMAC-Specific OEP Sequence Stall new
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Enhanced Multiply-Accumulate Unit (EMAC)
In Figure 4-8 , the OEP stalls the store-accumulator instruction for 3 cycles: the depth of the EMAC
pipeline minus 1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is performed, the just-updated accumulator 0 value is available.
As with change or use stalls between accumulators and general-purpose registers, introducing intervening instructions that do not reference the busy register can reduce or eliminate sequence-related store-MAC instruction stalls. In fact, a major benefit of the EMAC is the addition of three accumulators to minimize stalls caused by exchanges between the accumulator(s) and the general-purpose registers.
4.5.2
Data Representation
MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand type.
• Two’s complement signed integer: In this format, an N-bit operand value lies in the range
-2
(N-1)
< operand < 2
(N-1)
- 1. The binary point is right of the lsb.
• Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2
N
- 1. The binary point is right of the lsb.
• Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining bits signify the first N-1 bits after the binary point. Given an N-bit number, a
N-1 a
N-2 a
N-3
... a
2 a
1 a
0
, its value is given by the equation in
.
value = – ( ) +
∑ i = 0
2
( )
⋅ ai
Figure 4-9. Two’s Complement, Signed Fractional Equation
This format can represent numbers in the range -1 < operand < 1 - 2
(N-1)
.
For words and longwords, the largest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or
(1 - 2
-15
); the most positive longword is 0x7FFF_FFFF or (1 - 2
-31
).
4.5.3
MAC Opcodes
MAC opcodes are described in the ColdFire Programmer’s Reference Manual.
Note the following:
• Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that involves the product and the accumulator.
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EMAC Instruction Set Summary
• The overflow (V) flag is handled differently. It is set if the complete product cannot be represented as a 40-bit value (this applies to 32 × 32 integer operations only) or if the combination of the product with an accumulator cannot be represented in the given number of bits. The EMAC design includes an additional product/accumulation overflow bit for each accumulator that are treated as sticky indicators and are used to calculate the V bit on
each MAC or MSAC instruction. See Section 4.4.1, “MAC Status Register (MACSR)
.”
• For the MAC design, the assembler syntax of the MAC (multiply and add to accumulator) and MSAC (multiply and subtract from accumulator) instructions does not include a reference to the single accumulator. For the EMAC, it is expected that assemblers support this syntax and that no explicit reference to an accumulator is interpreted as a reference to
ACC0. These assemblers would also support syntaxes where the destination accumulator is explicitly defined.
• The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where
<<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because a product can overflow, the following guidelines are implemented:
— For unsigned word and longword operations, a zero is shifted into the product on right shifts.
— For signed, word operations, the sign bit is shifted into the product on right shifts unless the product is zero. For signed, longword operations, the sign bit is shifted into the product unless an overflow occurs or the product is zero, in which case a zero is shifted in.
— For all left shifts, a zero is inserted into the lsb position.
The following pseudocode explains basic MAC or MSAC instruction functionality. This example is presented as a case statement covering the three basic operating modes with signed integers, unsigned integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {}, indicates a concatenation operation.
switch (MACSR[6:5])
{
/* MACSR[S/U, F/I] */ case 0: /* signed integers */ if (MACSR.OMC == 0 || MACSR.PAVx == 0) then {
MACSR.PAVx = 0
/* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]} else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]} if (U/Lx == 1) then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}
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Enhanced Multiply-Accumulate Unit (EMAC) else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]}
} else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0]
}
/* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */ if ((product[63:39] != 0x0000_00_0) && (product[63:39] != 0xffff_ff_1)) then { /* product overflow */
MACSR.PAVx = 1
MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then if (product[63] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ if (product[63] == 1) then result[47:0] = 0xffff_8000_0000 else result[47:0] = 0x0000_7fff_ffff
}
/* sign-extend to 48 bits before performing any scaling */ product[47:40] = {8{product[39]}} /* sign-extend */
/* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */
{ case 0: break;
/* no scaling specified */ case 1: /* SF = “<< 1” */ product[40:0] = {product[39:0], 0} break; case 2: /* reserved encoding */ break; case 3: /* SF = “>> 1” */ product[39:0] = {product[39], product[39:1]} break;
} if (MACSR.PAVx == 0) then {if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0]
}
/* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVx = 1
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EMAC Instruction Set Summary
MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVx
MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if ((ACCx[47:31] == 0x0000_0) || (ACCx[47:31] == 0xffff_1)) then MACSR.EV = 0 else MACSR.EV = 1 break; case 1,3: /* signed fractionals */ if (MACSR.OMC == 0 || MACSR.PAVx == 0) then {
MACSR.PAVx = 0 if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], 0x0000} if (U/Lx == 1) then operandX[31:0] = {Rx[31:16], 0x0000} else operandX[31:0] = {Rx[15:0], 0x0000}
} else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0]
}
/* perform the multiply */ product[63:0] = (operandY[31:0] * operandX[31:0]) << 1
/* check for product rounding */ if (MACSR.R/T == 1) then { /* perform convergent rounding */ if (product[23:0] > 0x80_0000) then product[63:24] = product[63:24] + 1 else if ((product[23:0] == 0x80_0000) && (product[24] == 1)) then product[63:24] = product[63:24] + 1
}
/* sign-extend to 48 bits and combine with accumulator */
/* check for the -1 * -1 overflow case */ if ((operandY[31:0] == 0x8000_0000) && (operandX[31:0] == 0x8000_0000)) then product[71:64] = 0x00 else product[71:64] = {8{product[63]}}
/* zero-fill */
/* sign-extend */ if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[71:24] else result[47:0] = ACCx[47:0] + product[71:24]
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Enhanced Multiply-Accumulate Unit (EMAC)
/* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVx = 1
MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x007f_ffff_ff00 else result[47:0] = 0xff80_0000_0000
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVx
MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if ((ACCx[47:39] == 0x00_0) || (ACCx[47:39] == 0xff_1)) then MACSR.EV = 0 else MACSR.EV = 1 break; case 2: /* unsigned integers */ if (MACSR.OMC == 0 || MACSR.PAVx == 0) then {
MACSR.PAVx = 0
/* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {0x0000, Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} if (U/Lx == 1) then operandX[31:0] = {0x0000, Rx[31:16]} else operandX[31:0] = {0x0000, Rx[15:0]}
} else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0]
}
/* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */ if (product[63:40] != 0x0000_00) then { /* product overflow */
MACSR.PAVx = 1
MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */
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EMAC Instruction Set Summary result[47:0] = 0xffff_ffff_ffff
}
/* zero-fill to 48 bits before performing any scaling */ product[47:40] = 0 /* zero-fill upper byte */
/* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */
{ case 0: break;
/* no scaling specified */ case 1: /* SF = “<< 1” */ product[40:0] = {product[39:0], 0} break; case 2: /* reserved encoding */ break; case 3: /* SF = “>> 1” */ product[39:0] = {0, product[39:1]} break;
}
/* combine with accumulator */ if (MACSR.PAVx == 0) then {if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0]
}
/* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVx = 1
MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ result[47:0] = 0xffff_ffff_ffff
}
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVx
MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 break; if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1
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Enhanced Multiply-Accumulate Unit (EMAC)
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Chapter 5
Cache
5.1
Introduction
This chapter describes the MCF5271 cache operation.
5.1.1
Features
• Configurable as instruction, data, or split instruction/data cache
• 8-Kbyte direct-mapped cache
• Single-cycle access on cache hits
• Physically located on the Coldfire core's high-speed local bus
• Nonblocking design to maximize performance
• Separate instruction and data 16-Byte line-fill buffers
• Configurable instruction cache miss-fetch algorithm
5.1.2
Physical Organization
The cache is a direct-mapped single-cycle memory. It may be configured as an instruction cache, a write-through data cache, or a split instruction/data cache. The cache storage is organized as 512 lines, each containing 16 bytes. The memory storage consists of a 512-entry tag array (containing addresses and a valid bit), and a data array containing 8 Kbytes, organized as 2048 × 32 bits.
Cache configuration is controlled by bits in the cache control register (CACR) that is detailed later in this chapter. For the instruction or data-only configurations, only the associated instruction or data line-fill buffer is used. For the split cache configuration, one-half of the tag and storage arrays is used for an instruction cache and one-half is used for a data cache. The split cache configuration uses both the instruction and the data line-fill buffers. The core’s local bus is a unified bus used for both instruction and data fetches. Therefore, the cache can have only one fetch, either instruction or data, active at one time.
For the instruction- or data-only configurations, the cache tag and storage arrays are accessed in parallel: fetch address bits [12:4] addressing the tag array and fetch address bits [12:2] addressing the storage array. For the split cache configuration, the cache tag and storage arrays are accessed in parallel. The msb of the tag array address is set for instruction fetches and cleared for operand fetches; fetch address bits [11:4] provide the rest of the tag array address. The tag array outputs the address mapped to the given cache location along with the valid bit for the line. This address field is compared to bits [31:13] for instruction- or data-only configurations and to bits [31:12] for a split configuration of the fetch address from the local bus to determine if a cache hit has occurred.
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Cache
If the desired address is mapped into the cache memory, the output of the storage array is driven onto the ColdFire core's local data bus, thereby completing the access in a single cycle.
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded into the cache.
The cache also contains separate 16-byte instruction and data line-fill buffers that provide temporary storage for the last line fetched in response to a cache miss. With each fetch, the contents of the associated line fill buffer are examined. Thus, each fetch address examines both the tag memory array and the associated line fill buffer to see if the desired address is mapped into either hardware resource. A cache hit in either the memory array or the associated line-fill buffer is serviced in a single cycle. Because the line fill buffer maintains valid bits on a longword basis, hits in the buffer can be serviced immediately without waiting for the entire line to be fetched.
If the referenced address is not contained in the memory array or the associated line-fill buffer, the cache initiates the required external fetch operation. In most situations, this is a 16-byte line-sized burst reference.
The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is released after the initial access of a miss. Thus, the cache or the SRAM module can service subsequent requests while the remainder of the line is being fetched and loaded into the fill buffer.
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Introduction
31
Local Address Bus
12 4 3 2 1 0 31 4
I or D Line Buffer
Address
External Data[31:0]
I or D Line Buffer Storage
MUX
=
Fill Hit
31
TAG
13
0
511
=
31
DATA
0
0
2047
MUX
Tag Hit
Figure 5-1. Cache Block Diagram
Local Data Bus
5.1.3
Operation
The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches from the ColdFire core and certain memory fetches initiated by the debug module. Typically, the debug module's memory references appear as supervisor data accesses but the unit can be programmed to generate user-mode accesses and/or instruction fetches. The cache processes any fetch access in the normal manner.
5.1.3.1
Interaction with Other Modules
Because both the cache and high-speed SRAM module are connected to the ColdFire core's local data bus, certain user-defined configurations can result in simultaneous fetch processing.
If the referenced address is mapped into the SRAM module, that module will service the request in a single cycle. In this case, data accessed from the cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the cache handles the request in the normal fashion.
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Cache
5.1.3.2
Memory Reference Attributes
For every memory reference the ColdFire core or the debug module generates, a set of “effective attributes” is determined based on the address and the access control registers (ACRs). This set of attributes includes the cacheable/noncacheable definition, the precise/imprecise handling of operand write, and the write-protect capability.
In particular, each address is compared to the values programmed in the ACRs. If the address matches one of the ACR values, the access attributes from that ACR are applied to the reference.
If the address does not match either ACR, then the default value defined in the cache control register (CACR) is used. The specific algorithm is as follows: if (address == ACR0_address including mask)
Effective Attributes = ACR0 attributes
else if (address == ACR1_address including mask)
Effective Attributes = ACR1 attributes
else Effective Attributes = CACR default attributes
5.1.3.3
Cache Coherency and Invalidation
The cache does not monitor ColdFire core data references for accesses to cached instructions.
Therefore, software must maintain instruction cache coherency by invalidating the appropriate cache entries after modifying code segments if instructions are cached.
The cache invalidation can be performed in several ways. For the instruction- or data-only configurations, setting CACR[CINV] forces the entire cache to be marked as invalid. The invalidation operation requires 512 cycles because the cache sequences through the entire tag array, clearing a single location each cycle. For the split configuration, CACR[INVI] and
CACR[INVD] can be used in addition to CACR[CINV] to clear the entire cache, only the instruction half, or only the data half. Any subsequent fetch accesses are postponed until the invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is executed, the cache entry defined by bits [12:4] of the source address register is invalidated, provided CACR[CPDI] is cleared. For the split data/instruction cache configuration, software directly controls bit 12 which selects whether an instruction cache or data cache line is being accessed.
These invalidation operations can be initiated from the ColdFire core or the debug module.
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Introduction
5.1.3.4
Reset
A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting CACR[CINV] before the cache can be enabled.
5.1.3.5
Cache Miss Fetch Algorithm/Line Fills
As discussed in Section 5.1.2, “Physical Organization ,” the cache hardware includes a 16-byte line-fill buffer for providing temporary storage for the last fetched line.
With the cache enabled as defined by CACR[CENB], a cacheable fetch that misses in both the tag memory and the line-fill buffer generates an external fetch. For data misses, the size of the external fetch is always 16 bytes. For instruction misses, the size of the external fetch is determined by the value contained in the 2-bit CLNF field of the CACR and the miss address.
relationship between the CLNF bits, the miss address, and the size of the external fetch.
Table 5-1. Initial Fetch Offset vs. CLNF Bits
CLNF[1:0
]
00
01
1X
00
Line
Line
Line
Longword Address Bits
01
Line
Line
Line
10
Line
Longword
Line
11
Longword
Longword
Line
Depending on the runtime characteristics of the application and the memory response speed, overall performance may be increased by programming the CLNF bits to values {00, 01}.
For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss address is accessed first followed by the remaining three longwords that are accessed by incrementing the longword address in a modulo-16 fashion as shown below:
if miss address[3:2] = 00
fetch sequence = {0x0, 0x4, 0x8, 0xC}
if miss address[3:2] = 01
fetch sequence = {0x4, 0x8, 0xC, 0x0}
if miss address[3:2] = 10
fetch sequence = {0x8, 0xC, 0x0, 0x4}
if miss address[3:2] = 11
fetch sequence = {0xC, 0x0, 0x4, 0x8}
Once an external fetch has been initiated and the data is loaded into the line-fill buffer, the cache maintains a special “most-recently-used” indicator that tracks the contents of the associated
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Cache line-fill buffer versus its corresponding cache location. At the time of the miss, the hardware indicator is set, marking the line-fill buffer as “most recently used.” If a subsequent access occurs to the cache location defined by bits [12:4] (or bits [11:4] for split configurations of the fill buffer address), the data in the cache memory array is now most recently used, so the hardware indicator is cleared. In all cases, the indicator defines whether the contents of the line-fill buffer or the memory data array are most recently used. At the time of the next cache miss, the contents of the line-fill buffer are written into the memory array if the entire line is present, and the line-fill buffer data is still most recently used compared to the memory array.
Generally, longword references are used for sequential instruction fetches. If the processor branches to an odd word address, a word-sized instruction fetch is generated.
For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts of non-cacheable references under control of CACR[CEIB]. With this bit set, a noncacheable instruction fetch is processed as defined by
Table 5-2 . For this condition, the line-fill buffer is
loaded and subsequent references can hit in the buffer, but the data is never loaded into the memory array.
Table 5-2 shows the relationship between CACR bits CENB and CEIB and the type of instruction
fetch.
Table 5-2. Instruction Cache Operation as Defined by CACR
CACR
[CENB]
0
CACR
[CEIB]
0
0
1
1
1
1
X
0
1
Type of
Instruction Fetch
N/A
N/A
Cacheable
Noncacheable
Noncacheable
Description
Cache is completely disabled; all instruction fetches are word or longword in size.
All instruction fetches are word or longword in size
Fetch size is defined by Table 5-1 and contents of the
line-fill buffer can be written into the memory array
All instruction fetches are word or longword in size, and not loaded into the line-fill buffer
Instruction fetch size is defined by Table 5-1 and
loaded into the line-fill buffer, but are never written into the memory array.
5.2
Memory Map/Register Definition
Three supervisor registers define the operation of the cache and local bus controller: the cache control register (CACR) and two access control registers (ACR0, ACR1).
below shows the memory map of the cache and access control registers.
The following lists several keynotes regarding the programming model table:
• The CACR and ACRs can only be accessed in supervisor mode using the MOVEC instruction with an Rc value of 0x002, 0x004 and 0x005, respectively.
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Memory Map/Register Definition
• Addresses not assigned to the registers and undefined register bits are reserved for future expansion. The user should write zeros to these reserved address spaces and read accesses will return zeros.
• The reset value column indicates the register initial value at reset. Certain registers may be uninitialized upon reset; that is, they may contain random values after reset.
• The access column indicates if the corresponding register allows both read/write functionality (R/W), read-only functionality (R), or write-only functionality (W). If a read access to a write-only register is attempted, zeros will be returned. If a write access to a read-only register is attempted, the access will be ignored and no write will occur.
Table 5-3. Memory Map of Cache Registers
Address Name Width Description Reset Value
Access
1
MOVEC with 0x002
MOVEC with 0x004
CACR
ACR0
MOVEC with 0x005
1
Readable through debug
ACR1
32 Cache Control Register
32 Access Control Register 0
32 Access Control Register 1
0x0000_0000
0x0000_0000
0x0000_0000
W
W
W
5.2.1
Registers Description
5.2.1.1
Cache Control Register (CACR)
The CACR controls the operation of the cache. The CACR provides a set of default memory access attributes used when a reference address does not map into the spaces defined by the ACRs.
The CACR is a 32-bit write-only supervisor control register. It is accessed in the CPU address space via the MOVEC instruction with an Rc encoding of 0x002. The CACR can be read when in background debug mode (BDM). At system reset, the entire register is cleared.
31
R
W CENB
Reset 0
30
0
—
29
0
15
R
W
Reset 0
Address
14
0
13
28 27
CPD CFRZ
0 0
12 11
26
0
10
—
25
0
9
24 23 22 21 20
CINV DISI DISD INVI INVD
0 0 0 0 0
8 7 6 5 4
—
0 0 0
CEIB DCM DBWE
0 0 0 0
—
0
DWP EUSP
0 0
MOVEC with 0x002
Figure 5-2. Cache Control Register (CACR)
19
0
0
3
—
18
0
0
2
—
17
0
1
16
0
CLNF
0
0
0
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Cache
Bits
31
30–29
28
27
26–25
24
23
22
Name
CENB
—
CPDI
CFRZ
—
CINV
DISI
DISD
Table 5-4. CACR Field Descriptions
Description
Cache enable.
The memory array of the cache is enabled only if CENB is asserted. This bit, along with the DISI (disable instruction caching) and DISD (disable data caching) bits, control the cache configuration.
0 Cache disabled
1 Cache enabled
Table 5-5 describes cache configuration.
Reserved, should be cleared.
Disable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the cache entry defined by bits [12:4] of the address is invalidated if CPDI = 0. If CPDI = 1, no operation is performed.
0 Enable invalidation
1 Disable invalidation
Cache freeze. This field allows the user to freeze the contents of the cache. When CFRZ is asserted line fetches can be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritten. If a given cache location is invalid, the contents of the line-fill buffer can be written into the memory array while CFRZ is asserted.
0 Normal Operation
1 Freeze valid cache lines
Reserved, should be cleared.
Cache invalidate. The cache invalidate operation is not a function of the CENB state (that is, this operation is independent of the cache being enabled or disabled). Setting this bit forces the cache to invalidate all, half, or none of the tag array entries depending on the state of the DISI, DISD, INVI, and INVD bits. The invalidation process requires several cycles of overhead plus 512 machine cycles to clear all tag array entries and 64256 cycles to clear half of the tag array entries, with a single cache entry cleared per machine cycle.
The state of this bit is always read as a zero. After a hardware reset, the cache must be invalidated before it is enabled.
0 No operation
1 Invalidate all cache locations
Table 5-6 describes how to set the cache invalidate all bit.
Disable instruction caching. When set, this bit disables instruction caching. This bit, along with the CENB (cache enable) and DISD (disable data caching) bits, control the cache configuration. See the CENB definition for a detailed description.
0 Do not disable instruction caching
1 Disable instruction caching
Table 5-5 describes cache configuration and Table 5-6
describes how to set the cache invalidate all bit.
Disable data caching. When set, this bit disables data caching. This bit, along with the
CENB (cache enable) and DISI (disable instruction caching) bits, control the cache configuration. See the CENB definition for a detailed description.
0 Do not disable data caching
1 Disable data caching
Table 5-5 describes cache configuration and Table 5-6
describes how to set the cache invalidate all bit.
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Bits
21
20
19–11
10
9
8
7–6
5
4
3–2
1–0
Memory Map/Register Definition
Name
INVI
INVD
—
CEIB
DCM
DBWE
—
DWP
EUSP
—
CLNF
Table 5-4. CACR Field Descriptions (Continued)
Description
CINV instruction cache only. This bit can not be set unless the cache configuration is split
(both DISI and DISD cleared). For instruction or data cache configurations this bit is a don’t-care. For the split cache configuration, this bit is part of the control for the invalidate all operation. See the CINV definition for a detailed description
Table 5-6 describes how to set the cache invalidate all bit.
CINV data cache only. This bit can not be set unless the cache configuration is split (both
DISI and DISD cleared). For instruction or data cache configurations this bit is a don’t-care.
For the split cache configuration, this bit is part of the control for the invalidate all operation.
See the CINV definition for a detailed description
Table 5-6 describes how to set the cache invalidate all bit.
Reserved, should be cleared.
Cache enable noncacheable instruction bursting. Setting this bit enables the line-fill buffer to be loaded with burst transfers under control of CLNF[1:0] for noncacheable accesses.
Noncacheable accesses are never written into the memory array. See
.
0 Disable burst fetches on noncacheable accesses
1 Enable burst fetches on noncacheable accesses
Default cache mode. This bit defines the default cache mode: 0 is cacheable, 1 is noncacheable. For more information on the selection of the effective memory attributes, see
Section 5.1.3.2, “Memory Reference Attributes
.
0 Caching enabled
1 Caching disabled
Default buffered write enable. This bit defines the default value for enabling buffered writes.
If DBWE = 0, the termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is completed. If DBWE = 1, the write cycle on the local bus is terminated immediately and the operation buffered in the bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus and the external bus. Generally, enabled buffered writes provide higher system performance but recovery from access errors can be more difficult. For the ColdFire core, reporting access errors on operand writes is always imprecise and enabling buffered writes further decouples the write instruction and the signaling of the fault
0 Disable buffered writes
1 Enable buffered writes
Reserved, should be cleared.
Default write protection
0 Read and write accesses permitted
1 Only read accesses permitted
Enable user stack pointer. See
Section 3.2.3.2, “Supervisor/User Stack Pointers (A7 and
," for more information on the dual stack pointer implementation.
0 Disable the processor’s use of the User Stack Pointer
1 Enable the processor’s use of the User Stack Pointer
Reserved, should be cleared.
Cache line fill. These bits control the size of the memory request the cache issues to the
bus controller for different initial instruction line access offsets. See Table 5-1 for external
fetch size based on miss address and CLNF.
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Cache
Table 5-5 shows the relationship between CACR bits CENB, DISI, & DISD and the cache
configuration.
Table 5-5. Cache Configuration as Defined by CACR
CACR
[CENB]
0
1
CACR
[DISI] x
0
CACR
[DISD] x
0
Configuration Description
1
1
0
1
1
0
N/A
Split Instruction/
Data Cache
Cache is completely disabled
4 KByte direct-mapped instruction cache (uses lower half of tag and storage arrays) and 4 KByte direct-mapped write-through data cache (uses upper half of tag and storage arrays)
Instruction Cache 8 KByte direct-mapped instruction cache (uses all of tag and storage arrays)
Data Cache 8 KByte direct-mapped write-through data cache
(uses all of tag and storage arrays)
Table 5-6 shows the relationship between CACR bits DISI, DISD, INVI, & INVD and setting the
cache invalidate all bit.
Table 5-6. Cache Invalidate All as Defined by CACR
CACR
[DISI]
0
CACR
[DISD]
0
0
0
0
1
0
0
0
0
0
1
CACR
[INVI]
0
0
1
1 x x
CACR
[INVD]
0
1
0
1 x x
Configuration Operation
Split Instruction/
Data Cache
Split Instruction/
Data Cache
Split Instruction
Data Cache
Split Instruction/
Data Cache
Invalidate all entries in both 4 KByte instruction cache and 4 KByte data cache
Invalidate only 4 KByte data cache
Invalidate only 4 KByte instruction cache
No invalidate
Instruction Cache Invalidate 8 KByte instruction cache
Data Cache Invalidate 8 KByte data cache
5.2.1.2
Access Control Registers (ACR0, ACR1)
The ACRs provide a definition of memory reference attributes for two memory regions (one per
ACR). This set of effective attributes is defined for every memory reference using the ACRs or the set of default attributes contained in the CACR. The ACRs are examined for every processor memory reference that is not mapped to the SRAM memories.
The ACRs are 32-bit write-only supervisor control register. They are accessed in the CPU address space via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The ACRs can be read when in background debug mode (BDM). At system reset, both registers are cleared.
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Memory Map/Register Definition
NOTE
IPSBAR space cannot be cached. Ensure that ACR[AB] does not fall within this space.
31
R
W
Reset 0
15
R
W EN
Reset 0
Address
Bits
31–24
23–16
15
14–13
12–7
6
30
0
14
29
0
13
28 27
0
12
AB
0
11
26
0
10
25
0
9
24
0
8
23
0
7
22
0
6
21
0
5
20 19
0
AM
0
4 3
18
0
2
17
0
1
16
0
0
0
SM
0 0 0 0
—
0 0 0
CM BWE
0 0 0
—
0
MOVEC with 0x004, MOVEC with 0x005
Figure 5-3. Access Control Registers (ACR0, ACR1)
Table 5-7. ACR Field Descriptions
Name
AB
AM
EN
SM
—
CM
WP
0 0
—
0
Description
Address base. This 8-bit field is compared to address bits [31:24] from the processor's local bus under control of the ACR address mask. If the address matches, the attributes for the memory reference are sourced from the given ACR.
Address mask. This 8-bit field can mask any bit of the AB field comparison. If a bit in the
AM field is set, then the corresponding bit of the address field comparison is ignored.
ACR Enable. The EN bit defines the ACR enable. Hardware reset clears this bit, disabling the ACR.
0 ACR disabled
1 ACR enabled
Supervisor mode. This two-bit field allows the given ACR to be applied to references based on operating privilege mode of the ColdFire processor. The field uses the ACR for user references only, supervisor references only, or all accesses.
00 Match if user mode
01 Match if supervisor mode
1x Match always—ignore user/supervisor mode
Reserved, should be cleared.
Cache mode. This bit defines the cache mode: 0 is cacheable, 1 is noncacheable.
0 Caching enabled
1 Caching disabled
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Cache
Bits
5
4–3
2
1–0
Name
BWE
—
WP
—
Table 5-7. ACR Field Descriptions (Continued)
Description
Buffered write enable. This bit defines the value for enabling buffered writes. If BWE = 0, the termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is completed. If BWE = 1, the write cycle on the local bus is terminated immediately and the operation is then buffered in the bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus and the external bus.
Generally, the enabling of buffered writes provides higher system performance but recovery from access errors may be more difficult. For the V2 ColdFire core, the reporting of access errors on operand writes is always imprecise, and enabling buffered writes simply decouples the write instruction from the signaling of the fault even more.
0 Writes are not buffered.
1 Writes are buffered.
Reserved, should be cleared.
Write protect. The WP bit defines the write-protection attribute. If the effective memory attributes for a given access select the WP bit, an access error terminates any attempted write with this bit set.
0 Read and write accesses permitted
1 Only read accesses permitted
Reserved, should be cleared.
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Chapter 6
Static RAM (SRAM)
6.1
Introduction
This chapter is a description of the on-chip static RAM (SRAM) implementation that covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM.
6.1.1
Features
• One 64-Kbyte SRAM
• Single-cycle access
• Physically located on processor's high-speed local bus
• Memory location programmable on any 0-modulo-64 Kbyte address
• Byte, word, longword address capabilities
6.1.2
Operation
The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. The location of the memory block can be specified to any 0-modulo-64K address within the 4-Gbyte address space. The memory is ideal for storing critical code or data structures or for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can service processor-initiated access or memory-referencing commands from the debug module.
Depending on configuration information, instruction fetches may be sent to both the cache and the
SRAM block simultaneously. If the reference is mapped into the region defined by the SRAM, the
SRAM provides the data back to the processor, and the cache data is discarded. Accesses from the
SRAM module are not cached.
The SRAM is dual-ported to provide DMA or FEC access. The SRAM is partitioned into two physical memory arrays to allow simultaneous access to both arrays by the processor core and another bus master. See
Section 11.3, “Internal Bus Arbitration,” for more information.
6.2
Register Description
The SRAM programming model includes a description of the SRAM base address register
(RAMBAR), SRAM initialization, and power management.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 6-1
Static RAM (SRAM)
6.2.1
SRAM Base Address Register (RAMBAR)
The configuration information in the SRAM base address register (RAMBAR) controls the operation of the SRAM module.
• The RAMBAR holds the base address of the SRAM. The MOVEC instruction provides write-only access to this register.
• The RAMBAR can be read or written from the debug module in a similar manner.
• All undefined bits in the register are reserved. These bits are ignored during writes to the
RAMBAR, and return zeroes when read from the debug module.
• The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are unaffected.
NOTE
Do not confuse this RAMBAR with the SCM RAMBAR in
Section 11.2.1.2, “Memory Base Address Register (RAMBAR).”
Although similar, this core RAMBAR enables core access to the
SRAM memory, while the SCM RAMBAR enables peripheral (e.g.
DMA and FEC) access to the SRAM.
The RAMBAR contains several control fields. These fields are shown in Figure 6-1 .
31
R
W
Reset —
30
—
29
—
28
—
27
—
26
—
25
—
24 23
See Note
BA
— —
22
—
21
—
20
—
19
—
18
—
17
—
15
R
W 0
Reset —
Address
14
0
—
13
0
—
12 11 10 9 8 7
See Note
0 PRI1 PRI0 SPV WP
— — — — —
0
—
CPU + 0x0C05
6
0
—
5 4 3 2 1
C/I SC SD UC UD
— — — — —
Note: W for Core; R/W for Debug
Figure 6-1. SRAM Base Address Register (RAMBAR)
Bits
31–16
15–12
Name
BA
—
16
Table 6-1. RAMBAR Field Descriptions
Description
Base address. Defines the 0-modulo-64K base address of the SRAM module. By programming this field, the SRAM may be located on any 64-Kbyte boundary within the processor’s 4-Gbyte address space.
Reserved, should be cleared.
V
0
—
0
MCF5271 Reference Manual, Rev. 2
6-2 Freescale Semiconductor
Bits
11–10
9
8
7–6
5–1
0
Register Description
Name
PRI1
PRI0
Table 6-1. RAMBAR Field Descriptions (Continued)
Description
Priority bit. PRI1 determines if DMA/FEC or CPU has priority in upper 32k bank of memory.
PRI0 determines if DMA/FEC or CPU has priority in lower 32k bank of memory. If bit is set,
DMA/FEC has priority. If bit is cleared, CPU has priority. Priority is determined according to the following table.
PRI[1:0]
00
01
10
11
Upper Bank Priority Lower Bank Priority
CPU Accesses
CPU Accesses
DMA/FEC Accesses
CPU Accesses
DMA/FEC Accesses
CPU Accesses
DMA/FEC Accesses DMA/FEC Accesses
SPV
WP
—
C/I, SC, SD,
UC, UD
Note: The recommended setting for the priority bits is 00.
Secondary port valid. Allows access by DMA and FEC
0 DMA and FEC access to memory is disabled.
1 DMA and FEC access to memory is enabled.
Note: The BDE bit in the second RAMBAR register must also be set to allow dual port access to the SRAM. For more information, see
Section 11.2.1.2, “Memory Base Address
Write protect. Allows only read accesses to the SRAM. When this bit is set, any attempted write access will generate an access error exception to the ColdFire processor core.
0 Allows read and write accesses to the SRAM module
1 Allows only read accesses to the SRAM module
Reserved, should be cleared.
Address space masks (ASn)
These five bit fields allow certain types of accesses to be “masked,” or inhibited from accessing the SRAM module. The address space mask bits are:
C/I = CPU space/interrupt acknowledge cycle mask
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
V
For each address space bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address space is made, it is inhibited from accessing the SRAM module, and is processed like any other non-SRAM reference.
These bits are useful for power management as detailed in
Valid. A hardware reset clears this bit. When set, this bit enables the SRAM module; otherwise, the module is disabled.
0 Contents of RAMBAR are not valid
1 Contents of RAMBAR are valid
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
6-3
Static RAM (SRAM)
6.2.2
SRAM Initialization
After a hardware reset, the contents of the SRAM module are undefined. The valid bit of the
RAMBAR is cleared, disabling the module. If the SRAM requires initialization with instructions or data, the following steps should be performed:
1. Load the RAMBAR mapping the SRAM module to the desired location within the address space.
2. Read the source data and write it to the SRAM. There are various instructions to support this function, including memory-to-memory move instructions, or the MOVEM opcode.
The MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this opcode generally provides maximum performance.
3. After the data has been loaded into the SRAM, it may be appropriate to load a revised value into the RAMBAR with a new set of attributes. These attributes consist of the write-protect and address space mask fields.
The ColdFire processor or an external emulator using the debug module can perform these initialization functions.
6.2.3
SRAM Initialization Code
The following code segment describes how to initialize the SRAM. The code sets the base address of the SRAM at 0x2000_0000 and then initializes the SRAM to zeros.
RAMBASE EQU $20000000 ;set this variable to $20000000 move.l #RAMBASE+RAMVALID,D0 ;load RAMBASE + valid bit into D0.
movec.l D0, RAMBAR ;load RAMBAR and enable SRAM
The following loop initializes the entire SRAM to zero lea.l move.l
RAMBASE,A0
#16384,D0
;load pointer to SRAM
;load loop counter into D0
SRAM_INIT_LOOP: clr.l (A0)+ subq.l #1,D0 bne.b SRAM_INIT_LOOP
;clear 4 bytes of SRAM
;if done, then exit; else continue looping
MCF5271 Reference Manual, Rev. 2
6-4 Freescale Semiconductor
Register Description
6.2.4
Power Management
As noted previously, depending on the configuration defined by the RAMBAR, instruction fetch and operand read accesses may be sent to the SRAM and cache simultaneously. If the access is mapped to the SRAM module, it sources the read data and the unified cache access is discarded.
If the SRAM is used only for data operands, setting the ASn bits associated with instruction fetches can decrease power dissipation. Additionally, if the SRAM contains only instructions, masking
operand accesses can reduce power dissipation. Table 6-2
shows some examples of typical
RAMBAR settings.
Table 6-2. Typical RAMBAR Setting Examples
Data Contained in SRAM
Instruction Only
Data Only
Both Instructions And Data
RAMBAR[7:0]
0x2B
0x35
0x21
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
6-5
Static RAM (SRAM)
6-6
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Chapter 7
Clock Module
7.1
Introduction
The clock module allows the MCF5271 to be configured for one of several clocking methods.
Clocking modes include internal frequency modulated phase-locked loop (PLL) clocking with either an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device directly. The clock module contains:
• Crystal amplifier and oscillator (OSC)
• Frequency Modulated Phase-locked loop (PLL)
• Reduced frequency divider (RFD)
• Status and control registers
• Control logic
NOTE
Throughout this manual, f sys
refers to the core frequency and f refers to the internal bus frequency.
sys/2
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
7-1
Clock Module
XTAL
EXTAL
0 1
PLL x2
1
0
PLLSEL
1
PLLMODE
0
PLLREF
Oscillator
Clock Module f sys
÷ 2
ColdFire V2 Core
BDM
DMA
SDRAMC
EIM
Chip Selects
Watchdog
PIT
DMA Timers
QSPI
UART
I
2
C
RNG
MDHA
SKHA
FEC
GPIO
Figure 7-1. MCF5271 Clock Connections
7.1.1
Block Diagram
Figure 7-2 shows a block diagram of the entire clock module. The PLL block in this diagram is
expanded in detail in
.
7-2
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
EXTAL
External Clock
XTAL
OSC
Stop Mode
STPMD
Introduction
PLLREF
CLKGEN
CLKMOD[1:0] RSTOUT
Reference
Clock
LOCEN
MFD
PLL
CLKOUT
PLLMODE
LOLRE LOCRE
PLL Clock Out
Scaled PLL Clock Out
Internal Clock
LOCKS
LOCK
LOCS
RFD[2:0]
To Reset
Module
CLKOUT
PLLSEL DISCLK
Internal
Clocks
STOP MODE
PLLMODE
LOCK
FWKUP
Figure 7-2. Clock Module Block Diagram
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
7-3
Clock Module
EXTAL
XTAL OSC
Successive
Approximation
Frequency
Search
PFD/
Charge Pumps
Filter ICO
FM
Control
PLL OUT
MFD
Bus Interface
CLKMOD[1:0]
Control/Status
Registers
Figure 7-3. PLL Block Diagram
7.1.2
Features
Features of the clock module include:
• 8- to 25-MHz reference crystal oscillator
• Current controlled oscillator range from 50 MHz to 150 MHz
• Reduced frequency divider for reduced frequency operation without forcing the PLL to re-lock
• Programmable frequency modulation
• Support for low-power modes
• Self-clocked mode operation
• Separate clock out signal
7.1.3
Modes of Operation
The PLL operational mode must be configured during reset. The CLKMOD[1:0] package pins must be driven to the appropriate state for the desired mode from the time RSTOUT asserts until
it negates. Refer to Table 7-3 for valid states of CLKMOD[1:0]. If CLKMOD[1:0] are not asserted
during reset, the PLL will not default to any mode (so these pins must be hard-tied to power or ground for desired mode).
The clock module can be operated in normal PLL mode with crystal reference, normal PLL mode with external reference, 1:1 PLL mode, or external clock mode.
MCF5271 Reference Manual, Rev. 2
7-4 Freescale Semiconductor
Introduction
7.1.3.1
Normal PLL Mode with Crystal Reference
In normal mode with a crystal reference, the PLL receives an input clock frequency from the crystal oscillator circuit and multiplies the frequency to create the PLL output clock. It can synthesize frequencies ranging from 4x to 18x the reference frequency and has a post divider capable of reducing this synthesized frequency without disturbing the PLL. The user must supply a crystal oscillator that is within the appropriate input frequency range, the crystal manufacture’s recommended external support circuitry, and short signal route from the device to the crystal. In normal mode, the PLL can generate a frequency modulated clock or a non-modulated clock
(locked on a single frequency). The modulation rate, modulation depth, output clock divide ratio
(RFD), and whether the PLL is modulating or not can be programmed by writing to the PLL registers through the bus interface.
7.1.3.2
Normal PLL Mode with External Reference
Same as
Section 7.1.3.1, “Normal PLL Mode with Crystal Reference,” except EXTAL is driven
by an external clock generator rather than a crystal oscillator. However, the input frequency range is the same as the crystal reference. To enter normal mode with external clock Generator reference, the PLL configuration must be set by following the procedure outlined in
7.1.3.3
1:1 PLL Mode
When 1:1 PLL mode is selected, the PLL synthesizes a core clock frequency equal to two times the input reference frequency (f sys
=2 ×f ref
and f sys/2
=f ref
) The post divider is not active and the frequency modulation capability is not available. Further, modulation must not be present on the input reference clock. The input reference frequency is an external clock reference from a master
MCU CLKOUT pin or other external clock generator source. To enter 1:1 PLL mode, the PLL must be set by following the procedure outlined in
Section 7.4.3, “System Clock Generation.”
NOTE
When configured for 1:1 PLL mode, it is imperative that the
CLKOUT clock divider not be changed from its reset state of divide-by-2. Increasing or decreasing this divide ratio will produce unpredictable results from the PLL.
7.1.3.4
External Clock Mode (Bypass Mode)
During external clock mode, the PLL is completely bypassed and the user must supply an external clock on the EXTAL pin. The external clock is used directly to produce the internal core clocks.
Refer to the Hardware Specification document for external clock input requirements. In external clock mode, the analog portion of the PLL is disabled and no clocks are generated at the PLL
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 7-5
Clock Module output. Consequently, frequency modulation is not available. To enter external clock mode, the
PLL must be set by following the procedure outlined in Section 7.4.3, “System Clock Generation.”
NOTE
XTAL must be tied low in external clock mode when reset is asserted.
If it is not, clocks could be suspended indefinitely.
7.1.3.5
Low-power Mode Operation
This subsection describes the operation of the clock module in low-power and halted modes of operation. Low-power modes are described in
the clock module operation in low-power modes.
Table 7-1. Clock Module Operation in Low-power Modes
Low-power Mode
Wait
Clock Operation
Clocks sent to peripheral modules only
Doze
Stop
Clocks sent to peripheral modules only
All system clocks disabled, but clock module continues to run
Mode Exit
Exit not caused by clock module, but normal clocking resumes upon mode exit
Exit not caused by clock module, but normal clocking resumes upon mode exit
Exit not caused by clock module, but clock sources are re-enabled and normal clocking resumes upon mode exit
In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the
CPU, and SRAM are stopped. Each module can disable its clock locally at the module level.
During stop mode, the PLL continues to run. The external CLKOUT signal may be enabled or disabled when the device enters stop mode, depending on the LPCR[STPMD] bit settings.
The external CLKOUT output pin may be disabled to lower power consumption via the
SYNCR[DISCLK] bit. The external CLKOUT pin function is enabled by default at reset.
7.2
External Signal Descriptions
The clock module signals are summarized in Table 7-2
and a brief description follows. For more detailed information, refer to Chapter 14, “Signal Descriptions .”
Table 7-2. Signal Properties
Name
EXTAL
XTAL
CLKOUT
Function
Oscillator or clock input
Oscillator output
Internal bus clock output
MCF5271 Reference Manual, Rev. 2
7-6 Freescale Semiconductor
External Signal Descriptions
Table 7-2. Signal Properties (Continued)
Name
CLKMOD[1:0]
RSTOUT
Function
Clock mode select inputs
Reset signal from reset controller
7.2.1
EXTAL
This input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator.
7.2.2
XTAL
This output is an internal oscillator connection to the external crystal.
7.2.3
CLKOUT
This output reflects the internal bus clock.
7.2.4
CLKMOD[1:0]
The clock mode is selected during reset and reflected in the PLLMODE, PLLSEL, and PLLREF bits of the synthesizer status. Once reset is exited, the clock mode cannot be changed.
The clock mode selection during reset configuration is summarized in
.
Table 7-3. Clock Mode Selection
Signals
Clock Mode
CLKMOD[1] CLKMOD[0]
0
0
0
1
PLL Bypass Mode (external clock mode)
1:1 Mode
1
1 0 Normal mode with external reference
1
1 1 Normal mode with crystal reference
In 1:1 mode for the MCF5271, f sys
= 2 ×f ref_1:1
7.2.5
RSTOUT
The RSTOUT pin is asserted by one of the following:
• Internal system reset signal
• FRCRSTOUT bit in the reset control status register (RCR); see Section 10.3.1, “Reset
.”
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 7-7
Clock Module
7.3
Memory Map/Register Definition
The clock module programming model consists of these registers:
• Synthesizer control register (SYNCR), which defines clock operation
• Synthesizer status register (SYNSR), which reflects clock status
Table 7-4. Clock Module Memory Map
IPSBAR Offset Register Name
0x12_0000 Synthesizer Control Register (SYNCR)
0x12_0004 Synthesizer Status Register (SYNSR)
1
S = CPU supervisor mode access only.
Access
1
S
S
7.3.1
Register Descriptions
This subsection provides a description of the clock module registers.
7.3.1.1
Synthesizer Control Register (SYNCR)
R
W
Reset
31
0
30
0
—
29
0
28
0
27
0
26 25
MFD[2:0]
24
0 0 1
23
—
22
0 0
21 20
RFD[2:0]
19 18 17 16
LOCEN LOLRE LOCRE
0 1 0
W
Reset
15 14 13 12 11 10
R DISCLK LOLIRQ LOCIRQ RATE DEPTH
Address
0 0 0 0 0 0
9
0
8
0
7
0
6
0
IPSBAR + 0x0012_0000
5
0
4
EXP[9:0]
3
0 0
Figure 7-4. Synthesizer Control Register (SYNCR)
0
2
0
0
1
0
0
0
0
7-8
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Bits
31–27
26–24
23–22
21–19
18
17
Memory Map/Register Definition
Table 7-5. SYNCR Field Descriptions
Name Description
Reserved
MFD[2:0] Multiplication factor divider. The MFD bits control the value of the divider in the PLL feedback loop. The value specified by the MFD bits establish the multiplication factor applied to the reference frequency. The bit field encoding is shown in row one of the table below.
Note: Frequency modulation should be disabled (see DEPTH bits) prior to making a change to the MFD.
The following table illustrates the system frequency multiplier of the reference frequency
1
in normal PLL mode.
MFD[2:0]
000
(4x)
2
001
(6x)
(3)
010
(8x)
011
(10x)
100
(12x)
101
(14x)
110
(16x)
111
(18x)
000 ( ÷ 1)
001 ( ÷ 2)
010 ( ÷ 4) 3
011 ( ÷ 8)
100 ( ÷ 16)
101 ( ÷ 32)
110 ( ÷ 64)
4
2
1
1/2
1/4
1/8
1/16
6
3
3/2
3/4
3/8
3/16
3/32
8
4
2
1
1/2
1/4
1/8
10
5
5/2
5/4
5/8
5/16
5/32
12
6
3
3/2
3/4
3/8
3/16
14
7
7/2
7/4
7/8
7/16
7/32
16
8
4
2
1
1/2
1/4
18
9
9/2
9/4
9/8
9/16
9/32
1
2
3
111 ( ÷ 128) 1/32 3/64 1/16 5/64 3/32 7/64 1/8 9/64 f sys
= f ref
× 2(MFD + 2)/2 RFD
; f ref
× 2(MFD + 2) ≤ 150MHz, f sys/2
≤ 75MHz
MFD = 000 not valid for f ref
< 3 MHz
Default value out of reset
—
RFD
Reserved
Reduced frequency divider field. The binary value written to RFD[2:0] is the PLL frequency divisor. See table in MFD bit description. Changing RFD[2:0] does not affect the PLL or cause a relock delay. Changes in clock frequency are synchronized to the next falling edge of the current core clock. To avoid surpassing the allowable core operating frequency, write to RFD[2:0] only when the LOCK bit is set.
Note: In external clock mode, the RFD bits have no affect.
LOCEN Enables the loss-of-clock function. LOCEN does not affect the loss-of-lock function.
0 Loss-of-clock function disabled
1 Loss-of-clock function enabled
Note: In external clock mode, the LOCEN bit has no effect
.
LOLRE Loss-of-lock reset enable. This bit determines how the integration module handles a loss-of-lock indication. When operation in normal or 1:1 mode, the PLL must be locked before setting the LOLRE bit. Otherwise reset is immediately asserted.
0 Ignore loss-of-clock – no reset
1 Reset on loss-of-lock
Note: In external clock mode, the LOLRE bit has no effect
.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 7-9
Clock Module
Bits
16
15
14
13
12
11–10
9–0
Table 7-5. SYNCR Field Descriptions (Continued)
Name Description
LOCRE Loss-of-clock reset enable. Determines how the system handles a loss-of-clock condition.
When the LOCEN bit is clear, LOCRE has no effect. If the LOCS flag in SYNSR indicates a loss-of-clock condition, setting the LOCRE bit causes an immediate reset. To prevent an immediate reset, the LOCRE bit must be cleared before entering stop mode with the PLL disabled.
0 No reset on loss-of-clock
1 Reset on loss-of-clock
Note: In external clock mode, the LOCRE bit has no effect.
DISCLK Disable CLKOUT. This bit determines whether CLKOUT is active. When CLKOUT is disabled it is driven low.
0 CLKOUT driven normally
1 CLKOUT driven low (disabled).
LOLIRQ Loss-of-lock interrupt request. This bit determines if a loss-of-lock is ignored or if an interrupt is requested. When operating in normal or 1:1 PLL mode, the PLL must be locked before setting the LOLIRQ bit. Otherwise an interrupt is immediately requested.
0 Ignore loss-of-lock – no interrupt requested
1 Request interrupt on loss-of-lock
Note: In external clock mode, the LOLIRQ bit has no effect.
LOCIRQ Loss-of-clock interrupt request. This bit determines if a loss-of-clock is ignored or if an interrupt is requested. LOCIRQ has no effect when LOCEN is cleared. If the LOCF flag in
SYNSR indicates a loss-of-clock condition, setting (or having previously set) the LOCIRQ bit causes an interrupt to be immediately requested.
0 Ignore loss-of-clock – no interrupt requested
1 Request interrupt on loss-of-clock
Note: In external clock mode, the LOCIRQ bit has no effect.
RATE Modulation rate. This bit controls the rate of frequency modulation applied to the core frequency. Changing the rate by writing to the RATE bit will initiate the FM calibration sequence.
0 F m
1 F m
= F ref
= F ref
/ 80
/ 40
Note: Frequency modulation should be disabled prior to making a change to the RATE.
DEPTH Frequency modulation depth and enable.This bit field controls depth and enables the frequency modulation. When set to a value other than 0x0, the frequency modulation is automatically enabled.
00 Modulation Depth (% of f sys/2
01 Modulation Depth (% of f sys/2
10 Modulation Depth (% of f sys/2
11 Reserved
) = 0
) = 1.0 ± 0.2
) = 2.0 ± 0.2
Note: Frequency modulation should be disabled prior to making a change to the DEPTH.
EXP Expected difference value. Writing to this field enables Frequency Modulation (FM). This bit field holds the expected value of the difference between the reference and feedback counters. See
Section 7.4.5, “Frequency Modulation Depth Calibration,” for details on how
to calculate this value. Entering FM calibration mode requires the user to program the EXP field.
7-10
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
7.3.1.2
Synthesizer Status Register (SYNSR)
In the SYNSR, only the LOLF and LOCF flag bits are writeable. Writes to bits other than LOLF and LOCF have no effect.
31
R
W
Reset 0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
—
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
R
15 14 13
—
12 11 10 9 8 7
LOLF LOC MODE
1
6
PLL
SEL
1
5
PLL
REF
1
4
LOCKS
1
3 2 1
LOCK
2
LOCF CAL
DONE
0
CAL
PASS
W
Reset 0 0 0 0 0 0 0 0 See Note 1
Address IPSBAR + 0x0012_0004
1
2
Reset state determined during reset configuration
Reset state determined during reset
Figure 7-5. Synthesizer Status Register (SYNSR)
See
Note 2
0 0 0
Bits
31–10
9
8
Name
—
LOLF
LOC
Table 7-6. SYNSR Field Descriptions
Description
Reserved
Loss-of-lock flag. This bit provides the interrupt request flag. To clear the flag, write a 1 to this bit. Writing 0 has no effect.
This flag will not be set and an interrupt will not be requested under any one of the following conditions: (1) loss-of-lock caused by system reset, (2) writing to the SYNCR to modify the
MFD bits, or (3) enabling frequency modulation. The only way to clear this flag is to reset the part or write a 1 to this bit.
0 Interrupt service not requested
1 Interrupt service requested
Loss-of-clock status. This bit is an indication of whether a loss-of-clock condition is present when operating in normal and 1:1 PLL modes. If LOC = 0, the system clocks are operating normally. If LOC = 1, the system clocks have failed due to a reference failure or a PLL failure. If the read of the LOC bit and the loss-of-clock condition occur simultaneously, the bit does not reflect the current loss-of-clock condition. If a loss-of-clock condition occurs which sets this bit and the clocks later return to normal, this bit will be cleared.
A loss-of-clock condition can only be detected if LOCEN = 1. See
Note: LOC is always cleared in external clock mode.
0 Clocks are operating normally
1 Clocks are not operating normally.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 7-11
Clock Module
Bits
7
6
5
4
3
2
Table 7-6. SYNSR Field Descriptions (Continued)
Name Description
PLLMODE Clock mode. This bit is determined at reset and indicates which clock mode the system is utilizing (see
). See
Section 7.4.3, “System Clock Generation,” for details on how
to configure the system clock mode during reset.
0 External clock mode
1 PLL clock mode
PLLSEL PLL mode select. This bit is determined at reset and indicates which mode the PLL
operates in. PLLSEL is cleared in 1:1 PLL mode and external clock mode. See Chapter 10,
,” for details on how to configure the system clock mode during reset.
1 Normal PLL mode (see
0 1:1 PLL mode
PLLREF PLL clock reference source. Configured at reset and reflects the PLL reference source in normal PLL mode as shown in
1 Crystal clock reference
0 External clock reference
LOCKS Sticky indication of PLL lock status. The lock detect function sets the LOCKS bit when the
PLL achieves lock after:
• A system reset
• A write to SYNCR that changes the MFD[2:0] bits
• Frequency modulation is enabled
When the PLL loses lock, LOCKS is cleared. When the PLL relocks, LOCKS remains cleared until one of the three listed events occurs.
Furthermore, reading the LOCKS bit at the same time that the PLL loses lock does not reflect the current loss-of-lock condition.
In external clock mode, LOCKS remains cleared after reset. In normal PLL mode and 1:1
PLL mode, LOCKS is set after reset.
0 PLL loss-of-lock since last system reset or MFD change or currently not locked due to exit from STOP with FWKUP set
1 No unintentional PLL loss-of-lock since last system reset or MFD change
LOCK
LOCF
PLL lock status bit. Set when the PLL is locked. PLL lock occurs when the synthesized frequency is within approximately 0.75 percent of the programmed frequency. The PLL loses lock when a frequency deviation of greater than approximately 1.5 percent occurs.
Reading the LOCK bit at the same time that the PLL loses lock or acquires lock does not reflect the current condition of the PLL. The power-on reset circuit uses the LOCK bit as a condition for releasing reset.
If operating in external clock mode, LOCK remains cleared after reset.
0 PLL not locked
1 PLL locked
Loss-of-clock flag. This bit provides the interrupt request flag. Write a 1 to this bit to clear the flag. Writing 0 has no effect. Asserting reset will clear the flag. This flag is sticky in the sense that if clocks return to normal after the flag has been set, the bit will remain set until cleared by either writing 1 or asserting reset.
0 Interrupt service not requested
1 Interrupt service request
7-12
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Bits
1
0
Functional Description
Table 7-6. SYNSR Field Descriptions (Continued)
Name Description
CALDONE Calibration complete. This bit indicates whether the calibration sequence has been completed since the last time frequency modulation was enabled. If CALDONE = 0, the calibration sequence is either in progress or modulation is disabled. If CALDONE=1 then the calibration sequence has been completed, and frequency modulation is operating.
0 Calibration not complete
1 Calibration complete
CALPASS Calibration passed. The CALPASS bit tells whether the calibration routine was successful.
CALPASS CALDONE
0
1
1
1 unsuccessful successful
When the calibration routine is initiated, CALPASS is set and remains set until either modulation is disabled (by clearing the DEPTH bits in the SYNCR) or a failure occurs within the frequency modulation calibration sequence.
0 Calibration unsuccessful
1 Calibration successful
Table 7-7. System Clock Modes
PLLMODE:PLLSEL:PLLREF
000
100
110
111
Clock Mode
External clock mode (bypass PLL)
1:1 PLL mode
Normal PLL mode with external clock reference
Normal PLL mode with crystal reference
7.4
Functional Description
This subsection provides a functional description of the clock module.
7.4.1
System Clock Modes
The system clock source is determined during reset (see Table 7-3 and
). The values of the CLKMOD signals are latched during reset and are of no importance after reset is negated. If
CLKMOD1 or CLKMOD0 is changed during a reset other than power-on reset, the internal clocks may glitch as the system clock source is changed between external clock mode and PLL clock mode. Whenever CLKMOD1 or CLKMOD0 is changed in reset, an immediate loss-of-lock condition occurs.
Table 7-8 shows the clock-out frequency to clock-in frequency relationships for the possible
system clock modes. Refer to
Section 7.1.3, “Modes of Operation,” for details on each mode.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 7-13
Clock Module
Table 7-8. Clock Out and Clock In Relationships
System Clock Mode
Normal PLL clock mode
PLL Options
1
- without frequency modulation enabled: f sys
=
2f ref
)
-------------------------------------------
2
RFD
Cross-Reference
Section 7.1.3.1, “Normal PLL Mode with
Crystal Reference” and Section 7.1.3.2,
“Normal PLL Mode with External Reference”
1:1 PLL clock mode
External clock mode
- with frequency modulation: f sys
= f × MFD 2
2
RFD
±
--------------------------------------------------------f sys/2
= 2 × f ref_1:1 f sys/2
= f ref
Section 7.1.3.3, “1:1 PLL Mode”
Section 7.1.3.4, “External Clock Mode
1 f f ref
= input reference frequency sys/2
= CLKOUT frequency
MFD ranges from 0 to 7
RFD ranges from 0 to 7 f ref
∆F m
in external clock mode must not exceed 150MHz
= f sys/2
× k
where k = 2
±0.6, 4±0.6, or 6±0.6%.
7.4.2
Clock Operation During Reset
In external clock mode, the system is static and does not recognize reset until clocks are applied to EXTAL and XTAL.
In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input reference clock to the PLL begins operating within the limits given in the electrical specifications.
If a PLL failure causes a reset, the system enters reset using the reference clock. Then the system clock source changes to the PLL operating in SCM. If SCM is not functional, the system becomes static. Alternately, if the LOCEN bit in SYNCR is cleared when the PLL fails, the system becomes static. If external reset is asserted, the system cannot enter reset unless the PLL is capable of operating in SCM.
7.4.2.1
Power-On Reset (POR)
When a POR is detected, the PLL registers will be initialized to their default state. The PLL will not begin operating until the VDDPLL POR signal has negated. At this point, the PLL will begin operating in SCM until a valid reference clock becomes present as indicated by the loss-of-clock circuit. Refer to
Section 10.4.1.1, “Power-On Reset ,” for more information.
MCF5271 Reference Manual, Rev. 2
7-14 Freescale Semiconductor
Functional Description
7.4.2.2
External Reset
Once POR for both the device and the VDDPLL supplies have negated, the PLL will begin its lock detect algorithm. However, if a valid reference is not present, the PLL will continue to operate in
SCM until one is present. The system will not come out of reset until a valid reference is present
and the PLL has acquired lock at the default MFD (see Table 7-5
for the default MFD value).
Following the initial lock with the default MFD, the MFD in the SYNCR may be modified for the desired operating frequency. If the PLL is not able to lock due to an MFD and crystal frequency combination that attempts to force the current controlled oscillator (ICO) outside of its operating range, reset will not negate.
Refer to Section 10.4.1.1, “Power-On Reset ,” for more information.
NOTE
When running in an unlocked state, the clocks generated by the PLL are not guaranteed to be stable and may exceed the maximum specified frequency of the device. It is always recommended that the
RFD be used as described in
to insulate the system from any potential frequency overshoot of the PLL clocks.
7.4.3
System Clock Generation
In normal PLL clock mode, the default core frequency is one and a half times (1.5x) the reference frequency after reset. The RFD[2:0] and MFD[2:0] bits in the SYNCR select the frequency multiplier with default values of RFD = 0b010 (
÷4) and MFD = 0b001 (×6) (see Table 7-5
).
When programming the PLL, do not exceed the maximum system clock frequency listed in the electrical specifications. Use this procedure to accommodate the frequency overshoot that occurs when the MFD bits are changed. If frequency modulation is going to be enabled, the maximum allowable frequency must be reduced by the programmed ∆F m
.
1. Determine the appropriate value for the MFD and RFD fields in the SYNCR; remember to include the ∆F m
if frequency modulation is enabled. The amount of jitter in the system clocks can be minimized by selecting the maximum MFD factor that can be paired with an
RFD factor to provide the required frequency. See Table 7-5
.
2. Write a value of RFD factor (from step 1) + 1 to the RFD field of the SYNCR.
3. If frequency modulation is enabled (by writing to the EXP bit field), disable frequency modulation by writing 0x0 to the DEPTH field of the SYNCR.
4. If programming the MFD, write the MFD value from step 1 to the SYNCR. If enabling frequency modulation, skip this step.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 7-15
Clock Module
5. Monitor the LOCK flag in SYNSR. When the PLL achieves lock, write the RFD value from step 1 to the RFD field of the SYNCR. This changes the system clocks frequency to the required frequency.
6. If frequency modulation was enabled initially, it can be re-enabled following the steps
listed in Section 7.4.4, “Programming the Frequency Modulation.”
NOTE
Keep the maximum system clock frequency below the limit given in the Electrical Characteristics.
7.4.4
Programming the Frequency Modulation
Frequency modulation is useful for spreading the energy over a broader frequency spectrum in order to reduce EMI.
In normal PLL clock mode, the default synthesis mode is without frequency modulation enabled.
When frequency modulation (FM) is enabled three parameters must be set to generate the desired level of modulation: the RATE, DEPTH, and EXP bit fields of the SYNCR. RATE and DEPTH determine the modulation rate and the modulation depth. The EXP field controls the FM calibration routine described in
Section 7.4.5, “Frequency Modulation Depth Calibration.”
The equation that shows how to obtain the values to be programmed for EXP is as follows (see
Section 7.4.5, “Frequency Modulation Depth Calibration,”
for details):
EXP =
( 2 (
100
)×M×P )
Figure 7-6 illustrates the affects of the parameters and the modulation waveform built into the
modulation hardware. The modulation waveform is always a triangle wave and its shape is not programmable.
Note, the modulation rates given are specific to a reference frequency of 8 MHz.
F mod
= F ref
⁄ Q where Q = {40,80} giving modulation rates of 200 kHz, and 100 kHz. Therefore, the utilization of a non 8 MHz reference will result in scaled modulation rates.
The following steps should be used for proper programming of the frequency modulation mode.
These steps ensure proper operation of the calibration routine and prevent frequency overshoot from the sequence.
1. Determine the appropriate value for the EXP field, based upon the selected MFD and desired depth, in the synthesizer control register (SYNCR), as shown in the equation above.
Write this value to the EXP field of the SYNCR. The MFD should be programmed to the appropriate value prior to Step 2.
2. Disable modulation by clearing the DEPTH field in the SYNCR.
3. Monitor LOCK bit. Do not proceed until the PLL is locked in non-modulation mode.
MCF5271 Reference Manual, Rev. 2
7-16 Freescale Semiconductor
Functional Description
4. Write a value of RFD = RFD + 1 to the RFD field of the SYNCR to ensure the maximum system frequency is not exceeded during the calibration routine.
5. Program the desired modulation rates and depths to the RATE and DEPTH fields in the
SYNCR. This action initiates the calibration sequence.
6. Allow time for the calibration sequence. Wait for the PLL to lock (the LOCK bit to set in the SYNSR). At this time CALDONE should be asserted. CALPASS will be asserted if the calibration was successful. If not, the calibration can be re-initiated by repeating from step 2. When the PLL achieves lock, write the desired RFD value.
Please note that the frequency modulation system is dependent upon several factors. The accuracies of the VDDPLL/VSSPLL voltage, of the crystal oscillator frequency, and of the manufacturing variation.
For example, if a 5% accurate supply voltage is utilized, then a 5% modulation depth error will result. If the crystal oscillator frequency is skewed from 8MHz, the resulting modulation frequency will be proportionally skewed. Finally, the error due to the manufacturing and environment variation alone can cause the frequency modulation depth error to be greater than
20%.
f
F max
∆Fm t
∆Fm
F min
∆t = -----------mod
Fmax = f
Fmin = f sys/2
+ {1%, 2%} sys/2
- {1%, 2%}
Fmod = Fref/Q where Q = {40, 80}
Figure 7-6. Frequency Modulation Waveform
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 7-17
Clock Module
7.4.5
Frequency Modulation Depth Calibration
The frequency modulation calibration system tunes a reference current into the modulation D/A so that the modulation depth (F max
and F min
) remains within specification. Frequency modulation should be disabled prior to making a change to either the MFD, DEPTH, or RATE. Upon enabling frequency modulation a new calibration sequence is performed. A change to MFD, DEPTH, or
RATE while in modulation will invalidate calibration results.
Entering the FM calibration mode requires the user to program the EXP field of the SYNCR.
Values for EXP can be found using the following equation:
EXP =
( 2 × MFD 2
100
)×M×P )
Example:
For the value of MFD = 4, the number of reference clock cycles to be counted (M) would
for a complete list of values to be used for the variable (M) based on MFD setting. To obtain a percent modulation (P) of 1%, the EXP field would have to be set at:
EXP = ( 2 ( )×480×1 = 57.6
Rounding this value to the closest integer yields the value of 58 that should be entered into the EXP field for this example.
This routine will correct for process variations, but as temperature can change after the calibration has been performed, variation due to temperature drift is not eliminated. This system is also voltage dependent, so if supply voltages change after the sequence takes place, error incurred will not be corrected. The calibration system reuses the two counters in the lock detect circuit: the reference and feedback counters. The reference counter is still clocked by the reference clock, but the feedback counter is clocked by the ICO clock.
When the calibration routine is initiated (writing to the DEPTH bits), the CALPASS status bit is immediately set and the CALDONE status bit is immediately cleared.
When calibration is induced the ICO is given time to settle. Then both the feedback and reference counters start counting. Full ICO clock cycles are counted by the feedback counter during this time to give the initial center frequency count. When the reference counter has counted to the programmed number of reference count cycles, the input to the feedback counter is disabled and the result is placed in the COUNT0 register. The calibration system then enables modulation at programmed ∆F m
. The ICO is given time to settle. Both counters are reset and restarted. The feedback counter begins to count full ICO clock cycles again to obtain the delta-frequency count.
When the reference counter has counted to the new programmed number of reference count cycles, the feedback counter is stopped again.
The delta-frequency count minus the center frequency count (COUNT0) results in a delta count proportional to the reference current into the modulation D/A. That delta count is subtracted from the expected value given in the EXP field of the SYNCR register resulting in an error count. The
MCF5271 Reference Manual, Rev. 2
7-18 Freescale Semiconductor
Functional Description sign of this error count determines the direction taken by the calibration D/A to update the calibration current. After obtaining the error count for the present iteration, both counters are cleared. The stored count of COUNT0 is preserved while a new feedback count is obtained, and the process to determine the error count is repeated. The calibration system repeats this process eight times, once for each bit of the calibration D/A.
After the last decision is made the CALDONE bit of the SYNSR is set. If an error occurs during the calibration routine, then CALPASS is immediately cleared. If the routine completed successfully then CALPASS remains set.
Figure 7-7 shows a block diagram of the calibration circuitry and its associated registers.
Figure 7-8 shows a flow chart showing the steps taken by the calibration circuit.
Count 0 Expected (EXP) Error (ERR)
Reference Counter
Control
ICO Counter
13
13
10
13 A B
10
A–B= delta count
10
C D
C–D=error count
Figure 7-7. FM Auto-Calibration Data Flow
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
7-19
Clock Module
Enter Calibration
Mode; Set PCALPASS=1
For MFD=0,1: M=960.
For MFD=2,3,4: M=480.
For MFD=5,6,7: M=240.
Count M reference clock cycles. Store value of feedback counter in CAL0.
Enable FM. N=7.
CAL[N] = 1
Allow system 3 ×384 reference counts to settle.
Count M reference clock cycles. CALX = value in feedback counter.
A
N=0?
NO
N=N-1
YES
CALDONE=1
DONE let DIFF=CALX-CAL0
DIFF>0
YES let ERR=DIFF-EXP
NO
PCALPASS=0
ERR>0
NO
YES
CAL[N]=0
A
7-20
Figure 7-8. FM Auto-calibration Flow Chart
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Functional Description
7.4.6
PLL Operation
In PLL mode, the PLL synthesizes the system clocks. The PLL can multiply the reference clock frequency by 4x to 18x, provided that the system clock frequency remains within the range listed in the electrical specifications. For example, if the reference frequency is 8 MHz, the PLL can synthesize frequencies of 32 MHz to 144 MHz. In addition, the RFD can reduce the system frequency by dividing the output of the PLL. The RFD is not in the feedback loop of the PLL, so changing the RFD divisor does not affect PLL operation. Finally, the PLL can be frequency modulated to reduce electromagnetic interference often associated with clock circuitry.
Figure 7-9 shows the external support circuitry for the crystal oscillator with example component
values. Actual component values depend on crystal specifications.
C1
C2
8-MHz Crystal Configuration
C1 = C2 = 16 pF
RF
≥ 1 MΩ
RS = 470
Ω
VSSPLL EXTAL XTAL VSSPLL
ON-CHIP
RF
RS
Figure 7-9. Crystal Oscillator Example
The following subsections describe each major block of the PLL. Refer to Figure 7-10 to see how
these functional sub-blocks interact.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
7-21
Clock Module
Lock
Detect
Loss of
Clock Detect
LOCK
LOC
FM
Modulation
Control
Charge
Pump
EXTAL reference clock feedback
PFD up down
ICO
ICO clkout
Charge
Pump
VDDPLL / VSSPLL
Filter
MFD
VDDI / VSSI
Figure 7-10. Frequency Modulated PLL Block Diagram
7.4.6.1
Phase and Frequency Detector (PFD)
The PFD is a dual-latch phase-frequency detector. It compares both the phase and frequency of the reference and feedback clocks. The reference clock comes from either the crystal oscillator or an external clock source.
The feedback clock comes from one of the following:
• CLKOUT in 1:1 PLL mode
• ICO output divided by two if CLKOUT is disabled in 1:1 PLL mode
• ICO output divided by the MFD in normal PLL mode
When the frequency of the feedback clock equals the frequency of the reference clock, the PLL is frequency-locked. If the falling edge of the feedback clock lags the falling edge of the reference clock, the PFD pulses the UP signal. If the falling edge of the feedback clock leads the falling edge of the reference clock, the PFD pulses the DOWN signal. The width of these pulses relative to the reference clock depends on how much the two clocks lead or lag each other. Once phase lock is achieved, the PFD continues to pulse the UP and DOWN signals for very short durations during each reference clock cycle. These short pulses continually update the PLL and prevent the frequency drift phenomenon known as dead-banding. “Dead-band” is a term used to describe the minimum amount of phase error between the reference and feedback clocks that a phase detector cannot correct.
MCF5271 Reference Manual, Rev. 2
7-22 Freescale Semiconductor
Functional Description
7.4.6.2
Charge Pump/Loop Filter
In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode the current magnitude of the charge pump varies with the MFD as shown in
Table 7-9. Charge Pump Current and MFD in Normal Mode Operation
Charge Pump Current
1X
2X
4X
MFD
0 ≤ MFD < 2
2 ≤ MFD < 6
6 ≤ MFD
The UP and DOWN signals from the PFD control whether the charge pump applies or removes charge, respectively, from the loop filter. The filter is integrated on the chip.
7.4.6.3
Current Controlled Oscillator (ICO)
The current into the ICO controls the frequency of the ICO output. The frequency-to-current relationship (ICO gain) is positive.
7.4.6.4
Multiplication Factor Divider (MFD)
When the PLL is not in 1:1 PLL mode, the MFD divides the output of the ICO and feeds it back to the PFD. The PFD controls the ICO frequency via the charge pump and loop filter such that the reference and feedback clocks have the same frequency and phase. Thus, the frequency of the input to the MFD, which is also the output of the ICO, is the reference frequency multiplied by the same amount that the MFD divides by. For example, if the MFD divides the ICO frequency by six, the PLL is frequency locked when the ICO frequency is six times the reference frequency. The presence of the MFD in the loop allows the PLL to perform frequency multiplication, or synthesis.
In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication factor is two.
7.4.6.5
PLL Lock Detection
The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when frequency lock is achieved. Phase lock is inferred by the frequency relationship, but is not guaranteed. The LOCK flag in the SYNSR reflects the PLL lock status. A sticky lock flag, LOCKS, is also provided.
The lock detect function uses two counters. One is clocked by the reference and the other is clocked by the PLL feedback. When the reference counter has counted N cycles, its count is compared to that of the feedback counter. If the feedback counter has also counted N cycles, the process is repeated for N + K counts. Then, if the two counters still match, the lock criteria is relaxed by one count and the system is notified that the PLL has achieved frequency lock.
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Freescale Semiconductor 7-23
Clock Module
After lock is detected, the lock circuit continues to monitor the reference and feedback frequencies using the alternate count and compare process. If the counters do not match at any comparison time, then the LOCK flag is cleared to indicate that the PLL has lost lock. At this point, the lock criteria is tightened and the lock detect process is repeated.
The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL tries to lock. Alternating between tight and relaxed lock criteria prevents the lock detect function from randomly toggling between locked and non-locked status due to phase sensitivities.
Figure 7-11 shows the sequence for detecting locked and non-locked conditions.
In external clock mode, the PLL is disabled and cannot lock.
Start with Tight Lock
Criteria
Reference Count
≠ Feedback Count
Loss-of-Lock Detected
Set Tight Lock Criteria and Notify System of Loss of Lock Condition
Reference Count
≠ Feedback Count
Count N
Reference Cycles and Compare
Number of Feedback
Cycles Elapsed
Reference Count =
Feedback Count = N
In Same Count/Compare Sequence
Count N + K
Reference Cycles and Compare Number of Feedback Cycles
Elapsed
Lock Detected.
Set Relaxed Lock
Condition and Notify
System of Lock
Condition
Figure 7-11. Lock Detect Sequence
Reference Count =
Feedback Count = N + K
IN Same Count/Compare Sequence
7.4.6.6
PLL Loss-of-Lock Conditions
Once the PLL acquires lock after reset, the LOCK and LOCKS flags are set. If the MFD is changed, or if an unexpected loss-of-lock condition occurs, the LOCK and LOCKS flags are cleared. While the PLL is in the non-locked condition, the system clocks continue to be sourced from the PLL as the PLL attempts to relock. Consequently, during the relocking process, the system clocks frequency is not well defined and may exceed the maximum system frequency, violating the system clock timing specifications.
However, once the PLL has relocked, the LOCK flag is set. The LOCKS flag remains cleared if the loss-of-lock is unexpected. The LOCKS flag is set when the loss-of-lock is caused by changing
MCF5271 Reference Manual, Rev. 2
7-24 Freescale Semiconductor
Functional Description
MFD. If the PLL is intentionally disabled during stop mode, then after exit from stop mode, the
LOCKS flag reflects the value prior to entering stop mode once lock is regained.
7.4.6.7
PLL Loss-of-Lock Reset
If the LOLRE bit in the SYNCR is set, a loss-of-lock condition asserts reset. Reset reinitializes the
LOCK and LOCKS flags. Therefore, software must read the LOL bit in the reset status register
(RSR) to determine if a loss-of-lock caused the reset. See Section 10.3.2, “Reset Status Register
To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock.
In external clock mode, the PLL cannot lock. Therefore, a loss-of-lock condition cannot occur, and the LOLRE bit has no effect.
7.4.6.8
PLL Loss-of-Lock Interrupt Request
The PLL provides the ability to request an interrupt when a loss-of-lock condition occurs by programming the LOLIRQ bit in the SYNCR. An interrupt is requested by the PLL if LOLIRQ is set.
In external clock mode, the PLL cannot lock. Therefore, a loss-of-lock condition cannot occur, and the LOLIRQ bit has no effect.
7.4.6.9
Loss-of-Clock Detection
The LOCEN bit in the SYNCR enables the loss-of-clock detection circuit to monitor the input clocks to the phase and frequency detector (PFD). When either the reference or feedback clock frequency falls below the minimum frequency (see electrical specification for this value), the loss-of-clock circuit sets the sticky LOCF bit, and non-sticky LOC bit, in the SYNSR.
In external clock mode, the loss-of-clock circuit is disabled.
7.4.6.10 Loss-of-Clock Reset
The clock module can assert a reset when a loss-of-clock or loss-of-lock occurs. When a loss-of-clock condition is recognized, reset is asserted if the LOCRE bit in SYNCR is set. The
LOCS bit in SYNSR is cleared after reset. Therefore, the LOC bit must be read in the RSR to determine that a loss-of-clock condition occurred. LOCRE has no effect in external clock mode.
To exit reset in PLL mode, the reference must be present, and the PLL must acquire lock.
Reset initializes the clock module registers to a known startup state as described in Section 7.3,
“Memory Map/Register Definition .”
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Freescale Semiconductor 7-25
Clock Module
7.4.6.11 Loss-of-Clock Interrupt Request
When a loss-of-clock condition is detected, the PLL will request an interrupt if the LOCIRQ bit in the SYNCR is set. The LOCIRQ bit has no affect in external clock mode or if LOCEN is cleared.
7.4.6.12 Alternate Clock Selection
Depending on which clock source fails, the loss-of-clock circuit switches the system clocks source to the remaining operational clock. The alternate clock source generates the system clocks until reset is asserted. As
Table 7-10 shows, if the reference fails, the PLL goes out of lock and into
self-clocked mode (SCM). The PLL remains in SCM until the next reset. When the PLL is operating in SCM, the system frequency depends on the value in the RFD field. The SCM system frequency stated in electrical specifications assumes that the RFD has been programmed to binary
000. If the loss-of-clock condition is due to PLL failure, the PLL reference becomes the system clocks source until the next reset, even if the PLL regains and relocks.
Table 7-10. Loss-of-Clock Summary
Clock
Mode
System Clock Source
Before Failure
Reference Failure Alternate
Clock Selected by LOC
Circuit
1
Until Reset
PLL Failure Alternate
Clock Selected by LOC
Circuit Until Reset
PLL PLL PLL self-clocked mode PLL reference
None
1
The LOC circuit monitors the reference and feedback inputs to the PFD. See Figure 7-10
.
NA
A special loss-of-clock condition occurs when both the reference and the PLL fail. The failures may be simultaneous, or the PLL may fail first. In either case, the reference clock failure takes priority and the PLL attempts to operate in SCM. If successful, the PLL remains in SCM until the next reset. If the PLL cannot operate in SCM, the system remains static until the next reset. Both the reference and the PLL must be functioning properly to exit reset.
7.4.6.13 Loss-of-Clock in Stop Mode
Table 7-11 shows the resulting actions for a loss-of-clock in Stop Mode when the device is being
clocked by the various clocking methods.
Table 7-11. Stop Mode Operation (Sheet 1 of 5)
MODE
In
EXT X X X X X X
Expected
PLL
Action at
Stop
—
PLL Action
During Stop
—
Lose reference clock
MODE
Out
EXT
Stuck
0
—
0
—
0
—
Comments
MCF5271 Reference Manual, Rev. 2
7-26 Freescale Semiconductor
Functional Description
Table 7-11. Stop Mode Operation (Sheet 2 of 5) (Continued)
MODE
In
Expected
PLL
Action at
Stop
NRM 0 0 0 Off Off 0 Lose lock, f.b. clock, reference clock
NRM X 0 0 Off Off 1 Lose lock, f.b. clock, reference clock
PLL Action
During Stop
Regain
No regain
MODE
NRM
Out
Stuck
Regain clocks, but don’t regain lock
SCM–> unstable
NRM
No reference clock regain
SCM–>
Stuck
‘LK
—
1
—
‘LC
—
Comments
0–>‘LK 0–>1 1–>‘LC Block LOCS and
LOCKS until clock and lock respectively regain; enter
SCM regardless of LOCEN bit until reference regained
0–> 0–> 1–> Block LOCS and
LOCKS until clock and lock respectively regain; enter
SCM regardless of LOCEN bit
— — —
NRM 0 0 0 Off On 0 Lose lock
No f.b. clock regain
Regain NRM ‘LK 1 ‘LC Block LOCKS from being cleared
NRM 0 0 0 Off On 1 Lose lock
Lose reference clock or no lock regain
Lose reference clock, regain
No lock regain
Stuck
NRM
Unstable
NRM
‘LK
—
1
— —
‘LC
0–>‘LK 0–>1 ‘LC
Block LOCKS from being cleared
Block LOCKS until lock regained
Lose reference clock or no f.b. clock regain
Lose reference clock, regain
Stuck
Unstable
NRM
— — —
0–>‘LK 0–>1 ‘LC LOCS not set because
LOCEN = 0
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Freescale Semiconductor 7-27
Clock Module
MODE
In
Table 7-11. Stop Mode Operation (Sheet 3 of 5) (Continued)
NRM 0 0 0 On On 0
Expected
PLL
Action at
Stop
—
PLL Action
During Stop
MODE
Out
— NRM
Lose lock or clock Stuck
Lose lock, regain NRM
Lose clock and lock, regain
NRM
0
0
‘LK
—
1
1
1
—
‘LC
—
‘LC
‘LC
Comments
LOCS not set because
LOCEN = 0
NRM 0 0 0 On On 1 —
NRM X X 1 Off X X Lose lock, f.b. clock, reference clock
NRM 0 0 1 On On X —
NRM 1 0 0 Off Off 0 Lose lock, f.b. clock, reference clock
NRM 1 0 0 Off On 0 Lose lock, f.b. clock
—
Lose lock
NRM
Unstable
NRM
Lose lock, regain NRM
Lose clock Stuck
Lose clock, regain without lock
Unstable
NRM
Lose clock, regain with lock
NRM
RESET RESET
— NRM
Lose lock or clock RESET
Regain
No regain
Regain
NRM
Stuck
NRM
‘LK
0
1 ‘LC
0–>1 ‘LC
0
—
0
1
—
‘LC
—
0–>1 ‘LC
0
—
1
—
‘LC
— Reset immediately
‘LK
‘LK
—
‘LK
—
—
1
1
1
—
—
—
‘LC
— Reset immediately
‘LC REF not entered during stop;
SCM entered during stop only during oscillator startup
—
‘LC REF mode not entered during stop
— No f.b. clock or lock regain
Lose reference clock
Stuck
SCM 0 0 1 Wakeup without lock
MCF5271 Reference Manual, Rev. 2
7-28 Freescale Semiconductor
Table 7-11. Stop Mode Operation (Sheet 4 of 5) (Continued)
MODE
In
Expected
PLL
Action at
Stop
NRM 1 0 0 Off On 1 Lose lock, f.b. clock
PLL Action
During Stop
MODE
Out
Regain f.b. clock Unstable
NRM
0–>‘LK 0–>1 ‘LC
Functional Description
Comments
REF mode not entered during stop
NRM 1 0 0 On On 0 —
No f.b. clock regain
Lose reference clock
—
Lose reference clock
Lose f.b. clock
Stuck
SCM
NRM
SCM
REF
0
‘LK
0
0
—
0
1
0
X
—
1
—
‘LC
1
1
Wakeup without lock
Wakeup without lock
Wakeup without lock
NRM 1 0 0 On On 1 —
Lose lock Stuck
Lose lock, regain NRM clock
—
Lose reference
Lose f.b. clock
NRM
SCM
REF
0
‘LK
0
—
0
1
1
0
— —
‘LC
‘LC
1
X 1
Wakeup without lock
Wakeup without lock
NRM 1 0 1 On On X —
NRM 1 1 X Off X X Lose lock, f.b. clock, reference clock
NRM 1 1 0 On On 0 —
Lose lock Unstable
NRM
— NRM
Lose lock or clock RESET
RESET
—
Lose clock
RESET
NRM
RESET
Lose lock Stuck
Lose lock, regain NRM
0
‘LK
—
—
‘LK
—
0
—
0–>1 ‘LC
1
—
—
‘LC
— Reset immediately
— Reset immediately
1
—
1
—
‘LC
— Reset immediately
—
‘LC
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
7-29
Clock Module
Table 7-11. Stop Mode Operation (Sheet 5 of 5) (Continued)
MODE
In
Expected
PLL
Action at
Stop
PLL Action
During Stop
MODE
Out
Comments
NRM 1 1 0 On On 1 — —
Lose clock
NRM
RESET
‘LK
—
1
—
‘LC
— Reset immediately
0–>1 ‘LC
NRM 1 1 1 On On X —
Lose lock Unstable
NRM
Lose lock, regain NRM
— NRM
Lose clock or lock RESET
0
0
‘LK
—
1
1
—
‘LC
‘LC
— Reset immediately
REF 1 0 0 X X X — —
Lose reference clock
REF
Stuck
0
—
X
—
1
—
SCM 1 0 0 On On 0 — —
Lose reference clock
SCM
SCM
0 0 1 Wakeup without lock
Note:
PLL = PLL enabled during STOP mode.
OSC = Oscillator enabled during STOP mode.
MODES
NRM = normal PLL crystal clock reference or normal PLL external reference or PLL 1:1 mode. During PLL 1:1 or normal external reference mode, the oscillator is never enabled. Therefore, during these modes, refer to the OSC = On case regardless of
STPMD values.
EXT=external clock mode
REF=PLL reference mode due to losing PLL clock or lock from NRM mode
SCM=PLL self-clocked mode due to losing reference clock from NRM mode
RESET= immediate reset
LOCKS
‘LK= expecting previous value of LOCKS before entering stop
0–>‘LK= current value is 0 until lock is regained which then will be the previous value before entering stop
0–> = current value is 0 until lock is regained but lock is never expected to regain
LOCS
‘LC=expecting previous value of LOCS before entering stop
1–>‘LC= current value is 1 until clock is regained which then will be the previous value before entering stop
1–> =current value is 1 until clock is regained but CLK is never expected to regain
7.5
Interrupts
Refer to Section 7.4.6.8, “PLL Loss-of-Lock Interrupt Request,”
“Loss-of-Clock Interrupt Request.”
MCF5271 Reference Manual, Rev. 2
7-30 Freescale Semiconductor
Chapter 8
Power Management
8.1
Introduction
This chapter explains the low-power operation of the MCF5271.
8.1.1
Features
The following features support low-power operation.
• Four modes of operation: Run, Wait, Doze, and Stop
• Ability to shut down most peripherals independently
• Ability to shut down the external CLKOUT pin
8.2
Memory Map/Register Definition
The PM programming model consists of one register:
• The low-power control register (LPCR) specifies the low-power mode entered when the
STOP instruction is issued, and controls clock activity in this low-power mode.
Table 8-1. Chip Configuration Module Memory Map
IPSBAR Offset [31:24] [23:16] [15:8] [7:0]
Access
1
0x00_0010 Core Reset Status
Register (CRSR)
2
Core Watchdog
Control Register
(CWCR)
Chip Configuration Register (CCR)
3
Low-Power
Interrupt Control
Register (LPICR)
Core Watchdog
Service Register
(CWSR)
S
0x11_0004 Reserved Low-Power Control
Register (LPCR)
S
1
2
3
S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.
The CRSR, CWCR, and CWSR are described in the System Control Module. They are shown here only to warn against accidental writes to these registers when accessing the LPICR.
The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to this register when accessing the LPCR.
8.2.1
Register Descriptions
The following subsection describes the PM registers.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 8-1
Power Management
8.2.1.1
Low-Power Interrupt Control Register (LPICR)
Implementation of low-power stop mode and exit from a low-power mode via an interrupt require communication between the CPU and logic associated with the interrupt controller. The LPICR is an 8-bit register that enables entry into low-power stop mode, and includes the setting of the interrupt level needed to exit a low-power mode.
NOTE
The setting of the low-power mode select (LPMD) field in the power management module’s low-power control register (LPCR) determines which low-power mode the device enters when a STOP instruction is issued.
If this field is set to enter stop mode, then the ENBSTOP bit in the
LPICR must also be set.
The following is the sequence of operations needed to enable this functionality:
1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired low-power mode) and loading the appropriate interrupt priority level.
2. At the appropriate time, the processor executes the privileged STOP instruction. Once the processor has stopped execution, it asserts a specific Processor Status (PST) encoding.
Issuing the STOP instruction when the LPICR[ENBSTOP] bit is set causes the SCM to enter stop mode.
3. The entry into a low-power mode is processed by the low-power mode control logic, and the appropriate clocks (usually those related to the high-speed processor core) are disabled.
4. After entering the low-power mode, the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests. The device waits for an event to generate an interrupt request with a priority level greater than the value programmed in
LPICR[XLPM_IPL[2:0]].
NOTE
Only a fixed (external) interrupt can bring a device out of stop mode.
To exit from other low-power modes, such as doze or wait, either fixed or programmable interrupts may be used; however, the module generating the interrupt must be enabled in that particular low-power mode.
5. Once an appropriately high interrupt request level arrives, the interrupt controller signals its presence, and the SCM responds by asserting the request to exit low-power mode.
6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.
7. With the processor clocks enabled, the core processes the pending interrupt request.
MCF5271 Reference Manual, Rev. 2
8-2 Freescale Semiconductor
Memory Map/Register Definition
Bits
7
6–4
3–0
W
Reset
7
R ENBSTOP
0
6 5
XLPM_IPL[2:0]
4 3
0
2
0
1
0
0
0
0 0 0 0 0 0 0
Address IPSBAR + 0x00_0012
Figure 8-1. Low-Power Interrupt Control Register (LPICR)
Table 8-2. LPICR Field Description
Name Description
ENBSTOP Enable low-power stop mode.
0 Low-power stop mode disabled
1 Low-power stop mode enabled. Once the core is stopped and the signal to enter stop mode is asserted, processor clocks can be disabled.
XLPM_IPL
[2:0]
—
Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the low-power mode.Refer to
Reserved, should be cleared.
.
XLPM_IPL[2:0]
000
001
010
011
100
101
11x
Table 8-3. XLPM_IPL Settings
Interrupts Level Needed to Exit Low-Power Mode
Any interrupt request exits low-power mode
Interrupt request levels [2-7] exit low-power mode
Interrupt request levels [3-7] exit low-power mode
Interrupt request levels [4-7] exit low-power mode
Interrupt request levels [5-7] exit low-power mode
Interrupt request levels [6-7] exit low-power mode
Interrupt request level [7] exits low-power mode
8.2.1.2
Low-Power Control Register (LPCR)
The LPCR controls chip operation and module operation during low-power modes.
R
W
Reset
7
LPMD
6 5
0
4
0
3
STPMD
2
0
1
0
0 0 0 0 0 0 0
Address IPSBAR + 0x11_0007
Figure 8-2. Low-Power Control Register (LPCR)
0
0
0
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 8-3
Power Management
Bits
7–6
5–4
3
2–0
Name
LPMD
Table 8-4. LPCR Field Descriptions
Description
Low-power mode select. Used to select the low-power mode the chip enters once the
ColdFire CPU executes the STOP instruction. These bits must be written prior to instruction execution for them to take effect. The LPMD[1:0] bits are readable and writable in all modes. Below illustrates the four different power modes that can be configured with the LPMD bit field.
LPMD[1:0]
11
10
01
00
Mode
STOP
WAIT
DOZE
RUN
Note: If LPCR[LPMD] is cleared, then the MCF5271 will stop executing code upon issue of a STOP instruction. However, no clocks will be disabled.
Reserved, should be cleared.
—
STPMD CLKOUT stop mode. Controls CLKOUT operation during stop mode.
0 CLKOUT enabled during stop mode.
1 CLKOUT disabled during stop mode.
— Reserved, should be cleared.
8.3
Functional Description
The functions and characteristics of the low-power modes, and how each module is affected by, or affects these modes are discussed in this section.
8.3.1
Low-Power Modes
The system enters a low-power mode by executing a STOP instruction. Which mode the device actually enters (either stop, wait, or doze) depends on what is programmed in LPCR[LPMD].
Entry into any of these modes idles the CPU with no cycles active, powers down the system and stops all internal clocks appropriately. During stop mode, the system clock is stopped low.
For entry into stop mode, the LPICR[ENBSTOP] bit must be set before a STOP instruction is issued.
A wakeup event is required to exit a low-power mode and return to run mode. Wakeup events consist of any of these conditions:
• Any type of reset
• Any valid, enabled interrupt request
Exiting from low power mode via an interrupt request requires:
MCF5271 Reference Manual, Rev. 2
8-4 Freescale Semiconductor
Functional Description
• An interrupt request whose priority is higher than the value programmed in the XLPM_IPL field of the LPICR.
• An interrupt request whose priority higher than the value programmed in the interrupt priority mask (I) field of the core’s status register.
• An interrupt request from a source which is not masked in the interrupt controller’s interrupt mask register.
• An interrupt request which has been enabled at the module of the interrupt’s origin.
8.3.1.1
Run Mode
Run mode is the normal system operating mode. Current consumption in this mode is related directly to the system clock frequency.
8.3.1.2
Wait Mode
Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU to exit from wait mode.
8.3.1.3
Doze Mode
Doze mode affects the CPU in the same manner as wait mode, except that each peripheral defines individual operational characteristics in doze mode. Peripherals which continue to run and have the capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode. Peripherals which are stopped will restart operation on exit from doze mode as defined for each peripheral.
8.3.1.4
Stop Mode
Stop mode affects the CPU in the same manner as the wait and doze modes, except that all clocks to the system are stopped and the peripherals cease operation.
Stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation.
The following subsections specify the operation of each module while in and when exiting low-power modes.
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MCF5271 Reference Manual, Rev. 2
8-5
Power Management
NOTE
Entering stop mode will disable the SDRAMC including the refresh counter. If SDRAM is used, then code is required to insure proper
entry and exit from stop mode. See Section 8.3.2.4, “SDRAM
” for more information.
8.3.1.5
Peripheral Shut Down
Most peripherals may be disabled by software in order to cease internal clock generation and remain in a static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description for further details). A peripheral may be disabled at any time and will remain disabled during any low-power mode of operation.
8.3.2
Peripheral Behavior in Low-Power Modes
8.3.2.1
ColdFire Core
The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any low-power mode.
8.3.2.2
Static Random-Access Memory (SRAM)
SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power mode.
8.3.2.3
System Control Module (SCM)
The SCM’s core watchdog timer can bring the device out of all low-power modes except stop mode. In stop mode, all clocks stop, and the core watchdog does not operate.
When enabled, the core watchdog can bring the device out of low-power mode via a core watchdog interrupt. This system setup must meet the conditions specified in
” for the core watchdog interrupt to bring the part out of low-power mode.
8.3.2.4
SDRAM Controller (SDRAMC)
SDRAM Controller operation is unaffected by either the wait or doze modes; however, the
SDRAMC is disabled by stop mode. Since all clocks to the SDRAMC are disabled by stop mode, the SDRAMC will not generate refresh cycles.
To prevent loss of data the SDRAMC should be placed in self-refresh mode by setting DCR[IS] before entering stop mode. The SDRAM self-refresh mode allows the SDRAM to enter a low-power state where internal refresh operations are used to maintain the integrity of the data stored in the SDRAM.
MCF5271 Reference Manual, Rev. 2
8-6 Freescale Semiconductor
Functional Description
When stop mode is exited clearing the DCR[IS] bit will cause the SDRAM to exit the self-refresh mode and allow bus cycles to the SDRAM to resume.
NOTE
The SDRAM is inaccessible while in the self-refresh mode.
Therefore, if stop mode is used the vector table and any interrupt handlers that could wake the processor should not be stored in or attempt to access SDRAM.
8.3.2.5
Chip Select Module
In wait and doze modes, the chip select module continues operation but does not generate interrupts; therefore it cannot bring a device out of a low-power mode. This module is stopped in stop mode.
8.3.2.6
DMA Controller (DMA0–DMA3)
In wait and doze modes, the DMA controller is capable of bringing the device out of a low-power mode by generating an interrupt either upon completion of a transfer or upon an error condition.
The completion of transfer interrupt is generated when DMA interrupts are enabled by the setting of the DCR[INT] bit, and an interrupt is generated when the DSR[DONE] bit is set. The interrupt upon error condition is generated when the DCR[INT] bit is set, and an interrupt is generated when either the CE, BES or BED bit in the DSR becomes set.
The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode.
8.3.2.7
UART Modules (UART0, UART1, and UART2)
In wait and doze modes, the UART may generate an interrupt to exit the low-power modes.
• Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART functions.
• The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode.
In stop mode, the UARTs stop immediately and freeze their operation, register values, state machines, and external pins. During this mode, the UART clocks are shut down. Coming out of stop mode returns the UARTs to operation from the state prior to the low-power mode entry.
8.3.2.8
I 2 C Module
When the I
2
C Module is enabled by the setting of the I2CR[IEN] bit and when the device is not in stop mode, the I
2
C module is operable and may generate an interrupt to bring the device out of a low-power mode. For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and the setting of the I2SR[IIF] generates the interrupt signal to the CPU and interrupt controller. The
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 8-7
Power Management setting of I2SR[IIF] signifies either the completion of one byte transfer or the reception of a calling address matching its own specified address when in slave receive mode.
In stop mode, the I
2
C Module stops immediately and freezes operation, register values, and external pins. Upon exiting stop mode, the I
2
C resumes operation unless stop mode was exited by reset.
8.3.2.9
Queued Serial Peripheral Interface (QSPI)
In wait and doze modes, the queued serial peripheral interface (QSPI) may generate an interrupt to exit the low-power modes.
• Clearing the QSPI enable bit (SPE) disables the QSPI function.
• The QSPI is unaffected by wait mode and may generate an interrupt to exit this mode.
In stop mode, the QSPI stops immediately and freezes operation, register values, state machines, and external pins. During this mode, the QSPI clocks are shut down. Coming out of stop mode returns the QSPI to operation from the state prior to the low-power mode entry.
8.3.2.10 DMA Timers (DTIM0–DTIM3)
In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power mode.
This interrupt can be generated when the DMA Timer is in either input capture mode or reference compare mode.
In input capture mode, where the capture enable (CE) field of the timer mode register (DTMR) has a non-zero value and the DMA enable (DMAEN) bit of the DMA timer extended mode register
(DTXMR) is cleared, an interrupt is issued upon a captured input. In reference compare mode, where the output reference request interrupt enable (ORRI) bit of DTMR is set and the
DTXMR[DMAEN] bit is cleared, an interrupt is issued when the timer counter reaches the reference value.
DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes. Upon exiting stop mode, the timer will resume operation unless stop mode was exited by reset.
8.3.2.11 Interrupt Controllers (INTC0, INTC1)
The interrupt controller is not affected by any of the low-power modes. All logic between the input sources and generating the interrupt to the processor will be combinational to allow the ability to wake up the CPU processor during low-power stop mode when all system clocks are stopped.
An interrupt request will cause the CPU to exit a low-power mode only if that interrupt’s priority level is at or above the level programmed in the interrupt priority mask field of the CPU’s status register (SR). The interrupt must also be enabled in the interrupt controller’s interrupt mask register as well as at the module from which the interrupt request would originate.
MCF5271 Reference Manual, Rev. 2
8-8 Freescale Semiconductor
Functional Description
8.3.2.12 Fast Ethernet Controller (FEC)
In wait and doze modes, the FEC may generate an interrupt to exit the low-power modes.
• Clearing the ECNTRL[ETHER_EN] bit disables the FEC function.
• The FEC is unaffected by wait mode and may generate an interrupt to exit this mode.
In stop mode, the FEC stops immediately and freezes operation, register values, state machines, and external pins. During this mode, the FEC clocks are shut down. Coming out of stop mode returns the FEC to operation from the state prior to the low-power mode entry.
8.3.2.13 I/O Ports
The I/O ports are unaffected by entry into a low-power mode. These pins may impact low-power current draw if they are configured as outputs and are sourcing current to an external load. If low-power mode is exited by a reset, the state of the I/O pins will revert to their default direction settings.
8.3.2.14 Reset Controller
A power-on reset (POR) will always cause a chip reset and exit from any low-power mode.
In wait and doze modes, asserting the external RESET pin for at least four clocks will cause an external reset that will reset the chip and exit any low-power modes.
In stop mode, the RESET pin synchronization is disabled and asserting the external RESET pin will asynchronously generate an internal reset and exit any low-power modes. Registers will lose current values and must be reconfigured from reset state if needed.
If the phase lock loop (PLL) in the clock module is active and if the appropriate (LOCRE, LOLRE) bits in the synthesizer control register are set, then any loss-of-clock or loss-of-lock will reset the chip and exit any low-power modes.
If the watchdog timer is still enabled during wait or doze modes, then a watchdog timer timeout may generate a reset to exit these low-power modes.
When the CPU is inactive, a software reset cannot be generated to exit any low-power mode.
8.3.2.15 Chip Configuration Module
The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode is exited by a reset, chip configuration may be executed if configured to do so.
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MCF5271 Reference Manual, Rev. 2
8-9
Power Management
8.3.2.16 Clock Module
In wait and doze modes, the clocks to the CPU and SRAM will be stopped and the system clocks to the peripherals are enabled. Each module may disable the module clocks locally at the module level. In stop mode, all clocks to the system will be stopped.
During stop mode, the PLL continues to run. The external CLKOUT signal may be enabled or disabled when the device enters stop mode, depending on the LPCR[STPMD] bit settings.
The external CLKOUT output pin may be disabled to lower power consumption via the
SYNCR[DISCLK] bit. The external CLKOUT pin function is enabled by default at reset.
8.3.2.17 Edge Port
In wait and doze modes, the edge port continues to operate normally and may be configured to generate interrupts (either an edge transition or low level on an external pin) to exit the low-power modes.
In stop mode, there is no system clock available to perform the edge detect function. Thus, only the level detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit the stop mode.
8.3.2.18 Watchdog Timer
In stop mode (or in wait/doze mode, if so programmed), the watchdog ceases operation and freezes at the current value. When exiting these modes, the watchdog resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the watchdog may generate a reset to exit the low-power modes.
8.3.2.19 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3)
In stop mode (or in doze mode, if so programmed), the programmable interrupt timer (PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the PIT may generate an interrupt to exit the low-power modes.
8.3.2.20 BDM
Entering halt mode via the BDM port (by asserting the external BKPT pin) will cause the CPU to exit any low-power mode.
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8-10 Freescale Semiconductor
Functional Description
8.3.2.21 JTAG
The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not affected by the system clock. The JTAG cannot generate an event to cause the CPU to exit any low-power mode. Toggling TCLK during any low-power mode will increase the system current consumption.
8.3.3
Summary of Peripheral State During Low-Power Modes
The functionality of each of the peripherals and CPU during the various low-power modes is
summarized in Table 8-5 . The status of each peripheral during a given mode refers to the condition
the peripheral automatically assumes when the STOP instruction is executed and the
LPCR[LPMD] field is set for the particular low-power mode. Individual peripherals may be disabled by programming its dedicated control bits. The wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the CPU into run mode.
Table 8-5. CPU and Peripherals in Low-Power Modes
Peripheral Status
1
/ Wakeup Capability
Module
CPU
SRAM
System Control Module
SDRAM Controller
Chip Select Module
DMA Controller
UART0, UART1 and UART2
I
2
C Module
QSPI
DMA Timers
Interrupt controller
Fast Ethernet Controller
I/O Ports
Reset Controller
Chip Configuration Module
Power Management
Clock Module
Edge port
Watchdog timer
Wait Mode
No
No
Yes
3
No
No
Yes
Yes
2
Yes
2
Yes
2
Yes
2
Yes
2
Yes
2
No
Yes
3
No
No
Yes
2
Yes
2
Yes
3
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Stopped
Stopped
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Program
Doze Mode
No
No
Yes
3
No
No
Yes
Yes
2
Yes
2
Yes
2
Yes
2
Yes
2
Yes
2
No
Yes
3
No
No
Yes
2
Yes
2
Yes
3
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Stopped
Stopped
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Program
Stop Mode
Stopped
Stopped
Enabled
Stopped
Enabled
Enabled
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Enabled
Stopped
Stopped
No
No
Yes
No
No
Yes
3
No
No
Yes
2
Yes
No
No
No
No
No
No
No
No
No
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 8-11
Power Management
Table 8-5. CPU and Peripherals in Low-Power Modes (Continued)
Peripheral Status
1
/ Wakeup Capability
Module
Programmable Interrupt Timers
BDM
Wait Mode
Enabled
Enabled
Yes
2
Yes
4
Doze Mode
Program
Enabled
Yes
2
Yes
Stop Mode
Stopped
Enabled
No
Yes
JTAG Enabled No Enabled No Enabled No
3
4
1
2
“Program” Indicates that the peripheral function during the low-power mode is dependent on programmable bits in the peripheral register map.
These modules can generate a interrupt which will exit a low-power mode. The CPU will begin to service the interrupt exception after wakeup.
These modules can generate a reset which will exit any low-power mode.
The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode.
Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect.
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Chapter 9
Chip Configuration Module (CCM)
9.1
Introduction
The Chip Configuration Module (CCM) controls the chip configuration and mode of operation for the MCF5271.
9.1.1
Block Diagram
Reset
Configuration
Chip Mode
Selection
Boot Device / Port
Size Selection
Output Pad
Strength Selection
Clock Mode
Selection
Chip Select
Configuration
Chip Configuration Register
Reset Configuration Register
Chip Identification Register
Chip Test Register
Figure 9-1. Chip Configuration Module Block Diagram
9.1.2
Features
The CCM performs these operations.
• Selects the chip operating mode
• Selects external clock or phase-lock loop (PLL) mode with internal or external reference
• Selects output pad drive strength
• Selects boot device and data port size
• Selects bus monitor configuration
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Freescale Semiconductor 9-1
Chip Configuration Module (CCM)
• Selects low-power configuration
• Selects transfer size function of the external bus
• Selects processor status (PSTAT) and processor debug data (DDATA) functions
• Selects BDM or JTAG mode
9.1.3
Modes of Operation
The MCF5271 device only operates in master mode. In master mode, the central processor unit
(CPU) can access external memories and peripherals.The external bus consists of a 32-bit data bus and 24 address lines. The available bus control signals include R/W, TS, TIP, TSIZ[1:0], TA, TEA,
OE, and BS[3:0]. Up to eight chip selects can be programmed to select and control external devices and to provide bus cycle termination. When interfacing to 16-bit ports, the port DATAL and DATAH (D[15:0]) pins and BS[1:0] can be configured as general-purpose input/output (I/O).
9.2
External Signal Descriptions
Table 9-1 provides an overview of the CCM signals.
Table 9-1. Signal Properties
Name Function
RCON
CLKMOD[1:0]
Reset configuration select
Clock mode select
1
D[25:24, 21:19, 16] Reset configuration override pins
1
Refer to
Chapter 7, “Clock Module” for more information.
Reset State
Internal weak pull-up device
—
—
9.2.1
RCON
If the external RCON pin is asserted during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the
external data pins (see Section 9.4, “Functional Description
”). The internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration.
9.2.2
CLKMOD[1:0]
The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset. Refer to
for more information.
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Freescale Semiconductor
Memory Map/Register Definition
9.2.3
D[25:24, 21:19, 16] (Reset Configuration Override)
If the external RCON pin is asserted during reset, then the states of these data pins during reset determine the chip mode of operation, boot device, clock mode, and certain module configurations after reset.
9.3
Memory Map/Register Definition
This subsection provides a description of the memory map and registers.
9.3.1
Programming Model
The CCM programming model consists of these registers:
• The chip configuration register (CCR) controls the main chip configuration.
• The reset configuration register (RCON) indicates the default chip configuration.
• The chip identification register (CIR) contains a unique part number.
Some control register bits are implemented as write-once bits. These bits are always readable, but once the bit has been written, additional writes have no effect, except during debug and test operations.
Some write-once bits can be read and written while in debug mode. When debug mode is exited, the chip configuration module resumes operation based on the current register values. If a write to a write-once register bit occurs while in debug mode, the register bit remains writable on exit from
shows the accessibility of write-once bits.
Table 9-2. Write-Once Bits Read/Write Accessibility
Configuration
All configurations
Debug operation
Master mode
Read/Write Access
Read-always
Write-always
Write-once
9.3.2
Memory Map
Table 9-3. Chip Configuration Module Memory Map
IPSBAR Offset
0x11_0004
0x11_0008
0x11_000C
0x11_0010
[31:24] [23:16] [15:8] [7:0]
Chip Configuration Register (CCR) Low-Power Control Register (LPCR)
2
Reset Configuration Register (RCON) Chip Identification Register (CIR)
Reserved
3
Unimplemented
4
Access
1
S
—
S
S
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Freescale Semiconductor 9-3
Chip Configuration Module (CCM)
3
4
1
2
S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.
See
Chapter 8, “Power Management,”
for a description of the LPCR. It is shown here only to warn against accidental writes to this register.
Writing to reserved addresses with values other than 0 could put the device in a test mode; reading returns 0s.
Accessing an unimplemented address has no effect and causes a cycle termination transfer error.
NOTE
To safeguard against unintentionally activating test logic, write
0x0000 to the above reserved location during initialization
(immediately after reset) to lock out test features. Setting any bits in the CCR may lead to unpredictable results.
9.3.3
Register Descriptions
The following subsection describes the CCM registers.
9.3.3.1
Chip Configuration Register (CCR)
W
Reset
15 14
R LOAD 0
Address
13
0
12
0
11
0
10
0
9
0
8
0
7 6 5 4 3
0 SZEN PSTEN 0 BME
See Note
2 1
BMT
0
IPSBAR + 0x11_0004
Note: The reset value of the LOAD field is determined during reset configuration. The SZEN is set and the BME bit is set to enable the bus monitor and all other bits in the register are cleared at reset.
Figure 9-2. Chip Configuration Register (CCR)
Bits
15
14–7
6
Name
LOAD
—
SZEN
Table 9-4. CCR Field Descriptions
Description
Pad driver load. The LOAD bit selects full or partial drive strength for selected pad output drivers. For maximum capacitive load, set the LOAD bit to select full drive strength. For reduced power consumption and reduced electromagnetic interference (EMI), clear the
LOAD bit to select partial drive strength.
0 Default drive strength.
1 Full drive strength.
Table 9-2 shows the read/write accessibility of this write-once bit.
Reserved, should be cleared.
TSIZ[1:0] enable. This read/write bit enables the TSIZ[1:0] function of the external pins.
0 TSIZ[1:0] function disabled. DMA Acknowlede function enabled on the TSIZ[1:0] pins.
1 TSIZ[1:0] function enabled. DMA Acknowlede function disabled on the TSIZ[1:0] pins.
MCF5271 Reference Manual, Rev. 2
9-4 Freescale Semiconductor
Bits
5
4
3
2–0
Memory Map/Register Definition
Table 9-4. CCR Field Descriptions (Continued)
Name Description
PSTEN PST[3:0]/DDATA[3:0] enable. This read/write bit enables the Processor Status (PST) and
Debug Data (DDATA)n functions of the external pins.
0 PST/DDATA function disabled.
1 PST/DDATA function enabled.
—
BME
Reserved, should be cleared.
Bus monitor enable. This read/write bit enables the bus monitor to operate during external bus cycles.
0 Bus monitor disabled for external bus cycles.
1 Bus monitor enabled for external bus cycles.
Table 9-2 shows the read/write accessibility of this write-once bit.
BMT Bus monitor timing. This field selects the timeout period (in system clocks) for the bus monitor.
000 65536
001 32768
010 16384
011 8192
100 4096
101 2048
110 1024
111 512
Table 9-2 shows the read/write accessibility of this write-once bit.
9.3.3.2
Reset Configuration Register (RCON)
At reset, RCON determines the default operation of certain chip functions. All default functions defined by the RCON values can only be overridden during reset configuration (see
”) if the external RCON pin is asserted. RCON is a read-only register.
15
R 0
W
Reset 0
Address
14
0
0
13
0
12
0
11
0
10
0
9
RCSC
8 7
0
6 5 4 3
0 RLOAD BOOTPS
0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x11_0008
Figure 9-3. Reset Configuration Register (RCON)
0
2
0
0
1 0
0 MODE
0 1
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MCF5271 Reference Manual, Rev. 2
9-5
Chip Configuration Module (CCM)
Bits
15–10
9–8
7–6
5
4–3
Name
—
RCSC
Table 9-5. RCON Field Descriptions
Description
Reserved, should be cleared.
Chip select configuration. Reflects the default chip select configuration. The default function of the chip select configuration can be overridden during reset configuration.
RCSC Chip Select Configuration
00
01
1
PADDR[7:5] = A[23:21]
PADDR[7] = CS6
PADDR[6:5] = A[22:21]
10 PADDR[7:6] = CS[6:5]
PADDR[5] = A[21]
11 PADDR[7:5] = CS[6:4]
1
This is the default value used for the MCF5271.
— Reserved, should be cleared.
RLOAD Pad driver load. Reflects the default pad driver strength configuration.
0 Partial drive strength (This is the default value used for the MCF5271.)
1 Full drive strength
BOOTPS Boot port size. Reflects the default selection for the boot port size. The below table shows the different port configurations for BOOTPS. The default function of the boot port size can be overridden during reset configuration.
BOOTPS[1:0] Boot Port Size
00
1
, 11
01
External 32 bits
External 16 bits
10 External 8 bits
1
This is the default value used for the MCF5271.
2–1
0
—
MODE
Reserved, should be cleared.
Chip configuration mode. Reflects the default chip configuration mode.
0 Reserved
1 Master mode (This is the only value available for the MCF5271.)
The default mode cannot be overridden during reset configuration.
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Freescale Semiconductor
Functional Description
9.3.3.3
Chip Identification Register (CIR)
15
R
W
Reset 0
Address
14
0
13 12 11
PIN
10 9 8
Bits
15–6
5–0
7 6 5 4 3
PRN
2 1 0
1 0 0 0 0 0 0 0 0 0
IPSBAR + 0x11_000A
Figure 9-4. Chip Identification Register (CIR)
Table 9-6. CIR Field Description
0
Name
PIN
PRN
0 0 0
Description
Part identification number. Contains a unique identification number for the device.
Part revision number. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order.
9.4
Functional Description
Six functions are defined within the chip configuration module:
1. Reset configuration
2. Chip mode selection
3. Boot device selection
4. Output pad strength configuration
5. Clock mode selections
6. Chip select configuration
These functions are described here.
9.4.1
Reset Configuration
During reset, the pins for the reset override functions are immediately configured to known states.
Table 9-7 shows the states of the external pins while in reset.
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MCF5271 Reference Manual, Rev. 2
9-7
Chip Configuration Module (CCM)
Table 9-7. Reset Configuration Pin States During Reset
Pin
Pin
Function
1
I/O
Output
State
Input
State
D[25:24, 21:19, 16],
RCON
Primary function
RCON function for all modes
2
Input
Input
—
—
Must be driven by external logic
Internal weak pull-up device
CLKMOD1, CLKMOD0 Not affected Input — Must be driven by external logic
1
2
If the external RCON pin is not asserted during reset, pin functions are determined by the default operation mode defined in the RCON register. If the external RCON pin is asserted, pin functions are determined by the override values driven on the external data bus pins.
During reset, the external RCON pin assumes its RCON pin function, but this pin changes to the function defined by the chip operation mode immediately after reset. See
.
If the RCON pin is not asserted during reset, the chip configuration and the reset configuration pin functions after reset are determined by RCON or fixed defaults, regardless of the states of the external data pins. The internal configuration signals are driven to levels specified by the RCON register’s reset state for default module configuration.
If the RCON pin is asserted during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins. (See
Table 9-8 ) The internal configuration signals are driven to reflect the levels
on the external configuration pins to allow for module configuration.
Table 9-8. Configuration During Reset
1
Pin(s) Affected
D[31:0], R/W, TA, TEA,
TSIZ[1:0], TS, TIP, OE,
A[23:0], BS[3:0], CS[3:0]
Default
Configuration
RCON0 = 0
Function
CS0
All output pins
RCON[4:3] = 00
RCON[5] = 1
Override Pins in Reset
2,3
D16
1
0
D[20:19]
00,11
10
01
D21
0
1
Chip Mode Selected
Master mode
4
Reserved
Boot Device
External with 32-bit port
External with 8-bit port
External with 16-bit port
Output Pad Drive Strength
Partial strength
4
Full strength
MCF5271 Reference Manual, Rev. 2
9-8 Freescale Semiconductor
Functional Description
Table 9-8. Configuration During Reset
1
(Continued)
Pin(s) Affected
Default
Configuration
No default
5
Override Pins in Reset
2,3
Function
Clock mode CLKMOD1, CLKMOD0 Clock Mode
00
01
10
11
External clock mode (PLL disabled)
1:1 PLL mode
Normal PLL mode with external clock reference
Normal PLL mode w/crystal reference
A[23:21]/CS[6:4] RCON[9:8] = 00 D[25:24]
00
10
01
Chip Select Configuration
PADDR[7:5] = A[23:21]
4
PADDR[7] = CS6
PADDR[6:5] = A[22:21]
PADDR[7:6] = CS[6:5]
PADDR[5] = A[21]
11 PADDR[7:5] = CS[6:4]
1
2
3
4
5
Modifying the default configurations is possible only if the external RCON pin is asserted.
The D[31:26, 23:22, 18:17, 15:0] pins do not affect reset configuration.
The external reset override circuitry drives the data bus pins with the override values while RSTOUT is asserted. It must stop driving the data bus pins within one CLKOUT cycle after RSTOUT is negated. To prevent contention with the external reset override circuitry, the reset override pins are forced to inputs during reset and do not become outputs until at least one CLKOUT cycle after RSTOUT is negated. RCON must also be negated within one cycle after RSTOUT is negated.
Default configuration
There is no default configuration for clock mode selection. The actual values for the CLKMOD pins must always be driven during reset. Once out of reset, the CLKMOD pins have no effect on the clock mode selection.
9.4.2
Chip Mode Selection
The chip mode is selected during reset and reflected in the MODE field of the reset configuration register (RCON). See
Section 9.3.3.2, “Reset Configuration Register (RCON).”
For the
MCF5271, there is only one valid chip mode setting.
Table 9-9. Chip Configuration Mode Selection
Chip Configuration
Mode
Master mode
Reserved
RCON[MODE]
D16 driven high
D16 driven low
During reset, certain module configurations depend on whether emulation mode is active as determined by the state of the internal emulation signal.
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Freescale Semiconductor 9-9
Chip Configuration Module (CCM)
9.4.3
Boot Device Selection
During reset configuration, the CS0 chip select pin is configured to select an external boot device.
In this case, the V (valid) bit in the CSMR0 register is ignored, and CS0 is enabled after reset. CS0 is asserted for the initial boot fetch accessed from address 0x0000_0000 for the Stack Pointer and address 0x0000_0004 for the program counter (PC). It is assumed that the reset vector loaded from address 0x0000_0004 causes the CPU to start executing from external memory space decoded by
CS0.
9.4.4
Output Pad Strength Configuration
Output pad strength is determined during reset configuration as shown in
is exited, the output pad strength configuration can be changed by programming the LOAD bit of the chip configuration register.
Table 9-10. Output Pad Driver Strength Selection
1
Optional Pin Function Selection RCON[RLOAD]
Output pads configured for partial strength D21 driven low
Output pads configured for full strength D21 driven high
1
Modifying the default configurations is possible only if the external RCON pin is asserted low.
9.4.5
Clock Mode Selection
The clock mode is selected during reset and reflected in the PLLMODE, PLLSEL, and PLLREF bits of SYNSR. Once reset is exited, the clock mode cannot be changed.
clock mode selection during reset configuration.
Table 9-11. Clock Mode Selection
1
Clock Mode
PLL SYNSR Bits
CLKMOD[1] CLKMOD[0]
PLLMODE PLLSEL PLLREF
0 0 0 0 0 External clock mode; PLL disabled
1:1 PLL mode
Normal PLL mode; external clock reference
0
1
1
0
1
1
0
1
0
0
Normal PLL mode; crystal oscillator reference 1 0 1 1 1
1
There is no default configuration for clock mode selection. The actual values for the CLKMOD pins must always be driven during reset. Once out of reset, the CLKMOD pins have no effect on the clock mode selection.
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Freescale Semiconductor
Reset
9.4.6
Chip Select Configuration
The chip select configuration (CS[6:4]) is selected during reset and reflected in the RCSC field of
the CCR. Once reset is exited, the chip select configuration cannot be changed. Table 9-8 shows
the different chip select configurations that can be implemented during reset configuration.
9.5
Reset
Reset initializes CCM registers to a known startup state as described in
The CCM controls chip configuration at reset as described in
Section 9.4, “Functional Description
.”
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MCF5271 Reference Manual, Rev. 2
9-11
Chip Configuration Module (CCM)
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Freescale Semiconductor
Chapter 10
Reset Controller Module
10.1 Introduction
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and then to keep a history of what caused the reset.
10.1.1 Block Diagram
illustrates the reset controller and is explained in the following sections.
RESET
Pin
Power-On
Reset
Watchdog
Timer Timeout
RSTOUT
Pin
Reset
Controller
PLL
Loss of Clock
PLL
Loss of Lock
To Internal Resets
Software
Reset
Figure 10-1. Reset Controller Block Diagram
10.1.2 Features
Module features include:
• Six sources of reset:
— External
— Power-on reset (POR)
— Watchdog timer
— Phase locked-loop (PLL) loss of lock
— PLL loss of clock
— Software
• Software-assertable RESET pin independent of chip reset state
• Software-readable status flags indicating the cause of the last reset
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Freescale Semiconductor 10-1
Reset Controller Module
10.2 External Signal Description
Table 10-1 provides a summary of the reset controller signal properties. The signals are described
in the following paragraphs.
Table 10-1. Reset Controller Signal Properties
Name Direction
Input
Hysteresis
RESET I Y
RSTOUT O —
1
RESET is always synchronized except when in low-power stop mode.
Input
Synchronization
Y
1
—
10.2.1 RESET
Asserting the external RESET for at least four rising CLKOUT edges causes the external reset request to be recognized and latched.
10.2.2 RSTOUT
This active-low output signal is driven low when the internal reset controller module resets the chip. When RSTOUT is active, the user can drive override options on the data bus.
10.3 Memory Map/Register Definition
The reset controller programming model consists of these registers:
• Reset control register (RCR), which selects reset controller functions
• Reset status register (RSR), which reflects the state of the last reset source
for the memory map and the following paragraphs for a description of the registers.
Table 10-2. Reset Controller Memory Map
IPSBAR Offset [31:24] [23:16] [15:8]
0x11_0000 RCR RSR Reserved
2
1
2
S/U = supervisor or user mode access.
Writes to reserved address locations have no effect and reads return 0s.
[7:0]
Reserved
2
Access
1
S/U
10.3.1 Reset Control Register (RCR)
The RCR allows software control for requesting a reset and for independently asserting the external RSTOUT pin.
MCF5271 Reference Manual, Rev. 2
10-2 Freescale Semiconductor
Memory Map/Register Definition
Bits
7
6
W
Reset
7 6
R SOFTRST FRCRSTOUT
Address
0 0
5
0
0
4
0
0
3
0
0
IPSBAR + 0x11_0000
2
0
0
Figure 10-2. Reset Control Register (RCR)
1
0
0
Table 10-3. RCR Field Descriptions
0
0
0
Name Description
SOFTRST Allows software to request a reset. The reset caused by setting this bit clears this bit.
1 Software reset request
0 No software reset request
FRCRSTOUT Allows software to assert or negate the external RSTOUT pin.
1 Assert RSTOUT pin
0 Negate RSTOUT pin
CAUTION: External logic driving reset configuration data during reset needs to be considered when asserting the RSTOUT pin when setting FRCRSTOUT.
— Reserved, should be cleared.
5–0
10.3.2 Reset Status Register (RSR)
The RSR contains a status bit for every reset source. When reset is entered, the cause of the reset condition is latched along with a value of 0 for the other reset sources that were not pending at the time of the reset condition. These values are then reflected in RSR. One or more status bits may be set at the same time. The cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset condition.
RSR can be read at any time. Writing to RSR has no effect.
R
W
Reset
Address
7
0
6
0
5 4 3
SOFT WDR POR
2
EXT
1
LOC
0 0 Reset Dependent
IPSBAR + 0x11_0001
Figure 10-3. Reset Status Register (RSR)
0
LOL
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MCF5271 Reference Manual, Rev. 2
10-3
Reset Controller Module
Bits
7–6
5
4
3
2
1
0
Name
—
SOFT
WDR
POR
EXT
LOC
LOL
Table 10-4. RSR Field Descriptions
Description
Reserved, should be cleared.
Software reset flag. Indicates that the last reset was caused by software.
0 Last reset not caused by software
1 Last reset caused by software
Watchdog timer reset flag. Indicates that the last reset was caused by a watchdog timer timeout.
0 Last reset not caused by watchdog timer timeout
1 Last reset caused by watchdog timer timeout
Power-on reset flag. Indicates that the last reset was caused by a power-on reset.
0 Last reset not caused by power-on reset
1 Last reset caused by power-on reset
External reset flag. Indicates that the last reset was caused by an external device asserting the external RESET pin.
0 Last reset not caused by external reset
1 Last reset state caused by external reset
Loss-of-clock reset flag. Indicates that the last reset state was caused by a PLL loss of clock.
0 Last reset not caused by loss of clock
1 Last reset caused by loss of clock
Loss-of-lock reset flag. Indicates that the last reset state was caused by a PLL loss of lock.
0 Last reset not caused by loss of lock
1 Last reset caused by a loss of lock
10.4 Functional Description
10.4.1 Reset Sources
Table 10-5 defines the sources of reset and the signals driven by the reset controller.
Table 10-5. Reset Source Summary
Type Source
Power on
External RESET pin (not stop mode)
External RESET pin (during stop mode)
Watchdog timer
Loss of clock
Loss of lock
Software
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Asynchronous
Synchronous
MCF5271 Reference Manual, Rev. 2
10-4 Freescale Semiconductor
Functional Description
To protect data integrity, a synchronous reset source is not acted upon by the reset control logic until the end of the current bus cycle. Reset is then asserted on the next rising edge of the system clock after the cycle is terminated. Whenever the reset control logic must synchronize reset to the end of the bus cycle, the internal bus monitor is automatically enabled regardless of the BME bit state in the chip configuration register (CCR). Then, if the current bus cycle is not terminated normally the bus monitor terminates the cycle based on the length of time programmed in the BMT field of the CCR.
Internal byte, word, or longword writes are guaranteed to complete without data corruption when a synchronous reset occurs. External writes, including longword writes to 16-bit ports, are also guaranteed to complete.
Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the system.
10.4.1.1 Power-On Reset
At power up, the reset controller asserts RSTOUT. RSTOUT continues to be asserted until V
DD has reached a minimum acceptable level and, if PLL clock mode is selected, until the PLL achieves phase lock. Then after approximately another 512 cycles, RSTOUT is negated and the part begins operation.
10.4.1.2 External Reset
Asserting the external RESET for at least four rising CLKOUT edges causes the external reset request to be recognized and latched. The bus monitor is enabled and the current bus cycle is completed. The reset controller asserts RSTOUT for approximately 512 cycles after RESET is negated and the PLL has acquired lock. The part then exits reset and begins operation.
In low-power stop mode, the system clocks are stopped. Asserting the external RESET in stop mode causes an external reset to be recognized.
10.4.1.3 Watchdog Timer Reset
A watchdog timer timeout causes timer reset request to be recognized and latched. The bus monitor is enabled and the current bus cycle is completed. If the RESET is negated and the PLL has acquired lock, the reset controller asserts RSTOUT for approximately 512 cycles. Then the part exits reset and begins operation.
10.4.1.4 Loss-of-Clock Reset
This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set and either the PLL reference or the PLL itself fails. The reset controller asserts RSTOUT for
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 10-5
Reset Controller Module approximately 512 cycles after the PLL has acquired lock. The part then exits reset and begins operation.
10.4.1.5 Loss-of-Lock Reset
This reset condition occurs in PLL clock mode when the LOLRE bit in the SYNCR is set and the
PLL loses lock. The reset controller asserts RSTOUT for approximately 512 cycles after the PLL has acquired lock. The part then exits reset and resumes operation.
10.4.1.6 Software Reset
A software reset occurs when the SOFTRST bit is set. If the RESET is negated and the PLL has acquired lock, the reset controller asserts RSTOUT for approximately 512 cycles. Then the part exits reset and resumes operation.
10.4.2 Reset Control Flow
The reset logic control flow is shown in Figure 10-4 . In this figure, the control state boxes have
been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate.
10-6
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
0
Functional Description
POR
1
LOSS OF CLOCK?
Y
N
2
LOSS OF LOCK?
Y
N
3 RESET
PIN OR WD TIMEOUT
OR SW RESET?
Y
N
12
NEGATE RSTOUT
5
ENABLE BUS MONITOR
6
BUS CYCLE
COMPLETE?
Y
7
ASSERT RSTOUT AND
LATCH RESET STATUS
N
4
ASSERT RSTOUT AND
LATCH RESET STATUS
8
RESET NEGATED?
N
Y
9
PLL MODE?
N
10
WAIT 512 CLKOUT CYCLES
Y
9A
PLL LOCKED?
Y
N
11
RCON ASSERTED?
Y
N
Figure 10-4. Reset Control Flow
11A
LATCH CONFIGURATION
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 10-7
Reset Controller Module
10.4.2.1 Synchronous Reset Requests
In this discussion, the reference in parentheses refer to the state numbers in
. All cycle counts given are approximate.
If the external RESET signal is asserted by an external device for at least four rising CLKOUT edges (3), if the watchdog timer times out, or if software requests a reset, the reset control logic latches the reset request internally and enables the bus monitor (5). When the current bus cycle is completed (6), RSTOUT is asserted (7). The reset control logic waits until the RESET signal is negated (8) and for the PLL to attain lock (9, 9A) before waiting 512 CLKOUT cycles (1). The reset control logic may latch the configuration according to the RCON signal level (11, 11A) before negating RSTOUT (12).
If the external RESET signal is asserted by an external device for at least four rising CLKOUT edges during the 512 count (10) or during the wait for PLL lock (9A), the reset flow switches to
(8) and waits for the RESET signal to be negated before continuing.
10.4.2.2 Internal Reset Request
If reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss of lock
(2), the reset control logic asserts RSTOUT (4). The reset control logic waits for the PLL to attain lock (9, 9A) before waiting 512 CLKOUT cycles (1). Then the reset control logic may latch the configuration according to the RCON pin level (11, 11A) before negating RSTOUT (12).
If loss of lock occurs during the 512 count (10), the reset flow switches to (9A) and waits for the
PLL to lock before continuing.
10.4.2.3 Power-On Reset
When the reset sequence is initiated by power-on reset (0), the same reset sequence is followed as for the other asynchronous reset sources.
10.4.3 Concurrent Resets
This section describes the concurrent resets. As in the previous discussion references in parentheses refer to the state numbers in
.
10.4.3.1 Reset Flow
If a power-on reset is detected during any reset sequence, the reset sequence starts immediately (0).
If the external RESET pin is asserted for at least four rising CLKOUT edges while waiting for PLL lock or the 512 cycles, the external reset is recognized. Reset processing switches to wait for the external RESET pin to negate (8).
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Functional Description
If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to complete (5, 6) for an external reset request, the cycle is terminated. The reset status bits are latched (7) and reset processing waits for the external RESET pin to negate (8).
If a loss-of-clock or loss-of-lock condition is detected during the 512 cycle wait, the reset sequence continues after a PLL lock (9, 9A).
10.4.3.2 Reset Status Flags
For a POR reset, the POR bit in the RSR are set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared even if another type of reset condition is detected during the reset sequence for the
POR.
If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to complete (5, 6) for an external reset request, the EXT, SOFT, and/or WDR bits along with the LOC and/or LOL bits are set.
If the RSR bits are latched (7) during the EXT, SOFT, and/or WDR reset sequence with no other reset conditions detected, only the EXT, SOFT, and/or WDR bits are set.
If the RSR bits are latched (4) during the internal reset sequence with the RESET pin not asserted and no SOFT or WDR event, then the LOC and/or LOL bits are the only bits set.
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Chapter 11
System Control Module (SCM)
11.1 Introduction
This section details the functionality of the System Control Module (SCM) which provides the programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit core watchdog timer (CWT), and the system control registers and logic. Specifically, the system control includes the internal peripheral system (IPS) base address register (IPSBAR), the processor’s dual-port RAM base address register (RAMBAR), and system control registers that include the core watchdog timer control.
11.1.1 Overview
The SCM provides the control and status for a variety of functions including base addressing and address space masking for both the IPS peripherals and resources (IPSBAR) and the ColdFire core memory space (RAMBAR). The MCF5271 CPU core supports one memory bank for the internal
SRAM.
The SACU provides the mechanism needed to implement secure bus transactions to the system address space.
The programming model for the system bus arbitration resides in the SCM. The SCM sources the necessary control signals to the arbiter for bus master management.
The CWT provides a means of preventing system lockup due to uncontrolled software loops via a special software service sequence. If periodic software servicing action does not occur, the CWT times out with a programmed response (interrupt) to allow recovery or corrective action to be taken.
NOTE
The core watchdog timer is available to provide compatibility with the watchdog timer implemented on previous ColdFire devices. However, there is a second watchdog timer available on the MCF5271 that has
new features. See Chapter 20, “Watchdog Timer Module ” for more
information. Please note that the core watchdog timer is unable to reset the device. It is only permitted to assert an interrupt. For resetting the device, use the second watchdog timer.
11.1.2 Features
The SCM includes these distinctive features:
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System Control Module (SCM)
• IPS base address register (IPSBAR)
— Base address location for 1-Gbyte peripheral space
— User control bits
• Processor-local memory base address register (RAMBAR)
• System control registers
— Core reset status register (CRSR) indicates type of last reset
— Core watchdog control register (CWCR) for watchdog timer control
— Core watchdog service register (CWSR) to service watchdog timer
• System bus master arbitration programming model (MPARK)
• System access control unit (SACU) programming model
— Master privilege register (MPR)
— Peripheral access control registers (PACRs)
— Grouped peripheral access control register (GPACR)
11.2 Memory Map/Register Definition
The memory map for the SCM registers is shown in Table 11-1
. All the registers in the SCM are memory-mapped as offsets within the 1-Gbyte IPS address space and accesses are controlled to these registers by the control definitions programmed into the SACU.
Table 11-1. SCM Register Map
IPSBAR
Offset
0x00_0000
0x00_0004
0x00_0008
0x00_000C
0x00_0010
0x00_0014
0x00_0018
0x00_001C
0x00_0020
0x00_0024
0x00_0028
0x00_002C
[31:24]
CRSR
MPR
PACR0
PACR4
PACR7
[23:16] [15:8]
IPSBAR
—
RAMBAR
—
CWCR
DMAREQC
2
LPICR
1
—
MPARK
PACR1
—
—
—
PACR2
PACR5
PACR8
[7:0]
CWSR
PACR3
PACR6
—
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Memory Map/Register Definition
Table 11-1. SCM Register Map (Continued)
IPSBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x00_0030
0x00_0034
GPACR
—
—
—
—
—
—
—
0x00_0038 — — — —
0x00_003C — — — —
1
2
The LPICR register is described in
Chapter 8, “Power Management ."
The DMAREQC register is described in
Chapter 14, “DMA Controller Module .”
11.2.1 Register Descriptions
11.2.1.1 Internal Peripheral System Base Address Register (IPSBAR)
The IPSBAR specifies the base address for the 1 Gbyte memory space associated with the on-chip peripherals. At reset, the base address is loaded with a default location of 0x4000_0000 and marked as valid (IPSBAR[V]=1). If desired, the address space associated with the internal modules can be moved by loading a different value into the IPSBAR at a later time.
If an address “hits” in overlapping memory regions, the following priority is used to determine what memory is accessed:
1. IPSBAR
2. RAMBAR
3. Cache
4. SDRAM
5. Chip Selects
NOTE
This is the list of memory access priorities when viewed from the processor core.
See
for descriptions of the bits in IPSBAR.
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System Control Module (SCM)
31 30
R
W
Reset 0
BA
1
15
R 0
W
Reset —
Address
14
0
—
29
0
—
13
0
28
0
—
12
0
27
0
—
11
0
26
0
—
10
0
25
0
—
9
0
24
0
—
8
0
23
0
—
7
0
22
0
—
6
0
21
0
—
5
0
20
0
—
4
0
19
0
— — — — — — — — — — —
IPSBAR + 0x000
Figure 11-1. IPS Base Address Register (IPSBAR)
Table 11-2. IPSBAR Field Description
—
3
0
Bits
31–30
29–1
0
Name
BA
—
V
18
0
—
2
0
—
17
0
—
1
0
—
16
0
—
0
V
1
Description
Base address. Defines the base address of the 1-Gbyte internal peripheral space. This is the starting address for the IPS registers when the valid bit is set.
Reserved, should be cleared.
Valid. Enables/disables the IPS Base address region. V is set at reset.
0 IPS Base address is not valid.
1 IPS Base address is valid.
11.2.1.2 Memory Base Address Register (RAMBAR)
The MCF5271 supports dual-ported local SRAM memory. This processor-local memory can be accessed directly by the core and/or other system bus masters. Since this memory provides single-cycle accesses at processor speed, it is ideal for applications where double-buffer schemes can be used to maximize system-level performance. For example, a DMA channel in a typical double-buffer (also known as a ping-pong scheme) application may load data into one portion of the dual-ported SRAM while the processor is manipulating data in another portion of the SRAM.
Once the processor completes the data calculations, it begins processing the just-loaded buffer while the DMA moves out the just-calculated data from the other buffer, and reloads the next data block into the just-freed memory region. The process repeats with the processor and the DMA
“ping-ponging” between alternate regions of the dual-ported SRAM.
The MCF5271 design implements the dual-ported SRAM in the memory space defined by the
RAMBAR register. There are two physical copies of the RAMBAR register: one located in the processor core and accessible only via the privileged MOVEC instruction at CPU space address
0xC05, and another located in the SCM at IPSBAR + 0x008. ColdFire core accesses to this memory are controlled by the processor-local copy of the RAMBAR, while (e.g., DMA, FEC, etc.) module accesses are enabled by the SCM's RAMBAR.
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Memory Map/Register Definition
The physical base address programmed in both copies of the RAMBAR is typically the same value; however, they can be programmed to different values. By definition, the base address must be a 0-modulo-size value.
31
R
W
Reset 0
15
R 0
W
Reset 0
Address
30
0
14
0
29
0
13
0
28
0
12
0
27
0
11
0
26 25
0 0 0
10 9 8
0 BDE 0
24
BA
23
0
7
0
22
0
6
0
21
0
5
0
20
0
4
0
19
0
3
0
18
0
2
0
17
0
1
0
16
0
0
0
Bits
31–16
15–10
9
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x008
Figure 11-2. Memory Base Address Register (RAMBAR)
0
Table 11-3. RAMBAR Field Description
Name
BA
—
BDE
—
0 0
Description
Base address. Defines the memory module's base address on a 64-Kbyte boundary corresponding to the physical array location within the 4 Gbyte address space supported by ColdFire.
Reserved, should be cleared.
Back door enable. Qualifies the DMA module accesses to the SRAM memory.
0 Disables DMA module accesses to the SRAM module.
1 Enables DMA module accesses to the SRAM module.
NOTE: The SPV bit in the CPU’s RAMBAR must also be set to allow dual port access to
the SRAM. For more information, see Section 6.2.1, “SRAM Base Address Register
Reserved, should be cleared.
8–0
The SRAM module is configured through the RAMBAR shown in
• RAMBAR specifies the base address of the SRAM.
• All undefined bits are reserved. These bits are ignored during writes to the RAMBAR and return zeros when read.
• The back door enable bit, RAMBAR[BDE], is cleared at reset, disabling the DMA module access to the SRAM.
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System Control Module (SCM)
NOTE
The SCM RAMBAR default value of 0x0000_0000 is invalid. The
RAMBAR located in the processor’s CPU space must be initialized with the valid bit, RAMBAR[V], set before the CPU (or modules) can
access the on-chip SRAM (see 6.2.1, “SRAM Base Address Register
” for more information. The SCM RAMBAR is implemented as 32 bits, all bits may be written and read. Bit fields
[15:10] and [8:0] are not used in the access decode.
For details on the processor's view of the local SRAM memories, see Section 6.2.1, “SRAM Base
11.2.1.3 Core Reset Status Register (CRSR)
The CRSR contains a bit for two of the reset sources to the CPU. A bit set to 1 indicates the last type of reset that occurred. The CRSR is updated by the control logic when the reset is complete.
Only one bit is set at any one time in the CRSR. The register reflects the cause of the most recent reset. To clear a bit, a logic 1 must be written to the bit location; writing a zero has no effect.
NOTE
The reset status register (RSR) in the reset controller module (see
Chapter 10, “Reset Controller Module ”) provides indication of all
reset sources except the core watchdog timer.
Bits
7
6–0
W
Reset
7
R EXT
Address
6
0
5
0
4
0
3
0
See Note
IPSBAR + 0x010
2
0
1
0
0
0
Note: The reset value of EXT depends on the last reset source. All other bits are initialized to zero.
Figure 11-3. Core Reset Status Register (CRSR)
Table 11-4. CRSR Field Descriptions
Name
EXT
—
Description
External reset.
1 An external device driving RESET caused the last reset. Assertion of reset by an external device causes the processor core to initiate reset exception processing. All registers are forced to their initial state.
Reserved, should be cleared.
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Memory Map/Register Definition
11.2.1.4 Core Watchdog Control Register (CWCR)
The core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit. The core watchdog timer can be enabled or disabled through CWCR[CWE].
By default it is disabled. If enabled, the watchdog timer requires the periodic execution of a core watchdog servicing sequence. If this periodic servicing action does not occur, the timer times out, resulting in a watchdog timer interrupt. If the timer times out and the core watchdog transfer acknowledge enable bit (CWCR[CWTA]) is set, a watchdog timer interrupt is asserted. If a core watchdog timer interrupt acknowledge cycle has not occurred after another timeout, CWT TA is asserted in an attempt to allow the interrupt acknowledge cycle to proceed by terminating the bus cycle. The setting of CWCR[CWTAVAL] indicates that the watchdog timer TA was asserted.
To prevent the core watchdog timer from interrupting, the CWSR must be serviced by performing the following sequence:
1. Write 0x55 to CWSR.
2. Write 0xAA to the CWSR.
Both writes must occur in order before the time-out, but any number of instructions can be executed between the two writes. This order allows interrupts and exceptions to occur, if necessary, between the two writes. Caution should be exercised when changing CWCR values after the software watchdog timer has been enabled with the setting of CWCR[CWE], because it is difficult to determine the state of the core watchdog timer while it is running. The countdown value is constantly compared with the time-out period specified by CWCR[CWT]. The following steps must be taken to change CWT:
1. Disable the core watchdog timer by clearing CWCR[CWE].
2. Reset the counter by writing 0x55 and then 0xAA to CWSR.
3. Update CWCR[CWT].
4. Re-enable the core watchdog timer by setting CWCR[CWE]. This step can be performed in step 3.
The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer transfer acknowledge. The register can be read at any time, but can be written only if the CWT is not pending. At system reset, the software watchdog timer is disabled.
W
Reset
7 6
R CWE CWRI
0 0
5 4
CWT
3 2 1
CWTA CWTAV
AL
0
CWTIC
0 0 0 0 0 0
Address IPSBAR + 0x011
Figure 11-4. Core Watchdog Control Register (CWCR)
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System Control Module (SCM)
Bits
7
6
5–3
Name
CWE
CWRI
CWT
Table 11-5. CWCR Field Description
Description
Core watchdog enable.
0 SWT disabled.
1 SWT enabled.
Core watchdog reset/interrupt select.
0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for the CWT is programmed in the interrupt control register 7 (ICR7) of INTC0.
1 Reserved. Please note that unlike legacy devices, this bit is not available since the core watchdog is unable to reset the device.
Core watchdog timing delay. These bits select the timeout period for the CWT. At system reset, the CWT field is cleared signaling the minimum time-out period but the watchdog is disabled (CWCR[CWE] = 0).
CWT [2:0]
100
101
110
111
000
001
010
011
CWT Time-Out Period
2
9
Bus clock frequency
2
11
Bus clock frequency
2
13
Bus clock frequency
2
15
Bus clock frequency
2
19
Bus clock frequency
2
23
Bus clock frequency
2
27
Bus clock frequency
2
31
Bus clock frequency
2
1
0
CWTA Core watchdog transfer acknowledge enable.
0 CWTA Transfer acknowledge disabled.
1 CWTA Transfer Acknowledge enabled. After one CWT time-out period of the unacknowledged assertion of the CWT interrupt, the transfer acknowledge asserts, which allows CWT to terminate a bus cycle and allow the interrupt acknowledge to occur.
CWTAVAL Core watchdog transfer acknowledge valid.
0 CWTA Transfer Acknowledge has not occurred.
1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit.
CWTIF Core watchdog timer interrupt flag.
0 CWT interrupt has not occurred
1 CWT interrupt has occurred. Write a 1 to clear the interrupt request.
11.2.1.5 Core Watchdog Service Register (CWSR)
The software watchdog service sequence must be performed using the CWSR as a data register to prevent a CWT time-out. The service sequence requires two writes to this data register: first a write of 0x55 followed by a write of 0xAA. Both writes must be performed in this order prior to the
CWT time-out, but any number of instructions or accesses to the CWSR can be executed between
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Internal Bus Arbitration the two writes. If the CWT has already timed out, writing to this register has no effect in negating
the CWT interrupt. Figure 11-5
illustrates the CWSR. At system reset, the contents of CWSR are uninitialized.
7
R
W
Reset —
6 5 4 3
CWSR[7:0]
2 1 0
— — — — — — —
Address IPSBAR + 0x013
Figure 11-5. Core Watchdog Service Register (CWSR)
11.3 Internal Bus Arbitration
The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic that controls which of up to four MBus masters (M0–M3 in
access to the external buses. The function of the arbitration logic is described in this section.
“back door” to SRAM
SRAM1
MPARK RAMBAR
CPU
M0
DMA
M2 MARB
EIM
Internal
Modules
FEC
M3 SDRAMC
Figure 11-6. Arbiter Module Functions
11.3.1 Overview
The basic functionality is that of a 4-port, pipelined internal bus arbitration module with the following attributes:
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System Control Module (SCM)
• The master pointed to by the current arbitration pointer may get on the bus with zero latency if the address phase is available. All other requesters face at least a one cycle arbitration pipeline delay in order to meet bus timing constraints on address phase hold.
• If a requester will get an immediate address phase (that is, it is pointed to by the current arbitration pointer and the bus address phase is available), it will be the current bus master and is ignored by arbitration. All remaining requesting ports are evaluated by the arbitration algorithm to determine the next-state arbitration pointer.
• There are two arbitration algorithms, fixed and round-robin. Fixed arbitration sets the next-state arbitration pointer to the highest priority requester. Round-robin arbitration sets the next-state arbitration pointer to the highest priority requester (calculated by adding a requester's fixed priority to the current bus master’s fixed priority and then taking this sum modulo the number of possible bus masters).
• The default priority is FEC (M3) > DMA (M2) > internal master (M1) > CPU (M0), where
M3 is the highest and M0 the lowest priority.
• There are two actions for an idle arbitration cycle, either leave the current arbitration pointer as is or set it to the lowest priority requester.
• The anti-lock-out logic for the fixed priority scheme forces the arbitration algorithm to round-robin if any requester has been held for longer than a specified cycle count.
11.3.2 Arbitration Algorithms
There are two modes of arbitration: fixed and round-robin. This section discusses the differences between them.
11.3.2.1 Round-Robin Mode
Round-robin arbitration is the default mode after reset. This scheme cycles through the sequence of masters as specified by MPARK[Mn_PRTY] bits. Upon completion of a transfer, the master is given the lowest priority and the priority for all other masters is increased by one.
next +1 next +2 next +3
M3 = 11 M2 =01 M1 = 10 M0 = 00
M3 = 00 M2 =10 M1 = 11 M0 = 01
M3 = 01 M2 =11 M1 = 00 M0 = 10
M3 = 10 M2 =00 M1 = 01 M0 = 11
If no masters are requesting, the arbitration unit must “park”, pointing at one of the masters. There are two possibilities, park the arbitration unit on the last active master, or park pointing to the highest priority master. Setting MPARK[PRK_LAST] causes the arbitration pointer to be parked on the highest priority master. In round-robin mode, programming the timeout enable and lockout bits MPARK[13,11:8] will have no effect on the arbitration.
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Internal Bus Arbitration
11.3.2.2 Fixed Mode
In fixed arbitration the master with highest priority (as specified by the MPARK[Mn_PRTY] bits) will win the bus. That master will relinquish the bus when all transfers to that master are complete.
If MPARK[TIMEOUT] is set, a counter will increment for each master for every cycle it is denied access. When a counter reaches the limit set by MPARK[LCKOUT_TIME], the arbitration algorithm will be changed to round-robin arbitration mode until all locks are cleared. The arbitration will then return to fixed mode and the highest priority master will be granted the bus.
As in round-robin mode, if no masters are requesting, the arbitration pointer will park on the highest priority master if MPARK[PRK_LAST] is set, or will park on the master which last requested the bus if cleared.
11.3.3 Bus Master Park Register (MPARK)
The MPARK controls the operation of the system bus arbitration module. The platform bus master connections are defined as:
• Master 3 (M3): Fast Ethernet Controller
• Master 2 (M2): 4-channel DMA
• Master 1 (M1): Reserved
• Master 0 (M0): V2 ColdFire Core
31
R 0
W
Reset 0
30
0
29
0
28
0
27
0
26 25
0 M2_P
_EN
24
0
23 22 21 20 19 18
M3_PRTY M2_PRTY M0_PRTY
0 1 1 0 0 0 0 1 1 1 0 0
15 14 13 12
R 0 FIXED TIME
W
OUT
PRK
LAST
Reset
Address
0 0 0 0
11
0
10 9
LCKOUT_TIME
0 0
8
0
7
0
0
IPSBAR + 0x01C
6
0
0
5
0
0
4
0
0
3
0
0
Figure 11-7. Default Bus Master Park Register (MPARK)
Table 11-6. MPARK Field Description
0
0
2
0
Bits
31–26
25
0
1
0
17
0
0
16
0
0
Name Description
— Reserved, should be cleared.
M2_P_EN DMA bandwidth control enable
0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
1 enable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
1
0
0
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Freescale Semiconductor 11-11
System Control Module (SCM)
Bits
24
23–22
21–20
19–18
17–15
14
13
12
11–8
7–0
Table 11-6. MPARK Field Description (Continued)
Name Description
— Reserved, should be cleared.
M3_PRTY Master priority level for master 3 (Fast Ethernet Controller)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
M2_PRTY Master priority level for master 2 (DMA Controller)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
M0_PRTY Master priority level for master 0 (ColdFire Core)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
— Reserved, should be cleared.
FIXED Fixed or round robin arbitration
0 round robin arbitration
1 fixed arbitration
TIMEOUT Timeout Enable
0 disable count for when a master is locked out by other masters.
1 enable count for when a master is locked out by other masters and allow access when
LCKOUT_TIME is reached.
PRKLAST Park on the last active master or highest priority master if no masters are active
0 park on last active master
1 park on highest priority master
LCKOUT_
TIME
—
Lock-out Time. Lock-out time for a master being denied the bus.
The lock out time is defined as 2^ LCKOUT_TIME[3:0].
Reserved, should be cleared.
The initial state of the master priorities is M3 > M2 > M1 > M0. System software should guarantee that the programmed Mn_PRTY fields are unique, otherwise the hardware defaults to the initial-state priorities.
11.4 System Access Control Unit (SACU)
This section details the functionality of the System Access Control Unit (SACU) which provides the mechanism needed to implement secure bus transactions to the address space mapped to the internal modules.
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System Access Control Unit (SACU)
11.4.1 Overview
The SACU supports the traditional model of two privilege levels: supervisor and user. Typically, memory references with the supervisor attribute have total accessibility to all the resources in the system, while user mode references cannot access system control and configuration registers. In many systems, the operating system executes in supervisor mode, while application software executes in user mode.
The SACU further partitions the access control functions into two parts: one control register defines the privilege level associated with each bus master, and another set of control registers define the access levels associated with the peripheral modules and the memory space.
The SACU’s programming model is physically implemented as part of the System Control
Module (SCM) with the actual access control logic included as part of the arbitration controller.
Each bus transaction targeted for the IPS space is first checked to see if its privilege rights allow access to the given memory space. If the privilege rights are correct, the access proceeds on the bus. If the privilege rights are insufficient for the targeted memory space, the transfer is immediately aborted and terminated with an exception, and the targeted module not accessed.
11.4.2 Features
Each bus transfer can be classified by its privilege level and the reference type. The complete set of access types includes:
• Supervisor instruction fetch
• Supervisor operand read
• Supervisor operand write
• User instruction fetch
• User operand read
• User operand write
Instruction fetch accesses are associated with the execute attribute.
It should be noted that while the bus does not implement the concept of reference type (code versus data) and only supports the user/supervisor privilege level, the reference type attribute is supported by the system bus. Accordingly, the access checking associated with both privilege level and reference type is performed in the IPS controller using the attributes associated with the reference from the system bus.
The SACU partitions the access control mechanisms into three distinct functions:
• Master privilege register (MPR)
— Allows each bus master to be assigned a privilege level:
– Disable the master’s user/supervisor attribute and force to user mode access
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 11-13
System Control Module (SCM)
– Enable the master’s user/supervisor attribute
— The reset state provides supervisor privilege to the processor core (bus master 0).
— Input signals allow the non-core bus masters to have their user/supervisor attribute enabled at reset. This is intended to support the concept of a trusted bus master, and also controls the ability of a bus master to modify the register state of any of the SACU control registers; that is., only trusted masters can modify the control registers.
• Peripheral access control registers (PACRs)
— Nine 8-bit registers control access to 17 of the on-chip peripheral modules.
— Provides read/write access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to these modules
• Grouped peripheral access control registers (GPACR0)
— One single register (GPACR) controls access to 14 of the on-chip peripheral modules
— Provide read/write/execute access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to each of these peripheral spaces
11.4.3 Memory Map/Register Definition
The memory map for the SACU program-visible registers within the System Control Module
(SCM) is shown in
. The MPR, PACR, and GPACR are 8 bits in width.
Table 11-7. SACU Register Memory Map
IPSBA
R
Offset
0x020
0x024
0x028
0x02c
0x030
0x034
0x038
0x03C
[31:28]
MPR
PACR0
PACR4
PACR7
GPACR
—
—
—
[27:24] [23:20]
—
PACR1
—
—
—
—
—
—
[19:16]
—
[15:12]
—
PACR2
PACR5
PACR8
—
—
—
—
[11:8]
—
[7:4] [3:0]
—
PACR3
PACR6
—
—
—
—
—
—
11.4.3.1 Master Privilege Register (MPR)
The MPR specifies the access privilege level associated with each bus master in the platform. The register provides one bit per bus master, where bit 3 corresponds to master 3 (Fast Ethernet
Controller), bit 2 to master 2 (DMA Controller), bit 1 to master 1 (), and bit 0 to master 0 (ColdFire core).
MCF5271 Reference Manual, Rev. 2
11-14 Freescale Semiconductor
System Access Control Unit (SACU)
Bits
7–4
3–0
R
W
Reset
7
0
6
0
5
0
4
0
3 2 1 0
MPR3 MPR2 MPR1 MPR0
0 0 0 0 0 0 1
Address IPSBAR + 0x020
Figure 11-8. Master Privilege Register (MPR)
1
Table 11-8. MPR Field Descriptions
Name
—
MPRn
Description
Reserved. Should be cleared.
Each 1-bit field defines the access privilege level of the given bus master n.
0 All bus master accesses are in user mode.
1 All bus master accesses use the sourced user/supervisor attribute.
Only trusted bus masters can modify the access control registers. If a non-trusted bus master attempts to write any of the SACU control registers, the access is aborted with an error termination and the registers remain unaffected.
The processor core is connected to bus master 0 and is always treated as a trusted bus master.
Accordingly, MPR0 is forced to 1 at reset.
11.4.3.2 Peripheral Access Control Registers (PACR0–PACR8)
Access to several on-chip peripherals is controlled by shared peripheral access control registers.
A single PACR defines the access level for each of the two modules. These modules only support operand reads and writes. Each PACR follows the format illustrated in
. For a list of
PACRs and the modules that they control, refer to Table 11-11
.
W
Reset
7
R LOCK1
0
6 5
ACCESS_CTRL1
4 3
LOCK0
2 1
ACCESS_CTRL0
0
0 0 0 0 0 0 0
Address IPSBAR + 0x24 + Offset
Figure 11-9. Peripheral Access Control Register (PACRn)
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
11-15
System Control Module (SCM)
Bits
7
6–4
3
2–0
Table 11-9. PACRn Field Descriptions
Name Description
LOCK1 This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted write to the PACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
ACCESS_
CTRL1
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in Table 11-10 .
LOCK0 This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted write to the PACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
ACCESS_
CTRL0
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in Table 11-10 .
Table 11-10. PACR ACCESS_CTRL Bit Encodings
Bits
100
101
110
111
000
001
010
011
Supervisor Mode
Read x
— x x x x x x
Write x
— x x x
—
—
—
User Mode
Read x
— x x
—
— x
—
Write x
— x
—
—
—
—
—
Table 11-11. Peripheral Access Control Registers (PACRn)
IPSBAR Offset
0x024
0x025
0x026
0x027
0x028
0x029
0x02A
0x02B
0x02C
Name
PACR0
PACR1
PACR2
PACR3
PACR4
—
PACR5
PACR6
PACR7
ACCESS_CTRL1
SCM
EIM
UART0
UART2
I
2
C
—
DTIM0
DTIM2
INTC0
Modules Controlled
ACCESS_CTRL0
SDRAMC
DMA
UART1
—
QSPI
—
DTIM1
DTIM3
INTC1
MCF5271 Reference Manual, Rev. 2
11-16 Freescale Semiconductor
System Access Control Unit (SACU)
Table 11-11. Peripheral Access Control Registers (PACRn) (Continued)
IPSBAR Offset
0x02D
0x02E
Name
—
PACR8
Modules Controlled
ACCESS_CTRL1
—
FEC0
ACCESS_CTRL0
—
—
At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. If an instruction fetch access to any of these peripheral modules is attempted, the IPS bus cycle is immediately terminated with an error.
11.4.3.3 Grouped Peripheral Access Control Register (GPACR)
The on-chip peripheral space starting at IPSBAR is subdivided into sixteen 64-Mbyte regions. The first region has a unique access control register associated with it. The other fifteen regions are in reserved space; the access control registers for these regions are not implemented. The access control register is 8 bits in width so that read, write, and execute attributes may be assigned to the given IPS region.
NOTE
The access control for modules with memory space protected by
PACR0–PACR8 are determined by the PACR0–PACR8 settings. The access control is not affected by GPACR, even though the modules are mapped in its 64-Mbyte address space.
W
Reset
7
R LOCK
0
6
0
5
0
4
0
3 2 1
ACCESS_CTRL
0
0 0 0 0 0 0 0
Address IPSBAR + 0x030
Figure 11-10. Grouped Peripheral Access Control Register (GPACR)
Table 11-12. (GPACR) Field Descriptions
Bits
7
6–4
3–0
Name Description
LOCK
—
ACCESS_
CTRL
This bit, once set, prevents subsequent writes to the GPACR. Any attempted write to the
GPACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
Reserved, should be cleared.
This 4-bit field defines the access control for the given memory region.
The encodings for this field are shown in Table 11-13 .
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 11-17
System Control Module (SCM)
At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. Bit encodings for the ACCESS_CTRL field in the GPACR are shown in
.
Table 11-14 shows the memory space protected by the GPACR and the modules mapped to this
space.
Table 11-13. GPACR ACCESS_CTRL Bit Encodings
Bits
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Read x x x x x
— x x x
— x x x x x x
Supervisor Mode
Write x x x x x
—
—
— x
— x x x
—
—
—
Execute
— x x x x x x x
—
—
—
—
—
—
—
—
Read x
— x x
—
— x
— x
— x x
—
— x
—
User Mode
Write x
—
—
—
—
—
—
— x
— x
—
—
—
—
—
Execute
— x x x
—
— x
—
—
—
—
—
—
—
—
—
Register
GPACR
Table 11-14. GPACR Address Space
Space Protected
(IPSBAR Offset)
0x0000_0000–0x03FF_FFFF
Modules Protected
All
11-18
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Chapter 12
General Purpose I/O Module
12.1 Introduction
Many of the pins associated with the MCF5271 external interface may be used for several different functions. Their primary functions are to provide external interfaces to access off-chip resources.
When not used for their primary function, many of the pins may be used as general-purpose digital
I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.
The general purpose I/O pins on the MCF5271 are grouped into 8-bit ports. Some ports do not use all 8 bits. Each GPIO port has registers that configure, monitor, and control the port pins.
is a block diagram of the MCF5271 ports.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
12-1
General Purpose I/O Module
PORT
ADDR
PORT
DATAH
PORT
DATAL
PORT
BUSCTL
PORT
BS
PORT
CS
PORT
SDRAM
A[23:21] / CS[6:4] / PADDR[7:5]
PORT
FECI2C
D[15:8] / PDATAH[7:0]
D[7:0] / PDATAL[7:0]
OE / PBUSCTL[7]
TA / PBUSCTL[6]
TEA / DREQ[1] / PBUSCTL[5]
R/W / PBUSCTL[4]
TSIZ[1:0] / DACK[1:0] / PBUSCTL[3:2]
TS / DACK[2] / PBUSCTL[1]
TIP / DREQ[0] / PBUSCTL[0]
BS[3:0] / CAS[3:0] / PBS[3:0]
CS[7:4] / PCS[7:4]
CS[3:2] / SD_CS[1:0] / PCS[3:2]
CS[1] / PCS[1]
SD_WE / PSDRAM[5]
SD_SCAS / PSDRAM[4]
SD_SRAS / PSDRAM[3]
SD_SCKE / PSDRAM[2]
SD_CS[1:0] / PSDRAM[1:0]
PORT
UARTH
UARTL
PORT
QSPI
PORT
TIMER
FEC_EMDC / I2C_SCL / U2TXD / PFECI2C[3]
FEC_EMDIO / I2C_SDA / U2RXD / PFECI2C[2]
I2C_SCL / PFECI2C[1]
I2C_SDA / PFECI2C[0]
U2TXD / PUARTH[1]
U2RXD / PUARTH[0]
U1CTS / U2CTS / PUARTL[7]
U1RTS / U2RTS / PUARTL[6]
U1TXD / PUARTL[5]
U1RXD / PUARTL[4]
U0CTS / PUARTL[3]
U0RTS / PUARTL[2]
U0TXD / PUARTL[1]
U0RXD / PUARTL[0]
QSPI_PCS1 / SD_SCKE / PQSPI[4]
QSPI_PCS0 / PQSPI[3]
QSPI_SCK / I2C_SCL / PQSPI[2]
QSPI_DIN / I2C_SDA / PQSPI[1]
QSPI_DOUT / PQSPI[0]
T3IN / U2CTS / QSPI_PCS2 / PTIMER[7]
T3OUT / U2RTS / QSPI_PCS3 / PTIMER[6]
T2IN / DREQ[2] / T2OUT / PTIMER[5]
T2OUT / DACK[2] / PTIMER[4]
T1IN / DREQ[1] / T1OUT / PTIMER[3]
T1OUT / DACK[1] / PTIMER[2]
T0IN / DREQ[0] / PTIMER[1]
T0OUT / DACK[0] / PTIMER[0]
PIN ASSIGNMENT CONTROL
DRIVE STRENGTH CONTROL
IPBus
Figure 12-1. MCF5271 Ports Module Block Diagram
MCF5271 Reference Manual, Rev. 2
12-2 Freescale Semiconductor
External Signal Description
12.1.1 Overview
The MCF5271 ports module controls the configuration for various external pins, including those used for:
• External bus accesses
• External device selection
• Ethernet data and control
• I
2
C serial control
• QSPI
• 32-bit platform timers
12.1.2 Features
The MCF5271 ports includes these distinctive features:
• Control of primary function use
— On all supported GPIO ports
— On pins whose GPIO (or lack thereof) is not supported by MCF5271 ports module:
IRQ[7:1]
• General purpose I/O support for all ports
— Registers for storing output pin data
— Registers for controlling pin data direction
— Registers for reading current pin state
— Registers for setting and clearing output pin data registers
12.2 External Signal Description
The MCF5271 ports control the functionality of several external pins. These pins are listed in
Table 12-2 under the GPIO column.
After reset ports ADDR, DATAH, DATAL, BUSCTL, BS and CS are configured for external memory. They are available for the user as GPIO if the corresponding registers are set appropriately. All other ports default to GPIO after reset.
NOTE
In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e.,
A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 12-3
General Purpose I/O Module
NOTE
The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their
GPIO functionality.
Table 12-1. MCF5270 and MCF5271 Signal Information and Muxing
Signal Name GPIO Alternate 1
Alternate
2
Dir.
1
MCF5270
MCF5271
160 QFP
MCF5270
MCF5271
196 MAPBGA
RESET
RSTOUT
—
—
—
—
Reset
—
—
Clock
I
O
83
82
N13
P13
EXTAL
XTAL
CLKOUT
—
—
—
—
—
—
—
—
—
—
Mode Selection
— I
I
O
O
86
85
89
M14
N14
K14
CLKMOD[1:0
]
RCON
A[23:21]
A[20:0]
D[31:16]
D[15:8]
D[7:0]
BS[3:0]
OE
TA
— 20,21 G5,H5
—
PADDR[7:5]
—
—
PDATAH[7:0]
PDATAL[7:0]
PBS[7:4]
PBUSCTL7
PBUSCTL6
— — I
External Memory Interface and Ports
79
CS[6:4]
—
—
—
—
CAS[3:0]
—
—
—
—
—
—
—
—
—
—
K10
O
O
I
O 126, 125, 124 B11, C11, D11
O 123:115,
112:106, 102:98
A12, B12, C12,
A13, B13, B14,
C13, C14, D12,
D13, D14, E11,
E12, E13, E14,
F12, F13, F14,
G11, G12, G13
O 22:30, 33:39 G1, G2, H1, H2,
H3, H4, J1, J2,
J3, J4, K1, K2,
K3, K4, L1, L2
O
O
42:49 M1, N1, M2, N2,
P2, L3, M3, N3
50:52, 56:60 P3, M4, N4, P4,
L5, M5, N5, P5
143:140
62
96
B6, C6, D7, C7
N6
H11
MCF5271 Reference Manual, Rev. 2
12-4 Freescale Semiconductor
External Signal Description
Table 12-1. MCF5270 and MCF5271 Signal Information and Muxing (Continued)
Signal Name
TEA
R/W
TSIZ1
TSIZ0
TS
TIP
CS[7:4]
GPIO
PBUSCTL5
PBUSCTL4
PBUSCTL3
PBUSCTL2
PBUSCTL1
PBUSCTL0
PCS[7:4]
Alternate 1
Alternate
2
Dir.
1
DREQ1
—
DACK1
DACK0
DACK2
DREQ0
—
—
—
—
—
—
—
Chip Selects
— O
O
O
I
O
O
O
MCF5270
MCF5271
160 QFP
—
95
—
—
97
—
—
MCF5270
MCF5271
196 MAPBGA
J14
J13
P6
P7
H13
H12
132,131
B9, A10, C10,
A11
A9, C9 CS[3:2]
CS1
CS0
PCS[3:2] SD_CS[1:0
]
PCS1
—
—
—
—
—
—
SDRAM Controller
O
O
O
SD_WE
SD_SCAS
SD_SRAS
SD_CKE
PSDRAM5
PSDRAM4
PSDRAM3
PSDRAM2
SD_CS[1:0] PSDRAM[1:0
]
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
IRQ[7:3] PIRQ[7:3]
External Interrupts Port
— — I
130
129
92
91
90
139
—
B10
D10
K13
K12
K11
E8
L12, L13
IRQ2
IRQ1
PIRQ2
PIRQ1
DREQ2
—
IRQ7=63
IRQ4=64
—
65
N7, M7, L7, P8,
N8
M8
L8
EMDC
EMDIO
ECOL
ECRS
ERXCLK
ERXDV
PFECI2C3 I2C_SCL
PFECI2C2 I2C_SDA
—
—
—
—
—
—
—
—
—
—
FEC
U2TXD O
U2RXD I/O
—
— I
I
—
— I
I
I
I
151
150
9
8
7
6
D4
D5
E2
E1
D1
D2
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 12-5
General Purpose I/O Module
Table 12-1. MCF5270 and MCF5271 Signal Information and Muxing (Continued)
Signal Name GPIO Alternate 1
Alternate
2
Dir.
1
ERXD[3:0]
ERXER
ETXCLK
ETXEN
ETXER
ETXD[3:0]
I2C_SDA
I2C_SCL
—
—
—
—
—
—
PFECI2C1
PFECI2C0
—
—
—
—
—
—
—
—
—
—
I
2
C
—
—
—
—
—
—
DMA
I/O
I/O
U2TXD
U2RXD
U1CTS
U1RTS
U1TXD
U1RXD
U0CTS
U0RTS
U0TXD
DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads. Please refer to the following pins for muxing:
TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1,
TSIZ0 and DT0OUT for DACK0, IRQ2 and DT2IN for
DREQ2, TEA and DT1IN for DREQ1, and TIP and DT0IN for
DREQ0.
QSPI
QSPI_CS1
QSPI_CS0
QSPI_CLK
QSPI_DIN
QSPI_DOUT
PQSPI4
PQSPI3
PQSPI2
PQSPI1
PQSPI0
SD_CKE
—
I2C_SCL
I2C_SDA
—
—
—
—
—
—
UARTs
O
I
O
O
O
PUARTH1
PUARTH0
PUARTL7
PUARTL6
PUARTL5
PUARTL4
PUARTL3
PUARTL2
PUARTL1
—
—
U2CTS
U2RTS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
O
O
I
O
I
O
O
I
I
I
I
O
O
O
—
—
—
133
134
12
15
14
—
—
136
135
MCF5270
MCF5271
160 QFP
5:2
159
158
157
156
155:152
—
146
147
148
149
D9
D8
F3
G3
F1
A8
A7
B8
C8
MCF5270
MCF5271
196 MAPBGA
D3, C1, C2, B1
B2
A2
C3
B3
A3, A4, C4, B4
J12
J11
—
B7
A6
C5
B5
A5
MCF5271 Reference Manual, Rev. 2
12-6 Freescale Semiconductor
External Signal Description
Table 12-1. MCF5270 and MCF5271 Signal Information and Muxing (Continued)
Signal Name
U0RXD
GPIO
PUARTL0
Alternate 1
Alternate
2
Dir.
1
MCF5270
MCF5271
160 QFP
13
MCF5270
MCF5271
196 MAPBGA
F2
DT3IN
DT3OUT
DT2IN
DT2OUT
DT1IN
DT1OUT
DT0IN
DT0OUT
DSCLK
PSTCLK
BKPT
DSI
DSO
JTAG_EN
DDATA[3:0]
PST[3:0]
—
—
—
—
—
—
—
PTIMER7
PTIMER6
PTIMER5
PTIMER4
PTIMER3
PTIMER2
PTIMER1
PTIMER0
—
— —
DMA Timers
TRST
TCLK
TMS
TDI
TDO
—
—
U2CTS
U2RTS
DREQ2
DACK2
—
—
DT2OUT
—
DREQ1
DACK1
DREQ0
DACK0
DT1OUT
—
—
—
BDM/JTAG
2
—
—
—
—
—
—
—
I
I
O
I
O
I
O
I
O
O
I
O
O
I
O
O
— — O
72
78
—
70
68
71
73
61
—
10
11
—
—
66
—
77:74
N9
P9
P10
M10
N10
K9
M12, N12, P12,
L11
M11, N11, P11,
L10
L6
M6
E4
F4
H14
G14
M9
L9
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
12-7
General Purpose I/O Module
Table 12-1. MCF5270 and MCF5271 Signal Information and Muxing (Continued)
Signal Name GPIO Alternate 1
Alternate
2
Dir.
1
MCF5270
MCF5271
160 QFP
MCF5270
MCF5271
196 MAPBGA
TEST
PLL_TEST
—
—
—
—
Test
—
—
Power Supplies
I
I 19
—
F5
VDDPLL
VSSPLL
—
—
—
—
—
— I
I 87
84
M13
L14
OVDD
VSS
—
—
—
—
—
— I
I 1, 18, 32, 41,
55, 69, 81, 94,
105, 114, 128,
138, 145
E5, E7, E10, F7,
F9, G6, G8, H7,
H8, H9, J6, J8,
J10, K5, K6, K8
17, 31, 40, 54,
67, 80, 88, 93,
104, 113, 127,
137, 144, 160
A1, A14, E6, E9,
F6, F8, F10, G7,
G9, H6, J5, J7,
J9, K7, P1, P14
VDD — — — I 16, 53, 103 D6, F11, G4, L4
1
2
Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.
If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
Refer to the Chapter 2, “Signal Descriptions ,” for more detailed descriptions of these pins and
other pins not controlled by the ports module. The function of most of the pins (primary function,
GPIO, etc.) is determined by the ports module pin assignment registers. Refer to Section 2.3,
for detailed descriptions of pin functions.
It should be noted from
that there are several cases where a function is available on more than one pin. While it is possible to enable the function on more than one pin simultaneously, this type of programming should be avoided for input functions to prevent unexpected behavior.
All multiple-pin functions are listed in Table 12-2 .
Table 12-2. MCF5271 Multiple-Pin Functions
Function
Chip select 6 (CS6)
Chip select 5 (CS5)
Chip select 4 (CS4)
SDRAM Chip select 1(SD_CS1)
Direction
O
O
O
O
Associated Pins
CS6, A23
CS5, A22
CS4, A21
CS3, SD_CS1
MCF5271 Reference Manual, Rev. 2
12-8 Freescale Semiconductor
Memory Map/Register Definition
Table 12-2. MCF5271 Multiple-Pin Functions (Continued)
Function
SDRAM Chip select 0 (SD_CS0)
SDRAMC clock enable (SD_CKE)
I
2
C serial data (I2C_SDA)
I
2
C serial clock (I2C_SCL)
DMA request 2 (DREQ2)
DMA request 1 (DREQ1)
DMA request 0 (DREQ0)
DMA acknowledge 2 (DACK2)
DMA acknowledge 1 (DACK1)
DMA acknowledge 0 (DACK0)
UART2 transmit data (U2TXD)
UART2 receive data (U2RXD)
UART2 clear-to-send (U2CTS)
UART2 request-to-send (U2RTS)
Timer output 2 (DT2OUT)
Timer output 1 (DT1OUT)
Direction
O
O
I
O
O
I
O
O
I
O
I
I
O
O
I/O
I/O
Associated Pins
CS2, SD_CS0
SD_CKE, QSPI_CS1
I2C_SDA, QSPI_DIN, FEC_MDIO
I2C_SCL, QSPI_CLK, FEC_MDC
IRQ2, DT2IN
TEA, DT1IN
TIP, DT0IN
TS, DT2OUT
TSIZ1, DT1OUT
TSIZ0, DT0OUT
U2TXD, FEC_MDC
U2RXD, FEC_MDIO
DT3IN, U1CTS
DT3OUT, U1RTS
DT2OUT, DT2IN
DT1OUT, DT1IN
12.3 Memory Map/Register Definition
Table 12-3 summarizes all the registers in the MCF5271 ports address space.
Table 12-3. MCF5271 Ports Module Memory Map
IPSBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x10_0000
0x10_0004
0x10_0008
0x000C
0x10_0010
0x10_0014
0x10_0018
0x001C
PODR_ADDR
PODR_BS
PODR_UARTH
PDDR_ADDR
PDDR_BS
PDDR_UARTH
Port Output Data Registers
PODR_DATAH
PODR_CS
PODR_DATAL
PODR_SDRAM
PODR_UARTL
Reserved
3
PODR_QSPI
Port Data Direction Registers
PDDR_DATAH
PDDR_CS
PDDR_DATAL
PDDR_SDRAM
PDDR_UARTL
Reserved
2
PDDR_QSPI
PODR_BUSCTL
PODR_FECI2C
PODR_TIMER
PDDR_BUSCTL
PDDR_FECI2C
PDDR_TIMER
Access
1
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 12-9
General Purpose I/O Module
Table 12-3. MCF5271 Ports Module Memory Map (Continued)
IPSBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x10_0020
0x10_0024
0x10_0028
0x002C
PPDSDR_ADDR
PPDSDR_BS
PPDSDR_UARTH
Port Pin Data/Set Data Registers
PPDSDR_DATAH
PPDSDR_CS
PPDSDR_DATAL
PPDSDR_SDRAM
PPDSDR_UARTL PPDSDR_QSPI
Reserved
2
Port Clear Output Data Registers
PPDSDR_BUSCTL
PPDSDR_FECI2C
PPDSDR_TIMER
0x10_0030
0x10_0034
0x10_0038
0x003C
PCLRR_ADDR
PCLRR_BS
PCLRR_UARTH
PCLRR_DATAH
PCLRR_CS
PCLRR_DATAL
PCLRR_SDRAM
PCLRR_UARTL PCLRR_QSPI
Reserved
2
PCLRR_BUSCTL
PCLRR_FECI2C
PCLRR_TIMER
0x10_0040
0x10_0044
0x10_0048
0x004C
PAR_AD
PAR_BS
PAR_UART
PAR_TIMER
Port Pin Assignment Registers
Reserved
2
PAR_CS
PAR_BUSCTL
PAR_SDRAM
PAR_QSPI
Reserved
2
PAR_FECI2C
Reserved
2
Drive Strength Control Registers
0x0050
0x10_0054
DSCR_EIM
DSCR_QSPI
0x10_0058
–
0x10_007F
1
S/U = supervisor or user mode access.
Reserved
2
DSCR_TIMER
Reserved
2
DSCR_FECI2C
Reserved
2
DSCR_UART
Access
1
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
12.3.1 Register Descriptions
12.3.1.1 Port Output Data Registers (PODR_x)
The PODR_x registers store the data to be driven on the corresponding port pins when the pins are configured for general purpose output. The PODR_x registers are each 8 bits wide, but not all ports use all 8 bits. The register definitions for all ports are shown in
.
The PODR_x registers are read/write. At reset, all implemented bits in the PODR_x registers are set. Reserved bits always remain cleared.
MCF5271 Reference Manual, Rev. 2
12-10 Freescale Semiconductor
Memory Map/Register Definition
Reading a PODR_x register returns the current values in the register, not the port x pin values. To set bits in a PODR_x register, write 1s to the PODR_x bits, or write 1s to the corresponding bits in the PPDSDR_x register. To clear bits in a PODR_x register, write 0s to the PODR_x bits, or write
0s to the corresponding bits in the PCLRR_x register.
R
W
Reset
7 6 5 4
PODR_x
3 2 1 0
1 1 1 1 1 1 1 1
Address IPSBAR + 0x10_0001 (PODR_DATAH); IPSBAR + 0x10_0002 (PODR_DATAL);
IPSBAR + 0x10_0003 (PODR_BUSCTL); ;IPSBAR + 0x10_0009 (PODR_UARTL);
IPSBAR + 0x10_000B (PODR_TIMER)
Figure 12-2. Port x Output Data Registers (PODR_x)
R
W
Reset
7
0
6
0
5
0
4
0
3 2
PODR_x
1 0
0 0 0 0 1 1 1 1
Address IPSBAR + 0x10_0004 (PODR_BS); IPSBAR + 0x10_0007 (PODR_FECI2C)
Figure 12-3. Port x Output Data Registers (PODR_x)
R
W
Reset
7 6
PODR_ADDR
5 4
0
3
0
2
0
1
0
0
0
1 1 1 0 0 0 0 0
Address IPSBAR + 0x10_0000 (PODR_ADDR)
Figure 12-4. Port ADDR Output Data Register (PODR_ADDR)
R
W
Reset
7 6 5 4
PODR_CS
3 2 1 0
0
1 1 1 1 1 1 1 0
Address IPSBAR + 0x10_0005 (PODR_CS)
Figure 12-5. Port CS Output Data Register (PODR_CS)
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
12-11
General Purpose I/O Module
R
W
Reset
7
0
6
0
5 4 3 2
PODR_SDRAM
1 0
0 0 1 1 1 1 1 1
Address IPSBAR + 0x10_0006 (PODR_SDRAM)
Figure 12-6. Port SDRAM Output Data Register (PODR_SDRAM)
R
W
Reset
7
0
6
0
5
0
4
0
3
0
2
0
1 0
PODR_UARTH
0 0 0 0 0 0 1 1
Address IPSBAR + 0x10_0008 (PODR_UARTH)
Figure 12-7. Port UARTH Output Data Register (PODR_UARTH)
R
W
Reset
7
0
6
0
5
0
4 3 2
PODR_QSPI
1 0
0 0 0 1 1 1 1 1
Address IPSBAR + 0x10_000A (PODR_QSPI)
Figure 12-8. Port QSPI Output Data Register (PODR_QSPI)
Table 12-4. PODR_x Field Descriptions
Name Description
—
PODR_x
Reserved, should be cleared.
Port x output data bits.
0 Drives 0 when the port x pin is general purpose output
1 Drives 1 when the port x pin is general purpose output
Note: See above figures for bit field positions.
12.3.1.2 Port Data Direction Registers (PDDR_x)
The PDDRs control the direction of the port x pin drivers when the pins are configured for general purpose I/O. The PDDR_x registers are each eight bits wide, but not all ports use all eight bits. The register definitions for all ports are shown in
The PDDRs are read/write. At reset, all bits in the PDDRs are cleared. Setting any bit in a PDDR_x register configures the corresponding port x pin as an output. Clearing any bit in a PDDR_x register configures the corresponding pin as an input.
MCF5271 Reference Manual, Rev. 2
12-12 Freescale Semiconductor
Memory Map/Register Definition
R
W
Reset
7 6 5 4
PDDR_x
3 2 1 0
0 0 0 0 0 0 0 0
Address IPSBAR + 0x10_0011 (PDDR_DATAH); IPSBAR + 0x10_0012 (PDDR_DATAL);
IPSBAR + 0x10_0013 (PDDR_BUSCTL); IPSBAR + 0x10_0019 (PDDR_UARTL);
IPSBAR + 0x10_001B (PDDR_TIMER)
Figure 12-9. Port Data Direction Registers (PDDR_x)
R
W
Reset
7
0
6
0
5
0
4
0
3 2
PDDR_x
1 0
0 0 0 0 0 0 0 0
Address IPSBAR + 0x10_0014 (PDDR_BS); IPSBAR + 0x10_0017 (PDDR_FECI2C)
Figure 12-10. Port Data Direction Registers (PDDR_x)
R
W
Reset
7 6
PDDR_ADDR
5 4
0
3
0
2
0
1
0
0
0
0 0 0 0 0 0 0 0
Address IPSBAR + 0x10_0010 (PDDR_ADDR)
Figure 12-11. Port ADDR Data Direction Register (PDDR_ADDR)
R
W
Reset
7 6 5 4
PDDR_CS
3 2 1 0
0
0 0 0 0 0 0 0 0
Address IPSBAR + 0x10_0015 (PDDR_CS)
Figure 12-12. Port CS Data Direction Register (PDDR_CS)
R
W
Reset
7
0
6
0
5 4 3 2
PDDR_SDRAM
1 0
0 0 0 0 0 0 0 0
Address IPSBAR + 0x10_0016 (PDDR_SDRAM)
Figure 12-13. Port SDRAM Data Direction Register (PDDR_SDRAM)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 12-13
General Purpose I/O Module
R
W
Reset
7
0
6
0
5
0
4
0
3
0
2
0
1 0
PDDR_UARTH
0 0 0 0 0 0 0 0
Address IPSBAR + 0x10_0018 (PDDR_UARTH)
Figure 12-14. Port UARTH Data Direction Register (PDDR_UARTH)
R
W
Reset
7
0
6
0
5
0
4 3 2
PDDR_QSPI
1 0
0 0 0 0 0 0 0 0
Address IPSBAR + 0x10_001A (PDDR_QSPI)
Figure 12-15. Port QSPI Data Direction Register (PDDR_QSPI)
Table 12-5. PDDR_x Field Descriptions
Name Description
—
PDDR_x
Reserved, should be cleared.
Port x output data direction bits.
1 Port x pin configured as output
0 Port x pin configured as input
Note: See above figures for bit field positions.
12.3.1.3 Port Pin Data/Set Data Registers (PPDSDR_x)
The PPDSDR_x registers reflect the current pin states and control the setting of output pins when the pin is configured for general purpose I/O. The PPDSDR_x registers are each eight bits wide, but not all ports use all eight bits. The register definitions for all ports are shown in
The PPDSDR_x registers are read/write. At reset, the bits in the PPDSDR_x registers are set to the current pin states. Reading a PPDSDR_x register returns the current state of the port x pins. Setting a PPDSDR_x register sets the corresponding bits in the PODR_x register. Writing 0s has no effect.
12-14
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
R
W
Reset
7 6 5 4
PPDSDR_x
3 2 1 0
Current Pin State
Address IPSBAR + 0x10_0021 (PPDSDR_DATAH); IPSBAR + 0x10_0022 (PPDSDR_DATAL);
IPSBAR + 0x10_0023 (PPDSDR_BUSCTL); IPSBAR + 0x10_0029 (PPDSDR_UARTL);
IPSBAR + 0x10_002B (PPDSDR_TIMER)
Figure 12-16. Port Pin Data/Set Data Registers (PPDSDR_x)
R
W
Reset
7
0
6
0
5
0
4
0
3 2
PPDSDR_x
1 0
0 0 0 0 Current Pin State
Address IPSBAR + 0x10_0024 (PPDSDR_BS); IPSBAR + 0x10_0027 (PPDSDR_FECI2C)
Figure 12-17. Port Pin Data/Set Data Registers (PPDSDR_x)
R
W
Reset
7 6
PPDSDR_ADDR
5 4
0
3
0
2
0
1
0
0
0
Current Pin State 0 0 0 0 0
Address IPSBAR + 0x10_0020 (PPDSDR_ADDR)
Figure 12-18. Port ADDR Pin Data/Set Data Register (PPDSDR_ADDR)
R
W
Reset
7 6 5 4
PPDSDR_CS
3 2 1 0
0
Current pin state 0
Address IPSBAR + 0x10_0025 (PPDSDR_CS)
Figure 12-19. Port CS Pin Data/Set Data Register (PPDSDR_CS)
R
W
Reset
7
0
6
0
5 4 3 2
PPDSDR_SDRAM
1 0
0 0 Current pin state
Address IPSBAR + 0x10_0026 (PPDSDR_SDRAM)
Figure 12-20. Port SDRAM Pin Data/Set Data Register (PPDSDR_SDRAM)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 12-15
General Purpose I/O Module
R
W
Reset
7
0
6
0
5
0
4
0
3
0
2
0
1 0
PPDSDR_UARTH
0 0 0 0 0 0 Current pin state
Address IPSBAR + 0x10_0028 (PPDSDR_UARTH)
Figure 12-21. Port UARTH Pin Data/Set Data Register (PPDSDR_UARTH)
R
W
Reset
7
0
6
0
5
0
4 3 2
PPDSDR_QSPI
1 0
0 0 0 Current Pin State
Address IPSBAR + 0x10_002A (PPDSDR_QSPI)
Figure 12-22. Port QSPI Pin Data/Set Data Register (PPDSDR_QSPI)
Table 12-6. PPDSDR_x Field Descriptions
Name Description
—
PPDSDR_x
Reserved, should be cleared.
Port x Pin Data/Set Data Bits.
0 Port x pin state is 0 (read)
1 Port x pin state is 1 (read); set corresponding PODR_x bit (write)
Note: See above figures for bit field positions.
12.3.1.4 Port Clear Output Data Registers (PCLRR_x)
Clearing a PCLRR_x register clears the corresponding bits in the PODR_x register. Setting it has no effect. Reading the PCLRR_x register returns 0s. Most PODR_x registers have a full 8-bit implementation, as shown in
Figure 12-23 . The remaining PODR_x registers use fewer than eight
bits. Their bit definitions are shown in
The PCLRR_x registers are read/write accessible.
R
W
Reset
7
0
6
0
5
0
4
0
0
PCLRR_x
0
3
0
2
0
1
0
0
0
0 0 0 0 0 0
Address IPSBAR + 0x10_0031 (PCLRR_DATAH); IPSBAR + 0x10_0032 (PCLRR_DATAL);
IPSBAR + 0x10_0033 (PCLRR_BUSCTL); IPSBAR + 0x10_0039 (PCLRR_UARTL);
IPSBAR + 0x10_003B (PCLRR_TIMER)
Figure 12-23. Port Clear Output Data Registers (PCLRR_x)
MCF5271 Reference Manual, Rev. 2
12-16 Freescale Semiconductor
Memory Map/Register Definition
R
W
Reset
7
0
6
0
5
0
4
0
3
0
2
0
0
PCLRR_x
0
1
0
0
0
0 0 0 0 0 0
Address IPSBAR + 0x10_0034 (PCLRR_BS); IPSBAR + 0x10_0037 (PCLRR_FECI2C)
Figure 12-24. Port Clear Output Data Registers (PCLRR_x)
R
W
Reset
7
0
6
0
0
PCLRR_ADDR
0 0
5
0
4
0
3
0
2
0
1
0
0
0
0 0 0 0 0
Address IPSBAR + 0x10_0030 (PCLRR_ADDR)
Figure 12-25. Port ADDR Clear Output Data Register (PCLRR_ADDR)()
R
W
Reset
7
0
6
0
5
0
4
0
PCLRR_CS
0
3
0
2
0
1
0
0
0
0 0 0 0 0 0 0
Address IPSBAR + 0x10_0035 (PCLRR_CS)
Figure 12-26. Port CS Clear Output Data Register (PCLRR_CS)
R
W
Reset
7
0
6
0
5
0
4
0
3
0
2
0
PCLRR_SDRAM
0 0
1
0
0
0
0 0 0 0 0 0
Address IPSBAR + 0x10_0036 (PCLRR_SDRAM)
Figure 12-27. Port SDRAM Clear Output Data Register (PCLRR_SDRAM)
R
W
Reset
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
PCLRR_UARTH
0 0 0 0 0 0 0 0
Address IPSBAR + 0x10_0038 (PCLRR_UARTH)
Figure 12-28. Port UARTH Clear Output Data Register (PCLRR_UARTH)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 12-17
General Purpose I/O Module
R
W
Reset
7
0
6
0
5
0
4
0
3
0
2
0
0
PCLRR_QSPI
0 0
1
0
0
0
0 0 0 0 0
Address IPSBAR + 0x10_003A (PCLRR_QSPI)
Figure 12-29. Port QSPI Clear Output Data Register (PCLRR_QSPI)
Table 12-7. PCLRR_x Field Descriptions
Name Description
—
PCLRR_x
Reserved, should be cleared.
Port x clear Data Bits.
0 Always returned for reads; clears corresponding
PODR_x bit for writes
1 Never returned for reads; no effect for writes
Note: See above figures for bit field positions.
12.3.1.5 Pin Assignment Registers (PAR_x)
The pin assignment registers control which functions are currently active on the external pins. All pin assignment registers are read/write.
12.3.1.5.1 Address/Data Pin Assignment Register (PAR_AD)
The PAR_AD register controls the functions of the A[23:21] pins and the D[15:0] pins.
Reset
Address
7 6 5
R PAR_
W
ADDR23
PAR_
ADDR22
PAR_
ADDR21
See Note
4
0
3
0
0 0
IPSBAR + 0x10_0040
2
0
0
1
0
0
0
PAR_
DATAL
See Note
Note: Reset state determined during reset configuration as shown in
Figure 12-30. Address/Data Pin Assignment Register (PAR_AD)
12-18
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
Table 12-8. Reset Values for PAR_AD Bits
Mode of
Operation
Port Size of
External Boot
Device
1
PAR_ADDR23
Reset Value
PAR_ADDR22
Reset Value
PAR_ADDR21
Reset Value
PAR_DATAL
Reset Value
Master mode 8-bit
16-bit
1
1
1
1
1
1
0
0
32-bit 1 1 1 1
1
Note if the port size of the external boot device is 8-bit or 16-bit, and the port size of the external SDRAM is 32-bit, the PAR_AD register must be written after reset to enable the primary functions on the D[15:0] pins before any
SDRAM accesses are attempted.
Table 12-9. PAR_AD Field Descriptions
Bits Name Description
7–5 PAR_ADDR The PAR_ADDR bits configure each of the A[23:21] pins for one of their primary functions or GPIO.
0 A[23:21] pin configured for GPIO
1 A[23:21] pin configured for address bit 23–21 function or CS[6:4] function
1
— Reserved, should be cleared.
4–1
0 PAR_DATAL The PAR_DATAL bit configures the D[15:0] pins for their primary functions or GPIO.
0 D[15:0] pins configured for GPIO
1 D[15:0] pins configured for data 15-0 functions
1
The selection between the address function and chip select function on each of the A[23:21] pins is determined by the value of the RCSC field in the CIM reset configuration register.
12.3.1.5.2 External Bus Control Pin Assignment Register (PAR_BUSCTL)
The PAR_BUSCTL register controls the functions of the external bus control signal pins.
15 14
R 0 PAR_
W
OE
13 12
0 PAR_
TA
11 10
PAR_TEA
9 8
0 PAR_
RWB
7 6
0 PAR_
TSIZ1
5 4
0 PAR_
TSIZ0
3 2
PAR_TS
1 0
PAR_TIP
Reset 0
Address
1 0 1 1 1 0 1 0 1 0 1 1 1
IPSBAR + 0x10_0042
Figure 12-31. External Bus Control Pin Assignment (PAR_BUSCTL)
1 1
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
12-19
General Purpose I/O Module
Table 12-10. PAR_BUSCTL Field Descriptions
Bits Name
15
14
13
12
11–10
9
8
7
6
5
4
—
—
Reserved, should be cleared.
Description
PAR_OE OE Pin Assignment Bit
The PAR_OE bit configures the OE pin for its primary function or GPIO.
0 OE pin configured for GPIO
1 OE pin configured for external bus OE function
Reserved, should be cleared.
PAR_TA TA pin assignment. The PAR_TA bit configures the OE pin for its primary function or GPIO.
0 TA pin configured for GPIO
1 TA pin configured for external bus TA function
PAR_TEA TEA pin assignment. The PAR_TEA field configures the TEA pin for its primary functions or GPIO.
0x TEA pin configured for general purposeI/O
10 TEA pin configured for DMA request 1 (DREQ1) function
11 TEA pin configured for external bus TEA function
— Reserved, should be cleared
PAR_RWB R/W Pin Assignment Bit
The PAR_RWB bit configures the R/W pin for its primary function or GPIO.
0 R/W pin configured for GPIO
1 R/W pin configured for external bus read/write function
— Reserved, should be cleared
PAR_TSIZ1 TSIZ[1] Pin Assignment Bits
The PAR_TSIZ1 bit configures the TSIZ[1] pin for its primary functions or GPIO.
0 TSIZ[1] pin configured for GPIO
1 TSIZ[1] pin configured for external bus TSIZ1 function or DMA acknowledge 1 function
NOTE: The selection between the TSIZ function and DMA function on each of the
TSIZ[1:0] pins is determined by the value of the SZEN field in the CIM chip configuration
register. Please refer to the Chapter 9, “Chip Configuration Module (CCM)
” for more information on chip configuration and the SZEN bit.
— Reserved, should be cleared
PAR_TSIZ0 TSIZ[0] Pin Assignment Bit
The PAR_TSIZ0 bit configures the TSIZ[0] pin for its primary functions or GPIO.
0 TSIZ[0] pin configured for GPIO
1 TSIZ[0] pin configured for external bus TSIZ0 function or DMA acknowledge 0 function
NOTE: The selection between the TSIZ function and DMA function on each of the
TSIZ[1:0] pins is determined by the value of the SZEN field in the CIM chip configuration
register. Please refer to the Chapter 9, “Chip Configuration Module (CCM)” for more
information on chip configuration and the SZEN bit.
12-20
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
Table 12-10. PAR_BUSCTL Field Descriptions (Continued)
Bits Name
3–2
1–0
PAR_TS TS Pin Assignment Field.
Description
The PAR_TS field configures the TS pin for one of its primary functions or GPIO.
0x TS pin configured for GPIO
10 TS pin configured for DMA acknowledge 2 function
11 TS pin configured for external bus TS function
PAR_TIP TIP Pin Assignment Field .
The PAR_TIP field configures the TIP pin for one of its primary functions or GPIO.
0x TIP pin configured for GPIO
10 TIP pin configured for DMA request 0 function
11 TIP pin configured for external bus TIP function
12.3.1.5.3 Byte Strobe Pin Assignment Register (PAR_BS)
The PAR_BS register controls the functions of the byte strobe pins.
Bits
7–4
3–0
R
W
Reset
7
0
6
0
5
0
4
0
3 2
PAR_BS
1 0
0 0 0 0 1 1 1 1
Address IPSBAR + 0x10_0044
Figure 12-32. Byte Strobe Pin Assignment Register (PAR_BS)
Table 12-11. PAR_BS Field Descriptions
Name Description
— Reserved, should be cleared.
PAR_BS BS[3:0] pin assignment. The PAR_BS[3:0] bits configure the BS[3:0] pins for their primary function or GPIO.
0 BS[3:0] pin configured for GPIO
1 BS[3:0] pin configured for BS[3:0] function
Refer to Chapter 9, “Chip Configuration Module (CCM)
” for more information on reset configuration.
12.3.1.5.4 Chip Select Pin Assignment Register (PAR_CS)
The PAR_CS register controls the functions of the EIM chip select pins.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
12-21
General Purpose I/O Module
Bits
7–4
3–2
1
R
W
Reset
7 6 5 4
PAR_CS
3 2 1 0
0
1 1 1 1 1 1 1 0
Address IPSBAR + 0x10_0045
Figure 12-33. Chip Select Pin Assignment Register (PAR_CS)
Table 12-12. PAR_CS Field Descriptions
Name Description
PAR_CS CS[7:4] pin assignment. The PAR_CS[7:4] bits configure the CS[7:4] pins for their primary functions or GPIO.
0 CS[7:4] pins configured for GPIO
1 CS[7:4] pins configured for EIM CS[7:4] function
CS[3:2] Pin Assignment Bit. The PAR_CS[3:2] bits configure the CS[3:2] pins for their primary functions or GPIO.
0 CS[3:2] pins configured for GPIO
1 CS[3:2] pins configured for EIM CS[3:2] or SD_CS[1:0] function
—
Note: The selection between the EIM chip select function and SDRAMC chip select function on each of the CS[3:2] pins is determined by the value of the PAR_SDRAM[7:6]
bits. See Section 12.3.1.5.5, “SDRAM Control Pin Assignment Register (PAR_SDRAM) ,”
for more details on the PAR_SDRAM bits.
CS1 Pin Assignment Bit. The PAR_CS1 bit configures the CS1 pin for its primary function or GPIO.
0 CS1 pin configured for GPIO
1 CS1 pin configured for EIM CS1 function
Reserved, should be cleared.
0
12.3.1.5.5 SDRAM Control Pin Assignment Register (PAR_SDRAM)
The PAR_SDRAM register controls the function of the SDRAM controller pins.
W
Reset
7 6
R PAR_CSSDCS
0 0
5
PAR_
SDWE
4
PAR_
SCAS
3
PAR_
SRAS
2
PAR_
SCKE
1 0
PAR_SDCS
1 1 1 1 1 1
Address IPSBAR + 0x10_0046
Figure 12-34. SDRAM Control Pin Assignment (PAR_SDRAM)
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MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Bits
7–6
5
4
3
2
1–0
Memory Map/Register Definition
Table 12-13. PAR_SDRAM Field Descriptions
Name Description
PAR_CSSDC
S
CS[3:2] pin primary function selection. The PAR_CSSDCS field configures each of the
CS[3:2] pins for one of its primary functions (either EIM chip select or SDRAMC chip select) when the PAR_CS[3:2] bits are 1s. The PAR_CSSDCS values have no effect on the
CS[3:2] pin functions when the PAR_CS[3:2] bits are 0s. Refer to
Select Pin Assignment Register (PAR_CS)
,” for more information on the PAR_CS bits.
CS3 CS2
00
01
10
11
CS3
CS3
SD_CS1
SD_CS1
CS2
SD_CS0
CS2
SD_CS0
Note: Only valid when PAR_CS[3:2] = 1.
PAR_SDWE SD_WE pin assignment. This bit configures the SD_WE pin for its primary function or
GPIO.
0 SD_WE pin configured for GPIO
1 SD_WE pin configured for SDRAMC WE function
PAR_SCAS SD_SCAS pin assignment. This bit configures the SD_SCAS pin for its primary function or
GPIO.
0 SD_SCAS pin configured for GPIO
1 SD_SCAS pin configured for SDRAMC CAS function
PAR_SRAS SD_SRAS pin assignment. This bit configures the SD_SRAS pin for its primary function or
GPIO.
0 SD_SRAS pin configured for GPIO
1 SD_SRAS pin configured for SDRAMC SRAS function
PAR_SCKE SD_CKE pin assignment. This bit configures the SD_CKE pin for its primary function or
GPIO.
0 SD_CKE pin configured for GPIO
1 SD_CKE pin configured for SDRAMC clock enable function
PAR_SDCS SD_CS[1:0] pin assignment. These bits configure the SD_CS[1:0] pins for their primary functions or GPIO.
0 SD_CS[1:0] pin configured for GPIO
1 SD_CS[1:0] pin configured for SD_CS[1:0] function
12.3.1.5.6 FEC/I2C Pin Assignment Register (PAR_FECI2C)
The PAR_FECI2C register controls the functions of the I
2
C and FEC pins.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
12-23
General Purpose I/O Module
Bits
7-0
W
Reset
7 6
R PAR_EMDC
0 0
5 4
PAR_EMDIO
3 2
PAR_SCL
1 0
PAR_SDA
0 0 0 0 0 0
Address IPSBAR + 0x10_0047
Figure 12-35. FEC/I2C Pin Assignment (PAR_FECI2C)
Table 12-14. PAR_FECI2C Field Descriptions
Name
PAR_EMDC
PAR_EMDIO
PAR_SCL
PAR_SDA
Description
FEC & I
2
C pin assignment. These bit fields configure the EMDC, EMDIO, I2C_SCL, and
I2C_SDA pins for one of their primary functions or GPIO.
PAR_EMDC PAR_EMDIO PAR_SCL PAR_SDA
00
01
10
11
GPIO
U2TXD
GPIO
U2RXD
GPIO
GPIO
I2C_SCL I2C_SDA Reserved
FEC_EMDC FEC_EMDIO I2C_SCL
GPIO
GPIO
Reserved
I2C_SDA
12.3.1.5.7 UART/IRQ2 Pin Assignment Register (PAR_UART)
The PAR_UART register controls the functions of the UART and IRQ2 pins.
15
R PAR_
DREQ2
W
Reset 0
Address
14
0
13 12 11 10 9 8 7 6
PAR_
U2RXD
PAR_
U2TXD
PAR_U1RXD PAR_U1TXD PAR_U1CTS
5 4
PAR_U1RTS
3 2 1 0
PAR_
U0RXD
PAR_
U0TXD
PAR_
U0CTS
PAR_
U0RTS
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x10_0048
Figure 12-36. UART Pin Assignment (PAR_UART)
0
Table 12-15. PAR_UART Field Descriptions
0 0
Bits Name
15
14
Description
PAR_DREQ2 IRQ2 pin assignment. This bit configures the IRQ2 pin for its IRQ function or its DMA
— function.
0 IRQ2 pin configured for IRQ 2 function
1 IRQ2 pin configured for DMA request 2 (DREQ2) function
Note: GPIO on the IRQ2 pin is obtained by (1) writing a 0 to the PAR_DREQ2 bit and
(2) disabling the IRQ 2 function in the EPORT module.
Reserved, should be cleared.
0
MCF5271 Reference Manual, Rev. 2
12-24 Freescale Semiconductor
Memory Map/Register Definition
Table 12-15. PAR_UART Field Descriptions (Continued)
Bits Name
13
12
11–4
Description
PAR_U2RXD U2RXD pin assignment. This bit configures the U2RXD pin for its primary function or
GPIO.
0 U2RXD pin configured for GPIO
1 U2RXD pin configured for UART2 receive data function
PAR_U2TXD U2TXD pin assignment. This bit configures the U2TXD pin for its primary function or
GPIO.
0 U2TXD pin configured for GPIO
1 U2TXD pin configured for UART2 transmit data function
PAR_U1RXD
PAR_U1TXD
PAR_U1CTS
PAR_U1RTS
UART 1 pin assignment. These bit fields configure the U1RXD, U1TXD, U1CTS, and
U1RTS pins for one of their primary functions or GPIO.
PAR_U1RXD PAR_U1TXD PAR_U1CTS
PAR_U1RT
S
00
01
10
11
GPIO
GPIO
Reserved
U1RXD
GPIO
GPIO
Reserved
U1TXD
GPIO
GPIO
U2CTS
U1CTS
GPIO
GPIO
U2RTS
U1RTS
12.3.1.5.8 QSPI Pin Assignment Register (PAR_QSPI)
The PAR_QSPI register controls the functions of the QSPI pins.
Bits
7–6
5
R
W
Reset
7 6
PAR_CS1
5
PAR_
CS0
4
PAR_DIN
3 2
PAR_
DOUT
1 0
PAR_SCK
0 0 0 0 0 0 0 0
Address IPSBAR + 0x10_004A
Figure 12-37. QSPI Pin Assignment Register (PAR_QSPI)
Table 12-16. PAR_QSPI Field Descriptions
Name Description
PAR_CS1 QSPI_CS1 pin assignment. This field configures the QSPI_CS1 pin for one of its primary functions or GPIO.
0x QSPI_CS1 pin configured for GPIO
10 QSPI_CS1 pin configured for SDRAMC SCKE function
11 QSPI_CS1 pin configured for QSPI CS1 function
PAR_CS0 QSPI_CS0 pin assignment. This bit configures the QSPI_CS0 pin for its primary function or GPIO.
0 QSPI_PSC0 pin configured for GPIO
1 QSPI_PSC0 pin configured for QSPI CS0 function
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Freescale Semiconductor 12-25
General Purpose I/O Module
Bits
4–3
2
1–0
Table 12-16. PAR_QSPI Field Descriptions (Continued)
Name Description
PAR_DIN QSPI_DIN pin assignment. This field configures the QSPI_DIN pin for one of its primary functions or GPIO.
0x QSPI_DIN pin configured for GPIO
10 QSPI_DIN pin configured for I
2
C SDA function
11 QSPI_DIN pin configured for QSPI DIN function
PAR_DOUT QSPI_DOUT pin assignment. This bit configures the QSPI_DOUT pin for its primary function or GPIO.
0 QSPI_DOUT pin configured for GPIO
1 QSPI_DOUT pin configured for QSPI DOUT function
PAR_SCK QSPI_SCK pin assignment. This field configures the QSPI_SCK pin for one of its primary functions or GPIO.
0x QSPI_SCK pin configured for GPIO
10 QSPI_SCK pin configured for I
2
C SCL function
11 QSPI_SCK pin configured for QSPI SCK function
12.3.1.6 Timer Pin Assignment Registers (PAR_TIMERH & PAR_TIMERL)
The PAR_TIMER register controls the functions of the DMA timer pins.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PAR_DT3IN PAR_DT2IN PAR_DT1IN PAR_DT0IN PAR_DT3OUT PAR_DT2OUT PAR_DT1OUT PAR_DT0OUT
W
Reset 0
Address
0 0 0 0 0 0 0 0 0
IPSBAR + 0x10_004C
0 0 0
Figure 12-38. Timer Pin Assignment Register (PAR_TIMER)
0 0 0
12-26
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Bits
15–8
7–0
Memory Map/Register Definition
Table 12-17. PAR_TIMER Field Description
Name
PAR_DT3IN
PAR_DT2IN
PAR_DT1IN
PAR_DT0IN
Description
Timer input pin assignment. These bit fields configure the DT3IN, DT2IN, DT1IN, and
DT0IN pins for one of their primary functions or GPIO.
00
01
10
11
PAR_T3IN
GPIO
QSPI_CS2
U2CTS
DT3IN
PAR_T2IN
GPIO
DT2OUT
DREQ2
DT2IN
PAR_T1IN
GPIO
DT1OUT
DREQ1
DT1IN
PAR_T0IN
GPIO
GPIO
DREQ0
DT0IN
PAR_DT3OUT
PAR_DT2OUT
PAR_DT1OUT
PAR_DT0OUT
Timer output pin assignment. These bit fields configure the DT3OUT, DT2OUT,
DT1OUT, and DT0OUT pins for one of their primary functions or GPIO.
PAR_T3OUT PAR_T2OUT PAR_T1OUT
PAR_T0OU
T
00
01
10
11
GPIO
QSPI_CS3
U2RTS
DT3OUT
GPIO
GPIO
DACK2
DT2OUT
GPIO
GPIO
DACK1
DT1OUT
GPIO
GPIO
DACK0
DT0OUT
12.3.1.7 Drive Strength Control Registers (DSCR_x)
The drive strength control registers set the output pin drive strengths. All drive strength control registers are read/write.
12.3.1.7.1 External Bus Drive Strength Control Register (DSCR_EIM)
The DSCR_EIM register controls the output drive strengths of several external bus pins: A[23:0],
D[31:0], BS[3:0], OE, R/W, CS[7:0], SD_SCAS, SD_SRAS, SD_WE, SCKE, SD_CS[1:0],
RSTOUT, TA, TEA, TIP, TS, and TSIZ[1:0].
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
12-27
General Purpose I/O Module
Bits
7–5
4
Reset
Address
R
W
7
0
0
6
0
0
5
0
0
4
DSCR_
EIM1
3
0
See Note 0
IPSBAR + 0x10_0050
0
2
0
1
0
0
0
DSCR_
EIM0
See Note
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Figure 12-39. External Bus Drive Strength Control Register (DSCR_EIM)
3–1
0
Table 12-18. DSCR_EIM Field Descriptions
Name Description
— Reserved, should be cleared.
DSCR_EIM1 EIM function drive strength 1. This bit sets the drive strength on the following pins:
A[23:0], D[31:0], BS[3:0], OE, R/W, CS[7:0], SD_SCAS, SD_SRAS, SD_WE, SCKE,
SD_CS[1:0], and RSTOUT.
0 Pins set at low drive
1 Pins set at high drive
— Reserved, should be cleared.
DSCR_EIM0 EIM function drive strength 0. The DSCR_EIM0 bit sets the drive strength on the following pins: TA, TEA, TIP, TS, and TSIZ[1:0].
0 Pins set at low drive
1 Pins set at high drive
12.3.1.7.2 FEC/I2C Drive Strength Control Register (DSCR_FECI2C)
The DSCR_FECI2C register controls the output drive strengths of the following pins: EMDC,
EMDIO, I2C_SDA, and I2C_SCL.
Reset
Address
R
W
7
0
0
6
0
0
5
0
0
4
DSCR_
FEC
3
0
See Note 0
IPSBAR + 0x10_0052
0
2
0
1
0
0
0
DSCR_
I2C
See Note
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Figure 12-40. FEC/I2C Drive Strength Control Register (DSCR_FECI2C)
12-28
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Bits
7–5
4
3–1
0
Memory Map/Register Definition
Table 12-19. DSCR_FECI2C Field Descriptions
Name Description
— Reserved, should be cleared.
DSCR_FEC EMDC, EMDIO output drive strength. This bit sets the drive strength on the EMDC and
EMDIO pins.
0 EMDC and EMDIO set at low drive
1 EMDC and EMDIO set at high drive
— Reserved, should be cleared.
DSCR_I2C I2C_SDA, I2C_SCL output drive strength. This bit sets the drive strength on the I2C_SDA and I2C_SCL pins.
0 I2C_SDA and I2C_SCL set at low drive
1 I2C_SDA and I2C_SCL set at high drive
12.3.1.7.3 UART/IRQ Drive Strength Control Register (DSCR_UART)
The DSCR_UART register controls the output drive strengths of the following pins: U2RXD,
U2TXD, U1RTS, U1CTS, U1RXD, U1TXD, U0RTS, U0CTS, U0RXD, U0TXD, and IRQ[7:1].
Bits
7
6
3
2
5
4
Reset
Address
R
W
7
0
0
6
DSCR_
IRQ
See Note
5
0
0
4
DSCR_
UART2
3
0
2
DSCR_
UART1
See Note 0
IPSBAR + 0x10_0053
See Note
1
0
0
0
DSCR_
UART0
See Note
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when RCON = 0
Figure 12-41. UART/IRQ Drive Strength Control Register (DSCR_UART)
Table 12-20. DSCR_UART Field Descriptions
Name Description
— Reserved, should be cleared.
DSCR_IRQ IRQ drive strength. This bit sets the drive strength on the IRQ[7:1] pins.
0 IRQ[7:1] pins set at low drive
1 IRQ[7:1] pins set at high drive
Reserved, should be cleared.
—
DSCR_
UART2
UART2 drive strength. This bit sets the drive strength on the U2RXD and U2TXD pins.
0 U2RXD, U2TXD pins set at low drive
1 U2RXD, U2TXD pins set at high drive
—
DSCR_
UART1
Reserved, should be cleared.
UART1 drive strength. This bit sets the drive strength on the U1RXD, U1TXD, U1CTS, and
U1RTS pins.
0 U1RXD, U1TXD, U1CTS, and U1RTS pins set at low drive
1 U1RXD, U1TXD, U1CTS, and U1RTS pins set at high drive
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 12-29
General Purpose I/O Module
Bits
1
0
Table 12-20. DSCR_UART Field Descriptions (Continued)
Name
—
DSCR_
UART0
Description
Reserved, should be cleared.
UART0 drive strength. This bit sets the drive strength on the U0RXD, U0TXD, U0CTS, and
U0RTS pins.
0 U0RXD, U0TXD, U0CTS, and U0RTS pins set at low drive
1 U0RXD, U0TXD, U0CTS, and U0RTS pins set at high drive
12.3.1.7.4 QSPI Drive Strength Control Register (DSCR_QSPI)
The DSCR_QSPI register controls the output drive strengths of the following pins: QSPI_CS1,
QSPI_CS0, QSPI_SCK, QSPI_DIN, and QSPI_DOUT.
Bits
7–1
0
R
W
Reset
Address
7
0
0
6
0
0
5
0
0
4
0
3
0
0 0
IPSBAR + 0x10_0054
0
2
0
1
0
0
0
DSCR_
QSPI
See Note
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Figure 12-42. QSPI Drive Strength Control Register (DSCR_QSPI)
Table 12-21. DSCR_QSPI Field Descriptions
Name Description
— Reserved, should be cleared.
DSCR_QSPI QSPI drive strength. This bit sets the drive strength on the QSPI_CS1, QSPI_CS0,
QSPI_SCK, QSPI_DIN, and QSPI_DOUT pins.
0 Pins set at low drive
1 Pins set at high drive
12.3.1.7.5 Timer Drive Strength Control Register (DSCR_TIMER)
The DSCR_TIMER register controls the output drive strengths of the following pins: DT3IN,
DT3OUT, DT2IN, DT2OUT, DT1IN, DT1OUT, DT0IN, and DT0OUT.
12-30
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Functional Description
Bits
7–1
0
R
W
Reset
Address
7
0
0
6
0
0
5
0
0
4
0
3
0
0 0
IPSBAR + 0x10_0055
0
2
0
1
0
0
0
DSCR_
TIMER
See Note
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Figure 12-43. Timer Drive Strength Control Register (DSCR_TIMER)
Name
—
DSCR_
TIMER
Table 12-22. DSCR_TIMER Field Descriptions
Description
Reserved, should be cleared.
Timer drive strength. This bit sets the drive strength on the DT3IN, DT3OUT, DT2IN,
DT2OUT, DT1IN, DT1OUT, DT0IN, and DT0OUT pins.
0 Pins set at low drive
1 Pins set at high drive
12.4 Functional Description
12.4.1 Overview
Initial pin function is determined during reset configuration. The pin assignment registers allow the user to select among various primary functions and general purpose I/O after reset.
Most pins are configured as general purpose I/O by default. The notable exceptions to this are external bus control pins, address/data pins, and chip select pins. These pins are configured for their primary functions after reset.
Every general purpose I/O pin is individually configurable as an input or an output via a data direction register (PDDR_x).
Every GPIO port has an output data register (PODR_x) and a pin data register (PPDSDR_x) to monitor and control the state of its pins. Data written to a PODR_x register is stored and then driven to the corresponding port x pins configured as outputs.
Reading a PODR_x register returns the current state of the register regardless of the state of the corresponding pins.
Reading a PPDSDR_x register returns the current state of the corresponding pins when configured as general purpose I/O, regardless of whether the pins are inputs or outputs.
Every GPIO port has a PPDSDR_x register and a clear register (PCLRR_x) for setting or clearing individual bits in the PODR_x register.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 12-31
General Purpose I/O Module
Initial pin output drive strength is determined during reset configuration. The DSCR_x registers allow the pin drive strengths to be configured on a per-function basis after reset.
The MCF5271 ports module does not generate interrupt requests.
12.4.2 Port Digital I/O Timing
Input data on all pins configured as general purpose input is synchronized to the rising edge of the
internal bus clock, CLKOUT, as shown in Figure 12-44 .
CLKOUT
Input
Pin
Register
Pin Data
Figure 12-44. General Purpose Input Timing
Data written to the PODR_x register of any pin configured as a general purpose output is immediately driven to its respective pin, as shown in
CLKOUT
Output Data
Register
Output Pin
Figure 12-45. General Purpose Output Timing
12.5 Initialization/Application Information
The initialization for the MCF5271 ports module is done during reset configuration. All registers are reset to a predetermined state. Refer to
Section 12.3, “Memory Map/Register Definition ,” for
more details on reset and initialization.
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Chapter 13
Interrupt Controller Modules
13.1 Introduction
This section details the functionality for the MCF5271 interrupt controller (INTC). The general features of the MCF5271 interrupt controller block include:
• 41 interrupt sources, organized as:
— 34 fully-programmable interrupt sources
— 7 fixed-level interrupt sources
• Each of the 41 sources has a unique interrupt control register (ICRx) to define the software-assigned levels and priorities within the level
• Unique vector number for each interrupt source
• Ability to mask any individual interrupt source, plus global mask-all capability
• Supports both hardware and software interrupt acknowledge cycles
• “Wake-up” signal from low-power stop modes
The 34 fully-programmable and seven fixed-level interrupt sources for the interrupt controller on the MCF5271 handle the complete set of interrupt sources from all of the modules on the device.
This section describes how the interrupt sources are mapped to the interrupt controller logic and how interrupts are serviced.
13.1.1 68K/ColdFire Interrupt Architecture Overview
Before continuing with the specifics of the MCF5271 interrupt controller, a brief review of the interrupt architecture of the 68K/ColdFire family is appropriate.
The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a
3-bit encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The processor samples for active interrupt requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machine’s status register (SR). If the priority level is greater than the SR[I] field at the sample point, the processor suspends normal instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the
SR[I] field. For correct operation, the ColdFire requires that, once asserted, the interrupt source remain asserted until explicitly disabled by the interrupt service routine.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 13-1
Interrupt Controller Modules
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode and then fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt acknowledge (IACK) cycle with the ColdFire implementation using a special encoding of the transfer type and transfer modifier attributes to distinguish this data fetch from a “normal” memory access. The fetched data provides an index into the exception vector table which contains 256 addresses, each pointing to the beginning of a specific exception service routine. In particular, vectors 64 - 255 of the exception vector table are reserved for user interrupt service routines. The first 64 exception vectors are reserved for the processor to handle reset, error conditions (access, address), arithmetic faults, system calls, etc. Once the interrupt vector number has been retrieved, the processor continues by creating a stack frame in memory. For ColdFire, all exception stack frames are 2 longwords in length, and contain 32 bits of vector and status register data, along with the 32-bit program counter value of the instruction that was interrupted (see
Section 3.6, “Exception Stack Frame Definition ” for more information on the stack frame format).
After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number as the offset, and then jumps to that address to begin execution of the service routine. After the status register is stored in the exception stack frame, the SR[I] mask field is set to the level of the interrupt being acknowledged, effectively masking that level and all lower values while in the service routine. For many peripheral devices, the processing of the IACK cycle directly negates the interrupt request, while other devices require that request to be explicitly negated during the processing of the service routine.
For the MCF5271, the processing of the interrupt acknowledge cycle is fundamentally different than previous 68K/ColdFire cores. In the new approach, all IACK cycles are directly handled by the interrupt controller, so the requesting peripheral device is not accessed during the IACK. As a result, the interrupt request must be explicitly cleared in the peripheral during the interrupt service
routine. For more information, see Section 13.1.2.3, “Interrupt Vector Determination
.”
Unlike the M68000 family, all ColdFire processors guarantee that the first instruction of the service routine is executed before sampling for interrupts is resumed. By making this initial instruction a load of the SR, interrupts can be safely disabled, if required.
During the execution of the service routine, the appropriate actions must be performed on the peripheral to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual at http://www.freescale.com/coldfire.
13.1.2 Interrupt Controller Theory of Operation
To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63 interrupt sources are organized as 7 levels, with each level supporting up to 9 prioritized requests.
Consider the priority structure within a single interrupt level (from highest to lowest priority) as shown in
.
MCF5271 Reference Manual, Rev. 2
13-2 Freescale Semiconductor
Introduction
Table 13-1. Interrupt Priority Within a Level
ICR[2:0]
—
011
010
001
000
111
110
101
100
Priority
7 (Highest)
6
5
4
Fixed Midpoint Priority
3
2
1
0 (Lowest)
Interrupt
Sources
8–63
8–63
8–63
8–63
1–7
8–63
8–63
8–63
8–63
The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt source 1–7 (IRQ[1:7] from the Edgeport module) are fixed at the corresponding level’s midpoint priority. Thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single interrupt level. The “fixed” interrupt source is hardwired to the given level, and represents the mid-point of the priority within the level. For the fully-programmable interrupt sources, the 3-bit level and the 3-bit priority within the level are defined in the 8-bit interrupt control register (ICRx).
The operation of the interrupt controller can be broadly partitioned into three activities:
• Recognition
• Prioritization
• Vector determination during IACK
13.1.2.1 Interrupt Recognition
The interrupt controller continuously examines the request sources and the interrupt mask register to determine if there are active requests. This is the recognition phase.
13.1.2.2 Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller. The decoded priority levels from all the interrupt controllers are logically summed together and the highest enabled interrupt request is then encoded into a 3-bit priority level that is sent to the processor core during this prioritization phase.
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Interrupt Controller Modules
13.1.2.3 Interrupt Vector Determination
Once the core has sampled for pending interrupts and begun interrupt exception processing, it generates an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a memory-mapped byte read by the processor, and routed to the appropriate interrupt controller.
Next, the interrupt controller extracts the level being acknowledged from address bits[4:2], and then determines the highest priority interrupt request active for that level, and returns the 8-bit interrupt vector for that request to complete the cycle. The 8-bit interrupt vector is formed using the following algorithm:
For INTC0, vector_number = 64 + interrupt source number
Recall vector_numbers 0 - 63 are reserved for the ColdFire processor and its internal exceptions.
Thus, the following mapping of bit positions to vector numbers applies for the INTC0: if interrupt source 1 is active and acknowledged,then vector_number = 65 if interrupt source 2 is active and acknowledged,then vector_number = 66
...
if interrupt source 8 is active and acknowledged,then vector_number = 72 if interrupt source 9 is active and acknowledged,then vector_number = 73
...
if interrupt source 62 is active and acknowledged,then vector_number = 126
The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector number.
If there is no active interrupt source for the given level, a special “spurious interrupt” vector
(vector_number = 24) is returned and it is the responsibility of the service routine to handle this error situation.
Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle since the interrupt controller completely services the acknowledge. This means the interrupt source must be explicitly disabled in the interrupt service routine. This design provides unique vector capability for all interrupt requests, regardless of the “complexity” of the peripheral device.
13.2 Memory Map/Register Definition
The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In the following discussion, there are a number of program-visible registers greater than 32 bits in size. For these control fields, the physical register is partitioned into two 32-bit values: a register “high” (the upper longword) and a register “low” (the lower longword). The nomenclature
<reg_name>H and <reg_name>L is used to reference these values.
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Memory Map/Register Definition
The registers and their locations are defined in
. The offsets listed start from the base address for each interrupt controller. The base addresses for the interrupt controllers are listed below:
Table 13-2. Interrupt Controller Base Addresses
Interrupt Controller Number Base Address
INTC0
Global IACK Registers Space
1
IPSBAR + 0xC00
IPSBAR + 0xF00
1
This address space only contains the SWIACK and L1ACK-L7IACK registers. See
“Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) " for more information
IPSBAR Offset
0xC00
0xC04
0xC08
0xC0C
0xC10
0xC14
0xC18
0xC1C - 0xC3C &
Table 13-3. Interrupt Controller Memory Map
Bits[31:24]
IRLR[7:1]
Bits[23:16] Bits[15:8]
Interrupt Pending Register High (IPRH), [63:32]
Interrupt Pending Register Low (IPRL), [31:1]
Interrupt Mask Register High (IMRH), [63:32]
Interrupt Mask Register Low (IMRL), [31:0]
Interrupt Force Register High (INTFRCH), [63:32]
Interrupt Force Register Low (INTFRCL), [31:1]
IACKLPR[7:0]
Reserved
Reserved
Bits[7:0]
0xC60
0xC64
0xC68
0xC6C
0xC70
0xC74
0xC78
0xC40
0xC44
0xC48
0xC4C
0xC50
0xC54
0xC58
0xC5C
ICR32
ICR36
ICR40
ICR44
ICR48
ICR52
ICR56
Reserved
ICR04
ICR08
ICR12
ICR16
ICR20
ICR24
ICR28
ICR33
ICR37
ICR41
ICR45
ICR49
ICR53
ICR57
ICR01
ICR05
ICR09
ICR13
ICR17
ICR21
ICR25
ICR29
ICR34
ICR38
ICR42
ICR46
ICR50
ICR54
ICR58
ICR02
ICR06
ICR10
ICR14
ICR18
ICR22
ICR26
ICR30
ICR35
ICR39
ICR43
ICR47
ICR51
ICR55
ICR59
ICR03
ICR07
ICR11
ICR15
ICR19
ICR23
ICR27
ICR31
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Interrupt Controller Modules
Table 13-3. Interrupt Controller Memory Map (Continued)
IPSBAR Offset
0xC7C
0xC80 - 0xCDC &
Bits[31:24]
ICR60
Bits[23:16]
ICR61
Reserved
Bits[15:8]
ICR62
Bits[7:0]
ICR63
0xCE0
0xCE4
0xCE8
0xCEC
0xCF0
0xCF4
0xCF8
0xCFC
SWIACK
L1IACK
L2IACK
L3IACK
L4IACK
L5IACK
L6IACK
L7IACK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
13.2.1 Register Descriptions
13.2.1.1 Interrupt Pending Registers (IPRH, IPRL)
The IPRH and IPRL registers, Figure 13-1
and Figure 13-2 , are each 32 bits in size, and provide
a bit map for each interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given source. The state of the interrupt mask register does not affect the IPR.
The IPR is cleared by reset. The IPR is a read-only register, so any attempted write to this register is ignored. Bit 0 is not implemented and reads as a zero.
30 29 28 27 26 25 24
INT
23 22 21 20 19 18 17 16 31
R
W
Reset 0
15
R
W
Reset 0
Address
0
14
0
13
0
12
0
11
0
10
0
9
0 0
8
INT
7
0
6
0
5
0
4
0
3
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_0C00
Figure 13-1. Interrupt Pending Register High (IPRHn)
0
0
2
0
1
0
0
0
0
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Bits
31–0
Name
INT
Memory Map/Register Definition
Table 13-4. IPRHn Field Descriptions
Description
Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRH samples the signal generated by the interrupting source. The corresponding IPRH bit reflects the state of the interrupt signal even if the corresponding
IMRHn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
31
R
W
Reset 0
15
R
W
Reset 0
Address
Bits
31–1
0
30
0
14
29
0
13
28
0
12
27
0
11
26
0
10
25
0
9
24
INT
23
0
8
INT
0
7
22
0
6
21
0
5
20
0
4
19
0
3
18
0
2
17
0
1
16
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_0C04
Figure 13-2. Interrupt Pending Register Low (IPRL)
Name
INT
—
0 0 0
Table 13-5. IPRLn Field Descriptions
Description
Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRL samples the signal generated by the interrupting source. The corresponding IPRL bit reflects the state of the interrupt signal even if the corresponding
IMRL bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
Reserved, should be cleared.
0
0
0
13.2.1.2 Interrupt Mask Register (IMRH, IMRL)
The IMRH and IMRL registers are each 32 bits in size and provide a bit map for each interrupt to allow the request to be disabled (1 = disable the request, 0 = enable the request). The IMR is set to all ones by reset, disabling all interrupt requests. The IMR can be read and written. A write that sets bit 0 of the IMR forces the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability.
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Interrupt Controller Modules
NOTE
If an interrupt source is being masked in the interrupt controller mask register (IMR) or a module’s interrupt mask register while the interrupt mask in the status register (SR[I]) is set to a value lower than the interrupt’s level, a spurious interrupt may occur. This is because by the time the status register acknowledges this interrupt, the interrupt has been masked. A spurious interrupt is generated because the CPU cannot determine the interrupt source. To avoid this situation for interrupts sources with levels 1-6, first write a higher level interrupt mask to the status register, before setting the mask in the IMR or the module’s interrupt mask register. After the mask is set, return the interrupt mask in the status register to its previous value. Since level 7 interrupts cannot be disabled in the status register prior to masking, use of the IMR or module interrupt mask registers to disable level 7 interrupts is not recommended.
31
R
W
Reset 1
15
R
W
Reset 1
Address
Bits
31–0
30
1
14
29
1
13
28
1
12
27
1
11
26
1
10
25
1
9
24 23
INT_MASK
1 1
8 7
INT_MASK
22
1
6
21
1
5
20
1
4
19
1
3
18
1
2
17
1
1
16
1
0
1 1 1 1 1 1 1 1 1 1 1
IPSBAR + 0x00_0C08
Figure 13-3. Interrupt Mask Register High (IMRH)
1
Table 13-6. IMRH Field Descriptions
1 1 1
Name Description
INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRH bit determines whether an interrupt condition can generate an interrupt. The corresponding
IPRH bit reflects the state of the interrupt signal even if the corresponding IMRH bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
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Memory Map/Register Definition
31
R
W
Reset 1
15
R
W
Reset 1
Address
Bits
31–1
0
30
1
14
29
1
13
28
1
12
27
1
11
26
1
10
25 24 23
INT_MASK
1 1 1
9 8
INT_MASK
7
22
1
6
21
1
5
20
1
4
19
1
3
18
1
2
17
1
1
16
1
0
MASK
ALL
1 1 1 1 1 1 1 1 1 1 1
IPSBAR + 0x00_0C0C
Figure 13-4. Interrupt Mask Register Low (IMRL)
1
Table 13-7. IMRL Field Descriptions
1 1 1
Name Description
INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRL bit determines whether an interrupt condition can generate an interrupt. The corresponding
IPRL bit reflects the state of the interrupt signal even if the corresponding IMRL bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
MASKALL Mask all interrupts. Setting this bit will force the other 63 bits of the IMRH and IMRL to ones, disabling all interrupt sources, and providing a global mask-all capability.
13.2.1.3 Interrupt Force Registers (INTFRCH, INTFRCL)
The INTFRCH and INTFRCL registers are each 32 bits in size and provide a mechanism to allow software generation of interrupts for each possible source for functional or debug purposes. The system design may reserve one or more sources to allow software to self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate INTFRC register. The assertion of an interrupt request via the INTFRC register is not affected by the interrupt mask register. The INTFRC register is cleared by reset.
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Interrupt Controller Modules
31
R
W
Reset 0
15
R
W
Reset 0
Address
Bits
31–0
30
0
14
29
0
13
28
0
12
27
0
11
26
0
10
25
0
9
24 23
INTFRCH
0 0
8 7
INTFRCH
22
0
6
21
0
5
20
0
4
19
0
3
18
0
2
17
0
1
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_C10
Figure 13-5. Interrupt Force Register High (INTFRCH)
Table 13-8. INTFRCH Field Descriptions
0 0
Name Description
INTFRCH Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
16
0
0
0
31
R
W
Reset 0
15
R
W
Reset 0
Address
Bits
31–1
0
30
0
14
29
0
13
28
0
12
27
0
11
26
0
10
25 24 23
INTFRCL
0 0 0
9 8
INTFRCL
7
22
0
6
21
0
5
20
0
4
19
0
3
18
0
2
17
0
1
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_0C14
Figure 13-6. Interrupt Force Register High (INTFRCH)
Table 13-9. INTFRCLn Field Descriptions
0 0
Name Description
INTFRCL Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
— Reserved, should be cleared.
16
0
0
0
0
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Memory Map/Register Definition
13.2.1.4 Interrupt Request Level Register (IRLR)
This 7-bit register is updated each machine cycle and represents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. This register output is encoded into the 3-bit priority interrupt level driven to the processor core.
Bits
7–1
0
R
W
Reset
7 6 5 4
IRQ
3 2 1 0
0
0 0 0 0 0 0 0 0
Address IPSBAR + 0x00_0C18
Figure 13-7. Interrupt Request Level Register (IRLR)
Table 13-10. IRQLR Field Descriptions
Name
IRQ
—
Description
Interrupt requests. Represents the prioritized active interrupts for each level.
0 There are no active interrupts at this level
1 There is an active interrupt at this level
Reserved
13.2.1.5 Interrupt Acknowledge Level and Priority Register (IACKLPR)
Each time an IACK is performed, the interrupt controller responds with the vector number of the highest priority source within the level being acknowledged. In addition to providing the vector number directly for the byte-sized IACK read, this 8-bit register is also loaded with information about the interrupt level and priority being acknowledged. This register provides the association between the acknowledged “physical” interrupt request number and the programmed interrupt
level/priority. The contents of this read-only register are described in Figure 13-8 and Table 13-11
.
Bits
7
R
W
Reset
7
0
6 5
LEVEL
4 3 2
PRI
1 0
0 0 0 0 0 0 0 0
Address IPSBAR + 0x00_0C19
Figure 13-8. IACK Level and Priority Register (IACKLPR)
Name
—
Table 13-11. IACKLPR Field Descriptions
Description
Reserved
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Interrupt Controller Modules
Bits
6–4
3–0
Table 13-11. IACKLPR Field Descriptions (Continued)
Name Description
LEVEL Interrupt level. Represents the interrupt level currently being acknowledged.
PRI Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently being acknowledged.
0 Priority 0
1 Priority 1
2 Priority 2
3 Priority 3
4 Priority 4
5 Priority 5
6 Priority 6
7 Priority 7
8 Mid-Point Priority associated with the fixed level interrupts only
13.2.1.6 Interrupt Control Register (ICRx, (x = 1, 2,..., 63))
Each ICRx specifies the interrupt level (1–7) and the priority within the level (0–7). All ICRx registers can be read, but only ICR8 to ICR63 can be written. It is the responsibility of the software to program the ICRx registers with unique and non-overlapping level and priority definitions.
Failure to program the ICRx registers in this manner can result in undefined behavior. If a specific interrupt request is completely unused, the ICRx value can remain in its reset (and disabled) state.
Bits
7–6
5–3
2–0
R:
W
Reset
Address
7
0
0
6
0
5 4
IL
3 2 1
IP
0 0 0
See Note
0 0 0
for register offsets
0
0
Note: Read only for ICR1-ICR7, else Read/Write
Note: It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping level and priority definitions.
Failure to program the ICRnx registers in this manner can result in undefined behavior. If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state.
Figure 13-9. Interrupt Control Register (ICRx)
Table 13-12. ICRx Field Descriptions
Name
—
IL
IP
Description
Reserved, should be cleared.
Interrupt level. Indicates the interrupt level assigned to each interrupt input.
Interrupt priority. Indicates the interrupt priority for internal modules within the interrupt-level assignment. 000 represents the lowest priority and 111 represents the highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the level, and the IP field will always read as 000.
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Memory Map/Register Definition
13.2.1.6.1 Interrupt Sources
The following tables list the interrupt sources for each interrupt request line for INTC0 and
INTC1.
Table 13-13. Interrupt Source Assignment For INTC
Sourc e
Modul e
18
19
20
21
22
7
8
5
6
3
4
1
2
EPORT
9
10
11
12
SCM
DMA
13 UART0
14 UART1
15 UART2
16
17 I
2
C
QSPI
TMR0
TMR1
TMR2
TMR3
Flag Source Description Flag Clearing Mechanism
EPF1 Edge port flag 1
EPF2 Edge port flag 2
EPF3 Edge port flag 3
EPF4 Edge port flag 4
EPF5 Edge port flag 5
EPF6 Edge port flag 6
EPF7 Edge port flag 7
SWTI Software watchdog timeout
Write EPF1 = 1
Write EPF2 = 1
Write EPF3 = 1
Write EPF4 = 1
Write EPF5 = 1
Write EPF6 = 1
Write EPF7 = 1
Cleared when service complete.
DONE DMA Channel 0 transfer complete Write DONE = 1
DONE DMA Channel 1 transfer complete Write DONE = 1
DONE DMA Channel 2 transfer complete Write DONE = 1
DONE DMA Channel 3 transfer complete Write DONE = 1
INT
INT
INT
UART0 interrupt
UART1 interrupt
UART2 interrupt
Automatically cleared
Automatically cleared
Automatically cleared
Not used
IIF
INT
INT
INT
I
2
C interrupt
QSPI interrupt
TMR0 interrupt
Write IIF = 0
Write 1 to appropriate QIR bit
Write 1 to appropriate TER0 bit
Write 1 to appropriate TER1 bit
INT
INT
TMR1 interrupt
TMR2 interrupt
TMR3 interrupt
Write 1 to appropriate TER2 bit
Write 1 to appropriate TER3 bit
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Interrupt Controller Modules
Table 13-13. Interrupt Source Assignment For INTC (Continued)
Sourc e
Modul e
FEC
35
36
37
38
31
32
33
34
39
40
41
42
43–63
27
28
29
30
23
24
25
26
PIT0
PIT1
PIT2
PIT3
RNG
SKHA
MDHA
Flag Source Description
X_INTF Transmit frame interrupt
X_INTB Transmit buffer interrupt
UN
RL
Transmit FIFO underrun
Collision retry limit
R_INTF Receive frame interrupt
R_INTB Receive buffer interrupt
MII
LC
MII interrupt
Late collision
HBERR Heartbeat error
GRA Graceful stop complete
EBERR Ethernet bus error
BABT Babbling transmit error
BABR Babbling receive error
PIF PIT interrupt flag
PIF
PIF
PIT interrupt flag
PIT interrupt flag
PIF
EI
INT
MI
PIT interrupt flag
RNG interrupt flag
SKHA interrupt flag
MDHA interrupt flag
Flag Clearing Mechanism
Write X_INTF = 1
Write X_INTB = 1
Write UN = 1
Write RL = 1
Write R_INTF = 1
Write R_INTB = 1
Write MII = 1
Write LC = 1
Write HBERR = 1
Write GRA = 1
Write EBERR = 1
Write BABT = 1
Write BABR = 1
Write PIF = 1 or write PMR
Write PIF = 1 or write PMR
Write PIF = 1 or write PMR
Write PIF = 1 or write PMR
Write RNGCR[CI] = 1
Write SKCMR[CI] = 1
Write MDCMR[CI] = 1
Not used
13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a processor-generated interrupt acknowledge cycle during exception processing. In either case, the interrupt controller’s actions are very similar.
First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of IACK arrives in the interrupt controller, the controller examines all the currently-active level n interrupt requests, determines the highest priority within the level, and then responds with the unique vector number corresponding to that specific interrupt source. The vector number is supplied as the data for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt
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Low-Power Wakeup Operation controller also loads the level and priority number for the level into the IACKLPR register, where it may be retrieved later.
This interrupt controller design also supports the concept of a software IACK. A software IACK is a useful concept that allows an interrupt service routine to determine if there are other pending interrupts so that the overhead associated with interrupt exception processing (including machine state save/restore functions) can be minimized. In general, the software IACK is performed near the end of an interrupt service routine, and if there are additional active interrupt sources, the current interrupt service routine (ISR) passes control to the appropriate service routine, but without taking another interrupt exception.
When the interrupt controller receives a software IACK read, it returns the vector number associated with the highest level, highest priority unmasked interrupt source for that interrupt controller. The IACKLPR register is also loaded as the software IACK is performed. If there are no active sources, the interrupt controller returns an all-zero vector as the operand. For this situation, the IACKLPR register is also cleared.
In addition to the software IACK registers within each interrupt controller, there are global software IACK registers. A read from the global SWIACK will return the vector number for the highest level and priority unmasked interrupt source from all interrupt controllers. A read from one of the LnIACK registers will return the vector for the highest priority unmasked interrupt within a level for all interrupt controllers.
R
W
Reset
7 6 5 4
VECTOR
3 2 1 0
0 0 0 0 0 0 0 0
Address
for register offsets
Figure 13-10. Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
Table 13-14. SWIACK and L1IACK-L7IACK Field Descriptions
Bits
7–0
Name Description
VECTOR Vector number. A read from the SWIACK register returns the vector number associated with the highest level, highest priority unmasked interrupt source. A read from one of the
LnACK registers returns the highest priority unmasked interrupt source within the level.
13.3 Low-Power Wakeup Operation
The System Control Module (SCM) contains an 8-bit low-power interrupt control register
(LPICR) used explicitly for controlling the low-power stop mode. This register must explicitly be programmed by software to enter low-power mode.
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Interrupt Controller Modules
Each interrupt controller provides a special combinatorial logic path to provide a special wake-up signal to exit from the low-power stop mode. This special mode of operation works as follows:
• First, LPICR[XLPM_IPL] is loaded with the mask level that will be specified while the core is in stop mode. LPICR[ENBSTOP] must be set to enable this mode of operation.
NOTE
The wakeup mask level taken from LPICR[XLPM_IPL] is adjusted by hardware to allow a level 7 IRQ to generate a wakeup. That is, the wakeup mask value used by the interrupt controller must be in the range of 0–6.
• Second, the processor executes a STOP instruction which places it in stop mode. Once the processor is stopped, each interrupt controller enables a special logic path which evaluates the incoming interrupt sources in a purely combinatorial path; that is, there are no clocked storage elements. If an active interrupt request is asserted and the resulting interrupt level is greater than the mask value contained in LPICR[XLPM_IPL], then each interrupt controller asserts the wake-up output signal, which is routed to the SCM where it is combined with the wakeup signals from the other interrupt controller and then to the PLL module to re-enable the device’s clock trees and resume processing.
For more information, see Section 8.2.1.1, “Low-Power Interrupt Control Register (LPICR) .”
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Chapter 14
DMA Controller Module
14.1 Introduction
This chapter describes the Direct Memory Access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail.
NOTE
The designation “n” is used throughout this section to refer to registers or signals associated with one of the four identical DMA channels:
DMA0, DMA1, DMA2 or DMA3.
14.1.1 Overview
The DMA controller module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module, shown in
, provides four channels that allow byte, word, longword, or 16-byte burst data transfers. Each channel has a dedicated source address register (SARn), destination address register (DARn), byte count register (BCRn), control register
(DCRn), and status register (DSRn). Transfers are dual address to on-chip devices, such as UART and SDRAM controller.
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MCF5271 Reference Manual, Rev. 2
14-1
DMA Controller Module
DREQ0 DREQ1 DREQ2
Internal
Bus
Channel
Requests
Channel 0 Channel 1 Channel 2 Channel 3
SAR0
DAR0
BCR0
DCR0
DSR0
SAR1
DAR1
BCR1
DCR1
DSR1
SAR2
DAR2
BCR2
DCR2
DSR2
SAR3
DAR3
BCR3
DCR3
DSR3
Channel
Attributes
Channel
Enables
MUX
Control
MUX
Interrupts
System Bus Address
System Bus Size
Current Master Attributes
Read Data Bus
Data Path
Data Path
Control
Write Data Bus
Arbitration/
Control
Bus Interface
Registered
Bus Signals
14-2
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Freescale Semiconductor
Introduction
DREQ0 DREQ1 DREQ2 DREQ3
Internal
Bus
Channel
Requests
Channel 0 Channel 1 Channel 2 Channel 3
SAR0
DAR0
BCR0
DCR0
DSR0
SAR1
DAR1
BCR1
DCR1
DSR1
SAR2
DAR2
BCR2
DCR2
DSR2
SAR3
DAR3
BCR3
DCR3
DSR3
Interrupts
Channel
Enables
MUX
Control
Channel
Attributes
MUX
System Bus Address
System Bus Size
Current Master Attributes
Read Data Bus
Data Path
Data Path
Control
Write Data Bus
Arbitration/
Control
Bus Interface
Registered
Bus Signals
Figure 14-1. DMA Signal Diagram
NOTE
Throughout this chapter “external request” and DREQ are used to refer to a DMA request from one of the on-chip UARTS, DMA timers, or DREQ signals. For details on the connections associated with DMA
request inputs, see Section 14.3.1, “DMA Request Control
.”
14.1.2 Features
The DMA controller module features are as follows:
• Four independently programmable DMA controller channels
• Auto-alignment feature for source or destination accesses
• Dual-address transfers
• Channel arbitration on transfer boundaries
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Freescale Semiconductor 14-3
DMA Controller Module
• Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
• Continuous-mode or cycle-steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
• Modulo addressing on source and destination addresses
• Automatic channel linking
14.2 DMA Transfer Overview
The DMA module can move data within system memory (including memory and peripheral devices) with minimal processor intervention, greatly improving overall system performance. The
DMA module consists of four independent, functionally equivalent channels, so references to
DMA in this chapter apply to any of the channels. It is not possible to implicitly address all four channels at once.
The processor generates DMA requests internally by setting DCR[START]; the UART modules and DMA timers can generate a DMA request by asserting internal DREQ signals. The processor can program bus bandwidth for each channel. The channels support cycle-steal and continuous
transfer modes; see Section 14.4.1, “Transfer Requests (Cycle-Steal and Continuous Modes)
.”
The DMA controller supports dual-address transfers. The DMA channels support up to 32 data bits.
• Dual-address transfers—A dual-address transfer consists of a read followed by a write and is initiated by an internal request using the START bit or by asserting DREQn. Two types of transfer can occur: a read from a source device or a write to a destination device. See
for more information.
Control and Data
Memory/
Peripheral
Memory/
Peripheral
Control and Data
Figure 14-2. Dual-Address Transfer
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14-4 Freescale Semiconductor
Memory Map/Register Definition
Any operation involving the DMA module follows the same three steps:
1. Channel initialization—Channel registers are loaded with control information, address pointers, and a byte-transfer count.
2. Data transfer—The DMA accepts requests for operand transfers and provides addressing
and bus control for the transfers.
3. Channel termination—Occurs after the operation is finished, either successfully or due to
an error. The channel indicates the operation status in the channel’s DSR, described in
Section 14.3.4.1, “DMA Status Registers (DSR0–DSR3) .”
14.3 Memory Map/Register Definition
This section describes each internal register and its bit assignment. Note that modifying DMA
control registers during a DMA transfer can result in undefined operation.
shows the mapping of DMA controller registers.
Table 14-1. Memory Map for DMA Controller Module Registers
DMA
Channel
IPSBAR Offset [31:24] [23:16] [15:8]
—
0
1
0x00_0014
0x00_0100
0x00_0104
0x00_0108
0x00_010C
0x00_0110
0x00_0114
0x00_0118
Status Register 0
(DSR0)
DMA Request Control Register (DMAREQC)
1
Source Address Register 0 (SAR0)
Destination Address Register 0 (DAR0)
Byte Count Register 0 (BCR0)
Control Register 0 (DCR0)
Source Address Register 1 (SAR1)
Destination Address Register 1 (DAR1)
Status Register 1
(DSR1)
Control Register 1 (DCR1)
Source Address Register 2 (SAR2)
Destination Address Register 2 (DAR2)
2
0x00_011C
0x00_0120
0x00_0124
0x00_0128
Status Register 2
(DSR2)
3
0x00_012C
0x00_0130
0x00_0134
0x00_0138
Status Register 3
(DSR3)
0x00_013C
1
Located within the SCM, but listed here for clarity.
Byte Count Register 2 (BCR2)
Control Register 2 (DCR2)
Source Address Register 3 (SAR3)
Destination Address Register 3 (DAR3)
Byte Count Register 3 (BCR3)
Control Register 3 (DCR3)
[7:0]
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Freescale Semiconductor 14-5
DMA Controller Module
14.3.1 DMA Request Control (DMAREQC)
The DMAREQC register provides a software-controlled connection matrix for DMA requests. It logically routes DMA requests from the DMA timers and UARTs to the four channels of the DMA controller. Writing to this register determines the exact routing of the DMA request to the four channels of the DMA modules. If DCRn[EEXT] is set and the channel is idle, the assertion of the appropriate DREQn activates channel n.
31
R 0
W
Reset 0
15
R
W
Reset 0
Address
Bits
31–20
19-16
30
0
29
0
0 0
14 13
DMAC3
28
0
0
12
27
0
0
11
26
0
0 0
10 9
DMAC2
25
0
0
8
24
0
0
7
23
0
22
0
0 0
6 5
DMAC1
21
0
0
4
20
0
0
3
19 18 17
DMAREQC_EXT
16
0 0
2 1
DMAC0
0
0
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_0014
Figure 14-3. DMA Request Control Register (DMAREQC)
0
Table 14-2. DMAREQC Field Description
0 0
Name Description
— Reserved, should be cleared.
DMAREQC
_EXT
DMA request control for external (off-chip) requests. The DMAREQC_EXT[3:0] bits correspond to DMA channels 3, 2, 1, and 0. If set, the corresponding DMACn bit field is ignored. If cleared, refer to the appropriate DMACn bit field for configuring the internal
DMA requestor.
DMAREQC_EXT[3] is reserved and should be cleared to enable internal DMA channel 3 requests, while DMAREQC_EXT[2:0] controls the external DMA request/acknowledge signals. In order for an external request to activate a DMA channel the corresponding
DCRn[EEXT] bit must be set as well.
DMAREQC_
EXT[3]
DMAREQC_
EXT[2]
DMAREQC_
EXT[1]
0
1
See DMAC3
Reserved
See DMAC2
External
DREQ2
See DMAC1
External DREQ1
Note: GPIO must be configured to enable external DMA requests.
DMAREQC_
EXT[0]
See DMAC0
External
DREQ0
14-6
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Freescale Semiconductor
Bits
15–0
Memory Map/Register Definition
Table 14-2. DMAREQC Field Description (Continued)
Name Description
DMACn DMA channel n. Each four bit field defines the logical connection between the DMA requestors and that DMA channel.There are ten possible requesters (4 DMA Timers and
6 UARTs). Any request can be routed to any of the DMA channels. Effectively, the
DMAREQC provides a software-controlled routing matrix of the 10 DMA request signals to the 4 channels of the DMA module. DMAC3 controls DMA channel 3, DMAC2 controls
DMA channel 2, etc.
0100 DMA Timer 0.
0101 DMA Timer 1.
0110 DMA Timer 2.
0111 DMA Timer 3.
1000 UART0 Receive.
1001 UART1 Receive.
1010 UART2 Receive.
1100 UART0 Transmit.
1101 UART1 Transmit.
1110 UART2 Transmit.
All other values are reserved and will not generate a DMA request.
14.3.2 Source Address Registers (SAR0–SAR3)
SARn, shown in
, contains the address from which the DMA controller requests data.
16 31
R
W
Reset 0
30
0
29
0
28
0
27
0
26
0
25
0
24
SAR
23
0 0
22
0
21
0
20
0
19
0
18
0
15
R
W
Reset 0
Address
14 13 12 11 10 9 8
SAR
7 6 5 4 3 2
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_0100 (DMA0); IPSBAR + 0x00_0110 (DMA1);
IPSBAR + 0x00_0120 (DMA2); IPSBAR + 0x00_0130 (DMA3)
Figure 14-4. Source Address Registers (SARn)
0
NOTE
The backdoor enable bit must be set in the SCM RAMBAR as well as the secondary port valid bit in the Core RAMBAR in order to enable
backdoor accesses from the DMA to SRAM. See Section 11.2.1.2,
“Memory Base Address Register (RAMBAR)
” and
“SRAM Base Address Register (RAMBAR)
” for more details.
17
0
0
1
0
0
0
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Freescale Semiconductor 14-7
DMA Controller Module
14.3.3 Destination Address Registers (DAR0–DAR3)
DARn, shown in Figure 14-5 , holds the address to which the DMA controller sends data.
31
R
W
Reset 0
30
0
29
0
28
0
27
0
26
0
25
0
24
DAR
23
0 0
22
0
21
0
20
0
19
0
18
0
15
R
W
Reset 0
Address
14 13 12 11 10 9 8
DAR
7 6 5 4 3 2
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_0104 (DMA0); IPSBAR + 0x00_0114 (DMA1);
IPSBAR + 0x00_0124 (DMA2); IPSBAR + 0x00_0134 (DMA3)
Figure 14-5. Destination Address Registers (DARn)
0
NOTE
The DMA does not maintain coherency with the cache. Therefore,
DMAs should not transfer data to cacheable memory unless software is used to maintain the cache coherency.
17
0
0
1
16
0
0
0
14.3.4 Byte Count Registers (BCR0–BCR3) and DMA Status
Registers (DSR0–DSR3)
BCRn, shown in
, contains the number of bytes yet to be transferred for a given block.
BCRn decrements on the successful completion of the address transfer of a write transfer. BCRn decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively.
31
R
W
Reset 0
30
0
29
0
28
DSR
27
0 0
26
0
25
0
24
0
23
0
22
0
21
0
20
BCR
19
0 0
18
0
17
0
15
R
W
Reset 0
14 13 12 11 10 9 8
BCR
7 6 5 4 3 2 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address IPSBAR + 0x00_0108 (DMA0); IPSBAR + 0x00_0118 (DMA1);
IPSBAR + 0x00_0128 (DMA2); IPSBAR + 0x00_0138 (DMA3)
Figure 14-6. Byte Count Registers (BCRn) and Status Registers (DSRn)
16
0
0
0
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14-8 Freescale Semiconductor
Memory Map/Register Definition
DSRn[DONE], shown in Figure 14-7 , is set when the block transfer is complete.
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when the
DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no transfer occurs. See
Section 14.3.4.1, “DMA Status Registers (DSR0–DSR3) .”
14.3.4.1 DMA Status Registers (DSR0–DSR3)
In response to an event, the DMA controller writes to the appropriate DSRn bit,
. Only a write to DSRn[DONE] results in action.
Bits
7
6
5
4
3
2
R
W
Reset
7
0
6
CE
5
BES
4
BED
3
0
2
REQ
1 0
BSY DONE
0 0 0 0 0 0 0
Address See
Figure 14-7. DMA Status Registers (DSRn)
0
Table 14-3. DSRn Field Descriptions
Name
—
CE
BES
BED
—
REQ
Description
Reserved, should be cleared.
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
Reserved, should be cleared.
Request
0 No request is pending or the channel is currently active. Cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
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MCF5271 Reference Manual, Rev. 2
14-9
DMA Controller Module
Bits
1
0
Name
BSY
DONE
Table 14-3. DSRn Field Descriptions (Continued)
Description
Busy
0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 BSY is set the first time the channel is enabled after a transfer is initiated.
Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by resetting the status bits. When a transfer completes, software must clear DONE before reprogramming the DMA.
0 Writing or reading a 0 has no effect.
1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used in an interrupt handler to clear the DMA interrupt and error bits.
14.3.5 DMA Control Registers (DCR0–DCR3)
DCRn, shown in Figure 14-8 , is used for configuring the DMA controller module.
31 30 29 28
R INT EEXT CS AA
W
Reset 0 0 0 0
15
R
W
Reset 0
Address
14
SMOD
13
0 0
12
27 26
BWC
0
11
25
0 0
10
DMOD
9
0
8
24
0
23
0
22
SINC
0 0
7 6
D_REQ 0
21 20
SSIZE
0
5
0
4
LINKCC
19
DINC
0
3
LCH1
2
18 17
DSIZE
0 0
16
0
START
0
1
LCH2
0
0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_010C (DMA0); IPSBAR + 0x011C (DMA1);
IPSBAR + 0x012C (DMA2); IPSBAR + 0x013C (DMA3)
Figure 14-8. DMA Control Registers (DCRn)
Table 14-4. DCRn Field Descriptions
0 0 0 0
Bits
31
30
Name
INT
EEXT
Description
Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
Enable external request. Care should be taken because a collision can occur between the
START bit and DREQn when EEXT = 1.
0 External request is ignored.
1 Enables external request to initiate transfer. The internal request (initiated by setting the
START bit) is always enabled.
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14-10 Freescale Semiconductor
Bits
29
28
27–25
24-23
22
21–20
19
Memory Map/Register Definition
Name
CS
AA
BWC
Table 14-4. DCRn Field Descriptions (Continued)
Description
Cycle steal.
0 DMA continuously makes read/write transfers until the BCR decrements to 0.
1 Forces a single read/write transfer per request. The request may be internal by setting the START bit, or external by asserting DREQn.
Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that
is, transfers are optimized based on the address and size. See Section 14.4.4.2,
.”
0 Auto-align disabled
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches a multiple of the BWC value, the DMA releases the bus.
BWC
000
001
010
011
100
101
110
111
Number of kilobytes per block
DMA has priority and does not negate its request until transfer completes.
16 Kbytes
32 Kbytes
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
1024 Kbytes
—
SINC
SSIZE
DINC
Reserved, should be cleared.
Source increment. Controls whether a source address increments after each successful transfer.
0 No change to SAR after a successful transfer.
1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size.
Source size. Determines the data size of the source bus cycle for the DMA control module.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
Destination increment. Controls whether a destination address increments after each successful transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.
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Freescale Semiconductor 14-11
DMA Controller Module
Bits
18–17
16
15–12
Table 14-4. DCRn Field Descriptions (Continued)
Name Description
DSIZE Destination size. Determines the data size of the destination bus cycle for the DMA controller.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
START Start transfer.
0 DMA inactive
1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one system clock and is always read as logic 0.
SMOD Source address modulo. Defines the size of the source data circular buffer used by the
DMA Controller. If enabled (SMOD is non-zero), the buffer base address will be located on a boundary of the buffer size. The value of this boundary is based upon the initial source address (SAR).
14-12
11–8
7
6
DMOD Destination address modulo. Defines the size of the destination data circular buffer used by the DMA Controller. If enabled (DMOD value is non-zero), the buffer base address will be located on a boundary of the buffer size. The value of this boundary depends on the initial destination address (DAR).
.
DMOD
0000
0001
0010
...
1111
Circular Buffer Size
Buffer Disabled
16 Bytes
32 Bytes
...
256 Kbytes
D_REQ Disable request. DMA hardware automatically clears the corresponding DCRn[EEXT] bit when the byte count register reaches zero.
—
0 EEXT bit is not affected.
1 EEXT bit is cleared when the BCR is exhausted.
Reserved, should be cleared.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Bits
5–4
3-2
1-0
Functional Description
Table 14-4. DCRn Field Descriptions (Continued)
Name Description
LINKCC Link channel control. Allows DMA channels to have their transfers linked. The current
DMA channel will trigger a DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits.
00 No channel-to-channel linking
01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to
LCH2 after the BCR decrements to zero.
10 Perform a link to channel LCH1 after each cycle-steal transfer
11 Perform a link to channel LCH1 after the BCR decrements to zero
LCH1
LCH2
If not in cycle steal mode (DCRn[CS]=0) and LINKCC=01 or 10, then no link to LCH1 will occur.
If LINKCC = 01, a link to LCH1 is created after each cycle-steal transfer performed by the current DMA channel is completed. As the last cycle-steal is performed and the BCR reaches zero, then the link to LCH1 is closed and a link to LCH2 is created.
If the LINKCC field is non-zero, the contents of the bandwidth control field (DCRn[BWC]) are ignored and effectively forced to zero by the DMA hardware. This is done to prevent any non-zero bandwidth control settings from allowing channel arbitration while any type of link is to be performed.
Link channel 1. Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
Link channel 2. Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
14.4 Functional Description
In the following discussion, the term ‘DMA request’ implies that DCRn[START] or
DCRn[EEXT] is set, followed by assertion of and internal or external DMA request. The START bit is cleared when the channel begins an internal access.
Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE,DSIZE] are consistent with the source and destination addresses. If they are not consistent, the configuration error bit, DSRn[CE], is set. If misalignment is detected, no transfer occurs, DSRn[CE] is set, and, depending on the DCR configuration, an interrupt event is issued. Note that if the auto-align bit,
DCRn[AA], is set, error checking is performed on the appropriate registers.
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Freescale Semiconductor 14-13
DMA Controller Module
A read/write transfer reads bytes from the source address and writes them to the destination address. The number of bytes is the larger of the sizes specified by DCRn[SSIZE] and
DCRn[DSIZE]. See
Section 14.3.5, “DMA Control Registers (DCR0–DCR3)
.”
Source and destination address registers (SARn and DARn) can be programmed in the DCRn to increment at the completion of a successful transfer. BCRn decrements when an address transfer write completes for a single-address access (DCRn[SAA] = 0) or when SAA = 1.
14.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)
The DMA channel supports internal and external requests. A request is issued by setting
DCRn[START] or by asserting DREQn. Setting DCRn[EEXT] enables recognition of external
DMA requests. Selecting between cycle-steal and continuous modes minimizes bus usage for either internal or external requests.
• Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to destination occurs for each request. If DCRn[EEXT] is set, a request can be either internal or external.
An internal request is selected by setting DCRn[START]. An external request is initiated by asserting DREQn while DCRn[EEXT] is set. Note that multiple transfers will occur if
DREQn is continuously asserted.
• Continuous mode (DCRn[CS] = 0)—After an internal or external request, the DMA continuously transfers data until BCRn reaches zero or a multiple of DCRn[BWC] or until
DSRn[DONE] is set. If BCRn is a multiple of BWC, the DMA request signal is negated until the bus cycle terminates to allow the internal arbiter to switch masters. DCRn[BWC]
= 000 specifies the maximum transfer rate; other values specify a transfer rate limit.
The DMA performs the specified number of transfers, then relinquishes bus control. The
DMA negates its internal bus request on the last transfer before BCRn reaches a multiple of the boundary specified in BWC. On completion, the DMA reasserts its bus request to regain mastership at the earliest opportunity. The DMA loses bus control for a minimum of one bus cycle.
14.4.2 Dual-Address Data Transfer Mode
Each channel supports dual-address transfers. Dual-address transfers consist of a source data read and a destination data write. The DMA controller module begins a dual-address transfer sequence during a DMA request. If no error condition exists, DSRn[REQ] is set.
• Dual-address read—The DMA controller drives the SARn value onto the internal address bus. If DCRn[SINC] is set, the SARn increments by the appropriate number of bytes upon a successful read cycle. When the appropriate number of read cycles complete (multiple reads if the destination size is larger than the source), the DMA initiates the write portion of the transfer.
If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop.
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14-14 Freescale Semiconductor
Functional Description
• Dual-address write—The DMA controller drives the DARn value onto the address bus. If
DCRn[DINC] is set, DARn increments by the appropriate number of bytes at the completion of a successful write cycle. BCRn decrements by the appropriate number of bytes. DSRn[DONE] is set when BCRn reaches zero. If the BCRn is greater than zero, another read/write transfer is initiated. If the BCRn is a multiple of DCRn[BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters.
If a termination error occurs, DSRn[BED,DONE] are set and DMA transactions stop.
14.4.3 Channel Initialization and Startup
Before a block transfer starts, channel registers must be initialized with information describing configuration, request-generation method, and the data block.
14.4.3.1 Channel Prioritization
The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel 3 having the lowest) or in an order determined by DCRn[BWC]. If the BWC encoding for a DMA channel is 000, that channel has priority only over the channel immediately preceding it.
For example, if DCR3[BWC] = 000, DMA channel 3 has priority over DMA channel 2 (assuming
DCR2[BWC] ≠ 000) but not over DMA channel 1.
If DCR0[BWC] = DCR1[BWC] = 000, DMA0 still has priority over DMA1. In this case,
DCR1[BWC] = 000 does not affect prioritization.
Simultaneous external requests are prioritized either in ascending order or in an order determined by each channel’s DCRn[BWC] bits.
14.4.3.2 Programming the DMA Controller Module
Note the following general guidelines for programming the DMA:
• No mechanism exists within the DMA module itself to prevent writes to control registers during DMA accesses.
• If the DCRn[BWC] value of sequential channels are equal, the channels are prioritized in ascending order.
The DMAREQC register is configured to assign peripheral DMA requests or external DMA request signals to the individual DMA channels.
The SARn is loaded with the source (read) address. If the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. If the transfer is from memory to either a peripheral device or memory, the source address is the starting address of the data block. This can be any aligned byte address.
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Freescale Semiconductor 14-15
DMA Controller Module
The DARn should contain the destination (write) address. If the transfer is from a peripheral device to memory, or from memory to memory, the DARn is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, DARn is loaded with the address of the peripheral data register. This address can be any aligned byte address.
SARn and DARn change after each cycle depending on DCRn[SSIZE,DSIZE,
SINC,DINC,SMOD,DMOD] and on the starting address. Increment values can be 1, 2, 4, or 16 for byte, word, longword, or 16-byte line transfers, respectively. If the address register is programmed to remain unchanged (no count), the register is not incremented after the data transfer.
BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2,
4, or 16 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared for channel startup.
As soon as the channel has been initialized, it is started by writing a one to DCRn[START] or asserting DREQn, depending on the status of DCRn[EEXT]. Programming the channel for internal requests causes the channel to request the bus and start transferring data immediately. If the channel is programmed for external request, DREQn must be asserted before the channel requests the bus.
Changes to DCRn are effective immediately while the channel is active. To avoid problems with changing a DMA channel setup, write a one to DSRn[DONE] to stop the DMA channel.
14.4.4 Data Transfer
This section describes external requests, auto-alignment, and bandwidth control for DMA transfers.
14.4.4.1 External Request and Acknowledge Operation
The DMAREQC register in the System Control Module provides a software-controlled connection matrix between the on- and off-chipplatform DMA request and acknowledge signals.
Writing to this register determines the exact routing of the DMA requests to the four channels of the DMA module and the acknowledges back to the requesters. If DCRn[EEXT] is set and the channel is idle, the assertion of the appropriate DREQn or eTPU request activates channel n.
Channels 0, 1, and 2 initiate transfers to an external module by means of DREQ[32:0]. (They are also available internally to the UART & DTIM interrupt signals.) The request for channel 3 is not connected externally and is only available internally to the eTPU, UART, and DTIM interrupt signals. If DCRn[EEXT] = 1 and the channel is idle, the DMA initiates a transfer when DREQn is asserted or if the eTPU initiates a request.
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14-16 Freescale Semiconductor
Functional Description
shows the minimum 4-clock cycle delay from when DREQn is sampled asserted to when a DMA bus cycle begins. This delay may be longer, depending on DMA priority, bus
arbitration, and other factors. Figure 14-9 shows the relationship between the assertion of a
properly enabled DREQn, the DMA acknowledge, and the activation of the channel for a transfer where both the source and destination are mapped to chip select memories on the external bus.
0 1 2 3 4 5 6 7 8 9 10
CLKIN
DREQn
DACKn
TS
CS
TA
R/W
A[23:0]
0 1 2 3 4 5
Read
6 7 8
Write
9 10 11
CLKIN
DREQn
DACKn
TS
CS
TA
R/W
A[31:0]
Read Write
Figure 14-9. DREQ n Timing Constraints, Dual-Address DMA Transfer
Once the DMA module has detected the assertion of a properly-enabled DREQn, it responds with a 1-cycle assertion of an acknowledge signal. This request/acknowledge handshake is provided so the request can be negated.
Since bus timings can vary from device to device, the diagrams below are conditionalized for 5210 only. The information is really just a repeat from the EIM/FlexBus and SDRAMC chapters, so the customers should not need this information. -MH
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Freescale Semiconductor 14-17
DMA Controller Module
shows a dual-address, external peripheral-to-SDRAM DMA transfer. The DMA is not parked on the bus, so the diagram shows how the CPU can generate multiple bus cycles during
DMA transfers. In cycle-steal mode, the maximum length of DREQ assertion to maintain a single transfer is configuration-dependent. To avoid multiple transfers, for single-address accesses, no hold signal, byte accesses, and idle channels, DREQ may be asserted for no more than four clock cycles.
CLKIN
TS
AS
TIP
A[31:0]
R/W
SIZ[1:0]
D[31:0]
CSx
TA
DRAMW
SD_SRAS
SD_SCAS
RAS[1:0]
CAS[3:0]
DREQn
Precharge
DACKn
CPU DMA Read CPU DMA Write CPU
Figure 14-10. Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer
shows a single-address DMA transfer in which an external peripheral is reading from memory.
14-18
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Freescale Semiconductor
CLKIN
DREQ n
0 1 2 3 4 5 6 7 8 9 10
Functional Description
11
TS
A[31:0], SIZ[1:0]
TIP
R/W
CSx, AS
OE, BE/BWE
TA
D[31:0]
Figure 14-11. Single-Address DMA Transfer
14.4.4.2 Auto-Alignment
Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. To use this feature, DCRn[AA] must be set. The source is auto-aligned if DCRn[SSIZE] indicates a transfer size larger than DCRn[DSIZE]. Source alignment takes precedence over the destination when the source and destination sizes are equal.
Otherwise, the destination is auto-aligned. The address register chosen for alignment increments regardless of the increment value. Configuration error checking is performed on registers not chosen for alignment.
If BCRn is greater than 16, the address determines transfer size. Bytes, words, or longwords are transferred until the address is aligned to the programmed size boundary, at which time accesses begin using the programmed size.
If BCRn is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer size. For example, AA = 1, SARn = 0x0001, BCRn = 0x00F0, SSIZE = 00 (longword), and DSIZE
= 01 (byte). Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on destination registers. The access sequence is as follows:
1. Read byte from 0x0001—write 1 byte, increment SARn.
2. Read word from 0x0002—write 2 bytes, increment SARn.
3. Read longword from 0x0004—write 4 bytes, increment SARn.
4. Repeat longwords until SARn = 0x00F0.
5. Read byte from 0x00F0—write byte, increment SARn.
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Freescale Semiconductor 14-19
DMA Controller Module
If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size.
14.4.4.3 Bandwidth Control
Bandwidth control makes it possible to force the DMA off the bus to allow access to another device. DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates.
If a request is pending, the arbiter may then pass bus mastership to another device. If auto-alignment is enabled, DCRn[AA] = 1, the BCRn may skip over the programmed boundary, in which case, the DMA bus request is not negated.
If BWC = 000, the request signal remains asserted until BCRn reaches zero. DMA has priority over the core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus.
See
Section 11.3.3, “Bus Master Park Register (MPARK) .”
14.4.5 Termination
An unsuccessful transfer can terminate for one of the following reasons:
• Error conditions—When the MCF5271 encounters a read or write cycle that terminates
with an error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write before the transfer is halted. If the error occurred in a write cycle, data in the internal holding register is lost.
• Interrupts—If DCRn[INT] is set, the DMA drives the appropriate internal interrupt signal.
The processor can read DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits.
14-20
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Freescale Semiconductor
Chapter 15
Edge Port Module (EPORT)
15.1 Introduction
The edge port module (EPORT) has seven external interrupt pins, IRQ7–IRQ1.
Each pin can be configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising
edge, falling edge, or both), or a general-purpose input/output (I/O) pin. See Figure 15-1 .
Stop
Mode
EPPAR[2n, 2n + 1]
Edge Detect
Logic
EPFRn D0
D1
Q D0
D1
Q To Interrupt
Controller
EPPDRn
Synchronizer
EPIERn
Rising Edge of System Clock
EPDRn IRQn PIN
EPDDRn
Figure 15-1. EPORT Block Diagram
15.2 Low-Power Mode Operation
This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see
Chapter 8, “Power Management .”
shows
EPORT module operation in low-power modes, and describes how this module may exit from each mode.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
15-1
Edge Port Module (EPORT)
NOTE
The low-power interrupt control register (LPICR) in the System
Control Module specifies the interrupt level at or above which is needed to bring the device out of a low-power mode.
Table 15-1. Edge Port Module Operation in Low-power Modes
Low-power Mode
Wait
Doze
Stop
EPORT Operation
Normal
Normal
Level-sensing Only
Mode Exit
Any IRQn Interrupt at or above level in LPICR
Any IRQn Interrupt at or above level in LPICR
Any IRQn Interrupt set for level-sensing at or above level in LPICR
In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may be configured to exit the low-power modes by generating an interrupt request on either a selected edge or a low level on an external pin. In stop mode, there are no clocks available to perform the edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode.
NOTE
The input pin synchronizer is bypassed for the level-detect logic since no clocks are available.
15.3 Interrupt/General-Purpose I/O Pin Descriptions
All pins default to general-purpose input pins at reset. The pin value is synchronized to the rising edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values used in the edge/level detect logic are also synchronized to the rising edge of CLKOUT. These pins use
Schmitt triggered input buffers which have built in hysteresis designed to decrease the probability of generating false edge-triggered interrupts for slow rising and falling input signals.
When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are high at reset.
15.4 Memory Map/Register Definition
This subsection describes the memory map and register structure. Refer to
for a description of the EPORT memory map. The EPORT has an IPSBAR offset for base address of
0x0013_0000.
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15-2 Freescale Semiconductor
Memory Map/Register Definition
Table 15-2. Edge Port Module Memory Map
IPSBAR
Offset
Bits 15–8 Bits 7–0 Access
0x13_0000 EPORT Pin Assignment Register (EPPAR) S
0x13_0002 EPORT Data Direction Register (EPDDR) EPORT Interrupt Enable Register (EPIER) S
0x13_0004
0x13_0006
EPORT Data Register (EPDR)
EPORT Flag Register (EPFR)
EPORT Pin Data Register (EPPDR)
Reserved
2
S/U
S/U
1
2
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.
Writing to reserved address locations has no effect, and reading returns 0s.
1
15.4.1 Register Description
The EPORT programming model consists of these registers:
• The EPORT pin assignment register (EPPAR) controls the function of each pin individually.
• The EPORT data direction register (EPDDR) controls the direction of each one of the pins individually.
• The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin individually.
• The EPORT data register (EPDR) holds the data to be driven to the pins.
• The EPORT pin data register (EPPDR) reflects the current state of the pins.
• The EPORT flag register (EPFR) individually latches EPORT edge events.
15.4.1.1 EPORT Pin Assignment Register (EPPAR)
15 14
R EPPA7
W
Reset 0
Address
0
13 12
EPPA6
0 0
11 10
EPPA5
0 0
9
EPPA4
8
0 0
7
EPPA3
6
0 0
5
EPPA2
4
0 0
3
EPPA1
2
0
IPSBAR + 0x13_0000
Figure 15-2. EPORT Pin Assignment Register (EPPAR)
0
1
0
0
0
0
0
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
15-3
Edge Port Module (EPORT)
Bits
15–2
1–0
Table 15-3. EPPAR Field Descriptions
Name Description
EPPAn EPORT pin assignment select fields. The read/write EPPAn fields configure EPORT pins for level detection and rising and/or falling edge detection.
Pins configured as level-sensitive are inverted so that a logic 0 on the external pin represents a valid interrupt request. Level-sensitive interrupt inputs are not latched. To guarantee that a level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. Level sensitivity must be selected to bring the device out of stop mode with an IRQn interrupt.
Pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. A pin configured for edge detection can trigger an interrupt regardless of its configuration as input or output.
Interrupt requests generated in the EPORT module can be masked by the interrupt controller module. EPPAR functionality is independent of the selected pin direction.
Reset clears the EPPAn fields.
00 Pin IRQn level-sensitive
01 Pin IRQn rising edge triggered
10 Pin IRQn falling edge triggered
11 Pin IRQn both falling edge and rising edge triggered
— Reserved, should be cleared.
15.4.1.2 EPORT Data Direction Register (EPDDR)
15 14
R EPDD7
W
Reset 0
Address
0
13 12
EPDD6
0 0
11 10
EPDD5
0 0
9 8
EPDD4
0 0
7 6
EPDD3
0 0
5 4
EPDD2
0 0
3 2
EPDD1
0
IPSBAR + 0x13_0002
Figure 15-3. EPORT Data Direction Register (EPDDR)
0
Table 15-4. EPDD Field Descriptions
Bits
7–1
0
1
0
0
0
0
0
Name Description
EPDDn Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in EPDDR configures the corresponding pin as an input. Pin direction is independent of the level/edge detection configuration. Reset clears EPDD7–EPDD1.
To use an EPORT pin as an external interrupt request source, its corresponding bit in
EPDDR must be clear. Software can generate interrupt requests by programming the
EPORT data register when the EPDDR selects output.
0 Corresponding EPORT pin configured as input
1 Corresponding EPORT pin configured as output
— Reserved, should be cleared.
15-4
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Freescale Semiconductor
Memory Map/Register Definition
15.4.1.3 Edge Port Interrupt Enable Register (EPIER)
Bits
7–1
0
W
Reset
7 6 5 4 3 2 1
R EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1
0 0 0 0 0 0 0
0
0
0
Address IPSBAR + 0x13_0003
Figure 15-4. EPORT Port Interrupt Enable Register (EPIER)
Table 15-5. EPIER Field Descriptions
Name
EPIEn
—
Description
Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set,
EPORT generates an interrupt request when:
• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set.
• The corresponding pin level is low and the pin is configured for level-sensitive operation.
Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin.
Reset clears EPIE7–EPIE1.
0 Interrupt requests from corresponding EPORT pin disabled
1 Interrupt requests from corresponding EPORT pin enabled
Reserved, should be cleared.
15.4.1.4 Edge Port Data Register (EPDR)
Bits
7–1
0
W
Reset
7 6 5 4 3 2 1
R EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1
1 1 1 1 1 1 1
Address IPSBAR + 0x13_0004
Figure 15-5. EPORT Port Data Register (EPDR)
0
0
1
Name
EPDn
—
Table 15-6. EPDR Field Descriptions
Description
Edge port data bits. Data written to EPDR is stored in an internal register; if any pin of the port is configured as an output, the bit stored for that pin is driven onto the pin. Reading
EDPR returns the data stored in the register. Reset sets EPD7–EPD1.
Reserved, should be cleared.
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MCF5271 Reference Manual, Rev. 2
15-5
Edge Port Module (EPORT)
15.4.1.5 Edge Port Pin Data Register (EPPDR)
Bits
7–1
0
W
Reset
7 6 5 4 3 2 1
R EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1
Current pin state
Address IPSBAR + 0x13_0005
Figure 15-6. EPORT Port Pin Data Register (EPPDR)
0
0
0
Table 15-7. EPPDR Field Descriptions
Name Description
EPPDn Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins
IRQ7–IRQ1. Writing to EPPDR has no effect, and the write cycle terminates normally.
Reset does not affect EPPDR.
— Reserved, should be cleared.
15.4.1.6 Edge Port Flag Register (EPFR)
Bits
7–1
0
W
Reset
7 6 5 4 3 2 1
R EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1
0 0 0 0 0 0 0
Address IPSBAR + 0x13_0006
Figure 15-7. EPORT Port Flag Register (EPFR)
Table 15-8. EPFR Field Descriptions
0
0
0
Name
EPFn
—
Description
Edge port flag bits. When an EPORT pin is configured for edge triggering, its corresponding read/write bit in EPFR indicates that the selected edge has been detected.
Reset clears EPF7–EPF1.
Bits in this register are set when the selected edge is detected on the corresponding pin.
A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARn = 00), pin transitions do not affect this register.
0 Selected edge for IRQn pin has not been detected.
1 Selected edge for IRQn pin has been detected.
Reserved, should be cleared.
15-6
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Freescale Semiconductor
Chapter 16
Chip Select Module
16.1 Introduction
This chapter describes the chip select module, including the operation and programming model of the chip select registers, which include the chip select address, mask, and control registers.
NOTE
Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used for the bus (f sys/2
).
16.1.1 Overview
The following list summarizes the key chip select features:
• Eight independent, user-programmable chip select signals (CS[7:0]) that can interface with external SRAM, PROM, EPROM, EEPROM, Flash, and peripherals
• Address masking for 64-Kbyte to 4-Gbyte memory block sizes
• Enhanced secondary wait states
• Access error on writes to write-protect (WP) region
16.2 External Signal Description
This section describes the signals used by the chip select module.
16.2.1 Chip Selects (CS[7:0])
Each CSn can be independently programmed for an address location as well as for masking, port size, read/write burst capability, wait-state generation, and internal/external termination. Only CS0 is initialized at reset and may act as an external boot chip select to allow boot ROM to be at an external address space. Port size for CS0 is configured by the logic levels of D[20:19] when
RSTOUT negates and RCON is asserted.
16.2.2 Output Enable (OE)
Interfaces to memory or to peripheral devices and enables a read transfer. It is asserted and negated on the falling edge of the clock. OE is asserted only when one of the chip selects matches for the current address decode.
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Freescale Semiconductor 16-1
Chip Select Module
16.2.3 Byte Strobes (BS[3:0])
These signals are individually programmed through the byte-enable mode bit, CSCRn[BEM], described in
Section 16.4.1.3, “Chip Select Control Registers (CSCR0–CSCR7)
.”
These generated signals provide byte data select signals, which are decoded from the transfer size,
A1, and A0 signals in addition to the programmed port size and burstability of the memory accessed, as shown below.
The below table also shows the interaction of the byte-enable/byte-write enables with related signals.
Table 16-1. Byte Enables/Byte Write Enable Signal Settings
Transfer Size Port Size
Byte
Word
Longword
8-bit
16-bit
32-bit
8-bit
16-bit
32-bit
8-bit
16-bit
32-bit
A1
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
A0
BS3
D[31:24]
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
BS2
D[23:16]
0
0
1
1
0
1
1
0
1
0
0
1
1
1
1
1
1
1
0
1
0
1
0
1
1
1
1
BS1
D[15:8]
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
BS0
D[7:0]
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
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16-2 Freescale Semiconductor
Chip Select Operation
Table 16-1. Byte Enables/Byte Write Enable Signal Settings (Continued)
Transfer Size Port Size
Line 8-bit
16-bit
32-bit
A1
0
1
1
1
0
0
0
A0
0
0
0
1
0
1
0
BS3
D[31:24]
0
0
0
0
0
0
0
BS2
D[23:16]
0
0
1
1
1
1
0
BS1
D[15:8]
1
1
1
1
1
1
0
BS0
D[7:0]
1
1
1
1
1
1
0
16.3 Chip Select Operation
Each chip select has a dedicated set of registers for configuration and control.
• Chip select address registers (CSARn) control the base address of the chip select. See
• Chip select mask registers (CSMRn) provide 16-bit address masking and access control.
• Chip select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, and automatic acknowledge generation features. See
CS0 is a global chip select after reset and provides relocatable boot ROM capability.
16.3.1 General Chip Select Operation
When a bus cycle is initiated, the MCF5271 first compares its address with the base address and mask configurations programmed for chip selects 0–7 (configured in CSCR0–CSCR7) and
DRAM blocks 0 and 1 (configured in DACR0 and DACR1). If the driven address matches a programmed chip select or DRAM block, the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed in the respective configuration register.
Otherwise, the following occurs:
• If the address and attributes do not match in CSAR or DACR, the MCF5271 runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port.
• Should an address and attribute match in multiple CSCRs, the matching chip select signals are driven; however, the chip select signals are driven during an external burst-inhibited bus cycle with external termination on a 32-bit port.
• If the address and attribute match both DACRs or a DACR and a CSAR, the operation is undefined.
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Freescale Semiconductor 16-3
Chip Select Module
Table 16-2 shows the type of access as a function of match in the CSARs and DACRs.
Table 16-2. Accesses by Matches in CSARs and DACRs
Number of CSCR Matches
0
1
Multiple
0
1
Multiple
0
1
Multiple
Number of DACR Matches
1
1
Multiple
Multiple
Multiple
0
1
0
0
Type of Access
External
Defined by CSAR
External, burst-inhibited, 32-bit
Defined by DACRs
Undefined
Undefined
Undefined
Undefined
Undefined
16.3.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 16.4.1.3 for
more information.
Figure 16-1 shows the correspondence between the data bus and the external
byte strobe control lines (BS[3:0]). Note that all byte lanes are driven, although the state of unused byte lanes is undefined.
External data bus
32-bit port memory
16-bit port memory
BS3 BS2 BS1
D[31:24] D[23:16] D[15:8]
Byte 0 Byte 1 Byte 2
BS0
D[7:0]
Byte 3
Byte 0
Byte 2
Byte 1
Byte 3
Driven, undefined
8-bit port memory
Byte 0
Byte 1
Byte 2
Byte 3
Driven, undefined
Figure 16-1. Connections for External Memory Port Sizes
16.3.2 Enhanced Wait State Operation
The chip-select logic has been enhanced to add the notion of secondary wait-state counter values to be used after the initial wait-state value (where the existing wait state field becomes the initial access wait state) is applied to the first access. Two fields in the Chip-Select Control Registers
MCF5271 Reference Manual, Rev. 2
16-4 Freescale Semiconductor
Chip Select Operation
(CSCRn) are defined as the secondary read wait state (SRWS) value and the secondary write wait state (SWWS) value. The application of the secondary wait state values is only enabled when the auto-acknowledge feature is enabled, i.e., CSCRn[AA] = 1.
High-performance memory devices typically require a x-y-y-y response where x is the initial wait-state value and y is the secondary wait-state value. For non-SDRAM memory devices likely to be connected to a MCF5271 device, memory response times of {5-9}-{1-2}-{1-2}-{1-2} are typical. This function is supported with the secondary wait state counters.
S0 S1 S2 S3 WS S4 S5 WS S6 S7 WS S8 S9 WS S10 S11
CLKOUT
A[23:0]
R/W, TIP
TSIZ[1:0]
TS
CSn, OE, BSn
D[31:0]
TA
Write Write Write Write
Figure 16-2. Secondary Wait State Writes
S0 S1 S2 S3 WS S4 S5 WS S6 S7 WS S8 S9 WS S10 S11
CLKOUT
A[23:0]
R/W, TIP
TSIZ[1:0]
TS
CSn, OE, BSn
D[31:0]
TA
Write Write Write Write
Figure 16-3. Secondary Wait State Reads
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 16-5
Chip Select Module
Each CSCR, shown in
Figure 16-6 , controls the auto-acknowledge, port size, burst capability, and
activation of each chip select.
16.3.2.1 External Boot Chip Select Operation
CS0, the external boot chip select, allows address decoding for boot ROM before system initialization. Its operation differs from other external chip select outputs after system reset.
After system reset, CS0 is asserted for every external access. No other chip select can be used until the valid bit, CSMR0[V], is set, at which point CS0 functions as configured and CS[7:1] can be used. At reset, the port size function of the external boot chip select is determined by the logic levels of the inputs on D[20:19].
and
Table 16-3 list the various reset encodings for the
configuration signals multiplexed with D[20:19].
Table 16-3. D[20:19] External Boot Chip Select Configuration
D[20:19]
00
01
10
11
Boot Device/Data Port Size
External (32-bit)
External (16-bit)
External (8-bit)
External (32-bit)
Provided the required address range is in the chip select address register (CSAR0), CS0 can be programmed to continue decoding for a range of addresses after the CSMR0[V] is set, after which the external boot chip select can be restored only by a system reset.
16.4 Memory Map/Register Definition
Table 16-4 shows the chip select register memory map. Reading reserved locations returns zeros.
Table 16-4. Chip Select Registers
IPSBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x00_0080 Chip select address register—bank 0 (CSAR0) Reserved
1
0x00_0084
0x00_0088
0x00_008C
Chip select mask register—bank 0 (CSMR0)
Reserved
Chip select control register—bank 0 (CSCR0)
Chip select address register—bank 1 (CSAR1)
0x00_0090
0x00_0094
0x00_0098
Chip select mask register—bank 1 (CSMR1)
Reserved
Chip select control register—bank 1 (CSCR1)
Chip select address register—bank 2 (CSAR2)
0x00_009C Chip select mask register—bank 2 (CSMR2)
MCF5271 Reference Manual, Rev. 2
16-6 Freescale Semiconductor
Memory Map/Register Definition
Table 16-4. Chip Select Registers (Continued)
IPSBAR
Offset
0x00_00A0
0x00_00A4
[31:24]
Reserved
[23:16]
Chip select address register—bank 3 (CSAR3)
[15:8] [7:0]
Chip select control register—bank 2 (CSCR2)
0x00_00A8
0x00_00A
C
Reserved
Chip select mask register—bank 3 (CSMR3)
Chip select control register—bank 3 (CSCR3)
0x00_00B0 Chip select address register—bank 4 (CSAR4)
0x00_00B4
0x00_00B8
0x00_00B
C
Reserved
Chip select address register—bank 5 (CSAR5)
Chip select mask register—bank 4 (CSMR4)
Chip select control register—bank 4 (CSCR4)
Reserved
0x00_00C0
0x00_00C4
0x00_00C8
Chip select mask register—bank 5 (CSMR5)
Reserved
Chip select control register—bank 5 (CSCR5)
Chip select address register—bank 6 (CSAR6) Reserved
0x00_00C
C
Chip select mask register—bank 6 (CSMR6)
0x00_00D0 Reserved
0x00_00D4 Chip-select address register—bank 7 (CSAR7)
Chip select control register—bank 6 (CSCR6)
Reserved
0x00_00D8
0x00_00D
C
Reserved
Chip-select mask register—bank 7 (CSMR7)
Chip-select control register—bank 7 (CSCR7)
1
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect.
16.4.1 Chip Select Module Registers
The chip select module is programmed through the chip select address registers
(CSAR0–CSAR7), chip select mask registers (CSMR0–CSMR7), and the chip select control registers (CSCR0–CSCR7).
16.4.1.1 Chip Select Address Registers (CSAR0–CSAR7)
The CSARs, Figure 16-4 , specify the chip select base addresses.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
16-7
Chip Select Module
15
R
W
Reset —
Address
Bits
15–0
14 13 12 11 10 9 8
BA
7 6 5 4 3 2 1 0
— — — — — — — — — — — —
IPSBAR + 0x00_0080 (CSAR0); IPSBAR + 0x00_008C (CSAR1);
IPSBAR + 0x00_0098 (CSAR2); IPSBAR + 0x00_00A4 (CSAR3);
IPSBAR + 0x00_00B0 (CSAR4); IPSBAR + 0x00_00BC (CSAR5);
IPSBAR + 0x00_00C8 (CSAR6); IPSBAR + 0x00_00D4 (CSAR7)
Figure 16-4. Chip Select Address Registers (CSARn)
Table 16-5. CSARn Field Description
—
Name
BA
— —
Description
Base address. Defines the base address for memory dedicated to chip select CS[7:0]. BA is compared to bits 31–16 on the internal address bus to determine if chip select memory is being accessed.
16.4.1.2 Chip Select Mask Registers (CSMR0–CSMR7)
The CSMRs,
, are used to specify the address masks for the respective chip selects.
17 16 31
R
W
Reset —
15
R 0
W
Reset —
Address
30
—
14
0
29 28
—
13
0
—
12
0
27 26
—
11
0
—
10
0
25 24
BAM
23
—
9
0
—
8
WP
—
7
0
22
—
6
0
21 20
—
5
0
—
4
0
19 18
—
3
0
—
2
0
— — — — — — — — — — — —
IPSBAR + 0x00_0084 (CSMR0); IPSBAR + 0x00_0090 (CSMR1);
IPSBAR + 0x00_009C (CSMR2); IPSBAR + 0x00_00A8 (CSMR3);
IPSBAR + 0x00_00B4 (CSMR4); IPSBAR + 0x00_00C0 (CSMR5);
IPSBAR + 0x00_00CC (CSMR6); IPSBAR + 0x00_00D8 (CSMR7)
Figure 16-5. Chip Select Mask Registers (CSMRn)
—
—
1
0
—
0
V
— 0
16-8
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Bits
31–16
8
7–1
0
Name
BAM
WP
—
V
Memory Map/Register Definition
Table 16-6. CSMRn Field Descriptions
Description
Base address mask. Defines the chip select block by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be ignored in the decode.
0 Corresponding address bit is used in chip select decode.
1 Corresponding address bit is a don’t care in chip select decode.
The block size for CS[7:0] is 2 n
where n = (number of bits set in respective
CSMR[BAM]) + 16. For example, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0001, CS0 addresses a 128-Kbyte (2 access 32 Mbytes (2
25
17
byte) range from 0x0000–0x1_FFFF. Likewise, for CS0 to access 16 Mbytes (2
24
bytes) of address space starting at location 0x0000, and for CS1 to
bytes) of address space starting after the CS0 space, then
CSAR0 = 0x0000, CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and
CSMR1[BAM] = 0x00FF.
Write protect. Controls write accesses to the address range in the corresponding CSAR.
Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the appropriate chip select not being selected and an access error exception will occur.
0 Both read and write accesses are allowed.
1 Only read accesses are allowed.
Reserved, should be cleared.
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip selects do not assert until V is set (except for CS0, which acts as the global chip select). Reset clears each CSMRn[V].
0 Chip select invalid
1 Chip select valid
16.4.1.3 Chip Select Control Registers (CSCR0–CSCR7)
Each CSCR, shown in
, controls the auto-acknowledge, port size, burst capability, and activation of each chip select. Note that to support the external boot chip select, CS0, the CSCR0 reset values differ from the other CSCRs. CS0 allows address decoding for boot ROM before system initialization.
15 14
R SRWS
W
Reset: CSCR0 0
—
0
— Reset: Other
CSCRs
Address
13
1
—
12
IWS
11
1
—
1
—
10
1
—
9
0
0
—
8
AA
1
—
7
0
—
PS
6
0
—
5 4 3
BEM BSTR BSTW
0
—
0
—
0
—
IPSBAR + 0x00_008A (CSCR0); IPSBAR + 0x00_0096 (CSCR1);
IPSBAR + 0x00_00A2 (CSCR2); IPSBAR + 0x00_00AE (CSCR3);
IPSBAR + 0x00_00BA (CSCR4); IPSBAR + 0x00_00C6 (CSCR5);
IPSBAR + 0x00_00D2 (CSCR6); IPSBAR + 0x00_00DE (CSCR7)
Figure 16-6. Chip Select Control Registers (CSCRn)
0
—
2 1
SWWS
0
0
—
0
—
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Freescale Semiconductor 16-9
Chip Select Module
Bits
15–14
13–10
9
8
7–6
5
4
Name
SRWS
IWS
—
AA
PS
BEM
BSTR
Table 16-7. CSCRn Field Descriptions
Description
Secondary Read Wait States. The number of wait states applied to all reads after the initial one if properly enabled (SRSW is non-zero and CSCR[AA] = 1). The default value of this field is secondary read wait states disabled. See
Section 16.3.2, “Enhanced Wait State
Operation,” for timing diagrams.
00 Secondary read wait states are disabled. Use CSCR[IWS] for all accesses.
01 0 wait states for the secondary read accesses
10 1 wait state for the secondary read accesses
11 2 wait states for the secondary read accesses
Initial Wait States. The number of wait states inserted before an internal transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait states). If AA = 0, TA must be asserted by the external system regardless of the number of wait states generated. In that case, the external transfer acknowledge ends the cycle. An external TA supercedes the generation of an internal TA.
Reserved, should be cleared.
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by the chip select address.
0 No internal TA is asserted. Cycle is terminated externally.
1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn and the external system asserts an external TA before the wait-state countdown asserts the internal TA, the cycle is terminated. Burst cycles increment the address bus between each internal termination.
Port size. Specifies the width of the data associated with each chip select. It determines where data is driven during write cycles and where data is sampled during read cycles. See
00 32-bit port size. Valid data sampled and driven on D[31:0]
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that must be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide the appropriate mode of byte enable in support of these SRAMs.
0 BS is not asserted for read. BS is asserted for data write only.
1 BS is asserted for read and write accesses.
Burst read enable. Specifies whether burst reads are used for memory associated with each CSn.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and
32-bit ports.
16-10
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Freescale Semiconductor
Bits
3
2–0
Code Example
Table 16-7. CSCRn Field Descriptions (Continued)
Name Description
BSTW Burst write enable. Specifies whether burst writes are used for memory associated with each CSn.
0 Break data larger than the specified port size into individual port-sized, non-burst writes.
For example, a longword write to an 8-bit port takes four byte writes.
1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports.
SWWS Secondary write wait states. The number of wait states applied to all writes after the initial one if properly enabled (SWWS is non-zero and CSCR[AA] = 1). The default for this field is
secondary write wait states disabled. See
Section 16.3.2, “Enhanced Wait State
Operation,” for timing diagrams. This field is encoded as:
000 Secondary write wait states are disabled. Use CSCR[IWS] for all accesses.
001 0 wait states for the secondary write accesses
010 1 wait state for the secondary write accesses
011 2 wait states for the secondary write accesses
100 3 wait states for the secondary write accesses
101 4 wait states for the secondary write accesses
110 5 wait states for the secondary write accesses
111 6 wait states for the secondary write accesses
16.5 Code Example
CSAR0 EQU IPSBARx+0x080 ;Chip select 0 address register
CSMR0 EQU IPSBARx+0x084 ;Chip select 0 mask register
CSCR0 EQU IPSBARx+0x08A ;Chip select 0 control register
CSAR1 EQU IPSBARx+0x08C ;Chip select 1 address register
CSMR1 EQU IPSBARx+0x090 ;Chip select 1 mask register
CSCR1 EQU IPSBARx+0x096 ;Chip select 1 control register
CSAR2 EQU IPSBARx+0x098 ;Chip select 2 address register
CSMR2 EQU IPSBARx+0x09C ;Chip select 2 mask register
CSCR2 EQU IPSBARx+0x0A2 ;Chip select 2 control register
CSAR3 EQU IPSBARx+0x0A4 ;Chip select 3 address register
CSMR3 EQU IPSBARx+0x0A8 ;Chip select 3 mask register
CSCR3 EQU IPSBARx+0x0AE ;Chip select 3 control register
CSAR4 EQU IPSBARx+0x0B0 ;Chip select 4 address register
CSAR4 EQU IPSBARx+0x0B4 ;Chip select 4 mask register
CSMR4 EQU IPSBARx+0x0BA ;Chip select 4 control register
CSAR5 EQU IPSBARx+0x0BC ;Chip select 5 address register
CSMR5 EQU IPSBARx+0x0C0 ;Chip select 5 mask register
CSCR5 EQU IPSBARx+0x0C6 ;Chip select 5 control register
CSAR6 EQU IPSBARx+0x0C8 ;Chip select 6 address register
CSMR6 EQU IPSBARx+0x0CC ;Chip select 6 mask register
CSCR6 EQU IPSBARx+0x0D2 ;Chip select 6 control register
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Freescale Semiconductor 16-11
Chip Select Module
CSAR7 EQU IPSBARx+0x0D4 ;Chip select 7 address register
CSMR7 EQU IPSBARx+0x0D8 ;Chip select 7 mask register
CSCR7 EQU IPSBARx+0x0DE ;Chip select 7 control register
; All other chip selects should be programmed and made valid before global
; chip select is de-activated by validating CS0
; Program Chip Select 3 Registers move.w #0x0040,D0 ;CSAR3 base address 0x00400000 move.w D0,CSAR3 move.w #0x00A0,D0 move.w D0,CSCR3
;CSCR3 = no wait states, AA=0, PS=16-bit, BEM=1,
;BSTR=0, BSTW=0 move.l #0x001F0101,D0;Address range from 0x00400000 to 0x005FFFFF move.l D0,CSMR3 ;WP,V=1; SC,UC=0
; Program Chip Select 2 Registers move.w #0x0020,D0 move.w D0,CSAR2
;CSAR2 base address 0x00200000 (to 0x003FFFFF) move.w #0x0538,D0 move.w D0,CSCR2
;CSCR2 = 1 wait state, AA=1, PS=32-bit, BEM=1,
;BSTR=1, BSTW=1 move.l #0x001F0001,D0 ;Address range from 0x00200000 to 0x003FFFFF move.l D0,CSMR2 ;W=0; V=1
; Program Chip Select 1 Registers move.w #0x0000,D0 move.w D0,CSAR1 move.w #0x09B0,D0 move.w D0,CSCR1
;CSAR1 base addresses 0x00000000 (to 0x001FFFFF)
;and 0x80000000 (to 0x801FFFFF)
;CSCR1 = 2 wait states, AA=1, PS=16-bit, BEM=1,
;BSTR=1, BSTW=0 move.l #0x801F0001,D0 ;Address range from 0x00000000 to 0x001FFFFF and move.l D0,CSMR1 ;0x80000000 to 0x801FFFFF
;WP=0, V=1
; Program Chip Select 0 Registers move.w #0x0080,D0 move.w D0,CSAR0
;CSAR0 base address 0x00800000 (to 0x009FFFFF) move.w #0x0D80,D0 move.w D0,CSCR0
;CSCR0 = three wait states, AA=1, PS=16-bit, BEM=0,
;BSTR=0, BSTW=0
; Program Chip Select 0 Mask Register (validate chip selects) move.l #0x001F0001,D0 ;Address range from 0x00800000 to 0x009FFFFF move.l D0,CSMR0 ;WP=0; V=1
16-12
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Chapter 17
External Interface Module (EIM)
17.1 Introduction
This chapter describes data-transfer operations, error conditions, and reset operations. Chapter 17,
“SDRAM Controller (SDRAMC) ,” describes DRAM cycles.
NOTE
Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used for the bus (f sys/2
).
NOTE
The timing diagrams within this chapter show 32 address lines,
A[31:0]. However, only the lowest 24 address signals are available externally on the MCF5271 device, A[23:0].
17.1.1 Features
The following list summarizes bus operation features:
• Up to 24 bits of address and 32 bits of data
• Access 8-, 16-, and 32-bit data port sizes
• Generates byte, word, longword, and line-size transfers
• Burst and burst-inhibited transfer support
• Optional internal termination for external bus cycles
• Enhanced secondary wait state
17.2 Bus and Control Signals
Table 17-1 summarizes MCF5271 bus signals described in
Chapter 2, “Signal Descriptions .”
Table 17-1. ColdFire Bus Signal Summary
Signal Name
A[23:0]
BS[3:0]
1
D[31:0]
OE
Description
Address bus
Byte selects
Chip selects
Data bus
Output enable
I/O
O
O
O
I/O
O
CLKOUT Edge
Rising
Falling
Falling
Rising
Falling
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 17-1
External Interface Module (EIM)
Table 17-1. ColdFire Bus Signal Summary (Continued)
Signal Name Description I/O CLKOUT Edge
R/W Read/write O Rising
TSIZ[1:0]
TA
Transfer size
Transfer acknowledge
O
I
Rising
Rising
TIP Transfer in progress O Rising
TS Transfer start O Rising
1
These signals change after the falling edge. In the Electrical Specifications, these signals are specified off of the rising edge because CLKIN is squared up internally.
Table 17-2 explains the transfer size encoding of the TSIZ[1:0] signals.
Table 17-2. Transfer Size Encoding
TSIZ[1:0]
00
01
10
11
Transfer Size
Longword
Byte
Word
16-byte line
17.3 Bus Characteristics
The MCF5271 uses its internal bus clock to generate CLKOUT (see Chapter 7, “Clock Module
”).
Therefore, the external bus operates at the same speed as the bus clock rate of f , where all bus sys/2 operations are synchronous to the rising edge of CLKOUT, and some of the bus control signals
(BS, OE, and CSn) are synchronous to the falling edge, shown in
. Bus characteristics may differ somewhat for interfacing with external DRAM.
17-2
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Bus Errors
CLKOUT t vo t ho
Rising-Edge
Signals t vo
Falling-Edge
Signals t si t hi
Inputs t t vo
=Propagation delay of signal relative to CLKOUT edge t ho si t hi
=Output hold time relative to CLKOUT edge
=Required input setup time relative to CLKOUT edge
=Required input hold time relative to CLKOUT edge
Figure 17-1. Signal Relationship to CLKOUT for Non-DRAM Access t ho
17.4 Bus Errors
Attempting to write to a range of addresses that is write protected (CSARn[WP] = 1) will not assert the corresponding chip select. Also, an access error exception will occur. See
Section 16.4.1.2, “Chip Select Mask Registers (CSMR0–CSMR7)”
and
for more details.
17.5 Data Transfer Operation
Data transfers between the MCF5271 and other devices involve the following signals:
• Address bus (A[23:0])
• Data bus (D[31:0])
• Control signals (TS and TA)
• CSn, OE, BSn
• Attribute signals (R/W, TSIZ, and TIP)
The address bus, write data, TS, and all attribute signals change on the rising edge of CLKOUT.
Read data is latched into the MCF5271 on the rising edge of CLKOUT.
The MCF5271 bus supports byte, word, and longword operand transfers and allows accesses to 8-,
16-, and 32-bit data ports. Aspects of the transfer, such as the port size, the number of wait states for the external slave being accessed, and whether internal transfer termination is enabled, can be programmed in the chip-select control registers (CSCRs) and the DRAM control registers
(DACRs).
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 17-3
External Interface Module (EIM)
shows the byte lanes that external memory should be connected to and the sequential transfers if a longword is transferred for three port sizes. For example, an 8-bit memory should be connected to D[31:24] (BS3). A longword transfer takes four transfers on D[31:24], starting with the MSB and going to the LSB.
Byte Enable
Processor
External
Data Bus
32-Bit Port
Memory
BS3
D[31:24]
Byte 0
BS2
D[23:16]
Byte 1
BS1
D[15:8]
Byte 2
BS0
D[7:0]
Byte 3
16-Bit Port
Memory
Byte 0
Byte 2
Byte 1
Byte 3
Driven with indeterminate values
8-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 3
Driven with indeterminate values
Figure 17-2. Connections for External Memory Port Sizes
The timing relationship of chip selects (CS[7:0]), byte selects (BS[3:0]), and output enable (OE) with respect to CLKOUT is similar in that all transitions occur during the low phase of CLKOUT.
However, due to differences in on-chip signal routing, signals may not assert simultaneously.
CLKOUT
CS[7:0]
BS[3:0]
OE
Figure 17-3. Chip-Select Module Output Timing Diagram
17.5.1 Bus Cycle Execution
When a bus cycle is initiated, the MCF5271 first compares the address of that bus cycle with the base address and mask configurations programmed for chip selects 0–7 (configured in
CSCR0–CSCR7) and DRAM block 0 and 1 address and control registers (configured in DACR0 and DACR1). If the driven address compares with one of the programmed chip selects or DRAM blocks, the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed by the user in the respective configuration register. Otherwise, the following occurs:
• If the address and attributes do not match in CSCR or DACR, the MCF5271 runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port.
MCF5271 Reference Manual, Rev. 2
17-4 Freescale Semiconductor
Data Transfer Operation
• Should an address and attribute match in multiple CSCRs, the matching chip-select signals are driven; however, the MCF5271 runs an external burst-inhibited bus cycle with external termination on a 32-bit port.
• Should an address and attribute match both DACRs or a DACR and a CSCR, the operation is undefined.
Table 17-3 shows the type of access as a function of match in the CSCRs and DACRs.
Table 17-3. Accesses by Matches in CSCRs and DACRs
Number of CSCR Matches
0
1
Multiple
0
1
Multiple
0
1
Multiple
Number of DACR Matches
1
1
0
1
0
0
Multiple
Multiple
Multiple
Type of Access
External
Defined by CSCR
External, burst-inhibited, 32-bit
Defined by DACRs
Undefined
Undefined
Undefined
Undefined
Undefined
Basic operation of the MCF5271 bus is a three-clock bus cycle.
1. During the first clock, the address, attributes, and TS are driven.
2. Data and TA are sampled during the second clock of a bus-read cycle. During a read, the external device provides data and is sampled at the rising edge at the end of the second bus clock. This data is concurrent with TA, which is also sampled at the rising edge of the clock.
During a write, the ColdFire device drives data from the rising clock edge at the end of the first clock to the rising clock edge at the end of the bus cycle. Wait states can be added between the first and second clocks by delaying the assertion of TA. TA can be configured to be generated internally through the CSCRs. If TA is not generated internally, the system must provide it externally.
3. The last clock of the bus cycle uses what would be an idle clock between cycles to provide
hold time for address, attributes and write data. Figure 17-6 and
basic read and write operations.
17.5.2 Data Transfer Cycle States
The data transfer operation in the MCF5271 is controlled by an on-chip state machine. Each bus clock cycle is divided into two states. Even states occur when CLKOUT is high and odd states
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 17-5
External Interface Module (EIM) occur when CLKOUT is low. The state transition diagram for basic and fast termination read and write cycles are shown in
.
Next Cycle
S0
S5 S1
Basic
Read/Write
Fast
Termination
S4 S2
Wait
States
S3
Figure 17-4. Data Transfer State Transition Diagram
Table 17-4 describes the states as they appear in subsequent timing diagrams.
Table 17-4. Bus Cycle States
State
S0
S1
S2
S3
S4
All
Cycle
All
Fast
Termination
Low
Read/write
(skipped fast termination)
Write
High
CLKOUT
High
Description
The read or write cycle is initiated in S0. On the rising edge of CLKOUT, the
MCF5271 places a valid address on the address bus and drives R/W high for a read and low for a write, if it is not already in the appropriate state. The MCF5271 asserts TIP, TSIZ[1:0], and TS on the rising edge of CLKOUT.
The appropriate CSn, BSn, and OE signals assert on the CLKOUT falling edge.
TA must be asserted during S1. Data is made available by the external device and is sampled on the rising edge of CLKOUT with TA asserted.
TS is negated on the rising edge of CLKOUT in S2.
Read/write
(skipped for fast termination)
Read
Low
The data bus is driven out of high impedance as data is placed on the bus on the rising edge of CLKOUT.
The MCF5271 waits for TA assertion. If TA is not sampled as asserted before the rising edge of CLKOUT at the end of the first clock cycle, the MCF5271 inserts wait states (full clock cycles) until TA is sampled as asserted.
All
Read
(including fast-terminati on)
High
Data is made available by the external device on the falling edge of CLKOUT and is sampled on the rising edge of CLKOUT with TA asserted.
The external device should negate TA.
The external device can stop driving data after the rising edge of CLKOUT.
However data could be driven through the end of S5.
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17-6 Freescale Semiconductor
Data Transfer Operation
State
S5 S5
Cycle
Read
Write
Table 17-4. Bus Cycle States (Continued)
CLKOUT
Low
Description
CSn, BSn, and OE are negated on the CLKOUT falling edge of S5. The MCF5271 stops driving address lines and R/W on the rising edge of CLKOUT, terminating the read or write cycle. At the same time, the MCF5271 negates TIP, and TSIZ[1:0] on the rising edge of CLKOUT.
Note that the rising edge of CLKOUT may be the start of S0 for the next access cycle.
The external device stops driving data between S4 and S5.
The data bus returns to high impedance on the rising edge of CLKOUT. The rising edge of CLKOUT may be the start of S0 for the next access.
NOTE
An external device has at most two CLKOUT cycles after the start of
S4 to tristate the data bus. This applies to basic read cycles, fast termination cycles, and the last transfer of a burst.
17.5.3 Read Cycle
During a read cycle, the MCF5271 receives data from memory or from a peripheral device.
is a read cycle flowchart.
MCF5271 System
1.
Set R/W to read
2.
Place address on A[31:0]
3.
Assert TIP, and TSIZ[1:0]
4.
Assert TS
5.
Negate TS
1.
Decode address and select the appropriate slave device.
2.
Drive data on D[31:0]
3.
Assert TA
1.
Sample TA low and latch data
1.
Negate TA.
2.
Stop driving D[31:0]
1.
Start next cycle
Figure 17-5. Read Cycle Flowchart
The read cycle timing diagram is shown in
.
NOTE
In the following timing diagrams, TA waveforms apply for chip selects programmed to enable either internal or external termination.
TA assertion should look the same in either case.
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Freescale Semiconductor 17-7
External Interface Module (EIM)
S0 S1 S2 S3 S4 S5
CLKOUT
R/W
A[31:0], TSIZ[1:0]
TIP
TS
CSn, BSn, OE
D[31:0] Read
TA
Figure 17-6. Basic Read Bus Cycle
Note the following characteristics of a basic read:
• In S3, data is made available by the external device on the falling edge of CLKOUT and is sampled on the rising edge of CLKOUT with TA asserted.
• In S4, the external device can stop driving data after the rising edge of CLKOUT. However data could be driven up to S5.
• For a read cycle, the external device stops driving data between S4 and S5.
States are described in Table 17-4 .
17.5.4 Write Cycle
During a write cycle, the MCF5271 sends data to the memory or to a peripheral device. The write
cycle flowchart is shown in Figure 17-7 .
17-8
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
MCF5271
1.
Set R/W to write
2.
Place address on A[31:0]
3.
Assert TIP and TSIZ[1:0]
4.
Assert TS
5.
Place data on D[31:0]
6.
Negate TS
System
1.
Decode address
2.
Store data on D[31:0]
3.
Assert TA
1.
Sample TA low
2.
Stop driving data from D[31:0]
1.
Start next cycle
1.
Negate TA
Figure 17-7. Write Cycle Flowchart
The write cycle timing diagram is shown in Figure 17-8 .
S0 S1 S2
CLKOUT
A[31:0], TSIZ[1:0]
S3 S4 S5
R/W
TIP
TS
CSn, BSn
D[31:0]
TA
Write
Figure 17-8. Basic Write Bus Cycle
Table 17-4 describes the six states of a basic write cycle.
Data Transfer Operation
17.5.5 Fast Termination Cycles
Two clock cycle transfers are supported on the MCF5271 bus. In most cases, this is impractical to use in a system because the termination must take place in the same half-clock during which TS is asserted. As this is atypical, it is not referred to as the zero-wait-state case but is called the fast-termination case. Fast termination cycles occur when the external device or memory asserts
TA less than one clock after TS is asserted. This means that the MCF5271 samples TA on the rising
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 17-9
External Interface Module (EIM)
edge of the second cycle of the bus transfer. Figure 17-9 shows a read cycle with fast termination.
Note that fast termination cannot be used with internal termination.
S0 S1 S4 S5
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn, OE
D[31:0]
TA
Read
Figure 17-9. Read Cycle with Fast Termination
shows a write cycle with fast termination.
S0 S1 S4 S5
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn
D[31:0]
TA
Write
Figure 17-10. Write Cycle with Fast Termination
17.5.6 Back-to-Back Bus Cycles
The MCF5271 runs back-to-back bus cycles whenever possible. For example, when a longword read is started on a word-size bus, the processor performs two back-to-back word read accesses.
Back-to-back accesses are distinguished by the continuous assertion of TIP throughout the cycle.
shows a read back-to-back with a write.
MCF5271 Reference Manual, Rev. 2
17-10 Freescale Semiconductor
Data Transfer Operation
S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn
OE
D[31:0]
Read Write
TA
Figure 17-11. Back-to-Back Bus Cycles
Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to the type of operations to be placed back to back. The initiation of a back-to-back cycle is not user definable.
17.5.7 Burst Cycles
The MCF5271 can be programmed to initiate burst cycles if its transfer size exceeds the size of the port it is transferring to. For example, a word transfer to an 8-bit port would take a 2-byte burst cycle. A line transfer to a 32-bit port would take a 4-longword burst cycle.
The MCF5271 bus can support 2-1-1-1 burst cycles to maximize cache performance and optimize
DMA transfers. A user can add wait states by delaying termination of the cycle. The initiation of a burst cycle is encoded on the size pins. For burst transfers to smaller port sizes, TSIZ[1:0] indicates the size of the entire transfer. For example, if the MCF5271 writes a longword to an 8-bit port, TSIZ[1:0] = 00 for the first byte transfer and does not change.
The CSCRs can be used to enable bursting for reads, writes, or both. MCF5271 memory space can be declared burst-inhibited for reads and writes by clearing the appropriate
CSCRn[BSTR,BSTW]. A line access to a burst-inhibited region first accesses the MCF5271 bus encoded as a line access. The TSIZ[1:0] encoding does not exceed the programmed port size. The address changes if internal termination is used but does not change if external termination is used, as shown in
.
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Freescale Semiconductor 17-11
External Interface Module (EIM)
17.5.7.1 Line Transfers
A line is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not begin on the aligned address; therefore, the bus interface supports line transfers on multiple address
boundaries. Table 17-5 shows allowable patterns for line accesses.
Table 17-5. Allowable Line Access Patterns
A[3:2]
00
01
10
11
Longword Accesses
0–4–8–C
4–8–C–0
8–C–0–4
C–0–4–8
17.5.7.2 Line Read Bus Cycles
and
Figure 17-13 show a line access read with zero wait states. The access starts like
a basic read bus cycle with the first data transfer sampled on the rising edge of S4, but the next pipelined burst data is sampled a cycle later on the rising edge of S6. Each subsequent pipelined data burst is single cycle until the last one, which can be held for up to two CLKOUT cycles after
TA is asserted. Note that CSn is asserted throughout the burst transfer. This example shows the timing for external termination, which differs from the internal termination example in
only in that the address lines change only at the beginning (assertion of TS and TIP) and end (negation of TIP) of the transfer.
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn, OE
D[31:0] Read Read Read Read
TA
Figure 17-12. Line Read Burst (2-1-1-1), External Termination
shows timing when internal termination is used.
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17-12 Freescale Semiconductor
Data Transfer Operation
S0 S1 S2 S3 S4
S5
S6 S7 S8 S9 S10 S11 S12 S13
CLKOUT
A[31:0]
TSIZ[1:0]
R/W
TIP
TS
CSn, BSn, OE
D[31:0]
Read Read Read Read
TA
Figure 17-13. Line Read Burst (2-1-1-1), Internal Termination
shows a line access read with one wait state programmed in CSCRn to give the peripheral or memory more time to return read data. This figure follows the same execution as a zero-wait state read burst with the exception of an added wait state.
.
WS WS WS
S0 S1 S2 S3 S4 S5 S6 S7
WS
S8 S9 S10 S11 S20 S13
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn, OE
D[31:0]
Read Read Read Read
TA
Figure 17-14. Line Read Burst (3-2-2-2), External Termination
shows a burst-inhibited line read access with fast termination. The external device executes a basic read cycle while determining that a line is being transferred. The external device uses fast termination for subsequent transfers.
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Freescale Semiconductor 17-13
External Interface Module (EIM)
S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S6 S7
CLKOUT
A[31:0]
R/W
A[3:2] = 00 A[3:2] = 01 A[3:2] = 10 A[3:2] = 11
TIP
TSIZ[1:0]
TS
CSn, BSn, OE
D[31:0]
Line Longword
Read Read Read Read
TA
Basic Fast Fast Fast
Figure 17-15. Line Read Burst-Inhibited, Fast Termination, External Termination
17.5.7.3 Line Write Bus Cycles
shows a line access write with zero wait states. It begins like a basic write bus cycle with data driven one clock after TS. The next pipelined burst data is driven a cycle after the write data is registered (on the rising edge of S6). Each subsequent burst takes a single cycle. Note that
as with the line read example in Figure 17-12
, CSn remain asserted throughout the burst transfer.
This example shows the behavior of the address lines for both internal and external termination.
Note that when external termination is used, the address lines change with TSIZ[1:0].
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11
CLKOUT
A[31:0]
Internal Termination
A[31:0]
External Termination
TSIZ[1:0]
R/W, TIP
TS
CSn, OE, BSn
D[31:0] Write Write Write Write
TA
Figure 17-16. Line Write Burst (2-1-1-1), Internal/External Termination
MCF5271 Reference Manual, Rev. 2
17-14 Freescale Semiconductor
Secondary Wait State Operation
shows a line burst write with one wait-state insertion.
S0 S1 S2 S3 WS S4 S5 WS S6 S7 WS S8 S9 WS S10 S11
CLKOUT
A[31:0]
R/W, TIP
TSIZ[1:0]
TS
CSn, OE, BSn
D[31:0]
Write Write Write Write
TA
A[31:0]
R/W, TIP
Figure 17-17. Line Write Burst (3-2-2-2) with One Wait State
shows a burst-inhibited line write. The external device executes a basic write cycle while determining that a line is being transferred. The external device uses fast termination to end each subsequent transfer.
S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5
CLKOUT
A[3:2] = 00 A[3:2] = 01 A[3:2] = 10 A[3:2] = 11
TSIZ[1:0]
TS
CSn
OE, BSn
D[31:0]
TA
Line
Write Write
Longword
Write Write
Basic Fast Fast
Figure 17-18. Line Write Burst-Inhibited
Fast
17.6 Secondary Wait State Operation
Refer to Section 16.3.2, “Enhanced Wait State Operation,” for information and timing diagrams
of the secondary wait state operation.
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Freescale Semiconductor 17-15
External Interface Module (EIM)
17.7 Misaligned Operands
Because operands can reside at any byte boundary, unlike opcodes, they are allowed to be misaligned. A byte operand is properly aligned at any address, a word operand is misaligned at an odd address, and a longword is misaligned at an address not a multiple of four. Although the
MCF5271 enforces no alignment restrictions for data operands (including program counter (PC) relative data addressing), additional bus cycles are required for misaligned operands.
Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch a misaligned instruction word causes an address error exception.
The MCF5271 converts misaligned, cache-inhibited operand accesses to multiple aligned accesses.
shows the transfer of a longword operand from a byte address to a 32-bit port. In this example, TSIZ[1:0] specify a byte transfer and a byte offset of 0x1. The slave device supplies the byte and acknowledges the data transfer. When the MCF5271 starts the second cycle,
TSIZ[1:0] specify a word transfer with a byte offset of 0x2. The next two bytes are transferred in this cycle. In the third cycle, byte 3 is transferred. The byte offset is now 0x0, the port supplies the final byte, and the operation is complete.
Transfer 1
Transfer 2
31
—
—
24 23
Byte 0
—
16 15
—
Byte 1
8 7
—
Byte 2
0
A[2:0]
001
010
Transfer 3 Byte 3 — — — 100
Figure 17-19. Example of a Misaligned Longword Transfer (32-Bit Port)
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the cache. The example in
differs from that in
Figure 17-19 in that the operand
is word-sized and the transfer takes only two bus cycles.
Transfer 1
Transfer 2
31
—
Byte 1
24 23
—
—
16 15
—
—
8 7
Byte 0
—
0
A[2:0]
001
100
Figure 17-20. Example of a Misaligned Word Transfer (32-Bit Port)
17-16
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Freescale Semiconductor
Chapter 18
Synchronous DRAM Controller Module
18.1 Introduction
This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter describes the programming model and signal timing, as well as the command set required for synchronous operations. It also includes extensive examples that the designer can follow to better understand how to configure the
DRAM controller for synchronous operations.
NOTE
The timing diagrams within this chapter show 32 address lines,
A[31:0]. However, only the lowest 24 address signals are available externally on the MCF5271 device, A[23:0].
18.1.1 Block Diagram
The basic components of the SDRAM controller are shown in
.
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MCF5271 Reference Manual, Rev. 2
18-1
Synchronous DRAM Controller Module
DRAM Controller Module
D[31:0] internal
Q[31:0] internal
A[31:0]
Internal
Bus
Data
Generation
Address
Multiplexing
Control Logic and
State Machine
D[31:0]
Q[31:0]
A[23:0]
Memory Block 0 Hit Logic
DRAM Address/Control Register 0
(DACR0)
Memory Block 1 Hit Logic
DRAM Address/Control Register 1
(DACR1)
DRAM Control
Register (DCR)
Refresh Counter
SD_SCAS
SD_SRAS
SD_CKE
SD_CS[1:0]
SD_WE
BS[3:0]
OE
Figure 18-1. Synchronous DRAM Controller Block Diagram
The DRAM controller’s major components are as follows:
• DRAM address and control registers (DACR0 and DACR1): The DRAM controller consists of two configuration register units, one for each supported memory block. DACR0 is accessed at IPSBAR + 0x00_0048; DACR1 is accessed at IPSBAR + 0x00_0050. The register information is passed on to the hit logic.
• Control logic and state machine: Generates all SDRAM signals, taking hit information and bus-cycle characteristic data from the block logic in order to generate SDRAM accesses.
Handles refresh requests from the refresh counter.
— DRAM control register (DCR): Contains data to control refresh operation of the DRAM controller. Both memory blocks are refreshed concurrently as controlled by DCR[RC].
— Refresh counter: Determines when refresh should occur; controlled by the value of
DCR[RC]. It generates a refresh request to the control block.
• Hit logic: Compares address and attribute signals of a current SDRAM bus cycle to both
DACRs to determine if an SDRAM block is being accessed. Hits are passed to the control logic along with characteristics of the bus cycle to be generated.
• Address multiplexing: Multiplexes addresses to allow column and row addresses to share pins. This allows glueless interface to SDRAMs.
• Data Generation: Controls the data input and data output transmission between the on-platform and off-platform data buses.
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18-2 Freescale Semiconductor
Introduction
18.1.2 Overview
The synchronous DRAM controller module provides glueless integration of SDRAM with the
ColdFire product. The key features of the DRAM controller include the following:
• Support for two independent blocks of SDRAM
• Interface to standard SDRAM components
• Programmable SD_SRAS, SD_SCAS, and refresh timing
• Support for 8-, 16-, and 32-bit wide SDRAM blocks
18.1.2.1 Definitions
The following terminology is used in this chapter:
• SDRAM block: Any group of DRAM memories selected by one of the MCF5271
SD_SRAS[1:0] signals. Thus, the MCF5271 can support two independent memory blocks.
The base address of each block is programmed in the DRAM address and control registers
(DACR0 and DACR1).
• SDRAM: RAMs that operate like asynchronous DRAMs but with a synchronous clock, a pipelined, multiple-bank architecture, and a faster speed.
• SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit
SDRAM component might be configured as four 512K x 32 banks. Banks are selected through the SDRAM component’s bank select lines.
18.1.3 Operation
By running synchronously with the system clock, SDRAM can (after an initial latency period) be accessed on every clock; 5-1-1-1 is a typical MCF5271 burst rate to the SDRAM.
Note that because the MCF5271 cannot have more than one page open at a time, it does not support interleaving.
SDRAM controllers are more sophisticated than asynchronous DRAM controllers. Not only must they manage addresses and data, but they must send special commands for such functions as
precharge, read, write, burst, auto-refresh, and various combinations of these functions. Table 18-1
lists common SDRAM commands.
Table 18-1. SDRAM Commands
Command
ACTV
MRS
NOP
Definition
Activate. Executed before
READ
or
WRITE
executes; SDRAM registers and decodes row address.
Mode register set.
No-op. Does not affect SDRAM state machine; DRAM controller control signals negated; SD_CS[1:0] asserted.
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Synchronous DRAM Controller Module
Table 18-1. SDRAM Commands (Continued)
Command
PALL
READ
REF
SELF
SELFX
WRITE
Definition
Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is opened.
Read access. SDRAM registers column address and decodes that a read access is occurring.
Refresh. Refreshes internal bank rows of an SDRAM component.
Self refresh. Refreshes internal bank rows of an SDRAM component when it is in low-power mode.
Exit self refresh. This command is sent to the DRAM controller when DCR[IS] is cleared.
Write access. SDRAM registers column address and decodes that a write access is occurring.
SDRAMs operate differently than asynchronous DRAMs, particularly in the use of data pipelines and commands to initiate special actions. Commands are issued to memory using specific encodings on address and control pins. Soon after system reset, a command must be sent to the
SDRAM mode register to configure SDRAM operating parameters.
18.2 External Signal Description
Table 18-2 describes the behavior of DRAM signals in synchronous mode.
Table 18-2. Synchronous DRAM Signal Connections
Signal Description
SD_SRAS
SD_SCAS
SD_WE
SD_CS[1:0]
SD_CKE
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS.
Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SD_SCAS should be connected to the corresponding SDRAM SD_SCAS.
SDRAM read/write. Asserted for write operations and negated for read operations.
Select each memory block of SDRAMs connected to the MCF5271. One SD_CS signal selects one SDRAM block and connects to the corresponding CS signals.
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is deasserted, memory can enter a power-down mode in which operations are suspended or capable of entering self-refresh mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SD_CKE to provide command-bit functionality.
BS[3:0] BS[3:0] function as byte enables to the SDRAMs. They connect to the BS signals (or mask qualifiers) of the SDRAMs.
OE Output Enable for SDRAM write data. During a write to the SDRAM, OE will be asserted during the time that data is valid. This signal could be used to control the three-stating and activation of the on-chip I/O buffers that are connected to the SDRAM data (Q) lines. This signal is low during
SDRAM reads. Do not confuse this signal with BS.
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18-4 Freescale Semiconductor
18.3 Memory Map/Register Definition
The DRAM controller registers memory map is shown in
.
Table 18-3. DRAM Controller Registers
IPSBAR
Offset
0x00_0040
0x00_0044
0x00_0048
0x00_004C
0x00_0050
0x00_0054
[31:24] [23:16] [15:8]
DRAM control register (DCR) —
—
DRAM address and control register 0 (DACR0)
DRAM mask register block 0 (DMR0)
DRAM address and control register 1 (DACR1)
DRAM mask register block 1 (DMR1)
Memory Map/Register Definition
[7:0]
18.3.1 DRAM Control Register (DCR)
The DCR, shown in
, controls refresh logic.
15
R 0
W
Reset 0
Address
Bits
15–14
13
14 13 12 11
0 NAM COC IS
10
RTIM
9 8 7 6 5 4
RC
3 2 1 0
0
Name
—
NAM
— — — — — — — — — —
IPSBAR + 0x00_0040
Figure 18-2. DRAM Control Register (DCR)
Table 18-4. DCR Field Descriptions
— — — —
Description
Reserved, should be cleared.
No address multiplexing. Some implementations require external multiplexing. For example, when linear addressing is required, the SDRAM should not multiplex addresses on SDRAM accesses.
0 The SDRAM controller multiplexes the external address bus to provide column addresses.
1 The SDRAM controller does not multiplex the external address bus to provide column addresses.
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18-5
Synchronous DRAM Controller Module
Bits
12
11
10–9
8–0
Name
COC
IS
RTIM
RC
Table 18-4. DCR Field Descriptions (Continued)
Description
Command on SDRAM clock enable (SD_CKE). Implementations that use external multiplexing (NAM = 1) must support command information to be multiplexed onto the
SDRAM address bus.
0 SD_CKE functions as a clock enable; self-refresh is initiated by the SDRAM controller through DCR[IS].
1 SD_CKE drives command information. Because SD_CKE is not a clock enable, self-refresh cannot be used (setting DCR[IS]). Thus, external logic must be used if this functionality is desired. External multiplexing is also responsible for putting the command information on the proper address bit.
Initiate self-refresh command.
0 Take no action or issue a SELFX command to exit self refresh.
1 If DCR[COC] = 0, the SDRAM controller sends a
SELF
command to both SDRAM blocks to put them in low-power, self-refresh state where they remain until IS is cleared. When
IS is cleared, the controller sends a
SELFX
command for the SDRAMs to exit self-refresh.
The refresh counter is suspended while the SDRAMs are in self-refresh; the SDRAM controls the refresh period.
Refresh timing. Determines the timing operation of auto-refresh in the SDRAM controller.
Specifically, it determines the number of bus clocks inserted between a REF command and the next possible
ACTV
command. This same timing is used for both memory blocks controlled by the SDRAM controller. This corresponds to t
RC
00 3 clocks
in the SDRAM specifications.
01 6 clocks
1x 9 clocks
Refresh count. Controls refresh frequency. The number of bus clocks between refresh cycles is (RC + 1) x 16. Refresh can range from 16–8192 bus clocks to accommodate both standard and low-power SDRAMs with bus clock operation from less than 2 MHz to greater than 50 MHz.
The following example calculates RC for an auto-refresh period for 4096 rows to receive
64 ms of refresh every 15.625 µs for each row (1172 bus clocks at 75 MHz). This operation is the same as in asynchronous mode.
# of bus clocks = 1172 = (RC field + 1) x 16
RC = (1172 bus clocks/16) -1 = 72.25, which rounds to 72; therefore, RC = 0x48.
18.3.2 DRAM Address and Control Registers (DACR0/DACR1)
The DACRn registers, shown in
, contain the base address compare value and the control bits for memory blocks 0 and 1 of the SDRAM controller. Address and timing are also controlled by bits in DACRn.
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Freescale Semiconductor
Memory Map/Register Definition
31
R
W
Reset —
30
—
29
—
28
—
27
—
26
—
25
BA
24
— —
23
—
22
—
21
—
20
—
19
—
18
—
15
R RE
W
Reset 0
Address
14
0
13
CASL
12 11
0
10 9
CBM
8 7 6
0 IMRS
5
PS
4 3
IP
0 — — 0 — — — 0 0 — — — 0
IPSBAR+0x00_0048 (DACR0); 0x00_0050 (DACR1)
Figure 18-3. DRAM Address and Control Registers (DACRn)
2
0
Table 18-5. DACRn Field Descriptions
Bits
31–18
17–16
15
14
13–12
Name
BA
—
RE
—
CASL
17
0
0
1
0
0
0
0
0
16
0
0
Description
Base address register. With DCMR[BAM], determines the address range in which the associated DRAM block is located. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match, the address hits in the associated DRAM block. BA functions the same as in asynchronous operation.
Reserved, should be cleared.
Refresh enable. Determines when the DRAM controller generates a refresh cycle to the
DRAM block.
0 Do not refresh associated DRAM block
1 Refresh associated DRAM block
Reserved, should be cleared.
CAS latency. Affects the following SDRAM timing specifications. Timing nomenclature varies with manufacturers. Refer to the SDRAM specification for the appropriate timing nomenclature:
Number of Bus Clocks
Parameter
CASL=
00
1
CASL =
01
2
CASL=
10
3
CASL=
11
3 t
RCD
—SD_SRAS assertion to SD_SCAS assertion t
CASL
—SD_SCAS assertion to data out t
RAS
— ACTV command to precharge command t
RP
—Precharge command to ACTV command t
RWL , t
RDL
—Last data input to precharge command t
EP
—Last data out to precharge command
1
2
1
1
1
2
4
2
1
1
3
6
3
1
1
3
6
3
1
1
11 — Reserved, should be cleared.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 18-7
Synchronous DRAM Controller Module
Bits
10–8
Name
CBM
Table 18-5. DACRn Field Descriptions (Continued)
Description
Command and bank MUX [2:0]. Because different SDRAM configurations cause the command and bank select lines to correspond to different addresses, these resources are programmable. CBM determines the addresses onto which these functions are multiplexed.
7
6
5–4
3
2–0
—
IMRS
PS
IP
—
CBM Command Bit Bank Select Bits
000
001
010
011
17
18
19
20
18 and up
19 and up
20 and up
21 and up
100
101
21
22
22 and up
23 and up
110 23 24 and up
111 24 25 and up
This encoding and the address multiplexing scheme handle common SDRAM organizations.
Bank select bits include a base bit and all address bits above for SDRAMs with multiple bank select bits.
Reserved, should be cleared.
Initiate mode register set (
MRS
) command. Setting IMRS generates a
MRS
command to the associated SDRAMs. In initialization, IMRS should be set only after all DRAM controller registers are initialized and
PALL
and
REFRESH
commands have been issued. After IMRS is set, the next access to an SDRAM block programs the SDRAM’s mode register. Thus, the address of the access should be programmed to place the correct mode information on the SDRAM address pins. Because the SDRAM does not register this information, it doesn’t matter if the
IMRS access is a read or a write or what, if any, data is put onto the data bus. The DRAM controller clears IMRS after the MRS command finishes.
0 Take no action
1 Initiate MRS command
Port size. Indicates the port size of the associated block of SDRAM, which allows for dynamic sizing of associated SDRAM accesses. PS functions the same in asynchronous operation.
00 32-bit port
01 8-bit port
1x 16-bit port
Initiate precharge all ( PALL ) command. The DRAM controller clears IP after the PALL command is finished. Accesses via IP should be no wider than the port size programmed in PS.
0 Take no action.
1 A
PALL
command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the
PALL
command to the
SDRAM block.
Reserved, should be cleared.
MCF5271 Reference Manual, Rev. 2
18-8 Freescale Semiconductor
Memory Map/Register Definition
18.3.3 DRAM Controller Mask Registers (DMR0/DMR1)
, includes mask bits for the base address and for address attributes.
31
R
W
Reset —
15
R 0
W
Reset 0
Address
Bits
31–18
17–9
8
7-1
0
30
—
14
0
29
—
13
0
28
—
12
0
27
—
11
0
26
—
10
0
25
BAM
24
—
9
0
—
8
WP
23
—
7
0
22
—
6
0
21
—
5
0
20
—
4
0
19
—
3
0
18
—
2
0
0
1
0
17
0
16
0
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_004C (DMR0); 0x00_0054 (DMR1)
Figure 18-4. DRAM Controller Mask Registers (DMRn)
0
Name
BAM
—
WP
—
V
0 0
Table 18-6. DMRn Field Descriptions
Description
Base address mask. Masks the associated DACRn[BA]. Lets the DRAM controller connect to various DRAM sizes. Mask bits need not be contiguous (see
0 The associated address bit is used in decoding the DRAM hit to a memory block.
1 The associated address bit is not used in the DRAM hit decode.
Reserved, should be cleared.
Write protect. Determines whether the associated block of DRAM is write protected.
0 Allow write accesses
1 Prohibit write accesses. The DRAM controller deasserts the external DRAMW (Write
Enable) signal and an access error exception occurs.
Reserved, should be cleared.
Valid. Cleared at reset to ensure that the DRAM block is not erroneously decoded.
0 Do not decode DRAM accesses.
1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded.
0
0
V
18.3.4 General Synchronous Operation Guidelines
To reduce system logic and to support a variety of SDRAM sizes, the DRAM controller provides
SDRAM control signals as well as a multiplexed row address and column address to the SDRAM.
18.3.4.1 Address Multiplexing
Table 18-7 shows the generic address multiplexing scheme for SDRAM configurations. All
possible address connection configurations can be derived from this table.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 18-9
Synchronous DRAM Controller Module
NOTE
Because the device has 24 external address lines, the maximum
SDRAM address size is 128 Mbits.
The following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the MCF5271 to the SDRAM. To use the tables, find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the MCF5271, which is not necessarily the SDRAM port size. For example, if two
1M x 16-bit SDRAMs together form a 1M x 32-bit memory, the port size is 32 bits. Most
SDRAMs likely have fewer address lines than are shown in the tables, so follow only the connections shown until all SDRAM address lines are connected.
Table 18-7. Generic Address Multiplexing Scheme
Address Pin Row Address Column Address
20
21
22
23
9
17
18
19
24
25
13
12
11
10
17
16
15
14
17
16
15
14
13
12
11
10
20
21
22
23
9
17
18
19
24
25
6
7
4
5
8
2
3
0
1
17
18
19
20
21
22
23
24
Notes Relating to Port Sizes
8-bit port only
8- and 16-bit ports only
16-bit port only or 32-bit port with only 8 column address lines
16-bit port only when at least 9 column address lines are used
18-10
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
V
Memory Map/Register Definition
Table 18-8. MCF5271 to SDRAM Interface (8-Bit Port, 9-Column Address Lines)
MCF5271
Pins
A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23
Row 17 16 15 14 13 12 11 10 9 18 19 20 21 22 23
Column 0 1 2 3 4 5 6 7 8
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
Table 18-9. MCF5271 to SDRAM Interface (8-Bit Port,10-Column Address Lines)
MCF5271 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A20 A21 A22 A23
Pins
Row 17 16 15 14 13 12 11 10 9 19 20 21 22 23
Column 0 1 2 3 4 5 6 7 8 18
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Table 18-10. MCF5271 to SDRAM Interface (8-Bit Port,11-Column Address Lines)
MCF5271
Pins
A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23
Row 17 16 15 14 13 12 11 10 9 19 21 22 23
Column 0 1 2 3 4 5 6 7 8 18 20
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Table 18-11. MCF5271 to SDRAM Interface (8-Bit Port,12-Column Address Lines)
MCF5271
Pins
A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23
Row 17 16 15 14 13 12 11 10 9 19 21 23
Column 0 1 2 3 4 5 6 7 8 18 20 22
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Table 18-12. MCF5271 to SDRAM Interface (8-Bit Port,13-Column Address Lines)
MCF5271
Pins
A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23
Row 17 16 15 14 13 12 11 10 9 19 21 23
Column 0 1 2 3 4 5 6 7 8 18 20 22
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 18-11
Synchronous DRAM Controller Module
Table 18-13. MCF5271 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)
MCF5271
Pins
A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
Row 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23
Column 1 2 3 4 5 6 7 8
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
Table 18-14. MCF5271 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)
MCF5271
Pins
A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23
Row 16 15 14 13 12 11 10 9 18 19 20 21 22 23
Column 1 2 3 4 5 6 7 8 17
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Table 18-15. MCF5271 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)
MCF5271
Pins
A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23
Row 16 15 14 13 12 11 10 9 18 20 21 22 23
Column 1 2 3 4 5 6 7 8 17 19
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Table 18-16. MCF5271 to SDRAM Interface (16-Bit Port, 11-Column Address Lines)
MCF5271
Pins
A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23
Row 16 15 14 13 12 11 10 9 18 20 22 23
Column 1 2 3 4 5 6 7 8 17 19 21
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Table 18-17. MCF5271 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)
MCF5271
Pins
A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22
Row 16 15 14 13 12 11 10 9 18 20 22
Column 1 2 3 4 5 6 7 8 17 19 21
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
MCF5271 Reference Manual, Rev. 2
18-12 Freescale Semiconductor
Memory Map/Register Definition
Table 18-18. MCF5271 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)
MCF5271
Pins
A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22
Row
Column
SDRAM
Pins
16
1
A0
15
2
A1
14
3
A2
13
4
A3
12
5
A4
11
6
A5
10
7
A6
9
8
A7
18
17
A8
20
19
A9
22
21
A10
Table 18-19. MCF5271 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)
MCF5271
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
Row 15 14 13 12 11 10 9 17 18 19 20 21 22 23
Column 2 3 4 5 6 7 8 16
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Table 18-20. MCF5271 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)
MCF5271
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23
Row 15 14 13 12 11 10 9 17 19 20 21 22 23
Column 2 3 4 5 6 7 8 16 18
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Table 18-21. MCF5271 to SDRAM Interface (32-Bit Port, 10-Column Address Lines)
MCF5271
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23
Row 15 14 13 12 11 10 9 17 19 21 22 23
Column 2 3 4 5 6 7 8 16 18 20
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Table 18-22. MCF5271 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
MCF5271
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23
Row
Column
SDRAM
Pins
15
2
A0
14
3
A1
13
4
A2
12
5
A3
11
6
A4
10
7
A5
9
8
A6
17
16
A7
19
18
A8
21
20
23
22
A9 A10
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 18-13
Synchronous DRAM Controller Module
Table 18-23. MCF5271 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
MCF5271
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23
Row
Column
SDRAM
Pins
15
2
A0
14
3
A1
13
4
A2
12
5
A3
11
6
A4
10
7
A5
9
8
A6
17
16
A7
19
18
A8
21
20
A9
23
22
A10
shows the SDRAM connections for port sizes of 32, 16 or 8 bits.
Byte Enable
Processor
External
Data Bus
32-Bit Port
Memory
16-Bit Port
Memory
BS3
D[31:24]
BS2
D[23:16]
BS1
D[15:8]
Byte 0
Byte 0
Byte 2
Byte 1
Byte 1
Byte 3
Byte 2
BS0
D[7:0]
Byte 3
Driven with indeterminate values
8-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 3
Driven with indeterminate values
Figure 18-5. SDRAM connections for port sizes of 32, 16, or 8 bits
18.3.4.2 Interfacing Example
The tables in the previous section can be used to configure the interface in the following example.
To interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the MCF5271, the connections shown in
Table 18-24. SDRAM Hardware Connections
SDRAM
Pins
MCF5271
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A15 A14 A13 A12 A11 A10 A9 A17 A18 A19
A10 = CMD BA0 BA1
A20 A21 A22
18.3.4.3 Burst Page Mode
SDRAM can efficiently provide data when an SDRAM page is opened. As soon as SD_SCAS is issued, the SDRAM accepts a new address and asserts SD_SCAS every CLKOUT for as long as accesses occur in that page. In burst page mode, there are multiple read or write operations for every
ACTV
command in the SDRAM if the requested transfer size exceeds the port size of the
MCF5271 Reference Manual, Rev. 2
18-14 Freescale Semiconductor
Memory Map/Register Definition associated SDRAM. The primary cycle of the transfer generates the ACTV and READ or WRITE commands; secondary cycles generate only READ or WRITE commands. As soon as the transfer completes, the PALL command is generated to prepare for the next access.
Note that in synchronous operation, burst mode and address incrementing during burst cycles are controlled by the MCF5271 DRAM controller. Thus, instead of the SDRAM enabling its internal burst incrementing capability, the MCF5271 controls this function. This means that the burst function that is enabled in the mode register of SDRAMs must be disabled when interfacing to the
MCF5271.
shows a burst read operation. In this example, DACR[CASL] = 01 for an
SD_SRAS-to-SD_SCAS delay (t
RCD
) of 2 system clock cycles. Because t
RCD is equal to the read
CAS latency (SD_SCAS assertion to data out), this value is also 2 system clock cycles. Notice that
NOP s are executed until the last data is read. A
PALL
command is executed one cycle after the last data transfer.
SYSCLK
Row Column Column Column Column A[31:0]
SD_SRAS t
RCD
= 2
SD_SCAS t
EP
SD_WE
D[31:0]
SD_CS[0] or [1]
BS[3:0] t
CASL
= 2
ACTV NOP READ READ READ READ NOP
Figure 18-6. Burst Read SDRAM Access
NOP PALL
shows the burst write operation. In this example, DACR[CASL] = 01, which creates an SD_SRAS-to-SD_SCAS delay (t
RCD
) of 2 system clock cycles. Note that data is available upon
SD_SCAS assertion and a burst write cycle completes two cycles sooner than a burst read cycle with the same t
RCD.
The next bus cycle is initiated sooner, but cannot begin an SDRAM cycle until the precharge-toACTV delay completes.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 18-15
Synchronous DRAM Controller Module
SYSCLK
A[31:0]
SRAS
SCAS
Row t
CASL
= 2
DRAMW
D[31:0]
SDRAM_CS[0] or [1]
OE
DQM[3:0]
Column Column Column t
RWL
Column
ACTV NOP WRITE WRITE WRITE WRITE NOP
Figure 18-7. Burst Write SDRAM Access
PALL t
RP
Accesses in synchronous burst page mode always cause the following sequence:
1.
ACTV
command
2.
NOP commands to assure SD_SRAS-to-SD_SCAS delay (if CAS latency is 1, there are no
NOP
commands).
3. Required number of READ or WRITE commands to service the transfer size with the given port size.
4. Some transfers need more NOP commands to assure the ACTV -to-precharge delay.
5.
PALL
command
6. Required number of idle clocks inserted to assure precharge-toACTV delay.
18.3.4.4 Auto-Refresh Operation
The DRAM controller is equipped with a refresh counter and control. This logic is responsible for providing timing and control to refresh the SDRAM without user interaction. Once the refresh counter is set, and refresh is enabled, the counter counts to zero. At this time, an internal refresh
MCF5271 Reference Manual, Rev. 2
18-16 Freescale Semiconductor
Memory Map/Register Definition request flag is set and the counter begins counting down again. The DRAM controller completes any active burst operation and then performs a PALL operation. The DRAM controller then initiates a refresh cycle and clears the refresh request flag. This refresh cycle includes a delay from any precharge to the auto-refresh command, the auto-refresh command, and then a delay until any
ACTV command is allowed. Any SDRAM access initiated during the auto-refresh cycle is delayed until the cycle is completed.
shows the auto-refresh timing. In this case, there is an SDRAM access when the refresh request becomes active. The request is delayed by the precharge to
ACTV
delay programmed into the active SDRAM bank by the CAS bits. The REF command is then generated and the delay required by DCR[RTIM] is inserted before the next
ACTV
command is generated. In this example, the next bus cycle is initiated, but does not generate an SDRAM access until T
RC
is finished. Because both chip selects are active during the
REF
command, it is passed to both blocks of external SDRAM.
CLKOUT
A[31:0]
SD_SRAS
SD_SCAS
SD_WE t
RCD
= 2 t
RC
= 6
SD_CS[0] or [1]
PALL REF
Figure 18-8. Auto-Refresh Operation
ACTV
18.3.4.5 Self-Refresh Operation
Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at the same time to perform an internal refresh operation and to maintain the integrity of the data stored in the
SDRAM. The DRAM controller supports self-refresh with DCR[IS]. When IS is set, the SELF command is sent to the SDRAM. When IS is cleared, the
SELFX
command is sent to the DRAM
controller. Figure 18-9 shows the self-refresh operation.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
18-17
Synchronous DRAM Controller Module
CLKOUT
SD_SRAS
SD_SCAS
SD_WE
SD_CS[0] or [1] t
RCD
= 2 t
RC
= 6
SD_CKE
(DCR[COC] = 0)
PALL SELF SELFX
Self-
Refresh
Active
Figure 18-9. Self-Refresh Operation
First
Possible
ACTV
18.3.5 Initialization Sequence
Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller supports this sequence with the following procedure:
1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before any action is taken on the SDRAMs. This is normally around 100 µs.
2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet enable
PALL
or
REF
commands.
3. Issue a PALL command to the SDRAMs by setting DACR[IP] and accessing a SDRAM location. Wait the time (determined by t
RP
) before any other execution.
4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur.
5. Before issuing the
MRS
command, determine if the DMR mask bits need to be modified to allow the MRS to execute properly
6. Issue the
MRS
command by setting DACR[IMRS] and accessing a location in the
SDRAM. Note that mode register settings are driven on the SDRAM address bus, so care must be taken to change DMR[BAM] if the mode register configuration does not fall in the address range determined by the address mask bits. After the mode register is set,
DMR mask bits can be restored to their desired configuration.
MCF5271 Reference Manual, Rev. 2
18-18 Freescale Semiconductor
Memory Map/Register Definition
18.3.5.1 Mode Register Settings
It is possible to configure the operation of SDRAMs, namely their burst operation and SD_SCAS latency, through the SDRAM component’s mode register. SD_SCAS latency is a function of the speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller operates at a SD_SCAS latency of 1, 2, or 3.
Although the MCF5271 DRAM controller supports bursting operations, it does not use the bursting features of the SDRAMs. Because the MCF5271 can burst operand sizes of 1, 2, 4, or 16 bytes long, the concept of a fixed burst length in the SDRAMs mode register becomes problematic.
Therefore, the MCF5271 DRAM controller generates the burst cycles rather than the SDRAM device. Because the MCF5271 generates a new address and a
READ
or
WRITE
command for each transfer within the burst, the SDRAM mode register should be set either not to burst or to a burst length of one. This allows bursting to be controlled by the MCF5271.
The SDRAM mode register is written by setting the associated block’s DACR[IMRS]. First, the base address and mask registers must be set to the appropriate configuration to allow the mode register to be set. Note that improperly set DMR mask bits may prevent access to the mode register address. Thus, the user should determine the mapping of the mode register address to the
MCF5271 address bits to find out if an access is blocked. If the DMR setting prohibits mode register access, the DMR should be reconfigured to enable the access and then set to its necessary configuration after the MRS command executes.
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to the SDRAM address space generates the MRS command to that SDRAM. The address of the access should be selected to place the correct mode information on the SDRAM address pins. The address is not multiplexed for the MRS command. The MRS access can be a read or write. The important thing is that the address output of that access needs the correct mode programming information on the correct address bits.
shows the
MRS
command, which occurs in the first clock of the bus cycle.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
18-19
Synchronous DRAM Controller Module
CLKOUT
A[31:0]
SD_SRAS,
SD_SCAS
SD_WE
D[31:0]
SD_CS[1] or [0]
MRS
Figure 18-10. Mode Register Set ( MRS ) Command
18.4 SDRAM Example
This example interfaces a 512K x 32-bit x 4 bank SDRAM component to a MCF5271 operating at 40 MHz bus speed (80 MHz core).
lists design specifications for this example.
Table 18-25. SDRAM Example Specifications
Parameter
Speed grade (-8E)
10 rows, 8 columns
Two bank-select lines to access four internal banks
ACTV -to-read/write delay (t
RCD
)
Period between auto-refresh and ACTV command (t
RC
ACTV command to precharge command (t
RAS
)
Precharge command to ACTV command (t
RP
)
Last data input to PALL command (t
RWL
)
Auto-refresh period for 4096 rows (t
REF
)
Specification
40 MHz (25-ns period)
20 ns (min.)
48 ns (min.)
20 ns (min.)
1 bus clock (25 ns)
64 mS
18.4.1 SDRAM Interface Configuration
To interface this component to the MCF5271 DRAM controller, use the connection table that
corresponds to a 32-bit port size with 8 columns ( Table 18-24
). Two pins select one of four banks
when the part is functional. Table 18-26 shows the proper hardware connections.
MCF5271 Reference Manual, Rev. 2
18-20 Freescale Semiconductor
SDRAM Example
MCF5271
Pins
SDRAM
Pins
A15
A0
Table 18-26. SDRAM Hardware Connections
A14 A13 A12 A11 A10 A9 A17 A18 A19 A20
A1 A2 A3 A4 A5 A6 A7 A8 A9
A21 A22
A10 = CMD BA0 BA1
18.4.2 DCR Initialization
At power-up, the DCR has the following configuration if synchronous operation and SDRAM address multiplexing are desired.
15
Field —
Setting 0
(hex)
14 13 12 11
— NAM COC IS
0 0 0 0
10
RTIM
9
0 0
8 7 6 5 4
RC
0 0 0 0 1
0026
Figure 18-11. Initialization Values for DCR
3
0
2
1
This configuration results in a value of 0x0026 for DCR, as shown in Table 18-27 .
Table 18-27. DCR Initialization Values
1
1
0
0
Bits Name Setting
15–1
4
13
12
11
10–9
8–0
—
NAM
COC
IS
RTIM
RC
00
0
0
Reserved.
Description
Indicating SDRAM controller multiplexes address lines internally
SD_CKE is used as clock enable instead of command bit because user is not multiplexing address lines externally and requires external command feed.
0 At power-up, allowing power self-refresh state is not appropriate because registers are being set up.
00 Because t
RC
value is 70 ns, indicating a 3-clock refresh-toACTV timing.
0x26 Specification indicates auto-refresh period for 4096 rows to be 64 mS or refresh every 15.625
µs for each row, or 625 bus clocks at 40 MHz. Because DCR[RC] is incremented by 1 and multiplied by 16, RC = (625 bus clocks/16) -1 = 38.06 = 0x38
18.4.3 DACR Initialization
As shown in
, the SDRAM is programmed to access only the second 512-Kbyte block of each 1-Mbyte partition in the SDRAM (each 16 Mbytes). The starting address of the SDRAM is 0xFF88_0000. Continuous page mode feature is used.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 18-21
Synchronous DRAM Controller Module
Bank 0
SDRAM Component
Bank 1 Bank 2
Accessible
Memory
Bank 3
1 Mbyte
512 Kbyte
1 Mbyte
512 Kbyte
1 Mbyte
512 Kbyte
1 Mbyte
512 Kbyte
512 Kbyte 512 Kbyte 512 Kbyte
Figure 18-12. SDRAM Configuration
The DACRs should be programmed as shown in
.
512 Kbyte
31
Field
Setting 1
(hex)
17–16
15
14
13–12
11
10–8
7
6
30
1
F
29
—
RE
1
—
CASL
—
CBM
—
IMRS
28
1
27
1
26
1
F
25
BA
24
1 1
23
1
22
0
8
21
0
20
0
19
1
18
0
8
17
—
0
16
—
0
15 14
Field RE —
Setting
(hex)
0 0
0
13
CASL
12
0 0
11
—
0
10
0
3
9
CBM
1
8
1
7 6
— IMRS
0 0
0
5
0
PS
4
0
Figure 18-13. DACR Register Configuration
3
IP
0
2
—
0
0
1
—
0
0
—
0
This configuration results in a value of DACR0 = 0xFF88_0300, as described in
.
DACR1 initialization is not needed because there is only one block. Subsequently,
DACR1[RE,IMRS,IP] should be cleared; everything else is a don’t care.
Table 18-28. DACR Initialization Values
Bits
31–18
Name
BA
Setting Description
1111_1111_
1000_10
Base address. So DACR0[31–16] = 0xFF88, placing the starting address of the SDRAM accessible memory at 0xFF88_0000.
00
0
Reserved.
Keeps auto-refresh disabled because registers are being set up at this time.
0
00
0
011
0
0
Reserved.
Indicates a delay of data 1 cycle after SD_SCAS is asserted
Reserved.
Command bit is pin 20 and bank selects are 21 and up.
Reserved.
Indicates
MRS
command has not been initiated.
MCF5271 Reference Manual, Rev. 2
18-22 Freescale Semiconductor
SDRAM Example
Bits
5–4
3
2–0
Table 18-28. DACR Initialization Values (Continued)
Name
PS
IP
—
Setting
00
0
000
Description
32-bit port.
Indicates precharge has not been initiated.
Reserved.
18.4.4 DMR Initialization
Again, in this example only the second 512-Kbyte block of each 1-Mbyte space is accessed in each bank. In addition, the SDRAM component is mapped only to readable and writable supervisor and user data. The DMRs have the following configuration.
31
Field
Setting 0
(hex)
30
0
0
29
0
28
0
27
0
26
0
0
25
BAM
24
0 0
23
0
22
1
7
21
1
20
1
19
0
18
1
4
15
Field —
Setting 0
(hex)
14
—
0
0
13
—
0
12
—
0
11
—
0
10
—
0
9 8 7
— WP —
0 0 0
6
—
0
0 0
Figure 18-14. DMR0 Register
5
—
0
4
—
0
3
—
0
With this configuration, the DMR0 = 0x0074_0001, as described in
.
Table 18-29. DMR0 Initialization Values
2
—
0
1
1
—
0
17
—
0
Bits Name
31–18 BAM
17–16
15–9
8
7-1
0
—
—
WP
—
V
0
V
1
16
—
0
Setting Description
With bits 17 and 16 as don’t cares, BAM = 0x0074, which leaves bank select bits and upper 512K select bits unmasked. Note that bits 22 and 21 are set because they are used as bank selects; bit 20 is set because it controls the 1-Mbyte boundary address.
00 Reserved.
0000_000 Reserved.
0 Allow reads and writes
0000_000 Reserved.
1 Enable accesses.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
18-23
Synchronous DRAM Controller Module
18.4.5 Mode Register Initialization
When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding
MCF5271 address pins must be determined while being aware of masking requirements.
lists the desired initialization setting:
Table 18-30. Mode Register Initialization
MCF5271 Pins
A9
A10
A11
A12
A20
A19
A18
A17
A13
A14
A15
SDRAM Pins
A6
A5
A4
A3
A10
A9
A8
A7
A2
A1
A0
Mode Register Initialization
Reserved
WB
Opmode
Opmode
CASL
CASL
CASL
BT
BL
BL
BL
1
0
0
0
0
0
X
0
0
0
0
Next, this information is mapped to an address to determine the hexadecimal value.
31
Field
Setting x
(hex)
30 x
0
29 x
28 x
27 x
26 x
0
25 x
24 x
23 x
22 x
0
21 x
20 x
19
0
18
0
0
17
0
16 x
15
Field
Setting 0
(hex)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V x 0 0 0 1 0 0 x x x x x x
0 8 0
Table 18-31. Mode Register Mapping to MCF5271 A[31:0] x
0 x
Although A[31:20] corresponds to the address programmed in DACR0, according to how DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before the mode register bit is set, DMR0[19] must be set to enable masking.
MCF5271 Reference Manual, Rev. 2
18-24 Freescale Semiconductor
SDRAM Example
18.4.6 Initialization Code
The following assembly code initializes the SDRAM example.
Power-Up Sequence:
//Initialize DCR move.w #0x0026, d0 move.w d0, DCR move.l #0xFF880300, d0 move.l d0, DACR0 move.l #0x00740001, d0 move.l d0, DMR0
Precharge Sequence:
//Initialize DACR0
//Initialize DMR0 move.l #0xFF880308, d0 move.l d0, DACR0
//Set DACR0[IP]
//Write and value to memory location to init.
precharge move.l d0, 0xFF880000
Refresh Sequence: move.l #0xFF888300, d0 move.l d0, DACR0
//Enable refresh bit in DACR0
Mode Register Initialization Sequence: move.l #0x00600001, d0 move.l #0xFF888340, d0 move.l d0, DACR0 move.l #0x00000000, d0 move.l d0, 0xFF800800
//Initialize DMR0 move.ld0, DMR0
//Enable DACR0[IMRS]; DACR0[RE] remains set
//Access SDRAM address to initialize mode register
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
18-25
Synchronous DRAM Controller Module
18-26
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Chapter 19
Fast Ethernet Controller (FEC)
19.1 Introduction
This chapter provides a feature-set overview, a functional block diagram, and transceiver connection information for both the 10 and 100 Mbps MII (Media Independent Interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included.
19.1.1 Overview
The Ethernet Media Access Controller (MAC) is designed to support both 10 and 100 Mbps
Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports three different standard
MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and the 10 Mbps-only 7-wire interface, which uses a subset of the
MII pins.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module” ) prior to configuring the FEC.
19.1.2 Block Diagram
The block diagram of the FEC is shown below. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE
802.3 standards.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
19-1
Fast Ethernet Controller (FEC)
SIF
Bus
Controller
Descriptor
Controller
(RISC + microcode)
CSR RAM
RAM I/F
FIFO
Controller
DMA
FEC Bus
MIB
Counters
Transmit Receive
MII
MDO
MDEN
MDI
I/O
PAD
ETXEN
ETXD[3:0]
ETXER
ETCLK
ECRS,ECOL
ERXCLK
ERXDV
ERXD[3:0]
ERXER
EMDIO EMDC
MII/7-WIRE DATA
OPTION
Figure 19-1. FEC Block Diagram
The descriptor controller is a RISC-based controller that provides the following functions in the
FEC:
• Initialization (those internal registers not initialized by the user or hardware)
• High level control of the DMA channels (initiating DMA transfers)
• Interpreting buffer descriptors
• Address recognition for receive frames
• Random number generation for transmit collision backoff timer
MCF5271 Reference Manual, Rev. 2
19-2 Freescale Semiconductor
Introduction
NOTE
DMA references in this section refer to the FEC’s DMA engine. This
DMA engine is for the transfer of FEC data only, and is not related to
the DMA controller described in Chapter 14, “DMA Controller
Module ,” nor to the DMA timers described in
.”
The RAM is the focal point of all data flow in the Fast Ethernet Controller and is divided into transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR register.
User data flows to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the transmit block and receive data flows from the receive block into the receive FIFO.
The user controls the FEC by writing, through the SIF (Slave Interface) module, into control registers located in each block. The CSR (control and status register) block provides global control
(e.g. Ethernet reset and enable) and interrupt handling registers.
The MII block provides a serial channel for control/status communication with the external physical layer device (transceiver). This serial channel consists of the EMDC (Management Data
Clock) and EMDIO (Management Data Input/Output) lines of the MII interface.
The DMA block provides multiple channels allowing transmit data, transmit descriptor, receive data and receive descriptor accesses to run independently.
The Transmit and Receive blocks provide the Ethernet MAC functionality (with some assist from microcode).
The Message Information Block (MIB) maintains counters for a variety of network events and statistics. It is not necessary for operation of the FEC but provides valuable counters for network management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and
some of the IEEE 802.3 counters. See Section 19.2.3, “MIB Block Counters Memory Map ” for
more information.
19.1.3 Features
The FEC incorporates the following features:
• Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
• IEEE 802.3 full duplex flow control
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 19-3
Fast Ethernet Controller (FEC)
• Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate of 50 MHz
• Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25 MHz
• Retransmission from transmit FIFO following a collision (no processor bus utilization)
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization)
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
19.1.4 Modes of Operation
The primary operational modes are described in this section.
19.1.4.1 Full and Half Duplex Operation
Full duplex mode is intended for use on point to point links between switches or end node to switch. Half duplex mode is used in connections between an end node and a repeater or between repeaters. Selection of the duplex mode is controlled by TCR[FDEN].
When configured for full duplex mode, flow control may be enabled. Refer to the
TCR[RFC_PAUSE] and TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and
Duplex Flow Control ,” for more details.
19.1.5 Interface Options
The following interface options are supported. A detailed discussion of the interface
configurations is provided in Section 19.3.5, “Network Interface Options ”.
19.1.5.1 10 Mbps and 100 Mbps MII Interface
MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100 Mbps operation. The MAC-PHY interface may be configured to operate in MII mode by asserting
RCR[MII_MODE].
The speed of operation is determined by the ETXCLK and ERXCLK pins which are driven by the external transceiver. The transceiver will either auto-negotiate the speed or it may be controlled by
MCF5271 Reference Manual, Rev. 2
19-4 Freescale Semiconductor
Memory Map/Register Definition software via the serial management interface (EMDC/EMDIO pins) to the transceiver. Refer to the
MMFR and MSCR register descriptions as well as the section on the MII for a description of how to read and write registers in the transceiver via this interface.
19.1.5.2 10 Mpbs 7-Wire Interface Operation
The FEC supports a 7-wire interface as used by many 10 Mbps ethernet transceivers. The
RCR[MII_MODE] bit controls this functionality. If this bit is cleared, the MII mode is disabled and the 10 Mbps, 7-wire mode is enabled.
19.1.6 Address Recognition Options
The address options supported are promiscuous, broadcast reject, individual address (hash or exact match), and multicast hash match. Address recognition options are discussed in detail in
Section 19.3.8, “Ethernet Address Recognition
.”
19.1.7 Internal Loopback
Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in
Section 19.3.13, “ Internal and External Loopback
.”
19.2 Memory Map/Register Definition
This section gives an overview of the registers, followed by a description of the buffers.
The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The CSRs are used for mode control and to extract global status information. The descriptors are used to pass data buffers and related buffer information between the hardware and software.
19.2.1 High-Level Module Memory Map
The FEC implementation requires a 1-Kbyte memory map space. This is divided into 2 sections of 512 bytes each. The first is used for control/status registers. The second contains event/statistic counters held in the MIB block.
defines the top level memory map.
Table 19-1. Module Memory Map
Address
IPSBAR + 0x1000–11FF
IPSBAR + 0x1200–13FF
Function
Control/Status Registers
MIB Block Counters
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 19-5
Fast Ethernet Controller (FEC)
19.2.2 Register Memory Map
Table 19-2 shows the FEC register memory map with each register address, name, and a brief
description.
Table 19-2. FEC Register Memory Map
IPSBAR Offset
0x1084
0x10C4
0x10E4
0x10E8
0x10EC
0x1118
0x111C
0x1120
0x1004
0x1008
0x1010
0x1014
0x1024
0x1040
0x1044
0x1064
0x1124
0x1144
0x114C
0x1150
0x1180
0x1184
0x1188
Name
RCR
TCR
PALR
PAUR
OPD
IAUR
IALR
GAUR
EIR
EIMR
RDAR
TDAR
ECR
MDATA
MSCR
MIBC
GALR
TFWR
FRBR
FRSR
ERDSR
ETDSR
EMRBR
Description
Interrupt Event Register
Interrupt Mask Register
Receive Descriptor Active Register
Transmit Descriptor Active Register
Ethernet Control Register
MII Data Register
MII Speed Control Register
MIB Control/Status Register
Receive Control Register
Transmit Control Register
Physical Address Low Register
Physical Address High+ Type Field
Opcode + Pause Duration
Upper 32 bits of Individual Hash Table
Lower 32 Bits of Individual Hash Table
Upper 32 bits of Group Hash Table
Lower 32 bits of Group Hash Table
Transmit FIFO Watermark
FIFO Receive Bound Register
FIFO Receive FIFO Start Registers
Pointer to Receive Descriptor Ring
Pointer to Transmit Descriptor Ring
Maximum Receive Buffer Size
Size
(bits)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
19.2.3 MIB Block Counters Memory Map
Table 19-3 defines the MIB Counters memory map which defines the locations in the MIB RAM
space where hardware maintained counters reside. These fall in the 0x1200-0x13FF address offset range. The counters are divided into two groups.
MCF5271 Reference Manual, Rev. 2
19-6 Freescale Semiconductor
Memory Map/Register Definition
RMON counters are included which cover the Ethernet Statistics counters defined in RFC 1757.
In addition to the counters defined in the Ethernet Statistics group, a counter is included to count truncated frames as the FEC only supports frame lengths up to 2032 bytes. The RMON counters are implemented independently for transmit and receive to insure accurate network statistics when operating in full duplex mode.
IEEE counters are included which support the Mandatory and Recommended counter packages defined in Section 5 of ANSI/IEEE Std. 802.3 (1998 edition). The IEEE Basic Package objects are supported by the FEC but do not require counters in the MIB block. In addition, some of the recommended package objects which are supported do not require MIB counters. Counters for transmit and receive full duplex flow control frames are included as well.
Table 19-3. MIB Counters Memory Map
IPSBAR Offset
0x1220
0x1224
0x1228
0x122C
0x1230
0x1234
0x1238
0x123C
0x1200
0x1204
0x1208
0x120C
0x1210
0x1214
0x1218
0x121C
0x1240
0x1244
0x1248
0x124C
0x1250
0x1254
0x1258
0x125C
0x1260
Mnemonic
RMON_T_DROP
RMON_T_PACKETS
RMON_T_BC_PKT
RMON_T_MC_PKT
RMON_T_CRC_ALIGN
RMON_T_UNDERSIZE
RMON_T_OVERSIZE
RMON_T_FRAG
RMON_T_JAB
RMON_T_COL
RMON_T_P64
RMON_T_P65TO127
RMON_T_P128TO255
RMON_T_P256TO511
RMON_T_P512TO1023
RMON_T_P1024TO2047
RMON_T_P_GTE2048
RMON_T_OCTETS
IEEE_T_DROP
IEEE_T_FRAME_OK
IEEE_T_1COL
IEEE_T_MCOL
IEEE_T_DEF
IEEE_T_LCOL
IEEE_T_EXCOL
Description
Count of frames not counted correctly
RMON Tx packet count
RMON Tx Broadcast Packets
RMON Tx Multicast Packets
RMON Tx Packets w CRC/Align error
RMON Tx Packets < 64 bytes, good crc
RMON Tx Packets > MAX_FL bytes, good crc
RMON Tx Packets < 64 bytes, bad crc
RMON Tx Packets > MAX_FL bytes, bad crc
RMON Tx collision count
RMON Tx 64 byte packets
RMON Tx 65 to 127 byte packets
RMON Tx 128 to 255 byte packets
RMON Tx 256 to 511 byte packets
RMON Tx 512 to 1023 byte packets
RMON Tx 1024 to 2047 byte packets
RMON Tx packets w > 2048 bytes
RMON Tx Octets
Count of frames not counted correctly
Frames Transmitted OK
Frames Transmitted with Single Collision
Frames Transmitted with Multiple Collisions
Frames Transmitted after Deferral Delay
Frames Transmitted with Late Collision
Frames Transmitted with Excessive Collisions
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 19-7
Fast Ethernet Controller (FEC)
Table 19-3. MIB Counters Memory Map (Continued)
IPSBAR Offset
0x12AC
0x12B0
0x12B4
0x12B8
0x12BC
0x12C0
0x12C4
0x12C8
0x12CC
0x12D0
0x12D4
0x12D8
0x12DC
0x12E0
0x128C
0x1290
0x1294
0x1298
0x129C
0x12A0
0x12A4
0x12A8
0x1264
0x1268
0x126C
0x1270
0x1274
0x1284
0x1288
Mnemonic
IEEE_T_MACERR
IEEE_T_CSERR
IEEE_T_SQE
IEEE_T_FDXFC
IEEE_T_OCTETS_OK
RMON_R_PACKETS
RMON_R_BC_PKT
RMON_R_MC_PKT
RMON_R_CRC_ALIGN
RMON_R_UNDERSIZE
RMON_R_OVERSIZE
RMON_R_FRAG
RMON_R_JAB
RMON_R_RESVD_0
RMON_R_P64
RMON_R_P65TO127
RMON_R_P128TO255
RMON_R_P256TO511
RMON_R_P512TO1023
RMON_R_P1024TO2047
RMON_R_P_GTE2048
RMON_R_OCTETS
IEEE_R_DROP
IEEE_R_FRAME_OK
IEEE_R_CRC
IEEE_R_ALIGN
IEEE_R_MACERR
IEEE_R_FDXFC
IEEE_R_OCTETS_OK
Description
Frames Transmitted with Tx FIFO Underrun
Frames Transmitted with Carrier Sense Error
Frames Transmitted with SQE Error
Flow Control Pause frames transmitted
Octet count for Frames Transmitted w/o Error
RMON Rx packet count
RMON Rx Broadcast Packets
RMON Rx Multicast Packets
RMON Rx Packets w CRC/Align error
RMON Rx Packets < 64 bytes, good crc
RMON Rx Packets > MAX_FL bytes, good crc
RMON Rx Packets < 64 bytes, bad crc
RMON Rx Packets > MAX_FL bytes, bad crc
RMON Rx 64 byte packets
RMON Rx 65 to 127 byte packets
RMON Rx 128 to 255 byte packets
RMON Rx 256 to 511 byte packets
RMON Rx 512 to 1023 byte packets
RMON Rx 1024 to 2047 byte packets
RMON Rx packets w > 2048 bytes
RMON Rx Octets
Count of frames not counted correctly
Frames Received OK
Frames Received with CRC Error
Frames Received with Alignment Error
Receive Fifo Overflow count
Flow Control Pause frames received
Octet count for Frames Rcvd w/o Error
19.2.4 Register Description
The following sections describe each register in detail.
MCF5271 Reference Manual, Rev. 2
19-8 Freescale Semiconductor
Memory Map/Register Definition
19.2.4.1 Ethernet Interrupt Event Register (EIR)
When an event occurs that sets a bit in the EIR, an interrupt will be generated if the corresponding bit in the interrupt mask register (EIMR) is also set. The bit in the EIR is cleared if a one is written to that bit position; writing zero has no effect. This register is cleared upon hardware reset.
These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB,
RXF, RXB, and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR, BABR, BABT, LC and RL. Interrupts resulting from internal errors are
HBERR and UN.
Some of the error interrupts are independently counted in the MIB block counters. Software may choose to mask off these interrupts since these errors will be visible to network management via the MIB counters.
• HBERR - IEEE_T_SQE
• BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)
• BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)
• LATE_COL - IEEE_T_LCOL
• COL_RETRY_LIM - IEEE_T_EXCOL
• XFIFO_UN - IEEE_T_MACERR
31
R HB
W
ERR
30 29 28 27 26 25 24 23 22
BABR BABT GRA TXF TXB RXF RXB MII EB
ERR
Reset 0 0 0 0 0 0 0 0 0 0
R 0
W
Reset 0
Address
15 14
0
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
21 20 19
LC RL UN
0
5
0
0
4
0
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1004
Figure 19-2. Ethernet Interrupt Event Register (EIR)
0
3
0
Bits
31
30
0
2
0
18
0
0
0
1
0
17
0
0
16
0
0
Table 19-4. EIR Field Descriptions
Name Description
HBERR Heartbeat error. This interrupt indicates that HBC is set in the TCR register and that the
COL input was not asserted within the Heartbeat window following a transmission.
BABR Babbling receive error. This bit indicates a frame was received with length in excess of
RCR[MAX_FL] bytes.
0
0
0
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 19-9
Fast Ethernet Controller (FEC)
Bits
29
28
27
26
25
24
23
22
21
20
19
18–0
Table 19-4. EIR Field Descriptions (Continued)
Name Description
BABT
GRA
Babbling transmit error. This bit indicates that the transmitted frame length has exceeded
RCR[MAX_FL] bytes. This condition is usually caused by a frame that is too long being placed into the transmit data buffer(s). Truncation does not occur.
Graceful stop complete. This interrupt will be asserted for one of three reasons. Graceful stop means that the transmitter is put into a pause state after completion of the frame currently being transmitted.
1) A graceful stop, which was initiated by the setting of the TCR[GTS] bit is now complete.
2) A graceful stop, which was initiated by the setting of the TCR[TFC_PAUSE] bit is now complete.
3) A graceful stop, which was initiated by the reception of a valid full duplex flow control
“pause” frame is now complete. Refer to Section 19.3.10, “ Full Duplex Flow Control.”
TXF
TXB
RXF
RXB Receive buffer interrupt. This bit indicates that a receive buffer descriptor has been updated that was not the last in the frame.
MII interrupt. This bit indicates that the MII has completed the data transfer requested.
MII
EBERR Ethernet bus error. This bit indicates that a system bus error occurred when a DMA transaction was underway. When the EBERR bit is set, ECR[ETHER_EN] will be cleared, halting frame processing by the FEC. When this occurs software will need to insure that the FIFO controller and DMA are also soft reset.
LC Late collision. This bit indicates that a collision occurred beyond the collision window (slot time) in half duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.
RL
Transmit frame interrupt. This bit indicates that a frame has been transmitted and that the last corresponding buffer descriptor has been updated.
Transmit buffer interrupt. This bit indicates that a transmit buffer descriptor has been updated.
Receive frame interrupt. This bit indicates that a frame has been received and that the last corresponding buffer descriptor has been updated.
UN
—
Collision retry limit. This bit indicates that a collision occurred on each of 16 successive attempts to transmit the frame. The frame is discarded without being transmitted and transmission of the next frame will commence. Can only occur in half duplex mode.
Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete frame was transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded.
Reserved, should be cleared.
19.2.4.2 Interrupt Mask Register (EIMR)
The EIMR register controls which interrupt events are allowed to generate actual interrupts. All implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the corresponding bits in both the EIR and EIMR registers are set, the interrupt will be signalled to the
CPU. The interrupt signal will remain asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.
MCF5271 Reference Manual, Rev. 2
19-10 Freescale Semiconductor
Memory Map/Register Definition
31
R HB
ERR
W
30 29 28 27 26 25 24 23 22
BABR BABT GRA TXF TXB RXF RXB MII EB
ERR
Reset 0 0 0 0 0 0 0 0 0 0
Address
15
R 0
W
Reset 0
14
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
21 20 19
LC RL UN
0
5
0
0
Table 19-5. EIMR Field Descriptions
0
4
0
0
IPSBAR + 0x1008
Figure 19-3. Interrupt Mask Register (EIMR)
0
3
0
0
Bits
31–19
18–0
0
2
0
18
0
0
0
1
0
17
0
0
16
0
0
Name Description
and
Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The corresponding EIMR bit determines whether an interrupt condition can generate an interrupt. At every processor clock, the EIR samples the signal generated by the interrupting source. The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is set.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is not masked.
— Reserved, should be cleared.
0
0
0
19.2.4.3 Receive Descriptor Active Register (RDAR)
RDAR is a command register, written by the user, that indicates that the receive descriptor ring has been updated (empty receive buffers have been produced by the driver with the empty bit set).
Whenever the register is written, the RDAR bit is set. This is independent of the data actually written by the user. When set, the FEC will poll the receive descriptor ring and process receive frames (provided ECR[ETHER_EN] is also set). Once the FEC polls a receive descriptor whose empty bit is not set, then the FEC will clear the RDAR bit and cease receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors have been placed into the receive descriptor ring.
The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
19-11
Fast Ethernet Controller (FEC)
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
Bits
31–25
24
23–0
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
0
9
0
25 24 23
0 RDAR 0
0
8
0
0
7
0
0
6
0
22
0
0
5
0
21
0
0
4
0
20
0
0
3
0
19
0
0
2
0
18
0
0
1
0
17
0
16
0
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1010
Figure 19-4. Receive Descriptor Active Register (RDAR)
0
Table 19-6. RDAR Field Descriptions
Name
—
RDAR
—
0 0
Description
Reserved, should be cleared.
Set to one when this register is written, regardless of the value written. Cleared by the FEC device whenever no additional “empty” descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared.
Reserved, should be cleared.
0
0
0
19.2.4.4 Transmit Descriptor Active Register (TDAR)
The TDAR is a command register which should be written by the user to indicate that the transmit descriptor ring has been updated (transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor).
Whenever the register is written, the TDAR bit is set. This value is independent of the data actually written by the user. When set, the FEC will poll the transmit descriptor ring and process transmit frames (provided ECR[ETHER_EN] is also set). Once the FEC polls a transmit descriptor whose ready bit is not set, then the FEC will clear the TDAR bit and cease transmit descriptor ring polling until the user sets the bit again, signifying additional descriptors have been placed into the transmit descriptor ring.
The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set.
19-12
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
Bits
31–25
24
23–0
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
0
9
0
25 24 23
0 TDAR 0
0
8
0
0
7
0
0
6
0
22
0
0
5
0
21
0
0
4
0
20
0
0
3
0
19
0
0
2
0
18
0
0
1
0
17
0
16
0
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1014
Figure 19-5. Transmit Descriptor Active Register (TDAR)
0
Name
—
TDAR
—
0 0
Table 19-7. TDAR Field Descriptions
Description
Reserved, should be cleared.
Set to one when this register is written, regardless of the value written. Cleared by the FEC device whenever no additional “ready” descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared.
Reserved, should be cleared.
0
0
0
19.2.4.5 Ethernet Control Register (ECR)
ECR is a read/write user register, though both fields in this register may be altered by hardware as well. The ECR is used to enable/disable the FEC.
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
31
R 0
W
Reset 1
15
R 0
W
Reset 0
Address
Bits
31–2
1
14
0
1
13
0
1
12
0
0
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
0
4
0
0
Name
—
0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1024
Figure 19-6. Ethernet Control Register (ECR)
0
Table 19-8. ECR Field Descriptions
Description
Reserved.
0
3
0
0 0 0
2 1 0
0 ETHER
_EN
RESET
0 0 0
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 19-13
Fast Ethernet Controller (FEC)
Bits
1
0
Table 19-8. ECR Field Descriptions (Continued)
Name Description
ETHER_EN When this bit is set, the FEC is enabled, and reception and transmission are possible.
When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When ETHER_EN is deasserted, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer descriptor and FIFO pointers. The ETHER_EN bit is altered by hardware under the following conditions:
• ECR[RESET] is set by software, in which case ETHER_EN will be cleared
• An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN will be cleared
RESET When this bit is set, the equivalent of a hardware reset is performed but it is local to the
FEC. ETHER_EN is cleared and all other FEC registers take their reset values. Also, any transmission/reception currently in progress is abruptly aborted. This bit is automatically cleared by hardware during the reset sequence. The reset sequence takes approximately
8 system clock cycles after RESET is written with a 1.
19.2.4.6 MII Management Frame Register (MMFR)
The MMFR is accessed by the user and does not reset to a defined value. The MMFR register is used to communicate with the attached MII compatible PHY device(s), providing read/write access to their MII registers. Performing a write to the MMFR will cause a management frame to be sourced unless the MSCR has been programmed to 0. In the case of writing to MMFR when
MSCR = 0, if the MSCR register is then written to a non-zero value, an MII frame will be generated with the data previously written to the MMFR. This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero.
31 30
R
W
Reset —
ST
—
14 15
R
W
Reset —
Address
29
OP
28
—
13
—
12
27
—
11
26
—
10
25
PA
—
9
24 23
— —
8
DATA
7
22
—
6
21
—
5
20
RA
—
4
19
—
3
18
—
2
— — — — — — — — — — — —
IPSBAR + 0x1040
Figure 19-7. MII Management Frame Register (MMFR)
—
17
TA
16
—
1
—
0
— —
19-14
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
Bit
31–30
29–28
27–23
22–18
17–16
15–0
Name
ST
OP
PA
RA
TA
DATA
Table 19-9. MMFR Field Descriptions
Description
Start of frame delimiter. These bits must be programmed to 01 for a valid MII management frame.
Operation code. This field must be programmed to 10 (read) or 01 (write) to generate a valid MII management frame. A value of 11 will produce “read” frame operation while a value of 00 will produce “write” frame operation, but these frames will not be MII compliant.
PHY address. This field specifies one of up to 32 attached PHY devices.
Register address. This field specifies one of up to 32 registers within the specified PHY device.
Turn around. This field must be programmed to 10 to generate a valid MII management frame.
Management frame data. This is the field for data to be written to or read from the PHY register.
To perform a read or write operation on the MII Management Interface, the MMFR register must be written by the user. To generate a valid read or write management frame, the ST field must be written with a 01 pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame will be generated but will not comply with the IEEE 802.3 MII definition.
To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern will cause the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time the contents of the MMFR register will be altered as the contents are serially shifted and will be unpredictable if read by the user. Once the write management frame operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR register will match the original value written.
To generate an MII Management Interface read frame (read a PHY register) the user must write
{01 10 PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a don’t care). Writing this pattern will cause the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time the contents of the MMFR register will be altered as the contents are serially shifted, and will be unpredictable if read by the user. Once the read management frame operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR register will match the original value written except for the DATA field whose contents have been replaced by the value read from the
PHY register.
If the MMFR register is written while frame generation is in progress, the frame contents will be altered. Software should use the MII_STATUS register and/or the MII interrupt to avoid writing to the MMFR register while frame generation is in progress.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 19-15
Fast Ethernet Controller (FEC)
19.2.4.7 MII Speed Control Register (MSCR)
The MSCR provides control of the MII clock (EMDC pin) frequency and allows a preamble drop on the MII management frame.
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
Bits
31–8
7
6–1
0
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
0
9
0
25
0
24
0
23
0
0 0
8 7
0 DIS_
PRE
0
6
22
0
0
5
21
0
20
0
19
0
0 0
4 3
MII_SPEED
0
2
18
0
0
1
17
0
0
0
0
16
0
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1044
Figure 19-8. MII Speed Control Register (MSCR)
0
Table 19-10. MSCR Field Descriptions
0 0 0
Name Description
— Reserved, should be cleared.
DIS_PRE Asserting this bit will cause preamble (32 1’s) not to be prepended to the MII management frame. The MII standard allows the preamble to be dropped if the attached PHY device(s) does not require it.
MII_SPEED MII_SPEED controls the frequency of the MII management interface clock (EMDC) relative to the system clock. A value of 0 in this field will “turn off” the EMDC and leave it in low voltage state. Any non-zero value will result in the EMDC frequency of
1/(MII_SPEED × 2) of the system clock frequency.
— Reserved, should be cleared.
The MII_SPEED field must be programmed with a value to provide an EMDC frequency of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to a non-zero value in order to source a read or write management frame. After the management frame is complete the MSCR register may optionally be set to zero to turn off the
EMDC. The EMDC generated will have a 50% duty cycle except when MII_SPEED is changed during operation (change will take effect following either a rising or falling edge of EMDC).
If the system clock is 75 MHz, programming MII_SPEED to 0x0F will result in an EMDC frequency of 75 MHz / (15 × 2) = 2.5 MHz. A table showing optimum values for MII_SPEED as a function of system clock frequency is provided below.
MCF5271 Reference Manual, Rev. 2
19-16 Freescale Semiconductor
Memory Map/Register Definition
Table 19-11. Programming Examples for MSCR
System Clock Frequency
25 MHz
33 MHz
40 MHz
50 MHz
66 MHz
75 MHz
MSCR[MII_SPEED]
0x5
0x7
0x8
0xA
0xE
0xF
EMDC frequency
2.5 MHz
2.36 MHz
2.5 MHz
2.5 MHz
2.36 MHz
2.5 MHz
19.2.4.8 MIB Control Register (MIBC)
The MIBC is a read/write register used to provide control of and to observe the state of the MIB block. This register is accessed by user software if there is a need to disable the MIB block operation. For example, in order to clear all MIB counters in RAM the user should disable the MIB block, then clear all the MIB RAM locations, then enable the MIB block. The MIB_DIS bit is reset
for the locations of the MIB counters.
31
R MIB_
DIS
30
MIB_
IDLE
W
Reset 1 1
15
R 0
W
Reset 0
Address
14
0
0
Bits
31
30
29–0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
25
0
0
9
0
0
8
0
24
0
23
0
0
7
0
0
6
0
22
0
21
0
0
5
0
0
4
0
20
0
19
0
0
3
0
0
2
0
18
0
17
0
0
1
0
0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1064
Figure 19-9. MIB Control Register (MIBC)
0 0 0
Table 19-12. MIBC Field Descriptions
Name Description
MIB_DIS A read/write control bit. If set, the MIB logic will halt and not update any MIB counters.
MIB_IDLE A read-only status bit. If set the MIB block is not currently updating any MIB counters.
— Reserved.
16
0
0
0
0
0
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
19-17
Fast Ethernet Controller (FEC)
19.2.4.9 Receive Control Register (RCR)
The RCR, programmed by the user, controls the operational mode of the receive block and should be written only when ECR[ETHER_EN] = 0 (initialization time).
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
Bits
31–27
26–16
15–6
5
4
3
2
1
0
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
0
11
0
27
0
26
1
10
0
25
0
9
0
24
1
8
0
23
1
7
0
22 21
MAX_FL
20 19 18 17 16
1 1 0 1 1 1 0
6 5 4
0 FCE BC_
REJ
3 2
PROM MII_
MODE
1 0
DRT LOOP
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1084
Figure 19-10. Receive Control Register (RCR)
0
Table 19-13. RCR Field Descriptions
0 0 1
Name Description
— Reserved, should be cleared.
MAX_FL Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame. Transmit frames longer than MAX_FL will cause the BABT interrupt to occur. Receive Frames longer than MAX_FL will cause the BABR interrupt to occur and will set the LG bit in the end of frame receive buffer descriptor. The recommended default value to be programmed by the user is 1518 or 1522 (if VLAN Tags are supported).
—
FCE
Reserved, should be cleared.
Flow control enable. If asserted, the receiver will detect PAUSE frames. Upon PAUSE frame detection, the transmitter will stop transmitting data frames for a given duration.
BC_REJ Broadcast frame reject. If asserted, frames with DA (destination address) =
FF_FF_FF_FF_FF_FF will be rejected unless the PROM bit is set. If both BC_REJ and
PROM = 1, then frames with broadcast DA will be accepted and the M (MISS) bit will be set in the receive buffer descriptor.
PROM Promiscuous mode. All frames are accepted regardless of address matching.
MII_MODE Media independent interface mode. Selects external interface mode. Setting this bit to one selects MII mode, setting this bit equal to zero selects 7-wire mode (used only for serial 10
Mbps). This bit controls the interface mode for both transmit and receive blocks.
DRT Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode).
1 Disable reception of frames while transmitting (normally used for half duplex mode).
LOOP Internal loopback. If set, transmitted frames are looped back internal to the device and the transmit output signals are not asserted. The system clock is substituted for the ETXCLK when LOOP is asserted. DRT must be set to zero when asserting LOOP.
MCF5271 Reference Manual, Rev. 2
19-18 Freescale Semiconductor
Memory Map/Register Definition
19.2.4.10 Transmit Control Register (TCR)
The TCR is read/write and is written by the user to configure the transmit block. This register is cleared at system reset. Bits 2 and 1 should be modified only when ECR[ETHER_EN] = 0.
31
R 0
W
Reset 0
15
R 0
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
25
0
0
9
0
24
0
0
8
0
23
0
0
7
0
22
0
0
6
0
21
0
20
0
19
0
18
0
17
0
16
0
0 0 0 0 0 0
5 4 3 2 1 0
0 RFC_
PAUSE
TFC_
PAUSE
FEDN HBC GTS
W
Reset 0
Address
Bits
31–5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x10C4
Figure 19-11. Transmit Control Register (TCR)
0 0 0 0
Table 19-14. TCR Field Descriptions
Name Description
—
RFC_PAUS
E
Reserved, should be cleared.
Receive frame control pause. This read-only status bit will be asserted when a full duplex flow control pause frame has been received and the transmitter is paused for the duration defined in this pause frame. This bit will automatically clear when the pause duration is complete.
TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC will stop transmission of data frames after the current transmission is complete. At this time, the GRA interrupt in the EIR register will be asserted. With transmission of data frames stopped, the MAC will transmit a MAC Control PAUSE frame.
Next, the MAC will clear the TFC_PAUSE bit and resume transmitting data frames. Note that if the transmitter is paused due to user assertion of GTS or reception of a PAUSE frame, the MAC may still transmit a MAC Control PAUSE frame.
FDEN
HBC
Full duplex enable. If set, frames are transmitted independent of carrier sense and collision inputs. This bit should only be modified when ETHER_EN is deasserted.
Heartbeat control. If set, the heartbeat check is performed following end of transmission and the HB bit in the status register will be set if the collision input does not assert within the heartbeat window. This bit should only be modified when ETHER_EN is deasserted.
GTS Graceful transmit stop. When this bit is set, the MAC will stop transmission after any frame that is currently being transmitted is complete and the GRA interrupt in the EIR register will be asserted. If frame transmission is not currently underway, the GRA interrupt will be asserted immediately. Once transmission has completed, a “restart” can be accomplished by clearing the GTS bit. The next frame in the transmit FIFO will then be transmitted. If an early collision occurs during transmission when GTS = 1, transmission will stop after the collision. The frame will be transmitted again once GTS is cleared. Note that there may be old frames in the transmit FIFO that will be transmitted when GTS is reasserted. To avoid this deassert ECR[ETHER_EN] following the GRA interrupt.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 19-19
Fast Ethernet Controller (FEC)
19.2.4.11 Physical Address Low Register (PALR)
The PALR is written by the user. This register contains the lower 32 bits (bytes 0,1,2,3) of the
48-bit address used in the address recognition process to compare with the DA (Destination
Address) field of receive frames with an individual DA. In addition, this register is used in bytes
0 through 3 of the 6-byte source address field when transmitting PAUSE frames. This register is not reset and must be initialized by the user.
31
R
W
Reset —
15
R
W
Reset —
Address
Bits
31–0
30
—
14
29
—
13
28
—
12
27
—
11
26
—
10
25
—
9
24 23
PADDR1
— —
8 7
PADDR1
22
—
6
21
—
5
20
—
4
19
—
3
18
—
2
17
—
1
16
—
0
— — — — — — — — — — — —
IPSBAR + 0x10E4
Figure 19-12. Physical Address Low Register (PALR)
Table 19-15. PALR Field Descriptions
— — —
Name Description
PADDR1 Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual address to be used for exact match, and the source address field in PAUSE frames.
19.2.4.12 Physical Address High Register (PAUR)
The PAUR is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the
48-bit address used in the address recognition process to compare with the DA (destination address) field of receive frames with an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte Source Address field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) used for transmission of PAUSE frames. This register is not reset and bits 31:16 must be initialized by the user.
19-20
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
31
R
W
Reset —
15
R
W
Reset 1
Address
BIts
31–16
15–0
30
—
14
29
—
13
28
—
12
27
—
11
26
—
10
25
—
9
24 23
PADDR2
— —
8
TYPE
7
22
—
6
21
—
5
20
—
4
19
—
3
18
—
2
17
—
1
16
—
0
0 0 0 1 0 0 0 0 0 0 0 1
IPSBAR + 0x10E8
Figure 19-13. Physical Address High Register (PAUR)
Table 19-16. PAUR Field Descriptions
0 0 0
Name Description
PADDR2 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames.
TYPE Type field in PAUSE frames. These 16-bits are a constant value of 0x8808.
19.2.4.13 Opcode/Pause Duration Register (OPD)
The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode field is a constant value,
0x0001. When another node detects a PAUSE frame, that node will pause transmission for the duration specified in the pause duration field. This register is not reset and must be initialized by the user.
31
R
W
Reset 0
15
R
W
Reset —
Address
30
0
14
29
0
13
28
0
12
27
0
11
26
0
10
25 24 23
OPCODE
22
0 0 0
9 8 7
PAUSE_DUR
0
6
21
0
5
20
0
4
19
0
3
18
— — — — — — — — — — — —
IPSBAR + 0x10EC
Figure 19-14. Opcode/Pause Duration Register (OPD)
—
0
2
17
0
1
16
— —
1
0
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Freescale Semiconductor 19-21
Fast Ethernet Controller (FEC)
Bits
31–16
15–0
Table 19-17. OPD Field Descriptions
Name Description
OPCODE Opcode field used in PAUSE frames.
These bits are a constant, 0x0001.
PAUSE_DUR Pause Duration field used in PAUSE frames.
19.2.4.14
Descriptor Individual Upper Address Register (IAUR)
The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit individual address hash table used in the address recognition process to check for possible match with the DA field of receive frames with an individual DA. This register is not reset and must be initialized by the user.
31
R
W
Reset —
30
—
29
—
28
—
27
—
26
—
25
—
24 23
IADDR1
— —
22
—
21
—
20
—
19
—
18
—
17
—
R
W
15 14 13 12 11 10 9 8 7
IADDR1
6 5 4 3 2 1
Reset —
Address
— — — — — — — —
IPSBAR + 0x1118
— — — — —
Figure 19-15. Descriptor Individual Upper Address Register (IAUR)
—
Table 19-18. IAUR Field Descriptions
Bits
31–0
16
—
0
—
Name Descriptions
IADDR1 The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
19.2.4.15 Descriptor Individual Lower Address Register (IALR)
The IALR register is written by the user. This register contains the lower 32 bits of the 64-bit individual address hash table used in the address recognition process to check for possible match with the DA field of receive frames with an individual DA. This register is not reset and must be initialized by the user.
19-22
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Freescale Semiconductor
Memory Map/Register Definition
31
R
W
Reset —
30
—
29
—
28
—
27
—
26
—
25
—
24 23
IADDR2
— —
22
—
21
—
20
—
19
—
18
—
17
—
16
—
R
W
15 14 13 12 11 10 9 8 7
IADDR2
6 5 4 3 2 1
Reset —
Address
— — — — — — — —
IPSBAR + 0x111C
— — — — —
Figure 19-16. Descriptor Individual Lower Address Register (IALR)
—
Bits
31–0
0
—
Table 19-19. IALR Field Descriptions
Name Description
IADDR2 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
19.2.4.16 Descriptor Group Upper Address Register (GAUR)
The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. This register must be initialized by the user.
31
R
W
Reset —
30
—
29
—
28
—
27
—
26
—
25
—
24 23
GADDR1
— —
22
—
21
—
20
—
19
—
18
—
17
—
R
W
15 14 13 12 11 10 9 8 7
GADDR1
6 5 4 3 2
Reset —
Address
— — — — — — — — — — — — —
IPSBAR + 0x1120
Figure 19-17. Descriptor Group Upper Address Register (GAUR)
1
—
16
—
0
—
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MCF5271 Reference Manual, Rev. 2
19-23
Fast Ethernet Controller (FEC)
Bits
31–0
Table 19-20. GAUR Field Descriptions
Name Description
GADDR1 The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of
GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
19.2.4.17 Descriptor Group Lower Address Register (GALR)
The GALR register is written by the user. This register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. This register must be initialized by the user.
31
R
W
Reset —
30
—
29
—
28
—
27
—
26
—
25
—
24 23
GADDR2
— —
22
—
21
—
20
—
19
—
18
—
17
—
R
W
15 14 13 12 11 10 9 8 7
GADDR2
6 5 4 3 2
Reset —
Address
— — — — — — — — — — — — —
IPSBAR + 0x1124
Figure 19-18. Descriptor Group Lower Address Register (GALR)
1
—
Bits
31–0
Table 19-21. GALR Field Descriptions
Name Description
GADDR2 The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of
GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
16
—
0
—
19.2.4.18 FIFO Transmit FIFO Watermark Register (TFWR)
The TFWR is a 2-bit read/write register programmed by the user to control the amount of data required in the transmit FIFO before transmission of a frame can begin. This allows the user to minimize transmit latency (TFWR = 0x) or allow for larger bus access latency (TFWR = 11) due to contention for the system bus. Setting the watermark to a high value will minimize the risk of transmit FIFO underrun due to contention for the system bus. The byte counts associated with the
TFWR field may need to be modified to match a given system requirement (worst case bus access latency by the transmit data DMA channel).
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Memory Map/Register Definition
31
R 0
W
Reset 0
30
0
0
29
0
0
28
0
0
27
0
0
26
0
0
25
0
0
24
0
0
23
0
0
22
0
0
21
0
0
20
0
0
19
0
0
18
0
0
15
R 0
W
Reset 0
Address
14
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
IPSBAR + 0x1144
Figure 19-19. FIFO Transmit FIFO Watermark Register (TFWR)
Table 19-22. TFWR Field Descriptions
Bits
31–2
1–0
Name
—
TFWR
Descriptions
Reserved, should be cleared.
Number of bytes written to transmit FIFO before transmission of a frame begins
0x 64 bytes written
10 128 bytes written
11 192 bytes written
17
0
0 0
1
TFWR
0
0 0
16
0
19.2.4.19 FIFO Receive Bound Register (FRBR)
The FRBR is an 8-bit register that the user can read to determine the upper address bound of the
FIFO RAM. Drivers can use this value, along with the FRSR to appropriately divide the available
FIFO RAM between the transmit and receive data paths.
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
0
14
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
8
0
7
0 0
6 5
R_BOUND
0
4
0 0 0 0 1 1 0 0 0 0 0 0
IPSBAR + 0x114C
Figure 19-20. FIFO Receive Bound Register (FRBR)
0
3
0
2
0
0
1
0
0
0
0
0
0
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Freescale Semiconductor 19-25
Fast Ethernet Controller (FEC)
Bits
31–10
9–2
1–0
Table 19-23. FRBR Field Descriptions
Name Descriptions
— Reserved, read as 0 (except bit 10, which is read as 1).
R_BOUND Read-only. Highest valid FIFO RAM address.
— Reserved, should be cleared.
19.2.4.20 FIFO Receive Start Register (FRSR)
The FRSR is programmed by the user to indicate the starting address of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed into the FRSR.
The receive FIFO uses addresses from FRSR to FRBR inclusive.
The FRSR register is initialized by hardware at reset. FRSR only needs to be written to change the default value.
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
Bits
31–10
9–2
1–0
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
25
0
0
9
0
8
24
0
23
0
0
7
22
0
21
0
0 0
6 5
R_FSTART
0
4
20
0
19
0
0
3
0
2
18
0
17
0
0
1
0
0 0 0 0 1 0 1 0 0 0 0
IPSBAR + 0x1150
Figure 19-21. FIFO Receive Start Register (FRSR)
0
Table 19-24. FRSR Field Descriptions
0 0
Name Descriptions
— Reserved, read as 0 (except bit 10, which is read as 1).
R_FSTART Address of first receive FIFO location. Acts as delimiter between receive and transmit
FIFOs.
— Reserved, read as 0.
0
16
0
0
0
0
19.2.4.21 Receive Descriptor Ring Start Register (ERDSR)
The ERDSR is written by the user. It provides a pointer to the start of the circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16).
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19-26 Freescale Semiconductor
Memory Map/Register Definition
This register is not reset and must be initialized by the user prior to operation.
31
R
W
Reset —
30
—
29
—
28
—
27
—
26
—
25 24 23
R_DES_START
22
— — — —
21
—
20
—
19
—
18
—
R
W
15 14 13 12 11 10 9 8
R_DES_START
7 6 5 4 3 2
Reset —
Address
— — — — — — — — — — — — —
IPSBAR + 0x1180
Figure 19-22. Receive Descriptor Ring Start Register (ERDSR)
Table 19-25. ERDSR Field Descriptions
Bits
31–2
1–0
Name
R_DES_
START
—
Descriptions
Pointer to start of receive buffer descriptor queue.
Reserved, should be cleared.
17
—
1
0
—
16
—
0
0
—
19.2.4.22 Transmit Buffer Descriptor Ring Start Registers (ETSDR)
The ETSDR is written by the user. It provides a pointer to the start of the circular transmit buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). Bits 1 and 0 should be written to 0 by the user. Non-zero values in these two bit positions are ignored by the hardware.
This register is not reset and must be initialized by the user prior to operation.
31
R
W
Reset —
30
—
29
—
28
—
27
—
26
—
25 24 23
X_DES_START
22
— — — —
21
—
20
—
19
—
18
—
17
—
15
R
W
Reset —
14 13 12 11 10 9 8
X_DES_START
7 6 5 4 3 2 1
0
— — — — — — — — — — — — — —
Address IPSBAR + 0x1184
Figure 19-23. Transmit Buffer Descriptor Ring Start Register (ETDSR)
16
—
0
0
—
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Freescale Semiconductor 19-27
Fast Ethernet Controller (FEC)
Bits
31–2
1–0
Name
X_DES_
START
—
Table 19-26. ETDSR Field Descriptions
Descriptions
Pointer to start of transmit buffer descriptor queue.
Reserved, should be cleared.
19.2.4.23 Receive Buffer Size Register (EMRBR)
The EMRBR is a 9-bit register programmed by the user. The EMRBR register dictates the maximum size of all receive buffers. Note that because receive frames will be truncated at 2k-1 bytes, only bits 10–4 are used. This value should take into consideration that the receive CRC is always written into the last receive buffer. To allow one maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger. The EMRBR must be evenly divisible by 16. To insure this, bits 3-0 are forced low. To minimize bus utilization (descriptor fetches) it is recommended that EMRBR be greater than or equal to 256 bytes.
The EMRBR register does not reset, and must be initialized by the user.
17
0
16
0
31
R 0
W
Reset —
15
R 0
W
Reset —
Address
Bits
30–11
10–4
3–0
30
0
—
14
0
29
0
—
13
0
28
0
—
12
0
27
0
—
11
0
26
0
—
10
25
0
—
9
24
0
23
0
22
0
— — —
8 7
R_BUF_SIZE
6
21
0
—
5
20
0
—
4
19
0
— — — — — — — — — — — —
IPSBAR + 0x1188
Figure 19-24. Receive Buffer Size Register (EMRBR)
Table 19-27. EMRBR Field Descriptions
Name
—
R_BUF_
SIZE
—
Descriptions
Reserved, should be written to 0 by the host processor.
Receive buffer size.
Reserved, should be written to 0 by the host processor.
—
3
0
18
0
—
2
0
—
—
1
0
—
0
0
— —
19.2.5 Buffer Descriptors
This section provides a description of the operation of the driver/DMA via the buffer descriptors.
It is followed by a detailed description of the receive and transmit descriptor fields.
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19-28 Freescale Semiconductor
Memory Map/Register Definition
19.2.5.1 Driver/DMA Operation with Buffer Descriptors
The data for the FEC frames must reside in memory external to the FEC. The data for a frame is placed in one or more buffers. Associated with each buffer is a buffer descriptor (BD) which contains a starting address (32-bit aligned pointer), data length, and status/control information
(which contains the current state for the buffer). To permit maximum user flexibility, the BDs are also located in external memory and are read in by the FEC DMA engine.
Software “produces” buffers by allocating/initializing memory and initializing buffer descriptors.
Setting the RxBD[E] or TxBD[R] bit “produces” the buffer. Software writing to either the TDAR or RDAR tells the FEC that a buffer has been placed in external memory for the transmit or receive data traffic, respectively. The hardware reads the BDs and “consumes” the buffers after they have been produced. After the data DMA is complete and the buffer descriptor status bits have been written by the DMA engine, the RxBD[E] or TxBD[R] bit will be cleared by hardware to signal the buffer has been “consumed.” Software may poll the BDs to detect when the buffers have been consumed or may rely on the buffer/frame interrupts. These buffers may then be processed by the driver and returned to the free list.
The ECR[ETHER_EN] signal operates as a reset to the BD/DMA logic. When ECR[ETHER_EN] is deasserted the DMA engine BD pointers are reset to point to the starting transmit and receive
BDs. The buffer descriptors are not initialized by hardware during reset. At least one transmit and receive buffer descriptor must be initialized by software before the ECR[ETHER_EN] bit is set.
The buffer descriptors operate as two separate rings. ERDSR defines the starting address for receive BDs and ETDSR defines the starting address for transmit BDs. The last buffer descriptor in each ring is defined by the Wrap (W) bit. When set, W indicates that the next descriptor in the ring is at the location pointed to by ERDSR and ETDSR for the receive and transmit rings, respectively. Buffer descriptor rings must start on a 32-bit boundary; however, it is recommended they are made 128-bit aligned.
19.2.5.1.1 Driver/DMA Operation with Transmit BDs
Typically a transmit frame will be divided between multiple buffers. An example is to have an application payload in one buffer, TCP header in a 2nd buffer, IP header in a 3rd buffer,
Ethernet/IEEE 802.3 header in a 4th buffer. The Ethernet MAC does not prepend the Ethernet header (destination address, source address, length/type field(s)), so this must be provided by the driver in one of the transmit buffers. The Ethernet MAC can append the Ethernet CRC to the frame. Whether the CRC is appended by the MAC or by the driver is determined by the TC bit in the transmit BD which must be set by the driver.
The driver (TxBD software producer) should set up Tx BDs in such a way that a complete transmit frame is given to the hardware at once. If a transmit frame consists of three buffers, the BDs should be initialized with pointer, length and control (W, L, TC, ABC) and then the TxBD[R] bits should be set = 1 in reverse order (3rd, 2nd, 1st BD) to insure that the complete frame is ready in memory
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Freescale Semiconductor 19-29
Fast Ethernet Controller (FEC) before the DMA begins. If the TxBDs are set up in order, the DMA Controller could DMA the first
BD before the 2nd was made available, potentially causing a transmit FIFO underrun.
In the FEC, the DMA is notified by the driver that new transmit frame(s) are available by writing to the TDAR register. When this register is written to (data value is not significant) the FEC RISC will tell the DMA to read the next transmit BD in the ring. Once started, the RISC + DMA will continue to read and interpret transmit BDs in order and DMA the associated buffers, until a transmit BD is encountered with the R bit = 0. At this point the FEC will poll this BD one more time. If the R bit = 0 the second time, then the RISC will stop the transmit descriptor read process until software sets up another transmit frame and writes to TDAR.
When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the
R bit, indicating that the hardware consumer is finished with the buffer.
19.2.5.1.2 Driver/DMA Operation with Receive BDs
Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore the driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to the EMRBR register.
The driver (RxBD software producer) should set up some number of “empty” buffers for the
Ethernet by initializing the address field and the E and W bits of the associated receive BDs. The hardware (receive DMA) will consume these buffers by filling them with data as frames are received and clearing the E bit and writing to the L (1 indicates last buffer in frame) bit, the frame status bits (if L = 1) and the length field.
If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the frame. For non-last buffers, the length field in the receive BD will be written by the DMA (at the same time the E bit is cleared) with the default receive buffer length value. For end of frame buffers the receive BD will be written with L = 1 and information written to the status bits (M, BC, MC,
LG, NO, CR, OV, TR). Some of the status bits are error indicators which, if set, indicate the receive frame should be discarded and not given to higher layers. The frame status/length information is written into the receive FIFO following the end of the frame (as a single 32-bit word) by the receive logic. The length field for the end of frame buffer will be written with the length of the entire frame, not just the length of the last buffer.
For simplicity the driver may assign the default receive buffer length to be large enough to contain an entire frame, keeping in mind that a malfunction on the network or out of spec implementation could result in giant frames. Frames of 2k (2048) bytes or larger are truncated by the FEC at 2032 bytes so software is guaranteed never to see a receive frame larger than 2032 bytes.
Similar to transmit, the FEC will poll the receive descriptor ring after the driver sets up receive
BDs and writes to the RDAR register. As frames are received the FEC will fill receive buffers and update the associated BDs, then read the next BD in the receive descriptor ring. If the FEC reads
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19-30 Freescale Semiconductor
Memory Map/Register Definition a receive BD and finds the E bit = 0, it will poll this BD once more. If the BD = 0 a second time the FEC will stop reading receive BDs until the driver writes to RDAR.
19.2.5.2 Ethernet Receive Buffer Descriptor (RxBD)
In the RxBD, the user initializes the E and W bits in the first longword and the pointer in second longword. When the buffer has been DMA’d, the Ethernet controller will modify the E, L, M, BC,
MC, LG, NO, CR, OV, and TR bits and write the length of the used portion of the buffer in the first longword. The M, BC, MC, LG, NO, CR, OV and TR bits in the first longword of the buffer descriptor are only modified by the Ethernet controller when the L bit is set.
15 14 13 12 11
Offset + 0 E RO1 W RO2 L
Offset + 2
Offset + 4
Offset + 6
10
—
9
—
8
M
7 6 5 4 3 2 1 0
BC MC LG NO — CR OV TR
Data Length
Rx Data Buffer Pointer - A[31:16]
Rx Data Buffer Pointer - A[15:0]
Figure 19-25. Receive Buffer Descriptor (RxBD)
Table 19-28. Receive Buffer Descriptor Field Definitions
Word
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Bits
15
14
13
12
11
10–9
Field Name
E
RO1
W
RO2
L
—
Description
Empty. Written by the FEC (=0) and user (=1).
0 The data buffer associated with this BD has been filled with received data, or data reception has been aborted due to an error condition. The status and length fields have been updated as required.
1 The data buffer associated with this BD is empty, or reception is currently in progress.
Receive software ownership. This field is reserved for use by software. This read/write bit will not be modified by hardware, nor will its value affect hardware.
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ERDSR.
Receive software ownership. This field is reserved for use by software. This read/write bit will not be modified by hardware, nor will its value affect hardware.
Last in frame. Written by the FEC.
0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
Reserved.
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19-31
Fast Ethernet Controller (FEC)
Table 19-28. Receive Buffer Descriptor Field Definitions (Continued)
Word Bits Field Name Description
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
8
7
6
5
4
3
2
1
M
BC
MC
LG
NO
—
CR
OV
Miss. Written by the FEC. This bit is set by the FEC for frames that were accepted in promiscuous mode, but were flagged as a “miss” by the internal address recognition. Thus, while in promiscuous mode, the user can use the
M-bit to quickly determine whether the frame was destined to this station.
This bit is valid only if the L-bit is set and the PROM bit is set.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
Will be set if the DA is broadcast (FF-FF-FF-FF-FF-FF).
Will be set if the DA is multicast and not BC.
Rx frame length violation. Written by the FEC. A frame length greater than
RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The receive data is not altered in any way unless the length exceeds 2032 bytes.
Receive non-octet aligned frame. Written by the FEC. A frame that contained a number of bits not divisible by 8 was received, and the CRC check that occurred at the preceding byte boundary generated an error. This bit is valid only if the L-bit is set. If this bit is set the CR bit will not be set.
Reserved.
Receive CRC error. Written by the FEC. This frame contains a CRC error and is an integral number of octets in length. This bit is valid only if the L-bit is set.
Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M, LG, NO, CR, and CL lose their normal meaning and will be zero. This bit is valid only if the L-bit is set.
Offset + 0
Offset + 2
0
15–0
TR Will be set if the receive frame is truncated (frame length > 2032 bytes). If the TR bit is set the frame should be discarded and the other error bits should be ignored as they may be incorrect.
Data
Length
Data length. Written by the FEC. Data length is the number of octets written by the FEC into this BD’s data buffer if L = 0 (the value will be equal to
EMRBR), or the length of the frame including CRC if L = 1. It is written by the
FEC once as the BD is closed.
A[31:16] RX data buffer pointer, bits [31:16]
1
0ffset + 4 15–0
Offset + 6 15–0 A[15:0] RX data buffer pointer, bits [15:0]
1
The receive buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
NOTE
Whenever the software driver sets an E bit in one or more receive descriptors, the driver should follow that with a write to RDAR.
19.2.5.3 Ethernet Transmit Buffer Descriptor (TxBD)
Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s
TxBDs. The Ethernet controller confirms transmission by clearing the ready bit (R bit) when
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19-32 Freescale Semiconductor
Memory Map/Register Definition
DMA of the buffer is complete. In the TxBD the user initializes the R, W, L, and TC bits and the length (in bytes) in the first longword, and the buffer pointer in the second longword.
The FEC will set the R bit = 0 in the first longword of the BD when the buffer has been DMA’d.
Status bits for the buffer/frame are not included in the transmit buffer descriptors. Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the
MIB block. See
Section 19.2.3, “MIB Block Counters Memory Map ” for more details.
15 14 13 12 11
Offset + 0 R TO1 W TO2 L
Offset + 2
Offset + 4
Offset + 6
10 9 8
TC ABC —
7
—
6
—
Data Length
Tx Data Buffer Pointer - A[31:16]
Tx Data Buffer Pointer - A[15:0]
5
—
4
—
Figure 19-26. Transmit Buffer Descriptor (TxBD)
3
—
Table 19-29. Transmit Buffer Descriptor Field Definitions
2
—
Word
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Offset + 0
Bits
15
14
13
12
11
10
9
8–0
1
—
0
—
Field Name
R
TO1
W
TO2
L
TC
ABC
—
Description
Ready. Written by the FEC and the user.
0 The data buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer. The FEC clears this bit after the buffer has been transmitted or after an error condition is encountered.
1 The data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. No fields of this BD may be written by the user once this bit is set.
Transmit software ownership. This field is reserved for software use. This read/write bit will not be modified by hardware, nor will its value affect hardware.
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ETDSR.
Transmit software ownership. This field is reserved for use by software. This read/write bit will not be modified by hardware, nor will its value affect hardware.
Last in frame. Written by user.
0 The buffer is not the last in the transmit frame.
1 The buffer is the last in the transmit frame.
Tx CRC. Written by user (only valid if L = 1).
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
Append bad CRC. Written by user (only valid if L = 1).
0 No effect
1 Transmit the CRC sequence inverted after the last data byte (regardless of
TC value).
Reserved.
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Freescale Semiconductor 19-33
Fast Ethernet Controller (FEC)
Table 19-29. Transmit Buffer Descriptor Field Definitions (Continued)
Word Bits Field Name Description
Offset + 2
Offset + 4
15–0
15–0
Data
Length
Data Length, written by user.
Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modified by the FEC. Bits [15:5] are used by the DMA engine, bits[4:0] are ignored.
A[31:16] Tx data buffer pointer, bits [31:16]
1
Offset + 6 15–0 A[15:0] Tx data buffer pointer, bits [15:0].
1
The transmit buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
NOTE
Once the software driver has set up the buffers for a frame, it should set up the corresponding BDs. The last step in setting up the BDs for a transmit frame should be to set the R bit in the first BD for the frame.
The driver should follow that with a write to TDAR which will trigger the FEC to poll the next BD in the ring.
19.3 Functional Description
This section describes the operation of the FEC, beginning with the hardware and software initialization sequence, then the software (Ethernet driver) interface for transmitting and receiving frames.
Following the software initialization and operation sections are sections providing a detailed description of the functions of the FEC.
19.3.1 Initialization Sequence
This section describes which registers are reset due to hardware reset, which are reset by the FEC
RISC, and what locations the user must initialize prior to enabling the FEC.
19.3.1.1 Hardware Controlled Initialization
In the FEC, registers and control logic that generate interrupts are reset by hardware. A hardware reset deasserts output signals and resets general configuration bits.
Other registers reset when the ECR[ETHER_EN] bit is cleared. ECR[ETHER_EN] is deasserted by a hard reset or may be deasserted by software to halt operation. By deasserting
ECR[ETHER_EN], the configuration control registers such as the TCR and RCR will not be reset, but the entire data path will be reset.
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19-34 Freescale Semiconductor
Table 19-30. ECR[ETHER_EN] De-Assertion Effect on FEC
Register/Machine
XMIT block
RECV block
DMA block
RDAR
TDAR
Descriptor Controller block
Reset Value
Transmission is aborted (bad CRC appended)
Receive activity is aborted
All DMA activity is terminated
Cleared
Cleared
Halt operation
Functional Description
19.3.2 User Initialization (Prior to Setting ECR[ETHER_EN])
The user needs to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact values will depend on the particular application. The sequence is not important.
Ethernet MAC registers requiring initialization are defined in
Table 19-31. User Initialization (Before ECR[ETHER_EN])
Description
Initialize EIMR
Clear EIR (write 0xFFFF_FFFF)
TFWR (optional)
IALR / IAUR
GAUR / GALR
PALR / PAUR (only needed for full duplex flow control)
OPD (only needed for full duplex flow control)
RCR
TCR
MSCR (optional)
Clear MIB_RAM (locations IPSBAR + 0x1200-0x12FC)
FEC FIFO/DMA registers that require initialization are defined in
.
Table 19-32. FEC User Initialization (Before ECR[ETHER_EN])
Description
Initialize FRSR (optional)
Initialize EMRBR
Initialize ERDSR
Initialize ETDSR
Initialize (Empty) Transmit Descriptor ring
Initialize (Empty) Receive Descriptor ring
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Freescale Semiconductor 19-35
Fast Ethernet Controller (FEC)
19.3.3 Microcontroller Initialization
In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted. After the microcontroller initialization sequence is complete, the hardware is ready for operation.
shows microcontroller initialization operations.
Table 19-33. Microcontroller Initialization
Description
Initialize BackOff Random Number Seed
Activate Receiver
Activate Transmitter
Clear Transmit FIFO
Clear Receive FIFO
Initialize Transmit Ring Pointer
Initialize Receive Ring Pointer
Initialize FIFO Count Registers
19.3.4 User Initialization (After Asserting ECR[ETHER_EN])
After asserting ECR[ETHER_EN], the user can set up the buffer/frame descriptors and write to the TDAR and RDAR. Refer to
Section 19.2.5, “Buffer Descriptors
” for more details.
19.3.5 Network Interface Options
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for
10 Mbps Ethernet. The interface mode is selected by the RCR[MII_MODE] bit. In MII mode
(RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE 802.3 standard and supported by the EMAC. These signals are shown in
below.
Table 19-34. MII Mode
Signal Description
Transmit Clock
Transmit Enable
Transmit Data
Transmit Error
Collision
Carrier Sense
Receive Clock
EMAC pin
ETXCLK
ETXEN
ETXD[3:0]
ETXER
ECOL
ECRS
ERXCLK
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19-36 Freescale Semiconductor
Functional Description
Table 19-34. MII Mode (Continued)
Signal Description
Receive Data Valid
Receive Data
Receive Error
Management Data Clock
Management Data
Input/Output
EMAC pin
ERXDV
ERXD[3:0]
ERXER
EMDC
EMDIO
The 7-wire serial mode interface (RCR[MII_MODE] = 0) operates in what is generally referred to as the “AMD” mode. 7-wire mode connections to the external transceiver are shown in
.
Table 19-35. 7-Wire Mode Configuration
SIGNAL DESCRIPTION
Transmit Clock
Transmit Enable
Transmit Data
Collision
Receive Clock
Receive Data Valid
Receive Data
EMAC PIN
ETXCLK
ETXEN
ETXD[0]
ECOL
ERXCLK
ERXDV
ERXD[0]
19.3.6 FEC Frame Transmission
The Ethernet transmitter is designed to work with almost no intervention from software. Once
ECR[ETHER_EN] is asserted and data appears in the transmit FIFO, the Ethernet MAC is able to transmit onto the network.
When the transmit FIFO fills to the watermark (defined by the TFWR), the MAC transmit logic will assert ETXEN and start transmitting the preamble (PA) sequence, the start frame delimiter
(SFD), and then the frame information from the FIFO. However, the controller defers the transmission if the network is busy (ECRS asserts). Before transmitting, the controller waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit times. If so, the transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense
originally became inactive). See Section 19.3.14.1, “ Transmission Errors
” for more details.
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Freescale Semiconductor 19-37
Fast Ethernet Controller (FEC)
If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so that they do not have to be retrieved from system memory in case of a collision. This improves bus utilization and latency in case immediate retransmission is necessary.
When all the frame data has been transmitted, the FCS (Frame Check Sequence or 32-bit Cyclic
Redundancy Check, CRC) bytes are appended if the TC bit is set in the transmit frame control word. If the ABC bit is set in the transmit frame control word, a bad CRC will be appended to the frame data regardless of the TC bit value. Following the transmission of the CRC, the Ethernet controller writes the frame status information to the MIB block. Short frames are automatically padded by the transmit logic (if the TC bit in the transmit buffer descriptor for the end of frame buffer = 1).
Both buffer (TXB) and frame (TFINT) interrupts may be generated as determined by the settings in the EIMR.
The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and
XFIFO_UN. If the transmit frame length exceeds MAX_FL bytes the BABT interrupt will be asserted, however the entire frame will be transmitted (no truncation).
To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When the
TCR[GTS] is set, the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues transmission until the current frame either finishes or terminates with a collision. After the transmitter has stopped the GRA (graceful stop complete) interrupt is asserted.
If TCR[GTS] is cleared, the FEC resumes transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
19.3.7 FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can perform address recognition, CRC checking, short frame checking, and maximum frame length checking.
When the driver enables the FEC receiver by setting ECR[ETHER_EN], it will immediately start processing receive frames. When ERXDV is asserted, the receiver will first check for a valid
PA/SFD header. If the PA/SFD is valid, it will be stripped and the frame will be processed by the receiver. If a valid PA/SFD is not found, the frame will be ignored.
In serial mode, the first 16 bit times of RX_D0 following assertion of ERXDV are ignored.
Following the first 16 bit times the data sequence is checked for alternating 1/0s. If a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time
21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected.
When a 11 is detected, the PA/SFD sequence is complete.
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Functional Description
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur, but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.
Once a collision window (64 bytes) of data has been received and if address recognition has not rejected the frame, the receive FIFO is signalled that the frame is “accepted” and may be passed on to the DMA. If the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified to “reject” the frame. Thus, no collision fragments are presented to the user except late collisions, which indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and once the entire frame is written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the M, BC, MC, LG, NO, CR, OV and TR status bits, and the frame length. See
Section 19.3.14.2, “ Reception Errors
” for more details.
Receive Buffer (RXB) and Frame Interrupts (RFINT) may be generated if enabled by the EIMR register. A receive error interrupt is babbling receiver error (BABR). Receive frames are not truncated if they exceed the max frame length (MAX_FL); however, the BABR interrupt will occur and the LG bit in the Receive Buffer Descriptor (RxBD) will be set. See
“Ethernet Receive Buffer Descriptor (RxBD)
” for more details.
When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory. The Ethernet controller then waits for a new frame.
The Ethernet controller receives serial data lsb first.
19.3.8 Ethernet Address Recognition
The FEC filters the received frames based on destination address (DA) type — individual
(unicast), group (multicast), or broadcast (all-ones group address). The difference between an individual address and a group address is determined by the I/G bit in the destination address field.
A flowchart for address recognition on received frames is illustrated in the figures below.
Address recognition is accomplished through the use of the receive block and microcode running
on the microcontroller. The flowchart shown in Figure 19-27
illustrates the address recognition
decisions made by the receive block, while Figure 19-28
illustrates the decisions made by the microcontroller.
If the DA is a broadcast address and broadcast reject (RCR[BC_REJ]) is deasserted, then the frame will be accepted unconditionally, as shown in
Figure 19-27 . Otherwise, if the DA is not a broadcast
address, then the microcontroller runs the address recognition subroutine, as shown in
.
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Freescale Semiconductor 19-39
Fast Ethernet Controller (FEC)
If the DA is a group (multicast) address and flow control is disabled, then the microcontroller will perform a group hash table lookup using the 64-entry hash table programmed in GAUR and
GALR. If a hash match occurs, the receiver accepts the frame.
If flow control is enabled, the microcontroller will do an exact address match check between the
DA and the designated PAUSE DA (01:80:C2:00:00:01). If the receive block determines that the received frame is a valid PAUSE frame, then the frame will be rejected. Note the receiver will detect a PAUSE frame with the DA field set to either the designated PAUSE DA or the unicast physical address.
If the DA is the individual (unicast) address, the microcontroller performs an individual exact match comparison between the DA and 48-bit physical address that the user programs in the PALR and PAUR registers. If an exact match occurs, the frame is accepted; otherwise, the microcontroller does an individual hash table lookup using the 64-entry hash table programmed in registers, IAUR and IALR. In the case of an individual hash match, the frame is accepted. Again, the receiver will accept or reject the frame based on PAUSE frame detection, shown in
.
If neither a hash match (group or individual), nor an exact match (group or individual) occur, then if promiscuous mode is enabled (RCR[PROM] = 1), then the frame will be accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected.
Similarly, if the DA is a broadcast address, broadcast reject (RCR[BC_REJ]) is asserted, and promiscuous mode is enabled, then the frame will be accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected.
In general, when a frame is rejected, it is flushed from the FIFO.
19-40
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Functional Description
Accept/Reject
Frame
True
Broadcast Addr
?
False
Receive
Address
Recognition
False
Receive Frame
Set BC bit in RCV BD
BC_REJ = 1
?
True
False
PROM = 1
?
True
Hash Match
?
True
False
Exact Match
?
Receive Frame
Set MC bit in RCV BD if multicast
True
False
Pause Frame
?
False
True
Reject Frame
Flush from FIFO
Reject Frame
Flush from FIFO
Receive Frame
Set M (Miss) bit in Rcv BD
Set MC bit in Rcv BD if multicast
Set BC bit in Rcv BD if broadcast
Receive Frame
NOTES:
BC_REJ - field in RCR register (BroadCast REJect)
PROM - field in RCR register (PROMiscous mode)
Pause Frame - valid PAUSE frame received
Figure 19-27. Ethernet Address Recognition—Receive Block Decisions
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
19-41
Fast Ethernet Controller (FEC)
Receive Address
Recognition
Group
I/G Address
?
FCE
?
False
False
True
Pause Address
?
True
Receive Frame
Hash Search
Group Table
Individual
False
Hash Search
Individual Table
Exact Match
?
True
Receive Frame
Match
?
False
True
Receive Frame
True
Match
?
False
Reject Frame
Flush from FIFO
Receive Frame
Reject Frame
Flush from FIFO
NOTES:
FCE - field in RCR register (Flow Control Enable)
I/G - Individual/Group bit in Destination Address (least significant bit in first byte received in MAC frame)
Figure 19-28. Ethernet Address Recognition—Microcode Decisions
19.3.9 Hash Algorithm
The hash table algorithm used in the group and individual hash filtering operates as follows. The
48-bit destination address is mapped into one of 64 bits, which are represented by 64 bits stored in GAUR, GALR (group address hash match) or IAUR, IALR (individual address hash match).
This mapping is performed by passing the 48-bit address through the on-chip 32-bit CRC generator and selecting the 6 most significant bits of the CRC-encoded result to generate a number between 0 and 63. The msb of the CRC result selects GAUR (msb = 1) or GALR (msb = 0). The least significant 5 bits of the hash result select the bit within the selected register. If the CRC generator selects a bit that is set in the hash table, the frame is accepted; otherwise, it is rejected.
For example, if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory. Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses.
The effectiveness of the hash table declines as the number of addresses increases.
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19-42 Freescale Semiconductor
Functional Description
The hash table registers must be initialized by the user. The CRC32 polynomial to use in computing the hash is:
X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + +
A table of example Destination Addresses and corresponding hash values is included below for reference.
Table 19-36. Destination Address to 6-Bit Hash
48-bit DA
65:ff:ff:ff:ff:ff
55:ff:ff:ff:ff:ff
15:ff:ff:ff:ff:ff
35:ff:ff:ff:ff:ff b5:ff:ff:ff:ff:ff
95:ff:ff:ff:ff:ff d5:ff:ff:ff:ff:ff f5:ff:ff:ff:ff:ff db:ff:ff:ff:ff:ff fb:ff:ff:ff:ff:ff bb:ff:ff:ff:ff:ff
8b:ff:ff:ff:ff:ff
0b:ff:ff:ff:ff:ff
3b:ff:ff:ff:ff:ff
7b:ff:ff:ff:ff:ff
5b:ff:ff:ff:ff:ff
27:ff:ff:ff:ff:ff
07:ff:ff:ff:ff:ff
57:ff:ff:ff:ff:ff
77:ff:ff:ff:ff:ff f7:ff:ff:ff:ff:ff c7:ff:ff:ff:ff:ff
97:ff:ff:ff:ff:ff a7:ff:ff:ff:ff:ff
99:ff:ff:ff:ff:ff b9:ff:ff:ff:ff:ff
Hash Decimal
Value
12
13
14
15
10
11
8
9
6
7
4
5
2
3
0
1
20
21
22
23
16
17
18
19
24
25
6-bit Hash (in hex)
0xc
0xd
0xe
0xf
0x8
0x9
0xa
0xb
0x4
0x5
0x6
0x7
0x0
0x1
0x2
0x3
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
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Freescale Semiconductor 19-43
Fast Ethernet Controller (FEC)
1f:ff:ff:ff:ff:ff
3f:ff:ff:ff:ff:ff bf:ff:ff:ff:ff:ff
9f:ff:ff:ff:ff:ff df:ff:ff:ff:ff:ff ef:ff:ff:ff:ff:ff
93:ff:ff:ff:ff:ff b3:ff:ff:ff:ff:ff f3:ff:ff:ff:ff:ff d3:ff:ff:ff:ff:ff
53:ff:ff:ff:ff:ff
73:ff:ff:ff:ff:ff
23:ff:ff:ff:ff:ff
13:ff:ff:ff:ff:ff
3d:ff:ff:ff:ff:ff
0d:ff:ff:ff:ff:ff f9:ff:ff:ff:ff:ff c9:ff:ff:ff:ff:ff
59:ff:ff:ff:ff:ff
79:ff:ff:ff:ff:ff
29:ff:ff:ff:ff:ff
19:ff:ff:ff:ff:ff d1:ff:ff:ff:ff:ff f1:ff:ff:ff:ff:ff b1:ff:ff:ff:ff:ff
91:ff:ff:ff:ff:ff
11:ff:ff:ff:ff:ff
31:ff:ff:ff:ff:ff
71:ff:ff:ff:ff:ff
51:ff:ff:ff:ff:ff
7f:ff:ff:ff:ff:ff
4f:ff:ff:ff:ff:ff
Table 19-36. Destination Address to 6-Bit Hash (Continued)
48-bit DA
6-bit Hash (in hex)
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x2a
0x2b
0x2c
0x2d
0x2e
0x2f
0x30
0x31
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
0x20
0x21
Hash Decimal
Value
54
55
56
57
50
51
52
53
46
47
48
49
42
43
44
45
38
39
40
41
34
35
36
37
30
31
32
33
26
27
28
29
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19-44 Freescale Semiconductor
Table 19-36. Destination Address to 6-Bit Hash (Continued)
48-bit DA
5d:ff:ff:ff:ff:ff
7d:ff:ff:ff:ff:ff fd:ff:ff:ff:ff:ff dd:ff:ff:ff:ff:ff
9d:ff:ff:ff:ff:ff bd:ff:ff:ff:ff:ff
6-bit Hash (in hex)
0x3a
0x3b
0x3c
0x3d
0x3e
0x3f
Hash Decimal
Value
58
59
60
61
62
63
Functional Description
19.3.10 Full Duplex Flow Control
Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
To enable pause frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] asserted) and flow control enable (RCR[FCE]) must be asserted. The FEC detects a pause frame when the fields of the incoming frame match the pause frame specifications, as shown in the table below. In addition, the receive status associated with the frame should indicate that the frame is valid.
Table 19-37. PAUSE Frame Field Specification
48-bit Destination Address
48-bit Source Address
16-bit Type
16-bit Opcode
16-bit PAUSE Duration
0x0180_c200_0001 or Physical Address
Any
0x8808
0x0001
0x0000–0xFFFF
Pause frame detection is performed by the receiver and microcontroller modules. The microcontroller runs an address recognition subroutine to detect the specified pause frame destination address, while the receiver detects the type and opcode pause frame fields. On detection of a pause frame, TCR[GTS] is set by the FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer begins to increment. Note that the pause timer makes use of the transmit backoff timer hardware, which is used for tracking the appropriate collision backoff time in half-duplex mode. The pause timer increments once every slot time, until
OPD[PAUSE_DUR] slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is deasserted allowing MAC data frame transmission to resume. Note that the receive flow control pause (TCR[RFC_PAUSE]) status bit is set while the transmitter is paused due to reception of a pause frame.
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Freescale Semiconductor 19-45
Fast Ethernet Controller (FEC)
To transmit a pause frame, the FEC must operate in full-duplex mode and the user must assert flow control pause (TCR[TFC_PAUSE]). On assertion of transmit flow control pause
(TCR[TFC_PAUSE]), the transmitter sets TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted. On completion of pause frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are cleared internally.
The user must specify the desired pause duration in the OPD register.
Note that when the transmitter is paused due to receiver/microcontroller pause frame detection, transmit flow control pause (TCR[TFC_PAUSE]) still may be asserted and will cause the transmission of a single pause frame. In this case, the EIR[GRA] interrupt will not be asserted.
19.3.11 Inter-Packet Gap (IPG) Time
The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a transmission or after the backoff algorithm completes, the transmitter waits for carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times, it will be ignored and a collision will occur.
The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an inter-packet gap between receive frames is less than 28 bit times, the following frame may be discarded by the receiver.
19.3.12 Collision Handling
If a collision occurs during frame transmission, the Ethernet controller will continue the transmission for at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the collision occurs during the preamble sequence, the JAM pattern will be sent after the end of the preamble sequence.
If a collision occurs within 512 bit times, the retry process is initiated. The transmitter waits a random number of slot times. A slot time is 512 bit times. If a collision occurs after 512 bit times, then no retransmission is performed and the end of frame buffer is closed with a Late Collision
(LC) error indication.
19.3.13 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both of the FIFOs are used and the FEC actually operates in a full-duplex fashion. Both internal and external loopback are configured using combinations of the LOOP and DRT bits in the RCR register and the FDEN bit in the TCR register.
For both internal and external loopback set FDEN = 1.
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Functional Description
For internal loopback set RCR[LOOP] = 1 and RCR[DRT] = 0. ETXEN and ETXER will not assert during internal loopback. During internal loopback, the transmit/receive data rate is higher than in normal operation because the internal system clock is used by the transmit and receive blocks instead of the clocks from the external transceiver. This will cause an increase in the required system bus bandwidth for transmit and receive data being DMA’d to/from external memory. It may be necessary to pace the frames on the transmit side and/or limit the size of the frames to prevent transmit FIFO underrun and receive FIFO overflow.
For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external transceiver for loopback.
19.3.14 Ethernet Error-Handling Procedure
The Ethernet controller reports frame reception and transmission error conditions using the FEC
RxBDs, the EIR register, and the MIB block counters.
19.3.14.1 Transmission Errors
19.3.14.1.1 Transmitter Underrun
If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame are then flushed and closed. The UN bit is set in the EIR. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame.
The “UN” interrupt will be asserted if enabled in the EIMR register.
19.3.14.1.2 Retransmission Attempts Limit Expired
When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and the RL bit is set in the EIR. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame.
The “RL” interrupt will be asserted if enabled in the EIMR register.
19.3.14.1.3 Late Collision
When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and the LC bit is set in the EIR register. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame.
The “LC” interrupt will be asserted if enabled in the EIMR register.
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Fast Ethernet Controller (FEC)
19.3.14.1.4 Heartbeat
Some transceivers have a self-test feature called “heartbeat” or “signal quality error.” To signify a good self-test, the transceiver indicates a collision to the FEC within 4 microseconds after completion of a frame transmitted by the Ethernet controller. This indication of a collision does not imply a real collision error on the network, but is rather an indication that the transceiver still seems to be functioning properly. This is called the heartbeat condition.
If the HBC bit is set in the TCR register and the heartbeat condition is not detected by the FEC after a frame transmission, then a heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets the HB bit in the EIR register, and generates the HBERR interrupt if it is enabled.
19.3.14.2 Reception Errors
19.3.14.2.1Overrun Error
If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV bit in the RxBD. All subsequent data in the frame will be discarded and subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and space is made available.
At this point the receive frame/status word is written into the FIFO with the OV bit set. This frame must be discarded by the driver.
19.3.14.2.2Non-Octet Error (Dribbling Bits)
The Ethernet controller handles up to seven dribbling bits when the receive frame terminates past an non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a
CRC error, then the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, then no error is reported.
19.3.14.2.3CRC Error
When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in the
RxBD. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required.
19.3.14.2.4Frame Length Violation
When the receive frame length exceeds MAX_FL bytes the BABR interrupt will be generated, and the LG bit in the end of frame RxBD will be set. The frame is not truncated unless the frame length exceeds 2032 bytes).
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Functional Description
19.3.14.2.5Truncation
When the receive frame length exceeds 2032 bytes the frame is truncated and the TR bit is set in the receive BD.
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Chapter 20
Watchdog Timer Module
20.1 Introduction
The watchdog timer (WDT) is a 16-bit timer used to help software recover from runaway code.
The watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown by servicing the watchdog.
20.1.1 Low-Power Mode Operation
This subsection describes the operation of the watchdog module in low-power modes and halted mode of operation (by issuing a HALT instruction). Low-power modes are described in
shows the watchdog module operation in the low-power modes, and shows how this module may facilitate exit from each mode.
Table 20-1. Watchdog Module Operation in Low-power Modes
Low-power Mode
Wait
Doze
Stop
Watchdog Operation
Normal if WCR[WAIT] cleared, stopped otherwise
Normal if WCR[DOZE] cleared, stopped otherwise
Stopped
Mode Exit
Upon Watchdog reset
Upon Watchdog reset
No
In wait mode with the watchdog control register’s WAIT bit (WCR[WAIT]) set, watchdog timer operation stops. In wait mode with the WCR[WAIT] bit cleared, the watchdog timer continues to operate normally. In doze mode with the WCR[DOZE] bit set, the watchdog timer module operation stops. In doze mode with the WCR[DOZE] bit cleared, the watchdog timer continues to operate normally. Watchdog timer operation stops in stop mode. When stop mode is exited, the watchdog timer continues to operate in its pre-stop mode state.
In halted mode (entered by issuing a HALT instruction) with the WCR[HALTED] bit set, watchdog timer module operation stops. When halted mode is exited, watchdog timer operation continues from the state it was in before entering halted mode, but any updates made in halted mode remain. If the WCR[HALTED] bit is cleared, the watchdog timer continues to operate normally after executing a HALT instruction. This is a debug feature available for the user
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20-1
Watchdog Timer Module
20.1.2 Block Diagram
Internal Bus
16-bit WCNTR 16-bit WSR
Internal Bus
Clock
Divide by
4096
16-bit Watchdog Counter
Count = 0
Reset
EN
WAIT
DOZE
HALTED
16-bit WMR
Load Counter
Internal Bus
Figure 20-1. Watchdog Timer Block Diagram
20.2 Memory Map/Register Definition
This subsection describes the memory map and registers for the watchdog timer. The watchdog timer has a IPSBAR offset for base address of 0x14_0000. Refer to
for an overview of the watchdog memory map.
Table 20-2. Watchdog Timer Module Memory Map
IPSBAR Offset [31:24] [23:16] [15:8] [7:0] Access
1
0x14_0000 Watchdog Control Register (WCR) Watchdog Modulus Register (WMR) S
0x14_0004 Watchdog Count Register (WCNTR) Watchdog Service Register (WSR) S/U
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.
20.2.1 Register Description
The watchdog timer programming model consists of these registers:
• Watchdog control register (WCR), which configures watchdog timer operation
• Watchdog modulus register (WMR), which determines the timer modulus reload value
• Watchdog count register (WCNTR), which provides visibility to the watchdog counter value
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20-2 Freescale Semiconductor
Memory Map/Register Definition
• Watchdog service register (WSR), which requires a service sequence to prevent reset
20.2.1.1 Watchdog Control Register (WCR)
The 16-bit WCR configures watchdog timer operation.
15
R 0
W
Reset 0
Address
Bits
15–4
3
2
1
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4 3 2 1 0
0 WAIT DOZE HALTED EN
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x14_0000
Figure 20-2. Watchdog Control Register (WCR)
1
Table 20-3. WCR Field Descriptions
1 1 1
Name Description
—
WAIT
Reserved, should be cleared.
Wait mode bit. Controls the function of the watchdog timer in wait mode. Once written, the
WAIT bit is not affected by further writes except in halted mode. Reset sets WAIT.
0 Watchdog timer not affected in wait mode
1 Watchdog timer stopped in wait mode
DOZE
HALTED Halted mode bit. Controls the function of the watchdog timer in halted mode. Once written, the HALTED bit is not affected by further writes except in halted mode.
During halted mode, watchdog timer registers can be written and read normally. When halted mode is exited, timer operation continues from the state it was in before entering halted mode, but any updates made in halted mode remain. If a write-once register is written for the first time in halted mode, the register is still writable when halted mode is exited.
0 Watchdog timer not affected in halted mode
1 Watchdog timer stopped in halted mode
Note: Changing the HALTED bit from 1 to 0 during halted mode starts the watchdog timer.
Changing the HALTED bit from 0 to 1 during halted mode stops the watchdog timer.
EN
Doze mode bit. Controls the function of the watchdog timer in doze mode. Once written, the DOZE bit is not affected by further writes except in halted mode. Reset sets DOZE.
0 Watchdog timer not affected in doze mode
1 Watchdog timer stopped in doze mode
Watchdog enable bit. Enables the watchdog timer. Once written, the EN bit is not affected by further writes except in halted mode. When the watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state.
0 Watchdog timer disabled
1 Watchdog timer enabled
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Watchdog Timer Module
20.2.1.2 Watchdog Modulus Register (WMR)
15
R
W
Reset 1
Address
Bits
15–0
14 13 12 11 10 9 8
WM
7 6 5 4 3 2 1 0
1
Name
WM
1 1 1 1 1 1 1 1 1 1
IPSBAR + 0x14_0002
Figure 20-3. Watchdog Modulus Register (WMR)
1
Table 20-4. WMR Field Descriptions
1 1 1
Description
Watchdog modulus. Contains the modulus that is reloaded into the watchdog counter by a service sequence. Once written, the WM[15:0] field is not affected by further writes except in halted mode. Writing to WMR immediately loads the new modulus value into the watchdog counter. The new value is also used at the next and all subsequent reloads.
Reading WMR returns the value in the modulus register.
Reset initializes the WM[15:0] field to 0xFFFF.
Note: The prescaler counter is reset anytime a new value is loaded into the watchdog counter and also during reset.
20.2.1.3 Watchdog Count Register (WCNTR)
15
R
W
Reset 1
Address
Bits
15–0
14 13 12 11 10 9 8
WC
7 6 5 4 3 2 1 0
1
Name
WC
1 1 1 1 1 1 1 1 1 1
IPSBAR + 0x14_0004
Figure 20-4. Watchdog Count Register (WCNTR)
1
Table 20-5. WCNTR Field Descriptions
1 1 1
Description
Watchdog count field. Reflects the current value in the watchdog counter. Reading the
16-bit WCNTR with two 8-bit reads is not guaranteed to return a coherent value. Writing to
WCNTR has no effect, and write cycles are terminated normally.
20.2.1.4 Watchdog Service Register (WSR)
When the watchdog timer is enabled, writing 0x5555 and then 0xAAAA to WSR before the watchdog counter times out prevents a reset. If WSR is not serviced before the timeout, the watchdog timer sends a signal to the reset controller module that sets the RSR[WDR] bit and asserts a system reset.
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20-4 Freescale Semiconductor
Memory Map/Register Definition
Both writes must occur in the order listed before the timeout, but any number of instructions can be executed between the two writes. However, writing any value other than 0x5555 or 0xAAAA to WSR resets the servicing sequence, requiring both values to be written to keep the watchdog timer from causing a reset.
15
R
W
Reset 0
Address
14
0
13 12 11 10 9 8
WS
7 6 5 4 3
0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x0014_0006
Figure 20-5. Watchdog Service Register (WSR)
0
2
0
1
0
0
0
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Watchdog Timer Module
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Freescale Semiconductor
Chapter 21
Programmable Interrupt Timer Modules
(PIT0–PIT3)
21.1 Introduction
This chapter describes the operation of the four programmable interrupt timer modules,
PIT0–PIT3.
21.1.1 Overview
The PIT is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention. The timer can either count down from the value written in the modulus register, or it can be a free-running down-counter.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module” ) prior to configuring the PIT modules.
21.1.2 Block Diagram
Internal Bus
16-bit PCNTRn
16-bit PIT Counter
Internal Bus
Clock (f sys/2
)
Prescaler
EN
PRE[3:0]
DOZE
DBG
OVW
16-bit PMRn
COUNT = 0
Load
Counter
RLD
PIF
PIE
To Interrupt
Controller
Internal Bus
Figure 21-1. PIT Block Diagram
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Freescale Semiconductor 21-1
Programmable Interrupt Timer Modules (PIT0–PIT3)
21.1.3 Low-Power Mode Operation
This subsection describes the operation of the PIT modules in low-power modes and debug mode
of operation. Low-power modes are described in the Power Management Module. Table 21-1
shows the PIT module operation in low-power modes, and how it can exit from each mode.
NOTE
The low-power interrupt control register (LPICR) in the System
Control Module specifies the interrupt level at or above which the device can be brought out of a low-power mode.
Table 21-1. PIT Module Operation in Low-power Modes
Low-power Mode
Wait
Doze
Stop
Debug
PIT Operation Mode Exit
Normal N/A
Normal if PCSRn[DOZE] cleared, stopped otherwise
Any IRQn Interrupt at or above level in LPICR
Stopped
Normal if PCSRn[DBG] cleared, stopped otherwise
No
No. Any IRQn Interrupt will be serviced upon normal exit from debug mode
In wait mode, the PIT module continues to operate as in run mode and can be configured to exit the low-power mode by generating an interrupt request. In doze mode with the PCSRn[DOZE] bit set, PIT module operation stops. In doze mode with the PCSRn[DOZE] bit cleared, doze mode does not affect PIT operation. When doze mode is exited, the PIT continues to operate in the state it was in prior to doze mode. In stop mode, the system clock is absent, and PIT module operation stops.
In debug mode with the PCSRn[DBG] bit set, PIT module operation stops. In debug mode with the PCSRn[DBG] bit cleared, debug mode does not affect PIT operation. When debug mode is exited, the PIT continues to operate in its pre-debug mode state, but any updates made in debug mode remain.
21.2 Memory Map/Register Definition
This section contains a memory map, shown in
, and describes the register structure for
PIT0–PIT3.
Table 21-2. Programmable Interrupt Timer Modules Memory Map
IPSBAR Offset
0x15_0000
0x15_0004
[31:24] [23:16]
PIT Control and Status Register
(PCSR0)
PIT Count Register (PCNTR0)
[15:8] [7:0]
PIT Modulus Register (PMR0)
Reserved
2
Access
1
S
S/U
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21-2 Freescale Semiconductor
Memory Map/Register Definition
Table 21-2. Programmable Interrupt Timer Modules Memory Map (Continued)
IPSBAR Offset [31:24] [23:16] [15:8] [7:0] Access
1
0x15_0008–
0x15_FFFF
0x16_0000
Reserved —
PIT Control and Status Register
(PCSR1)
PIT Modulus Register (PMR1) S
0x16_0004
0x16_0008–
0x16_FFFF
0x17_0000
PIT Count Register (PCNTR1)
Reserved
Reserved
2
S/U
—
PIT Control and Status Register
(PCSR2)
PIT Modulus Register (PMR2) S
0x17_0004
0x17_0008–
0x17_FFFF
0x18_0000
PIT Count Register (PCNTR2)
Reserved
Reserved
2
S/U
—
0x18_0004
PIT Control and Status Register
(PCSR3)
PIT Count Register (PCNTR3)
PIT Modulus Register (PMR3)
Reserved
2
S
S/U
0x18_0008–
0x18_FFFF
Reserved —
1
2
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.
Accesses to reserved address locations have no effect and result in a cycle termination transfer error.
21.2.1 Register Description
The PIT programming model consists of these registers:
• The PIT control and status register (PCSRn) configures the timer’s operation.
• The PIT modulus register (PMRn) determines the timer modulus reload value.
• The PIT count register (PCNTRn) provides visibility to the counter value.
21.2.1.1 PIT Control and Status Register (PCSRn)
15
R 0
W
Reset 0
Address
14
0
13
0
12
0
11 10
PRE
9 8 7 6 5 4 3 2 1 0
0 DOZE DBG OVW PIE PIF RLD EN
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x0015_0000 (PIT0); IPSBAR + 0x0016_0000 (PIT1);
IPSBAR + 0x0017_0000 (PIT2); IPSBAR + 0x0018_0000 (PIT3)
Figure 21-2. PIT Control and Status Register (PCSRn)
0 0 0
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Freescale Semiconductor 21-3
Programmable Interrupt Timer Modules (PIT0–PIT3)
Bits
15–12
11–8
Name
—
PRE
Table 21-3. PCSRn Field Descriptions
Description
Reserved, should be cleared.
Prescaler. The read/write prescaler bits select the system clock divisor to generate the PIT clock. To accurately predict the timing of the next count, change the PRE[3:0] bits only when the enable bit (EN) is clear. Changing PRE[3:0] resets the prescaler counter. System reset and the loading of a new value into the counter also reset the prescaler counter.
Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN bit stops the prescaler counter.
PRE
0000
0001
0010
...
1101
1110
1111
System Clock Divisor
2
0
2
1
2
2
...
2 13
2
14
2
15
7
6
5
4
3
2
—
DOZE
DBG
OVW
PIE
PIF
Reserved, should be cleared.
Doze mode bit. The read/write DOZE bit controls the function of the PIT in doze mode.
Reset clears DOZE.
0 PIT function not affected in doze mode
1 PIT function stopped in doze mode
When doze mode is exited, timer operation continues from the state it was in before entering doze mode.
Debug mode bit. Controls the function of the PIT in debug mode. Reset clears DBG. During debug mode, register read and write accesses function normally. When debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain.
0 PIT function not affected in debug mode
1 PIT function stopped in debug mode
Note: Changing the DBG bit from 1 to 0 during debug mode starts the PIT timer. Likewise, changing the DBG bit from 0 to 1 during debug mode stops the PIT timer.
Overwrite. Enables writing to PMRn to immediately overwrite the value in the PIT counter.
0 Value in PMRn replaces value in PIT counter when count reaches 0x0000.
1 Writing PMRn immediately replaces value in PIT counter.
PIT interrupt enable. This read/write bit enables the PIF flag to generate interrupt requests.
0 PIF interrupt requests disabled
1 PIF interrupt requests enabled
PIT interrupt flag. This read/write bit is set when the PIT counter reaches 0x0000. Clear
PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF.
0 PIT count has not reached 0x0000.
1 PIT count has reached 0x0000.
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21-4 Freescale Semiconductor
Bits
1
0
Memory Map/Register Definition
Name
RLD
EN
Table 21-3. PCSRn Field Descriptions (Continued)
Description
Reload bit. The read/write reload bit enables loading the value of PMRn into the PIT counter when the count reaches 0x0000.
0 Counter rolls over to 0xFFFF on count of 0x0000
1 Counter reloaded from PMRn on count of 0x0000
PIT enable bit. Enables PIT operation. When the PIT is disabled, the counter and prescaler are held in a stopped state. This bit is read anytime, write anytime.
0 PIT disabled
1 PIT enabled
21.2.1.2 PIT Modulus Register (PMRn)
The 16-bit read/write PMRn contains the timer modulus value that is loaded into the PIT counter when the count reaches 0x0000 and the PCSRn[RLD] bit is set.
When the PCSRn[OVW] bit is set, PMRn is transparent, and the value written to PMRn is immediately loaded into the PIT counter. The prescaler counter is reset anytime a new value is loaded into the PIT counter and also during reset. Reading the PMRn returns the value written in the modulus latch. Reset initializes PMRn to 0xFFFF.
15
R
W
Reset 1
Address
14
1
13 12 11 10 9 8
PM
7 6 5 4 3
1 1 1 1 1 1 1 1 1 1 1
IPSBAR + 0x0015_0002 (PIT0);IPSBAR + 0x0016_0002 (PIT1);
IPSBAR + 0x0017_0002 (PIT2); IPSBAR + 0x0018_0002 (PIT3)
Figure 21-3. PIT Modulus Register (PMRn)
2
1
1
1
0
1
21.2.1.3 PIT Count Register (PCNTRn)
The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two
8-bit reads is not guaranteed to be coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally.
15
R
W
Reset 1
Address
14
1
13 12 11 10 9 8
PC
7 6 5 4 3 2
1 1 1 1 1 1 1 1 1 1 1
IPSBAR + 0x0015_0004 (PIT0), IPSBAR + 0x0016_0004 (PIT1),
IPSBAR + 0x0017_0004 (PIT2), IPSBAR + 0x0018_0004 (PIT3)
Figure 21-4. PIT Count Register (PCNTR)
1
1
1
0
1
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Freescale Semiconductor 21-5
Programmable Interrupt Timer Modules (PIT0–PIT3)
21.3 Functional Description
This section describes the PIT functional operation.
21.3.1 Set-and-Forget Timer Operation
This mode of operation is selected when the RLD bit in the PCSR register is set.
When the PIT counter reaches a count of 0x0000, the PIF flag is set in PCSRn. The value in the modulus register is loaded into the counter, and the counter begins decrementing toward 0x0000.
If the PCSRn[PIE] bit is set, the PIF flag issues an interrupt request to the CPU.
When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000.
PIT CLOCK
COUNTER
MODULUS
PIF
0x0002 0x0001
0x0005
0x0000 0x0005
Figure 21-5. Counter Reloading from the Modulus Latch
21.3.2 Free-Running Timer Operation
This mode of operation is selected when the PCSRn[RLD] bit is clear. In this mode, the counter rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement.
When the counter reaches a count of 0x0000, the PCSRn[PIF] flag is set. If the PCSRn[PIE] bit is set, the PIF flag issues an interrupt request to the CPU.
When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000.
PIT CLOCK
COUNTER
MODULUS
PIF
0x0002 0x0001
0x0005
0x0000 0xFFFF
Figure 21-6. Counter in Free-Running Mode
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21-6 Freescale Semiconductor
Functional Description
21.3.3 Timeout Specifications
The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the internal bus clock period as selected by the PCSRn[PRE] bits. The PMRn[PM] bits select the timeout period.
Timeout period =
21.3.4 Interrupt Operation
Table 21-4 shows the interrupt request generated by the PIT.
Table 21-4. PIT Interrupt Requests
Interrupt Request
Timeout
Flag
PIF
Enable Bit
PIE
The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR.
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Programmable Interrupt Timer Modules (PIT0–PIT3)
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Chapter 22
DMA Timers (DTIM0–DTIM3)
22.1 Introduction
This chapter describes the configuration and operation of the four Direct Memory Access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or triggers.
Additionally, programming examples are included.
NOTE
The designation “n” is used throughout this section to refer to registers or signals associated with one of the four identical timer modules—DTIM0, DTIM1, DTIM2, or DTIM3.
22.1.1 Overview
Each DMA timer module has a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clocking source using the
DTINn signal. If the system clock is selected, it can be divided by 16 or 1. The selected clock source is routed to an 8-bit programmable prescaler that clocks the actual DMA timer counter register (DTCNn). Using the DTMRn, DTXMRn, DTCRn, and DTRRn registers, the DMA timer may be configured to assert an output signal, generate an interrupt, or initiate a DMA transfer on a particular event.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module” ) prior to configuring the DMA Timers.
is a block diagram of one of the four identical timer modules.
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22-1
DMA Timers (DTIM0–DTIM3)
Internal Bus Clock
(÷1 or ÷16 )
DTINn
Capture
Detection
DMA Timer
Clock
Generator clock
15 0
DMA Timer Mode Register (DTMRn)
Prescaler Mode Bits
7 0
DMA Timer Extended Mode
Register (DTXMRn)
Divider
31
DMA Timer Counter Register (DTCNn)
(contains incrementing value)
0
31
DMA Timer Capture Register (DTCRn)
(latches DTCN value when triggered by DTINn)
0 31
DMA Timer Reference Register (DTRRn)
(reference value for comparison with DTCN)
0
7
DMA Timer Event Register (DTERn)
(indicates capture or when DTCN = DTRRn)
0
DTOUTn
To Interrupt controller
DREQn
Figure 22-1. DMA Timer Block Diagram
22.1.2 Features
Each DMA timer module has the following features:
• Maximum timeout period of 234,562 seconds at 75 MHz (~5 hours)
• 13-ns resolution at 75 MHz
• Programmable sources for the clock input, including external clock
• Programmable prescaler
• Input-capture capability with programmable trigger edge on input pin
• Programmable mode for the output pin on reference compare
• Free run and restart modes
• Programmable interrupt or DMA request on input capture or reference-compare
22.2 Memory Map/Register Definition
The following features are programmable through the timer registers, shown in Table 22-1 :
22.2.1 Prescaler
The prescaler clock input is selected from system clock (divided by 1 or 16) or from the corresponding timer input, DTINn. DTINn is synchronized to the system clock. The
MCF5271 Reference Manual, Rev. 2
22-2 Freescale Semiconductor
Memory Map/Register Definition synchronization delay is between two and three system clocks. The corresponding DTMRn[CLK] selects the clock input source. A programmable prescaler divides the clock input by values from
1 to 256. The prescaler output is an input to the 32-bit counter, DTCNn.
22.2.2 Capture Mode
Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value when the corresponding input capture edge detector senses a defined DTINn transition. The capture edge bits (DTMRn[CE]) select the type of transition that triggers the capture and sets the timer event register capture event bit, DTERn[CAP]. If DTERn[CAP] is set and DTXMRn[DMAEN] is one, a DMA request is asserted. If DTERn[CAP] is set and DTXMRn[DMAEN] is zero, an interrupt is asserted.
22.2.3 Reference Compare
Each DMA timer can be configured to count up to a reference value, at which point DTERn[REF] is set. If DTMRn[ORRI] is one and DTXMRn[DMAEN] is zero, an interrupt is asserted. If
DTMRn[ORRI] is one and DTXMRn[DMAEN] is one, a DMA request is asserted. If the free run/restart bit DTMRn[FRR] is set, a new count starts. If it is clear, the timer keeps running.
22.2.4 Output Mode
When a timer reaches the reference value selected by DTRR, it can send an output signal on
DTOUTn. DTOUTn can be an active-low pulse or a toggle of the current output as selected by the
DTMRn[OM] bit.
22.2.5 Memory Map
The timer module registers, shown in
Table 22-1 , can be modified at any time.
Table 22-1. DMA Timer Module Memory Map
IPSBAR
Offset
0x00_0400
0x00_0404
0x00_0408
0x00_040C
0x00_0440
[31:24] [23:16] [15:8]
DMA Timer0 Mode Register (DTMR0) DMA Timer0
Extended Mode
Register (DTXMR0)
DMA Timer0 Reference Register (DTRR0)
DMA Timer0 Capture Register (DTCR0)
DMA Timer0 Counter Register (DTCN0)
DMA Timer1 Mode Register (DTMR1) DMA Timer1
Extended Mode
Register (DTXMR1)
[7:0]
DMA Timer0 Event
Register (DTER0)
DMA Timer1 Event
Register (DTER1)
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Freescale Semiconductor 22-3
DMA Timers (DTIM0–DTIM3)
Table 22-1. DMA Timer Module Memory Map (Continued)
IPSBAR
Offset
0x00_0444
0x00_0448
0x00_044C
0x00_0480
[31:24] [23:16] [15:8]
0x00_0484
0x00_0488
0x00_048C
0x00_04C0
0x00_04C4
0x00_04C8
0x00_04CC
[7:0]
DMA Timer1 Reference Register (DTRR1)
DMA Timer1 Capture Register (DTCR1)
DMA Timer1 Counter Register (DTCN1)
DMA Timer2 Mode Register (DTMR2) DMA Timer2
Extended Mode
Register (DTXMR2)
DMA Timer2 Reference Register (DTRR2)
DMA Timer2 Capture Register (DTCR2)
DMA Timer2 Counter Register (DTCN2)
DMA Timer3 Mode Register (DTMR3) DMA Timer3
Extended Mode
Register (DTXMR3)
DMA Timer3 Reference Register (DTRR3)
DMA Timer3 Capture Register (DTCR3)
DMA Timer3 Counter Register (DTCN3)
DMA Timer2 Event
Register (DTER2)
DMA Timer3 Event
Register (DTER3)
22.2.6 DMA Timer Mode Registers (DTMRn)
DTMRs, shown in Figure 22-2 , program the prescaler and various timer modes.
15
R
W
Reset 0
Address
Bits
15–8
7–6
14 13 12
PS
11 10 9 8 7
CE
6 5 4 3
OM ORRI FRR
2
CLK
1 0
RST
0
Name
PS
CE
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_0400 (DTMR0); IPSBAR + 0x00_0440 (DTMR1);
IPSBAR + 0x00_0480 (DTMR2); IPSBAR + 0x00_04C0 (DTMR3)
Figure 22-2. DMA Timer Mode Registers (DTMRn)
Table 22-2. DTMRn Field Descriptions
0 0 0
Description
Prescaler value. The prescaler is programmed to divide the clock input (system clock/(16 or 1) or clock on DTINn) by values from 1 (PS = 0x00) to 256 (PS = 0xFF).
Capture edge.
00 Disable capture event output
01 Capture on rising edge only
10 Capture on falling edge only
11 Capture on any edge
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22-4 Freescale Semiconductor
Bits
5
4
3
2–1
0
Memory Map/Register Definition
Name
OM
ORRI
FRR
CLK
RST
Table 22-2. DTMRn Field Descriptions (Continued)
Description
Output mode.
0 Active-low pulse for one system clock cycle (13-ns resolution at 75 MHz).
1 Toggle output.
Output reference request, interrupt enable. If ORRI is set when DTERn[REF] = 1, a DMA request or an interrupt occurs, depending on the value of DTXMRn[DMAEN] (DMA request if =1, interrupt if =0).
0 Disable DMA request or interrupt for reference reached (does not affect DMA request or interrupt on capture function).
1 Enable DMA request or interrupt upon reaching the reference value.
Free run/restart
0 Free run. Timer count continues to increment after reaching the reference value.
1 Restart. Timer count is reset immediately after reaching the reference value.
Input clock source for the timer
00 Stop count
01 System clock divided by 1
10 System clock divided by 16. Note that this clock source is not synchronized with the timer; thus successive time-outs may vary slightly.
11 DTINn pin (falling edge)
Reset timer. Performs a software timer reset similar to an external reset, although other register values can still be written while RST = 0. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless the timer is enabled.
0 Reset timer (software reset)
1 Enable timer
22.2.7 DMA Timer Extended Mode Registers (DTXMRn)
DTXMRn, shown in
Figure 22-3 , program DMA request and increment modes for the timers.
Bits
7
W
Reset
7
R DMAEN
0
6
0
5
0
4
0
3
0
2
0
1
0
0
MODE16
0 0 0 0 0 0 0
Address IPSBAR + 0x00_0402 (DTXMR0); IPSBAR + 0x00_0442 (DTXMR1);
IPSBAR + 0x00_0482 (DTXMR2); IPSBAR + 0x00_04C2 (DTXMR3)
Figure 22-3. DMA Timer Extended Mode Registers (DTXMRn)
Table 22-3. DTXMR n Field Descriptions
Name Description
DMAEN DMA request. Enables DMA request output on counter reference match or capture edge event.
0 DMA request disabled
1 DMA request enabled
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Freescale Semiconductor 22-5
DMA Timers (DTIM0–DTIM3)
Bits
6–1
0
Table 22-3. DTXMR n Field Descriptions (Continued)
Name Description
— Reserved, should be cleared.
MODE16 Selects the increment mode for the timer. MODE16 = 1 is intended to exercise the upper bits of the 32-bit timer in diagnostic software without requiring the timer to count through its entire dynamic range. When set, the counter’s upper 16 bits mirror its lower 16 bits.
All 32 bits of the counter are still compared to the reference value.
0 Increment timer by 1
1 Increment timer by 65,537
22.2.8 DMA Timer Event Registers (DTERn)
DTERn, shown in Figure 22-4 , reports capture or reference events by setting DTERn[CAP] or
DTERn[REF]. This reporting is done regardless of the corresponding DMA request or interrupt enable values, DTXMRn[DMAEN] and DTMRn[ORRI,CE].
Writing a 1 to either DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect bit value); both bits can be cleared at the same time. If configured to generate an interrupt request, the REF and CAP bits must be cleared early in the interrupt service routine so the timer module can negate the interrupt request signal to the interrupt controller. If configured to generate a DMA request, the processing of the DMA data transfer automatically clears both the REF and CAP flags via the internal DMA ACK signal.
R
W
Reset
7
0
6
0
5
0
4
0
3
0
2
0
1
REF w1c
0 0 0 0 0 0 0
Address IPSBAR + 0x00_0403 (DTER0); IPSBAR + 0x00_0443 (DTER1);
IPSBAR + 0x00_0483 (DTER2); IPSBAR + 0x00_04C3 (DTER3)
Figure 22-4. DMA Timer Event Registers (DTERn)
0
CAP w1c
0
22-6
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Bits
7–2
1
0
Name
—
REF
Memory Map/Register Definition
Table 22-4. DTERn Field Descriptions
Description
Reserved, should be cleared.
Output reference event. The counter value, DTCNn, equals the reference value, DTRRn.
Writing a one to REF clears the event condition. Writing a zero has no effect.
REF DTMRn[ORRI] DTXMRn[DMAEN]
1
1
0
1
1
X
0
0
1
1
X
0
1
0
1
No event
No request asserted
No request asserted
Interrupt request asserted
DMA request asserted
CAP Capture event. The counter value has been latched into DTCRn. Writing a one to CAP clears the event condition. Writing a zero has no effect.
CAP DTMRn[CE]
1
1
1
1
1
1
1
0
1
X
00
00
01
01
10
10
11
11
DTXMRn
[DMAEN]
1
0
1
0
1
1
0
X
0
No event
Disable capture event output
Disable capture event output
Capture on rising edge & trigger interrupt
Capture on rising edge & trigger DMA
Capture on falling edge & trigger interrupt
Capture on falling edge & trigger DMA
Capture on any edge & trigger interrupt
Capture on any edge & trigger DMA
22.2.9 DMA Timer Reference Registers (DTRRn)
Each DTRRn, shown in Figure 22-5
, contains the reference value compared with the respective free-running timer counter (DTCNn) as part of the output-compare function. The reference value is not matched until DTCNn equals DTRRn, and the prescaler indicates that DTCNn should be incremented again. Thus, the reference register is matched after DTRRn+1 time intervals.
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MCF5271 Reference Manual, Rev. 2
22-7
DMA Timers (DTIM0–DTIM3)
31
R
W
Reset 1
15
R
W
Reset 1
Address
30
1
14
29
1
13
28
1
12
27
1
11
26
1
10
25
1
9
24
REF
23
1 1
8
REF
7
22
1
6
21
1
5
20
1
4
19
1
3
18
1
2
17
1
1
16
1
0
1 1 1 1 1 1 1 1 1 1 1 1
IPSBAR + 0x00_0404 (DTRR0); IPSBAR + 0x00_0444 (DTRR1);
IPSBAR + 0x00_0484 (DTRR2); IPSBAR + 0x00_04C4 (DTRR3)
Figure 22-5. DMA Timer Reference Registers (DTRRn)
1 1 1
22.2.10 DMA Timer Capture Registers (DTCRn)
Each DTCRn, shown in Figure 22-6 , latches the corresponding DTCNn value during a capture
operation when an edge occurs on DTINn, as programmed in DTMRn. The system clock is assumed to be the clock source. DTINn cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation will result if DTINn is set as the clock source when the input capture mode is used.
31
R
W
Reset 0
15
R
W
Reset 0
Address
30
0
14
29
0
13
28
0
12
27
0
11
26 25 24 23 22 21
CAP (32-bit capture counter value)
0 0 0 0 0 0
10 9 8 7 6 5
CAP (32-bit capture counter value)
20
0
4
19
0
3
18
0
2
17
0
1
16
0
0
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_0408 (DTCR0); IPSBAR + 0x00_0448 (DTCR1);
IPSBAR + 0x00_0488 (DTCR2); IPSBAR + 0x00_04C8 (DTCR3)
Figure 22-6. DMA Timer Capture Registers (DTCRn)
0 0 0
22.2.11 DMA Timer Counters (DTCNn)
The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Writing to DTCNn, shown in
, clears it. The timer counter increments on the clock source rising edge (system clock ÷ 1, system clock ÷ 16, or DTINn).
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22-8 Freescale Semiconductor
Using the DMA Timer Modules
31
R
W
Reset 0
15
R
W
Reset 0
Address
30
0
14
29
0
13
28
0
12
27 26 25 24 23 22 21
CNT (32-bit timer counter value count)
20
0
11
0 0 0 0 0 0
10 9 8 7 6 5
CNT (32-bit timer counter value count)
0
4
19
0
3
18
0
2
17
0
1
16
0
0
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_040C (DTCN0); IPSBAR + 0x00_044C (DTCN1);
IPSBAR + 0x00_048C (DTCN2); IPSBAR + 0x00_04CC (DTCN3)
Figure 22-7. DMA Timer Counters (DTCNn)
0 0 0
22.3 Using the DMA Timer Modules
The general-purpose timer modules are typically used in the following manner, though this is not necessarily the program order in which these actions must occur:
• The DTMRn and DTXMRn registers are configured for the desired function and behavior.
— Count and compare to a reference value stored in the DTRRn register
— Capture the timer value on an edge detected on DTINn
— Configure DTOUTn output mode
— Increment counter by 1 or by 65,537 (16-bit mode)
— Enable/disable interrupt or DMA request on counter reference match or capture edge
• The DTMRn[CLK] register is configured to select the clock source to be routed to the prescaler.
— System clock (can be divided by 1 or 16)
— DTINn, the maximum value of DTINn is 1/5 of the system clock, as described in the
MCF5271 Electrical Characteristics.
NOTE
DTINn may not be configured as a clock source when the timer capture mode is selected or indeterminate operation will result.
• The 8-bit DTMRn[PS] prescaler value is set
• Using DTMRn[RST] the counter is cleared and started
• Timer events are either handled with an interrupt service routine, a DMA request, or by a software polling mechanism
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Freescale Semiconductor 22-9
DMA Timers (DTIM0–DTIM3)
22.3.1 Code Example
The following code provides an example of how to initialize DMA Timer0 and how to use the timer for counting time-out periods.
DTMR0 EQU IPSBARx+0x400;Timer0 mode register
DTMR1 EQU IPSBARx+0x440 ;Timer1 mode register
DTRR0 EQU IPSBARx+0x404 ;Timer0 reference register
DTRR1 EQU IPSBARx+0x444 ;Timer1 reference register
DTCR0 EQU IPSBARx+0x408 ;Timer0 capture register
DTCR1 EQU IPSBARx+0x448 ;Timer1 capture register
DTCN0 EQU IPSBARx+0x40C ;Timer0 counter register
DTCN1 EQU IPSBARx+0x44C ;Timer1 counter register
DTER0 EQU IPSBARx+0x403 ;Timer0 event register
DTER1 EQU IPSBARx+0x443 ;Timer1 event register
* TMR0 is defined as: *
*[PS] = 0xFF, divide clock by 256
*[CE] = 00
*[OM] = 0 disable capture event output output=active-low pulse
*[ORRI] = 0,
*[FRR] = 1,
*[CLK] = 10,
*[RST] = 0, disable ref. match output restart mode enabled system clock/16 timer0 disabled move.w #0xFF0C,D0 move.w D0,TMR0 move.l #0x0000,D0;writing to the timer counter with any move.l DO,TCN0 ;value resets it to zero move.l #AFAF,DO ;set the timer0 reference to be move.l #D0,TRR0 ;defined as 0xAFAF
The simple example below uses Timer0 to count time-out loops. A time-out occurs when the reference value, 0xAFAF, is reached. timer0_ex clr.l DO clr.l D1 clr.l D2 move.l #0x0000,D0 move.l D0,TCN0 move.b #0x03,D0 move.b D0,TER0 move.w TMR0,D0 bset #0,D0 move.w D0,TMR0
TMR0[RST]
T0_LOOP move.b TER0,D1
;reset the counter to 0x0000
;writing ones to TER0[REF,CAP]
;clears the event flags
;save the contents of TMR0 while setting
;the 0 bit. This enables timer 0 and starts counting
;load the value back into the register, setting
;load TER0 and see if
MCF5271 Reference Manual, Rev. 2
22-10 Freescale Semiconductor
Using the DMA Timer Modules btst #1,D1 beq T0_LOOP addi.l #1,D2 cmp.l #5,D2 beq T0_FINISH back.
move.b #0x02,D0 flag move.b D0,TER0 jmp T0_LOOP
T0_FINISH
HALT
;TER0[REF] has been set
;Increment D2
;Did D2 reach 5? (i.e. timer ref has timed)
;If so, end timer0 example. Otherwise jump
;writing one to TER0[REF] clears the event
;End processing. Example is finished
22.3.2 Calculating Time-Out Values
The formula below determines time-out periods for various reference values:
Time-out period = (1/clock frequency) x (1 or 16) x (DTMRn[PS] + 1) x (DTRRn[REF] + 1)
When calculating time-out periods, add 1 to the prescaler to simplify calculating, because
DTMRn[PS] = 0x00 yields a prescaler of 1 and DTMRn[PS] = 0xFF yields a prescaler of 256.
For example, if a 75-MHz timer clock is divided by 16, DTMRn[PS] = 0x7F, and the timer is referenced at 0x11E1A (73,242 decimal), the time-out period is as follows:
Time-out period = [1/(75 x 10
6
)] x (16) x (127 + 1) x (73,242 + 1) = 2.00 s
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
22-11
DMA Timers (DTIM0–DTIM3)
22-12
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Chapter 23
Queued Serial Peripheral Interface (QSPI)
Module
23.1 Introduction
This chapter describes the queued serial peripheral interface (QSPI) module. Following a feature set overview is a description of operation including details of the QSPI’s internal RAM organization. The chapter concludes with the programming model and a timing diagram.
23.1.1 Overview
The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address and data registers.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module” ) prior to configuring the QSPI Module.
23.1.2 Features
• Programmable queue to support up to 16 transfers without user intervention
• Supports transfer sizes of 8 to 16 bits in 1-bit increments
• Four peripheral chip-select lines for control of up to 15 devices
• Baud rates from 147.1 Kbps to 18.75 Mbps at 75 MHz
• Programmable delays before and after transfers
• Programmable QSPI clock phase and polarity
• Supports wraparound mode for continuous transfers
23.1.3 Module Description
The QSPI module communicates with the integrated ColdFire CPU using internal memory mapped registers starting at IPSBAR + 0x340. See
Section 23.3, “Memory Map/Register
.” A block diagram of the QSPI module is shown in Figure 23-1
.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 23-1
Queued Serial Peripheral Interface (QSPI) Module
23.1.3.1 Interface and Signals
The module provides access to as many as 15 devices with a total of seven signals: QSPI_DOUT,
QSPI_DIN, QSPI_CLK, QSPI_CS0, QSPI_CS1, QSPI_CS2, and QSPI_CS3.
Peripheral chip-select signals, QSPI_CS[3:0], are used to select an external device as the source or destination for serial data transfer. Signals are asserted at a logic level corresponding to the value of the QSPI_CS[3:0] bits in the command RAM whenever a command in the queue is executed. More than one chip-select signal can be asserted simultaneously.
Although QSPI_CS[3:0] will function as simple chip selects in most applications, up to 15 devices can be selected by decoding them with an external 4-to-16 decoder.
Queue Control
Block
Queue
Pointer
4
Comparator
End Queue
Pointer
Control Logic
Status
Regs
Control
Regs
Done
QSPI
Address
Register
4
4
Chip
Select
Logic
Array 4
Command
80-Byte
QSPI
RAM msb lsb
8/16 Bit Shift Reg.
Rx/Tx Data Reg.
QSPI
Data
Register
QSPI_DIN
QSPI_DOUT
4
Delay
Counter
QSPI_CS[3:0]
Internal Bus
Internal Bus
Clock (f sys/2
)
Divide by 2
Baud Rate
Generator
Figure 23-1. QSPI Block Diagram
QSPI_CLK
Table 23-1. QSPI Input and Output Signals and Functions
Signal Name
QSPI Data Output (QSPI_DOUT)
QSPI Data Input (QSPI_DIN)
Hi-Z or Actively Driven
Configurable
N/A
Function
Serial data output from QSPI
Serial data input to QSPI
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23-2 Freescale Semiconductor
Operation
Table 23-1. QSPI Input and Output Signals and Functions (Continued)
Signal Name Hi-Z or Actively Driven
Serial Clock (QSPI_CLK) Actively driven
Peripheral Chip Selects (QSPI_CS[3:0]) Actively driven
Function
Clock output from QSPI
Peripheral selects
23.1.4 Internal Bus Interface
Because the QSPI module only operates in master mode, the master bit in the QSPI mode register,
QMR[MSTR], must be set for the QSPI to function properly. The QSPI can initiate serial transfers but cannot respond to transfers initiated by other QSPI masters.
23.2 Operation
The QSPI uses a dedicated 80-Byte block of static RAM accessible both to the module and the
CPU to perform queued operations. The RAM is divided into three segments as follows:
• 16 command control bytes (command RAM)
• 16 transmit data words (transfer RAM)
• 16 receive data words (transfer RAM)
The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF).
NOTE
Throughout ColdFire documentation, “word” is used consistently and exclusively to designate a 16-bit data unit. The only exceptions to this appear in discussions of serial communication modules such as QSPI that support variable-length data units. To simplify these discussions the functional unit is referred to as a ‘word’ regardless of length.
The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queued commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their completion. As another option, QIR[SPIFE] can be enabled to generate an interrupt.
The QSPI uses four queue pointers. The user can access three of them through fields in QSPI wrap register (QWR):
• The new queue pointer, QWR[NEWQP], points to the first command in the queue.
• An internal queue pointer points to the command currently being executed.
• The completed queue pointer, QWR[CPTQP], points to the last command executed.
• The end queue pointer, QWR[ENDQP], points to the final command in the queue.
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Freescale Semiconductor 23-3
Queued Serial Peripheral Interface (QSPI) Module
The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, the following sequence repeats:
1. The command pointed to by the internal pointer is executed.
2. The value in the internal pointer is copied into QWR[CPTQP].
3. The internal pointer is incremented.
Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed.
After each command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs, QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting
QWR[WREN] enables wraparound mode.
QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0 unless another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but is changed to show the last queue entry before the QSPI is enabled. QWR[NEWQP] and
QWR[ENDQP] can be written at any time. When the QWR[NEWQP] value changes, the internal pointer value also changes unless a transfer is in progress, in which case the transfer completes normally. Leaving QWR[NEWQP] and QWR[ENDQP] set to 0x0 causes a single transfer to occur when the QSPI is enabled.
Data is transferred relative to QSPI_CLK which can be generated in any one of four combinations of phase and polarity using QMR[CPHA,CPOL]. Data is transferred with the most significant bit
(msb) first. The number of bits transferred defaults to 8, but can be set to any value between 8 and
16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]).
23.2.1 QSPI RAM
The QSPI contains an 80-Byte block of static RAM that can be accessed by both the user and the
QSPI. This RAM does not appear in the device memory map because it can only be accessed by the user indirectly through the QSPI address register (QAR) and the QSPI data register (QDR).
The RAM is divided into three segments with 16 addresses each:
• Receive data RAM, the initial destination for all incoming data
• Transmit data RAM, a buffer for all out-bound data
• Command RAM, where commands are loaded
The transmit and command RAM are user write-only. The receive RAM is user read-only.
shows the RAM configuration. The RAM contents are undefined immediately after a reset.
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data and 16 bytes of commands.
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23-4 Freescale Semiconductor
Operation
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and causes the value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at the address specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.
Relative
Address
0x00
0x01
...
0x0F
Register Function
QTR0 Transmit RAM
QTR1
...
QTR15
16 bits wide
0x10
0x11
...
0x1F
QRR0 Receive RAM
QRR1
...
QRR15
16 bits wide
0x20
0x21
...
0x2F
QCR0 Command RAM
QCR1
...
QCR15
8 bits wide
Figure 23-2. QSPI RAM Model
23.2.1.1 Receive RAM
Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the
QSPI RAM space. The user reads this segment to retrieve data from the QSPI. Data words with less than 16 bits are stored in the least significant bits of the RAM. Unused bits in a receive queue entry are set to zero upon completion of the individual queue entry.
QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine which locations in receive RAM contain valid data.
23.2.1.2 Transmit RAM
Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses
0x0 to 0xF. The user normally writes 1 word into this segment for each queue command to be executed. The user cannot read data in the transmit RAM.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 23-5
Queued Serial Peripheral Interface (QSPI) Module
Outbound data must be written to transmit RAM in a right-justified format. The unused bits are ignored. The QSPI copies the data to its data serializer (shift register) for transmission. The data is transmitted most significant bit first and remains in transmit RAM until overwritten by the user.
23.2.1.3 Command RAM
The CPU writes one byte of control information to this segment for each QSPI command to be executed. Command RAM, referred to as QCR0–15, is write-only memory from a user’s perspective.
Command RAM consists of 16 bytes with each byte divided into two fields. The peripheral chip select field controls the QSPI_CS signal levels for the transfer. The command control field provides transfer options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in
QWR[NEWQP] through the address in QWR[ENDQP].
The QSPI executes a queue of commands defined by the control bits in each command RAM entry which sequence the following actions:
• Chip-select pins are activated
• Data is transmitted from transmit RAM and received into the receive RAM
• The synchronous transfer clock QSPI_CLK is generated
Before any data transfers begin, control data must be written to the command RAM, and any out-bound data must be written to transmit RAM. Also, the queue pointers must be initialized to the first and last entries in the command queue.
Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity are controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which
QSPI_CLK edge is used to drive outgoing data and to latch incoming data.
23.2.2 Baud Rate Selection
The maximum QSPI clock frequency is one-fourth the clock frequency of the internal bus clock.
Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to derive the QSPI_CLK rate from the internal bus clock divided by two.
A baud rate value of zero turns off the QSPI_CLK.
The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression:
QMR[BAUD] = f sys/2
/ (2 × [desired QSPI_CLK baud rate]
MCF5271 Reference Manual, Rev. 2
23-6 Freescale Semiconductor
Operation
Table 23-2. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate
QMR [BAUD]
8
16
2
4
32
255
Internal Bus Clock
75 MHz
18.75 MHz
9.375 MHz
4.688 MHz
2.344 MHz
1.172 MHz
147.1 kHz
23.2.3 Transfer Delays
The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer. The time between QSPI_CS assertion and the leading QSPI_CLK edge, and the time between the end of one transfer and the beginning of the next, are both independently programmable.
The chip select to clock delay enable bit in command RAM, QCR[DSCK], enables the programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK.
QDLYR[QCD] determines the period of delay before the leading edge of QSPI_CLK. The following expression determines the actual delay before the QSPI_CLK leading edge:
QSPI_CS-to-QSPI_CLK delay = QDLYR[QCD]/f sys/2
QDLYR[QCD] has a range of 1–127.
When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the QSPI_CLK period is used.
The command RAM delay after transmit enable bit, QCR[DT], enables the programmable delay period from the negation of the QSPI_CS signals until the start of the next transfer. The delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. There are two transfer delay options: the user can choose to delay a standard period after serial transfer is complete or can specify a delay period. Writing a value to QDLYR[DTL] specifies a delay period.
QCR[DT] determines whether the standard delay period (DT = 0) or the specified delay period
(DT = 1) is used. The following expression is used to calculate the delay:
Delay after transfer = 32 × QDLYR[DTL] /f sys/2
(DT = 1) where QDLYR[DTL] has a range of 1–255.
A zero value for DTL causes a delay-after-transfer value of 8192/f sys/2
.
Standard delay after transfer = 17/f sys/2
(DT = 0)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 23-7
Queued Serial Peripheral Interface (QSPI) Module
Adequate delay between transfers must be specified for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay between successive transfers. If the internal bus clock is operating at a slower rate, the delay between transfers must be increased proportionately.
23.2.4 Transfer Length
There are two transfer length options. The user can choose a default value of 8 bits or a programmed value of 8 to 16 bits. The programmed value must be written into QMR[BITS]. The command RAM bits per transfer enable field, QCR[BITSE], determines whether the default value
(BITSE = 0) or the BITS[3–0] value (BITSE = 1) is used. QMR[BITS] gives the required number of bits to be transferred, with 0b0000 representing 16.
23.2.5 Data Transfer
Operation is initiated by setting QDLYR[SPE]. Shortly after QDLYR[SPE] is set, the QSPI executes the command at the command RAM address pointed to by QWR[NEWQP]. Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is simultaneously received is stored at the pointer address in receive RAM.
When the proper number of bits has been transferred, the QSPI stores the working queue pointer value in QWR[CPTQP], increments the working queue pointer, and loads the next data for transfer from the transmit RAM. The command pointed to by the incremented working queue pointer is executed next unless a new value has been written to QWR[NEWQP]. If a new queue pointer value is written while a transfer is in progress, then that transfer is completed normally.
When the CONT bit in the command RAM is set, the QSPI_CS signals are asserted between transfers. When CONT is cleared, QSPI_CS[3:0] are negated between transfers. The QSPI_CS signals are not high impedance.
When the QSPI reaches the end of the queue, it asserts the SPIF flag, QIR[SPIF]. If QIR[SPIFE] is set, an interrupt request is generated when QIR[SPIF] is asserted. Then the QSPI clears
QDLYR[SPE] and stops, unless wraparound mode is enabled.
Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address
0x0, or to the address specified by QWR[NEWQP], depending on the state of QWR[WRTO].
In wraparound mode, the QSPI cycles through the queue continuously, even while requesting interrupt service. QDLYR[SPE] is not cleared when the last command in the queue is executed.
New receive data overwrites previously received data in the receive RAM. Each time the end of the queue is reached, QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven
QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request.
Additional interrupt requests during servicing can be prevented by clearing QIR[SPIFE].
MCF5271 Reference Manual, Rev. 2
23-8 Freescale Semiconductor
Memory Map/Register Definition
There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or setting QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended because this may abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and stops the first time it reaches the end of the queue after QWR[WREN] is cleared. After
QWR[HALT] is set, the QSPI finishes the current transfer, then stops executing commands. After the QSPI stops, QDLYR[SPE] can be cleared.
23.3 Memory Map/Register Definition
Table 23-3 is the QSPI register memory map. Reading reserved locations returns zeros.
Table 23-3. QSPI Registers
IPSBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x00_0340
0x00_0344
0x00_0348
QSPI Mode Register (QMR)
QSPI Delay Register (QDLYR)
QSPI Wrap Register (QWR)
Reserved
1
0x00_034C QSPI Interrupt Register (QIR)
0x00_0350 QSPI Address Register (QAR)
0x00_0354 QSPI Data Register (QDR)
1
Addresses not assigned to a register and undefined register bits are reserved for expansion.
Write accesses to these reserved address spaces and reserved register bits have no effect.
23.3.1 QSPI Mode Register (QMR)
The QMR, shown in
, determines the basic operating modes of the QSPI module.
Parameters such as QSPI_CLK polarity and phase, baud rate, master mode operation, and transfer size are determined by this register. The data output high impedance enable, DOHIE, controls the operation of QSPI_DOUT between data transfers. When DOHIE is cleared, QSPI_DOUT is actively driven between transfers. When DOHIE is set, QSPI_DOUT assumes a high impedance state.
NOTE
Because the QSPI does not operate in slave mode, the master mode enable bit, QMR[MSTR], must be set for the QSPI module to operate correctly.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
23-9
Queued Serial Peripheral Interface (QSPI) Module
15 14
R MSTR DOHIE
W
Reset 0
Address
0
13
0
12
BITS
11 10 9 8
CPOL CPHA
7 6 5
0 0 0 0 1 0
IPSBAR + 0x00_0340
0 0
Figure 23-3. QSPI Mode Register (QMR)
0
4
BAUD
3
0
Table 23-4. QMR Field Descriptions
Bits
15
14
13–10
2
1
1
0
0
0
Name Description
MSTR Master mode enable.
0 Reserved, do not use.
1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.
DOHIE Data output high impedance enable. Selects QSPI_DOUT mode of operation.
0 Default value after reset. QSPI_DOUT is actively driven between transfers.
1 QSPI_DOUT is high impedance between transfers.
BITS Transfer size. Determines the number of bits to be transferred for each entry in the queue.
BITS
0000
0001–0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits per Transfer
16
Reserved
8
9
10
11
12
13
14
15
9
8
7–0
CPOL
CPHA
BAUD
Clock polarity. Defines the clock polarity of QSPI_CLK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.
Clock phase. Defines the QSPI_CLK clock-phase.
0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of
QSPI_CLK.
1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of
QSPI_CLK.
Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value of zero disables the QSPI. A value of 1 is an invalid setting. The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression:
QMR[BAUD] = f sys/2
/ (2 × [desired QSPI_CLK baud rate])
MCF5271 Reference Manual, Rev. 2
23-10 Freescale Semiconductor
Memory Map/Register Definition
shows an example of a QSPI clocking and data transfer.
QSPI_CLK
QSPI_DOUT 15 14 13 12 11 10 msb
9 8 7 6 5 4 3 2 1 0
QSPI_DIN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A
B
QSPI_CS
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
Figure 23-4. QSPI Clocking and Data Transfer Example
23.3.2 QSPI Delay Register (QDLYR)
shows the QDLYR.
15
R SPE
W
Reset 0
Address
14
0
Bits
15
14–8
7–0
13 12 11
QCD
10 9 8 7 6 5 4
DTL
3 2 1 0
Name
SPE
QCD
DTL
0 0 0 1 0 0 0 0
IPSBAR + 0x00_0344
0 0
Figure 23-5. QSPI Delay Register (QDLYR)
0 1 0 0
Table 23-5. QDLYR Field Descriptions
Description
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command RAM. Automatically cleared by the QSPI when a transfer completes. The user can also clear this bit to abort transfer unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT].
QSPICLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay from assertion of the chip selects to valid QSPI_CLK transition.
Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 23-11
Queued Serial Peripheral Interface (QSPI) Module
23.3.3 QSPI Wrap Register (QWR)
15 14 13 12
R HALT WREN WRTO CSIV
W
Reset 0
Address
0 0 0
11
0
10 9
ENDQP
0
8 7
0 0 0
IPSBAR + 0x00_0348
0
6 5
CPTQP
0
Figure 23-6. QSPI Wrap Register (QWR)
4
0
Table 23-6. QWR Field Descriptions
Bits
15
14
13
12
11–8
7–4
3–0
3
0
2 1
NEWQP
0 0
0
0
Name Description
HALT
WREN Wraparound enable. Enables wraparound mode.
0 Execution stops after executing the command pointed to by QWR[ENDQP].
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed to by QWR[NEWQP] and continue execution.
WRTO
Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once it has completed execution of the current command.
Wraparound location. Determines where the QSPI wraps to in wraparound mode.
0 Wrap to RAM entry zero.
1 Wrap to RAM entry pointed to by QWR[NEWQP].
CSIV QSPI_CS inactive level.
0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during a transfer (that is, inactive state is 0, chip selects are active high).
1 QSPI chip select outputs return to one when not driven from the value in the current command RAM entry during a transfer (that is, inactive state is 1, chip selects are active low).
ENDQP End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.
CPTQP Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed. This field is read only.
NEWQP Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer.
23.3.4 QSPI Interrupt Register (QIR)
shows the QIR.
23-12
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
15
R WCE
FB
W
14
ABR
TB
Reset
Address
0 0
13 12
0 ABR
TL
11
WCE
FE
10
ABR
TE
0
9 8 7
0 SPIFE 0
6
0
5
0
4 3 2 1 0
0 WCEF ABRT 0 SPIF
0 0 0 0 0 0 0
IPSBAR + 0x00_034C
0 0
Figure 23-7. QSPI Interrupt Register (QIR)
0 0 0 0
Table 23-7. QIR Field Descriptions
BIts
15
14
13
12
11
10
1
0
9
8
7–4
3
2
Name Description
WCEFB Write collision access error enable. A write collision occurs during a data transfer when the
RAM entry containing the command currently being executed is written to by the CPU with the QDR. When this bit is asserted, the write access to QDR results in an access error.
ABRTB Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer.
When set, an attempt to clear QDLYR[SPE] during a transfer results in an access error.
— Reserved, should be cleared.
ABRTL Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR.
QDLYR[SPE] is only cleared by the QSPI when a transfer completes.
WCEFE Write collision interrupt enable. Interrupt enable for WCEF. Setting this bit enables the interrupt, and clearing it disables the interrupt.
ABRTE Abort interrupt enable. Interrupt enable for ABRT flag. Setting this bit enables the interrupt, and clearing it disables the interrupt.
—
SPIFE
Reserved, should be cleared.
QSPI finished interrupt enable. Interrupt enable for SPIF. Setting this bit enables the interrupt, and clearing it disables the interrupt.
— Reserved, should be cleared.
WCEF Write collision error flag. Indicates that an attempt has been made to write to the RAM entry that is currently being executed. Writing a 1 to this bit clears it and writing 0 has no effect.
ABRT Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR rather than by completion of the command queue by the QSPI. Writing a 1 to this bit clears it and writing 0 has no effect.
—
SPIF
Reserved, should be cleared.
QSPI finished flag. Asserted when the QSPI has completed all the commands in the queue. Set on completion of the command pointed to by QWR[ENDQP], and on completion of the current command after assertion of QWR[HALT]. In wraparound mode, this bit is set every time the command pointed to by QWR[ENDQP] is completed. Writing a 1 to this bit clears it and writing 0 has no effect.
The command and data RAM in the QSPI are indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 23-13
Queued Serial Peripheral Interface (QSPI) Module
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also causes the value in QAR to increment.
Correspondingly, a read at QDR returns the data in the RAM at the address specified by
QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.
NOTE
The QAR does not wrap after the last queue entry within each section of the RAM. The application software must handle address range errors.
23.3.5 QSPI Address Register (QAR)
The QAR, shown in
Figure 23-8 , is used to specify the location in the QSPI RAM that read and
write operations affect.
15
R 0
W
Reset 0
Address
14
0
0
13
0
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5 4
0 0 0 0 0 0 0
IPSBAR + 0x00_0350
0
Figure 23-8. QSPI Address Register
0
3
ADDR
2
0 0
1
0
0
0
23.3.6 QSPI Data Register (QDR)
The QDR, shown in Figure 23-9 , is used to access QSPI RAM indirectly. The CPU reads and
writes all data from and to the QSPI RAM through this register.
15
R
W
Reset 0
Address
14
0
13 12 11 10 9 8
DATA
7 6 5 4
0 0 0 0 0 0 0 0 0
IPSBAR + 0x00_0354
Figure 23-9. QSPI Data Register (QDR)
0
3
0
2
0
1
0
0
0
23.3.7 Command RAM Registers (QCR0–QCR15)
The command RAM is accessed using the upper byte of QDR. The QSPI cannot modify information in command RAM.
There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select field enables external peripherals for transfer. The command field provides transfer operations.
MCF5271 Reference Manual, Rev. 2
23-14 Freescale Semiconductor
Memory Map/Register Definition
NOTE
The command RAM is accessed only using the most significant byte of QDR and indirect addressing based on QAR[ADDR].
shows the command RAM register.
15 14 13 12
R
W CONT BITSE DT DSCK
Reset
Address
— — — —
11
—
10 9
QSPI_CS
— —
8
—
7
0
—
6
0
—
5
0
—
4
0
—
3
0
—
QAR[ADDR]
Figure 23-10. Command RAM Registers (QCR0–QCR15)
2
0
—
Bits
15
14
13
12
11–8
7–0
1
0
—
0
0
—
Table 23-8. QCR0–QCR15 Field Descriptions
Name Description
CONT
BITSE
DT
DSCK
Continuous.
0 Chip selects return to inactive level defined by QWR[CSIV] when transfer is complete.
1 Chip selects remain asserted after the transfer of 16 words of data (see note below).
Bits per transfer enable.
0 Eight bits
1 Number of bits set in QMR[BITS]
Delay after transfer enable.
0 Default reset value.
1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have a latency requirement. The delay between transfers is determined by QDLYR[DTL].
Chip select to QSPI_CLK delay enable.
0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period.
1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK.
QSPI_CS Peripheral chip selects. Used to select an external device for serial data transfer. More than one chip select may be active at once, and more than one device can be connected to each chip select. Bits 11–8 map directly to QSPI_CS[3:0], respectively. If it is desired to use those bits as a chip select value, then an external demultiplexor must be connected to the
QSPI_CS[3:0] pins.
— Reserved, should be cleared.
NOTE
In order to keep the chip selects asserted for all transfers, the
QWR[CSIV] bit must be set to control the level that the chip selects return to after the first transfer.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
23-15
Queued Serial Peripheral Interface (QSPI) Module
QSPI_CS[3:0]
QS1
QSPI_CLK
QS2
QSPI_DOUT
QS3 QS4 QS5
QSPI_DIN
QS1: QSPI_CS to QSPI_CLK
QS2: QSPI_CLK to QSPI_DOUT VALID
QS3: QSPI_CLK to QSPI_DOUT HOLD
QS4: QSPI_DIN to QSPI_CLK SETUP
QS5: QSPI_DIN to QSPI_CLK HOLD
1 T1 is defined as the clock period in ns.
Min
1T1
0 ns
10 ns
10 ns
Figure 23-11. QSPI Timing
Max
20 ns
23.3.8 Programming Example
The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of
4.688 MHz. The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are used in this example.
1. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the falling clock edge, and a QSPI_CLK frequency of 4.688 MHz (assuming a 75-MHz internal bus clock).
2. Write QDLYR with the desired delays.
3. Write QIR with 0xD00F to enable write collision, abort bus errors, and clear any interrupts.
4. Write QAR with 0x0020 to select the first command RAM entry.
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23-16 Freescale Semiconductor
Memory Map/Register Definition
5. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00,
0x7B00, 0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for each chip select. The chip selects are active low in this example.
6. Write QAR with 0x0000 to select the first transmit RAM entry.
7. Write QDR with sixteen 12-bit words of data.
8. Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry 15.
9. Set QDLYR[SPE] to enable the transfers.
10. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are complete.
11. Write QAR with 0x0010 to select the first receive RAM entry.
12. Read QDR to get the received data for each transfer.
13. Repeat steps 5 through 13 to do another transfer.
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MCF5271 Reference Manual, Rev. 2
23-17
Queued Serial Peripheral Interface (QSPI) Module
23-18
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Chapter 24
UART Modules
24.1 Introduction
This chapter describes the use of the universal asynchronous receiver/transmitters (UARTs) implemented on the MCF5271 and includes programming examples.
NOTE
The designation “n” is used throughout this section to refer to registers or signals associated with one of the three identical UART modules:
UART0, UART1, or UART2.
24.1.1
Overview
The MCF5271 contains three independent UARTs. Each UART can be clocked by the internal bus clock, eliminating the need for an external UART clock. As
shows, each UART module interfaces directly to the CPU and consists of the following:
• Serial communication channel
• Programmable clock generation
• Interrupt control logic and DMA request logic
• Internal channel control logic
Internal Channel
Control Logic
UART
Serial
Communications
Channel
Interrupt Control
Logic
Interrupt Request
(to Interrupt Controller)
Transmit DMA Request
Receive DMA Request
(To SCM and DMA Controller)
DMA Request
Logic
Programmable
Clock
Generation
Figure 24-1. UART Block Diagram
UnCTS
UnRTS
UnRXD
UnTXD
Internal Bus Clock (f sys/2
) or External clock (DTnIN)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 24-1
UART Modules
NOTE
UARTn can be clocked by the DTnIN pin. However, if the timers are used, then input capture mode is not available for that timer.
The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus clock or an external clock using the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start, stop, and parity bits. It outputs the resulting stream on the channel transmitter serial data output (UnTXD). See
Section 24.4.2.1, “Transmitter .”
The receiver converts serial data from the channel receiver serial data input (UnRXD) to parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the bus during read operations. The receiver may be polled, interrupt driven, or use
DMA requests for servicing. See
Section 24.4.2.2, “Receiver .”
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module” ) prior to configuring the UART module.
24.1.2
Features
The MCF5271 contains three independent UART modules with the following features:
• Each can be clocked by an external clock or by the internal bus clock (eliminating a need for an external UART clock).
• Full-duplex asynchronous/synchronous receiver/transmitter channel
• Quadruple-buffered receiver
• Double-buffered transmitter
• Independently programmable receiver and transmitter clock sources
• Programmable data format:
— 5–8 data bits plus parity
— Odd, even, no parity, or force parity
— One, one-and-a-half, or two stop bits
• Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode
• Automatic wake-up mode for multidrop applications
• Four maskable interrupt conditions
• All three UARTs have DMA request capability
• Parity, framing, and overrun error detection
MCF5271 Reference Manual, Rev. 2
24-2 Freescale Semiconductor
External Signal Description
• False-start bit detection
• Line-break detection and generation
• Detection of breaks originating in the middle of a character
• Start/end break interrupt/status
24.2 External Signal Description
shows both the external and internal signal groups.
An internal interrupt request signal is provided to notify the interrupt controller of an interrupt condition. The output is the logical NOR of unmasked UISRn bits. The interrupt level and priority are programmed in the interrupt controller
—
ICR13 for UART0, ICR14 for UART1, and ICR15 for
UART2. See Section 13.2.1.6, “Interrupt Control Register (ICRx, (x = 1, 2,..., 63)).”
Note that the UARTs can also be configured to automatically transfer data by using the DMA rather than interrupting the core. When there is data in the receiver FIFO or when the transmit holding register is empty, a DMA request can be issued. For more information on generating DMA
requests, refer to Section 24.4.6.1.2, “Setting up the UART to Request DMA Service
,” and
Section 14.3.1, “DMA Request Control (DMAREQC)
.”
Table 24-1 briefly describes the UART module signals.
NOTE
The terms ‘assertion’ and ‘negation’ are used to avoid confusion between active-low and active-high signals. ‘Asserted’ indicates that a signal is active, independent of the voltage level; ‘negated’ indicates that a signal is inactive.
Table 24-1. UART Module Signals
Signal
Transmitter Serial
Data Output
(UnTXD)
Receiver Serial
Data Input
(UnRXD)
Clear-to- Send
(UnCTS)
Request-to-Send
(UnRTS)
Description
UnTXD is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loop-back mode. Data is shifted out on UnTXD on the falling edge of the clock source, with the least significant bit (lsb) sent first.
Data received on UnRXD is sampled on the rising edge of the clock source, with the lsb received first.
This input can generate an interrupt on a change of state.
This output can be programmed to be negated or asserted automatically by either the receiver or the transmitter. When connected to a transmitter’s UnCTS, UnRTS can control serial data flow.
shows a signal configuration for a UART/RS-232 interface.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 24-3
UART Modules
UART
UnRTS
UnCTS
UnTXD
UnRXD
RS-232 Transceiver
DI2
DO2
DI1
DO1
Figure 24-2. UART/RS-232 Interface
24.3 Memory Map/Register Definition
This section contains a detailed description of each register and its specific function. Flowcharts in
,” describe basic UART module programming. The operation of
the UART module is controlled by writing control bytes into the appropriate registers. Table 24-2
is a memory map for UART module registers.
NOTE
UART registers are accessible only as bytes.
NOTE
Interrupt can mean either an interrupt request asserted to the CPU or a
DMA request.
Table 24-2. UART Module Memory Map
IPSBAR
Offset
UART0
UART1
UART2
0x00_0200
0x00_0240
0x00_0280
0x00_0204
0x00_0244
0x00_0284
0x00_0208
0x00_0248
0x00_0288
0x00_020C
0x00_024C
0x00_028C
[31:24]
UART Mode Registers
1
(UMR1n) , (UMR2n)
(Read) UART Status Registers (USRn)
(Write) UART Clock Select register
(Read) Do not access
2
(Write) UART Command Registers (UCRn)
(UART/Read) UART Receive Buffers (URBn)
(UART/Write) UART Transmit Buffers (UTBn)
[23:16] [15:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[7:0]
MCF5271 Reference Manual, Rev. 2
24-4 Freescale Semiconductor
Memory Map/Register Definition
Table 24-2. UART Module Memory Map (Continued)
IPSBAR
Offset
UART0
UART1
UART2
[31:24] [23:16] [15:8] [7:0]
0x00_0210
0x00_0250
0x00_0290
0x00_0214
0x00_0254
0x00_0294
0x00_0218
0x00_0258
0x00_0298
(Read) UART Input Port Change Register
(UIPCRn)
(Write) UART Auxiliary Control Register
(UACRn)
(Read) UART interrupt Status Register (UISRn)
(Write) UART Interrupt Mask Register (UIMRn)
(Write) UART Divider Upper Register (UBG1n)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x00_021C
0x00_025C
0x00_029C
(Write) UART Divider Lower Register (UBG2n)
Reserved
Reserved
0x00_0234
0x00_0274
0x00_02B4
(Read) UART Input Port Register (UIPn)
Reserved
Reserved
0x00_0238
0x00_0278
0x00_02B8
(Write) UART Output Port Bit Set Command
Register (UOP1n)
Reserved
Reserved
0x00_023C
0x00_027C
0x00_02BC
(Write) UART Output Port Bit Reset Command
Register (UOP0n)
Reserved
Reserved
1
2
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur.
This address is for factory testing. Reading this location results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed.
24.3.1
UART Mode Registers 1 (UMR1n)
The UMR1n registers control configuration. UMR1n can be read or written when the mode register pointer points to it, at RESET or after a
RESET MODE REGISTER POINTER
command using
UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
24-5
UART Modules
24-6
Bits
7
6
5
4–3
2
1–0
7 6
R RXRTS RXIRQ/
FFULL
W
Reset 0 0
5
ERR
4
PM
3 2
PT
1
B/C
0 0 0 0 0
Address IPSBAR + 0x0200 (UART0); IPSBAR + 0x0240 (UART1);
IPSBAR + 0x0280 (UART2)
After UMR1n is read or written, the pointer points to UMR2n.
Figure 24-3. UART Mode Registers 1 (UMR1n)
0
0
Table 24-3. UMR1n Field Descriptions
Name Description
RxRTS Receiver request-to-send. Allows the UnRTS output to control the UnCTS input of the transmitting device to prevent receiver overrun. If both the receiver and transmitter are incorrectly programmed for UnRTS control, UnRTS control is disabled for both. Transmitter
RTS control is configured in UMR2n[TxRTS].
0 The receiver has no effect on UnRTS.
1 When a valid start bit is received, UnRTS is negated if the UART's FIFO is full. UnRTS is reasserted when the FIFO has an empty position available.
RxIRQ/
FFULL
Receiver interrupt select.
0 RxRDY is the source that generates interrupt or DMA requests.
1 FFULL is the source that generates interrupt or DMA requests.
ERR
PM
PT
Error mode. Configures the FIFO status bits, USRn[RB,FE,PE].
0 Character mode. The USRn values reflect the status of the character at the top of the FIFO.
ERR must be 0 for correct A/D flag information when in multidrop mode.
1 Block mode. The USRn values are the logical OR of the status for all characters reaching the top of the FIFO since the last RESET ERROR STATUS command for the channel was issued.
See Section 24.3.5, “UART Command Registers (UCRn) .”
Parity mode. Selects the parity or multidrop mode for the channel. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of
PM affects PT, as shown below.
Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or address character is transmitted (PM = 11).
PM Parity Mode Parity Type (PT= 0) Parity Type (PT= 1)
00 With parity
01 Force parity
Even parity
Low parity
10 No parity
11 Multidrop mode Data character
Odd parity
High parity n/a
Address character
B/C Bits per character. Select the number of data bits per character to be sent. The values shown do not include start, parity, or stop bits.
00 5 bits
01 6 bits
10 7 bits
11 8 bits
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
24.3.2
UART Mode Register 2 (UMR2n)
The UMR2n registers control UART module configuration. UMR2n can be read or written when the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses do not update the pointer.
Bits
7–6
5
R
W
Reset
7
CM
6 5 4
TXRTS TXCTS
3 2
SB
1
0 0 0 0 0 0 0
Address IPSBAR + 0x0200 (UART0); IPSBAR + 0x0240 (UART1);
IPSBAR + 0x0280 (UART2)
After UMR1n is read or written, the pointer points to UMR2n.
Figure 24-4. UART Mode Register 2 (UMR2n)
0
0
Table 24-4. UMR2n Field Descriptions
Name Description
CM
Channel mode. Selects a channel mode. Section 24.4.3, “Looping Modes ,” describes individual
modes.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
TxRTS Transmitter ready-to-send. Controls negation of UnRTS to automatically terminate a message transmission. Attempting to program a receiver and transmitter in the same channel for UnRTS control is not permitted and disables UnRTS control for both.
0 The transmitter has no effect on UnRTS.
1 In applications where the transmitter is disabled after transmission completes, setting this bit automatically clears UOP[RTS] one bit time after any characters in the channel transmitter shift and holding registers are completely sent, including the programmed number of stop bits.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
24-7
UART Modules
Bits
4
3–0
Table 24-4. UMR2n Field Descriptions (Continued)
Name Description
TxCTS Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter.
0 UnCTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of UnCTS each time it is ready to send a character. If UnCTS is asserted, the character is sent; if it is deasseted, the channel UnTXD remains in the high state and transmission is delayed until UnCTS is asserted. Changes in UnCTS as a character is being sent do not affect its transmission.
SB Stop-bit length control. Selects the length of the stop bit appended to the transmitted character.
Stop-bit lengths of 9/16 to 2 bits are programmable for 6–8 bit characters. Lengths of 1-1/16 to
2 bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high condition at the center of the first stop-bit position, that is, one bit time after the last data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing bit 3 selects one stop bit and setting bit 3 selects two stop bits for transmission.
SB
0000
0001
0010
0011
0100
0101
0110
0111
5 Bits
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
6–8 Bits
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
SB
1000
1001
1010
1011
1100
1101
1110
1111
5–8 Bits
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
24.3.3
UART Status Registers (USRn)
The USRn registers, shown in Figure 24-5 , show the status of the transmitter, the receiver, and the
FIFO.
W
Reset
7
R RB
Address
0
6
FE
0
5
PE
0
4 3 2 1 0
OE TXEMP TXRDY FFULL RXRDY
0 0 0 0
IPSBAR + 0x0204 (USR0); IPSBAR + 0x0244 (USR1);
IPSBAR + 0x0284 (USR2)
Figure 24-5. UART Status Register (USRn)
0
MCF5271 Reference Manual, Rev. 2
24-8 Freescale Semiconductor
Bits
7
6
5
4
3
2
1
0
Memory Map/Register Definition
Table 24-5. USRn Field Descriptions
Name Description
RB
FE
PE
Received break. The received break circuit detects breaks that originate in the middle of a received character. However, a break in the middle of a character must persist until the end of the next detected character time.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. Only a single FIFO position is occupied when a break is received. Further entries to the FIFO are inhibited until UnRXD returns to the high state for at least one-half bit time, which is equal to two successive edges of the UART clock. RB is valid only when RxRDY = 1.
Framing error.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RxRDY = 1.
Parity error. Valid only if RxRDY = 1.
0 No parity error occurred.
1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was received with incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the received address or data (A/D) bit. PE is valid only when RxRDY = 1.
OE Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. OE is cleared by the RESET ERROR STATUS command in UCRn.
TxEMP Transmitter empty.
0 The transmit buffer is not empty. Either a character is being shifted out, or the transmitter is disabled. The transmitter is enabled/disabled by programming UCRn[TC].
1 The transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission.
TxRDY Transmitter ready.
0 The CPU loaded the transmitter holding register or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TxRDY is set when a character is sent to the transmitter shift register or when the transmitter is first enabled.
If the transmitter is disabled, characters loaded into the transmitter holding register are not sent.
FFULL FIFO full.
0 The FIFO is not full but may hold up to two unread characters.
1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full are lost.
RxRDY Receiver ready.
0 The CPU has read the receive buffer and no characters remain in the FIFO after this read.
1 One or more characters were received and are waiting in the receive buffer FIFO.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 24-9
UART Modules
24.3.4
UART Clock Select Registers (UCSRn)
The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal
bus clock as the clocking source for the transmitter and receiver. See Section 24.4.1,
“Transmitter/Receiver Clock Source
.” The transmitter and receiver can use different clock sources. To use the internal bus clock for both, set UCSRn to 0xDD.
Bits
7–4
3–0
7 6 5 4 3 2 1 0
R
W
Reset
RCS TCS
0 0 0 0 0 0 0
Address IPSBAR + 0x0204 (UCSR0); IPSBAR + 0x0244 (UCSR1);
IPSBAR + 0x0284 (UCSR2)
Figure 24-6. UART Clock Select Register (UCSRn)
0
Table 24-6. UCSRn Field Descriptions
Name
RCS
TCS
Description
Receiver clock select. Selects the clock source for the receiver channel.
1101 Prescaled internal bus clock
1110 DTIN divided by 16
1111 DTIN
Transmitter clock select. Selects the clock source for the transmitter channel.
1101 Prescaled internal bus clock
1110 DTIN divided by 16
1111 DTIN
24.3.5
UART Command Registers (UCRn)
The UCRs, shown in Figure 24-7 , supply commands to the UART. Only multiple commands that
do not conflict can be specified in a single write to a UCRn. For example,
RESET TRANSMITTER and ENABLE TRANSMITTER cannot be specified in one command.
7 6 5 4 3 2 1
R
W
Reset
0
0 0
MISC
0 0 0
TC
0 0
RC
Address IPSBAR + I0x0208 (UCR0); IPSBAR + 0x0248 (UCR1);
IPSBAR + 0x0288 (UCR2)
Figure 24-7. UART Command Register (UCRn)
0
0
describes UCRn fields and commands. Examples in Section 24.4.2, “Transmitter and
Receiver Operating Modes ,” show how these commands are used.
MCF5271 Reference Manual, Rev. 2
24-10 Freescale Semiconductor
Memory Map/Register Definition
Table 24-7. UCRn Field Descriptions
Bits Value
6–4
3–2
Command Description
MISC Field (This field selects a single command.)
000
NO COMMAND
001
RESET MODE
REGISTER POINTER
010 RESET RECEIVER
—
Causes the mode register pointer to point to UMR1n.
Immediately disables the receiver, clears USRn[FFULL,RxRDY], and reinitializes the receiver FIFO pointer. No other registers are altered. Because it places the receiver in a known state, use this command instead of RECEIVER DISABLE when reconfiguring the receiver.
011
RESET TRANSMITTER
Immediately disables the transmitter and clears USRn[TxEMP,TxRDY]. No other registers are altered. Because it places the transmitter in a known state, use this command instead of
TRANSMITTER DISABLE
when reconfiguring the transmitter.
100
RESET ERROR
STATUS
Clears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after a data block is received.
Clears the delta break bit, UISRn[DB]. 101 RESET BREAK –
CHANGE INTERRUPT
110
START BREAK
111 STOP BREAK
Forces UnTXD low. If the transmitter is empty, the break may be delayed up to one bit time. If the transmitter is active, the break starts when character transmission completes. The break is delayed until any character in the transmitter shift register is sent. Any character in the transmitter holding register is sent after the break. The transmitter must be enabled for the command to be accepted. This command ignores the state of UnCTS.
Causes UnTXD to go high (mark) within two bit times. Any characters in the transmit buffer are sent.
TC Field (This field selects a single command)
00
NO ACTION TAKEN
01
11
TRANSMITTER
ENABLE
10
TRANSMITTER
DISABLE
—
Causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled.
Enables operation of the channel’s transmitter. USRn[TxEMP,TxRDY] are set. If the transmitter is already enabled, this command has no effect.
Terminates transmitter operation and clears USRn[TxEMP,TxRDY]. If a character is being sent when the transmitter is disabled, transmission completes before the transmitter becomes inactive. If the transmitter is already disabled, the command has no effect.
Reserved, do not use.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
24-11
UART Modules
Table 24-7. UCRn Field Descriptions (Continued)
Bits Value
1–0
Command Description
RC (This field selects a single command)
00
NO ACTION TAKEN
Causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled.
01 RECEIVER ENABLE If the UART module is not in multidrop mode (UMR1n[PM] ≠ 11),
RECEIVER ENABLE enables the channel's receiver and forces it into search-for-start-bit state. If the receiver is already enabled, this command has no effect.
10 RECEIVER DISABLE Disables the receiver immediately. Any character being received is lost. The command does not affect receiver status bits or other control registers. If the
UART module is programmed for local loop-back or multidrop mode, the receiver operates even though this command is selected. If the receiver is already disabled, the command has no effect.
11 — Reserved, do not use.
24.3.6
UART Receive Buffers (URBn)
The receive buffers (shown in
) contain one serial shift register and three receiver holding registers, which act as a FIFO. UnRXD is connected to the serial shift register. The CPU reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift
register is full (see Figure 24-18
). RB contains the character in the receiver.
7 6 5 4 3 2 1
Reset
Address
R
W
RB
1 1 1 1 1 1 1
IPSBAR + 0x020C (URB0); IPSBAR + 0x024C (URB1);
IPSBAR + 0x028C (URB2)
Figure 24-8. UART Receive Buffer (URBn)
0
1
24.3.7
UART Transmit Buffers (UTBn)
The transmit buffers consist of the transmitter holding register and the transmitter shift register.
The holding register accepts characters from the bus master if channel’s USRn[TxRDY] is set. A write to the transmit buffer clears USRn[TxRDY], inhibiting any more characters until the shift register can accept more data. When the shift register is empty, it checks if the holding register has a valid character to be sent (TxRDY = 0). If there is a valid character, the shift register loads it and sets USRn[TxRDY] again. Writes to the transmit buffer when the channel’s TxRDY = 0 and when the transmitter is disabled have no effect on the transmit buffer.
shows UTBn. TB contains the character in the transmit buffer.
MCF5271 Reference Manual, Rev. 2
24-12 Freescale Semiconductor
Memory Map/Register Definition
7 6 5 4 3 2 1
Reset
Address
R
W TB
0 0 0 0 0 0 0
IPSBAR + 0x020C(UTB0); IPSBAR + 0x024C(UTB1);
IPSBAR + 0x028C(UTB2)
Figure 24-9. UART Transmit Buffer (UTBn)
0
0
24.3.8
UART Input Port Change Registers (UIPCRn)
The UIPCRs, shown in
Figure 24-10 , hold the current state and the change-of-state for UnCTS.
Bits
7–5
4
3–1
0
R
W
Reset
7
0
6
0
5
0
4
COS
3
0
2
0
1
0
0
CTS
0 0 0 0 1 1 1 UnCTS
Address IPSBAR + 0x0210 (UIPCR0); IPSBAR + 0x0250 (UIPCR1); IPSBAR +
0x0290 (UIPCR2)
Figure 24-10. UART Input Port Change Register (UIPCRn)
Table 24-8. UIPCRn Field Descriptions
Name
—
COS
—
CTS
Description
Reserved, should be cleared.
Change of state (high-to-low or low-to-high transition).
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears
UISRn[COS].
1 A change-of-state longer than 25–50 µs occurred on the UnCTS input. UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected.
Reserved, should be cleared.
Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the state of UnCTS. If UnCTS is detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled.
0 The current state of the UnCTS input is asserted.
1 The current state of the UnCTS input is deasserted.
24.3.9
UART Auxiliary Control Register (UACRn)
The UACRs, shown in Figure 24-8 , control the input enable.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 24-13
UART Modules
Bits
7–1
0
7 6 5 4 3 2 1 0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IEC
0
Address IPSBAR + 0x0210 (UACR0); IPSBAR + 0x0250 (UACR1); IPSBAR +
0x0290 (UACR2)
Figure 24-11. UART Auxiliary Control Register (UACRn)
Table 24-9. UACRn Field Descriptions
Name
—
IEC
Description
Reserved, should be cleared.
Input enable control.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition on the UnCTS input (if UIMRn[COS] = 1).
24.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
The UISRs, shown in
, provide status for all potential interrupt sources. UISRn contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, the internal interrupt output is asserted. If a UIMRn bit is cleared, the state of the corresponding UISRn bit has no effect on the output.
The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits.
NOTE
True status is provided in the UISRn regardless of UIMRn settings.
UISRn is cleared when the UART module is reset.
R
(UISRn)
W
(UIMRn)
Reset
7
COS
COS
6
0
0
5
0
0
4
0
0
3
0
0
2 1 0
DB FFULL/
RXRDY
TXRDY
DB FFULL/
RXRDY
TXRDY
0 0 0 0 0 0 0 0
Address IPSBAR + 0x0214 (UISR0); IPSBAR + 0x0254 (UISR1); IPSBAR +
0x0294 (UISR2)
Figure 24-12. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
MCF5271 Reference Manual, Rev. 2
24-14 Freescale Semiconductor
Bits
7
6–3
2
1
Memory Map/Register Definition
Name
COS
—
DB
FFULL/
RxRDY
Table 24-10. UISRn/UIMRn Field Descriptions
Description
Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on UnCTS and was programmed in UACRn[IEC] to cause an interrupt.
Reserved, should be cleared.
Delta break.
0 No new break-change condition to report. Section 24.3.5, “UART Command Registers
,” describes the RESET BREAK CHANGE INTERRUPT command.
1 The receiver detected the beginning or end of a received break.
Status of FIFO or receiver, depending on UMR1[FFULL/RxRDY] bit. Duplicate of
USRn[FIFO] & USRn[RxRDY]
UIMRn
[FFULL/RxRDY
]
UISRn
[FFULL/RxRDY]
0
1
0
0
0
1
1 1
UMR1n[FFULL/RxRDY]
0 (RxRDY)
Receiver not ready
Receiver not ready
Receiver is ready,
Do not interrupt
Receiver is ready, interrupt
1 (FIFO)
FIFO not full
FIFO not full
FIFO is full,
Do not interrupt
FIFO is full, interrupt
0 TxRDY Transmitter ready. This bit is the duplication of USRn[TxRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled.
Characters loaded into the transmitter holding register when TxRDY = 0 are not sent.
1 The transmitter holding register is empty and ready to be loaded with a character.
24.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)
The UBG1n registers hold the msb, and the UBG2n registers hold the lsb of the preload value.
UBG1n and UBG2n concatenate to provide a divider to the internal bus clock for
transmitter/receiver operation, as described in Section 24.4.1.2.1, “internal Bus Clock Baud
.”
7 6 5 4 3 2 1 0
R
W
Reset 0 0 0
Divider MSB
0 0 0 0 0
Address IPSBAR + 0x0218 (UBG10); IPSBAR + 0x0258 (UBG11);
IPSBAR + 0x0298 (UBG12)
Figure 24-13. UART Baud Rate Generator Register (UBG1n)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 24-15
UART Modules
7 6 5 4 3 2 1 0
R
W
Reset 0 0 0
Divider LSB
0 0 0 0 0
Address IPSBAR + 0x021C (UBG20); IPSBAR + 0x025C (UBG21);
IPSBAR + 0x029C (UBG22)
Figure 24-14. UART Baud Rate Generator Register (UBG2n)
NOTE
The minimum value that can be loaded on the concatenation of
UBG1n with UBG2n is 0x0002. The UBG2n reset value of 0x00 is invalid and must be written to before the UART transmitter or receiver are enabled. Both UBG1n and UBG2n are write-only and cannot be read by the CPU.
24.3.12 UART Input Port Register (UIPn)
The UIPn registers, shown in
Figure 24-15 , show the current state of the UnCTS input.
Bits
7–1
0
R
W
Reset
7
0
6
0
5
0
4
0
3
0
2
0
1
0
1 1 1 1 1 1 1
Address IPSBAR + 0x0234 (UIP0); IPSBAR + 0x0274 (UIP1);
IPSBAR + 0x02B4 (UIP2)
Figure 24-15. UART Input Port Register (UIPn)
0
CTS
1
Table 24-11. UIPn Field Descriptions
Name
—
CTS
Description
Reserved
Current state of clear-to-send. The UnCTS value is latched and reflects the state of the input pin when UIPn is read. Note: This bit has the same function and value as
UIPCRn[RTS].
0 The current state of the UnCTS input is logic 0.
1 The current state of the UnCTS input is logic 1.
24.3.13 UART Output Port Command Registers (UOP1n/UOP0n)
The UnRTS output can be asserted by writing a 1 to UOP1n[RTS] and negated by writing a 1 to
UOP0n[RTS]. See
MCF5271 Reference Manual, Rev. 2
24-16 Freescale Semiconductor
Functional Description
Bits
7–1
0
7 6 5 4 3 2 1 0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RTS
0
Address UART0: IPSBAR + 0x0238 (UOP1), IPSBAR + 0x023C (UOP0)
UART1: IPSBAR + 0x0278 (UOP1), IPSBAR + 0x027C (UOP0)
UART2: IPSBAR + 0x02B8 (UOP1) IPSBAR + 0x02BC (UOP0)
Figure 24-16. UART Output Port Command Registers (UOP1n/UOP0n)
Table 24-12. UOP1/UOP0 Field Descriptions
Name
—
RTS
Description
Reserved, should be cleared.
Output port output. Controls assertion (UOP1)/negation (UOP0) of UnRTS output.
0 Not affected.
1 Asserts UnRTS in UOP1. Negates UnRTS in UOP0.
24.4 Functional Description
This section describes operation of the clock source generator, transmitter, and receiver.
24.4.1
Transmitter/Receiver Clock Source
The internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each UART.
The clock generator might not produce standard baud rates if the internal bus clock is used, so enable the 16-bit divider.
24.4.1.1 Programmable Divider
shows, the UARTn transmitter and receiver can use the following clock sources:
• An external clock signal on the DTnIN pin. When not divided, DTnIN provides a synchronous clock mode; when divided by 16, it is asynchronous.
• The internal bus clock supplies an asynchronous clock source that is divided by 32 and then
divided by the 16-bit value programmed in UBG1n and UBG2n. See Section 24.3.11,
“UART Baud Rate Generator Registers (UBG1n/UBG2n) .”
The choice of DTIN or internal bus clock is programmed in the UCSR.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
24-17
UART Modules
DTnOUT
DTnIN
On-Chip
Timer Module
UnTXD Tx Buffer
UART
Clocking sources programmed in UCSR
TIN x1
Prescaler
Tx x16
Prescaler
TIN
Rx
Clock
Generator
16-Bit
Divider x32
Prescaler
UnRXD Rx Buffer f sys/2
Figure 24-17. Clocking Source Diagram
NOTE
If DTnIN is a clocking source for either the timer or UART, that timer module cannot use DTnIN for timer input capture.
24.4.1.2 Calculating Baud Rates
The following sections describe how to calculate baud rates.
24.4.1.2.1 internal Bus Clock Baud Rates
When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is as follows:
Baudrate =
[ f
-----------------------------------
32 x divider
]
Using a 75 MHz internal bus clock and letting baud rate = 9600, then
Divider =
[
75MHz
32 x 9600
]
= 244 decimal
)
= 0x00F4 hexadecimal ) therefore UBG1n = 0x00 and UBG2n = 0x.
MCF5271 Reference Manual, Rev. 2
24-18 Freescale Semiconductor
Functional Description
24.4.1.2.2 External Clock
An external source clock (DTnIN) can be used as is or divided by 16.
If f extc
is the external clock frequency, then the baud rate can be described with this equation:
Baudrate = f
(16 or 1)
24.4.2
Transmitter and Receiver Operating Modes
is a functional block diagram of the transmitter and receiver showing the command and operating registers, which are described generally in the following sections and described in
detail in Section 24.3, “Memory Map/Register Definition .”
UARTn
UART Command Register (UCRn) W
UART Mode Register 1 (UMR1n)
UART Mode Register 2 (UMR2n)
R/W
R/W
UART Status Register (USRn) R
UART
Transmit Buffer
(UTBn)
(2 Registers)
Transmitter Holding Register
Transmitter Shift Register
W
UnTXD
FIFO
UART Receive
Buffer (URBn)
(4 Registers)
Receiver Holding Register 1
Receiver Holding Register 2
Receiver Holding Register 3
Receiver Shift Register
R
Figure 24-18. Transmitter and Receiver Functional Diagram
External
Interface
UnRXD
24.4.2.1 Transmitter
The transmitter is enabled through the UART command register (UCRn). When it is ready to accept a character, the UART sets USRn[TxRDY]. The transmitter converts parallel data from the
CPU to a serial bit stream on UnTXD. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits.
The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 24-19
UART Modules
After the stop bits are sent, if no new character is in the transmitter holding register, the UnTXD output remains high (mark condition) and the transmitter empty bit, USRn[TxEMP], is set.
Transmission resumes and TxEMP is cleared when the CPU loads a new character into the UART transmit buffer (UTBn). If the transmitter receives a disable command, it continues until any character in the transmitter shift register is completely sent.
If the transmitter is reset through a software command, operation stops immediately (see
Section 24.3.5, “UART Command Registers (UCRn) ”). The transmitter is reenabled through the
UCRn to resume operation after a disable or software reset.
If the clear-to-send operation is enabled, UnCTS must be asserted for the character to be transmitted. If UnCTS is negated in the middle of a transmission, the character in the shift register is sent and UnTXD remains in mark state until UnCTSn is reasserted. If the transmitter is forced to send a continuous low condition by issuing a
SEND BREAK
command, the transmitter ignores the state of UnCTS.
If the transmitter is programmed to automatically negate UnRTS when a message transmission completes, UnRTS must be asserted manually before a message is sent. In applications in which the transmitter is disabled after transmission is complete and UnRTS is appropriately programmed, UnRTS is negated one bit time after the character in the shift register is completely transmitted. The transmitter must be manually reenabled by reasserting UnRTS before the next message is to be sent.
shows the functional timing information for the transmitter.
24-20
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Functional Description
UnTXD C1
1
C1 in transmission
C2 C3 Break C4 C6
Transmitter
Enabled
USRn[TxRDY] internal module select
UnCTS
3
W
2
C1
1
W
C2
W W
C3 Start break
W W W
C4 Stop break
C5 not transmitted
W
C6
UnRTS
4 Manually asserted by BIT SET command
1
Cn = transmit characters
2
W = write
3
UMR2n[TxCTS] = 1
4
UMR2n[TxRTS] = 1
Figure 24-19. Transmitter Timing Diagram
Manually asserted
24.4.2.2 Receiver
The receiver is enabled through its UCRn, as described in Section 24.3.5, “UART Command
.”
When the receiver detects a high-to-low (mark-to-space) transition of the start bit on UnRXD, the state of UnRXD is sampled eight times on the edge of the bit time clock starting one-half clock after the transition (asynchronous operation) or at the next rising edge of the bit time clock
(synchronous operation). If UnRXD is sampled high, the start bit is invalid and the search for the valid start bit begins again.
If UnRXD is still low, a valid start bit is assumed and the receiver continues sampling the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. Data on the UnRXD input is sampled on the rising edge of the programmed clock source. The lsb is received first. The data is then transferred to a receiver holding register and USRn[RxRDY] is set. If the character is less than eight bits, the most significant unused bits in the receiver holding register are cleared.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 24-21
UART Modules
After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a non-zero character is received without a stop bit (framing error) and UnRXD remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit were detected. Parity error, framing error, overrun error, and received break conditions set the respective PE, FE, OE, RB error and break flags in the USRn at the received character boundary and are valid only if USRn[RxRDY] is set.
If a break condition is detected (UnRXD is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register and USRn[RB,RxRDY] are set.
UnRXD must return to a high condition for at least one-half bit time before a search for the next start bit begins.
The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. If the break begins in the middle of a character, the receiver places the damaged character in the Rx FIFO and sets the corresponding USRn error bits and
USRn[RxRDY]. Then, if the break lasts until the next character time, the receiver places an all-zero character into the Rx FIFO and sets USRn[RB,RxRDY].
shows receiver functional timing.
UnTXD C1 C2 C3 C4 C5 C6 C7 C8
C6, C7, and C8 will be lost
Receiver
Enabled
USRn[RxRDY]
USRn[FFULL] internal module select Status
Data
(C1)
Overrun
USRn[OE]
UnRTS
1
Manually asserted first time, automatically negated if overrun occurs
UOP0[RTS] = 1
1
UMR2n[TxRTS] = 1
C5 will be lost
Figure 24-20. Receiver Timing
Status
Data
(C2)
Status
Data
Status
Data
(C3) (C4)
Reset by command
Automatically asserted when ready to receive
MCF5271 Reference Manual, Rev. 2
24-22 Freescale Semiconductor
Functional Description
24.4.2.3 FIFO
The FIFO is used in the UART’s receive buffer logic. The FIFO consists of three receiver holding registers. The receive buffer consists of the FIFO and a receiver shift register connected to the
UnRXD (see
Figure 24-18 ). Data is assembled in the receiver shift register and loaded into the top
empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the
CPU is quadruple-buffered.
In addition to the data byte, three status bits, parity error (PE), framing error (FE), and received break (RB), are appended to each data character in the FIFO; OE (overrun error) is not appended.
By programming the ERR bit in the channel’s mode register (UMR1n), status is provided in character or block modes.
USRn[RxRDY] is set when at least one character is available to be read by the CPU. A read of the receive buffer produces an output of data from the top of the FIFO. After the read cycle, the data at the top of the FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom of the FIFO. The FIFO-full status bit (FFULL) is set if all three positions are filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt and either TxRDY or RxRDY can be used to generate a DMA request.
The two error modes are selected by UMR1n[ERR] as follows:
• In character mode (UMR1n[ERR] = 0, status is given in the USRn for the character at the top of the FIFO.
• In block mode, the USRn shows a logical OR of all characters reaching the top of the FIFO since the last
RESET ERROR STATUS
command. Status is updated as characters reach the top of the FIFO. Block mode offers a data-reception speed advantage where the software overhead of error-checking each character cannot be tolerated. However, errors are not detected until the check is performed at the end of an entire message—the faulting character is not identified.
In either mode, reading the USRn does not affect the FIFO. The FIFO is popped only when the receive buffer is read. The USRn should be read before reading the receive buffer. If all three receiver holding registers are full, a new character is held in the receiver shift register until space is available. However, if a second new character is received, the contents of the the character in the receiver shift register is lost, the FIFOs are unaffected, and USRn[OE] is set when the receiver detects the start bit of the new overrunning character.
To support flow control, the receiver can be programmed to automatically negate and assert
UnRTS, in which case the receiver automatically negates UnRTS when a valid start bit is detected and the FIFO is full. The receiver asserts UnRTS when a FIFO position becomes available; therefore, overrun errors can be prevented by connecting UnRTS to the UnCTS input of the transmitting device.
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Freescale Semiconductor 24-23
UART Modules
NOTE
The receiver can still read characters in the FIFO if the receiver is disabled. If the receiver is reset, the FIFO, UnRTS control, all receiver status bits, and interrupts, and DMA requests are reset. No more characters are received until the receiver is reenabled.
24.4.3
Looping Modes
The UART can be configured to operate in various looping modes as shown in
.
These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs and in
Section 24.3, “Memory Map/Register Definition
.”
The UART’s transmitter and receiver should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted.
24.4.3.1 Automatic Echo Mode
In automatic echo mode, shown in
Figure 24-21 , the UART automatically resends received data
bit by bit. The local CPU-to-receiver communication continues normally, but the
CPU-to-transmitter link is disabled. In this mode, received data is clocked on the receiver clock and re-sent on UnTXD. The receiver must be enabled, but the transmitter need not be.
Rx UnRXD Input
CPU
Disabled
Tx
Disabled
UnTXD Output
Figure 24-21. Automatic Echo
Because the transmitter is inactive, USRn[TxEMP,TxRDY] are inactive and data is sent as it is received. Received parity is checked but is not recalculated for transmission. Character framing is also checked, but stop bits are sent as they are received. A received break is echoed as received until the next valid start bit is detected.
24.4.3.2 Local Loop-Back Mode
shows how UnTXD and UnRXD are internally connected in local loop-back mode.
This mode is for testing the operation of a local UART module channel by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations.
24-24
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Functional Description
Rx
Disabled
UnRXD Input
CPU
Tx
Disabled
UnTXD Output
Figure 24-22. Local Loop-Back
Features of this local loop-back mode are as follows:
• Transmitter and CPU-to-receiver communications continue normally in this mode.
• UnRXD input data is ignored
• UnTXD is held marking
• The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be.
24.4.3.3 Remote Loop-Back Mode
In remote loop-back mode, shown in
, the channel automatically transmits received data bit by bit on the UnTXD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote channel. For this mode, the transmitter uses the receiver clock.
Because the receiver is not active, received data cannot be read by the CPU and all status conditions are inactive. Received parity is not checked and is not recalculated for transmission.
Stop bits are sent as they are received. A received break is echoed as received until the next valid start bit is detected.
Disabled
Rx
Disabled
UnRXD Input
CPU
Disabled
Tx
Disabled
UnTXD Input
Figure 24-23. Remote Loop-Back
24.4.4
Multidrop Mode
Setting UMR1n[PM] programs the UART to operate in a wake-up mode for multidrop or multiprocessor applications. In this mode, a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations.
Although slave stations have their channel receivers disabled, they continuously monitor the master’s data stream. When the master sends an address character, the slave receiver channel notifies its respective CPU by setting USRn[RxRDY] and generating an interrupt (if programmed to do so). Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 24-25
UART Modules master station. Slave stations not addressed continue monitoring the data stream. Data fields in the data stream are separated by an address character. After a slave receives a block of data, its CPU disables the receiver and repeats the process. Functional timing information for multidrop mode is shown in
UnTXD
A/D
ADD1 1
Master Station
A/D
C0
A/D
ADD2 1
Transmitter
Enabled
USRn[TxRDY] internal module select
UMR1n[PM] = 11
UMR1n[PT] = 1
ADD 1 C0
UMR1n[PT] = 0
A/D A/D
ADD 2
UMR1n[PT] = 2
Peripheral Station
A/D
UnRXD 0 ADD1 1 C0
Receiver
Enabled
A/D
ADD2 1
A/D
0
USRn[RxRDY] internal module select
UMR1n [PM] = 11
UMR1n[PM] = 11
ADD 1 Status Data
(C0)
Figure 24-24. Multidrop Mode Timing Diagram
Status Data
(ADD 2)
A character sent from the master station consists of a start bit, a programmed number of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. A/D = 1 indicates an address character; A/D = 0 indicates a data character. The polarity of A/D is selected through
UMR1n[PT]. UMR1n should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and loads the character into the receiver holding register FIFO provided the received A/D bit is a one (address tag). The character is discarded if the received A/D bit is zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU through the receiver holding register during read operations.
MCF5271 Reference Manual, Rev. 2
24-26 Freescale Semiconductor
Functional Description
In either case, the data bits are loaded into the data portion of the FIFO while the A/D bit is loaded into the status portion of the FIFO normally used for a parity error (USRn[PE]).
Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode may still contain error detection and correction information. One way to provide error detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character.
24.4.5
Bus Operation
This section describes bus operation during read, write, and interrupt acknowledge cycles to the
UART module.
24.4.5.1 Read Cycles
The UART module responds to reads with byte data. Reserved registers return zeros.
24.4.5.2 Write Cycles
The UART module accepts write data as bytes only. Write cycles to read-only or reserved registers complete normally without exception processing, but data is ignored.
24.4.6
Programming
The software flowchart, Figure 24-25 , consists of the following:
• UART module initialization—These routines consist of SINIT and CHCHK (See
and
Figure 24-26 ). Before SINIT is called at system initialization, the calling
routine allocates 2 words on the system FIFO. On return to the calling routine, SINIT passes
UART status data on the FIFO. If SINIT finds no errors, the transmitter and receiver are enabled. SINIT calls CHCHK to perform the checks. When called, SINIT places the UART in local loop-back mode and checks for the following errors:
— Transmitter never ready
— Receiver never ready
— Parity error
— Incorrect character received
• I/O driver routine—This routine (See
and
) consists of INCH, the terminal input character routine which gets a character from the receiver, and OUTCH, which sends a character to the transmitter.
• Interrupt handling—Consists of SIRQ (See Figure 24-28 ), which is executed after the
UART module generates an interrupt caused by a change-in-break (beginning of a break).
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 24-27
UART Modules
SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor.
24.4.6.1 Interrupt and DMA Request Initialization
24.4.6.1.1 Setting up the UART to Generate Core Interrupts
The list below gives the steps needed to properly initialize the UART to generate an interrupt request to the core.
1. Initialize ICRx register in the interrupt controller (ICR13 for UART0, ICR14 for UART1, and ICR15 for UART2).
2. Unmask appropriate bits in IMR in the interrupt controller (bits 13-15 for UART0-UART2 respectively).
3. Unmask appopriate bits in the core’s Status Register (SR) to enable interrupts.
4. If TxRDY or RxRDY are being used to generate interrupt requests, then verify that
DMAREQC (in the SCM) does not also assign the UART’s TxRDYand RxRDY into
DMA channels.
5. Initialize interrupts in the UART, see Table 24-13 .
Table 24-13. UART Interrupts
Register
UMR1x
UIMRx
UIMRx
UIMRx
UIMRx
Bit
2
1
6
7
0
Interrupt
RxIRQ
Change of State (COS)
Delta Break
RxFIFO Full
TxRDY
24.4.6.1.2 Setting up the UART to Request DMA Service
The UART is capable of generating two different DMA request signals–transmit DMA requests and receive DMA requests.
The transmit DMA request signal is asserted when the TxRDY (transmitter ready) in the UART
Interrupt Status Register, UISRn[TxRDY], is set. When the transmit DMA request signal is asserted, the DMA can initiate a data copy, reading the next character to be transmitted from memory and writing it into the UART transmit buffer (UTBn). This would allow the DMA channel to stream data from memory to the UART for transmission without processor intervention. Once the entire message has been moved into the UART, the DMA would typically generate an end-of-data-transfer interrupt request to the CPU. The resulting interrupt service routine (ISR) could query the UART programming model to determine the end-of-transmission status.
MCF5271 Reference Manual, Rev. 2
24-28 Freescale Semiconductor
Functional Description
Similarly, the receive DMA request signal is asserted when the FFULL/RxRDY (FIFO full or receive ready) flag in the Interrupt Status Register, UISR[FFULL/RxRDY], is set. When the receive DMA request signal is asserted, the DMA can initiate a data move, reading the appropriate characters from the UART Receive Buffer (URBn) and storing them in memory. This allows the
DMA channel to stream data from the UART receive buffer into memory without processor intervention. Once the entire message has been moved from the UART, the DMA would typically generate an end-of-data-transfer interrupt request to the CPU. The resulting interrupt service routine (ISR) should query the UART programming model to determine the end-of-transmission status. In typical applications, the receive DMA request should be configured to use RxRDY directly (and not FFULL) to remove any complications related to retrieving the final characters from the FIFO buffer.
The implementation described in this section allows independent DMA processing of transmit and receive data while still supporting interrupt notification to the processor for CTS change-of-state and “delta break” error handling.
To configure the UART for DMA requests:
1. Initialize the DMAREQC in the SCM to map the desired UART DMA requests to the desired DMA channels. For example; setting DMAREQC[7:4] to 1000 maps UART0 receive DMA requests to DMA channel 1; setting DMAREQC[11:8] to 1101 maps UART1 transmit DMA requests to DMA channel 2; and so on. It is possible to independently map transmit based and receive based UART DMA requests in the DMAREQC.
2. Disable interrupts using the UIMR register. The appropriate UIMR bits must be cleared so that interrupt requests are disabled for those conditions for which a DMA request is desired. For example; to generate transmit DMA requests from UART1, then
UIMR1[TxRDY] should be cleared. This will prevent TxRDY from generating an interrupt request while a transmit DMA request is generated.
3. Configure the GPACR and appropriate PACR registers located in the SCM for DMA access to IPSBAR space.
4. Initialize the DMA channel. The DMA should be configured for cycle steal mode and a source and destination size of one byte. This will cause a single byte to be transferred for each UART DMA request.
shows the DMA requests.
Table 24-14. UART DMA Requests
Register
UISRn
UISRn
Bit
1
0
DMA Request
Receive DMA request
Transmit DMA request
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Freescale Semiconductor 24-29
UART Modules
24.4.6.2 UART Module Initialization Sequence
shows the UART module initialization sequence.
Table 24-15. UART Module Initialization Sequence
Register Setting
UCRn Reset the receiver and transmitter.
Reset the mode pointer (MISC[2–0] = 0b001).
UIMRn Enable the preferred interrupt sources.
UACRn Initialize the input enable control (IEC bit).
UCSRn Select the receiver and transmitter clock. Use timer as source if required.
UMR1n If preferred, program operation of receiver ready-to-send (RxRTS bit).
Select receiver-ready or FIFO-full notification (RxRDY/FFULL bit).
Select character or block error mode (ERR bit).
Select parity mode and type (PM and PT bits).
Select number of bits per character (B/Cx bits).
UMR2n Select the mode of operation (CMx bits).
If preferred, program operation of transmitter ready-to-send (TxRTS).
If preferred, program operation of clear-to-send (TxCTS bit).
Select stop-bit length (SBx bits).
UCRn Enable transmitter and/or receiver.
24-30
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
SERIAL MODULE
SINIT
INITIATE:
CHANNEL
INTERRUPTS
CHK1
CALL CHCHK
SAVE CHANNEL
STATUS
ENABLE
ANY
ERRORS
?
N
ENABLE RECEIVER
Y
ASSERT
REQUEST TO SEND
SINITR
RETURN
Figure 24-25. UART Mode Programming Flowchart
Functional Description
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
24-31
UART Modules
CHCHK
CHCHK
PLACE CHANNEL IN
LOCAL LOOPBACK
MODE
ENABLE
TRANSMITTER CLEAR
STATUS WORD
TxCHK
IS
TRANSMITTER
READY
?
SNDCHR Y
N
SEND CHARACTER
TO TRANSMITTER
RxCHK
HAS
CHARACTER BEEN
RECEIVED
?
Y
N
N
WAITED
TOO LONG
?
N
WAITED
TOO LONG
?
Y
SET TRANSMITTER-
NEVER-READY FLAG
Y SET RECEIVER-
NEVER-READY FLAG
A
Figure 24-26. UART Mode Programming Flowchart (Continued)
B
24-32
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Functional Description
A
FRCHK
HAVE
FRAMING ERROR
?
N
SET FRAMING
ERROR FLAG
PRCHK
HAVE
PARITY ERROR
?
Y
SET PARITY
ERROR FLAG
CHRCHK
GET CHARACTER
FROM RECEIVER
N
SAME AS
TRANSMITTED
CHARACTER
?
N
SET INCORRECT
CHARACTER FLAG
Y
B
RSTCHN
DISABLE
TRANSMITTER
RESTORE
TO ORIGINAL MODE
RETURN
B
Figure 24-27. UART Mode Programming Flowchart (Continued)
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
24-33
UART Modules
ABRKI
SIRQ
WAS
IRQ CAUSED
BY BEGINNING
OF A BREAK
?
Y
CLEAR CHANGE-IN-
BREAK STATUS BIT
ABRKI1
N
HAS
END-OF-BREAK
IRQ ARRIVED
YET
?
Y
CLEAR CHANGE-IN-
BREAK STATUS BIT
N
REMOVE BREAK
CHARACTER FROM
RECEIVER FIFO
INCH
DOES
CHANNEL A
RECEIVER HAVE A
CHARACTER
?
Y
PLACE CHARACTER
IN D0
N
RETURN
REPLACE RETURN
ADDRESS ON SYSTEM
STACK AND MONITOR
WARM START ADDRESS
SIRQR
RTE
Figure 24-28. UART Mode Programming Flowchart (Continued)
24-34
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Functional Description
OUTCH
IS
TRANSMITTER
READY
?
Y
SEND CHARACTER
TO TRANSMITTER
N
RETURN
Figure 24-29. UART Mode Programming Flowchart (Continued)
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
24-35
UART Modules
24-36
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
I
Chapter 25
2
C Interface
25.1 Introduction
This chapter describes the MCF5271 I and I
2
2
C module, including I
2
C protocol, clock synchronization,
C programming model registers. It also provides extensive programming examples.
25.2 Overview
I
2
C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications
I that require occasional communication between many devices over a short distance. The flexible
2
C bus allows additional devices to be connected to the bus for expansion and system development.
The interface is designed to operate up to 100 Kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of the internal bus clock divided by 20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
The I
2
C system is a true multiple-master bus; it uses arbitration and collision detection to prevent data corruption in the event that multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer.
NOTE
The I
2
C module is designed to be compatible with the Philips I
2
C bus protocol. For information on system configuration, protocol, and restrictions, see The I
2
C Bus Specification, Version 2.1.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module” ) prior to configuring the I
2
C module.
25.3 Features
The I
2
C module has the following key features:
• Compatibility with I
2
C bus standard version 2.1
• Support for 3.3-V tolerant devices
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 25-1
I
2
C Interface
• Multiple-master operation
• Software-programmable for one of 50 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
is a block diagram of the I
2
C module.
IRQ
Internal Bus
Address Data
Registers and ColdFire Interface
Address Decode Data MUX
I
2
C Frequency
Divider Register
(IFDR)
Clock
Control
I
2
C Control
Register
(I2CR)
Start, Stop, and
Arbitration
Control
I
2
C Status
Register
(I2SR)
I
2
C Data
I/O Register
(I2DR)
I
2
C Address
Register
(IADR)
In/Out
Data
Shift
Register
Input
Sync
Address
Compare
25-2
I2C_SCL I2C_SDA
Figure 25-1. I
2
C Module Block Diagram
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
I
2
C System Configuration
shows the relationships of the below I
Section 25.5, “Memory Map/Register Definition ":
2
C registers, which are described in
• I
2
C address register (I2ADR)
• I
2
C frequency divider register (I2FDR)
• I
2
C control register (I2CR)
• I
2
C status register (I2SR)
• I
2
C data I/O register (I2DR)
25.4 I
2
C System Configuration
The I
2
C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL) for data transfer. For I
2
C compliance, all devices connected to these two signals must have open drain or open collector outputs. The logic AND function is exercised on both lines with external pull-up resistors.
Out of reset, the I
2
C default state is as a slave receiver. Thus, when not programmed to be a master or responding to a slave transmit address, the I
2
C module should return to the default slave receiver
state. See Section 25.6.1, “Initialization Sequence ,” for exceptions.
Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer, and STOP signal. These are discussed in the following sections.
25.4.1 START Signal
When no other device is bus master (both I2C_SCL and I2C_SDA lines are at logic high), a device
can initiate communication by sending a START signal (see A in Figure 25-2 ). A START signal
is defined as a high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves.
I2C_SCL msb
1 2 3 4 5 6
Interrupt bit set
(Byte complete)
I2C_SCL held low while
Interrupt is serviced lsb
7 8 msb
2 3 4 5 6 lsb
7 8
I2C_SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
A
START
Signal
Calling Address
B
XXX D7 D6 D5 D4 D3 D2 D1 D0
E
Data Byte
R/W ACK
C
Bit
D
Figure 25-2. I
2
C Standard Communication Protocol
No
ACK
Bit
STOP
Signal
F
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 25-3
I
2
C Interface
25.4.2 Slave Address Transmission
The master sends the slave address in the first byte after the START signal (B). After the seven-bit calling address, it sends the R/W bit (C), which tells the slave data transfer direction (0 = write transfer, 1 = read transfer).
Each slave must have a unique address. An I
2
C master must not transmit its own slave address; it cannot be master and slave at the same time.
The slave whose address matches that sent by the master pulls I2C_SDA low at the ninth serial clock (D) to return an acknowledge bit.
25.4.3 Data Transfer
When successful slave addressing is achieved, the data transfer can proceed (E) on a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master.
Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high,
as Figure 25-2 shows. I2C_SCL is pulsed once for each data bit, with the msb being sent first. The
receiving device must acknowledge each byte by pulling I2C_SDA low at the ninth clock;
therefore, a data byte transfer takes nine clock pulses. See Figure 25-3 .
I2C_SCL
I2C_SCL Held Low while
Interrupt is Serviced
1 2 3 4 5 6 7 8 9
I2C_SDA
START
Signal
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit0
R/W
Slave Address
ACK from
Receiver
1 2 3 4 5 6 7 8 9
Interrupt Bit Set
(Byte Complete)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Data Byte
No
ACK
Bit
STOP
Signal
Figure 25-3. Data Transfer
25.4.4 Acknowlege
The transmitter releases the I2C_SDA line high during the acknowledge clock pulse as shown in
. The receiver pulls down the I2C_SDA line during the acknowledge clock pulse so that it remains stable low during the high period of the clock pulse.
If it does not acknowledge the master, the slave receiver must leave I2C_SDA high. The master can then generate a STOP signal to abort the data transfer or generate a START signal (repeated start, shown in
Figure 25-5 and discussed in Section 25.4.6, “Repeated START”
) to start a new calling sequence.
MCF5271 Reference Manual, Rev. 2
25-4 Freescale Semiconductor
I
2
C System Configuration
I2C_SCL
I2C_SDA by Transmitter
I2C_SDA by Receiver
1 2 3 4 5 6 7 8 9
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
Bit0
R/W
START Signal
Figure 25-4. Acknowledgement by Receiver
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means end-of-data to the slave. The slave releases I2C_SDA for the master to generate a STOP or
START signal (
).
25.4.5 STOP Signal
The master can terminate communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of I2C_SDA while I2C_SCL is at logical high (F). The master can generate a STOP even if the slave has generated an acknowledgment at which point the slave must release the bus. The master may also generate a START signal following a calling address, without first generating a STOP signal. Refer to
Section 25.4.6, “Repeated START.”
I2C_SCL msb
1 2 3 4 5 lsb
6 7 8 9 msb
1 2 3 4 5 lsb
6 7 8 9
I2C_SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
Signal
Calling Address
R/W ACK
Bit
Repeated
START
Signal
A
New Calling Address
Stop
Figure 25-5. Repeated START
R/W No
ACK
Bit
STOP
Signal
25.4.6 Repeated START
A repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.
Various combinations of read/write formats are then possible:
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 25-5
I
2
C Interface
• The first example in Figure 25-6 is the case of master-transmitter transmitting to
slave-receiver. The transfer direction is not changed.
• The second example in
is the master reading the slave immediately after the first byte. At the moment of the first acknowledge, the master-transmitter becomes a master-receiver and the slave-receiver becomes slave-transmitter.
• In the third example in Figure 25-6 the START condition and slave address are both
repeated using the repeated START signal. This is to communicate with same slave in a different mode without releasing the bus. The master transmits data to the slave first, and then the master reads data from slave by reversing the R/W bit.
ST = Start
SP = Stop
A = Acknowledge (I2C_SDA low)
A = Not Acknowledge (I2C_SDA high)
Rept ST = Repeated Start
From Master to Slave
From Slave to Master
Example 1:
ST 7bit Slave Address
R/W
0 A Register Address A DATA A/A SP
Example 2:
ST 7bit Slave Address
R/W
1 A DATA A DATA A SP
Example 3:
ST
7-bit Slave
Address
R/W
1 A DATA A/A
Rept
ST
Master Transmits to Slave
R/W
7-bit Slave 0
Address
A DATA A DATA A/A SP
Master Reads from Slave
Figure 25-6. Data Transfer, Combined Format
1
Note: No acknowledge on the last byte
25.4.7 Clock Synchronization and Arbitration
I
2
C is a true multi-master bus that allows more than one master to be connected to it. If two or more masters devices simultaneously request control of the bus, a clock synchronization procedure determines the bus clock. Because wire-AND logic is performed on the I2C_SCL line, a high-to-low transition on the I2C_SCL line affects all the devices connected on the bus. The devices start counting their low period and once a device’s clock has gone low, it holds the
I2C_SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the I2C_SCL line if another device clock is still within
MCF5271 Reference Manual, Rev. 2
25-6 Freescale Semiconductor
I
2
C System Configuration its low period. Therefore, synchronized clock I2C_SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see
). When all devices concerned have counted off their low period, the synchronized clock I2C_SCL line is released and pulled high. There is then no difference between the device clocks and the state of the
I2C_SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the I2C_SCL line low again.
The relative priority of the contending masters is determined by a data arbitration procedure. A bus master loses arbitration if it transmits logic "1" while another master transmits logic "0". The losing masters immediately switch over to slave receive mode and stop driving I2C_SDA output
(see Figure 25-7 ). In this case the transition from master to slave mode does not generate a STOP
condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration.
I2C_SCL
I2C_SDA by
Master1
I2C_SDA by
Master2
I2C_SDA
Master 2 Loses Arbitration, and becomes slave-receiver
Figure 25-7. Arbitration Procedure
Wait
Start counting high period
I2C_ SCL1
I2C_ SCL2
I2C_ SCL
Internal Counter Reset
Figure 25-8. Clock Synchronization
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 25-7
I
2
C Interface
25.4.8 Handshaking and Clock Stretching
The clock synchronization mechanism can be used as a handshake in data transfers. Slave devices can hold I2C_SCL low after completing one byte transfer. In such a case, the clock mechanism halts the bus clock and forces the master clock into wait states until the slave releases I2C_SCL.
Slaves may also slow down the transfer bit rate. After the master has driven I2C_SCL low, the slave can drive I2C_SCL low for the required period and then release it. If the slave I2C_SCL low period is longer than the master I2C_SCL low period, the resulting I2C_SCL bus signal low period is stretched.
25.5 Memory Map/Register Definition
Table 25-1 lists the configuration registers used in the I
2
C interface.
Table 25-1. I
2
C Interface Memory Map
IPSBAR Offset
0x0300
0x0304
0x0308
0x030C
0x0310
Mnemonic
I2ADR
I2FDR
I2CR
I2SR
I2DR
[31:24]
I
2
C Address Register
I
2
C Frequency Divider Register
I
2
C Control Register
I
2
C Status Register
I
2
C Data I/O Register
[23:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Access
R/W
R/W
R/W
R/W
R/W
25.5.1 I
2
C Address Register (I2ADR)
The I2ADR holds the address the I
2
C responds to when addressed as a slave. Note that it is not the address sent on the bus during the address transfer.
Bits
7–1
0
Reset
Address
R
W
7 6 5 4
ADR
3 2 1
0 0 0 0 0 0 0
IPSBAR + 0x00_0300
Figure 25-9. I
2
C Address Register (I2ADR)
Name
ADR
—
0
0
0
Table 25-2. I2ADR Field Descriptions
Description
Slave address. Contains the specific slave address to be used by the I
2
C module. Slave mode is the default I
2
C mode for an address match on the bus.
Reserved, should be cleared.
MCF5271 Reference Manual, Rev. 2
25-8 Freescale Semiconductor
Memory Map/Register Definition
25.5.2 I
2
C Frequency Divider Register (I2FDR)
The I2FDR, shown in Figure 25-10
, provides a programmable prescaler to configure the I
2 for bit-rate selection.
C clock
Bits
7–6
5–0
R
W
Reset
7
0
6
0
5 4 3
IC
2 1 0
0 0 0 0 0 0 0 0
Address IPSBAR + 0x00_0304
Figure 25-10. I
2
C Frequency Divider Register (I2FDR)
Table 25-3. I2FDR Field Descriptions
Name
—
IC
Description
Reserved, should be cleared.
I
2
C clock rate. Prescales the clock for bit-rate selection. The serial bit clock frequency is equal to the internal bus clock divided by the divider shown below. Due to potentially slow
I2C_SCL and I2C_SDA rise and fall times, bus signals are sampled at the prescaler frequency.
IC Divider IC Divider IC Divider IC Divider
144
160
192
240
80
88
104
128
44
48
56
68
28
30
34
40
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
288
320
384
480
576
640
768
960
1152
1280
1536
1920
2304
2560
3072
3840
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
20
22
24
26
28
32
36
40
48
56
64
72
80
96
112
128
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
640
768
896
1024
1280
1536
1792
2048
320
384
448
512
160
192
224
256
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 25-9
I
2
C Interface
25.5.3 I
2
C Control Register (I2CR)
The I2CR is used to enable the I
2 operation as a slave or a master.
C module and the I
2
C interrupt. It also contains bits that govern
Bits
7
6
5
4
3
W
Reset
7
R IEN
Address
0
6 5 4 3 2
IIEN MSTA MTX TXAK RSTA
0 0 0 0
IPSBAR + 0x00_0308
0
1
0
0
Figure 25-11. I
2
C Control Register (I2CR)
Table 25-4. I2CR Field Descriptions
Name
IEN
IIEN
MSTA
MTX
TXAK
0
0
0
Description
I
2
C enable. Controls the software reset of the entire I
2
C module. If the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is detected. Master mode is not aware that the bus is busy; so initiating a start cycle may corrupt the current bus cycle, ultimately causing either the current master or the I
2
C module to lose arbitration, after which bus operation returns to normal.
0 The I
1 The I
2
2
C module is disabled, but registers can still be accessed.
C module is enabled. This bit must be set before any other I2CR bits have any effect.
I
2
C interrupt enable.
0 I
2
C module interrupts are disabled, but currently pending interrupt condition are not
1 I cleared.
2
C module interrupts are enabled. An I
2
C interrupt occurs if I2SR[IIF] is also set.
Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a STOP signal.
0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.
1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.
Transmit/receive mode select bit. Selects the direction of master and slave transfers.
0 Receive
1 Transmit. When the device is addressed as a slave, software should set MTX according to I2SR[SRW]. In master mode, MTX should be set according to the type of transfer required. Therefore, when the MCU addresses a slave device, MTX is always 1.
Transmit acknowledge enable. Specifies the value driven onto I2C_SDA during acknowledge cycles for both master and slave receivers. Note that writing TXAK applies only when the I
2
C bus is a receiver.
0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
1 No acknowledge signal response is sent (that is, acknowledge bit = 1).
MCF5271 Reference Manual, Rev. 2
25-10 Freescale Semiconductor
Bits
2
Memory Map/Register Definition
Table 25-4. I2CR Field Descriptions (Continued)
Name Description
RSTA Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration.
0 No repeat start
1 Generates a repeated START condition.
— Reserved, should be cleared.
1–0
25.5.4 I
2
C Status Register (I2SR)
This I2SR contains bits that indicate transaction direction and status.
Bits
7
6
5
4
3
W
Reset
7
R ICF
Address
1
6
IAAS
0
5
IBB
0
4
IAL
0
3
0
0
IPSBAR + 0x00_030C
2
SRW
0
1
IIF
0
Figure 25-12. I
2
C Status Register (I2SR)
Table 25-5. I2SR Field Descriptions
0
RXAK
1
Name Description
ICF Data transferring bit. While one byte of data is transferred, ICF is cleared.
0 Transfer in progress
1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer.
IAAS I
2
C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit.
0 Not addressed.
1 Addressed as a slave. Set when its own address (IADR) matches the calling address.
IBB I
2
C bus busy bit. Indicates the status of the bus.
0 Bus is idle. If a STOP signal is detected, IBB is cleared.
1 Bus is busy. When START is detected, IBB is set.
IAL Arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by writing zero to it.)
• I2C_SDA sampled low when the master drives high during an address or data-transmit cycle.
• I2C_SDA sampled low when the master drives high during the acknowledge bit of a data-receive cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
— Reserved, should be cleared.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 25-11
I
2
C Interface
Bits
2
1
0
Name
SRW
IIF
RXAK
Table 25-5. I2SR Field Descriptions (Continued)
Description
Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling address sent from the master. SRW is valid only when a complete transfer has occurred, no other transfers have been initiated, and the I
2
C module is a slave and has an address match.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
I
2
C interrupt. Must be cleared by software by writing a zero in the interrupt routine.
0 No I
2
C interrupt pending
1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of the following occurs:
• Complete one byte transfer (set at the falling edge of the ninth clock)
• Reception of a calling address that matches its own specific address in slave-receive mode
• Arbitration lost
Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle.
0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus
1 No acknowledge signal was detected at the ninth clock.
25.5.5 I
2
C Data I/O Register (I2DR)
In master-receive mode, reading the I2DR allows a read to occur and initiates next the byte data to be received. In slave mode, the same function is available once the I
2
C has received its slave address.
7 6 5 4 3 2 1
Reset
Address
R
W
Data
0 0 0 0 0 0 0
IPSBAR + 0x00_0310
Figure 25-13. I
2
C Data I/O Register (I2DR)
0
0
25-12
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
I
2
C Programming Examples
Bit
7
–0
Name
DATA
Table 25-6. I2DR Field Description
Description
I
2
C data. In master transmit mode, when data is written to this register, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates the reception of the next byte of data. In slave mode, the same functions are available after an address match has occurred.
Note: 1. In master transmit mode, the first byte of data written to I2DR following assertion of I2CR[MSTA] is used for the address transfer and should comprise the calling address
(in position D7–D1) concatenated with the required R/W bit (in position D0). This bit (D0) is not automatically appended by the hardware, software must provide the appropriate
R/W bit.
Note: 2. I2CR[MSTA] generates a start when a master does not already own the bus.
I2CR[RSTA] generates a start (restart) without the master first issuing a stop (i.e., the master already owns the bus). In order to start the read of data, a dummy read to this register starts the read process from the slave. The next read of the I2DR register contains the actual data.
25.6 I
2
C Programming Examples
The following examples show programming for initialization, signaling START, post-transfer software response, signalling STOP, and generating a repeated START.
25.6.1 Initialization Sequence
Before the interface can transfer serial data, registers must be initialized, as follows:
1. Set I2FDR[IC] to obtain I2C_SCL frequency from the system bus clock. See
Section 25.5.2, “I2C Frequency Divider Register (I2FDR) .”
2. Update the I2ADR to define its slave address.
3. Set I2CR[IEN] to enable the I
2
C bus interface system.
4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and interrupt-enable or not.
NOTE
If I2SR[IBB] is set when the I
2
C bus module is enabled, execute the following pseudocode sequence before proceeding with normal initialization code. This issues a STOP command to the slave device, placing it in idle state as if it were just power-cycled on.
I2CR = 0x0
I2CR = 0xA0 dummy read of I2DR
I2SR = 0x0
I2CR = 0x0
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Freescale Semiconductor 25-13
I
2
C Interface
25.6.2 Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode. On a multiple-master bus system, I2SR[IBB] must be tested to determine whether the serial bus is free. If the bus is free (IBB = 0), the START signal and the first byte (the slave address) can be sent. The data written to the data register comprises the address of the desired slave and the lsb indicates the transfer direction.
The free time between a STOP and the next START condition is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the
I2C_SCL period, it may be necessary to wait until the I
2
C is busy after writing the calling address to the I2DR before proceeding with the following instructions.
The following example signals START and transmits the first byte of data (slave address):
CHFLAG MOVE.B I2SR,-(A0)
BTST.B #5, (A0)+
BNE.S CHFLAG
TXSTART MOVE.B I2CR,-(A0)
BSET.B #4,(A0)
MOVE.B (A0)+, I2CR
MOVE.B I2CR, -(A0)
BSET.B #5, (A0)
MOVE.B (A0)+, I2CR
MOVE.B CALLING,-(A0)
MOVE.B (A0)+, I2DR
IFREE MOVE.B I2SR,-(A0)
;Check I2SR[MBB]
;If I2SR[MBB] = 1, wait until it is clear
;Set transmit mode
;Set master mode
;Generate START condition
;Transmit the calling address, D0=R/W
;Check I2SR[MBB]
;If it is clear, wait until it is set.
BTST.B #5, (A0)+
BEQ.S IFREE;
25.6.3 Post-Transfer Software Response
Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is finished. I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during initialization by setting I2CR[IIEN]. Software must first clear I2SR[IIF] in the interrupt routine.
I2SR[ICF] is cleared either by reading from I2DR in receive mode or by writing to I2DR in transmit mode.
Software can service the I
2
C I/O in the main program by monitoring IIF if the interrupt function is disabled. Polling should monitor IIF rather than ICF because that operation is different when arbitration is lost.
When an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the address is sent. If master receive mode is required I2CR[MTX] should be toggled.
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25-14 Freescale Semiconductor
I
2
C Programming Examples
During slave-mode address cycles (I2SR[IAAS] = 1), I2SR[SRW] is read to determine the direction of the next transfer. MTX is programmed accordingly. For slave-mode data cycles (IAAS
= 0), SRW is invalid. MTX should be read to determine the current transfer direction.
The following is an example of a software response by a master transmitter in the interrupt routine
).
I2SR LEA.L I2SR,-(A7)
BCLR.B #1,(A7)+
MOVE.B I2CR,-(A7)
BTST.B #5,(A7)+
BEQ.S SLAVE
MOVE.B I2CR,-(A7)
BTST.B #4,(A7)+
BEQ.S RECEIVE
MOVE.B I2SR,-(A7)
BTST.B #0,(A7)+
BNE.B END
TRANSMITMOVE.B DATABUF,-(A7)
MOVE.B (A7)+, I2DR
;Load effective address
;Clear the IIF flag
;Push the address on stack,
;check the MSTA flag
;Branch if slave mode
;Push the address on stack
;check the mode flag
;Branch if in receive mode
;Push the address on stack,
;check ACK from receiver
;If no ACK, end of transmission
;Stack data byte
;Transmit next byte of data
25.6.4 Generation of STOP
A data transfer ends when the master signals a STOP, which can occur after all data is sent, as in the following example.
MASTX MOVE.B I2SR, -(A7)
BTST.B #0,(A7)+
BNE.B END
MOVE.B TXCNT,D0
BEQ.S END
MOVE.B DATABUF,-(A7)
MOVE.B (A7)+,I2DR
MOVE.B TXCNT,D0
END
SUBQ.L #1,D0
MOVE.B D0,TXCNT
BRA.S EMASTX;Exit
LEA.L I2CR,-(A7)
BCLR.B #5,(A7)+
EMASTX RTE
;If no ACK, branch to end
;Get value from the transmitting counter
;If no more data, branch to end
;Transmit next byte of data
;Decrease the TXCNT
;Generate a STOP condition
;Return from interrupt
For a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last byte. Before the last byte is read, a STOP signal must be generated, as in the following example.
MASR MOVE.B RXCNT,D0
SUBQ.L #1,D0
MOVE.B D0,RXCNT
BEQ.S ENMASR
MOVE.B RXCNT,D1
;Decrease RXCNT
;Last byte to be read
;Check second-to-last byte to be read
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Freescale Semiconductor 25-15
I
2
C Interface
EXTB.L D1
SUBI.L #1,D1;
BNE.S NXMAR
LAMAR BSET.B #3,I2CR
BRA NXMAR
ENMASR BCLR.B #5,I2CR
NXMAR MOVE.B I2DR,RXBUF
;Not last one or second last
;Disable ACK
;Last one, generate STOP signal
;Read data and store RTE
25.6.5 Generation of Repeated START
After the data transfer, if the master still wants the bus, it can signal another START followed by another slave address without signalling a STOP, as in the following example.
;Repeat START (RESTART) RESTART MOVE.B I2CR,-(A7)
BSET.B #2, (A7)
MOVE.B (A7)+, I2CR
MOVE.B CALLING,-(A7)
MOVE.B CALLING,-(A7)
MOVE.B (A7)+, I2DR
;Transmit the calling address, D0=R/W-
25.6.6 Slave Mode
In the slave interrupt service routine, software should poll the I2SR[IAAS] bit to determine if the controller has received its slave address. If IAAS is set, software should set the transmit/receive mode select bit (I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears the IAAS automatically. The only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred; interrupts resulting from subsequent data transfers will have
IAAS cleared. A data transfer can now be initiated by writing information to I2DR for slave transmits, or read from I2DR in slave-receive mode. A dummy read of I2DR in slave/receive mode releases I2C_SCL, allowing the master to send data.
In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data.
Setting RXAK means an end-of-data signal from the master receiver, after which software must switch it from transmitter to receiver mode. Reading I2DR then releases I2C_SCL so that the master can generate a STOP signal.
25.6.7 Arbitration Lost
If several devices try to engage the bus at the same time, one becomes master. Hardware immediately switches devices that lose arbitration to slave receive mode. Data output to I2C_SDA stops, but I2C_SCL is still generated until the end of the byte during which arbitration is lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with I2SR[IAL] = 1 and
I2CR[MSTA] = 0.
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2
C Programming Examples
If a device that is not a master tries to transmit or do a START, hardware inhibits the transmission, clears MSTA without signalling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, the slave service routine should first test IAL and software should clear it if it is set.
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MCF5271 Reference Manual, Rev. 2
25-17
I
2
C Interface
Clear
IIF
Y Master
Mode?
N
TX TX/Rx
?
RX Y
Arbitration
Lost?
N
Last Byte
Transmitted
?
N
Y
Y
RXAK= 0
?
Y
N
End of
ADDR Cycle
(Master RX)
?
N
Write Next
Byte to I2DR
Last
Byte to be
Read ?
N
Y
Y
2nd Last
Byte to be
Read?
N
Set TXAK =1
Generate
STOP Signal
Clear IAL
N
IAAS=1
?
Address
Cycle
Y
(Read) Y
Y
SRW=1
?
N (WRITE)
IAAS=1
?
N
Data
Cycle
Tx/Rx
?
TX
RX
Set TX
Mode
Write Data to I2DR
Y
Tx Next
Byte
ACK from
Receiver
?
N
Read Data from I2DR and Store
Switch to
Rx Mode
Set RX
Mode
Switch to
Rx Mode
Dummy Read from I2DR
Generate
STOP Signal
Read Data from I2DR
And Store
Dummy Read from I2DR
Dummy Read from I2DR
RTE
Figure 25-14. Flow-Chart of Typical I
2
C Interrupt Routine
MCF5271 Reference Manual, Rev. 2
25-18 Freescale Semiconductor
Chapter 26
Message Digest Hardware Accelerator
(MDHA)
26.1 Introduction
This chapter describes the Message Digest Hardware Accelerator (MDHA).
26.1.1
Overview
The MDHA is a hardware implementation of two of the world’s most popular cryptographic hash functions: SHA-1 and MD5. SHA-1 and MD5 are both critical algorithms to the IPSec (IP
Security) Protocol, a fast-spreading protocol for authentication and encryption over the internet in networking equipment. The MDHA also includes circuitry to automate the process of generating an HMAC (Hashed Message Authentication Code) as specified by RFC 2104 and EHMAC
(Enhanced Hashed Message Authentication Code), using only the SHA-1 algorithm.
26.1.2
Features
The MDHA computes a single message digest (or hash or integrity check) value of all the data presented on the input bus, using either the MD5 or SHA-1 algorithms for bulk data hashing. The
MDHA includes these distinctive features:
• MD5 one way 128-bit hash function specified in RFC 1321.
• SHA-1 one way 160-bit hash function specified by the ANSI X9.30-2 and FIPS 180-1 standards.
• HMAC support for all algorithms, as specified in RFC 2104.
• EHMAC support for the SHA-1 algorithm.
• EHMAC key support up to 160 bits.
• Processes 512 bit blocks organized as 16 × 32 bit longwords.
• Automatic Message and Key Padding.
• Internal 16x32 bit FIFO for temporary storage of hashing data.
With any hash algorithm, the larger message is mapped onto a smaller output space. Therefore collisions are potential, albeit not probable. The 160-bit hash value is a sufficiently large space such that collisions are extremely rare. The security of the hash function is based on the difficulty of locating collisions. That is, it is computationally infeasible to construct two distinct but similar messages that produce the same hash output.
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Freescale Semiconductor 26-1
Message Digest Hardware Accelerator (MDHA)
This module is useful in many applications including hashing messages to generate digital signatures or computation of a shared secret. The digital signature is typically computed on a small input, however if the data to be signed is large, it is inefficient to sign the entire data. Instead, the large input data is hashed to a smaller value which is then signed. If the message is also sent to the verifying authority along with the signature, the verifying authority can verify the signature by recovering the hash value from the signature using the public key of the sender, hashing the message itself, and then comparing the computed hash value with the recovered hash value. If they match, then the verifying authority is confident that the data was signed by the owner of the private key that matches the public key, where the private key presumably is only known by the sender.
This provides a measure of authentication and non-repudiation.
A conceptual block diagram of the MDHA module is shown in Figure 26-1
. Multiple input blocks are written to the MDHA module, and at the end, the hash value is read as the 160-bit output for
SHA-1 or 128-bit output for MD5.
160-bit constant
Hash value
160-bit value
512-bit block n
Plaintext blocks
512-bit block n-1
...
512-bit block 2
512-bit block 1
SHA-1
128-bit constant
Output
Register
Hash value
128-bit value
MD5
Figure 26-1. MDHA Hashing Process
26.1.3
Modes of Operation
• One-way hashing generation—a message digest, or a hash, is the result of a one-way function performed on a message. Two different hash functions can be used:
— SHA-1: Secure Hash Algorithm defined in Federal Information Processing Standards
Publication 180-1.
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26-2 Freescale Semiconductor
Memory Map/Register Definition
— MD5: Message Digest 5 Algorithm defined by Ron Rivest of MIT Laboratory for
Computer Science and RSA Data Security, INC.
• MAC: A Message Authentication Code is a one-way function performed on a message with two user defined keys:
— HMAC—Hashed message authentication can be used with either the SHA-1 or MD5 algorithm defined in Federal Information Processing Standards Publication 198.
— EHMAC—Enhanced Hashed message authentication can only be used with the SHA-1 algorithm.
26.2 Memory Map/Register Definition
Table 26-1 shows the MDHA memory map.
Table 26-1. MDHA Module Memory Map
IPSBAR
Offset
0x19_0000
0x19_0004
0x19_0008
0x19_000C
0x19_0010
0x19_0014
0x19_001C
0x19_0020
0x19_0030
0x19_0034
0x19_0038
0x19_003C
0x19_0040
0x19_0044
0x19_0048–
0x19_006F
0x19_0070
0x19_0074
0x19_0078
0x19_007C
0x19_0080
Mnemonic
MDA0
MDB0
MDC0
MDD0
MDE0
MDMDS
—
MDMR
MDCR
MDCMR
MDSR
MDISR
MDIMR
MDDSR
MDIN
MDA1
MDB1
MDC1
MDD1
MDE1
[31:24] [23:16] [15:8]
MDHA Mode Register
MDHA Control Register
MDHA Command Register
MDHA Status Register
MDHA Interrupt Status Register
MDHA Interrupt Mask Register
MDHA Data Size Register
MDHA Input FIFO Register
Message Digest A0 Register
Message Digest B0 Register
Message Digest C0 Register
Message Digest D0 Register
Message Digest E0 Register
Message Data Size Register
Reserved
Message Digest A1 Register
Message Digest B1 Register
Message Digest C1 Register
Message Digest D1 Register
Message Digest E1 Register
[7:0] Access
R/W
R/W
R/W
R/W
R/W
R/W
—
R
R/W
R/W
R/W
R/W
R/W
W
R
R/W
R/W
R/W
R/W
R/W
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Freescale Semiconductor 26-3
Message Digest Hardware Accelerator (MDHA)
26.2.1
MDHA Mode Register (MDMR)
The MDMR stores the current processing mode. It can be written before a hashing operation begins. Once the hashing operation has begun an error will be generated if the register is written.
This register is reset only via a hardware or software reset.
.
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
Bits
31–11
10
9
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
0 0 0 0 0 0 0
11 10 9
0 SSL MAC
FULL
8 7 6 5
SWAP OPAD IPAD INIT
20
0
0 0
4
MAC
3
19
0
18
0
17
0
16
0
0 0 0
2 1 0
PDATA 0 ALG
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x19_0000
Figure 26-2. MDHA Mode Register (MDMR)
Table 26-2. MDMR Field Descriptions
0 0 0 0
Name Description
—
SSL
Reserved, should be cleared.
Secure socket layer MAC. Implements the SSL defined MAC. Only applicable for the MD5 algorithm.
0 Do not perform SSL.
1 Perform SSL
MACFULL Message authentication code full. Allows the user to input a key and message data and have the accelerator do the complete MAC in one step. Used directly with HMAC or
EHMAC mode.
0 Do not perform MAC FULL.
1 Perform MAC FULL.
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Freescale Semiconductor
2
1
0
Bits
8
7
6
5
4-3
Memory Map/Register Definition
Name
SWAP
Table 26-2. MDMR Field Descriptions (Continued)
Description
Swap message digest. For SHA-1 only. Swap the output direction of the Message Digest data. The data registers are reversed and byte swapped. This allows for viewing data in the reverse order which might be used by other algorithms. See the table below for an example.
0 Do not perform swap.
1 Swap output direction.
Algorithm
SHA-1
Message
Digest
Register
A0
B0
C0
D0
E0
L
P
D
H
T
SWAP = 0
K
O
C
G
S
J
N
B
F
R
I
M
A
E
Q
I
E
Q
M
A
SWAP = 1
J
F
R
N
B
K
G
S
O
C
L
H
T
P
D
OPAD
IPAD
INIT
MAC
Outer padding of message. Exlusive OR the message with 0x5C5C_5C5C. Hash used with HMAC. Requires key to be loaded into the FIFO
0 Do not perform padding
1 Perform padding
Inner padding of message. Exclusive OR the message with 0x3636_3636. Hash used with
HMAC. Requires key to be loaded into the FIFO
0 Do not perform padding
1 Perform padding
Initialization. Performs algorithm specific initialization of the digest registers. Most operation will require this bit to be set. Only static operations that are continuing from a known intermediate hash value should clear this bit.
0 Do not perform initialization
1 Initialize the selected algorithm’s starting registers
Message authentication code. Performs message authentication on messages. Requires keys loaded into the context and key registers.
00 Do not perform MAC
01 Perform HMAC
10 Perform EHMAC
11 Reserved
PDATA Pad data bit. Performs automatic message padding on the current partial message block.
0 Do not perform padding
1 Perform padding
—
ALG
Reserved, should be cleared.
Algorithm. Selects which algorithm the MDHA module uses
0 Secure Hash Algorithm (SHA-1)
1 Message Digest 5 (MD5)
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Freescale Semiconductor 26-5
Message Digest Hardware Accelerator (MDHA)
26.2.1.1 Invalid Modes
The following mode combinations will trigger an interrupt to the interrupt controller and set the mode error bit in the MDHA interrupt status register.
Table 26-3. Invalid MDMR Bit Settings
MDMR bit settings
Setting any reserved bits.
IPAD=1 OPAD=1
IPAD=1
OPAD=1
MAC=10
(EHMAC)
MAC=10
(EHMAC)
MAC=10
(EHMAC)
MAC=01
(HMAC)
MAC=01
(HMAC)
SSL=1
SWAP=1
PDATA=1
PDATA=1
IPAD=1
OPAD=1
ALG=1
(MD5)
IPAD
OPAD
ALG=0
(SHA-1)
ALG=1
(MD5)
Comments
—
Asserting both of the signals at the same time causes a mode to occur that the MDHA is not capable of performing. These two modes must be performed separately.
According to HMAC and EHMAC standards no padding is done to the data when the IPAD function is performed.
According to HMAC and EHMAC standards no padding is done to the data when the OPAD function is performed.
MDHA requires that the IPAD step be performed as a separate hash operation than message authentication.
MDHA requires that the OPAD step be performed as a separate hash operation than message authentication.
The standard for EHMAC is only defined for the SHA-1 algorithm.
MDHA requires that the IPAD step be performed as a separate hash operation than message authentication.
MDHA requires that the OPAD step be performed as a separate hash operation than message authentication.
SSL MAC is only functional for the MD5 algorithm.
The SWAP bit is designed to support a particular function for the
SHA-1 algorithm and is invalid for MD5.
26.2.2
MDHA Control Register (MDCR)
The MDCR contains bits that should be set following a hardware reset.
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Freescale Semiconductor
Memory Map/Register Definition
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
Bits
31–1
0
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
0
9
0
25
0
0
8
0
24
0
0
7
0
23
0
0
6
0
22
0
0
5
0
21
0
20
0
0
4
0
0
3
0
19
0
0
Name
—
IE
0 0 0 0 0 0 0 1 0 0
IPSBAR + 0x19_0004
Figure 26-3. MDHA Control Register (MDCR)
Table 26-4. MDCR Field Descriptions
0
Description
Reserved
Interrupt enable. Enables/Disables interrupts from the MDHA module.
0 Disable interrupt
1 Enable interrupt
0
18
0
0
2
0
0
1
0
17
0
16
0
0
0
0
IE
0
26.2.3
MDHA Command Register (MDCMR)
The MDCR will always read zeros. The bits in the command register are used for software control of hashing and resetting.
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
0
14
0
0
0 0 0 0 0 0 0 0 0 0 0 0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
0 0 0 0 0 0 0 1 0 0
IPSBAR + 0x19_0008
Figure 26-4. MDHA Command Register (MDCMR)
3
0
GO CI
0 0
2
0
17
0
16
0
0 0
1
0
0
0
RI SWR
0 0
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MCF5271 Reference Manual, Rev. 2
26-7
Message Digest Hardware Accelerator (MDHA)
Bits
31–4
3
2
1
0
Name
—
GO
CI
RI
SWR
Table 26-5. MDCMR Field Descriptions
Description
Reserved
Go. Indicates that all data has been loaded into the input FIFOand the module should complete all processing. This bit is self clearing.
0 Do not complete all processing.
1 Finish all processing.
Clear IRQ. Clears errors in the MDISR register and deasserts any interrupt requests from the MDHA module. This bit is self clearing.
0 Do not clear interrupts & errors.
1 Clear interrupts & errors.
Re-initialize. Re-initializes memory and clears all registers except the MDESM and MDCR.
0 No re-initialization
1 Re-initialize the MDHA module
Software reset. Resets all registers and re-initialize memory of the MDHA. Functionally equivalent to hardware reset. This bit is self clearing.
0 No reset
1 Software reset
26.2.4
MDHA Status Register (MDSR)
The MDSR stores the current status of the MDHA. This register is used to debug errors and to give a view into the workings of the MDHA’s internal engines.
31
R 0
W
Reset 0
15
Field
W
Reset 0
Address
30
0
29
0
0
14
APD
0
13
Bits
31–24
23–16
28
0
0
12
0
27
0
0
11
0
26
0
0
10
25
0
0
9
FS
24
0
23 22 21 20
IFL
19 18 17 16
0
8
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
GNW HSH 0 BUSY RD ERR DONE INT
0
Name
—
IFL
0 0 0 1 0 0 0 0 0 0
IPSBAR + 0x19_000C
Figure 26-5. MDHA Status Register (MDSR)
Table 26-6. MDSR Field Descriptions
1 0 0 0
Bit Description
Reserved, should be cleared.
Input FIFO level. Read-only. The current number of longwords that are in the Input FIFO.
IFL will range from 0–16 longwords (0x00-0x10).
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26-8 Freescale Semiconductor
Bits
15–13
12–11
10–8
7
6
5
4
3
2
1
0
Memory Map/Register Definition
Name
APD
—
FS
GNW
HSH
—
BUSY
RD
ERR
DONE
INT
Table 26-6. MDSR Field Descriptions (Continued)
Bit Description
Auto pad state. Read-only. Indicates the current state of the autopadder for debug purposes.
000 Perform standard auto padding.
001 Pad last word.
010 Add a word for padding.
011 Last hash for the EHMAC.
100 Stall state (Auto Padder will pass no data to engine). This is the default state that the module enters whenever there is an error.
All other settings are reserved.
Reserved, should be cleared.
FIFO size. Read-only. Indicates the size of the internal FIFO, which is fixed at 16 longwords for the MCF5271.
100 16 longwords
Get next word. Read-only. Indicates that the MDHA engine has not filled an entire block and is requesting more data.
0 Does not need any data
1 Requesting more data
Hashing. Read-only. Indicates that data is currently being hashed
0 Waiting for more data
1 Hashing current data
Reserved, should be cleared.
Busy. Read-only. Indicates that the module is busy processing data.
0 Idle or done
1 Busy processing data
Reset interrupt. Read-only. Indicates the MDHA module has completed resetting.
0 Reset in progress
1 Completed reset sequence
Error interrupt. Read-only. Indicates that an error has occurred. Set if any bit in the MDISR is set.
0 No Error
1 Error has occurred
Done interrupt. Read-only. Indicates that the MDHA module has completed processing the requested amount of data.
0 Not complete
1 Done processing
MDHA single interrupt. Read-only. Indicates that either the MDHA module has finished processing the message and the hash result is ready to be read from the message digest register or there is an error.
0 No interrupt
1 Done or error interrupt
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Message Digest Hardware Accelerator (MDHA)
26.2.5
MDHA Interrupt Status & Mask Registers (MDISR and
MDIMR)
The MDISR describes the current error that has taken place. An interrupt request is generated when any one of these bits is set unless the corresponding bit is set in the MDIMR. MDISR is only cleared after a hardware or software reset has been performed. The bit definitions for MDISR and
MDIMR are similar.
NOTE
Masking errors should only be used for debug purposes. A masked error will most likely cause invalid data.
31
R 0
W
Reset 0
30
0
0
29
0
0
28
0
0
27
0
0
26
0
0
25
0
0
24
0
0
23
0
0
22
0
0
21
0
0
20
0
0
19
0
0
18
0
0
17
0
0
16
0
0
15
R 0
W
Reset 0
14
0
13
0
12
0
11
0
10 9 8 7 6 5 4
0 GTDS ERE RMDP 0 DSE IME
3 2 1 0
0 NEIF 0 IFO
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address IPSBAR + 0x19_0010
Figure 26-6. MDHA Interrupt Status & Mask Registers (MDISR and MDIMR)
0
Table 26-7. MDISR & MDIMR Field Descriptions
Bits
31–10
9
8
7
6
Name
—
GTDS
ERE
RMDP
—
Bit Description
Reserved, should be cleared.
Greater than data size error. Read only. Indicates that the GO bit was set in the MDCR and the data size written to the MDDSR is greater then the amount of data written to the FIFO.
0 No error
1 Datasize is greater than the message size
Early read error. Read only. A context register was read from while the module was busy processing data.
0 No error
1 Early read error
Register modified during processing. Read only. An MDHA register was modified while the module was busy processing data.
0 No error
1 Register modified
Reserved, should be cleared.
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Bits
5
4
1
0
3
2
Memory Map/Register Definition
Table 26-7. MDISR & MDIMR Field Descriptions (Continued)
Name
DSE
IME
—
NEIF
—
IFO
Bit Description
Illegal data size. Read only. Illegal data size was written to the MDHA Data Size Register
(MDDSR). Data size written into the MDDSR is greater than the allocated size.
0 No error
1 Illegal data size in MDDSR
Illegal mode interrupt. Read only. Illegal mode is set in the MDMR. Consult
Section 26.2.1.1, “Invalid Modes,”
for more information on invalid modes.
0 No error
1 Illegal value in MDMR
Reserved, should be cleared.
Non-empty input FIFO upon done. Read only. The Input FIFO contained data when processing was completed
0 No error
1 FIFO contained data when finished processing
Reserved
Input FIFO Overflow. Read only. The Input FIFO has been written to while full.
0 No overflow occurred
1 Input FIFO overflow error
26.2.6
MDHA Data Size Register (MDDSR)
The MDDSR stores the size of the last block of data to be processed. This value is in bytes. The first two bits are used to identify the ending byte location in the last word. This is used to add the data padding when auto padding is selected in the MDMR. Load this register with the amount of data to be processed in the FIFO. This register is cleared when the MDHA is reset, re-initialized and at the end of processing the complete message.
18 17 16 31
R 0
W
Reset 0
15
R
W
Reset 0
Address
30
0
29
0
0
14
0
0
13
28 27
0
12
0
11
26
0
10
25
0
9
24 23 22 21
MDHA Data Size
0 0 0
8 7
MDHA Data Size
6
0
5
20
0
4
19
0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x19_001C
Figure 26-7. MDHA Data Size Register (MDDSR)
0
0
3
0
2
0
0
1
0
0
0
0
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Message Digest Hardware Accelerator (MDHA)
26.2.7
MDHA Input FIFO (MDIN)
The MDIN provides temporary storage for data to be used during hashing. The FIFO is a write only register and attempting to read from this register will always return 0. If the FIFO is written to when the FIFO Level is full then an interrupt request is generated and the MDISR[IFO] bit will
be set. The MDSR[IFL], described in Section 26.2.4, “MDHA Status Register (MDSR),” can be
polled to monitor how many 32-bit longwords are currently resident in the FIFO.
26.2.8
MDHA Message Digest Registers 0 (MDx0)
The MDHA message digest registers 0 consist of five 32-bit registers (MDA0, MDB0, MDC0,
MDD0, and MDE0). These registers store the five (SHA-1) or four (MD5) 32-bit longwords that are the final answer (digest/context) of the hashing process. Message digest data may only be read if the MDSR[DONE] bit is set. Any reads prior to this result is an early read error (MDISR[ERE]).
The message digest registers will always return all zeros when an error is generated. Each word
(4 bytes) in the MDx0 is assumed to be in little endian byte order for all reads/writes. All corrections will be done internal. This register is cleared when the MDHA is reset or re-initialized.
The reset values for the registers are the algorithms defined chaining variable values.
31 0
R
W
Reset
MDA0, MDB0, MDC0, MDD0, MDE0
Address
0x0123_4567 (MDA0); 0x89AB_CDEF (MDB0);
0xFEDC_BA98 (MDC0); 0x7654_3210 (MDD0); 0xF0E1_D2C3 (MDE0)
IPSBAR + 0x19_0030 (MDA0); IPSBAR + 0x19_0034 (MDB0);
IPSBAR + 0x19_0038 (MDC0); IPSBAR + 0x19_003C (MDD0); IPSBAR + 0x19_0040 (MDE0)
Figure 26-8. MDHA Message Digest Registers 0 (MDx0)
26.2.9
MDHA Message Data Size Register (MDMDS)
The MDMDS is a 32-bit register which, when read, will store the size of the current hash operation. This register is also used to write in the data size from a resumed hash operation. This data size will be added to the MDDSR to complete the auto pad step.
31 0
R
W
Message Data Size
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address IPSBAR + 0x19_0044
Figure 26-9. MDHA Message Data Size Register (MDMDS)
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Functional Description
26.2.10 MDHA Message Digest Registers 1 (MDx1)
The MDHA message digest registers 1 consist of five 32-bit digest registers (MDA1, MDB1,
MDC1, MDD1, and MDE1). These registers store the OPAD resulted digest to be used for the second hash operation in the HMAC or EHMAC mode. This digest is written directly to the message digest registers 0 after the first hash has been completed. The registers are write only and any attempts to read from them will always return the value zero.
31 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W MDA1, MDB1, MDC1, MDD1, MDE1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address IPSBAR + 0x19_0070 (MDA1); IPSBAR + 0x19_0074 (MDB1);
IPSBAR + 0x19_0078 (MDC1); IPSBAR + 0x19_007C (MDD1); IPSBAR + 0x19_0080 (MDE1)
Figure 26-10. MDHA Message Digest Registers 1 (MDx1)
26.3 Functional Description
The MDHA module consists of three sub-blocks: the FIFO, MDHA Top Control block, and the
MDHA Logic block. A block level diagram of the MDHA module is shown in Figure 26-11 .
Internal Bus Clock (f sys/2
)
MDHA Top Control
Address/Data
FIFO (16x32bit)
Address Decoder
Auto-padder
Hashing
Engine
Hashing
Engine Control
Interface
Control
Status Interrupt
MDHA Logic
Figure 26-11. MDHA Block Diagram
To Interrupt
Controller
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Message Digest Hardware Accelerator (MDHA)
26.3.1
MDHA Top Control
The MDHA Top Control block enables the FIFO whenever the MDHA module is enabled. This block also captures both error and done status from the MDHA Logic block and generates a single interrupt to the interrupt controller.
26.3.2
FIFO
The FIFO block contains a 16 × 32-bit FIFO that is used for temporary storage of the data to be hashed.
26.3.3
MDHA Logic
The MDHA logic block consists of 7 sub-blocks: the address decoder, interface control, auto-padder, auto-padder control, algorithm engine, algorithm engine control, and status interrupt as shown in
.
26.3.3.1 Address Decoder
The address decoder drives out the proper data from the module or captures incoming data into the appropriate register.
26.3.3.2 Interface Control
The interface block decodes the MDMR and outputs all control signals to all other blocks. Control signals are received from other modules to send a pop signal to the FIFO.
26.3.3.3 Auto-Padder
The Auto-padder takes longwords in from the FIFO and then either passes it directly to the engine or pads the word according to the control bits that are set. The IPAD and OPAD is done to all longwords in this block before they are passed directly to the engine. This block takes care of passing the proper data to the engine for the EHMAC mode of operation. This is done by an internal counter that will leave 351 bits in the Input FIFO.
26.3.3.4 Hashing Engine
This module is the core of the Message Digest Hardware Accelerator that is capable of computing the Secure Hash Algorithm (SHA-1) or Message Digest 5 (MD5).
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Initialization/Application Information
26.3.3.5 Hashing Engine Control
This module is the control unit of the MDHA that is capable of computing the Secure Hash
Algorithm (SHA-1) and Message Digest 5 algorithm (MD5). This module keeps track of all rounds and tells the rest of the module when the operation has been completed.
26.3.3.6 Status Interrupt
This block generates the error interrupt if the host performs an illegal operation. The cause of the error is flagged in the MDISR (
Section 26.2.5, “MDHA Interrupt Status & Mask Registers
). If an error occurs, the MDHA core engine is halted. This prevents the core from continuing operation with invalid data.
26.4 Initialization/Application Information
26.4.1
Performing a Standard HASH Operation
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, data padding, and algorithm initialization.
4. Write message data into the FIFO in longwords.
5. MDDSR register write. Load this register with the length of the message data (without padding) in bytes.
6. Set MDCMR[GO].
7. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful completion (or failure).
NOTE
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message data. This will most likely occur if the MDDSR write is not received or auto-padding is disabled and a partial message block is provided.
8. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from the message digest registers.
26.4.2
Performing a HMAC Operation Without the MACFULL Bit
The HMAC is done in three separate steps without the MACFULL bit. Each step requires the reinitialization of the MDHA.
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Message Digest Hardware Accelerator (MDHA)
26.4.2.1 Generation of Key with IPAD
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, IPAD, and MD initialization.
4. The data FIFO is filled with the key.
5. MDDSR register write. Load this register with the length of the key (without padding) in bytes.
6. MDHA does the required IPAD of key.
7. MDHA does the required algorithm’s auto padding of message.
8. Set the MDCMR[GO] bit.
9. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful completion (or failure).
NOTE
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message data. This will most likely occur if the MDDSR write is not received or auto-padding is disabled and a partial message block is provided.
10. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest and the message digest count from the message digest registers.
26.4.2.2 Generation of Key with OPAD
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, OPAD, and MD initialization.
4. The data FIFO is filled with the key.
5. MDDSR register write. Load this register with the length of the key (without padding) in bytes.
6. MDHA does the required OPAD of key.
7. MDHA does the required algorithm’s auto padding of message.
8. Set the MDCMR[GO] bit.
9. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful completion (or failure).
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Initialization/Application Information
NOTE
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message data. This will most likely occur if the MDDSR write is not received or auto-padding is disabled and a partial message block is provided.
10. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest and the message digest count from the message digest registers.
26.4.2.3 HMAC Hash
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, data padding, and HMAC.
4. MDMDS register write. Load this register with the length of the message from the OPAD step.
5. Direct context load of (OPAD XOR key) into MDx1 registers from the OPAD step in the previous section.
6. Direct context load of (IPAD XOR key) into MDx0 registers from the IPAD step.
7. Direct context load of MDMDS register from the IPAD step (this should be 64 bytes).
8. Fill data FIFO with message to be hashed.
9. MDDSR register write. Load this register with the length of the message data (without padding) in bytes.
10. MDHA does the required algorithm’s auto padding of the message.
11. Set the MDCMR[GO] bit.
12. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful completion (or failure).
NOTE
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message data. This will most likely occur if the MDDSR write is not received or auto-padding is disabled and a partial message block is provided.
13. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from the message digest registers.
26.4.3
Performing a SHA-1 EHMAC
EHMAC can only be performed with the SHA-1 algorithm. The Enhanced HMAC requires the keys to be hashed with IPAD and OPAD prior to the step below. The IPAD and OPAD step can be
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Message Digest Hardware Accelerator (MDHA)
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts.
3. MDMR register write. Select algorithm, data padding, and EHMAC.
4. Direct context load of (OPAD XOR key) into MDx1 registers from OPAD step.
5. MDMDS register write. Load this register with the length of the message from the OPAD step.
6. Direct context load of (IPAD XOR key) into MDx0 registers from IPAD step.
7. Direct context load of MDMDS register from the IPAD step (this should be 64 bytes).
8. Fill data FIFO with message to be hashed.
9. MDDSR register write. Load this register with the length of the message data (without padding) in bits.
10. MDHA does the required algorithm’s auto padding of the message.
11. Set the MDCMR[GO] bit.
12. Wait for MDSR[DONE] to be set or done interrupt to be triggered to indicate successful completion (or failure).
NOTE
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message data. This will most likely occur if the MDDSR write is not received or auto-padding is disabled and a partial message block is provided.
13. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from the message digest registers.
26.4.4
Performing a MAC Operation With the MACFULL Bit
The HMAC/EHMAC is done in one step with the MACFULL bit.
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, data padding, HMAC or EHMAC, and
MACFULL bits.
4. Direct context load of key into MDx1 registers.
5. MDMDS register write. Load this register with the length of the key.
6. Fill data FIFO with message to be hashed.
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Initialization/Application Information
7. MDDSR register write. Load this register with the length of the message data (without padding) in bytes.
8. MDHA does the required algorithm’s auto padding of the message.
9. Set the MDCMR[GO] bit.
10. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful completion (or failure).
NOTE
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message data. This will most likely occur if the MDDSR write is not received or auto-padding is disabled and a partial message block is provided.
11. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from the message digest registers.
26.4.5
Performing an NMAC
An NMAC consists of one Hash operation.
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, data padding, HMAC.
4. Direct context load of the second key into DDx1 registers from OPAD step.
5. MDMDS register write. Load this register with the length of the key.
6. Direct context load of the first key into MDx0 registers from IPAD step.
7. MDDSR register write. Load this register with the length of the message data (without padding) in bits.
8. Direct context load of MDMDS register with key size (for NMAC load with data size of 0 bytes).
9. Fill data FIFO with message to be hashed.
10. MDHA does the required algorithm’s auto padding of the message.
11. Set the MDCMR[GO] bit.
12. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful completion (or failure).
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Message Digest Hardware Accelerator (MDHA)
NOTE
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message data. This will most likely occur if the MDDSR write is not received or auto-padding is disabled and a partial message block is provided.
13. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from the message digest registers.
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Chapter 27
Random Number Generator (RNG)
27.1 Introduction
This chapter describes the Random Number Generator (RNG), including a programming model, functional description, and application information.
27.1.1 Overview
The Random Number Generator (RNG) module is capable of generating 32-bit random numbers.
It is designed to comply with FIPS-140 standards for randomness and non-determinism. The random bits are generated by clocking shift registers with clocks derived from ring oscillators. The configuration of the shift registers ensures statistically good data (i.e. data that looks random). The oscillators with their unknown frequencies provide the required entropy needed to create random data.
27.2 Memory Map/Register Definition
The address map for the RNG module is shown in
Table 27-1 . Detailed register descriptions are
found in the following section.
Table 27-1. RNG Module Memory Map
[31:24] [7:0] IPSBAR Offset
0x1A_0000
0x1A_0004
0x1A_0008
0x1A_000C
Mnemonic
RNGCR
RNGSR
RNGER
RNGOUT
[23:16] [15:8]
RNG Control Register
RNG Status Register
RNG Entropy Register
RNG Output FIFO
Access
R/W
R
W
R
27.2.1 RNG Control Register (RNGCR)
Immediately following reset, the RNG begins generating entropy in its internal shift registers.
Random data is not pushed to the output FIFO until after the GO bit in the RNGCR is set to a one.
After this, a random 32-bit word is pushed to the FIFO every 256 cycles. If the FIFO is full, then no push will occur.
In this way the FIFO will be kept as close to full as possible. The fields in the RNGCR are defined in
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Random Number Generator (RNG)
Bits
31–4
3
2
1
0
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
0
9
0
25
0
24
0
0
8
0
0
7
0
23
0
22
0
0
6
0
0
5
0
21
0
0
4
0
20
0
19
0
18
0
17
0
16
0
0 0 0 0
3 2 1 0
CI IM HA GO
Name
—
CI
IM
HA
GO
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1A_0000
Figure 27-1. RNG Control Register (RNGCR)
0 0 0 0
Table 27-2. RNGCR Field Descriptions
Description
Reserved
Clear interrupt. Writing a one to this bit clears the error interrupt and RNGSR[EI].
0 Do not clear error interrupt.
1 Clear error interrupt.
Interrupt mask.
0 Error interrupt is enabled.
1 Error interrupt is masked.
High assurance. Notifies core when FIFO underflow has occurred (FIFO is read while empty). Enables the Security Violation bit in the RNGSR. Bit is sticky and can only be cleared by hardware reset.
0 Disable security violation notification.
1 Enable security violation notification.
Go bit. Starts/stops random data from being generated. Bit is sticky and can only be cleared by hardware reset.
0 FIFO is not loaded with random data.
1 FIFO will be loaded with random data.
27.2.2 RNG Status Register (RNGSR)
The RNGSR, shown in Figure 27-2 , is a read only register which reflects the internal status of the
RNG.
27-2
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Memory Map/Register Definition
.
31
R 0
W
Reset 0
15
R
W
Reset 0
Address
Bits
31–24
23–16
15–8
7–4
3
2
1
0
30
0
0
14
29
0
0
13
28
0
27
0
0 0
12
OFL
11
26
0
0
10
25
0
0
9
0
8
24
0
23
0
7
0
22
0
6
0
21
0
5
0
1
4
0
20
OFS
19 18 17 16
0 0 0 0
3 2 1 0
EI FUF LRS SV
Name
—
OFS
OFL
—
EI
FUF
LRS
SV
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1A_0004
Figure 27-2. RNG Status Register (RNGSR)
0
Table 27-3. RNGSR Field Descriptions
0 0 0
Description
Reserved
Output FIFO size. Indicates size of the Output FIFO (16 words) & maximum possible value of RNGR[OFL].
Output FIFO level. Indicates current number of random words in the Output FIFO. Used to determine if valid random data is available for reading from the FIFO without causing an underflow condition.
Reserved
Error interrupt. Signals a FIFO underflow. Reset by a write to RNGCR[CI] and not masked by RNGCR[IM].
0 FIFO not read while empty.
1 FIFO read while empy.
FIFO underflow. Signals FIFO underflow. Reset by reading status register.
0 FIFO not read while empy, since last read of RNGSR.
1 FIFO read while empty, since last read of RNGSR.
Last read status. Reflects status of most recent read of the FIFO
0 During last read, FIFO was not empty.
1 During last read, FIFO was empy (underflow condition).
Security violation. When enabled by RNGCR[HA], signals that a FIFO underflow has occurred. Bit is sticky and is only cleared by hardware reset
0 No violation occurred or RNGCR[HA] is cleared.
1 Security violation (FIFO underflow) has occurred.
27.2.3 RNG Entropy Register (RNGER)
The RNGER is a write-only register which allows the user to insert entropy into the RNG. This register allows an external user to continually seed the RNG with externally generated random data. Although the use of this register is recommended, it is optional. The RNGER can be written at any time during operation.
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Random Number Generator (RNG)
Each time the RNGER is written, the value is used to update the internal state of the RNG. The update is performed in such a way that the entropy in the RNG’s internal state is preserved. Use of the RNGER can increase the entropy but never decrease it.
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
30
0
0
29
0
0
28
0
0
27
0
0
26
0
0
25
0
0
24
0
0
ENT
0
23
0
22
0
0
21
0
0
20
0
0 0
14
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
0
8
0
0
ENT
0
7
0
6
0
0
5
0
0
4
0
0
IPSBAR + 0x1A_0008
Figure 27-3. RNG Entropy Register (RNGER)
0
3
0
19
0
0
2
0
18
0
0
0
1
0
17
0
0
0
0
0
16
0
0
27.2.4 RNG Output FIFO (RNGOUT)
The RNGOUT provides temporary storage for random data generated by the RNG. As long as the
FIFO is not empty, a read of this address will return 32 bits of random data. If the FIFO is read when it is empty, Error Interrupt, FIFO Underflow and Last Read bits in the RNGSR will be set.
If the interrupt is enabled in the RNGCR an interrupt will be triggered to the interrupt controller.
The RNGSR[OFL], described in
Section 27.2.2, “RNG Status Register (RNGSR)
,” can be polled to monitor how many 32-bit words are currently resident in the FIFO. A new random word is pushed into the FIFO every 256 clock cycles (as long as the FIFO is not full). It is very important that the user polls RNGSR[OFL] to make sure random values are present before reading from the
FIFO.
31
R
W
Reset 0
15
R
W
Reset 0
Address
30 29 28 27
0
14
0
13
0
0
12
0
11
26 25 24 23
Random Output
22
0
10
0 0 0 0
9 8 7
Random Output
6
21 20 19 18 17 16
0
5
0
4
0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1A_000C
Figure 27-4. RNG Output FIFO (RNGOUT)
0
0
3
0
2
0
0
1
0 0
0
0
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Functional Description
27.3 Functional Description
The RNG has three functional blocks. They are the Output FIFO, internal bus interface and the
RNG Core/Control Logic blocks, as shown in
Figure 27-5 . The following sections describe these
blocks in more detail.
Random Number
Generator
RNG Core/Control
Logic
Internal
Control
Signals
Internal Bus
Output FIFO
Figure 27-5. RNG Block Diagram
27.3.1 Output FIFO
The Output FIFO provides temporary storage for random data generated by the RNG Core/Control
Logic block. This allows the user to read multiple random long words back to back. The RNGSR, allows the user to monitor the number of random words in the FIFO through the Output FIFO
Level field. If the user reads from the FIFO when it is empty and the interrupt is enabled, the RNG will drive an interrupt request to the interrupt controller. It is very important that the user polls the
RNGSR[OFL] bit to make sure random values are present before reading from the FIFO.
27.3.2 RNG Core/Control Logic Block
This block contains the RNG’s control logic as well as its core engine used to generate random data.
27.3.3 RNG Control Block
The Control Block contains the address decoder, all addressable registers, and control state machines for the RNG. This block is responsible for communication with both the peripheral interface and the FIFO interface. The block also controls the Core Engine to generate random data.
The general functionality of the block is as follows. After reset, entropy is generated and stored in the RNG’s shift registers. After the GO Bit is set in the RNGCR, the FIFO is loaded with a random word every 256 cycles. The process of loading the FIFO continues as long as the FIFO is not full.
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Freescale Semiconductor 27-5
Random Number Generator (RNG)
27.3.4 RNG Core Engine
The Core Engine Block contains the logic used to generate random data. The logic within the Core
Engine contains the internal shift registers as well as the logic used to generate the two oscillator based clocks. This logic is "brainless" and must be controlled by the Control Block. The Control
Block controls how the shift registers are configured as well as when the oscillator clocks are turned on.
27.4 Initialization/Application Information
The intended general operation of the RNG is as follows:
1. Reset/initialize
2. Write to the RNG entropy register (optional).
3. Write to the RNG control register and set the interrupt mask, high assurance, and GO bits.
4. Poll RNG status register for FIFO level
5. Read available random data from RNG output FIFO
6. Repeat steps 3 and 4 as needed
27-6
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Chapter 28
Symmetric Key Hardware Accelerator
(SKHA)
28.1 Introduction
The Symmetric Key Hardware Accelerator (SKHA) is a cryptographic hardware coprocessor designed to implement two widely used symmetric key block cipher algorithms, AES (Advanced
Encryption Standard) and DES (Data Encryption Standard).
28.1.1 Features
The SKHA supports the following block ciphers:
• AES
— 128-bit key
— Electronic Code Book (ECB), Cipher Block Chaining (CBC), Counter (CTR) cipher modes.
• DES
— 64 bit key (with parity)
— ECB, CBC, and CTR modes
• Triple-DES (3DES)
— 2 key & 3 key (128-bits & 192-bits with parity)
— Key parity check
— ECB, CBC, and CTR modes
28.1.2 Modes of Operation
The SKHA module can encrypt and decrypt the following security algorithms and cipher modes:
• Algorithms: AES, DES, or 3DES
• Cipher modes: ECB, CBC, CTR
28.1.2.1 Data Ecryption Standard (DES & 3DES) Algorithm
The SKHA is able to perform bulk data encryption/decryption in compliance with the Data
Encryption Standard algorithm (ANSI x3.92, FIPS 46-2), as well as 3DES, which is an extension of the DES algorithm.
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Symmetric Key Hardware Accelerator (SKHA)
In DES mode, the SKHA operates by permuting 64-bit data blocks with a shared key and an initialization vector (IV). The SKHA supports two modes of IV operation: Electronic Code Book
(ECB) and Cipher Block Chaining (CBC).
The processor supplies data to the SKHA, and the data will be encrypted and subsequently made available to the processor via an output FIFO. The session key is input to the block prior to encryption.
DES is a block cipher that uses a 56-bit key (64 bits with CRC) to encrypt 64-bit blocks of data,
one block at a time. A conceptual diagram of this process is shown in Figure 28-1 . DES is a
symmetric algorithm, so each of the two communicating parties share the same 64-bit key for encryption and decryption. DES processing begins after this shared session key is agreed upon.
The text or binary message to be encrypted (typically called plaintext) is partitioned into n sets of
64-bit blocks. Each block is processed, in turn, by the DES engine, producing n sets of encrypted
(ciphertext) blocks. These blocks may be transmitted to the other entity.
Decryption is handled in the reverse manner. The ciphertext blocks are processed one at a time by a DES module in the recipient’s system. The same key is used, and the DES block manages the key processing internally so that the plaintext blocks are recovered.
64-bit key
64-bit block n
64-bit block n-1
...
64-bit block 2
64-bit block 1
64-bit block n
Ciphertext blocks
64-bit block n-1
...
64-bit block 2
64-bit block 1
DES
Figure 28-1. DES Encryption Process
In addition, the SKHA module can compute 3DES, which is an extension to the DES algorithm whereby every 64-bit input block is processed three times. The SKHA supports two key (K1=K3) or three key 3DES. A diagram of 3DES is shown in
.
28-2
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Introduction
64-bit K
1
64-bit K
2
64-bit K
3
64-bit block n
Plaintext blocks
64-bit block 1
Ciphertext blocks
64-bit block n
64-bit block 1
DES
1
DES
2
DES
3
Figure 28-2. Triple-DES Encryption Process (ECB Mode)
28.1.2.2 Advanced Encryption Standard (AES) Algorithm
In AES mode, SKHA is used to accelerate bulk data encryption/decryption in compliance with the advanced encryption standard algorithm (AESA) Rinjdael. AES executes on 128-bit blocks with
128-bit key size.
AES is a symmetric key algorithm, the sender and receiver use the same key for both encryption and decryption. The session key and initialization vector (CBC mode) are supplied to the SKHA module prior to encryption. The processor supplies data to the module that is processed as 128-bit input. The SKHA engine performs ten rounds for encryption or decryption. AES operates in ECB,
CBC, and CTR modes.
128-bit key
128-bit block n
Plaintext blocks
128-bit block n-1
...
128-bit block 2
128-bit block 1
128-bit block n
Ciphertext blocks
128-bit block n-1
...
128-bit block 2
128-bit block 1
AES
Figure 28-3. AES Encryption Process
28.1.2.3 Electronic Code Book (ECB) Cipher Mode
The simplest mode is ECB. Each block is processed independently, as shown in
. There is no context used in this mode. Each block of plaintext is encrypted to determine the corresponding ciphertext. In decrypt mode, the ciphertext blocks are decrypted to restore the plaintext.
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Symmetric Key Hardware Accelerator (SKHA)
Plain 1
Encrypt(k)
Plain 2
Encrypt(k)
Plain 3
Encrypt(k)
Plain N
...
Encrypt(k)
Cipher 1 Cipher 2
Decrypt(k) Decrypt(k)
Cipher 3
Decrypt(k)
Cipher N
...
Decrypt(k)
Plain 1 Plain 2 Plain 3
Figure 28-4. ECB Mode Processing
Plain N
28.1.2.4 Cipher Block Chaining (CBC) Cipher Mode
Cipher Block Chaining mode encrypts the output of the previous block with the current block input as shown in
. For decryption, the previous ciphertext block is mixed with the decrypted block as shown in
. A 128-bit random initialization vector (IV) must be loaded prior to processing a message. The context registers are updated internally and must be read and restored during a context switch.
Plain 1 Plain 2 Plain N
IV
...
Encrypt(k)
Encrypt(k) Encrypt(k)
Cipher 1 Cipher 2
Figure 28-5. CBC Encryption
Cipher N
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Introduction
Cipher N Cipher 1 Cipher 2
Decrypt(k) Decrypt(k)
...
Decrypt(k)
IV
Plain 1 Plain 2
Figure 28-6. CBC Decryption
Plain N
28.1.2.5 Counter (CTR) Cipher Mode
In counter mode, a random 128-bit initial counter value is incremented modulo 2 n processed. The modulus size can be set between 2
8
through 2
128
with each block
, by powers of 8 (SKMR[CTRM]).
The running counter is encrypted and XOR’d with the plaintext to derive the ciphertext, or with
the ciphertext to recover the plaintext as shown in Figure 28-7 .
Counter
Encrypt(k)
Counter+1
...
Counter + N-1
Encrypt(k) Encrypt(k)
Plain 1
Cipher 1
Counter
Encrypt(k)
Plain 2 Plain N
Cipher N Cipher 2
Counter+1 Counter + N-1
...
Encrypt(k) Encrypt(k)
Cipher 1 Cipher 2 Cipher N
Plain 1 Plain 2
Figure 28-7. CTR Mode Processing
Plain N
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Symmetric Key Hardware Accelerator (SKHA)
28.2 Memory Map/Register Definition
Table 28-1 shows the SKHA module memory map.
Table 28-1. Module Memory Map
IPSBAR
Offset
0x1B_0070
0x1B_0074
0x1B_0078
0x1B_007C
0x1B_0080
0x1B_0084
0x1B_0088
0x1B_008C
0x1B_0090
0x1B_0094
0x1B_0098
0x1B_009C
0x1B_0000
0x1B_0004
0x1B_0008
0x1B_000C
0x1B_0010
0x1B_0014
0x1B_0018
0x1B_001C
0x1B_0020
0x1B_0024
0x1B_0030
0x1B_0034
0x1B_0038
0x1B_003C
0x1B_0040
0x1B_0044
Mnemonic
SKC1
SKC2
SKC3
SKC4
SKC5
SKC6
SKC7
SKC8
SKC9
SKC10
SKC11
SKC12
SKIN
SKOUT
SKK1
SKK2
SKK3
SKK4
SKK5
SKK6
SKMR
SKCR
SKCMR
SKSR
SKESR
SKEMR
SKKSR
SKDSR
[31:24] [23:16] [15:8] ]7:0]
SKHA Mode Register
SKHA Control Register
SKHA Command Register
SKHA Status Register
SKHA Error Status Register
SKHA Error Status Mask Register
SKHA Key Size Register
SKHA Data Size Register
SKHA Input FIFO
SKHA Output FIFO
SKHA Key 1
SKHA Key 2
SKHA Key 3
SKHA Key 4
SKHA Key 5
SKHA Key 6
SKHA Context 1 (IV/Nonce/Running Offset/CTR/MAC)
SKHA Context 2
SKHA Context 3
SKHA Context 4
SKHA Context 5
SKHA Context 6
SKHA Context 7
SKHA Context 8
SKHA Context 9
SKHA Context 10
SKHA Context 11
SKHA Context 12
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
R/W
R/W
W
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
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Memory Map/Register Definition
28.2.1 Register Descriptions
28.2.1.1 SKHA Mode Register (SKMR)
The SKMR is used to select the cipher algorithm, direction, and cipher mode as shown in
. If the mode is modified during message processing, the SKESR[RM] bit will be set.
The mode may be modified once the module has completed processing, SKSR[DONE] is set.
NOTE
If reserved bits or undefined modes are set, a mode error will be generated.
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
30
0
29
0
0
14
0
0
0
13
0
28
0
27
0
0
12
0
0
11
26
0
25
0
0 0
10
CTRM
9
24
0
23
0
0
8
0 0
7 6
DKP 0
22
0
21
0
0
5
0
20
0
19
0
18
0
17
0
0 0
4
CM
3
0
2
DIR
0 0
1
ALG
0
0 0 0 0 0 0
0 0
0
0
IPSBAR + 0x1B_0000
Figure 28-8. SKHA Mode Register (SKMR)
0
0 0
16
0
0
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28-7
Symmetric Key Hardware Accelerator (SKHA)
Bits
31–12
11–8
Name
—
CTRM
Table 28-2. SKMR Field Descriptions
Description
Reserved, should be cleared.
Counter mode modulus. Specifies modulus size for counter mode. In counter mode, the initial counter value will be incremented modulo 2
N
.
CTR Modulus
CTRM
DES or 3DES AES
0000
0001
...
0110
0111
1000
2
8
2
16
...
2
56
2
64
Reserved
1
Reserved
1
1001
...
1110
1111
...
Reserved
1
Reserved
1
2
2
...
120
128
Note: If CTRM is set to reserved settings for DES or 3DES, a mode error will occur.
2
8
2
16
...
2
56
2
64
2
72
2
80
7
6–5
4–3
2
1–0
DKP
—
CM
DIR
ALG
Disable key parity check. Disables checking DES parity
0 Check for DES key parity errors
1 Do not check for DES key parity errors
Note: A mode error will be generated if this bit is set to one while in AES mode.
Reserved, should be cleared.
Cipher mode. Selects the cipher mode.
00 ECB
01 CBC
10 Reserved
11 CTR
Direction. Selects encryption or decryption
0 Decrypt
1 Encrypt
Algorithm. Selects which algorithm the SKHA module uses
00 AES
01 DES
10 3DES
11 Reserved
28.2.1.2 SKHA Control Register (SKCR)
The SKCR contains bits that should be set after a hardware reset.
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Memory Map/Register Definition
\
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
Bits
31–1
0
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
25
0
0
9
0
0
8
0
24
0
23
0
0
7
0
0
6
0
22
0
21
0
0
5
0
0
4
0
20
0
19
0
0
Name
—
IE
0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1B_0004
Figure 28-9. SKHA Control Register (SKCR)
Table 28-3. SKCR Field Descriptions
Description
Reserved
Interrupt enable.
0 Interrupts disabled
1 Interrupts enabled
0
0
3
0
0
2
0
18
0
17
0
0
0
1
0
0
16
0
0
0
IE
0
28.2.1.3 SKHA Command Register (SKCMR)
31
R 0
W
Reset 0
15
R 0
W
Reset 0
Address
Bits
31–4
3
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
0
11
0
26
0
0
10
0
25
0
0
9
0
0
8
0
24
0
23
0
0
7
0
0
6
0
22
0
21
0
0
5
0
0
4
0
20
0
19
0
18
0
0 0
3 2
GO CI
17
0
16
0
0 0
1 0
RI SWR
0
Name
—
GO
0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1B_0008
Figure 28-10. SKHA Command Register (SKCMR)
0 0 0 0
Table 28-4. SKCMR Field Descriptions
Description
Reserved
Go. Indicates that all data has been loaded into the module and the module should complete all processing. This bit is self resetting.
0 Do not finish processing
1 Complete all processing
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Symmetric Key Hardware Accelerator (SKHA)
Bits
2
1
0
Name
CI
RI
SWR
Table 28-4. SKCMR Field Descriptions (Continued)
Description
Clear Interrupt Request. Clears errors in the SKHA error status registers and deasserts any pending interrupt request to the interrupt controller. This bit is self resetting.
0 Do not clear interrupts & errors
1 Clear interrupt requests & errors
Reinitialize. Reinitializes memory and clears all registers except SKHA Error Status Mask and
Control registers. This bit is self clearing.
0 No Reinitialization
1 Reinitialize SKHA module
Software Reset. Functionally equivalent to a hardware resert. All registers are reset and
FIFOs are cleared. This bit is self clearing.
0 No reset
1 Perform software reset
28.2.1.4 SKHA Status Register (SKSR)
The SKSR is read-only and reflects the current state of the SKHA. It also contains the internal state values of the DES and AES state machines for the purposes of debugging. A write to this register has no effect.
31
R
W
Reset 0
15
R
W
Reset 0
Address
Bits
31–24
23–16
15–11
10–8
7–5
30 29 28
OFL
27
0 0 0
14 13
AESES
12
0
11
26 25 24
0 0 0
10 9
DESES
8
23
0
7
0
22
0
6
0
21 20
IFL
19 18 17 16
0 0 0 0 0 0
5 4 3 2 1 0
0 BUSY RD ERR DONE INT
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1B_000C
Figure 28-11. SKHA Status Register (SKSR)
Table 28-5. SKSR Field Descriptions
0 0 0 0
Name Description
OFL
IFL
Output FIFO level. This 8-bit value indicates the number of data words in the Output FIFO.
Input FIFO level. This 8-bit value indicates the number data words in the Input FIFO.
AESES AES engine state. Current value of AES engine state machine (Debug only)
DESES DES engine state. Current value of DES engine state machine (Debug only)
— Reserved.
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Bits
4
3
2
1
0
Memory Map/Register Definition
Name
BUSY
RD
ERR
DONE
INT
Table 28-5. SKSR Field Descriptions (Continued)
Description
Busy. Indicates the SKHA is busy. Mode, key data, context, and key size registers may not be modified and context registers may not be read while busy.
0 SKHA idle
1 SKHA busy
Reset done. Indicates if reset of the SKHA module has completed.
0 Reset in progress
1 Reset complete
Error interrupt. Indicates that an error has occurred.
0 No error
1 Error occurred
Done interrupt. Indicates that the module has finished processing.
0 Not done
1 Done processing
SKHA interrupt. Indicates that the module has finished processing data and the result is ready to be read from the Output FIFO or there is an error. This bit will assert when an interrupt request in generated unless the SKHACR[IE] bit is not set.
0 No interrupt
1 Done or error interrupt
28.2.1.5 SKHA Error Status Register (SKESR)
The read-only SKESR indicates the type of error that has occurred. These errors are described below and shown in
. When an error occurs, the SKHA engine will halt and assert an interrupt request to the interrupt controller. If multiple errors occur, only the first error will be flagged. The SKHA must be reset when any error occurs. A write to this register has no effect.
31
R 0
W
Reset 0
15
R 0
30
0
0
14
0
29
0
0
13
0
28
0
0
12
0
27
0
26
0
25
0
24
0
23
0
22
0
21 20
0 0
19
0
18
0
17
0
16
0
0 0 0 0 0 0 0 0 0 0 0 0
11 10 9 8 7 6 5
0 KRE KPE ERE RMDP KSE DS
E
4 3 2 1 0
IME NEOF NEIF OFU IFO
W
Reset 0
Address
0 0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1B_0010
Figure 28-12. SKHA Error Status Register (SKESR)
0 0 0
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Symmetric Key Hardware Accelerator (SKHA)
Bits
31–11
10
9
8
7
6
5
4
3
2
1
0
Name
—
KRE
KPE
ERE
RMDP
KSE
DSE
IME
NEOF
NEIF
OFU
IFO
Table 28-6. SKESR Field Descriptions
Bit Description
Reserved
Key read error. An illegal attempt to read the key registers during processing has been detected.
0 No error
1 Key read error occurred
Key parity error. Indicates if a DES key parity error has occurred. Key parity checking can
be disabled by setting the SKMR[DKP] bit (See Section 28.2.1.1, “SKHA Mode Register
0 No error
1 Key parity error occurred
Early read.
0 No error
1 A context register was read from while the module was busy processing data.
Register modified during processing
0 No error
1 A register was modified during processing
Key size Error
0 No error
1 Illegal key size was written into the SKHA key size register
Data size error
0 No error
1 Illegal data size was written into the SKHA data size register
Illegal mode error.
0 No error
1 Illegal mode specified
Non-empty output FIFO upon start.
0 No error
1 Output FIFO contains data upon start of processing
Non-empty input FIFO upon done.
0 No error
1 Input FIFO contained data when processing was complete
Output FIFO underflow
0 No error
1 Output FIFO was read while empty
Input FIFO overflow.
0 No error
1 Input FIFO has been written to while full
28.2.1.6 SKHA Error Status Mask Register (SKESMR)
The SKESMR (located at address IPSBAR + 0x1B_0014) allows the user to mask off any of the
SKHA Error bits and not generate an interrupt. If the error occurs while the corresponding bit is set then the error will be set in the SKESR but the interrupt will not be generated. Additional errors will be flagged in the SKESR until an unmasked error is generated.
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Memory Map/Register Definition
NOTE
Masking errors should only be used for debug purposes. A masked error will most likely cause invalid data.
28.2.1.7 SKHA Key Size Register (SKKSR)
The 6-bit SKKSR is used to set the number of bytes in the key. For AES, this value is always 16
(0x10). For Single DES, the key size must be 8 bytes (0x08). For two key Triple-DES the value should be 16 (0x10), while three key Triple-DES requires a key size of 24 bytes (0x18). The
SKKSR must be set after the key data is written. Once the key size is set, the contents of the key register will be used to initialize the SKHA. If an illegal key size is specified, a key size error will occur, setting SKESR[KSE] and triggering an interrupt to the interrupt controller if KSE is not masked. If the key size is modified during message processing, a register modified error will be generated, setting SKESR[RMDP] and triggering an interrupt to the interrupt controller if RMDP is not masked.
31
R 0
W
Reset 0
15
R
W
R 0
Address
30
0
0
14
29
0
0
13
28
0
0
12
27
0
26
0
0 0
11
—
10
25
0
0
9
0
8
24
0
23
0
0
7
0
6
22
0
21
0
0
5
20
0
19
0
18
0
17
0
0 0 0 0
4 3 2
Key Size in bytes
1
0
0
16
0
0 0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1B_0018
Figure 28-13. SKHA Key Size Register (SKKSR)
0 0 0 0
28.2.1.8 SKHA Data Size Register (SKDSR)
The 32-bit SKDSR holds the number of bytes to process. This value is set prior to loading message data. The SKHA internally decrements this value as it processes the message. The SKDSR may be read at any time to determine the number of bytes that remain to be processed. This value may be modified during message processing. The value written will be internally added to the current value of data size. The SKHA will continue to process data until the value in SKDSR reaches zero.
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Symmetric Key Hardware Accelerator (SKHA)
31
R
W
Reset 0
30
0
29
0
28
0
27
0
26 25 24 23 22
Number of bytes to process
0 0 0 0 0
21
0
20
0
19
0
18
0
17
0
16
0
15
R
W
Reset 0
Address
14
0
13 12 11 10 9 8 7 6
Number of bytes to process
5 4 3
0 0 0 0 0 0 0 0 0 0
IPSBAR + 0x1B_001C
Figure 28-14. SKHA Data Size Register (SKDSR)
0
2
0
1
0
0
0
The value of data size must be a multiple of 8 for DES/3DES or a multiple of 16 for AES.
However, for CTR mode, data size may be a multiple of 8. If an illegal data size is set, a data size error will be generated, setting SKESR[DSE] and generating an interrupt request to the interrupt controller if the DSE bit is not masked.
28.2.1.9 SKHA Input FIFO
The SKHA Input FIFO provides temporary storage for data to be used during processing. The input to the FIFO is accessible through the address IPSBAR + 0x1B_0020 in the address map. The input FIFO is a write-only register and attempting to read from this register will always return zero.
If the FIFO is written to when the FIFO level is full then an interrupt will be generated and
SKESR[IFO] bit will be set. The SKSR[IFL] field, described in Section 28.2.1.4, “SKHA Status
can be polled to monitor how many 32-bit words are currently resident in the
FIFO.
28.2.1.10 SKHA Output FIFO
The SKHA Output FIFO provides temporary storage for data post-processing. The output from the FIFO is accessible through the address IPSBAR + 0x1B_0024 in the address map. The output
FIFO is a read-only register and attempting to write to this register has no effect. If the output FIFO is read from when the FIFO level is empty then an interrupt is generated and SKESR[OFU] is set.
The SKSR[OFL] field, described in Section 28.2.1.4, “SKHA Status Register (SKSR),” can be
polled to monitor how many 32-bit words are currently resident in the FIFO.
28.2.1.11 SKHA Key Data Registers (SKKDRn)
The six 32-bit SKKDRn are write-only and hold the symmetric key. The key should be loaded with the first four bytes placed in Key 1, followed by Key 2, etc. The key should be loaded before setting the key size. Any key data beyond the value specified in the SKKSR will be ignored.
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28-14 Freescale Semiconductor
Memory Map/Register Definition
For AES, which uses a 128-bit key, SKKDR1–SKKDR4 must be written. For single DES,
SKKDR1–SKKDR2 must be written (56-bit key & 8-bit parity). For 2-key 3DES, SKKDR1–4 must be written. For 3-key 3DES, SKKDR1–6 must be written. The SKKDRn registers are
Table 28-7. SKHA Key Data Register Definitions
Algorithm
AES
DES
2 key
3DES
3 key
3DES
SKKDR1 SKKDR2 SKKDR3 SKKDR4
Bytes 1–4
Bytes 1–4
Bytes 5–8
Bytes 5–8
Bytes 9–12
—
Bytes 13–16
—
K1 Bytes 1–4 K1 Bytes 5–8 K2 Bytes 1–4 K2 Bytes 5–8
SKKDR5
—
—
—
SKKDR6
—
—
—
K1 Bytes 1–4 K1 Bytes 5–8 K2 Bytes 1–4 K2 Bytes 5–8 K3 Bytes 1–4 K3 Bytes 5–8
Attempting to read the SKKDRn registers will generate an illegal address error. If the key registers are modified during message processing, a register modify error will be generated, setting
SKESR[RMDP] and triggering an interrupt to the interrupt controller (if RMDP is not masked).
28.2.1.12 SKHA Context Registers (SKCRn)
Prior to loading key data, the user must write the appropriate initialization data to the SKHA.
Following a done interrupt, the user must read the contents of the SKCRn registers prior to switching context. These values must be restored to resume processing of the original message.
The SKCRn registers are loaded differently depending on the algorithm and cipher mode. The location and values are summarized in
. Context should be loaded with the lower bytes in the lowest 32-bit context register.
Ex: 0x0123456789ABCDEF101112131415161718191A1B1C1D1E1F would be loaded as follows:
SKCR1 = 0x0102030405060708090A0B0C0D0E0F
SKCR2 = 0x101112131415161718191A1B1C1D1E1F
Table 28-8. SKHA Context Register Definitions
SKHA Context Register n (32-bits each)
Algorithm
/Mode
DES-ECB
1 2 3 4 5 6 7 8 9 10 11 12
— — — — — — — — — — — —
DES-CBC IV* — — — — — — — — — —
AES-ECB
— — — — — — — — — — — —
AES-CBC IV* — — — — — — — —
DES-CTR
Counter* — — — — — — — — — —
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Symmetric Key Hardware Accelerator (SKHA)
Table 28-8. SKHA Context Register Definitions (Continued)
SKHA Context Register n (32-bits each)
Algorithm
/Mode
AES-CTR
1 2 3 4 5 6 7 8 9 10 11 12
Counter* — — — — — — — —
*Must be written at start of new message
The value written to the IV/Nonce registers will be replaced with the running initialization vector,
IV, (CBC mode) or running counter (CTR mode) once processing begins.
If any context registers are read prior to the SKSR[DONE] bit being set, an early read error,
SKESR[ERE], will be generated and an interrupt request will be sent to the interrupt controller (if
ERE is not masked).
28.3 Functional Description
At the top level, the SKHA consists of seven functional blocks: The input FIFO, the output FIFO, transmit FIFO interface, receive FIFO interface, internal bus interface, top control and the SKHA logic.
Internal Bus
Top Control
Input FIFO Output FIFO
Transmit Receive
SKHA Logic
Internal Bus Interface
Internal Bus
Figure 28-15. SKHA Block Diagram
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Functional Description
28.3.1 Transmit FIFO Interface Block
This block translates the internal FIFO control signals to the input FIFO and passes the message data to the SKHA logic block. The SKHA logic block will continue to pop data from the input
FIFO until the FIFO is empty.
For AES, four 32-bit words are required to process a block. For DES/3DES, two 32-bit words are required to process a block.
28.3.2 Receive FIFO Interface Block
This block translates the internal FIFO control signals to the output FIFO and pass the processed message data from the SKHA logic block. The SKHA logic block will push the same number of words to the output FIFO as it pops from the input FIFO. The SKHA logic block will push to the output FIFO as long as the FIFO is not full. Once the last word is pushed to the output FIFO, the done interrupt will be asserted.
28.3.3 Top Control Block
This block generates the input and output FIFO transmit, receive and request signals and translates other internal signals at the top level.
28.3.4 SKHA Logic Block
This block contains the internal address decoder, addressable registers (key data, key size, data size, mode, context data, and status), interrupt and error logic, and the core engine as shown in
.
.
Key
Registers
Key Size
Register
Error Status
Block
Address
Decoder
SKHA
Core
In Block
Out Block
Mode
Register
Data Size
Register
Status
Register
SKHA LOGIC
Figure 28-16. SKHA Logic Block Diagram
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Symmetric Key Hardware Accelerator (SKHA)
28.3.4.1 Address Decode Logic
The address decoder translates the internal address to write to the proper SKHA registers.
28.3.4.2 Error Interrupt/Status Logic
This block generates the error interrupt if the host performs an illegal operation. The cause of the error is flagged in the SKHA error status register (
Section 28.2.1.5, “SKHA Error Status Register
) and an interrupt is triggered to the interrupt controller. If an error occurs, the SKHA core engine is halted. This prevents the core from continuing operation with invalid data. These error interrupts may be masked off selectively by setting the appropriate bits in the SKHA error status mask register (
Section 28.2.1.6, “SKHA Error Status Mask Register (SKESMR)”
)
28.3.4.3 SKHA Core
The heart of the SKHA is the core processing engine, Figure 28-17 . The core contains the DES
and AES block cipher engines. Also, the cipher mode (ECB, CBC, CTR) is implemented in this block. The SKHA logic block drives the cipher mode, algorithm, processing direction, key, and input block to the Mode Control logic.
While DES and AES operate differently internally, the Mode Control logic operates on top of the
AES and DES engines. The Mode Control logic interfaces to both engines and feeds the input block and key to the selected engine. When the selected engine processes a block, it returns a
"done" signal with the output block. The Mode Control logic in turn returns a "done" signal to the
SKHA logic block along with the processed message block.
When the entire message is processed (following write to the “End of Message” register), the
SKHA logic block sets SKSR[DONE] and generates an interrupt request to the interrupt controller. This will indicate to the user that it is safe to read context.
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Freescale Semiconductor
Initialization/Application Information
Input
Output
Mode Control
Logic
AES
Engine
DES
Engine
128 64 or 192
Key Data
Figure 28-17. SKHA Core Block Diagram
28.3.5 Security Assurance Features
The SKHA features simple security assurance features to prevent operation in the presence of hardware faults and to shield visibility to sensitive data. Further, any user error or internal hardware fault will cause the internal state machines to enter an idle/error state. In this case, the
SKHA must be reset to resume operation, SKCMR[SWR]. Readable registers may be accessed to determine the nature of the error.
28.4 Initialization/Application Information
28.4.1 General Operation
The intended general operation of the SKHA is as follows for ECB, CBC and CTR modes:
1. Reset/initialize.
2. Set algorithm, processing direction, and cipher mode in the SKMR.
3. Write initialization vector/counter to the SKCRn registers, if necessary.
4. Write symmetric key to SKKDRn registers.
5. Set number of bytes in key in the SKKSR.
6. Set the number of bits in the message in the SKDSR.
7. Load the input FIFO with message data.
8. Set the SKCMR[GO] bit.
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Symmetric Key Hardware Accelerator (SKHA)
9. Wait for interrupt, SKSR[INT].
10. Unload processed message data from the output FIFO.
11. Read contents of context registers, if necessary.
12. Set the SKCMR[CI] bit, to clear the done interrupt.
28.4.2 Operation with Context Switch
The intended operation to process part of one message, followed by an intermediate message, and resume processing the original message is as follows:
1. Reset/initialize.
2. Set algorithm, set processing direction and cipher mode in the SKMR.
3. Write IV/Nonce to SKCRn registers.
4. Write the symmetric key to SKKDRn registers.
5. Write the number of bytes in the key to SKKSR.
6. Set number of bits in the first part of message 1 in the SKDSR.
7. Load the input FIFO with first part of message 1.
8. Set the SKCMR[GO] bit.
9. Wait for done interrupt, SKSR[DONE].
10. Unload processed message data from the output FIFO.
11. Read context registers and store contents in memory.
12. Set the SKCMR[CI] bit, to clear the done interrupt.
13. Reset/initialize.
14. Process intermediate message as described in Section 28.4.1, “General Operation.”
15. Reset/initialize.
16. Set algorithm, processing direction and cipher mode in the SKMR.
17. Restore context registers from memory.
18. Restore symmetric key to SKKDRn.
19. Write number of bytes in the key to the SKKSR.
20. Set number of bits in remaining part of message 1 to SKDSR.
21. Load the input FIFO with the remaining portion of message 1.
22. Set the SKCMR[GO] bit.
23. Wait for interrupt, SKSR[INT].
24. Unload processed message data from the output FIFO.
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Chapter 29
IEEE 1149.1 Test Access Port (JTAG)
29.1 Introduction
The Joint Test Action Group, or JTAG, is a dedicated user-accessible test logic, that complies with the IEEE 1149.1 standard for boundary-scan testability, to help with system diagnostic and manufacturing testing.
This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST.
29.1.1 Block Diagram
shows the block diagram of the JTAG module.
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IEEE 1149.1 Test Access Port (JTAG)
TAP CONTROLLER
TDI/DSI
1-BIT BYPASS REGISTER
-BIT BOUNDARY SCAN REGISTER
31
0
0
32-BIT IDCODE REGISTER
1-BIT TEST_CTRL REGISTER
JTAG_EN
TCLK
TMS/BKPT
TRST/DSCLK
5-BIT TAP INSTRUCTION DECODER
4
5-BIT TAP INSTRUCTION REGISTER
0
Disable DSCLK
Force BKPT = 1
DSI = 0
JTAG Module
1
0
1
0
TDO/DSO
DSO to Debug Module
DSI
BKPT
DSCLK
Figure 29-1. JTAG Block Diagram
29.1.2 Features
The basic features of the JTAG module are the following:
• Performs boundary-scan operations to test circuit board electrical continuity
• Bypasses instruction to reduce the shift register path to a single cell
• Sets chip output pins to safety states while executing the bypass instruction
• Samples the system pins during operation and transparently shift out the result
• Selects between JTAG TAP controller and Background Debug Module (BDM) using a dedicated JTAG_EN pin
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External Signal Description
29.1.3 Modes of Operation
The JTAG_EN pin can select between the following modes of operation:
• JTAG mode
• BDM - background debug mode (For more information, refer to
).”
29.2 External Signal Description
The JTAG module has five input and one output external signals, as described in Table 29-1 .
Table 29-1. Signal Properties
Name
JTAG_EN
TCLK
TMS/BKPT
TDI/DSI
TRST/DSCLK
TDO/DSO
Direction
Input
Input
Input
Input
Input
Output
Function
JTAG/BDM selector input
JTAG Test clock input
JTAG Test mode select / BDM Breakpoint
JTAG Test data input / BDM Development serial input
JTAG Test reset input / BDM Development serial clock
JTAG Test data output / BDM Development serial output
Reset State
—
—
—
—
—
Hi-Z / 0
Pull up
—
Active
Active
Active
Active
—
29.2.1 JTAG Enable (JTAG_EN)
The JTAG_EN pin selects between the Debug module and JTAG. If JTAG_EN is low, the Debug
module is selected; if it is high, the JTAG is selected. Table 29-2 summarizes the pin function
selected depending upon JTAG_EN logic state.
Table 29-2. Pin Function Selected
Module selected
Pin Function
JTAG_EN = 0
BDM
—
BKPT
DSI
DSO
DSCLK
JTAG_EN = 1
JTAG
TCLK
TMS
TDI
TDO
TRST
Pin Name
—
TCLK
BKPT
DSI
DSO
DSCLK
When one module is selected, the inputs into the other module are disabled or forced to a known
logic level as shown in Table 29-3 , in order to disable the corresponding module.
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IEEE 1149.1 Test Access Port (JTAG)
Table 29-3. Signal State to the Disable Module
Disabling JTAG
Disabling BDM
JTAG_EN = 0
TRST = 0
TMS = 1
—
JTAG_EN = 1
—
Disable DSCLK
DSI = 0
BKPT = 1
NOTE
The JTAG_EN does not support dynamic switching between JTAG and BDM modes.
29.2.2 Test Clock Input (TCLK)
The TCLK pin is a dedicated JTAG clock input to synchronize the test logic. Pulses on TCLK shift data and instructions into the TDI pin on the rising edge and out of the TDO pin on the falling edge.
TCLK is independent of the processor clock. The TCLK pin has an internal pull-up resistor and holding TCLK high or low for an indefinite period does not cause JTAG test logic to lose state information.
29.2.3 Test Mode Select/Breakpoint (TMS/BKPT)
The TMS pin is the test mode select input that sequences the TAP state machine. TMS is sampled on the rising edge of TCLK. The TMS pin has an internal pull-up resistor.
The BKPT pin is used to request an external breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes.
29.2.4 Test Data Input/Development Serial Input (TDI/DSI)
The TDI pin receives serial test and data, which is sampled on the rising edge of TCLK. Register values are shifted in least significant bit (lsb) first. The TDI pin has an internal pull-up resistor.
The DSI pin provides data input for the debug module serial communication port.
29.2.5 Test Reset/Development Serial Clock (TRST/DSCLK)
The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the TAP controller to the test-logic-reset state.
The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency is 1/5 the processor clock speed. At the rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.
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Memory Map/Register Definition
29.2.6 Test Data Output/Development Serial Output (TDO/DSO)
The TDO pin is the lsb-first data output. Data is clocked out of TDO on the falling edge of TCLK.
TDO is tri-stateable and is actively driven in the shift-IR and shift-DR controller states.
The DSO pin provides serial output data in BDM mode.
29.3 Memory Map/Register Definition
The JTAG module registers are not memory mapped and are only accessible through the
TDO/DSO pin.
29.3.1 Register Descriptions
All registers are shift-in and parallel load.
29.3.1.1 Instruction Shift Register (IR)
The JTAG module uses a -bit shift register with no parity. The IR transfers its value to a parallel hold register and applies an instruction on the falling edge of TCLK when the TAP state machine is in the update-IR state. To load an instruction into the shift portion of the IR, place the serial data on the TDI pin before each rising edge of TCLK. The msb of the IR is the bit closest to the TDI pin, and the lsb is the bit closest to the TDO pin.
29.3.1.2 IDCODE Register
The IDCODE is a read-only register; its value is chip dependent. For more information, see
Section 29.4.3.2, “IDCODE Instruction .”
30
PRN
29 28 27 26 25
DC
24 23 22 21 20 19
PIN
18 17 16
R
W
Reset
31
15
R
W
Reset
PRN
14
PIN
13
PIN
12
0
11
1
10
1
9
1
8
0 1
7 6
JEDEC
5
0 0 0 0 0 0
Figure 29-2. IDCODE Register
0
4
1
3
PIN
2
1 1
1
0
0
ID
1
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IEEE 1149.1 Test Access Port (JTAG)
Bits
31–28
27–22
21–12
11–1
0
Table 29-4. IDCODE Field Descriptions
Name Description
PRN
DC
Part revision number. Indicate the revision number of the device.
Freescale Design Center number.
PIN Part identification number. Indicate the device number.
JEDEC Joint Electron Device Engineering Council ID bits. Indicate the reduced JEDEC ID for
Freescale.
ID IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and not the bypass register according to the IEEE standard 1149.1.
29.3.1.3 Bypass Register
The bypass register is a single-bit shift register path from TDI to TDO when the BYPASS,
CLAMP, or HIGHZ instructions are selected. After entry into the Capture-DR state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the bypass register is always a logic 0.
29.3.1.4 TEST_CTRL Register
The TEST_CTRL register is a 1-bit shift register path from TDI to TDO when the
ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold register on the rising edge of TCLK when the TAP state machine is in the Update-DR state.
The DSE bit selects the drive strength used in JTAG mode.
R
W
0
DSE
Reset
0
Figure 29-3. 1-Bit TEST_CTRL Register
29.3.1.5 Boundary Scan Register
The boundary scan register is connected between TDI and TDO when the EXTEST, SAMPLE or
SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on output pins, and selects a logic value and direction for bidirectional pins or high impedance for tri-stated pins.
The boundary scan register contains bits for bonded-out and non bonded-out signals excluding
JTAG signals, analog signals, power supplies, compliance enable pins, device configuration pins, and clock signals.
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Functional Description
29.4 Functional Description
29.4.1 JTAG Module
The JTAG module consists of a TAP controller state machine, which is responsible for generating all control signals that execute the JTAG instructions and read/write data registers.
29.4.2 TAP Controller
The TAP controller is a state machine that changes state based on the sequence of logical values on the TMS pin.
shows the machine’s states. The value shown next to each state is the value of the TMS signal sampled on the rising edge of the TCLK signal.
Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state.
As
shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state.
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IEEE 1149.1 Test Access Port (JTAG)
1 TEST-LOGIC-RESET
0
0 RUN-TEST/IDLE
1
1
SELECT DR-SCAN
0
1
CAPTURE-DR
0
SHIFT-DR
1
0
0
1
0
PAUSE-DR
1
EXIT2-DR
1
UPDATE-DR
1 0
0
1
SELECT IR-SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
1
EXIT1-IR
0
0
1
0
0
PAUSE-IR
1
EXIT2-IR
1
UPDATE-IR
1 0
Figure 29-4. TAP Controller State Machine Flow
29.4.3 JTAG Instructions
The below table describes public and private instructions.
Table 29-5. JTAG Instructions
Instruction
IDCODE
SAMPLE/PRELOAD
SAMPLE
IR[4:0] Instruction Summary
00001 Selects IDCODE register for shift
00010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation
00011 Selects boundary scan register for shifting and sampling without disturbing functional operation
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Functional Description
Table 29-5. JTAG Instructions (Continued)
Instruction IR[4:0] Instruction Summary
EXTEST
ENABLE_TEST_CTRL
HIGHZ
00100 Selects boundary scan register while applying fixed values to output pins and asserting functional reset
00110
01001
Selects TEST_CTRL register
Selects bypass register while tri-stating all output pins and asserting functional reset
CLAMP 01100 Selects bypass while applying fixed values to output pins and asserting functional reset
ACCESS_AUX_TAP_eTPU 10000 Enables access to the eTPU Nexus TAP controller
BYPASS
Reserved
11111 all others
Selects bypass register for data operations
Decoded to select bypass register
1
1
Freescale reserves the right to change the decoding of the unused opcodes in the future.
29.4.3.1 EXTEST Instruction
The external test (EXTEST) instruction selects the boundary scan register. It forces all output pins and bidirectional pins configured as outputs to the values preloaded with the
SAMPLE/PRELOAD instruction and held in the boundary scan update registers. EXTEST can also configure the direction of bidirectional pins and establish high-impedance states on some pins. EXTEST asserts internal reset for the MCU system logic to force a predictable internal state while performing external boundary scan operations.
29.4.3.2 IDCODE Instruction
The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path between the TDI and TDO pin. This instruction allows interrogation of the MCU to determine its version number and other part identification data. The shift register lsb is forced to logic 1 on the rising edge of TCLK following entry into the capture-DR state. Therefore, the first bit to be shifted out after selecting the IDCODE register is always a logic 1. The remaining 31 bits are also forced to fixed values on the rising edge of TCLK following entry into the capture-DR state.
IDCODE is the default instruction placed into the instruction register when the TAP resets. Thus, after a TAP reset, the IDCODE register is selected automatically.
29.4.3.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction has two functions:
• PRELOAD - initialize the boundary scan register update cells before selecting EXTEST or
CLAMP. This is achieved by ignoring the data shifting out on the TDO pin and shifting in initialization data. The update-DR state and the falling edge of TCLK can then transfer this
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IEEE 1149.1 Test Access Port (JTAG) data to the update cells. The data is applied to the external output pins by the EXTEST or
CLAMP instruction.
29.4.3.4 ENABLE_TEST_CTRL Instruction
The ENABLE_TEST_CTRL instruction selects a -bit shift register (TEST_CTRL) for connection as a shift path between the TDI and TDO pin. When the user transitions the TAP controller to the
UPDATE_DR state, the register transfers its value to a parallel hold register.
29.4.3.5 HIGHZ Instruction
The HIGHZ instruction eliminates the need to backdrive the output pins during circuit-board testing. HIGHZ turns off all output drivers, including the 2-state drivers, and selects the bypass register. HIGHZ also asserts internal reset for the MCU system logic to force a predictable internal state.
29.4.3.6 CLAMP Instruction
The CLAMP instruction selects the 1-bit bypass register and asserts internal reset while simultaneously forcing all output pins and bidirectional pins configured as outputs to the fixed values that are preloaded and held in the boundary scan update register. CLAMP enhances test efficiency by reducing the overall shift path to a single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary scan register.
29.4.3.7 BYPASS Instruction
The BYPASS instruction selects the bypass register, creating a single-bit shift register path from the TDI pin to the TDO pin. BYPASS enhances test efficiency by reducing the overall shift path when a device other than the ColdFire processor is the device under test on a board design with multiple chips on the overall boundary scan chain. The shift register lsb is forced to logic 0 on the rising edge of TCLK after entry into the capture-DR state. Therefore, the first bit shifted out after selecting the bypass register is always logic 0. This differentiates parts that support an IDCODE register from parts that support only the bypass register.
29.5 Initialization/Application Information
29.5.1 Restrictions
The test logic is a static logic design, and TCLK can be stopped in either a high or low state without loss of data. However, the system clock is not synchronized to TCLK internally. Any mixed operation using both the test logic and the system functional logic requires external synchronization.
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Initialization/Application Information
Using the EXTEST instruction requires a circuit-board test environment that avoids device-destructive configurations in which MCU output drivers are enabled into actively driven networks.
Low-power stop mode considerations:
• The TAP controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. Leaving the test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality.
• The TCLK input is not blocked in low-power stop mode. To consume minimal power, the
TCLK input should be externally connected to V
DD
.
• The TMS, TDI, and TRST pins include on-chip pull-up resistors. For minimal power consumption in low-power stop mode, these three pins should be either connected to V
DD or left unconnected.
29.5.2 Nonscan Chain Operation
Keeping the TAP controller in the test-logic-reset state ensures that the scan chain test logic is transparent to the system logic. It is recommended that TMS, TDI, TCLK, and TRST be pulled up. TRST could be connected to ground. However, since there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST.
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IEEE 1149.1 Test Access Port (JTAG)
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Chapter 30
Debug Support
30.1 Introduction
This chapter describes the Revision A enhanced hardware debug support in the MCF5271.
30.1.1 Overview
The debug module is shown in
ColdFire CPU Core
High-speed core bus
(f sys
)
Debug Module
Control
BKPT
Trace Port
PST[3:0], DDATA[3:0]
PSTCLK
Communication Port
DSCLK, DSI, DSO
Figure 30-1. Processor/Debug Module Interface
Debug support is divided into three areas:
• Real-time trace support—The ability to determine the dynamic execution path through an application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel output bus that reports processor execution status and data to an external emulator system. See
Section 30.3, “Real-Time Trace Support
.”
• Background debug mode (BDM)—Provides low-level debugging in the ColdFire processor complex. In BDM, the processor complex is halted and a variety of commands can be sent to the processor to access memory and registers. The external emulator uses a three-pin, serial, full-duplex channel. See
Section 30.5, “Background Debug Mode
,” and
Section 30.4, “Memory Map/Register Definition
.”
• Real-time debug support—BDM requires the processor to be halted, which many real-time embedded applications cannot do. Debug interrupts let real-time systems execute a unique service routine that can quickly save the contents of key registers and variables and return the system to normal operation. External development systems can access saved data because the hardware supports concurrent operation of the processor and BDM-initiated
commands. See Section 30.6, “Real-Time Debug Support .”
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Debug Support
30.2 External Signal Description
Table 30-1 describes debug module signals. All ColdFire debug signals are unidirectional and
related to a rising edge of the processor’s clock signal. The standard 26-pin debug connector is shown in
Section 30.8, “Freescale-Recommended BDM Pinout
.”
Table 30-1. Debug Module Signals
Signal Description
Development Serial
Clock (DSCLK)
Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two consecutive rising PSTCLK edges.) Clocks the serial communication port to the debug module during packet transfers. Maximum frequency is 1/5 the processor status clock (PSTCLK) speed. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.
Development Serial
Input (DSI)
Internally synchronized input that provides data input for the serial communication port to the debug module.
Development Serial
Output (DSO)
Provides serial output communication for debug module responses. DSO is registered internally.
Breakpoint (BKPT) Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status signals
(PST[3:0]) as the value 0xF.
PSTCLK
. PSTCLK indicates when the development system should sample PST and
DDATA values.
Debug Data
(DDATA[3:0])
Processor Status
(PST[3:0])
These output signals display the register breakpoint status as a default, or optionally, captured address and operand values. The capturing of data values is controlled by the setting of the
CSR. Additionally, execution of the WDDATA instruction by the processor captures operands which are displayed on DDATA. These signals are updated each processor cycle.
These output signals report the processor status. Table 30-2
shows the encoding of these signals. These outputs indicate the current status of the processor pipeline and, as a result, are not related to the current bus transfer. The PST value is updated each processor cycle.
shows PSTCLK timing with respect to PST and DDATA.
PSTCLK
PST or DDATA
Figure 30-2. PSTCLKTiming
30.3 Real-Time Trace Support
Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The
ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system. This port is partitioned into two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and the other allows operand data to be
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Real-Time Trace Support displayed (debug data, DDATA). The processor status may not be related to the current bus transfer.
External development systems can use PST outputs with an external image of the program to completely track the dynamic execution path. This tracking is complicated by any change in flow, especially when branch target address calculation is based on the contents of a program-visible register (variant addressing). DDATA outputs can be configured to display the target address of such instructions in sequential nibble increments across multiple processor clock cycles, as described in
Section 30.3.1, “Begin Execution of Taken Branch (PST = 0x5)
.” Two 32-bit storage elements form a FIFO buffer connecting the processor’s high-speed local bus to the external development system through PST[3:0] and DDATA[3:0]. The buffer captures branch target addresses and certain data values for eventual display on the DDATA port, one nibble at a time starting with the least significant bit (lsb).
Execution speed is affected only when both storage elements contain valid data to be dumped to the DDATA port. The core stalls until one FIFO entry is available.
Table 30-2 shows the encoding of these signals.
Table 30-2. Processor Status Encoding
PST[3:0]
Definition
Hex Binary
0x0 0000 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more processor clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
0x1 0001 Begin execution of one instruction. For most instructions, this encoding signals the first processor clock cycle of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and
WDDATA instructions, generate different encodings.
0x2 0010 Reserved
0x3 0011 Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to enter user mode.
0x4 0100 Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to the DDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is signaled on the PST port, followed by the appropriate marker, and then the data transfer on the DDATA port. Transfer length depends on the WDDATA operand size.
0x5 0101 Begin execution of taken branch. For some opcodes, a branch target address may be displayed on
DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins the data output. See
Section 30.3.1, “Begin Execution of Taken Branch (PST = 0x5) .”
0x6 0110 Reserved
0x7 0111 Begin execution of return from exception (RTE) instruction.
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Table 30-2. Processor Status Encoding (Continued)
PST[3:0]
Definition
Hex Binary
0x8–
0xB
1000–
1011
Indicates the number of bytes to be displayed on the DDATA port on subsequent processor clock cycles. The value is driven onto the PST port one PSTCLK cycle before the data is displayed on
DDATA.
0x8 Begin 1-byte transfer on DDATA.
0x9 Begin 2-byte transfer on DDATA.
0xA Begin 3-byte transfer on DDATA.
0xB Begin 4-byte transfer on DDATA.
0xC 1100 Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace) generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle mode, PST outputs are driven with 0xC until exception processing completes.
0xD 1101 Entry into emulator mode.
Displayed during emulation mode (debug interrupt or optionally trace).
Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception processing completes.
0xE 1110 Processor is stopped. Appears in multiple-cycle format when the MCF5271 executes a STOP instruction. The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the stopped mode is exited
.
0xF 1111 Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display
0xF until the processor is restarted or reset. (see
30.3.1 Begin Execution of Taken Branch (PST = 0x5)
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed on DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data output.
Bytes are displayed in least-to-most-significant order. The processor captures only those target addresses associated with taken branches which use a variant addressing mode, that is, RTE and
RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and all exception vectors.
The simplest example of a branch instruction using a variant address is the compiled code for a C language case statement. Typically, the evaluation of this statement uses the variable of an expression as an index into a table of offsets, where each offset points to a unique case within the structure. For such change-of-flow operations, the MCF5271 uses the debug pins to output the following sequence of information on successive processor clock cycles:
1. Use PST (0x5) to identify that a taken branch was executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially on the
DDATA pins. Encodings 0x9–0xB identify the number of bytes displayed.
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Memory Map/Register Definition
3. The new target address is optionally available on subsequent cycles using the DDATA port. The number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes).
Another example of a variant branch instruction would be a JMP (A0) instruction.
shows the PST and DDATA outputs that indicate a JMP (A0) execution (assuming the CSR was programmed to display the lower 2 bytes of an address).
PSTCLK
PST 0x5 0x9 default default default default
DDATA 0x0 0x0 A[3:0] A[7:4] A[11:8] A[15:12]
Figure 30-3. Example JMP Instruction Output on PST/DDATA
PST 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the subsequent 4 nibbles of DDATA display the lower 2 bytes of address register A0 in least-to-most-significant nibble order. The PST output after the JMP instruction completes depends on the target instruction. The PST can continue with the next instruction before the address has completely displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO.
30.4 Memory Map/Register Definition
In addition to the existing BDM commands that provide access to the processor’s registers and the memory subsystem, the debug module contains 19 registers to support the required functionality.
These registers are also accessible from the processor’s supervisor programming model by executing the WDEBUG instruction (write only). Thus, the breakpoint hardware in the debug module can be written by the external development system using the debug serial interface or by the operating system running on the processor core. Software is responsible for guaranteeing that accesses to these resources are serialized and logically consistent. Hardware provides a locking mechanism in the CSR to allow the external development system to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]). BDM commands must not be issued if the MCF5271 is using the WDEBUG instruction to access debug module registers or the resulting behavior is undefined.
These registers, shown in
, are treated as 32-bit quantities, regardless of the number of implemented bits.
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Debug Support
Table 30-3. Debug Programming Model
[31:24] [23:16] [15:8] [7:0] Mnemonic
— Address Attribute Trigger Register
Address Low Breakpoint Register
Address High Breakpoint Register
Configuration/Status Register
Data Breakpoint Register
Data Breakpoint Mask Register
PC Breakpoint Register
PC Breakpoint Mask Register
AATR
ABLR
ABHR
CSR
DBR
DBMR
PBR
PBMR
Trigger Definition Registers TDR
Note: Each debug register is accessed as a 32-bit register; reserved fields above are not used (don’t care). All debug control registers are writable from the external development system or the CPU via the WDEBUG instruction. CSR is write-only from the programming model. It can be read or written through the BDM port using the rdmreg and wdmreg commands.
Figure 30-4. Debug Programming Model
These registers are accessed through the BDM port by the commands, WDMREG and RDMREG , described in
Section 30.5.3.3, “Command Set Descriptions .” These commands contain a 5-bit
field, DRc, that specifies the register, as shown in
.
Table 30-4. BDM/Breakpoint Registers
DRc[4–0] Register Name
0x00 Configuration/status register
0x01–0x05 Reserved
0x06
0x07
Address attribute trigger register
Trigger definition register
0x08
0x09
Program counter breakpoint register
Program counter breakpoint mask register
0x0A–0x0B Reserved
0x0C Address breakpoint high register
0x0D
0x0E
0x0F
Address breakpoint low register
Data breakpoint register
Data breakpoint mask register
Mnemonic
CSR
—
AATR
TDR
PBR
PBMR
—
ABHR
ABLR
DBR
DBMR
Initial State Page
0x0001_0000
— —
0x0000_0005
0x0000_0000
—
—
—
—
—
—
—
—
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Memory Map/Register Definition
NOTE
Debug control registers can be written by the external development system or the CPU through the WDEBUG instruction.
CSR is write-only from the programming model. It can be read or written through the BDM port using the RDMREG and WDMREG commands.
30.4.1 Revision A Shared Debug Resources
In the Revision A implementation of the debug module, certain hardware structures are shared
between BDM and breakpoint functionality as shown in Table 30-5 .
Table 30-5. Rev. A Shared BDM/Breakpoint Hardware
Register
AATR
ABHR
DBR
BDM Function Breakpoint Function
Bus attributes for all memory commands Attributes for address breakpoint
Address for all memory commands Address for address breakpoint
Data for all BDM write commands Data for data breakpoint
Thus, loading a register to perform a specific function that shares hardware resources is destructive to the shared function. For example, a BDM command to access memory overwrites an address breakpoint in ABHR. A BDM write command overwrites the data breakpoint in DBR.
30.4.2 Address Attribute Trigger Register (AATR)
The AATR, shown in
, defines address attributes and a mask to be matched in the trigger. The register value is compared with address attribute signals from the processor’s local high-speed bus, as defined by the setting of the trigger definition register (TDR). AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the
WDMREG
command.
15
R
W RM
Reset 0
DRc[4:0]
14 13 12 11 10 9 8 7 6 5 4 3 2
0
SZM
0 0
TTM
0 0
TMM
0 0
R
0 0
SZ
0 0
TT
0
0x06
Figure 30-5. Address Attribute Trigger Register (AATR)
1
1 0
TM
0 1
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Debug Support
Bits
15
14–13
12–11
10–8
7
6–5
4–3
2–0
Table 30-6. AATR Field Descriptions
Name Description
RM
SZM
TTM
TMM
R
SZ
TT
TM
Read/write mask. Setting RM masks R in address comparisons.
Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.
Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.
Transfer modifier mask. Setting a TMM bit masks the corresponding TM bit in address comparisons.
Read/write. R is compared with the R/W signal of the processor’s local bus.
Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
Transfer type. Compared with the local bus transfer type signals.
00 Normal processor access
01 Reserved
10 Emulator mode access
11 Acknowledge/CPU space access
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding indicates an external or DMA access (for backward compatibility). These bits affect the TM bits.
Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental information for each transfer type. These bits also define the TM encoding for BDM memory commands (for backward compatibility).
TM
000
001
010
011
100
101
110
111
TT=00
(normal mode)
Explicit cach line push
User data access
User code access
Reserved
Reserved
Supervisor data access
Supervisor code access
Reserved
TT=10
(emulator mode)
Reserved
Reserved
Reserved
Reserved
Reserved
Emulator mode access
Emulator code
Access
Reserved
TT=11
(acknowledge/CPU space transfers)
CPU space access
Interrupt ack level 1
Interrupt ack level 2
Interrupt ack level 3
Interrupt ack level 4
Interrupt ack level 5
Interrupt ack level 6
Interrupt ack level 7
30.4.3 Address Breakpoint Registers (ABLR, ABHR)
The ABLR and ABHR, shown in
, define regions in the processor’s data address space that can be used as part of the trigger. These register values are compared with the address for each
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Memory Map/Register Definition transfer on the processor’s high-speed local bus. The trigger definition register (TDR) identifies the trigger as one of three cases:
1. Identical to the value in ABLR
2. Inside the range bound by ABLR and ABHR inclusive
3. Outside that same range
ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction and via the BDM port using the RDMREG and WDMREG commands. ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and via the
BDM port using the WDMREG command.
31
R
W
Reset —
15
R
W
Reset —
DRc[4:0]
Bits
31–0
30
—
14
29
—
13
28
—
12
27
—
11
26
—
10
25
—
9
24 23
Address
— —
8 7
22
—
6
21
—
5
20
—
4
19
—
3
18
—
2
17
—
1
16
—
0
— — — — — —
Address
— — — — — —
0x0D (ABLR); 0x0C (ABHR)
Figure 30-6. Address Breakpoint Registers (ABLR, ABHR)
— — —
Table 30-7. ABLR Field Description
Name Description
Address Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for specific addresses are programmed into ABLR.
Bits
31–0
Table 30-8. ABHR Field Description
Name Description
Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
30.4.4 Configuration/Status Register (CSR)
The CSR defines the debug configuration for the processor and memory subsystem and contains status information from the breakpoint logic. CSR is write-only from the programming model. It can be read from and written to through the BDM port. CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and through the BDM port using the
RDMREG and WDMREG commands.
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Debug Support
31
R
W
Reset 0
30 29
BSTAT
0 0
28
0
27 26 25 24
FOF TRG HALT BKPT
23
0 0 0 0 0
22
HRL
21
0 0
20
0
19
0
0
18
0
0
17 16
0 IPW
0 0
15 14 13
R MAP TRC EMU
W
Reset 0
DRc[4:0]
0 0
12
DDC
11
0 0
10
UHE
0
9
0
BTB
8
0
0x00
7 6 5 4 3
0 NPL IPI SSM 0
0 0 0 0
Figure 30-7. Configuration/Status Register (CSR)
0
Table 30-9. CSR Field Descriptions
Bits
31–28
27
26
25
24
23–20
19–17
16
15
14
Name
BSTAT
FOF
TRG
HALT
BKPT
HRL
—
IPW
MAP
TRC
2
0
0
1
0
0
0
0
0
Description
Breakpoint status. Provides read-only status information concerning hardware breakpoints. BSTAT is cleared by a TDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM. FOF is cleared whenever CSR is read.
Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and forced entry into BDM. Reset, the debug GO command, or reading CSR will clear
TRG.
Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM.
Reset, the debug
GO
command, or reading CSR will clear HALT.
Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM.
Reset, the debug
GO
command, or reading CSR will clear BKPT.
Hardware revision level. Indicates the level of debug module functionality. An emulator could use this information to identify the level of functionality supported.
0000 Initial debug functionality (Revision A) (This is the only valid value for the MCF5271)
Reserved, should be cleared.
Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s programming model registers. IPW can be modified only by commands from the external development system.
Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space,
TT = 10, TM = 101 or 110.
Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a trace exception occurs. If TRC=0, the processor enters supervisor mode.
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Bits
13
12–11
10
9–8
7
6
5
4
3–0
Memory Map/Register Definition
Name
EMU
DDC
UHE
BTB
—
NPL
IPI
SSM
—
Table 30-9. CSR Field Descriptions (Continued)
Description
Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See
Section 30.6.1.1, “Emulator Mode .”
Debug data control. Controls operand data capture for DDATA, which displays the number of bytes defined by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long displays 32 bits (one nibble at a time across multiple
PSTCLK cycles). See Table 30-2
.
00 No operand data is displayed.
01 Capture all write data.
10 Capture all read data.
11 Capture all read and write data.
User halt enable. Selects the CPU privilege level required to execute the HALT instruction.
0 HALT is a supervisor-only instruction.
1 HALT is a supervisor/user instruction.
Branch target bytes. Defines the number of bytes of branch target address DDATA displays.
00 0 bytes
01 Lower 2 bytes of the target address
10 Lower 3 bytes of the target address
11 Entire 4-byte target address
See
Section 30.3.1, “Begin Execution of Taken Branch (PST = 0x5) .”
Reserved, should be cleared.
Non-pipelined mode. Determines whether the core operates in pipelined or mode or not.
0 Pipelined mode
1 Nonpipelined mode. The processor effectively executes one instruction at a time with no overlap. This adds at least 5 cycles to the execution time of each instruction. Given an average execution latency of 1.6 cycles/instruction, throughput in non-pipeline mode would be 6.6 cycles/instruction, approximately 25% or less of pipelined performance.
Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering instruction executes. In normal pipeline operation, the occurrence of an address and/or data breakpoint trigger is imprecise. In non-pipeline mode, triggers are always reported before the next instruction begins execution and trigger reporting can be considered precise.
Ignore pending interrupts.
1 Core ignores any pending interrupt requests signalled while in single-instruction-step mode.
0 Core services any pending interrupt requests that were signalled while in single-step mode.
Single-step mode. Setting SSM puts the processor in single-step mode.
0 Normal mode.
1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed. On receipt of the
GO
command, the processor executes the next instruction and halts again. This process continues until SSM is cleared.
Reserved, should be cleared.
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30.4.5 Data Breakpoint/Mask Registers (DBR, DBMR)
The DBR, shown in
, specifies data patterns used as part of the trigger into debug mode. DBR bits are masked by setting corresponding DBMR bits, as defined in TDR. DBR is accessible in supervisor mode as debug control register 0x0E, using the WDEBUG instruction and through the BDM port using the
RDMREG
and
WDMREG
commands. DBMR is accessible in supervisor mode as debug control register 0x0F, using the WDEBUG instruction and via the BDM port using the
WDMREG
command.
31
R
W
Reset —
15
R
W
Reset —
DRc[4:0]
Bits
31–0
30
—
14
29
—
13
28
—
12
27
—
11
26 25 24 23 22
Data (DBR); Mask (DBMR)
21
— — — — — —
10 9 8 7 6
Data (DBR); Mask (DBMR)
5
20
—
4
19
—
3
18
—
2
17
—
1
16
—
0
— — — — — — — — — — — —
0x0E (DBR), 0x0F (DBMR)
Figure 30-8. Data Breakpoint/Mask Registers (DBR/DBMR)
—
Name
Data
— —
Table 30-10. DBR Field Descriptions
Description
Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a breakpoint trigger.
Bits
31–0
Name
Mask
Table 30-11. DBMR Field Descriptions
Description
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows the corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a DBMR bit causes that bit to be ignored.
The DBR supports both aligned and misaligned references.
shows relationships between processor address, access size, and location within the 32-bit data bus.
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Memory Map/Register Definition
Table 30-12. Access Size and Operand Data Location
A[1:0]
0x
1x xx
00
01
10
11
Access Size
Byte
Byte
Byte
Byte
Word
Word
Longword
Operand Location
D[31:24]
D[23:16]
D[15:8]
D[7:0]
D[31:16]
D[15:0]
D[31:0]
30.4.6 Program Counter Breakpoint/Mask Registers (PBR, PBMR)
The PBR defines an instruction address for use as part of the trigger. This register’s contents are compared with the processor’s program counter register when TDR is configured appropriately.
PBR bits are masked by setting corresponding PBMR bits. Results are compared with the processor’s program counter register, as defined in TDR.
shows the PC breakpoint register.
The PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands using values shown in
Section 30.5.3.3, “Command Set Descriptions
.”
31
R
W
Reset —
15
R
W
Reset —
DRc[4:0]
Bits
31–0
30
—
14
29
—
13
28
—
12
27
—
11
26
—
10
25 24 23 22
—
Program Counter
— — —
9 8 7 6
21
—
5
20
—
4
19
—
3
18
—
2
17
—
1
16
—
0
— — — — — —
Program Counter
— — — — — —
0x08
Figure 30-9. Program Counter Breakpoint Register (PBR)
— — —
Table 30-13. PBR Field Descriptions
Name Description
Address PC breakpoint address. The 32-bit address to be compared with the PC as a breakpoint trigger.
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shows PBMR. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG instruction and via the BDM port using the wdmreg command.
31
R
W
Reset —
30
—
29
—
28
—
27
—
26
—
25
—
24 23
—
Mask
—
22
—
21
—
20
—
19
—
18
—
17
—
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
R
W
Reset —
DRc[4:0]
— — — — — — —
Mask
—
0x09
— — — — —
Figure 30-10. Program Counter Breakpoint Mask Register (PBMR)
—
Bits
31–0
Name
Mask
Table 30-14. PBMR Field Descriptions
Description
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
16
—
0
—
30.4.7 Trigger Definition Register (TDR)
The TDR, shown in Table 30-11 , configures the operation of the hardware breakpoint logic that
corresponds with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers within the debug module. The TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured as a one- or two-level trigger. TDR[31–16] define the second-level trigger and bits 15–0 define the first-level trigger.
NOTE
The debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR (by clearing TDR[29,13])before defining triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the
WDMREG
command.
30-14
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Memory Map/Register Definition
31 30
R
W
Reset 0
TRC
0
14 15
R
W 0
Reset 0
DRc[4:0]
Bits
31–30
15–14
29/13
28–22/
12–6
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
29 28 27 26 25 24 23 22 21 20 19 18 17 16
EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI
0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
EBL EDLW EDWL EDWU EDLL EDLM EDUM EDUU DI EAI EAR EAL EPC PCI
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x07
Figure 30-11. Trigger Definition Register (TDR)
Table 30-15. TDR Field Descriptions
Name
TRC
—
EBL
EDx
DI
Description
Trigger response control. Determines how the processor responds to a completed trigger condition. The trigger response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
Reserved, should be cleared.
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a breakpoint trigger. Clearing it disables all breakpoints at that level.
Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints.
EDLW Data longword. Entire processor’s local data bus.
EDWL Lower data word.
EDW
U
Upper data word.
EDLL Lower lower data byte. Low-order byte of the low-order word.
EDLM Lower middle data byte. High-order byte of the low-order word.
EDUM Upper middle data byte. Low-order byte of the high-order word.
EDUU Upper upper data byte. High-order byte of the high-order word.
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value other than the DBR contents.
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MCF5271 Reference Manual, Rev. 2
30-15
Debug Support
Bits
20–18/4–2
20/4
19/3
18/2
17/1
16/0
Name
EAx
EPC
PCI
Table 30-15. TDR Field Descriptions (Continued)
Description
Enable address bits. Setting an EA bit enables the corresponding address breakpoint.
Clearing all three bits disables the breakpoint.
EAI Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR and ABHR.
EAR
EAL
Enable address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR.
Enable address breakpoint low. The breakpoint is based on the address in the
ABLR.
Enable PC breakpoint. If set, this bit enables the PC breakpoint.
Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR and PBMR to enable a trigger. If cleared, the PC breakpoint is defined within the region defined by PBR and PBMR.
30.5 Background Debug Mode (BDM)
The ColdFire Family implements a low-level system debugger in the microprocessor hardware.
Communication with the development system is handled through a dedicated, high-speed serial command interface. The ColdFire architecture implements the BDM controller in a dedicated hardware module. Although some BDM operations, such as CPU register accesses, require the
CPU to be halted, other BDM commands, such as memory accesses, can be executed while the processor is running.
30.5.1 CPU Halt
Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority:
1. A catastrophic fault-on-fault condition automatically halts the processor.
2. A hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT. This type of halt is always first made pending in the processor.
Next, the processor samples for pending halt and interrupt conditions once per instruction.
When a pending condition is asserted, the processor halts execution at the next sample point. See
Section 30.6.1, “Theory of Operation
.”
3. The execution of a HALT instruction immediately suspends execution. Attempting to execute HALT in user mode while CSR[UHE] = 0 generates a privilege violation exception. If CSR[UHE] = 1, HALT can be executed in user mode. After HALT executes, the processor can be restarted by serial shifting a GO command into the debug module.
Execution continues at the instruction after HALT.
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30-16 Freescale Semiconductor
Background Debug Mode (BDM)
4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt condition is postponed until the processor core samples for halts/interrupts. The processor samples for these conditions once during the execution of each instruction. If there is a pending halt condition at the sample time, the processor suspends execution and enters the halted state.
The assertion of BKPT should be considered in the following two special cases:
• After the system reset signal is negated, the processor waits for 16 processor clock cycles before beginning reset exception processing. If the BKPT input is asserted within eight cycles after RESET is negated, the processor enters the halt state, signaling halt status (0xF) on the PST outputs. While the processor is in this state, all resources accessible through the debug module can be referenced. This is the only chance to force the processor into emulation mode through CSR[EMU].
After system initialization, the processor’s response to the
GO
command depends on the set of BDM commands performed while it is halted for a breakpoint. Specifically, if the PC register was loaded, the
GO
command causes the processor to exit halted state and pass control to the instruction address in the PC, bypassing normal reset exception processing.
If the PC was not loaded, the
GO
command causes the processor to exit halted state and continue reset exception processing.
• The ColdFire architecture also handles a special case of BKPT being asserted while the processor is stopped by execution of the STOP instruction. For this case, the processor exits the stopped mode and enters the halted state, at which point, all BDM commands may be exercised. When restarted, the processor continues by executing the next sequential instruction, that is, the instruction following the STOP opcode.
The CSR[27–24] bits indicate the halt source, showing the highest priority source for multiple halt conditions.
30.5.2 BDM Serial Interface
When the CPU is halted and PST reflects the halt status, the development system can send unrestricted commands to the debug module. The debug module implements a synchronous protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a
delay relative to the rising edge of the processor clock. See Table 30-1 . The development system
serves as the serial communication channel master and must generate DSCLK.
The serial channel operates at a frequency from DC to 1/5 of the PSTCLK frequency. The channel uses full-duplex mode, where data is sent and received simultaneously by both master and slave devices. The transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. As shown in
Figure 30-12 , all state transitions are enabled on a rising edge of PSTCLK
when DSCLK is high; that is, DSI is sampled and DSO is driven.
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Freescale Semiconductor 30-17
Debug Support
C1 C2 C3 C4
PSTCLK
DSCLK
DSI Current Next
BDM State
Machine
DSO
Current State Next State
Past Current
Figure 30-12. BDM Serial Interface Timing
DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor clock as well as the DSI. DSO is delayed from the
DSCLK-enabled CLK rising edge (registered after a BDM state machine state change). All events in the debug module’s serial state machine are based on the processor clock rising edge. DSCLK must also be sampled low (on a positive edge of CLK) between each bit exchange. The msb is transferred first. Because DSO changes state based on an internally-recognized rising edge of
DSCLK, DSO cannot be used to indicate the start of a serial transfer. The development system must count clock cycles in a given transfer. C1–C4 are described as follows:
• C1—First synchronization cycle for DSI (DSCLK is high).
• C2—Second synchronization cycle for DSI (DSCLK is high).
• C3—BDM state machine changes state depending upon DSI and whether the entire input data transfer has been transmitted.
• C4—DSO changes to next value.
NOTE
A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.
30.5.2.1 Receive Packet Format
The basic receive packet,
Figure 30-13 , consists of 16 data bits and 1 status bit
.
16
S
15 14 13 12 11 10 9 8 7
Data Field [15:0]
6 5
Figure 30-13. Receive BDM Packet
4 3 2 1 0
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30-18 Freescale Semiconductor
Bits
16
15–0
Background Debug Mode (BDM)
Name
S
Table 30-16. Receive BDM Packet Field Description
Description
Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.
S
0
0
1
1
1
Data xxxx
FFFF
0000
0001
FFFF
Message
Valid data transfer
Status OK
Not ready with response; come again
Error–Terminated bus cycle; data invalid
Illegal Command
D Data. Contains the message to be sent from the debug module to the development system. The response message is always a single word, with the data field encoded as shown above.
30.5.2.2 Transmit Packet Format
The basic transmit packet, Figure 30-14 , consists of 16 data bits and 1 reserved bit.
16
—
15 14 13 12 11 10 9 8 7 6 5
D
Figure 30-14. Transmit BDM Packet
4 3 2 1
Bits
16
15–0
0
Table 30-17. Transmit BDM Packet Field Description
Name
—
D
Description
Reserved, should be cleared.
Data bits 15–0. Contains the data to be sent from the development system to the debug module.
30.5.3 BDM Command Set
summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior.
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MCF5271 Reference Manual, Rev. 2
30-19
Debug Support
Table 30-18. BDM Command Summary
Command Mnemonic Description
CPU
State
1
Section
Command
(Hex)
Read A/D register
Write A/D register
Read memory location
Write memory location
Dump memory block
RAREG
RDREG
WAREG
/
WDREG
READ
WRITE
/ Read the selected address or data register and return the results through the serial interface.
Write the data operand to the specified address or data register.
Read the data at the memory location specified by the longword address.
Write the operand data to the memory location specified by the longword address.
Halted
Halted
0x218 {A/D,
Reg[2:0]}
0x208 {A/D,
Reg[2:0]}
Steal
0x1900—byte
0x1940—word
0x1980—lword
2
Steal
0x1800—byte
0x1840—word
0x1880—lword
2
Steal
0x1D00—byte
0x1D40—word
0x1D80—lword
2
Fill memory block
DUMP
FILL
Used with READ to dump large blocks of memory.
An initial
READ
is executed to set up the starting address of the block and to retrieve the first result. A
DUMP
command retrieves subsequent operands.
Used with WRITE to fill large blocks of memory. An initial
WRITE
is executed to set up the starting address of the block and to supply the first operand. A
FILL
command writes subsequent operands.
Steal
0x1C00—byte
0x1C40—word
0x1C80—lword
2
Resume execution
GO
No operation
NOP
The pipeline is flushed and refilled before resuming instruction execution at the current PC.
Perform no operation; may be used as a null command.
Read the system control register.
Halted
Parallel
0x0000
Halted
0x0C00
0x2980 Read control register
RCREG
Write control register
WCREG
Write the operand data to the system control register.
Halted
0x2880
Read debug module register
RDMREG Read the debug module register.
Parallel
0x2D {0x4
DRc[4:0]}
3
Write debug module register
WDMREG Write the operand data to the debug module register.
Parallel
2
3
1 General command effect and/or requirements on CPU operation:
- Halted. The CPU must be halted to perform this command.
- Steal. Command generates bus cycles that can be interleaved with bus accesses.
- Parallel. Command is executed in parallel with CPU activity. lword = longword
0x4 is a three-bit field.
0x2C {0x4
DRc[4:0]}
3
Unassigned command opcodes are reserved by Freescale. All unused command formats within any revision level perform a
NOP
and return the illegal command response.
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30-20 Freescale Semiconductor
Background Debug Mode (BDM)
30.5.3.1 ColdFire BDM Command Format
All ColdFire Family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words, as shown in
15
Bits
15–10
9
8
7–6
14 13 12
Operation
11 10 9
0
8
R/W
7 6
Op Size
5
0
Extension Word(s)
Figure 30-15. BDM Command Format
4
0
Table 30-19. BDM Field Descriptions
3
A/D
2 1
Register
0
Name Description
Operation Specifies the command. These values are listed in
— Reserved, should be cleared.
R/W Direction of operand transfer.
0 Data is written to the CPU or to memory from the development system.
1 The transfer is from the CPU to the development system.
Op Size Operand data size for sized operations. Addresses are expressed as 32-bit absolute values. Note that a command performing a byte-sized memory read leaves the upper 8 bits of the response data undefined. Referenced data is returned in the lower 8 bits of the response.
00
01
10
11
Operand Size
Byte
Word
Longword
Reserved
Bit Values
8 bits
16 bits
32 bits
—
5–4
3
2–0
—
A/D
Reserved, should be cleared.
Address/data. Determines whether the register field specifies a data or address register.
0 Indicates a data register.
1 Indicates an address register.
Register Contains the register number in commands that operate on processor registers.
30.5.3.1.1 Extension Words as Required
Some commands require extension words for addresses and/or immediate data. Addresses require two extension words because only absolute long addressing is permitted. Longword accesses are forcibly longword-aligned and word accesses are forcibly word-aligned. Immediate data can be 1 or 2 words long. Byte and word data each requires a single extension word and longword data requires two extension words.
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Freescale Semiconductor 30-21
Debug Support
Operands and addresses are transferred most-significant word first. In the following descriptions of the BDM command set, the optional set of extension words is defined as address, data, or operand data.
30.5.3.2 Command Sequence Diagrams
The command sequence diagram in Figure 30-16
shows serial bus traffic for commands. Each bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands. Command and result transactions overlap to minimize latency.
Commands transmitted to the debug module
Command code transmitted during this cycle
High-order 16 bits of memory address
Low-order 16 bits of memory address
Non-serial-related activity Sequence taken if operation has not completed
READ (LONG)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
READ
MEMORY
LOCATION
XXX
’NOT READY’
Next
Command
Code
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
XXX
MS RESULT
NEXT CMD
LS RESULT
Data used from this transfer
XXX
BERR
NEXT CMD
’NOT READY’
Sequence taken if illegal command is received by debug module
Results from previous command
Sequence taken if bus error occurs on memory access
Responses from the debug module
High- and low-order 16 bits of result
Figure 30-16. Command Sequence Diagram
The sequence is as follows:
• In cycle 1, the development system command is issued (
READ
in this example). The debug module responds with either the low-order results of the previous command or a command complete status of the previous command, if no results are required.
• In cycle 2, the development system supplies the high-order 16 address bits. The debug module returns a not-ready response unless the received command is decoded as unimplemented, which is indicated by the illegal command encoding. If this occurs, the development system should retransmit the command.
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30-22 Freescale Semiconductor
Background Debug Mode (BDM)
NOTE
A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.
• In cycle 3, the development system supplies the low-order 16 address bits. The debug module always returns a not-ready response.
• At the completion of cycle 3, the debug module initiates a memory read operation. Any serial transfers that begin during a memory access return a not-ready response.
• Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is sent to the debug module during the final transfer. If a memory or register access is terminated with a bus error, the error status (S = 1, DATA = 0x0001) is returned instead of result data.
30.5.3.3 Command Set Descriptions
The following sections describe the commands summarized in Table 30-18 .
NOTE
The BDM status bit (S) is 0 for normally completed commands; S = 1 for illegal commands, not-ready responses, and transfers with bus-errors.
Section 30.5.2, “BDM Serial Interface ,” describes the
receive packet format.
Freescale reserves unassigned command opcodes for future expansion. Unused command formats in any revision level perform a NOP and return an illegal command response.
30.5.3.3.1 Read A/D Register ( RAREG / RDREG )
Read the selected address or data register and return the 32-bit result. A bus error response is returned if the CPU core is not halted.
Command/Result Formats:
Command
Result
15 14
0x2
13 12 11 10
0x1
9 8 7 6
0x8
5 4
D[31:16]
D[15:0]
Figure 30-17. RAREG / RDREG Command Format
3
A/D
Command Sequence:
2 1
Register
0
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Freescale Semiconductor 30-23
Debug Support
RAREG/RDREG
???
XXX
MS RESULT
NEXT CMD
LS RESULT
Operand Data:
Result Data:
XXX
BERR
NEXT CMD
’NOT READY’
Figure 30-18. RAREG
/
RDREG Command Sequence
None
The contents of the selected register are returned as a longword value, most-significant word first.
30.5.3.3.2 Write A/D Register (
WAREG
/
WDREG
)
The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted.
Command Format:
15 14
0x2
13 12 11 10
0x0
9 8 7 6
0x8
5 4 3
A/D
D[31:16]
D[15:0]
Figure 30-19. WAREG / WDREG Command Format
2 1
Register
0
Command Sequence
Operand Data
Result Data
WAREG/WDREG
???
MS DATA
’NOT READY’
LS DATA
’NOT READY’
NEXT CMD
’CMD COMPLETE’
XXX
BERR
NEXT CMD
’NOT READY’
Figure 30-20. WAREG / WDREG Command Sequence
Longword data is written into the specified address or data register. The data is supplied most-significant word first.
Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete.
30-24
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Freescale Semiconductor
Background Debug Mode (BDM)
30.5.3.3.3 Read Memory Location (
READ
)
Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.
Command/Result Formats:
Byte
Command
Result
Word Command
Result
Longword Command
Result
15 14
0x1
13 12 11 10
0x9
9 8 7 6
0x0
5 4
X X X X X X X
A[31:16]
A[15:0]
X
0x1 0x9 0x4
A[31:16]
A[15:0]
D[15:0]
0x1 0x9 0x8
A[31:16]
A[15:0]
D[31:16]
D[15:0]
Figure 30-21. READ Command/Result Formats
D[7:0]
3
Command Sequence:
2
0x0
1
0x0
0x0
0
READ (B/W)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
READ
MEMORY
LOCATION
XXX
’NOT READY’
NEXT CMD
RESULT
XXX
BERR
NEXT CMD
’NOT READY’
READ (LONG)
???
Freescale Semiconductor
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
READ
MEMORY
LOCATION
XXX
’NOT READY’
XXX
MS RESULT
XXX
BERR
Figure 30-22. READ Command Sequence
MCF5271 Reference Manual, Rev. 2
NEXT CMD
LS RESULT
NEXT CMD
’NOT READY’
30-25
Debug Support
Operand Data
Result Data
The only operand is the longword address of the requested location.
Word results return 16 bits of data; longword results return 32. Bytes are returned in the LSB of a word result; the upper byte is undefined. 0x0001
(S = 1) is returned if a bus error occurs.
30.5.3.3.4 Write Memory Location ( WRITE )
Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.
Command Formats:
2
0x0
1 0
Byte
Word
Longword
15
X
14
0x1
13 12 11 10
0x8
9 8 7 6
0x0
5 4
X X X X X X
A[31:16]
A[15:0]
X
0x1 0x8 0x4
A[31:16]
A[15:0]
D[15:0]
0x1 0x8 0x8
A[31:16]
A[15:0]
D[31:16]
D[15:0]
Figure 30-23. WRITE Command Format
D[7:0]
3
0x0
0x0
30-26
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Freescale Semiconductor
Background Debug Mode (BDM)
Command Sequence:
WRITE (B/W)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
DATA
’NOT READY’
WRITE
MEMORY
LOCATION
XXX
’NOT READY’
NEXT CMD
’CMD COMPLETE’
XXX
BERR
NEXT CMD
’NOT READY’
WRITE (LONG)
???
MS ADDR
’NOT READY’
LS ADDR
’NOT READY’
MS DATA
’NOT READY’
LS DATA
’NOT READY’
WRITE
MEMORY
LOCATION
XXX
’NOT READY’
NEXT CMD
’CMD COMPLETE’
Operand Data
Result Data
XXX
BERR
NEXT CMD
’NOT READY’
Figure 30-24. WRITE Command Sequence
This two-operand instruction requires a longword absolute address that specifies a location to which the data operand is to be written. Byte data is sent as a 16-bit word, justified in the LSB; 16- and 32-bit operands are sent as 16 and 32 bits, respectively
Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete. A value of 0x0001 (with S set) is returned if a bus error occurs.
30.5.3.3.5 Dump Memory Block ( DUMP )
DUMP is used with the READ command to access large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. If an initial READ is not executed before the first DUMP , an illegal command response is returned. The DUMP command retrieves subsequent operands. The initial address is incremented by the operand size
(1, 2, or 4) and saved in a temporary register. Subsequent DUMP commands use this address,
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Freescale Semiconductor 30-27
Debug Support perform the memory read, increment it by the current operand size, and store the updated address in the temporary register.
NOTE
DUMP does not check for a valid address; it is a valid command only when preceded by NOP , READ , or another DUMP command. Otherwise, an illegal command response is returned. NOP can be used for intercommand padding without corrupting the address pointer.
The size field is examined each time a
DUMP
command is processed, allowing the operand size to be dynamically altered.
Command/Result Formats:
15 12 11 8 7 4
Byte
Word
Command
Result
Command
Result
Longword Command
Result
X X
0x1
0x1
0x1
X X X X
0xD
0xD
0xD
X X
D[15:0]
0x0
0x4
0x8
D[31:16]
D[15:0]
Figure 30-25. DUMP Command/Result Formats
D[7:0]
3
0x0
0x0
0x0
0
30-28
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Freescale Semiconductor
Background Debug Mode (BDM)
Command Sequence:
DUMP (B/W)
???
XXX
’ILLEGAL’
READ
MEMORY
LOCATION
NEXT CMD
’NOT READY’
XXX
’NOT READY’
NEXT CMD
RESULT
XXX
BERR
NEXT CMD
’NOT READY’
DUMP (LONG)
???
READ
MEMORY
LOCATION
XXX
’NOT READY’
NEXT CMD
MS RESULT
NEXT CMD
LS RESULT
Operand Data:
Result Data:
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
XXX
BERR
Figure 30-26. DUMP Command Sequence
NEXT CMD
’NOT READY’
None
Requested data is returned as either a word or longword. Byte data is returned in the least-significant byte of a word result. Word results return 16 bits of significant data; longword results return 32 bits. A value of 0x0001
(with S set) is returned if a bus error occurs.
30.5.3.3.6 Fill Memory Block (
FILL
)
A FILL command is used with the WRITE command to access large blocks of memory. An initial
WRITE
is executed to set up the starting address of the block and to supply the first operand. The
FILL command writes subsequent operands. The initial address is incremented by the operand size
(1, 2, or 4) and saved in a temporary register after the memory write. Subsequent
FILL
commands use this address, perform the write, increment it by the current operand size, and store the updated address in the temporary register.
If an initial WRITE is not executed preceding the first FILL command, the illegal command response is returned.
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Debug Support
NOTE
The
FILL
command does not check for a valid address—
FILL
is a valid command only when preceded by another FILL , a NOP , or a WRITE command. Otherwise, an illegal command response is returned. The
NOP command can be used for intercommand padding without corrupting the address pointer.
The size field is examined each time a FILL command is processed, allowing the operand size to be altered dynamically.
Command Formats:
Byte
Word
Longword
15
X
14
0x1
13
X X
0x1
12
X
11
X
10
0xC
9
X
0xC
X
8
X
7 6
0x0
5
0x4
D[15:0]
0x1 0xC 0x8
D[31:16]
D[15:0]
Figure 30-27. FILL Command Format
4
D[7:0]
3 2
0x0
1
0x0
0x0
0
Command Sequence:
FILL (LONG)
???
MS DATA
’NOT READY’
LS DATA
’NOT READY’
WRITE
MEMORY
LOCATION
XXX
’NOT READY’
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
NEXT CMD
’CMD COMPLETE’
XXX
BERR
NEXT CMD
’NOT READY’
FILL (B/W)
???
DATA
’NOT READY’
WRITE
MEMORY
LOCATION
XXX
’NOT READY’
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
NEXT CMD
’CMD COMPLETE’
XXX
BERR
Figure 30-28. FILL Command Sequence
NEXT CMD
’NOT READY’
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30-30 Freescale Semiconductor
Operand Data:
Result Data:
Background Debug Mode (BDM)
A single operand is data to be written to the memory location. Byte data is sent as a 16-bit word, justified in the least-significant byte; 16- and 32-bit operands are sent as 16 and 32 bits, respectively.
Command complete status (0xFFFF) is returned when the register write is complete. A value of 0x0001 (with S set) is returned if a bus error occurs.
30.5.3.3.7 Resume Execution (
GO
)
The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes. If a GO command is issued and the CPU is not halted, the command is ignored.
15 14
0x0
13 12 11 10 9 8 7 6 5
0xC 0x0
Figure 30-29. GO Command Format
4 3 2
0x0
1 0
Command Sequence:
GO
???
NEXT CMD
’CMD COMPLETE’
Operand Data:
Result Data:
Figure 30-30.
GO
Command Sequence
None
The command-complete response (0xFFFF) is returned during the next shift operation.
30.5.3.3.8 No Operation (
NOP
)
NOP
performs no operation and may be used as a null command where required.
Command Formats:
15 14
0x0
13 12 11 10 9 8 7 6 5
0x0 0x0
Figure 30-31. NOP Command Format
4 3 2
0x0
1
Command Sequence:
0
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Freescale Semiconductor 30-31
Debug Support
NOP
???
NEXT CMD
’CMD COMPLETE’
Operand Data:
Result Data:
Figure 30-32.
NOP
Command Sequence
None
The command-complete response, 0xFFFF (with S cleared), is returned during the next shift operation.
30.5.3.3.9 Read Control Register (
RCREG
)
Reads the selected control register and returns the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same as that used by the
MOVEC instruction.
Command/Result Formats:
0
Command
Result
15 14
0x2
13
0x0
0x0
12 11 10
0x9
9
0x0
8 7 6
0x8
0x0
Rc
5 4
D[31:16]
D[15:0]
Figure 30-33. RCREG Command/Result Formats
3
Rc encoding:
Rc
0x002
0x004
0x005
0x800
0x801
0x804
0x805
0x806
0x807
Table 30-20. Control Register Map
Register Definition
Cache Control Register (CACR)
Access Control Register (ACR0)
Access Control Register (ACR1)
Other Stack Pointer (OTHER_A7)
Vector Base Register (VBR)
MAC Status Register (MACSR)
MAC Mask Register (MASK)
MAC Accumulator 0 (ACC0)
MAC Accumulator 0,1 Extension Bytes (ACCEXT01)
2
0x0
0x0
1
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30-32 Freescale Semiconductor
Background Debug Mode (BDM)
Rc
0x808
0x809
0x80A
0x80B
0x80E
0x80F
0xC04
Table 30-20. Control Register Map
Register Definition
MAC Accumulator 2,3 Extension Bytes (ACCEXT23)
MAC Accumulator 1 (ACC1)
MAC Accumulator 2 (ACC2)
MAC Accumulator 3 (ACC3)
Status Register (SR)
Program Register (PC)
RAM Base Address Register 0 (RAMBAR0)
Command Sequence:
RCREG
???
MS ADDR
’NOT READY’
MS ADDR
’NOT READY’
READ
CONTROL
REGISTER
XXX
’NOT READY’
NEXT CMD
MS RESULT
NEXT CMD
LS RESULT
XXX
BERR
Figure 30-34. RCREG Command Sequence
NEXT CMD
’NOT READY’
Operand Data:
Result Data:
The only operand is the 32-bit Rc control register select field.
Control register contents are returned as a longword, most-significant word first. The implemented portion of registers smaller than 32 bits is guaranteed correct; other bits are undefined.
BDM Accesses of the Stack Pointer Registers (A7: SSP, USP)
The V2 core of the MCF5271supports two unique stack pointer (A7) registers: the supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two programmable-visible 32-bit registers does not uniquely identify one as the SSP and the other as the USP. Rather, the hardware uses one 32-bit register as the currently-active A7 and the other register is named simply the “other_A7”. Thus, the contents of the two hardware registers is a function of the operating mode of the processor: if SR[S] = 1
then
else
A7 = Supervisor Stack Pointer other_A7 = User Stack Pointer
A7 = User Stack Pointer other_A7 = Supervisor Stack Pointer
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Debug Support
The BDM programming model supports reads and writes to the A7 and other_A7 registers directly. It is the responsibility of the external development system to determine the mapping of the two hardware registers (A7, other_A7) to the two program-visible definitions (supervisor and user stack pointers), based on the Supervisor bit of the status register.
BDM Accesses of the EMAC Registers
The presence of rounding logic in the output datapath of the EMAC requires that special care be taken during any BDM-initiated reads and writes of its programming model. In particular, it is necessary that any result rounding modes be disabled during the read/write process so the exact bit-wise contents of the EMAC registers are accessed.
As an example, any BDM read of an accumulator register (ACCn) must be preceded by two commands accessing the MAC status register. Specifically, the following BDM sequence is required:
BdmReadACCn (
rcreg macsr; // read macsr contents & save
wcreg #0,macsr; // disable all rounding modes
rcreg accn; // read the desired accumulator
wcreg #saved_data,macsr;// restore the original macsr
)
Likewise, the following BDM sequence is needed to write an accumulator register:
BdmWriteACCn (
rcreg macsr; // read macsr contents & save
wcreg #0,macsr; // disable all rounding modes
wcreg #data,accn; // write the desired accumulator
wcreg #saved_data,macsr;// restore the original macsr
)
Additionally, it is required that writes to the accumulator extension registers be performed after the corresponding accumulators are updated. This is needed since a write to any accumulator alters the contents of the corresponding extension register.
For more information on saving and restoring the complete EMAC programming model, see
Section 4.4.1.1.2, “Saving and Restoring the EMAC Programming Model
.”
30.5.3.3.10Write Control Register (
WCREG
)
The operand (longword) data is written to the specified control register. The write alters all 32 register bits.
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Background Debug Mode (BDM)
Command/Result Formats:
Command
Result
15
Command Sequence:
14
0x2
13
0x0
0x0
12 11 10
0x8
9
0x0
8 7 6
0x8
0x0
R c
5 4
D[31:16]
D[15:0]
Figure 30-35. WCREG Command/Result Formats
3 2
0x0
0x0
1 0
WCREG
???
MS ADDR
’NOT READY’
MS ADDR
’NOT READY’
MS DATA
’NOT READY’
LS DATA
’NOT READY’
WRITE
CONTROL
REGISTER
XXX
’NOT READY’
NEXT CMD
’CMD COMPLETE’
Operand Data:
Result Data:
NEXT CMD
’NOT READY’
Figure 30-36. WCREG Command Sequence
This instruction requires two longword operands. The first selects the register to which the operand data is to be written; the second contains the data.
Successful write operations return 0xFFFF. Bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001.
30.5.3.3.11 Read Debug Module Register ( RDMREG )
Read the selected debug module register and return the 32-bit result. The only valid register selection for the RDMREG command is CSR (DRc = 0x00). Note that this read of the CSR clears
CSR[FOF, TRG, HALT, BKPT]; as well as the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled.
Command/Result Formats:
MCF5271 Reference Manual, Rev. 2
XXX
BERR
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Debug Support
Command
Result
15 14
0x2
13 12 11 10
0xD
9 8 7 6
100
5 4
D[31:16]
D[15:0]
Figure 30-37. RDMREG Command/Result Formats
3 2
DR c
1
shows the definition of DRc encoding.
Table 30-21. Definition of DRc Encoding—Read
DRc[4:0]
0x00
0x01–0x1F
Debug Register Definition
Configuration/Status
Reserved
Mnemonic
CSR
—
Initial State
0x0
—
Command Sequence:
0
Page
—
RDMREG
???
XXX
MS RESULT
NEXT CMD
LS RESULT
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
Operand Data:
Result Data:
Figure 30-38. RDMREG Command Sequence
None
The contents of the selected debug register are returned as a longword value.
The data is returned most-significant word first.
30.5.3.3.12Write Debug Module Register (
WDMREG
)
The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction.
Command Format:
15 14
0x2
13 0 12 11 10
0xC
9 8 7 6
100
5 4
D[31:16]
D[15:0]
Figure 30-39.
WDMREG
BDM Command Format
3 2
DRc
1
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30-36 Freescale Semiconductor
Table 30-4 shows the definition of the DRc write encoding.
Command Sequence:
WDMREG
???
MS DATA
’NOT READY’
LS DATA
’NOT READY’
NEXT CMD
’CMD COMPLETE’
Real-Time Debug Support
Operand Data:
Result Data:
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
Figure 30-40.
WDMREG
Command Sequence
Longword data is written into the specified debug register. The data is supplied most-significant word first.
Command complete status (0xFFFF) is returned when register write is complete.
30.6 Real-Time Debug Support
The ColdFire Family provides support debugging real-time applications. For these types of embedded systems, the processor must continue to operate during debug. The foundation of this area of debug support is that while the processor cannot be halted to allow debugging, the system can generally tolerate small intrusions into the real-time operation.
The debug module provides three types of breakpoints—PC with mask, operand address range, and data with mask. These breakpoints can be configured into one- or two-level triggers with the exact trigger response also programmable. The debug module programming model can be written from either the external development system using the debug serial interface or from the processor’s supervisor programming model using the WDEBUG instruction. Only CSR is readable using the external development system.
30.6.1 Theory of Operation
Breakpoint hardware can be configured to respond to triggers in several ways. The response
desired is programmed into TDR. As shown in Table 30-22
, when a breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status, operands, or branch addresses.
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Debug Support
Table 30-22. DDATA[3:0]/CSR[BSTAT] Breakpoint Response
DDATA[3:0]
1
CSR[BSTAT]
1
Breakpoint Status
0000
0010
0100
0000
0001
0010
No breakpoints enabled
Waiting for level-1 breakpoint
Level-1 breakpoint triggered
1010
1100
0101
0110
Waiting for level-2 breakpoint
Level-2 breakpoint triggered
1
Encodings not shown are reserved for future use.
The breakpoint status is also posted in the CSR. Note that CSR[BSTAT] is cleared by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. Status is also cleared by writing to TDR.
BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates, a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner—exception recognition and processing are initiated before the excepting instruction is executed. All other breakpoint events are recognized on the processor’s local bus, but are made pending to the processor and sampled like other interrupt conditions. As a result, these interrupts are imprecise.
In systems that tolerate the processor being halted, a BDM-entry can be used. With
TDR[TRC] = 01, a breakpoint trigger causes the core to halt (PST = 0xF).
If the processor core cannot be halted, the debug interrupt can be used. With this configuration,
TDR[TRC] = 10, the breakpoint trigger becomes a debug interrupt to the processor, which is treated higher than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC breakpoint to occur before the targeted instruction executes. This is possible because the PC breakpoint is enabled when interrupt sampling occurs. For address and data breakpoints, reporting is considered imprecise because several instructions may execute after the triggering address or data is detected.
As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for multiple cycles. The core enters emulator mode when exception processing begins. After the standard 8-byte exception stack is created, the processor fetches a unique exception vector, 12, from the vector table.
Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. All interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use supervisor instructions to save the necessary context such as the state of all program-visible registers into a reserved memory area.
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Real-Time Debug Support
When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator mode. After the debug interrupt handler completes execution, the external development system can use BDM commands to read the reserved memory locations.
If a hardware breakpoint such as a PC trigger is left unmodified by the debug interrupt service routine, another debug interrupt is generated after the completion of the RTE instruction.
30.6.1.1 Emulator Mode
Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be entered in three different ways:
• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if
RESET is negated and the processor begins reset exception processing. It can be set while
the processor is halted before reset exception processing begins. See Section 30.5.1, “CPU
• A debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins.
• Setting CSR[TRC] forces the processor into emulation mode when trace exception processing begins.
While operating in emulation mode, the processor exhibits the following properties:
• All interrupts are ignored, including level-7 interrupts.
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory accesses are forced into a specially mapped address space signaled by TT = 0x2, TM = 0x5 or 0x6. This includes stack frame writes and the vector fetch for the exception that forced entry into this mode.
The RTE instruction exits emulation mode. The processor status output port provides a unique encoding for emulator mode entry (0xD) and exit (0x7).
30.6.2 Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM commands.
BDM commands may be executed while the processor is running, except those following operations that access processor/memory registers:
• Read/write address and data registers
• Read/write control registers
For BDM commands that access memory, the debug module requests the processor’s local bus.
The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access. After the debug module bus cycle, the processor reclaims the bus.
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Debug Support
Breakpoint registers must be carefully configured in a development system if the processor is executing. The debug module contains no hardware interlocks, so TDR should be disabled while breakpoint registers are loaded, after which TDR can be written to define the exact trigger. This prevents spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU is writing the debug’s registers (DSCLK must be inactive).
Note that the debug module requires the use of the internal bus to perform BDM commands. In
Revision A, if the processor is executing a tight loop that is contained within a single aligned longword, the processor may never grant the internal bus to the debug module, for example: align4 label1: nop bra.b label1 or align4 label2: bra.w label2
The processor grants the internal bus if these loops are forced across two longwords.
30.7 Processor Status, DDATA Definition
This section specifies the ColdFire processor and debug module’s generation of the processor status (PST) and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA output for an instruction is defined as follows:
PST = 0x1, {PST = [0x89B], DDATA= operand} where the {...} definition is optional operand information defined by the setting of the CSR.
The CSR provides capabilities to display operands based on reference type (read, write, or both).
A PST value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to follow on the
DDATA output {1, 2, or 4 bytes}. Additionally, for certain change-of-flow branch instructions,
CSR[BTB] provides the capability to display the target instruction address on the DDATA output
{2, 3, or 4 bytes} using a PST value of {0x9, 0xA, or 0xB}.
30.7.1 User Instruction Set
shows the PST/DDATA specification for user-mode instructions. Rn represents any
{Dn, An} register. In this definition, the ‘y’ suffix generally denotes the source and ‘x’ denotes the destination operand. For a given instruction, the optional operand data is displayed only for those effective addresses referencing memory. The ‘DD’ nomenclature refers to the DDATA outputs.
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Processor Status, DDATA Definition
Instruction clr.l
clr.w
cmp.l
cmpi.l
divs.l
divs.w
divu.l
divu.w
bclr bra.{b,w} bset bset bsr.{b,w} btst btst clr.b
asl.l
asr.l
bitrev.l
byterev.l
bcc.{b,w} bchg bchg bclr add.l
add.l
addi.l
addq.l
addx.l
and.l
and.l
andi.l
Table 30-23. PST/DDATA Specification for User-Mode Instructions
Operand Syntax
<ea>y,Rx
Dy,<ea>x
#imm,Dx
#imm,<ea>x
Dy,Dx
<ea>y,Dx
Dy,<ea>x
#imm,Dx
{Dy,#imm},Dx
{Dy,#imm},Dx
Dx
Dx
#imm,<ea>x
Dy,<ea>x
#imm,<ea>x
Dy,<ea>x
#imm,<ea>x
Dy,<ea>x
#imm,<ea>x
Dy,<ea>x
<ea>x
<ea>x
<ea>x
<ea>y,Rx
#imm,Dx
<ea>y,Dx
<ea>y,Dx
PST/DDATA
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1 if taken, then PST = 0x5, else PST = 0x1
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x5
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x5, {PST = 0xB, DD = destination operand}
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0x8, DD = destination operand}
PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x1, {PST = 0x9, DD = destination operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
<ea>y,Dx PST = 0x1, {PST = 0x9, DD = source operand}
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Debug Support move.w
movem.l
movem.l
moveq muls.l
muls.w
mulu.l
mulu.w
lea link.w
lsl.l
lsr.l
move.b
move.l
move.w
move.w
neg.l
negx.l
nop not.l
or.l
or.l
ori.l
pea
Table 30-23. PST/DDATA Specification for User-Mode Instructions (Continued)
Instruction eor.l
eori.l
ext.l
ext.w
extb.l
ff1.l
jmp jsr
Operand Syntax PST/DDATA
Dy,<ea>x
#imm,Dx
Dx
Dx
Dx
Dx
<ea>x
<ea>x
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x5, {PST = [0x9AB], DD = target address} 1
PST = 0x5, {PST = [0x9AB], DD = target address},
{PST = 0xB , DD = destination operand}
1
<ea>y,Ax
Ay,#imm
{Dy,#imm},Dx
{Dy,#imm},Dx
PST = 0x1
PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x1
PST = 0x1
<ea>y,<ea>x
<ea>y,<ea>x
<ea>y,<ea>x
CCR,Dx
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1, {PST = 0x9, DD = source}, {PST = 0x9, DD = destination}
PST = 0x1
{Dy,#imm},CCR PST = 0x1
#list,<ea>x PST = 0x1, {PST = 0xB, DD = destination},...
2
<ea>y,#list PST = 0x1, {PST = 0xB, DD = source},...
2
#imm,Dx
<ea>y,Dx
<ea>y,Dx
<ea>y,Dx
<ea>y,Dx
Dx
Dx
Dx
<ea>y,Dx
Dy,<ea>x
#imm,Dx
<ea>y
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = destination operand}
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Processor Status, DDATA Definition
Table 30-23. PST/DDATA Specification for User-Mode Instructions (Continued)
Instruction Operand Syntax PST/DDATA pulse rems.l
remu.l
rts scc sub.l
sub.l
subi.l
PST = 0x4
<ea>y,Dx:Dw PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source operand},
PST = 0x5, {PST = [0x9AB], DD = target address}
Dx
<ea>y,Rx
Dy,<ea>x
#imm,Dx
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1 subq.l
subx.l
swap trap
#imm,<ea>x
Dy,Dx
Dx
#imm
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1
PST = 0x1
3 trapf tst.b
tst.l
tst.w
unlk wddata.b
wddata.l
<ea>x
<ea>x
<ea>x
Ax
<ea>y
<ea>y
PST = 0x1
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x4, {PST = 0x8, DD = source operand
PST = 0x4, {PST = 0xB, DD = source operand wddata.w
<ea>y PST = 0x4, {PST = 0x9, DD = source operand
1
2
3
For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi),
(d8,PC,Xi).
For Move Multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the operand address reaches a 0-modulo-16 boundary and there are four or more registers to be transferred. For these line-sized transfers, the operand data is never captured nor displayed, regardless of the CSR value.
The automatic line-sized burst transfers are provided to maximize performance during these sequential memory access operations.
During normal exception processing, the PST output is driven to a 0xC indicating the exception processing state. The exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed.
Exception ProcessingPST = 0xC,{PST = 0xB,DD = destination},// stack frame
{PST = 0xB,DD = destination},// stack frame
{PST = 0xB,DD = source},// vector read
PST = 0x5,{PST = [0x9AB],DD = target}// handler PC
The PST/DDATA specification for the reset exception is shown below:
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor 30-43
Debug Support
Exception ProcessingPST = 0xC,
PST = 0x5,{PST = [0x9AB],DD = target}// handler PC
The initial references at address 0 and 4 are never captured nor displayed since these accesses are treated as instruction fetches.
For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST output is needed for one of the optional marker values or for the taken branch indicator (0x5).
shows the PST/DDATA specification for multiply-accumulate instructions.
Table 30-24. PST/DDATA Specification for MAC Instructions
Instruction move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
mac.l
mac.l
mac.w
mac.w
move.l
move.l
move.l
move.l
msac.l
msac.l
msac.w
msac.w
Operand Syntax
Ry,Rx,Accx
Ry,Rx,Accx
PST = 0x1
PST = 0x1
PST/DDATA
<ea>y,Accx PST = 0x1
Accy,Accx PST = 0x1
<ea>y,MACR PST = 0x1
<ea>y,MASK PST = 0x1
<ea>y,Accext01 PST = 0x1
<ea>y,Accext23 PST = 0x1
Accy,Rx PST = 0x1
MACSR,CCR PST = 0x1
MACSR,Rx PST = 0x1
MASK,Rx PST = 0x1
Accext01,Rx
Accext23,Rx
PST = 0x1
PST = 0x1
Ry,Rx,Accx PST = 0x1
Ry,Rx,<ea>,Rw,Accx PST = 0x1, {PST = 0xB, DD = source operand}
Ry,Rx,Accx PST = 0x1
Ry,Rx,<ea>,Rw,Accx PST = 0x1, {PST = 0xB, DD = source operand}
30.7.2 Supervisor Instruction Set
The supervisor instruction set has complete access to the user mode instructions plus the opcodes
shown below. The PST/DDATA specification for these opcodes is shown in Table 30-25 .
30-44
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Freescale-Recommended BDM Pinout
Table 30-25. PST/DDATA Specification for Supervisor-Mode Instructions
Instruction Operand Syntax cpushl halt move.w
move.w
movec rte stldsr.w
stop wdebug
PST/DDATA
SR,Dx PST = 0x1
{Dy,#imm},SR PST = 0x1, {PST = 0x3}
Ry,Rc PST = 0x1
PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 3}, { PST =0xB,
DD =source operand},
PST = 0x5, {[PST = 0x9AB], DD = target address}
#imm
#imm
<ea>y
PST = 0x1
PST = 0x1,
PST = 0xF
PST = 0x1, {PST = 0xA, DD = destination operand, PST = 0x3}
PST = 0x1,
PST = 0xE
PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}
The move-to-SR, STLDSR, and RTE instructions include an optional PST = 0x3 value, indicating an entry into user mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, a multiple-cycle status of 0xD is signaled.
Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state
(PST = 0xF) display this status throughout the entire time the ColdFire processor is in the given mode.
30.8 Freescale-Recommended BDM Pinout
The ColdFire BDM connector, Figure 30-41
, is a 26-pin Berg connector arranged 2 ×13.
Freescale Semiconductor
MCF5271 Reference Manual, Rev. 2
30-45
Debug Support
Developer reserved
1
GND
GND
RESET
Pad-Voltage
2
GND
PST2
PST0
DDATA2
DDATA0
Freescale reserved
GND
Core-Voltage
10
12
14
16
6
8
2
4
18
20
22
24
26
9
11
13
15
5
7
1
3
17
19
21
23
25
BKPT
DSCLK
Developer reserved
1
DSI
DSO
PST3
PST1
DDATA3
DDATA1
GND
Freescale reserved
PSTCLK
TA
1
Pins reserved for BDM developer use.
2
Supplied by target
Figure 30-41. Recommended BDM Connector
30-46
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Register Memory Map
Appendix A
Register Memory Map Quick Reference
A.1 Register Memory Map
summarizes the address, name, and byte assignment for registers within the MCF5271
CPU space.
Table A-2 lists an overview of the memory map for the on-chip modules. Each module
through
Section 11.2.1.1, “Internal Peripheral
System Base Address Register (IPSBAR),”
for determining the value of IPSBAR.
Table A-1. CPU Space Register Memory Map
Address
CPU @ 0x002
CPU @ 0x004
CPU @ 0x005
CPU @ 0x800
CPU @ 0x801
CPU @ 0x804
CPU @ 0x805
CPU @ 0x806
CPU @ 0x807
CPU @ 0x808
CPU @ 0x809
CPU @ 0x80A
CPU @ 0x80B
CPU @ 0x80E
CPU @ 0x80F
CPU @ 0xC05
Name
Cache Control Register
Access Control Register 0
Access Control Register 1
Other Stack Pointer
Vector Base Register
MAC Status Register
MAC Mask Register
MAC Accumulator 0
MAC Accumulator 0, 1 extension bytes
MAC Accumulator 2, 3 extension bytes
MAC Accumulator 1
MAC Accumulator 2
MAC Accumulator 3
Status Register
Program Counter
RAM Base Address Register
Mnemonic
CACR
ACR0
ACR1
OTHER_A7
VBR
MACSR
MASK
ACC0
ACCext01
ACCext23
ACC1
ACC2
ACC3
SR
PC
RAMBAR
Size
16
16
32
32
16
16
16
16
32
8
16
16
32
32
32
32
Table A-2. MCF5271 Memory Map
Address Module Name
IPSBAR + 0x00 0000 System Control Module (SCM)
IPSBAR + 0x00 0040 SDRAMC
IPSBAR + 0x00 0080 EIM (Chip Selects)
Size
64 bytes
64 bytes
128 bytes
Module Map
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor A-1
Register Memory Map Quick Reference
Table A-2. MCF5271 Memory Map (Continued)
Address Module Name
IPSBAR + 0x00 0100 DMA (Channel 0)
IPSBAR + 0x00 0110 DMA (Channel 1)
IPSBAR + 0x00 0120 DMA (Channel 2)
IPSBAR + 0x00 0130 DMA (Channel 3)
IPSBAR + 0x00 0200 UART0
IPSBAR + 0x00 0240 UART1
IPSBAR + 0x00 0280 UART2
IPSBAR + 0x00 02C0 Reserved
IPSBAR + 0x00 0300 I
2
C
IPSBAR + 0x00 0340 QSPI
IPSBAR + 0x00 0380 Reserved
IPSBAR + 0x00 0400 DMA Timer0
IPSBAR + 0x00 0440 DMA Timer1
IPSBAR + 0x00 0480 DMA Timer2
IPSBAR + 0x00 04C0 DMA Timer3
IPSBAR + 0x00 0500 Reserved
IPSBAR + 0x00 0C00 INTC0
IPSBAR + 0x00 0D00 INTC1
IPSBAR + 0x00 0E00 Reserved
IPSBAR + 0x00 0F00 Global Interrupt Ack Cycles
IPSBAR + 0x00 1000 Fast Ethernet Controller - Registers and MIB RAM
IPSBAR + 0x00 1400 Fast Ethernet Controller - FIFO Memory
IPSBAR + 0x00 1800 Reserved
IPSBAR + 0x10 0000 GPIO
IPSBAR + 0x11 0000 CCM
IPSBAR + 0x12 0000 Clocks (PLL)
IPSBAR + 0x13 0000 Edge Port
IPSBAR + 0x14 0000 Watchdog Timer
IPSBAR + 0x15 0000 PIT0
IPSBAR + 0x16 0000 PIT1
IPSBAR + 0x17 0000 PIT2
IPSBAR + 0x18 0000 PIT3
IPSBAR + 0x19 0000 MDHA
Size
256 bytes
256 bytes
256 bytes
256 bytes
1 Kbyte
1 Kbyte
1018 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 bytes
64 bytes
128 bytes
64 bytes
64 bytes
64 bytes
64 bytes
1792 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
Module Map
—
—
—
—
MCF5271 Reference Manual, Rev. 2
A-2 Freescale Semiconductor
Table A-2. MCF5271 Memory Map (Continued)
Module Name Address
IPSBAR + 0x1A 0000 RNG
IPSBAR + 0x1B 0000 SKHA
IPSBAR + 0x1C 0000 Reserved
Table A-3. SCM Memory Map
Base Address: IPSBAR
Offset Page Register Description
0x00_0000
0x00_0004
0x00_0008
0x00_000C
0x00_0010
—
—
Internal Peripheral System Base Address Register
Memory Base Address Register
Core Reset Status Register
Core Watchdog Control Register
Low Power Interrupt Control Register
Core Watchdog Service Register
0x00_0018
0x00_001C
0x00_0020
0x00_0024
0x00_0028
0x00_002C
—
Bus Master Park Register
Master Privilege Register
Peripheral Access Control Registers (0–3)
Peripheral Access Control Registers (4–6)
Peripheral Access Control Registers (7–8)
0x00_0030
Grouped Peripheral Access Control Register
1
The LPICR is described in
Chapter 8, “Power Management.”
[31:24]
CRSR
MPR
PACR0
PACR4
PACR7
GPACR
Size
64 Kbytes
64 Kbytes
~1022 Mbytes
Module Map
—
[23:16]
IPSBAR
[15:8]
CWCR
PACR1
RAMBAR
MPARK
LPICR
1
PACR2
PACR5
PACR8
[7:0]
CWSR
PACR3
PACR6
Base Address: IPSBAR
Offset
0x00_0040
0x00_0044
0x00_0048
0x00_004C
0x00_0050
0x00_0054
Page
—
Base Address: IPSBAR
Offset
0x00_0080
0x00_0084
0x00_0088
0x00_008C
0x00_0090
0x00_0094
0x00_0098
0x00_009C
0x00_00A0
0x00_00A4
0x00_00A8
0x00_00AC
0x00_00B0
0x00_00B4
0x00_00B8
Page
16-8
16-7
16-8
16-9
16-7
Table A-4. SDRAMC Memory Map
Register Description
DRAM Control Register
[31:24]
DCR
[23:16] [15:8] [7:0]
DRAM Address and Control Register 0
DRAM Mask Register block 0
DRAM Address and Control Register 1
DRAM Mask Register block 1
Table A-5. EIM (Chip Selects) Memory Map
Register Description
Chip Select Address Register—Bank 0
Chip Select Mask Register—Bank 0
Chip Select Control Register—Bank 0
Chip Select Address Register—Bank 1
Chip Select Mask Register—Bank 1
Chip Select Control Register—Bank 1
Chip Select Address Register—Bank 2
Chip Select Mask Register—Bank 2
Chip Select Control Register—Bank 2
Chip Select Address Register—Bank 3
Chip Select Mask Register—Bank 3
Chip Select Control Register—Bank 3
Chip Select Address Register—Bank 4
Chip Select Mask Register—Bank 4
Chip Select Control Register—Bank 4
DACR0
DMR0
DACR1
DMR1
[31:24]
CSAR0
[23:16]
CSMR0
[15:8]
CSCR0
[7:0]
CSAR1
CSMR1
CSCR1
CSAR2
CSMR2
CSCR2
CSAR3
CSMR3
CSCR3
CSAR4
CSMR4
CSCR4
Base Address: IPSBAR
Offset
0x00_00BC
0x00_00C0
0x00_00C4
0x00_00C8
0x00_00CC
0x00_00D0
0x00_00D4
0x00_00D8
0x00_00DC
Page
Base Address:
DMA0: IPSBAR + 0x00_0100
DMA1: IPSBAR + 0x00_0110
DMA2: IPSBAR + 0x00_0120
DMA3: IPSBAR + 0x00_0130
Offset
0x0
0x4
0x8
0xC
Page
Table A-5. EIM (Chip Selects) Memory Map (Continued)
Register Description
Chip Select Address Register—Bank 5
Chip Select Mask Register—Bank 5
Chip Select Control Register—Bank 5
Chip Select Address Register—Bank 6
Chip Select Mask Register—Bank 6
Chip Select Control Register—Bank 6
Chip Select Address Register—Bank 7
Chip Select Mask Register—Bank 7
Chip Select Control Register—Bank 7
Table A-6. DMA Memory Map
[31:24]
CSAR5
[23:16]
CSMR5
[15:8]
CSCR5
[7:0]
CSAR6
CSMR6
CSCR6
CSAR7
CSMR7
CSCR7
Register Description
Source Address Register n
Destination Address Register n
DMA Status Register n
Byte Count Register n
DMA Control Register n
[31:24]
DSRn
[23:16]
SARn
DARn
[15:8]
DCRn
BCRn
[7:0]
Table A-7. UART Memory Map
Base Address:
UART0: IPSBAR + 0x00_0200
UART1: IPSBAR + 0x00_0240
UART2: IPSBAR + 0x00_0280
Offset Page Register Description [31:24] [23:16] [15:8] [7:0]
0x00
0x04
0x08
0x0C
0x10
UART Mode Registers
1
(Read) UART Status Register
(Write) UART Clock Select Register
(Read) Do not access
2
(Write) UART Command Register
(UART/Read) UART receive buffer
(UART/Write) UART transmit buffer
(Read) UART Input Port change Register
(Write) UART Auxiliary Control Register
UMR1n
UMR2n
USRn
UCSRn
UCRn
URBn
UTBn
UIPCRn
UACRn
0x14
0x18
0x1C
(Read) UART Interrupt Status Register
(Write) UART Interrupt Mask Register
(Read) Do not access
UART Divider Upper Register
(Read) Do not access
UART Divider Lower Register
UISRn
UIMRn
UBG1n
UBG2n
0x34
0x38
0x3C
(Read) UART Input Port Register
(Read) Do not access
(Write) UART Output Port Bit Set Command Register
(Read) Do not access
(Write) UART Output Port Bit Reset Command Register
UIPn
UOP1n
UOP0n
1
2
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur.
This address is for factory testing. Reading this location results in undesired effects and possible incorrect transmission or reception of characters.
Register contents may also be changed.
Table A-8. I
2
C Memory Map
Base Address: IPSBAR
Offset Page
0x00_0300
0x00_0304
0x00_0308
0x00_030C
0x00_0310
Register Description
I
2
C Address Register
I
2
C Frequency Divider Register
I
2
C Control Register
I
2
C Status Register
I
2
C Data I/O Register
Table A-9. QSPI Memory Map
[31:24]
I2ADR
I2FDR
I2CR
I2SR
I2DR
[23:16] [15:8]
Base Address: IPSBAR
Offset Page
0x00_0340
0x00_0344
0x00_0348
0x00_034C
0x00_0350
0x00_0354
Register Description
QSPI Mode Register
QSPI Delay Register
QSPI Wrap Register
QSPI Interrupt Register
QSPI Address Register
QSPI Data Register
[31:24]
QMR
QDLYR
QWR
QIR
QAR
QDR
[23:16] [15:8]
Table A-10. DMA Timer Memory Map
Base Address:
DMA Timer 0: IPSBAR + 0x00_0400
DMA Timer 1: IPSBAR + 0x00_0440
DMA Timer 2: IPSBAR + 0x00_0480
DMA Timer 3: IPSBAR + 0x00_04C0
Offset
0x00
0x04
Page
Register Description
DMA Timer n Mode Register
DMA Timer n Extended Mode Register
DMA Timer n Event Register
DMA Timer n Reference Register
[31:24]
DTMRn
[23:16]
DTRRn
[15:8]
DTXMRn
[7:0]
[7:0]
[7:0]
DTERn
Table A-10. DMA Timer Memory Map (Continued)
Base Address:
DMA Timer 0: IPSBAR + 0x00_0400
DMA Timer 1: IPSBAR + 0x00_0440
DMA Timer 2: IPSBAR + 0x00_0480
DMA Timer 3: IPSBAR + 0x00_04C0
Offset
0x08
0x0C
Page
Register Description
DMA Timer n Capture Register
DMA Timer n Counter Register
[31:24] [23:16]
DTCRn
DTCNn
[15:8]
Table A-11. INTCn Memory Map
Base Address:
INTC0: IPSBAR + 0x00_0C00
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
Page
0x18
0x1C–0x3C
0x40
0x44
0x48
0x4C
0x50
0x54
0x58
—
Register Description
Interrupt Pending Register High
Interrupt Pending Register Low
Interrupt Mask Register High
Interrupt Mask Register Low
Interrupt Force Register High
Interrupt Force Register Low
Interrupt Request Level Register (IRLR)
Interrupt Acknowledge Level and Priority
Register (IACKLPR)
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
[31:24]
IRLR[7:1]
ICR04
ICR08
ICR12
ICR16
ICR20
ICR24
ICR01
ICR05
ICR09
ICR13
ICR17
ICR21
ICR25
[23:16]
IPRH
IPRL
IMRH
IMRL
INTFRCH
INTFRCL
[15:8]
IACKLPR[7:0]
ICR02
ICR06
ICR10
ICR14
ICR18
ICR22
ICR26
[7:0]
[7:0]
ICR03
ICR07
ICR11
ICR15
ICR19
ICR23
ICR27
Table A-11. INTCn Memory Map (Continued)
Base Address:
INTC0: IPSBAR + 0x00_0C00
Offset
0x7C
0x80 - 0xDC
0xE0
0xE4
0xE8
0xEC
0xF0
0xF4
0xF8
0xFC
0x5C
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
Page
Base Address: IPSBAR
Offset Page
0x00_1004
0x00_1008
0x00_1010
Register Description
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Interrupt Control Registers
Software IACK Register
Level 1 IACK Register
Level 2 IACK Register
Level 3 IACK Register
Level 4 IACK Register
Level 5 IACK Register
Level 6 IACK Register
Level 7 IACK Register
Table A-12. FEC Memory Map
SWIACK
L1IACK
L2IACK
L3IACK
L4IACK
L5IACK
L6IACK
L7IACK
Register Description
Interrupt Event Register
Interrupt Mask Register
Receive Descriptor Active Register
[31:24]
[31:24]
ICR28
ICR32
ICR36
ICR40
ICR44
ICR48
ICR52
ICR56
ICR60
[23:16]
ICR29
ICR33
ICR37
ICR41
ICR45
ICR49
ICR53
ICR57
ICR61
[23:16]
EIR
EIMR
RDAR
[15:8]
[15:8]
ICR30
ICR34
ICR38
ICR42
ICR46
ICR50
ICR54
ICR58
ICR62
[7:0]
ICR31
ICR35
ICR39
ICR43
ICR47
ICR51
ICR55
ICR59
ICR63
[7:0]
Base Address: IPSBAR
Offset Page
0x00_1014
0x00_1024
0x00_1040
0x00_1044
0x00_1064
0x00_1084
0x00_10C4
0x00_10E4
0x00_10E8
0x00_10EC
0x00_1118
0x00_111C
0x00_1120
0x00_1124
0x00_1144
0x00_114C
0x00_1150
0x00_1180
0x00_1184
0x00_1188
Table A-12. FEC Memory Map (Continued)
[31:24] Register Description
Transmit Descriptor Active Register
Ethernet Control Register
MII Data Register
MII Speed Control Register
MIB Control/Status Register
Receive Control Register
Transmit Control Register
Physical Address Low Register
Physical Address High+ Type Field
Opcode + Pause Duration
Upper 32 bits of Individual Hash Table
Lower 32 Bits of Individual Hash Table
Upper 32 bits of Group Hash Table
Lower 32 bits of Group Hash Table
Transmit FIFO Watermark
FIFO Receive Bound Register
FIFO Receive FIFO Start Registers
Pointer to Receive Descriptor Ring
Pointer to Transmit Descriptor Ring
Maximum Receive Buffer Size
[23:16]
PAUR
OPD
IAUR
IALR
GAUR
GALR
TFWR
FRBR
TDAR
ECR
MDATA
MSCR
MIBC
RCR
TCR
PALR
FRSR
ERDSR
ETDSR
EMRBR
[15:8] [7:0]
Base Address: IPSBAR
Offset Page
0x00_1200
0x00_1204
0x00_1208
0x00_120C
0x00_1210
0x00_1214
0x00_1218
0x00_121C
0x00_1220
0x00_1224
0x00_1228
0x00_122C
0x00_1230
0x00_1234
0x00_1238
0x00_123C
0x00_1240
0x00_1244
0x00_1248
0x00_124C
0x00_1250
0x00_1254
0x00_1258
0x00_125C
0x00_1260
Table A-13. FEC MIB Counters Memory Map
[31:24] Register Description
Count of frames not counted correctly
RMON Tx packet count
RMON Tx Broadcast Packets
RMON Tx Multicast Packets
RMON Tx Packets w CRC/Align error
RMON Tx Packets < 64 bytes, good crc
RMON Tx Packets > MAX_FL bytes, good crc
RMON Tx Packets < 64 bytes, bad crc
RMON Tx Packets > MAX_FL bytes, bad crc
RMON Tx collision count
RMON Tx 64 byte packets
RMON Tx 65 to 127 byte packets
RMON Tx 128 to 255 byte packets
RMON Tx 256 to 511 byte packets
RMON Tx 512 to 1023 byte packets
RMON Tx 1024 to 2047 byte packets
RMON Tx packets w > 2048 bytes
RMON Tx Octets
Count of frames not counted correctly
Frames Transmitted OK
Frames Transmitted with Single Collision
Frames Transmitted with Multiple Collisions
Frames Transmitted after Deferral Delay
Frames Transmitted with Late Collision
Frames Transmitted with Excessive Collisions
[23:16] [15:8]
RMON_T_DROP
RMON_T_PACKETS
RMON_T_BC_PKT
RMON_T_MC_PKT
RMON_T_CRC_ALIGN
RMON_T_UNDERSIZE
RMON_T_OVERSIZE
RMON_T_FRAG
RMON_T_JAB
RMON_T_COL
RMON_T_P64
RMON_T_P65TO127
RMON_T_P128TO255
RMON_T_P256TO511
RMON_T_P512TO1023
RMON_T_P1024TO2047
RMON_T_P_GTE2048
RMON_T_OCTETS
IEEE_T_DROP
IEEE_T_FRAME_OK
IEEE_T_1COL
IEEE_T_MCOL
IEEE_T_DEF
IEEE_T_LCOL
IEEE_T_EXCOL
[7:0]
Base Address: IPSBAR
Offset Page
0x00_1264
0x00_1268
0x00_126C
0x00_1270
0x00_1274
0x00_1278–
0x00_1280
0x00_1284
0x00_1288
0x00_128C
0x00_1290
0x00_1294
0x00_1298
0x00_129C
0x00_12A0
0x00_12A4
0x00_12A8
0x00_12AC
0x00_12B0
0x00_12B4
0x00_12B8
0x00_12BC
0x00_12C0
0x00_12C4
0x00_12C8
Table A-13. FEC MIB Counters Memory Map (Continued)
Register Description
Frames Transmitted with Tx FIFO Underrun
Frames Transmitted with Carrier Sense Error
Frames Transmitted with SQE Error
Flow Control Pause frames transmitted
Octet count for Frames Transmitted w/o Error
RMON Rx packet count
RMON Rx Broadcast Packets
RMON Rx Multicast Packets
RMON Rx Packets w CRC/Align error
RMON Rx Packets < 64 bytes, good crc
RMON Rx Packets > MAX_FL bytes, good crc
RMON Rx Packets < 64 bytes, bad crc
RMON Rx Packets > MAX_FL bytes, bad crc
RMON Rx 64 byte packets
RMON Rx 65 to 127 byte packets
RMON Rx 128 to 255 byte packets
RMON Rx 256 to 511 byte packets
RMON Rx 512 to 1023 byte packets
RMON Rx 1024 to 2047 byte packets
RMON Rx packets w > 2048 bytes
RMON Rx Octets
Count of frames not counted correctly
[31:24] [23:16] [15:8]
IEEE_T_MACERR
IEEE_T_CSERR
IEEE_T_SQE
IEEE_T_FDXFC
IEEE_T_OCTETS_OK
RMON_R_PACKETS
RMON_R_BC_PKT
RMON_R_MC_PKT
RMON_R_CRC_ALIGN
RMON_R_UNDERSIZE
RMON_R_OVERSIZE
RMON_R_FRAG
RMON_R_JAB
RMON_R_RESVD_0
RMON_R_P64
RMON_R_P65TO127
RMON_R_P128TO255
RMON_R_P256TO511
RMON_R_P512TO1023
RMON_R_P1024TO2047
RMON_R_P_GTE2048
RMON_R_OCTETS
IEEE_R_DROP
[7:0]
Base Address: IPSBAR
Offset Page
0x00_12CC
0x00_12D0
0x00_12D4
0x00_12D8
0x00_12DC
0x00_12E0
Base Address: IPSBAR
Offset
0x10_0000
0x10_0004
0x10_0008
0x10_000C
0x10_0010
0x10_0014
0x10_0018
0x10_001C
0x10_0020
Page
0x10_0024
0x10_0028
0x10_002C
Table A-13. FEC MIB Counters Memory Map (Continued)
Register Description
Frames Received OK
Frames Received with CRC Error
Frames Received with Alignment Error
Receive Fifo Overflow count
Flow Control Pause frames received
Octet count for Frames Rcvd w/o Error
[31:24]
Table A-14. GPIO (Ports) Memory Map
[23:16] [15:8]
IEEE_R_FRAME_OK
IEEE_R_CRC
IEEE_R_ALIGN
IEEE_R_MACERR
IEEE_R_FDXFC
IEEE_R_OCTETS_OK
Register Description
Port Output Data Registers
Port Data Direction Registers
Port Pin Data/Set Data Registers
[7:0]
[31:24] [23:16] [15:8] [7:0]
PODR_ADDR
PODR_BS
PODR_UARTH
PODR_ETPU
PDDR_ADDR
PDDR_BS
PDDR_UARTH
PDDR_ETPU
PODR_DATAH
PODR_CS
PODR_UARTL
PDDR_DATAH
PDDR_CS
PDDR_UARTL
PODR_DATAL
PODR_SDRAM
PODR_QSPI
PDDR_DATAL
PDDR_SDRAM
PDDR_QSPI
PODR_BUSCTL
PODR_FECI2C
PODR_TIMER
PDDR_BUSCTL
PDDR_FECI2C
PDDR_TIMER
PPDSDR_ADDR PPDSDR_DATAH PPDSDR_DATAL PPDSDR_BUSCTL
PPDSDR_BS PPDSDR_CS
PPDSDR_SDRA
M
PPDSDR_UARTH PPDSDR_UARTL PPDSDR_QSPI
PPDSDR_ETPU
PPDSDR_FECI2C
PPDSDR_TIMER
Table A-14. GPIO (Ports) Memory Map (Continued)
Base Address: IPSBAR
Offset
0x10_0030
0x10_0034
0x10_0038
0x10_003C
0x10_0040
0x10_0044
0x10_0048
0x10_004C
0x10_0050
0x10_0054
Page
Register Description
Port Clear Output Data Registers
Pin Assignment Registers
Drive Strength Control Registers
[31:24] [23:16]
PCLRR_ADDR
PCLRR_BS
PCLRR_UARTH
PCLRR_ETPU
PCLRR_DATAH
PCLRR_CS
PCLRR_UARTL
PAR_AD
PAR_BS
PAR_UART
PAR_CS
PAR_TIMER
DSCR_EIM DSCR_ETPU
DSCR_QSPI DSCR_TIMER
[15:8]
PCLRR_DATAL
PCLRR_SDRAM
PCLRR_QSPI
[7:0]
PCLRR_BUSCTL
PCLRR_FECI2C
PCLRR_TIMER
PAR_BUSCTL
PAR_SDRAM PAR_FECI2C
PAR_QSPI
PAR_ETPU
DSCR_FECI2C DSCR_UART
Table A-15. CCM Memory Map
Base Address: IPSBAR
Offset Page Register Description [31:24] [23:16] [15:8] [7:0]
0x11_0004
Chip Configuration Register
Low-Power Control Register
CCR
LPCR
1
0x11_0008
Reset Configuration Register
Chip Identification Register
RCON
CIR
0x11_000C
0x11_0010
—
—
Reserved
2
Unimplemented
3
1
2
3
See Chapter 8, “Power Management
,” for a description of the LPCR. It is shown here only to warn against accidental writes to this register.
Writing to reserved addresses with values other than 0 could put the device in a test mode; reading returns 0s.
Accessing an unimplemented address has no effect and causes a cycle termination transfer error.
Base Address: IPSBAR
Offset
0x12_0000
0x12_0004
Page
Base Address: IPSBAR
Offset
0x13_0000
0x13_0004
Page
Base Address: IPSBAR
Offset
0x14_0000
0x14_0004
Page
Table A-16. Clocks Memory Map
Register Description
Synthesizer Control Register
Synthesizer Status Register
[31:24]
Table A-17. Edge Port Memory Map
[23:16]
SYNCR
SYNSR
[15:8]
[15:8]
EPDDR
Register Description
EPORT Pin Assignment Register
EPORT Data Direction Register
EPORT Interrupt Enable Register
EPORT Data Register
EPORT Pin Data Register
EPORT Flag Register
[31:24]
EPPAR
[23:16]
EPDR
Table A-18. Watchdog Timer Memory Map
EPPDR
Register Description
Watchdog Control Register
Watchdog Modulus Register
Watchdog Count Register
Watchdog Service Register
[31:24]
WCR
[23:16]
WCNTR
EPFR
[15:8]
WMR
WSR
[7:0]
[7:0]
EPIER
[7:0]
Table A-19. PITn Memory Map
Base Address:
PIT0: IPSBAR + 0x15_0000
PIT1: IPSBAR + 0x16_0000
PIT2: IPSBAR + 0x17_0000
PIT3: IPSBAR + 0x18_0000
Offset
0x0000
0x0004
Page
Base Address: IPSBAR
Offset Page
0x19_0000
0x19_0004
0x19_0008
0x19_000C
0x19_0010
0x19_0014
0x19_001C
0x19_0020–
0x19_002C
0x19_0030
0x19_0034
0x19_0038
0x19_003C
0x19_0040
0x19_0044
0x19_0048–
0x19_006C
—
Register Description
PIT Control and Status Register
PIT Modulus Register
PIT Count Register
[31:24]
PCSRn
[23:16]
Table A-20. MDHA Memory Map
PCNTRn
Register Description
MDHA Mode Register
MDHA Control Register
MDHA Command Register
MDHA Status Register
MDHA Interrupt Status Register
MDHA Interrupt Mask Register
MDHA Data Size Register
MDHA Input FIFO Register
Message Digest A0 Register
Message Digest B0 Register
Message Digest C0 Register
Message Digest D0 Register
Message Digest E0 Register
Message Data Size Register
[31:24]
[15:8]
[23:16]
MDMR
MDCR
MDCMR
MDSR
MDISR
MDIMR
MDDSR
[15:8]
MDIN
MDA0
MDB0
MDC0
MDD0
MDE0
MDMDS
PMRn
[7:0]
[7:0]
Base Address: IPSBAR
Offset Page
0x19_0070
0x19_0074
0x19_0078
0x19_007C
0x19_0080
Base Address: IPSBAR
Offset Page
0x1A_0000
0x1A_0004
0x1A_0008
0x1A_000C
Base Address: IPSBAR
Offset Page
0x1B_0000
0x1B_0004
0x1B_0008
0x1B_000C
0x1B_0010
0x1B_0014
0x1B_0018
0x1B_001C
0x1B_0020
Table A-20. MDHA Memory Map (Continued)
Register Description
Message Digest A1 Register
Message Digest B1 Register
Message Digest C1 Register
Message Digest D1 Register
Message Digest E1 Register
[31:24]
Table A-21. RNG Memory Map
[23:16]
MDA1
MDB1
MDC1
MDD1
MDE1
[15:8]
Register Description
RNG Control Register
RNG Status Register
RNG Entropy Register
RNG Output FIFO
[31:24]
Table A-22. SKHA Memory Map
Register Description
SKHA Mode Register
SKHA Control Register
SKHA Command Register
SKHA Status Register
SKHA Interrupt Status Register
SKHA Interrupt Mask Register
SKHA Key Size Register
SKHA Data Size Register
SKHA Input FIFO
[31:24]
[23:16]
RNGCR
RNGSR
RNGER
RNGOUT
[15:8]
[23:16]
SKMR
SKCR
SKCMR
SKSR
SKESR
SKEMR
SKKSR
SKDSR
SKIN
[15:8]
[7:0]
[7:0]
[7:0]
Table A-22. SKHA Memory Map (Continued)
Base Address: IPSBAR
Offset Page
0x1B_0024
0x1B_0030
0x1B_0034
0x1B_0038
0x1B_003C
0x1B_0040
0x1B_0044
0x1B_0048–
0x1B_006C
—
0x1B_0070
0x1B_0074
0x1B_0078
0x1B_007C
0x1B_0080
0x1B_0084
0x1B_0088
0x1B_008C
0x1B_0090
0x1B_0094
0x1B_0098
0x1B_009C
Register Description
SKHA Output FIFO
SKHA Key 1
SKHA Key 2
SKHA Key 3
SKHA Key 4
SKHA Key 5
SKHA Key 6
SKHA Context 1 (IV/Nonce/Running Offset/CTR/MAC)
SKHA Context 2
SKHA Context 3
SKHA Context 4
SKHA Context 5
SKHA Context 6
SKHA Context 7
SKHA Context 8
SKHA Context 9
SKHA Context 10
SKHA Context 11
SKHA Context 12
[31:24] [23:16]
SKOUT
SKK1
SKK2
SKK3
SKK4
SKK5
SKK6
[15:8]
SKC1
SKC2
SKC3
SKC4
SKC5
SKC6
SKC7
SKC8
SKC9
SKC10
SKC11
SKC12
[7:0]
Index
B
Bus
–
data transfer
line read bus cycles 17-12 line transfers 17-12
C
Cache
,
registers
access control 0–1 (ACRn) 3-8 ,
CCM configuration
clock mode 9-10 output pad strength 9-10
operation
registers
reset configuration (RCON) 9-5
signals
Chip select module
operation
port sizing 16-4 wait state 16-4
registers
signals
chip select (CS7–0) 16-1 output enable (OE) 16-1
Clock module
operation
PLL
charge pump/loop filter 7-22 ,
loss-of-clock
alternate clock selection 7-25 detection 7-25 reset 7-25
loss-of-lock
multiplication factor divider (MFD) 7-23
phase and frequency detector (PFD) 7-22
voltage control output (VCO) 7-23
registers
synthesizer control (SYNCR) 7-8
synthesizer status (SYNSR) 7-11
signals
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor Index-1
Core
registers
program counter (PC) 3-3 stack pointer (A7) 3-3 ,
D
Debug
BDM commands
–
registers
address attribute trigger (AATR) 30-7
address breakpoint (ABLR, ABHR) 30-8
configuration/status (CSR) 30-9
data breakpoint/mask (DBR, DBMR) 30-12
program counter breakpoint/mask (PBR,
trigger definition (TDR) 30-14
signals
MCF5271 Reference Manual, Rev. 2
DMA data transfer
DMA controller
registers
destination address (DARn) 14-8
request control (DMAREQC) 14-6
E
EMAC
instructions
operation
registers
EPORT
registers
port data (EPDR) 15-5 port interrupt enable (EPIER) 15-5
Index-2 Freescale Semiconductor
Ethernet
buffer descriptors
errors
reception
CRC 19-48 frame length 19-48 non-octet 19-48 overrun 19-48
transmission
late collision 19-47 underrun 19-47
operation
10 Mbps and 100 Mbps MII 19-37
registers
descriptor group upper/lower address
descriptor individual upper/lower
descriptor individual upper/lower address
FIFO receive bound (FRBR) 19-25
FIFO receive start (FRSR) 19-26
FIFO transmit FIFO watermark (TFWR) 19-25
MII management frame (MMFR) 19-14
MII speed control (MSCR) 19-16
opcode/pause duration (OPD) 19-21
physical address low (PALRn) 19-20 physical address low/high (PALR, PAUR) 19-20
receive buffer size (EMRBR) 19-28
receive descriptor active (RDAR) 19-11
receive descriptor ring start (ERDSR) 19-27
transmit buffer descriptor ring start (ETSDR) 19-27
transmit descriptor active (TDAR) 19-12
Exceptions
External interface module (EIM), see bus
F
G
GPIO
operation
registers
drive strength control (DSCR_x) 12-27
port clear output data (PCLRR_x) 12-16
port data direction (PDDR_x) 12-12
port output data (PODR_x) 12-10
port pin data/set data (PPDSDR_x) 12-14
I
I
2
C
clock
handshaking 25-8 memory map 25-8
programming examples
repeated START generation 25-16
registers
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor Index-3
frequency divider (I2FDR) 25-9
Instructions
enhancements
execution timing
JTAG
Interrupt controller interrupts
prioritization 13-3 recognition 13-3
vector determination 13-4 memory map 13-4
operation
registers
interrupt control (ICRnx) 13-12
interrupt force high/low (INTFRCHn,
interrupt pending high/low (IPRHn, IPRLn) 13-6
interrupt request level (IRLRn) 13-11
J
JTAG instructions
registers
IDCODE 29-5 instruction shift (IR) 29-5
signals
test data input/development serial input
test data output/development serial output
test reset/development serial clock
L
Low-power modes
peripheral behavior
I
2
MCF5271 Reference Manual, Rev. 2
Index-4 Freescale Semiconductor
M
MDHA
operation
registers
input FIFO (MDIF) 26-12 message data size (MDMDS) 26-12 message digest registers 0 (MDDx0) 26-12
message digest registers 1 (MDDx1) 26-13
Memory map
I
2
timers
MCF5271 Reference Manual, Rev. 2
P
PLL
loss-of-clock
alternate clock selection 7-25 detection 7-25 reset 7-25
loss-of-lock
multiplication factor divider (MFD) 7-23
phase and frequency detector (PFD) 7-22
voltage control output (VCO) 7-23
Power management
peripheral behavior
I
2
registers
low-power interrupt control (LPICR) 8-2
Freescale Semiconductor Index-5
Q
QSPI
operation
RAM
registers
address (QAR) 23-14 command RAM (QCRn) 23-14 data (QDR) 23-14
Rx
Tx
R
Registers cache
access control 0–1 (ACRn) 3-8 ,
CCM
reset configuration (RCON) 9-5
chip select module
clock module
synthesizer control (SYNCR) 7-8
synthesizer status (SYNSR) 7-11
core
program counter (PC) 3-3 stack pointer (A7) 3-3 ,
Index-6 debug
address attribute trigger (AATR) 30-7
address breakpoint (ABLR, ABHR) 30-8
configuration/status (CSR) 30-9
data breakpoint/mask (DBR, DBMR) 30-12
program counter breakpoint/mask
trigger definition (TDR) 30-14
DMA controller
destination address (DARn) 14-8
request control (DMAREQC) 14-6
EMAC
EPORT
port data (EPDR) 15-5 port interrupt enable (EPIER) 15-5
Ethernet
descriptor group upper/lower address
descriptor individual upper/lower
descriptor individual upper/lower address
FIFO receive bound (FRBR) 19-25
FIFO receive start (FRSR) 19-26
FIFO transmit FIFO watermark (TFWR) 19-25
MII management frame (MMFR) 19-14
MII speed control (MSCR) 19-16
opcode/pause duration (OPD) 19-21
physical address low (PALRn) 19-20 physical address low/high (PALR, PAUR) 19-20
receive buffer size (EMRBR) 19-28
receive descriptor active (RDAR) 19-11
receive descriptor ring start (ERDSR) 19-27
transmit buffer descriptor ring start (ETSDR) 19-27
transmit descriptor active (TDAR) 19-12
GPIO
drive strength control (DSCR_x) 12-27
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
port clear output data (PCLRR_x) 12-16
port data direction (PDDR_x) 12-12
port output data (PODR_x) 12-10
port pin data/set data (PPDSDR_x) 12-14
I
2
C
frequency divider (I2FDR) 25-9
interrupt controller interrupt acknowledge level and priority
interrupt control (ICRnx) 13-12
interrupt force high/low (INTFRCHn,
interrupt pending high/low (IPRHn, IPRLn) 13-6
interrupt request level (IRLRn) 13-11
JTAG
IDCODE 29-5 instruction shift (IR) 29-5
MDHA
input FIFO (MDIF) 26-12 message data size (MDMDS) 26-12 message digest registers 0 (MDDx0) 26-12
message digest registers 1 (MDDx1) 26-13
power management
low-power interrupt control (LPICR) 8-2
QSPI
address (QAR) 23-14 command RAM (QCRn) 23-14 data (QDR) 23-14
reset controller
RNG
MCF5271 Reference Manual, Rev. 2
SCM
core watchdog control (CWCR) 11-7
core watchdog service (CWSR) 11-8
grouped peripheral access control (GPACR) 11-17
peripheral access control (PACRn) 11-15
SDRAM controller
address and control 0–1 (DACRn) 18-6
mode register
SKHA
error status mask (SKESMR) 28-12
SRAM
timers
DTIM
capture (DTCRn) 22-8 counters (DTCNn) 22-8
PIT
control and status (PCSR) 21-3
count (PCNTR) 21-5 modulus (PMR) 21-5
WDT
count (WCNTR) 20-4 modulus (WMR) 20-4 service (WSR) 20-4
UART modules
auxiliary control (UACRn) 24-13
baud rate generator (UBG1n/UBG2n) 24-15
clock select (UCSRn) 24-10 command (UCRn) 24-10
input port change (UIPCRn) 24-13
interrupt status/mask (UISRn/UIMRn) 24-14
Freescale Semiconductor Index-7
output port command (UOP1n/UOP0n) 24-16
Reset controller
registers
requests
internal 10-8 synchronous 10-8
signals
RNG
registers
S
SCM
registers
core watchdog control (CWCR) 11-7
core watchdog service (CWSR) 11-8
grouped peripheral access control (GPACR) 11-17
peripheral access control (PACRn) 11-15
SDRAM controller
example
MCF5271 Reference Manual, Rev. 2
synchronous
registers
address and control 0–1 (DACRn) 18-6
mode register
signals
Signals
CCM
chip select module
chip select (CS7–0) 16-1 output enable (OE) 16-1
clock module
debug
JTAG
test data input/development serial input
test data output/development serial output
test mode select/breakpoint (TMS/BKPT) 29-4
test reset/development serial clock
QSPI
Index-8 Freescale Semiconductor
reset controller
SDRAM controller
SKHA
operation
registers
error status mask (SKESMR) 28-12
SRAM
operation
registers
,
T
Timers
DTIM
operation
registers
capture (DTCRn) 22-8 counters (DTCNn) 22-8
PIT
operation
,
registers
control and status (PCSR) 21-3
count (PCNTR) 21-5 modulus (PMR) 21-5
WDT
operation
,
registers
count (WCNTR) 20-4 modulus (WMR) 20-4 service (WSR) 20-4
U
UART modules
clock select registers (UCSRn) 24-10
clock source
command registers (UCRn) 24-10
input port change (UIPCRn) 24-13
operation looping modes
automatic echo 24-24 local loop-back 24-24
registers
auxiliary control (UACRn) 24-13
baud rate generator (UBG1n/UBG2n) 24-15
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor Index-9
interrupt status/mask (UISRn/UIMRn) 24-14
output port command (UOP1n/UOP0n) 24-16
Index-10
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
General Purpose I/O Module
Interrupt Controller Modules
DMA Controller Module
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Synchronous DRAM Controller
Fast Ethernet Controller (FEC)
Watchdog Timer Module
Programmable Interrupt Timers (PITs)
DMA Timers
Queued Serial Peripheral Interface (QSPI)
UART Modules
I
2
C interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Debug Support
Register Memory Map Quick Reference
Index
27
28
29
30
A
IND
21
22
23
24
25
26
16
17
18
19
20
9
10
11
12
13
14
15
6
7
8
1
2
3
4
5
15
16
17
18
19
20
21
10
11
12
13
14
7
8
9
5
6
3
4
1
2
22
23
24
25
26
27
28
29
30
A
IND
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
General Purpose I/O Module
Interrupt Controller Modules
DMA Controller Module
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Synchronous DRAM Controller
Fast Ethernet Controller (FEC)
Watchdog Timer Module
Programmable Interrupt Timers (PITs)
DMA Timers
Queued Serial Peripheral Interface (QSPI)
UART Modules
I
2
C interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Debug Support
Register Memory Map Quick Reference
Index
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