INTERDATA Model 3, Model 4 Digital Systems Reference Manual

Publication Number 29-004R02
REFERENCE
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Publication Number 29-004 R02
(C) INTERDATA INC., 1967
All Rights Reserved
REFERENCE
MANUAL
2 CRESCENT PLACE/OCEANPORT, NEW JERSEY 07757
IN"TTIERDATA.
PRINTED IN U.S.A.
August 1969
TABLE OF CONTENTS
CHAPTER 1 SYSTEM ARCHITECTURE... .... a 0000000 . 0. 0.2. 0. 0. 0. 0. . 1-1
1.1 INTRODUCTION .......... à +. 6060 8000 66600000 ... . 1-1
1.2 SCOPE OF MANUAL .,...Q.ooosxocdceoosoooooocroo0oooa o о, 1-2
1.3 PROCESSOR ORGANIZATION ...ovo..eveoooscoroooo ‘ 1-2
1.3.1 General Registers ........ Ce ee eee eee ... 1-2
1.3.2 — Arithmetic/Logical Unit ........... 1 00 00 0000 1-2
1.3.3 Control Unit .......4.404.00 00000 0 000 0006 .. 1-4
1.3.4 Memory...................... ... 1-4
1.4 STORAGE WORD FORMATS ....ñooóoroeoscodococoossoooooooo 1-4
1.4.1 Hexadecimal Notation ......Qc0eocososooosoooooocaoo 1-5
1.4.2 Arithmetic Data ......ñ_oseooccoosoooo ro e oo. 1-5
1.4.3 Logical Data . . . vc vi i vt tt tt te eee aon о. ...... 1-6
1.4.4 Information Positioning ......osooXcoeooooo co su о, 1-6
1.5 INSTRUCTION WORD FORMATS .....eñ.eocsooooe: e coco. 1-7
1.6 GENERAL REGISTERS AND STORAGE ADDRESSING ....... 1-9
1.6.1 General Registers .....e.ossoooeooco ce es ete se 1-9
1.6.2 Storage Addressing ..... 0. 00 0. 0... 0. 0... 0... e eco 1-9
1.6.3 Address Modification By Indexing .....seososocoo . 1-9
1.7 PROGRAM STATUS WORD .................... ct ee 1-9
1.7.1 Status 4. ev ve tt i i et he ti te ee eee eee eee . 1-10
1.7.2 = Condition Code ............... e ecoroco roo . 1-10
1.7.3 Instruction Address . . vv cv tc tt ec tv oo eo ov oa . 1-10
1.7.4 Instruction Execution .....o0oocoocoooooroo . 1-11
1.8 INTERRUPT SYSTEM ...oeocoscocorcsoosooo oo oo ooo e... 1-11
1.8.1 Interrupt Procedure . . . . . . co cv ii toi vo veo ... 1-11
1.8.2 Acknowledgement of External Interrupts. . ......... 1-12
1.8.3 Internal Interrupts .. 1.024400 000 0 0 0 0 0 0 0 0 00 0 1-12
1.8.4 Power Failure ....ozo_osccoosoosooosooooooooo . 1-12
1.9 INPUT/OUTPUT SYSTEM 9000000 000000000000. 00 00 .. 1-12
1.9.1 Basic Input/Output Programming ........... .... 1-13
1.9.2 Program Controlled Input/Output + . «vv vv oo vo ov. 1-13
1.9.3 Interrupt Controlled Input/Output .......... ...... 1-13
1.9.4 Block Input/Output Programming . ........... ‘ce 1-14
1.9.5 Condition Code for Input/Output .. ....... cov .n.. 1-14
1.9.6 Direct Memory Access Channel ................ 1-14
1.9.7 Selector Channel .....e.o_ososcoooodoeooo e... 1-15
CHAPTER 2 INSTRUCTION REPERTOIRE... ............. 1.810 00 6 0000000 2-1
2.1 INTRODUCTION .....00 0000 00 00 0 000 00 0 00 0 0 0 0 00000 2-1
2.2 LOAD AND STORE INSTRUCTIONS ... 0.040 4 0 0 0 00000 6 . 2-2
2.2.1 Load Halfword ...e..ñ.eoocosoorroooreoene aro . 2-3
2.2.2 Store Halfword ................. ct ee esa es 2-3
2.2.3 Load Byte vv vv titties ee... 2-4
2.2.4 Store Byte ....Q.osoecscooocosrooo . 0.0 0.0... 0... 0.0... 2-4
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TABLE OF CONTENTS (Continued)
2.2.5 Load Multiple .. 444240000000 0 4 0 0 0 4 0 4 0 0 00 0
2.2.6 Store Multiple . . . ........... . 0... 0. 0.0.0.0. 0 0.00 .
2.2.7 Floating-Point Load . . ........... 2..2... ...,.
2.2.8 Floating-Point Store .,............ cet tae eae
2.2.9 Load Program Status Word .... cv tv tv vv v0 vos
2.2.10 Unchain ............ GC 00 0 0 0 000 0 00 0 00000000 .
2.2.11 Autoload ................ 02000000 cee ees
FIXED POINT ARITHMETIC INSTRUCTIONS. ....Qeeo.ooocoo
2.3.1 Add Halfword 12424240 0 4 0 4 4 0 8 8 0 0 4 4 a 8 0 0 a 0 0
2.3.2 Add With Carry Halfword 1.142420 4 4 4 a 0 6 0 4 0 04 0
2.3.3 Subtract Halfword 122240200400 0 0 4 4 0 0 0 0 0 2 0 0
2.3.4 Subtract With Carry Halfword ............... .
2.3.5 Multiply Halfword .............. cee te ee ees
2.3.6 Divide Halfword ,............. 1.00 00 000000 .
FLOATING-POINT ARITHMETIC INSTRUCTIONS .....e. ..
2,41 Floating-Point Add ................ co eee .
2.4.2 Floating-Point Subtract ...... 8000 0 4646 RN
2.4.3 Floating-Point Multiply... ... viv vv vv eve... ...
2.4.4 Floating-Point Divide . , . ....... tes aa ea ease as
LOGICAL INSTRUCTIONS 1.442020 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 0
2,51 AND Halfword....+4....24 4040 0008 00 0 ce eee ee
2.5.2 OR Halfword ............. 10 0 00 000000 “ee
2.5.3 Exclusive OR Halfword .. ...... ci ive 6 4 0 6 6
2.5.4 Compare Logical Halfword .............. ....
2.9.9 Floating-Point Compare .......... ch se eee eee
SHIFT INSTRUCTIONS . 4444 4 4 0 0 0 0 0 0 0 4 0 0 1 0 80 6 ...
2.6.1 Shift Left Halfword Arithmetic ............... .
2.6.2 Shift Right Halfword Arithmetic ................
2.6.3 Shift Left Halfword Logical .......... eee eee .
2.6.4 Shift Right Halfword Logical .. 4424444 00 450 00 0
BRANCH INSTRUCTIONS ,...... 8 1 4 8 0 0 0 0 0 0 0 00 0 à ..
2.7.1 Branch on True Condition .. 40 0404 0 0 0 044» “oe
2.7.2 bBranchon False Condition .....eQ.oeoosse nooo.
2.7.3 Branch Unconditional ,........... ce tt tee ee es
2.7.4 No Operation .....o rose, osooosrooo coo. ...
2.7.5 Branch On Index High .. 14144 4 0 0 0 0 0 0 4 6 8 4 4 0 0 4 6
2.7.6 Branch On Index Low or Equal 0 0 0 4 8 8 0 0 2 0 6 ea.
2.7.7 Branch And Link .. 0440 0 00 0 0 0 0 0 0 0 0 0 0 0 4 0 4 6
EXTENDED MNEMONIC CODES FOR BRANCH
ON CONDITION .. 4.44 4 4 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 00 000 0 6 .
2.8.1 Branch on Zero... 42444000 1 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0
2.8.2 Branch On Not Zero... . .. ci iii iii iio viv un.
2.8.3 Branch On Plus 2.422000 06 0 44 0 0 0 0 0 0 0 6 0 0 0 6 6
2.8.4 Branch On Not Plus .. 1.400 0 00 0 00 0 11 0 0 0000 6
2, 8.5 Branch On Minus .. 2024000 4 0 0 0 4 0 8 0 0 0 0 0 0 0 0 + à
2.8.6 Branch On Not Minus L 11242484 4 884 84 81 4 a 4 2 0
2.817 Branch On Carry 2.000 0 0 4 0 4 0 0 0 0000 e...
2.8.8 Branch On OverfloW,...Ñ..oeoesosooosoocsro cee
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TABLE OF CONTENTS (Continued)
2.8.9 Branch On Low ...0Qe.eosoocoooooaoooosoooooo 2-31
2.8.10 Branch On Not Low .. .. .. .......... ct ts ee ee 2-31
2.8.11 BranchOn Equal ............¢¢0¢... ce eee ees 2-32
2.8.12 Branch On Not Equal .....óooere, 2 orcooooaoro 2-32
2.9 DEVICE INTERRUPT AND CONTROL INSTRUCTIONS. ..... . 2-33
2.9.1 Acknowledge Interrupt ......ooscosoosoo eco 2-34
2.9.2 Sense Status ............ 1 4e 0 0 0 1 0 0 0 8 6 000 0 2-34
2.9.3 Output Command .. 20424000 0 00 0 4 0 0 4 4 0 0 1 0 0 6 2-35
2.10 INPUT/OUTPUT INSTRUCTIONS ,.....Q.e.eoecm e. race. 2-36
2.10.1 Read Data .. 22044040 0 0 4 4 0 0 0 0 6 0 0 0 6 0 0 04 4 0 . 2-31
2. 10. 2 Write Data Фо + 5 « « 8s 8 e + + + + e + * e. Фо Ф т о фо + + ес 0 . . о e. 2-37
2.10.3 Read Block ....o.orreroedororeoo Cee ee eee 2-38
2.10.4 Write Block . . . cv vv vv io toe eet on GC eee eae a 2-38
CHAPTER 3 CONSOLE OPERATION AND DISPLAY 1.142040 2110 0 1 02 0 1 a a = 3-1
3.1 INTRODUCTION .. 2400 41 1 0 0 0 0 1 0 0 8 0 0 a 0 8 0 0 0 0 0 0 4 0 0 0 3-1
3.2 CONTROL SWITCHES, 44 44 2 4 4 0 8 0 0 0 0 4 0 4 0 0 8 0 0 0 0 0 0 0 0 3-1
3.3 MODE CONTROL SWITCH ....oooseocoaoo e... . . . .. . 3-2
3.4 SPEED CONTROL SWITCH ...... oes o nooreñaoooo e ono 3-2
3.5 REGISTER DISPLAY SWITCH ,....o..eoosoo ce eee ees 3-2
3.6 DATA/ADDRESS SWITCHES 1110240444 4 10 0 0 4 4 0 1 aa a ee 3-3
3.7 REGISTER DISPLAY 1.444000 6 0 4 0 0 4 0 0 0 0 0 0 6 0 4 ooo. 3-3
3.8 CONSOLE OPERATING PROCEDURES ......oaooooo . . 3-3
3.9 DISPLAY PANEL PROGRAMMING .................... 3-4
APPENDIX 1 SUMMARY OF INSTRUCTIONS - ALPHABETICAL BY NAME. .... .« Al-1
APPENDIX 2 SUMMARY OF INSTRUCTIONS - NUMERICAL BY OP CODE ....... A2-1
APPENDIX 3 ARITHMETIC REFERENCES ....eosooo 00 600000000000 ... A3-1
APPENDIX 4 INPUT/OUTPUT REFERENCES ...ococooooocoooo 00 0. 0.0. 0.0. 0. A4-1
APPENDIX 5 MODEL 3 REFERENCE DATA … + e. + + $ | еб. 5. |* | т Фе * _.* 6 + ee e 6 9 | . $4 А5-1
APPENDIX 6 MODEL 4 REFERENCE DATA ................ ........... A6-1
ILLUSTRATIONS
1-1 INTERDATA Digital Systems, Typical Block Diagram ,...... 1-1
1-2 System Block Diagram , . 124402 00 0 0 00 0004 à cee ee se ss 1-3
1-3 Storage Word Formats .......... 000000 0 00 0000000 1-5
1-4 Fixed-Point Word Formats ........... + 0 00 000000 “oo 1-5
1-5 Floating-Point Word Format ,....Q.o_ oseosroeooooooooeoo . 1-5
1-6 Floating-Point Word Layout .....n.éFoesosoosoosoe coo ... 1-6
1-7 Instruction Word Formats .. .. 0.24 40000000 0 00 0000 0 . 1-7
1-8 Program Status Word Format 444040 4 0 0 4 0 0 0 0 0 4 0 6 1-10
1-9 Status Byte Format ,....... ...... 0 0 0 0 0 0 0 0 04 0 000 1-12
3-1 Display Panel ,,........... Cee eee eee tee ce eee 3-1
iii/iv
CHAPTER 1
SYSTEM ARCHITECTURE
1.1 INTRODUCTION INTERDATA Digital Systems are designed
for the user who has small-scale yet sophis-
ticated requirements, and provide maximum
system flexibility to solve a wide range of
industrial control and scientific computa-
tional problems.
INTERDATA Digital Systems are modular -
ly structured to provide a high degree of
flexibility in configuring application oriented
systems, The building blocks used in the
organization of a system are the Processor,
Memory Modules, interface to peripheral These third generation units use dual in-
devices, and system modules. See Fig- line integrated circuits to provide excellent
ure 1-1, reliability. The systems are modular,
Core Memory Modules |
Метогу Bus
Read-only General Standard Memory
| Memory Pro ' Registers | | elec of | | Bus interface
(SMBI)
Multiplexor Bus (byte, 256 devices)
Selector | Bus (byte)
Special
Device
(Halfword)
Standard peripherai | |
devices and system components
I
Figure 1-1. INTERDATA Digital Systems, Typical Block Diagram
1-1
furnishing the user with an expandable
building block structure that can be adapted
to a variety of system requirements. Stand-
ard units can easily be configured into
operational systems for specialized require-
ments. This modularity and field expand-
ibility, especially in the I/O area, provides
a system which may be easily and econom-
ically adapted to changing system require-
ments.
Features of these systems include a mem-
ory that is addressable and alterable to the
8-bit byte level. Memory is field expand-
able from 1024 bytes to 65, 536 bytes.
All memory is directly addressable with the
primary instruction word; no paging or in-
direct addressing is required.
Sixteen 16-bit general purpose registers can be
used as accumulators or index registers.
Register-to-register instructions permit
operations between any two of the 16 General
Registers, eliminating redundant loads and
stores.
A comprehensive instruction set includes ef-
ficient byte processing instructions, single
instructions for loop control which incre-
ment, test and branch on indexing values,
as well as instructions that test the condition
code and branch directly to any location in
memory.
Logical and arithmetic shift instructions can
shift up to 15 bit positions with a single
instruction.
A flexible Systems Interface includes an
integrated priority interrupt facility and
provides for connecting up to 256 devices.
INTERDATA Digital Systems have third
generation data compatibility including ASCII
and EBCDIC information codes.
1.2 SCOPE OF MANUAL
This manual is intended as a general ref-
erence to ail INTERDATA Digital Systems.
Because of this general nature, all informa-
tion provided does not apply equally to all
INTERDATA Models. On the contrary,
1-2
some features described are optional, and/
or only available on the more sophisticated
systems. Appendices provide specific de-
tails for each of the current INTERDATA
Digital Systems.
1.3 PROCESSOR ORGANIZATION
The various elements of the system are or-
ganized around the primary controlling
unit - The Processor, The Processor con-
tains facilities for:
1. Arithmetic and logical processing
of data
2. Sequencing instructions in the re-
quired order
3. Fetching and storing information
4, Addressing memory
5. Initiating or controlling communi-
cations with external devices
6. Changing states in response to
interrupts
The Processor consists of a group of six-
teen 16-bit General Registers, an Arithmetic/
Logical Unit (ALU), and a Read-Only-Memory
(ROM) control unit. Figure 1-2 is a block
diagram of an INTERDATA Digital System,
1.3.1 General Registers
The General Registers can be used as ac-
cumulators in fixed-point arithmetic and
logical operations, or as index registers
in address arithmetic and indexing opera-
tions. Each register has a capacity of six-
+{tann hinarw dicita
¿cen viñary us one halfword,
A,
Lidge VI ICI 15 Vii, Леда
Ad
For some operations, such as multiplica-
tion and division, two adjacent registers
are coupled to form a 32-bit fullword., In 8-
‘bit byte operations the rightmost 8 bits of
a General Register are used.
1.3.2 Arithmetic/Logical Unit
та EAR wo SF TY
The Arithmetic/ Logical Unit (ALU) processes
binary integers, floating-point fractions, and
logical information. The operands are lo-
cated in the General Registers and/or core
TS RL
Po
CORE MEMORY
ADDRESS
DATA
+
о
' HIGH SPEED MEMORY BUS 3
LJ CE ] E lr Gs Co o o EE Mo
PROCESSOR
0 11412 15,16 31
LOCATION
| K — STATUS |CC COUNTER |
SELECTOR CHANNEL PROGRAM STATUS WORD SMBI
a 15
о 7,8 1112 15,16 31
RAR MAGNITUDE
ОР | %2| ADPRESS/DATA
| INSTRUCTION REGISTER |
SELECTOR CHANNEL BU
| H— FIXED POINT — |
NN REGISTERS
all 7,8 31 N (16) N
EXP, FRACTION SPECIAL
| FLOATING POINT DEVICE
N YN REGISTERS X
| — |
MAGNETIC
DISC
MAGNETIC TAPE | — |
J ARITHMETIC
AND
LOGICAL UNIT
MULTIPLEXOR BUS
LIL
PAPER TAPE
LINE PRINTER
Figure 1-2,
memory, fixed-point data is treated as
signed, 15-bit integers in the halfword for-
mat, or as signed, 31-bit integers in the
fullword format. Positive numbers are ex-
pressed in true binary form with a sign bit of
zero. Negative numbers are represented in
two's complement form with a sign bit of one.
The numeric value of zero is always repre-
sented as positive, Table 1-1 shows several
examples of the fixed-point number repre-
sentation used in INTERDATA Systems.
CARD READER
System Block Diagram
TELETYPE
DISPLAY PANEL
TABLE 1-1, EXAMPLES OF FIXED-POINT
REPRESENTATION
Number | Decimal Binary
215-1 | 32767 | 0111 1111 1111 1111
20 1 0000 0000 0000 0001
0 0 0000 0000 0000 0000
-2Y) -1 1111 1111 1111 1111
-(215) |-32768 | 1000 0000 0000 0000
1-3
All fixed-point operations are performed
upon one operand in a General Register
with the other operand in either a General
Register or a core memory location.
Multiple-precision arithmetic operations
are made convenient by the two's comple-
ment representation, and by recognition of
the carry/borrow from one operation to
another.
Some INTERDATA Digital Systems provide
the capability for floating-point arithmetic
operations. The INTERDATA format for
single-precision, floating-point data is iden-
tical to that used in the IBM System/360.
This format represents numbers in the range
from 5.4 X 10-79 to 7.2 X 1075, with six
digits of precision.
A floating-point number consists of a signed
exponent and a signed fraction. The quantity
expressed by this number is the product of
the fraction and the number 16 raised to the
power of the exponent. The exponent is ex-
pressed in excess 64 binary notation; the
fraction is expressed as a hexadecimal num-
ber having a radix point to the left of the high
order digit. Table 1-2 provides several
examples of the floating point number repre-
sentation,
TABLE 1-2. EXAMPLES OF FLOATING-
POINT NUMBER REPRESENTATION
Value Binary
1.0 0100 0001 0001 0000
- 0000 0000 0000 0000
1.0 1100 0001 0001 0000
a 0000 0000 0000 0000
9 5 0100 0001 1001 1000
0000 0000 0000 0000
re 1100 0000 1000 0000
0000 0000 0600 0000
1111 1111 1111 1111
1111 1111 1111 1111
— nN
16-65 1000 0000 0001 0000
0000 0000 0000 0000
0100 0000 0001 1001
1001 1001 1001 1010
1.3.3 Control Unit
The Processor operates under the direction
of a control unit which has a pre-wired
micro-program contained in the Read-Only-
Memory (ROM). The micro program is a
sequence of micro operations which fetches
the Processor instructions, decodes them,
and processes the operands located in the
General Registers and core memory
locations.
For example, to fetch an instruction, the
micro-program loads the memory address
register with the instruction address, com-
mands a memory read operation, and when
the memory data is ready, transfers the
content of the memory data register to the
working register.
1.3.4 Memory
INTERDATA Systems provide for connection
of multiple memory blocks on a Memory Bus
to the Processor. Each memory block con-
sists of a magnetic core memory plane with
independent Read/Write Control.
The 16-bit halfword data register permits
all 16-bit instructions and arithmetic or
logical data to be handled in a single mem-
ory cycle. Multiple halfword data requires
an additional memory cycle for each 16-bit
halfword. Byte operations are performed
by selectively manipulating the right or
left 8 bits of the 16-bit halfword.
Memory elements can be expanded to a
maximum dynamic addressing range of
65, 536 8-bit bytes or 32,768 16-bit
halfwords.
The optional Memory Parity feature pro-
vides for checking of all data transfers in
a sa À Aust £
ana oui O1 MEMOory.
1.4 STORAGE WORD FORMATS
The INTERDATA instruction Set manipu-
lates data of three different word lengths:
8 bit bytes, 16 bit halfwords or 32 bit full-
words. In each format the bits are num-
bered from left to right, starting with the 1.4.2 Arithmetic Data
number zero. The format for each word The basic fixed-point arithmetic operand is
length is shown on Figure 1-3. the 16-bit halfword. In multiply and divide
operations, 32-bit fullwords are manipulated.
E See Figure 1-4.
HALFWORD
| |
HALFWORD о >
О 718 5 S INTEGER
Ol 15
S| INDEX QUANTITY
FULLWORD |
O 7/8 15116 23/24 Ji FULLWORD
OLI 31
S INTEGER PRODUCT
Figure 1-3. Storage Word Formats
olf 31
1.4.1 Hexadecimal Notation $ DIVIDEND
Binary information is expressed in hexa-
decimal notation (base 16) in the INTER- Figure 1-4. Fixed-Point Word Formats
DATA Systems. Four binary bits of
information can be expressed by a single The halfword arithmetic operand matches
can be expressed by a string of two hexa- fixed-point arithmetic instructions to be used
decimal digits, halfword information by four for address arithmetic. Arithmetic, logical,
hex digits, and fullword information by 8 and shift instructions can also be used for
hex digits. Table 1-3 lists hexadecimal, address manipulation or computation.
binary, and decimal equivalents.
Each floating-point value requires two half-
TABLE 1-3. HEXADECIMAL NOTATION words. The floating-point format is shown
Hexadecimal Binary Decimal | 718 15
S X A
0 0000 0 8
1 0001 1
2 0010 2 S = sign of the fraction
9 0011 3 X = exponent, in excess 64 code
4 0100 4 AB = fraction
5 0101 5
6 0110 6 Figure 1-5. Floating-Point Word Format
7 0111 7
8 1000 8 Sign and magnitude representation is used,
9 1001 9 in which the sign bit S is zero for positive
A 1010 10 values, and one for negative values. The
B 1011 11 fraction AB contains six hexadecimal digits
C 1100 19 as shown in Figure 1-6. The value of a
D 1101 13 floating-point fraction can be expressed as:
E 1110 14 _1 _9 _3 -6
F 1111 15 F,-46 +F,.16 +F ,.16 to... FFL. 16
1-5
| 718 lijià 15
S X F | F2
F3 F4 FS F6
Figure 1-6. Floating-Point Word Layout
A normalized floating-point number has a
non-zero, high-order hexadecimal fraction
digit (F1). If one or more high-order frac-
tion digits (F,F9...) are zero, the number
is said to be unnormalized. The range of
the magnitude (M) of a normalized floating-
point number is:
- -6 63
16%” <M< (1 - 16°) . 16
or approximately
— 75
9 <M< 7.2. 10
5.4 - 10
All floating point numbers are assumed to be
normalized prior to their use as operands.
No pre-normalization is performed, all re-
sults are post-normalized. The floating-
point load instruction will normalize un-
normalized floating-point numbers.
Exponent overflow is defined as a resultant
exponent greater than +63. Exponent under-
flow is defined as a resultant exponent less
than -64. The Overflow flag is set whenever
exponent overflow or underflow is detected.
If overflow, the exponent and fraction of the
result are set to all ones. The sign of the
result is not affected by the overflow. If un-
derflow, the sign, exponent and fraction of
the sum are set to zero.
The floating-point value in which all data
bits are zero is called true zero. A true
zero may arise as the result of an arithme-
tic operation due to exponent underflow, or
when a result fraction is zero due to loss of
significance. In general, zero values partici-
pate as normal numbers in all arithmetic
operations. If the resultant exponent of an
addition, subtraction, multiplication, or
division overflows, all bits of the exponent
and fraction are set, and the correct sign is
generated.
1-6
The floating-point registers have even num-
bers. The register address specified by the
Rj and Ry fields should be even numbers (0,
2,4,6 etc.) otherwise the next lower even
register will be used, There are eight 32-
bit floating-point registers available. The
floating-point registers are separate from
the general registers and are addressable
only by floating-point instructions.
1.4.3 Logical Data
Logical information is handled as 16-bit half-
words or as 8-bit bytes. Halfword operations
are performed on all 16 bits of an operand
located in memory or a General Register.
Logical data is subject to such operations as
AND, OR, EXCLUSIVE OR, and COMPARE
LOGICAL.
Load Byte and Store Byte instructions are
provided to facilitate byte manipulation.
These instructions, when combined with
indexed addressing, enable the processing
of input/output character strings.
1.4.4 Information Positioning
Core memory locations are numbered con-
secutively, beginning at location 0000, for
each eight bit byte. Since the address field
of an instruction word is 16-bits in length,
each of the 65,536 bytes in memory is
directly addressable with the primary in-
struction word.
The INTERDATA System transmits binary
information between memory and the Proc-
essor as 16-bit halfwords. The instruction
being performed determines if the address
specified is that of a byte, a halfword or a
fullword. If a byte of information is de-
sired, either the left or right byte of the
halfword read from memory is manipulated
as determined by the specific address, If
a halfword of information is desired, the
entire 16 bits read irom memory are used.
If a fullword is desired, a second 16 bits
is read from memory and combined with
the original halfword.
Bytes of information are addressed by their
specific hexadecimal address.
A group of bytes
combined to form a halfword or a full word are
addressed by the leftmost byte in the group.
Halfwords are positioned so that the address
is a multiple of 2, Fullwords are positioned
so that the address is a multiple of 4. Table
1-4 illustrates the addressing scheme. Table
1-5 lists the valid last hexadecimal digits for
each type of addressing.
TABLE 1-4. MEMORY ADDRESS DATA
Hexadecimal Address
0050 0051 0052 0053 0054 0055 0056 0057
Hexadecimal 01 23 45 67 89 AB CD EF
Contents _ _ _ _
| B B B B
Word Length Byte Byte Byte Byte yte yte yte yte
Positions Halfword Halfword Halfword Halfword
Fullword Fullword
TABLE 1-5, PERMISSIBLE ADDRESSES In general, each format specifies three
things: The operation to be performed, the
Word Length Last Hex address of the first operand, and the ad-
Desired Digit of Address dress of the second operand. The first
operand is normally a General Register
Byte any Which contains the result of a previous op-
eration. The second operand is normally
Halfword 0,2,4,6,8,A,C,E the contents of a General Register, the
Fullword 0,4,8,C contents of a core memory location, or a
Refer to Table 1-4, If the address specified
were 0050:
1. A byte oriented instruction would
extract the data constant 0116 as its
operand.
2. A halfword oriented instruction
would extract the data constant
3. 0123;4 as its operand.
3. A fullword oriented instruction
would extract the data constant
01234567, as its operand.
1.5 INSTRUCTION WORD FORMATS
Instructions in INTERDATA Systems have
three formats:
1. Register to Register [RR]
2. Register to Indexed Memory [RX]
3. Register to Storage [RS]
data constant used as the other participating
operand.
A 16-bit halfword format is used for reg-
ister to register operations. A 32-bit full-
word format is used for the register to
indexed memory, and the register to storage
formats. The specific formats are shown
on Figure 1-7,
16-BIT HALFWORD
REGISTER-TO-REGISTER
О 718 1112 15
OP R R2
[RR]
32-BIT FULLWORD
REGISTER TO INDEXED MEMORY
[RX]
О 718 2 1516
ОР RI | X2 A
REGISTER-TO-STORAGE [Rs]
O 718 112 15/16 31
OP R1| x2 A
Figure 1-7. Instruction Word Formats
1-7
The $-bit OP field in all three formats
specifies the machine operation to be per-
formed. The operation code can be written
as two hexadecimal characters.
The 4-bit R1 field in the three instruction
formats specifies the address of the first
operand. The Rl field is normally the ad-
dress of a General Register and is written
as one hexadecimal character.
The 4-bit R2 field in the RR instruction
format specifies the address of the second
operand. The R2 field is always a register
address and is written as one hexadecimal
character.
The 4-bit X2 field in the RX and RS formats
specifies a General Register whose content
is used as an index value. The X2 field is
always the address of a General Register
and is written as a single hex character.
The 16-bit A field specifies a memory ad-
dress in the RX format, or contains an inte-
ger value to be used as an immediate operand
in the RS format. It is written as a string of
four hex characters.
The RR instructions are used for operations
between two registers. The first operand
is the contents of the register specified by
the R1 field of the instruction word. The
second operand is the contents of the register
specified by the R2 field.
The RX instructions are used for operations
between a register and memory with the op-
tion of indexing. The first operand is the re-
gister specified by the R1 field of the instruc-
tion word. The second operard | he contents
field of the instruction y he
of the A field and the contents of the General
Register specified by the X2 field if indexing
is specified,
In the RS instructions, the first operand is
the contents of the General Register specified
by the R1 field of the instruction word, The
second operand is the number contained in the
A field, or the number generated by adding
the A field to the contents of the General
1-8
Register specified by the X2 field if indexing
is specified. The second operand of an RS
instruction specifies the number of bit posi-
tions in shift instructions, or forms the sec-
ond operand in immediate instructions. An
immediate operand is two bytes of data used
as an operand and carried in the halfword
address field itself. The value in the ad-
dress field is treated as a signed integer
instead of a memory location address.
For the Branch on Condition instructions the
first operand is the M1 field. This field is a
4-bit mask which is to be tested against the
condition code contained in the Program Status
Word.
Table 1-6 summarizes the first and second
operand designations for each instruction
format.
TABLE 1-6. DESIGNATIONS FOR
FIRST AND SECOND OPERANDS
First The contents of RR, RX
Operand: | the register and RS
specified by the
R1 Field (R1).
The M1 Field RR and RX,
Branch on
Condition,
Second The contents of RR
Operand: | the register
specified by the
R2 Field (R2).
The contents RX
of the address
derived by
adding the A
field and the
nanntnante nf the
CIL IL UE 1
General Register
specified by the
X2 field.
[A + (X2)]
The A field plus RS
the contents of the
General Register
specified by the
X2 field.
A + (X2)
All instructions are aligned on halfword
boundaries. The RR instruction format is
a 16-bit halfword; the RX and RS formats
are 32-bit fullwords which are treated as
two halfwords for alignment purposes.
This permits mixing of halfword and full-
word instructions without the requirement
of halfword No Operation instructions to
force fullword instruction alignment.
16 GENERAL REGISTERS AND
STORAGE ADDRESSING
1.6.1 General Registers
The sixteen General Registers function as
accumulators or index registers in all
arithmetic and logical operations. Each
General Register is a 16-bit halfword con-
sisting of two 8-bit bytes. For arithmetic
operations, bit zero (leftmost position) is
considered the sign bit. Bit one is the
most significant bit,
The General Registers are numbered from
zero to fifteen (decimal) which is written
in hexadecimal notation as 0, 1, 2, 3, 4, 5,
6, 7, 8, 9, A, B, C, D, E, and F. General
Register addresses are only permitted in the
R1, R2 and X2 fields of an instruction word.
The General Registers have not been given
specific functional assignments. However,
the following operational restrictions should
be noted:
1. It is not possible to use General
Register zero as an index register.
In the RX and RS instruction for-
mats, a zero entry in the X2 field
indicates that no indexing is to
take place.
2. Thefirst operand (R1) must specify an
even numbered General Register for
multiplication and division operations.
3. The first operand (R1) for the
Branch on Index instructions speci-
fies the first of three general reg-
isters. General Register D is the
maximum value for R1 in this case,
1.6.2 Storage Addressing
Locations in core memory are addressed by
the RX instruction. The address portion, A,
of the instruction is a 16-bit halfword, making
it possible for the address field to specify all
65,036 bytes, the maximum available memory,
If an address specified is greater than the
highest memory location available, no mem-
ory access takes place, and a word consisting
of all zeros is used in place of the word nor-
mally read from memory.
Programs cannot be looped from the highest
memory location back to location 0000,
1.6.3 Address Modification by Indexing
The General Registers in INTERDATA sys-
tems facilitate address modification. Fifteen
different General Registers may be used as in
index registers for this purpose.
If the contents of the A field of an instruction
word are to be modified, the address of the
General Register, whose content is to be
used as the modifier, is placed in the X2
field of the instruction word. During decoding
of the instruction word, the contents of the
specified index register is added to the A
field to obtain the effective address of the
second operand. The index value in a Gen-
eral Register may be signed to permit indexing
in either direction.
All of the General Registers except General
Register Zero may by used as index registers.
If the X2 field of the instruction word is zero,
no indexing is specified, and the A portion
of the instruction word is not modified. Thus,
General Register Zero cannot be used as an
index register.
1.1 PROGRAM STATUS WORD
The 32-bit Program Status Word (PSW)
contains the information required for pro-
gram execution. The PSW has a 12-bit
Status field, a 4-bit Condition Code field,
and a 16-bit Instruction Address field,
See Figure 1-8.
1-9
PSW
O 11112 15116 3!
STATUS CC | INSTRUCTION ADDRESS
Figure 1-8. Program Status Word Format
In general, the Program Status Word is
used to control instruction sequencing and
to store indications of the status of the sys-
tem in relation to the program currently being
executed. The active or controlling PSW is
referred to as the current PSW, When a
program interrupt occurs, the current
PSW is automatically preserved for sub-
sequent reinstatement or inspection. By
loading a new PSW, the status of the
Processor can be changed.
1.7.1 Status
The status of the current user program is
defined by bits 0 through 11 of the Program
Status Word. When bit 0 is set the Processor
is halted in a high speed, interruptable wait
loop during which interrupts will be recog-
nized immediately. When bit 0 is reset, the
Processor is active and interrupts which are
enabled will be recognized after execution of
the current instruction. Bits 1 through 11
are mask bits for interrupts.
Assignment of the Status bits is listed on
Table 1-7.
1.7.2 Condition Code
The 4-bit Condition Code (CC) of the Program
Status Word is set after execution of arithmetic,
logical, shift, and input/output instructions.
In general, the condition code bits 12 through
15 indicate Carry, Overflow, Greater, and
Less, in that order. The condition code set-
ting has a different interpretation when set
by an input/output instruction and is de
in that section.
Following an arithmetic operation the con-
dition code indicates whether the resuit was
greater or less than zero, whether a carry
or borrow took place, and whether an over-
flow has occurred.
1-10
TABLE 1-7. PSW STATUS BIT
ASSIGNMENTS
PSW bit Assignment
0 Wait state
1 External Interrupt Enable
2 Machine Malfunction
Interrupt Enable
3 Fixed-point Divide Fault
Interrupt Enable
4 Reserved
о Floating-point Divide
Fault Interrupt Enable
6
thru Not Assigned
11
Assignment of Condition Code bits is listed
on Table 1-8,
TABLE 1-8. PSW CONDITION CODE
BIT ASSIGNMENTS
PSW Bit Assignment Symbol
12 Carry/Borrow (C)
13 Overflow (V)
14 Greater than zero (G)
15 Less than zero (1)
1.7.3 Instruction Address
The 16-bit Instruction Address field of the
Program Status Word specifies the location
of the next instruction to be fetched and
processed. The sixteen bit address field
has the capability of addressing the maxi-
mum core memory of 32,768 halfwords.
After instruction execution, the instruction
Address Field is incremented by 2 if the
executed instruction was in the halfword RR
format (2 bytes).
cremented by 4 if the executed instruction
was in the fullword RX or RS format (4
bytes).
MY. = A Aaa Ma bd or os
11€ AUVILODSD LICIU 15 Lli-
1.7.4 Instruction Execution
During normal processing of a program, in-
structions are fetched from the location
specified by the Instruction Address, the
instruction is executed, the Instruction
Address is incremented, and another fetch
and execute cycle begins.
This sequence can be changed when a two-way
conditional choice is required, for entrance
and return to and from a subroutine, or for
iterative groups of instructions, called loops.
Subroutine linkage provides for the introduc-
tion of a new Instruction Address and preser-
vation of the incremented current Instruction
Address as the location for return to the main
program. The instruction that provides this
facility is the Branch and Link instruction.
Decision making is implemented by the Branch
on Condition instructions which inspect the
setting of the 4-bit Condition Code (PSW 12:15).
Loop control can be performed by the condi-
tional branch when it tests the outcome of
arithmetic and counting operations. For
frequent combinations of such tests, the
Branch on Index instructions provide a con-
venient means of performing these tasks.
1.8 INTERRUPT SYSTEM
System interrupts are provided to detect the
presence of illegal instructions, machine
malfunctions, divide faults, and requests
for service from external devices. The
control of interrupts centers around the
Status field of the Program Status Word
(PSW (0:11)). A zero in this field disables
an interrupt; a one in this field enables an
interrupt.
The PSW which defines the operating status
of the Processor is called the current PSW.
There are five additional Program Status
Words, each associated with a specific class
of interrupt. The new PSW defines the ac-
tion to be taken for each type of interrupt;
the old PSW is a reserved storage area in
which the current PSW is placed when an
interrupt is recognized.
Each new PSW re-defines the status of the
machine, usually inhibiting interrupts of its
own class, or possibly all interrupts. The
instruction address field of each new PSW
specifies the starting location of the sub-
program to service the interrupt condition,
Exit from an interrupt service sub-program
is accomplished by the Load Program Status
Word instruction specifying the stored old
PSW. This restores the machine status and
the instruction address which was current
at the time the interrupt occurred.
The Dedicated core locations of the re-
definitive Program Status Word Pairs vary
from model to model and are given in Ap-
pendices 5 and 6.
1.8.1 Interrupt Procedure
After execution of each instruction, the
Processor interrogates for interrupts. If
an interrupt is found pending and the ap-
propriate bit in the Status Field of the PSW
is a one (enabled) the interrupt will take
place. The current PSW is automatically
stored as the old PSW for the class of inter-
rupt which is to be serviced and the new
PSW for the class of interrupt being serv-
iced becomes the current PSW, After the
sequence of instructions servicing the in-
terrupt has been completed, the old PSW
for the class of interrupts being serviced is
normally loaded and becomes the current
PSW,
Note that the new PSW location is not altered
by this interrupt procedure, so that subse-
quent interrupts of the same class will be
serviced in the same manner. The old PSW
location serves as a temporary storage
register for exit from the interrupt service
sub-program and may vary each time an
interrupt request is processed.
If an interrupt request cccurs and the ap-
propriate bit in the Status Field of the PSW
is a zero (disabled) an interrupt will not
occur and the request is ignored.
1-11
External interrupt requests from peripheral
devices remain pending, that is the interrupt
request will be repeated after execution of
each instruction, until enabled by the PSW
and serviced by the program. Program re-
start use of the Initialize switch clears pend-
ing interrupts from external devices.
1.8.2 Acknowledgement of External
Interrupts
The Acknowledge Interrupt instruction
clears the interrupt request and returns
the device address and status byte from the
peripheral causing the interrupt. The right-
most 4 bits of the status byte are copied
into the condition code (PSW 12:15) while
the leftmost 4 bits of the status byte have
meanings unique to each peripheral device.
See Figure 1-9. The device number and
device status byte provide sufficient infor-
mation to determine the cause and action
required by any external interrupt.
O _34 7
— tol PSW (12:15
ive о )
STATUS
BYTE
Figure 1-9, Status Byte Format
1.8.3 Internal Interrupts
Interrupts which originate in the Processor
are the Illegal Instruction, Machine Mal-
function, and Divide Fault Interrupts.
The Illegal Instruction interrupt is not rep-
resented by an enabling bit in the PSW, and
is therefore always operative. An illegal
instruction is defined as an operation code
which cannot be decoded into a legal repre-
sentation for processing. No attempt is
made to execute the illegal instruction, nor
is the instruction address field of the PSW
incremented. Therefore, the old PSW
stored as a result of the illegal instruction
interrupt points to the address of the illegal
instruction.
1-12
The Machine Malfunction Interrupt, enabled
by bit 2 of the Program Status Word, is in-
dicative of a Processor failure from which
no programmed recovery can be made, The
Machine Malfunction Interrupt is generated
by Memory parity error. When the memory
parity option is present in the Processor, a
parity bit is appended to each byte of mem-
ory. The parity bit is set to maintain odd
parity. That is, if a memory byte contains
an odd number of ones the parity bit is zero;
if the memory byte contains an even number
of ones, the parity bit is one,
Parity is recomputed for each byte transfer,
and the parity bits of the transferred byte
and the original byte are compared. If the
parity bits are different, and bit 2 of the Pro-
gram Status Word is set to enable the inter-
rupt, a Machine Malfunction Interrupt is
generated.
The fixed-point Divide Fault interrupt,
enabled by bit 3 of the Program Status Word,
is indicative of quotient overflow. The in-
terrupt takes place prior to alteration of the
operand registers, permitting the interrupt
service subroutine to examine these values.
The floating-point Divide Fault interrupt, if
enabled by bit 5 of the current Program
Status word, results from a floating-point
division by zero.
1.8.4 Power Failure
When power failure is detected, the instruc-
tion being executed is completed and the
Processor and memory are put in a locked
state. Power up will initialize the Proc-
essor to the «tahia at tho tima nf nawar
SE US VAS кб как сы НЕК нала ЛО ЛР МУ
failure. The Processor will be placed in
the Halt mode, from which normal execu-
tion may proceed,
1.9 INPUT/OUTPUT SYSTEM
INTERDATA Systems can transfer informa-
tion between the Processor and peripheral
devices in several modes:
1. A single 8-bit byte at a time
through the General Registers,
2. A single 8-bit byte at a time 1. An Output Command which specifies
through core memory. the function to be performed is
sent to the device.
3. A block of information at a time ent to ic
(string of bytes) under Processor 2. A Sense Status instruction sets the
control. condition code, indicating the state
of the device, i.e., busy, device
4, A block of information directly unavailable. etc
, .
from, or to memory and the
peripheral device under control of 3. A Branch on True Condition in-
an optional Selector Channel. struction waits for the not true
condition, In this case the branch
is taken back to the Sense Status
instruction. The effect of this is to
1.9.1 Basic Input/Output Programming
In general, any data transfer requires a produce a wait loop until the device
series of operations concerned with the is able to transfer data.
device or system with which information is
being transferred. Before data can be 4. When the Branch on True Condition
transferred, the device or system must be fails, the device is ready to trans-
able to accept a command. The Output fer data. The next instruction,
Command instructs the device to perform Read Data or Write Data, causes
such functions as: switch to send mode, the data transfer to take place.
switch to receive mode, go forward, etc, 5. If more than a single byte of infor
Once the device is in the correct mode of mation is to be transferred,
operation, the data transfer can take place. additional steps are required for
indexing. A typical procedure
There are two methods of input/output pro- would be:
gramming, The first method, called pro-
gram controlled, interrogates the device to 1. Initialize general registers
determine if it is ready to transfer data, with an index value and
and waits if necessary until transfer can increment
take place. The second method, called in- 2. Output Command
terrupt controlled, permits the device to
demand service when the device itself is
ready for data transfer. 4, Branch on True Condition to
sense status if not ready
3. Sense Status
Either method of input/output, program
controlled or interrupt controlled, can be 5. Read Data, indexed
used with the Read Data and Write Data 6. Branch on Index to cause in-
instructions to transfer information to or crement and test for number
from the General Registers or core of characters input,
memory.
1.9.3 Interrupt Controlled Input/Output
1.9.2 Program Controlled Input/Output Interrupt controlled data transfer involves
Program controlled data transfer can be the same basic principles used for pro-
accomplished in many ways. The exact gram controlled data transfer. The im-
sequence of instructions depends on the portant difference is that the device is
particular device with which data transfer permitted to interrupt when ready to
is to take place. The following steps transfer data. The wait loop is eliminated
describe the general approach to program and the time saved can be used for inter-
controlled data transfer. nal processing. The following steps de-
1-13
scribe the general approach to interrupt
controlled data transfer.
1. Device signals Processor with
an interrupt request,
2. An Acknowledge Interrupt in-
struction returns the device
address and status byte to the
Processor.
3. A Read/Write Data instruction
causes data transfer to take place.
1.9.4 Block Input/Output Programming
The Optional Read Block and Write Block in-
structions greatly simplify programming of
strings of data. The single instruction
causes information to be transferred be-
tween a device and sequential locations in
core memory. Transfer is terminated when
a pre-determined location is reached, or
when an unusual device status is encountered.
Prior to block transfer, an Output Com-
mand and Sense Status instruction are used
to specify the function and test the status
of the device. The block transfer in-
struction can then perform all remaining
steps of input/output. Note that the com-
plete attention of the processor is given to
the data block transfer and that normal
processing will not resume until comple-
tion of this instruction.
1.9.5 Condition Code for Input/Output
The 4-bit Condition Code (CC) of the Pro-
gram Status Word is set after execution oí
input/output instructions and the device in-
terrupt and control instructions. The inter-
pretation of the condition code after an
input/output instruction differs from the
setting caused by arithmetic and logical
operations,
Following an input/output or device control
instruction, the condition code indicates the
An
device response such as available, busy, or
unavailable. It is important to note that data
transfer cannot take place until all bits of the
condition code are zero,
1-14
Assignment of Condition Code bits for input/
output is shown on Table 1-9,
TABLE 1-9. PSW CONDITION CODE BIT
ASSIGNMENTS I/O INSTRUCTIONS
PSW Bit Assignment Mnemonic
12 Device busy (BSY)
13 Examine status (EX)
14 End of medium (EOM)
15 Device unavailable (DU)
The Device Busy condition indicates that the
device is not available or ready for transfer
of data.
An Examine Status condition indicates that
the leftmost 4-bits of the device status byte
must be tested to fully determine the device
condition.
If, after a Sense Status or Acknowledge
Interrupt instruction, the examine bit of the
condition code is set, and the leftmost 4 bits
of the status byte are zero, an improper
device response has occurred or a power
down is in process. The data transfer is
aborted and the device is released. If the
examine bit is set after a Read or Write,
or Output Command Instruction, an im-
proper device response has occurred or a
power down is in process. A Sense Status
instruction should be executed and the left-
most 4 bits of the status byte tested to de-
termine the nature of the failure.
The End Of Medium condition is caused by
the presence of a code or indicator at the
end of a punched card, or paper or mag-
netic tape.
The Trarxrina FElnacrai
mn a in ln TE 1 1 1 1
16 1Jevice unavaliiaocic CORGITION indi cates
5
that the device is mechanically unable to
transfer data.
1.9.6 Standard Memory Bus interface
The optional SMBI provides a high speed data
path between a single external device and
the system core memory. Data is trans-
ferred 16 bits in parallel at up to the cycle
rate of the memory.
The SM BI operates on a cycle stealing
basis; that is, when the channel is ready
to transfer data, a memory service re-
quest is generated causing the memory to
service the SMBI at the conclusion of its
present cycle, The transfer takes place
autonomously, the Processor having no
awareness of the transfer, and with no ap-
parent interruption to normal processing.
1.9.7 Selector Channel
The optional Selector Channel provides
INTERDATA Digital Systems with the cap-
ability for block data transfer between an
I/O device and memory. Once initiated, the
transfer is performed automatically by the
Selector Channel. No further control by the
Processor is required. The Processor
initiates the transfer by specifying the de-
vice address, whether to read or write, the
starting address in memory, and the final
address in memory. The Processor is then
free to continue with its program while the
Selector Channel completes the transfer.
When the transfer is completed successfully,
or terminated due to a fault, the Processor
is notified via an interrupt.
1-15/16
2.1
CHAPTER 2
INSTRUCTION REPERTOIRE
INTRODUCTION
The instruction repertoire has been grouped
by function in this Chapter.
1.
2.
The use and
The name of the instruction.
Instruction word chart for every
format the instruction uses, in-
cluding: mnemonic operation code,
and first and second operand desig-
nations in the correct assembler
format. The format type is desig-
nated by [RR], [RX], or [RS]. An
instruction diagram with hexa-
decimal operation code and the
locations of all fields is also
provided.
A description of instruction
operation.
A diagrammatic representation of
instruction operation.
A chart illustrating the possible
variations of the condition code in
the Current Program Status Word
as a result of performing the in-
struction. A 1 indicates set, a
zero indicates reset. It is impor-
tant to note that any instruction
which changes the condition code
can change all four bits, The con-
ditions listed on the chart are only
those conditions which are meaning-
ful after a particular instruction.
Other bits may be changed, but
their condition is not meaningful.
À programming note to provide ad-
ditional pertinent or clarifying
information.
operation of each instruction is presented in
the following format:
ADD HALFWORD
1.
3
4
5
6
|
|
AHR R1, R2 [RR]
O 718 Пе 15
DA R1 | R2
AH RI, A(X2) [RX]
О 718 112 1516 31
4A R1 | X2 A
AHI R1, A(X2) [Rs]
O 718 Hil2 15116
CA R1 | X2 A
The 16-bit second operand is algebrai-
cally added to the General Register
specified by R1. The resulting sum is
contained in R1, the second operand is
unchanged.
(Rl) <—— (R1) + (R2)
(RL) <——— (R1) +[(A + (X2)]
(Rl) <—— (R1) + A + (X2)
[RR]
[RX]
[RS]
RESULTING CONDITION CODE:
12
13]14]15
C
V
— © © | ©
o-olr
Sum is zero.
Sum is less than zero.
Sum is greater than zero.
Arithmetic overflow.
Carry
PROGRAMMING NOTE
The ADD HALFWORD IMMEDIATE
(AHI) instruction produces a value which
is the algebraic sum of the address field
itself plus the content of a General
Register index (X2), plus the first oper-
and General Register (R1).
2-1
The symbols and abbreviations used in the
instruction diagrams are defined as follows:
()
[]
nz
A
R1
R2
M1
(0:7)
(8:15)
(16:31)
PSW
CC
Parentheses or Brackets. Read
as "the content of ...".
Arrow. Read as "is replaced
by ..." or "replaces ...".
The 16-bit halfword address
which is a part of the RX and
RS instructions.
The register address desig-
nated as the first operand.
The register address desig-
nated as the second operand
of an RR instruction.
The address of a General
Register the content of which
is used as an index value.
Mask of 4 bits specifying
Branch on Condition testing.
A bit grouping within a byte,
a halfword, or a fullword.
Read as "0 thru 7 inclusive",
"bits 8 thru l5inclusive", etc.
Program Status Word of 32
bits containing the Status,
Condition Code, and current
instruction address.
Condition Code of 4 bits con-
tained in the PSW.
Carry Bit contained in the
condition code (bit 12 of PSW).
Overflow Bit contained in the
condition code (bit 13 of PSW).
Greater Than bit contained in the
— ME TA
condition code (bit 14 of PSW).
Less Than bit contained in the
condition code (bit 15 of PSW).
Arithmetic operations - Add,
Subtract, Multiply, and Divide
respectively.
Logical comparison
2.2 LOAD AND STORE INSTRUCTIONS
The load and store instructions transfer in-
formation between core memory and the
General Registers or the Program Status
Word. Load and store operations are per-
formed on 8-bit bytes, 16-bit halfwords, or
32-bit fullwords.
2.2.1 Load Halfword 2.2.2 Store Halfword
LHR RI, R2 RR
0 718 ii2 15 [RR] ST RI, АК ie she [RX]
08 R1 | R2 3
40 R1 X2 A
LH RI, A(X2) [Rx]
0 718 112 15l6 31
48 RI | X2 A The 16-bit first operand is stored in the
7 core memory location specified by the
LHI R1, A(X2) [RS] second operand. The first operand is
0 718 иг 15/16 31 unchanged
C8 R1 X2 A
(Rl) — [A +(X2)] [RX]
The 16-bit second operand is loaded into the
General Register specified by R1. The
second operand is unchanged, Resulting Condition Code:
(Rl) <——— (R2) [RR] Unchanged.
(Rl) <——— [A + (X2)] [RX]
(В1) <— A + (X2) [RS]
Resulting Condition Code:
12113114115
Civ
Operand is zero.
Operand is less than zero.
Operand is greater than zero.
G
0
0
]
© — © |
Programming Note:
The LOAD HALFWORD IMMEDIATE (LHI)
instruction produces a value which is the
algebraic sum of the value of the address
field itself and the content of a General
Register index (X2).
2-3
2.2.3 Load Byte
LBR RI, R2 [RR]
O 718 Hie 15
93 R1 | R2
LB Ri, A(X2) [RX]
О 718 "112 15116 31
D3 R1 | x2 A
The 8-bit second operand is loaded into the
rightmost (least significant) 8 bits of the
General Register specified by R1. The left-
most (most significant) 8 bits of R1 are set
to zero. The second operand is unchanged.
[R1 (8:15)] <—— [R2 (8:15)] [RR]
[В1 (0:7)] =— Zero
[R1 (8:15)) =—[A + (X2)] [RX]
[R1 (0:7)) —— Zero
Resulting Condition Code:
Unchanged.
2-4
2.2.4 Store Byte
STBR RI, R2 [RR]
О 718 lie 15
92 R1 | R2
STB R1, A(X2) [RX]
O 718 112 15l6 3!
D2 RT | X2 A
The rightmost (least significant) 8-bit byte
of the first operand is stored in the General
Register or core memory location specified
by the second operand. The first operand
is unchanged.
[RR]
[RX]
[RL (8:15)]—[R2 (8:15)]
[R1 (8:15))— [A + (X2)]
Resulting Condition Code:
Unchanged.
Programming Note:
In the register-to-register (RR) form of this
instruction the leftmost byte, R2(0:7), is
unchanged.
2.2.5 Load Multiple
O 718 1912 15]i6
D1 К] X2 A
LM R1, A(X2) [RX]
3!
Sequential halfwords from memory are
loaded into successive General Registers,
beginning with the General Register speci-
fied by the R1 field. The first halfword is
defined by[(A+(X2)]. The operation is ter-
minated when R15 is loaded from memory.
Note that any number of sequential General
Registers can be loaded in this manner.
1. (R1)-<— [A + (X2)]
2. Rl: X'F'
if R1 = X'F', the instruction is
finished
if R1% X'F', then:
3. Rl-—Rl1+1
4, A<«— À + 2, return to equation 1
Resulting Condition Code:
Unchanged.
2.2.6 Store Multiple
STM R1, A(X2) [RX]
0 718 2 1S16 31
DO R1 | X2 A
Successive General Registers are stored
sequentially into memory, beginning with
the General Register specified by the R1
field. The first storage address is deter-
mined by[(A + (X2)]. The operation is
terminated when R15 is stored in memory.
Note that any number of sequential General
Registers can be transferred in this manner.
1. (R1)—[A + (X2)]
2. Rl: X'F'
if R1 = X'F', then instruction is
finished
if R1 # X'F', then:
3. Rl«<—RI+1
4 A+— A + 2, return to equation 1
Resulting Condition Code:
Unchanged.
2-5
2.2.7 Floating-Point Load
LER R1, R2 [RR]
O 718 12 15
28 К! R2
LE R1, A(X2) [RX]
О 718 12 ISO 31
68 К! X2
The floating-point second operand is normal-
ized and placed in the floating-point register
specified as the first operand. During nor-
malization, the fraction is shifted left hexa-
decimally (4 bits at a time) until the most
significant hexadecimal digit is not zero.
The exponent is decremented by one for
each hexadecimal shift required. Zeros
are shifted into the least significant hexa-
decimal digit of the fraction. The second
operand is unchanged.
If the normalization causes exponent under-
flow, the entire floating-point result is set
to zero and the overflow flag is set,
(RL) «<—— (R2) (RR)
(Rl) =— [A + (X2)] (RX)
Resulting Condition Code:
12113114115
CIVIGIL
010] Zero
011! Less than zero.
110] Greater than zero.
] Exponent underflow.
2.2.8 Floating Point Store
STE RI, A(X2)
O
7
8
[RX]
3i
60
R]
The floating-point first operand is placed
in the core memory location specified by
The first operand is unchanged.
A + (X2).
(R1) ——— [A + (X2)]
Resulting Condition Code:
Unchanged.
2.2.9 Load Program Status Word
LPSW A(X2) [RX]
0 718 12 15}I6 31
A 32-bit operand is loaded into the Current
Program Status Word. The operand is
unchanged.
[PSW (0:31)]<—— [A + (X2)] [RX]
Resulting Condition Code:
Determined by PSW loaded by the instruction.
2.2.10 Unchain
UNCH RI, R2 [RR]
О 7/8 2 15
98 ЕН
The UNCHAIN instruction is associated with
the optional High Speed Interrupt (See Appen-
dix 6). This instruction decrements the
High Speed Interrupt Pointer by eight and
loads the Program Status Word from the
push-down stack entry whose address is the
new value of the High Speed Interrupt Pointer.
High Speed Interrupt Pointer «—High Speed
Interrupt
Pointer - 8
[ PSW(0:31) ]J«— (High Speed Interrupt
Pointer)
Resulting Condition Code:
Determined by PSW loaded by the instruction.
2.2.11 Autoload
AL A(X2) [RX]
O 78 | te _1sl6 31
DS | | x2 A
The AUTOLOAD instruction loads memory
with a block of data from a byte oriented in-
put device (e.g. teletype, photo-electric
paper tape reader, magnetic tape, etc.).
The data is read a byte at a time and stored
in successive memory locations starting
with location X'80', The last byte is load-
ed into the memory location specified by
the address of the second operand, A + (X2).
Any blank or zero bytes that are input prior
to the first non zero byte are considered to
be leader and are therefore ignored; all other
zero bytes are stored as data. The input
device is specified by memory location X'78',
The device command code is specified by
memory location X'79', this is the normal
binary input device specification.
n=0
‚ (X'80')-—byte in
р 0+1
(Х'80' + п) <— Бубе #n
> 9 NH
. If A + (X2) = X'80' + n, instruction
is finished, otherwise return to
equation 2.
Resulting Condition Code:
12]13]14]15
Data transfer completed correctly.
Device Busy (BSY)
1 Examine Status (EX)
1 End of Medium (EOM)
1| Device Unavailable (DU)
— Ol O
<
©
o
2-8
2.3 FIXED POINT ARITHNETIC
INSTRUCTIONS
The Fixed Point Arithmetic instructions
provide for addition, subtraction, multipli-
cation and division of halfword operands.
Multiple precision arithmetic operations are
performed by the add/subtract with carry
halfword instructions.
2.3.1 Add Halfword
AHR R1, R2 [RR]
O 718 HI2 15
DA RI | R2
AH RI, A(X2) [RX]
O 718 2 15116 3)
AA R1 | x2 A
AHI RI, A(X2) [RS]
O 718 2 15116 3]
CA RI | x2 A
The 16-bit second operand is algebraically
added to the General Register specified by
R1, The resulting sum is contained in Rl,
the second operand is unchanged.
(R1) — (R1) + (R2) [RR]
(R1) < (R1) +[A + (X2)] [RX]
(R1) — (R1) +A + (2) [RS]
Resulting Condition Code:
12113114115
Civ
Sum is zero.
Sum is less than zero.
Sum is greater than zero.
] Arithmetic overflow.
] Carry
— O © | G)
o—-oIir
Programming Note:
The ADD HALFWORD IMMEDIA TE (AHI)
instruction produces a value which is the
algebraic sum of the address field itself plus
the content of a General Register index (X2),
plus the first operand General Register (R1).
2.3.2 Add With Carry Halfword
ACHR RI, R2 [RA]
о 718 112 15
DE RI | R2
ACH RI, A(X2) [RX]
О 718 __ИН2 15/16 31
4E RI | X2 A
The 16-bit second operand and the carry bit of
the condition code are algebraically added to
the General Register specified by R1. The re-
sulting sum is contained in R1, the second
operand is unchanged.
(R1) = (R1) + (R2) + C [RR]
(R1) < (R1) +[A + (X2)] + C[RX]
Resulting Condition Code:
12/1314 15
Civ
Sum is zero.
Sum is less than zero.
Sum is greater than zero.
1 Arithmetic overflow.
1 Carry
— O O ©
© — © | Г
Programming Note:
Multiple precision addition operations require
a carry forward from the least significant oper-
ands to the most significant. To accomplish
this, the locations containing the least signifi-
cant portions of the two operands are summed
using the Add Halfword instruction. A carry
forward, if it occurs, is retained in the carry
bit position of the condition code (PSW 12).
The locations containing the next least signifi-
cant portions of the two operands are then
summed using the Add With Carry Halfword
instruction. The carry bit contained in the
condition code (set from the previous addition)
participates in this sum; the carry bit position.
is then set to reflect the new result.
The Add With Carry Halfword instruction is
used on succeeding pairs of operands until the
most significant operands of the multiple pre-
cision words have been summed. The result-
ing condition code is valid for testing the
multiple precision word.
2.3.3 Subtract Halfword
SHR R1, R2 [RR]
О 718 12 15
08 RI | R2
SH R1, A(X2) [RX]
O 718 112 1516 31
4B RI | X2
SHI RI, A(X2) [RS]
O 7,8 _ hi2 1ISh6 31
CB RI | X2
2.3.4 Subtract With Carry Halfword
SCHR R1, R2 [RR]
0 718 12 15
OF RI | R2
SCH R1, A(X2) [RX]
О 718 112 15|16 3!
4F RI | X2
The 16-bit second operand with the carry
The 16-bit second operand is subtracted
from the General Register specified by RL,
The difference is contained in R1, the
second operand is unchanged.
(R1) — (R1) - (R2) [RR]
(RL) = (R1) - [А + (X2)] [RX]
(R1) < (R1) - A - (X2) [RS]
Resulting Condition Code:
1213114115
Civ
Difference is zero.
Difference is less than zero.
G
0
0
1
Oo — E
Difference is greater than zero.
1 Arithmetic overflow
1 Borrow
Programming Note:
The SUBTRACT HALFWORD IMMEDIATE
(SHI) instruction produces a value which is
the difference between the first operand
General Register (R1) less the sum of the
address field itself and the content of a
General Register index (X2).
2-10
(borrow) bit is subtracted from the General
Register specified by R1. The difference
is contained in R1, the second operand is
unchanged.
(R1) + (R1) - (R2) - C [RR]
(R1) < (RL) - [A + (X2))-C [RX]
Resulting Condition Code:
12113114
IS
Civ
G
0
0
1
o—olr
Difference is zero.
Difference is less than zero.
Difference is greater than zero.
Arithmetic overflow.
Borrow
Programming Note:
See Add with Carry Halfword.
2.3.5 Multiply Halfword
MHR R1, R2 [RR]
0 718 112 15
OC RI | R2
MH R1, A(X2) [RX]
0 7/8 Пг 15Sh6 31
AC RI | X2
2.3.6 Divide Halfword
DHR RI, R2 [RR]
0 718 M2 15
0D RI | R2
DH R1, A(X2) [RX]
О 718 2 15/16 31
4D RI | X2
The 16-bit second operand is multiplied by
the contents of the General Register specified
by R1 +1. The first operand, the contents
of the General Register specified by R1, must
specify an even numbered register. The re-
sulting 32-bit product is contained in R1 and
R1 +1, an even-odd pair; the second operand
is unchanged. The sign of the product is deter-
mined by the rules of algebra.
[RR]
(R1, R1 +1)<—— (R1 +1)*(A + (X2)] [RX]
(R1, R1 +1)<——(R1 +1)*(R2)
Resulting Condition Code:
Unchanged.
Programming Note:
After multiplication, the most significant 15
bits with sign are contained in R1. The least
significant 16 bits are contained in RL +1.
The 16-bit second operand is divided into the
32-bit dividend contained in the General Reg-
ister specified by R1 and R1 +1. The first
operand, Rl, must specify an even numbered
register. The resulting 15-bit quotient with
sign is contained in R1 + 1; a 15-bit re-
mainder with sign is contained in R1, the
second operand is unchanged. The sign of
the result is determined by the rules of
algebra; the sign of the remainder is the same
as the sign of the dividend.
(В1 +1) < — — (R1, RI +1)/(R2)
(В1) —
[RR]
Remainder
(R1 + 1) «=——— (R1, R1 +1)/[A + (X2)[RX]
(R1) = Remainder
Resulting Condition Code:
Unchanged.
Programming Note:
A quotient which cannot be expressed in 15
bits plus sign will cause a Divide Fault inter-
rupt if enabled by bit 3 of the Program Status
Word. The operands will remain unchanged.
2-11
2.4 FLOATING-POINT ARITHMETIC
INSTRUCTIONS
The Floating-Point Arithmetic instructions
provide for addition, subtraction, multiplica-
tion, and division of floating-point operands.
These instructions are normally used to per-
form calculations on operands with a wide
range of magnitude, and yield results which
are scaled to preserve precision.
2-12
2.4.1 Floating-Point Add
AER RI, R2 [RR]
O 7/8 HZ 15
2A RI | R2
AE R1, A(X2) [RX]
O 718 H12 15116 31
6A Р1 | x2 А
The exponents of the two operands are com-
pared. If the exponents differ, the fraction
with the smaller exponent is right shifted
hexadecimally (4 bits at a time) and its ex-
ponent is incremented by one for each hexa-
decimal shift until the two exponents agree,
The fractions are then algebraically added
andifa carry results, the exponent of the
sum is incremented by one and the fraction
(result) is shifted right one hexadecimal
position (4 bits). The carry is shifted into
the most significant hexadecimal digit of the
fraction. If an exponent overflow results,
the exponent and fraction of the result are
set to all ones and the Overflow flag is set.
The sign of the result is not affected by the
overflow.
If no carry results from the addition of frac-
tions, the sum is normalized. During nor-
malization, the fraction is shifted left hexa-
decimally (4 bits at a time) until the most
significant hexadecimal digit is not zero.
The exponent is decremented by one for
each hexadecimal shift required. Zeros
are shifted into the least significant hexa-
decimal digit of the fraction.
If the normalization causes exponent under-
ео £1 a dass жуть “wm О + о
How, tne sign, ex
and iracti
+
nen
©
pm)
cm ara cot tn 7ov
MM LALLE CL 4 и RAW Ww WS Ld Nr A
set. If a zero sum is generated from adding
two equal magnitudes with unlike signs, the
entire floating-point result is zeroed,
1
ha Ove
- “SY Wr
wil
©
e
an
LA
(a
(R1)<—— (R1) + (R2) (RR)
(В1) «— —— (В1) +[A + (X2)] (RX)
2.4.1
Floating-Point Add (Continued)
Resulting Condition Code:
12
13114
IS
C
V
Oo — Of
Sum is zero.
Sum is less than zero.
Sum is greater than zero.
Exponent overflow or underflow.
2.4.2 Floating-Point Subtract
SER RI, R2 [RR]
0 718 12 15
2B RI | R2
SE R, A(X2) [RX]
O 718 _ 1112 15116 31
6B RT | X2 A
The exponents of the two operands are com-
pared. If the exponents differ, the fraction
with the smaller exponent is right shifted
hexadecimally (4 bits at a time) and its ex-
ponent is incremented by one for each hexa-
decimal shift until the two exponents agree.
The fractions are then algebraically subtrac-
ted. If a carry results, the exponent of the
difference is incremented by one and the frac-
tion (result) is shifted right one hexadecimal
position (4 bits). The carry is shifted into
the most significant hexadecimal digit of the
fraction. If an exponent overflow occurs,
the exponent and fraction of the result are
set to all ones and the Overflow flag is set.
The sign of the result is not affected by the
overflow.
If no carry results from the subtraction of
fractions, the difference is normalized by
shifting the fraction left hexadecimally (4
bits at a time) until the most significant
hexadecimal digit is not zero. The expon-
ent is decremented by one for each hexa-
decimal shift required. Zeros are shifted
into the least significant hexadecimal digit
of the fraction.
If the normalization causes exponent under-
flow, the entire floating-point result is set
to zero and the Overflow flag is set.
(R1)<—— (R1) - (R2) (RR)
(Rl)=—— (R1) -[A + (X2)] (RX)
Resulting Condition Code:
m2 1314115
CIVIGIL
010} Difference is zero.
O}1| Difference is less than zero.
110] Difference is greater than zero.
] Exponent overflow or underflow.
2-13
2.4.3 Floating-Point Multiply
MER R1, R2 [RR]
O 718 Hite 15
2C RI | R2
ME R1, A(X2) [RX]
О 718 Hie 1516 31
6C R1 | x2 A
The exponents of the two operands are ad-
ded to produce the exponent of the result.
The resultant exponent is readjusted to ex-
cess 64 notation. If an exponent overflow
occurs, the exponent and fraction of the
product are set to ones and the Overflow
flag is set. The sign of the product is de-
termined by the rules of algebra. If an
exponent underflow occurs, the entire
floating-point result is set to zero and the
Overflow flag is set.
If an exponent overflow or underflow does
not occur, the multiplication takes place.
If the product is zero, the entire floating-
point result is zero. If the result is not
zero, normalization may occur. During
normalization, the fraction is shifted left
hexadecimally (4 bits at a time) until the
most significant hexadecimal digit is not
zero. The exponent of the result is decre-
mented by one for each hexadecimal shift
required. After normalization, the pro-
duct is rounded to 24 bits.
If normalization causes the exponent to un-
derflow, the entire floating point result is
set to zero and the Overflow flag is set.
(В1) + — (R1)*(R2) (RR)
(R1) <—— (R1)*[A + (X2)] (RX)
Resulting Condition Code:
N
a
+
a
Product is zero.
Product is less than zero.
— D ©O | ©)
© — © |r
Product is greater than zero.
] Exponent overflow or underflow.
2-14
2.4.4 Floating-Point Divide
DER RI, R2 [RR]
O 718 lle 15
2D RI | R2
DE RI, A(X2) [RX]
O 718 iz 15116 31
0 | rR1 | x2 A
The exponents of the two operands are sub-
tracted to produce the exponent of the result.
The resultant exponent is readjusted to ex-
cess 64 notation. If an exponent overflow
occurs, the exponent and fraction of the
quotient are set to all ones and the Overflow
flag is set. The sign of the quotient is de-
termined by the rules of algebra. If an ex-
ponent underflow occurs, the entire floating-
point result is set to zero and the Overflow
flag is set. If the divisor (the second oper-
and) is zero, a floating-point divide fault
interrupt is caused if enabled by bit 5 of the
Program Status Word, and the operands are
unchanged.
If the exponent overflow or underflow does
not occur, and if the divisor is not zero,
the second operand is divided into the first’
operand . Division continues until the quo-
tient is normalized, adjusting the exponent
for each additional division required. If an
exponent underflow occurs, the entire float-
ing -point result is set to zero and the Over-
flow flag is set.
No remainder is returned to the user. The
quotient is rounded to compensate for the loss
of the remainder.
(R1)<——— (R1)/(R2) (RR)
(R1)
vee
Resulting Condition Code:
1234] 15
CIVIG|L
010} Quotient is zero.
0171| Quotient is less than zero
1{0| Quotient is greater than zero
] Exponent overflow or underflow
2.5 LOGICAL INSTRUCTIONS
The Logical instructions operate bit by bit
on the first operand and its corresponding
bit in the second operand. These operations
provide for masking selected portions of a
halfword, or comparison for relative
magnitude.
2.5.
1 AND Halfword
NHR R1, R2 [RR]
O 718 lN2 15
04 R1 | R2
NH RI, A(X2) [Rx]
O 718 l:12 15116 31
44 R1 | X2
NHI RI, A(X2) [RS]
О 718 112 15/16 31
C4 RI | X2
The logical product of the 16-bit second
operand and the content of the General Reg-
ister specified by R1 replaces the content of
R1. The 16-bit product is formed on a bit-
by -bit basis.
(R1) — (R1) AND (R2) [RR]
(R1) — (R1) AND [A + (X2)] [RX]
(R1) — (R1) AND A + (X2) [RS]
Resulting Condition Code:
12
13114115
C
V
Logical product is zero.
\
(Logical product is not zero.
— © © | ©
© — © |
Programming Note:
The AND HALFWORD IMMEDIATE (NHI) in-
struction produces a value which is the logi-
cal product of the address field itself plus
the content of a General Register index (X2)
with the first operand General Register (R1).
The truth table for the AND function is:
0 AND 0 =0
0 AND 1 =0
1 AND 0 =0
1 AND 1 =1
2-15
2.5.2 OR Halfword
OHR R1, R2 [RR]
O 718 12 15
06 RI | R2
OH RI, A(X2) [RX]
О 718 2 15416 31
46 R1 | X2 A
-
OHI RI, A(X2) [RS]
O 718 112 15116 31
C6 RI | X2 A
The logical sum of the 16-bit second operand
and the content of the General Register spec-
ified by R1 replaces the content of R1. The
16-bit sum is formed on a bit-by -bit basis.
(R1) — (R1) OR (R2) [RR]
(R1) < (R1) OR [A + (X2)] [RX]
(В1) < (R1) OR A + (X2) [Rs]
Resulting Condition Code:
1213/14/15
Civ
Logical sum is zero.
\
f Logical sum is not zero.
— © © | ©)
© — © |
Programming Note:
The OR HALFWORD IMMEDIATE (OHI) in-
struction produces a value which is the logical
sum of the address field itself plus the content
of a General Register index (X2) with the first
operand General Register (R1).
The truth table for the OR function is:
2.53 Exclusive OR Halfword
XHR RI, R2 [RR]
О 7/8 12 15
07 R1 | R2
XH R1, A(X2) [RX]
0 7/8 11942 1516 31
47 RI | X2 A
XHI R1, A(X2) [RS]
O 718 12 15116 31
C7 RI | X2 A
The Logical difference of the 16-bit second
operand and the General Register specified
by R1 replaces the content of R1. The 16-bit
difference is formed on a bit-by-bit basis.
(R1) < (R1) XOR (R2) [RR]
(В1) < (R1) XOR[A + (X2)] [RX]
(R1) = (R1) XOR A + (X2) [RS]
Resulting Condition Code:
12113114715
CIVIGIL
010] Logical difference is zero.
7 ; } Logical difference is not zero.
Programming Note:
The EXCLUSIVE OR HALFWORD IMME -
DIATE (XHI) instruction produces a value
which is the logical difference of the address
field itself plus the content of the General
Register index (X2) with the first operand
General Register (R1).
The truth table for the EXCLUSIVE OR func-
tion is:
0 XOR 0
0 XOR 1
1 XOR 0
Il
HH O
2-16
0 OR 0=0
0 OR 1=1
1 OR 9=1
1 OR 1=1
1 XOR 1 =0
2.5.4 Compare Logical Halfword
CLHR RI, R2 [RR]
О 718 112 15
05 R1 | R2
CLH RI, A(X2) [RX]
0 718 11112 15116 31
45 81 | X2 А
CLHI R1, A(X2) [Rs]
О 718 12 _15!16 31
C5 RI | X2 A
The first operand specified by R1 is com-
pared logically to the 16-bit second operand.
The result is indicated by the setting of the
condition code (PSW 12:15); both operands
remain unchanged.
(CC) = (R1) : (R2) [RR]
(СС) < (R1) : LA + (X2)] [RX]
(CC) = (R1) : A + (X2) [RS]
Resulting Condition Code:
12/13/1415
CIVIGIL
010 First operand equal to second operand.
7 9 First operand not equal to second operand.
] First operand less than second operand.
0 First operand equal to or greater than
second operand.
Programming Note:
The logical comparison is performed by sub-
tracting the second operand from the first
operand. The result is in the condition code
setting, the operands are not modified.
The COMPARE LOGICAL HALFWORD IM-
MEDIATE (CLHI) instruction produces a
value which is the logical comparison of the
address field itself plus the content of a
General Register index (X2) with the first
operand General Register (R1).
2.5.5 Floating-Point Compare
CER RI, R2 [RA]
O 718 lie 15
29 RI | R2
CE RI, A(X2) — [RX]
О 718 112 15116 31
69 RI | X2 A
The first operand is compared to the second
operand. Comparison is algebraic, taking
into account the sign, fraction, and exponent
of each number. The result is indicated by
the setting of the condition code (PSW12:15).
Both operands remain unchanged.
(CC)<—— (R1):(R2) (RR)
(CC)<—— (R1):[A + (X2)] (RX)
Resulting Condition Code:
1213/1415
CIVIGIL
0(0| First operand equals second operand
O11] First operand is less than the second operand
110 First operand is greater than the second operand
0 First operand is less than or equal to the
second operand
0 First operand is greater than or equal to the
second operand
] First operand is less than the second operand
2-17
2.6 SHIFT INSTRUCTIONS
The Shift instructions provide for arithme-
tic and logical manipulation of information
contained in the General Registers. Bits
shifted out of the high or low order end of a
General Register are passed through the
carry bit position of the condition code
(PSW 12). After execution of a shift in-
struction, the last bit which was shifted out
is contained in the carry position.
The number of bit positions shifted is speci-
fied by the sum of the value A with the con-
tent of the General Register index (X2).
Note that the address field of the instruction
2-18
(A) is not interpreted as a memory location
address but as an unsigned integer. The
value of A may be from 0 to FFFF.
A shift of zero positions causes the condi-
tion code to be set properly with no altera-
tion to the information contained in the
General Register.
A shift specification of more than 15 bit posi-
tions will not give meaningful results, since
only the four least significant bits of the
sum of A plus (X2) are used to specify the
number of positions to be shifted.
2.6.1 Shift Left Halfword Arithmetic
SLHA R1, A(X2) [RS]
O 718 11112 15/16 31
CF R1 X2 A
The content of the first operand (R1) is
shifted left the number of bit positions
specified by the second operand. Bits 1
through 15 are shifted, the sign bit is un-
changed. High order bits shifted out of
position 1 are shifted thru the carry bit of
the PSW and then lost. Zeros are shifted
into position 15.
Result is zero.
Result is less than zero.
Result is greater than zero.
0 Last bit that was shifted out was a zero.
] Last bit that was shifted out was a one.
— 6061
o—-olr
2.6.2 Shift Right Halfword Arithmetic
SRHA R1, A(X2) [RS]
O 718 112 15116 31
X2 À
CE К]
The content of the first operand (R1) is
shifted right the number of bit positions
specified by the second operand. Bits 1
through 15 are shifted, the sign bit is un-
changed. Low order bits shifted out of
position 15 are shifted thru the carry bit of
the PSW and then lost. The sign bit is pro-
pogated right into position 1.
1211314115
Result is zero.
Result is less than zero.
Result is greater than zero.
0 Last bit that was shifted out was a zero.
] Last bit that was shifted out was a one.
— © © | ©)
© — © |r
2-19
2.6.3 Shift Left Halfword Logical
SLHL RI, A(X2) [RS]
O 718 1:12 15116 31
CD К] X2 À
The content of the first operand (R1) is
shifted left the number of positions specified
by the second operand. All 16 bits of the
halfword are shifted. High order bits shifted
out of position 0 are shifted thru the carry
bit of the PSW and then lost. Zeros are
shifted into position 15.
(R1)
4
(C)
Resulting Condition Code:
12]13]14}15
Result is zero.
Result is less than zero.
Result is greater than zero.
0 Last bit that was shifted out was a zero.
1 Last bit that was shifted out was a one.
-l O O ©
oO —=O |r
2-20
2.6.4 Shift Right Halfword Logical
SRHL RI, A(X2) [RS]
O 718 Hil2 15116 31
CC R1 X2 À
The content of the first operand (R1) is
shifted right the number of bit positions
specified by the second operand. All 16 bits
of the halfword are shifted. Low order bits
shifted out of position 15 are shifted thru the
carry bit of the PSW and then lost. Zeros
are shifted into position zero.
(R1)
——
Y
(C)
Resulting Condition Code:
Result is zero.
Result is less than zero.
Result is greater than zero.
Last bit that was shifted out was a zero.
1 Last bit that was shifted out was a one.
— © © | ©
© — © |r
2.7 BRANCH INSTRUCTIONS
Branch instructions are programmed decisions
providing entry to subprograms, as well as
testing the result of arithmetic logical, or
indexing operations.
Many Processor operations result in setting
of the Condition Code in the Program Status
Word (PSW (12:15)). The Branch on Condition
instructions implement the testing of the
Condition Code through use of a mask field
contained in the instruction itself (M1 field).
The 4-bit M1 field is not a register address,
but rather an image of the condition code to
be tested.
2-21
27.1 Branch on True Condition”
BTCR MI, R2 [RR]
О 7/8 12 15
02 MI | R2
BTC M1, A(X2) [Rx]
О 718 12 ISE 31
42 MI | X2 A
The condition code field of the Program Status
Word [PSW (12:15)] is tested for the conditions
specified by the mask field (M1). If any of
the conditions tested are found to be true, a
Branch is executed to the 16-bit address
specified by the second operand. If none of
the conditions tested are found to be true the
next sequential instruction is executed.
Tested Condition True:
[PSW (16:31) ]-<— (R2) [RR]
Tested Condition Not True:
[PSW (16:31)]<——— [PSW (16:31) ] + 2
Tested Condition True:
[PSW (16:31) ]=— A + (X2) [RX]
Tested Condition Not true:
[PSW (16:31)]<—— [PSW (16:31)] + 4
Programming Note:
A logical AND is performed between each bit
in the condition code and its corresponding
bit in the M1 field. If any resultant bit is a
one, the branch will occur. The condition
code (PSW (12:15)) is not changed.
Example: (Branch occurs)
CC 1010
AND
M1 1100
1000 BTC result: Branchif
bit remains after AND,
2.7.2 Branch on False Condition*
BFCR MI, R2 [RR]
0 718 112 15
93 MI | R2
BFC M1, A(X2) [RX]
О 718 lie 1516 3!
43 MI | X2 A
The condition code field of the Program Status
Word [PSW (12:15)] is tested for the condition:
specified by the mask field (M1). If all
conditions tested are found to be false, a
Branch is executed to the 16-bit address
specified by the second operand. If any of
the conditions tested are found to be true,
the next sequential instruction is executed.
Tested Condition False:
[PSW (16:31)] < — (В2) [RR]
Tested Condition Not false:
[PSW (16:31) ] «— —— [(PSW (16:31) ]+2
Tested Condition False:
[PSW (16:31)]-<——— A + (X2) [RX]
Tested Condition Not false:
[PSW (16:31)]<——— [PSW (16:31)] +4
Programming Note:
A logical AND is performed between each bit
in the condition code and its corresponding
bit in the M1 field. If any resultant bit is a
one, the branch will not occur. The condi-
tion code (PSW (12:15)) is not changed.
Example: (Branch does not occur)
CC 1010
AND
M1 1100
BFC result: Branch
if no bit remains after
AND
1000
*Refer to Section 2. 8 for information on Entended Mnemonic Codes for conditional
branch instructions.
2-22
2.7.3 Branch Unconditional
BR R2 [RR]
О 7/8 12 15
03 0 R2
В A(X2) [RX]
О 718 112 1516 3!
43 9 | X? A
The 16-bit address specified by the second
operand is transferred to the instruction ad-
dress field of the Program Status Word
(PSW (16:31)). The next instruction executed
will be accessed from the location specified
by the new instruction address.
[PSW (16:31) ]<—— (R2) — [RR]
[PSW (16:31)]-«— A + (X2) [RX]
Programming Note:
The Branch Unconditional instruction is a
form of the Branch on False Condition in-
struction where no condition is specified for
testing.
2.7.4 No Operation
NOPR R2 [RR]
О 718 12 15
02 0 | R2
NOP A(X2) [RX]
O 718 __ lille 1516 31
42 g | x A
The second operand is ignored and therefore
may assume any value. The (M1) field is
zero, The instruction address field of the
Program Status Word (PSW (16:31) ) is
incremented and the next sequential instruc-
tion is accessed for execution.
[PSW (16:31) J<e— LPSW (16:31)]+2 [RR]
[PSW (16:31) - — [PSW (16:31)] + 4 [RX]
Programming Note:
The No Operation instruction is a form of the
Branch on True Condition instruction where
no condition is specified for testing. The No
Operation instruction is useful to replace 16
or 32 bits of erroneous or redundant coding
or to reserve memory locations within a
program for anticipated future coding. This
instruction may also be employed as an
inactive instruction in timing sequences.
2-23
2.7.5 Branch on Index High
BXH R1, A(X2) [RS]
О 718 H:2 15116 31
co R1 X2 À
Prior to execution of this instruction, the
General Register specified by the first oper-
and (R1) must contain a 16-bit final address,
R1 +1 must contain a 16-bit negative
value, and R1 + 2 must contain a 16-bit
comparand value (limit or starting address).
All values may be signed.
Execution of this instruction causes the final
address (R1) to be decreased by adding
(R1 +1) and logically compared to the limit
(R1 + 2). As long as the count (R1) is greater
than the limit (R1 + 2), the 16-bit address
specified by the second operand is trans-
ferred to the instruction address field of the
Program Status Word [PSW (16:31)]. The
next instruction executed will be accessed
from the location specified by the new
instruction address.
When the count is not greater than the index
limit, the instruction following Branch on
Index High will be executed.
(R1) — (R1) + (R1 +1) [RS]
(R1) : (R1 + 2)
if (В1) > (В1 + 2)
[PSW (16:31) ]+—— A + (X2)
if (R1) < (R1 +2);
[PSW (16:31) J+— [PSW (16:31)] + 4
Programming Note:
General Register 13 is the maximum speci-
fication for the R1 field, since a block of
three consecutive General Registers is re-
quired.
A logical comparison treats all 16-bits of
the halfword as magnitude bits.
2-24
2.7.6 Branch on Index Low or Equal
BXLE RI, A(X2) [RS]
O 718 12. 15116 31
CT К] X2 A
Prior to execution of this instruction, the
General Register specified by the first oper-
and (R1) must contain a 16-bit count value
(starting address), R1 +1 must contain a
16-bit increment value, and R1 + 2 must
contain a 16-bit comparand (limit or final
address). All values may be signed.
Execution of this instruction causes the count
(R1) to be incremented by (R1 + 1) and logi-
cally compared to the index limit. As long
as the count (R1) is equal to or less than the
limit (R1 + 2), the 16-bit address specified
by the second operand is transferred to the
instruction address field of the Program
Status Word [PSW (16:31)]. The next in-
struction executed will be accessed from the
location specified by the new instruction
address. When the starting address is greater
than the limit, the instruction following Branch
on Index Low will be executed.
(В1) - (R1) + (R1 +1) [RS]
(R1) : (R1 + 2)
if (В1) < (В1 + 2)
[PSW (16:31) | «— A + (X2)
if (В1) > (В1 + 2) ;
[PSW (16:31)]<— [PSW (16:31)] + 4
Programming Note:
(lonoral Ra
1 oictar 12 ie tha mavimim ea
WA Nu” LL A LAL AV вый Ни а. A. A le Dad Ww Le)
fication for the R1 field since a block of
three consecutive General Registers is
required.
A logical comparison treats all 16-bits of the
halfword as magnitude bits.
2.7.7 Branch and Link
BALR RI, R2 [RR]
O 78 hi2 15
01 R1 | R2
BAL R1, A(X2) [RX]
О #8 2 516 3!
41 R1 | X2 A
The Branch and Link instruction is executed
in two phases. The instruction address field
of the Program Status Word [PSW (16:31) ]
is incremented and transferred to the General
Register specified by the first operand. (R1).
Then the second operand is loaded into the
instruction address field [PSW (16:31)]. The
next instruction executed will be accessed
from the location specified by the new
instruction address.
(R1) <—— [PSW (16:31)] + 2[RR]
[PSW (16:31)] «—— (В?)
(R1) <—— [ PSW (16:31) + 4(RX]
[PSW (16:31) ] —— A + (X2)
Programming Note:
The Branch and Link instruction is required
for entry to sub--programs. It differs from
the Branch Unconditional instruction in that
the current instruction address field is
preserved in a specified General Register
to be used as the sub-program exit address.
Exit from the sub-program is effected by a
Branch Unconditional instruction through the
General Register in which the exit address
has been maintained.
2-25
2.8 EXTENDED MNEMONIC CODES FOR
BRANCH ON CONDITION
To simplify the coding of conditional branch instruction set, but are translated by the
instructions for the programmer, an ex- assembler into the proper operation code
tended set of mnemonic codes has been and M1 field combinations.
provided in the Symbolic Assembler, The
most frequently used branch instructions
have been provided with mnemonics which
are not a part of the machine language
The extended mnemonic codes are for in-
structions in the RX format.
2-26
2.8.1 Branch on Zero
BZ A(X2) [RX]
0 718 1112 15/16 31
43 3 X2 À
The Condition Code field of the Program
Status Word [PSW (12:15)] is tested for the
zero condition. If this condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the con-
dition is not met, the next sequential
instruction is executed.
CC = Zero; [PSW (16:31)]<- A + (X2) [RX]
CC # Zero; [PSW (16:31) — [PSW (16:31)] + 4
Condition Code Tested:
1211314115
CIVIGIL
010 Branch
011 No B h
110 o Branc
Valid After:
LH, LE
AH, ACH, SH, SCH, AE, SE, ME, DE
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2.8.2 Branch on Not Zero
BNZ A(X2) [RX]
O 718 __ 112 1SIE6 31
42 3 X2 À
The Condition Code field of the Program
Status Word [PSW (12:15)] is tested for the
not zero condition. If this condition is met,
a Branch is executed to the 16-bit address
specified by the second operand. If the con-
dition is not met, the next sequential
instruction is executed.
CC # Zero; [PSW (16:31)]+ A + (X2) [RX]
CC = Zero; [PSW (16:31) ]J-<- [PSW (16:31)] + 4
Condition Code Tested:
1213114115
CIVIGIL
0/0 No branch
o } Branch
Valid After:
LH, LE
AH, ACH, SH, SCH, AE, SE, ME, DE
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2-27
2.8.3 Branch on Plus
BP A(X2) [RX]
0 718 12 1516 31
42 2 X2 À
The Condition Code field of the Program
Status Word [PSW (12:15)] is tested for the
plus condition. If this condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
CC = Plus; [PSW (16:31) ]<— A+(X2) [RX]
CC # Plus; [PSW (16:31)]<—[PSW (16:31)] + 4
Condition Code Tested:
12113114/15
Civ
} No branch
Branch
— D © | ©
© == Ol
Valid After:
LH, LE
AH, ACH, SH, SCH, AE, SE, ME, DE
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2-28
2.8.4 Branch on Not Plus
BNP A(X2) [RX]
O 718 #112 15116 31
43 2 X2 À
The Condition Code field of the Program
Status Word [PSW (12:15)] is tested for the
not plus condition. If this condition is met,
a Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
CC # Plus;[PSW (16:31)]<+ A+(X2) [RX]
CC = Plus; [PSW (16:31)]-<—[PSW (16:31)] + 4
Condition Code Tested:
12113114115
CIVIGIL
9 | } Branch
10 | No Branch
Valid After:
LH, LE
AH, ACH, SH, SCH, AE, SE, ME, DE
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2.8.5 Branch on Minus
BM A(X2) [RX]
О 718 1112 15116 31
42 ] X2 A
The condition code field of the Program
Status Word [PSW (12:15) ] is tested for the
minus condition, If the condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
CC = Minus; [PSW (16:31)]<— A+ (X2) [RX]
CC # Minus; [PSW (16:31)]<— PSW (16:31) + 4
Condition Code Tested:
1213114115
CIVIGIL
010 No branch
071 Branch
1/0 No branch
Valid After:
LH, LE
AH, ACH, SH, SCH, AE, SE, ME, DE
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2.8.6 Branch on Not Minus
BNM A(X2) [RX]
О 7/8 1112 15116 31
43 ] X2 À
The condition code field of the Program
Status Word [PSW (12:15)] is tested for the
not minus condition. If the condition is met,
a Branch is executed to the 16-bit address
specified by the second operand, If the
condition is not met, the next sequential
instruction is executed.
CC # Minus;[PSW (16:31)]+—A+(X2) [RX]
CC = Minus; [PSW (16:31)]-—[PSW (16:31)]+ 4
Condition Code Tested:
12113114115
CIV
Branch
No branch
Branch
= с © | ©)
© — © | |
Valid After:
LH, LE
AH, ACH, SH, SCH, AE, SE, ME, DE
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2-29
2.8.7 Branch on Carry
BC A(X2) [RX]
о 718 1112 15116 3!
42 8 X2 A
The condition code field of the Program
Status Word [ PSW (12:15) ] is tested for the
carry condition, If the condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
CC = Carry;[PSW (16:31)]<— A+(X2) [RX]
CC # Carry; [PSW (16:31) ]+—[PSW (16:31)]+ 4
Condition Code Tested:
12113114115
CIVIGIL
1 Branch
0 No Branch
Valid After:
AH, ACH, SH, SCH
SLHA, SRHA, SLHL, SRHL
2-30
2.8.8 Branch on Overflow
BO A(X2) [RX]
0 718 12 1516 31
42 4 X2 À
The condition code field of the Program
Status Word [PSW (12:15) ] is tested for the
overflow condition. If the condition is met,
a Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
CC =Overflow:[PSW (16:31)}+— A +(X2) [RX]
CC £Overflow:[ PSW (16:31)]<—[PSW (16:31)]+ 4
Condition Code Tested:
12113114115
CIVIGIL
V
1 Branch
0 No Branch
Valid After:
AH, ACH, SH, SCH, AE, SE, ME, DE, LE
2.8.9 Branch on Low
BL A(X2) [RX]
O 718 112 15]i6 31
42 8 X2 A
The condition code field of the Program
Status Word [PSW (12:15)] is tested for the
low condition. If the condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
CC = Low; [PSW (16:31) }+ A + (X2) [RX]
CC # Low; [PSW (16:31)]—-[PSW (16:31)] + 4
Condition Code Tested:
12113114115
CIVIGIL
] Branch
0 No branch
Valid After:
CLH, CE
2.8.10 Branch on Not Low
BNL A(X2) [RX]
О 718 г I5]16 31
43 8 X2 À
The condition code field of the Program Status
Word [PSW (12:15)] is tested for the not low
condition, If the condition is met, a Branch
is executed to the 16-bit address specified
by the second operand. If the condition is
not met, the next sequential instruction is
executed.
CC = Now low; [PSW (16:31) }+— A + (X2) [RX]
CC # Not low;[ PSW (16:31) }+—[PSW (16:31 )]+ 4
Condition Code Tested:
12713114115
VIGIL
Branch
No Branch
- OO
Valid After:
CLH, CE
2-31
2.8.11 Branch on Equal
BE A(X2) [RX]
O 7/8 11112 15|16 31
43 3 X2 A
The condition code field of the Program
Status Word [ PSW (12:15) ] is tested for the
equal condition. If the condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
CC = Equal; [PSW (16:31) =— A + (X2) [RX]
CC # Equal; [PSW (16:31) -— [PSW (16:31)]+4
Condition Code Tested:
12113114115
CIVIGIL
010 Branch
011 No Branch
110
Valid After:
CLH, CE
2-32
2.8.12 Branch on Not Equal
BNE A(X2) [RX]
O 718 Hil2 15116 3!
42 3 X2 A
The condition code field of the Program Status
Word [PSW (12:15)] is tested for the not equal
condition. If the condition is met, a Branch
is executed to the 16-bit address specified by
the second operand. If the condition is not
met, the next sequential instruction is
executed.
CC = Not equal; [PSW (16:31)]<— А + (X2) [RX]
CC # Not equal; [PSW (16:31)]——[(PSW (16:31 jl+ 4
Condition Code Tested:
12113114115
Civ
No Branch
} Branch
— © OO | ©
O — © rr
Valid After:
CLH, CE
2.9 DEVICE INTERRUPT AND CONTROL
INSTRUCTIONS
The Interrupt and Control instructions pro-
vide for Processor interrogation and control
of peripheral devices in the system.
2-33
2.9.1
Acknowledge Interrupt
AIR RI, R2 [RR]
О 718 HI 2 15
OF RI | R2
Al R1, A(X2) [RX]
0 718 Ille 15116 31
DF RI | X2
2.9.2 Sense Status
SSR R1, R2 [RR]
0 718 112 15
9D RT | R2
SS RI, A(X2) [RX]
O 718 112 15/16 31
DD RT | x2
The address of the interrupting device re-
places the content of the 16-bit General
Register specified by the first operand (R1).
The 8-bit device status byte replaces the
content of the location specified by the
second operand. The Condition Code is set
equal to the right-most four bits of the device
status byte. The device interrupt condition
is then cleared.
[R1 (8:15) ]+—— Device address [RR]
[В1 (0:7)]-<——— Zero
[R2 (8:15)]<——— Status byte
[R2 (0:7)]<——— Zero
[PSW (12:15) }— Status byte (4:7)
[R1 (8:15) }+—— Device number [RX]
[R1 (0:7) }+——— Zero
[A +(X2)]-<——— Status byte
[PSW (12:15)]«— Status byte (4:7)
Resulting Condition Code:
12113114115
CIVIGIL
1101010| Device busy (BSY)
011/0{0| Examine status (EX)
0{0{1/0| End of medium (EOM)
0|0/0|1| Device unavailable (DU)
2-34
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The device is addressed and the 8-
bit device status byte replaces the content of
the location specified by the second operand.
The Condition Code is set equal to the right-
most four bits of the device status byte.
The first operand is unchanged.
[R2 (8:15))<——— Status byte [RR]
[R2 (0:7)]-<——— Zero
[PSW (12:15) }+— Status byte (4:7)
[A + (X2)]-<——— Status byte [RX]
[PSW (12:15) }—— Status byte (4:7)
Resulting Condition Code:
1211314115
CIVIGIL
1/0 [010 | Device busy (BSY)
O 11 [1010 | Examine Status (EX)
O0 10 11/0 | End of Medium (ECM)
О 10 1011 | Device unavailable (DU)
2.9.3 Output Command
OCR RI, R2 [RR]
0 7/8 Hpz2 15
9E RI | R2
OC RI, A(X2) [Rx]
0 718 12 1516 31
DE R1 | X2 A
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The device is addressed and the
8-bit device command byte specified by the
second operand is transmitted to the ad-
dressed device. Both operands remain
unchanged.
Device + [R2 (8:15) ] [RR]
Device «+ [A+ (X2)] [RX]
Resulting Condition Code:
12]13]14{15
CIV|GIL
0/11/0|0| Examine Status (EX)
Programming Note:
The Examine Status bit is set if the device
cannot complete the command action.
2-35
2.10 INPUT/OUTPUT INSTRUCTIONS
The Input/Output instructions provide for
transfer of 8-bit byte information between
the Processor and peripheral devices in the
system.
2-36
2.10.2 Write Data
WDR RI, R2 [RR]
O 718 12 15
9A RI | R2
WD RI, A(X2) [RX]
О 718 112 15116 3!
РА RI | X2
2.10.1 Read Data
RDR RI, R2 [RR]
O 718 "2 15
9B R1 | R2
RD RI, A(X2) [RX]
o 718 lle 1516 31
DB RI | X2
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The device is addressed and a single
8-bit data byte is transmitted from the device
replacing the content of the location specified
by the second operand.
[R2 (8:15)] Data byte [RR]
[В2 (0:7)) < — — Zero
[A + (X2) 1+——— Data byte [RX]
Resulting Condition Code:
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The device is addressed and a single
8-bit data byte is transmitted to the device.
Both operands remain unchanged.
[R2 (8:15) } (Device) [RR]
[A + (X2) ] ————(Device) [RX]
Resulting Condition Code:
12
13
14
IS
C
V
G
L
12
13
14
IS
C
V
G
L
]
Examine Status (EX)
1 Examine Status (EX)
2-37
2.10.3 Read Block
RBR RI, R2 [RR]
0 718 12 15
97 RI | R2
RB R1, A(X2) [RX]
O 718 1112 1516 31
D7 RI | X2 A
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The 16-bit second operand location,
(R2) or [A + (X2)] contains the starting ad-
dress of the data buffer to be transferred.
The next sequential halfword, (R2 + 1) or
[A + (X2) + 2] contains the ending address of
the data buffer. The starting address must
be equal to, or less than, the ending address.
Data transfer is inclusive of the buffer limits,
The READ BLOCK instruction causes trans-
fer of 8-bit data bytes from a device to
consecutive memory locations. No other
instructions are executed during transfer of
the data block. The condition code portion
of the Program Status Word [ PSW (12:15)]
will be set to zero after a normal transfer,
In the event of an abnormal block data trans-
fer, the condition code will not be zero.
Resulting Condition Code:
121314115
VIGIL
С
0101010
1
Block data transfer completed correctly.
Device busy (BSY)
1 Examine status (EX)
1 End of medium (EOM)
1 | Device unavailable (DU)
2-38
2.10.4 Write Block
WBR R1, R2 [RR]
О 718 г 15
96 R1 | R2
WB RI, A(X2) [RX]
О 718 2 156 3!
D6 RI | X2 A
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The 16-bit second operand location,
(R2) or [A + (X2) ] contains the starting ad-
dress of the data buffer to be transferred.
The next sequential halfword, (R2 + 1) or
[A + (X2) + 2] contains the ending address of
the data buffer. The starting address must
be equal to, or less than, the ending address.
Data transfer is inclusive of the buffer
limits.
The WRITE BLOCK instruction causes trans-
fer of 8-bit data bytes from consecutive mem-
ory locations to a device. No other instructions
are executed during transfer of the data block.
The condition code portion of the Program
Status Word [PSW (12:15)] will be set to zero
after a normal transfer. In the event of an
abnormal block data transfer, the condition
code will not be zero.
Resulting Condition Code:
12113114115
VIGIL
O!0/0| Block data transfer completed correctly.
Device busy (BSY)
1 Examine status (EX)
] End of medium (EOM)
1 | Device unavailable (DU)
— OO
CHAPTER 3
CONSOLE OPERATION AND DISPLAY
3.1 INTRODUCTION
The discussion which follows pertains to a
typical Display Panel, shown on Figure 3-1,
and the operating controls associated with it.
Different models may vary.
The control console is comprised of six dis-
tinct elements:
1. Control Switches: POWER,
INITIALIZE, and EXECUTE,
2. MODE CONTROL Rotary Switch,
3. SPEED CONTROL rotary switch,
4, REGISTER DISPLAY rotary
5, Sixteen Data/Address switches.
6. Display of two 16-bit halfword
registers.
Each of the elements is described in the
following sections. Console operating pro-
cedures are provided following the
descriptions.
3.2 CONTROL SWITCHES
The latching POWER switch applies power
to the Processor and device controllers. An
indicator lamp is associated with the POWER
switch. switch.
ITN" EEE AI"A
REGISTER DISPLAY
OFF INST
RI4/15 PSW
RI2/13 e RO/I
RIO/I! R2/3
R8/9 сут RAS
DISPLAY |
SPEED CONTROL O | 23 4 5 6 7 8 9101 12131415
OOO OOOO OOOO OOOO0
DISPLAY 2
O 123 4567 8 91011 12 13 1415
SLOW FAST OOOO OOOO OOOO OOOO
MODE CONTROL
RUN ADRS
ÁS
ga © MEMR
FLT
VARI gy MEMW
WAIT Ts
oO I 2 3 45 6 7 8 9 10il 12 1314 15
CT Oo POr porro aaaE II 11
EXEC INIT PWR
N POWER
Figure 3-1. Display Panel 3-1
The momentary INITIALIZE switch resets
peripheral device interrupts and certain
other functions in the Processor. After
initialization, the Processor is left in the
Halt mode,
The momentary EXECUTE switch causes
the Processor to perform the function
selected by the MODE CONTROL switch.
The associated indicator lamp is on when
the Processor is in the interruptable Wait
state or Halt mode; the lamp is off when
the Processor is in the Run mode,
3.3 MODE CONTROL SWITCH
The rotary MODE CONTROL switch selects
the following modes of operation which be-
come effective when the EXECUTE switch
is depressed:
RUN: the Processor continuously exe-
cutes instructions at rated speed.
HALT: instruction execution is stopped at
(FIX) the moment the EXECUTE switch
is depressed and the Processor is
placed in the Wait state. The reg-
ister displays are operative in this
mode.
HALT: The HALT FLP position is similar
(FLP) to the HALT (or HALT FIX) posi-
tion except that in Processors
equipped with optional floating-
point hardware, the selected regis-
ters are displayed in the floating-
point format.
VARI: the Processor executes instructions
(FIX) at the rate selected by the variable
SPEED CONTROL, The register
displays are operative in this mode.
VARI: The VARI FLP position is similar
(FLP) to the VARI (or VARI FIX) position
except that in Processors equipped
with the optional floating-point
hardware, the selected registers
are displayed in the floating-point
format.
3-2
ADRS: selects the instruction location
address portion of the Program
Status Word (PSW(16:31)). The
new address is entered in the six-
teen Address Switches below the
register display.
MEMR: the Memory Read mode permits
display of memory data in the
register display.
MEMW: the Memory Write mode permits
entry of data into memory from
the sixteen Data Switches below
the register display.
3.4 SPEED CONTROL SWITCH
The variable SPEED CONTROL switch pro-
vides a dynamically changing display when
in the Variable mode. The rate of display
can vary from 1 to 1000 cps by rotating
the control clockwise from SLOW to FAST.
When in the SNGL position, a single in-
struction is executed and displayed each
time the EXECUTE switch is depressed.
3.5 REGISTER DISPLAY SWITCH
The REGISTER DISPLAY switch selects
pairs of 16-bit registers for display in the
lighted panel positions labeled DISPLAY 1
and DISPLAY 2. Beginning at the one
o'clock position and moving clockwise, the
registers displayed are:
INST: (D1) The current instruction,
(D2) The Address field of the cur-
rent instruction if RX or RS
format,
PSW: (D1) The Program Status and
Condition Code.
(DZ) The location address of the
current instruction.
RO/1: (D1) General Register 0.
(D2) General Register 1,
(Note: the seven succeeding pairs
of General Registers are selected
„= Зее © aT À
DIIIALALIY.)
OFF: (D1) and (D2) are blank.,
3.6 DATA/ADDRESS SWITCHES
The 16 Input Register latching pushbutton
switches provide a means of entering infor-
mation manually. An address set in the
switches is entered into the instruction loca-
tion address portion of the Program Status
Word (PSW (16:31)) when the ADRS mode is
selected and the EXECUTE switch is de-
pressed.
Data set in the switches is written into
memory when the MEMW mode is selected
and the EXECUTE switch is depressed.
The halfword location written into is speci-
fied by the instruction address portion of
the PSW,
3.7 REGISTER DISPLAY
The two 16-bit halfword register displays
are operative when the VARIable Mode or
when MEMR or MEMW have been selected.
The display registers remain static when in
the RUN mode.
3.8 CONSOLE OPERATING PROCEDURES
To bring up power and initialize the system:
1. Depress the latching POWER
switch.
2, Depress the momentary
INITIALIZE switch.
To shut down power to the system:
1. Set the MODE CONTROL switch to
HALT.
2. Depress the momentary EXECUTE
switch,
3. Release the latching POWER switch,
To begin execution of a program:
The system must be in the Halt mode.
1. Set the MODE CONTROL switch to
ADRS.
2. Enter the program starting address
in the 16 address switches.
3. Depress the momentary
EXECUTE switch.
4. Set the MODE CONTROL switch to
RUN.
5. Depress the EXECUTE switch.
To halt execution of a program:
1. Set the MODE CONTROL switch to
HALT,
2. Depress the EXECUTE switch.
To read memory from display registers:
The system must be in the Halt mode.
1. Set the MODE CONTROL switch to
ADRS,
2. Enter the memory read starting
address in the 16 address
switches.
3. Depress the EXECUTE switch.
4, Set the MODE CONTROL switch to
MEMR.
5. Depress the EXECUTE switch,
6. The memory data is read from
display register 2 (D2). The
memory address of the data be-
ing displayed is in display regis-
ter 1 (D1).
7. Depress the EXECUTE switch to
display memory data from suc-
cessive memory locations. The
memory address is automatically
incremented each time the
EXECUTE switch is depressed.
To write into memory:
The system must be in the Halt mode.
1. Set the MODE CONTROL switch to
ADRS,
2, Enter the memory write starting
address in the 16 address switches.
3. Depress the EXECUTE switch.
Set the MODE CONTROL switch to
MEMW,
Enter the data to be written into
memory in the 16 data switches.
Depress the EXECUTE switch.
The memory data entered is dis-
played in display register 2 (D2).
The memory address which was
written into is displayed in display
register 1 (D1). To write into
successive memory locations re-
peat from Step 5. The memory ad-
dress is automatically incremented
with each depression of the
EXECUTE switch.
To display the Instruction Register, Pro-
gram Status Word or General Registers:
The system must be in the Halt mode.
1.
Set the REGISTER DISPLAY switch
to select the registers desired for
display.
Depress the EXECUTE switch.
The registers selected for display
will appear in D1 and D2,
To display registers in the VARlable speed
mode:
The system must be in the Halt mode.
1.
3-4
Set the MODE CONTROL switch to
ADRS.
Enter the starting memory loca-
tion address in the 16 address
switches.
Depress the EXECUTE switch.
Set the MODE CONTROL switch to
VARI
5. Set the SPEED CONTROL switch to
SINGL or to a SLOW - FAST
setting.
6. Set the REGISTER DISPLAY switch
to select the registers desired for
display.
7. Depress the EXECUTE switch to
begin operation of the program
with display of the selected regis-
ters. If SNGL step was selected,
the EXECUTE switch is depressed
to cause single step execution of
successive instructions.
8. The REGISTER DISPLAY switch
setting can be changed during
operation in the variable speed
mode. The SPEED CONTROL
switch can also be changed from
SNGL to a SLOW-FAST setting
without halting operations.
3.9 DISPLAY PANEL PROGRAMMING
The Display Panel may also be accessed by
program as a peripheral device. The Data/
Address Switches may be read (Byte 0 =
Switches 8 through 15, Byte 1 = Switches 0
through 7) and the Display Registers may be
loaded as follows: Byte 0 = Display Register
2-bits 8 through 15, Byte 1 = Display Reg-
ister 2-bits 0 through 7, Byte 2 = Display
Register 1-bits 8 through 15, and Byte 3 =
Display Register -1 bits 0 through 7. Two
modes of operation are available, Normal
and Incremental. In Normal mode, Byte 0
is accessed each time the Display is ad-
dressed, In incremental mode, the Bytes
are accessed successively by each Write Data
nn Pear Tata imatmintinn Tha atatnna nf than
VI LUT ALI КИС ДЮ СЕ ДЛЕ, А 1155 ЮБК UA LIC
MODE CONTROL and REGISTER DISPLAY
Switches may be read via a Sense Status in-
struction. See Appendix 4, page A4-1
APPENDIX 1
SUMMARY OF INSTRUCTIONS - ALPHABETICAL BY NAME
INSTRUCTION TYPE MNEMONIC OP CODE
Acknowledge Interrupt RR AIR 9F
Acknowledge Interrupt RX Al DF
Add Halfword RR AHR 0A
Add Halfword RX AH 4A
Add Halfword Immediate RS AHI CA
Add with Carry Halfword RR ACHR ОЕ
Add with Carry Halfword RX ACH 4E
AND Halfword RR NHR 04
AND Halfword RX NH 44
AND Halfword Immediate RS NHI C4
Autoload RX AL D5
Branch and Link RR BALR 01
Branch and Link RX BAL 41
Branch on False Condition RR BFCR 03
Branch on False Condition RX BFC 43
Branch on True Condition RR BTCR 02
Branch on True Condition RX BTC 42
Branch on Index Low or Equal RS BXLE C1
Branch on Index High RS BXH Co
Branch Unconditional RR BR 03
Branch Unconditional RX B 43
Branch on Overflow* RX BO 424
Branch on Zero* RX BZ 433
Branch on Not Zero* RX BNZ 423
Branch on Equal* RX BE 433
Branch on Not Equal* RX BNE 423
*Extended Mnemonics - See Section 2.8
Al-1
INSTRUCTION TYPE MNEMONIC OP CODE
Branch on Plus* RX BP 422
Branch on Not Plus* RX BNP 432
Branch on Low* RX BL 428
Branch on Not Low* RX BNL 438
Branch on Minus* RX BM 421
Branch on Not Minus* RX BNM 431
Branch on Carry* RX BC 428
Compare Logical Halfword RR CLHR 05
Compare Logical Halfword RX CLH 45
Compare Logical Halfword Immediate RS CLHI C5
Divide Halfword RR DHR OD
Divide Halfword RX DH 4D
Exclusive OR Halfword RR XHR 07
Exclusive OR Halfword RX XH 47
Exclusive OR Halfword Immediate RS XHI C7
Floating-Point Add RR AER 2A
Floating-Point Add RX AE 6A
Floating-Point Compare RR CER 29
Floating-Point Compare RX CE 69
Floating-Point Divide RR DER 2D
Floating-Point Divide RX DE 6D
Floating-Point Load RR LER 28
Floating-Point Load RX LE 68
Floating-Point Multiply RR MER 2C
Floating-Point Multiply RX ME 6C
Floating-Point Store RX STE 60
Floating-Point Subtract RR SER 2B
Floating-Point Subtract RX SE 6B
Load Byte RR LBR 93
Load Byte RX LB D3
Load Halfword RR LHR 08
Load Halfword RX LH 48
Load Halfword Immediate RS LHI C8
*Extended Mnemonic - See Section 2. 8
A1-2
INSTRUCTION TYPE MNEMONIC OP CODE
Load Multiple RX LM D1
Load Program Status Word RX LPSW C2
Multiply Halfword RR MHR ОС
Multiply Halfword RX MH 4C
No Operation RR NOPR 020
No Operation RX NOP 420
OR Halfword RR OHR 06
OR Halfword RX OH 46
OR Halfword Immediate RS ОНТ C6
Output Command RR OCR 9E
Output Command RX OC DE
Read Block RR RBR 97
Read Block RX RB D7
Read Data RR RDR 9B
Read Data RX RD DB
Shift Left Arithmetic RS SLHA CF
Shift Left Logical RS SLHL CD
Shift Right Arithmetic RS SRHA CE
Shift Right Logical RS SRHL CC
Store Byte RR STBR 92
Store Byte RX STB D2
Store Halfword RX STH 40
Store Multiple RX STM DO
Subtract Halfword RR SHR 0B
Subtract Halfword RX SH 4B
Subtract Halfword Immediate RS SHI CB
Subtract with Carry Halfword RR SCHR OF
Subtract with Carry Halfword RX SCH 4F
Sense Status RR SSR 9D
Sense Status RX SS DD
Unchain RR UNCH 90
Write Block RR WBR 96
Write Block RX WB D6
Write Data RR WDR 9A
Write Data RX WD DA
A1-3/A1-4
APPENDIX 2
SUMMARY OF INSTRUCTIONS - NUMERICAL BY OP CODE
OP CODE TYPE MNEMONIC INSTRUCTION
01 RR BALR Branch and Link
02 RR BTCR Branch on True Condition
03 RR BFCR Branch on False Condition
04 RR NHR AND Halfword
05 RR CLHR Compare Halfword
06 RR OHR OR Halfword
07 RR XHR Exclusive OR Halfword
08 RR LHR Load Halfword
0A RR AHR Add Halfword
0B RR SHR Subtract Halfword
оС RR MHR Multiply Halfword
0D RR DHR Divide Halfword
OE RR ACHR Add with Carry Halfword
OF RR SCHR Subtract with Carry Halfword
28 RR LER Floating-Point Load
29 RR CER Floating-Point Compare
2A RR AER Floating-Point Add
2B RR SER Floating-Point Subtract
2C RR MER Floating-Point Multiply
2D RR DER Floating-Point Divide
40 RX STH Store Halfword
41 RX BAL Branch and Link
42 RX BTC Branch on True Condition
43 RX BFC Branch on False Condition
44 RX NH AND Halfword
45 RX CLH Compare Logical Halfword
46 RX OH OR Halfword
47 RX XH Exclusive OR Halfword
48 RX LH Load Halfword
4A RX AH Add Halfword
4B RX SH Subtract Halfword
4C RX MH Multiply Halfword
4D RX DH Divide Halfword
4E RX ACH Add with Carry Halfword
4F RX SCH Subtract with Carry Halfword
60 RX STE Floating-Point Store
A2-1
OP CODE TYPE MNEMONIC INSTRUCTION
68 RX LE Floating-Point Load
69 RX CE Floating-Point Compare
6A RX AE Floating-Point Add
6B RX SE Floating-Point Subtract
6C RX ME Floating-Point Multiply
6D RX DE Floating-Point Divide
90 RR UNCH Unchain
92 RR STBR Store Byte
93 RR LBR Load Byte
96 RR WBR Write Block
97 RR RBR Read Block
9A RR WDR Write Data
9B RR RDR Read Data
9D RR SSR Sense Status
9E RR OCR Output Command
IF RR AIR Acknowledge Interrupt
Co RS BXH Branch on Index High
C1 RS BXLE Branch on Index Low or Equal
C2 RX LPSW Load Program Status Word
C4 RS NHI AND Halfword Immediate
C5 RS CLHI Compare Logical Halfword Immediate
C6 RS OHI OR Halfword Immediate
CT RS XHI Exclusive OR Halfword Immediate
C8 RS LHI Load Halfword Immediate
CA RS AHI Add Halfword Immediate
CB RS SHI Subtract Halfword Immediate
CC RS SRH L Shift Right Logical
CD RS SLHL Shift Left Logical
CE RS SRHA Shift Right Arithmetic
CF RS SLHA Shift Left Arithmetic
DO RX STM Store Multiple
D1 RX LM Load Multiple
D2 RX STB Store Byte
D3 RX LB Load Byte
D5 RX AL Autoload
D6 RX WB Write Block
D7 RX RB Read Block
DA RX WD Write Data
DB RX RD Read Data
DD RX SS Sense Status
DE RX OC Output Command
DF RX Al Acknowledge Interrupt
А2-2
68
137
549
1 099
00 4$ NH
16
67
134
268
536
073
147
294
589
179
359
719
438
877
755
511
p=
16
32
65
131
262
524
048
097
194
388
777
554
108
217
435
870
741
483
967
934
869
738
476
953
906
813
627
576
152
304
608
216
432
864
728
456
912
824
648
296
592
184
368
736
472
944
888
776
wn o 3
4 O Un F-
APPENDIX 3
TABLE OF POWERS OF TWO
92-n
1.0
0.5
0.25
0.125
0.062
0.031
0.015
0.007
0.003
0.001
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
0.000
25
625
812
906
953
976
488
244
122
061
030
015
007
003
001
000
000
000
000
000
000
000
000
000
000
000
000
000
000
900
000
000
000
000
000
000
25
125
562
281
140
070
035
517
258
629
814
907
953
476
238
119
059
029
014
007
003
001
000
000
000
000
000
000
000
000
000
000
000
625
312
156
578
7 89
394
697
348
674
837
418
209
604
802
901
450
725
862
931
465
232
116
058
029
014
007
003
001
000
25
125
062
531
265
632
316
158
579
289
644
322
161
580
290
645
322
661
830
415
207
103
551
275
637
818
909
25
625
812
406
203
101
550
775
387
193
596
298
149
574
287
643
321
660
830
915
957
978
989
494
25
125
562
781
390
695
847
923
461
230
615
307
653
826
913
456
228
614
807
403
701
ARITHMETIC REFERENCES
625
312 5
656 25
828 125
062
031
515
257
914
957
478
739
628
814
407
703
869
934
467
733
366
183
091
545
851
425
712
856
772 928
25
625
812
906
453
226
613
806
903
951
475
237
5
25
125
562 5
281 25
640 625
320 312 5
660 156 25
830 078 125
915 039 062 5
A3-1
A3-2
TABLE OF POWERS OF
SIXTEEN
16° n
1 0
16 1
256 2
4 096 3
65 536 4
1 048 576 5
16 777 216 6
268 435 456 7
4 294 967 296 8
68 719 476 736 9
1 099 511 627 776 10
17 592 186 044 416 11
281 474 976 710 656 12
4 503 599 627 370 496 13
72 057 594 037 927 936 14
152 921 504 606 846 976 15
Decimal Values
a al
HEXADECIMAL ADDITION TABLE
12| 3 | 4 |5 | 6 | 7| 8 | 9 | А| В | с | р Е ®
213 | 4| 56| 7 | 8 |9 | А | В | с | р | Е| Е 10
34| 5| 6 |7 | 8 | 9 | А | В | с | р | Е | в |10 | 11
4 | 5 | 6 | 7 | 8 | 9 | А | В | с | р | Е | Е | 10 | 11 112
5 |6 |7 | 8 | 9 | А | В | с | р | Е| Е | 10 | 11 112 113
6 |7 | 8 | 9 | А | В | с | р | Е | Е |10 | 11 | 12 113 | 14
7 | 8 | 9 | А | В | с | р | Е | Е | 10 | 11_ | 12 | 13 | 14 | 15
8 | 9 | А | В | с | р | Е | Е | 10 | 11 |12 | 13 | 14 | 15 | 16
9 А | В | С | | E | F |10 | 11 | 12 [13 | 14 | 15 |16 |17
A|B|C| DE F |10 |11 |12 | 13 114 | 15 |16 |17 |18
В | С | р | Е | Е |10 |11 |12 | 13 | 14 |15 | 16 | 17 |18 [19
C | D | E | Е |10 | 11 |12 |13 | 14 | 15 |16 | +7 | 18 [19 |1A
D | E | F |10 |11 | 12 |13 |14 |15 | 16 |17 | 18 | 19 |1A|1B
E | F |10 [11 |12 | 13 | 14|15 |16 | 17 |18 | 19 | 1A|1B|1C
F |10 |11 (12 |13 | 14 |15 |16 | 17 | 18 |19 | LA | 1B/1C |1D
10 11 112 [13 |14 | 15 [16 |17 |18 | 19 |1A |1B | 1С 110 |1Е
11213145 6 (78 9|Aa|Blc|D|lEI!|F
A3-3
HEXADECIMAL MULTIPLICATION TABLE
A3-4
2 3 4 5 6 7 8 9 A B C D E F
1 2 3 4 9 6 7 8 9 A B C D E F | 1
2 4 6 8 A C E | 10 | 12 | 14 | 16 | 18 | 1A | 1C |1E | 2
3 6 9 C F | 12 | 15 | 18 | 1B | 1E | 21 | 24 | 27 | 2A | 2D | 3
4 8 C | 10 | 14 | 18 | 1C | 20 | 24 | 28 | 2C | 30 | 34 | 38 | 3C | 4
5 A F | 14 | 19 | 1E | 23 | 28 | 2D | 32 | 37 | 3C | 41 | 46 | 4B | 5
6 C | 12 | 18 | 1E | 24 | 2A | 30 | 36 | 3C | 42 | 48 | 4E | 54 | 5A | 6
7 E | 15 | 1C | 23 | 2A | 31 | 38 | 3F | 46 | 4D | 54 | 5B | 62 | 69 | 7
8 10 | 18 | 20 | 28 | 30 | 38 | 40 | 48 | 50 | 58 | 60 | 68 | 70 | 78 | 8
9 12 | 1B | 24 | 2D | 36 | 3F | 48 | 51 | 5A | 63 | 6C | 75 | ТЕ | 87 | 9
A 14 | 1E | 28 | 32 | 3C | 46 | 50 | 5A | 64 | GE | 78 | 82 | 8С | 96 | A
B 16 | 21 | 2C | 37 | 42 | 4D | 58 | 63 | 6E | 79 84 | 8F | 9A | A5 | B
C 18 | 24 | 30 | 3C | 48 | 54 | 60 | 6C | 78 | 84 | 90 | 9C | A8 | B4 | C
D 1А | 27 | 34 | 41 | 4E | 5B | 68 | 75 | 82 | 8F | 9С | A9 | B6 | C3 | D
E 1C | 2A | 38 | 46 | 54 | 62 | 70 | 7E | 8C | 9A | A8 | B6 | C4 | D2 | E
F 1E | 2D | 3C | 4B | 5A | 69 | 78 | 87 | 96 | A5 | B4 | C3 | D2 | El | E
2 3 4 5 6 7 8 9 A B C D E F
APPENDIX 4
INPUT/ OUTPUT REFERENCES
DISPLAY STATUS AND COMMAND EYTE DATA
HEX ADDRESS 01
BIT
NUMBER
STATUS
BYTE
MODE
REGISTER DISPLAY
COMMAND
BYTE
NORM
INC
MODE
CONTROL
SWITCH
REGISTER
STATUS:
RUN
ADR
OFF
DISPLAY | PSW
SWITCH
RO,
R2,
R4,
R6,
R8,
COMMAND:
NOR
INC
(VARI (FIX)
VARI FLT
HALT (FIX)
HALT FLT
MEM WRITE
MEM READ
S
R1
R3
R5
R7
R9
R10, R11
R12, R13
R14, R15
M
>| DIS | HF JO JO
REG DISPLAY
INST
>| DI SEE | |
Pri | Po DI AD SIA
Ор О | © | | ©
pa | | | pi fp [= [= |S oO
== l=lolo|lolol=|olo
lO lo|=~olo|lo|l=|o
© РНЕ НЕС | | | р
In the Normal Mode, Byte 0 of the registers or switches is accessed
each time an I/O operation is directed to the Display Panel.
In the Incremental Mode, subsequent I/O operations access subsequent
bytes of the registers or switches.
A4-1
TELETYPE STATUS AND COMMAND BYTE DATA
HEX ADDRESS 02
BIT
NUMBER 0 1 2 3 4 5 6 7
STATUS
BYTE BRK BSY EX DU
COMMAND PWR | PWR
BYTE DISABLE | ENABLE | UNBLOCK |BLOCK | WRT |READ ON OFF
BRK The Break bit is set when the Break key on the Teletype is depressed, or the
Teletype is logically disconnected from the Controller.
BSY The significance of the Busy bit depends upon whether a Read or a Write
operation is in progress. During Write mode, BSY is normally low, and
goes high only while data is being received by the device. During Read
mode, BSY is normally high, and goes low only when data has been re-
ceived from the device, but not yet been transferred to the Processor.
During Read mode, BSY goes high again as soon as the Processor accepts
the data.
EX The Examine bit is set whenever BRK is set,
DU The Device Unavailable bit is set whenever the Teletype is in the OFF or
LOCAL mode, or power is not connected to the Teletype.
DISABLE This command disables the Device Interrupt to the Processor from the
Device Controller.
ENABLE This command enables the Device Interrupt to the Processor from the
Device Controller.
UNBLOCK This command enables the printer to print data entered via either the key-
board or the tape reader.
BLOCK This command disables the feature described above.
WRT |} The Write and Read commands are used to define the significance of the
READ BSY bit.
PWR ON | The Power On and Power Off commands are significant only with those Tele-
PWR OFF) types proyided with an optional Power Control Box, The option permits
А4-2
switching Teletype power under program control.
HIGH SPEED PAPER TAPE READER STATUS AND COMMAND BYTE DATA
HEX ADDRESS 03
BIT
NUMBER 0 1 2 3 4 5 6 7
STATUS
BYTE OVERFLOW NMTN | BSY | EX DU
TD DISABLE ENABLE | STOP | RUN INCR | SLEW | REV | FWD
OVERFLOW The Overflow bit is available for use with paper tape readers which operate
in the Slew mode. The bit is set if the next character is read before a Data
Request (DR) is received for the present character.
NMTN The No Motion bit is set any time the tape is not moving
BSY The Busy bit is reset anytime there is a character in the buffer and no Data
Request (DR) has been received from the Processor.
EX The Examine bit is set whenever either Overflow or NMTN is set.
DU The Device Unavailable bit is set if Reader Power is off, or if the LOAD/
READY lever on the reader is in the LOAD position,
DISABLE This command disables the Device Interrupt.
ENABLE This command enables the Device Interrupt.
STOP The Stop command stops reader tape motion.
RUN The Run command starts the reader tape motion.
INCR The Increment command directs the reader to read in Increment mode,
The tape is stepped to the next character after each character is input to
the Processor.
SLEW The Slew command applies only to readers capable of operation in the Slew
mode. In Slew mode the tape is started and continues to run until a
particular character or string of characters on the tape is sensed.
REV The Reverse command applies only to bi-directional tape readers.
FWD The Forward command directs the reader to move the tape forward.
A4-3
CARD READER STATUS AND COMMAND BYTE DATA
(HEX ADDRESS 04)
BIT
NUMBER 0 1 2 3 4 5 6 7
STATUS
BYTE EOV TBL HE NMTN BSY | EX EOM DU
COMMAND
BYTE DISABLE ENABLE FEED
EOV The EOV bit is set when the data is not taken from the Device Controller
buffer before the next column of data arrives from the read station, This
bit is reset by a FEED Command,
TBL/DU These bits are set when the Card Reader fails to pick a card upon command,
or When an error condition occurs in the Card Reader, The error conditions
are:
1. Card Motion Error
2. Light Current Error
3. Dark Current Error
These error conditions prevent the reading of any more cards until manually
reset by the operator.
HE The HE bit is set when the last card in the input hopper has been read. When
HE sets, NMTN is set. The HE bit must be manually reset by the operator.
NMTN The NMTN is set except for the time between a FEED command and the time
it takes for a card to pass through the read station.
BSY The BSY bit is set while the Device Controller is awaiting data from the Card
Reader. It resets when the data is available to be transferred.
EX The EX bit sets when any one of the upper four (4) bits of the Status byte is
set.
EOM The EOM bit is set whenever NMTN is set, and when the input hopper becomes
empty. Reset when FEED command is issued.
DISABLE This command disables the Card Reader Device Interrupt.
ENABLE This command enables the Card Reader Device interrupt.
FEED This command initiates a new card feed cycle; however, no action occurs if
TBL, DU, or HE is set.
TELETYPE/ASCII/HEX CONVERSION TABLE
HEX (MSD) —| 8 9 A B|C|D|E|F
(LSD) Teletype 8 DEPENDS UPON PARITY |
Tape 7 0 0 0 От |1 |1 |1
Channels =f 17 0 0 1 ılololılı
| 5 0 1 0 1 |0 | 1 |0 |1
Ÿ 413121] 1
9 0 |0 | 0| 0 | NULL | DCo SPACE | 0 | E | P
1 о |0 | 0| 1 | SUM |X-ON 1 | A] Q
2 |0 |0 | 1| 0 | ЕОА e " 2 | B|R
3 0 |0 |1| 1 | EOM |X-OFF # 3 | С | $
4 о |1 | 0| 0 | EOT om $ 4 | D|T
5 O |1 |0| 1 |WRU |ERR % 5 |E|U
6 0 | 1 |1/| о | ВО SYNC & 6 | F|V
7 0 |1 |1| 1 | BELL | LEM 7|G|W
8 1 | 0 | 0| 0 | FEp So ( 8 | H| X
9 1 | 0 | 0| 1 | HT/SK |S1 ) 9 [I |Y
A 1 |0 |1| 0 | LF So * J |Z
B |1|0|1) 1|VT S3 + ‚x IL
C 1 |1 | 0| 0 | FF S4 , < | L|\ ACK
D 1 |1 | 0| 1 | CR S5 - = | м | ] ODE
1 [11] 0] SO Se > | NI] ESC
111 |1) 1 [SI S7 / ? | O DEL
A4-5
ASCIN/ CARD CODE CONVERSION TABLE
7-BIT
ASCII
CODE
8-BIT
ASCII
CODE
7-BIT
ASCII
CODE
8-BIT
ASCII
CODE
CARD
CODE
CARD
CODE
GRAPHIC
GRAPHIC
40
C0
20 0-8-2
12-8-7
A0
SPACE
41 12-1
Cl
21
Al
12-2
42
C2
22 8-7
23
A2
12-3
C3
A3
44 12-4
45
C4
24 11-8-3
25
А4
12-5
C5
0-8-4
A5
%
46 12-6
C6
26 12
27
A6
47 12-7
C7
8-5
AT
TT
AN A + A
re re —]
oa A
<< SH «+
со © < M
© © © ©
оно м
TY
CI
N A AN
ee EE A
oo << (A
N N N N
со © < M
< < <<
о Хх +
11-3
4C
4D
4E
4F
50
ol
52
53
CC
0-8-3
2C
2D
2E
2F
30
31
AC
11-4
CD
CE
11
12-8-3
AD
11-5
AE
11-6
CF
0-1
AF
11-7
DO
BO
11-8
D1
Bi
11-9
D2
32
B2
0-2
0-3
D3
33
34
35
B3
D4
59
об
57
58
59
5A
D5
B5
0-5
D6
36
B6
0-6
0-7
D7
37
B7
D8
38
B8
D9
39
B9
0-9
DA
N La 7 E
8-2
11-8-6
12-8-4
3A
BA
Sol)
e
с = =
ry = A
MAO AQ
LD LD Ww
ADA
AAA
8-6
0-8-6
B
3C
3D
2
AQ
pe
BC
BD
BE
ve em VI
E 11-8-7
oF
DE
dE
SF
0-8-5
DF
0-8-7
BF
A4-6
APPENDIX 5
MODEL 3 REFERENCE DATA
1. INTRODUCTION
This Appendix describes the characteristics
of the Model 3 Digital System.
1.1 PROCESSOR ORGANIZATION
The various elements of the Model 3 Digital
System are organized around the primary
controlling unit, the Processor. The Pro-
cessor consists of a group of sixteen 16-bit
General Registers and an Arithmetic Logic
Unit (ALU). See Figure A5-1.
1.2 GENERAL REGISTERS
The sixteen General Registers can be used
as accumulators in fixed-point arithmetic
and logical operations, or as index registers
in address arithmetic and indexing operations.
Each register is sixteen bits, or one halfword
long.
1.3 ARITHMETIC LOGIC UNIT
The Arithmetic Logic Unit (ALU) processes
both binary integers and logical information.
The operands can be located in the General
Registers and/or core memory. Positive
fixed-point data is expressed in true binary
form with a sign bit of zero. Negative fixed-
point data is expressed in two's complement
form with a sign bit of one.
2. CORE MEMORY ALLOCATION
The micro-program uses the first 80 bytes
of core memory. See Table A5-1.
2.1 GENERAL REGISTERS
The General Registers are assigned conse-
cutive byte addresses beginning at address
X'0000'. The address in memory is equal
to twice the register number. For example,
General Register 5 is maintained in the half-
word core location at address X'000A'.
NOTE
For program compatibility with
other INTERDATA Digital Sys-
tems, the General Registers
should not be referenced by their
absolute memory addresses.
2.2 HARDWARE REGISTERS
Core locations X'0020' through X'002D'
maintain hardware registers set aside for
Display support. On Model 3 systems with
special expanded displays, the 12 o'clock
position on the REGISTER DISPLAY Switch
causes the display support core locations
to be output to the display registers when in
the Variable mode.
2.2.1 Instruction Register. Core
locations X'0020' through X'0023' hold the
current Instruction Word:
OPERATION
CODE R1/M! | R2/X2 ADDRESS
Ne > A —
Y Y Y Y
20 21 22 23
А5-1
CORE MEMORY
о
ADDRESS
15
о
DATA
IL
HIGH SPEED MEMORY BUS
il
y
SELECTOR CHANNEL
MAGNETIC
DISC
А5-2
SELECTOR CHANNEL BUS
MAGNETIC TAPE
AN
A
Figure A5-1,
T
O
{|
12 15
ZN
3
STATUS
cc
LOCATION
COUNTER
U
=
о
PROGRAM STATUS WORD
7,8 11.12 15,16
ADDRESS/DATA
31
DIRECT
MEMORY ACCESS
CHANNEL
ОР ATA
INSTRUCTION REGISTER
15
RO
RI
e
R2
GENERAL
y REGISTERS a
RI3
dur
RIA
RIS
«=
Lg = PROC ESSOR
TR TTR o НЫ E Ce CE еж KN
7 E —
LINE PRINTER
PAPER TAPE
ARITHMETIC
AND
LOGICAL UNIT
MULTIPLEXOR BUS
À
CARD READER
TELETYPE
Model 3 System Block Diagram
SPECIAL
DEVICE
Pa — — — —-——
DISPLAY PANEL
TABLE A5-1
MODEL 3 CORE MEMORY ALLOCATION
FOR REGISTERS AND PROGRAM STATUS WORDS
Hexadecimal Memory Address
General Registers
00-01
02-03
04-05
06-07
08-09
0A-0B
0C-0D
0E-0F
10-11
12-13
14-15
16-17
18-19
1A-1B
1C-1D
1E-1F
Hardware Registers (Display Support)
20-23
24-25
26-27
28-29
2A-2B
2C-2D
2E-2F
Program Status Words
30-33
34-37
38-3B
3C-3F
40-43
44-47
48-4B
4C-4F
50
Register Assignment
RO
R1
R2
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Instruction Register
Current PSW: Status and Condition Code
Current PSW: Location Counter
Display Support: First Operand
Display Support: Second Operand
Display Support: Result
Unassigned
Old PSW: Illegal Instruction Interrupt
New PSW: Illegal Instruction Interrupt
Old PSW: Machine Malfunction Interrupt
New PSW: Machine Malfunction Interrupt
Old PSW: External Device Interrupt
New PSW: External Device Interrupt
Old PSW: Divide Fault Interrupt
New PSW: Divide Fault Interrupt
First User Available Memory Location
A5-3
2.2.2 Program Status Word.
Core locations X'0024' through X'0027'
maintain the current Program Status Word:
STATUS CODE | LOCATION COUNTER
ha A, — A A, À
Y Y Y Y
24 25 26 27
2.2.3 Display Support. Core
locations X'0028' through X'002D' save the
first operand, second operand and result for
display support:
FIRST OPERAND
bu A. A
28 29
SECOND OPERAND
Ч A.
Y Y
2A 28
RESULT
hs A, A
Y Y
2C 2D
2.3 SYSTEM INTERRUPTS
System Interrupts are provided to detect the
presence of Illegal Instructions, Machine
Malfunctions, Divide Fault, and External
Device Interrupts. Interrupts are controlled
by the Status field (bits 0 through 11) of the
Current Program Status Word. Individual
bits in the Status field correspond to a parti-
cular category of interrupts. A ZERO bit
disables a corresponding category of inter-
rupts and a ONE bit enables a corresponding
category of interrupts. See Table A5-2.
TABLE A5-2.
PSW STATUS FIELD ASSIGNMENTS
Bit Set Meaning
0 Wait State
1 External Device Interrupt
enable
2 Machine Malfunction Interrupt
enable
3 Divide Fault Interrupt enable
4 Restart/Continue*
5 through| Unassigned
11
*for no-display machines
А5-4
There are four additional PSW's, each as-
sociated with a specific class of interrupt.
The PSW's are dedicated in core in pairs of
fullword locations. The New PSW defines
the action to be taken for each type of inter-
rupt; the Old PSW is a reserved storage area
for the Current PSW when the interrupt is
taken.
After each User's instruction is executed,
the Processor tests for interrupts. If an
interrupt is found pending, and the corres-
ponding bit in the Current PSW is set, the
Current PSW is saved in the Old PSW save
area for that interrupt, and the New PSW
replaces the Current PSW. This action
results in a Branch to an appropriate service
subroutine.
2.3.1 Wait State. Bit zero of the
Current PSW, when set, places the Proces-
sor into a high-speed interruptable Wait
(idle) state. During this idle or halted state,
the Processor is still responsive to enabled
interrupts. When bit zero of the Current
PSW is reset, the Processor is in the Run
mode and only responds to enabled interrupts
at the conclusion of each User's instructions.
2.3.2 External Device Interrupt.
Bit one of the Current PSW, when set, al-
lows external devices to interrupt the Pro-
cessor. When the Processor finishes an
instruction, if an I/O interrupt is pending
and if bit one of the Current PSW is set, a
PSW swap takes place.
2. 3. 3 Machine Malfunction Inter-
overy can he made. Such items as Memory
Parity Error, I0 Device failure, ‘Power
Failure fall into this category, but only the
Memory Parity Error generates the interrupt.
2.3.4 Divide Fault Interrupt.
The Divide Fault Interrupt is indicative of
a division that vields a quotient greater than
15 bits. This usually occurs when a division
by zero is attempted.
2.3.5 Restart/Continue. Mach-
ines without a display console are designated
Auto Load machines and have a special
micro-code ROM. The special ROM pro-
vides the features necessary to load a pro-
gram, select a starting address for a program
or automatically restart or continue after a
power failure or power down.
Bit 4 of the PSW is designated the restart/
continue bit for no display Model 3's. This
bit controls the starting address (location
counter) when leaving the HALT state and
going to the RUN state. If bit 4 is set, in-
struction execution will begin at X'0050', If
reset, instruction execution resumes follow-
ing the point where the machine was halted.
The status of this bit is controlled by the
program being executed.
3. ADDITIONAL DATA
Table A5-3 lists the Model 3 Instruction Set
and Op Codes. Table A5-4 lists the Model
3 Instruction Timing.
A5-5
TABLE A5-3
OP-CODE
Least Most Significant Digit
Significant
Digit 0 4 9 C D
0 STH BXH
1 BALR BAL BXLE
2 BTCR BTC STBR LPSW STB
3 BFCR BFC LBR LB
4 NHR NH NHI
5 CLHR CLH CLHI
6 OHR OH WBR OHI WB
7 XHR XH RBR XHI RB
8 LHR LH LHI
9
A AHR AH WDR AHI WD
B SHR SH RDR SHI RD
C MHR MH SRHL
D DHR DH SSR SLHL SS
E ACHR ACH OCR SRHA OC
F SCHR SCH AIR SLHA Al
RR RX RR RS RX
R1, R2 R1, A(X2) R1, R2 R1, A(X2) R1, A(X2)
Category/Operand Format
A5-6
TABLE A5-4
MODEL 3 INSTRUCTION TIMING IN MICROSECONDS
RS RX
no no
Instruction RR index indexed index indexed Comments
ACH 30 — - 38 40
AH 28 36 38 36 38
Al 41 - - 49 51
ВАТ, 25 - — 32 33
BFC 28/22 - - 32/30 | 34/32 br/no br
BTC 29/23 - - 33/30 | 34/32 br/no br
BXH — 44 45 — —
BXLE - 44 45 ~ -
CLH 29 37 39 37 39
LB 22 - — 30 32
LH 25 36 37 35 37
LPSW - - — 35 37
NH 27 36 37 35 37
OC 33 - - 41 43
ОН 27 36 37 35 37
RD 38 - - 38 40
SCH 30 - - 38 40
SH 28 36 38 36 38
SLHA - 39+4n 49+4n - -
SLHL - 39+3n 49+3n - -
SRHA - 39+4n 49+4n - -
SRHL - 39+3n 49+3n - -
SS 38 — - 38 40
STB 24 - - 32 34
STH — — — 30 32
WD 33 - — 41 43
XH 27 35 37 35 37
HIGH SPEED ARITHMETIC AND INPUT/OUTPUT OPTION
DH 93/180 - - 101/194| 102/195 best/worst
MH 106/146 { - - 114/154| 115/155 best/worst
RB 50+10n - - 50+10n | 51+10n
WB 50+10n ~ - 50+10n | 51+10n
PSW swap time:
Memory Cycle time:
23 usec
1.5 usec
Selector Channel transfer rate:
Note: I/O execution times assume 200 ns sync response.
Read/Write:
500 KBS
Direct Memory Access Channel transfer rate:
900 KBS
number of bytes or shifts
A5-7/A5-8
APPENDIX 6
MODEL 4 DIGITAL SYSTEM REFERENCE DATA
1. INTRODUCTION
This Appendix describes the characteristics
of the Model 4 Digital System.
1.1 PROCESSOR ORGANIZATION
The various elements of the Model 4 Digital
System are organized around the primary
controlling unit, the Processor. The Pro-
cessor consists of a group of sixteen 16-bit
General Registers, eight 32-bit floating-
point registers, and an Arithmetic Logic
Unit (ALU). See Figure A6-1.
1.2 GENERAL REGISTERS
The sixteen General Registers can be used
as accumulators in fixed-point arithmetic
and logical operations, or as index registers
in address arithmetic and indexing operations.
Each register is sixteen bits, or one halfword,
long.
1.3 FLOATING—POINT REGISTERS
The eight Floating-Point Registers are used
as accumulators in floating-point arithmetic
operations. Each register is thirty-two bits,
or one fullword, long. Bit 0 is the sign bit
of the fraction, bits 1 through 7 are the ex-
ponent of the fraction, and bits 8 through 31
contain a fraction expressed and manipulated
in hexadecimal.
1.4 ARITHMETIC LOGIC UNIT
The Arithmetic Logic Unit (ALU) processes
both binary integers and logical information.
The operands can be located in the fixed-
point registers, the floating-point registers,
and/or core memory. Positive fixed-point
data is expressed in true binary form with
a sign bit of zero. Negative fixed-point data
is expressed in two's complement form with
a sign bit of one. Floating-point operands
are expressed in signed magnitude form.
2. CORE MEMORY ALLOCATION
The micro-program uses the first 80 bytes
of core memory. See Table A6-2.
21 FLOATING-POINT REGISTERS
The Floating- Point Registers are assigned
consecutive byte addresses beginning at ad-
dress X'0000'. The address in memory is
equal to twice the register number (only
even number addresses are permitted).
For example, Floating-Point Register 6 is
maintained in the fullword core location at
address X'000C".
NOTE
For program compatibility with other
INTERDATA Digital Systems, the
Floating-Point registers should not
be referenced by their absolute memory
addresses. The Floating-Point registers
should be referenced only by the Floating-
Point instructions.
A6-1
CORE MEMORY
ADDRESS
HIGH SPEED MEMORY BUS
PROCESSOR
LOCATION
COUNTER
PROGRAM STATUS WORD
STATUS cc
DIRECT
ACCE
CHANNEL
SELECTOR CHANNEL
MAGNITUDE
ОР ADDRESS/DATA
i
INSTRUCTION REGISTER
FIXED POINT
REGISTERS
(18)
7,8
FRACTION
FLOATING POINT
REGISTERS
(8)
EXP. SPECIAL
DEVICE
MAGNETIC TAPE
MAGNETIC
DISC
ARITHMETIC
AND
LOGICAL UNIT
@
Dee DI
LINE PRINTER PAPER TAPE CARO READER
4
fn
4
<<
0
Mm
DISPLAY PANEL
Figure A6-1. Model 4 System Block Diagram
A6-2
TABLE A6-1
PHYSICAL AND ENVIRONMENTAL SPECIFICATIONS
PHYSICAL SPECIFICATIONS
Dimensions
Card file 18.7" x 10.47" x 12" (RETMA Standard)
Display 19" x 13.97" x 2" (RETMA Standard)
Power Supply 18.81" x 10.47" x 7.5"
Weight
Processor card file 22 Ibs.
Display 10 lbs.
Power Supply 50.5 lbs.
Options
8K Memory Module 5.5 lbs.
Copper I/O board 1 Ib.
Wire-Wrap I/O board 1.5 lbs.
Expansion Chassis 7.2 lbs.
Desk Top Cabinet 11 lbs. 13.97" x 19" x 24"
System Cabinet 125 lbs. 67" x 23" x 24"
Power
115 VAC +10%, 57 to 63 HZ
110 Watts Processor and Display
180 Watts with TTY Controller and 8K bytes core
280 Watts with one full expansion chassis
Environmental
Temperature 0°C to 50°C operating
-55°C to 85°C storage
Humidity 0% to 90% without condensation
A6-3
TABLE A6-2
CORE MEMORY ALLOCATION FOR REGISTERS
AND PROGRAM STATUS WORDS
Hexadecimal Memory Address Register Assignment
Floating-Point Registers
00 - 03....eco,oe.eeceeo0rc.oreoercorocooeoe RO
04 - 07...c.oeeo—rc.omeoccccoreereocarcarcarce R2
08 - OB. ....coeccooccrcosraroaccacracacacarce R4
OC - OF...ececococcooorocooraconecoaocerao R6
I sa 0000000 R8
14 -—17....ecoscoocccovareoraraccarecavo R10
18-1B..........0.0.000c00ce 00000000 u08 R12
OE оо вов ьовоововововвввеее R14
20 - 21...cwe.crcocoococsocoascoccosanorcareneo High Speed Interrupt Pointer
22 - 23....0.06.0.0ec... 00.0000. 00000000000 Register Save Pointer
24 - 25......oresss0ccoco0arrercaocarorcooo Current PSW: Status and Condition Code
26 ZZ 000000000000000000000000000000000 Current PSW: Location Counter
28 - 2B..e.c.ccoccorcsorcomccocacorocaacoo ..... Old PSW Flp Divide Fault Interrupt
A ane 0000 as 00 00 New PSW Flp Divide Fault Interrupt
80 - 33...0..008.0ss0cmeoccocooresarcoresoo Old PSW Illegal Instruction Interrupt
34 - $T .o.cceoorcaceococeoacoracanacareroo New PSW Illegal Instruction Interrupt
A e0s 000 0ac0 00 Old PSW Machine Malfunction Interrupt
C- 3F,......eoor_ocscocecocsacocareoccaccareo New PSW Machine Malfunction Interrupt
N 000 00000000000000000 Old PSW External Device Interrupt
44 — Al 000000000 00000 0000000000000000000 New PSW External Device Interrupt
48 - 4В........... e ecocoracoroocacacdoroo Old PSW Fix Divide Fault Interrupt
3 00000000 0000000002 00.0000 New PSW Fix Divide Fault Interrupt
90 W0000 00000000 EEE e0 0000 First User Available Memory Location
PSW STATUS FIELD ASSIGNMENTS
Bit Set Meaning
0 Wait State
1 External Device Interrupt
2 Machine Malfunction Interrupt
3 Fixed-Point Divide Fault Interrupt
a Ti ech Слои] Теа + итак +
4 11111 WIPECTU UILL LL up
5 Floating-Point Divide Fault Interrupt
6 through 11 Unassigned
A6-4
2.2 HIGH SPEED INTERRUPT POINTER
Core location X'0020' (the High Speed Inter-
cupt Pointer) contains the starting address
of an eight byte block defined as follows:
PSW (save)
LOC (save)
The first halfword is a save area for the
current PSW when a High Speed Interrupt is
taken. The second halfword is a save area
for the current location counter. The next
fullword is the next instruction to be per-
formed. This instruction should be a branch
to a service subroutine as an automatic
"push-down'" takes place when High Speed
Interrupts occur. Location X'0020' is in-
cremented by eight every time the interrupt
takes place, defining another eight byte
block. For example, if location X'0020' con-
ains the address X'1300', when the High
Speed Interrupt is taken, the Current Pro-
gram Status Word is saved in location X'1300';
the Location Counter is saved in location
X'1302'; the Pointer (location X'0020') is
incremented by eight; the hardware PSW is
set to zero (disabling all other categories
of interrupts) and the location counter is
set to X'1304'. Fullword X'1304' should
contain a branch to a service subroutine.
If, during this service subroutine, another
High Speed Interrupt occurs, the same ac-
tions take place and another service subrou-
tine is entered. As many interrupt service
subroutines as the programmer anticipates
may be so nested.
When a service subroutine is completed,
those unfinished subroutines entered earlier
must be completed before the main program
is re-entered. This reversal of the "push-
down' process is done through the Un-Chain
(UNCH) instruction. This instruction decre-
ments the High Speed Interrupt Pointer by
eight and loads PSW from that save area.
The following is a sample of push-down
stack programming.
HSINTA DS 2
DS 2
B SRVCA
HSINTB DS 2
DS 2
B SRVCB
HSINTC DS 2
DS 2
B SRVCC
If the UNCH instruction is terminating ser-
vice subroutine SRVCC, the PSW is loaded
from location HSINTC which returns pro-
gram control to the remainder of SRVCB.
Figure A6-2 depicts a three level chain and
unchain process which eventually returns con-
trol to the main program with the High Speed
Interrupt Pointer back to its original value.
The High Speed 1/0 Interrupt, available as
an option, operates on a priority above the
normal I/O Interrupt. If I/O Attention and
Fast 1/O Attention occur simultaneously,
the Fast I/O Interrupt is serviced first.
Bit 4 of PSW enables the Fast I/O Inter-
rupt.
2.3 REGISTER SAVE POINTER
The halfword in core location X'0022' con-
tains the starting address of the save arec.
in core for storing the fixed-point Genera!
Registers. When the Processor is initializ=d
- either manually or due to a power failure -
the General Registers are automatically
stored in this save area. For example, if
the Pointer contains the address X'1FE0',
RO is stored in location X'1FE0', R1 is
stored in location X'1FE2', .... R14 is
stored in location X'1FFC', and R15 is
stored in location X'1FFE', When power
is restored or the initialize sequence term-
inates, the General Registers are fetched
from the save area and loaded into the hard-
A6-5
ware registers. The address placed in the
Register Save Pointer should be selected so
as not to overwrite current resident pro-
grams, or the dedicated core area. On
machines without the floating-point option,
it is convenient to store the fixed-point reg-
isters in the area normally used by the float-
ing-point registers. This is done by setting
the halfword at location X'22' to Zero. Half-
word core location X'0024' is used to save the
current PSW Status and Condition Code during
initialize sequences. Location X'0026' is used
to save the Current PSW Location Counter dur-
ing initialize sequences.
2.4 SYSTEM INTERRUPTS
System Interrupts are provided to detect the
presence of Illegal Instructions, Machine
Malfunctions, Fixed-Point Divide Fault,
Floating-Point Divide Fault, External De-
vice Interrupts, and High Speed Device In-
PROGRAM = Sa
\
HS INT
| PSW(SAVE)
|
| LOC(SAVE)
— BRANCH —
PSW(SAVE)
LOC(SAVE)
— BRANCH—
PSW(SAVE)
LOC(SAVE)
— BRANCH —
(SRVCA)
SERVICE
SUBROUTINE
terrupts. Interrupts are controlled by the
Status Field (bits 0 through 11) of the Cur-
rent Program Status Word. Individual bits
in the Status Field correspond to a particu-
lar category of interrupts. Generally, a
ZERO bit disables a corresponding category
of interrupts and a ONE bit enables a cor-
responding category of interrupts. There are
five additional PSW's, each associated with
a specific class of interrupt. The PSW's
are dedicated in core in pairs of fullword
locations. The New PSW defines the action
to be taken for each type of interrupt; the
Old PSW is a reserved storage area for the
Current PSW when the interrupt is taken.
After each User's instruction is executed,
the Processor tests for interrupts. If an
interrupt is found pending, and the corres-
ponding enabling bit in the Current PSW is
set, the Current PSW is saved in the Old
PSW save area for that interrupt, and the
New PSW replaces the Current PSW. This
action results in a branch to an appropriate
service subroutine.
(SRVCB) (SRVCC)
SERVICE
SUBROUTINE
SERVICE
SUBROUTINE
с
О HIGH SPEED INTERRUPT
> INTERRUPT CHAINING
—— —— —— INTERRUPT UN-CHAIN PATH
Figure A6-2. Interrupt Chaining
A6-6
3. CONSOLE OPERATION AND DISPLAY 4,
3.1 INTRODUCTION 5
This section describes the operation of the
Model 4 Display Panel, shown on Figure A6-3 6
The control console is comprised of six dis-
tinct elements:
1. Control Switches: POWER,
INITIALIZE, and EXECUTE.
REGISTER DISPLAY Rotary
Switch.
Sixteen Display/ Address
Switches.
Display of two 16-bit halfword
Registers.
3.2 CONSOLE OPERATING PROCEDURES
To Bring Up Power And Initialize The Svstem:
2. MODE CONTROL Rotary 1
Switch. -
Depress the latching POWER
Switch.
3. SPEED CONTROL Rotary 2. Depress the momentary
Switch, INITIALIZE Switch.
INTERDATA
REGISTER DISPLAY
OFF INST
RI4/15 PSW
JO
RIO/ II R2/3
R8/9 R6/7 R4/5
SPEED CONTROL A 3 4 5 6 7 8 9 10 12 13 14 15
OOOO OOOO OO OO OO
DISPLAY 2
o 1 2 3 4 5 6 7 8 9 10 Ii 12 13 14 15
SLOW | FAST OOOO OOOO OO
SNGL
MODE CONTROL
RUN ADRS
“er
HALT
FIX O MEMR
e
VARI
FIX MEMW
o
о i 2 3 4 5 6 7 8 9 10 |! 12 13 14 15
LUS TT] TT |
EXEC INIT PWR
POWER
Figure A6-3. Model 4 Display Panel
A6-7
To Shut Down Power To The System:
1.
Set the MODE CONTROL
Switch to a HALT position.
Depress the momentary
EXECUTE Switch.
Release the latching POWER
Switch.
To Begin Execution Of A Program:
Depress the EXECUTE
Switch.
Set the MODE CONTROL
Switch to MEMR.
Depress the EXECUTE
Switch.
The memory data is read from
Display Register 2. The mem-
ory address of the data being
displayed is in Display Register
1.
Each time the EXECUTE
Switch is depressed, suc-
cessive halfword memory
locations can be read.
The memory address is
automatically incremented
by 2 each time the EXE-
CUTE Switch is depressed.
To Write Into Memory:
The system must be in a HALT Mode.
1. Set the MODE CONTROL
Switch to ADRS.
2. Enter the program starting
address in the 16 address
switches.
3. Depress the momentary
EXECUTE Switch.
4. If the REGISTER DISPLAY
Switch is in the PSW position,
the updated location counter
will appear in Display Regis-
ter 2. Otherwise, the regis-
ter(s) selected will be displayed.
5. Set the MODE CONTROL
Switch to RUN.
6. Depress the EXECUTE
Switch.
To Read Memory From Display Registers
The system must be in a HALT Mode.
1. Set the MODE: CONTROL
Switch to ADRS.
2. Enter the Memory Read
A6-8
starting address in the 16
address switches.
The system must be in a HALT Mode.
QT
+
Set the MODE CONTROL
Switch to ADRS.
Enter the Memory Write
Starting address in the 16
address switches.
Depress the EXECUTE
Switch.
Set the MODE CONTROL
Switch to MEMW.
Enter the data to be written
into memory in the 16 data
switches.
Depress the EXECUTE
Switch,
To Disp
The memory data entered is
displayed in Display Register
2. The memory address which
was Written into, is displayed
on Display Register 1. To
Write into successive halfword
locations, repeat from step 5.
The location counter (memory
address) is automatically in-
cremented by 2 each time the
EXECUTE Switch is depressed.
lay The Instruction Register:
The system must be in a HALT Mode.
1.
Set the REGISTER DISPLAY
Switch to INST.
Depress the EXECUTE
Switch.
Two successive halfwords are
read from the memory address
specified by the PSW Location
Counter field.
If the first halfword is an RR
instruction, Displays 1 and 2
have the following format:
0 718 11/12 15
OP R1/M1 R2
0 718 11112 15
OP R1/M1 R2/X2
If the first halfword is an RX or RS instruc-
tion, Displays 1 and 2 have the following
format:
To Display The Program Status Word:
The system must be in a HALT Mode.
1.
0 1 2 3 45 6 7 8 9101112 13 14 15
Set the REGISTER DISPLAY
Switch to PSW.
Depress the EXECUTE
Switch.
The Current PSW Status and
Condition Code field appear in
Display 1, and the Location
Counter in Display 2. The for-
mat is as follows:
STATUS Condition Code
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LOCATION COUNTER
To Display The Fixed-Point General Registers:
The system must be in the FIX-HALT
Mode.
Set the REGISTER DISPLAY
Switch to select the desired
even/odd register pair.
Depress the EXECUTE
Switch.
The even register selected is
displayed in Display Register
1 and the odd register is dis-
played in Display Register 2.
To Display The Floating-Point Registers:
OP R1/M1 X2
31
ADDRESS
The system must be in the FLT-HALT
Mode.
Set the REGISTER DISPLAY
Switch to select the desired
register. The floating-point
registers have only even ad-
dresses.
A6-9
Depress the EXECUTE
Switch.
The selected floating-point
register (32-bits) is displayed
in Display Register 1 and 2 in
the following format:
011 718 15
S EXPONENT FRACTION
16 31
FRACTION
To Display Registers In The Variable Speed
Mode:
The system must be in a HALT mode.
1.
A6-10
Set the MODE CONTROL
Switch to ADRS.
Enter the program starting
address in the 16 address
switches.
Depress the EXECUTE
Switch.
Set the MODE CONTROL
Switch to fixed-point or
floating-point VARI.
Set the SPEED CONTROL
Switch to SNGL or to a
continuously variable SLOW-
FAST setting.
Set the REGISTER DISPLAY
Switch to select the desired
register(s).
Depress the EXECUTE
Switch to begin operation
of the program with dis-
play of the selected regis-
ters. If SNGL step was
selected, the EXECUTE
Switch is depressed to
cause single step execu-
tion of successive instruc-
tions.
8. The REGISTER DISPLAY
Switch setting and/or the
SPEED CONTROL Switch
may be changed without
first halting.
4. BINARY LOADER
4.1 Introduction
The expanded Model 4 repertoire permits
the use of a shorter binary loading program.
The binary loader is used to load the boot-
strap front end of the Absolute Loader, the
Relocating Loader, and the General Loader.
The Binary Loader must be manually loaded
into memory. See the Listing, Table A6-3.
The first two instructions of the Loader are
necessary only to satisfy the bootstrap pro-
gram being loaded.
4,2 Operating Procedures
1. Manually key the Binary Loader
program (Table A6-3) into core
memory.
2. Adjust the Device Definition
Table for the appropriate bi-
nary input device (BIN DV).
3. Select ADRS Mode.
4. Enter starting address X'0068'
on the Data Entry Switches.
5. Depress EXECUTE.
6. Place the tape to be loaded
into the reader. Tape leader
will be ignored.
7. Select RUN Mode.
8. Depress INITIALIZE, then
EXECUTE.
5.
TABLE A6-3.
BINARY LOADER
0068 C830 LOAD LHI 3,1
006A 0001
006C D3A0 LB 10, BINDV
006E 0078
0070 D500 AL 0,X'CF'
0072 00CF
0074 4300 B X'80'
0076 0080
0078 0294 BINDV DC Х'0294'
007A 0298 BOUTDV DC X'0298' Device Definition Table
007C 0294 SINDV DC X'0294' (See list below)
007E 0298 LISTDV DC X'0298'
TTY | HSPTR | HSPTP |} CARD | M. TAPE LINE PTR
BINDV 0294 0399 0595
BOUTDV 0298 0392 059A
SINDV 0294 0399 04A0 0595
LISTDV 0298 059A 0780
ADDITIONAL DATA A6-5. The High Speed Arithmetic and
The Model 4 Instruction Repertoire is shown
in Table A6~4. The Model 4 Instruction
Timing in Microseconds is shown in Table
Input/Output Option is shown in Table A6-6.
The Floatinr-Point Instruction Option is
The High-Speed
shown in Table A6-7.
Interrupt is shown in Table A6-8.
A6-11
MODEL 4 INSTRUCTION REPERTOIRE
TABLE A6-4
RR RR RX RX RR RS RX RS
00 20 40 STH | 60 STE 90 UNCH CO BXH DO STM| EO
01 BALR 21 41 BAL | 61 91 C1 BXLE DI IM | El
02 BTCR 22 42 BTC | 62 92 STBR C2 LPSW D2 STB| E2
03 BFCR 23 43 BFC | 63 93 LBR C3 D3 LB | E3
04 NHR 24 44 NH 64 94 C4 NHI D4 E4
05 CLHR 25 45 CLH | 65 95 C5 CLHI D5 AL | ES
06 OHR 26 46 OH 66 96 WBR C6 OHI D6 WB | E6
07 XHR 27 47 XH 67 97 RBR C7 XHI D7 RB | E7
08 LHR 28 LER 48 LH 68 LE 98 C8 LHI D8 ES
09 29 CER 49 69 CE 99 C9 D9 E9
0A AHR 2A AER 4A AH 6A AE 9A WDR CA AHI DA WD | EA
0B SHR 2B SER 4B SH 6B SE 9B RDR CB SHI DB RD | EB
0C MHR 2C MER 4C MH 6C ME IC CC SHRL DC EC
0D DHR 2D DER 4D DH 6D DE 9D SSR CD SLHL DD SS |ED
OE ACHR 2E 4E ACH | 6E 9E OCR CE SRHA DE OC | EE
OF SCHR 2F 4F SCH | 6F 9F AIR CF SLHA DF Al ¡[EF
A6-12
Table A6-5
MODEL 4 INSTRUCTION TIMING IN MICROSECONDS
RS RX
Instruction RR no index indexed no index indexed Comments
ACH 3.6 — - 6 6.4
AH 3.2 4 6 5.6 6
Al 8 - — 10 10.4
AL — — — 10+8. 8n 10.4+8.8n | device
BAL 3. 6 - - 4.8 5.2 dependent
BFC 4.8 - - 6/5.6 6.4/6 no br. /br.
BTC 4.8 - - 5. 6/6 6/6. 4 no br. /br.
BXH — 11.6 14 - -
BXLE - 11.2 14 - —
CLH 3.2 4 6 5.6 6
LB 3.6 — 5.2 5.6
LH 2.8 ‚ 2 5.2 4.8 5.2
LM — - - 8.4+3.2n 8. 8+3. 2n
LPSW - - - 8 8.4
NH 2.8 3.6 6 5.6 6
OC 6 — - 7.2 7.6
OH 2.8 3.6 6 5.6 6
RD 6 — — 8 8.4
SCH 3.6 - - 6 6.4
SH 3.2 4 6 5.6 6
SLHA — 5. 2+. 4п 7. 2+. An - -
SLHL 4+, 4n 6+. 4n ~ -
SRHA — 4. 8+. 4n 6. 8+. 4n - —
SRHL - 4+, 4n 6+.4n - -
SS 7.2 - - 8.4 8.8
STB 4,8 - — 6 6.4
STH — — — 6 6.4
STM — — ~ 8+3. 6n 8.4+3. 6n
WD 6 - - 7.2 7.6
XH 2.8 3.6 . 6 5.2 5.6
TABLE A6-6
HIGH SPEED ARITHMETIC AND INPUT/OUTPUT OPTION
DH 38/44 - - 38. 1/45 39/45 best/worst
MH 22. 8/35 - - 24/40 24/40 best/worst
RB 16+6. 5n - — 14+6.4n 14+6, 4n
WB 16+6n - — 14+6n 14+6n
n =
number of bytes or shifts
Note: I/O Execution Times assume 150 ns sync response.
A6-13
A-1176
TABLE A6-7
FLOATING-POINT INSTRUCTION SET OPTION
Instruction RR (min/ave/max) RX (min/ave/max)
if indexed, add .4 usec)
LE 21.6/22.2/34.4 23.2/23.8/40.0
STE — 14.0
CE 16. 4/20.4 18.0/22.0
AE 46.4/54.8/78.4 48.0/56.4/80.0
SE 48. 0/55. 6/87. 2 49.6/57.2/88. 8
ME 135. 6/156. 0/183. 6 137. 2/157. 6/184. 2
DE 188. 8/211. 6/243. 6 190.4/213. 2/244. 0
TABLE A6-8
HIGH SPEED INTERRUPT OPTION
Instruction RR RX
UNCH 14 us
High Speed Interrupt swap : 9.6 usec
OTHER TIMING FACTORS:
Memory cycle time : 1 usec
PSW swap time : 16 usec
Selector Channel transfer rate : 500 KBS
Direct Memory Access Channel transfer rate,
Read/Write
o
<
o
un
A6-14
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