INTERDATA Computer Systems Reference Manual

©
INTI ELE ALEA.
REFERENCE
MANUAL
Publication Number 29-004
November 1967
€
LINIE D.AU A.
REFERENCE
MANUAL
Publication Number 29-004
November 1967
(c) INTERDATA, inc. 2 Crescent Place, Oceanport, N.J. 07757
All Rights Reserved.
Printed in U.S.A.
CHAPTER 1
CHAPTER 2
TABLE OF CONTENTS
SYSTEM ARCHITECTURE ................. . . 0.0. 0.0. 0. 0.0.00
1.1 INTRODUCTION 2.240000 0 000 0 0 0 0 0 0 0 0 0000 ......
1.2 PROCESSOR ORGANIZATION .....Ñ.oocooXaoeo . . ..
1.2.1 General Registers ............ ........... .
1.2.2 Arithmetic/Logical Unit .....eQeeñeoeoceosse.es..
1.2.3 Control Unit ....e.ooocoocodooosooseseoo ooo
1.2.4 Memory............. ct ce ee ese tate se se
1.3 STORAGE WORD FORMATS © vv tv evo noses cs ete ees ea
1.3.1 Hexadecimal Notation ......ñw ocoeosoococoo ere
1.3.2 Arithmetic Data ....... ...... 600000 0000000
1.3.3 Logical Data......04.0.00 0000000 0 00 00000 0
1.3.4 Information Positioning .. 000000 0000000000
1.4 INSTRUCTION WORD FORMATS 404.000 00 0000000000
1.5 GENERAL REGISTERS AND STORAGE ADDRESSING ......
1.5.1 General Registers ....eQooéoeo,exooeoecooo e ecocoo
1.5.2 Storage Addressing .. 0.000000 0 00 0000 0 0 ..
1.5.3 Address Modification By Indexing .......0 0000.
1.6 PROGRAM STATUS WORD ...................... ..
1.6.1 Status ......... . 0. 0. 0. 2.0.0.0.0. 0.0.0.0. 0.0. 0. 0.0 .. ..
1.6.2 Condition Code .......0.00 0000 00 000 0 00 4 0 .
1.6.3 Instruction Address 000000000044 cts a tse ae
1.6.4 Instruction Execution .......0.0 000000000000 4
1.7 INTERRUPT SYSTEM ......0. 01000 0000 1 000 0 00000 0
1.7.1 Imterrupt Procedure ..... 0000 000 01000000 .
1.7.2 Acknowledgement of Interrupts . 0 0.0. 0 2... 0. 2. 0. 0. 0.0.08
1.7.3 Internal Interrupts « vo vo vo ttt tt tte vv ens nan
1.7.4 Power Failure .....oeocasodoooaooro orar
1.8 INPUT/OUTPUT SYSTEM .,.....eceeocecocdacdoooraco ..
1.8.1 Basic Input/Output Programming 00 000 00 0000006
1.8.2 Program Controlled Input/Output ............ .
1.8.3 Interrupt Controlled Input/Output ..............
1.8.4 Block Input/Output Programming ......ooecscocoo
1.8.5 Condition Code for Input/Output ...............
1.8.6 Direct Memory Access Channel ...............
INSTRUCTION REPERTOIRE ..........................
2.1 INTRODUCTION ... iii titi 00 0 0 0 0 80 a a a 0 a aa a a ae
2.2 LOAD AND STORE INSTRUCTIONS ..................
2.2.1 Load Halfword 0... ео
2.2.2 Store Halfword ,...eQocoocecoooooceoeeo ooo вое
2.2.3 Load Byte ....... Ce eee eae.
2.2.4 StoreByte ............ ........ 60000000 6
2.2.5 Load Program Status Word 2020200 0 ea 0 an au 0
pod
|
=
pt 1 1 |
N N N
1, 1. 1. 1 1 |
DD © © © © © DD 00 00 330 Ural OT pn pb ib i
pri pd pub ped pink ped ped ped ped fd fin punk ped feed punk funk feed peed fd pd ped
ii
2.3
2.4
2.6
2.7
2.8
2.9
TABLE OF CONTENTS (Continued)
FIXED POINT ARITHMETIC INSTRUCTIONS
e a 0. a + a * * . e.
2.3.1 Add Halfword ,....ooecsoosoocsooooooeco oro
2.3.2 Add With Carry Halfword ...00000000 00 00.0. 00.00
2.3.3 Subtract Halfword ......¢c ccc. . oe ..
2.3.4 Subtract With Carry Halfword .......¢c...... .
2.3.5 Multiply Halfword ..... cc eo eve toes .....
2.3.6 Divide Halfword ........... 0100006 ... .
LOGICAL INSTRUCTIONS . . cv see. 00000 .
2.4.1 — AND wHalfword............... 000 0 0 04 00 6
2.4.2 OR Halfword 0000000000004 enredo. oeaeo .
2.4.3 Exclusive OR Halfword 2.0.000000000 00000 0.08 .
2.44 Compare Logical Halfword ...ooeóorceeroorsoeoo
SHIFT INSTRUCTIONS ..... 0000000 00000000 ce es eee
2.5.1 Shift Left Halfword Arithmetic ............….
2.5.2 = Shift Right Halfword Arithmetic ...... . e...
2.5.3 — Shift Left Halfword Logical ......... ....
2.5.4 Shift Right Halfword Logical .......... ......
BRANCH INSTRUCTIONS 00000000000 0000 00 00.00.00. 008
2.6.1 Branch On True Condition ............ ......
2.6.2 Branch On False Condition .......... cee
2.6.3 Branch Unconditional .......¢¢.... ce eva ane
2.6.4 No Operation ,.......00... . o ..nreoo e...
2.6.5 BranchOnIndex High ............ . 0.0...
2.6.6 BranchOnIndexloworEqual............. «oe
2.6.7 — Branch And Link .......0.04000 0000000006 . .
EXTENDED MNEMONIC CODES FOR BRANCH
ON CONDITION . 0000000.000.0.0.0.0.0.0.0. 0.0.0.0. 0.0.0.0. 0.0. 0804 .
2.7.1 Branch On Zero 2000000000008. 000000. 0.0000 .
2.7.2 Branch On Not Zero „ .... . . . г... . roo aoosoeo
2.7.3 Branch On Plus.... 0 0 0 0 6 0000000 ct es ves .
2.7.4 Branch On Not Plus ........... ве ое .
2.7.5 BranchOn Minus 05000004000 ... e .. o
2.7.6 Branch On Not Minus ...... . e eccoroeo .
2.7.7 BranchOn Carry ...... .... ct eee .
2.7.8 Branch On Overflow cr ee cee ae a 00 00 60000
2.7.9 Branch On Low ....eo.ecsssoo. ce ee eee eee ..
2.7.10 Branchon Not Low ..... Ce eee ee ce ee ae .
2.7.11 Branch On Equal ...2.4.2.40 00000 0 00 0 0 8000 6
2.7,12 Branch On Not Equal .....4.44 00 440000 .. .
DEVICE INTERRUPT AND CONTROL INSTRUC TIONS......
2.8.1
2. 8.2
2.8.3
N N NN
O © DO ©
SC“ N
Acknowledge Interrupt ....
Sense Status
Output Command ....
INPUT/OUTPUT INSTRUCTIONS ........
Read Data.
Write Data .
Read Block .
Write Block
. + #4 & e
Фе » +6 +6 6 & & #4 E à @ $ 8 # a +
[J » » * ее LJ
+ a 5 0 8 & e a # °
“ a + 4 . .
ев . … + # #
+ + + + 6 = # 0 + # + e
. 9 +» #t # 6 E
a # à . . + +
. ° » . ©
ео & a ® 5 & 6 4 zz. »
2-12
2-12
2-13
2-14
2-14
2-15
2-15
2-16
2-17
2-17
2-18
2-18
2-19
2-19
2-20
2-21
2-22
2-22
2-23
2-23
2-24
2-24
2-25
2-25
2-26
2-26
2-27
2-27
2-28
2-29
2-29
2-30
2-31
2-32
2-32
2-33
2-33
CHAPTER 3
APPENDIX 1
APPENDIX 2
APPENDIX 3
APPENDIX 4
APPENDIX 5
TABLE OF CONTENTS (Continued)
CONSOLE OPERATION AND DISPLAY. . tt tc eves esses
INTRODUCTION. . ..Ñ.oQooccooccooocrcocrorocaoo reo
CONTROL SWITCHE Se 0 0000000000000 0000000000
MODE CONTROL SWITCH. 00000000000 00.0.0000. 0000
SPEED CONTROL SWITCH 2000000000000 000000000
REGISTER DISPLAY SWITCH 0000000000000 00 0. 0.000
DATA/ADDRESS SWITCHES ....eooeecacccsoccoooees
REGISTER DISPLAY. 000000000000 00002 00.00.00. 000
CONSOLE OPERATING PROCEDURES 00000000000 000
CO 43 ©) UI» LIN MH
CORE MEMORY ALLOCATION FOR GENERAL REGISTERS AND
PROGRAM STATUS WORDS. 0000000000000 000.0 00.0.0080. 00
SUMMARY OF INSTRUCTIONS - ALPHABETICAL BY NAME ...
SUMMARY OF INSTRUCTIONS - NUMERICAL BY OP CODE ...
ARITHMETIC REFERENCES...Ñ.oocovcscoooasoooooa re caeo
INPUT/OUTPUT REFERENCES....occocccooacocoooeocroo
ILLUSTRATIONS
1-1 INTERDATA Computer Systems, Typical Block Diagram ...
1-2 System Block Diagram ...e.oocécseososooacsocooooso
1-3 Storage Word Formats .......................
1-4 Arithmetic Word Formats .....+.+...............
1-5 Instruction Word Formats,...c_eococosoosoooooreococo
1-6 Program Status Word Format ....oeoccoscosresocoorooo
1-7 Status Byte Format ........................
3-1 General Purpose Display Panel 000 005 050010030000
A2-1
A3-1
A4-1
A5-1
pod
|
{4 1 1
со нок
но 00 UB 0
iii
CHAPTER 1
SYSTEM ARCHITECTURE
1.1 INTRODUCTION The INTERDATA Systems are designed for
h - is-
INTERDATA Computer Systems are modu- the user who has small-scale yet sophis
. , ticated requirements, and provide maximum
larly structured to provide a high degree of ea
alado + DAS ная system flexibility to solve a wide range of
flexibility in configuring application oriented industrial control and scientific computa
systems. The building blocks used in the maustrial co © ap
organization of a system are the Processor, tional problems.
Memory Modules, interface to peripheral These third generation units use dual in-
devices, and system modules. See Fig- line integrated circuits to provide excellent
ure 1-1, reliability, The systems are modular,
| Core Memory Modules
Memory Bus
E Model 2
[1 Model 3
™ 3 Registers
| Model 4 | я 4
Read-only Direct
Memory onlector Memory Access
q Channel
Multiplexor Bus (byte, 256 devices)
16
General
Selector | Bus (byte)
Special
Device
Halfword
Standard peripheral | (Halfword)
devices and system components
Ny
|
Figure 1-1. INTERDATA Computer Systems, Typical Block Diagram
1-1
furnishing the user with an expandable
building block structure that can be adapted
to a variety of system requirements.
Standard units can easily be configured into
operational systems for specialized re-
quirements,
Features of these systems include a 2
microsecond, 16-bit halfword memory that
is addressable and alterable to the 8-bit
byte level. Memory is field expandable
from 1024 bytes to 65,536 bytes.
All memory is directly addressable with the
primary instruction word; no paging or in-
direct addressing is required.
Sixteen general purpose registers, each 16
bits in width, can be used as accumulators
or index registers.
Register-to-register instructions permit
operations between any two of the 16 General
Registers, eliminating redundant loads and
stores.
A comprehensive instruction set includes ef-
ficient byte processing instructions, single
instructions for loop control which incre-
ment, test and branch on indexing values,
as well as instructions that test the condition
code and branch directly to any location in
memory.
Logical and arithmetic shift instructions can
shift up to 15 bit positions with a single
instruction,
À flexible Systems Interface includes an
integrated priority interrupt facility and
provides for connecting up to 256 devices.
The INTERDATA Systems have third gen-
eration data compatibility including ASCII
and EBCDIC information codes.
1.2 PROCESSOR ORGANIZATION
The various elements of the system are or-
ganized around the primary controlling
unit - The Processor, The Processor con-
tains facilities for:
1. Arithmetic and logical processing
of data
2. Sequencing instructions in the re-
quired order
3. Fetching and storing information
4, Addressing memory
5, Initiating or controlling communi-
cations with external devices
6. Changing states in response to
interrupts
The Processor consists of a group of six-
teen 16-bit General Registers, an Arithmetic/
Logical Unit (ALU), and a Read-Only-Memor y
(ROM) control unit. See Figure 1-2,
1.2.1 General Registers
The General Registers can be used as ac-
cumulators in fixed-point arithmetic and
logical operations, or as index registers
in address arithmetic and indexing opera-
tions. Each register has a capacity of six-
teen binary digits, which is one halfword.
For some operations, such as multiplica-
tion and division, two adjacent registers
are coupled to form a 32-bit fullword. In 8-
bit byte operations the rightmost 8 bits of
a General Register are used.
1.2.2 Arithmetic/Logical Unit
The Arithmetic/Logical Unit (ALU) proc-
esses both binary integers and logical in-
formation. The operands are located in the
General Registers and/or core memory.
Fixed-point data is treated as signed, 15-
bit integers in the halfword format, or as
signed, 31-bit integers in the fuliword
format. Positive numbers are expressed
in true binary form with a sign bit of zero.
Negative numbers are represented in two's
complement form with a sign bit of one.
The numeric value of zero is always rep-
resented as positive, Table 1-1 shows
several examples of the number repre-
sentation used in INTERDATA Systems.
All fixed-point operations are performed
upon one operand in a General Register
with the other operand in either a General
Register or a core memory location.
PROCESSOR
O 112 1516 3
LOCATION AN
STATUS сс COUNTER {
PROGRAM STATUS WORD
0 78 112 1516 31
o | | % ADDRESS Cam
INSTRUCTION REGISTER
0 5
RO
RI
= GENERAL A
> REGISTERS
RIA
RIS
1
CORE MEMORY
||
|
Ib
+
SZ
1
—
Nu
ARITHMETIC / LOGICAL UNIT
— —— —— — — — o.
1 £
ADDRESS DATA
HIGH SPEED MEMORY BUS
0 7
SCR
ADDRESS DATA
SOR DIRECT MEMORY
ACCESS CHANNEL
Ls
=
DEVICE DEVICE
CONTROLLER CD CONTROLLER
N
V
TELETYPE ADDRESS DATA
лы SELECTOR
CHANNEL
MULTIPLEXOR BUS
5 7
4 4 7g
Ц
DEVICE
CONTROLLER
DEVICE
CONTROLLER
DEVICE
CONTROLLER
DEVICE
CONTROLLER
, SELECTOR CHANNEL BUS
A
1
DEVICE
CONTROLLER
Figure 1-2, System Block Diagram
Ц
DEVICE
CONTROLLER
1-3
TABLE 1-1. EXAMPLES OF NUMBER
RE PRESENTATION
Number | Decimal Binary
215.1 | 32767 | 0111 1111 1111 1111
9° 1 0000 0000 0000 0001
0 0 | 0000 0000 0000 0000
29 1 1111 1111 1111 1111
-217 | -32768 | 1000 0000 0000 0000
Multiple-precision arithmetic operations
are made convenient by the two's comple-
ment representation, and by recognition of
the carry/borrow from one word to another.
1.2.3 Control Unit
The Processor operates under the direction
of a control unit which has a pre-wired
micro-program contained in the Read-Only-
Memory (ROM). The micro program is a
sequence of micro operations which fetches
the Processor instructions, decodes them,
and processes the operands located in the
General Registers and core memory
locations.
For example, to fetch an instruction, the
micro-program loads the memory address
register with the instruction address, com-
mands a memory read operation, and when
the memory data is ready, transfers the
content of the memory data register to the
working register.
1.2.4 Memory
INTERDATA Systems provide for connection
of multiple memory blocks on a Memory Bus
to the Processor. Each memory block con-
sists of a magnetic core memory plane with
independent Read/Write Control. All memory
blocks share a 16-bit halfword Memory Data
Register and a Memory Address Register.
The 16-bit halfword data register permits
all 16-bit instructions and fixed-point or
logical data to be handled in a single mem-
ory cycle. Multiple halfword data requires
an additional memory cycle for each 16-bit
1-4
halfword. Byte operations are performed
by selectively manipulating the right or
left 8 bits of the 16-bit halfword.
Memory elements can be expanded to a
maximum dynamic addressing range of
65,536 8-bit bytes or 35,768 16-bit
halfwords.
The optional Memory Parity feature pro-
vides for checking of all data transfers in
and out of memory.
1.3 STORAGE WORD FORMATS
The INTERDATA Instruction Set manipu-
lates data of three different word lengths:
8 bit bytes, 16 bit halfwords or 32 bit full-
words. In each format the bits are num-
bered from left to right, starting with the
number zero. The format for each word
length is shown on Figure 1-3.
BYTE
O
HALFWORD
O 718 15
FULLWORD
0 7/8 _ she 23124 3
Figure 1-3. Storage Word Formats
1.3.1 Hexadecimal Notation
Binary information is expressed in hexa-
decimal notation (base 16) in the INTER-
DATA Systems. Four binary bits of
information can be expressed by a single
hexadecimal digit, Thus, byte information
can be expressed by a string of two hexa-
decimal digits, halfword information by four
hex digits, and fullword information by 8
hex digits. Table 1-2 lists hexadecimal,
binary, and decimal equivalents,
TABLE 1-2. HEXADECIMAL NOTATION
Hexadecimal Binary Decimal
0 0000 0
1 0001 1
2 0010 2
3 0011 3
4 0100 4
О 0101 О
6 0110 6
7 0111 7
8 1000 8
9 1001 9
A 1010 10
B 1011 11
C 1100 12
D 1101 13
E 1110 14
F 1111 15
1.3.2 Arithmetic Data
The basic arithmetic operand is the 16-bit
halfword. In multiply and divide operations,
32-bit fullwords are manipulated. See Fig-
ure 1-4,
HALFWORD
ofl 15
5 INTEGER
Ol IS
S| INDEX QUANTITY
FULLWORD
Ol 31
S INTEGER PRODUCT
S DIVIDEND
Figure 1-4, Arithmetic Word Formats
The halfword arithmetic operand matches
the address field of an instruction, permitting
fixed-point arithmetic instructions to be used
for address arithmetic. Arithmetic, logical,
and shift instructions can also be used for
address manipulation or computation.
1.3.3 Logical Data
Logical information is handled as 16-bit
halfwords or as 8-bit bytes. Halfword
operations are performed on all 16 bits of
an operand located in memory or a General
Register. Logical data is subject to such
operations as AND, OR, EXCLUSIVE OR,
and COMPARE LOGICAL.
Load Byte and Store Byte instructions are
provided to facilitate byte manipulation.
These instructions, when combined with
indexed addressing, enable the processing
of input/output character strings.
1.3.4 Information Positioning
Core memory locations are numbered con-
secutively, beginning at location 0000, for
each eight bit byte, Since the address field
of an instruction word is 16-bits in length,
each of the 65,536 bytes in memory is
directly addressable with the primary in-
struction word,
The INTERDATA System transmits binary
information between memory and the Proc-
essor as 16-bit halfwords. The instruction
being performed determines if the address
specified is that of a byte, a halfword or a
fullword. If a byte of information is de-
sired, either the left or right byte of the
halfword read from memory is manipulated
as determined by the specific address. If
a halfword of information is desired, the
entire 16 bits read from memory are used.
If a fullword is desired, a second 16 bits
is read from memory and combined with
the original halfword.
Bytes of information are addressed by their
specific hexadecimal address. A group of
bytes combined to form a halfword or a full
word are addressed by the leftmost byte in
the group. Halfwords are positioned so
that the address is a multiple of 2, Full-
words are positioned so that the address is
a multiple of 4, Table 1-3 illustrates the
addressing scheme, Table 1-4 lists the
valid last hexadecimal digits for each type
of addressing.
1-5
TABLE 1-3. MEMORY ADDRESS DATA
Hexadecimal Address
0050 0051 0052 0053 0054 0055 0056 0057
Hexadecimal 01 23 45 67 89 AB CD EF
Contents
ÉL a) Nt”
Word Length Byte Byte Byte Byte ~ Byte _ Byte byte Byte Byte
Positions Halfword Halfword Halfword Halfword
Fullword Fullword
Refer to Table 1-3. If the address specified
were 0050:
1. A byte oriented instruction would
extract the data constant 014 gas its
operand.
2. A halfword oriented instruction
would extract the data constant
012316 as its operand.
3. A fullword oriented instruction
would extract the data constant
01234567, 6 as its operand.
TABLE 1-4. PERMISSIBLE ADDRESSES
Word Length Last Hex
Desired Digit of Address
Byte any
Halfword 0,2,4,6,8,A,C,E
Fullword 0,4,8,C
14 INSTRUCTION WORD FORMATS
Instructions in INTERDATA Systems have
three formats:
1, Register to Register [RR]
2. Register to Indexed Memory [RX]
3. Register to Storage [RS]
In general, each format specifies three
things: The operation to be performed, the
address of the first operand, and the ad-
dress of the second operand. The first
operand is normally a General Register
which contains the result of a previous op-
eration, The second operand is normally
1-6
the contents of a General Register, the
contents of a core memory location, or a
data constant used as the other participat-
ing operand.
A 16-bit halfword format is used for reg-
ister to register operations. A 32-bit full-
word format is used for the register to
indexed memory, and the register to storage
formats. The specific formats are shown
on Figure 1-5,
16-BIT HALFWORD
REGISTER-TO-REGISTER [RR]
O 718 Ina 15
OP RI R2
32-BIT FULLWORD
REGISTER TO INDEXED MEMORY [RX]
O 718 11H12 15116 31
ОР R1 | x2 A
REGISTER-TO-STORAGE [RS]
O 718 112 JSI6 3]
ОР R1| x2 A
Figure 1-5, Instruction Word Formats
The 8-bit OP field in all three formats
specifies the machine operation to be per-
formed. The operation code can be written
as two hexadecimal characters.
The 4-bit R1 field in the three instruction
formats specifies the address of the first
operand. The R1 field is normally the ad-
dress of a General Register and is written
as one hexadecimal character.
The 4-bit R2 field in the RR instruction
format specifies the address of the second
operand. The R2 field is always a General
Register address and is written as one
hexadecimal character.
The 4-bit X2 field in the RX and RS formats
specifies a General Register whose content
is used as an index value. The X2 field is
always the address of a General Register
and is written as a single hex character.
The 16-bit A field specifies a memory ad-
dress in the RX format, or contains an inte-
ger value to be used as an immediate operand
in the RS format. It is written as a string of
four hex characters.
The RR instructions are used for operations
between two General Registers, The first
operand is the contents of the register
specified by the R1 field of the instruction
word. The second operand is the contents
of the General Register specified by the R2
field,
The RX instructions are used for operations
between a General Register and memory
with the option of indexing, The first oper-
and is the General Register specified by the
R1 field of the instruction word. The second
operand is the contents of the memory loca-
tion specified by the A field of the instruc-
tion word, or by the sum of the A field and
the contents of the General Register speci-
fied by the X2 field if indexing is specified.
In the RS instructions, the first operand is
the contents of the General Register speci-
fied by the R1 field of the instruction word.
The second operand is the number contained
in the A field, or the number generated by
adding the A field to the contents of the
General Register specified by the X2 field
if indexing is specified, The second oper-
and of an RS instruction specifies the num-
ber of bit positions in shift instructions, or
forms the second operand in immediate in-
structions. An immediate operand is two
bytes of data used as an operand and carried
in the halfword address field itself, The
value in the address field is treated as a
signed integer instead of a memory location
address,
For the Branch on Condition instructions
the first operand is the M1 field. This
field is a 4-bit mask which is to be tested
against the condition code contained in the
Program Status Word.
Table 1-5 summarizes the first and second
operand designations for each instruction
format.
TABLE 1-5. DESIGNATIONS FOR
FIRST AND SECOND OPERANDS
First The contents of | RR, RX
operand: | General Regis- | and RS
ter R1 (R1)
The M1 field RR and RX,
Branch on
Condition
Second The contents of | RR
operand: | General Regis-
ter R2 (R2)
The contents of | RX
the address de-
rived by adding
the A field and
the contents of
Register X2,
(A + (X2))
The A field plus | RS
the contents of
register X2,
A + (X2)
All instructions are aligned on halfword
boundaries. The RR instruction format is
a 16-bit halfword; the RX and RS formats
are 32-bit fullwords which are treated as
two halfwords for alignment purposes.
This permits mixing of halfword and full-
word instructions without the requirement
of halfword No Operation instructions to
force fullword instruction alignment.
1.5 GENERAL REGISTERS AND STORAGE
ADDRESSING
1.5.1 General Registers
The sixteen General Registers function as
accumulators or index registers in all
arithmetic and logical operations. Each
1-7
General Register is a 16-bit halfword соп-
sisting of two 8-bit bytes. For arithmetic
operations, bit zero (leftmost position) is
considered the sign bit. Bit one is the most
significant bit.
The General Registers are numbered from
zero to fifteen (decimal) which is written in
hexadecimal notation as 0, 1, 2, 3, 4, 5, 6,
7, 8,9, A, B,C, D, E, and F, General
Register addresses are the only addresses
permitted in the R1, R2 and X2 fields of an
instruction word.
The General Registers have not been given
specific functional assignments, However,
the following operational restrictions should
be noted:
1. It is not possible to use General
Register zero as an index register,
In the RX and RS instruction for-
mats, a zero entry in the X2 field
indicates that no indexing is to take
place.
2, The first operand (Rl) must specify
an even numbered General Register
for multiplication and division
operations.
3. The first operand (R1) for the
Branch on Index instructions speci-
fies the first of three general reg-
isters. General Register D is the
maximum value for Rl in this case.
1.5.2 Storage Addressing
Locations in core memory are addressed by
the RX instruction. The address portion, A,
of the instruction is a 16-bit halfword, mak-
ing it possible for the address field to
specify all 65,536 bytes, the maximum
available memory.
If an address specified is greater than the
highest memory location available, no mem-
ory access takes place, and a word consist-
ing of all zeros is used in place of the word
normally read from memory.
Programs cannot be looped from the highest
memory location back to location 0000.
1-8
1.5.3 Address Modification by Indexing
The General Registers in INTERDATA
Systems facilitate address modification.
Fifteen different General Registers may be
used as index registers for this purpose.
If the contents of the A field of an instruc-
tion word are to be modified, the address
of the General Register, whose content is
to be used as the modifier, is placed in the
X2 field of the instruction word. During
decoding of the instruction word, the con-
tents of the specified index register is
added to the A field to obtain the effective
address of the second operand. The index
value in a General Register may be signed
to permit indexing in either direction.
All of the General Registers except Gen-
eral Register Zero may be used as index
registers. If the X2 field of the instruction
word is zero, no indexing is specified, and
the A portion of the instruction word is not
modified. Thus, General Register Zero
cannot be used as an index register,
1.6 PROGRAM STATUS WORD
The 32-bit Program Status Word (PSW)
contains the information required for pro-
gram execution, The PSW has a 12-bit
Status field, a 4-bit Condition Code field,
and a 16-bit Instruction Address field, See
See Figure 1-6,
P SW
О 112 15116 3!
STATUS CC |INSTRUCTION ADDRESS
Figure 1-6, Program Status Word Format
In general, the Program Status Word is
used to control instruction sequencing and
to store indications of the status of the sys-
tem in relation to the program currently
being executed. The active or controlling
PSW is referred to as the current PSW.
When a program interrupt occurs, the cur-
rent PSW is automatically preserved for
subsequent reinstatement or inspection. By
loading a new PSW, the status of the Proc-
essor can be changed.
1.6.1 Status
The status of the current user program is
defined by bits 0 through 11 of the Program
Status Word. When bit 0 is set the Proc-
essor is halted in a high speed, interrup-
table wait loop during which interrupts will
be recognized immediately. When bit 0 is
reset, the Processor is active and inter-
rupts which are enabled will be recognized
after execution of the current instruction.
Bits 1, 2 and 3 are mask bits for interrupts.
Assignment of the Status bits is listed on
Table 1-6,
TABLE 1-6. PSW STATUS BIT
TABLE 1-7. PSW CONDITION CODE
BIT ASSIGNMENTS
ASSIGNMENTS
PSW Bit Assignment
0 Wait state
1 External Interrupt Enable
2 Machine Malfunction Inter-
rupt Enable
3 Divide Fault Interrupt Enable
4 thru 11 | Not assigned
1.6.2 Condition Code
The 4-bit Condition Code (CC) of the Pro-
gram Status Word is set after execution of
arithmetic, logical, shift, and input/output
instructions. In general, the condition code
bits 12 through 15 indicate Carry, Overflow,
Greater, and Less, in that order. The con-
dition code setting has a different interpre-
tation when set by an input/output instruction
and is described in that section.
Following an arithmetic operation the condi-
tion code indicates whether the result was
greater or less than zero, whether a carry
or borrow took place, and whether an over-
flow has occurred.
Assignment of Condition Code bits is listed
on Table 1-7,
PSW Bit Assignment Symbol
12 Carry/Borrow (C)
13 Overflow (V)
14 Greater than zero (G)
15 Less than zero (L)
1.6.3 Instruction Address
The 16-bit Instruction Address field of the
Program Status Word specifies the location
of the next instruction to be fetched and
processed. The sixteen bit address field
has the capability of addressing the maxi-
mum core memory of 65,536 bytes.
After instruction execution, the Instruction
Address Field is incremented by 2 if the
executed instruction was in the halfword RR
format (2 bytes). The Address Field is in-
cremented by 4 if the executed instruction
was in the fullword RX or RS format (4
bytes).
1.6.4 Instruction Execution
During normal processing of a program,
instructions are fetched from the location
specified by the Instruction Address, the
instruction is executed, the Instruction Ad-
dress is incremented, and another fetch
and execute cycle begins.
This sequence can be changed when a two-
way conditional choice is required, for en-
trance and return to and from a subroutine,
or for iterative groups of instructions,
called loops.
Subroutine linkage provides for the intro-
duction of a new Instruction Address and
preservation of the incremented current
Instruction Address as the location for re-
turn to the main program. The instruction
that provides this facility is the Branch and
Link instruction.
1-9
Decision making is implemented by the
Branch on Condition instructions which in-
spect the setting of the 4-bit Condition Code
(PSW 12:15).
Loop control can be performed by the condi-
tional branch when it tests the outcome of
arithmetic and counting operations. For
frequent combinations of such tests, the
Branch on Index instructions provide a con-
venient means of performing these tasks.
1.7 INTERRUPT SYSTEM
System interrupts are provided to detect the
presence of illegal instructions, machine
malfunctions, divide faults, and requests
for service from external devices. The
control of interrupts centers around the
Status field of the Program Status Word
(PSW (0:11)). A zero in this field disables
an interrupt; a one in this field enables an
interrupt.
The PSW which defines the operating status
of the Processor is called the current PSW,
There are four additional Program Status
Words, each associated with a specific class
of interrupt. The new PSW defines the ac-
tion to be taken for each type of interrupt;
the old PSW is a reserved storage area in
which the current PSW is placed when an
interrupt is recognized.
Each new PSW re-defines the status of the
machine, usually inhibiting interrupts of its
own class, or possibly all interrupts. The
instruction address field of each new PSW
specifies the starting location of the sub-
program to service the interrupt condition.
Exit from an interrupt service sub-program
is accomplished by the Load Program Status
Word instruction specifying the stored old
PSW, This restores the machine status and
the instruction address which was current at
the time the interrupt occurred.
1.7.1 Interrupt Procedure
After execution of each instruction, .the
Processor interrogates for interrupts. If
an interrupt is found pending and the ap-
propriate bit in the Status Field of the PSW
is a one (enabled) the interrupt will take
1-10
place. The current PSW is automatically
stored as the old PSW for the class of inter-
rupt which is to be serviced and the new
PSW for the class of interrupt being serv-
iced becomes the current PSW. After the
sequence of instructions servicing the in-
terrupt has been completed, the old PSW
for the class of interrupts being Serviced is
normally loaded and becomes the current
PSW.
Note that the new PSW location is not altered
by this interrupt procedure, so that subse-
quent interrupts of the same class will be
serviced in the same manner. The old PSW
location serves as a temporary storage
register for exit from the interrupt service
sub-program and may vary each time an
interrupt request is processed.
If an interrupt request occurs and the ap-
propriate bit in the Status Field of the PSW
is a zero (disabled) an interrupt will not
occur and the request is ignored.
External interrupt requests from peripheral
devices remain pending, that is the inter-
rupt request will be repeated after execu-
tion of each instruction, until enabled by
the PSW and serviced by the program.
Program restart use of the Initialize switch
clears pending interrupts from external
devices.
1.7.2 Acknowledgement of Interrupts
The Acknowledge Interrupt instruction
clears the interrupt request and returns
the device address and status byte from the
peripheral causing the interrupt. The right-
most 4 bits of the status byte are copied
into the condition code (PSW 12:15) while
the leftmost 4 bits of the status byte have
meanings unique to each peripheral device.
See Figure 1-7, The device number and
CC | pe to(PSW (12:15))
bits
| STATUS
BYTE
Figure 1-7, Status Byte Format
device status byte provide sufficient infor-
mation to determine the cause and action
required by any external interrupt.
1.7.3 Internal Interrupts
Interrupts which originate in the Processor
are the Illegal Instruction, Machine Mal-
function, and Divide Fault Interrupts.
The Illegal Instruction interrupt is not rep-
resented by an enabling bit in the PSW, and
is therefore always operative. An illegal
instruction is defined as an operation code
which cannot be decoded into a legal repre-
sentation for processing. No attempt is
made to execute the illegal instruction, nor
is the instruction address field of the PSW
incremented. Therefore, the old PSW
stored as a result of the illegal instruction
interrupt points to the address of the illegal
instruction.
The Machine Malfunction Interrupt, enabled
by bit 2 of the Program Status Word, is in-
dicative of a Processor failure from which
no programmed recovery can be made.
Causes of the machine malfunction interrupt
are memory parity error or a power failure.
When the memory parity option is present in
the Processor, a parity bit is appended to
each byte of memory. The parity bit is set
to maintain odd parity. That is, if a mem-
ory byte contains an odd number of ones the
parity bit is zero; if the memory byte con-
tains an even number of ones, the parity bit
is one.
Parity is recomputed for each byte transfer,
and the parity bits of the transferred byte
and the original byte are compared. If the
parity bits are different, and bit 2 of the Pro-
gram Status Word is set to enable the inter-
rupt, a Machine Malfunction Interrupt is
generated.
The Divide Fault interrupt, enabled by
bit 3 of the Program Status Word, is indica-
tive of quotient overflow, The interrupt
takes place prior to alteration of the operand
registers, permitting the interrupt service
subroutine to examine these values.
1.7.4 Power Failure
When power failure is detected, the instruc:
tion being executed is completed and the
Processor and memory are put in a locked
state. Power up will initialize the Ргос-
essor to the status at the time of power
failure. The Processor will be placed in
the Halt mode, from which normal execu-
tion may proceed.
1.8 INPUT/QUTPUT SYSTEM
INTERDATA Systems can transfer informa-
tion between the Processor and peripheral
devices in several modes:
1. A single 8-bit byte at a time
through the General Registers,
2. A single 8-bit byte at a time
through core memory.
3. A block of information at a time
(string of bytes) under Processor
control.
4, A block of information directly
from, or to memory and the
peripheral device under control of
an optional Selector Channel.
1.8.1 Basic Input/Output Programming
In general, any data transfer requires a
series of operations concerned with the de-
vice or system with which information is
being transferred. Before data can be
transferred, the device or system must be
able to accept a command. The Output
Command instructs the device to perform
such functions as: switch to send mode,
switch to receive mode, go forward, etc.
Once the device is in the correct mode of
operation, the data transfer can take place.
There are two methods of input/output pro-
gramming. The first method, called pro-
gram controlled, interrogates the device to
determine if it is ready to transfer data,
and waits if necessary until transfer can
take place. The second method, called in-
terrupt controlled, permits the device to
demand service when the device itself is
ready for data transfer,
1-11
Either method of input/output, program
controlled or interrupt controlled, can be
used with the Read Data and Write Data
instructions to transfer information to or
from the General Registers or core
memory.
1.8.2 Program Controlled Input/Output
Program controlled data transfer can be
accomplished in many ways. The exact
sequence of instructions depends on the
particular device with which data transfer
is to take place. The following steps
describe the general approach to program
controlled data transfer.
1. An Output Command which specifies
the function to be performed is
sent to the device.
2. A Sense Status instruction sets the
condition code, indicating the state
of the device, i.e., busy, device
unavailable, etc.
3. A Branch on True Condition in-
struction waits for the not true
condition. In this case the branch
is taken back to the sense status
instruction. The effect of this is to
produce a wait loop until the device
is able to transfer data.
4, When the Branch on True Condition
fails, the device is ready to trans-
fer data. The next instruction,
Read Data or Write Data, causes
the data transfer to take place
5. If more than a single byte of infor-
mation is to be transferred,
additional steps are required for
indexing and storing the input data.
A typical procedure would be:
1. Output Command
2. Initialize general registers
with an index value and
increment
3. Sense Status
1-12
4, Branch on True Condition to
sense status if not ready
5. Read Data, indexed
6. Branch on Index to cause in-
crement and test for number
of characters input.
1.8.3 Interrupt Controlled Input/Output
Interrupt controlled data transfer involves
the same basic principles used for pro-
gram controlled data transfer. The im-
portant difference is that the device is
permitted to interrupt when ready to
transfer data. The wait loop is eliminated
and the time saved can be used for inter-
nal processing. The following steps de-
scribe the general approach to interrupt
controlled data transfer,
1. Device signals Processor with
an interrupt request.
2. An Acknowledge Interrupt in-
struction returns the device
address and status byte to the
Processor.
3. A Read/Write Data instruction
causes data transfer to take
place.
1.8.4 Block Input/Output Programming
The Optional Read Block and Write Block in-
structions greatly simplify programming of
strings of data. The single instruction
causes information to be transferred be-
tween a device and sequential locations in
core memory. Transfer is terminated when
a pre-determined location is reached, or
when an unusual device status is encountered.
Prior to block transfer, an Output Com-
mand and Sense Status instruction are used
to specify the function and test the status
of the device. The block transfer in-
struction can then perform all remaining
steps of input/output. Note that the com-
plete attention of the processor is given to
the data block transfer and that normal
processing will not resume until comple-
tion of the instruction.
1.8.5 Condition Code for Input/Output
The 4-bit Condition Code (CC) of the Pro-
gram Status Word is set after execution of
input/output instructions and the device in-
terrupt and control instructions. The inter-
pretation of the condition code after an
input/output instruction differs from the
setting caused by arithmetic and logical
operations.
Following an input/output or device control
instruction, the condition code indicates the
device response such as available, busy, or
unavailable, It is important to note that data
transfer cannot take place until all bits of the
condition code are zero.
Assignment of Condition Code bits for input/
output is shown on Table 1-8.
TABLE 1-8, PSW CONDITION CODE BIT
ASSIGNMENTS 1/0 INSTRUCTIONS
PSW Bit Assignment Mnemonic
12 Device busy (BSY)
13 Examine status (EX)
14 End of medium (EOM)
15 Device unavailable (DU)
The Device Busy condition indicates that the
device is not available or ready for transfer
of data.
An Examine Status condition indicates that
the leftmost 4-bits of the device status byte
must be tested to fully determine the device
condition.
If, after a Sense Status or Acknowledge
Interrupt instruction, the examine bit of the
condition code is set, and the leftmost 4 bits
of the status byte are zero, an improper
device response has occurred or a power
down is in process. The data transfer is
aborted and the device is released. If the
examine bit is set after a Read or Write,
or Output Command Instruction, an im-
proper device response has occurred or a
power down is in process. A Sense Status
instruction should be executed and the left-
most 4 bits of the status byte tested to de-
termine the nature of the failure.
The End Of Medium condition is caused by
the presence of a code or indicator at the
end of a punched card, or paper or mag-
netic tape.
The Device Unavailable condition indicates
that the device is mechanically unable to
transfer data.
1.8.6 Direct Memory Access Channel
The Direct Memory Access Channel pro-
vides high speed data transfer between
core memory and a single external device,
Data is transferred 16 bits in parallel at
up to the cycle rate of the memory.
The DMAC operates on a cycle stealing
basis; that is, when the channel is ready
to transfer data, a memory service re-
quest is generated causing the memory
to service the DMAC at the conclusion of
its present cycle. The transfer takes
place autonomously, the Processor having
no awareness of the transfer, and with no
apparent interruption to normal
processing.
1-13
2.1
CHAPTER 2
INSTRUCTION REPERTOIRE
INTRODUCTION
The instruction repertoire has been grouped
by function in this Chapter.
1.
2.
The use and
The name of the instruction.
Instruction word chart for every
format the instruction uses, in-
cluding: mnemonic operation code,
and first and second operand desig-
nations in the correct assembler
format. The format type is desig-
nated by [RR], [RX], or [RS]. An
instruction diagram with hexa-
decimal operation code and the
locations of all fields is also
provided.
A description of instruction
operation.
A diagrammatic representation of
instruction operation.
A chart illustrating the possible
variations of the condition code in
the Current Program Status Word
as a result of performing the in-
struction. A 1 indicates set, a
zero indicates reset. It is impor-
tant to note that any instruction
which changes the condition code
can change all four bits. The con-
ditions listed on the chart are only
those conditions which are meaning-
ful after a particular instruction.
Other bits may be changed, but
their condition is not meaningful,
A programming note to provide ad-
ditional pertinent or clarifying
information,
operation of each instruction is presented in
the following format:
1.
4
:
|
ADD HALFWORD
AHR RI, R2 [RR]
O 718 jz 15
ЙА R1 | R2
AH RI, A(X2) [RX]
O 718 11112 1SH16 3]
4A RI | X2 A
AHI RI, A(X2) [Rs]
O 718 112 15/16 3!
CA RI | X2 A
The 16-bit second operand is algebrai-
cally added to the General Register
specified by R1. The resulting sum is
contained in R1, the second operand is
unchanged.
(Rl) € (В1) + (R2) [RR]
(Rl) <—— — (R1) + (A + (X2) ) [RX]
(Rl) «—— (Rl) + A +(X2) [RS]
RESULTING CONDITION CODE:
1213/14/15]
CIVIGIL
010 | Sum is zero.
0|1 | Sum is less than zero.
1/0 | Sum is greater than zero.
1 Arithmetic overflow.
1 Саггу
PROGRAMMING NOTE
6.
The ADD HALFWORD IMMEDIATE
(AHI) instruction produces a value which
is the algebraic sum of the address field
itself plus the content of a General
Register index (X2), plus the first oper-
and General Register (R1),
2-1
The symbols and abbreviations used in the
instruction diagrams are defined as follows:
2-2
(>)
R1
R2
M1
(0:7)
(8:15)
(16:31)
PSW
CC
Parentheses. Read as "the
content of ...".
Arrow. Read as "is replaced
by ..." or "replaces ...".
The 16-bit halfword address
which is a part of the RX and
RS instructions.
The General Register address
designated as the first
operand.
The General Register address
designated as the second
operand of an RR instruction.
The address of a General
Register the content of which
is used as an index. value.
Mask of 4 bits specifying
Branch on Condition testing.
A bit grouping within a byte,
a halfword, or a fullword.
Read as "0 thru 7 inclusive,
"bits 8 thru l5inclusive", etc.
Program Status Word of 32
bits containing the Status,
Condition Code, and current
instruction address.
Condition Code of 4 bits con-
tained in the PSW,
Carry Bit contained in the
condition code (bit 12 of PSW).
Overflow Bit contained in the
condition code (bit 13 of PSW).
Greater Than bit contained in the
condition code (bit 14 of PSW).
Less Than bit contained in the
condition code (bit 15 of PSW).
Arithmetic operations - Add,
Subtract, Multiply, and Divide
respectively.
Logical comparison
2.2 LOAD AND STORE INSTRUCTIONS
The load and store instructions transfer in-
formation between core memory and the
General Registers or the Program Status
Word. Load and store operations are per-
formed on 8-bit bytes, 16-bit halfwords, or
32-bit fullwords.
2.2.2 Store Halfword
STH R1, A(X2)
0
7
8
12
IS
[Rx]
31
49
К!
X2
2.2.1 Load Halfword
LHR R1, R2 [RR]
O 718 le 15
08 RI R2
LH R1, A(X2) [RX]
O 718 112 156 3|
48 RI | X2
LHI RI, A(X2 [Rs]
O 718 2 15146 31
C8 RI | X2 A
The 16-bit second operand is loaded into the
General Register specified by R1. The
second operand is unchanged.
(Rl) «— (R2) [RR]
[RX]
[Rs]
(В1) + — (A + (X2))
(Rl) <+—— A+ (X2)
Resulting Condition Code:
1213114115
Civ
Operand is zero.
Operand is less than zero.
Operand is greater than zero.
— © © | о
о —- © | г
Programming Note:
The LOAD HALFWORD IMMEDIATE (LHI)
instruction produces a value which is the
algebraic sum of the value of the address
field itself and the content of a General
Register index (X2).
The 16-bit first operand is stored in the
General Register or core memory location
specified by the second operand. The first
operand is unchanged.
(Rl) — (A + (X2)) [RX]
Resulting Condition Code:
Unchanged.
2-3
2.2.3 Load Byte
LBR RI, R2 [В R]
0 718 _ 12 15
93 R1 | R2
LB RI, A(X2) [RX]
0 718 _H]12 15)i6 3!
D3 R1 | X2 A
The 8-bit second operand is loaded into the
rightmost 8 bits of the General Register
specified by R1. The leftmost 8 bits of R1
are set to zero. The second operand is
unchanged.
(R1 (8:15) ) 4«—— (R2 (8:15) ) [RR]
(R1 (0:7) ) <—— Zero
(В1 (8:15) ) «— (A + (X2) ) [RX]
(RI (0:7) ) <—— Zero
Resulting Condition Code:
Unchanged.
2.2.4 Store Byte
STBR RI, R2 [RR]
0 718 11215
92 R1 | R2
STB R1, A(X2) [RX]
0 718 №2 15416 3!
D2 R1 | X2 A
The rightmost 8-bit byte of the first operand
is stored in the General Register or core
memory location specified by the second
operand. The first operand is unchanged.
(R1 (8:15) ) ——æ (R2 (8:15) ) [RR]
(R1 (8:15) ) ——» (A + (2) ) [RX]
Resulting Condition Code:
Unchanged.
Programming Note:
In the register-to-register (RR) form of this
instruction the leftmost byte, R2(0:7), is
unchanged.
2.2.5 , Load Program Status Word
LPSW A(X2) [RX]
0 zj8__ 12 _ 1516 31
c2 E 1x2 A
A 32-bit operand is loaded into the Current
Program Status word. The operand is
unchanged.
(PSW (0:31) ) «— (A + (2) ) [RX]
Resulting Condition Code:
Determined by PSW loaded by the instruction.
2-5
2.3 FIXED POINT ARITHMETIC
INSTRUCTIONS
The Fixed Point Arithmetic instructions
provide for addition, subtraction, multipli-
cation and division of halfword operands.
Multiple precision arithmetic operations are
performed by the add/subtract with carry
halfword instructions.
2-6
2.3.1
Add Halfword
AHR RI, R2 [RR]
О 718 thle 15
ВА R1 | R2
AH R1, A(X2) [RX]
O 718 11112 _ 156 3
4A RI | X2 A
AHI RI, A(X2) [RS]
О #8 112 15/16 31
CA R1 | X2 A
2.3.2 Add With Carry Halfword
ACHR R1, R2 [RR]
0 7|8 12 _ 15|
ЙЕ RI | R2
ACH R1, A(X2) [RX]
10 718 1e 1516 3
4E RI | X2 A
The 16-bit second operand and the carry bit of
the condition code are algebraically added to
The 16-bit second operand is algebraically
added to the General Register specified by
R1, The resulting sum is contained in R1,
the second operand is unchanged.
(Rl) «——— (R1) + (R2) [RR]
[RX]
[RS]
(RI) «<——— (R1) + (A+(X2) )
(Rl) «—— (RI) + A + (X2)
Resulting Condition Code:
= |
го
ol
14115]
G
o |
<
Sum is less than zero.
Sum is greater than zero.
1 Arithmetic overflow.
] Carry
L
0 | Sum is zero.
1
0
— O O
Programming Note:
The ADD HALFWORD IMMEDIATE (AHI)
instruction produces a value which is the
algebraic sum of the address field itself plus
the content of a General Register index (X2),
plus the first operand General Register (R1).
the General Register specified by R1. The re-
sulting sum is contained in R1, the second
operand is unchanged.
(Rl) «—— —— (R1) + (R2) + C [RR]
(Rl) «<— —— (R1) + (A + (X2) +C [RX]
Resulting Condition Code:
12/13/1415
Civ
Sum is zero.
Sum is less than zero.
Sum is greater than zero.
1 Arithmetic overflow.
] Carry
— © © | ©
© -—- © | Г
Programming Note:
Multiple precision addition operations require
a carry forward from the least significant oper-
ands to the most significant. To accomplish
this, the locations containing the least signifi-
cant portions of the two operands are summed
using the Add Halfword instruction. A carry
forward, if it occurs, is retained in the carry
bit position of the condition code (PSW (12) ).
The locations containing the next least signifi-
cant portions of the two operands are then
summed using the Add With Carry Halfword
instruction. The carry bit contained in the
condition code (set from the previous addition)
participates in this sum; the carry bit position
is then set to reflect the new result.
The Add With Carry Halfword instructionisused
on succeeding pairs of operands until the most
significant operands of the multiple precision
words have been summed. The resulting con-
dition code is valid for testing the multiple
precision word.
2.3.3 Subtract Halfword
SCHR RI, R2 [RR]
0 718 112 15
OF R1 | R2
SCH RI, A(X2) [RX]
О 718 1112 1516 31
4F R1 | X2 A
The 16-bit second operand is subtracted
from the General Register specified by R1.
The difference is contained in R1, the
second operand is unchanged.
RI) <— (R1) - (R2)
[RR]
[RX]
[RS]
(RI) <——— (RI) - (A + (X2) )
(Rl) €————— (R1) - À - (X2)
Resulting Condition Code:
Difference is zero.
Difference is less than zero.
Difference is greater than zero.
] Arithmetic overflow
1 Carry (borrow)
— OQ O G>
QO =O |r
Programming Note:
The SUBTRACT HALFWORD IMMEDIATE
(SHI) instruction produces a value which is
the difference between the first operand
General Register (R1) less the address field
itself plus the content of a General Register
index (X2).
2.3.4 Subtract With Carry Halfword
SHR RI, R2 [RA]
O 718 12 15
0B RI | R2
SH RI, A(X2) [RX]
О 718 _tili2 15/16 31
4B RI | X2 | A
SHI R1, A(X2) [RS]
0 718 12 15/16 31
CB RI X2 | A
The 16-bit second operand with the carry
(borrow) bit is subtacted from the General
Register specified by R1. The difference
is contained in R1, the second operand is
unchanged.
(Rl) <—— —- (R1) - (R2) - С
[RR]
(Rl) «——— (Rl) - (A+(X2))-C [RX]
Resulting Condition Code:
BEE
CIVIGIL
010 | Difference is zero.
0|1 | Difference is less than zero.
1/0 | Difference is greater than zero.
1 Arithmetic overflow.
] Borrow
Programming Note:
See Add with Carry Halfword.
2.3.5 Multiply Halfword
MHR R1, R2 [RR]
О 718 2 15
gC RI | R2
MH RI, A(X2) [Rx]
О 718 112 15116 3!
AC RI | X2
2.3.6 Divide Halfword
DHR RI, R2 [RR]
0 718 if12 15
0D В] R2
DH RI, A(X2) [RX]
0 718 1112 15/16 31
4D R] X2
The 16-bit second operand is multiplied with
the General Register specified by R1 + 1.
The first operand, R1, must specify an even
numbered register. The resulting 32-bit
product is contained in R1 and R1 +1, an
even-odd pair; the second operand is un-
changed, The sign of the product is deter-
mined by the rules of algebra.
(R1, R1 + 1) <— (R1+1)* (R2) [RR]
RX]
(R1, Ri +1) <«— (R1+1)* (A+(X2))
Resulting Condition Code:
Unchanged.
Programming Note:
After multiplication, the most significant 15
bits with sign are contained in R1, The
least significant 16 bits are contained in
R1 +1.
The 16-bit second operand is divided into the
32-bit dividend contained in the General Reg-
ister specified by R1 and R1 + 1. The first
operand, R1, must specify an even numbered
register. The resulting 15-bit quotient with
sign is contained in R1 + 1; a 15-bit re-
mainder with sign is contained in R1, the
second operand is unchanged. The sign of
the result is determined by the rules of
algebra; the sign of the remainder is the same
as the sign of the dividend.
(R1 +1) «——— (R1, R1 +1)/(R2) [RR]
(R1) @#————— Remainder
(R1 + 1) e— (RI, R1+1)/(A + (X2)) [RX]
(R1) «————— Remainder
Resulting Condition Code:
Unchanged.
Programming Note:
A quotient which cannot be expressed in 16
bits will cause an Arithmetic Fault interrupt
if enabled by bit 3 of the Program Status
Word. The operands will remain unchanged.
2.4 LOGICAL INSTRUCTIONS
The Logical instructions operate bit by bit
on the first operand and its corresponding
bit in the second operand. These operations
provide for masking selected portions of a
halfword, or for comparison for relative
magnitude.
2-10
2.4.1 AND Halfword
NHR RI, R2 [RR]
O 718 Hil2_ 15
04 К] R2
NH R1, A(X2) [RX]
0 718 1412 1516 31
44 RI | X2 A
NHI RI, A(X2) [Rs]
O 7/8 1112 1Sh6 31
C4 RI | X2 A
The logical product of the 16-bit second
operand and the content of the General Reg-
ister specified by R1 replaces the content of
R1, The 16-bit product is formed on a bit-
by-bit basis.
(Rl) <«——— (Ri) AND (R2) [RR]
(Rl) @«———— (R1) AND (A+(X2)) [RX]
(Rl) @«————— (R1) AND A+(X2) [RS]
Resulting Condition Code:
hetisja
clv
Logical product is zero.
\
fLogical product is not zero.
— © © | ©
о - © | га
Programming Note:
The AND HALFWORD IMMEDIATE (NHI) in-
struction produces a value which is the logi-
cal product of the address field itself plus
the content of a General Register index (X2)
with the first operand General Register (R1).
The truth table for the AND function is:
0 AND 0 =
0 AND 1 =
1 AND 0 =
1 AND 1 =
2.4.2 OR Halfword
OHR RI, R2 [RR]
O 718 iz 15
06 RI | R2
OH RI, A(X2) [RX]
O 718 112 1516 31
46 RI | X2 A
OHI RI, A(X2) [RS]
O 718 tii 1516 31
C6 R1 | X2 A
The logical sum of the 16-bit second operand
and the content of the General Register spec-
ified by R1 replaces the content of R1, The
16-bit sum is formed on a bit-by-bit basis.
(В1) «— — —— (В1) ОВ (В2) [RR]
(Rl) «— — —— (В1) OR (A+(X2)) [RX]
(В1) «— — —— (В1) ОВ А + (Х2) [Rs]
Resulting Condition Code:
121314115
CIVIGIL
010 | Logical sum is zero.
of . .
110 } Logical sum is not zero.
Programming Note:
The OR HALFWORD IMMEDIATE (OHI) in-
struction produces a value which is the logical
sum of the address field itself plus the content
of a General Register index (X2) with the first
operand General Register (R1)
The truth table for the OR function is:
0 OR 0 =
0 OR 1 =
1 OR 0 =
1 OR 1 =
2-11
2.4.3 Exclusive OR Halfword
XHR R1, R2 [RR]
0 718 Hie 15
97 RI | R2
XH R1, A(X2) [RX]
0 718 1112 1516 3l
47 R1 | X2
XHI R1, A(X2) [Rs]
О 78 _Ни2г 15116 31
C7 R1 | X2
2.4.4 Compare Logical Halfword
CLHR RI, R2 [RR]
O 718 2 15
05 R1 | R2
CLH RI, A(X2) [RX]
O 718 111412 1516 3l
45 RI | X2
CLHI R1, A(X2) [RS]
0 718 ile 15116 31
C5 RI | X2
The logical difference of the 16-bit second
operand and the General Register specified
by R1 replaces the content of R1, The 16-bit
difference is formed on a bit-by-bit basis.
(Rl) <«———— (R1) XOR (R2) [RR]
(Rl) «—— (R1) XOR (A+(X2)) [RX]
(Rl) «— — — (R1) XOR A + (X2) [RS]
Resulting Condition Code:
The first operand specified by R1 is com-
pared logically to the 16-bit second operand.
The result is indicated by the setting of the
condition code (PSW 12:15); both operands
remain unchanged.
(CC) «——— (R1) : (R2) [RR]
[RX]
[Rs]
(CC) + ———— (R1) : (A+(X2))
(CC) «— —— (Ri) : A+ (2)
Resulting Condition Code:
12]! 314115
C|IVIGIL
010} Logical difference is zero.
1 ; } Logical difference is not zero.
Programming Note:
The EXCLUSIVE OR HALFWORD IMME-
DIATE (XHD instruction produces a value
which is the logical difference of the address
field itself plus the content of the General
Register index (X2) with the first operand
General Register (R1).
The truth table for the EXCLUSIVE OR func-
tion is:
0 XOR 0 =0
0 XOR 1 =1
1 XOR 0 =
1 XOR 1 =0
2-12
12113114115
CIVIGIL
010 First operand equal to second operand.
7 9 First operand not equal to second operand.
] First operand less than second operand.
0 First operand equal to or greater than
second operand.
Programming Note:
The logical comparison is performed by sub-
tracting the second operand from the first
operand. The result is in the condition code
setting, the operands are not modified.
The COMPARE LOGICAL HALFWORD IM-
MEDIATE (CLHI) instruction produces a
value which is the logical comparison of the
address field itself plus the content of a
General Register index (X2) with the first
operand General Register (R1).
2.5 SHIFT INSTRUCTIONS
The Shift instructions provide for arithme-
tic and logical manipulation of information
contained in the General Registers. Bits
shifted out of the high or low order end of a
General Register are passed through the
carry bit position of the condition code
(PSW 12), After execution of a shift in-
struction, the last bit which was shifted out
is contained in the carry position.
The number of bit positions shifted is speci-
fied by the sum of the value A with the con-
tent of the General Register index (X2).
Note that the address field of the instruction
(A) is not interpreted as a memory location
address but as an unsigned integer. The
value of A may be from 0 to FFFF.
A shift of zero positions causes the condi-
tion code to be set properly with no altera-
tion to the information contained in the
General Register.
A shift specification of more than 15 bit posi-
tions will give meaningful results, since only
the four least significant bits of the sum of A
plus (X2) are used to specify the nimber of
positions to be shifted.
2-13
2.5.1 Shift Left Halfword Arithmetic
SLHA R1, A(X2) [RS]
0 718 12 15116 31
2.5.2 Shift Right Halfword Arithmetic
SRHA R1, A(X2) [RS]
O 718 112 15116 31
CF R1 X2 A
CE К] X2 A
The content of the first operand (R1) is
shifted left the number of bit positions
specified by the second operand. Bits 1
through 15 are shifted, the sign bit is un-
changed. High order bits shifted out of
position 1 are shifted thru the carry bit of
the PSW and then lost. Zeros are shifted
into position 15,
(R1)
(C)
Resulting Condition Code:
12113114115
Civ
Result is zero.
Result is less than zero.
Result is greater than zero.
— O O | G)
Oo — ol
] Last bit that was shifted out was a one.
2-14
0 Last bit that was shifted out was a zero.
The content of the first operand (R1) is
shifted right the number of bit positions
specified by the second operand. Bits 1
through 15 are shifted, the sign bit is un-
changed. Low order bits shifted out of
position 15 are shifted thru the carry bit of
the PSW and then lost. The sign bit is pro-
pogated right into position 1.
(R1)
О | E
S
— y
Resulting Condition Code:
12[13[14] 15)
CIVIGIL
010] Result is zero.
011] Result is less than zero.
110] Result is greater than zero.
0 Last bit that was shifted out was a zero.
1 Last bit that was shifted out was a one.
2.5.3 Shift Left Halfword Logical
SLHL R1, A(X2) [RS]
0 718 l!N2 15116 31
CD К] X2 A
The content of the first operand (R1) is
shifted left the number of positions speci-
fied by the second operand. All 16 bits of
the halfword are shifted. High order bits
shifted out of position 0 are shifted thru the
carry bit of the PSW and then lost. Zeros
are shifted into position 15.
(R1)
o IS
Y F
(C)
Resulting Condition Code:
12{13]
pr —
Civ
Г |
Ja
15]
Result is zero.
Result is less than zero.
Result is greater than zero.
Last bit that was shifted out was a zero.
Last bit that was shifted out was a one.
_— OO 6)
© — O | Г
— ©
2.5.4 Shift Right Halfword Logical
SRHL R1, A(X2) [Rs]
О 718 12 15116 31
cc |R1 | R2 | A
The content of the first operand (R1) is
shifted right the number of bit positions
specified by the second operand. All 16 bits
of the halfword are shifted. Low order bits
shifted out of position 15 are shifted thru the
carry bit of the PSW and then lost. Zeros
are shifted into position zero.
(R1)
0 IS
L
— y
(C)
Resulting Condition Code:
Result is zero.
Result is less thon zero.
Result is greater than zero.
0 Last bit that was shifted out was a zero.
1 Last bit that was shifted out was a one.
— © © | ©
© =н= © | Г”
2-15
2.6 BRANCH INSTRUCTIONS
Branch instructions are programmed deci-
sions providing entry to subprograms, as
well as testing the result of arithmetic,
logical, or indexing operations.
Many Processor operations result in setting
of the Condition Code in the Program Status
Word (PSW (12:15)). The Branch on
2-16
Condition instructions implement the testing
of the Condition Code through use of a mask
field contained in the instruction itself (M1
field).
The 4-bit M1 field is not a memory address,
but rather is an image of the condition code
to be tested,
2.6.1 Branch on True Condition*
BTCR MI, R2 [RR]
о 718 1112 15
02 M1 | R2
BTC M1, A(X2) [RX]
O 7/8 112 15116 31
42 M1 | X2 A
2.6.2 Branch on False Condition*
BFCR MI, R2 [RR]
о 7/8 2 15
03 MI | R2
BFC MI, A(X2) [RX]
0 718_ 112 1516 31
43 M1 | X2 A
The condition code field of the Program
Status Word (PSW (12:15)) is tested for the
conditions specified by the mask field (M1).
If any of the conditions tested are found to be
true, a Branch is executed to the 16-bit ad-
dress specified by the second operand. If
none of the conditions tested are found to be
true the next sequential instruction is exe-
cuted.
Tested Condition True:
(PSW (16:31) ) «— (R2)
Tested Condition Not True:
(PSW (16:31) ) «—— (PSW (16:31) ) + 2
[RR]
Tested Condition True:
(PSW (16:31) ) @—— A + (X2) [RX]
Tested Condition Not true:
(PSW (16:31) ) «— (PSW (16:31) ) +4
Programming Note:
A logical AND is performed between each bit
in the condition code and its corresponding
bit in the Mi field, If any resultant bit is a
one, the branch will occur. The condition
code (PSW (12:15)) is not changed.
Example:
CC 1010
AND
Mi 1100
1000 BTC result: Branch if
| bit remains after AND.
The condition code field of the Program
Status Word (PSW (12:15)) is tested for the
condition specified by the mask field (M1).
If all conditions tested are found to be false,
a Branch is executed to the 16-bit address
specified by the second operand. If any of
the conditions tested are found to be true,
the next sequential instruction is executed.
Tested Condition False:
(PSW (16:31) ) € — (В?) [RR]
Tested Condition Not false:
(PSW (16:31) ) «— (PSW (16:31) ) + 2
Tested Condition False:
(PSW (16:31) ) «-— A + (X2)
Tested Condition Not false:
RX]
(PSW (16:31) ) «— (PSW (16:31) ) + 4
Programming Note:
A logical AND is performed between each bit
in the condition code and its corresponding
bit in the Mi field. If any resultant bit is a
one, the branch will not occur. The condi-
tion code (PSW (12:15) ) is not changed.
Example:
CC 1010
AND
Mi 1100
1000 BFC result: Branch
if no bit remains after
AND. 1
*Refer to Section 2.7 for information on Extended Mnemonic Codes for conditional
branch instructions.
2-17
2.6.3 Branch Unconditional
BR R2 [RR]
О 718 12 15
93 9 | R2
B A(X2) [RX]
о 7/8 nji2_ 15]16 3i
43 9 | X2 A
The 16-bit address specified by the second
operand is transferred to the instruction ad-
dress field of the Program Status Word
(PSW (16:31) ). The next instruction exe-
cuted will be accessed from the location
specified by the new instruction address.
(PSW (16:31) ) «—— (В?) [RR]
(PSW (16:31) ) «— A + (X2) [RX]
Programming Note:
The Branch Unconditional instruction is a
form of the Branch on False Condition in-
struction where no condition is specified for
testing.
2.6.4 No Operation
NOPR R2 [RR]
о 718 12 15
92 g | R2
NOP A(X2) [RX]
о 7/8 НИ2г 1516 31
42 g | X2 A
The second operand is ignored and therefore
may assume any value. The (M1) field is
zero. The instruction address field of the
Program Status Word (PSW (16:31) ) is
incremented and the next sequential instruc-
tion is accessed for execution.
(PSW (16:31) ) @——— (PSW (16:31) ) + 2 [RR]
(PSW (16:31) ) @—— (PSW (16:31) ) + 4 [RX]
Programming Note:
The No Operation instruction is a form of the
Branch on True Condition instruction where
no condition is specified for testing. The No
Operation instruction is useful to replace 16
or 32 bits of erroneous or redundant coding
or to reserve memory locations within a
program for anticipated future coding. This
instruction may also be employed as an
inactive instruction in timing sequences.
2.6.5 Branch on Index High
BXH RI, A(X2)
O 718 112 1516
Co R1 X2 À
[R si
Prior to execution of this instruction, the
General Register specified by the first oper-
and (R1) must contain a 16-bit count value,
R1 + 1 must contain a 16-bit increment
value, and R1 + 2 must contain a 16-bit
comparand value (limit). All values may be
signed,
Execution of this instruction causes the count
(R1) to be incremented by (R1 + 1) and logi-
cally compared to the limit. As long as the
count (R1) is greater than the limit (R1 + 2),
the 16-bit address specified by the second
operand is transferred to the instruction ad-
dress field of the Program Status Word (PSW
(16:31) ). . The next instruction executed will
be accessed from the location specified by
the new instruction address.
When the count is not greater than the index
limit, the instruction following Branch on
Index High will be executed.
(R1) <- (R1) + (R1 +1) [RS]
(R1) : (R1 +2)
if (R1)> (R1 +2)
(PSW (16:31) ) «— A + (X2)
if (R1)<(R1 +2);
(PSW (16:31) ) «—— (PSW (16:31)) + 4
Programming Note:
General Register 13 is the maximum speci-
fication for the R1 field, since a block of
three consecutive General Registers is re-
quired.
A logical comparison treats all 16-bits of
the halfword as magnitude bits.
2.6.6 Branch on Index Low or Equal
BXLE RI, A(X2) [RS]
О 718 12 _ 15116 3i
C1 К] X2 A
Prior to execution of this instruction, the
General Register specified by the first oper-
and (R1) must contain a 16-bit count value,
R1 + 1 must contain a 16-bit increment
value, and R1 + 2 must contain a 16-bit
comparand (limit). All values may be
signed.
Execution of this instruction causes the count
(R1) to be incremented by (R1 + 2) and logi-
cally compared to the index limit. As long
as the count (R1) is equal to or less than the
limit (R1 + 2), the 16-bit address specified
by the second operand is transferred to the
instruction address field of the Program
Status Word (PSW (16:31)). The next instruc-
tion executed will be accessed from the lo-
cation specified by the new instruction
address. When the count is not equal to, or
less than, the limit, the instruction following
Branch on Index Low will be executed.
(R1) <— (Rl) + (R1 +1) [RS]
(R1) : (R1 + 2)
if (В1) < (В1 + 2)
(PSW (16:31)) «—— A + (X2)
if (R1)>(R1+2);
(PSW (16:31) ) «-— (PSW (16:31)) +4
Programming Note:
General Register 13 is the maximum speci-
fication for the R1 field since a block of
three consecutive General Registers is
required.
A logical comparison treats all 16-bits of the
halfword as magnitude bits,
2-19
2.6.7 Bronch and Link
BALR RI, R2 [RR]
O 718 12 15
91 RI | R2
BAL R1, A(X2) [Rx]
O 7/18 _ 1112 1516 31
41 RI | X2 A
The Branch and Link instruction is executed
in two phases. The instruction address field
of the Program Status Word (PSW (16:31))
is incremented and transferred to the loca-
tion specified by the first operand (R1). The
second operand then becomes the new con-
tent of the instruction address field (PSW
(16:31) ). The next instruction executed will
be accessed from the location specified by
the new instruction address.
(R1) <—— (PSW (16:31) ) + 2 [RR]
(PSW (16:31) ) «— (R2)
(R1) <— (PSW (16:31) ) +4 [RX]
(PSW (16:31) ) «— A + (2?)
Programming Note:
The Branch and Link instruction is required
for entry to sub-programs, It differs from
the Branch Unconditional instruction in that
the current instruction address field is
preserved in a specified General Register
to be used as the sub-program exit address.
Exit from the sub-program is effected by a
Branch Unconditional instruction through the
General Register in which the exit address
has been maintained.
2-20
2.7 EXTENDED MNEMONIC CODES FOR
BRANCH ON CONDITION
To simplify the coding of conditional branch
instructions for the programmer, an ex-
tended set of mnemonic codes has been
provided in the Symbolic Assembler. The
most frequently used branch instructions
have been provided with mnemonics which
are not a part of the machine language
instruction set, but are translated by the
assembler into the proper operation code
and M1 field combinations.
The extended mnemonic codes are for in-
structions in the RX format.
2-21
2.7.1 Branch on Zero
BZ A(X2) [RX]
O 7/8 _ 1112 16 31
43 3 | x2
The Condition Code field of the Program
Status Word (PSW (12:15) ) is tested for the
zero condition. If this condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the con-
dition is not met, the next sequential
instruction is executed.
(PSW (16:31)) «— CC = Zero: (A+(X2) [RX]
(PSW (16:31) ) <— CC # Zero: (PSW (16:31)) +4
Condition Code Tested:
Zs
CIVIGIL
010 Branch
9/77 0 Ne Branch
110 o Branc
Valid After:
LH
AH, ACH, SH, SCH
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2-22
2.7.2 Branch on Not Zero
BNZ A(X2) [RX]
0 7/8 {12 1516 3
42 3 X2 À
The Condition Code field of the Program
Status Word (PSW (12:15) ) is tested for the
not zero condition, If this condition is met,
a Branch is executed to the 16-bit address
specified by the second operand. If the con-
dition is not met, the next sequential
instruction is executed.
(PSW (16:31) ) — CC # Zero; A+(X2) [RX]
(PSW (16:31) ) —— CC = Zero; (PSW (16:31)) +4
Condition Code Tested:
—
1211314115
CIVIG
L
0 No branch В
5 } Branch
— O O
Valid After:
LH
AH, ACH, SH, SCH
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2.7.3 Branch on Plus
BP A(X2) [RX]
0 7/8 uji2 _ 1516 31
42 2 X2 A
The Condition Code field of the Program
Status Word (PSW (12:15)) is tested for the
plus condition, If this condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
(PSW (16:31) ) «— CC = Plus; A+(X2) [RX]
(PSW (16:31) ) #+— CC £ Plus; (PSW (16:31)) +4
Condition Code Tested:
121! 3/14/15
CIVIGIL
О 1 } No branch
110 Branch
Valid After:
LH
AH, ACH, SH, SCH
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2.7.4 Branch on Not Plus
BNP A(X2) [RX]
O 718 l1i2 156 31
43 2 X2 A
The Condition Code field of the Program
Status Word (PSW (12:15)) is tested for the
not plus condition. If this condition is met,
a Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
(PSW (16:31) ) «— CC £Plus; A+ (X2) [RX]
(PSW (16:31) ) «— CC = Plus; (PSW (16:31)) +4
Condition Code Tested:
12113114115
CIV
} Branch
No Branch
— © © | ©
QO = <> Г
Valid After:
LH
AH, ACH, SH, SCH
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2-23
2.7.5 Bronch on Minus
BM A(X2)
Q 718 2 1516
42 1 X2 A
[RX]
The condition code field of the Program
Status Word (PSW (12:15)) is tested for the
minus condition. If the condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
(PSW (16:31) ) +— CC = Minus; A +(X2) [RX]
(PSW (16:31) ) «— CC # Minus; (PSW (16:31)) +4
Condition Code Tested:
[12]13]i4]15]
civielL
010 No branch
011 Branch
110 No branch
Valid After:
LH
AH, ACH, SH, SCH
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2-24
2.7.6 Branch on Not Minus
BNM A(X2)
Q 718 1112 15/16
43 1 X2 A
[RX]
The condition code field of the Program
Status Word (PSW (12:15)) is tested for the
not minus condition. If the condition is met,
a Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
(PSW (16:31) ) @— CC #Minus; A +(X2) [RX]
(PSW (16:31) )«— CC = Minus; (PSW (16:31)) +4
Condition Code Tested:
рен Г
12[13]14] 15)
CIVIGIL
01 Branch
1 | No branch
O | Branch
= © © | O.
Valid After:
LH
AH, ACH, SH, SCH
SLHA, SRHA, SLHL, SRHL
NH, OH, XH
2.7.7 Branch on Carry
BC A(X2)
О 718 г 1516
42 8 X2 A
[R q
The condition code field of the Program
Status Word (PSW (12:15) ) is tested for the
carry condition. If the condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed. -
(PSW (16:31) ) #+— CC =Carry; A +(X2) [RX]
(PSW (16:31) ) «— CC £ Carry; (PSW (16:31)) +4
Condition Code Tested:
1213/14/15
VIGIL
C
1 Branch
0 No Branch
Valid After:
AH, ACH, SH, SCH
SLHA, SRHA, SLHL, SRHL
2.7.8 Branch on Overflow
BO A(X2)
О 718 иг 1516
42 4 X2 A
[R X]
The condition code field of the Program
Status Word (PSW (12:15)) is tested for the
overflow condition. If the condition is met,
a Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
(PSW (16:31) ) «— CC =Overflow; A+(X2) [RX]
(PSW (16:31)) «— CC =Overflow; (PSW(16:31) +4
Condition Code Tested:
1213/1415
CIVIGIL
] Branch
0 No Branch
Valid After:
AH, ACH, SH, SCH
2-25
2.7.9 Branch on Low
BL A(X2)
0 7/8 uji2 __isjie
42 8 X2 A
[R a
The condition code field of the Program
Status Word (PSW (12:15) ) is tested for the
low condition. If the condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
(PSW (16:31) )#— CC = Low A + (X2)
[RX]
(PSW (16:31) )#— CC #£ Low (PSW (16:31) ) +4
Condition Code Tested:
(211311415
| CIV{GIL
] Branch
No branch
Valid After:
CLH
2-26
2.7.10 Branch on Not Low
BNL A(X2)
О 718 2 1516
43 8 X2 A
[RX]
31
The condition code field of the Program Status
Word (PSW (12:15)) is tested for the not low
condition. If the condition is met, a Branch
is executed to the 16-bit address specified
by the second operand. If the condition is
not met, the next sequential instruction is
executed.
(PSW (16:31) ) «— CC =Now low A+(X2) [RX]
(PSW (16:31) ) + CC # Not low (PSW (16:31)) + 4
Condition Code Tested:
1213/14/15
ViGiL
Branch
No Branch
- Oo
Valid After:
CLH
2.7.11 Branch on Equal
BE A(X2) [RX]
О 718 112 1516 31
43 3 X2 A
The condition code field of the Program
Status Word (PSW (12:15)) is tested for the
equal condition. If the condition is met, a
Branch is executed to the 16-bit address
specified by the second operand. If the
condition is not met, the next sequential
instruction is executed.
(PSW (16:31) )«— CC = Equal A + (X2) [RX]
(PSW (16:31) ) «— CC £ Equal (PSW (16:31)) +4
Condition Code Tested:
12].3[14]15,
CIVIGIL
0/0 Branch
01 No Branch
110
Valid After:
CLH
2.7.12 Branch on Not Equal
BNE A(X2)
О 718 12 15116
42 3 X2 A
[RX]
The condition code field of the Program Status
Word (PSW (12:15)) is tested for the not equal
condition. If the condition is met, a Branch
is executed to the 16-bit address specified by
the second operand. HM the condition is not
met, the next sequential instruction is
executed.
(PSW (16:31) ) «— CC =Not equal A+ (X2) [RX]
(PSW (16:31) ) «— CC #Not equal (PSW (16:31)) +4
Condition Code Tested:
12]13[14]15)
CIVIGIL
010 No Branch
011 1% Branch
1 0 ran
Valid After:
CLH
2-27
2.8 DEVICE INTERRUPT AND CONTROL
INSTRUCTIONS
The Interrupt and Control instructions pro-
vide for Processor interrogation and control
of peripheral devices in the system.
2-28
2.8.1 Acknowledge Interrupt
AIR R1, R2 [RR]
0 718 uji2 15
9F RI R2
Al R1, A(X2) [RX]
O 718 {jz 15116 3!
DF RI | X2
2.8.2 Sense Status
SSR RI, R2 [RA]
O 718 12 15
9D RI | R2
SS R1, A(X2) [RX]
Q 718 12 1516 31
DD R1 | x2
The address of the interrupting device re-
places the content of the 16-bit General
Register specified by the first operand (R1).
The 8-bit device status byte replaces the
content of the location specified by the
second operand. The Condition Code is set
equal to the right-most four bits of the device
status byte.
The device interrupt condition
is then cleared.
(R1 (8:15) ) «+ — Device address
[RR]
(R1 (0:7)) «+ —— Zero
(R2 (8:15) ) €+——— Status byte
(R2 (0:7) ) 4+ ——— Zero
(PSW (12:15) ) €+— Status byte (4:7)
(R1 (8:15) ) €—— Device number
[RX]
(R1 (0:7) ) € —— Zero
(A + (X2)) <-— Status byte
(PSW (12:15) )€— Status byte (4:7)
Resulting Condition Code:
12
13
14
2
|
© сэ © — | С)
о © — © | <
© — © © | ©)
— СЭ © © fo"
Device busy (BSY)
Examine status (EX)
End of medium (EOM)
Device unavailable (DU)
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The device is addressed and the 8-
bit device status byte replaces the content of
the location specified by the second operand.
The Condition Code is set equal to the right-
most four bits of the device status byte.
The first operand is unchanged.
(R2 (8:15) ) + —— Status byte [RR]
(R2 (0:7) ) 4+——— Zero
(PSW (12:15) ) «— Status byte (4:7)
(A + (2))<-—— Status byte [RX]
(PSW (12:15) ) €— Status byte (4:7)
Resulting Condition Code:
pa
Gala
C|VIGIL
1 [0 10j0 | Device busy (BSY)
O 11 [010 | Examine Status (EX)
O [0 |1/0 | End of Medium (ECM)
010 1011 | Device unavailable (DU)
2-29
2.8.3 Output Command
OCR RI, R2 [RA]
O 718 2 15
9E RI | R2
OC RI, A(X?) [RX]
O 7/8 иг 1516 31
DE RI | X2 A
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The device is addressed and the
8-bit device command byte specified by the
second operand is transmitted to the ad-
dressed device. Both operands remain
unchanged.
Device «——— (R2 (8:15)) [RR]
Device + (A + (X2)) [RX]
Resulting Condition Code:
12/13/1415
CIVIGIL
01110/0| Examine Status (EX)
2-30
29 INPUT/QUTPUT INSTRUCTIONS
The Input/Output instructions provide for
transfer of 8-bit byte information between
the Processor and peripheral devices in the
system.
2-31
2.9.1 Read Date
КОВ R1 R2 [RR]
O 718 Hitz 15
9B R1 | R2
RD R1, A(X2) [RX]
O 718 Ile 15116 31
DB RI | X2 A
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The device is addressed and a single
8-bit data byte is transmitted from the device
replacing the content of the location specified
by the second operand.
(R2 (8:15) ) «——— Data byte [RR]
(R2 (0:7)) <+—— Zero
(A + (X2)) «<——— Data byte [RX]
Resulting Condition Code:
12]13)14]15
1 a pr —
CIVIGIL
90111010
Examine Status (EX)
2-32
2.9.2 Write Data
WDR RI, R2 [RR]
O 718 Mie 15
9A RI | R2
WD R1, A(X2) [RX]
0 718 lili2 15/16 31
DA |rı | x2 | A
The 16-bit General Register specified by the
first operand (R1) contains the device ad-
dress. The device is addressed and a single
8-bit data byte is transmitted to the device.
Both operands remain unchanged.
(R2 (8:15) ) ——» (Device) [RR]
(A + (X2)) —— (Device) [RX]
Resulting Condition Code:
1213/14/15
Civ [GIL
0/1/0/0
Examine Status (EX)
CHAPTER 3
CONSOLE OPERATION AND DISPLAY
3.1 INTRODUCTION 1. Control Switches: POWER,
The discussion which follows pertains to the INITIALIZE, and EXECUTE.
General Purpose Display Panel, shown on 2. MODE CONTROL Rotary Switch.
Figure 3-1, and the operating controls as-
sociated with it. 3. SPEED CONTROL rotary switch,
4, REGISTER DISPLAY rotary
The control console is comprised of six dis- .
switch,
tinct elements:
= Kae -—— a rn ВНОК селе, EE
eur re! E = Ye sE al (Turia = CRE
" = “a та “я .
=" = x. pe | he Hs > = т т = q Ts Ta x .. ot ah a on . - - . . -
=” “. © = - = | "E ME = x e. “ " a - "= =
: М: Era e A + . y x
" =" r "oa " a - =
“ - >
. - „* LE ~
5 ". 7 - Fr " =, Bro. -
a 11 ’ SrE E SE
ge à Ds . Че =. TTT ag TERE ET ДНИ с
Lez E TEA Aa EE 2 LA - E E RE A ES се meat Rowen Ee a
Bea —. — 7 INESIS E =" "№ г. ES ENE -N 7; SL
<= 15 .L EI PEE ES AA, "7 RISE" IEEE в вл в в
Ё
i
17 MEET AS EVE BEST à CEE Rte ES
H. ETE = E FA = PEE zo: So
E PEE E ata E
PR Bo A Dat о
ГУ HE Cod EE | A
В boro E "ie? Lo PA АС + =
nm = — su ни e E Yin be = + E : ,!
rh '
POr "
A 1,
В mewn = Case LEO A BC
3 8 CE EEE END N N me
EPR ry RTI, ZZ та TEE Ae ATTY GE SELL ESS EC
TTY ABET IRATE y EN АЛ УЗО УЧ
=r я = E re mr AFP N Srey — TT je = En y
" "a Ta „М лы Do Pr an A A E cs ER
Figure 3-1. General Purpose Display Panel
5. Sixteen Data/Address switches.
6. Display of two 16-bit halfword
registers.
Each of the elements is described in the
following sections. Console operating pro-
cedures are provided following the
descriptions.
3.2 CONTROL SWITCHES
The latching POWER switch applies power
to the Processor and device controllers.
An indicator lamp is associated with the
POWER switch.
The momentary INITIALIZE switch resets
peripheral device interrupts and certain
other functions in the Processor. After
initialization, the Processor is left in the
‘Halt mode.
The momentary EXECUTE switch causes
the Processor to perform the function
selected by the MODE CONTROL switch.
The associated indicator lamp is on when
the Processor is in the interruptable Wait
state or Halt mode; the lamp is off when
the Processor is in the Run mode.
3.3 MODE CONTROL SWITCH
The six position, rotary MODE CONTROL
switch selects the following modes of oper-
ation which become effective when the
EXECUTE switch is depressed:
RUN: the Processor continuously
executes instructions at rated
speed.
HALT: instruction execution is stopped at
the moment the EXECUTE switch
is depressed and the processor is
placed in the Wait state.
VARI: the Processor executes instruc-
tions at the rate selected by the
variable SPEED CONTROL, The
register displays are operative in
this mode.
ADRS: selects the instruction location
address portion of the Program
Status Word (PSW(16:31)). The
new address is entered in the
sixteen Address Switches below
the register display.
MEMR: the Memory Read mode permits
display of memory data in the
register display.
MEMW: the Memory Write mode permits
entry of data into memory from
the sixteen Data Switches below
the register display.
3.4 SPEED CONTROL SWITCH
The variable SPEED CONTROL switch pro-
vides a dynamically changing display when
in the Variable mode. The rate of display
can vary from 1 to 1000 cps by rotating
the control clockwise from SLOW to FAST,
When in the SNGL position, a single in-
struction is executed and displayed each
time the EXECUTE switch is depressed.
3.5 REGISTER DISPLAY SWITCH
The REGISTER DISPLAY switch selects
pairs of 16-bit registers for display in the
lighted panel positions labeled DISPLAY 1
and DISPLAY 2. Beginning at the one
o'clock position and moving clockwise, the
registers displayed are:
INST: (Dl) The current instruction.
(D2) The Address field of the cur-
rent instruction if RX or RS
format.
PSW: (D1) The Program Status and
Condition Code.
(D2) The location address of the
current instruction.
RO/1: (D1) General Register 0.
(D2) General Register 1.
(Note: the seven succeeding pairs
of General Registers are selected
similarly. )
OFF: (D1) and (D2) are blank.
REGISTER DISPLAY: The position at
12 o'clock displays the second
operand in (D1) and the result
in (D2),
3.6 DATA/ADDRESS SWITCHES
The 16 Input Register latching pushbutton
switches provide a means of entering infor-
mation manually. An address set in the
switches is entered into the instruction loca-
tion address portion of the Program Status
Word (PSW (16:31)) when the ADRS mode is
selected and the EXECUTE switch is
depressed.
Data set in the switches is written into
memory when the MEMW mode is selected
and the EXECUTE switch is depressed.
The halfword location written into is speci-
fied by the instruction address portion of
the PSW.
3.7 REGISTER DISPLAY
The two 16-bit halfword register displays
are operative when the VARIable Mode or
when MEMR or MEMW have been selected.
The display registers remain static when in
the RUN mode.
The diagrams above the register display in-
dicate the data format in (D1) and (D2) when
the PSW, Instruction Register, a General
Register pair, or MEMR/MEMW are select-
ed for display.
3.8 CONSOLE OPERATING PROCEDURES
To bring up power and initialize the system:
1. Depress the latching POWER
switch.
2. Depress the momentary
INITIALIZE switch.
To shut down power to the system:
1. Set the Mode Control switch to
HALT,
2. Depress the momentary EXECUTE
switch,
3. Release the latching POWER
switch.
To begin execution of a program:
The system must be in the Halt mode.
1. Set the Mode Control switch to
ADRS.
2. Enter the program starting address
in the 16 address switches.
3. Depress the momentary
EXECUTE switch.
4. Set the Mode Control switch to
RUN.
5. Depress the EXECUTE switch.
To halt execution of a program:
1. Set the Mode Control switch to
HALT.
2. Depress the EXECUTE switch,
To read memory from display registers:
The system must be in the Halt mode.
1. Set the Mode Control switch to
ADRS.
2. Enter the memory read starting
address in the 16 address
switches.
3. Depress the EXECUTE switch.
4. Set the Mode Control switch to
MEMR.
5. Depress the EXECUTE switch.
6. The memory data is read from
display register 2 (D2). The
memory address of the data be-
ing displayed is in display
register 1 (D1).
7. Depress the EXECUTE switch to
display memory data from suc-
cessive memory locations. The
memory address is automatically
incremented each time the
EXECUTE switch is depressed.
To write into memory:
The system must be in the Halt mode.
1. Set the Mode Control switch to
ADRS.
3-3
Enter the memory write starting
address in the 16 address switches.
Depress the EXECUTE switch.
Set the Mode Control switch to
MEMW.
Enter the data to be written into
memory in the 16 data switches.
Depress the EXECUTE switch,
The memory data entered is dis-
played in display register 2 (D2).
The memory address which was
written into is displayed in display
register 1 (D1). To write into
successive memory locations re-
peat from Step 5. The memory ad-
dress is automatically incremented
with each depression of the
EXECUTE switch.
To display the Instruction Register, Pro-
gram Status Word or General Registers:
The system must be in the Halt mode.
1,
Set the Register Display switch to
select the registers desired for
display.
Depress the EXECUTE switch,
The registers selected for display
will appear in D1 and D2 in the for-
mat indicated by the four diagrams
above the lighted display.
To display registers in the VARIable speed
mode:
The system must be in the Halt mode.
Set the Mode Control switch to
ADRS.
Enter the starting memory loca-
tion address in the 16 address
switches,
Depress the EXECUTE switch.
Set the Mode Control switch to
VARL
Set the Speed Control switch to
SINGL or to a SLOW - FAST
setting,
Set the REGISTER DISPLAY switch
to select the registers desired for
display.
Depress the EXECUTE switch to
begin operation of the program
with display of the selected regis-
ters. If SNGL step was Selected,
the EXECUTE switch is depressed
to cause single step execution of
successive instructions.
The REGISTER DISPLAY switch
setting can be changed during
operation in the variable speed
mode. The SPEED CONTROL
switch can also be changed from
SNGL to a SLOW-FAST setting
without halting operations.
APPENDIX 1
CORE MEMORY ALLOCATION FOR
GENERAL REGISTERS AND PROGRAM STATUS WORDS
Hexadecimal Memory Address Register Assignment
General Registers
00
02
04
06
08
ОА
0C
OE
10
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
30
34
38
3C
40
44
48
4C
OL eee ке,. RO
03 RR R1
05 LL LL a ea ea a aa ea ea a ee ae ee R2
US R3
PS R4
0B... RR KK R5
OD ennracaaia sena renacer, R6
OF a R7
11 LL LL Lee aa ee ae eee La R8
BR R9
A R10
17 andere aranenearerrvar a R11
19 enano rorenooen. R12
1B 2.201010 0 0 ea LL aa ea aa R13
1D 2.220211 La es es ea es as a ee R14
1F 2.201 2ea aa ea ea a ee ea La a 4e R15
- 21 200000404440 0 4 0 0 4 4 40 0 4 14 26 Instruction Register
A Instruction Address Register
A Current PSW: Status and Condition Code
27 ee ee ee et tee eee eee Current PSW: Instruction Address Counter
= 29 222821000401 1 640 0 10 1 0 0 0 0 a 0 à Display support: First operand
2B ..Ñ.eooroooeroeernernaoaao ea noo Display support: Second oper and
2D 2022420200 0 6 2 5 0 4 6 4 0 eee Display support: Result
= 33 222042000240 0 0 4 0 4 0 4 4 0 0 1 a 40 Old PSW: Illegal Instruction Interrupt
37 0011 20 0 0 4 4 0 0 4 0 0 4 1 1 6 1 0 0 0e» New PSW: Illegal Instruction Interrupt
ЗВ ..oerereoro aro oe area noaao Old PSW: Machine Malfunction Interrupt
ЗЕ enoreosecrore_o cono room. New PSW: Machine Malfunction Interrupt
43 210100 0 4 0 0 4 0 0 0 0 0 0 0 4 0 8 1 oo 0 Old PSW: External Device Interrupt
47 200244 420 8 4 0 4 0 6 оо ввело New PSW: External Device Interrupt
= Old PSW: Divide Fault Interrupt
4В 12124 04 0 4 4 4 44 4 0 4 8 4 1 0 4 a a 1e 6 New PSW: Divide Fault Interrupt
Ce eh eee eee teem ete eee eee. First user available memory location.
Al-1
APPENDIX 2
SUMMARY OF INSTRUCTIONS - ALPHABETICAL BY NAME
INSTRUCTION TYPE MNEMONIC OP CODE
Acknowledge Interrupt RR AIR 9F
Acknowledge Interrupt RX Al DF
Add Halfword RR AHR 0A
Add Halfword RX AH 4A
Add Halfword Immediate RS AHI CA
Add with Carry Halfword RR ACHR OE
Add with Carry Halfword RX ACH 4E
AND Halfword RR NHR 04
AND Halfword RX NH 44
AND Halfword Immediate RS NHI C4
Branch and Link RR BALR 01
Branch and Link RX BAL 41
Branch on False Condition RR BFCR 03
Branch on False Condition RX BFC 43
Branch on True Condition RR BTCR 02
Branch on True Condition RX BTC 42
Branch on Index Low or Equal RS BXLE Cl
Branch on Index High RS BXH CO
Branch Unconditional RR BR 03
Branch Unconditional RX B 43
Branch on Overflow* RX BO 424
Branch on Zero* RX BZ 433
Branch on Not Zero* RX BNZ 423
Branch on Equal* RX BE 433
Branch on Not Equal* RX BNE 423
Branch on Plus* RX BP 422
Branch on Not Plus* RX BNP 432
Branch on Low* RX BL 428
Branch on Not Low* RX BNL 438
Branch on Minus* RX BM 421
Branch on Not Minus* RX BNM 431
*Extended Mnemonics - See Section 2. 7
A2-1
INSTRUCTION TYPE MNEMONIC OP CODE
Branch on Carry* RX BC 428
Compare Logical Halfword RR CLHR 05
Compare Logical Halfword RX CLH 45
Compare Logical Halfword Immediate RS CLHI C5
Divide Halfword RR DHR 0D
Divide Halfword RX DH 4D
Exclusive OR Halfword RR XHR 07
Exclusive OR Halfword RX XH 47
Exclusive OR Halfword Immediate RS XHI СТ
Load Byte RR LBR 93
Load Byte RX LB D3
Load Halfword RR LHR 08
Load Halfword RX LH 48
Load Halfword Immediate RS LHI C8
Load Program Status Word RX LPSW C2
Multiply Halfword RR MER OC
Multiply Halfword RX MH 4C
No Operation RR NOPR 02
No Operation RX NOP 42
OR Halfword RR OHR 06
OR Halfword RX OH 46
OR Halfword Immediate RS OHI C6
Read Block RR RBR 97
Read Block RX RB D7
Read Data RR RDR 9B
Read Data RX RD DB
Output Command RR OCR 9E
Output Command RX OC DE
Shift Left Arithmetic RS SLHA CF
Shift Left Logical RS SLHL CD
Shift Right Arithmetic RS SRHA CE
Shift Right Logical RS SRHL CC
Store Byte RR STBR 92
Store Byte RX STB D2
Store Halfword RX STH 40
*Extended Mnemonic - See Section 2.7
A2-2
INSTRUCTION TYPE MNEMONIC OP CODE
Subtract Halfword RR SHR 0B
Subtract Halfword RX SH 4B
Subtract Halfword Immediate RS SHI CB
Subtract with Carry Halfword RR SCHR OF
Subtract with Carry Halfword RX SCH 4F
Sense Status RR SSR 9D
Sense Status RX SS DD
Write Block RR WBR 96
Write Block RX WB D6
Write Data RR WDR 9A
Write Data RX WD DA
A2-3
APPENDIX 3
SUMMARY OF INSTRUCTIONS - NUMERICAL BY OP CODE
OP CODE TYPE MNEMONIC INSTRUCTION
01 RR BALR Branch and Link
02 RR BTCR Branch on True Condition
03 RR BFCR Branch on False Condition
04 RR NHR AND Halfword
05 RR CLHR Compare Halfword
06 RR OHR OR Halfword
07 RR XHR Exclusive OR Halfword
08 RR LHR Load Halfword
0A RR AHR Add Halfword
0B RR SHR Subtract Halfword
10 RR MHR Multiply Halfword
0D RR DHR Divide Halfword
OE RR ACHR Add with Carry Halfword
OF RR SCHR Subtract with Carry Halfword
40 RX STH Store Halfword
41 RX BAL Branch and Link
42 RX BTC Branch on True Condition
43 RX BFC Branch on False Condition
44 RX NH AND Halfword
45 RX CLH Compare Logical Halfword
46 RX OH OR Halfword
47 RX XH Exclusive OR Halfword
48 RX LH Load Halfword
4A RX AH Add Halfword
4B RX SH Subtract Halfword
4C RX MH Multiply Halfword
4D RX DH Divide Halfword
4E RX ACH Add with Carry Halfword
4F RX SCH Subtract with Carry Halfword
92 RR STBR Store Byte
93 RR LBR Load Byte
96 RR WBR Write Block
97 RR RBR Read Block
9A RR WDR Write Data
9B RR RDR Read Data
9D RR SSR Sense Status
JE RR OCR Output Command
OF RR AIR Acknowledge Interrupt
CoO RS BXH Branch on Index High
Cl RS BXLE Branch on Index Low or Equal
C2 RX LPSW Load Program Status Word
A3-1
OP CODE TY PE MNEMONIC INSTRUCTION
C4 RS NHI AND Halfword Immediate
C5 RS CLHI Compare Logical Halfword Immediate
C6 RS OHI OR Halfword Immediate
СТ RS XHI Exclusive OR Halfword Immediate
Cs RS LHI Load Halfword Immediate
CA RS AHI Add Halfword Immediate
CB RS SHI Subtract Halfword Immediate
CC RS SRHL Shift Right Logical
CD RS SLHL Shift Left Logical
CE RS SRHA Shift Right Arithmetic
CH RS SLHA Shift Left Arithmetic
D2 RX STB Store Byte
D3 RX LB Load Byte
D6 RX WB Write Block
D7 RX RB Read Block
DA RX WD Write Data
DB RX RD Read Data
DD RX SS Sense Status
DE RX OC Output Command
DF RX Al Acknowledge Interrupt
A3-2
|
17
34
68
137
274
549
1 099
© & N —
16
33
67
134
268
536
073
147
294
589
179
359
719
438
877
755
511
APPENDIX 4
ARITHMETIC REFERENCES
TABLE OF POWERS OF TWO
20 n 270
1 0 1.0
2 1 0.5
4 2 0.25
8 3 0.125
16 4 0.062 5
32 5 0.031 25
64 6 0.015 625
128 7 0.007 812 5
256 8 0.003 906 25
512 9 0.001 953 125
024 10 0.000 976 562 5
048 11 0.000 488 281 25
N HH
4 096 12 0.000 244 140 625
8 192 13 0.000 122 070 312 5
16 384 14 0.000 061 035 156 25
32 768 15 0.000 030 517 578 125
65 536 16 0.000 015 258 789 062 5
131 072 17 0.000 007 629 394 531 25
262 144 18 0.000 003 814 697 265 625
524 288 19 0.000 001 907 348 632 812 5
048 576 20 0.000 000 953 674 316 406 25
097 152 21 0.000 000 476 837 158 203 125
194 304 22 0.000 000 238 418 579 101 562 5
388 608 23 0.000 000 119 209 289 550 781 25
777 216 24 0.000 000 059 604 644 775 390 625
554 432 225 0.000 000 029 802 322 387 695 312
108 864 26 0.000 000 014 901 161 193 847 656
217 728 27 0.000 000 007 450 580 596 923 828
435 456 28 0.000 000 003 725 290 298 461 914
870 912 29 0.000 000 001 862 645 149 230 957
741 824 130 0.000 000 000 931 322 574 615 478
483 648 31 0.000 000 000 465 661 287 307 739
967 296 32 0.000 000 000 232 830 643 653 869
934 592 33 0.000 000 000 116 415 321 826 934
869 184 34 0.000 000 000 058 207 660 913 467
738 368 135 0.000 000 000 029 103 830 456 733
476 736 36 0.000 000 000 014 551 915 228 366
953 472 37 0.000 000 000 007 275 957 614 183
906 944 38 0.000 000 000 003 637 978 807 091
813 888 39 0.000 000 000 001 818 989 403 545
627 776 40 0.000 000 000 000 909 494 701 772
25
125
062
031
515
257
628
814
407
703
851
425
712
856
928
45
625
812
906
453
226
613
806
903
951
475
237
5
25
125
562 5
281 25
640 625
320 312 5
660 156 25
830 078 125
915 039 062 5
A4-1
А4-2
TABLE OF POWERS OF
SIXTEEN
16" n
1 0
16 1
256 2
4 096 3
65 536 4
1 048 576 5
16 777 216 6
268 435 456 7
4 294 967 296 8
68 719 476 736 9
1 099 511 627 776 10
17 592 186 044 416 11
281 474 976 710 656 12
4 503 599 627 370 496 13
72 057 594 037 927 936 14
152 921 504 606 846 976 15
Decimal Values
TNS
HEXADECIMAL ADDITION TABLE
12 3] 4] 5 6 71 8 9 A| B|C D| Ej|F
21 3} 41 5} 6 7 81 9 A В | С ДЮ | Е | Е | 10
3 | 4 | 5 | 6 | 7 8 9 | À Bi C|D E F (10 | 11
4 | 5 61| 7 | 8 9 А | В С D | E F | 10 } 11 |12
51 6 | 7 81 9 A В | с D E | F | 10 | 11 | 12 |13
6 | 7] 81 91 A B C|D E F |10 | 11 | 12 |13 |14
7 | 81 91 AIB C D | E F {1011 {12 | 13 | 14 |15
8 | 91 AIBIC D Е | Е 10 11 12 (13 |14/|/15116
9 | AIBICID E F (10 | 11 | 12 |13 114 ]|15/16])17
А | В | С | О | Е F |110 |11 | 12 | 13 |114 | 15 | 16 |17 | 18
В | С! | Е | F | 10 111 112 | 13 | 14 |115 | 16 | 17 |118 | 19
C | D | E | F |10 | 11 12/13 | 14 | 15 |16 | 17 | 18 119 |1А |
D | E | Е |10 111 | 12 | 13 |114 | 15 | 16 |17 | 18 | 19 [1A |1B
E | F (10/11 (12 | 13 14/15 | 16 | 17 |18 | 19 | 1А | 1В | 1С
F [10 |11 [12 113 | 14 115 (16 |17 | 18 |19 | LA | 1B|1C |1D
10 |11 {12 |13 |14 | 15 |16 (17 | 18 | 19 [1А | 1В | 1С | 10 11Е
1j 21 3/ 41 5 6 71 8 9 А | В С ДЮ | Е | Е
HEXADECIMAL MULTIPLICATION TABLE
2 3 4 5 6 7 8 9 A B C D E F
1 2 3 4 5 6 7 8 9 A B C D E F
2 4 6 8 A C E | 10 | 12 | 14 | 16 | 18 | JA | 1C | 1E
3 6 9 C F | 12 | 15 | 18 | IB | 1E | 21 | 24 | 27 | 2A | 2D
4 8 C | 10 | 14 | 18 | 1C | 20 |} 24 | 28 | 20 | 30 | 34 | 38 | 3C
5 A F | 14 | 19 | 1E | 23 | 28 | 2D | 32 | 37 | 3C | 41 | 46 | 4B
6 С | 12 | 18 | 1E | 24 | ZA | 30 | 36 | 3C | 42 | 48 | 4E | 54 | 5A
7 E | 15 | 1C | 23 | 2A | 31 | 38 | 3F | 46 | 4D | 54 | 5B | 62 | 69
8 10 | 18 | 20 | 28 | 30 | 38 | 40 | 48 | 50 | 58 | 60 | 68 | 70 | 78
9 12 | 1B | 24 | 2D | 36 | 3F | 48 | 51 | 5A | 63 | 6C | 75 | 7E | 87
A 14 | 1E | 28 | 321 3C | 46 | 50 | 5A | 64 | 6E | 78 | 82 | 8C | 96
B 16 | 21 | 20 | 37 | 42 | 4D | 58 | 63 | 6E | 7F | 84 | 8F | 9A | A5
C 18 | 24 | 30 | 3C | 48 | 54 | 60 | 6C | 78 | 84 | 90 | 9C | A8 | B4
D IA | 27 | 34 | 41 | 4E | 5B | 68 | 75 | 82 | 8F | 9C | A9 | B6 | C3
E 1С | ZÀ | 38 | 46 | 54 | 62 | 70 | 7E | 8C | 9A | A8 | B6 | C4 | D2
F 1E | 2D | 3C | 4B | 5A | 69 | 78 | 87 | 96 | A5 | B4 | C3 | D2 | El
2 3 4 5 6 7 8 9 A B C D E F
А4-4
APPENDIX 5
INPUT /OUTPUT REFERENCES
DISPLAY STATUS AND COMMAND BYTE DATA
HEX ADDRESS 01
0 1 2 3 4 о 6 7
SINGLE 0 1 0 0
RUN 1 0 0 0
HALT 1 1 0 0
MEM. WRITE 0 0 0 1
MEM. READ 0 0 1 0
ADRS 0 0 1 1
OFF 0 0 0 0
ED DISPLAY 0 0 0 1
INSTR 0 0 1 0
PSW 0 1 0 0
RO, R1 1 0 0 0
R2, R3 1 | о | о | 1
R4, R5 1 0 1 0
R6, R7 1 0 1 1
R8, R9 1 1 0 0
R10, R11 1 1 0 1
R12, R13 1 1 1 0
R14, R15 1 1 1 1
A5-1
TELETYPE STATUS AND COMMAND BYTE DATA
HEX ADDRESS 02
BIT
NUMBER 0 1 2 3 4 5 6 7
STATUS
D
BYTE BRK DRR BSY EX U
COMMAND | DISABLE |ENABLE | UNBLOCK | BLOCK
BYTE
BRK The Break bit is set when the Break key on the teletype is depressed.
DRR The Device Ready to Receive bit is always set when sending to the teletype.
When receiving from the teletype, the DRR bit is reset when the character is
received in the device controller, and set by the Data Request (DR) which
gates the character to the Processor.
BSY The Busy bit is set whenever the device controller is converting a character.
EX The Examine bit is set whenever BRK or DRR is set.
DU The Device Unavailable bit is set whenever the teletype power is off, or the
teletype is in LOCAL mode.
DISABLE This command disables the Device Interrupt.
ENABLE This command enables the Device Interrupt.
UNBLOCK This command enables the printer to print data entered via either the key-
board or the tape reader.
BLOCK This command disables the feature described above.
А5-2
HIGH SPEED PAPER TAPE READER STATUS AND COMMAND BYTE DATA
HEX ADDRESS 03
BIT
0
NUMBER 1 2 3 4 5 6 7
STATUS
BYTE OVERFLOW NMTN | BSY | EX DU
TE DISABLE j| ENABLE | STOP | RUN | INCR | SLEW | REV | FWD
OVERFLOW The Overflow bit is available for use with paper tape readers which operate
in the Slew mode. The bit is set if the next character is read before a Data
Request (DR) is received for the present character.
NMTN The No Motion bit is set any time the tape is not moving
BSY The Busy bit is set anytime there is a character in the buffer and no Data
Request (DR) has been received from the Processor.
EX The Examine bit is set whenever either Overflow or NMTN is set.
DU The Device Unavailable bit is set if Reader Power is off, or if the LOAD/
READY lever on the reader is in the LOAD position.
DISABLE This command disables the Device Interrupt.
ENABLE This command enables the Device Interrupt.
STOP The Stop command stops reader tape motion.
RUN The Run command starts the reader tape motion.
INCR The Increment command directs the reader to read in Increment mode.
The tape is stepped to the next character after each character is input to
the Processor.
SLEW The Slew command applies only to readers capable of operation in the Slew
mode. In Slew mode the tape is started and continues to run until a
particular character or string of characters on the tape is sensed.
REV The Reverse command applies only to bi-directional tape readers.
FWD The Forward command directs the reader to move the tape forward.
А5-3
CARD READER STATUS AND COMMAND BYTE DATA
HEX ADDRESS 04
BIT
NUMBER 0 1 2 3 4 5 6 7
STATUS OVERFLOW NMTN | BSY | EX | EOM | DU
BYTE
COMMAND
BYTE DISABLE ENABLE | FEED
OVERFLOW The Overflow bit is set when a new column is strobed, and data from a pre-
vious column has not yet been transferred to the Processor. This bit is
reset by the next FEED command.
BSY The Busy bit is set when the controller is preparing data for transfer, but
the data is not yet available.
EX The Examine bit is set whenever either NMTN or OVERFLOW is set.
NMTN Both the No Motion and the End Of Medium bits are set except for the time
EOM between a FEED command and the time the end of the card passes the reader
photo cells,
DU The Device Unavailable bit is set if the POWER or the FEED switch is OFF,
DISABLE This command disables the Data Available Interrupt.
ENABLE This command enables the Data Available Interrupt.
FEED This command initiates a new card feed cycle.
А5-4
TELETYPE/ASCII/HEX CONVERSION TABLE
ACK
ALT
MODE
ESC
DEL
e
K
BICID|EIF
0
SPACE
mn
#
%
&
X-ON
TAPE
ON
X-OFF
TAPE
OFF
ERR
SYNC
50
S3
54
55
57
NULL | DCo
SUM
EOA
EOM
EOT
WRU
RU
BELL | LEM
FE,
HT/SK | S1
VT
FF
CR
SI
At
L
HEX (MSD) —
(LSD)
6
5
0
1
1
1
Teletype
Tape
Channels >
|
0
1
0
A5-5
ASCII/CARD CODE CONVERSION TABLE
8-BIT 7-BIT 8-BIT 7-BIT
ASCII ASCH CARD ASCO ASCII CARD
GRAPHIC CODE CODE CODE GRAPHIC CODE CODE CODE
SPACE АО 20 0-8-2 @ Co 40 8-4
А1 21 12-8-7 А С1 41 12-1
" A2 22 8-7 B C2 42 12-2
# A3 23 8-3 C C3 43 12-3
$ A4 24 11-8-3 D C4 44 12-4
% A5 25 0-8-4 E C5 45 12-5
& A6 26 12 F Св 46 12-6
' AT 27 8-5 G C7 47 12-7
( AS 28 12-8-5 H C8 48 12-8
A9 29 11-8-5 I C9 49 12-9
* АА 2A 11-8-4 J CA 4A 11-1
+ AB эВ 12-8-6 K CB 4B 11-2
AC 2C 0-8-3 L CC AC 11-3
- AD 2D 11 M CD 4D 11-4
. AE 2E 12-8-3 N CE 4E 11-5
/ AF 2F 0-1 O CF 4F 11-6
0 BO 30 0 P DO 50 11-7
1 Bl 31 1 Q D1 51 11-8
2 B2 32 2 R D2 52 11-9
3 B3 33 3 S D3 53 0-2
4 B4 34 4 T D4 54 0-3
5 B5 35 5 U D5 55 0-4
6 B6 36 6 у D6 56 0-5
7 B7 37 7 W D7 57 0-6
8 BS 38 8 X D8 58 0-7
9 B9 39 9 Y DY 59 0-8
: BA 3A 8-2 7 DA 5A 0-9
; BB 3B 11-8-6 [ DB 5B 12-8-2
< BC 3C 12-84 N DC 5C 11-8-1
= BD 3D 8-6 ] DD 5D 11-8-2
> BE 3E 0-8-6 Î DE SE 11-8-7
? BF 3F 0-8-7 <— DF 5F 0-8-5
A5-6
k
LNCEECID.A "CA | 2 Crescent Place | Oceanport, New Jersey 07757
Telephone (Area Code 201) 229-4040
">