The M41T93 is a low-power serial SPI bus real-time clock (RTC) with a built-in 32.768 kHz oscillator (external crystal-controlled for the QFN16 package, and embedded crystal for the

SOX18 package). Eight bytes of the register map are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 17 bytes of the register map provide status/control of the two alarms, watchdog, 8-bit counter, and square wave functions. An additional seven bytes are made available as user SRAM.

Addresses and data are transferred serially via a serial SPI bus-compatible interface. The built-in address register is incremented automatically after each WRITE or READ data byte.

The M41T93 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the clock operations can be supplied by a small lithium button battery when a power failure occurs.

Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupt, watchdog timer, programmable 8-bit counter, and square wave outputs. The eight clock address locations contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. The M41T93 is supplied in either a

QFN16 or an SOX18, 300 mil SOIC which includes an embedded 32 KHz crystal. The

SOX18 package requires only a user-supplied battery to provide non-volatile operation.

6/56 DocID12615 Rev 8

M41T93 Description

(1)

SDI

SCL

Figure 1. Logic diagram

VBAT VCC

SQW

(2)

IRQ/OUT/FT

(3)

RST

(3)

SDO

VSS

1. For QFN16 package only

2. Defaults to 32 KHz on power-up

3. Open drain

Symbol

(1)

IRQ/FT/OUT

SQW

(2)

RST

SDI

SDO

Table 1. Signal names

32 KHz oscillator input

32 KHz oscillator output

Description

Interrupt/frequency test/output driver (open drain)

32 KHz programmable square wave output

Power-on reset output (open drain)

Chip enable

Serial data address input

Serial data address output

SCL

BAT

(3)

Serial clock input

Battery supply voltage (tie V

BAT

to V

if no battery is connected)

Do not use

Supply voltage

Ground

1. For QFN16 package only

2. Defaults to 32 KHz on power-up

3. Do not use (must be tied to V

)

AI11818

DocID12615 Rev 8 7/56

Description

Figure 2. QFN16 connections

RST

(1)

SQW

(2)

16 15 14 13

M41T93

7 8

12 SDO

IRQ/FT/OUT

(1)

10 SCL

9 SDI

1. Open drain output

2. Defaults to 32 KHz on power-up

Figure 3. SOX18 connections

(1)

RST

(2)

(3)

SQW

(4)

VBAT

VSS

M41T93

(1)

VCC

SDO

IRQ/FT/OUT

(2)

SCL

SDI

1. NF pins must be tied to V

. Pins 2 and 3, and 16 and 17 are internally shorted together.

2. Open drain output

3. Do not use (must be tied to V

)

4. Defaults to 32 KHz on power-up

M41T93

AI11819

AI11820

8/56 DocID12615 Rev 8

M41T93

CRYSTAL

SDI

SCL

SDO

Figure 4. Block diagram

32KHz

OSCILLATOR

SPI

INTERFACE

WRITE

PROTECT

VCC < VRST

(2)

REAL TIME CLOCK

CALENDAR

OSCILLATOR FAIL

CIRCUIT

ALARM1

ALARM2

OFIE

A1IE

WATCHDOG

FREQUENCY TEST

OUTPUT DRIVER

8-BIT COUNTER

SQUARE WAVE

8 BITS OF OTP

USER SRAM (7 Bytes)

OUT

TIE

SQWE

INTERNAL

POWER

VCC

VBAT

VRST/VSO

(2)

COMPARE trec

TIMER

1. Open drain output

2. V

RST

= V

= 2.93 V (S), 2.63 V (R), and 2.32 V (Z)

SQW

Description

IRQ/FT/OUT

(1)

RST

(1)

AI11821

DocID12615 Rev 8 9/56

Description M41T93

Figure 5. Hardware hookup

VCC

M41T93

VCC

IRQ/FT/OUT

(1)

RST

(1)

SCL

VBAT

SDO

SDI

VSS

SQW

MCU

(ST6, ST7, ST9, ST10, Others)

VCC

INT

Reset Input

SCL

SDI

SDO

(2)

SPI Interface with

(CPOL = 0, CPHA = 0)

32KHz CLKIN

AI11822

1. Open drain output

2. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.

Mode

Disable reset

Table 2. Function table

SCL

Input disabled

SDI

Input disabled

WRITE L Data bit latch

AI04630

READ L X

AI04631

1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.

SDO

High Z

Next data bit shift

(1)

Figure 6. Data and clock timing

CPOL = 0, CPHA = 0

SCL

SDI MSB LSB

SDO MSB LSB

AI04632

Note: Supports SPI mode 0 (CPOL = 0, CPHA = 0) only.

10/56 DocID12615 Rev 8

M41T93

1.1

1.1.1

1.1.2

1.1.3

1.1.4

Description

SPI signal description

Serial data output (SDO)

The output pin is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock.

Serial data input (SDI)

The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock.

Serial clock (SCL)

The serial clock provides the timing for the serial interface (as shown in

Figure 23 on page 48

and

Figure 24 on page 48

). The W/R bit, addresses, or data are latched, from the input pin, on the rising edge of the clock input. The output data on the SDO pin changes state after the falling edge of the clock input.

The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode

0: (CPOL, CPHA) = (0,0).

For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and

output data (SDO) is shifted out on the high-to-low transition of SCL (see

Table 2 on page 10

and

Figure 6 on page 10

Chip enable (E)

When E is high, the memory device is deselected, and the SDO output pin is held in its high impedance state.

After power-on, a high-to-low transition on E is required prior to the start of any operation.

DocID12615 Rev 8 11/56

Operation

2 Operation

2.1

M41T93

The M41T93 clock operates as a slave device on the SPI serial bus. It is accessed by a simple serial interface that is SPI bus-compatible. The bus signals are SCL, SDI, SDO, and E (see

Table 1 on page 7

and

Figure 5 on page 10

). The device is selected when the

chip enable input (E) is held low. All instructions, addresses and data are shifted serially in and out of the chip. The most significant bit is presented first, with the data input (SDI) sampled on the first rising edge of the clock (SCL) after the chip enable (E) goes low. The 32 bytes contained in the device can then be accessed sequentially in the following order:



1 st

byte: tenths/hundredths of a second register



2 nd

byte: seconds register



3 rd

byte: minutes register



4 th

byte: century/hours register



5 th

byte: day register



6 th

byte: date register



7 th

byte: month register



8 th

byte: year register



9 th

byte: digital calibration register



10 th

byte: watchdog register



11 th

- 15 th

bytes: alarm 1 registers



16 th

byte: flags register



17 th

byte: timer value register



18 th

byte: timer control register



19 th

byte: analog calibration register



20 th

byte: square wave register



21 st

- 25 th

bytes: alarm 2 registers



26 th

- 32 nd

bytes: user RAM

The M41T93 clock continually monitors V

CC fall below V

RST

for an out-of tolerance condition. Should V

CC counter. Inputs to the device will not be recognized at this time to prevent erroneous data

, the device terminates any access in progress and resets the device address from being written to the device from an out-of-tolerance system.

The power input will also be switched from the V

pin to the external battery when V

CC falls below the battery back-up switchover voltage (V

= V

RST

). At this time the clock registers will be maintained by the battery supply. As system power returns and V

rises above V

, the battery is disconnected, and the power supply is switched to external V

The device remains write protected until t

REC

PFD seconds elapse after V

CC rises above

(min). For more information on battery storage life refer to application note AN1012.

SPI bus characteristics

The serial peripheral interface (SPI) bus is intended for synchronous communication between different ICs. It consists of four signal lines: serial data input (SDI), serial data output (SDO), serial clock (SCL) and a chip enable (E).

12/56 DocID12615 Rev 8

M41T93 Operation

By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

The E input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data transfer between the master (micro) and the slave (M41T93) device.

The SCL input, which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus (see

Figure 5 on page 10

The M41T93 can be driven by a microcontroller with its SPI peripheral running in only mode

0: (CPOL, CPHA) = (0,0).

For this mode, input data (SDI) is latched in by the low-to-high transition of clock SCL, and

output data (SDO) is shifted out on the high-to-low transition of SCL (see

Table 2

and

Figure 6 on page 10

There is one clock for each bit transferred. Address and data bits are transferred in groups of eight bits. Since only 32 addresses are required, address bit 6 is a “don’t care”.

2.2

Note:

READ and WRITE cycles

Address and data are shifted MSB first into the serial data input (SDI) and out of the serial data output (SDO). Any data transfer considers the first bit to define whether a READ or

WRITE will occur. This is followed by seven bits defining the address to be read or written.

Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE operation. The address is always the second through the eighth bit written after the enable

(E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a '0,' one or more READ cycles will occur (see

Figure 7

and

Figure 8 on page 14

Data transfers can occur one byte at a time or in multiple byte burst mode, during which the address pointer will be automatically incremented. For a single byte transfer, one byte is read or written and then E is driven high. For a multiple byte transfer all that is required is that E continue to remain low. Under this condition, the address pointer will continue to increment as stated previously. Incrementing will continue until the device is deselected by taking E high. The address will wrap to 00h after incrementing to 3Fh.

Reads and writes of the internal counters are performed through a set of buffer/transfer registers as shown in

Figure 9 on page 17

. At the start of any read or write cycle, the counters are copied to the buffer/transfer registers. Thus, the time/date is effectively frozen for the user until the access is completed, although the counters are still running and maintaining the correct time.

This is true both in READ and WRITE mode.

DocID12615 Rev 8 13/56

Operation M41T93

Figure 7. READ mode sequence

0 1 2 3 4 5

7 8 9 12 13 14 15 16 17

SCL

W/R BIT

SDI

SDO

7 BIT ADDRESS

MSB

6 5 4

2 1 0

HIGH IMPEDANCE

DATA OUT

(BYTE 1)

DATA OUT

(BYTE 2)

MSB

5 4 3 2 1 0 7

MSB

6 5 4 3 2 1 0

AI04635

Figure 8. WRITE mode sequence

4 5

6 7 8 9 10 15

SCL

W/R BIT

SDI

SDO

7 BIT ADDR

DATA BYTE

MSB

6 5 4 3 2 1

0 7

MSB

6 5 4 3 2 1 0 7

HIGH IMPEDANCE

AI04636

14/56 DocID12615 Rev 8

M41T93

2.3

Operation

Data retention and battery switchover (V

SO

= V

RST

)

Once V

falls below the switchover voltage (V

= V

RST

), the device automatically switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life (see

Figure 22 on page 47

). At this time the clock registers and user

RAM will be maintained by the attached battery supply.

When it is powered back up, the device switches back from battery to V

CC hysteresis. When V

rises above V

RST on battery storage life refer to application note AN1012.

at V

, it will recognize the inputs. For more information

2.4

Note:

Power-on reset (t rec

)

The M41T93 continuously monitors V

CC typical) after V

rises above V

RST

. When V

falls to the power fail detect trip point, the RST output pulls low (open drain) and remains low after power-up for t rec

(max).

(210 ms

The t rec below V

period does not affect the RTC operation. Write protect only occurs when V

RST

. When V

rises above V

RST output is affected by the t rec

RST

period.

, the RTC will be selectable immediately. Only the

The RST pin is an open drain output and an appropriate pull-up resistor to V

CC chosen to control the rise time.

should be

DocID12615 Rev 8 15/56

Clock operation M41T93

Note:

The M41T93 is driven by a quartz-controlled oscillator with a nominal frequency of

32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC.

The 8-byte clock register (see

Table 3 on page 20

) is used to both

set the clock and to read the date and time from the clock, in binary coded decimal format.

Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers.

Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical).

Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST bit to '0.' This provides an additional “kick-start” to the oscillator circuit.

Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0

(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The ninth clock register is the digital calibration register, while the analog calibration register is found at address 12h (these are both described in the clock calibration section). Bit D7 of register 09h (watchdog register) contains the oscillator fail interrupt enable bit (OFIE). When the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see

Oscillator fail detection on page 38

) will also generate an interrupt output.

A WRITE to ANY location within the first eight bytes of the clock registers (00h-07h), including the ST bit and CB0-CB1 bits will result in an update of the RTC counters and a reset of the divider chain. This could result in an inadvertent change of the current time. For example, the ST bit is in the seconds register (address 01h) and the century bits (CB0-CB1) are in the hours register (address 03h), so the user should take care to not alter these other parameters when changing the ST bit or the century bits.

The eight clock registers may be read one byte at a time, or in a sequential block. At the start of a read cycle, a copy of the time/date counters is placed in the buffer/transfer registers and can then be transferred out sequentially without concern that the time/date increments during the transfer and thus yields a corrupt value. For example, if the user were to read the seconds register, then start another bus cycle to read the minutes register, the minutes counter could have incremented during the time between the two read cycles. The seconds and minutes values would not be from the same instant in time; they would not be coherent. By using the sequential read feature, the values shifted out are from the same instant in time and are thus coherent.

Similarly, when writing to the RTC registers, during one write cycle, the user can sequentially transfer all eight bytes of time/date into the buffer/transfer registers whereupon they will be loaded simultaneously into the RTC counters thus ensuring a coherent update of the time/date.

16/56 DocID12615 Rev 8

M41T93

3.1

SDI

SCL

SDO

Clock operation

Clock data coherency

In order to synchronize the data during reads and writes of the real-time clock device, a set of buffer transfer registers resides between the SPI serial interface on the user side, and the clock/calendar counters in the part. While the read/write data is transferred in and out of the device one bit at a time to the user, the transfers between the buffer registers and counters occur such that all the bits are copied simultaneously. This keeps the data coherent and ensures that none of the counters are incremented while the data is being transferred.

Figure 9. Clock data coherency

32KHz

OSC

RTC

COUNTERS

AT START OF READ OR WRITE,

DATA IN COUNTERS IS COPIED TO

BUFFER/TRANSFER REGISTERS.

READ / WRITE

BUFFER-TRANSFER

REGISTERS

SPI

INTERFACE

SECONDS

MINUTES

HOURS

DAY-OF-WEEK

DATE

MONTHS

YEARS

CENTURIES

DIVIDE BY 32768

1 Hz

COUNTER

AFTER A WRITE, DATA IS TRANSFERRED

FROM BUFFERS TO COUNTERS

NON-CLOCK

REGISTERS

SQUAREWAVE

CALIBRATION

HALT BIT SET AT POWER-DOWN

ALARM / HALT

WATCHDOG

3.1.1 Example of incoherency

Without having the intervening buffer/transfer registers, if the user began directly reading the counters at 23:59:59, a read of the seconds register would return 59 seconds. After the address pointer incremented, the next read would return 59 minutes. Then the next read should return 23 hours, but if the clock happened to increment between the reads, the user would see 00 hours. When the time was re-assembled, it would appear as 00:59:59, and thus be incorrect by one hour.

By using the buffer/transfer registers to hold a copy of the time, the user is able to read the entire set of registers without any values changing during the read.

Similarly, when the application needs to change the time in the counters, it is necessary that all the counters be loaded simultaneously. Thus, the user writes sequentially to the various buffer/transfer registers, then they are copied to the counters in a single transfer thereby coherently loading the counters.

DocID12615 Rev 8 17/56

Clock operation

3.1.2 Accessing the device

M41T93

The M41T93 is comprised of 32 addresses which provide access to registers for time and date, digital and analog calibration, two alarms, watchdog, flags, timer, squarewave and

NVRAM. The clock and alarm parameters are in binary coded decimal (BCD) format. The calibration, timer, watchdog, and squarewave parameters are in a binary format.

In the case of the M41T93, at the start of each read or write serial transfer, the counters are automatically copied to the buffer registers. In the event of a write to any register in the range 0-7, at the end of the serial transfer, the buffer registers are copied back into the counters thus revising the date/time. Any of the eight clock registers (addresses 0-7) not updated during the transfer will have its old value written back into the counters. For example, if only the seconds value is revised, the other seven counters will end up with the same values they had at the start of the serial transfer.

However, writes which do not affect the clock registers - that is, a write only to the non-clock registers (addresses 0x08 to 0x1F) - will not cause the buffer registers to be copied back to the counters. The counters are only updated if a register in the range 0-7 was written.

Whenever the RTC registers (addresses 0-7) are written, the divider chain from the oscillator is reset.

3.2

Note:

Halt bit (HT) operation

When the part is powered down into battery backup mode, a control bit, called the Halt or

HT bit, is set automatically. This inhibits any subsequent transfers from the counters to the buffer registers thereby freezing in the buffer registers the time/date of the last access of the part.

Repeated reads of the clock registers will return the same value. After the HT bit is cleared, by writing bit 6 of address 0x0C to 0, the next read of the RTC will return the present time.

Writes to the RTC registers (addresses 0-7) with the HT bit set can cause time corruption.

Since the buffer registers contain the time of the last access prior to the HT bit being set, any write in the address range 0-7 will result in the time of the last access being copied back into the counters.

Example: The last access was November 17, 2009, at 16:15:07.77. The system later powered down thus setting the HT bit and freezing that value in the buffers. Later, on

December 18, 2009, at 03:22:43.35, the system is powered up and the user writes the seconds to 46 without first clearing the HT bit. At the end of the serial transfer, the old time/date, with the seconds modified to 46, will be written back into the clock registers thereby corrupting them. The new, wrong time will be November 17, 2009, at 16:15: 46 .77.

This makes it appear the RTC lost time during the power outage.

Thus, at power-up, the user should always clear the HT bit (write bit 6 to 0 at address 0x0C) before writing to any address in the range 0-7.

A typical power-up flow is to read the time of last access, then clear the HT bit, then read the current time.

18/56 DocID12615 Rev 8

M41T93

3.2.1

Clock operation

Power-down time stamp

Some applications may need to determine the amount of time spent in backup mode. That can be calculated if the time of power-down and the time of power-up are known. The latter is straightforward to obtain. But the time of power-down is only available if an access occurred just prior to power-down. That is, if there was an access of the device just prior to power-down, the time of the access would have been frozen in the buffer transfer registers and thus the approximate time of power-down could be obtained.

If an application requires the time of power-down, the best way to implement it is to set up the software to do frequent reads of the clock, such as once every 1 or 5 seconds. That way, at power-up, the buffer-transfer registers will contain a time value within 1 (or 5) seconds of the actual time of power-down. For more information, please refer to AN1572,

“Power-down time-stamp function in serial real-time clocks (RTCs)”.

DocID12615 Rev 8 19/56

Clock operation M41T93

Table 3. Clock/control register map (32 bytes)

Addr

Function/range BCD format

D7 D6 D5 D4 D3 D2 D1 D0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Fh

10h

11h

CB1

OUT

0.1 seconds

CB0

10 seconds

10 minutes

10 hours

10 Years

FT DCS

10 date

10M

DC4 DC3

Year

DC1

OFIE BMB4 BMB3 BMB2 BMB1 BMB0

A1IE SQWE ABE Al1 10M

RB1

Alarm1month

0Bh RPT14 RPT15

0Ch RPT13 HT

0Dh RPT12

0Eh RPT11

WDF

AI1 10 date

AI1 10 hour

Alarm1 10 minutes

TI/TP TIE 0

0.01 seconds

Seconds

Minutes

Hours (24-hour format)

Day of week

Date: day of month

Month

Alarm1 10 seconds

AF1 AF2

(1)

BL TF

Timer countdown value

DC2

Alarm1 date

Alarm1 hour

Alarm1 minutes

Alarm1 seconds

TD1

Seconds

Minutes

00-99

00-59

Century/hours 0-3/00-23

Day 01-7

Date

Month

01-31

01-12

00-99 Year

DC0 Digital calibration

RB0 Watchdog

Al1 month

Al1 date

Al1 hour

Al1 min

Al1 sec

01-12

01-31

00-23

00-59

TD0

12h

16h

17h

ACS

RPT23

RPT22

18h RPT21

19h-

1Fh

AC6

13h RS3 RS2

14h 0 0

15h RPT24 RPT25

AC5 AC4

RS1 RS0

0 Al2 10M

AI2 10 date

0 AI2 10 hour

Alarm2 10 minutes

Alarm2 10 seconds

AC3

User SRAM (7 bytes)

AC2

AC1

AL2E

Alarm2 month

Alarm2 date

Alarm2 minutes

Alarm2 seconds

AC0

OTP

Flags

Timer value

Timer control

Analog calibration

SQW

SRAM/Al2 month 01-12

SRAM/Al2 date 01-31

SRAM/Al2 hour

SRAM/Al2 min

SRAM/Al2 sec

00-23

00-59

SRAM

1. AF2 will always read 0 if the AL2E bit is set to 0.

0 = Must be set to zero

ABE = Alarm in battery backup enable bit

A1IE = Alarm1 interrupt enable bit

AC0-AC6 = analog calibration bits

ACS = analog calibration sign bit

AF1, AF2 = Alarm flag

AL2E = Alarm 2 enable bit

BL = Battery low bit

BMB0-BMB4 = Watchdog multiplier bits

CB0, CB1 = Century bits

DC0-DC4 = Digital calibration bits

DCS = Digital calibration sign bit

FT = Frequency test bit

HT = Halt update bit

OF = Oscillator fail bit

OUT= Output level

OFIE = Oscillator fail interrupt enable

OTP = OTP control bit

RB0-RB2 = Watchdog resolution bits

RPT11-RPT15 = Alarm 1 repeat mode bits

RPT21-RPT25 = Alarm 2 repeat mode bits

RS0-RS3 = SQW frequency

SQWE = Square wave enable

SRAM/ALM2 = SRAM/Alarm 2 bit

ST = Stop bit

TD0, TD1 = Timer frequency bits

TE = Timer enable bit

TF = Timer flag

TI/TP = Timer interrupt or pulse

TIE = Timer interrupt enable

WDF = Watchdog flag

20/56 DocID12615 Rev 8

M41T93

3.3

Clock operation

Real-time clock accuracy

The M41T93 is driven by a quartz controlled oscillator with a nominal frequency of

32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Temperature also affects the crystal frequency, causing additional error (see

Figure 11 on page 26

The M41T93 provides the option of clock correction through either manufacturing calibration or in-application calibration. The total possible compensation is typically –93 ppm to +156 ppm. The two compensation circuits that are available are:

The analog calibration register (12h) can be used to adjust internal (on-chip) load capacitors for oscillator capacitance trimming. There are two load capacitors C

(see

Figure 10

), nominally 25 pF each, one on either side of the crystal. The

effective load capacitance is the series equivalent of C

25 pF, the effective load capacitance is 12.5pF.

and C

and

. For the nominal

Writing to the analog calibration register adjusts both capacitors by the same amount.

That is, the two capacitors will always have the same value. They can be adjusted up or down in 0.25 pF steps. The maximum adjustment up is +9.75 pF for a total of

34.75 pF (17.4 pF effective load) to slow the oscillator. The maximum downward adjustment is –18 pF for a total of 7 pF (3.5 pF effective load) to speed up the oscillator.

2. A digital calibration register (08h) can also be used to adjust the clock counter by adding or subtracting a pulse at the 512 Hz divider stage. This approach provides periodic compensation of approximately –63 ppm to +126 ppm (see

Digital calibration

(periodic counter correction) on page 22

This range of load values translates to an approximate frequency range adjustment of

–15 to +95 ppm (see

Analog calibration (programmable load capacitance) on page 25

Figure 10. Internal load capacitance adjustment

CXI

CXO

Crystal Oscillator

AI11804

DocID12615 Rev 8 21/56

Clock operation M41T93

3.4.1

The M41T93 oscillator is designed for use with a 12.5 pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at

25 °C.

The M41T93 design provides the following two methods for clock error correction.

Digital calibration (periodic counter correction)

This method employs the use of periodic counter correction by adjusting the ratio of the

100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100Hz divider stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to provide the input frequency to the fraction of seconds clock register. By adjusting the number of

512 Hz input pulses used to generate 100 output pulses, the clock can be sped up or slowed down, as shown in

Figure 13 on page 29

When a non-zero value is loaded into the five calibration bits (DC4 – DC0) found in the digital calibration register (08h) and the sign bit is 1, (indicating positive calibration), the

100 Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512. Since the 100 pulses are now being output in a shorter window, this has the effect of speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when the sign bit is 0, indicating negative calibration, the block outputs 100 pulses for every 513 input pulses.

Since the 100 pulses are then being output in a longer window, this has the effect of slowing down the clock by 1/512 seconds for each second the circuit is active.

The amount of calibration is controlled by using the value in the calibration register (N) to generate the adjustment in one second increments. This is done for the first N seconds once every eight minutes for positive calibration, and for N seconds once every sixteen minutes for negative calibration

(see

Table 4 on page 24

For example, if the calibration register is set to '100010,' then the adjustment will occur for two seconds in every minute. Similarly, if the calibration register is set to '000011,' then the adjustment will occur for 3 seconds in every alternating minute.

The digital calibration bits (DC4 – DC0) occupy the five lower order bits in the digital calibration register (08h). These bits can be set to represent any value between 0 and 31 in binary form. The sixth bit (DCS) is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative) cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or –2.034 ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month, which corresponds to a total range of +5.5 or –2.75 minutes per month.

One method of determining the amount of digital calibration required is to use the frequency test output (FT) of the device (see

Section 3.14: IRQ/FT/OUT pin, frequency test, interrupts and the OUT bit on page 38

for more information on enabling the FT output).

When FT is enabled, a 512 Hz signal is output on the IRQ/FT/OUT pin. This signal can be measured using a highly accurate timing device such as a frequency counter. The measured value is then compared to 512 Hz and the oscillator error in ppm is then determined.

The user should keep in mind that changes in the digital calibration value will not affect the signal measured on the FT pin. While the analog calibration circuit does affect the oscillator,

22/56 DocID12615 Rev 8

M41T93 Clock operation

the digital calibration circuitry uses periodic counter correction which occurs downstream of the 512 Hz divider chain and hence has no effect on the FT pin.

Note: 1 The modified pulses are not observable on the frequency test (FT) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation.

2 Positive digital calibration is performed on an eight minute cycle, therefore the value in the calibration register should not be modified more frequently than once every eight minutes for positive values of calibration. Negative digital calibration is performed on a sixteen minute cycle, therefore negative values in the calibration register should not be modified more frequently than once every sixteen minutes.

DocID12615 Rev 8 23/56

Clock operation M41T93

15 (01111)

16 (10000)

17 (10001)

18 (10010)

19 (10011)

20 (10100)

21 (10101)

22 (10110)

23 (10111)

24 (11000)

25 (11001)

26 (11010)

27 (11011)

28 (11100)

29 (11101)

30 (11110)

31 (11111)

0 (00000)

1 (00001)

2 (00010)

3 (00011)

4 (00100)

5 (00101)

6 (00110)

7 (00111)

8 (01000)

9 (01001)

10 (01010)

11 (01011)

12 (01100)

13 (01101)

14 (01110)

Calibration value (binary)

Table 4. Digital calibration values

Calibration value rounded to the nearest ppm

DC4 – DC0

Negative calibration (DCS = 0) to slow a fast clock

Positive calibration (DCS = 1) to speed up a slow clock

–39

–41

–43

–45

–31

–33

–35

–37

–55

–57

–59

–61

–47

–49

–51

–53

–63

N/491520 (per minute)

–22

–24

–26

–28

–14

–16

–18

–20

–2

–4

–6

–8

–10

–12

110

114

118

122

102

106

126

N/245760 (per minute)

24/56 DocID12615 Rev 8

M41T93

3.4.2

Clock operation

Analog calibration (programmable load capacitance)

A second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. As discussed in

Section 3.4.1

, the 512 Hz frequency test output can be used to determine the amount of frequency error in the oscillator. Changes in the analog calibration value will affect the frequency test output, thus the user can immediately see the effects of these changes (see

Section 3.14 on page 38

for more information on enabling the FT output).

By design, the oscillator is intended to be 0 ppm (± crystal accuracy) at room temperature

(25 °C, see

Figure 11 on page 26

) when a 12.5 pF crystal is connected. Referring to

Figure 12 on page 28

, the device has two load capacitors, C

and C

, connected from the

XI and XO pins to ground. These are nominally 25 pF each. The effective load capacitance is the series equivalent of these two:

LOAD



---------------------------

For the nominal case of C

= C

= 25 pF,

LOAD

25 25

12.5pF

Thus, the nominal effective load capacitance matches the crystal specification of 12.5 pF.

The analog calibration register can be digitally adjusted, up or down, in increments of

0.25 pF, to change the capacitance of C

and C

. The default value is 25 pF. The maximum is 34.75 pF, to slow the clock, and the minimum is 7 pF, to speed up the clock.

The analog calibration value is in sign-magnitude format with the most significant bit the sign bit. The table below shows the approximate weighting for each of the bits.

b7 b6 b5 b4 b3 b2 b1 b0 sign 16 8 4 2 1 0.5

0.25

While the 7 bits plus sign suggest a total adjustment range of ±31.75 pF, the logic inside the device limits this to the range +9.75 pF / –18 pF. The table below summarizes the nominal, upper and lower limits of the load capacitance and the expected effect on the operating frequency of the oscillator.

LOAD

(pF)

, C

(pF)

ACAL

(Addr 0x12)

Oscillator frequency

12.5

17.4

25 (default)

34.75 (+9.75)

0x00

0x27

0 ppm

–15 ppm (slow)

3.5

7 (–18) 0xC8 +95 ppm (fast)

The asymmetrical nature of the adjustment range (+9.75 pF / –18 pF) is due to the nature of the frequency versus temperature curve (

Figure 11

) of 32.768 kHz watch crystals. The oscillator will slow down at temperatures both above and below room level (~25 °C). Hence, it usually needs to be sped up, so more adjustment range is provided to remove capacitance than to increase it.

DocID12615 Rev 8 25/56

Clock operation M41T93

As shown in

Figure 12

, the relationship between oscillator speed and load capacitance is not linear. When operating on the left end of the curve, small changes in load capacitance have more effect than when operating on the right end of the curve. For example, at –15 pF, a 3 pF reduction to –18 pF should result in the part running about 30 ppm faster (from

+65 ppm to +95 ppm). Conversely, at +5 pF, adding 3 pF to get to +8 pF should only slow the part by about 4 ppm (from –8 ppm to –12 ppm).

3.4.3 Pre-programmed calibration value

Users of the M41T83 in the embedded crystal package have the option of using the factory programmed analog calibration value (refer to

Section 3.16 on page 42

Figure 11. Crystal accuracy across temperature

Frequency (ppm)

–80

–100

–120

–20

–40

–60

ΔF

= K x (T – T

)

= –0.036 ppm/

°C

± 0.006 ppm/

°C

= 25

°C ± 5°C

–140

–160

–40 –30 –20 –10 0 10 20 30

Temperature

°C

40 50 60 70 80

AI07888

Addr

Analog calibration value

ACS

(±)

Table 5. Analog calibration values

AC6

(16 pF)

AC5

(8 pF)

AC4

(4 pF)

AC3

(2 pF)

AC2

( 1pF)

AC1

(0.5 pF)

AC0

(0.25 pF)

, C

LOAD

(1)

12h

0 pF

3 pF

5 pF

–7 pF

9.75 pF

(2)

–18 pF

(3) x

1. C

LOAD

= 1/(1/C

+ 1/C

)

2. Maximum negative calibration value

3. Maximum positive calibration value

25 pF 12.5 pF

28 pF 14 pF

30 pF

18 pF

15 pF

9 pF

34.75 pF 17.4 pF

7 pF 3.5 pF

26/56 DocID12615 Rev 8

M41T93 Clock operation

The on-chip capacitance can be calculated as follows:

LOAD

= 12.5 + [ACS:(AC6:AC0 value, decimal)] ● 0.125 pF where ACS is the sign.

Examples:

ACAL (addr 12h) = 0

➔

LOAD

= 12.5 pF

ACAL = 10111100b

➔

LOAD

= 5 pF

ACAL = 00010100b

➔

LOAD

= 15 pF

Note:

With the analog calibration adjusted to its lowest value, the oscillator will see a minimum of

3.5 pF load capacitance as shown on the bottom row of

Table 5

These are typical values, and the total load capacitance seen by the crystal will include approximately 1-2 pF of package and board capacitance in addition to the analog calibration register value.

Any invalid value of analog calibration will result in the default capacitance of 25 pF (for C

XI and C

Combining the digital adjustment range (–63 to +126 ppm) and analog adjustment range

(–15 to +95 ppm), the approximate overall adjustment range of the M41T93’s timekeeping is

–78 to +221 ppm.

Figure 12

represents a typical curve of clock ppm adjustment versus the analog calibration value. Actual crystals may vary, so users should evaluate the crystals to be used with an

M41T93 device before establishing the adjustment values for a given application.

DocID12615 Rev 8 27/56

Clock operation M41T93

Figure 12. Clock accuracy vs. on-chip load capacitors

100.0

XI XO

80.0

60.0

Crystal

Oscillator

40.0

20.0

FASTER

0.0

SLOWER

-20.0

OFFSET TO

, C

(pF)

NET EQUIV. LOAD

CAP., C

LOAD

, (pF)

-18.0 -15.0

3.5

5.0

Analog Calibration

Value, AC, register 0x12

0xC8 0xBC

DECREASING LOAD CAP.

-10.0

7.5

0xA8

-5.0

0x94

On-Chip

LOAD

+ C

INCREASING LOAD CAP.

0.0

12.5

0x00

5.0

0x14

9.75

17.4

0x27 ai13906

28/56 DocID12615 Rev 8

M41T93

Note:

32KHz

Clock operation

Two methods are available for ascertaining how much calibration a given M41T93 may require:



The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses either or both of the calibration bytes.



The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT pin. The IRQ/FT/ OUT pin will toggle at 512 Hz when FT and

OUT bits = '1' and ST = '0.' Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of

512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring either a

–10 (xx001010) to be loaded into the digital calibration byte, or +6 pF (00011000) into the analog calibration byte for correction.

Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring either a –10 (xx001010) to be loaded into the digital calibration byte, or +6 pF (00011000) loaded into the analog calibration byte, for correction.

Setting or changing the digital calibration byte does not affect the frequency test, square wave, or watchdog timer frequency, but changing the analog calibration byte DOES affect all functions derived from the low current oscillator (see

Figure 13 ).

Figure 13. Clock divider chain and calibration circuits

512Hz Output

Frequency Test

Remainder of

Divider Circuit

Square Wave

Watchdog Timer

8-bit Timer

CXI

÷64 ÷2

Low Current

Oscillator

CXO

÷64

Digital Calibration Circuitry

(divide by 511/512/513)

1Hz Signal

Clock

Counters

Analog Calibration

Circuitry

AI11806c

DocID12615 Rev 8 29/56

Clock operation M41T93

Figure 14. Crystal isolation example

Crystal

Local Grounding

Plane (Layer 2)

XI XO

VSS

Note:

3.5

Note:

AI11814

The substrate pad should be tied to V

Setting the alarm clock registers

Address locations 0Ah-0Eh (alarm 1) and 14h-18h (alarm 2) contain the alarm settings.

Either alarm can be configured independently to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. Bits RPT15–RPT11 and RPT25-RPT21 put the alarms in the repeat mode of operation.

Table 6 on page 31

shows the possible bit configurations.

Codes not listed in the table default to the once-per-second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT15–RPT11 and/or RPT25-RPT21, AF1 (alarm 1 flag) or AF2 (alarm 2 flag) is set. If A1IE (alarm 1 interrupt enable) is set, the alarm condition activates the IRQ/FT/OUT output pin. To disable either of the alarms, write a '0' to the alarm date registers and to the RPTx5–RPTx1 bits.

If the address pointer is allowed to increment to the flag register address, or the last address written is “Alarm Seconds,” the address pointer will increment to the flag address, and an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address.

The IRQ output is cleared by a READ of the flags register (0Fh). A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to 0.

The IRQ/FT/OUT pin can also be activated in the battery backup mode. This requires the

ABE bit (alarm in backup enable) to be set (see

Section 3.14.2: Backup mode

for additional conditions which apply). Once an interrupt is asserted in backup mode, it will remain true until V

is restored and a subsequent read of the flags register occurs.

30/56 DocID12615 Rev 8

M41T93

3.6

Clock operation

Optional second programmable alarm

When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic 1, registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as the alarm function described above. When the alarm 2 condition is met, the AF2 bit will be set. Reading the flags register (0Fh) will clear it. There is no IRQ2 interrupt output on the M41T93, so no external event can be directly triggered by the alarm 2 function, but the AF2 bit can be polled to initiate a response.

The AL2E bit defaults on initial power-up to a logic 0 (alarm 2 disabled). In this mode, the five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of non-volatile SRAM.

Figure 15. Backup mode alarm waveform

VCC

VPFD

VSO trec

AF1 bit in flags register

IRQ/FT/OUT

HIGH-Z

AI11824

Note: ABE and A1IE bits = 1.

RPT5

RPT4

RPT3

Table 6. Alarm repeat modes

RPT2 RPT1 Alarm setting

Once per second

Once per minute

Once per hour

Once per day

Once per month

Once per year

The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits

RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the

DocID12615 Rev 8 31/56

Clock operation M41T93

specified period, the M41T93 sets the WDF (watchdog flag) and generates a watchdog interrupt.

Watchdog, address 09h

OFIE

BMB4

BMB3

BMB2

BMB1

BMB0

RB1

RB0

The watchdog timer is reset by writing to the watchdog register. The time-out period then starts over.

Watchdog interrupt

On the M41T93, provided that the necessary configuration bits are set, the IRQ/FT/OUT output will be asserted when the watchdog times out (see

Section 3.14

for additional conditions which apply).

Should the watchdog time out, to de-assert the IRQ/FT/OUT output, the lower seven bits of the watchdog register (09h) must be written. This will de-assert the output and re-initialize the watchdog. Writing these seven bits to 0 will de-assert the output and disable the watchdog.

A READ of the flags register will reset the watchdog flag (bit D7; register OFh) but not deassert the IRQ/FT/OUT output. The watchdog function is automatically disabled upon power-up and the watchdog register is cleared.

3.8 8-bit (countdown) timer

The timer value register is an 8-bit binary countdown timer. It is enabled and disabled via the timer control register (11h) TE bit. Other timer properties such as the source clock, or interrupt generation are also selected in the timer control register (see

Table 7

). For

accurate read back of the countdown value, the serial clock (SCL) must be operating at a frequency of at least twice the selected timer clock.

The timer control register selects one of four source clock frequencies for the timer (4096,

64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a softwareloaded 8-bit binary value (register 10h) and decrements to 1. On the next tick of the counter, it reloads the timer countdown value and sets the timer flag (TF) bit. The TF bit can only be cleared by software. When asserted, the timer flag (TF) can also be used to generate an interrupt (IRQ/FT/OUT) on the M41T93. Writing the timer countdown value (10h) has no effect on the TF bit or the IRQ/FT/OUT output.

32/56

On the M41T93, there are two choices for the output depending on the TI/TP configuration bit (timer interrupt/timer pulse, bit 6, register 11h).

Normal interrupt mode

With TI/TP = 0, the output will assert like a normal interrupt, staying low until the TF bit is cleared by software by reading the flags register (0Fh).

Free-running mode

When TI/TP is a 1, the output is a free-running waveform as depicted in

Figure 16

. After

being low for the specified time (as shown in

Table 8

), the output automatically goes high

DocID12615 Rev 8

M41T93 Clock operation

without need of software clearing any bits. The TF bit will still be set each time the timer reloads, but it is not necessary for the software to clear it in this mode. Furthermore, clearing the TF bit has no effect on the output in this mode.

While writes to the timer countdown register (10h) control the reload value, reads of this register return the current countdown timer value.

Addr

0Fh

10h

11h

D7 D6

Table 7. Timer control register map

D5 D4 D3 D2 D1 D0

WDF

AF1

TI/TP

AF2 BL TF OF

Timer countdown value

(2)

TIE 0

(1)

TD1

1. Bit positions labeled with 0 should always be written with logic 0.

2. Writing to the timer register will not reset the TF bit nor clear the interrupt.

(1)

TD0

Function

Flags

Timer value

Timer control

When the timer is in the free-running mode, with a value of n programmed into the timer countdown value, the output will nominally be low for one cycle of the specified clock source and high for n-1 cycles with an overal period of n cycles. Thus, the countdown period is n/source clock frequency.

For the special case of n = 1, as shown in

Table 8

, when the clock source is 4096 or 64 Hz,

the low time (T

) is half the clock period instead of a full clock period.

Table 8. Timer interrupt operation in free-running mode (with TI/TP = 1)

IRQ low time – T

(seconds)

(1)

Source clock (Hz)

IRQ period – T

IRQ

(seconds) n = 1

(2) n > 1 n = 1 n > 1

4096

1/60

1/8192 = 122 μs 1/4096 = 244 μs 1/4096 = 244 μs

1/128 = 7.8 ms 1/64 = 15.6 ms

1/64

1/64 = 15.6 ms

1 minute

1. IRQ/FT/OUT is asserted coincident with TF going true.

2. n = loaded countdown timer value (0 < n < 255). The timer is stopped when n = 0.

n / 4096 n / 64 n n minutes

Figure 16. Timer output waveform in free-running mode (with TI/TP = 1)

IRQ

IRQ/FT/OUT

AM03012v1

DocID12615 Rev 8 33/56

Clock operation M41T93

3.8.2

3.8.3

3.8.4

Timer flag (TF)

At the end of a timer countdown, when the timer reloads, TF is set to logic 1. Regardless of the state of TF bit (or TI/TP bit), the timer will continue decrementing and reloading.

If both timer and alarm interrupts are used in the application, the source of the interrupt can be determined by reading the flag bits. Refer to

Section 3.14

for more information on the

interaction of these bits. The TF bit is cleared by reading the flags register. This will deassert an interrupt output due to the timer.

Timer interrupt enable (TIE)

In normal interrupt mode (TI/TP = 0), when TF is asserted, the interrupt output is asserted (if

TIE = 1). To de-assert the interrupt, the TF bit or the TIE bit must be reset. Disabling the interrupt by clearing the TIE bit will de-assert the output, but does not clear the TF bit. Thus, if TIE is re-enabled prior to clearing TF, the interrupt will assert immediately.

Timer enable (TE)



TE = 0

When TE = 0, or when the timer register (10h) is set to 0, the timer is disabled.



TE = 1

The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the counter will begin counting from the same value as when it was disabled.

3.8.5 TD1/0

These are the timer source clock frequency selection bits (see

Table 9

). These bits

determine the source clock for the countdown timer (see

Table 7

). When not in use, the TD1

and TD0 bits should be set to 11 (1/60 Hz) for power saving.

Table 9. Timer source clock frequency selection (244.1 μs to 4.25 hrs)

TD1 TD0 Timer source clock frequency (Hz)

4096 (244.1 μs)

64 (15.6 ms)

1 (1 s)

1/60 (60 s)

Note: Writing to the timer register will not reset the TF bit nor clear the interrupt.

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M41T93

3.9

Note:

Clock operation

RS3

Square wave output

The M41T93 offers the user a programmable square wave function which is output on the

SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These

frequencies are listed in

Table 10

. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah.

If the SQWE bit is set to '1', and V

CC squarewave output will be disabled.

falls below the switchover (V

) voltage, the

Square wave bits

RS2

Table 10. Square wave output frequency

RS1

RS0

Square wave

Frequency

128

None

32.768

8.192

4.096

2.048

1.024

512

256

Units

Hz kHz kHz

– kHz kHz kHz

DocID12615 Rev 8 35/56

Clock operation M41T93

3.10 Battery low warning

The M41T93 automatically checks the battery each time V

CC clock rolls over at midnight.

powers up and each time the

BAT

is compared to V

(approximately 2.5 V), then the battery low (BL) bit, D4 of flags register 0Fh, is set if the battery voltage is found to be less than V greater than V

, the BL bit is cleared during battery check.

. Similarly, if V

BAT

The BL bit retains its state until the next battery check occurs. This means the BL bit will not clear immediately upon battery replacement, but only after the next battery check occurs at the next power-up or midnight rollover.

If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity. Clock data should be considered suspect and verified as correct. A fresh battery should be installed.

If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V

CC is supplied. In order to ensure data integrity during subsequent periods of battery backup mode, the battery should be replaced.

Midnight rollover check

As shown in

Figure 17

,during the midnight rollover check, the M41T93 applies a load to the battery, then compares V

BAT

to V

BL and updates the BL bit accordingly. Because a load is present, an open condition on the V

BAT

pin will result in the BL bit being set. After the check is performed, the RTC removes the load.

Power-up battery check

During the power-up check, no load is applied to the battery under the assumption the battery has already been stressed to its working level by having powered the RTC in backup mode. If no battery is present, V

BAT indeterminate.

will be floating and the battery check result will be

Figure 17. Battery check

At power-up and at rollover

BAT

Only at rollover

=2.5V

AM03009v1

36/56 DocID12615 Rev 8

M41T93 Clock operation

The M41T93 only checks the battery when powered by VCC. It does not check the battery while in backup mode. Thus, users are advised that during long periods in backup mode, the battery can drop to a level at which timekeeping may fail or data becomes corrupted. If, at power-up, a battery low is indicated, data integrity should be verified.

Forcing a battery check

If it is desired to check the battery at an arbitrary time, one common technique is for the application software to write the time to just before midnight, 23:59:59, and then wait two seconds thereby letting the clock rollover and causing the BL bit to update. The application then restores the time back to its previous value plus two seconds.

The M41T93 includes 2 century bits (CB1, CB0) which function as a 2-bit binary counter that increments at the end of each century. The user may arbitrarily assign the meaning of

CB1:CB0 to represent any century value, but the simplest way of using these bits is to extend the year register by mapping them directly to bits 9 and 8 (with the year register comprising bits 7:0). Higher order century bits can be maintained in the application software.

Figure 18. Two-bit binary counter (century bits CB1:CB0)

CB1:CB0

Century

2000 -2099

2100 - 2199

2200 - 2299

2300 - 2399

Example: 16-bit year value

MAINTAIN

ADDITIONAL

YEAR BITS IN

SOFTWARE

LOWER 8 BITS

CONTAINED IN

YEAR REGISTER

(07h)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CB1:CB0

00 01

11 10

LET CB1:CB0 REPRESENT

BITS 9 AND 8 TO EXTEND

THE YEAR REGISTER

In this example, CB1:CB0 represent the two lower bits of the century byte.

Leap year

Leap year occurs every four years, in years which are multiples of 4. For example, 2012 was a leap year. An exception to that is any year which is a multiple of 100. For example, the year 2100 is not a leap year. A contradiction to that is that years which are multiples of 400 are indeed leap years. Hence, while 2100 is not a leap year, 2400 is.

During any year which is a multiple of 4, ST RTC and TIMEKEEPER devices will automatically insert leap day, February 29. Therefore, the application software must correct for this during the exception years (2100, 2200, etc.) as noted above.

DocID12615 Rev 8 37/56

Clock operation M41T93

3.12 Oscillator fail detection

Note:

If the oscillator fail (OF) bit is internally set to a 1, this indicates that the oscillator has either stopped, or was stopped for some period of time. This bit can be used to judge the validity of the clock and date data. This bit will be set to 1 any time the oscillator stops.

In the event the OF bit is found to be set to 1 at any time other than the initial power-up, the

STOP bit (ST) should be written to a 1, then immediately reset to 0. This will restart the oscillator. This is called kick-starting, and it injects extra current into the oscillator for a short period of time to help it get started.

The following conditions can cause the OF bit to be set:



The voltage present on V

CC or battery is insufficient to support oscillation.



The ST bit is set to 1.



External interference of the crystal



The first time power is applied (defaults to a 1 on power-up).

If the OF bit cannot be written to 0 four seconds after the initial power-up, the user should perform the kick-start of the oscillator as noted above. Kick-starting should only be performed when the OF bit is set.

For the M41T93, if the oscillator fail interrupt enable bit (OFIE) is set to a 1, the IRQ/FT/OUT pin will also be asserted (see

Section 3.13

and

Section 3.14

for additional conditions which

apply). The IRQ/FT/OUT output is de-asserted by resetting the OF bit to 0, NOT by reading the flags register. The OF bit will remain a 1 until written to 0. Reading the flags register has no effect on OF.

The oscillator must start and have run for at least 4 seconds before attempting to reset the

OF bit to 0.

The oscillator fail detect circuit functions during backup mode. If a triggering event occurs to disrupt the oscillator during a power-down condition, the OF bit will be set accordingly.

3.13 Oscillator fail interrupt enable

With the OFIE bit set, the OF bit will cause the IRQ/FT/OUT output to be asserted (see

Section 3.14.1

and

3.14.2

for additional conditions that apply). The IRQ/FT/OUT output is cleared by resetting the OF bit to 0 (NOT by reading the flags register). Clearing the OFIE bit will also cause the IRQ/FT/OUT output to de-assert, but if OFIE is subsequently set prior to clearing OF, the IRQ/FT/OUT output will assert immediately upon setting OFIE. Clearing the OF bit is necessary to prevent such an inadvertent interrupt.

If the alarm in backup enable bit, ABE, is set (along with OFIE), the oscillator fail detect will cause an interrupt in the IRQ/FT/OUT pin during backup mode. For additional information on this, refer to

Section 3.14.2

3.14 IRQ/FT/OUT pin, frequency test, interrupts and the OUT bit

Four interrupt sources, the frequency test function, and the discrete output bit OUT all share the IRQ/FT/OUT pin. Priority is built into the part such that some functions dominate others.

Additionally, the priority depends on configuration bits such as OUT and ABE, and on whether the part is operating on V

CC or is in the backup mode. This pin is an open drain output and requires an external pull-up resistor.

38/56 DocID12615 Rev 8

M41T93 Clock operation

Figure 19

shows the various signal sources and controlling bits for the IRQ/FT/OUT output pin.

Figure 19. IRQ/FT/OUT output pin circuit

TIMER reload

TI/TP

TIE

IRQ/OUT/FT

LOGIC

Write OF to 0 to clear

OFIE

OUT

ABE

A1IE

OFIE

TIE w-dog running

IRQ/OUT/FT

Read FLAGS register to clear

AF1

AI1E

WDF

Write watchdog register to clear

PRE

WDOG

AM03013v1

The timer, oscillator fail detect circuit, alarm 1, and watchdog are ORed together as the primary interrupt sources. The frequency test signal, FT, is used to enable a 512 Hz output on the IRQ/FT/OUT pin for calibrating the RTC. When not used as an interrupt or frequency test output, the pin can be used as a discrete logic output controlled by the OUT bit. The

ABE bit is used to enable interrupts during backup mode.

Operating on V

, all four interrupt sources are available. During backup, the timer and watchdog are disabled, and the only interrupt sources are alarm 1 and the oscillator fail detect circuit.

DocID12615 Rev 8 39/56

Clock operation M41T93

3.14.1 Active mode operation on V

On V

, the operation of the output circuit is as shown in

Table 11

OUT

(1)

0 x

(2)

Table 11. Priority for IRQ/FT/OUT pin when operating on V

A1IE

(3)

+ OFIE

+ TIE

(5)

(4)

+ watchdog

(6) running

Pin Comment

0 x 0

When OUT is 0 and FT is not enabled, OUT dominates and none of the interrupt sources have any effect.

1 x

512 Hz

When FT = 1 and OUT = 1 and no interrupts are enabled, the output will be the 512 Hz frequency test (FT) signal.

IRQ

When one or more interrupts are enabled, and OUT is a 1, the pin stays high until one of the interrupts is asserted.

When OUT is 1, FT is 0 and no interrupts are enabled, the pin is high.

1. OUT is bit 7 of register 08h (digital calibration).

2. FT is bit 6 of register 08h (digital calibration).

3. A1IE is bit 7 of register 0Ah (alarm 1, month).

4. OFIE is bit 7 of register 09h (watchdog).

5. TIE is bit 5 of register 11h (timer control).

6. The watchdog is controlled by register 09h (watchdog).

When OUT is 0 and FT is 0, the pin will be 0 regardless of whether any interrupts are enabled.

When FT is a 1, the 512 Hz signal will be output if OUT is 0 or if no interrupts are enabled.

The interrupt sources control the pin when OUT is 1 and one or more of the interrupts are enabled.

If OUT is 1, FT is 0 and no interrupts are enabled, then the pin will be 1.

40/56 DocID12615 Rev 8

M41T93 Clock operation

In backup mode, the operation of the output circuit is as shown in

Table 12

OUT

(1)

Table 12. Priority for IRQ/FT/OUT pin when operating in backup mode

ABE

(2)

A1IE

(3)

+ OFIE

(4)

Pin Comment

0 x

1 x

0 x

IRQ

When ABE is 0, the pin is 1 regardless of OUT or the interrupt sources.

When OUT is 1 and no interrupts are enabled, the pin is 1. (A1IE and OFIE are the only interrupts applicable in this mode).

When ABE is 1 and OUT is 0, OUT dominates and regardless of the interrupt sources.

When one or more interrupts are enabled, ABE is a 1, and OUT is a 1, the pin stays high until one of the interrupts is asserted.

1. OUT is bit 7 of register 08h (digital calibration).

2. ABE is bit 5 of register 0Ah (alarm 1, month).

3. A1IE is bit 7 of register 0Ah (alarm 1, month).

4. OFIE is bit 7 of register 09h (watchdog).

In backup mode, frequency test is disabled. Thus, the FT bit is a ‘don’t care’.

ABE enables interrupts in backup. If it is 0, the output pin is a 1 regardless of the other bits.

The pin is also a 1 when OUT is a 1 and no interrupts are enabled.

When OUT is 0 and ABE is a 1, the pin is 0 regardless of the interrupts.

Thus, in order to enable interrupts in backup mode, OUT must be a 1 and ABE must be a 1, and one or more of the interrupt enables must be a 1.

Simultaneous interrupts

Since more than one interrupt source can cause the IRQ/FT/OUT pin to go low, more than one interrupt may be pending when the microprocessor services the interrupt. Therefore, the application software should read the flags register (0Fh) to discern which condition or conditions are causing the pin to be asserted.

Also be aware that once a flag causes the pin to assert, other flags could subsequently also go true. Since the pin is already low due to the first, no additional output transition will occur.

That is why the software must check the flags register.

Example: If the watchdog is in use and the oscillator fail detect interrupt is enabled, and the watchdog times out, the IRQ/FT/OUT pin will go low. If, in the intervening time before the processor services the interrupt, something disturbs the oscillator, such as a drop of moisture landing on the crystal pins, the OF bit will also be set. Thus, when the software services the interrupt, it must service both sources: it must re-initialize the watchdog and clear the OF bit in order to de-assert the IRQ/FT/OUT pin. By reading the flags register, the software will know both flags were set and that both need service.

DocID12615 Rev 8 41/56

Clock operation M41T93

3.15 Initial power-on defaults

Upon initial application of power to the device, the register bits will initially power-on in the state indicated in

Table 13

and

Table 14

Condition

(1)

Table 13. Initial power-on default values (part 1)

ST CB1 CB0 OUT FT

DCS

ACS

Digital calib.

Analog calib.

OFIE Watchdog

(2)

Initial power-up

Subsequent power-up

(3)(4)

1. All other control bits power-up in an undetermined state

2. BMB0-BMB4, RB0, RB1

3. With battery backup

4. UC = Unchanged

A1IE SQWE ABE

Condition

(1)

Initial power-up

Subsequent power-up

(2)(3)

RPT11-15 HT OF TE TI/TP TIE TD1 TD0 RS0 RS1-3 OTP RPT21-25 AL2E

Table 14. Initial power-up default values (part 2)

1. All other control bits power-up in an undetermined state

2. With battery backup

3. UC = Unchanged

3.16 OTP bit operation (SOX18 package only)

Using the factory-supplied analog calibration value

When the OTP (one time programmable) bit is set to a 1, the factory calibration value in the internal OTP register will be transferred to the analog calibration register (12h) and is “read only.” The OTP value is programmed by the manufacturer, and will contain the value necessary to achieve typically ±5 ppm

(a)

only) at room temperature after two SMT reflows. This clock accuracy can be guaranteed to drift no more than ±3 ppm the first year, and ±1 ppm for each following year due to crystal aging.

If the OTP bit is set to 0, the analog calibration register will become a WRITE/READ register and function like an ordinary register, allowing the user to implement any desired value of analog calibration.

When the user sets the OTP bit, they need to wait for approximately 8 ms before the analog registers transfer the value from the OTP to the analog registers due to the OTP read operation.

42/56 a. Max. value = +12 ppm / –5 pmm based on limited data

DocID12615 Rev 8

M41T93 Maximum ratings

Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 15. Absolute maximum ratings

Parameter Value

(1)

STG

SLD

(2)

Storage temperature (V

Supply voltage

Power dissipation

off, oscillator off)

Lead solder temperature for 10 seconds

Input or output voltages

Output current

–55 to 125

–0.3 to 7.0

260

–0.2 to Vcc+0.3

35.7



Thermal resistance, junction to ambient

QFN16

SOX18

1. Data based on characterization results, not tested in production.

2. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds (according to

JEDEC J-STD-020D).

°C/W

Unit

°C

V mA

DocID12615 Rev 8 43/56

DC and AC parameters

5 DC and AC parameters

Note:

M41T93

This section summarizes the operating and measurement conditions, as well as the DC and

AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.

Table 16. Operating and AC measurement conditions

Parameter

Supply voltage (V

)

Ambient operating temperature (T

)

Load capacitance (C

, typical)

Input rise and fall times

Input pulse voltages

Input and output timing ref. voltages

M41T93

2.38 V to 5.5 V

–40 to +85 °C

30 pF

 50 ns

0.2V

to 0.8V

0.3V

to 0.7V

Output Hi-Z is defined as the point where data is no longer driven.

Figure 20. Measurement AC I/O waveform

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol

Table 17. Capacitance

Parameter

(1)(2)

Min Max

OUT

(3)

Input capacitance

Output capacitance -

1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested

2. At 25 °C, f = 1 MHz

3. Outputs deselected

Unit

pF pF

AI02568

44/56 DocID12615 Rev 8

M41T93 DC and AC parameters

Sym

CC1

CC2

BAT

Parameter

Operating voltage (S)

Operating voltage (R)

Operating voltage (Z)

Input leakage current

Output leakage current

Supply current

SCL = 0.1V

/0.9V

SDO = open

Supply current (standby)

Table 18. DC characteristics

Test condition

(1)

–40 to 85 °C

0 V

 V

0 V

 V

OUT

 V

CC f

SCL

= 2 MHz f

SCL

= 5 MHz f

SCL

= 10 MHz

E = V

;

All inputs

 V

– 0.2 V;

 V

+ 0.2 V

5.5 V

3.0 V

Input low voltage

Input high voltage

Output low voltage

RST

BAT

= 3.0 V,

= 1.0 mA

SQW, IRQ/FT/OUT

SDO

= 3.0 V,

= 1.0 mA

= 3.0 V,

= 3.0 mA

= 3.0 V, I

= –1.0 mA (push-pull) Output high voltage

Pull-up supply voltage

(open drain)

Backup supply voltage

IRQ/FT/OUT

Battery supply current

25 °C; V

= 0 V; OSC on; V

32 KHz off

BAT

= 3 V;

Min

3.00

2.70

2.38

–0.3

0.7V

2.4

1.8

Typ

6.5

365

1. Valid for ambient operating temperature: T

= –40 to 85 °C; V

= 2.38 V to 5.5 V (except where noted)

Max

5.50

±1

0.5

1.0

2.0

0.3V

+0.3

0.4

Unit

μA

μA mA mA

V mA

μA

0.4

5.5

450

V nA

DocID12615 Rev 8 45/56

DC and AC parameters M41T93

Figure 21. I

CC2

vs. temperature

10.000

9.000

8.000

7.000

6.000

5.000

4.000

(3.0V)

(5.0V)

3.000

2.000

-40 -20 0 20

Temperature (°C)

40 60 80

Symbol

Table 19. Crystal electrical characteristics

Parameter

(1)(2)

Min Typ Max Units

Resonant frequency

Series resistance

Load capacitance -

32.768

12.5

(3) kHz k

 pF

1. Externally supplied if using the QFN16 package. STMicroelectronics recommends the Citizen CFS-145

(1.5 x 5 mm) and the KDS DT-38 (3 x 8 mm) for thru-hole, or the KDS DMX-26S (3.2 x 8 mm) or Micro

Crystal MS3V-T1R (1.5 x 5 mm) for surface-mount, tuning fork-type quartz crystals.

2. Load capacitors are integrated within the M41T93. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.

3. Guaranteed by design.

Symbol

Table 20. Oscillator characteristics

Parameter

(1)(2)

Conditions Min

STA t

STA

XI,

(1)

Oscillator start voltage

Oscillator start time

Capacitor input, capacitor output

IC-to-IC frequency variation

(2)(3)

1. With default analog calibration value ( = 0)

2. Reference value

3. T

= 25 °C, V

= 5.0 V

4 s

= V

2.0

–10

Typ

25 ai 13909

Max Units

+10

V s pF ppm

46/56 DocID12615 Rev 8

M41T93 DC and AC parameters

Figure 22. Power down/up mode AC waveforms

VCC

VSO

SCL

SDI tPD

DON'T CARE trec

AI11839

Sym

Table 21. Power down/up trip points DC characteristics

Parameter

(1)(2)

Min Typ Max Unit

RST

Reset threshold voltage

2.85

2.55

2.93

2.63

3.0

2.7

Battery backup switchover

Z 2.25

RST

2.32

2.38

Hysteresis t rec

Reset pulse width (V

rising)

to reset delay, V

RST

– 100 mV; for V

= (V

RST

+ 100 mV), falling to

slew rate of 10 mV/μs

140

2.5

280

1. All voltages referenced to V

2. Valid for ambient operating temperature: T

= –40 to 85 °C; V

= 2.38 to 5.5 V (except where noted)

V mV ms

μs

DocID12615 Rev 8 47/56

DC and AC parameters

Figure 23. Input timing requirements

SCL tCHEL tDVCH

SDI tCHDX

MSB IN

HIGH IMPEDANCE

SDO tELCH tCHEH tDLDH tDHDL tCLCH

LSB IN tEHEL tEHCH tCHCL

Figure 24. Output timing requirements

SCL tCH

SDO tCLQV tCLQX

MSB OUT tCL

LSB OUT tQLQH tQHQL

SDI

ADDR. LSB IN

M41T93

AI12295 tEHQZ

AI04634

48/56 DocID12615 Rev 8

M41T93 DC and AC parameters

Sym

Table 22. AC characteristics

< 2.7 V

Parameter

(1)

Min Max

 2.7 V

Units

Min Max

SCL t

ELCH t

EHCH t

EHEL t

CHEH t

CHEL t

(2) t

CLCH

(3) t

CHCL

(3) t

DVCH t

CHDX t

EHQZ

(3) t

CLQV t

CLQX t

QLQH

(3) t

QHQL

(3)

SCL clock frequency

E active setup time

E not active setup time

E deselect time

E active hold time

E not active hold time

Clock high time

Clock low time

Clock rise time

Clock fall time

Data in setup time

Data in hold time

Output disable time

Clock low to output valid

Output hold time

Output rise time

Output fall time

D.C.

100

D.C.

1. Valid for ambient operating temperature: T

= –40 to 85 °C; V

= 2.38 to 5.5 V (except where noted)

2. t

and t

must never be lower than the shortest possible clock period, 1/f

C(max)

3. Value guaranteed by characterization, not 100% tested in production

MHz ns ns ns ns ns ns ns

μs

μs ns ns ns ns ns ns ns

DocID12615 Rev 8 49/56

Package mechanical data

6 Package mechanical data

M41T93

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at:

www.st.com

ECOPACK

is an ST trademark.

50/56 DocID12615 Rev 8

M41T93 Package mechanical data

Figure 25. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size, outline

A3 ddd C

L b

A e

(2)

QFN16-A2

1. Drawing is not to scale

2. Substrate pad should be tied to V

Table 23. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body, mech. data mm inches

Sym

Typ Min Max Typ Min Max

E2 e

L ddd

N b

–

0.65

0.20

0.40

–

0.90

0.02

0.20

0.30

4.00

–

4.00

2.50

–

0.30

0.08

0.33

0.80

0.00

–

0.25

3.90

2.50

3.90

2.80

–

0.50

–

1.00

0.05

–

0.35

4.10

2.80

4.10

0.067

0.020

0.008

0.016

–

0.035

0.001

0.008

0.010

0.118

0.067

0.118

0.061

–

0.012

0.003

0.013

0.032

0.000

–

0.007

0.114

0.061

0.114

0.071

–

0.020

–

0.039

0.002

–

0.012

0.122

0.071

0.122

DocID12615 Rev 8 51/56

Package mechanical data M41T93

Figure 26. QFN16 – 16-lead, quad, flat, no lead, 4 x 4 mm, recommended footprint

2.70

0.70

0.20

(2)

4.50

2.70

Note:

0.325

0.35

0.65

1. Dimensions shown are in millimeters (mm)

2. Substrate pad should be tied to V

Figure 27. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data

3.2

6.0 ± 0.2

VSOJ20

AI11815

1.5

SMT

CRYSTAL

3.9

ST QFN16

3.9

Dimensions shown are in millimeters (mm).

7.0 ± 0.3

AI11816

52/56 DocID12615 Rev 8

M41T93 Package mechanical data

Figure 28. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal

9 1 h x 45

E H

Note:

10 18

A2 A ddd

B e



SO-J

Drawing is not to scale.

Table 24. SOX18 – 18-lead plastic SO, 300 mils, embedded crystal, pkg. mech. data mm inches

Sym

Typ Min Max Typ Min Max

D ddd



E e

–

11.61

–

1.27

–

7.57

–

10.16

0.51

0°

2.44

0.15

2.29

0.41

0.20

11.56

–

2.69

0.31

2.39

0.51

0.31

11.66

0.10

7.67

–

10.52

0.81

8°

–

0.457

–

0.050

–

0.298

–

0.400

0.020

0°

0.096

0.006

0.090

0.016

0.008

0.455

–

0.106

0.012

0.094

0.020

0.012

0.459

0.004

0.302

–

0.414

0.032

8°

DocID12615 Rev 8 53/56

Part numbering M41T93

Example:

Device family

M41T

Device type

Table 25. Ordering information

Operating voltage

S = V

= 3.00 to 5.5 V

R = V

= 2.70 to 5.5 V

Z = V

= 2.38 to 5.5 V

Package

QA = QFN16 (4 mm x 4 mm)

(1)

= SOX18

Temperature range

6 = –40 °C to +85 °C

Shipping method

F = ECOPACK

package, tape & reel

M41T 93 S QA 6 F

1. The SOX18 package includes an embedded 32,768 Hz crystal.

For other options, or for more information on any aspect of this device, please contact the

ST sales office nearest you.

54/56 DocID12615 Rev 8

M41T93 Revision history

Date

12-Oct-2011

04-Sep-2013

11-Nov-2013

Revision

Table 26. Document revision history

Changes

Updated

Features

, title,

Section 3.1: Clock data coherency

Section 3.2: Halt bit (HT) operation

; added

Figure 9

, added footnote

Table 25: Ordering information

Updated

Features

bullet concerning accuracy

Updated

Updated

2.2

Updated

Section 3

3.3

3.4.1

3.4.2

Updated

Updated

Textual update in

Removed figure entitled “Alarm interrupt reset waveform”

Updated

Section 3.7

3.8

3.8.1

Table 7

and

Added

Figure 16

Removed section concerning TI/TP bit

Updated

Section 3.8.2

and

3.8.3

Removed table entitled “Timer countdown value register bits (addr 11h)”

Updated

Section 3.10

3.11

Added

Figure 18

Removed table entitled “Century bits examples”

Removed section concerning output driver pin

Updated

3.13

Updated

Updated

Updated test condition for V

Table 18

Removed section concerning crystal component suppliers

Updated

Table 25

Minor textual updates throughout document

Updated

Section 3.10: Battery low warning

and added

Figure 17

; updated

Section 3.4.2: Analog calibration (programmable load capacitance)

and added

Section 3.4.3: Pre-programmed calibration value

; updated

Section 3.16: OTP bit operation (SOX18 package only)

; updated

Table 15

DocID12615 Rev 8 55/56

M41T93

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All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

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OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

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56/56 DocID12615 Rev 8

Reklama

Serial SPI bus real-time clock (RTC) with battery switchover

-

Features

±

Contents

List of tables

List of figures

1.1

SPI signal description

2 Operation

2.1

SPI bus characteristics

2.2

READ and WRITE cycles

2.3

Data retention and battery switchover (V

SO

= V

RST

)

2.4

Power-on reset (t rec

)

3.1

Clock data coherency

3.2

Halt bit (HT) operation

3.3

Real-time clock accuracy

3.5

Setting the alarm clock registers

3.6

Optional second programmable alarm

Watchdog interrupt

3.8 8-bit (countdown) timer

Normal interrupt mode

Free-running mode

3.9

Square wave output

3.10 Battery low warning

Midnight rollover check

Power-up battery check

Forcing a battery check

Leap year

3.12 Oscillator fail detection

3.13 Oscillator fail interrupt enable

3.14 IRQ/FT/OUT pin, frequency test, interrupts and the OUT bit

Simultaneous interrupts

3.15 Initial power-on defaults

3.16 OTP bit operation (SOX18 package only)

Using the factory-supplied analog calibration value

5 DC and AC parameters

6 Package mechanical data

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