STMicroelectronics M41T94 Datasheet
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M41T94
Serial real-time clock with 44 bytes NVRAM and reset
16
1
SO16 (MQ)
SNAPHAT
®
(SH) battery & crystal
28
1
SOH28 (MH)
Datasheet
-
production data
Choice of power-fail deselect voltages
(V
CC
= 2.7 to 5.5 V):
– THS = V
SS
; 2.55 V V
PFD
2.70 V
– THS = V
CC
; 4.20 V V
PFD
4.50 V
Packaging includes a 28-lead SOIC and
SNAPHAT ® top (to be ordered separately) or
16-lead SOIC
28-lead SOIC package provides direct connection for a SNAPHAT ® top which contains the battery and crystal
RoHS compliant
– Lead-free second level interconnect
Features
Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century
32 KHz crystal oscillator integrating load capacitance (12.5 pF) providing exceptional oscillator stability and high crystal series resistance operation
Serial peripheral interface (2 MHz SPI)
Ultralow battery supply current of 500 nA (max)
2.7 to 5.5 V operating voltage
2.5 to 5.5 V oscillator operating voltage
Battery low flag
Automatic switchover and deselect circuitry
44 bytes of general purpose RAM
Programmable alarm and interrupt function
(valid even during battery backup mode)
Accurate programmable watchdog timer (from
62.5 ms to 128 s)
Microprocessor power-on reset
December 2014
This is information on a product in full production.
DocID007564 Rev 7 1/39 www.st.com
2/39
Contents
Contents
M41T94
Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DocID007564 Rev 7
M41T94
Contents
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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39
List of tables
List of tables
M41T94
definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SOH28 – 28-lead plastic small outline, battery SNAPHAT
, package mechanical data . . 33
housing for 48 mAh battery & crystal, package mechanical data . 34
housing for 120 mAh battery & crystal, package mech. data . . . . 35
battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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M41T94
List of figures
List of figures
RSTIN1 and RSTIN2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SOH28 – 28-lead plastic small outline, battery SNAPHAT
, package outline . . . . . . . . . . 33
housing for 48 mAh battery & crystal, package outline. . . . . . . . . 34
housing for 120 mAh battery & crystal, package outline. . . . . . . . 35
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Description
1 Description
M41T94
The M41T94 is a serial real-time clock with 44 bytes of NVRAM and a RESET output. A built-in 32,768 Hz oscillator (external crystal controlled) and 8 bytes of the SRAM (see
Table 4 on page 18 ) are used for the clock/calendar function and are configured in binary
coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/control of alarm, watchdog and square wave functions. Addresses and data are transferred serially via a serial SPI interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The
M41T94 has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button-cell supply when a power failure occurs. Functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupts, watchdog timer and programmable square wave output.
Other features include a power-on reset as well as two additional debounced inputs
(RSTIN1 and RSTIN2) which can also generate an output reset (RST). The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The ninth clock address location controls user access to the clock information and also stores the clock software calibration setting.
The M41T94 is supplied in either a 16-lead plastic SOIC (requiring user supplied crystal and battery) or a 28-lead SOIC SNAPHAT ® package (which integrates both crystal and battery in a single SNAPHAT top). The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4TXX-BR12SH” (see
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
6/39 DocID007564 Rev 7
M41T94
Figure 1. Logic diagram
VCC VBAT
(1)
XI
(1)
XO
(1)
SCL
SDI
E
RSTIN1
RSTIN2
WDI
THS
M41T94
RST
IRQ/FT/OUT
SQW
SDO
VSS
AI03683
1. For SO16 package only.
Figure 2. 16-pin SOIC connections
XI
XO
RST
WDI
RSTIN1
RSTIN2
VBAT
VSS
5
6
3
4
7
8
1
2
M41T94
16
15
14
13
12
11
10
9
AI03684
VCC
E
IRQ/FT/OUT
THS
SDI
SQW
SCL
SDO
Description
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39
Description
E
IRQ/FT/OUT
RST
RSTIN1
RSTIN2
SCL
SDI
SDO
SQW
THS
WDI
XI
(1)
XO
(1)
V
BAT
(1)
V
CC
V
SS
1. For SO16 package only.
Table 1. Signal names
Chip enable
Interrupt/frequency test/out output (open drain)
Reset output (open drain)
Reset 1 input
Reset 2 input
Serial clock input
Serial data input
Serial data output
Square wave output
Threshold select pin
Watchdog input
Oscillator input
Oscillator output
Battery supply voltage
Supply voltage
Ground
Figure 3. 28-pin SOIC connections
SQW
NC
NC
NC
NC
NC
NC
WDI
RSTIN1
RSTIN2
NC
NC
NC
VSS
6
7
8
4
5
9
10
1
2
3
11
12
13
14
M41T94
25
24
23
22
21
20
19
18
17
16
15
28
27
26
AI03685
VCC
E
IRQ/FT/OUT
NC
NC
THS
NC
NC
SCL
NC
RST
SDI
SDO
NC
M41T94
8/39 DocID007564 Rev 7
M41T94
E
SDO
SDI
SCL
Crystal
WDI
VCC
VBAT
SPI
INTERFACE
32KHz
OSCILLATOR
Figure 4. Block diagram
REAL TIME CLOCK
CALENDAR
44 BYTES
USER RAM
RTC w/ALARM
& CALIBRATION
AF
WDF
WATCHDOG
SQUARE WAVE
VBL= 2.5V
COMPARE
VSO = 2.5V
COMPARE
VPFD = 4.4V
COMPARE
(2.65V if THS = V
SS
)
POR
BL
RSTIN1
RSTIN2
1. Open drain output
Figure 5. Hardware hookup
SPI Interface with
(CPOL, CPHA)(1) =
('0','0') or ('1','1')
D
Q
C
Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
C Q D
M41T94
E
C Q D
XXXXX
E
C Q D
XXXXX
E
Description
IRQ/FT/OUT
(1)
SQW
RST
(1)
AI04785
1. CPOL (clock polarity) and CPHA (clock phase) are bits that may be set in the SPI control register of the MCU.
AI03686
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Description
Mode
Disable reset
WRITE
E
H
L
Table 2. Function table
SCL
Input disabled
SDI
Input disabled
Data bit latch
AI04630
READ L X
AI04631
1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 6. Data and clock timing
CPOL CPHA
0 0 C
1 1 C
SDI
SDO
MSB
MSB
LSB
LSB
M41T94
SDO
High Z
High Z
Next data bit shift
(1)
AI04632
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M41T94 Signal description
2.1
2.2
2.3
2.4
Serial data output (SDO)
The output pin is used to transfer data serially out of the memory. Data is shifted out on the falling edge of the serial clock.
Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock.
Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 7 on page 13
and Figure 8 on page 14 ). The W/R bit, addresses, or data are latched, from the input pin,
on the rising edge of the clock input. The output data on the SDO pin changes state after the falling edge of the clock input.
The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock
SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see
Table 2 on page 10 and Figure 6 on page 10 ).
Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high impedance state. After power-on, a high-to-low transition on E is required prior to the start of any operation.
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Operation
3 Operation
M41T94
The M41T94 clock operates as a slave device on the SPI serial bus. Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL,
SDI and SDO (see Table 1 on page 8 and
Figure 5 on page 9 ). The device is selected when
the chip enable input (E) is held low. All instructions, addresses and data are shifted serially in and out of the chip. The most significant bit is presented first, with the data input (SDI) sampled on the first rising edge of the clock (SCL) after the chip enable (E) goes low. The 64 bytes contained in the device can then be accessed sequentially in the following order:
1 st
byte: tenths/hundredths of a second register
2 nd byte: seconds register
3 rd
byte: minutes register
4 th byte: century/hours register
5 th
byte: day register
6 th byte: date register
7 th
byte: month register
8 th byte: year register
9 th
byte: control register
10 th byte: watchdog register
11 th
- 16 th
bytes: Alarm registers
17 th - 19 th bytes: reserved
20 th
byte: square wave register
21 st - 64 th bytes: user RAM
The M41T94 clock continually monitors V
CC fall below V
PFD
for an out-of tolerance condition. Should V
CC counter. Inputs to the device will not be recognized at this time to prevent erroneous data
, the device terminates an access in progress and resets the device address from being written to the device from a an out-of-tolerance system. When V
CC
V
SO rises above V
SO
V
CC
.
falls below
, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. As system power returns and V
CC
, the battery is disconnected, and the power supply is switched to external
Write protection continues until V
CC
reaches V
PFD
(min) plus t
REC
(min). For more information on battery storage life refer to application note AN1012.
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M41T94
3.1
Operation
SPI bus characteristics
The serial peripheral interface (SPI) bus is intended for synchronous communication between different ICs. It consists of four signal lines: serial data input (SDI), serial data output (SDO), serial clock (SCL) and a chip enable (E).
By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
The E input is used to initiate and terminate a data transfer. The SCL input is used to synchronize data transfer between the master (micro) and the slave (M41T94) devices.
The SCL input, which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus (see
The M41T94 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock
SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see
Table 2 on page 10 and Figure 6 on page 10 ).
There is one clock for each bit transferred. Address and data bits are transferred in groups of eight bits. Due to memory size the second most significant address bit is a Don’t Care
(address bit 6).
Figure 7. Input timing requirements tEHEL
E tELCH tCHEH tEHCH
SCL tDVCH tCHCL tCHDX tCLCH
SDI MSB IN LSB IN tDLDH tDHDL
HIGH IMPEDANCE
SDO
AI04633
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Operation M41T94
Figure 8. Output timing requirements
E
SCL tCH tCLQV tCLQX
MSB OUT tCL tEHQZ
SDO LSB OUT tQLQH tQHQL
SDI
ADDR. LSB IN
AI04634
Symbol
Table 3. AC characteristics
Parameter
(1)
Min t
CLQX t
DHDL
(3) t
DLDH
(3) t
DVCH t
EHCH t
EHEL t
EHQZ
(3) t
ELCH t
QHQL
(3) t
QLQH
(3) f
SCL t
CH
(2) t
CHCL
(3) t
CHDX t
CHEH t
CL
(2) t
CLCH
(3) t
CLQV
Serial clock input frequency
Clock high
Clock transition (fall time)
Serial clock input high to input data transition
Serial clock input high to chip enable high
Clock low
Clock transition (rise time)
Serial clock input low to output valid
Serial clock input low to output data transition
Input data transition (fall time)
Input data transition (rise time)
Input data to serial clock input high
Chip enable high to serial clock input high
Chip enable high to chip enable low
Chip enable high to output high-z
Chip enable low to serial clock input high
Output data transition (fall time)
Output data transition (rise time)
DC
200
50
200
200
0
40
200
200
200
1. Valid for ambient operating temperature: T
A
= –40 to 85°C; V
CC
= 2.7 to 5.5 V (except where noted).
2. t
CH
+ t
CL
1/f
SCL
3. Value guaranteed by design, not 100% tested in production.
Max
2
1
1
150
1
1
250
100
100
Unit ns ns ns ns ns
μ s
μ s ns ns ns ns ns
μ s ns
MHz ns
μ s ns
14/39 DocID007564 Rev 7
M41T94
3.2
Note:
Operation
Read and write cycles
Address and data are shifted MSB first into the serial data input (SDI) and out of the serial data output (SDO). Any data transfer considers the first bit to define whether a READ or
WRITE will occur. This is followed by seven bits defining the address to be read or written.
Data is transferred out of the SDO for a READ operation and into the SDI for a WRITE operation. The address is always the second through the eighth bit written after the Enable
(E) pin goes low. If the first bit is a '1,' one or more WRITE cycles will occur. If the first bit is a '0,' one or more READ cycles will occur (see Figure
Figure 9 on page 16 and Figure 10 on page 16
).
Data transfers can occur one byte at a time or in multiple byte burst mode, during which the address pointer will be automatically incremented. For a single byte transfer, one byte is read or written and then E is driven high. For a multiple byte transfer all that is required is that E continue to remain low. Under this condition, the address pointer will continue to increment as stated previously. Incrementing will continue until the device is deselected by taking E high. The address will wrap to 00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). Although the clock continues to maintain the correct time, this will prevent updates of time and date during either a READ or WRITE of these address locations by the user. The update will resume either due to a deselect condition or when the pointer increments to an non-clock or RAM address (08h to 3Fh).
This is true both in READ and WRITE mode.
3.3 Data retention mode
With valid V
CC
applied, the M41T94 can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M41T94 will automatically deselect, write protecting itself when V
CC
falls between V
PFD
(max) and V
PFD
(min) (see
). At this time, the reset pin (RST) is driven active and will remain active until V returns to nominal levels. When V switched from the V
CC
CC
falls below the switchover voltage (V
SO
CC
), power input is
pin to the SNAPHAT battery (or external battery for SO16) at this time, and the clock registers are maintained from the attached battery supply. All outputs become high impedance. On power-up, when V
CC protection continues for t
REC
returns to a nominal value, write
by internally inhibiting E. The RST signal also remains active during this time (see
Figure 17 on page 30 ). Before the next active cycle, chip enable should
be taken high for at least t
EHEL
, then low.
For a further more detailed review of battery lifetime calculations, please see application note AN1012.
DocID007564 Rev 7 15/39
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Operation M41T94
Figure 9. Read mode sequence
E
0 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 22
SCL
W/R BIT 7 BIT ADDRESS
SDI
SDO
7
MSB
6 5 4 3 2 1 0
HIGH IMPEDANCE
DATA OUT
(BYTE 1)
DATA OUT
(BYTE 2)
7
MSB
6 5 4 3 2 1 0 7
MSB
6 5 4 3 2 1 0
AI04635
Figure 10. Write mode sequence
E
0 1 2 3 4 5 6 7 8 9 10 15
SCL
W/R BIT
SDI
SDO
7 BIT ADDR DATA BYTE
7
MSB
6 5 4 3 2 1 0 7
MSB
6 5 4 3 2 1 0 7
HIGH IMPEDANCE
AI04636
16/39 DocID007564 Rev 7
M41T94 Clock operations
The eight byte clock register (see
Table 4 on page 18 ) is used to both set the clock and to
read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY ENABLE bit
(CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from
'0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and years. The ninth clock register is the control register (this is described in the clock calibration section).
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second.
The eight clock registers may be read one byte at a time, or in a sequential block. The control register (address location 08h) may be accessed independently. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
When a power failure occurs, the halt update bit (HT) will automatically be set to a '1.' This will prevent the clock from updating the clock registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a '0' will allow the clock to update the clock registers with the current time. For more information, see application note
AN1572.
The M41T94 offers 20 internal registers which contain clock, alarm, watchdog, flag, square wave and control data (see
). These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT ™ cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy.
The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address.
The system-to-user transfer of clock data will be halted whenever the clock addresses (00h to 07h) are being written. The update will resume either due to a deselect condition or when the pointer increments to a non-clock or RAM address.
Clock and alarm registers store data in BCD. Control, watchdog and square wave registers store data in binary format.
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Clock operations M41T94
Table 4. Clock register map (1)
Addr
00h
D7 D6 D5
0.1 seconds
D4
01h
02h
ST
0
03h CEB CB
10 seconds
10 minutes
10 Hours
D3 D2 D1
0.01 seconds
Seconds
Minutes
D0
Hours (24 hour format)
04h
05h
06h
07h
TR
0
0
0
0
0
0
10 date
0
0
10 Years
10M
0 Day of week
Date: day of month
Month
Year
08h OUT FT S Calibration
09h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0
0Ah AFE SQWE ABE Al 10M
0Bh RPT4 RPT5 AI 10 date
0Ch RPT3 HT
0Dh RPT2
0Eh RPT1
AI 10 hour
Alarm 10 minutes
Alarm 10 seconds
0Fh WDF AF
10h 0 0
0
0
BL
0
11h
12h
13h
0
0
0
0
0
0
RS3 RS2 RS1
0
0
RS0
0
0
0
0
0
Alarm month
Alarm date
Alarm hour
Alarm minutes
Alarm seconds
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1. Keys:
S = Sign bit
FT = Frequency test bit
ST = Stop bit
0 = Must be set to zero
BL = Battery low flag (read only)
BMB0-BMB4 = Watchdog multiplier bits
CEB = Century enable bit
CB = Century bit
OUT = Output level
AFE = Alarm flag enable flag
RB0-RB1 = Watchdog resolution bits
WDS = Watchdog steering bit
ABE = Alarm in battery back-up mode enable bit
RPT1-RPT5 = Alarm repeat mode bits
WDF = Watchdog flag (read only)
WDF = Watchdog flag (read only)
AF = Alarm flag (read only)
SQWE = Square wave enable
RS0-RS3 = SQW frequency
HT = Halt update bit
TR = t
REC
bit
Function/range
BCD format
Seconds 00-99
Seconds
Minutes
00-59
00-59
Century/hours 0-1/00-23
Day
Date
Month
Year
Control
Watchdog
Al month
Al date
Al hour
Al min
Al sec
Flags
Reserved
Reserved
Reserved
SQW
01-7
01-31
01-12
00-99
01-12
01-31
00-23
00-59
00-59
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M41T94
4.3
Note:
Clock operations
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the
M41T94 is in the battery backup to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 5 on page 19 shows
the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting.
When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set, the alarm condition activates the IRQ/FT/OUT pin.
I f the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the “Alarm Seconds,” the address pointer will increment to the flag address, causing this situation to occur.
To disable the alarm, write '0' to the alarm date register and to RPT1–5. The IRQ/FT/OUT output is cleared by a READ to the flags register. This READ of the flags register will also reset the alarm flag (D6; register 0Fh). See
The IRQ/FT/OUT pin can also be activated in the battery backup mode. The IRQ/FT/OUT will go low if an alarm occurs and both ABE (alarm in battery backup mode enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the flag register at system boot-up to determine if an alarm was generated while the M41T94 was in the deselect mode during power-up.
illustrates the backup mode alarm timing.
RPT5
1
1
0
1
1
1
RPT4
1
0
0
1
1
1
Table 5. Alarm repeat mode
RPT3 RPT2 RPT1
0
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
Alarm setting
Once per second
Once per minute
Once per hour
Once per day
Once per month
Once per year
0Eh
Figure 11. Alarm interrupt reset waveforms
0Fh 10h
ACTIVE FLAG
IRQ/FT/OUT HIGH-Z
AI03664
DocID007564 Rev 7 19/39
39
Clock operations
Figure 12. Backup mode alarm waveforms
VCC
VPFD
VSO
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register tREC
IRQ/FT/OUT
HIGH-Z HIGH-Z
AI03920
M41T94
20/39 DocID007564 Rev 7
M41T94 Clock operations
Note:
4.5
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog register, address 09h. bits BMB4-BMB0 store a binary multiplier and the two lower order bits
RB1-RB0 select the resolution, where 00 =
1
/
16
second, 01 =
1
/
4
second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
Watchdog register = 3*1 or 3 seconds).
Accuracy of timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M41T94 sets the
WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by reading the flags register (0Fh).
The most significant bit of the watchdog register is the watchdog steering bit (WDS). When set to a '0,' the watchdog will activate the IRQ/FT/OUT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for t
REC
. The watchdog register and the AFE, ABE, SQWE, and FT bits will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.'
The watchdog timer can be reset by two methods:
1.
a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI), or
2. the microprocessor can perform a WRITE of the watchdog register.
The time-out period then starts over. The WDI pin should be tied to V
SS
if not used. In order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effectively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT/OUT pin. This will also disable the watchdog function until it is again programmed correctly. A
READ of the flags register will reset the watchdog flag (bit D7; register 0Fh).
The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. If the watchdog function is set to output to the IRQ/FT/OUT pin and the frequency test (FT) function is activated, the watchdog function prevails and the frequency test function is denied.
Square wave output
The M41T94 offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table
. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah.
DocID007564 Rev 7 21/39
39
Clock operations
RS3
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
M41T94
Square wave bits
RS2
1
1
0
1
1
0
0
1
0
1
1
0
1
0
0
0
Table 6. Square wave output frequency
RS1
0
1
1
0
1
0
1
1
0
0
1
1
0
0
0
1
RS0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
Square wave
Frequency
4
2
16
8
1
256
128
64
32
None
32.768
8.192
4.096
2.048
1.024
512
Units
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
– kHz kHz kHz kHz kHz
Hz
4.7
The M41T94 continuously monitors V
CC
V
PFD be chosen to control rise time.
. When V
CC
falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for t
REC
after V
CC
passes
(max). The RST pin is an open drain output and an appropriate pull-up resistor should
Reset inputs (RSTIN1 & RSTIN2)
The M41T94 provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a reset generated by a power cycle.
Table 7 on page 23 and Figure 13 on page 23 illustrate the AC reset characteristics of this
function. Pulses shorter than t
RLRH1
and t
RLRH2 and RSTIN2 are each internally pulled up to V
will not generate a reset condition. RSTIN1
CC
through a 100 k resistor.
22/39 DocID007564 Rev 7
M41T94 Clock operations
Figure 13. RSTIN1 and RSTIN2 timing waveforms
RSTIN1 tRLRH1
RSTIN2 tRLRH2
RST
(1) tR1HRH tR2HRH
AI03665
Table 7. Reset AC characteristics (1)
Symbol t
RLRH1
(2) t
RLRH2
(3) t
R1HRH
(4) t
R2HRH
(4)
Parameter
RSTIN1 low to RSTIN1 high
RSTIN2 low to RSTIN2 high
RSTIN1 high to RST high
RSTIN2 high to RST high
Min
200
100
40
40
Max
200
200
1. Valid for ambient operating temperature: T
A
= –40 to 85°C; V
CC
= 2.7 to 5.5 V (except where noted).
2. Pulse width less than 50 ns will result in no RESET (for noise immunity).
3. Pulse width less than 20 ms will result in no RESET (for noise immunity).
4. Programmable (see Table on page 26 ).
Unit ns ms ms ms
4.8 Calibrating the clock
The M41T94 is driven by a quartz-controlled oscillator with a nominal frequency of
32,768 Hz. Uncalibrated clock accuracy will not exceed ±35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. When the
Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 14 on page 24
).
Therefore, the M41T94 design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as
shown in Figure 15 on page 25 . The number of times pulses are blanked (subtracted,
negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the control register (8h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
DocID007564 Rev 7 23/39
39
Clock operations
Note:
M41T94 adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T94 may require.
The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in application note AN934: TIMEKEEPER ® calibration. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of 1h) is '0,' the frequency test bit (FT, D6 of 8h) is '1,' the alarm flag enable bit (AFE, D7 of Ah) is '0,' and the watchdog steering bit (WDS, D7 of 9h) is '1' or the watchdog register (9h = 0) is reset.
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte for correction.
Setting or changing the calibration byte does not affect the frequency test output frequency.
The IRQ/FT/OUT pin is an open drain output which requires a pull-up resistor for proper operation. A 500 to 10 k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down.
Figure 14. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
–40 –30 –20 –10 0
Δ F = K x (T –T
F
T
O
O
= 25
°
C ± 5
°
C
) 2
K = –0.036 ppm/
°
C
2
± 0.006 ppm/
°
C
2
10 20 30
Temperature
°
C
40 50 60 70 80
AI00999b
24/39 DocID007564 Rev 7
M41T94 Clock operations
Figure 15. Calibration waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Bits D7 and D6 of clock register 03h contain the CENTURY ENABLE bit (CEB) and the
CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
4.10 Output driver pin
Note:
When the FT bit, AFE bit and watchdog register are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the control register. In other words, when
D7 (OUT bit) and D6 (FT bit) of address location 08h are a '0,' then the IRQ/FT/OUT pin will be driven low.
The IRQ/FT/OUT pin is an open drain which requires an external pull-up resistor.
4.11 Battery low warning
Note:
The M41T94 automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit
D4 of flags register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5 V. The BL bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.
Data should be considered suspect and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal V
CC
is supplied. In order to insure data integrity during subsequent periods of battery backup mode, the battery should be replaced. The SNAPHAT ® top may be replaced while V
CC
is applied to the device.
This will cause the clock to lose time during the interval the SNAPHAT disconnected.
® battery/crystal top is
DocID007564 Rev 7 25/39
39
Clock operations M41T94
The M41T94 only monitors the battery when a nominal V
CC
is applied to the device. Thus applications which require extensive durations in the battery backup mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
4.12 t
REC
bit
Bit D7 of clock register 04h contains the t
REC continuation of the deselect time after V
CC
bit (TR). t
REC
refers to the automatic
reaches V
PFD
. This allows for a voltage setting time before WRITEs may again be performed to the device after a power-down condition.
The t
REC
bit will allow the user to set the length of this deselect time as defined by Table 8 on page 26
.
4.13 Initial power-on defaults
Upon initial application of power to the device, the following register bits are set to a '0' state:
Watchdog register, TR, FT, AFE, ABE, and SQWE. The following bits are set to a '1' state:
ST, OUT, and HT (see
t
REC
bit (TR)
0
0
1
1. Default setting
Table 8. t
REC
definitions t
REC
time
STOP bit (ST)
Min
0
1
X
96
40
50
Max
98
200
(1)
2000
Units ms ms
μ s
Condition TR
Table 9. Default values
ST HT Out FT AFE ABE SQWE
WATCHDOG register
(1)
Initial power-up
(battery attach for
SNAPHAT
®
)
(2)
Subsequent power-up
(with battery backup)
(3)
0
UC
1. BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
1
UC
1
1
1
UC
0
0
0
0
0
0
0
0
0
0
26/39 DocID007564 Rev 7
M41T94 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Symbol
T
STG
Table 10. Absolute maximum ratings
Parameter
Storage temperature (V
CC
off, oscillator off)
SNAPHAT
®
SOIC
Value
–40 to 85
–55 to 125
Unit
°C
°C
V
CC
T
SLD
(1)
V
IO
I
O
P
D
Supply voltage
Lead solder temperature for 10 seconds
Input or output voltage
Output current
Power dissipation
–0.3 to 7
260
–0.3 to V
20
1
CC
+0.3
V
°C
V mA
W
1. For SO16 and SOH28 package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (the time above 255°C must not exceed 30 seconds).
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup mode.
Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT ® sockets.
DocID007564 Rev 7 27/39
39
DC and AC parameters
6 DC and AC parameters
M41T94
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 11. DC and AC measurement conditions (1)
Parameter M41T94
V
CC
supply voltage
Ambient operating temperature
Load capacitance (C
L
)
Input rise and fall times
Input pulse voltages
Input and output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
2.7 to 5.5 V
–40 to 85°C
100 pF
50 ns
0.2 to 0.8V
CC
0.3 to 0.7V
CC
Figure 16. AC testing input/output waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI02568
Symbol
Table 12. Capacitance
Parameter
(1)(2)
Min Max
C
IN
C
OUT
(3) t
LP
Input capacitance
Output capacitance
Low-pass filter input time constant (SDA and SCL)
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. At 25°C, f = 1 MHz.
3. Outputs are deselected.
7
10
50
Unit pF pF ns
28/39 DocID007564 Rev 7
M41T94 DC and AC parameters
Symb.
Parameter
Table 13. DC characteristics
Test condition
(1)
Min Typ Max Unit
I
BAT
Battery current OSC on
Battery current OSC off
T
A
= 25°C, V
V
BAT
CC
= 0 V,
= 3 V
400
50
500 nA nA
I
CC1
I
CC2
I
LI
(2)
I
LO
(3)
V
IH
V
IL
V
BAT
V
OH
V
OL
Supply current
Supply current (standby)
Input leakage current
Output leakage current
Input high voltage
Input low voltage
Battery voltage
Output high voltage
Output low voltage
(5)
(5)
Output low voltage (open drain)
(6)
Pull-up supply voltage (open drain) f = 2 MHz
SCL, SDI = V
CC
– 0.3 V
0 V V
IN
V
CC
0 V V
OUT
V
CC
I
OH
= –1.0 mA
I
OL
= 3.0 mA
I
OL
= 10 mA
RST, IRQ/FT/OUT
0.7V
CC
–0.3
2.5
2.4
V
CC
2
1.4
±1
±1 mA mA
μ
μ
A
A
+ 0.3
V
0.3V
0.4
0.4
5.5
CC
3.5
(4)
V
V
V
V
V
V
PFD
Power fail deselect (THS = V
CC
)
Power fail deselect (THS = V
SS
)
Battery backup switchover
4.20
2.55
4.40
2.60
4.50
2.70
V
SO
2.5
1. Valid for ambient operating temperature: T
A
= –40 to 85°C; V
CC
= 2.7 to 5.5 V (except where noted).
2. RSTIN1 and RSTIN2 internally pulled up to V
100 k resistor.
CC
through 100 k resistor. WDI internally pulled-down to V
SS
through
3. Outputs deselected.
4. For rechargeable back-up, V
BAT
(max) may be considered V
CC
.
5. For SQW pin (CMOS).
6. For IRQ/FT/OUT, RST pins (open drain): if pulled up to supply other than V
3.0 V when V
CC
= 0 V (during battery backup mode).
CC
, this supply must be equal to, or less than
V
V
Symbol
Table 14. Crystal electrical characteristics (externally supplied)
Parameter
(1)(2)
Typ Min Max Unit f
0
R
S
C
L
Resonant frequency
Series resistance
Load capacitance
32.768
12.5
50 kHz k pF
1. Load capacitors are integrated within the M41T94. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. These characteristics are externally supplied.
2. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:
1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations.
DocID007564 Rev 7 29/39
39
DC and AC parameters M41T94
Figure 17. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO tF tR tFB tDR
DON'T CARE tRB tREC
RECOGNIZED INPUTS RECOGNIZED
RST
OUTPUTS VALID
(PER CONTROL INPUT)
HIGH-Z
VALID
(PER CONTROL INPUT)
AI03687
Symbol t
F
(2) t
FB
(3) t
R t
RB t
REC
(4) t
DR
V
PFD
V
PFD
V
PFD
V
SS
to V
PFD
Table 15. Power down/up AC characteristics
(min) to V
SS
Parameter
(1)
(max) to V
PFD
(min) V
V
CC
(min) to V
PFD
CC
fall time
(max) V
CC
(min) V
CC
Power up deselect time
rise time
Expected data retention time
fall time
rise time
Min
300
10
10
1
40
10
(5)
Typ Max
200
Unit
μ
μ
μ
μ s s s ms
YEARS
1. Valid for ambient operating temperature: T
A
= –40 to 85°C; V
CC
= 2.7 to 5.5 V (except where noted).
2. V
PFD
(max) to V
PFD until 200 μ s after V
(min) fall time of less than t
F
CC
passes V
PFD
(min).
may result in deselection/write protection not occurring
3. V
PFD
(min) to V
SS
fall time of less than t
FB
may cause corruption of RAM data.
4. Programmable (see
5. At 25°C, V
CC
= 0 V (when using SOH28 + M4T28-BR12SH SNAPHAT
®
top).
s
30/39 DocID007564 Rev 7
M41T94
7 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
DocID007564 Rev 7 31/39
39
Package mechanical data
Figure 18. SO16 – 16-lead plastic small outline package outline
M41T94
Note:
0016020_G
Drawing is not to scale.
Table 16. SO16 – 16-lead plastic small outline package mechanical data millimeters inches
Symbol
Min Typ Max Min Typ Max c
D
E
E1
A
A1
A2 b
L k e h ccc
0.10
1.25
0.31
0.17
9.80
5.80
3.80
0.25
0.40
0°
9.90
6.00
3.90
1.27
1.75
0.25
0.51
0.25
10.00
6.20
4.00
0.50
1.27
8°
0.10
0.004
0.050
0.012
0.007
0.386
0.228
0.150
0.010
0.016
0°
0.390
0.236
0.154
0.050
0.004
0.069
0.010
0.020
0.010
0.394
0.244
0.157
0.020
0.050
8°
32/39 DocID007564 Rev 7
M41T94 Package mechanical data
Figure 19. SOH28 – 28-lead plastic small outline, battery SNAPHAT ® , package outline
Note:
1011859_I
Drawing is not to scale.
Table 17. SOH28 – 28-lead plastic small outline, battery SNAPHAT ® , package mechanical data millimeters inches
Symbol
Min Typ Max Min Typ Max
B1
C
D
E
A
A1
A2
B
L
X
H e
0.051
2.337
0.355
0.355
0.152
17.710
8.230
11.510
0.406
0°
1.270
3.048
0.355
2.692
0.508
0.610
0.317
18.490
8.890
12.700
1.270
8°
0.002
0.092
0.014
0.014
0.006
0.697
0.324
0.453
0.016
0°
0.050
0.120
0.014
0.106
0.020
0.024
0.013
0.728
0.350
0.500
0.050
8°
DocID007564 Rev 7 33/39
39
Package mechanical data M41T94
Figure 20. SH – 4-pin SNAPHAT ® housing for 48 mAh battery & crystal, package outline
Note:
1011860_J
Drawing is not to scale.
Table 18. SH – 4-pin SNAPHAT ® housing for 48 mAh battery & crystal, package mechanical data millimeters inches
Symbol
Min Typ Max Min Typ Max
A3
B
D
E
A
A1
A2 eA eB
L
T
7.239
6.477
0.000
0.457
21.082
14.224
15.545
3.200
2.032
6°
9.779
7.747
6.985
0.381
0.559
21.844
14.986
15.951
3.607
2.286
8°
0.285
0.255
0.000
0.018
0.830
0.560
0.612
0.126
0.080
6°
0.385
0.305
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
8°
34/39 DocID007564 Rev 7
M41T94 Package mechanical data
Figure 21. SH – 4-pin SNAPHAT ® housing for 120 mAh battery & crystal, package outline
Note:
7027195_H
Drawing is not to scale.
Table 19. SH – 4-pin SNAPHAT
®
housing for 120 mAh battery & crystal, package mech. data millimeters inches
Symbol
Min Typ Max Min Typ Max
B
D
E eA
A
A1
A2
A3 eB
L
T
8.001
7.239
0.000
0.457
21.082
17.272
15.545
3.200
2.032
6°
10.541
8.509
7.747
0.381
0.559
21.844
18.034
15.951
3.607
2.286
8°
0.315
0.285
0.000
0.018
0.830
0.680
0.612
0.126
0.080
6°
0.415
0.335
0.305
0.015
0.022
0.860
0.710
0.628
0.142
0.090
8°
DocID007564 Rev 7 35/39
39
Part numbering M41T94
Table 20. Ordering information scheme
Example:
Device type
M41T
Supply voltage and write protect voltage
94 = V
CC
= 2.7 to 5.5 V
THS = V
CC
; 4.20 V V
PFD
4.50 V
THS = V
SS
; 2.55 V V
PFD
2.70 V
Package
MQ = SO16
MH
(1)
= SOH28
Temperature range
6 = –40 to 85°C
M41T 94 MH 6 F
Shipping method
F = Lead-free package (ECOPACK
®
), tape & reel
1. The 28-pin SOIC package (SOH28) requires the SNAPHAT reel form (see
).
®
battery/crystal package which is ordered separately under the part number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in tape &
Caution: Do not place the SNAPHAT ® battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Part number
M4T28-BR12SH1
M4T32-BR12SHx
Table 21. SNAPHAT ® battery table
Description
Lithium battery (48 mAh) and crystal SNAPHAT
®
Lithium battery (120 mAh) and crystal SNAPHAT
®
Package
SH
SH
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M41T94
Figure 22. Recycling symbols
Environmental information
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
DocID007564 Rev 7 37/39
39
Revision history M41T94
Date
Apr-2002
25-Apr-2002
03-Jul-2002
06-Nov-2002
26-Mar-2003
28-Apr-2003
15-Jun-2004
29-Aug-2006
09-Nov-2007
13-Jan-2009
01-Dec-2014
Revision
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
Table 22. Document revision history
Changes
First edition
Adjust graphic (
Figure 4 on page 9 ); fix table text (
,
Table 20 on page 36 ); adjust characteristics (
Modify DC, Crystal Electrical Characteristics footnotes, Default Value table (
Table 13 on page 29 , Table 14 on page 29 ,
Correct dimensions (
)
Update test condition (
)
New Si changes ( Figure 4 on page 9 ;
,
Table 8 on page 26 , Table 9 on page 26 )
Reformatted; added Lead-free information; update characteristics
(
;
Changed document to new template; amalgamated diagrams in
Features on page 1 ; updated Package mechanical data in
Package mechanical data ; small text changes for entire document,
ECOPACK compliant
Added lead-free second level interconnect information to cover page and
Section 7: Package mechanical data ; minor formatting changes
throughout document; updated
,
Section 10: References
; updated text in
Section 7: Package mechanical data
; added
Section 9: Environmental information
.
Updated Section 7: Package mechanical data
(
,
Removed shipping option in tubes from Table 20
Updated Section 9: Environmental information
Removed Section 10: References
38/39 DocID007564 Rev 7
M41T94
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
DocID007564 Rev 7 39/39
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