STM32F469xx

STM32F469xx
ARM®Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/384+4KB RAM, USB OTG HS/FS,
Ethernet, FMC, dual Quad-SPI, Graphical accelerator, Camera IF, LCD-TFT & MIPI DSI
Datasheet - production data
Features
&"'!
• Core: ARM® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
• Memories
–
–
–
–
Up to 2 MB of Flash memory organized into two
banks allowing read-while-write
Up to 384+4 KB of SRAM including 64-KB of
CCM (core coupled memory) data RAM
Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR, SDRAM, Flash NOR/NAND
memories
Dual-flash mode Quad-SPI interface
• Graphics:
–
–
–
–
Chrom-ART Accelerator™ (DMA2D), graphical
hardware accelerator enabling enhanced
graphical user interface with minimum CPU load
LCD parallel interface, 8080/6800 modes
LCD TFT controller supporting up to XGA
resolution
MIPI® DSI host controller supporting up to 720p
30Hz resolution
LQFP176 (24 × 24 mm)
LQFP208 (28 x 28 mm)
–
–
•
1.7 V to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
4-to-26 MHz crystal oscillator
Internal 16 MHz factory-trimmed RC (1%
accuracy)
32 kHz oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Low power
–
–
Sleep, Stop and Standby modes
VBAT supply for RTC, 20×32 bit backup registers
+ optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
• Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 180 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. 2x watchdogs and
SysTick timer
October 2015
This is information on a product in full production.
WLCSP168
• Debug mode
–
–
SWD & JTAG interfaces
Cortex®-M4 Trace Macrocell™
• Up to 161 I/O ports with interrupt capability
–
–
Up to 157 fast I/Os up to 90 MHz
Up to 159 5 V-tolerant I/Os
• Up to 21 communication interfaces
–
–
–
–
–
–
Up to 3 × I2C interfaces (SMBus/PMBus)
Up to 4 USARTs and 4 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem control)
Up to 6 SPIs (45 Mbits/s), 2 with muxed fullduplex I2S for audio class accuracy via internal
audio PLL or external clock
1 x SAI (serial audio interface)
2 × CAN (2.0B Active)
SDIO interface
• Advanced connectivity
–
–
• Clock, reset and supply management
–
–
–
–
UFBGA169 (7 × 7 mm)
UFBGA176 (10 x 10 mm)
TFBGA216 (13 x 13 mm)
–
–
USB 2.0 full-speed device/host/OTG controller
with on-chip PHY
USB 2.0 high-speed/full-speed device/host/OTG
controller with dedicated DMA, on-chip fullspeed PHY and ULPI
Dedicated USB power rail enabling on-chip
PHYs operation throughout the entire MCU
power supply range
10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit parallel camera interface up to
54 Mbytes/s
• True random number generator
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
Table 1. Device summary
Reference
Part numbers
STM32F469xx
STM32F469AE, STM32F469AG, STM32F469AI
STM32F469BE, STM32F469BG, STM32F469BI
STM32F469IE, STM32F469IG, STM32F469II
STM32F469NE, STM32F469NG, STM32F469NI
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Contents
STM32F469xx
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1
2
1.1.1
LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1.2
LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1.3
UFBGA176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1.4
TFBGA216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1
ARM® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . 19
2.2
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19
2.3
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20
2.6
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7
Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9
Flexible Memory Controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.10
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.11
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.12
DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.13
Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.14
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25
2.15
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.16
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.17
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.18
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.19
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.20
2/208
Compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.19.1
Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.19.2
Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.20.1
Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.20.2
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Contents
2.20.3
3
Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 32
2.21
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 33
2.22
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.23
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.24
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.24.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.24.2
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.24.3
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.24.4
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.24.5
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.24.6
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.25
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.26
Universal synchronous/asynchronous receiver transmitters (USART) . . 37
2.27
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.28
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.29
Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.30
Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.31
Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.32
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40
2.33
Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 40
2.34
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.35
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 41
2.36
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 41
2.37
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.38
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.39
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.40
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.41
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.42
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.43
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.44
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Contents
STM32F469xx
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1
4/208
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.2
VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.3
Operating conditions at power-up / power-down (regulator ON) . . . . . . 92
5.3.4
Operating conditions at power-up / power-down (regulator OFF) . . . . . 92
5.3.5
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 92
5.3.6
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.7
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.3.8
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.9
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.10
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.3.11
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.3.12
PLL spread spectrum clock generation (SSCG) characteristics . . . . . 119
5.3.13
MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.3.14
MIPI D-PHY PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.3.15
MIPI D-PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.3.16
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.17
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.18
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 128
5.3.19
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.20
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.3.21
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.3.22
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.3.23
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.3.24
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
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7
Contents
5.3.25
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.3.26
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.3.27
Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.3.28
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.3.29
FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.3.30
Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.3.31
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 182
5.3.32
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 183
5.3.33
SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 185
5.3.34
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
6.1
WLCSP168 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
6.2
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.3
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.4
UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.5
LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.6
TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.7
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 206
A.1
8
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
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List of tables
STM32F469xx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
6/208
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F469xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 30
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 32
Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM32F469xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
STM32F469xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 91
VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 92
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 92
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM,
regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled), regulator ON . . . . . . . . . . . . . . . 97
Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator enabled except prefetch),
regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . . 99
Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 100
Typical and maximum current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 101
Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 102
Typical and maximum current consumption in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 103
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PLLSAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
DocID028196 Rev 2
STM32F469xx
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
List of tables
SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 122
DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
DSI regulator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 150
Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 151
Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 151
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 155
ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 155
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings . . . . . . . . . . . . . . . . 163
Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 163
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 164
Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 165
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 166
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DocID028196 Rev 2
7/208
8
List of tables
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
8/208
STM32F469xx
Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 168
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 173
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 177
SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 186
Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . 187
RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 196
UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 197
LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 206
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
DocID028196 Rev 2
STM32F469xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Incompatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Incompatible board design for LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
UFBGA176 port-to-terminal assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TFBGA216 port-to-terminal assignment differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STM32F469xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM32F469xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 27
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 28
PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 32
Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 32
STM32F46x WLCSP168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32F46x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STM32F46x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STM32F46x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM32F46x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32F46x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in Low drive mode) . . . . . . . . . . . . . . . . . . . . . . 103
Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in High drive mode) . . . . . . . . . . . . . . . . . . . . . . 104
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
HSI deviation vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 123
MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 123
FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
DocID028196 Rev 2
9/208
10
List of figures
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
10/208
STM32F469xx
SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 147
ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 157
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 157
12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 162
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 164
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 165
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 167
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 173
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 176
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 177
SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Quad-SPI SDR timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Quad-SPI DDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip
scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 192
LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 198
LQFP208 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm, package outline . . . . . . . . . 202
TFBGA216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DocID028196 Rev 2
STM32F469xx
1
Description
Description
The STM32F469xx devices are based on the high-performance ARM® Cortex®-M4 32-bit
RISC core operating at a frequency of up to 180 MHz. The Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all ARM® single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F469xx devices incorporate high-speed embedded memories (Flash memory
up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an
extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB
buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers,
and a true random number generator (RNG). They also feature standard and advanced
communication interfaces:
•
Up to three I2Cs
•
Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can
be clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
•
Four USARTs plus four UARTs
•
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
•
Two CANs
•
One SAI serial audio interface
•
An SDMMC host interface
•
Ethernet and camera interface
•
LCD-TFT display controller
•
Chrom-ART Accelerator™
•
DSI Host.
Advanced peripherals include an SDMMC interface, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory, and camera interface for CMOS sensors. Refer to
Table 2 for the list of peripherals available on each part number.
The STM32F469xx devices operate in the –40 to +105 °C temperature range from a 1.7 to
3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full
speed mode, is available on all packages.
The supply voltage can drop to 1.7 V (refer to Section 2.19.2). A comprehensive set of
power-saving mode allows the design of low-power applications.
The STM32F469xx devices are offered in 5 packages, ranging from 168 pins to 216 pins.
The set of included peripherals changes with the device chosen, according to Table 2.
DocID028196 Rev 2
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44
Description
STM32F469xx
These features make the STM32F469xx microcontrollers suitable for a wide range of
applications:
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
Figure 5 shows the general block diagram of the device family.
Table 2. STM32F469xx features and peripheral counts
Peripherals
STM32F469Ax
Flash memory in Kbytes
SRAM in
Kbytes
512
1024 2048
STM32F469Ix
512
STM32F469Bx
1024 2048
512
System
384(160+32+128+64)
Backup
4
FMC memory controller
Yes
Quad-SPI
Yes
Ethernet
Timers
No
Generalpurpose
10
Advancedcontrol
2
Basic
2
1024 2048
Yes
2S
6/2(full duplex)(1)
SPI / I
I2C
3
USART/UART
4/4
Communication USB OTG FS
interfaces
USB OTG HS
Yes
Yes
CAN
2
SAI
1
SDIO
Yes
Camera interface
Yes
MIPI-DSI Host
Yes
LCD-TFT
Yes
Chrom-ART Accelerator™
(DMA2D)
Yes
12/208
512
Yes
Random number generator
GPIOs
1024 2048
STM32F469Nx
114
131
DocID028196 Rev 2
161
161
STM32F469xx
Description
Table 2. STM32F469xx features and peripheral counts (continued)
Peripherals
STM32F469Ax
STM32F469Ix
STM32F469Bx
3
12-bit ADC
Number of channels
24
12-bit DAC
Number of channels
Yes
2
Maximum CPU frequency
180 MHz
1.7 to 3.6V(2)
Operating voltage
Operating temperatures
Package
STM32F469Nx
Ambient operating temperature: −40 to 85 °C / −40 to 105 °C
Junction temperature: −40 to 105 °C / −40 to 125 °C
UFBGA169
WLCSP168
LQFP176
UFBGA176
LQFP208
TFBGA216
1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
2. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2).
DocID028196 Rev 2
13/208
44
Description
1.1
STM32F469xx
Compatibility throughout the family
STM32F469xx devices are not compatible with other STM32F4xx devices. Figure 1 and
Figure 2 show incompatible board designs, respectively, for LQFP176 and LQFP208
packages (highlighted pins). The UFBGA176 and TFBGA216 ballouts are compatible with
other STM32F4xx devices, only few IO port pins are substituted, as shown in Figure 3 and
Figure 4. The UFBGA169 package is incompatible with other STM32F4xx devices.
1.1.1
LQFP176 package
DocID028196 Rev 2
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14/208
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1.1.2
Description
LQFP208 package
Figure 2. Incompatible board design for LQFP208 package
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1. Pins from 118 to 128 and pin 137 are not compatible
DocID028196 Rev 2
15/208
44
Description
1.1.3
STM32F469xx
UFBGA176 package
Figure 3. UFBGA176 port-to-terminal assignment differences
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1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.
16/208
DocID028196 Rev 2
STM32F469xx
1.1.4
Description
TFBGA216 package
Figure 4. TFBGA216 port-to-terminal assignment differences
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1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.
DocID028196 Rev 2
17/208
44
Description
STM32F469xx
Figure 5. STM32F469xx block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to
APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration
in the RCC_DCKCFGR register.
18/208
DocID028196 Rev 2
STM32F469xx
Functional overview
2
Functional overview
2.1
ARM® Cortex®-M4 with FPU and embedded Flash and SRAM
The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional
code-efficiency, delivering the high-performance expected from an ARM core in the memory
size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F46x line is compatible with all ARM tools and software.
Figure 5 shows the general block diagram of the STM32F46x line.
Note:
Cortex®-M4 with FPU core is binary compatible with the Cortex®-M3 core.
2.2
Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard
ARM® Cortex®-M4 with FPU processors. It balances the inherent performance advantage
of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which normally require
the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark® benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 180 MHz.
2.3
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DocID028196 Rev 2
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44
Functional overview
2.4
STM32F469xx
Embedded Flash memory
The devices embed a Flash memory of up to 2 Mbytes available for storing programs and
data.
2.5
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
2.6
Embedded SRAM
All devices embed:
•
Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory)
data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
•
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
2.7
Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB
and APB peripherals) and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
20/208
DocID028196 Rev 2
STM32F469xx
Functional overview
Figure 6. STM32F469xx Multi-AHB matrix
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DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
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Functional overview
STM32F469xx
The DMA can be used with the main peripherals:
2.9
•
SPI and I2S
•
I2C
•
USART
•
General-purpose, basic and advanced-control timers TIMx
•
DAC
•
SDIO
•
Camera interface (DCMI)
•
ADC
•
SAI1
•
QUADSPI.
Flexible Memory Controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
•
The NOR/PSRAM memory controller
•
The NAND/memory controller
•
The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
•
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•
8-,16-,32-bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
Read FIFO for SDRAM controller
•
The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
22/208
DocID028196 Rev 2
STM32F469xx
2.10
Functional overview
Quad-SPI memory interface (QUADSPI)
All STM32F469xx devices embeds a Quad-SPI memory interface, which is a specialized
communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can
work in direct mode through registers, external flash status register polling mode and
memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting
8, 16 and 32-bit access. Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
2.11
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2.12
•
2 displays layers with dedicated FIFO (64x32-bit)
•
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•
Up to 8 Input color formats selectable per layer
•
Flexible blending between two layers using alpha value (per pixel or constant)
•
Flexible programmable parameters for each layer
•
Color keying (transparency color)
•
Up to 4 programmable interrupt events.
DSI Host (DSIHOST)
The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
These interfaces are as follows:
•
•
•
LTDC interface:
–
Used to transmit information in Video Mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
–
Through a customized for mode, this interface can be used to transmit information
in full bandwidth in the Adapted Command Mode (DBI).
APB slave interface:
–
Allows the transmission of generic information in Command mode, and follows a
proprietary register interface.
–
Can operate concurrently with either LTDC interface in either Video Mode or
Adapted Command Mode.
Video mode pattern generator:
–
Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli.
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Functional overview
STM32F469xx
The DSI Host main features:
•
Compliant with MIPI® Alliance standards
•
•
Interface with MIPI® D-PHY
Supports all commands defined in the MIPI® Alliance specification for DCS:
–
Transmission of all Command mode packets through the APB interface
–
Transmission of commands in low-power and high-speed during Video Mode
•
Supports up to two D-PHY data lanes
•
Bidirectional communication and escape mode support through data lane 0
•
Supports non-continuous clock in D-PHY clock lane for additional power saving
•
Supports Ultra Low-Power mode with PLL disabled
•
ECC and Checksum capabilities
•
Support for End of Transmission Packet (EoTp)
•
Fault recovery schemes
•
3D transmission support
•
Configurable selection of system interfaces:
•
–
AMBA APB for control and optional support for Generic and DCS commands
–
Video Mode interface through LTDC
–
Adapted Command Mode interface through LTDC
Independently programmable Virtual Channel ID in
–
Video Mode
–
Adapted Command Mode
–
APB Slave
Video Mode interfaces features:
•
LTDC interface color coding mappings into 24-bit interface:
–
16-bit RGB, configurations 1, 2, and 3
–
18-bit RGB, configurations 1 and 2
–
24-bit RGB
•
Programmable polarity of all LTDC interface signals
•
Extended resolutions beyond the DPI standard maximum resolution of 800x480 pixels:
maximum resolution is limited by available DSI physical link bandwidth:
–
Number of lanes: 2
–
Maximum speed per lane: 500Mbps
Adapted interface features:
24/208
•
Support for sending large amounts of data through the memory_write_start (WMS) and
memory_write_continue (WMC) DCS commands
•
LTDC interface color coding mappings into 24-bit interface:
–
16-bit RGB, configurations 1, 2, and 3
–
18-bit RGB, configurations 1 and 2
–
24-bit RGB
DocID028196 Rev 2
STM32F469xx
Functional overview
Video mode pattern generator:
2.13
•
Vertical and horizontal color bar generation without LTDC stimuli
•
BER pattern without LTDC stimuli
Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
Rectangle filling with a fixed color
•
Rectangle copy
•
Rectangle copy with pixel format conversion
•
Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
2.14
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4 with FPU core.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.15
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected
to the 16 external interrupt lines.
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44
Functional overview
2.16
STM32F469xx
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio
class performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
2.17
Boot modes
At startup, boot pins are used to select one out of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to application note AN2606 for details.
2.18
Note:
26/208
Power supply schemes
•
VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
•
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 2.19.2). Refer to Table 3 to identify the packages supporting this option.
•
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
•
VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6V) for USB transceivers.
For example, when device is powered at 1.8V, an independent power supply 3.3V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
it is independent from VDD or VDDA but it must be the last supply to be provided and the
first to disappear.
DocID028196 Rev 2
STM32F469xx
Functional overview
The following conditions must be respected:
–
During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
–
VDDUSB rising and falling time rate specifications must be respected.
–
In operating mode phase, VDDUSB could be lower or higher than VDD:
– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.The VDDUSB
supplies both USB transceivers (USB OTG_HS and USB OTG_FS).
– If only one USB transceiver is used in the application, the GPIOs associated to
the other USB transceiver are still supplied by VDDUSB.
– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by VDDUSB are operating between VDD_MIN and VDD_MAX.
Figure 7. VDDUSB connected to an external independent power supply
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The DSI (Display Serial Interface) sub-system uses several power supply pins which are
independent from the other supply pins:
•
VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI DPHY. This supply must be connected to global VDD.
•
VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected externally
to VDD12DSI.
•
VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes
pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.
•
VSSDSI pin is an isolated supply ground used for DSI sub-system.
•
If DSI functionality is not used at all, then:
–
VDDDSI pin must be connected to global VDD.
–
VCAPDSI pin must be connected externally to VDD12DSI but the external
capacitor is no more needed.
–
VSSDSI pin must be grounded.
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Functional overview
STM32F469xx
2.19
Power supply supervisor
2.19.1
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.19.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON must be
connected to VSS, as shown in Figure 8.
Figure 8. Power supply supervisor interconnection with internal reset OFF
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The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 9).
A comprehensive set of power-saving mode allows to design low-power applications.
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Functional overview
When the internal reset is OFF, the following integrated features are no more supported:
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
•
The brownout reset (BOR) circuitry must be disabled
•
The embedded programmable voltage detector (PVD) is disabled
•
VBAT functionality is no more available and VBAT pin should be connected to VDD.
All packages allow to disable the internal reset through the PDR_ON signal when connected
to VSS.
Figure 9. PDR_ON control with internal reset OFF
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1. PDR_ON signal to be kept always low.
2.20
Voltage regulator
The regulator has four operating modes:
•
•
2.20.1
Regulator ON
–
Main regulator mode (MR)
–
Low power regulator (LPR)
–
Power-down
Regulator OFF
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
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Functional overview
STM32F469xx
There are three power modes configured by software when the regulator is ON:
•
MR mode used in Run/sleep modes or in Stop modes
–
In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
–
In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
•
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
•
–
LPR operates in normal mode (default mode when LPR is ON)
–
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to
Section 2.18 and Table 123.
All packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode(1)
Voltage regulator
configuration
Run mode
Sleep mode
Stop mode
Standby mode
Normal mode
MR
MR
MR or LPR
-
Over-drive
mode(2)
MR
MR
-
-
Under-drive mode
-
-
MR or LPR
-
Power-down
mode
-
-
-
Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
2.20.2
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
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Functional overview
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Operating conditions.The two
2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer
to Section 2.18.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
•
The over-drive and under-drive modes are not available.
•
The Standby mode is not available.
Figure 10. Regulator OFF
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The following conditions must be respected:
Note:
•
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
•
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 11).
•
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 12).
•
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
The minimum value of V12 depends on the maximum frequency targeted in the application
(see Operating conditions).
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Functional overview
STM32F469xx
Figure 11. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1 , VCAP_2 stabilization
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1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 12. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1 , VCAP_2 stabilization
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1. This figure is valid whatever the internal reset mode (ON or OFF).
2.20.3
Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
32/208
Package
Regulator ON
Regulator OFF
WLCSP168
UFBGA169
LQFP208
Yes
No
LQFP176
UFBGA176
TFBGA216
Yes
BYPASS_REG set
to VSS
Yes
BYPASS_REG set
to VDD
DocID028196 Rev 2
Internal reset ON
Internal reset OFF
Yes
Yes
PDR_ON set to VDD PDR_ON set to VSS
STM32F469xx
2.21
Functional overview
Real-time clock (RTC), backup SRAM and backup registers
The backup domain includes:
•
The real-time clock (RTC)
•
4 Kbytes of backup SRAM
•
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is
also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data
which need to be retained in VBAT and standby mode. This memory area is disabled by
default to minimize power consumption (see Section 2.22). It can be enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 2.22).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or from the VBAT pin.
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Functional overview
2.22
STM32F469xx
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5):
–
Normal mode (default mode when MR or LPR is enabled)
–
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
Table 5. Voltage regulator modes in stop mode
•
Voltage regulator
configuration
Main regulator (MR)
Low-power regulator (LPR)
Normal mode
MR ON
LPR ON
Under-drive mode
MR in under-drive mode
LPR in under-drive mode
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
2.23
VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
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Note:
Functional overview
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
2.24
Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
Table 6. Timer feature comparison
Timer
type
Advanced
control
General
purpose
Basic
Counter Counter Prescaler
Timer
resolution
type
factor
Max
Max
DMA
Capture/
Complementary interface timer
request
compare
output
clock
clock
generation channels
(MHz) (MHz)(1)
TIM1,
TIM8
16-bit
Any integer
Up,
between 1
Down,
Up/down and 65536
Yes
4
Yes
90
180
TIM2,
TIM5
32-bit
Any integer
Up,
between 1
Down,
Up/down and 65536
Yes
4
No
45
90/180
TIM3,
TIM4
16-bit
Any integer
Up,
between 1
Down,
Up/down and 65536
Yes
4
No
45
90/180
TIM9
16-bit
Up
Any integer
between 1
and 65536
No
2
No
90
180
TIM10
,
TIM11
16-bit
Up
Any integer
between 1
and 65536
No
1
No
90
180
TIM12
16-bit
Up
Any integer
between 1
and 65536
No
2
No
45
90/180
TIM13
,
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
1
No
45
90/180
TIM6,
TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
45
90/180
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the
RCC_DCKCFGR register.
2.24.1
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
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Functional overview
STM32F469xx
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (edge- or center-aligned modes)
•
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
2.24.2
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F46x devices
(see Table 6 for differences).
•
TIM2, TIM3, TIM4, TIM5
The STM32F46x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/down
counter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit autoreload up/down counter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
2.24.3
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
2.24.4
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
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Functional overview
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
2.24.5
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
2.24.6
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
2.25
•
A 24-bit downcounter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source.
Inter-integrated circuit interface (I2C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the
7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 7).
Table 7. Comparison of I2C analog and digital filters
Analog filter
Pulse width of
suppressed spikes
2.26
≥ 50 ns
Digital filter
Programmable length from 1 to 15
I2C peripheral clocks
Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate
at up to 5.62 bit/s.
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STM32F469xx
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
Table 8. USART feature comparison(1)
USART
name
Max. baud
Max. baud
Standard
Modem
SPI
Smartcard rate in Mbit/s rate in Mbit/s
APB
LIN
irDA
features (RTS/CTS)
master
(ISO 7816) (oversampling (oversampling mapping
by 16)
by 8)
USART1
X
X
X
X
X
X
5.62
11.25
APB2
(max.
90 MHz)
USART2
X
X
X
X
X
X
2.81
5.62
APB1
(max.
45 MHz)
USART3
X
X
X
X
X
X
2.81
5.62
APB1
(max.
45 MHz)
UART4
X
-
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
UART5
X
-
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
USART6
X
X
X
X
X
X
5.62
11.25
APB2
(max.
90 MHz)
UART7
X
-
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
UART8
X
-
X
-
X
-
2.81
5.62
APB1
(max.
45 MHz)
1. X = feature supported.
2.27
Serial peripheral interface (SPI)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,
SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
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2.28
Functional overview
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes, and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
Note:
For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port
B and GPIO Port D.
2.29
Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
2.30
Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).
2.31
Audio and LCD PLL(PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
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Functional overview
2.32
STM32F469xx
Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
2.33
Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
2.34
•
Supports 10 and 100 Mbit/s rates
•
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F4xx reference manual for details)
•
Tagged MAC frame support (VLAN support)
•
Half-duplex (CSMA/CD) and full-duplex operation
•
MAC control sublayer (control frames) support
•
32-bit CRC generation and removal
•
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
32-bit status code for each transmitted or received frame
•
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•
Triggers interrupt when system time becomes greater than target time
Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
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Functional overview
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
2.35
Universal serial bus on-the-go full-speed (OTG_FS)
The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
•
Combined Rx and Tx FIFO size of 1.28 KB with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
•
12 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
USB 2.0 LPM (Link Power Management) support
•
Internal FS OTG PHY support
•
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.36
Universal serial bus on-the-go high-speed (OTG_HS)
The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)
for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
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44
Functional overview
STM32F469xx
The major features are:
2.37
•
Combined Rx and Tx FIFO size of 4 KB with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
8 bidirectional endpoints
•
16 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
USB 2.0 LPM (Link Power Management) support
•
Internal FS OTG PHY support
•
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
•
Internal USB DMA
•
HNP/SNP/IP inside (no need for any external resistor)
•
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
2.38
•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication can be 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports continuous mode or snapshot (a single frame) mode
•
Capability to automatically crop the image black & white.
Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
2.39
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
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2.40
Functional overview
Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
2.41
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
2.42
Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
two DAC converters: one for each output channel
•
8-bit or 10-bit monotonic output
•
left or right data alignment in 12-bit mode
•
synchronized update capability
•
noise-wave generation
•
triangular-wave generation
•
dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel
•
external triggers for conversion
•
input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
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44
Functional overview
2.43
STM32F469xx
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
2.44
Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F46x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
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3
Pinouts and pin description
Pinouts and pin description
Figure 13. STM32F46x WLCSP168 pinout
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DocID028196 Rev 2
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79
Pinouts and pin description
STM32F469xx
Figure 14. STM32F46x UFBGA169 ballout
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46/208
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
Figure 15. STM32F46x UFBGA176 ballout
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DocID028196 Rev 2
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79
Pinouts and pin description
STM32F469xx
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48/208
DocID028196 Rev 2
069
STM32F469xx
Pinouts and pin description
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DocID028196 Rev 2
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79
Pinouts and pin description
STM32F469xx
Figure 18. STM32F46x TFBGA216 ballout
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1. The above figure shows the package top view.
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STM32F469xx
Pinouts and pin description
Table 9. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
I/O structure
Notes
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TTa
3.3 V tolerant I/O directly connected to analog parts
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
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79
Pinouts and pin description
STM32F469xx
B2
F9
A2
1
1
A3
PE2
I/O
FT
-
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
C1
E10
A1
2
2
A2
PE3
I/O
FT
-
TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT
-
-
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, LCD_B0,
EVENTOUT
-
-
TRACED2, TIM9_CH1,
SPI4_MISO,
SAI1_SCK_A, FMC_A21,
DCMI_D6, LCD_G0,
EVENTOUT
-
-
C2
C11
D1
B12
B1
B2
3
4
LQFP208
Alternate functions
LQFP176
Notes
Pin name
(function after
reset)(1)
Pin types
TFBGA216
UFBGA176
UFBGA169
WLCSP168
Pin Number
I/O structures
Table 10. STM32F469xx pin and ball definitions
3
4
A1
B1
PE4
PE5
I/O
I/O
FT
FT
Additional
functions
-
D2
D11
B3
5
5
B2
PE6
I/O
FT
-
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SPI4_MOSI, SAI1_SD_A,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
-
-
-
-
-
G6
VSS
S
-
-
-
-
-
-
-
-
-
F5
VDD
S
-
-
-
-
E5
C12
C1
6
6
C1
VBAT
S
-
-
-
-
-
-
D2
7
7
C2
PI8
I/O
FT
EVENTOUT
RTC_TAMP1/
RTC_TAMP2/
RTC_TS
G4
D12
D1
8
8
D1
PC13
I/O
FT
EVENTOUT
RTC_TAMP1/
RTC_TS/
RTC_OUT
E1
E11
E1
9
9
E1
PC14OSC32_IN
(PC14)
I/O
FT
EVENTOUT
OSC32_IN
F1
E12
F1
10
10
F1
PC15OSC32_OUT
(PC15)
I/O
FT
(3)
EVENTOUT
OSC32_OUT
-
-
-
-
-
G5
VDD
S
-
-
-
-
E2
G9
D3
11
11
E4
PI9
I/O
FT
CAN1_RX, FMC_D30,
LCD_VSYNC,
EVENTOUT
-
52/208
(2)
(3)
(2)
(3)
(2)
(3)
(2)
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
Table 10. STM32F469xx pin and ball definitions (continued)
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
E4
F10
E3
12
12
D5
PI10
I/O
FT
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
-
F2
F11
E4
13
13
F3
PI11
I/O
FT
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
-
F5
F12
F2
14
14
F2
VSS
S
-
-
-
-
F4
G11
F3
15
15
F4
VDD
S
-
-
-
-
F3
G10
E2
16
16
D2
PF0
I/O
FT
I2C2_SDA, FMC_A0,
EVENTOUT
-
G3
H10
H3
17
17
E2
PF1
I/O
FT
I2C2_SCL, FMC_A1,
EVENTOUT
-
G5
G12
H2
18
18
G2
PF2
I/O
FT
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
-
19
E3
PI12
I/O
FT
LCD_HSYNC,
EVENTOUT
-
-
-
-
-
20
G3
PI13
I/O
FT
LCD_VSYNC,
EVENTOUT
-
-
-
-
-
21
H3
PI14
I/O
FT
H4
H11
J2
19
22
H2
PF3
I/O
Notes
UFBGA169
Pin Number
Alternate functions
Additional
functions
LCD_CLK, EVENTOUT
-
FT
(4)
FMC_A3, EVENTOUT
ADC3_IN9
FMC_A4, EVENTOUT
ADC3_IN14
L4
J10
J3
20
23
J2
PF4
I/O
FT
(4)
H3
H12
K3
21
24
K3
PF5
I/O
FT
(4)
FMC_A5, EVENTOUT
ADC3_IN15
G7
J11
G2
22
25
H6
VSS
S
-
-
-
-
G8
J12
G3
23
26
H5
VDD
S
-
-
-
-
(4)
TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_Rx,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_IN4
(4)
TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_Tx,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_IN5
(4)
SPI5_MISO,
SAI1_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_IN6
-
-
-
-
-
-
K2
K1
L3
24
25
26
27
28
29
K2
K1
L3
PF6
PF7
PF8
I/O
I/O
I/O
FT
FT
FT
DocID028196 Rev 2
53/208
79
Pinouts and pin description
STM32F469xx
Table 10. STM32F469xx pin and ball definitions (continued)
Notes
30
L2
PF9
I/O
FT
H1
K10
L1
28
31
L1
PF10
I/O
FT
(4)
QUADSPI_CLK,
DCMI_D11, LCD_DE,
EVENTOUT
ADC3_IN8
G2
K11
G1
29
32
G1
PH0-OSC_IN
(PH0)
I/O
FT
-
EVENTOUT
OSC_IN
G1
K12
H1
30
33
H1
PH1-OSC_OUT
I/O
(PH1)
FT
-
EVENTOUT
OSC_OUT
H2
H9
J1
31
34
J1
NRST
M1
J9
M2
32
35
M2
PC0
UFBGA169
N1
L12
-
-
M3
M4
33
34
36
37
M3
M4
Pin name
(function after
reset)(1)
PC1
PC2
Pin types
27
TFBGA216
L2
LQFP208
-
SPI5_MOSI, SAI1_FS_B,
TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
LQFP176
-
(4)
UFBGA176
Alternate functions
WLCSP168
I/O structures
Pin Number
I/O RST
I/O
I/O
I/O
Additional
functions
ADC3_IN7
-
FT
(4)
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_IN10
FT
(4)
TRACED0,
SPI2_MOSI/I2S2_SD,
SAI1_SD_A, ETH_MDC,
EVENTOUT
ADC123_IN11
(4)
SPI2_MISO, I2S2ext_SD,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
ADC123_IN12
ADC123_IN13
FT
-
-
M5
35
38
L4
PC3
I/O
FT
(4)
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
-
-
-
36
39
J5
VDD
S
-
-
-
-
-
-
-
-
-
J6
VSS
S
-
-
-
-
J2
L11
M1
37
40
M1
VSSA
S
-
-
-
-
-
-
N1
-
-
N1
VREF-
S
-
-
-
-
-
-
P1
38
41
P1
VREF+
S
-
-
-
-
J3
M12
R1
39
42
R1
VDDA
S
-
-
-
-
(5)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
UART4_TX,
ETH_MII_CRS,
EVENTOUT
ADC123_IN0,
WKUP
J5
54/208
L10
N3
40
43
N3
PA0WKUP(PA0)
I/O
FT
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
K2
L2
K9
L9
M11
P2
F4
41
42
43
44
45
46
N2
P2
K4
PA1
PA2
PH2
Pin types
TFBGA216
LQFP208
LQFP176
UFBGA176
N2
Pin name
(function after
reset)(1)
I/O
I/O
I/O
Notes
K1
WLCSP168
UFBGA169
Pin Number
I/O structures
Table 10. STM32F469xx pin and ball definitions (continued)
FT
TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
(4)
QUADSPI_BK1_IO3,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK, LCD_R2,
EVENTOUT
ADC123_IN1
FT
(4)
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
ETH_MDIO, LCD_R1,
EVENTOUT
ADC123_IN2
-
QUADSPI_BK2_IO0,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
-
FT
Alternate functions
Additional
functions
L1
N12
G4
44
47
J4
PH3
I/O
FT
-
QUADSPI_BK2_IO1,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
M2
M10
H4
45
48
H4
PH4
I/O
FT
-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
-
L3
K8
J4
46
49
J3
PH5
I/O
FT
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
EVENTOUT
-
ADC123_IN3
K3
N10
R2
47
50
R2
PA3
I/O
FT
(4)
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
J1
N11
-
-
51
K6
VSS
S
-
-
-
-
-
-
L4
48
-
L5
BYPASS_REG
I
FT
-
-
-
J4
P12
K4
49
52
K5
VDD
S
-
-
-
-
-
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
ADC12_IN4,
DAC_OUT1
N2
M9
N4
50
53
N4
PA4
I/O TTa
DocID028196 Rev 2
55/208
79
Pinouts and pin description
STM32F469xx
N3
L8
P11
P3
51
52
54
55
P4
P3
PA5
PA6
Pin types
TFBGA216
LQFP208
LQFP176
UFBGA176
P4
Pin name
(function after
reset)(1)
I/O TTa
I/O
FT
Notes
M3
WLCSP168
UFBGA169
Pin Number
I/O structures
Table 10. STM32F469xx pin and ball definitions (continued)
Alternate functions
Additional
functions
-
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, SPI1_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_IN5,
DAC_OUT2
(4)
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
TIM13_CH1,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_IN6
ADC12_IN7
K4
J8
R3
53
56
R3
PA7
I/O
FT
(4)
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N, SPI1_MOSI,
TIM14_CH1,
QUADSPI_CLK,
ETH_MII_RX_DV/ETH_R
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
-
-
N5
54
57
N5
PC4
I/O
FT
(4)
ETH_MII_RXD0/ETH_RMI
I_RXD0, FMC_SDNE0,
EVENTOUT
ADC12_IN14
-
-
P5
55
58
P5
PC5
I/O
FT
(4)
ETH_MII_RXD1/ETH_RMI
I_RXD1, FMC_SDCKE0,
EVENTOUT
ADC12_IN15
-
-
-
-
59
L7
VDD
S
-
-
-
-
-
-
-
-
60
L6
VSS
S
-
-
-
-
N4
P10
R5
56
61
R5
PB0
I/O
FT
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N, LCD_R3,
(4)
OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1,
EVENTOUT
ADC12_IN8
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LCD_R6,
(4)
OTG_HS_ULPI_D2,
ETH_MII_RXD3, LCD_G0,
EVENTOUT
ADC12_IN9
K5
N9
R4
57
62
R4
PB1
I/O
FT
L5
P9
M6
58
63
M5
PB2BOOT1(PB2)
I/O
FT
-
EVENTOUT
-
-
-
-
-
64
G4
PI15
I/O
FT
-
LCD_G2, LCD_R0,
EVENTOUT
-
-
-
-
-
65
R6
PJ0
I/O
FT
-
LCD_R7, LCD_R1,
EVENTOUT
-
-
-
-
-
66
R7
PJ1
I/O
FT
-
LCD_R2, EVENTOUT
-
56/208
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
Table 10. STM32F469xx pin and ball definitions (continued)
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Pin Number
Alternate functions
-
-
-
-
67
P7
PJ2
I/O
FT
-
DSIHOST_TE, LCD_R3,
EVENTOUT
-
-
-
-
-
68
N8
PJ3
I/O
FT
-
LCD_R4, EVENTOUT
-
-
-
-
-
69
M9
PJ4
I/O
FT
-
LCD_R5, EVENTOUT
-
M5
K7
R6
59
70
P8
PF11
I/O
FT
-
SPI5_MOSI,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
-
N5
M8
P6
60
71
M6
PF12
I/O
FT
-
FMC_A6, EVENTOUT
-
J6
N8
M8
61
72
K7
VSS
S
-
-
-
-
K6
P8
N8
62
73
L8
VDD
S
-
-
-
-
M4
J7
N6
63
74
N6
PF13
I/O
FT
-
FMC_A7, EVENTOUT
-
H5
L7
R7
64
75
P6
PF14
I/O
FT
-
FMC_A8, EVENTOUT
-
M6
H8
P7
65
76
M8
PF15
I/O
FT
-
FMC_A9, EVENTOUT
-
N6
J6
N7
66
77
N7
PG0
I/O
FT
-
FMC_A10, EVENTOUT
-
M7
P7
M7
67
78
M7
PG1
I/O
FT
-
FMC_A11, EVENTOUT
-
N7
N7
R8
68
79
R8
PE7
I/O
FT
-
TIM1_ETR, UART7_Rx,
QUADSPI_BK2_IO0,
FMC_D4, EVENTOUT
-
G6
M7
P8
69
80
N9
PE8
I/O
FT
-
TIM1_CH1N, UART7_Tx,
QUADSPI_BK2_IO1,
FMC_D5, EVENTOUT
-
H6
K6
P9
70
81
P9
PE9
I/O
FT
-
TIM1_CH1,
QUADSPI_BK2_IO2,
FMC_D6, EVENTOUT
-
J7
-
M9
71
82
K8
VSS
S
-
-
-
-
L6
-
N9
72
83
L9
VDD
S
-
-
-
-
H7
P6
R9
73
84
R9
PE10
I/O
FT
-
TIM1_CH2N,
QUADSPI_BK2_IO3,
FMC_D7, EVENTOUT
-
K7
N6
P10
74
85
P10
PE11
I/O
FT
-
TIM1_CH2, SPI4_NSS,
FMC_D8, LCD_G3,
EVENTOUT
-
L7
M6
R10
75
86
R10
PE12
I/O
FT
-
TIM1_CH3N, SPI4_SCK,
FMC_D9, LCD_B4,
EVENTOUT
-
J8
L6
N11
76
87
R12
PE13
I/O
FT
-
TIM1_CH3, SPI4_MISO,
FMC_D10, LCD_DE,
EVENTOUT
-
DocID028196 Rev 2
Additional
functions
57/208
79
Pinouts and pin description
STM32F469xx
Table 10. STM32F469xx pin and ball definitions (continued)
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Pin Number
Alternate functions
K8
J5
P11
77
88
P11
PE14
I/O
FT
-
TIM1_CH4, SPI4_MOSI,
FMC_D11, LCD_CLK,
EVENTOUT
-
L8
P5
R11
78
89
R11
PE15
I/O
FT
-
TIM1_BKIN, FMC_D12,
LCD_R7, EVENTOUT
-
-
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
-
-
M8
N5
R12
79
90
P12
PB10
I/O
FT
Additional
functions
N8
K5
R13
80
91
R13
PB11
I/O
FT
-
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN,
DSIHOST_TE, LCD_G5,
EVENTOUT
N9
N4
M10
81
92
L11
VCAP1
S
-
-
-
-
M9
P4
-
-
93
K9
VSS
S
-
-
-
-
L9
P3
N10
82
94
L10
VDD
S
-
-
-
-
-
-
-
-
95
M14
PJ5
I/O
FT
-
LCD_R6, EVENTOUT
-
-
I2C2_SMBA, SPI5_SCK,
TIM12_CH1,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
-
-
-
M11
83
96
P13
PH6
I/O
FT
-
-
N12
84
97
N13
PH7
I/O
FT
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
H8
M5
-
-
98
P14
PH8
I/O
FT
-
I2C3_SDA, FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
H9
L5
-
-
99
N14
PH9
I/O
FT
-
I2C3_SMBA, TIM12_CH2,
FMC_D17, DCMI_D0,
LCD_R3, EVENTOUT
-
J9
M4
-
-
100
P15
PH10
I/O
FT
-
TIM5_CH1, FMC_D18,
DCMI_D1, LCD_R4,
EVENTOUT
-
58/208
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
Table 10. STM32F469xx pin and ball definitions (continued)
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Pin Number
Alternate functions
K9
N3
-
-
101
N15
PH11
I/O
FT
-
TIM5_CH2, FMC_D19,
DCMI_D2, LCD_R5,
EVENTOUT
-
H10
P2
-
-
102 M15
PH12
I/O
FT
-
TIM5_CH3, FMC_D20,
DCMI_D3, LCD_R6,
EVENTOUT
-
-
H7
-
-
-
K10
VSS
S
-
-
-
-
-
-
-
-
103
K11
VDD
S
-
-
-
-
-
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK, CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMI
I_TXD0, OTG_HS_ID,
EVENTOUT
-
-
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS, CAN2_TX, OTG_HS_VBU
OTG_HS_ULPI_D6,
S
ETH_MII_TXD1/ETH_RMI
I_TXD1, EVENTOUT
-
TIM1_CH2N,
TIM8_CH2N, SPI2_MISO,
I2S2ext_SD,
USART3_RTS,
TIM12_CH1,
OTG_HS_DM,
EVENTOUT
-
-
N10
N11
N12
H5
K4
P1
P12
P13
R14
85
86
87
104
105
106
L13
K14
R14
PB12
PB13
PB14
I/O
I/O
I/O
FT
FT
FT
Additional
functions
N13
N2
R15
88
107
R15
PB15
I/O
FT
-
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2,
OTG_HS_DP, EVENTOUT
L10
L4
P15
89
108
L15
PD8
I/O
FT
-
USART3_TX, FMC_D13,
EVENTOUT
-
M10
N1
P14
90
109
L14
PD9
I/O
FT
-
USART3_RX, FMC_D14,
EVENTOUT
-
L11
M3
N15
91
110
K15
PD10
I/O
FT
-
USART3_CK, FMC_D15,
LCD_B3, EVENTOUT
-
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79
Pinouts and pin description
STM32F469xx
J4
92
111
N10
PD11
Pin types
TFBGA216
LQFP208
LQFP176
UFBGA176
N14
Pin name
(function after
reset)(1)
I/O
FT
Notes
M11
WLCSP168
UFBGA169
Pin Number
I/O structures
Table 10. STM32F469xx pin and ball definitions (continued)
Alternate functions
Additional
functions
-
USART3_CTS,
QUADSPI_BK1_IO0,
FMC_A16/FMC_CLE,
EVENTOUT
-
-
M13
M2
N13
93
112 M10
PD12
I/O
FT
-
TIM4_CH1,
USART3_RTS,
QUADSPI_BK1_IO1,
FMC_A17/FMC_ALE,
EVENTOUT
M12
H4
M15
94
113
M11
PD13
I/O
FT
-
TIM4_CH2,
QUADSPI_BK1_IO3,
FMC_A18, EVENTOUT
-
J10
M1
-
95
114
J10
VSS
S
-
-
-
-
K10
-
J13
96
115
J11
VDD
S
-
-
-
-
L12
L3
M14
97
116
L12
PD14
I/O
FT
-
TIM4_CH3, FMC_D0,
EVENTOUT
-
L13
L2
L14
98
117
K13
PD15
I/O
FT
-
TIM4_CH4, FMC_D1,
EVENTOUT
-
K13
L1
J12
99
118
H11
VDDDSI
S
-
-
-
-
-
-
-
-
-
H10
VSS
S
-
-
-
-
K12
K1
K12
K12
VCAPDSI
S
-
-
-
-
-
K2
D13
G13
VDD12DSI
S
-
-
-
-
J12
K3
M12 101 120
J12
DSIHOST_D0P I/O
-
-
-
-
J13
J3
M13 102 121
J13
DSIHOST_D0N I/O
-
-
-
-
K11
H1
H12 103 122 G12
-
-
-
-
H12
J1
L12
104 123
H12 DSIHOST_CKP I/O
-
-
-
-
H13
J2
L13
105 124
H13 DSIHOST_CKN I/O
-
-
-
-
J11
-
-
-
-
-
G12
H3
E12
107 126
F12
DSIHOST_D1P I/O
-
-
-
-
G13
H2
E13
108 127
F13
DSIHOST_D1N I/O
-
-
-
-
H11
-
F13
G5
L15
F12
G4
E13
G2
60/208
100 119
-
-
D13 106 125
H12 109 128
-
-
VSSDSI
VDD12DSI
S
S
VSSDSI
S
-
-
-
-
110 129 M13
PG2
I/O
FT
-
FMC_A12, EVENTOUT
-
K15
111
PG3
I/O
FT
-
FMC_A13, EVENTOUT
-
K14
112 131
PG4
I/O
FT
-
FMC_A14/FMC_BA0,
EVENTOUT
-
130 M12
N12
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
Table 10. STM32F469xx pin and ball definitions (continued)
WLCSP168
UFBGA176
LQFP176
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions
E12
G1
K13
113 132
N11
PG5
I/O
FT
-
FMC_A15/FMC_BA1,
EVENTOUT
-
F11
G3
J15
114 133
J15
PG6
I/O
FT
-
DCMI_D12, LCD_R7,
EVENTOUT
-
-
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
-
E11
H6
J14
LQFP208
UFBGA169
Pin Number
115 134
J14
PG7
I/O
FT
Additional
functions
D13
G6
H14
H14
PG8
I/O
FT
-
SPI6_NSS,
USART6_RTS,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
G9
F2
G12 117 136 G10
VSS
S
-
-
-
-
G11
F1
H13
VDDUSB
S
-
-
-
-
-
TIM3_CH1, TIM8_CH1,
I2S2_MCK, USART6_TX,
SDIO_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
-
-
TIM3_CH2, TIM8_CH2,
I2S3_MCK, USART6_RX,
SDIO_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
-
TRACED1, TIM3_CH3,
TIM8_CH3, USART6_CK,
SDIO_D0, DCMI_D2,
EVENTOUT
-
-
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN,
QUADSPI_BK1_IO0,
SDIO_D1, DCMI_D3,
EVENTOUT
-
-
MCO1, TIM1_CH1,
I2C3_SCL, USART1_CK,
OTG_FS_SOF, LCD_R6,
EVENTOUT
-
-
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX, DCMI_D0,
EVENTOUT
OTG_FS_VBU
S
F9
F10
E10
G10
D8
E8
F3
G7
F4
F5
E1
E2
H15
116 135
118 137
119 138
G11
H15
G15 120 139 G15
G14 121 140 G14
F14
F15
E15
122 141
123 142
124 143
F14
F15
E15
PC6
PC7
PC8
PC9
PA8
PA9
I/O
I/O
I/O
I/O
I/O
I/O
FT
FT
FT
FT
FT
FT
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79
Pinouts and pin description
STM32F469xx
F7
C15 126 145
D15
PA10
I/O
C15
PA11
I/O
Notes
A13
Pin name
(function after
reset)(1)
Pin types
D15 125 144
TFBGA216
UFBGA176
E3
LQFP208
WLCSP168
E9
LQFP176
UFBGA169
Pin Number
I/O structures
Table 10. STM32F469xx pin and ball definitions (continued)
Alternate functions
Additional
functions
FT
-
TIM1_CH3, USART1_RX,
OTG_FS_ID, DCMI_D1,
EVENTOUT
-
-
TIM1_CH4,
USART1_CTS,
CAN1_RX, OTG_FS_DM,
LCD_R4, EVENTOUT
-
-
FT
A12
F6
B15
127 146
B15
PA12
I/O
FT
-
TIM1_ETR,
USART1_RTS, CAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
A11
D1
A15
128 147
A15
PA13(JTMSSWDIO)
I/O
FT
-
JTMS-SWDIO,
EVENTOUT
-
D12
D2
F13
129 148
E11
VCAP2
S
-
-
-
-
D11
C1
F12
130 149
F10
VSS
S
-
-
-
-
D10
C2
G13 131 150
F11
VDD
S
-
-
-
-
D9
B1
-
-
151
E12
PH13
I/O
FT
-
TIM8_CH1N, CAN1_TX,
FMC_D21, LCD_G2,
EVENTOUT
-
C13
D3
-
-
152
E13
PH14
I/O
FT
-
TIM8_CH2N, FMC_D22,
DCMI_D4, LCD_G3,
EVENTOUT
-
C12
E4
-
-
153
D13
PH15
I/O
FT
-
TIM8_CH3N, FMC_D23,
DCMI_D11, LCD_G4,
EVENTOUT
-
-
TIM5_CH4,
SPI2_NSS/I2S2_WS(6),
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
-
SPI2_SCK/I2S2_CK(6),
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
-
TIM8_CH4, SPI2_MISO,
I2S2ext_SD, FMC_D26,
DCMI_D9, LCD_G7,
EVENTOUT
-
-
-
B13
C11
B12
E5
C3
A1
B10
B2
-
-
62/208
E14
132 154
D14 133 155
-
NC
(7)
156
C13 134 157
D9
135
-
E14
D14
C14
PI0
I/O
PI1
I/O
PI2
I/O
FT
FT
FT
C13
PI3
I/O
FT
-
TIM8_ETR,
SPI2_MOSI/I2S2_SD,
FMC_D27, DCMI_D10,
EVENTOUT
F9
VSS
S
-
-
-
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
Table 10. STM32F469xx pin and ball definitions (continued)
WLCSP168
UFBGA176
LQFP176
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Alternate functions
-
B5
C9
136 158
E10
VDD
S
-
-
-
-
A10
D4
A14
137 159
A14
PA14(JTCKSWCLK)
I/O
FT
-
JTCK-SWCLK,
EVENTOUT
-
-
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
EVENTOUT
-
-
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
SDIO_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
-
I2S3ext_SD, SPI3_MISO,
USART3_RX, UART4_RX,
QUADSPI_BK2_NCS,
SDIO_D3, DCMI_D4,
EVENTOUT
-
-
B11
C10
B9
A2
D5
B3
A13
B14
B13
LQFP208
UFBGA169
Pin Number
138 160
139 161
140 162
A13
B14
B13
PA15(JTDI)
PC10
PC11
I/O
I/O
I/O
FT
FT
FT
Additional
functions
A9
C4
A12
141 163
A12
PC12
I/O
FT
-
TRACED3,
SPI3_MOSI/I2S3_SD,
USART3_CK, UART5_TX,
SDIO_CK, DCMI_D9,
EVENTOUT
C9
E6
B12
142 164
B12
PD0
I/O
FT
-
CAN1_RX, FMC_D2,
EVENTOUT
-
C7
A3
C12 143 165
C12
PD1
I/O
FT
-
CAN1_TX, FMC_D3,
EVENTOUT
-
B8
C5
D12 144 166
D12
PD2
I/O
FT
-
TRACED2, TIM3_ETR,
UART5_RX, SDIO_CMD,
DCMI_D11, EVENTOUT
-
-
C8
D6
D11
145 167
C11
PD3
I/O
FT
-
SPI2_SCK/I2S2_CK,
USART2_CTS,
FMC_CLK, DCMI_D5,
LCD_G7, EVENTOUT
C6
B4
D10 146 168
D11
PD4
I/O
FT
-
USART2_RTS,
FMC_NOE, EVENTOUT
-
B7
C6
C11
147 169
C10
PD5
I/O
FT
-
USART2_TX, FMC_NWE,
EVENTOUT
-
F8
A4
D8
148 170
F8
VSS
S
-
-
-
-
F7
-
C8
149 171
E9
VDD
S
-
-
-
-
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79
Pinouts and pin description
STM32F469xx
D7
E7
B11
150 172
B11
PD6
I/O
FT
-
SPI3_MOSI/I2S3_SD,
SAI1_SD_A,
USART2_RX,
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT
A8
A5
A11
151 173
A11
PD7
I/O
FT
-
USART2_CK, FMC_NE1,
EVENTOUT
-
-
-
-
-
174
B10
PJ12
I/O
FT
-
LCD_G3, LCD_B0,
EVENTOUT
-
-
-
-
-
175
B9
PJ13
I/O
FT
-
LCD_G4, LCD_B1,
EVENTOUT
-
-
-
-
-
176
C9
PJ14
I/O
FT
-
LCD_B2, EVENTOUT
-
-
-
-
-
177
D10
PJ15
I/O
FT
-
LCD_B3, EVENTOUT
-
-
LQFP208
Alternate functions
LQFP176
Notes
Pin name
(function after
reset)(1)
Pin types
TFBGA216
UFBGA176
WLCSP168
UFBGA169
Pin Number
I/O structures
Table 10. STM32F469xx pin and ball definitions (continued)
Additional
functions
-
E6
D7
C10 152 178
D9
PG9
I/O
FT
-
USART6_RX,
QUADSPI_BK2_IO2,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
E7
C7
B10
153 179
C8
PG10
I/O
FT
-
LCD_G3, FMC_NE3,
DCMI_D2, LCD_B2,
EVENTOUT
-
B6
B6
B9
154 180
B8
PG11
I/O
FT
-
ETH_MII_TX_EN/ETH_R
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
-
-
SPI6_MISO,
USART6_RTS, LCD_B4,
FMC_NE4, LCD_B1,
EVENTOUT
-
-
TRACED0, SPI6_SCK,
USART6_CTS,
ETH_MII_TXD0/ETH_RMI
I_TXD0, FMC_A24,
LCD_R0, EVENTOUT
-
-
A7
A6
A6
E8
B8
A8
155 181
156 182
C7
B3
PG12
PG13
I/O
I/O
FT
FT
-
-
A7
157 183
A4
PG14
I/O
FT
-
TRACED1, SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RMI
I_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
B7
D7
158 184
F7
VSS
S
-
-
-
-
-
A7
C7
159 185
E8
VDD
S
-
-
-
-
64/208
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
Table 10. STM32F469xx pin and ball definitions (continued)
UFBGA169
WLCSP168
UFBGA176
LQFP176
LQFP208
TFBGA216
Pin name
(function after
reset)(1)
Pin types
I/O structures
Notes
Pin Number
Alternate functions
-
-
-
-
186
D8
PK3
I/O
FT
-
LCD_B4, EVENTOUT
-
-
-
-
-
187
D7
PK4
I/O
FT
-
LCD_B5, EVENTOUT
-
-
-
-
-
188
C6
PK5
I/O
FT
-
LCD_B6, EVENTOUT
-
-
-
-
-
189
C5
PK6
I/O
FT
-
LCD_B7, EVENTOUT
-
-
-
-
-
190
C4
PK7
I/O
FT
-
LCD_DE, EVENTOUT
-
F6
D8
B7
160 191
B7
PG15
I/O
FT
-
USART6_CTS,
FMC_SDNCAS,
DCMI_D13, EVENTOUT
-
FT
-
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
SPI3_SCK/I2S3_CK,
EVENTOUT
-
FT
-
NJTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
I2S3ext_SD, EVENTOUT
-
-
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, LCD_G7,
EVENTOUT
-
-
TIM4_CH1, I2C1_SCL,
USART1_TX, CAN2_TX,
QUADSPI_BK1_NCS,
FMC_SDNE1, DCMI_D5,
EVENTOUT
-
-
B5
A8
A10
161 192
PB3(JTDO/TRA
A10
I/O
CESWO)
D6
C8
A9
162 193
A9
D5
C5
B8
G8
A6
B6
163 194
164 195
A8
B6
PB4(NJTRST)
PB5
PB6
I/O
I/O
I/O
FT
FT
Additional
functions
B4
A9
B5
165 196
B5
PB7
I/O
FT
-
TIM4_CH2, I2C1_SDA,
USART1_RX, FMC_NL,
DCMI_VSYNC,
EVENTOUT
A5
F8
D6
166 197
E6
BOOT0
I
B
-
-
VPP
-
TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
ETH_MII_TXD3,
SDIO_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
D4
B9
A5
167 198
A7
PB8
I/O
FT
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79
Pinouts and pin description
STM32F469xx
C4
E9
B4
168 199
B4
PB9
I/O
FT
-
TIM4_CH4, TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
CAN1_TX, SDIO_D5,
DCMI_D7, LCD_B7,
EVENTOUT
A4
A10
A4
169 200
A6
PE0
I/O
FT
-
TIM4_ETR, UART8_Rx,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
A3
C9
A3
170 201
A5
PE1
I/O
FT
-
UART8_Tx, FMC_NBL1,
DCMI_D3, EVENTOUT
-
E3
B10
D5
202
F6
VSS
S
-
-
-
-
C3
D9
C6
171 203
E5
PDR_ON
S
-
-
-
-
D3
A11
C5
172 204
E7
VDD
S
-
-
-
-
B3
D10
D4
173 205
C3
PI4
I/O
FT
-
TIM8_BKIN, FMC_NBL2,
DCMI_D5, LCD_B4,
EVENTOUT
-
A2
C10
C4
174 206
D3
PI5
I/O
FT
-
TIM8_CH1, FMC_NBL3,
DCMI_VSYNC, LCD_B5,
EVENTOUT
-
A1
B11
C3
175 207
D6
PI6
I/O
FT
-
TIM8_CH2, FMC_D28,
DCMI_D6, LCD_B6,
EVENTOUT
-
B1
A12
C2
176 208
D4
PI7
I/O
FT
-
TIM8_CH3, FMC_D29,
DCMI_D7, LCD_B7,
EVENTOUT
-
-
LQFP208
Alternate functions
LQFP176
Notes
Pin name
(function after
reset)(1)
Pin types
TFBGA216
UFBGA176
UFBGA169
WLCSP168
Pin Number
I/O structures
Table 10. STM32F469xx pin and ball definitions (continued)
Additional
functions
-
1. Function availability depends on the chosen device.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website:
www.st.com.
4.
FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
5. If the device is delivered in an WLCSP168, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the
BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low).
6. PI0 and PI1 cannot be used for I2S2 full-duplex mode.
7. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the
output data register to avoid extra current consumption in low power modes.
66/208
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
Table 11. FMC pin definition
Pin name
NOR/PSRAM/SR
AM
NOR/PSRAM
Mux
NAND16
SDRAM
PF0
A0
-
-
A0
PF1
A1
-
-
A1
PF2
A2
-
-
A2
PF3
A3
-
-
A3
PF4
A4
-
-
A4
PF5
A5
-
-
A5
PF12
A6
-
-
A6
PF13
A7
-
-
A7
PF14
A8
-
-
A8
PF15
A9
-
-
A9
PG0
A10
-
-
A10
PG1
A11
-
-
A11
PG2
A12
-
-
A12
PG3
A13
-
-
PG4
A14
-
-
BA0
PG5
A15
-
-
BA1
PD11
A16
A16
CLE
-
PD12
A17
A17
ALE
-
PD13
A18
A18
-
-
PE3
A19
A19
-
-
PE4
A20
A20
-
-
PE5
A21
A21
-
-
PE6
A22
A22
-
-
PE2
A23
A23
-
-
PG13
A24
A24
-
-
PG14
A25
A25
-
-
PD14
D0
DA0
D0
D0
PD15
D1
DA1
D1
D1
PD0
D2
DA2
D2
D2
PD1
D3
DA3
D3
D3
PE7
D4
DA4
D4
D4
PE8
D5
DA5
D5
D5
PE9
D6
DA6
D6
D6
PE10
D7
DA7
D7
D7
DocID028196 Rev 2
67/208
79
Pinouts and pin description
STM32F469xx
Table 11. FMC pin definition (continued)
68/208
Pin name
NOR/PSRAM/SR
AM
NOR/PSRAM
Mux
NAND16
SDRAM
PE11
D8
DA8
D8
D8
PE12
D9
DA9
D9
D9
PE13
D10
DA10
D10
D10
PE14
D11
DA11
D11
D11
PE15
D12
DA12
D12
D12
PD8
D13
DA13
D13
D13
PD9
D14
DA14
D14
D14
PD10
D15
DA15
D15
D15
PH8
D16
-
-
D16
PH9
D17
-
-
D17
PH10
D18
-
-
D18
PH11
D19
-
-
D19
PH12
D20
-
-
D20
PH13
D21
-
-
D21
PH14
D22
-
-
D22
PH15
D23
-
-
D23
PI0
D24
-
-
D24
PI1
D25
-
-
D25
PI2
D26
-
-
D26
PI3
D27
-
-
D27
PI6
D28
-
-
D28
PI7
D29
-
-
D29
PI9
D30
-
-
D30
PI10
D31
-
-
D31
PD7
NE1
NE1
-
-
PG9
NE2
NE2
NCE
-
PG10
NE3
NE3
-
-
PG11
-
-
-
-
PG12
NE4
-
-
-
PD3
CLK
CLK
-
-
PD4
NOE
NOE
NOE
-
PD5
NWE
NWE
NWE
-
PD6
NWAIT
NWAIT
NWAIT
-
PB7
NADV
NADV
-
-
DocID028196 Rev 2
STM32F469xx
Pinouts and pin description
Table 11. FMC pin definition (continued)
Pin name
NOR/PSRAM/SR
AM
NOR/PSRAM
Mux
NAND16
SDRAM
PF6
-
-
-
-
PF7
-
-
-
-
PF8
-
-
-
-
PF9
-
-
-
-
PF10
-
-
-
-
PG6
-
-
-
-
PG7
-
-
INT
-
PE0
NBL0
NBL0
-
-
PE1
NBL1
NBL1
-
NBL1
PI4
NBL2
-
-
NBL2
PI5
NBL3
-
-
NBL3
PG8
-
-
-
SDCLK
PC0
-
-
-
SDNWE
PF11
-
-
-
SDNRAS
PG15
-
-
-
SDNCAS
PH2
-
-
-
SDCKE0
PH3
-
-
-
SDNE0
PH6
-
-
-
SDNE1
PH7
-
-
-
SDCKE1
PH5
-
-
-
SDNWE
PC2
-
-
-
SDNE0
PC3
-
-
-
SDCKE0
PB5
-
-
-
SDCKE1
PB6
-
-
-
SDNE1
DocID028196 Rev 2
69/208
79
AF0
AF1
AF2
AF3
AF4
AF5
AF6
SYS
TIM1/2
TIM3/4/
5
PA0
-
TIM2_CH1/
TIM2_ETR
PA1
-
PA2
DocID028196 Rev 2
Port A
AF8
AF9
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
TIM5_CH1
TIM8_ETR
-
-
-
USART2_
CTS
UART4_
TX
-
TIM2_CH2
TIM5_CH2
-
-
-
-
USART2_
RTS
UART4_
RX
-
TIM2_CH3
TIM5_CH3
TIM9_CH1
-
-
-
USART2_T
X
PA3
-
TIM2_CH4
TIM5_CH4
TIM9_CH2
-
-
-
PA4
-
-
-
-
-
SPI1_NSS
PA5
-
TIM2_CH1/
TIM2_ETR
-
TIM8_CH1
N
-
PA6
-
TIM1_BKIN
TIM3_CH1
TIM8_BKI
N
PA7
-
TIM1_
CH1N
TIM3_CH2
PA8
MCO1
TIM1_CH1
PA9
-
PA10
AF10
AF12
AF13
AF14
AF15
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
-
ETH_MII_CRS
-
-
-
EVENT
OUT
QUADSPI_
BK1_IO3
-
ETH_MII_RX_
CLK/ETH_RMI
I_REF_CLK
-
-
LCD_R2
EVENT
OUT
-
-
-
ETH_MDIO
-
-
LCD_R1
EVENT
OUT
USART2_
RX
-
LCD_B2
OTG_HS
_ULPI_D0
ETH_MII_COL
-
-
LCD_B5
EVENT
OUT
SPI3_NSS/
I2S3_WS
USART2_
CK
-
-
-
-
OTG_HS_S
OF
DCMI_HS
YNC
LCD_VSY
NC
EVENT
OUT
SPI1_SCK
-
-
-
-
OTG_HS
_ULPI_C
K
-
-
-
LCD_R4
EVENT
OUT
-
SPI1_
MISO
-
-
-
TIM13_CH1
-
-
-
DCMI_PIX
CLK
LCD_G2
EVENT
OUT
TIM8_CH1
N
-
SPI1_
MOSI
-
-
-
TIM14_CH1
QUADSPI
_CLK
ETH_MII_RX_
DV/ETH_RMII
_CRS_DV
FMC_SDN
WE
-
-
EVENT
OUT
-
-
I2C3_SCL
-
-
USART1_
CK
-
-
OTG_FS_
SOF
-
-
-
LCD_R6
EVENT
OUT
TIM1_CH2
-
-
I2C3_SMBA
SPI2_SCK/I
2S2_CK
-
USART1_T
X
-
-
-
-
-
DCMI_D0
-
EVENT
OUT
-
TIM1_CH3
-
-
-
-
-
USART1_
RX
-
-
OTG_FS_
ID
-
-
DCMI_D1
-
EVENT
OUT
PA11
-
TIM1_CH4
-
-
-
-
-
USART1_
CTS
-
CAN1_RX
OTG_FS_
DM
-
-
-
LCD_R4
EVENT
OUT
PA12
-
TIM1_ETR
-
-
-
-
-
USART1_
RTS
-
CAN1_TX
OTG_FS_
DP
-
-
-
LCD_R5
EVENT
OUT
PA13
JTMSSWDIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA14
JTCKSWCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PA15
JTDI
TIM2_CH1/
TIM2_ETR
-
-
-
SPI1_NSS
SPI3_NSS/
I2S3_WS
-
-
-
-
-
-
-
-
EVENT
‘OUT
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
STM32F469xx
AF11
Port
AF7
Pinouts and pin description
70/208
Table 12. Alternate function
AF0
AF1
AF2
AF3
AF5
AF6
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
PB0
-
TIM1_CH2N
TIM3_CH3
TIM8_CH2
N
-
-
-
-
-
LCD_R3
OTG_HS
_ULPI_D1
ETH_MII_
RXD2
-
-
LCD_G1
EVENT
OUT
PB1
-
TIM1_CH3N
TIM3_CH4
TIM8_CH3
N
-
-
-
-
-
LCD_R6
OTG_HS
_ULPI_D2
ETH_MII_
RXD3
-
-
LCD_G0
EVENT
OUT
PB2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PB3
JTDO/T
RACES
WO
TIM2_CH2
-
-
SPI1_SCK
SPI3_SCK/
I2S3_CK
-
-
-
-
-
-
-
-
EVENT
OUT
PB4
NJTRST
-
TIM3_CH1
-
-
SPI1_MISO
SPI3_MIS
O
I2S3ext_S
D
-
-
-
-
-
-
-
EVENT
OUT
PB5
-
-
TIM3_CH2
-
I2C1_SMBA
SPI1_MOSI
SPI3_MOS
I/I2S3_SD
-
CAN2_RX
OTG_HS
_ULPI_D7
ETH_PPS
OUT
FMC_
SDCKE1
DCMI_D10
LCD_G7
EVENT
OUT
PB6
-
-
TIM4_CH1
-
I2C1_SCL
-
-
USART1_T
X
-
CAN2_TX
QUADSPI
_BK1_NC
S
-
FMC_
SDNE1
DCMI_D5
EVENT
OUT
PB7
-
-
TIM4_CH2
-
I2C1_SDA
-
-
USART1_
RX
-
-
-
-
FMC_NL
DCMI_VS
YNC
EVENT
OUT
PB8
-
-
TIM4_CH3
TIM10_CH
1
I2C1_SCL
-
-
-
-
CAN1_RX
-
ETH_MII_
TXD3
SDIO_D4
DCMI_D6
LCD_B6
EVENT
OUT
PB9
-
-
TIM4_CH4
TIM11_CH
1
I2C1_SDA
SPI2_NSS/I
2S2_WS
-
-
-
CAN1_TX
-
-
SDIO_D5
DCMI_D7
LCD_B7
EVENT
OUT
PB10
-
TIM2_CH3
-
-
I2C2_SCL
SPI2_SCK/I
2S2_CK
-
USART3_T
X
-
QUADSPI_
BK1_NCS
OTG_HS
_ULPI_D3
ETH_MII_RX_
ER
-
-
LCD_G4
EVENT
OUT
PB11
-
TIM2_CH4
-
-
I2C2_SDA
-
USART3_
RX
-
OTG_HS
_ULPI_D4
ETH_MII_TX_
EN/ETH_RMII
_TX_EN
-
DSIHOST_
TE
LCD_G5
EVENT
OUT
PB12
-
TIM1_BKIN
-
-
I2C2_SMBA
SPI2_NSS/I
2S2_WS
-
USART3_
CK
-
CAN2_RX
OTG_HS
_ULPI_D5
ETH_MII_TXD
0/ETH_RMII_T
XD0
OTG_HS_
ID
-
-
EVENT
OUT
PB13
-
TIM1_CH1N
-
-
-
SPI2_SCK/I
2S2_CK
-
USART3_
CTS
-
CAN2_TX
OTG_HS
_ULPI_D6
ETH_MII_TXD
1/ETH_RMII_T
XD1
-
-
-
EVENT
OUT
PB14
-
TIM1_CH2N
-
TIM8_CH2
N
-
SPI2_MISO
I2S2ext_S
D
USART3_
RTS
-
TIM12_CH1
-
-
OTG_HS_
‘DM
-
-
EVENT
OUT
PB15
RTC_RE
FIN
TIM1_CH3N
-
TIM8_CH3
N
-
SPI2_MOSI
/I2S2_SD
-
-
-
TIM12_CH2
-
-
OTG_HS_
DP
-
-
EVENT
‘OUT
Port
DocID028196 Rev 2
Port B
AF7
AF8
AF9
AF10
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
STM32F469xx
AF4
Pinouts and pin description
71/208
Table 12. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
SYS
TIM1/2
TIM3/4/
5
PC0
-
-
PC1
TRACED
0
PC2
AF12
AF13
AF14
AF15
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
-
-
-
-
-
-
-
-
-
FMC_SDN
WE
-
LCD_R5
EVENT
OUT
-
-
-
-
SPI2_MOSI
/I2S2_SD
SAI1_SD_
A
-
-
-
ETH_MDC
-
-
-
EVENT
OUT
-
-
-
-
-
SPI2_MISO
I2S2ext_S
D
-
-
-
OTG_HS
_ULPI_DI
R
ETH_MII_TXD
2
FMC_SDN
E0
-
-
EVENT
OUT
PC3
-
-
-
-
-
SPI2_MOSI
/I2S2_SD
-
-
-
-
OTG_HS
_ULPI_N
XT
ETH_MII_TX_
CLK
FMC_SDC
KE0
-
-
EVENT
OUT
PC4
-
-
-
-
-
-
-
-
-
-
-
ETH_MII_RXD
0/ETH_RMII_R
XD0
FMC_SDN
E0
-
-
EVENT
OUT
PC5
-
-
-
-
-
-
-
-
-
-
-
ETH_MII_RXD
1/ETH_RMII_R
XD1
FMC_SDC
KE0
-
-
EVENT
OUT
PC6
-
-
TIM3_CH1
TIM8_CH1
-
I2S2_MCK
-
-
USART6
_TX
-
-
-
SDIO_D6
DCMI_D0
LCD_HSY
NC
EVENT
OUT
PC7
-
-
TIM3_CH2
TIM8_CH2
-
-
I2S3_MCK
-
USART6
_RX
-
-
-
SDIO_D7
DCMI_D1
LCD_G6
EVENT
OUT
PC8
TRACED
1
-
TIM3_CH3
TIM8_CH3
-
-
-
-
USART6
_CK
-
-
-
SDIO_D0
DCMI_D2
-
EVENT
OUT
PC9
MCO2
-
TIM3_CH4
TIM8_CH4
I2C3_SDA
I2S_CKIN
-
-
-
QUADSPI_
BK1_IO0
-
-
SDIO_D1
DCMI_D3
-
EVENT
OUT
PC10
-
-
-
-
-
-
SPI3_SCK/
I2S3_CK
USART3_
TX
UART4_
TX
QUADSPI_
BK1_IO1
-
-
SDIO_D2
DCMI_D8
LCD_R2
EVENT
OUT
PC11
-
-
-
-
-
I2S3ext_SD
SPI3_MIS
O
USART3_
RX
UART4_
RX
QUADSPI_
BK2_NCS
-
-
SDIO_D3
DCMI_D4
-
EVENT
OUT
PC12
TRACED
3
-
-
-
-
-
SPI3_MOS
I/I2S3_SD
USART3_
CK
UART5_
TX
-
-
-
SDIO_CK
DCMI_D9
-
EVENT
OUT
PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVENT
‘OUT
DocID028196 Rev 2
Port C
AF8
AF9
AF10
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
OTG_HS
_ULPI_ST
P
STM32F469xx
AF11
Port
AF7
Pinouts and pin description
72/208
Table 12. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
PD0
-
-
-
-
-
-
-
-
-
CAN1_RX
-
-
FMC_D2
-
-
EVENT
OUT
PD1
-
-
-
-
-
-
-
-
-
CAN1_TX
-
-
FMC_D3
-
-
EVENT
OUT
PD2
TRACED
2
-
TIM3_ETR
-
-
-
-
-
UART5_
RX
-
-
-
SDIO_CMD
DCMI_D11
-
EVENT
OUT
PD3
-
-
-
-
-
SPI2_SCK/I
2S2_CK
-
USART2_
CTS
-
-
-
-
FMC_CLK
DCMI_D5
LCD_G7
EVENT
OUT
PD4
-
-
-
-
-
-
-
USART2_
RTS
-
-
-
-
FMC_NOE
-
-
EVENT
OUT
PD5
-
-
-
-
-
-
-
USART2_T
X
-
-
-
-
FMC_NWE
-
-
EVENT
OUT
PD6
-
-
-
-
-
SPI3_MOSI
/I2S3_SD
SAI1_SD_
A
USART2_
RX
-
-
-
-
FMC_NWAI
T
DCMI_D10
LCD_B2
EVENT
OUT
PD7
-
-
-
-
-
-
-
USART2_
CK
-
-
-
-
FMC_NE1
-
-
EVENT
OUT
PD8
-
-
-
-
-
-
-
USART3_T
X
-
-
-
-
FMC_D13
-
-
EVENT
OUT
PD9
-
-
-
-
-
-
-
USART3_
RX
-
-
-
-
FMC_D14
-
-
EVENT
OUT
PD10
-
-
-
-
-
-
-
USART3_
CK
-
-
-
-
FMC_D15
-
LCD_B3
EVENT
OUT
PD11
-
-
-
-
-
-
-
USART3_
CTS
-
QUADSPI_
BK1_IO0
-
-
FMC_A16/F
MC_CLE
-
-
EVENT
OUT
PD12
-
-
TIM4_CH1
-
-
-
-
USART3_
RTS
-
QUADSPI_
BK1_IO1
-
-
FMC_A17/F
MC_ALE
-
-
EVENT
OUT
PD13
-
-
TIM4_CH2
-
-
-
-
-
-
QUADSPI_
BK1_IO3
-
-
FMC_A18
-
-
EVENT
OUT
PD14
-
-
TIM4_CH3
-
-
-
-
-
-
-
-
-
FMC_D0
-
-
EVENT
OUT
PD15
-
-
TIM4_CH4
-
-
-
-
-
-
-
-
-
FMC_D1
-
-
EVENT
‘OUT
Port
AF7
AF8
AF9
AF10
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
Pinouts and pin description
73/208
Table 12. Alternate function (continued)
DocID028196 Rev 2
Port D
STM32F469xx
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
PE0
-
-
TIM4_ETR
-
-
-
-
-
UART8_
Rx
-
-
-
FMC_NBL0
DCMI_D2
-
EVENT
OUT
PE1
-
-
-
-
-
-
-
-
UART8_
Tx
-
-
-
FMC_NBL1
DCMI_D3
-
EVENT
OUT
PE2
TRACEC
LK
-
-
-
-
SPI4_SCK
SAI1_MCL
K_A
-
-
QUADSPI_
BK1_IO2
-
ETH_MII_TXD
3
FMC_A23
-
-
EVENT
OUT
PE3
TRACED
0
-
-
-
-
-
SAI1_SD_
B
-
-
-
-
-
FMC_A19
-
-
EVENT
OUT
PE4
TRACED
1
-
-
-
-
SPI4_NSS
SAI1_FS_
A
-
-
-
-
-
FMC_A20
DCMI_D4
LCD_B0
EVENT
OUT
PE5
TRACED
2
-
-
TIM9_CH1
-
SPI4_MISO
SAI1_SCK
_A
-
-
-
-
-
FMC_A21
DCMI_D6
LCD_G0
EVENT
OUT
PE6
TRACED
3
-
-
TIM9_CH2
-
SPI4_MOSI
SAI1_SD_
A
-
-
-
-
-
FMC_A22
DCMI_D7
LCD_G1
EVENT
OUT
PE7
-
TIM1_ETR
-
-
-
-
-
-
UART7_
Rx
-
QUADSPI
_BK2_IO0
-
FMC_D4
-
-
EVENT
OUT
PE8
-
TIM1_CH1N
-
-
-
-
-
-
UART7_
Tx
-
QUADSPI
_BK2_IO1
-
FMC_D5
-
-
EVENT
OUT
PE9
-
TIM1_CH1
-
-
-
-
-
-
-
-
QUADSPI
_BK2_IO2
-
FMC_D6
-
-
EVENT
OUT
PE10
-
TIM1_CH2N
-
-
-
-
-
-
-
-
QUADSPI
_BK2_IO3
-
FMC_D7
-
-
EVENT
OUT
PE11
-
TIM1_CH2
-
-
-
SPI4_NSS
-
-
-
-
-
-
FMC_D8
-
LCD_G3
EVENT
OUT
PE12
-
TIM1_CH3N
-
-
-
SPI4_SCK
-
-
-
-
-
-
FMC_D9
-
LCD_B4
EVENT
OUT
PE13
-
TIM1_CH3
-
-
-
SPI4_MISO
-
-
-
-
-
-
FMC_D10
-
LCD_DE
EVENT
OUT
PE14
-
TIM1_CH4
-
-
-
SPI4_MOSI
-
-
-
-
-
-
FMC_D11
-
LCD_CLK
EVENT
OUT
PE15
-
TIM1_BKIN
-
-
-
-
-
-
-
-
-
-
FMC_D12
-
LCD_R7
EVENT
‘OUT
Port
AF7
AF8
AF9
AF10
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
Pinouts and pin description
74/208
Table 12. Alternate function (continued)
DocID028196 Rev 2
Port E
STM32F469xx
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
PF0
-
-
-
-
I2C2_SDA
-
-
-
-
-
-
-
FMC_A0
-
-
EVENT
OUT
PF1
-
-
-
-
I2C2_SCL
-
-
-
-
-
-
-
FMC_A1
-
-
EVENT
OUT
PF2
-
-
-
-
I2C2_SMBA
-
-
-
-
-
-
-
FMC_A2
-
-
EVENT
OUT
PF3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A3
-
-
EVENT
OUT
PF4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A4
-
-
EVENT
OUT
PF5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A5
-
-
EVENT
OUT
PF6
-
-
-
TIM10_CH
1
-
SPI5_NSS
SAI1_
SD_B
-
UART7_
Rx
QUADSPI_
BK1_IO3
-
-
-
-
-
EVENT
OUT
PF7
-
-
-
TIM11_CH
1
-
SPI5_SCK
SAI1_
MCLK_B
-
UART7_
Tx
QUADSPI_
BK1_IO2
-
-
-
-
-
EVENT
OUT
PF8
-
-
-
-
-
SPI5_MISO
SAI1_
SCK_B
-
-
TIM13_CH1
QUADSPI
_BK1_IO0
-
-
-
-
EVENT
OUT
PF9
-
-
-
-
-
SPI5_MOSI
SAI1_
FS_B
-
-
TIM14_CH1
QUADSPI
_BK1_IO1
-
-
-
-
EVENT
OUT
PF10
-
-
-
-
-
-
-
-
-
QUADSPI_
CLK
-
-
DCMI_D11
LCD_DE
EVENT
OUT
PF11
-
-
-
-
-
SPI5_MOSI
-
-
-
-
-
-
FMC_SDN
RAS
DCMI_D12
-
EVENT
OUT
PF12
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A6
-
-
EVENT
OUT
PF13
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A7
-
-
EVENT
OUT
PF14
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A8
-
-
EVENT
OUT
PF15
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A9
-
-
EVENT
‘OUT
Port
AF7
AF8
AF9
AF10
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
Pinouts and pin description
75/208
Table 12. Alternate function (continued)
DocID028196 Rev 2
Port F
STM32F469xx
AF0
AF1
AF2
AF3
AF5
AF6
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
PG0
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A10
-
-
EVENT
OUT
PG1
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A11
-
-
EVENT
OUT
PG2
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A12
-
-
EVENT
OUT
PG3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A13
-
-
EVENT
OUT
PG4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A14/F
MC_BA0
-
-
EVENT
OUT
PG5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A15/F
MC_BA1
-
-
EVENT
OUT
PG6
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_D12
LCD_R7
EVENT
OUT
PG7
-
-
-
-
-
USART6
_CK
-
-
-
FMC_INT
DCMI_D13
LCD_CLK
EVENT
OUT
PG8
-
-
-
-
-
SPI6_NSS
-
-
USART6
_RTS
-
-
ETH_PPS_OU
T
FMC_SDCL
K
LCD_G7
EVENT
OUT
PG9
-
-
-
-
-
-
-
-
USART6
_RX
QUADSPI_
BK2_IO2
-
-
FMC_NE2/
FMC_NCE
DCMI_VS
YNC
PG1
0
-
-
-
-
-
-
-
-
LCD_G3
-
-
FMC_NE3
DCMI_D2
LCD_B2
EVENT
OUT
PG11
-
-
-
-
-
-
-
-
-
-
-
ETH_MII_TX_
EN/ETH_RMII
_TX_EN
-
DCMI_D3
LCD_B3
EVENT
OUT
PG1
2
-
-
-
-
-
SPI6_MISO
-
-
USART6
_RTS
LCD_B4
-
-
FMC_NE4
-
LCD_B1
EVENT
OUT
PG1
3
TRACED
0
-
-
-
-
SPI6_SCK
-
-
USART6
_CTS
-
-
ETH_MII_TXD
0/ETH_RMII_T
XD0
FMC_A24
-
LCD_R0
EVENT
OUT
PG1
4
TRACED
1
-
-
-
-
SPI6_MOSI
-
-
USART6
_TX
QUADSPI_
BK2_IO3
-
-
FMC_A25
-
LCD_B0
EVENT
OUT
PG1
5
-
-
-
-
-
-
-
-
USART6
_CTS
-
-
-
-
DCMI_D13
-
EVENT
‘OUT
Port
DocID028196 Rev 2
Port
G
AF7
AF8
AF9
AF10
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
SAI1_MCL
K_A
EVENT
OUT
STM32F469xx
AF4
Pinouts and pin description
76/208
Table 12. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
SYS
TIM1/2
TIM3/4/
5
PH0
-
-
PH1
-
PH2
AF8
AF9
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PH3
-
-
-
-
-
-
-
PH4
-
-
-
-
I2C2_SCL
-
PH5
-
-
-
-
I2C2_SDA
PH6
-
-
-
-
PH7
-
-
-
PH8
-
-
PH9
-
PH10
AF10
AF12
AF13
AF14
AF15
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
QUADSPI_
BK2_IO0
-
ETH_MII_CRS
FMC_SDC
KE0
-
LCD_R0
EVENT
OUT
-
-
QUADSPI_
BK2_IO1
-
ETH_MII_COL
FMC_SDN
E0
-
LCD_R1
EVENT
OUT
-
-
-
LCD_G5
OTG_HS
_ULPI_N
XT
-
-
-
LCD_G4
EVENT
OUT
SPI5_NSS
-
-
-
-
-
-
FMC_SDN
WE
-
-
EVENT
OUT
I2C2_SMBA
SPI5_SCK
-
-
-
TIM12_CH1
-
ETH_MII_RXD
2
FMC_SDN
E1
-
-
EVENT
OUT
-
I2C3_SCL
SPI5_MISO
-
-
-
-
-
ETH_MII_RXD
3
FMC_SDC
KE1
DCMI_D9
-
EVENT
OUT
-
-
I2C3_SDA
-
-
-
-
-
-
-
FMC_D16
DCMI_HS
YNC
LCD_R2
EVENT
OUT
-
-
-
I2C3_SMBA
-
-
-
-
TIM12_CH2
-
-
FMC_D17
DCMI_D0
LCD_R3
EVENT
OUT
-
-
TIM5_CH1
-
-
-
-
-
-
-
-
-
FMC_D18
DCMI_D1
LCD_R4
EVENT
OUT
PH11
-
-
TIM5_CH2
-
-
-
-
-
-
-
-
-
FMC_D19
DCMI_D2
LCD_R5
EVENT
OUT
PH12
-
-
TIM5_CH3
-
-
-
-
-
-
-
-
-
FMC_D20
DCMI_D3
LCD_R6
EVENT
OUT
PH13
-
-
-
TIM8_CH1
N
-
-
-
-
-
CAN1_TX
-
-
FMC_D21
-
LCD_G2
EVENT
OUT
PH14
-
-
-
TIM8_CH2
N
-
-
-
-
-
-
-
-
FMC_D22
DCMI_D4
LCD_G3
EVENT
OUT
PH15
-
-
-
TIM8_CH3
N
-
-
-
-
-
-
-
-
FMC_D23
DCMI_D11
LCD_G4
EVENT
‘OUT
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
DocID028196 Rev 2
Port H
EVENT
OUT
STM32F469xx
AF11
Port
AF7
Pinouts and pin description
77/208
Table 12. Alternate function (continued)
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
PI0
-
-
TIM5_CH4
-
-
SPI2_NSS/I
2S2_WS
-
-
-
-
-
-
FMC_D24
DCMI_D13
LCD_G5
EVENT
OUT
PI1
-
-
-
-
-
SPI2_SCK/I
2S2_CK
-
-
-
-
-
-
FMC_D25
DCMI_D8
LCD_G6
EVENT
OUT
PI2
-
-
-
TIM8_CH4
-
SPI2_MISO
I2S2ext_S
D
-
-
-
-
-
FMC_D26
DCMI_D9
LCD_G7
EVENT
OUT
PI3
-
-
-
TIM8_ETR
-
SPI2_MOSI
/I2S2_SD
-
-
-
-
-
-
FMC_D27
DCMI_D10
PI4
-
-
-
TIM8_BKI
N
-
-
-
-
-
-
-
-
FMC_NBL2
DCMI_D5
LCD_B4
EVENT
OUT
PI5
-
-
-
TIM8_CH1
-
-
-
-
-
-
-
-
FMC_NBL3
DCMI_VS
YNC
LCD_B5
EVENT
OUT
PI6
-
-
-
TIM8_CH2
-
-
-
-
-
-
-
-
FMC_D28
DCMI_D6
LCD_B6
EVENT
OUT
PI7
-
-
-
TIM8_CH3
-
-
-
-
-
-
-
-
FMC_D29
DCMI_D7
LCD_B7
EVENT
OUT
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PI9
-
-
-
-
-
-
-
-
-
CAN1_RX
-
-
FMC_D30
-
LCD_VSY
NC
EVENT
OUT
PI10
-
-
-
-
-
-
-
-
-
-
-
ETH_MII_RX_
ER
FMC_D31
-
LCD_HSY
NC
EVENT
OUT
PI11
-
-
-
-
-
-
-
-
-
LCD_G6
OTG_HS
_ULPI
_DIR
-
-
-
-
EVENT
OUT
PI12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_HSY
NC
EVENT
OUT
PI13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_VSY
NC
EVENT
OUT
PI14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_CLK
EVENT
OUT
PI15
-
-
-
-
-
-
-
-
-
LCD_G2
-
-
-
-
LCD_R0
EVENT
‘OUT
Port
AF7
AF8
AF9
AF10
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
Pinouts and pin description
78/208
Table 12. Alternate function (continued)
EVENT
OUT
DocID028196 Rev 2
Port I
EVENT
OUT
STM32F469xx
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF11
AF12
AF13
AF14
AF15
SYS
TIM1/2
TIM3/4/
5
TIM8/9/
10/11
I2C1/2/3
SPI1/2/3
/4/5/6
SPI2/3/
SAI1
ETH
FMC/SD
IO/OTG2
_FS
DCMI/
DSI
HOST
LCD
SYS
PJ0
-
-
-
-
-
-
-
-
-
LCD_R7
-
-
-
-
LCD_R1
EVENT
OUT
PJ1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R2
EVENT
OUT
PJ2
-
-
-
-
-
-
-
-
-
-
-
-
-
DSIHOST
_TE
LCD_R3
EVENT
OUT
PJ3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R4
EVENT
OUT
PJ4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R5
EVENT
OUT
PJ5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R6
EVENT
OUT
PJ12
-
-
-
-
-
-
-
-
-
LCD_G3
-
-
-
-
LCD_B0
EVENT
OUT
PJ13
-
-
-
-
-
-
-
-
-
LCD_G4
-
-
-
-
LCD_B1
EVENT
OUT
PJ14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B2
EVENT
OUT
PJ15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
EVENT
OUT
PK3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B4
EVENT
OUT
PK4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B5
EVENT
OUT
PK5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B6
EVENT
OUT
PK6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B7
EVENT
OUT
PK7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_DE
EVENT
OUT
Port
AF7
AF8
AF9
AF10
USAR CAN1/2/ QUAD
SPI2/3/
T6/UA TIM12/1 SPI/OT
USART
RT4/5 3/14/QU G2_HS
1/2/3
ADSPI/L /OTG1
/7/8
_FS
CD
Pinouts and pin description
79/208
Table 12. Alternate function (continued)
DocID028196 Rev 2
Port J
Port K
STM32F469xx
Memory mapping
4
STM32F469xx
Memory mapping
The memory map is shown in Figure 19.
Figure 19. Memory map
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80/208
DocID028196 Rev 2
STM32F469xx
Memory mapping
Table 13. STM32F469xx register boundary addresses(1)
Bus
Boundary address
-
0xE00F FFFF - 0xFFFF FFFF
Reserved
0xE000 0000 - 0xE00F FFFF
Cortex®-M4 internal peripherals
0xD000 0000 - 0xDFFF FFFF
FMC bank 6
0xC000 0000 - 0xCFFF FFFF
FMC bank 5
®
Cortex -M4
AHB3
-
AHB2
Peripheral
0xA000 1000 - 0xA0001FFF
Quad-SPI control register
0xA000 2000 - 0xBFFF FFFF
Reserved
0xA000 0000- 0xA000 0FFF
FMC control register
0x9000 0000 - 0x9FFF FFFF
Quad-SPI bank
0x8000 0000 - 0x8FFF FFFF
FMC bank 3
0x7000 0000 - 0x7FFF FFFF
FMC bank 2 (reserved)
0x6000 0000 - 0x6FFF FFFF
FMC bank 1
0x5006 0C00- 0x5FFF FFFF
Reserved
0x5006 0800 - 0x5006 0BFF
RNG
0x5005 0400 - 0x5006 07FF
Reserved
0x5005 0000 - 0x5005 03FF
DCMI
0x5004 0000- 0x5004 FFFF
Reserved
0x5000 0000 - 0x5003 FFFF
USB OTG FS
DocID028196 Rev 2
81/208
84
Memory mapping
STM32F469xx
Table 13. STM32F469xx register boundary addresses(1) (continued)
Bus
Boundary address
Peripheral
-
0x4008 0000- 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
USB OTG HS
0x4002 BC00- 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Chrom (DMA2D)
0x4002 9400 - 0x4002 AFFF
Reserved
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF
ETHERNET MAC
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
AHB1
82/208
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
DMA2
0x4002 6000 - 0x4002 63FF
DMA1
0x4002 5000 - 0x4002 5FFF
Reserved
0x4002 4000 - 0x4002 4FFF
BKPSRAM
0x4002 3C00 - 0x4002 3FFF
Flash interface register
0x4002 3800 - 0x4002 3BFF
RCC
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
GPIOK
0x4002 2400 - 0x4002 27FF
GPIOJ
0x4002 2000 - 0x4002 23FF
GPIOI
0x4002 1C00 - 0x4002 1FFF
GPIOH
0x4002 1800 - 0x4002 1BFF
GPIOG
0x4002 1400 - 0x4002 17FF
GPIOF
0x4002 1000 - 0x4002 13FF
GPIOE
0x4002 0C00 - 0x4002 0FFF
GPIOD
0x4002 0800 - 0x4002 0BFF
GPIOC
0x4002 0400 - 0x4002 07FF
GPIOB
0x4002 0000 - 0x4002 03FF
GPIOA
DocID028196 Rev 2
STM32F469xx
Memory mapping
Table 13. STM32F469xx register boundary addresses(1) (continued)
Bus
APB2
Boundary address
Peripheral
0x4001 7400 - 0x4001 FFFF
Reserved
0x4001 6C00 - 0x4001 73FF
DSI Host
0x4001 6800 - 0x4001 6BFF
LCD-TFT
0x4001 5C00 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
SAI1
0x4001 5400 - 0x4001 57FF
SPI6
0x4001 5000 - 0x4001 53FF
SPI5
0x4001 4C00 - 0x4001 4FFF
Reserved
0x4001 4800 - 0x4001 4BFF
TIM11
0x4001 4400 - 0x4001 47FF
TIM10
0x4001 4000 - 0x4001 43FF
TIM9
0x4001 3C00 - 0x4001 3FFF
EXTI
0x4001 3800 - 0x4001 3BFF
SYSCFG
0x4001 3400 - 0x4001 37FF
SPI4
0x4001 3000 - 0x4001 33FF
SPI1
0x4001 2C00 - 0x4001 2FFF
SDIO
0x4001 2400 - 0x4001 2BFF
Reserved
0x4001 2000 - 0x4001 23FF
ADC1 - ADC2 - ADC3
0x4001 1800 - 0x4001 1FFF
Reserved
0x4001 1400 - 0x4001 17FF
USART6
0x4001 1000 - 0x4001 13FF
USART1
0x4001 0800 - 0x4001 0FFF
Reserved
0x4001 0400 - 0x4001 07FF
TIM8
0x4001 0000 - 0x4001 03FF
TIM1
DocID028196 Rev 2
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84
Memory mapping
STM32F469xx
Table 13. STM32F469xx register boundary addresses(1) (continued)
Bus
Boundary address
-
0x4000 8000- 0x4000 FFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
UART8
0x4000 7800 - 0x4000 7BFF
UART7
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PWR
0x4000 6C00 - 0x4000 6FFF
Reserved
0x4000 6800 - 0x4000 6BFF
CAN2
0x4000 6400 - 0x4000 67FF
CAN1
0x4000 6000 - 0x4000 63FF
Reserved
0x4000 5C00 - 0x4000 5FFF
I2C3
0x4000 5800 - 0x4000 5BFF
I2C2
0x4000 5400 - 0x4000 57FF
I2C1
0x4000 5000 - 0x4000 53FF
UART5
0x4000 4C00 - 0x4000 4FFF
UART4
0x4000 4800 - 0x4000 4BFF
USART3
0x4000 4400 - 0x4000 47FF
USART2
0x4000 4000 - 0x4000 43FF
I2S3ext
0x4000 3C00 - 0x4000 3FFF
SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF
SPI2 / I2S2
0x4000 3400 - 0x4000 37FF
I2S2ext
0x4000 3000 - 0x4000 33FF
IWDG
0x4000 2C00 - 0x4000 2FFF
WWDG
0x4000 2800 - 0x4000 2BFF
RTC & BKP Registers
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIM14
0x4000 1C00 - 0x4000 1FFF
TIM13
0x4000 1800 - 0x4000 1BFF
TIM12
0x4000 1400 - 0x4000 17FF
TIM7
0x4000 1000 - 0x4000 13FF
TIM6
0x4000 0C00 - 0x4000 0FFF
TIM5
0x4000 0800 - 0x4000 0BFF
TIM4
0x4000 0400 - 0x4000 07FF
TIM3
0x4000 0000 - 0x4000 03FF
TIM2
APB1
1. The reserved boundary address are shown in grayed cells
84/208
DocID028196 Rev 2
Peripheral
STM32F469xx
5
5.1
Electrical characteristics
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 20.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 21.
Figure 20. Pin loading conditions
Figure 21. Pin input voltage
-#5PIN
-#5PIN
#P&
6).
-36
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-36
85/208
187
Electrical characteristics
5.1.6
STM32F469xx
Power supply scheme
Figure 22. Power supply scheme
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1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.19 and Section 2.20.
2. The two 2.2 µF ceramic capacitors on VCAP_1 and VCAP_2 should be replaced by two 100 nF decoupling
capacitors when the voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4. VDDA and VSSA must be connected to VDD and VSS, respectively.
Caution:
86/208
Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
DocID028196 Rev 2
STM32F469xx
5.1.7
Electrical characteristics
Current consumption measurement
Figure 23. Current consumption measurement scheme
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5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14, Table 15, and Table 16
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Table 14. Voltage characteristics
Symbol
Min
Max
− 0.3
4.0
Input voltage on FT pins(2)
VSS − 0.3
VDD+4.0
Input voltage on TTa pins
VSS − 0.3
4.0
Input voltage on any other pin
VSS − 0.3
4.0
VSS
9.0
Variations between different VDD power pins
-
50
|VSSX −VSS|
Variations between all the different ground pins
-
50
VESD(HBM)
Electrostatic discharge voltage (human body model)
VDD–VSS
VIN
Ratings
External main supply voltage
(including VDDA, VDD, VDDUSB, VDDDSI and VBAT)(1)
Input voltage on BOOT pin
|ΔVDDx|
Unit
V
mV
see Section 5.3.18
1. All main power (VDD, VDDA, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
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187
Electrical characteristics
STM32F469xx
Table 15. Current characteristics
Symbol
Ratings
Max.
ΣIVDD
Total current into sum of all VDD_x power lines (source)(1)
Σ IVSS
(1)
290
− 290
Total current out of sum of all VSS_x ground lines (sink)
Σ IVDDUSB
Total current into VDDUSB power line (source)
25
IVDD
Maximum current into each VDD_x power line (source)(1)
IVSS
(1)
Maximum current out of each VSS_x ground line (sink)
100
− 100
Output current sunk by any I/O and control pin
IIO
ΣIIO
25
Output current sourced by any I/Os and control pin
− 25
Total output current sunk by sum of all I/O and control pins (2)
120
Total output current sunk by sum of all USB I/Os
25
Total output current sourced by sum of all I/Os and control
Injected current on FT pins
IINJ(PIN) (3)
pins(2)
ΣIINJ(PIN)
mA
− 120
(4)
− 5/+0
Injected current on NRST and BOOT0 pins (4)
Injected current on TTa pins(5)
(5)
Unit
Total injected current (sum of all I/O and control
±5
pins)(6)
±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.24.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
5. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 14 for the values of the maximum allowed input voltage.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 16. Thermal characteristics
Symbol
TSTG
TJ
88/208
Ratings
Storage temperature range
Maximum junction temperature
DocID028196 Rev 2
Value
Unit
− 65 to +150
°C
125
°C
STM32F469xx
Electrical characteristics
5.3
Operating conditions
5.3.1
General operating conditions
Table 17. General operating conditions
Symbol
fHCLK
Conditions(1)
Min
Typ
Max
Power Scale 3 (VOS[1:0] bits in PWR_CR
register = 0x01),
Regulator ON, over-drive OFF
0
-
120
-
144
-
168
-
168
-
180
Parameter
Internal AHB clock frequency
Power Scale 2 (VOS[1:0] bits
in PWR_CR register = 0x10),
Regulator ON
Power Scale 1 (VOS[1:0] bits
in PWR_CR register= 0x11),
Regulator ON
fPCLK1
Internal APB1 clock frequency
fPCLK2
Internal APB2 clock frequency
VDD
(3)(4)
VDDA
VDDUSB
VDDDSI
VBAT
Analog operating voltage
(ADC limited to 2.4 M samples)
Over-drive
ON
Over-drive
OFF
Over-drive
ON
0
0
-
42
Over-drive ON
0
-
45
Over-drive OFF
0
-
84
Over-drive ON
0
-
90
1.7(2)
-
3.6
1.7(2)
-
2.4
2.4
-
3.6
1.7
3.3
3.6
3.0
-
3.6
-
3.6
-
3.6
-
Must be the same potential as
MHz
0
Over-drive OFF
Standard operating voltage
Analog operating voltage
(ADC limited to 1.2 M samples)
Over-drive
OFF
Unit
VDD(5)
V
USB supply voltage
USB not used
(supply voltage for PA11, PA12,
USB used
PB14 and PB15 pins)
DSI system operating voltage
-
1.7(2)
Backup operating voltage
-
1.65
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187
Electrical characteristics
STM32F469xx
Table 17. General operating conditions (continued)
Symbol
Conditions(1)
Parameter
Power Scale 3 ((VOS[1:0] bits in
PWR_CR register = 0x01), 120 MHz
HCLK max frequency
Power Scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 144 MHz
Regulator ON: 1.2 V internal
HCLK max frequency with over-drive OFF
voltage on VCAP_1/VCAP_2 pins
or 168 MHz with over-drive ON
V12
VIN
PD
Typ
Max
1.08
1.14
1.20
1.20
1.26
1.32
1.26
1.32
1.40
Regulator OFF: 1.2 V external
voltage must be supplied from
external regulator on
VCAP_1/VCAP_2 pins(6)
Max frequency 120 MHz
1.10
1.14
1.20
Max frequency 144 MHz
1.20
1.26
1.32
Max frequency 168 MHz
1.26
1.32
1.38
Input voltage on RST and FT
pins(7)
2 V ≤VDD ≤3.6 V
− 0.3
-
5.5
VDD ≤2 V
− 0.3
-
5.2
Input voltage on TTa pins
-
− 0.3
-
VDDA
+0.3
Input voltage on BOOT0 pin
-
0
-
9
WLCSP168
-
-
645
UFBGA169
Power dissipation at TA = 85 °C LQFP176
for suffix 6 or TA = 105 °C for
UFBGA176
suffix 7(8)
-
-
385
-
-
526
-
-
513
LQFP208
-
-
1053
TFBGA216
-
-
690
− 40
-
85
Low power dissipation
− 40
-
105
Maximum power dissipation
− 40
-
105
− 40
-
125
6 suffix version
− 40
-
105
7 suffix version
− 40
-
125
TA
Ambient temperature for 7
suffix version
Junction temperature range
Maximum power dissipation
(9)
Low power
dissipation(9)
Unit
V
Power Scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 168 MHz
HCLK max frequency with over-drive OFF
or 180 MHz with over-drive ON
Ambient temperature for 6
suffix version
TJ
Min
V
mW
°C
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
3. When the ADC is used, refer to Table 77.
4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
5. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
6. The over-drive mode is not supported when the internal regulator is OFF.
7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
90/208
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Table 18. Limitations depending on the operating power supply range
Operating
power
supply range
VDD =
1.7 to 2.1 V(3)
VDD =
2.1 to 2.4 V
VDD =
2.4 to 2.7 V
VDD =
2.7 to 3.6 V(5)
ADC
operation
Maximum Flash
memory access
frequency with
no wait states
(fFlashmax)
Maximum HCLK
frequency
vs.
Flash memory wait
states (1)(2)
20 MHz(4)
168 MHz
with 8 wait states
and over-drive OFF
Conversion time
up to 1.2 Msps
22 MHz
180 MHz
with 8 wait states
and over-drive ON
24 MHz
180 MHz
with 7 wait states
and over-drive ON
30 MHz
180 MHz
with 5 wait states
and over-drive ON
Conversion time
up to 2.4 Msps
I/O operation
No I/O
compensation
I/O compensation
works
Possible Flash
memory
operations
8-bit erase
and program
operations only
16-bit erase
and program
operations
16-bit erase
and program
operations
32-bit erase
and program
operations
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
4. Prefetch is not available.
5. When VDDUSB is connected to VDD, the voltage range for USB full speed PHYs can drop down to 2.7 V. However the
electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V.
5.3.2
VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP1/VCAP2 pins. CEXT is specified in Table 19.
Figure 24. External capacitor CEXT
&
(65
5/HDN
069
1. Legend: ESR is the equivalent series resistance.
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187
Electrical characteristics
STM32F469xx
Table 19. VCAP1/VCAP2 operating conditions(1)
Symbol
Parameter
Conditions
CEXT
Capacitance of external capacitor
2.2 µF
ESR
ESR of external capacitor
<2Ω
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
5.3.3
Operating conditions at power-up / power-down (regulator ON)
Subject to general operating conditions for TA.
Table 20. Operating conditions at power-up / power-down (regulator ON)
Symbol
tVDD
5.3.4
Parameter
Min
Max
VDD rise time rate
20
∞
VDD fall time rate
20
∞
Unit
µs/V
Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for TA.
Table 21. Operating conditions at power-up / power-down (regulator OFF)(1)
Symbol
tVDD
tVCAP
Parameter
Conditions
Min
Max
VDD rise time rate
Power-up
20
∞
VDD fall time rate
Power-down
20
∞
VCAP_1 and VCAP_2 rise time rate
Power-up
20
∞
VCAP_1 and VCAP_2 fall time rate
Power-down
20
∞
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
5.3.5
Reset and power control block characteristics
The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.
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Electrical characteristics
Table 22. Reset and power control block characteristics
Symbol
Conditions
Programmable voltage
detector level selection
VPVD
VPVDhyst
Parameter
(1)
Power-on/power-down
reset threshold
VPDRhyst(1)
PDR hysteresis
VBOR1
Brownout level 1 threshold
VBOR2
Brownout level 2 threshold
VBOR3
Brownout level 3 threshold
VBORhyst
Typ
Max
PLS[2:0]=000 (rising edge)
2.09
2.14
2.19
PLS[2:0]=000 (falling edge)
1.98
2.04
2.08
PLS[2:0]=001 (rising edge)
2.23
2.30
2.37
PLS[2:0]=001 (falling edge)
2.13
2.19
2.25
PLS[2:0]=010 (rising edge)
2.39
2.45
2.51
PLS[2:0]=010 (falling edge)
2.29
2.35
2.39
PLS[2:0]=011 (rising edge)
2.54
2.60
2.65
PLS[2:0]=011 (falling edge)
2.44
2.51
2.56
PLS[2:0]=100 (rising edge)
2.70
2.76
2.82
PLS[2:0]=100 (falling edge)
2.59
2.66
2.71
PLS[2:0]=101 (rising edge)
2.86
2.93
2.99
PLS[2:0]=101 (falling edge)
2.65
2.84
2.92
PLS[2:0]=110 (rising edge)
2.96
3.03
3.10
PLS[2:0]=110 (falling edge)
2.85
2.93
2.99
PLS[2:0]=111 (rising edge)
3.07
3.14
3.21
PLS[2:0]=111 (falling edge)
2.95
3.03
3.09
-
100
-
Falling edge
1.60
1.68
1.76
Rising edge
1.64
1.72
1.80
-
40
-
Falling edge
2.13
2.19
2.24
Rising edge
2.23
2.29
2.33
Falling edge
2.44
2.50
2.56
Rising edge
2.53
2.59
2.63
Falling edge
2.75
2.83
2.88
Rising edge
2.85
2.92
2.97
PVD hysteresis
VPOR/PDR
(1)
Min
-
-
Unit
V
mV
V
mV
V
BOR hysteresis
-
-
100
-
mV
POR reset temporization
-
0.5
1.5
3.0
ms
IRUSH(1)
InRush current on voltage
regulator power-on (POR or
wakeup from Standby)
-
-
160
200
mA
ERUSH(1)
InRush energy on voltage
regulator power-on (POR or
wakeup from Standby)
-
-
5.4
µC
TRSTTEMPO(1)(2)
VDD = 1.7 V, TA = 105 °C,
IRUSH = 171 mA for 31 µs
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first
instruction is read by the user application code.
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5.3.6
STM32F469xx
Over-drive switching characteristics
When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 23. They are subject to general
operating conditions for TA.
Table 23. Over-drive switching characteristics(1)
Symbol
Tod_swen
Tod_swdis
Parameter
Over_drive switch
enable time
Conditions
Min
Typ
Max
HSI
-
45
-
HSE max for 4 MHz
and min for 26 MHz
45
-
100
External HSE
50 MHz
-
40
-
HSI
-
20
-
20
-
80
-
15
-
HSE max for 4 MHz
Over_drive switch
and min for 26 MHz.
disable time
External HSE
50 MHz
Unit
µs
1. Guaranteed by design.
5.3.7
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 23.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark® code.
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Electrical characteristics
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in input mode with a static value at VDD or VSS (no load).
•
All peripherals are disabled except if it is explicitly mentioned.
•
The Flash memory access time is adjusted both to fHCLK frequency and VDD range
(see Table 18: Limitations depending on the operating power supply range).
•
When the regulator is OFF, the V12 is provided externally, as described in Table 17:
General operating conditions.
•
The voltage scaling and over-drive mode are adjusted to fHCLK frequency as follows:
–
Scale 3 for fHCLK ≤ 120 MHz
–
Scale 2 for 120 MHz < fHCLK ≤ 144 MHz
–
Scale 1 for 144 MHz < fHCLK ≤ 180 MHz. The over-drive is only ON at 180 MHz.
•
The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
•
External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz.
•
The typical current consumption values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage
range and for ambient temperature TA= 25 °C unless otherwise specified.
•
The maximum values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage range and a
maximum ambient temperature (TA), unless otherwise specified.
•
For the voltage range 1.7 V ≤ VDD ≤ 2.1 V the maximum frequency is 168 MHz.
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STM32F469xx
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM,
regulator ON
Max(1)
Symbol
Parameter
Conditions
fHCLK (MHz)
Typ
180
All
Peripherals
enabled(2)(3)
IDD
Supply
current in
RUN mode
All
Peripherals
disabled(2)
TA =
25 °C
TA =
85 °C
TA =
105 °C
103
109(4)
142
175(4)
168
94
99
124
149
150
84
89
114
140
144
77
81
104
127
120
57
60
79
98
90
43
46
64
84
60
30
33
51
70
30
16
19
37
57
25
14
16
34
54
16
7
10
28
48
8
4
7
26
46
4
3
6
24
44
2
3
5
23
43
180
50
56(4)
89
124(4)
168
45
51
75
102
150
41
46
70
97
144
37
42
63
88
120
28
31
49
69
90
21
24
42
63
60
15
17
36
56
30
9
11
29
49
25
7
10
28
48
16
4
7
25
45
8
3
6
22
44
4
3
5
23
43
2
2
5
23
43
Unit
mA
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
4. Guaranteed by test in production.
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Electrical characteristics
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled), regulator ON
Max(1)
Symbol
Parameter
Conditions
All Peripherals
enabled(2)(3)
IDD
Supply current in
RUN mode
All Peripherals
disabled
fHCLK
(MHz)
Typ
168
TA =
25 °C
TA =
85 °C
TA =
105 °C
97
102
128
154
150
87
92
118
143
144
80
84
108
131
120
65
68
88
108
90
51
54
73
93
60
37
41
59
79
30
21
23
42
62
25
18
20
39
59
168
49
55
79
105
150
44
49
44
100
144
40
45
68
92
120
36
39
58
78
90
29
32
51
71
60
22
25
44
64
30
13
15
34
54
25
11
13
32
52
Unit
mA
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
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STM32F469xx
Table 26. Typical and maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator enabled except prefetch),
regulator OFF
Max(1)
Typ
Symbol
Parameter
Conditions
All Peripherals
enabled(2) (3)
Supply current
in RUN mode
IDD12 / IDD
from V12 and
VDD supply
All Peripherals
disabled
fHCLK
(MHz)
IDD12
IDD
168
93
150
TA = 25 °C
TA = 85 °C
TA = 105 °C Unit
IDD12
IDD
IDD12
IDD
IDD12
IDD
1
98
1
123
1
148
1
83
1
88
1
113
1
138
1
144
76
1
80
1
103
1
126
1
120
56
1
59
1
78
1
97
1
90
43
1
45
1
64
1
83
1
60
29
1
32
1
50
1
70
1
30
15
1
18
1
36
1
56
1
25
13
1
15
1
34
1
53
1
168
44
1
50
1
72
1
94
1
150
40
1
45
1
68
1
90
1
144
36
1
40
1
62
1
82
1
120
27
1
30
1
48
1
66
1
90
20
1
23
1
41
1
60
1
60
14
1
16
1
35
1
53
1
30
8
1
10
1
28
1
47
1
25
7
1
9
1
27
1
46
1
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, DSI regulator, an additional power
consumption should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
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STM32F469xx
Electrical characteristics
Table 27. Typical and maximum current consumption in Sleep mode, regulator ON
Max(1)(2)(3)
Symbol
Parameter
Conditions fHCLK (MHz)
All
Peripherals
enabled
IDD
Supply
current in
Sleep mode
All
Peripherals
disabled
Typ
Unit
TA = 25 °C
TA = 85 °C
TA = 105 °C
180
78
88(4)
118
151(4)
168
71
76
101
127
150
64
71
94
119
144
58
62
85
109
120
43
46
65
85
90
33
37
54
74
60
23
25
44
63
30
13
15
34
53
25
11
13
32
52
16
5
8
27
47
8
4
7
25
45
4
3
5
24
44
2
2
5
23
43
63
96(4)
(4)
180
23
29
168
21
25
50
76
150
19
23
48
74
144
17
31
43
67
120
13
16
34
54
90
10
13
31
51
60
7
10
28
48
30
5
7
25
45
25
4
7
25
45
16
2
5
23
43
8
2
5
23
43
4
2
5
23
43
2
2
4
23
42
mA
1. Guaranteed based on test during characterization.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC
for the analog part.
4. Guaranteed by test in production.
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Electrical characteristics
STM32F469xx
Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF
Max(1)
Typ
Symbol
Parameter
Conditions
All
Peripherals
enabled
IDD12 / IDD
Supply current
in RUN mode
from V12 and
VDD supply
All
Peripherals
disabled
fHCLK
(MHz)
IDD12
IDD
168
70
150
TA = 25 °C
TA = 105 °C
IDD12
IDD
IDD12
IDD
IDD12
IDD
1
75
1
100
1
126
1
63
1
70
1
93
1
118
1
144
57
1
61
1
84
1
108
1
120
42
1
45
1
64
1
84
1
90
32
1
36
1
53
1
73
1
60
22
1
24
1
43
1
63
1
30
12
1
14
1
33
1
53
1
25
10
1
12
1
31
1
51
1
168
20
1
24
1
49
1
75
1
150
18
1
22
1
47
1
73
1
144
16
1
19
1
42
1
66
1
120
12
1
14
1
33
1
53
1
90
10
1
12
1
30
1
50
1
60
7
1
9
1
27
1
47
1
30
4
1
6
1
24
1
44
1
25
4
1
6
1
24
1
44
1
1. Guaranteed based on test during characterization.
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Unit
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STM32F469xx
Electrical characteristics
Table 29. Typical and maximum current consumption in Stop mode
Max(1)
Symbol
Parameter
Supply current in Stop
mode with voltage
regulator in main
regulator mode
IDD_STOP_NM
(normal mode)
Supply current in Stop
mode with voltage
regulator in Low Power
regulator mode
Supply current in Stop
mode with voltage
regulator in main
regulator and underIDD_STOP_UDM drive mode
(under-drive
Supply current in Stop
mode)
mode with voltage
regulator in Low Power
regulator and underdrive mode
Conditions
Typ
TA =
25 °C
TA =
TA =
85 °C 105 °C
Flash memory in Stop mode, all
oscillators OFF, no independent
watchdog
0.63
3
17
33
Flash memory in Deep power
down mode, all oscillators OFF,
no independent watchdog
0.58
3
17
33
Flash memory in Stop mode, all
oscillators OFF, no independent
watchdog
0.50
2
15
28
Flash memory in Deep power
down mode, all oscillators OFF,
no independent watchdog
0.44
2
15
28
Flash memory in Deep power
down mode, main regulator in
under-drive mode, all oscillators
OFF, no independent watchdog
0.21
1
6
12
Flash memory in Deep power
down mode, Low Power regulator
in under-drive mode, all
oscillators OFF, no independent
watchdog
0.14
1
6
13
Unit
mA
1. Data based on characterization, tested in production.
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Electrical characteristics
STM32F469xx
Table 30. Typical and maximum current consumption in Standby mode
Typ(1)
Symbol
Parameter
Max(2)
TA =
25 °C
TA = 25 °C
Conditions
TA =
85 °C
TA =
105 °C
VDD =
1.7 V
VDD=
2.4 V
VDD =
3.3 V
Backup SRAM ON, RTC and
LSE oscillator OFF
1.7
2.5
2.9
6(3)
18
35(3)
Backup SRAM OFF, RTC and
LSE oscillator OFF
1.0
1.8
2.20
5(3)
15
30(3)
Backup SRAM OFF, RTC ON
and LSE oscillator in Power
Drive mode
1.7
2.7
3.2
7
20
39
Supply current
Backup SRAM ON, RTC ON
IDD_STBY in Standby
and LSE oscillator in Power
mode
Drive mode
2.4
3.4
4.0
8
25
48
Backup SRAM ON, RTC ON
and LSE oscillator in High
Drive mode
3.2
4.2
4.8
10
29
57
Backup SRAM OFF, RTC ON
and LSE oscillator in High
Drive mode
2.5
3.5
4.1
8
25
48
VDD = 3.3 V
1. PDR is off for VDD=1.7 V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by
additional 1.2 μA
2. Based on characterization, not tested in production unless otherwise specified.
3. Based on characterization, tested in production.
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STM32F469xx
Electrical characteristics
Table 31. Typical and maximum current consumption in VBAT mode
Max(2)
Typ
Symbol
TA =
25 °C
TA = 25 °C
Conditions(1)
Parameter
VBAT = VBAT= VBAT =
1.7 V 2.4 V 3.3 V
TA =
85 °C
TA =
105 °C Unit
VBAT = 3.3 V
Backup SRAM ON, RTC ON
and LSE oscillator in Low
Power mode
1.431
1.577
1.825
1.9
12.0
24.0
Backup SRAM OFF, RTC ON
and LSE oscillator in Low
Power mode
0.720
0.849
1.060
1.1
7.0
13.9
2.212
2.368
2.630
2.80
17.3
34.6
1.499
1.637
1.862
2.0
12.3
24.5
Backup SRAM ON, RTC and
LSE OFF
0.710
0.720
0.760
0.8(3)
5.0
10.0(3)
Backup SRAM OFF, RTC and
LSE OFF
0.018
0.020
0.024
0.2(3)
2.0
4.0(3)
Backup SRAM ON, RTC ON
Backup
and LSE oscillator in High
IDD_VBAT domain supply Drive mode
current
Backup SRAM OFF, RTC ON
and LSE oscillator in High
Drive mode
µA
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Based on characterization, tested in production.
3. Based on test during characterization.
Figure 25. Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in Low drive mode)
6
1.65V
IDD_VBAT (μA)
5
1.70V
1.80V
4
2.00V
3
2.40V
2
2.70V
3.00V
1
0
3.30V
3.60V
0
20
40
60
80
100
Temperature (°C)
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Electrical characteristics
STM32F469xx
Figure 26. Typical VBAT current consumption
(RTC ON / backup SRAM ON and LSE in High drive mode)
IDD_VBAT (μA)
7
1.65V
6
1.70V
5
1.80V
2.00V
4
2.40V
3
2.70V
2
3.00V
1
3.30V
0
3.60V
0
20
40
60
Temperature (°C)
80
100
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 58.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 33), the I/Os used by
an application also contribute to the current consumption. When an I/O pin switches, it uses
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Electrical characteristics
the current from the MCU supply voltage to supply the I/O pin circuitry and to
charge/discharge the capacitive load (internal or external) connected to the pin:
I SW = V DD × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
Table 32. Switching output I/O current consumption(1)
I/O toggling
Symbol
Parameter
Conditions
VDD = 3.3 V
C= CINT(2)
IDDIO
I/O switching
Current
VDD = 3.3 V
CEXT = 0 pF
C = CINT + CEXT + CS
DocID028196 Rev 2
frequency
(fsw)
Typ
2 MHz
0.0
8 MHz
0.2
25 MHz
0.6
50 MHz
1.1
60 MHz
1.3
84 MHz
1.8
90 MHz
1.9
2 MHz
0.1
8 MHz
0.4
25 MHz
1.23
50 MHz
2.43
60 MHz
2.93
84 MHz
3.86
90 MHz
4.07
Unit
mA
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Electrical characteristics
STM32F469xx
Table 32. Switching output I/O current consumption(1) (continued)
I/O toggling
Symbol
Parameter
Conditions
VDD = 3.3 V
CEXT = 10 pF
C = CINT + CEXT + CS
IDDIO
I/O switching
Current
VDD = 3.3 V
CEXT = 22 pF
C = CINT + CEXT + CS
VDD = 3.3 V
CEXT = 33 pF
C = CINT + Cext + CS
frequency
(fsw)
Typ
2 MHz
0.18
8 MHz
0.67
25 MHz
2.09
50 MHz
3.6
60 MHz
4.5
84 MHz
7.8
90 MHz
9.8
2 MHz
0.26
8 MHz
1.01
25 MHz
3.14
50 MHz
6.39
60 MHz
10.68
2 MHz
0.33
8 MHz
1.29
25 MHz
4.23
50 MHz
11.02
Unit
mA
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
2. This test is performed by cutting the LQFP176 package pin (pad removal).
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
At startup, all I/O pins are in analog input configuration.
•
All peripherals are disabled unless otherwise mentioned.
•
I/O compensation cell enabled.
•
The ART accelerator is ON.
•
Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
•
HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
The given value is calculated by measuring the difference of current consumption
•
106/208
–
with all peripherals clocked off
–
with only one peripheral clocked on
–
fHCLK = 180 MHz (Scale1 + over-drive ON), fHCLK = 144 MHz (Scale 2),
fHCLK = 120 MHz (Scale 3)
Ambient operating temperature is 25 °C and VDD=3.3 V.
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Table 33. Peripheral current consumption
IDD(Typ)(1)
Peripheral
AHB1
(up to
180 MHz)
AHB2
(up to
180 MHz)
AHB3
(up to
180 MHz)
Unit
Scale 1
Scale 2
Scale 3
GPIOA
3.16
3.00
2.58
GPIOB
2.67
2.62
2.25
GPIOC
2.42
2.31
2.10
GPIOD
2.22
2.10
1.79
GPIOE
2.60
2.48
2.23
GPIOF
2.39
2.27
2.08
GPIOG
2.27
2.13
1.98
GPIOH
2.34
2.20
2.02
GPIOI
2.52
2.37
2.17
GPIOJ
2.16
2.03
1.86
GPIOK
2.20
2.06
1.89
OTG_HS+ULPI
36.49
33.89
29.90
CRC
0.62
0.55
0.50
BKPSRAM
0.83
0.74
0.63
DMA1(2)
3.3 x N + 6.8
3 x N + 6.3
2.7 x N + 5.5
DMA2(2)
3.4 x N + 5.7
3.1 x N + 5.3
2.8 x N + 4.6
DMA2D
33.33
30.66
26.98
ETH_MAC
ETH_MAC_TX
ETH_MAC_RX
ETH_MAC_PTP
22.30
20.69
18.19
USB_OTG_FS
34.33
31.96
28.35
DVCMI
3.61
3.35
2.98
RNG
1.94
1.82
1.61
QUADSPI
16.83
15.57
13.83
FMC
17.22
15.92
14.00
12.17
11.19
9.97
Bus matrix(3)
DocID028196 Rev 2
µA/MHz
µA/MHz
µA/MHz
µA/MHz
107/208
187
Electrical characteristics
STM32F469xx
Table 33. Peripheral current consumption (continued)
IDD(Typ)(1)
Peripheral
APB1
(up to
45 MHz)
108/208
Unit
Scale 1
Scale 2
Scale 3
TIM2
19.11
17.56
15.33
TIM3
15.62
14.22
12.17
TIM4
16.22
14.64
12.83
TIM5
18.44
16.72
14.00
TIM6
3.18
2.69
2.17
TIM7
3.11
2.56
2.00
TIM12
8.67
7.56
6.50
TIM13
6.11
5.33
4.43
TIM14
6.44
5.61
4.67
PWR
17.44
15.61
13.53
USART2
5.44
4.64
3.93
USART3
5.51
4.72
4.00
UART4
5.22
4.64
3.83
UART5
5.33
4.64
3.83
UART7
5.56
4.78
4.10
UART8
5.24
4.64
3.93
I2C1
4.78
4.08
3.43
I2C2
5.11
4.50
3.73
I2C3
4.78
4.08
3.43
SPI2/I2S2(4)
4.11
3.53
3.00
SPI3/I2S3(4)
4.33
3.67
3.17
CAN1
8.89
7.83
6.87
CAN2
7.22
6.44
5.50
DAC(5)
2.89
2.69
2.40
WWDG
1.73
1.44
1.00
DocID028196 Rev 2
µA/MHz
STM32F469xx
Electrical characteristics
Table 33. Peripheral current consumption (continued)
IDD(Typ)(1)
Peripheral
APB2
(up to
90 MHz)
Unit
Scale 1
Scale 2
Scale 3
SDIO
7.94
7.18
6.37
TIM1
19.44
17.81
15.80
TIM8
19.44
17.81
15.80
TIM9
8.44
7.60
6.77
TIM10
5.67
5.03
4.50
TIM11
5.72
5.10
4.55
ADC1(6)
5.06
4.54
4.05
ADC2(6)
5.00
4.47
3.97
ADC3(6)
5.26
4.75
4.17
USART1
4.83
4.33
3.83
USART6
4.83
4.33
3.83
SPI1
2.11
1.76
1.60
SPI4
2.11
1.69
1.60
SPI5
2.11
1.76
1.60
SPI6
2.11
1.76
1.60
SYSCFG
1.72
1.35
1.22
LTDC
37.61
34.53
30.60
SAI1
3.44
3.01
2.72
DSI
32.98
30.32
26.87
µA/MHz
1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.
2. DMA1/DMA2 current consumption is calculated by the equation. N: is the number of streams enabled,
N= [1..8]
3. The BusMatrix is automatically active when at least one master is ON.
4. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
5. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.8 mA per DAC channel for the analog part.
6. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.6 mA per ADC for the analog part.
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187
Electrical characteristics
5.3.8
STM32F469xx
Wakeup time from low-power modes
The wakeup times given in Table 34 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
For Stop or Sleep modes: the wakeup event is WFE.
•
WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 34. Low-power mode wakeup timings
Symbol
Parameter
tWUSLEEP(2)
tWUSTOP(2)
tWUSTOP(2)
Wakeup from Sleep
Wakeup from Stop mode
with MR/LP regulator in
normal mode
Wakeup from Stop mode
with MR/LP regulator in
Under-drive mode
tWUSTDBY (2)(3) Wakeup from Standby mode
Conditions
-
Typ(1) Max(1)
5
6
Main regulator is ON
12.9
13.0
Main regulator is ON and Flash
memory in Deep power down mode
105
109
Low power regulator is ON
22
25.4
Low power regulator is ON and Flash
memory in Deep power down mode
114
121
Main regulator in under-drive mode
(Flash memory in Deep power-down
mode)
107
111
Low power regulator in under-drive
mode (Flash memory in Deep
power-down mode)
115
121
318
371
-
Unit
CPU clock
cycles
µs
1. Based on test during characterization.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
3. tWUSTDBY maximum value is given at –40 °C.
5.3.9
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 58. However, the recommended clock input
waveform is shown in Figure 27.
The characteristics given in Table 35 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
110/208
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
summarized in Table 17.
Table 35. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1
-
50
MHz
fHSE_ext
External user clock source
frequency(1)
VHSEH
OSC_IN input pin high level voltage
0.7VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3VDD
-
V
tw(HSE)
tw(HSE)
OSC_IN high or low time
5
-
-
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1)
-
-
10
-
-
5
-
pF
-
45
-
55
%
VSS ≤VIN ≤VDD
-
-
±1
µA
(1)
ns
Cin(HSE)
OSC_IN input capacitance(1)
DuCy(HSE) Duty cycle
IL
OSC_IN Input leakage current
1. Guaranteed by design.
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 58. However, the recommended clock input
waveform is shown in Figure 28.
The characteristics given in Table 36 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
Table 36. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
32.768
1000
kHz
fLSE_ext
User External clock source frequency(1)
VLSEH
OSC32_IN input pin high level voltage
0.7VDD
-
VDD
VLSEL
OSC32_IN input pin low level voltage
VSS
-
0.3VDD
tw(LSE)
tf(LSE)
OSC32_IN high or low time(1)
450
-
-
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
-
-
50
-
-
5
-
pF
-
30
-
70
%
VSS ≤VIN ≤VDD
-
-
±1
µA
Cin(LSE)
ns
OSC32_IN input capacitance(1)
DuCy(LSE) Duty cycle
IL
-
V
OSC32_IN Input leakage current
1. Guaranteed by design.
DocID028196 Rev 2
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187
Electrical characteristics
STM32F469xx
Figure 27. High-speed external clock source AC timing diagram
6(3%(
6(3%,
TR(3%
TF(3%
T7(3% T
T7(3%
4(3%
%XTERNAL
CLOCKSOURCE
F(3%?EXT
),
/3#?).
34-&
AI
Figure 28. Low-speed external clock source AC timing diagram
9/6(+
9/6(/
WU/6(
WI/6(
W:/6(
26&B,1
,/
W:/6( W
7/6(
([WHUQDO
FORFNVRXUFH
I/6(BH[W
670)
DL
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 37. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 37. HSE 4-26 MHz oscillator characteristics (1)
Symbol
Parameter
fOSC_IN
RF
112/208
Conditions
Min
Typ
Max
Unit
Oscillator frequency
-
4
-
26
MHz
Feedback resistor
-
-
200
-
kΩ
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Table 37. HSE 4-26 MHz oscillator characteristics (1) (continued)
Symbol
IDD
Parameter
HSE current consumption
ACCHSE(2)
Conditions
Min
Typ
Max
VDD=3.3 V,
ESR= 30 Ω,
CL=5 pF@25 MHz
-
450
-
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF@25 MHz
-
530
-
-
− 500
-
500
ppm
Startup
-
-
1
mA/V
VDD is stabilized
-
2
-
ms
HSE accuracy
Gm_crit_max Maximum critical crystal gm
tSU(HSE)
(3)
Startup time
Unit
µA
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is based on characterization and not tested in production. It is measured
for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 29). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from www.st.com.
Figure 29. Typical application with an 8 MHz crystal
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
&/
0+]
UHVRQDWRU
&/
I+6(
26&B,1
5(;7
5)
26&B28 7
%LDV
FRQWUROOHG
JDLQ
670)
DL
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the informations given in this paragraph are based on
characterization results obtained with typical external components specified in Table 38.
In the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
DocID028196 Rev 2
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187
Electrical characteristics
STM32F469xx
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
RF
IDD
ACCLSE(3)
Parameter
Min
Typ
Max
Unit
-
MΩ
Feedback resistor
LSE current consumption
Low power
-
18.4
-
mode(2)
-
-
1
(2)
-
-
3
High drive mode
LSE accuracy
− 500
-
500
-
-
0.56
(2)
-
-
1.5
Startup time
-
2
-
Low power mode
High drive mode
µA
(2)
-
Gm_crit_max Maximum critical crystal gm
tSU(LSE)(4)
Conditions
VDD is stabilized
ppm
µA/V
s
1. Guaranteed by design.
2. LSE mode cannot be changed “on the fly” otherwise, a glitch can be generated on OSCIN pin.
3. This parameter depends on the crystal used in the application. Refer to application note AN2867.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is based on characterization and not tested in production. It is
measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from www.st.com.
Figure 30. Typical application with a 32.768 kHz crystal
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
&/
I/6(
26&B,1
%LDV
5) FRQWUROOHG
JDLQ
N+ ]
UHVRQDWRU
26&B28 7
&/
670)
DL
5.3.10
Internal clock source characteristics
The parameters given in Table 39 and Table 40 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 17.
High-speed internal (HSI) RC oscillator
Table 39. HSI oscillator characteristics (1)
Symbol
fHSI
ACCHSI
Parameter
Conditions
Min
Frequency
-
HSI user trimming step(2)
-
TA = –10 to 85
DocID028196 Rev 2
-
16
-
MHz
-
-
1
%
−8
-
4.5
%
°C(3)
−4
-
4
%
−1
-
1
%
TA = 25 °C(4)
114/208
Unit
°C(3)
TA = –40 to 105
HSI oscillator accuracy
Typ Max
STM32F469xx
Electrical characteristics
Table 39. HSI oscillator characteristics (1) (continued)
Symbol
tsu(HSI)
(2)
Parameter
Conditions
Min
-
-
2.2
4
µs
-
-
60
80
µA
HSI oscillator startup time
IDD(HSI)(2) HSI oscillator power consumption
Typ Max
Unit
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design
3. Based on test during characterization.
4. Factory calibrated, parts not soldered.
Figure 31. HSI deviation vs. temperature
HSI deviation versus temperature (1)
1.5%
Deviation
1.0%
0.5%
0.0%
-40°C
0°C
25°C
85°C
105°C
TA(°C)
-0.5%
Min
Max
Typical
-1.0%
-1.5%
1. Based on test during characterization.
DocID028196 Rev 2
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187
Electrical characteristics
STM32F469xx
Low-speed internal (LSI) RC oscillator
Table 40. LSI oscillator characteristics (1)
Symbol
Parameter
fLSI(2)
tsu(LSI)
Min
Typ
Max
Unit
17
32
47
kHz
Startup time
-
15
40
µs
Power consumption
-
0.4
0.6
µA
Frequency
(3)
IDD(LSI)(3)
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
2. Based on test during characterization.
3. Guaranteed by design.
Figure 32. ACCLSI versus temperature
MAX
AVG
MIN
.ORMALIZEDDEVIATI ON
4EMPERAT URE #
-36
5.3.11
PLL characteristics
The parameters given in Table 41 and Table 42 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.
Table 41. Main PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
fPLL_IN
PLL input clock(1)
-
0.95(2)
1
2.10
fPLL_OUT
PLL multiplier output clock
-
24
-
180
fPLL48_OUT
48 MHz PLL multiplier output clock
-
-
48
75
fVCO_OUT
PLL VCO output
-
192
-
432
116/208
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Unit
MHz
STM32F469xx
Electrical characteristics
Table 41. Main PLL characteristics (continued)
Symbol
tLOCK
Parameter
Conditions
PLL lock time
Min
Typ
Max
VCO freq = 192 MHz
75
-
200
VCO freq = 432 MHz
100
-
300
RMS
-
25
-
peak to peak
-
±150
-
RMS
-
15
-
peak to peak
-
±200
-
Cycle-to-cycle jitter
System clock
120 MHz
Period Jitter
(3)
Jitter
Unit
µs
ps
Main clock output (MCO) for RMII
Ethernet
Cycle to cycle at 50 MHz on
1000 samples
-
32
-
Main clock output (MCO) for MII
Ethernet
Cycle to cycle at 25 MHz on
1000 samples
-
40
-
Bit Time CAN jitter
Cycle to cycle at 1 MHz on
1000 samples
-
330
-
IDD(PLL)(4)
PLL power consumption on VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
IDDA(PLL)(4)
VCO freq = 192 MHz
PLL power consumption on VDDA
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel can degrade the Jitter up to +30%.
4. Based on test during characterization.
Table 42. PLLI2S (audio PLL) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLI2S_IN
PLLI2S input clock(1)
-
0.95(2)
1
2.10
fPLLI2S_OUT
PLLI2S multiplier output
clock
-
-
-
216
fVCO_OUT
PLLI2S VCO output
-
192
-
432
tLOCK
PLLI2S lock time
VCO freq = 192 MHz
75
-
200
VCO freq = 432 MHz
100
-
300
RMS
-
90
-
-
peak to peak
-
±280
-
ps
Average frequency of 12.288 MHz,
N=432, R=5
on 1000 samples
-
90
-
ps
Cycle to cycle at 48 KHz
on 1000 samples
-
400
-
ps
Master I2S clock jitter
Jitter(3)
WS I2S clock jitter
Cycle to cycle at
12.288 MHz on 48KHz
period, N=432, R=5
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MHz
µs
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Electrical characteristics
STM32F469xx
Table 42. PLLI2S (audio PLL) characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
IDD(PLLI2S)(4)
PLLI2S power consumption VCO freq = 192 MHz
on VDD
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
IDDA(PLLI2S)(4)
PLLI2S power consumption VCO freq = 192 MHz
on VDDA
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
Unit
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Based on test during characterization.
Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLSAI_IN
PLLSAI input clock(1)
-
0.95(2)
1
2.10
fPLLSAI_OUT
PLLSAI multiplier output clock
-
-
-
216
fVCO_OUT
PLLSAI VCO output
-
192
-
432
tLOCK
PLLSAI lock time
VCO freq = 192 MHz
75
-
200
VCO freq = 432 MHz
100
-
300
RMS
-
90
-
peak
to
peak
-
±280
-
ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-
90
-
ps
FS clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-
400
-
ps
IDD(PLLSAI)(4)
PLLSAI power consumption on
VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
IDDA(PLLSAI)(4)
PLLSAI power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
Main SAI clock jitter
(3)
Jitter
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Based on test during characterization.
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MHz
µs
mA
STM32F469xx
5.3.12
Electrical characteristics
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 54). It is available only on the main PLL.
Table 44. SSCG parameters constraint
Symbol
Parameter
Min
Typ
Max(1)
Unit
fMod
Modulation frequency
-
-
10
KHz
md
Peak modulation depth
0.25
-
2
%
MODEPER * INCSTEP
-
-
-
215
−1
-
1. Guaranteed by design.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round [ f PLL_IN ⁄ ( 4 × f Mod ) ]
fPLL_IN and fMod must be expressed in Hz.
As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
6
3
MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP = round [ ( ( 2
15
– 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ]
fVCO_OUT must be expressed in MHz.
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP = round [ ( ( 2
15
– 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2
15
– 1 ) × PLLN )
As a result:
md quantized % = ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2
DocID028196 Rev 2
15
– 1 ) × 240 ) = 2.002%(peak)
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Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.
Figure 33. PLL output clock waveforms in center spread mode
)UHTXHQF\
3//B287
PG
)
PG
WPRGH
7LPH
[WPRGH
069
Figure 34. PLL output clock waveforms in down spread mode
)UHTXHQF\
3//B287
)
[PG
WPRGH
7LPH
[WPRGH
069
5.3.13
MIPI D-PHY characteristics
The parameters given in Table 45 and Table 46 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.
Table 45. MIPI D-PHY characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
12.5
ns
Hi-Speed Input/Output Characteristics
UINST
120/208
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-
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STM32F469xx
Electrical characteristics
Table 45. MIPI D-PHY characteristics(1) (continued)
Symbol
Conditions
Min
Typ
Max
HS transmit common mode
voltage
-
150
200
250
|∆VCMTX|
VCMTX mismatch when output
is Differential-1 or Differential-0
-
-
-
5
|VOD|
HS transmit differential voltage
-
140
200
270
|∆VOD|
VOD mismatch when output is
Differential-1 or Differential-0
-
-
-
14
VOHHS
HS output high voltage
-
-
-
360
ZOS
Single ended output
impedance
-
40
50
62.5
Ω
∆ZOS
Single ended output
impedance mismatch
-
-
-
10
%
20%-80% rise and fall time
-
100
-
0.35*UI
ps
VCMTX
tHSr & tHSf
Parameter
Unit
mV
LP Receiver Input Characteristics
VIL
Logic 0 input voltage (not in
ULP State)
-
-
-
550
VIL-ULPS
Logic 0 input voltage in ULP
State
-
-
-
300
VIH
Input high level voltage
-
880
-
-
Vhys
Voltage hysteresis
-
25
-
-
mV
LP Emitter Output Characteristics
VIL
Output low level voltage
-
1.1
1.2
1.2
V
VIL-ULPS
Output high level voltage
-
-50
-
50
mV
VIH
Output impedance of LP
transmitter
-
110
-
-
Ω
Vhys
15%-85% rise and fall time
-
-
-
25
ns
LP Contention Detector Characteristics
VILCD
Logic 0 contention threshold
-
-
-
200
VIHCD
Logic 0 contention threshold
-
450
-
-
mV
1. Guaranteed based on test during characterization.
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Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions(1)
Symbol
Parameter
Conditions
Min
Typ
Max
TLPX
Transmitted length of any LowPower state period
-
50
-
-
Time that the transmitter drives
the Clock Lane LP-00 Line
TCLK-PREPARE state immediately before the
HS-0 Line state starting the HS
transmission.
-
38
-
95
TCLK-PREPARE Time that the transmitter drives
+
the HS-0 state prior to starting
TCLK-ZERO
the clock.
-
300
-
-
TCLK-PRE
Time that the HS clock shall be
driven by the transmitter prior to
any associated Data Lane
beginning the transition from
LP to HS mode.
-
8
-
-
TCLK-POST
Time that the transmitter
continues to send HS clock
after the last associated Data
Lane has transitioned to LP
Mode.
-
62+52*UI
-
-
TCLK-TRAIL
Time that the transmitter drives
the HS-0 state after the last
payload clock bit of an HS
transmission burst.
-
60
-
-
THS-PREPARE
Time that the transmitter drives
the Data Lane LP-00 Line state
immediately before the HS-0
Line state starting the HS
transmission.
-
40+4*UI
-
85+6*UI
THS-PREPARE
+
THS-ZERO
THS-PREPARE+ Time that the
transmitter drives the HS-0
state prior to transmitting the
Sync sequence.
-
145+10*UI
-
-
THS-TRAIL
Time that the transmitter drives
the flipped differential state
after last payload data bit of a
HS transmission burst.
-
Max
(n*8*UI,
60+n*4*UI)
-
-
THS-EXIT
Time that the transmitter drives
LP-11 following a HS burst.
-
100
-
-
TREOT
30%-85% rise time and fall time
-
-
-
35
TEOT
Transmitted time interval from
the start of THS-TRAIL or
TCLK-TRAIL, to the start of the
LP-11 state following a HS
burst.
-
-
-
105+
n*12UI
1. Guaranteed based on test during characterization.
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Unit
ns
UI
ns
STM32F469xx
Electrical characteristics
Figure 35. MIPI D-PHY HS/LP clock lane transition timing diagram
7&/.3267
7(27
9,/
&ORFN
/DQH
7&/.75$,/
7+6(;,7
7/3; 7&/.35(3$5( 7&/.=(52 7&/.35(
'DWD
/DQH
7/3; 7+635(3$5(
9,/
069
Figure 36. MIPI D-PHY HS/LP data lane transition timing diagram
&ORFN
/DQH
'DWD
/DQH
7/3;
7+635(3$5(
/3
/3
7+6=(52
9,/
75(27
/3
7(27
7+675$,/
7+6(;,7
069
5.3.14
MIPI D-PHY PLL characteristics
The parameters given in Table 47 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.
Table 47. DSI-PLL characteristics(1)
Symbol
Conditions
Min
Typ
Max
PLL input clock
-
4
-
100
fPLL_INFIN PFD input clock
-
4
-
25
fPLL_OUT
-
31.25
-
500
-
500
-
1000
-
-
-
200
fPLL_IN
Parameter
PLL multiplier output clock
fVCO_OUT PLL VCO output
tLOCK
PLL lock time
DocID028196 Rev 2
Unit
MHz
µs
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Table 47. DSI-PLL characteristics(1) (continued)
Symbol
IDD(PLL)
Parameter
PLL power consumption on VDD12
Conditions
Min
Typ
Max
fVCO_OUT = 500 MHz
-
0.55
0.70
fVCO_OUT = 600 MHz
-
0.65
0.80
fVCO_OUT = 1000 MHz
-
0.95
1.20
Unit
mA
1. Based on test during characterization.
5.3.15
MIPI D-PHY regulator characteristics
The parameters given in Table 48 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.
Table 48. DSI regulator characteristics(1)
Symbol
Conditions
Min
Typ
Max
Unit
1.2 V internal voltage on VDD12DSI
-
1.15
1.20
1.30
V
CEXT
External capacitor on VCAPDSI
-
1.1
2.2
3.3
μF
ESR
External Serial Resistor
-
0
25
600
mΩ
-
100
120
125
µA
Ultra Low Power Mode
(Reg. ON + PLL OFF)
-
290
600
Stop State
(Reg. ON + PLL OFF)
-
290
600
10 MHz escape clock
(Reg. ON + PLL OFF)
-
4.3
5.0
20 MHz escape clock
(Reg. ON + PLL OFF)
-
4.3
5.0
300 Mbps - 1 data lane
(Reg. ON + PLL ON)
-
8.0
8.8
300 Mbps - 2data lane
(Reg. ON + PLL ON)
-
11.4
12.5
500 Mbps - 1 data lane
(Reg. ON + PLL ON)
-
13.5
14.7
500 Mbps - 2data lane
(Reg. ON + PLL ON)
-
18.0
19.6
500 Mbps - 2data lane
(Reg. ON + PLL ON)
-
21.4
23.3
CEXT = 2.2 µF
-
110
-
CEXT = 3.3 µF
-
-
160
External capacitor load at start
-
60
200
VDD12DSI
Parameter
IDDDSIREG Regulator power consumption
IDDDSI
IDDDSILP
IDDDSIHS
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
DSI system current consumption on
VDDDSI in LP mode communication(2)
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
in HS mode communication(3)
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
in HS mode with CLK like payload
tWAKEUP
Startup delay
IINRUSH
Inrush current on VDDDSI
1. Based on test during characterization.
2. Values based on an average traffic in LP Command Mode.
3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.
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µA
mA
mA
µs
mA
STM32F469xx
5.3.16
Electrical characteristics
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 49. Flash memory characteristics
Symbol
IDD
Parameter
Supply current
Conditions
Min
Typ
Max
Write / Erase 8-bit mode, VDD = 1.7 V
-
5
-
Write / Erase 16-bit mode, VDD = 2.1 V
-
8
-
Write / Erase 32-bit mode, VDD = 3.3 V
-
12
-
Unit
mA
Table 50. Flash memory programming
Symbol
tprog
Parameter
Word programming time
tERASE16KB Sector (16 KB) erase time
tERASE64KB Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
Conditions
Min(1)
Typ
Max(1) Unit
Program/erase parallelism
(PSIZE) = x 8/16/32
-
16
100(2)
Program/erase parallelism
(PSIZE) = x 8
-
400
800
Program/erase parallelism
(PSIZE) = x 16
-
300
600
Program/erase parallelism
(PSIZE) = x 32
-
250
500
Program/erase parallelism
(PSIZE) = x 8
-
1200
2400
Program/erase parallelism
(PSIZE) = x 16
-
700
1400
Program/erase parallelism
(PSIZE) = x 32
-
550
1100
Program/erase parallelism
(PSIZE) = x 8
-
2
4
Program/erase parallelism
(PSIZE) = x 16
-
1.3
2.6
Program/erase parallelism
(PSIZE) = x 32
-
1
2
DocID028196 Rev 2
µs
ms
ms
s
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Table 50. Flash memory programming (continued)
Symbol
tME
tBE
Vprog
Parameter
Mass erase time
Bank erase time
Programming voltage
Conditions
Min(1)
Typ
Max(1) Unit
Program/erase parallelism
(PSIZE) = x 8
-
16
32
Program/erase parallelism
(PSIZE) = x 16
-
11
22
Program/erase parallelism
(PSIZE) = x 32
-
8
16
Program/erase parallelism
(PSIZE) = x 8
-
16
32
Program/erase parallelism
(PSIZE) = x 16
-
11
22
Program/erase parallelism
(PSIZE) = x 32
-
8
16
32-bit program operation
2.7
-
3.6
16-bit program operation
2.1
-
3.6
8-bit program operation
1.7
-
3.6
s
V
1. Based on test during characterization.
2. The maximum programming time is measured after 100K erase operations.
Table 51. Flash memory programming with VPP
Symbol
Parameter
tprog
Double word programming
tERASE16KB
Sector (16 KB) erase time
tERASE64KB
Sector (64 KB) erase time
tERASE128KB Sector (128 KB) erase time
Conditions
Min(1)
Typ
Max(1)
Unit
-
16
100(2)
µs
-
230
-
-
490
-
-
875
-
-
6.9
-
s
s
TA = 0 to +40 °C
VDD = 3.3 V
VPP = 8.5 V
tME
Mass erase time
tBE
Bank erase time
-
-
6.9
-
Vprog
Programming voltage
-
2.7
-
3.6
VPP
VPP voltage range
-
7
-
9
IPP
Minimum current sunk on
the VPP pin
-
10
-
-
mA
Cumulative time during
which VPP is applied
-
-
-
1
hour
tVPP(3)
1. Guaranteed by design.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
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Electrical characteristics
Table 52. Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
1 kcycle(2) at TA = 85 °C
30
1 kcycle
(2)
10 kcycles
Unit
Min(1)
at TA = 105 °C
10
(2)
20
at TA = 55 °C
kcycles
Years
1. Based on test during characterization.
2. Cycling performed over the whole temperature range.
5.3.17
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 53. They are based on the EMS levels and classes
defined in application note AN1709.
Table 53. EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VFESD
VDD = 3.3 V, TFBGA216,
Voltage limits to be applied on any I/O pin
TA = +25 °C, fHCLK = 168 MHz,
to induce a functional disturbance
conforming to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, TFBGA216,
TA = +25 °C, fHCLK = 168 MHz,
conforming to IEC 61000-4-2
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
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STM32F469xx
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC? code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 54. EMI characteristics
Symbol Parameter
SEMI
5.3.18
Peak level
Conditions
Monitored
frequency band
Max vs. [fHSE/fCPU]
Unit
8/168 MHz 8/180 MHz
0.1 to 30 MHz
VDD = 3.3 V, TA = 25 °C, TFBGA216
30 to 130 MHz
package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral clocks 130 MHz to 1GHz
enabled, clock dithering disabled.
SAE EMI Level
0.1 to 30 MHz
VDD = 3.3 V, TA = 25 °C, TFBGA216
30 to 130 MHz
package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral clocks 130 MHz to 1GHz
enabled, clock dithering enabled
SAE EMI level
2
2
4
1
10
10
3
3
5
-10
3
-15
8
0
2
2
dBµV
-
dBµV
-
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards.
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Electrical characteristics
Table 55. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
VESD(HBM)
Electrostatic discharge
voltage
(human body model)
TA = +25 °C
conforming to ANSI/ESDA/JEDEC JS-001
2
Electrostatic discharge
voltage
VESD(CDM)
(charge device model)
TA = +25 °C conforming to ANSI/ESD S5.3.1,
LQFP176, LQFP208, UFBGA169, UFBGA176,
TFBGA216 and WLCSP148 packages
Maximum
Unit
value(1)
2000
V
C3
250
1. Guaranteed based on test during characterization.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 56. Electrical sensitivities(1)
Symbol
LU
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78A
Class
II level A
1. MSV on PA4 and PA5 is 5 V, versus 5.4 V on all IOs.
5.3.19
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 57.
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Table 57. I/O current injection susceptibility(1)
Functional susceptibility
Symbol
IINJ
Description
Negative
injection
Positive
injection
Injected current on BOOT0 and NRST pins
−0
NA
Injected current on DSIHOST_D0P,
DSIHOST_D0N, DSIHOST_D1P, DSIHOST_D0N,
DSIHOST_CKP, DSIHOST_CKN pins
−0
0
Injected current on PA0 and PC0 pins
−0
NA
Injected current on any other FT pin
−5
NA
Injected current on any other pin
−5
+5
Unit
mA
1. NA = not applicable.
Note:
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
5.3.20
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL
compliant.
Table 58. I/O static characteristics
Symbol
VIL
Parameter
Conditions
Min
Typ
FT, TTa and NRST I/O input low
level voltage
1.7 V≤VDD≤3.6 V
-
-
1.75 V≤VDD ≤3.6 V,
–40 °C≤TA ≤105 °C
-
-
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
-
BOOT0 I/O input low level
voltage
FT, TTa and NRST I/O input
high level voltage(5)
VIH
130/208
BOOT0 I/O input high level
voltage
1.7 V≤VDD≤3.6 V
1.75 V≤VDD ≤3.6 V,
–40 °C≤TA ≤105 °C
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
Max
Unit
0.35VDD − 0.04(1)
0.3VDD(2)
0.1VDD+0.1(1)
0.45VDD+0.3(1)
0.7VDD(2)
0.17VDD+0.7(1)
DocID028196 Rev 2
V
-
-
-
-
STM32F469xx
Electrical characteristics
Table 58. I/O static characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
1.7 V≤VDD≤3.6 V
10%VDD(3)
-
-
0.1
-
-
VSS ≤VIN ≤VDD
-
-
±1
VIN = 5 V
-
-
3
30
40
50
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
7
10
14
All pins
except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
30
40
50
7
10
14
-
5
-
FT, TTa and NRST I/O input
hysteresis
VHYS
BOOT0 I/O input hysteresis
Ilkg
RPU
RPD
CIO(8)
I/O input leakage current (4)
I/O FT input leakage current (5)
Weak pull-up
equivalent
resistor(6)
Weak pulldown
equivalent
resistor(7)
All pins
except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
1.75 V≤VDD ≤3.6 V, –
40 °C≤TA ≤105 °C
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
V
µA
VIN = VSS
kΩ
VIN = VDD
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
I/O pin capacitance
Unit
-
pF
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 57
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 57
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8.
Hysteresis voltage between Schmitt trigger switching levels. Based on test during characterization.
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 37.
Figure 37. FT I/O input characteristics
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which
can sink or source up to ±3mA. When using the PC13 to PC15 and PI8 GPIOs in output
mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2. In particular:
132/208
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 15).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 15).
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 17. All I/Os are CMOS and TTL compliant.
Table 59. Output voltage characteristics
Symbol
Parameter
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL (1)
Output low level voltage for an I/O pin
VOH (3)
Output high level voltage for an I/O pin
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL(1)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
Conditions
Min
Max
-
0.4
VDD − 0.4
-
-
0.4
2.4
-
-
1.3(4)
(2)
CMOS port
IIO = +8 mA
2.7 V ≤VDD ≤3.6 V
TTL port(2)
IIO =+ 8mA
2.7 V ≤VDD ≤3.6 V
IIO = +20 mA
2.7 V ≤VDD ≤3.6 V
IIO = +6 mA
1.8 V ≤VDD ≤3.6 V
IIO = +4 mA
1.7 V ≤VDD ≤3.6V
VDD
−1.3(4)
Unit
V
-
-
0.4(4)
VDD −0.4(4)
-
-
0.4(5)
VDD −0.4(5)
-
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 15 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data.
5. Guaranteed by design.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 38 and
Table 60, respectively.
Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.
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Table 60. I/O AC characteristics(1)(2)
OSPEEDRy
[1:0] bit
value(1)
Symbol
fmax(IO)out
Parameter
Maximum frequency
(3)
00
tf(IO)out/
tr(IO)out
fmax(IO)out
Output high to low level fall
time and output low to high
level rise time
Maximum frequency(3)
01
tf(IO)out/
tr(IO)out
fmax(IO)out
Output high to low level fall
time and output low to high
level rise time
Maximum frequency(3)
10
tf(IO)out/
tr(IO)out
134/208
Output high to low level fall
time and output low to high
level rise time
Conditions
Min
Typ
Max
CL = 50 pF, VDD ≥ 2.7 V
-
-
4
CL = 50 pF, VDD ≥ 1.7 V
-
-
2
CL = 10 pF, VDD ≥ 2.7 V
-
-
8
CL = 10 pF, VDD ≥ 1.8 V
-
-
4
CL = 10 pF, VDD ≥ 1.7 V
-
-
3
CL = 50 pF, VDD = 1.7 V to
3.6 V
-
-
100
CL = 50 pF, VDD≥ 2.7 V
-
-
25
CL = 50 pF, VDD≥ 1.8 V
-
-
12.5
CL = 50 pF, VDD≥ 1.7 V
-
-
10
CL = 10 pF, VDD ≥ 2.7 V
-
-
50
CL = 10 pF, VDD≥ 1.8 V
-
-
20
CL = 10 pF, VDD≥ 1.7 V
-
-
12.5
CL = 50 pF, VDD ≥ 2.7 V
-
-
10
CL = 10 pF, VDD ≥ 2.7 V
-
-
6
CL = 50 pF, VDD ≥ 1.7 V
-
-
20
CL = 10 pF, VDD ≥ 1.7 V
-
-
10
CL = 40 pF, VDD ≥ 2.7 V
-
-
50(4)
CL = 10 pF, VDD ≥ 2.7 V
-
-
100(4)
CL = 40 pF, VDD ≥ 1.7 V
-
-
25
CL = 10 pF, VDD ≥ 1.8 V
-
-
50
CL = 10 pF, VDD ≥ 1.7 V
-
-
42.5
CL = 40 pF, VDD ≥2.7 V
-
-
6
CL = 10 pF, VDD ≥ 2.7 V
-
-
4
CL = 40 pF, VDD ≥ 1.7 V
-
-
10
CL = 10 pF, VDD ≥ 1.7 V
-
-
6
DocID028196 Rev 2
Unit
MHz
ns
MHz
ns
MHz
ns
STM32F469xx
Electrical characteristics
Table 60. I/O AC characteristics(1)(2) (continued)
OSPEEDRy
[1:0] bit
value(1)
Symbol
fmax(IO)out
Parameter
Conditions
Maximum frequency(3)
11
tf(IO)out/
tr(IO)out
-
tEXTIpw
Output high to low level fall
time and output low to high
level rise time
Min
Typ
Max
CL = 30 pF, VDD ≥ 2.7 V
-
-
100(4)
CL = 30 pF, VDD ≥ 1.8 V
-
-
50
CL = 30 pF, VDD ≥ 1.7 V
-
-
42.5
CL = 10 pF, VDD≥ 2.7 V
-
-
180(4)
CL = 10 pF, VDD ≥ 1.8 V
-
-
100
CL = 10 pF, VDD ≥ 1.7 V
-
-
72.5
CL = 30 pF, VDD ≥ 2.7 V
-
-
4
CL = 30 pF, VDD ≥1.8 V
-
-
6
CL = 30 pF, VDD ≥1.7 V
-
-
7
CL = 10 pF, VDD ≥ 2.7 V
-
-
2.5
CL = 10 pF, VDD ≥1.8 V
-
-
3.5
CL = 10 pF, VDD ≥1.7 V
-
-
4
10
-
-
Pulse width of external signals
detected by the EXTI
controller
-
Unit
MHz
ns
ns
1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 38.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Figure 38. I/O AC characteristics definition
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Electrical characteristics
5.3.21
STM32F469xx
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 58).
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.
Table 61. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent resistor(1)
VIN = VSS
30
40
50
kΩ
-
-
-
100
VDD > 2.7 V
300
-
-
Internal Reset source
20
-
-
VF(NRST)
(2)
NRST Input filtered pulse
VNF(NRST)(2) NRST Input not filtered pulse
TNRST_OUT
Generated reset pulse duration
ns
µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design.
Figure 39. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 61. Otherwise the reset is not taken into account by the device.
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5.3.22
Electrical characteristics
TIM timer characteristics
The parameters given in Table 62 are guaranteed by design. Refer to Section 5.3.20 for
details on the input/output alternate function characteristics (output compare, input capture,
external clock, PWM output).
Table 62. TIMx characteristics(1)(2)
Symbol
tres(TIM)
fEXT
ResTIM
tMAX_COUNT
Parameter
Timer resolution time
Conditions(3)
Min
Max
Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK =
180 MHz
1
-
tTIMxCLK
AHB/APBx prescaler>4,
fTIMxCLK = 90 MHz
1
-
tTIMxCLK
0
fTIMxCLK/2
MHz
-
16/32
bit
-
65536 ×
65536
tTIMxCLK
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 180 MHz
Timer resolution
Maximum possible count
with 32-bit counter
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK =
4x PCLKx.
5.3.23
Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
•
Fast-mode (Fm): with a bit rate up to 400 kbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0386 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present. Refer to
Section 5.3.20 for more details on the I2C I/O characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 63. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes
that are suppressed by the analog
filter
50(2)
150(3)
ns
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Electrical characteristics
STM32F469xx
1. Guaranteed based on test during characterization.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 64 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).
Table 64. SPI dynamic characteristics(1)
Symbol
fSCK
1/tc(SCK)
Duty(SCK)
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Parameter
SPI clock frequency
Conditions
Min
Typ
Max
Master mode, 2.7 V≤VDD≤3.6 V,
SPI1,4,5,6,
-
-
45
Master mode, 1.71 V≤VDD≤3.6 V,
SPI1,4,5,6
-
-
22.5(2)
Master transmitter mode,
1.7 V≤VDD≤3.6 V, SPI1,4,5,6
-
-
45
Slave full duplex mode,
2.7 V≤VDD≤3.6 V, SPI1,4,5,6
-
-
22.5
Slave transmitter mode,
1.71 V≤VDD≤3.6 V, SPI1,4,5,6
-
-
33
Slave transmitter mode,
2.7 V≤VDD≤3.6 V, SPI1,4,5,6
-
-
45
Slave mode, 1.71 V≤VDD≤3.6 V,
SPI2,3
-
-
22.5
30
50
70
Duty cycle of SPI clock
Slave mode
frequency
DocID028196 Rev 2
Unit
MHz
%
STM32F469xx
Electrical characteristics
Table 64. SPI dynamic characteristics(1) (continued)
Symbol
Parameter
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode, SPI presc = 2
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4TPCLK
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2TPCLK
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
Conditions
Min
Typ
Max
TPCLK − 1.5
TPCLK
TPCLK+1.5
-
-
Master mode
2
-
-
Slave mode
3
-
-
Master mode
4
-
-
Slave mode
2
-
-
ta(SO)
Data output access time Slave mode, SPI presc = 2
7
-
21
tdis(SO)
Data output disable time Slave mode
5
-
12
Slave mode (after enable edge),
2.7V ≤ VDD ≤ 3.6V
-
11
15
Slave mode (after enable edge),
1.71 V≤VDD≤3.6 V
-
11
11.5
tv(SO)
Data output valid time
th(SO)
Data output hold time
Slave mode (after enable edge)
6
-
-
tv(MO)
Data output valid time
Master mode (after enable edge)
-
4.5
5
th(MO)
Data output hold time
Master mode (after enable edge)
2
-
-
Unit
ns
1. Guaranteed based on test during characterization.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
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Figure 40. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
th(NSS)
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
B I T1 IN
M SB IN
LSB IN
th(SI)
ai14134c
Figure 41. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
M SB IN
B I T1 IN
LSB IN
ai14135
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Electrical characteristics
Figure 42. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
SCK Input
tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
MS BIN
tr(SCK)
tf(SCK)
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
tv(MO)
B I T1 OUT
LSB OUT
th(MO)
ai14136
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I2S interface characteristics
Unless otherwise specified, the parameters given in Table 65 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(CK, SD, WS).
Table 65. I2S dynamic characteristics(1)
Symbol
Parameter
fMCK
I2S Main clock output
fCK
I2S clock frequency
DCK
Conditions
Min
Max
256x8K
256xFs(2)
Master data
-
64xFs
Slave data
-
64xFs
30
70
-
I2S clock frequency duty cycle Slave receiver
tv(WS)
WS valid time
Master mode
0
5
th(WS)
WS hold time
Master mode
0
-
Slave mode
3.5
-
tsu(WS)
WS setup time
Slave mode
PCM short pulse mode(3)
3.5
-
Slave mode
0.5
-
th(WS)
WS hold time
Slave mode
PCM short pulse mode(3)
1
-
Master receiver
5
-
Slave receiver
1.5
-
Master receiver
5
-
Slave receiver
1.5
-
Slave transmitter (after enable edge)
-
19
Master transmitter (after enable edge)
-
2.50
Slave transmitter (after enable edge)
5
-
Master transmitter (after enable edge)
0
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Unit
MHz
%
ns
1. Guaranteed based on test during characterization.
2. 128xFs maximum is 24.756 MHz (APB1 Maximum frequency).
3. Measurement done with respect to I2S_CK rising edge.
Note:
Refer to the I2S section of RM0386 reference manual for more details on the sampling
frequency (FS).
fMCK, fCK, and DCK values reflect only the digital peripheral behavior, source clock precision
might slightly change the values. The values of these parameters might be slightly impacted
by the source clock precision. DCK depends mainly on the value of ODD bit. The digital
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Electrical characteristics
contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of
(I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition.
Figure 43. I2S slave timing diagram (Philips protocol)(1)
CK Input
tc(CK)
CPOL = 0
CPOL = 1
tw(CKH)
th(WS)
tw(CKL)
WS input
tv(SD_ST)
tsu(WS)
SDtransmit
LSB transmit(2)
MSB transmit
Bitn transmit
tsu(SD_SR)
LSB receive(2)
SDreceive
th(SD_ST)
LSB transmit
th(SD_SR)
MSB receive
Bitn receive
LSB receive
ai14881b
1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 44. I2S master timing diagram (Philips protocol)(1)
tf(CK)
tr(CK)
CK output
tc(CK)
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS)
th(WS)
tw(CKL)
WS output
tv(SD_MT)
SDtransmit
LSB transmit(2)
MSB transmit
LSB receive(2)
LSB transmit
th(SD_MR)
tsu(SD_MR)
SDreceive
Bitn transmit
th(SD_MT)
MSB receive
Bitn receive
LSB receive
ai14884b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
STM32F469xx
SAI characteristics
Unless otherwise specified, the parameters given in Table 66 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 17, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C=30 pF
•
Measurement points are performed at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function
characteristics (SCK,SD,WS).
Table 66. SAI characteristics(1)
Symbol
Parameter
Conditions
Min
Max
fMCKL
SAI Main clock output
-
256 x 8K
256xFs
fCK
SAI clock frequency(2)
Master data: 32 bits
-
128xFs(3)
Slave data: 32 bits
-
128xFs
Master mode,
2.7V ≤ VDD ≤ 3.6V
-
17
Master mode,
1.71V ≤ VDD ≤ 3.6V
-
23
tv(FS)
FS valid time
tsu(FS)
FS setup time
Slave mode
10
-
th(FS)
FS hold time
Slave mode
0
-
Master receiver
1
-
Slave receiver
2
-
Master receiver
6
-
Slave receiver
1
-
Slave transmitter (after enable edge),
2.7V ≤ VDD ≤ 3.6V
-
14
Slave transmitter (after enable edge),
1.71V ≤ VDD ≤ 3.6V
-
23
Slave transmitter (after enable edge)
9
-
Master transmitter (after enable edge),
2.7V ≤ VDD ≤ 3.6V
-
20
Master transmitter (after enable edge),
1.71V ≤ VDD ≤ 3.6V
-
26
Master transmitter (after enable edge)
10
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
th(SD_B_ST)
th(SD_B_ST)
tv(SD_A_MT)
th(SD_A_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
1. Guaranteed based on test during characterization.
2. APB clock frequency must be at least twice SAI clock frequency.
3. With Fs = 192 kHz.
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DocID028196 Rev 2
Unit
MHz
ns
STM32F469xx
Electrical characteristics
Figure 45. SAI master timing waveforms
F3#+
3!)?3#+?8
TH&3
3!)?&3?8
OUTPUT
TV&3
TH3$?-4
TV3$?-4
3!)?3$?8
TRANSMIT
3LOTN
TSU3$?-2
3LOTN
TH3$?-2
3!)?3$?8
RECEIVE
3LOTN
-36
Figure 46. SAI slave timing waveforms
F3#+
3!)?3#+?8
TW#+(?8
3!)?&3?8
INPUT
TW#+,?8
TH&3
TSU&3
TH3$?34
TV3$?34
3!)?3$?8
TRANSMIT
3LOTN
TSU3$?32
3!)?3$?8
RECEIVE
3LOTN
TH3$?32
3LOTN
-36
DocID028196 Rev 2
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Electrical characteristics
STM32F469xx
USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Table 67. USB OTG full speed startup time
Symbol
Parameter
Max
Unit
tSTARTUP(1)
USB OTG full speed transceiver startup time
1
µs
1. Guaranteed by design.
Table 68. USB OTG full speed DC electrical characteristics
Symbol
Conditions
USB OTG full speed
transceiver operating
voltage
Min.(1) Typ. Max.(1) Unit
-
3.0(2)
-
3.6
VDI(3) Differential input sensitivity
I(USB_FS_DP/DM,
USB_HS_DP/DM)
0.2
-
-
VCM(3)
Differential common mode
range
Includes VDI range
0.8
-
2.5
VSE(3)
Single ended receiver
threshold
-
1.3
-
2.0
VOL
Static output level low
RL of 1.5 kΩ to 3.6 V(4)
-
-
0.3
2.8
-
3.6
17
21
24
0.65
1.1
2.0
VDD
Input
levels
Parameter
Output
levels
RPD
RPU
VOH
Static output level high
RL of 15 kΩ to
PA11, PA12, PB14, PB15
(USB_FS_DP/DM,
USB_HS_DP/DM)
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VSS(4)
V
VIN = VDD
kΩ
PA12, PB15 (USB_FS_DP,
USB_HS_DP)
VIN = VSS
1.5
1.8
2.1
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
VIN = VSS
0.25
0.37
0.55
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3. Guaranteed by design.
4. RL is the load connected on the USB OTG full speed drivers.
Note:
146/208
When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Figure 47. USB OTG full speed timings: definition of data signal rise and fall time
Crossover
points
Differen tial
Data L ines
VCRS
VS S
tr
tf
ai14137
Table 69. USB OTG full speed electrical characteristics(1)
Driver characteristics
Symbol
tr
tf
trfm
Parameter
Rise time(2)
Fall
time(2)
Conditions
Min
Max
CL = 50 pF
4
20
CL = 50 pF
4
20
tr/tf
90
110
%
-
1.3
2.0
V
Driving
high or low
28
44
Ω
Rise/ fall time matching
VCRS
Output signal crossover voltage
ZDRV
Output driver impedance(3)
Unit
ns
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
USB high speed (HS) characteristics
Unless otherwise specified, the parameters given in Table 72 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 71
and VDD supply voltage conditions summarized in Table 70, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
•
Capacitive load C = 20 pF / 15 pF, unless otherwise specified
•
Measurement points are done at CMOS levels: 0.5 VDD.
Refer to Section 5.3.20 for more details on the input/output characteristics.
Table 70. USB HS DC electrical characteristics
Symbol
Input level
Parameter
VDD
USB OTG HS operating voltage
Min.(1)
Max.(1)
Unit
1.7
3.6
V
1. All the voltages are measured from the local ground potential.
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Electrical characteristics
STM32F469xx
Table 71. USB HS clock timing parameters(1)
Symbol
Parameter
Min
Typ
Max
-
fHCLK value to guarantee proper operation of
USB HS interface
30
-
-
FSTART_8BIT
Frequency (first transition)
54
60
66
FSTEADY
Frequency (steady state) ±500 ppm
59.97
60
60.03
DSTART_8BIT
Duty cycle (first transition)
40
50
60
DSTEADY
Duty cycle (steady state) ±500 ppm
49.975
50
50.025
tSTEADY
Time to reach the steady state frequency and
duty cycle after the first transition
-
-
1.4
Peripheral
-
-
5.6
Host
-
-
-
-
-
-
tSTART_DEV
tSTART_HOST
Clock startup time after the
de-assertion of SuspendM
8-bit ±10%
8-bit ±10%
PHY preparation time after the first transition
of the input clock
tPREP
Unit
MHz
%
ms
ms
µs
1. Guaranteed by design.
Figure 48. ULPI timing diagram
#LOCK
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5,0)?$)2
5,0)?.84
T3#
T(#
T3$
T($
DATA)N
BIT
T$#
#ONTROLOUT
5,0)?340
DATAOUT
BIT
T$#
T$$
AIC
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DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Table 72. Dynamic characteristics: USB ULPI(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
tSC
Control in (ULPI_DIR, ULPI_NXT)
setup time
-
2.0
-
-
tHC
Control in (ULPI_DIR, ULPI_NXT)
hold time
-
1.5
-
-
tSD
Data in setup time
-
1.0
-
-
tHD
Data in hold time
-
1.0
-
-
2.7 V < VDD < 3.6 V,
CL = 20 pF
-
7.5
9.0
2.7 V < VDD < 3.6 V,
CL = 15 pF and
-40 < T < 125°C
-
7.5
12.0
1.7 V < VDD < 3.6 V,
CL = 15 pF and
-40 < T < 90°C
-
7.5
11.5
tDC/tDD Data/control output delay
Unit
ns
1. Guaranteed based on test during characterization.
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 74, Table 75 and Table 76 for
SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK
frequency summarized in Table 17 and VDD supply voltage conditions summarized in
Table 73, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 VDD.
Refer to Section 5.3.20 for more details on the input/output characteristics.
Table 73. Ethernet DC electrical characteristics
Symbol
Input level
Parameter
VDD
Ethernet operating voltage
Min.(1)
Max.(1)
Unit
2.7
3.6
V
1. All the voltages are measured from the local ground potential.
Table 74 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 49 shows the corresponding timing diagram.
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Electrical characteristics
STM32F469xx
Figure 49. Ethernet SMI timing diagram
W0'&
(7+B0'&
WG0',2
(7+B0',22
WVX0',2
WK0',2
(7+B0',2,
069
Table 74. Dynamics characteristics: Ethernet MAC signals for SMI(1)
Symbol
tMDC
Parameter
MDC cycle time(2.38 MHz)
Min
Typ
Max
400
400
403
Td(MDIO)
Write data valid time
THCLK - 1
THCLK
THCLK + 1.5
tsu(MDIO)
Read data setup time
12.5
-
-
th(MDIO)
Read data hold time
0
-
-
1. Guaranteed based on test during characterization.
Table 75 gives the list of Ethernet MAC signals for the RMII and Figure 50 shows the
corresponding timing diagram.
Figure 50. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667
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DocID028196 Rev 2
Unit
ns
STM32F469xx
Electrical characteristics
Table 75. Dynamics characteristics: Ethernet MAC signals for RMII(1)
Symbol
Parameter
Min
Typ
Max
tsu(RXD)
Receive data setup time
2.5
-
-
tih(RXD)
Receive data hold time
2.0
-
-
tsu(CRS)
Carrier sense setup time
0.5
-
-
tih(CRS)
Carrier sense hold time
1.5
-
-
td(TXEN)
Transmit enable valid delay time
5.5
6.5
11
td(TXD)
Transmit data valid delay time
6.0
6.5
11
Unit
ns
1. Guaranteed based on test during characterization.
Table 76 gives the list of Ethernet MAC signals for MII and Figure 50 shows the
corresponding timing diagram.
Figure 51. Ethernet MII timing diagram
MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
tsu(RXD)
tsu(ER)
tsu(DV)
tih(RXD)
tih(ER)
tih(DV)
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668
Table 76. Dynamics characteristics: Ethernet MAC signals for MII(1)
Symbol
Parameter
Min
Typ
Max
tsu(RXD)
Receive data setup time
1
-
-
tih(RXD)
Receive data hold time
3
-
-
tsu(DV)
Data valid setup time
0
-
-
tih(DV)
Data valid hold time
2.5
-
-
tsu(ER)
Error setup time
0
-
-
tih(ER)
Error hold time
2
-
-
td(TXEN)
Transmit enable valid delay time
0
7
13
td(TXD)
Transmit data valid delay time
0
7
13
Unit
ns
1. Guaranteed based on test during characterization.
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Electrical characteristics
STM32F469xx
CAN (controller area network) interface
Refer to Section 5.3.20 for more details on the input/output alternate function characteristics
(CANx_TX and CANx_RX).
5.3.24
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 77 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 17.
Table 77. ADC characteristics
Symbol
VDDA
VREF+
fADC
fTRIG(2)
VAIN
RAIN(2)
Parameter
Power supply
Positive reference voltage
ADC clock frequency
External trigger frequency
Conversion voltage range(3)
External input impedance
RADC(2)(4) Sampling switch resistance
CADC(2)
Internal sample and hold
capacitor
Conditions
Min
Typ
Max
1.7(1)
-
3.6
1.7(1)
-
VDDA
VDDA = 1.7(1) to 2.4 V
0.6
15
18
VDDA = 2.4 to 3.6 V
0.6
30
36
fADC = 30 MHz,
12-bit resolution
-
-
1764
kHz
-
-
-
17
1/fADC
-
0
(VSSA or VREFtied to ground)
-
VREF+
V
Details in Equation 1
-
-
50
kΩ
-
-
-
6
kΩ
-
-
4
7
pF
-
-
0.100
µs
1/fADC
VDDA −VREF+ < 1.2 V
Unit
V
MHz
tlat(2)
Injection trigger conversion
latency
fADC = 30 MHz
-
-
-
3(5)
tlatr(2)
Regular trigger conversion
latency
fADC = 30 MHz
-
-
0.067
µs
-
-
2(5)
1/fADC
tS(2)
Sampling time
fADC = 30 MHz
0.100
-
16
µs
-
3
-
480
1/fADC
tSTAB(2)
Power-up time
-
-
2
3
µs
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DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Table 77. ADC characteristics (continued)
Symbol
tCONV(2)
Parameter
Total conversion time
(including sampling time)
Conditions
Min
Typ
Max
fADC = 30 MHz
12-bit resolution
0.50
-
16.40
fADC = 30 MHz
10-bit resolution
0.43
-
16.34
fADC = 30 MHz
8-bit resolution
0.37
-
16.27
fADC = 30 MHz
6-bit resolution
0.30
-
16.20
Unit
µs
9 to 492
1/fADC
(tS for sampling +n-bit resolution for successive approximation)
Sampling rate
fS(2)
(fADC = 30 MHz, and
tS = 3 ADC cycles)
12-bit resolution
Single ADC
-
-
2
12-bit resolution
Interleave Dual ADC
mode
-
-
3.75
12-bit resolution
Interleave Triple ADC
mode
-
-
6
Msps
IVREF+(2)
ADC VREF
DC current consumption in
conversion mode
-
-
300
500
µA
IVDDA(2)
ADC VDDA
DC current consumption in
conversion mode
-
-
1.6
1.8
mA
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
2. Based on test during characterization.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 77.
Equation 1: RAIN max formula
R AIN
( k – 0.5 )
- – R ADC
= --------------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
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Electrical characteristics
STM32F469xx
Table 78. ADC static accuracy at fADC = 18 MHz(1)
Symbol
Parameter
Test conditions
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fADC =18 MHz
VDDA = 1.7 to 3.6 V
VREF = 1.7 to 3.6 V
VDDA −VREF < 1.2 V
Typ
Max(2)
±3
±4
±2
±3
±1
±3
±1
±2
±2
±3
Unit
LSB
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Based on test during characterization.
Table 79. ADC static accuracy at fADC = 30 MHz(1)
a
Symbol
ET
Parameter
Test conditions
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fADC = 30 MHz,
RAIN < 10 kΩ,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V,
VDDA −VREF < 1.2 V
Typ
Max(2)
±2
±5
±1.5
±2.5
±1.5
±3
±1
±2
±1.5
±3
Unit
LSB
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Based on test during characterization.
Table 80. ADC static accuracy at fADC = 36 MHz(1)
Symbol
ET
Parameter
Test conditions
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fADC =36 MHz,
VDDA = 2.4 to 3.6 V,
VREF = 1.7 to 3.6 V
VDDA −VREF < 1.2 V
Typ
Max(2)
±4
±7
±2
±3
±3
±6
±2
±3
±3
±6
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
2. Based on test during characterization.
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DocID028196 Rev 2
Unit
LSB
STM32F469xx
Electrical characteristics
Table 81. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol
Parameter
Test conditions
ENOB
Effective number of bits
SINAD
Signal-to-noise and distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
fADC =18 MHz
VDDA = VREF+= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
Min
Typ
Max
Unit
10.3
10.4
-
bits
64
64.2
-
64
65
-
− 67
− 72
-
dB
1. Guaranteed based on test during characterization.
Table 82. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol
Parameter
Test conditions
ENOB
Effective number of bits
SINAD
Signal-to noise and distortion ratio
SNR
Signal-to noise ratio
THD
Total harmonic distortion
fADC =36 MHz
VDDA = VREF+ = 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
Min
Typ
Max
Unit
10.6
10.8
-
bits
66
67
-
64
68
-
− 70
− 72
-
dB
1. Guaranteed based on test during characterization.
Note:
ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 5.3.20 does not affect the ADC accuracy.
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Electrical characteristics
STM32F469xx
Figure 52. ADC accuracy characteristics
6 $$!
6 2%&
;,3" )$%!, ORDEPENDINGONPACKAGE=
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1. See also Table 79.
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 53. Typical connection diagram using the ADC
670)
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FRQYHUWHU
97
9
5$'&
97
9
,/“—$
ELW
FRQYHUWHU
& $'&
DL
1. Refer to Table 77 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
156/208
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 54 or Figure 55,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 54. Power supply and reference decoupling (VREF+ not connected to VDDA)
670)
95()
—)Q)
9''$
—)Q)
966$95()
069
1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144,
and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA.
Figure 55. Power supply and reference decoupling (VREF+ connected to VDDA)
670)
95()9''$
—)Q)
95()9''$
069
1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144,
and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA.
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187
Electrical characteristics
5.3.25
STM32F469xx
Temperature sensor characteristics
Table 83. Temperature sensor characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VSENSE linearity with temperature
-
±1
±2
°C
Average slope
-
2.5
-
mV/°C
Voltage at 25 °C
-
0.76
-
V
tSTART(2)
Startup time
-
6
10
TS_temp(2)
ADC sampling time when reading the temperature (1 °C accuracy)
10
-
-
TL(1)
Avg_Slope
(1)
V25(1)
µs
1. Based on test during characterization.
2. Guaranteed by design.
Table 84. Temperature sensor calibration values
Symbol
Parameter
Memory address
TS_CAL1
TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V
0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL2
TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V
0x1FFF 7A2E - 0x1FFF 7A2F
5.3.26
VBAT monitoring characteristics
Table 85. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
KΩ
R
Resistor bridge for VBAT
-
50
-
Q
Ratio on VBAT measurement
-
4
-
Error on Q
–1
-
+1
%
ADC sampling time when reading the VBAT
1 mV accuracy
5
-
-
µs
Er(1)
TS_vbat(2)(2)
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
5.3.27
Reference voltage
The parameters given in Table 86 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.
Table 86. internal reference voltage
Symbol
VREFINT
TS_vrefint(1)
VRERINT_s(2)
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Parameter
Internal reference voltage
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C
1.18
1.21
1.24
V
10
-
-
µs
-
3
5
mV
ADC sampling time when reading the
internal reference voltage
Internal reference voltage spread over the
temperature range
VDD = 3V ± 10mV
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Table 86. internal reference voltage (continued)
Symbol
Parameter
TCoeff(2)
tSTART
(2)
Conditions
Min
Typ
Max
Unit
Temperature coefficient
-
30
50
ppm/°C
Startup time
-
6
10
µs
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design
Table 87. Internal reference voltage calibration values
Symbol
Parameter
VREFIN_CAL
5.3.28
Memory address
Raw data acquired at temperature of 30 °C VDDA = 3.3 V
0x1FFF 7A2A - 0x1FFF 7A2B
DAC electrical characteristics
Table 88. DAC characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Comments
-
VDDA
Analog supply voltage
1.7(1)
-
3.6
V
VREF+
Reference supply voltage
1.7(1)
-
3.6
V
VSSA
Ground
0
-
0
V
-
RLOAD(2)
Resistive load with buffer ON
5
-
-
kΩ
-
RO(2)
Impedance output with buffer
OFF
-
-
15
When the buffer is OFF, the Minimum
kΩ resistive load between DAC_OUT and
VSS to have a 1% accuracy is 1.5 MΩ
Capacitive load
-
-
50
pF
DAC_OUT Lower DAC_OUT voltage
with buffer ON
min(2)
0.2
-
-
V
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer ON
-
-
VDDA −
0.2
V
DAC_OUT Lower DAC_OUT voltage
with buffer OFF
min(2)
-
0.5
-
mV
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer OFF
-
-
VREF+ −
1LSB
V
-
170
240
CLOAD(2)
IVREF+(4)
DAC DC VREF current
consumption in quiescent
mode (Standby mode)
µA
-
50
75
DocID028196 Rev 2
VREF+ ≤VDDA
Maximum capacitive load at DAC_OUT
pin (when the buffer is ON).
It gives the maximum output excursion of
the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V and
(0x1C7) to (0xE38) at VREF+ = 1.7 V
It gives the maximum output excursion of
the DAC.
With no load, worst code (0x800) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
159/208
187
Electrical characteristics
STM32F469xx
Table 88. DAC characteristics (continued)
Symbol
Min
Typ
Max
Unit
Comments
-
280
380
µA
With no load, middle code (0x800) on the
inputs
-
475
625
µA
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
Differential non linearity
Difference between two
consecutive code-1LSB)
-
-
±0.5
LSB Given for the DAC in 10-bit configuration.
-
-
±2
LSB Given for the DAC in 12-bit configuration.
-
-
±1
LSB Given for the DAC in 10-bit configuration.
INL(4)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
-
-
±4
LSB Given for the DAC in 12-bit configuration.
-
-
±10
mV Given for the DAC in 12-bit configuration
Offset(4)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
-
-
±3
LSB
Given for the DAC in 10-bit at VREF+ =
3.6 V
-
-
±12
LSB
Given for the DAC in 12-bit at VREF+ =
3.6 V
Gain error
-
-
±0.5
%
Given for the DAC in 12-bit configuration
-
3
6
µs
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
IDDA(4)
DNL(4)
Gain
error(4)
Parameter
DAC DC VDDA current
consumption in quiescent
mode(3)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
(4)
tSETTLING
highest input codes when
DAC_OUT reaches final
value ±4LSB
THD(4)
Total Harmonic Distortion
Buffer ON
-
-
-
dB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
Update
rate(2)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-
-
1
MS/s
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
Wakeup time from off state
tWAKEUP(4) (Setting the ENx bit in the
DAC Control register)
-
6.5
10
µs
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and highest
possible ones.
Power supply rejection ratio
PSRR+ (2) (to VDDA) (static DC
measurement)
-
–67
–40
dB
No RLOAD, CLOAD = 50 pF
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2).
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed based on test during characterization.
160/208
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Figure 56. 12-bit buffered/non-buffered DAC
%XIIHUHG1RQEXIIHUHG'$&
%XIIHU
5/
'$&B287[
ELW
GLJLWDOWR
DQDORJ
FRQYHUWHU
&/
DL9
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
5.3.29
FMC characteristics
Unless otherwise specified, the parameters given in Tables 89 through 102 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 17, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output characteristics.
Asynchronous waveforms and timings
Figures 57 through 60 represent asynchronous waveforms, and Tables 89 through 96
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
•
AddressSetupTime = 0x1
•
AddressHoldTime = 0x1
•
DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
•
BusTurnAroundDuration = 0x0
•
Capacitive load CL = 30 pF
DocID028196 Rev 2
161/208
187
Electrical characteristics
STM32F469xx
Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
TW.%
&-#?.%
TV./%?.%
T W./%
T H.%?./%
&-#?./%
&-#?.7%
TV!?.%
&-#?!;=
T H!?./%
!DDRESS
TV",?.%
T H",?./%
&-#?.",;=
T H$ATA?.%
T SU$ATA?./%
TH$ATA?./%
T SU$ATA?.%
$ATA
&-#?$;=
T V.!$6?.%
TW.!$6
&-#?.!$6
&-#?.7!)4
TH.%?.7!)4
TSU.7!)4?.%
-36
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
162/208
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings(1)
Symbol
Min
Max
2THCLK − 0.5
2 THCLK+0.5
0
1
2THCLK
2THCLK+ 0.5
FMC_NOE high to FMC_NE high hold time
0
-
FMC_NEx low to FMC_A valid
-
2
th(A_NOE)
Address hold time after FMC_NOE high
0
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
-
2
th(BL_NOE)
FMC_BL hold time after FMC_NOE high
0
-
tsu(Data_NE)
Data to FMC_NEx high setup time
THCLK + 2.5
-
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
Parameter
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
tsu(Data_NOE)
Data to FMC_NOEx high setup time
THCLK +2
-
th(Data_NOE)
Data hold time after FMC_NOE high
0
-
th(Data_NE)
Data hold time after FMC_NEx high
0
-
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
-
0
FMC_NADV low time
-
THCLK +1
tw(NADV)
Unit
ns
1. Based on test during characterization.
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT
timings(1)
Symbol
Min
Max
FMC_NE low time
7THCLK+0.5
7THCLK+1
FMC_NWE low time
5THCLK − 1.5
5THCLK +2
tsu(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high
5THCLK+1.5
-
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
4THCLK+1
-
tw(NE)
tw(NOE)
Parameter
Unit
ns
1. Based on test during characterization.
DocID028196 Rev 2
163/208
187
Electrical characteristics
STM32F469xx
Figure 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
TW.%
&-#?.%X
&-#?./%
TV.7%?.%
TW.7%
T H.%?.7%
&-#?.7%
TV!?.%
&-#?!;=
TH!?.7%
!DDRESS
TV",?.%
&-#?.",;=
TH",?.7%
.",
TV$ATA?.%
TH$ATA?.7%
$ATA
&-#?$;=
T V.!$6?.%
&-#?.!$6 TW.!$6
&-#?.7!)4
TH.%?.7!)4
TSU.7!)4?.%
-36
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
th(A_NWE)
Address hold time after FMC_NWE high
tv(BL_NE)
FMC_NEx low to FMC_BL valid
Max
3THCLK
3THCLK+1
THCLK − 0.5
THCLK+ 0.5
THCLK
THCLK+ 0.5
THCLK +1.5
-
-
0
THCLK+0.5
-
-
1.5
THCLK+0.5
-
th(BL_NWE)
FMC_BL hold time after FMC_NWE high
tv(Data_NE)
Data to FMC_NEx low to Data valid
-
THCLK+ 2
th(Data_NWE)
Data hold time after FMC_NWE high
THCLK+0.5
-
tv(NADV_NE)
FMC_NEx low to FMC_NADV low
-
0.5
FMC_NADV low time
-
THCLK+ 0.5
tw(NADV)
1. Based on test during characterization.
164/208
Min
DocID028196 Rev 2
Unit
ns
STM32F469xx
Electrical characteristics
Table 92. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT
timings(1)
Symbol
tw(NE)
tw(NWE)
Parameter
Min
Max
FMC_NE low time
8THCLK+1
8THCLK+2
FMC_NWE low time
6THCLK − 1
6THCLK+2
6THCLK+1.5
-
4THCLK+1
-
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid
Unit
ns
1. Based on test during characterization.
Figure 59. Asynchronous multiplexed PSRAM/NOR read waveforms
TW.%
&-#? .%
TV./%?.%
T H.%?./%
&-#?./%
T W./%
&-#?.7%
TH!?./%
TV!?.%
&-#? !;=
!DDRESS
TV",?.%
TH",?./%
&-#? .",;=
.",
TH$ATA?.%
TSU$ATA?.%
T V!?.%
&-#? !$;=
TSU$ATA?./%
TH$ATA?./%
$ATA
!DDRESS
TH!$?.!$6
T V.!$6?.%
TW.!$6
&-#?.!$6
&-#?.7!)4
TH.%?.7!)4
TSU.7!)4?.%
-36
DocID028196 Rev 2
165/208
187
Electrical characteristics
STM32F469xx
Table 93. Asynchronous multiplexed PSRAM/NOR read timings(1)
Symbol
tw(NE)
tv(NOE_NE)
ttw(NOE)
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
Parameter
Min
Max
3THCLK − 1
3THCLK+0.5
2THCLK − 0.5
2THCLK
THCLK − 1
THCLK+1
FMC_NOE high to FMC_NE high hold time
1
-
FMC_NEx low to FMC_A valid
-
2
FMC_NEx low to FMC_NADV low
0
2
THCLK − 0.5
THCLK+0.5
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
FMC_NADV low time
th(AD_NADV)
FMC_AD(address) valid hold time after
FMC_NADV high)
0
-
th(A_NOE)
Address hold time after FMC_NOE high
THCLK − 0.5
-
th(BL_NOE)
FMC_BL time after FMC_NOE high
0
-
FMC_NEx low to FMC_BL valid
-
2
tv(BL_NE)
tsu(Data_NE)
Data to FMC_NEx high setup time
THCLK+1.5
-
tsu(Data_NOE)
Data to FMC_NOE high setup time
THCLK+1
-
th(Data_NE)
Data hold time after FMC_NEx high
0
-
th(Data_NOE)
Data hold time after FMC_NOE high
0
-
Unit
ns
1. Based on test during characterization.
Table 94. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)
Symbol
tw(NE)
tw(NOE)
Parameter
Min
Max
FMC_NE low time
8THCLK+0.5
8THCLK+2
FMC_NWE low time
5THCLK − 1
5THCLK +1.5
5THCLK +1.5
-
4THCLK+1
-
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid
1. Based on test during characterization.
166/208
DocID028196 Rev 2
Unit
ns
STM32F469xx
Electrical characteristics
Figure 60. Asynchronous multiplexed PSRAM/NOR write waveforms
TW.%
&-#? .%X
&-#?./%
TV.7%?.%
TW.7%
T H.%?.7%
&-#?.7%
TH!?.7%
TV!?.%
&-#? !;=
!DDRESS
TV",?.%
TH",?.7%
&-#? .",;=
.",
T V!?.%
T V$ATA?.!$6
!DDRESS
&-#? !$;=
TH$ATA?.7%
$ATA
TH!$?.!$6
T V.!$6?.%
TW.!$6
&-#?.!$6
&-#?.7!)4
TH.%?.7!)4
TSU.7!)4?.%
-36
Table 95. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol
tw(NE)
tv(NWE_NE)
tw(NWE)
th(NE_NWE)
tv(A_NE)
Parameter
Min
Max
4THCLK
4THCLK+0.5
THCLK − 1
THCLK+0.5
FMC_NWE low time
2THCLK
2THCLK+0.5
FMC_NWE high to FMC_NE high hold time
THCLK
-
-
0
0.5
1
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NEx low to FMC_A valid
tv(NADV_NE) FMC_NEx low to FMC_NADV low
tw(NADV)
FMC_NADV low time
FMC_AD (address) valid hold time
th(AD_NADV)
after FMC_NADV high
Unit
THCLK − 0.5 THCLK+ 0.5
THCLK − 2
-
th(A_NWE)
Address hold time after FMC_NWE high
THCLK
-
th(BL_NWE)
FMC_BL hold time after FMC_NWE high
THCLK − 2
-
-
2
-
THCLK +1.5
THCLK +0.5
-
tv(BL_NE)
FMC_NEx low to FMC_BL valid
tv(Data_NADV) FMC_NADV high to Data valid
th(Data_NWE) Data hold time after FMC_NWE high
ns
1. Based on test during characterization.
DocID028196 Rev 2
167/208
187
Electrical characteristics
STM32F469xx
Table 96. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)
Symbol
tw(NE)
tw(NWE)
Parameter
Min
Max
FMC_NE low time
9THCLK
9THCLK+0.5
FMC_NWE low time
7THCLK
7THCLK+2
6THCLK+1.5
-
4THCLK–1
-
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high
th(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT invalid
Unit
ns
1. Based on test during characterization.
Synchronous waveforms and timings
Figures 61 through 64 represent synchronous waveforms and Table 97 through Table 100
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable;
•
MemoryType = FMC_MemoryType_CRAM;
•
WriteBurst = FMC_WriteBurst_Enable;
•
CLKDivision = 1;
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
•
CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period:
168/208
•
For 2.7 V≤ VDD≤ 3.6 V, maximum FMC_CLK = 90 MHz at CL = 30 pF (on FMC_CLK).
•
For 1.71 V≤ VDD<1.9 V, maximum FMC_CLK = 60 MHz at CL = 10 pF (on FMC_CLK).
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Figure 61. Synchronous multiplexed NOR/PSRAM read timings
"53452.
TW#,+
TW#,+
&-#?#,+
$ATALATENCY
TD#,+,.%X,
&-#?.%X
T D#,+,.!$6,
TD#,+(.%X(
TD#,+,.!$6(
&-#?.!$6
TD#,+,!6
TD#,+(!)6
&-#?!;=
TD#,+,./%,
TD#,+(./%(
&-#?./%
T D#,+,!$6
&-#?!$;=
TD#,+,!$)6
TSU!$6#,+(
!$;=
TH#,+(!$6
TSU!$6#,+(
$
TSU.7!)46#,+(
&-#?.7!)4
7!)4#&'B
7!)40/,B
&-#?.7!)4
7!)4#&'B
7!)40/,B
TSU.7!)46#,+(
TSU.7!)46#,+(
TH#,+(!$6
$
TH#,+(.7!)46
TH#,+(.7!)46
TH#,+(.7!)46
-36
DocID028196 Rev 2
169/208
187
Electrical characteristics
STM32F469xx
Table 97. Synchronous multiplexed NOR/PSRAM read timings(1)
Symbol
Min
Max
2THCLK − 1
-
-
0
THCLK
-
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
-
0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
0
-
tw(CLK)
Parameter
FMC_CLK period
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
td(CLKH_NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
0
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
0
-
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
-
THCLK+0.5
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
THCLK − 0.5
-
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
0.5
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
tsu(ADV-CLKH)
FMC_A/D[15:0] valid data before FMC_CLK high
5
-
th(CLKH-ADV)
FMC_A/D[15:0] valid data after FMC_CLK high
0
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
4
-
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
0
-
1. Based on test during characterization.
170/208
DocID028196 Rev 2
Unit
ns
STM32F469xx
Electrical characteristics
Figure 62. Synchronous multiplexed PSRAM write timings
"53452.
TW#,+
TW#,+
&-#?#,+
$ATALATENCY
TD#,+,.%X,
TD#,+(.%X(
&-#?.%X
TD#,+,.!$6,
TD#,+,.!$6(
&-#?.!$6
TD#,+(!)6
TD#,+,!6
&-#?!;=
TD#,+(.7%(
TD#,+,.7%,
&-#?.7%
TD#,+,!$)6
TD#,+,!$6
&-#?!$;=
TD#,+,$ATA
TD#,+,$ATA
!$;=
$
$
&-#?.7!)4
7!)4#&'B
7!)40/,B
TSU.7!)46#,+(
TH#,+(.7!)46
TD#,+(.",(
&-#?.",
-36
DocID028196 Rev 2
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187
Electrical characteristics
STM32F469xx
Table 98. Synchronous multiplexed PSRAM write timings(1)
Symbol
Parameter
Max
tw(CLK)
FMC_CLK period, VDD range= 2.7 to 3.6 V
2THCLK − 1
-
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0…2)
-
1.5
td(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
THCLK
-
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
-
0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
0
-
-
0
THCLK
-
-
0
THCLK −0.5
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
td(CLKL-NWEL)
FMC_CLK low to FMC_NWE low
t(CLKH-NWEH)
FMC_CLK high to FMC_NWE high
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
3
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
td(CLKL-DATA)
FMC_A/D[15:0] valid data after FMC_CLK low
-
3
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
0
-
td(CLKH-NBLH)
FMC_CLK high to FMC_NBL high
THCLK −0.5
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
4
-
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
0
-
1. Based on test during characterization.
172/208
Min
DocID028196 Rev 2
Unit
ns
STM32F469xx
Electrical characteristics
Figure 63. Synchronous non-multiplexed NOR/PSRAM read timings
TW#,+
TW#,+
&-#?#,+
TD#,+,.%X,
TD#,+(.%X(
$ATALATENCY
&-#?.%X
TD#,+,.!$6,
TD#,+,.!$6(
&-#?.!$6
TD#,+(!)6
TD#,+,!6
&-#?!;=
TD#,+,./%,
TD#,+(./%(
&-#?./%
TSU$6#,+(
TH#,+($6
TSU$6#,+(
&-#?$;=
TH#,+($6
$
TSU.7!)46#,+(
&-#?.7!)4
7!)4#&'B
7!)40/,B
$
TH#,+(.7!)46
TSU.7!)46#,+(
&-#?.7!)4
7!)4#&'B
7!)40/,B
TSU.7!)46#,+(
T H#,+(.7!)46
TH#,+(.7!)46
-36
Table 99. Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol
Min
Max
2THCLK − 1
-
-
0.5
THCLK
-
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
-
0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
0
-
-
0
THCLK − 0.5
-
-
THCLK+2
THCLK − 0.5
-
tw(CLK)
t(CLKL-NExL)
td(CLKH-NExH)
Parameter
FMC_CLK period
FMC_CLK low to FMC_NEx low (x=0…2)
FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
td(CLKL-NOEL)
FMC_CLK low to FMC_NOE low
td(CLKH-NOEH)
FMC_CLK high to FMC_NOE high
tsu(DV-CLKH)
FMC_D[15:0] valid data before FMC_CLK high
5
-
th(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK high
0
-
FMC_NWAIT valid before FMC_CLK high
4
-
0
-
t(NWAIT-CLKH)
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
Unit
ns
1. Based on test during characterization.
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Electrical characteristics
STM32F469xx
Figure 64. Synchronous non-multiplexed PSRAM write timings
TW#,+
TW#,+
&-#?#,+
TD#,+,.%X,
TD#,+(.%X(
$ATALATENCY
&-#?.%X
TD#,+,.!$6,
TD#,+,.!$6(
&-#?.!$6
TD#,+(!)6
TD#,+,!6
&-#?!;=
TD#,+,.7%,
TD#,+(.7%(
&-#?.7%
TD#,+,$ATA
&-#?$;=
TD#,+,$ATA
$
$
&-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TD#,+(.",(
TH#,+(.7!)46
&-#?.",
-36
Table 100. Synchronous non-multiplexed PSRAM write timings(1)
Symbol
Min
Max
2THCLK − 1
-
-
0.5
THCLK
-
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
-
0
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
0
-
t(CLK)
Parameter
FMC_CLK period
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0…2)
t(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2)
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
0
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
0
-
FMC_CLK low to FMC_NWE low
-
0
THCLK −0.5
-
td(CLKL-NWEL)
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
td(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK low
-
2.5
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
0
-
td(CLKH-NBLH)
FMC_CLK high to FMC_NBL high
THCLK −0.5
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
4
-
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
0
-
1. Based on test during characterization.
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Unit
ns
STM32F469xx
Electrical characteristics
NAND controller waveforms and timings
Figures 65 through 68 represent synchronous waveforms, and Table 101 and Table 102
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
•
COM.FMC_SetupTime = 0x01;
•
COM.FMC_WaitSetupTime = 0x03;
•
COM.FMC_HoldSetupTime = 0x02;
•
COM.FMC_HiZSetupTime = 0x01;
•
ATT.FMC_SetupTime = 0x01;
•
ATT.FMC_WaitSetupTime = 0x03;
•
ATT.FMC_HoldSetupTime = 0x02;
•
ATT.FMC_HiZSetupTime = 0x01;
•
Bank = FMC_Bank_NAND;
•
MemoryDataWidth = FMC_MemoryDataWidth_16b;
•
ECC = FMC_ECC_Enable;
•
ECCPageSize = FMC_ECCPageSize_512Bytes;
•
TCLRSetupTime = 0;
•
TARSetupTime = 0;
•
Capacitive load CL = 30 pF.
In all timing tables, the THCLK is the HCLK clock period.
Figure 65. NAND controller waveforms for read access
&-#?.#%X
!,%&-#?!
#,%&-#?!
&-#?.7%
TD!,%./%
TH./%!,%
&-#?./%.2%
TSU$./%
TH./%$
&-#?$;=
-36
DocID028196 Rev 2
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187
Electrical characteristics
STM32F469xx
Figure 66. NAND controller waveforms for write access
&-#?.#%X
!,%&-#?!
#,%&-#?!
TH.7%!,%
TD!,%.7%
&-#?.7%
&-#?./%.2%
TH.7%$
TV.7%$
&-#?$;=
-36
Figure 67. NAND controller waveforms for common memory read access
&-#?.#%X
!,%&-#?!
#,%&-#?!
TH./%!,%
TD!,%./%
&-#?.7%
TW./%
&-#?./%
TSU$./%
TH./%$
&-#?$;=
-36
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DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Figure 68. NAND controller waveforms for common memory write access
&-#?.#%X
!,%&-#?!
#,%&-#?!
TD!,%./%
TW.7%
TH./%!,%
&-#?.7%
&-#?. /%
TD$.7%
TV.7%$
TH.7%$
&-#?$;=
-36
Table 101. Switching characteristics for NAND Flash read cycles
Symbol
Parameter
Max
Unit
4THCLK − 0.5 4THCLK+0.5
FMC_NOE low width
tw(N0E)
Min
tsu(D-NOE)
FMC_D[15-0] valid data before FMC_NOE high
9
-
th(NOE-D)
FMC_D[15-0] valid data after FMC_NOE high
0
-
td(ALE-NOE)
FMC_ALE valid before FMC_NOE low
-
3THCLK − 0.5
th(NOE-ALE)
FMC_NWE high to FMC_ALE invalid
3THCLK − 2
-
ns
Table 102. Switching characteristics for NAND Flash write cycles
Symbol
tw(NWE)
Parameter
FMC_NWE low width
Min
Max
4THCLK
4THCLK+1
0
-
Unit
tv(NWE-D)
FMC_NWE low to FMC_D[15-0] valid
th(NWE-D)
FMC_NWE high to FMC_D[15-0] invalid
3THCLK − 1
-
td(D-NWE)
FMC_D[15-0] valid before FMC_NWE high
5THCLK − 3
-
-
3THCLK −0.5
3THCLK − 1
-
td(ALE-NWE)
FMC_ALE valid before FMC_NWE low
th(NWE-ALE)
FMC_NWE high to FMC_ALE invalid
ns
SDRAM waveforms and timings
•
CL = 30 pF on data and address lines.
•
CL = 10 pF on FMC_SDCLK unless otherwise specified.
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Electrical characteristics
STM32F469xx
In all timing tables, the THCLK is the HCLK clock period.
•
For 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_SDCLK = 90 MHz, at CL = 30 pF (on
FMC_SDCLK).
•
For 1.71 V≤ VDD <1.9 V, maximum FMC_SDCLK = 75 MHz when CAS Latency = 3 and
60 MHz for CAS latency 1 or 2. CL = 10 pF (on FMC_SDCLK).
Figure 69. SDRAM read access waveforms (CL = 1)
&-#?3$#,+
TD3$#,+,?!DD#
TH3$#,+,?!DD2
TD3$#,+,?!DD2
&-#?!>@
2OWN
#OL
#OL
#OLI
#OLN
TH3$#,+,?!DD#
TH3$#,+,?3.$%
TD3$#,+,?3.$%
&-#?3$.%;=
TD3$#,+,?.2!3
TH3$#,+,?.2!3
&-#?3$.2!3
TH3$#,+,?.#!3
TD3$#,+,?.#!3
&-#?3$.#!3
&-#?3$.7%
TSU3$#,+(?$ATA
TH3$#,+(?$ATA
$ATA
&-#?$;=
$ATA
$ATAI
$ATAN
-36
Table 103. SDRAM read timings(1)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
tsu(SDCLKH _Data)
Data input setup time
2
-
th(SDCLKH_Data)
Data input hold time
0
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL- SDNE)
Chip select valid time
-
0.5
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
0.5
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
0.5
th(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
1. Guaranteed based on test during characterization.
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Unit
ns
STM32F469xx
Electrical characteristics
Table 104. LPSDR SDRAM read timings(1)
Symbol
Parameter
Min
Max
tW(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
tsu(SDCLKH_Data)
Data input setup time
2.5
-
th(SDCLKH_Data)
Data input hold time
0
-
td(SDCLKL_Add)
Address valid time
-
1
td(SDCLKL_SDNE)
Chip select valid time
-
1
th(SDCLKL_SDNE)
Chip select hold time
1
-
td(SDCLKL_SDNRAS
SDNRAS valid time
-
1
th(SDCLKL_SDNRAS)
SDNRAS hold time
1
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
1
th(SDCLKL_SDNCAS)
SDNCAS hold time
1
-
Unit
ns
1. Guaranteed based on test during characterization.
Figure 70. SDRAM write access waveforms
&-#?3$#,+
TD3$#,+,?!DD#
TH3$#,+,?!DD2
TD3$#,+,?!DD2
&-#?!>@
2OWN
#OL
#OL
#OLI
#OLN
TH3$#,+,?!DD#
TH3$#,+,?3.$%
TD3$#,+,?3.$%
&-#?3$.%;=
TH3$#,+,?.2!3
TD3$#,+,?.2!3
&-#?3$.2!3
TD3$#,+,?.#!3
TH3$#,+,?.#!3
TD3$#,+,?.7%
TH3$#,+,?.7%
&-#?3$.#!3
&-#?3$.7%
TD3$#,+,?$ATA
&-#?$;=
TD3$#,+,?.",
$ATA
$ATA
$ATAI
$ATAN
TH3$#,+,?$ATA
&-#?.",;=
-36
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Electrical characteristics
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Table 105. SDRAM write timings(1)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
td(SDCLKL _Data)
Data output valid time
-
2.5
th(SDCLKL _Data)
Data output hold time
3.5
-
td(SDCLKL_Add)
Address valid time
-
1.5
td(SDCLKL_SDNWE)
SDNWE valid time
-
1
th(SDCLKL_SDNWE)
SDNWE hold time
0
-
td(SDCLKL_ SDNE)
Chip select valid time
-
0.5
th(SDCLKL-_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
2
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
0.5
td(SDCLKL_SDNCAS)
SDNCAS hold time
0
-
td(SDCLKL_NBL)
NBL valid time
-
0.5
th(SDCLKL_NBL)
NBL output time
0
-
Unit
ns
1. Guaranteed based on test during characterization.
Table 106. LPSDR SDRAM write timings(1)
Symbol
Parameter
Min
Max
tw(SDCLK)
FMC_SDCLK period
2THCLK − 0.5
2THCLK+0.5
td(SDCLKL _Data)
Data output valid time
-
5
th(SDCLKL _Data)
Data output hold time
2
-
td(SDCLKL_Add)
Address valid time
-
2.8
td(SDCLKL-SDNWE)
SDNWE valid time
-
2
th(SDCLKL-SDNWE)
SDNWE hold time
1
-
td(SDCLKL- SDNE)
Chip select valid time
-
1.5
th(SDCLKL- SDNE)
Chip select hold time
1
-
td(SDCLKL-SDNRAS)
SDNRAS valid time
-
1.5
th(SDCLKL-SDNRAS)
SDNRAS hold time
1.5
-
td(SDCLKL-SDNCAS)
SDNCAS valid time
-
1.5
td(SDCLKL-SDNCAS)
SDNCAS hold time
1.5
-
td(SDCLKL_NBL)
NBL valid time
-
1.5
th(SDCLKL-NBL)
NBL output time
1.5
-
1. Guaranteed based on test during characterization.
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Unit
ns
STM32F469xx
5.3.30
Electrical characteristics
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 107 and Table 108 for Quad-SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table xx, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output alternate function
characteristics.
Table 107. Quad-SPI characteristics in SDR mode(1)
Symbol
Parameter
Test conditions
Min
Typ
Max
Fck
1/t(CK)
Quad-SPI clock frequency
tw(CKH)
Unit
2.7 V ≤ VDD ≤ 3.6 V, CL = 20 pF
-
-
90
1.71 V ≤ VDD ≤ 3.6 V, CL = 15 pF
-
-
84
Quad-SPI clock high time
‐
t(CK)/2-1
-
t(CK)/2
tw(CKL)
Quad-SPI clock low time
‐
t(CK)/2
-
t(CK)/2+1
ts(IN)
Data input set-up time
‐
0.5
-
-
th(IN)
Data input hold time
‐
3
-
-
tv(OUT)
Data output valid time
‐
-
3
4
th(OUT)
Data output hold time
‐
2.5
-
-
MHz
ns
1. Guaranteed based on test during characterization.
Figure 71. Quad-SPI SDR timing diagram
WU&.
&ORFN
'DWDRXWSXW
W&.
WZ&.+
WY287
WI&.
WK287
'
'
WV,1
'DWDLQSXW
WZ&./
'
'
WK,1
'
'
06Y9
DocID028196 Rev 2
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Electrical characteristics
STM32F469xx
Table 108. Quad-SPI characteristics in DDR mode(1)
Symbol
Fck
1/t(CK)
Parameter
Quad-SPI clock frequency
Test conditions
Min
Typ
Max
2.7 V ≤ VDD ≤ 3.6 V,
CL = 20 pF
-
-
80
Unit
MHz
1.71 V ≤ VDD ≤ 3.6 V,
CL = 15 pF
-
-
70
tw(CKH)
Quad-SPI clock high time
‐
t(CK)/2-1
-
t(CK)/2
tw(CKL)
Quad-SPI clock low time
-
t(CK)/2
-
t(CK)/2+1
tsr(IN)
tsf(IN)
Data input set-up time
2.7 V ≤ VDD ≤ 3.6 V
2
-
-
1.71 V ≤ VDD ≤ 3.6 V
0.5
-
-
thr(IN)
thf(IN)
Data input hold time
2.7 V ≤ VDD ≤ 3.6 V
3
-
-
1.71 V ≤ VDD ≤ 3.6 V
4.5
-
-
DHHC=0
-
8
10.5
DHHC=1
Pres=1,2…
-
Thclk/2+2
Thclk/2+2.5
DHHC=0
7
-
-
DHHC=1
Pres=1,2…
Thclk/2+0.5
-
-
tvr(OUT)
tvf(OUT)
Data output valid time
th(OUT)
tf(OUT)
Data output hold time
ns
1. Guaranteed based on test during characterization.
Figure 72. Quad-SPI DDR timing diagram
WU&.
&ORFN
W&.
WYI287
'DWDRXWSXW
WZ&.+
WKU287
'
WYU287
'
'
WZ&./
WKI287
'
WVI,1 WKI,1
'DWDLQSXW
'
'
WI&.
'
'
WVU,1 WKU,1
'
'
'
'
06Y9
5.3.31
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 109 for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
182/208
•
DCMI_PIXCLK polarity: falling
•
DCMI_VSYNC and DCMI_HSYNC polarity: high
•
Data formats: 14 bits
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 VDD
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Table 109. DCMI characteristics(1)
Symbol
Min
Max
Unit
-
0.4
-
-
54
MHz
Pixel clock input duty cycle
30
70
%
tsu(DATA)
Data input setup time
4
-
th(DATA)
Data input hold time
1
-
-
Parameter
Frequency ratio DCMI_PIXCLK/fHCLK
DCMI_PIXCLK Pixel clock input
DPixel
tsu(HSYNC)
tsu(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input setup time
3.5
-
th(HSYNC)
th(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time
0
-
ns
1. 1.Guaranteed based on test during characterization.
Figure 73. DCMI timing diagram
'&0,B3,;&/.
'&0,B3,;&/.
WVX+6<1&
WK+6<1&
'&0,B+6<1&
WVX96<1&
WK+6<1&
'&0,B96<1&
WVX'$7$ WK'$7$
'$7$>@
069
5.3.32
LCD-TFT controller (LTDC) characteristics
Unless otherwise specified, the parameters given in Table 110 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 17, with the following configuration:
•
LCD_CLK polarity: high
•
LCD_DE polarity: low
•
•
LCD_VSYNC and LCD_HSYNC polarity: high
Pixel formats: 24 bits
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load CL = 30 pF
•
Measurement points are done at CMOS levels: 0.5 VDD
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Electrical characteristics
STM32F469xx
Table 110. LTDC characteristics(1)
Symbol
Parameter
Min
Max
Unit
fCLK
LTDC clock output frequency
-
65
MHz
DCLK
LTDC clock output duty cycle
45
55
%
tw(CLKH)
tw(CLKL)
Clock High time, low time
tw(CLK)/2 − 0.5
tw(CLK)/2+0.5
tv(DATA)
Data output valid time
-
1.5
th(DATA)
Data output hold time
0
-
HSYNC/VSYNC/DE output valid time
-
0.5
HSYNC/VSYNC/DE output hold time
0
-
tv(HSYNC)
tv(VSYNC)
ns
tv(DE)
th(HSYNC)
th(VSYNC)
th(DE)
1. Based on test during characterization.
Figure 74. LCD-TFT horizontal timing diagram
W&/.
/&'B&/.
/&'B96<1&
WY+6<1&
WY+6<1&
/&'B+6<1&
WK'(
WY'(
/&'B'(
WY'$7$
/&'B5>@
/&'B*>@
/&'B%>@
1JYFM 1JYFM
1JYFM
/
WK'$7$
+6<1& +RUL]RQWDO
ZLGWK EDFNSRUFK
$FWLYHZLGWK
+RUL]RQWDO
EDFNSRUFK
2QHOLQH
069
184/208
DocID028196 Rev 2
STM32F469xx
Electrical characteristics
Figure 75. LCD-TFT vertical timing diagram
W&/.
/&'B&/.
WY96<1&
WY96<1&
/&'B96<1&
/&'B5>@
/&'B*>@
/&'B%>@
-LINESDATA
96<1& 9HUWLFDO
ZLGWK EDFNSRUFK
$FWLYHZLGWK
9HUWLFDO
EDFNSRUFK
2QHIUDPH
069
5.3.33
SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 111 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load C = 30 pF
•
Measurement points are done at CMOS levels: 0.5 VDD
Refer to Section 5.3.20 for more details on the input/output characteristics.
Figure 76. SDIO high-speed mode
TF
TR
T#
T7#+(
T7#+,
#+
T/6
T/(
$#-$
OUTPUT
T)35
T)(
$#-$
INPUT
AI
DocID028196 Rev 2
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187
Electrical characteristics
STM32F469xx
Figure 77. SD default mode
#+
T/6$
T/($
$#-$
OUTPUT
AI
Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
50
MHz
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
9.5
10.5
-
8.5
9.5
-
2.0
-
-
2.0
-
-
-
13
13.5
12.5
-
-
2.0
-
-
2.5
-
-
-
1.5
2.0
1.0
-
-
tW(CKL)
Clock low time
tW(CKH)
Clock high time
fpp =50 MHz
ns
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU
Input setup time HS
tIH
Input hold time HS
fpp =50 MHz
ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
Output valid time HS
tOH
Output hold time HS
fpp =50 MHz
ns
CMD, D inputs (referenced to CK) in SD default mode
tISUD
Input setup time SD
tIHD
Input hold time SD
fpp =25 MHz
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD
Output valid default time SD
tOHD
Output hold default time SD
fpp =25 MHz
1. Guaranteed based on test during characterization.
186/208
DocID028196 Rev 2
ns
STM32F469xx
Electrical characteristics
Table 112. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V(1)(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPP
Clock frequency in data transfer mode
-
0
-
50
MHz
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
9.5
10.5
-
8.5
9.5
-
0.5
-
-
3.5
-
-
-
13.5
14.5
13.0
-
-
tW(CKL)
Clock low time
tW(CKH)
Clock high time
fpp =50 MHz
ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU
Input setup time HS
tIH
Input hold time HS
fpp =50 MHz
ns
CMD, D outputs (referenced to CK) in eMMC mode
tOV
Output valid time HS
tOH
Output hold time HS
fpp =50 MHz
ns
1. Guaranteed based on test during characterization.
2. Cload = 20 pF.
5.3.34
RTC characteristics
Table 113. RTC characteristics
Symbol
Parameter
-
fPCLK1/RTCCLK frequency ratio
Conditions
Any read/write operation from/to an RTC register
DocID028196 Rev 2
Min
Max
4
-
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Package information
6
STM32F469xx
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
6.1
WLCSP168 package information
Figure 78. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip
scale package outline
$EDOOORFDWLRQ
H
)
EEE =
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H
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HHH =
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$6B0(B9
188/208
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STM32F469xx
Package information
Table 114. WLCSP168 - 168-pin, 4.891 x 5.692 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.525
0.555
0.585
0.0207
0.0219
0.0230
A1
-
0.170
-
-
0.0067
-
A2
-
0.380
-
-
0.0150
-
(2)
A3
-
0.025
-
-
0.0010
-
(3)
0.220
0.250
0.280
0.0087
0.0098
0.0110
D
4.856
4.891
4.926
0.1912
0.1926
0.1939
E
5.657
5.692
5.727
0.2227
0.2241
0.2255
e
-
0.400
-
-
0.0157
-
e1
-
4.400
-
-
0.1732
-
e2
-
5.200
-
-
0.2047
-
F
-
0.2455
-
-
0.0097
-
G
-
0.246
-
-
0.0097
-
aaa
-
-
0.100
-
-
0.0039
bbb
-
-
0.100
-
-
0.0039
ccc
-
-
0.100
-
-
0.0039
ddd
-
-
0.050
-
-
0.0020
eee
-
-
0.050
-
-
0.0020
b
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
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Package information
6.2
STM32F469xx
UFBGA169 package information
Figure 79. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline
= 6HDWLQJSODQH
$
$
GGG =
$
$
$
E
6,'(9,(:
$EDOO
LGHQWLILHU
$EDOO
LQGH[DUHD
;
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1
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7239,(:
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‘ HHH 0 = ; <
‘ III 0 =
$<9B0(B9
1. Drawing is not in scale.
Table 115. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array
package mechanical data
inches(1)
millimeters
Symbol
190/208
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.0020
0.0031
0.0043
A2
0.400
0.450
0.500
0.0157
0.0177
0.0197
A3
-
0.130
-
-
0.0051
-
A4
0.270
0.320
0.370
0.0106
0.0126
0.0146
b
0.230
0.280
0.330
0.0091
0.0110
0.0130
D
6.950
7.000
7.050
0.2736
0.2756
0.2776
D1
5.950
6.000
6.050
0.2343
0.2362
0.2382
E
6.950
7.000
7.050
0.2736
0.2756
0.2776
E1
5.950
6.000
6.050
0.2343
0.2362
0.2382
e
-
0.500
-
-
0.0197
-
DocID028196 Rev 2
STM32F469xx
Package information
Table 115. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
F
0.450
0.500
0.550
0.0177
0.0197
0.0217
ddd
-
-
0.100
-
-
0.0039
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Device Marking for UFBGA169
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 80. UFBGA169 marking example (package top view)
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1. Samples marked "ES" are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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Package information
6.3
STM32F469xx
LQFP176 package information
Figure 81. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline
C
!
!
!
# 3EATINGPLANE
MM
GAUGEPLANE
K
!
,
($
0).
)$%.4)&)#!4)/.
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:%
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(%
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:$
B
4?-%?6
1. Drawing is not to scale.
Table 116. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
-
1.450
0.0531
-
0.0060
b
0.170
-
0.270
0.0067
-
0.0106
C
0.090
-
0.200
0.0035
-
0.0079
D
23.900
-
24.100
0.9409
-
0.9488
E
23.900
-
24.100
0.9409
-
0.9488
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Package information
Table 116. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
e
-
0.500
-
-
0.0197
-
HD
25.900
-
26.100
1.0200
-
1.0276
HE
25.900
-
26.100
1.0200
-
1.0276
L
0.450
-
0.750
0.0177
-
0.0295
L1
-
1.000
-
-
0.0394
-
ZD
-
1.250
-
-
0.0492
-
ZE
-
1.250
-
-
0.0492
-
ccc
-
-
0.080
-
-
0.0031
k
0°
-
7°
0°
-
7°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information
STM32F469xx
Figure 82. LQFP176 recommended footprint
4?&0?6
1. Dimensions are expressed in millimeters.
194/208
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STM32F469xx
Package information
Device Marking for LQFP176
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 83. LQFP176 marking example (package top view)
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1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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Package information
6.4
STM32F469xx
UFBGA176+25 package information
Figure 84. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package outline
&
^ĞĂƚŝŶŐƉůĂŶĞ
Ϯ ϰ
ĚĚĚ ϭ
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1. Drawing is not to scale.
Table 117. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch,
ultra fine pitch ball grid array package mechanical data
inches(1)
millimeters
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.0020
0.0031
0.0043
A2
0.400
0.450
0.500
0.0157
0.0177
0.0197
A4
0.270
0.320
0.370
0.0106
0.0126
0.0146
b
0.230
0.280
0.330
0.0091
0.0110
0.0130
D
9.950
10.000
10.050
0.3917
0.3937
0.3957
E
9.950
10.000
10.050
0.3917
0.3937
0.3957
e
-
0.650
-
-
0.0256
-
F
0.400
0.450
0.500
0.0157
0.0177
0.0197
ddd
-
-
0.080
-
-
0.0031
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information
Figure 85. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball
grid array package recommended footprint
'SDG
'VP
Ϭϳͺ&Wͺsϭ
Table 118. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension
Recommended values
Pitch
0.65 mm
Dpad
0.300 mm
Dsm
0.400 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.300 mm
Stencil thickness
Between 0.100 mm and 0.125 mm
Pad trace width
0.100 mm
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Package information
6.5
STM32F469xx
LQFP208 package information
Figure 86. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline
6($7,1*
3/$1(
F
$
$
$
&
FFF &
PP
$
*$8*(3/$1(
.
/
'
/
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'
(
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(
E
3,1
,'(17,),&$7,21
H
6)@.&@7
1. Drawing is not to scale.
Table 119. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
198/208
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
--
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
DocID028196 Rev 2
STM32F469xx
Package information
Table 119. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
c
0.090
-
0.200
0.0035
-
0.0079
D
29.800
30.000
30.200
1.1732
1.1811
1.1890
D1
27.800
28.000
28.200
1.0945
1.1024
1.1102
D3
-
25.500
-
-
1.0039
-
E
29.800
30.000
30.200
1.1732
1.1811
1.1890
E1
27.800
28.000
28.200
1.0945
1.1024
1.1102
E3
-
25.500
-
-
1.0039
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7.0°
0°
3.5°
7.0°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package information
STM32F469xx
Figure 87. LQFP208 recommended footprint
-36
1. Dimensions are expressed in millimeters.
200/208
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STM32F469xx
Package information
Device Marking for LQFP208
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 88. LQFP208 marking example (package top view)
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
^dDϯϮ&ϰϳϵ/dϲ
3LQ
LGHQWLILHU
'DWHFRGH
z tt
06Y9
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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206
Package information
6.6
STM32F469xx
TFBGA216 package information
Figure 89. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm, package outline
= 6HDWLQJSODQH
GGG =
$
$ $
(
H
$EDOO
$EDOO
LGHQWLILHU LQGH[DUHD
)
;
(
$
)
'
H
'
<
5
%277209,(:
‘EEDOOV
‘ HHH 0 = < ;
‘ III 0 =
7239,(:
$/B0(B9
1. Drawing is not to scale.
Table 120. TFBGA216 - thin fine pitch ball grid array 13 × 13 × 0.8mm
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.100
-
-
0.0433
A1
0.150
-
-
0.0059
-
-
A2
-
0.760
-
-
0.0299
-
A4
-
0.210
-
-
0.0083
-
b
0.350
0.400
0.450
0.0138
0.0157
0.0177
D
12.850
13.000
13.150
0.5118
0.5118
0.5177
D1
-
11.200
-
-
0.4409
-
E
12.850
13.000
13.150
0.5118
0.5118
0.5177
E1
-
11.200
-
-
0.4409
-
e
-
0.800
-
-
0.0315
-
F
-
0.900
-
-
0.0354
-
ddd
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
202/208
DocID028196 Rev 2
STM32F469xx
Package information
Device Marking for TFBGA216
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 90. TFBGA216 marking example (package top view)
3URGXFWLGHQWLILFDWLRQ
^ϯϮ&
5HYLVLRQFRGH
ϰϳϵE/,ϲh
'DWHFRGH
z tt
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LGHQWLILHU
06Y9
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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206
Package information
6.7
STM32F469xx
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
•
TA max is the maximum ambient temperature in ° C,
•
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 121. Package thermal characteristics
Symbol
ΘJA
Parameter
Value
Thermal resistance junction-ambient
WLCSP168
31
Thermal resistance junction-ambient
LQFP176 - 24 × 24 mm / 0.5 mm pitch
38
Thermal resistance junction-ambient
LQFP208 - 28 × 28 mm / 0.5 mm pitch
19
Thermal resistance junction-ambient
UFBGA169 - 7 × 7mm / 0.5 mm pitch
52
Thermal resistance junction-ambient
UFBGA176 - 10 × 10 mm / 0.5 mm pitch
39
Thermal resistance junction-ambient
TFBGA216 - 13 × 13 mm / 0.8 mm pitch
29
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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7
Part numbering
Part numbering
Table 122. Ordering information scheme
Example:
STM32 F
469 V
I
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
469= STM32F469xx, USB OTG FS/HS, camera interface,
Ethernet, LCD-TFT, DSIHost, Quad-SPI,
Chrom-ART graphical accelerator.
Pin count
A = 168 and 169 pins
I = 176 pins
B = 208 pins
N = 216 pins
Flash memory size
E = 512 Kbytes of Flash memory
G = 1024 Kbytes of Flash memory
I = 2048 Kbytes of Flash memory
Package
T = LQFP
H = BGA
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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Recommendations when using internal reset OFF
Appendix A
STM32F469xx
Recommendations when using internal reset
OFF
When the internal reset is OFF, the following integrated features are no longer supported:
A.1
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•
The brownout reset (BOR) circuitry must be disabled.
•
The embedded programmable voltage detector (PVD) is disabled.
•
VBAT functionality is no more available and VBAT pin should be connected to VDD.
•
The over-drive mode is not supported.
Operating conditions
Table 123. Limitations depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
with no wait
states
(fFlashmax)
VDD =1.7 to
2.1 V(3)
Conversion
time up to
1.2 Msps
20 MHz(4)
Maximum Flash
memory access
frequency with
wait states (1)(2)
168 MHz with 8
wait states and
over-drive OFF
I/O operation
Possible Flash
memory
operations
8-bit erase and
– No I/O
program
compensation
operations only
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does
not impact the execution speed from Flash memory since the ART accelerator allows to achieve a
performance equivalent to 0 wait state program execution.
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 2.19.1: Internal reset ON).
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and
power.
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8
Revision history
Revision history
Table 124. Document revision history
Date
Revision
01-Sep-2015
1
Initial release.
2
Updated Table 4: Regulator ON/OFF and internal reset ON/OFF
availability and Table 54: EMI characteristics.
Updated Figure 33: PLL output clock waveforms in center spread
mode and Figure 34: PLL output clock waveforms in down spread
mode.
Updated title of Section 6.6: TFBGA216 package information.
13-Oct-2015
Changes
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STM32F469xx
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
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