STMicroelectronics STM32F439ZI Datasheet
Reklam
Reklam
STM32F437xx STM32F439xx
32b Arm
®
Cortex
®
-M4 MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, crypto,
USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera&LCD-TFT
Datasheet
-
production data
Features
• Core: Arm ® 32-bit Cortex ® -M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz,
MPU, 225 DMIPS/1.25 DMIPS/MHz
(Dhrystone 2.1), and DSP instructions
• Memories
– Up to 2 MB of Flash memory organized into two banks allowing read-while-write
– Up to 256+4 KB of SRAM including 64-KB of CCM (core coupled memory) data RAM
– Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, Compact
Flash/NOR/NAND memories
• LCD parallel interface, 8080/6800 modes
• LCD-TFT controller with fully programmable resolution (total width up to 4096 pixels, total height up to 2048 lines and pixel clock up to
83 MHz)
• Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D)
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1% accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low power
– Sleep, Stop and Standby modes
– V
BAT
supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 180 MHz, each with up to 4
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
&"'!
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)
LQFP208 (28 x 28 mm)
UFBGA176 (10 x 10 mm)
UFBGA169 (7 × 7 mm)
TFBGA216 (13 x 13 mm)
WLCSP143
• Debug mode
– SWD & JTAG interfaces
– Cortex-M4 Trace Macrocell™
• Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 90 MHz
– Up to 166 5 V-tolerant I/Os
• Up to 21 communication interfaces
– Up to 3 × I 2 C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (11.25 Mbit/s,
ISO7816 interface, LIN, IrDA, modem control)
– Up to 6 SPIs (45 Mbits/s), 2 with muxed full-duplex I 2 S for audio class accuracy via internal audio PLL or external clock
– 1 x SAI (serial audio interface)
– 2 × CAN (2.0B Active) and SDIO interface
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG controller with on-chip PHY
– USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit parallel camera interface up to
54 Mbytes/s
• Cryptographic acceleration: hardware acceleration for AES 128, 192, 256, Triple
DES, HASH (MD5, SHA-1, SHA-2), and HMAC
• True random number generator
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
January 2018
This is information on a product in full production.
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STM32F437xx and STM32F439xx
Reference
Table 1. Device summary
Part number
STM32F437xx
STM32F437VG, STM32F437ZG, STM32F437IG, STM32F437VI, STM32F437ZI, STM32F437II,
STM32F437AI
STM32F439xx
STM32F439VI, STM32F439VG, STM32F439ZG, STM32F439ZI, STM32F439IG, STM32F439II,
STM32F439BG, STM32F439BI, STM32F439NI, STM32F439AI, STM32F439NG
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STM32F437xx and STM32F439xx
Contents
3
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
®
Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . . 21
Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 21
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LCD-TFT controller (available only on STM32F439xx) . . . . . . . . . . . . . . 24
Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 25
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 32
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 32
BAT
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 36
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Inter-integrated circuit interface ( I
2 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Universal synchronous/asynchronous receiver transmitters (USART) . . 37
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40
Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 40
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 41
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 41
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Operating conditions at power-up / power-down (regulator ON) . . . . . . 98
Operating conditions at power-up / power-down (regulator OFF) . . . . . 98
Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 99
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 118
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PLL spread spectrum clock generation (SSCG) characteristics . . . . . 128
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 134
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 195
LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 196
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SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 198
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
WLCSP143 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
TFBGA216 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 229
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 230
USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 232
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
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List of tables
List of tables
STM32F437xx and STM32F439xx features and peripheral counts . . . . . . . . . . . . . . . . . . 16
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 29
STM32F437xx and STM32F439xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 75
STM32F437xx and STM32F439xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 87
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM . . . . . . 102
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 106
Typical and maximum current consumptions in V
BAT
mode. . . . . . . . . . . . . . . . . . . . . . . 106
Typical current consumption in Run mode, code with data processing running from
Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch),
VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Typical current consumption in Run mode, code with data processing running
from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . 109
Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . 110
LSE oscillator characteristics (f
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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List of tables STM32F437xx and STM32F439xx
Flash memory programming with V
PP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
2 S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
= 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
= 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 161
= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 161
monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 173
Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 175
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Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 177
Switching characteristics for PC Card/CF read and write cycles
Switching characteristics for PC Card/CF read and write cycles
Table 111. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
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List of figures
List of figures
STM32F437xx and STM32F439xx
Compatible board design between STM32F2xx and STM32F4xx
Startup in regulator OFF: slow V
DD
slope
- power-down reset risen after V
CAP_1
/V
CAP_2
slope stabilization . . . . . . . . . . . . . . . . . . . . . . . . 31
Startup in regulator OFF mode: fast V
- power-down reset risen before V
CAP_1
/V
CAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . 107
current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . 107
versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
2
S slave timing diagram (Philips protocol)
(1)
2
S master timing diagram (Philips protocol)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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Power supply and reference decoupling (V
REF+
Power supply and reference decoupling (V
REF+ not connected to V
DDA connected to V
DDA
). . . . . . . . . . . . . 164
). . . . . . . . . . . . . . . . 165
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 171
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 173
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 174
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 176
PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 184
PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 184
PC Card/CompactFlash controller waveforms for attribute memory
PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 186
PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 187
NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 190
NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 190
LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 200
WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 207
LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline . . . . . . . . . . . . . . 211
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List of figures STM32F437xx and STM32F439xx
LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 213
LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 215
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STM32F437xx and STM32F439xx
1 Introduction
Introduction
This datasheet provides the description of the STM32F437xx and STM32F439xx line of microcontrollers. For more details on the whole STMicroelectronics STM32 family, please refer to
Section 2.1: Full compatibility throughout the family .
The STM32F437xx and STM32F439xx datasheet should be read in conjunction with the
STM32F4xx reference manual.
For information on the Cortex ® -M4 core, please refer to the Cortex ® -M4 programming manual (PM0214), available from www.st.com
.
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Description
2 Description
STM32F437xx and STM32F439xx
The STM32F437xx and STM32F439xx devices are based on the high-performance Arm ®
Cortex ® -M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all Arm ® singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
The STM32F437xx and STM32F439xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbyte, up to 256 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two
APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, a true random number generator (RNG) and a cryptographic acceleration cell. They also feature standard and advanced communication interfaces.
• Up to three I
2
Cs
• Six SPIs, two I 2 Ss full duplex. To achieve audio class accuracy, the I 2 S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
• Four USARTs plus four UARTs
• An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI),
• Two CANs
• One SAI serial audio interface
• An SDIO/MMC interface
• Ethernet and camera interface
• LCD-TFT display controller
• Chrom-ART Accelerator™.
Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a
camera interface for CMOS sensors and a cryptographic acceleration cell. Refer to Table 2:
STM32F437xx and STM32F439xx features and peripheral counts for the list of peripherals
available on each part number.
The STM32F437xx and STM32F439xx devices operates in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor
(refer to
Section 3.17.2: Internal reset OFF
). A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F437xx and STM32F439xx devices offer devices in 8 packages ranging from
100 pins to 216 pins. The set of included peripherals changes with the device chosen.
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These features make the STM32F437xx and STM32F439xx microcontrollers suitable for a wide range of applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
Figure 4 shows the general block diagram of the device family.
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Peripherals
Table 2. STM32F437xx and STM32F439xx features and peripheral counts
STM32F437
Vx
STM32F439
Vx
STM32F437Zx STM32F437AI STM32F439AI STM32F439Zx STM32F437Ix STM32F439Ix STM32F439Bx STM32F439Nx
Flash memory in Kbytes
System
SRAM in
Kbytes
Backup
FMC memory controller
Ethernet
Timers
Generalpurpose
Advance d-control
Basic
Random number generator
SPI / I
2
S
I 2 C
USART/
UART
Communication interfaces
USB
OTG FS
USB
OTG HS
CAN
1024 2048 1024
4/2 (full duplex)
SAI
SDIO
Camera interface
LCD-TFT No
Chrom-ART Accelerator™
(DMA2D)
Cryptography
GPIOs 82
(2)
Yes
2048 1024 2048
No
2048
114
2048 1024 2048
256(112+16+64+64)
4
Yes (1)
Yes
Yes
10
2
2
Yes
3
4/4
Yes
Yes
2
1
Yes
Yes
Yes
Yes
6/2 (full duplex)
(2)
Yes
1024 2048
No
140
1024 2048 1024
Yes
168
2048 1024
168
2048
Peripherals
Table 2. STM32F437xx and STM32F439xx features and peripheral counts (continued)
STM32F437
Vx
STM32F439
Vx
STM32F437Zx STM32F437AI STM32F439AI STM32F439Zx STM32F437Ix STM32F439Ix STM32F439Bx STM32F439Nx
12-bit ADC
Number of channels
12-bit DAC
Number of channels
Maximum CPU frequency
Operating voltage
Operating temperatures
16
3
24
Yes
2
180 MHz
1.7 to 3.6 V (3)
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to + 125 °C
UFBGA169
WLCSP143
LQFP144
UFBGA176
LQFP176
Package LQFP100
WLCSP143
LQFP144
LQFP208 TFBGA216
1.
For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit
NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.
2.
The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3.
V
DD
/V
DDA
).
Description
2.1
STM32F437xx and STM32F439xx
Full compatibility throughout the family
The STM32F437xx and STM32F439xx devices are part of the STM32F4 family. They are fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle.
The STM32F437xx and STM32F439xx devices maintain a close compatibility with the whole STM32F10xx family. All functional pins are pin-to-pin compatible. The STM32F437xx and STM32F439xx, however, are not drop-in replacements for the STM32F10xx devices: the two families do not have the same power scheme, and so their power pins are different.
Nonetheless, transition from the STM32F10xx to the STM32F43x family remains simple as only a few pins are impacted.
, and
Figure 3 , give compatible board designs between the STM32F4xx,
STM32F2xx, and STM32F10xx families.
Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package
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DocID024244 Rev 11
STM32F437xx and STM32F439xx Description
Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package
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DocID024244 Rev 11
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Description STM32F437xx and STM32F439xx
Figure 4. STM32F437xx and STM32F439xx block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
2. The LCD-TFT is available only on STM32F439xx devices.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Functional overview
3.1 Arm
®
Cortex
®
-M4 with FPU and embedded Flash and SRAM
The Arm
®
Cortex
®
-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
The Arm
®
Cortex
®
-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.
Note:
The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.
The STM32F43x family is compatible with all Arm tools and software.
Figure 4 shows the general block diagram of the STM32F43x family.
Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard Arm ® Cortex ® advantage of the Arm ®
-M4 with FPU processors. It balances the inherent performance
Cortex ® -M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DocID024244 Rev 11
44
Functional overview
3.4 Embedded Flash memory
STM32F437xx and STM32F439xx
The devices embed a Flash memory of up to 2 Mbytes available for storing programs and data.
3.5 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.
All devices embed:
• Up to 256Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
• 4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or V BAT mode.
3.7 Multi-AHB matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Functional overview
Figure 5. STM32F437xx and STM32F439xx Multi-AHB matrix
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DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.
DocID024244 Rev 11
44
Functional overview STM32F437xx and STM32F439xx
The DMA can be used with the main peripherals:
• SPI and I
2
S
• I 2 C
• USART
• General-purpose, basic and advanced-control timers TIMx
• DAC
• SDIO
• Cryptographic acceleration
• Camera interface (DCMI)
• ADC
• SAI1.
3.9 Flexible memory controller (FMC)
All devices embed an FMC. It has four Chip Select outputs supporting the following modes:
PCCard/Compact Flash, SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND
Flash.
Functionality overview:
• 8-,16-, 32-bit data bus width
• Read FIFO for SDRAM controller
• Write FIFO
• Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
• 2 displays layers with dedicated FIFO (64x32-bit)
• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
• Up to 8 Input color formats selectable per layer
• Flexible blending between two layers using alpha value (per pixel or constant)
• Flexible programmable parameters for each layer
• Color keying (transparency color)
• Up to 4 programmable interrupt events.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Functional overview
3.11 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions:
• Rectangle filling with a fixed color
• Rectangle copy
• Rectangle copy with pixel format conversion
• Rectangle composition with blending and pixel format conversion.
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables.
An interrupt can be generated when an operation is complete or at a programmed watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
3.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex ® -
M4 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt latency.
The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected to the 16 external interrupt lines.
3.14 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
DocID024244 Rev 11
44
Functional overview STM32F437xx and STM32F439xx detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is
90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.
The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio class performance. In this case, the I 2 S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.
At startup, boot pins are used to select one out of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to application note AN2606 for details.
Note:
• V
DD
= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through V
DD
pins.
• V
SSA
, V
DDA
= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
• V
BAT
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V
DD
is not present.
V
DD
/V
DDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to
Section 3.17.2: Internal reset OFF ). Refer to
option.
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
DocID024244 Rev 11
STM32F437xx and STM32F439xx Functional overview reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when V
DD
V
POR/PDR
or V
BOR
is below a specified threshold,
, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors the V
DD
/V
DDA
power supply and compares it to the V
PVD
threshold. An interrupt can be generated when V higher than the V
DD
PVD
/V
DDA
drops below the V
PVD
threshold and/or when V
DD
/V
DDA
threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
is
This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor V
DD reset mode as long as V
DD
and should maintain the device in
is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to
Figure 6: Power supply supervisor interconnection with internal reset OFF
.
Figure 6. Power supply supervisor interconnection with internal reset OFF
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The V
DD
specified threshold, below which the device must be maintained under reset, is
).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• V
BAT
functionality is no more available and V
BAT
pin should be connected to V
DD
.
All packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal.
DocID024244 Rev 11
44
Functional overview
3'5 9
STM32F437xx and STM32F439xx
Figure 7. PDR_ON control with internal reset OFF
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The regulator has four operating modes:
• Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
• Regulator OFF
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
• MR mode used in Run/sleep modes or in Stop modes
– In Run/Sleep mode
The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Functional overview
The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling.
– In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
• LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
– LPR operates in normal mode (default mode when LPR is ON)
– LPR operates in under-drive mode (reduced leakage mode).
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost.
for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on V
CAP_1
and V
CAP_2
pin. Refer to
Figure 22: Power supply scheme
and
Table 19: VCAP1/VCAP2 operating conditions .
All packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode
(1)
Voltage regulator configuration
Run mode Sleep mode Stop mode Standby mode
MR or LPR Normal mode
Over-drive mode
(2)
Under-drive mode
MR
MR
-
MR
MR
-
Power-down mode
-
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when V
DD
= 1.7 to 2.1 V.
MR or LPR
-
-
-
-
Yes
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V
12
voltage source through V
CAP_1
and V
CAP_2
pins.
Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. Refer to
Table 17: General operating conditions
.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to
Figure 22: Power supply scheme
.
When the regulator is OFF, there is no more internal monitoring on V
12 supply supervisor should be used to monitor the V
12
. An external power
of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V
12
power domain.
DocID024244 Rev 11
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Functional overview STM32F437xx and STM32F439xx
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V
12 domain which is not reset by the NRST pin.
logic power
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.
• The over-drive and under-drive modes are not available.
• The Standby mode is not available.
Figure 8. Regulator OFF
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The following conditions must be respected:
• V
DD
should always be higher than V between power domains.
CAP_1
and V
CAP_2 to avoid current injection
• If the time for V
CAP_1
and V and V
CAP_2 reach V
12
CAP_2 to reach V
12 minimum value is faster than the time for
V
DD
to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
CAP_1 minimum value and until V
DD
).
• Otherwise, if the time for V
CAP_1 than the time for V
).
DD
and V
CAP_2 to reach V
12 minimum value is slower
to reach 1.7 V, then PA0 could be asserted low externally (see
• If V
CAP_1
and V
CAP_2
go below V
12 minimum value and V reset must be asserted on PA0 pin.
DD
is higher than 1.7 V, then a
The minimum value of V
12 depends on the maximum frequency targeted in the application
(see Table 17: General operating conditions
).
DocID024244 Rev 11
STM32F437xx and STM32F439xx Functional overview
Figure 9. Startup in regulator OFF: slow V
DD
- power-down reset risen after V
CAP_1
/V
CAP_2
slope stabilization
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1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast V
DD
- power-down reset risen before V
CAP_1
/V
CAP_2
slope stabilization
WLPH
9
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9
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1. This figure is valid whatever the internal reset mode (ON or OFF).
DocID024244 Rev 11
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Functional overview STM32F437xx and STM32F439xx
3.18.3 Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF
LQFP100
LQFP144,
LQFP208
WLCSP143,
LQFP176,
UFBGA169,
UFBGA176,
TFBGA216
Yes No
Yes No
Yes
BYPASS_REG set to V
SS
Yes
BYPASS_REG set to V
DD
Yes
PDR_ON set to
V
DD
Yes
PDR_ON connected to an external power supply supervisor
The backup domain includes:
• The real-time clock (RTC)
• 4 Kbytes of backup SRAM
• 20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see
Section 3.20: Low-power modes ). It can be
enabled by software.
The backup registers are 32-bit registers used to store 80 bytes of user application data when V
DD
power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see
Section 3.20: Low-power modes ).
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STM32F437xx and STM32F439xx Functional overview
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.
Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the V
DD
supply when present or from the V
BAT
pin.
The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
• Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
– Normal mode (default mode when MR or LPR is enabled)
– Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).
Voltage regulator configuration
Table 5. Voltage regulator modes in stop mode
Main regulator (MR) Low-power regulator (LPR)
Normal mode
Under-drive mode
MR ON
MR in under-drive mode
LPR ON
LPR in under-drive mode
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs.
The standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power.
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Functional overview STM32F437xx and STM32F439xx
3.21 V
BAT
operation
The V
BAT
pin allows to power the device V supercapacitor, or from V present.
DD
BAT
domain from an external battery, an external when no external battery and an external supercapacitor are
Note:
V
BAT
operation is activated when V
DD
is not present.
The V
BAT
pin supplies the RTC, the backup registers and the backup SRAM.
When the microcontroller is supplied from V
BAT do not exit it from V
BAT operation.
, external interrupts and RTC alarm/events
When PDR_ON pin is not connected to V
DD no more available and V
BAT
(Internal Reset OFF), the V pin should be connected to V DD .
BAT functionality is
3.22 Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Functional overview
Timer type
Timer
Counter resolution
Table 6. Timer feature comparison
Counter type
Prescaler factor
DMA request generation
Capture/ compare channels
Complementary output
Max interface clock
(MHz)
Max timer clock
(MHz)
(1)
Advanced
-control
General purpose
Basic
TIM1,
TIM8
TIM2,
TIM5
TIM3,
TIM4
TIM9
TIM10
,
TIM11
TIM12
TIM13
,
TIM14
TIM6,
TIM7
16-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
Up,
Down,
Up/down
Any integer between 1 and
65536
Up,
Down,
Up/down
Any integer between 1 and
65536
Up,
Down,
Up/down
Any integer between 1 and
65536
Up
Up
Any integer between 1 and
65536
Any integer between 1 and
65536
Up
Up
Up
Any integer between 1 and
65536
Any integer between 1 and
65536
Any integer between 1 and
65536
Yes
Yes
Yes
No
No
No
No
Yes
4
4
4
2
1
2
1
0
Yes
No
No
No
No
No
No
No
90
45
45
90
90
45
45
45
90/180
90/180
90/180
1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
180
90/180
90/180
180
180
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Functional overview STM32F437xx and STM32F439xx
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
There are ten synchronizable general-purpose timers embedded in the STM32F43x devices
(see Table 6 for differences).
• TIM2, TIM3, TIM4, TIM5
The STM32F43x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.
• TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.
These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
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STM32F437xx and STM32F439xx Functional overview
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:
• A 24-bit downcounter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.
circuit interface ( I
2
C)
Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the
7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see
).
Pulse width of suppressed spikes
Table 7. Comparison of I2C analog and digital filters
Analog filter Digital filter
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, UART5, UART7, and UART8).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
DocID024244 Rev 11
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Functional overview STM32F437xx and STM32F439xx communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 bit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller.
USART name
Standard features
Modem
(RTS/CTS)
Table 8. USART feature comparison (1)
LIN
SPI master irDA
Smartcard
(ISO 7816)
Max. baud rate in Mbit/s
(oversampling by 16)
Max. baud rate in Mbit/s
(oversampling by 8)
APB mapping
USART1
USART2
USART3
UART4
UART5
USART6
UART7
UART8
X
X
X
X
X
X
X
X
X
X
X
-
-
X
-
-
X
X
X
X
X
X
X
X
X
X
X
-
-
X
-
-
X
X
X
X
X
X
X
X
X
X
X
-
-
X
-
-
5.62
2.81
2.81
2.81
2.81
5.62
2.81
2.81
11.25
5.62
5.62
5.62
5.62
11.25
5.62
5.62
APB2
(max.
90 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
APB2
(max.
90 MHz)
APB1
(max.
45 MHz)
APB1
(max.
45 MHz)
1. X = feature supported.
3.25 Serial peripheral interface (SPI)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,
SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode.
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STM32F437xx and STM32F439xx Functional overview
3.26 Inter-integrated sound (I
2
S)
Two standard I
2
S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I
2
S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.
Note:
All I2Sx can be served by the DMA controller.
For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port
B and GPIO Port D.
3.27 Serial Audio interface (SAI1)
The serial audio interface (SAI1) is based on two independent audio sub-blocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is required.
SAI1 can be served by the DMA controller.
3.28 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I
2
S and SAI applications. It allows to achieve error-free I
2
S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I
2
S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz.
I
In addition to the audio PLL, a master clock input pin can be used to synchronize the
2
S/SAI flow with an external PLL (or Codec output).
3.29 Audio and LCD PLL(PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
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Functional overview STM32F437xx and STM32F439xx
3.30 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.
3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F4xx reference manual for details)
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time
3.32 Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
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STM32F437xx and STM32F439xx Functional overview
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
3.33 Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:
• Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 4 bidirectional endpoints
• 8 host channels with periodic OUT support
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed in case bus-powered devices are connected
3.34 Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 6 bidirectional endpoints
• 12 host channels with periodic OUT support
• Internal FS OTG PHY support
• External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• for OTG/Host modes, a power switch is needed in case bus-powered devices are connected
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Functional overview STM32F437xx and STM32F439xx
3.35 Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports continuous mode or snapshot (a single frame) mode
• Capability to automatically crop the image
3.36 Cryptographic acceleration
The devices embed a cryptographic accelerator. This cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to provide confidentiality, authentication, data integrity and non repudiation when exchanging messages with a peer.
• These algorithms consists of:
Encryption/Decryption
– DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
– AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter mode) chaining algorithms, 128, 192 or 256-bit key
Universal hash
– SHA-1 and SHA-2 (secure hash algorithms)
– MD5
– HMAC
The cryptographic accelerator supports DMA request generation.
3.37 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.
Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.
DocID024244 Rev 11
STM32F437xx and STM32F439xx
Fast I/O handling allowing maximum I/O toggling up to 90 MHz.
Functional overview
3.39 Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as V
BAT
, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and V
BAT conversion are enabled at the same time, only V
BAT
conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.
The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.
This dual digital Interface supports the following features:
• two DAC converters: one for each output channel
• 8-bit or 10-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• external triggers for conversion
• input voltage reference V
REF+
DocID024244 Rev 11
44
Functional overview STM32F437xx and STM32F439xx
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.
3.42 Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
3.43 Embedded Trace Macrocell™
The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F43x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DocID024244 Rev 11
STM32F437xx and STM32F439xx
4 Pinouts and pin description
Pinouts and pin description
Figure 11. STM32F43x LQFP100 pinout
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DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Figure 12. STM32F43x WLCSP143 ballout
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1. The above figure shows the package bump view.
DocID024244 Rev 11
STM32F437xx and STM32F439xx
Figure 13. STM32F43x LQFP144 pinout
Pinouts and pin description
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DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Figure 14. STM32F43x LQFP176 pinout
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-36
1. The above figure shows the package top view.
DocID024244 Rev 11
633!
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Figure 15. STM32F43x LQFP208 pinout
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-36
Pinouts and pin description STM32F437xx and STM32F439xx
Figure 16. STM32F43x UFBGA169 ballout
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1. The above figure shows the package top view.
2. The 4 corners balls, A1,A13, N1 and N13, are not bonded internally and should be left not connected on the PCB.
-36
DocID024244 Rev 11
STM32F437xx and STM32F439xx
Figure 17. STM32F43x UFBGA176 ballout
Pinouts and pin description
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1. The above figure shows the package top view.
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Figure 18. STM32F43x TFBGA216 ballout
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-36
1. The above figure shows the package top view.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Pinouts and pin description
Name
Pin name
Pin type
I/O structure
Table 9. Legend/abbreviations used in the pinout table
Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
S
I
Supply pin
Input only pin
I/O
FT
TTa
B
RST
Input / output pin
5 V tolerant I/O
3.3 V tolerant I/O directly connected to ADC
Dedicated BOOT0 pin
Bidirectional reset pin with weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Notes
Alternate functions
Additional functions
Functions selected through GPIOx_AFR registers
Functions directly selected/enabled through peripheral registers
Table 10. STM32F437xx and STM32F439xx pin and ball definitions
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
1 1 B2 A2 1 D8 1 A3
2 2 C1 A1 2 C10 2 A2
3 3 C2 B1 3 B11 3 A1
PE2
PE3
PE4
I/O FT -
I/O FT -
I/O FT -
TRACECLK,
SPI4_SCK,
SAI1_MCLK_A,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
TRACED0,
SAI1_SD_B, FMC_A19,
EVENTOUT
TRACED1, SPI4_NSS,
SAI1_FS_A, FMC_A20,
DCMI_D4, LCD_B0,
EVENTOUT
-
-
-
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
-
-
-
4
5
-
-
6
-
7
8
9
-
-
-
4
5
-
-
-
6 E5 C1
7
9
-
-
-
-
-
-
-
D1
D2
NC
(2)
E4
-
-
-
-
4
5
-
-
8
G6
F5
6 C11 6 C1
7 7 C2
8 E1 E1 9 D11 9 E1
F1
-
E2
E3
NC
B2
B3
-
-
D2
D1
F1
-
D3
E3
E4
4
5
8
10
-
11
12
13
D9
E8
D10
E11
-
-
-
-
10
-
F1
G5
11 E4
12
13
B1
B2
D1
D5
F3
F6 F2 14 E7 14 F2
F4 F3 15 E10 15 F4
PE5
PE6
V
V
V
SS
DD
BAT
PI8
PC13
I/O FT
I/O FT -
-
S -
S -
S -
(3)
I/O FT
(4)
TRACED2, TIM9_CH1,
SPI4_MISO,
SAI1_SCK_A,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
TRACED3, TIM9_CH2,
SPI4_MOSI,
SAI1_SD_A, FMC_A22,
DCMI_D7, LCD_G1,
EVENTOUT
-
-
-
EVENTOUT
I/O FT
(3)
(4)
EVENTOUT
-
-
-
-
-
TAMP_2
TAMP_1
PC14-
OSC32_IN
(PC14)
PC15-
OSC32_OUT
(PC15)
V
DD
I/O FT
(3)
(4)
I/O FT
(3)
(4)
S -
PI9
PI10
PI11
V
V
SS
DD
I/O FT
I/O FT
I/O FT
S
S
-
-
-
-
-
-
-
EVENTOUT
EVENTOUT
-
CAN1_RX, FMC_D30,
LCD_VSYNC,
EVENTOUT
ETH_MII_RX_ER,
FMC_D31,
LCD_HSYNC,
EVENTOUT
OTG_HS_ULPI_DIR,
EVENTOUT
-
-
OSC32_IN
(5)
OSC32_
OUT
-
-
-
-
-
-
(5)
DocID024244 Rev 11
STM32F437xx and STM32F439xx Pinouts and pin description
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
10 F2 E2 16 F11 16 D2
11 F3 H3 17 E9 17 E2
-
12 G5 H2 18 F10 18 G2
19 E3
-
-
-
-
20 G3
21 H3
13 G4 J2 19 G11 22 H2
14 G3 J3 20 F9 23 J2
15 H3 K3 21 F8 24 K3
10 16 G7 G2 22 H7 25 H6
11 17 G8 G3 23 26 H5
18
NC
K2 24 G10 27 K2
-
19
NC
20
NC
K1 25 F7 28 K1
L3 26 H11 29 L3
PF0
PF1
PF2
PI12
PI13
PI14
PF3
PF4
PF5
V
SS
V
DD
PF6
PF7
PF8
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
-
(5)
I2C2_SDA, FMC_A0,
EVENTOUT
I2C2_SCL, FMC_A1,
EVENTOUT
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
LCD_HSYNC,
EVENTOUT
LCD_VSYNC,
EVENTOUT
LCD_CLK, EVENTOUT
-
-
-
FMC_A3, EVENTOUT ADC3_IN9
I/O FT
I/O FT
S
S
-
-
(5)
(5)
-
-
FMC_A4, EVENTOUT
FMC_A5, EVENTOUT
ADC3_
IN14
ADC3_
IN15
-
-
I/O FT
I/O FT
I/O FT
(5)
(5)
(5)
-
-
TIM10_CH1,
SPI5_NSS,
SAI1_SD_B,
UART7_Rx,
FMC_NIORD,
EVENTOUT
TIM11_CH1,
SPI5_SCK,
SAI1_MCLK_B,
UART7_Tx,
FMC_NREG,
EVENTOUT
SPI5_MISO,
SAI1_SCK_B,
TIM13_CH1,
FMC_NIOWR,
EVENTOUT
ADC3_IN4
ADC3_IN5
ADC3_IN6
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
-
-
12
13
14
21
NC
15 26 G6 M2 32 H8 35 M2
16 27 H5 M3 33 K11 36 M3
17 28 H6 M4 34 J10 37 M4
18
22
23
24
25
29
H1
G2
G1
H2
H7
L2
L1
G1
H1
J1
M5
27
28
29
G8
G9
J11
30
31
32
30 H10 33
31
35
H9
J9
34
38
L2
L1
G1
H1
J1
L4
19 30 36 G7 39 J5
J6
20 31 J1 M1 37 K10 40 M1
J2 N1 N1
21 32 J3 P1 38 L11 41 P1
PF9
PF10
I/O FT
I/O FT
(5)
(5)
SPI5_MOSI,
SAI1_FS_B,
TIM14_CH1, FMC_CD,
EVENTOUT
FMC_INTR,
DCMI_D11, LCD_DE,
EVENTOUT
ADC3_IN7
ADC3_IN8
PH0-OSC_IN
(PH0)
PH1-
OSC_OUT
(PH1)
I/O FT -
I/O FT -
NRST I/O
RS
T
-
EVENTOUT
EVENTOUT
-
OSC_IN
OSC_OUT
(5)
-
(5)
PC0
PC1
PC2
PC3
V
DD
V
SS
V
SSA
V
V
REF –
REF+
I/O FT
I/O FT
I/O FT
I/O FT
S
(5)
(5)
(5)
S -
S -
S
S
-
-
-
(5)
-
-
-
OTG_HS_ULPI_STP,
FMC_SDNWE,
EVENTOUT
ETH_MDC,
EVENTOUT
SPI2_MISO,
I2S2ext_SD,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
-
-
-
-
-
ADC123_
IN10
ADC123_
IN11
ADC123_
IN12
ADC123_
IN13
-
-
-
-
-
DocID024244 Rev 11
STM32F437xx and STM32F439xx Pinouts and pin description
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
22
23
24
25
-
-
-
-
26
27
33
34
35
36
-
-
-
-
37
38
J4
J5
K1
K2
L2
L1
M2
L3
K3
-
R1
N3
N2
P2
F4
G4
H4
J4
R2
-
39
40
41
42
43
44
45
46
L10
K9
K8
L9
-
-
-
-
42
43
44
45
46
47
48
49
47 M11 50
R1
N3
N2
P2
K4
J4
H4
J3
R2
51 K6
V
DDA
PA0-WKUP
(PA0)
PA1
PA2
PH2
PH3
PH4
PH5
PA3
V
SS
S -
I/O FT
I/O FT
I/O FT
-
(6)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
UART4_TX,
ETH_MII_CRS,
EVENTOUT
ADC123_
IN0/WKUP
(5)
(5)
(5)
TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
ETH_MII_RX_CLK/ETH
_RMII_REF_CLK,
EVENTOUT
TIM2_CH3, TIM5_CH3,
TIM9_CH1,
USART2_TX,
ETH_MDIO,
EVENTOUT
ADC123_
IN1
ADC123_
IN2
I/O FT
I/O FT
I/O FT -
-
-
ETH_MII_CRS,
FMC_SDCKE0,
LCD_R0, EVENTOUT
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
I2C2_SCL,
OTG_HS_ULPI_NXT,
EVENTOUT
I/O FT
I/O FT
S -
-
(5)
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
EVENTOUT
TIM2_CH4, TIM5_CH4,
TIM9_CH2,
USART2_RX,
OTG_HS_ULPI_D0,
ETH_MII_COL,
LCD_B5, EVENTOUT
-
ADC123_
IN3
-
-
-
-
-
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
-
28
29
30
31 42 N3 P3 52 N10 55 P3
32
33
34
-
-
-
39
40
41
43
44
45
-
-
M1
J11
N2
M3
K4
L4
M4
-
-
L4
K4
N4
P4
R3
N5
P5
-
-
48
49
50 M10 53
51
53
54
55
-
-
N11
J8
M9
L8
M8
N9
J7
-
-
52
54
56
57
58
59
60
L5
K5
N4
P4
R3
N5
P5
L7
L6
BYPASS_
REG
V
DD
PA4
PA5
PA6
I
S
FT
-
I/O TTa
I/O TTa
I/O FT
PA7 I/O FT
-
-
(5)
(5)
-
-
-
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK,
OTG_HS_ULPI_CK,
EVENTOUT
ADC12_
IN4 /DAC_
OUT1
ADC12_
IN5/DAC_
OUT2
(5)
(5)
TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
SPI1_MISO,
TIM13_CH1,
DCMI_PIXCLK,
LCD_G2, EVENTOUT
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI,
TIM14_CH1,
ETH_MII_RX_DV/ETH_
RMII_CRS_DV,
EVENTOUT
-
ADC12_
IN6
ADC12_
IN7
PC4
PC5
V
DD
VSS
I/O FT
I/O FT
S
S
-
-
(5)
(5)
-
-
ETH_MII_RXD0/ETH_
RMII_RXD0,
EVENTOUT
ETH_MII_RXD1/ETH_
RMII_RXD1,
EVENTOUT
-
-
ADC12_
IN14
ADC12_
IN15
-
-
DocID024244 Rev 11
STM32F437xx and STM32F439xx Pinouts and pin description
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
35
36
46
47
N4
K5
R5
R4
56
57
N8
K7
61
62
R5
R4
37 48 L5 M6 58 L7 63 M5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
49
-
-
-
-
-
-
M5
-
-
-
-
-
-
R6
-
-
-
-
-
-
59
-
-
-
-
-
-
M7
64
65
66
70
G4
R6
R7
67 P7
68 N8
69 M9
P8
50 N5 P6 60 N7 71 M6
51 G9 M8 61 72 K7
52 D10 N8 62 73 L8
53 M6 N6 63 K6 74 N6
54 K7 R7 64 L6 75 P6
55 L7 P7 65 M6 76 M8
56 N6 N7 66 N6 77 N7
57 M7 M7 67 K5 78 M7
PB0
PB1
I/O FT
(5)
I/O FT
(5)
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
EVENTOUT
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
EVENTOUT
PF12
V
SS
V
DD
PF13
PF14
PF15
PG0
PG1
PB2-BOOT1
(PB2)
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
PF11
I/O FT -
I/O FT
I/O FT
I/O FT
I/O FT
-
-
-
-
EVENTOUT
LCD_R0, EVENTOUT
LCD_R1, EVENTOUT
LCD_R2, EVENTOUT
I/O FT LCD_R3, EVENTOUT
I/O FT LCD_R4, EVENTOUT
LCD_R5, EVENTOUT
I/O FT -
SPI5_MOSI,
FMC_SDNRAS,
DCMI_D12,
EVENTOUT
I/O FT FMC_A6, EVENTOUT
S -
S -
I/O FT FMC_A7, EVENTOUT
I/O FT FMC_A8, EVENTOUT
I/O FT FMC_A9, EVENTOUT
I/O FT FMC_A10, EVENTOUT
I/O FT FMC_A11, EVENTOUT
ADC12_
IN8
ADC12_
IN9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
38 58 N7 R8 68 L5 79 R8
39 59 J8 P8 69 M5 80 N9
40 60 K8 P9 70 N5 81 P9
-
-
42
61
62
41 63 L8 R9 73 J4 84 R9
64
J6
G10
M8
M9
N9
P10
71
72
74
H3
J5
K4
82
83
85
K8
L9
P10
43 65 N8 R10 75 L4 86 R10
44 66 H9 N11 76 N4 87 R12
45
46
47
67
68
69
J9
K9
L9
P11
R11
R12
77
78
79
M4
L3
M3
88
89
90
P11
R11
P12
48 70 M9 R13 80 N3 91 R13
PE7
PE8
PE9
V
SS
V
DD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
I/O FT -
I/O FT -
I/O FT -
TIM1_ETR, UART7_Rx,
FMC_D4, EVENTOUT
TIM1_CH1N,
UART7_Tx, FMC_D5,
EVENTOUT
TIM1_CH1, FMC_D6,
EVENTOUT
S
S -
-
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT -
-
-
-
-
-
-
-
TIM1_CH2N, FMC_D7,
EVENTOUT
TIM1_CH2, SPI4_NSS,
FMC_D8, LCD_G3,
EVENTOUT
TIM1_CH3N,
SPI4_SCK, FMC_D9,
LCD_B4, EVENTOUT
TIM1_CH3,
SPI4_MISO, FMC_D10,
LCD_DE, EVENTOUT
TIM1_CH4,
SPI4_MOSI, FMC_D11,
LCD_CLK, EVENTOUT
TIM1_BKIN, FMC_D12,
LCD_R7, EVENTOUT
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
USART3_TX,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
TIM2_CH4, I2C2_SDA,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_
RMII_TX_EN, LCD_G5,
EVENTOUT
DocID024244 Rev 11
-
-
-
-
-
-
-
-
-
-
-
-
-
STM32F437xx and STM32F439xx Pinouts and pin description
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
49 71 N9 M10 81 N2 92 L11
H2 93 K9
50 72 F8 N10 82 J6 94 L10
95 M14
-
-
-
-
N10 M11 83 -
M10 N12 84 97 N13
L10 M12 85 -
96 P13
98 P14
K10 M13 86 99 N14
N11 L13 87
M11 L12 88
100 P15
101 N15
-
-
L11 K12 89 102 M15
-
E7 H12 90
H8 J12 91
K10
103 K11
V
CAP_1
V
SS
V
DD
PJ5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
V
SS
V
DD
S -
S -
S -
-
-
I/O LCD_R6, EVENTOUT
I/O FT -
I2C2_SMBA,
SPI5_SCK,
TIM12_CH1,
ETH_MII_RXD2,
FMC_SDNE1,
DCMI_D8, EVENTOUT
I/O FT
I/O FT -
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
I2C3_SDA, FMC_D16,
DCMI_HSYNC,
LCD_R2, EVENTOUT
I/O FT -
I2C3_SMBA,
TIM12_CH2,
FMC_D17, DCMI_D0,
LCD_R3, EVENTOUT
I/O FT
I/O FT
I/O FT
S
S
-
-
-
-
-
-
-
TIM5_CH1, FMC_D18,
DCMI_D1, LCD_R4,
EVENTOUT
TIM5_CH2, FMC_D19,
DCMI_D2, LCD_R5,
EVENTOUT
TIM5_CH3, FMC_D20,
DCMI_D3, LCD_R6,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
51
52
73
74
N12 P12
M12 P13
92
93
M2 104 L13
N1 105 K14
53 75 M13 R14 94 K3 106 R14
54
55
56
57
76
77
78
79
L13
L12
R15
P15
K13 P14
K11 N15
95
96
97
98
J3
L2
107 R15
108 L15
M1 109 L14
H4 110 K15
PB12
PB13
PB14
PB15
PD8
PD9
PD10
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
USART3_CK,
CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_R
MII_TXD0,
OTG_HS_ID,
EVENTOUT
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
USART3_CTS,
CAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_R
MII_TXD1, EVENTOUT
-
OTG_HS_
VBUS
TIM1_CH2N,
TIM8_CH2N,
SPI2_MISO,
I2S2ext_SD,
USART3_RTS,
TIM12_CH1,
OTG_HS_DM,
EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
SPI2_MOSI/I2S2_SD,
TIM12_CH2,
OTG_HS_DP,
EVENTOUT
USART3_TX,
FMC_D13, EVENTOUT
USART3_RX,
FMC_D14, EVENTOUT
USART3_CK,
FMC_D15, LCD_B3,
EVENTOUT
-
-
-
-
-
DocID024244 Rev 11
STM32F437xx and STM32F439xx Pinouts and pin description
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
58 80 H10 N14 99 K2 111 N10
59 81 J13 N13 100 H6 112 M10
60 82 K12 M15 101 H5 113 M11
-
83
84
-
F7
102
J13 103
114 J10
L1 115 J11
61 85 H11 M14 104 J2 116 L12
-
-
-
-
-
-
-
-
-
-
-
-
-
62 86 J12 L14 105 K1 117 K13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
118 K12
119 J12
120 H12
121 J13
122 H13
123 G12
124 H11
125 H10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
126 G13
127 F12
128 F13
87 H13 L15 106 J1 129 M13
88
NC
K15 107 G3 130 M12
89 H12 K14 108 G5 131 N12
90 G13 K13 109 G6 132 N11
PD11
PD12
PD13
V
SS
V
DD
PD14
PD15
PJ11
VDD
VSS
PK0
PK1
PJ6
PJ7
PJ8
PJ9
PJ10
PK2
PG2
PG3
PG4
PG5
I/O FT
I/O FT
I/O FT
S
S
I/O FT
-
-
-
-
-
-
USART3_CTS,
FMC_A16, EVENTOUT
TIM4_CH1,
USART3_RTS,
FMC_A17, EVENTOUT
TIM4_CH2, FMC_A18,
EVENTOUT
-
-
TIM4_CH3, FMC_D0,
EVENTOUT
I/O FT -
TIM4_CH4, FMC_D1,
EVENTOUT
I/O FT LCD_R7, EVENTOUT
I/O FT LCD_G0, EVENTOUT
I/O FT LCD_G1, EVENTOUT
I/O FT LCD_G2, EVENTOUT
I/O FT LCD_G3, EVENTOUT
I/O FT LCD_G4, EVENTOUT
I/O FT -
I/O FT -
I/O FT LCD_G5, EVENTOUT
I/O FT LCD_G6, EVENTOUT
I/O FT LCD_G7, EVENTOUT
I/O FT FMC_A12, EVENTOUT
I/O FT FMC_A13, EVENTOUT
I/O FT
I/O FT -
-
FMC_A14/FMC_BA0,
EVENTOUT
FMC_A15/FMC_BA1,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
-
-
-
-
-
63
91
92
93 F13 H14 112 G2 135 H14
94 J7 G12 113 D2 136 G10
95 E6 H13 114 G1 137 G11
96
G11
G12
F9
J15 110 G4 133 J15
J14 111
H15 115
H1 134 J14
F2 138 H15
64 97 F10 G15 116 F3 139 G15
65 98 F11 G14 117 E4 140 G14
66
67
99 F12
100 E13
F14 118
F15 119
E3 141 F14
F1 142 F15
PG6
PG7
PG8
V
V
SS
DD
PC6
PC7
PC8
PC9
PA8
I/O FT -
I/O FT -
I/O FT -
S
S
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
-
-
FMC_INT2, DCMI_D12,
LCD_R7, EVENTOUT
USART6_CK,
FMC_INT3, DCMI_D13,
LCD_CLK, EVENTOUT
SPI6_NSS,
USART6_RTS,
ETH_PPS_OUT,
FMC_SDCLK,
EVENTOUT
-
-
TIM3_CH1, TIM8_CH1,
I2S2_MCK,
USART6_TX,
SDIO_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
TIM3_CH2, TIM8_CH2,
I2S3_MCK,
USART6_RX,
SDIO_D7, DCMI_D1,
LCD_G6, EVENTOUT
TIM3_CH3, TIM8_CH3,
USART6_CK,
SDIO_D0, DCMI_D2,
EVENTOUT
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, SDIO_D1,
DCMI_D3, EVENTOUT
MCO1, TIM1_CH1,
I2C3_SCL,
USART1_CK,
OTG_FS_SOF,
LCD_R6, EVENTOUT
-
-
-
-
-
-
-
-
-
-
DocID024244 Rev 11
STM32F437xx and STM32F439xx Pinouts and pin description
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
68 101 E8 E15 120 E2 143 E15
69 102 E9 D15 121 D5 144 D15
70
71
72
73 106 D12 F13 125 D1 148 E11
74 107 J10 F12 126 D2 149 F10
75 108 H4 G13 127 C1 150 F11
-
-
-
-
103 E10 C15 122 D4 145 C15
104 E11
105 E12 A15 124 D3 147 A15
-
-
-
B15 123 E1 146 B15
D13 E12 128 151 E12
C13 E13 129
C12 D13 130
B13 E14 131 -
-
152 E13
153 D13
154 E14
PA9
PA10
PA11
PA12
PA13
(JTMS-
SWDIO)
V
CAP_2
V
SS
V
DD
PH13
PH14
PH15
PI0
I/O FT -
I/O FT -
I/O FT -
I/O FT -
TIM1_CH2,
I2C3_SMBA,
USART1_TX,
DCMI_D0, EVENTOUT
TIM1_CH3,
USART1_RX,
OTG_FS_ID,
DCMI_D1, EVENTOUT
TIM1_CH4,
USART1_CTS,
CAN1_RX, LCD_R4,
OTG_FS_DM,
EVENTOUT
TIM1_ETR,
USART1_RTS,
CAN1_TX, LCD_R5,
OTG_FS_DP,
EVENTOUT
OTG_FS_
VBUS
-
-
-
I/O FT -
JTMS-SWDIO,
EVENTOUT
S
S
S
I/O FT -
I/O FT -
I/O FT -
I/O FT -
-
-
-
-
-
-
TIM8_CH1N,
CAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
TIM8_CH2N,
FMC_D22, DCMI_D4,
LCD_G3, EVENTOUT
TIM8_CH3N,
FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
TIM5_CH4,
SPI2_NSS/I2S2_WS
(7)
,
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
-
-
-
-
-
-
-
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
-
-
-
-
-
C11 D14 132
B12 C14 133
A12 C13 134 -
-
155 D14
156 C14
157 C13
-
-
-
D11
D3
D9
C9
135 F5 F9
136 A1 158 E10
76 109 A11 A14 137 B1 159 A14
77 110 B11 A13 138 C2 160 A13
78 111 C10 B14 139 A2 161 B14
79 112 B10 B13 140 B2 162 B13
80 113 A10 A12 141 C3 163 A12
81 114 D9 B12 142 B3 164 B12
PI1
PI2
PI3
V
SS
V
DD
PA14
(JTCK-
SWCLK)
PA15
(JTDI)
PC10
PC11
PC12
PD0
I/O FT -
I/O FT -
I/O FT -
S
S -
-
SPI2_SCK/I2S2_CK
(7)
,
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
TIM8_CH4,
SPI2_MISO,
I2S2ext_SD, FMC_D26,
DCMI_D9, LCD_G7,
EVENTOUT
TIM8_ETR,
SPI2_MOSI/I2S2_SD,
FMC_D27, DCMI_D10,
EVENTOUT
-
-
I/O FT -
JTCK-SWCLK/
EVENTOUT
I/O FT -
I/O FT -
I/O FT -
I/O FT -
I/O FT -
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS,
SPI3_NSS/I2S3_WS,
EVENTOUT
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX, SDIO_D2,
DCMI_D8, LCD_R2,
EVENTOUT
I2S3ext_SD,
SPI3_MISO,
USART3_RX,
UART4_RX, SDIO_D3,
DCMI_D4, EVENTOUT
SPI3_MOSI/I2S3_SD,
USART3_CK,
UART5_TX, SDIO_CK,
DCMI_D9, EVENTOUT
CAN1_RX, FMC_D2,
EVENTOUT
DocID024244 Rev 11
-
-
-
-
-
-
-
-
-
-
-
STM32F437xx and STM32F439xx Pinouts and pin description
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
82 115 C9 C12 143 C4 165 C12
83 116 B9 D12 144 A3 166 D12
84
85
86
117
118
A9
D8
120 -
D11 145 B4 167 C11
D10 146 B5 168 D11
121 D6 C8 149 C5 171 E9
87
88
-
-
-
-
119
122
123
-
-
-
-
C8
B8
A8
-
-
-
-
124
NC
C11 147 A4 169 C10
D8 148 170 F8
B11 150 F4 172 B11
A11 151 A5 173 A11
-
-
-
-
-
-
-
-
-
-
174 B10
175
176
B9
C9
177 D10
C10 152 E5 178 D9
PD1
PD2
PD3
PD4
PD5
V
SS
V
DD
PD6
PD7
PJ12
PJ13
PJ14
PJ15
PG9
I/O FT
I/O FT
I/O FT -
-
-
CAN1_TX, FMC_D3,
EVENTOUT
TIM3_ETR,
UART5_RX,
SDIO_CMD,
DCMI_D11,
EVENTOUT
SPI2_SCK/I2S2_CK,
USART2_CTS,
FMC_CLK, DCMI_D5,
LCD_G7, EVENTOUT
I/O FT
I/O FT -
-
USART2_RTS,
FMC_NOE,
EVENTOUT
USART2_TX,
FMC_NWE,
EVENTOUT
S -
S
I/O FT -
-
SPI3_MOSI/I2S3_SD,
SAI1_SD_A,
USART2_RX,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
I/O FT -
USART2_CK,
FMC_NE1/FMC_NCE2,
EVENTOUT
I/O FT LCD_B0, EVENTOUT
I/O FT LCD_B1, EVENTOUT
I/O FT LCD_B2, EVENTOUT
I/O FT LCD_B3, EVENTOUT
I/O FT -
USART6_RX,
FMC_NE2/FMC_NCE3,
DCMI_VSYNC (8) ,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
-
125
126 B7 B9 154 B6 180 B8
127
C7
A7
B10 153 C6 179
B8 155 A6 181
C8
C7
128
NC
A8 156 D6 182 B3
129
NC
A7 157 F6 183 A4
-
-
-
130 D7 D7 158 184 F7
-
-
131 L6 C7 159 E6 185 E8
186 D8
187 D7
-
-
-
-
-
-
-
-
-
-
-
-
188 C6
189 C5
190 C4
132 C6 B7 160 A7 191 B7
V
SS
V
DD
PK3
PK4
PK5
PK6
PK7
PG15
PG10
PG11
PG12
PG13
PG14
I/O FT
I/O FT
I/O FT
I/O FT -
-
-
-
LCD_G3,
FMC_NCE4_1/FMC_N
E3, DCMI_D2,
LCD_B2, EVENTOUT
ETH_MII_TX_EN/ETH_
RMII_TX_EN,
FMC_NCE4_2,
DCMI_D3, LCD_B3,
EVENTOUT
SPI6_MISO,
USART6_RTS,
LCD_B4, FMC_NE4,
LCD_B1, EVENTOUT
SPI6_SCK,
USART6_CTS,
ETH_MII_TXD0/ETH_R
MII_TXD0, FMC_A24,
EVENTOUT
I/O FT -
SPI6_MOSI,
USART6_TX,
ETH_MII_TXD1/ETH_R
MII_TXD1, FMC_A25,
EVENTOUT
S -
S -
I/O FT LCD_B4, EVENTOUT
I/O FT LCD_B5, EVENTOUT
I/O FT LCD_B6, EVENTOUT
I/O FT LCD_B7, EVENTOUT
I/O FT LCD_DE, EVENTOUT
I/O FT -
USART6_CTS,
FMC_SDNCAS,
DCMI_D13,
EVENTOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
DocID024244 Rev 11
STM32F437xx and STM32F439xx Pinouts and pin description
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
89 133 B6 A10 161 B7 192 A10
90
91
92
93
134
135
136
137
A6
D5
C5
B5
A9
A6
B6
B5
162 C7 193
163 C8 194
164 A8 195
165 B8 196
A9
A8
B6
B5
PB3
(JTDO/TRACE
SWO)
PB4
(NJTRST)
PB5
PB6
PB7
I/O FT
I/O FT -
I/O FT -
I/O FT -
I/O FT -
-
JTDO/TRACESWO,
TIM2_CH2, SPI1_SCK,
SPI3_SCK/I2S3_CK,
EVENTOUT
NJTRST, TIM3_CH1,
SPI1_MISO,
SPI3_MISO,
I2S3ext_SD,
EVENTOUT
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
CAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10,
EVENTOUT
TIM4_CH1, I2C1_SCL,
USART1_TX,
CAN2_TX,
FMC_SDNE1,
DCMI_D5, EVENTOUT
TIM4_CH2, I2C1_SDA,
USART1_RX, FMC_NL,
DCMI_VSYNC,
EVENTOUT
94 138 A5 D6 166 C9 197 E6 BOOT0 I B -
95 139 D4 A5 167 A9 198 A7 PB8 I/O FT -
TIM4_CH3,
TIM10_CH1,
I2C1_SCL, CAN1_RX,
ETH_MII_TXD3,
SDIO_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
-
-
-
-
-
V
PP
DocID024244 Rev 11
85
Pinouts and pin description STM32F437xx and STM32F439xx
Table 10. STM32F437xx and STM32F439xx pin and ball definitions (continued)
Pin number
Pin name
(function after reset)
(1)
Alternate functions
Additional functions
96
97
98
140
141
142
C4
B4
A4
B4
A4
A3
168 B9 199
169 B10 200
170 A10 201
B4
A6
A5
PB9
PE0
PE1
I/O FT
I/O FT
I/O FT -
-
-
TIM4_CH4,
TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
CAN1_TX, SDIO_D5,
DCMI_D7, LCD_B7,
EVENTOUT
TIM4_ETR,
UART8_RX,
FMC_NBL0, DCMI_D2,
EVENTOUT
UART8_Tx,
FMC_NBL1, DCMI_D3,
EVENTOUT
-
-
-
99 F5 D5 202 F6
143 C3 C6 171 A11 203 E5
100 144 K6 C5 172 D7 204 E7
V
SS
PDR_ON
V
DD
S
S
S -
-
-
-
-
-
-
-
-
-
B3
A3
A2
B1
D4
C4
C3
C2
173
174
175
176 -
-
-
205
206
207
208
C3
D3
D6
D4
PI4
PI5
PI6
PI7
I/O FT
I/O FT
I/O FT
I/O FT -
-
-
-
TIM8_BKIN,
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
TIM8_CH1,
FMC_NBL3,
DCMI_VSYNC,
LCD_B5, EVENTOUT
TIM8_CH2, FMC_D28,
DCMI_D6, LCD_B6,
EVENTOUT
TIM8_CH3, FMC_D29,
DCMI_D7, LCD_B7,
EVENTOUT
-
-
-
-
1. Function availability depends on the chosen device.
2. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid extra current consumption in low power modes.
3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
-
-
-
DocID024244 Rev 11
STM32F437xx and STM32F439xx Pinouts and pin description
4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com
.
5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
6. If the device is delivered in an WLCSP143, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the
BYPASS_REG pin is set to V
DD
(Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low).
7.
PI0 and PI1 cannot be used for I2S2 full-duplex mode.
8. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3.
DocID024244 Rev 11
85
Pinouts and pin description
Pin name
PE3
PE4
PE5
PE6
PE2
PG13
PG3
PG4
PG5
PD11
PD12
PD13
PF13
PF14
PF15
PG0
PG1
PG2
PF0
PF1
PF2
PF3
PF4
PF5
PF12
PG14
PD14
PD15
PD0
PD1
PE7
PE8
PE9
PE10
CF
A3
A4
A5
A6
A0
A1
A2
A7
A8
A9
A10
D0
D1
D2
D3
D4
D5
D6
D7
STM32F437xx and STM32F439xx
Table 11. FMC pin definition
NOR/PSRAM/
SRAM
NOR/PSRAM
Mux
A19
A20
A21
A22
A23
A24
A13
A14
A15
A16
A17
A18
A7
A8
A9
A10
A11
A12
A3
A4
A5
A6
A0
A1
A2
A25
D0
D1
D2
D3
D4
D5
D6
D7
A25
DA0
DA1
DA2
DA3
DA4
A16
A17
A18
A19
A20
A21
A22
A23
A24
DA5
DA6
DA7
NAND16
CLE
ALE
D0
D1
D2
D3
D4
D5
D6
D7
BA0
BA1
D0
D1
D2
D3
D4
D5
D6
D7
SDRAM
A7
A8
A9
A10
A11
A12
A3
A4
A5
A6
A0
A1
A2
DocID024244 Rev 11
Pin name
PI10
PD7
PG9
PG10
PG11
PG12
PI1
PI2
PI3
PI6
PI7
PI9
PD3
PD4
PD5
PD6
PB7
PD10
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PI0
PE11
PE12
PE13
PE14
PE15
PD8
PD9
STM32F437xx and STM32F439xx Pinouts and pin description
CF
Table 11. FMC pin definition (continued)
NOR/PSRAM/
SRAM
NOR/PSRAM
Mux
NAND16
D8
D9
D10
D11
D12
D13
D14
D15
NCE4_1
NCE4_2
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D8
D9
D10
D11
D12
D13
D14
D25
D26
D27
D28
D29
D30
D31
NE1
NE2
NE3
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
NE1
NE2
NE3
D8
D9
D10
D11
D12
D13
D14
D15
NCE2
NCE3
NOE
NWE
NWAIT
NE4
CLK
NOE
NWE
NWAIT
NL(NADV)
NE4
CLK
NOE
NWE
NWAIT
NL(NADV)
NOE
NWE
NWAIT
SDRAM
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D8
D9
D10
D11
D12
D13
D14
D25
D26
D27
D28
D29
D30
D31
DocID024244 Rev 11
85
Pin name
PE0
PE1
PI4
PI5
PG8
PC0
PF11
PG15
PH2
PH3
PF6
PF7
PF8
PF9
PF10
PG6
PG7
PH6
PH7
PH5
PC2
PC3
PB5
PB6
Pinouts and pin description STM32F437xx and STM32F439xx
CF
Table 11. FMC pin definition (continued)
NOR/PSRAM/
SRAM
NOR/PSRAM
Mux
NAND16
NIORD
NREG
NIOWR
CD
INTR
INT2
INT3
NBL0
NBL1
NBL2
NBL3
NBL0
NBL1
SDRAM
NBL0
NBL1
NBL2
NBL3
SDCLK
SDNWE
SDNRAS
SDNCAS
SDCKE0
SDNE0
SDNE1
SDCKE1
SDNWE
SDNE0
SDCKE0
SDCKE1
SDNE1
DocID024244 Rev 11
Port
Port A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA9
PA10
PA11
PA12
AF0
SYS
-
-
-
-
-
-
-
-
-
-
-
-
PA8 MCO1
TIM1_
CH1
TIM1_
CH2
TIM1_
CH3
TIM1_
CH4
TIM1_
ETR
AF1
TIM1/2
TIM2_
CH1/TIM2
_ETR
TIM2_
CH2
TIM2_
CH3
TIM2_
CH4
-
TIM2_
CH1/TIM2
_ETR
TIM1_
BKIN
TIM1_
CH1N
AF2
Table 12. STM32F437xx and STM32F439xx alternate function mapping
AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11
TIM3/4/5
TIM8/9/
10/11
I2C1/
2/3
SPI1/2/
3/4/5/6
SPI2/3/
SAI1
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
ETH
TIM5_
CH1
TIM5_
CH2
TIM5_
CH3
TIM5_
CH4
-
-
TIM3_
CH1
TIM3_
CH2
-
-
-
-
-
TIM8_
ETR
-
TIM9_
CH1
TIM9_
CH2
-
TIM8_
CH1N
TIM8_
BKIN
TIM8_
CH1N
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C3_
SCL
I2C3_
SMBA
-
-
-
-
-
SPI1_
MOSI
-
-
-
-
-
-
-
-
-
-
-
-
-
USART2_
CTS
UART4_TX
USART2_
RTS
UART4_RX
-
-
SPI1_
NSS
-
USART2_
TX
-
USART2_
RX
SPI3_
NSS/
I2S3_WS
USART2_
CK
SPI1_
SCK
SPI1_
MISO
-
-
-
-
-
USART1_
CK
USART1_
TX
USART1_
RX
USART1_
CTS
USART1_
RTS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OTG_HS_
ULPI_CK
-
TIM13_CH1 -
TIM14_CH1
-
-
OTG_FS_
SOF
ETH_MII_
RX_DV/
ETH_RMII
_CRS_DV
-
-
-
-
CAN1_RX
CAN1_TX
-
OTG_FS_
ID
OTG_FS_
DM
OTG_FS_
DP
-
-
-
AF12
-
-
-
-
-
-
-
-
AF13
FMC/SDIO
/OTG2_FS
DCMI
-
AF14
LCD
-
AF15
SYS
-
ETH_MII_
CRS
-
-
OTG_HS_
ULPI_D0
ETH_MII_
RX_CLK/E
TH_RMII_
REF_CLK
ETH_
MDIO
ETH_MII_
COL
-
-
-
-
-
-
-
EVEN
TOUT
EVEN
TOUT
-
-
-
-
LCD_B5
EVEN
TOUT
EVEN
TOUT
OTG_HS_
SOF
DCMI_
HSYNC
LCD_
VSYNC
EVEN
TOUT
-
EVEN
TOUT
DCMI_
PIXCLK
LCD_G2
EVEN
TOUT
EVEN
TOUT
-
-
DCMI_
D0
DCMI_
D1
-
LCD_R6
-
-
LCD_R4
LCD_R5
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Port
PA13
Port A PA14
JTMS-
SWDI
O
JTCK-
SWCL
K
-
-
PA15 JTDI
PB0
PB1
PB2 -
-
-
TIM2_
CH1/TIM2
_ETR
TIM1_
CH2N
TIM1_
CH3N
-
PB3
PB4
JTDO/
TRAC
ESWO
NJTR
ST
TIM2_
CH2
-
Port B
PB5
PB6
PB7
PB8
PB9
PB10
AF0
SYS
-
-
-
-
-
-
AF1
TIM1/2
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12
TIM3/4/5
TIM8/9/
10/11
I2C1/
2/3
SPI1/2/
3/4/5/6
SPI2/3/
SAI1
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
ETH
FMC/SDIO
/OTG2_FS
-
-
-
-
-
TIM2_
CH3
-
-
-
TIM3_
CH3
TIM3_
CH4
-
-
TIM3_
CH1
TIM3_
CH2
TIM4_
CH1
TIM4_
CH2
TIM4_
CH3
TIM4_
CH4
-
-
-
-
-
-
-
-
-
-
-
-
SPI1_
NSS
SPI3_
NSS/
I2S3_WS
-
TIM8_
CH2N
TIM8_
CH3N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM10_
CH1
TIM11_
CH1
-
-
I2C1_
SMBA
SPI1_
SCK
SPI1_
MISO
SPI1_
MOSI
I2C1_
SCL
I2C1_
SDA
I2C1_
SCL
-
-
-
I2C1_
SDA
I2C2_
SCL
SPI2_
NSS/I2
S2_WS
SPI2_
SCK/I2
S2_CK
SPI3_
SCK/
I2S3_CK
SPI3_
MISO
SPI3_
MOSI/
I2S3_SD
-
-
I2S3ext_
SD
-
-
USART1_
TX
USART1_
RX
-
-
-
-
-
USART3_
TX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OTG_HS_
ULPI_D3
ETH_MII_
RX_ER
-
-
-
AF13
DCMI
-
LCD_R3
LCD_R6
-
-
-
-
OTG_HS_
ULPI_D1
OTG_HS_
ULPI_D2
-
-
-
ETH_MII_
RXD2
ETH_MII_
RXD3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN2_RX
CAN2_TX
-
CAN1_RX
CAN1_TX
OTG_HS_
ULPI_D7
-
-
-
-
ETH_PPS
_OUT
-
-
-
ETH_MII_
TXD3
FMC_
SDCKE1
FMC_
SDNE1
FMC_NL
SDIO_D4
SDIO_D5
DCMI_
D10
-
EVEN
TOUT
DCMI_
D5
DCMI_
VSYNC
DCMI_
D6
-
-
LCD_B6
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
DCMI_
D7
LCD_B7
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
-
-
-
AF14
LCD
-
-
AF15
SYS
EVEN
TOUT
EVEN
TOUT
LCD_G4
EVEN
TOUT
Port
PB11
PB12
Port B
PB13
PB14
PC0
PC1
PC2
PC3
Port
C
PC4
PC5
PC6
PC7
AF0
SYS
-
-
-
-
-
-
-
-
-
-
-
-
PB15
RTC_
REFIN
AF1
TIM1/2
TIM2_
CH4
TIM1_
BKIN
TIM1_
CH1N
TIM1_
CH2N
TIM1_
CH3N
-
-
-
-
-
-
-
-
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
TIM3/4/5
-
-
-
-
-
-
-
-
-
TIM8/9/
10/11
TIM8_
CH2N
TIM8_
CH3N
-
-
-
-
I2C1/
2/3
I2C2_
SDA
I2C2_
SMBA
-
-
-
SPI1/2/
3/4/5/6
-
SPI2_
NSS/I2
S2_WS
SPI2_
SCK/I2
S2_CK
SPI2/3/
SAI1
-
-
-
SPI2_
MISO
SPI2_
MOSI/I2
S2_SD
I2S2ext_
SD
-
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
USART3_
RX
USART3_
CK
USART3_
CTS
USART3_
RTS
-
-
-
-
-
CAN2_RX
CAN2_TX
TIM12_CH1
OTG_HS_
ULPI_D4
OTG_HS_
ULPI_D5
OTG_HS_
ULPI_D6
ETH_MII_
TX_EN/
ETH_RMII
_TX_EN
ETH_MII_
TXD0/ETH
_RMII_
TXD0
ETH_MII_
TXD1/ETH
_RMII_TX
D1
-
-
OTG_HS_
ID
-
OTG_HS_
DM
TIM12_CH2 -
ETH
-
FMC/SDIO
/OTG2_FS
OTG_HS_
DP
-
OTG_HS_
ULPI_STP
-
FMC_SDN
WE
ETH_MDC -
-
-
-
-
SPI2_
MISO
SPI2_
MOSI/I2
S2_SD
I2S2ext_
SD
-
-
-
-
-
-
OTG_HS_
ULPI_DIR
OTG_HS_
ULPI_NXT
ETH_MII_
TXD2
ETH_MII_
TX_CLK
FMC_
SDNE0
FMC_
SDCKE0
-
-
TIM3_
CH1
TIM3_
CH2
-
-
TIM8_
CH1
TIM8_
CH2
-
-
-
-
I2S2_
MCK
-
-
-
-
-
-
I2S3_
MCK
-
-
-
-
-
-
USART6_
TX
USART6_
RX
-
-
-
-
-
-
-
-
ETH_MII_
RXD0/ETH
_RMII_
RXD0
ETH_MII_
RXD1/ETH
_RMII_
RXD1
-
-
-
SDIO_D6
SDIO_D7
DCMI
-
-
-
-
-
-
-
-
-
-
-
LCD
LCD_G5
-
-
-
-
-
-
-
-
-
-
SYS
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
DCMI_
D0
DCMI_
D1
LCD_
HSYNC
LCD_G6
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Port
PC8
PC10
Port
C
PC11
PC12
PC13
PC14
PC15
PD0
PD1
PD2
Port
D
PD3
PD4
PD5
PD6
AF0
SYS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PC9 MCO2
AF1
TIM1/2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12
TIM3/4/5
TIM3_
CH3
TIM3_
CH4
-
-
-
-
TIM8/9/
10/11
TIM8_
CH3
TIM8_
CH4
-
-
-
I2C1/
2/3
-
-
-
-
I2C3_
SDA
SPI1/2/
3/4/5/6
-
SPI2/3/
SAI1
-
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
-
USART6_
CK
-
I2S_
CKIN
-
-
-
I2S3ext
_SD
SPI3_
SCK/I2S
3_CK
SPI3_
MISO
SPI3_
MOSI/I2
S3_SD
USART3_
TX
UART4_TX
USART3_
RX
UART4_RX
USART3_
CK
UART5_TX -
-
-
-
-
-
-
-
-
ETH
-
-
-
-
-
-
FMC/SDIO
/OTG2_FS
-
-
-
-
TIM3_
ETR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI2_S
CK/I
2S2_CK
-
-
SPI3_
MOSI/I2
S3_SD
-
-
-
-
-
-
-
-
-
-
-
-
-
SAI1_
SD_A
USART2_
CTS
USART2_
RTS
USART2_
TX
USART2_
RX
-
-
-
-
UART5_RX
-
-
-
-
-
-
CAN1_RX
CAN1_TX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF13
DCMI
AF14
LCD
AF15
SYS
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
SDIO_CK
-
-
-
FMC_D2
DCMI_
D2
DCMI_
D3
DCMI_
D8
-
-
EVEN
TOUT
EVEN
TOUT
LCD_R2
EVEN
TOUT
DCMI_
D4
DCMI_
D9
-
-
-
-
-
-
-
DCMI_
D11
-
-
-
-
-
-
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
FMC_D3
SDIO_
CMD
FMC_CLK
DCMI_
D5
FMC_NOE
FMC_NWE -
-
LCD_G7
EVEN
TOUT
-
-
EVEN
TOUT
EVEN
TOUT
FMC_
NWAIT
DCMI_
D10
LCD_B2
EVEN
TOUT
Port
PD7
PD8
PD9
PD10
Port
D PD11
PD12
PD13
PD14
PD15
PE0
AF0
SYS
-
-
-
-
-
-
-
-
-
-
PE1 -
Port E
PE2
PE3
PE4
PE5
PE6
TRAC
ECLK
TRAC
ED0
TRAC
ED1
TRAC
ED2
TRAC
ED3
AF1
TIM1/2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM4_
CH1
TIM4_
CH2
TIM4_
CH3
TIM4_
CH4
TIM4_
ETR
-
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12
TIM3/4/5
TIM8/9/
10/11
I2C1/
2/3
SPI1/2/
3/4/5/6
SPI2/3/
SAI1
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
ETH
FMC/SDIO
/OTG2_FS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM9_
CH1
TIM9_
CH2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI4_
SCK
-
SPI4_
NSS
SPI4_M
ISO
SPI4_
MOSI
SAI1_
MCLK_A
SAI1_
SD_B
SAI1_
FS_A
SAI1_
SCK_A
SAI1_
SD_A
USART2_
CK
USART3_
TX
USART3_
RX
USART3_
CK
USART3_
CTS
USART3_
RTS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART8_Rx
UART8_Tx
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF13
DCMI
AF14
LCD
AF15
SYS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NE1/
FMC_
NCE2
FMC_D13
FMC_D14
FMC_D15
FMC_A16
FMC_A17
FMC_A18
FMC_D0
FMC_D1
FMC_
NBL0
FMC_
NBL1
ETH_MII_
TXD3
-
FMC_A23
FMC_A19
FMC_A20
FMC_A21
FMC_A22
-
EVEN
TOUT
-
DCMI_
D2
DCMI_
D3
-
-
-
-
-
-
-
-
-
DCMI_
D4
DCMI_
D6
DCMI_
D7
-
-
LCD_B3
-
-
-
-
-
-
-
-
-
LCD_B0
LCD_G0
LCD_G1
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Port
PE10
Port E PE11
PE12
PE7
PE8
PE9
Port F
PF3
PF4
PF5
PF6
PF7
PF0
PF1
PF2
PE13
PE14
PE15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF0
SYS
AF1
TIM1/2
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12
TIM3/4/5
TIM8/9/
10/11
I2C1/
2/3
SPI1/2/
3/4/5/6
SPI2/3/
SAI1
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
ETH
FMC/SDIO
/OTG2_FS
TIM1_
ETR
TIM1_
CH1N
TIM1_
CH1
TIM1_
CH2N
TIM1_
CH2
TIM1_
CH3N
TIM1_
CH3
TIM1_
CH4
TIM1_
BKIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C2_
SDA
I2C2_
SCL
I2C2_
SMBA
-
-
-
-
SPI4_
NSS
SPI4_
SCK
SPI4_
MISO
SPI4_
MOSI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UART7_Rx
UART7_Tx
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D4
FMC_D5
FMC_D6
FMC_D7
FMC_D8
FMC_D9
FMC_D10
FMC_D11
FMC_D12
FMC_A0
FMC_A1
FMC_A2
FMC_A3
AF13
DCMI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM10_
CH1
TIM11_
CH1
-
-
-
-
SPI5_
NSS
SPI5_
SCK
SAI1_
SD_B
SAI1_
MCLK_B
-
-
-
-
-
-
UART7_Rx
UART7_Tx -
-
-
-
-
-
-
-
-
-
-
FMC_A4
FMC_A5
FMC_
NIORD
FMC_
NREG
-
-
-
-
AF14
LCD
AF15
SYS
LCD_
CLK
-
-
-
-
-
-
LCD_G3
LCD_B4
LCD_DE
LCD_R7
-
-
-
-
-
-
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Port
PF8
PF9
PF10
PF11
Port F
PF12
PF13
PF14
PF15
PG0
PG1
PG2
PG3
Port
G
PG4
PG5
PG6
PG7
PG8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF0
SYS
AF1
TIM1/2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12
TIM3/4/5
TIM8/9/
10/11
I2C1/
2/3
SPI1/2/
3/4/5/6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPI5_
MISO
SPI5_
MOSI
-
SPI5_
MOSI
-
-
-
-
-
-
-
-
-
-
-
-
SPI6_
NSS
AF13 AF14 AF15
SPI2/3/
SAI1
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
SAI1_
SCK_B
SAI1_
FS_B
-
-
-
-
-
TIM13_CH1
TIM14_CH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART6_
CK
USART6_
RTS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ETH
FMC/SDIO
/OTG2_FS
DCMI LCD SYS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_
NIOWR
FMC_CD
FMC_INTR
FMC_
SDNRAS
DCMI_
D11
DCMI_
D12
FMC_A6
FMC_A7
FMC_A8
FMC_A9
FMC_A10
FMC_A11
FMC_A12
FMC_A13
FMC_A14/
FMC_BA0
FMC_A15/
FMC_BA1
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_INT2
FMC_INT3
DCMI_
D12
DCMI_
D13
ETH_PPS
_OUT
FMC_SDC
LK
-
LCD_DE
LCD_
CLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R7
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Port
PG9
PG10
PG11
Port
G
PG12
PG13
PG14
PH2
Port
H
PH3
PH4
PH5
PH6
PG15
PH0
PH1
-
-
-
-
-
-
-
-
AF0
SYS
-
-
-
-
-
-
AF1
TIM1/2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12
TIM3/4/5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF13 AF14 AF15
TIM8/9/
10/11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2C1/
2/3
-
-
-
-
-
-
-
-
-
-
SPI1/2/
3/4/5/6
SPI6_
MISO
SPI6_
SCK
SPI6_
MOSI
-
-
-
-
-
-
-
-
I2C2_
SCL
I2C2_
SDA
I2C2_
SMBA
-
SPI5_N
SS
SPI5_
SCK
SPI2/3/
SAI1
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART6_
RX
-
-
USART6_
RTS
USART6_
CTS
USART6_
TX
USART6_
CTS
-
-
-
-
-
-
-
ETH
FMC/SDIO
/OTG2_FS
DCMI LCD SYS
-
LCD_G3 -
-
-
-
FMC_NE2/
FMC_
NCE3
FMC_
NCE4_1/
FMC_NE3
DCMI_
VSYNC
(1)
DCMI_
D2
-
EVEN
TOUT
LCD_B2
EVEN
TOUT
-
ETH_MII_
TX_EN/
ETH_RMII
_TX_EN
FMC_
NCE4_2
DCMI_
D3
LCD_B3
EVEN
TOUT
LCD_B4 FMC_NE4 LCD_B1
EVEN
TOUT
-
-
-
-
ETH_MII_
TXD0/
ETH_RMII
_TXD0
ETH_MII_
TXD1/
ETH_RMII
_TXD1
FMC_A24
FMC_A25
-
FMC_
SDNCAS
-
-
-
-
EVEN
TOUT
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM12_CH1
-
-
OTG_HS_
ULPI_NXT
-
ETH_MII_
CRS
ETH_MII_
COL
FMC_
SDCKE0
FMC_SDN
E0
-
-
-
-
-
-
FMC_SDN
WE
FMC_
SDNE1
-
DCMI_
D8
DCMI_
D13
-
-
-
-
-
-
-
LCD_R0
LCD_R1
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
-
Port
PH7
PH8
PH9
PH10
Port
H
PH11
PH12
PH13
PH14
PH15
PI0
PI1
PI2
Port I
PI3
PI4
PI5
PI6
-
-
-
-
-
-
-
-
-
-
-
-
AF0
SYS
-
-
-
-
AF1
TIM1/2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
-
TIM5_
CH1
TIM5_
CH2
TIM5_
CH3
-
TIM3/4/5
TIM8/9/
10/11
I2C1/
2/3
SPI1/2/
3/4/5/6
SPI2/3/
SAI1
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
-
-
-
-
-
-
I2C3_
SCL
I2C3_
SDA
I2C3_
SMBA
SPI5_
MISO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM12_CH2
-
-
-
-
-
-
-
-
-
-
-
TIM8_
CH1N
TIM8_
CH2N
TIM8_
CH3N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CAN1_TX
-
-
-
-
-
-
-
TIM5_
CH4
-
-
-
-
-
-
-
TIM8_
CH4
TIM8_
ETR
TIM8_
BKIN
TIM8_
CH1
TIM8_
CH2
-
-
-
-
-
-
-
-
SPI2_
NSS/I2
S2_WS
SPI2_
SCK/I2
S2_CK
SPI2_
MISO
SPI2_M
OSI/I2S
2_SD
-
-
I2S2ext_
SD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ETH
-
-
-
-
-
FMC/SDIO
/OTG2_FS
ETH_MII_
RXD3
-
-
-
-
-
-
-
-
FMC_
SDCKE1
FMC_D16
FMC_D17
FMC_D18
FMC_D19
FMC_D20
FMC_D21
FMC_D22
FMC_D23
DCMI_
D9
DCMI_
HSYNC
DCMI_
D0
DCMI_
D1
DCMI_
D2
DCMI_
D3
-
DCMI_
D4
DCMI_
D11
-
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_G2
LCD_G3
LCD_G4
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
FMC_D24
DCMI_
D13
LCD_G5
EVEN
TOUT
FMC_D25
FMC_D26
DCMI
DCMI_
D8
DCMI_
D9
FMC_D27
DCMI_D
10
LCD SYS
LCD_G6
EVEN
TOUT
LCD_G7
EVEN
TOUT
EVEN
TOUT
FMC_
NBL2
FMC_
NBL3
FMC_D28
DCMI_D
5
DCMI_
VSYNC
DCMI_
D6
LCD_B4
LCD_B5
LCD_B6
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Port
PI10
Port I PI11
PI12
PI7
PI8
PI9
Port J
PJ3
PJ4
PJ5
PJ6
PJ7
PJ0
PJ1
PJ2
PI13
PI14
PI15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF0
SYS
AF1
TIM1/2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12
TIM3/4/5
TIM8/9/
10/11
I2C1/
2/3
SPI1/2/
3/4/5/6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIM8_
CH3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF13 AF14 AF15
SPI2/3/
SAI1
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ETH
FMC/SDIO
/OTG2_FS
DCMI LCD SYS
-
-
CAN1_RX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OTG_HS_
ULPI_DIR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FMC_D29
FMC_D30
ETH_MII_
RX_ER
FMC_D31
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DCMI_
D7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B7
-
LCD_
VSYNC
LCD_
HSYNC
-
LCD_
HSYNC
LCD_
VSYNC
LCD_
CLK
LCD_R0
LCD_R1
LCD_R2
LCD_R3
LCD_R4
LCD_R5
LCD_R6
LCD_R7
LCD_G0
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Port
PJ8
PJ9
PJ10
Port J
PJ11
PJ12
PJ13
PJ14
PJ15
PK0
PK1
PK2
Port K
PK3
PK4
PK5
PK6
AF0
SYS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF1
TIM1/2
Table 12. STM32F437xx and STM32F439xx alternate function mapping (continued)
AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12
TIM3/4/5
TIM8/9/
10/11
I2C1/
2/3
SPI1/2/
3/4/5/6
SPI2/3/
SAI1
SPI3/
USART1/
2/3
USART6/
UART4/5/7
/8
CAN1/2/
TIM12/13/14
/LCD
OTG2_HS
/OTG1_
FS
ETH
FMC/SDIO
/OTG2_FS
AF13
DCMI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PK7 -
1. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF14
LCD
AF15
SYS
LCD_G1
LCD_G2
LCD_G3
LCD_G4
LCD_B0
LCD_B1
LCD_B2
LCD_B3
LCD_G5
LCD_G6
LCD_G7
LCD_B4
LCD_B5
LCD_B6
LCD_B7
LCD_DE
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
EVEN
TOUT
Memory mapping STM32F437xx and STM32F439xx
The memory map is shown in
.
Figure 19. Memory map
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[)))))))
0E\WH
%ORFN
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EDQN
0E\WH
%ORFN
)0&EDQNWR
EDQN
[
[)))))))
0E\WH
%ORFN
3HULSKHUDOV
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[)))))))
0E\WH
%ORFN
65$0
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[)))))))
0E\WH
%ORFN
65$0
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5HVHUYHG
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65$0.%DOLDVHG
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5HVHUYHG
&&0GDWD5$0
.%GDWD65$0
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5HVHUYHG
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[[)))))))
[[))))
[&[))))
[[%)))
[)))&)[)))))))
[)))&[)))&
[)))$[))))))
[)))[)))$)
[))(&)[))())))
[))(&[))(&
[[))(%)))
[[))))
[[)))))))
[[)))))
[[))))))
[[)))))
5HVHUYHG
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SHULSKHUDOV
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5HVHUYHG
$+%
[([))))))))
[([()))))
[[')))))))
[&[)))))))
[%))
5HVHUYHG
[
[[)))))))
[))))
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$3%
5HVHUYHG
$3%
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[&[))))
[%))
[
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069
DocID024244 Rev 11
STM32F437xx and STM32F439xx Memory mapping
Table 13. STM32F437xx and STM32F439xx register boundary addresses
Bus Boundary address Peripheral
Cortex-M4
AHB3
AHB2
0xE00F FFFF - 0xFFFF FFFF
0xE000 0000 - 0xE00F FFFF
0xD000 0000 - 0xDFFF FFFF
0xC000 0000 - 0xCFFF FFFF
0xA000 1000 - 0xBFFF FFFF
0xA000 0000- 0xA000 0FFF
0x9000 0000 - 0x9FFF FFFF
0x8000 0000 - 0x8FFF FFFF
0x7000 0000 - 0x7FFF FFFF
0x6000 0000 - 0x6FFF FFFF
0x5006 0C00- 0x5FFF FFFF
0x5006 0800 - 0X5006 0BFF
0x5006 0400 - 0X5006 07FF
0x5006 0000 - 0X5006 03FF
0x5005 0400 - X5006 07FF
0x5005 0000 - 0X5005 03FF
0x5004 0000- 0x5004 FFFF
0x5000 0000 - 0X5003 FFFF
Reserved
Cortex-M4 internal peripherals
FMC bank 6
FMC bank 5
Reserved
FMC control register
FMC bank 4
FMC bank 3
FMC bank 2
FMC bank 1
Reserved
RNG
HASH
CRYP
Reserved
DCMI
Reserved
USB OTG FS
DocID024244 Rev 11
90
Memory mapping STM32F437xx and STM32F439xx
Table 13. STM32F437xx and STM32F439xx register boundary addresses (continued)
Bus Boundary address Peripheral
AHB1
0x4008 0000- 0x4FFF FFFF
0x4004 0000 - 0x4007 FFFF
0x4002 BC00- 0x4003 FFFF
0x4002 B000 - 0x4002 BBFF
0x4002 9400 - 0x4002 AFFF
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
0x4002 6800 - 0x4002 7FFF
0x4002 6400 - 0x4002 67FF
0x4002 6000 - 0x4002 63FF
0X4002 5000 - 0X4002 5FFF
0x4002 4000 - 0x4002 4FFF
0x4002 3C00 - 0x4002 3FFF
0x4002 3800 - 0x4002 3BFF
0X4002 3400 - 0X4002 37FF
0x4002 3000 - 0x4002 33FF
0x4002 2C00 - 0x4002 2FFF
0x4002 2800 - 0x4002 2BFF
0x4002 2400 - 0x4002 27FF
0x4002 2000 - 0x4002 23FF
0x4002 1C00 - 0x4002 1FFF
0x4002 1800 - 0x4002 1BFF
0x4002 1400 - 0x4002 17FF
0x4002 1000 - 0x4002 13FF
0X4002 0C00 - 0x4002 0FFF
0x4002 0800 - 0x4002 0BFF
0x4002 0400 - 0x4002 07FF
0x4002 0000 - 0x4002 03FF
Reserved
USB OTG HS
Reserved
DMA2D
Reserved
ETHERNET MAC
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Reserved
DMA2
DMA1
Reserved
BKPSRAM
Flash interface register
RCC
Reserved
CRC
Reserved
GPIOK
GPIOJ
GPIOI
GPIOH
DocID024244 Rev 11
STM32F437xx and STM32F439xx Memory mapping
Table 13. STM32F437xx and STM32F439xx register boundary addresses (continued)
Bus Boundary address Peripheral
APB2
0x4001 6C00- 0x4001 FFFF
0x4001 6800 - 0x4001 6BFF
0x4001 5C00 - 0x4001 67FF
0x4001 5800 - 0x4001 5BFF
0x4001 5400 - 0x4001 57FF
0x4001 5000 - 0x4001 53FF
0x4001 4C00 - 0x4001 4FFF
0x4001 4800 - 0x4001 4BFF
0x4001 4400 - 0x4001 47FF
0x4001 4000 - 0x4001 43FF
0x4001 3C00 - 0x4001 3FFF
0x4001 3800 - 0x4001 3BFF
0x4001 3400 - 0x4001 37FF
0x4001 3000 - 0x4001 33FF
0x4001 2C00 - 0x4001 2FFF
0x4001 2400 - 0x4001 2BFF
0x4001 2000 - 0x4001 23FF
0x4001 1800 - 0x4001 1FFF
0x4001 1400 - 0x4001 17FF
0x4001 1000 - 0x4001 13FF
0x4001 0800 - 0x4001 0FFF
0x4001 0400 - 0x4001 07FF
0x4001 0000 - 0x4001 03FF
Reserved
LCD-TFT
Reserved
SAI1
SPI6
SPI5
Reserved
TIM11
TIM10
TIM9
EXTI
SYSCFG
SPI4
SPI1
SDIO
Reserved
ADC1 - ADC2 - ADC3
Reserved
USART6
USART1
Reserved
TIM8
TIM1
DocID024244 Rev 11
90
Memory mapping STM32F437xx and STM32F439xx
Table 13. STM32F437xx and STM32F439xx register boundary addresses (continued)
Bus Boundary address Peripheral
APB1
0x4000 8000- 0x4000 FFFF
0x4000 7C00 - 0x4000 7FFF
0x4000 7800 - 0x4000 7BFF
0x4000 7400 - 0x4000 77FF
0x4000 7000 - 0x4000 73FF
0x4000 6C00 - 0x4000 6FFF
0x4000 6800 - 0x4000 6BFF
0x4000 6400 - 0x4000 67FF
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
0x4000 5800 - 0x4000 5BFF
0x4000 5400 - 0x4000 57FF
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 2000 - 0x4000 23FF
0x4000 1C00 - 0x4000 1FFF
0x4000 1800 - 0x4000 1BFF
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00 - 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
Reserved
UART8
UART7
DAC
PWR
Reserved
CAN2
CAN1
Reserved
I2C3
I2C2
I2C1
UART5
UART4
USART3
USART2
I2S3ext
SPI3 / I2S3
TIM14
TIM13
TIM12
TIM7
TIM6
TIM5
SPI2 / I2S2
I2S2ext
IWDG
WWDG
RTC & BKP Registers
Reserved
TIM4
TIM3
TIM2
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
6.1.1
Unless otherwise specified, all voltages are referenced to V
SS
.
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A the selected temperature range).
= 25 °C and T
A
= T
A max (given by
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).
Unless otherwise specified, typical data are based on T
A
= 25 °C, V
DD
1.7 V ≤ tested.
V
DD
= 3.3 V (for the
≤ 3.6 V voltage range). They are given only as design guidelines and are not
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )
.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
6.1.5
The loading conditions used for pin parameter measurement are shown in
.
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 21 .
Figure 20. Pin loading conditions Figure 21. Pin input voltage
-#5PIN
-#5PIN
#P& 6).
-36
-36
DocID024244 Rev 11
199
Electrical characteristics
6.1.6 Power supply scheme
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STM32F437xx and STM32F439xx
Figure 22. Power supply scheme
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1. To connect BYPASS_REG and PDR_ON pins, refer to Section 3.17: Power supply supervisor
and Section 3.18: Voltage regulator
2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is
OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the V
DD
pin.
4. V
DDA
=V
DD
and V
SSA
=V
SS
.
Caution: Each power supply pair (V
DD
/V
SS
, V
DDA
/V
SSA
...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 23. Current consumption measurement scheme
,''B9%$7
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,''
9''
9''$
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Absolute maximum ratings
Stresses above the absolute maximum ratings listed in
Table 14: Voltage characteristics
,
Table 15: Current characteristics
, and
Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Device mission profile (application conditions) is compliant with JEDEC JESD47
Qualification Standard, extended mission profiles are available on demand.
Symbol
Table 14. Voltage characteristics
Ratings Min Max Unit
V
|V
V
|
DD
Δ
V
V
–V
IN
DDx
SSX
− V
SS
|
SS
ESD(HBM)
|
External main supply voltage (including V
DDA
,
VBAT)
(1)
V
DD
and
Input voltage on FT pins
(2)
Input voltage on TTa pins
Input voltage on any other pin
Input voltage on BOOT0 pin
Variations between different V
DD
power pins
Variations between all the different ground pins including V
REF-
− 0.3
V
SS
− 0.3 V
DD
+4.0
V
SS
− 0.3
V
SS
− 0.3
4.0
4.0
V
-
SS
9.0
50
-
4.0
50
Electrostatic discharge voltage (human body model)
Absolute maximum ratings (electrical sensitivity)
V mV
1. All main power (V , V
DDA
) and ground (V supply, in the permitted range.
SS
, V
SSA
) pins must always be connected to the external power
2. V
IN
maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
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Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 15. Current characteristics
Ratings Max.
Unit
Σ
I
I
I
Σ I
Σ
I
VDD
I
VSS
VDD
VSS
IO
IO
Total current into sum of all V
DD_x power lines (source)
(1)
Total current out of sum of all V
SS_x ground lines (sink)
Maximum current into each V
DD_x
Maximum current out of each V
SS_x ground line (sink)
Output current sunk by any I/O and control pin
Output current sourced by any I/Os and control pin
Total output current sunk by sum of all I/O and control pins
(2)
Total output current sourced by sum of all I/Os and control pins
Injected current on FT pins
(4)
−
−
−
270
270
100
−
100
25
25
120
120 mA
Injected current on NRST and BOOT0 pins
− 5/+0
I
INJ(PIN)
(3)
Σ I
INJ(PIN)
(5)
Injected current on TTa pins
(5)
Total injected current (sum of all I/O and control pins)
(6)
±5
±25
1. All main power (V permitted range.
DD
, V
DDA
) and ground (V
SS
, V
SSA
) pins must always be connected to the external power supply, in the
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
5. A positive injection is induced by V exceeded. Refer to
>V
DDA
while a negative injection is induced by V
for the values of the maximum allowed input voltage.
IN
<V
SS
. I
INJ(PIN)
must never be
6. When several inputs are submitted to a current injection, the maximum negative injected currents (instantaneous values).
Σ I
INJ(PIN)
is the absolute sum of the positive and
Symbol
T
STG
T
J
Table 16. Thermal characteristics
Ratings
Storage temperature range
Maximum junction temperature
Value
− 65 to +150
125
Unit
°C
°C
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STM32F437xx and STM32F439xx Electrical characteristics
6.3.1 General operating conditions
Symbol f
HCLK f
PCLK1 f
PCLK2
V
DD
V
V
BAT
V
12
Parameter
Table 17. General operating conditions
Internal AHB clock frequency
Internal APB1 clock frequency
Internal APB2 clock frequency
Conditions
(1)
Min Typ Max Unit
Power Scale 3 (VOS[1:0] bits in
PWR_CR register = 0x01), Regulator
ON, over-drive OFF
Power Scale 2 (VOS[1:0] bits in PWR_CR register = 0x10),
Regulator ON
Overdrive OFF
Overdrive ON
Power Scale 1 (VOS[1:0] bits in PWR_CR register= 0x11),
Regulator ON
Overdrive OFF
Overdrive ON
Over-drive OFF
Over-drive ON
Over-drive OFF
Over-drive ON
0
0
0
0
0
0
0
1.7
(2) -
-
-
-
-
-
-
-
-
120
144
168
168
180
42
45
84
90
3.6
MHz
Standard operating voltage
Analog operating voltage
(ADC limited to 1.2 M samples)
Analog operating voltage
(ADC limited to 2.4 M samples)
Backup operating voltage
Must be the same potential as V
DD
(5)
1.7
2.4
1.65
-
-
2.4
3.6
3.6
V
Regulator ON: 1.2 V internal voltage on V
CAP_1
/V
CAP_2 pins
Regulator OFF: 1.2 V external voltage must be supplied from external regulator on
V
CAP_1
/V
CAP_2 pins
(6)
Power Scale 3 ((VOS[1:0] bits in
PWR_CR register = 0x01), 120 MHz
HCLK max frequency
Power Scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 144 MHz
HCLK max frequency with over-drive
OFF or 168 MHz with over-drive ON
Power Scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 168 MHz
HCLK max frequency with over-drive
OFF or 180 MHz with over-drive ON
Max frequency 120 MHz
Max frequency 144 MHz
Max frequency 168 MHz
1.08 1.14
1.20
1.20 1.26
1.32
1.26 1.32
1.40
1.10 1.14
1.20
1.20 1.26
1.32
1.26 1.32
1.38
V
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Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 17. General operating conditions (continued)
Parameter Conditions (1) Min Typ Max Unit
V
P
IN
D
Input voltage on RST and FT pins
(7)
Input voltage on TTa pins
Input voltage on BOOT0 pin
Power dissipation at T for suffix 6 or T
A suffix 7
(8)
A
= 85 °C
= 105 °C for
2 V
V
DD
≤
≤
V
DD
2 V
LQFP100
WLCSP143
LQFP144
UFBGA169
LQFP176
UFBGA176
LQFP208
≤ 3.6 V −
−
−
0.3
0.3
0.3
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.5
5.2
V
DDA
0.3
+
9
465
641
500
385
526
513
1053
V mW
T
T
A
J
Ambient temperature for 6 suffix version
TFBGA216
Maximum power dissipation
Low power dissipation
(9)
Ambient temperature for 7 suffix version
Maximum power dissipation
Low power dissipation
(9)
Junction temperature range
6 suffix version
7 suffix version
690
− 40 85
− 40 105
− 40 105
− 40 125
− 40 105
− 40 125
°C
°C
°C
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. V
DD
/V
DDA
minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to
).
3. When the ADC is used, refer to Table 74: ADC characteristics .
4. If V
REF+
pin is present, it must respect the following condition: V
DDA
-V
REF+
< 1.2 V.
5. It is recommended to power V and V
DDA from the same source. A maximum difference of 300 mV between V can be tolerated during power-up and power-down operation.
DD and V
DDA
6. The over-drive mode is not supported when the internal regulator is OFF.
7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
8. If T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
Jmax
.
9. In low power dissipation state, T
A
can be extended to this range as long as T
J
does not exceed T
Jmax
.
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STM32F437xx and STM32F439xx Electrical characteristics
Operating power supply range
Table 18. Limitations depending on the operating power supply range
ADC operation
Maximum Flash memory access frequency with no wait states
(f
Flashmax
)
Maximum HCLK frequency vs Flash memory wait states
(1)(2)
I/O operation
Possible Flash memory operations
V
DD
=1.7 to
2.1 V
(3)
V
DD
= 2.1 to
2.4 V
V
DD
= 2.4 to
2.7 V
V
DD
= 2.7 to
3.6 V
(5)
Conversion time up to 1.2 Msps
Conversion time up to 1.2 Msps
Conversion time up to 2.4 Msps
Conversion time up to 2.4 Msps
20 MHz
(4)
22 MHz
24 MHz
30 MHz
168 MHz with 8 wait states and over-drive
OFF
No I/O compensation
180 MHz with 8 wait states and over-drive
ON
No I/O compensation
180 MHz with 7 wait states and over-drive
ON
I/O compensation works
180 MHz with 5 wait states and over-drive
ON
I/O compensation works
8-bit erase and program operations only
16-bit erase and program operations
16-bit erase and program operations
32-bit erase and program operations
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution.
3. V
DD
/V
DDA
minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to
).
4. Prefetch is not available.
5. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V.
6.3.2 VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
EXT the VCAP1/VCAP2 pins. C
EXT
is specified in
to
Figure 24. External capacitor C
EXT
&
(65
5
/HDN
069
1. Legend: ESR is the equivalent series resistance.
Symbol
Table 19. VCAP1/VCAP2 operating conditions (1)
Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF
ESR ESR of external capacitor < 2 Ω
1. When bypassing the voltage regulator, the two 2.2 µF V replaced by two 100 nF decoupling capacitors.
CAP
capacitors are not required and should be
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Electrical characteristics STM32F437xx and STM32F439xx
Subject to general operating conditions for T
A
.
Table 20. Operating conditions at power-up / power-down (regulator ON)
Symbol Parameter Min Max Unit t
VDD
V
DD
rise time rate
V
DD
fall time rate
20
20
∞
∞
µs/V
Subject to general operating conditions for T
A
.
Table 21. Operating conditions at power-up / power-down (regulator OFF)
(1)
Symbol Parameter Conditions Min Max Unit t t
VDD
VCAP
V
DD
rise time rate Power-up
V
DD
fall time rate Power-down
V
CAP_1
and V
CAP_2 rise time rate Power-up
V
CAP_1
and V
CAP_2
fall time rate Power-down
20
20
20
20
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V
1.08 V.
DD
reach below
∞
∞
∞
∞
µs/V
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STM32F437xx and STM32F439xx
6.3.5 Reset and power control block characteristics
Electrical characteristics
The parameters given in
Table 22 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Symbol
Table 22. reset and power control block characteristics
Parameter Conditions
V
PVD
Programmable voltage detector level selection
V
PVDhyst
(1) PVD hysteresis
V
POR/PDR
Power-on/power-down reset threshold
Falling edge
Rising edge
V
PDRhyst
(1)
PDR hysteresis
V
V
BOR1
BOR2
Brownout level 1 threshold
Brownout level 2 threshold
V
BOR3
Brownout level 3 threshold
V
BORhyst
(1)
T
BOR hysteresis
POR reset temporization
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
PLS[2:0]=000 (rising edge)
PLS[2:0]=000 (falling edge)
PLS[2:0]=001 (rising edge)
PLS[2:0]=001 (falling edge)
PLS[2:0]=010 (rising edge)
PLS[2:0]=010 (falling edge)
PLS[2:0]=011 (rising edge)
PLS[2:0]=011 (falling edge)
PLS[2:0]=100 (rising edge)
PLS[2:0]=100 (falling edge)
PLS[2:0]=101 (rising edge)
PLS[2:0]=101 (falling edge)
PLS[2:0]=110 (rising edge)
PLS[2:0]=110 (falling edge)
PLS[2:0]=111 (rising edge)
PLS[2:0]=111 (falling edge)
Min Typ
2.09
2.14
2.19
1.98
2.04
2.08
2.23
2.30
2.37
2.13
2.19
2.25
2.39
2.45
2.51
2.29
2.35
2.39
2.54
2.60
2.65
2.44
2.51
2.56
2.70
2.76
2.82
2.59
2.66
2.71
2.86
2.93
2.99
2.65
2.84
2.92
2.96
3.03
3.10
2.85
2.93
2.99
3.07
3.14
3.21
2.95
3.03
3.09
100 -
1.60
1.68
1.76
1.64
1.72
1.80
40 -
2.13
2.19
2.24
2.23
2.29
2.33
2.44
2.50
2.56
2.53
2.59
2.63
2.75
2.83
2.88
2.85
2.92
2.97
100 -
0.5
1.5
Max Unit
3.0
V
V
V
V
V mV
V mV
V
V mV
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V ms
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Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 22. reset and power control block characteristics (continued)
Parameter Conditions Min Typ Max Unit
I
E
RUSH
(1)
RUSH
(1)
InRush current on voltage regulator poweron (POR or wakeup from Standby)
InRush energy on voltage regulator poweron (POR or wakeup from Standby)
V
DD
= 1.7 V, T
A
= 105 °C,
I
RUSH
= 171 mA for 31 µs
-
160
-
200
5.4
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from V when first instruction is read by the user application code.
BAT
) to the instant mA
µC
When the over-drive mode switches from enabled to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 23
. They are sbject to general operating conditions for T
A
.
Symbol
Table 23. Over-drive switching characteristics
(1)
Parameter Conditions
Tod_swen
Tod_swdis
HSI
Over_drive switch enable time
HSE max for 4 MHz and min for 26 MHz
External HSE
50 MHz
HSI
Over_drive switch disable time
HSE max for 4 MHz and min for 26 MHz.
External HSE
50 MHz
1. Guaranteed by design.
Min
45
20
-
-
-
-
Typ
45
40
20
-
-
15
Max
-
100
-
-
-
80
Unit
µs
DocID024244 Rev 11
STM32F437xx and STM32F439xx
6.3.7 Supply current characteristics
Electrical characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in
Figure 23: Current consumption measurement scheme
.
All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at V
DD
or V
SS
(no load).
• All peripherals are disabled except if it is explicitly mentioned.
• The Flash memory access time is adjusted both to f
HCLK
frequency and V
DD
(see Table 18: Limitations depending on the operating power supply range ).
range
• Regulator ON
• The voltage scaling and over-drive mode are adjusted to f
HCLK
– Scale 3 for f
HCLK
≤ 120 MHz
frequency as follows:
– Scale 2 for 120 MHz < f
HCLK
– Scale 1 for 144 MHz < f
HCLK
≤ 144 MHz
≤ 180 MHz. The over-drive is only ON at 180 MHz.
• The system clock is HCLK, f
PCLK1
= f
HCLK
/4, and f
PCLK2
= f
HCLK
/2.
• External clock frequency is 4 MHz and PLL is ON when f
HCLK
is higher than 25 MHz.
• The maximum values are obtained for V
DD temperature (T
A
= 3.6 V and a maximum ambient
), and the typical values for T
A
= 25 °C and V
DD
= 3.3 V unless otherwise specified.
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Electrical characteristics STM32F437xx and STM32F439xx
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled except prefetch) or RAM (1)
Max (2)
Symbol Parameter Conditions f
HCLK
(MHz) Typ
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Unit
I
DD
Supply current in
RUN mode
All
Peripherals enabled
(3)(4)
All
Peripherals
8
7
7
3
3
2
41
36
33
25
20
14
13
11
5
4
2
44
54
43
29
16
98
89
75
72
30
25
16
8
4
2
168
150
144
120
90
60
25
16
8
4
2
180
120
90
60
30
180
168
150
144
43
39
36
34
33
87
83
73
72
85
66
62
46
141
133
115
112
39
37
35
56
53
45
34
33
33
16
13
9
8
7
39
37
58
45
30
20
98
(5)
84
81
12
10
9
29
23
16
7
6
6 mA
26
24
22
21
20
20
66
57
56
43
41
34
30
27
23
21
20
69
72
56
52
34
123
116
100
96
1. Code and data processing running from SRAM1 using boot pins.
2. Guaranteed by characterization.
3. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.
5. Guaranteed by test in production.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 25. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled)
Max
(1)
Symbol Parameter Conditions f
HCLK
(MHz) Typ
TA=
25 °C
TA=85 °C TA=105 °C
Unit
I
DD
Supply current in
RUN mode
All Peripherals enabled
(2)(3)
8
4
25
16
2
180
168
150
120
90
60
30
180
168
150
144
7
5
17
12
3
57
50
46
66
54
37
20
103
98
87
85
21
16
11
8
7
62
54
50
71
58
39
24
112
107
95
92
35
30
24
22
21
87
76
70
85
69
47
39
140
126
112
108 mA
All Peripherals disabled
60
30
25
16
8
144
120
90
45
36
29
21
13
11
8
5
49
41
34
24
17
15
12
9
68
56
46
33
31
28
25
23
84
69
57
41
44
41
38
35
4
2
4
3
7
6.5
21
20
34
33
1. Guaranteed by characterization unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.
48
42
37
35
34
106
93
86
99
80
55
51
151
144
128
124
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Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 26. Typical and maximum current consumption in Sleep mode
Max
(1)
Parameter Conditions f
HCLK
(MHz) Typ
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Unit
I
DD
Supply current in
Sleep mode
All
Peripherals enabled
(2)
8
4
25
16
2
180
168
150
120
90
60
30
180
168
150
144
3
3
9
5
2
21
16
14
40
32
22
10
78
66
56
54
8
7
14
12
6.5
17
44
34
23
16
75
(3)
61
58
28
25
22
21
20
54
41
36
59
46
31
30
110
93
80
78 mA
All
Peripherals disabled
60
30
25
16
8
144
120
90
13
10
8
6
5
3
3
2
16.5
14
13
9
8
7
7
6
35
28
26
24
22
21
21
20
51
41
37
37
35
34
34
33
4
2
2
2
6
6
20
20
33
33
1. Guaranteed by characterization unless otherwise specified.
2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.
3. Based on characterization, tested in production.
40
40
35
34
33
52
72
56
45
43
130
96
94
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol
Table 27. Typical and maximum current consumptions in Stop mode
Max
(1)
Typ
Parameter Conditions
V
DD
= 3.6 V
T
A
=
25 °C
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C
Unit
Supply current in Stop mode with voltage regulator in main regulator mode
Flash memory in Stop mode, all oscillators OFF, no independent watchdog
Flash memory in Deep power down mode, all oscillators OFF, no independent watchdog
I
DD_STOP_NM
(normal mode)
Supply current in Stop mode with voltage regulator in Low Power regulator mode
Flash memory in Stop mode, all oscillators OFF, no independent watchdog
Flash memory in Deep power down mode, all oscillators OFF, no independent watchdog
I
DD_STOP_UDM
(under-drive mode)
Supply current in Stop mode with voltage regulator in main regulator and underdrive mode
Flash memory in Deep power down mode, main regulator in under-drive mode, all oscillators
OFF, no independent watchdog
Supply current in Stop mode with voltage regulator in Low Power regulator and underdrive mode
Flash memory in Deep power down mode, Low Power regulator in under-drive mode, all oscillators
OFF, no independent watchdog
1. Data based on characterization, tested in production.
0.40
0.35
0.29
0.23
0.19
0.10
1.50
14.00
25.00
1.50
14.00
25.00
1.10
10.00
18.00
1.10
10.00
18.00
0.50
6.00
9.00
0.40
4.00
7.00
mA
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Electrical characteristics STM32F437xx and STM32F439xx
Table 28. Typical and maximum current consumptions in Standby mode
Typ
(1)
Max
(2)
Symbol Parameter Conditions
T
A
= 25 °C
T
A
=
25 °C
T
A
=
85 °C
T
A
=
105 °C Unit
V
DD
=
1.7 V
V
DD
=
2.4 V
V
DD
=
3.3 V
V
DD
= 3.6 V
Backup SRAM ON, low-speed oscillator (LSE) and RTC ON
I
DD_STBY
Supply current in Standby mode
Backup SRAM OFF, lowspeed oscillator (LSE) and
RTC ON
Backup SRAM ON, RTC and
LSE OFF
Backup SRAM OFF, RTC and
LSE OFF
2.80
2.30
2.30
1.70
3.00
2.60
2.50
1.90
3.60
3.10
2.90
2.20
7.00
6.00
6.00
(3)
19.00
16.00
36.00
31.00
µA
1. The typical current consumption values are given with PDR OFF (internal reset OFF). When the PDR is OFF (internal reset
OFF), the typical current consumption is reduced by additional 1.2 µA.
2. Based on characterization, not tested in production unless otherwise specified.
3. Based on characterization, tested in production.
Table 29. Typical and maximum current consumptions in V
BAT
mode
Typ Max (2)
Symbol Parameter Conditions
(1)
T
A
= 25 °C
V
BAT
=
1.7 V
V
BAT
=
2.4 V
V
BAT
=
3.3 V
Backup SRAM ON, low-speed oscillator (LSE) and RTC ON
I
DD_VBAT
Backup domain supply current
Backup SRAM OFF, low-speed oscillator (LSE) and RTC ON
Backup SRAM ON, RTC and
LSE OFF
Backup SRAM OFF, RTC and
LSE OFF
1.28
0.66
0.70
0.10
1.40
0.76
0.72
0.10
1.62
0.97
0.74
0.10
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a C
L
of 6 pF for typical values.
2. Guaranteed by characterization results.
T
A
= 85 °C
V
6
3
5
2
BAT
T
A
=
105 °C
= 3.6 V
11
5
10
4
Unit
µA
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 25. Typical V
BAT
current consumption (LSE and RTC ON/backup RAM OFF)
# # #
4EMPERATURE
#
6
6
6
6
6
6
6
6
6
#
-36
Figure 26. Typical V
BAT
current consumption (LSE and RTC ON/backup RAM ON)
# # #
4EMPERATURE
#
6
6
6
6
6
6
6
6
6
#
-36
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Electrical characteristics STM32F437xx and STM32F439xx
Additional current consumption
The MCU is placed under the following conditions:
• All I/O pins are configured in analog mode.
• The Flash memory access time is adjusted to fHCLK frequency.
• The voltage scaling is adjusted to fHCLK frequency as follows:
– Scale 3 for f
HCLK
≤ 120 MHz,
– Scale 2 for 120 MHz < f
HCLK
≤ 144 MHz
– Scale 1 for 144 MHz < f
HCLK
≤ 180 MHz. The over-drive is only ON at 180 MHz.
• The system clock is HCLK, f
PCLK1
= f
HCLK
/4, and f
PCLK2
= f
HCLK
/2.
• HSE crystal clock frequency is 25 MHz.
• When the regulator is OFF, V12 is provided externally as described in
• T
A
= 25 °C .
Table 30. Typical current consumption in Run mode, code with data processing running from
Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch),
V
DD
=1.7 V (1)
Symbol Parameter Conditions f
HCLK
(MHz) Typ Unit
I
DD
Supply current in
RUN mode from
V
DD
supply
All Peripheral enabled
All Peripheral disabled
90
60
30
25
168
150
144
120
90
60
30
25
168
150
144
120
88.2
74.3
71.3
52.9
42.6
28.6
15.7
12.3
40.6
30.6
32.6
24.7
19.7
13.6
7.7
6.7
mA
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherls (such as ADC, or
DAC) is not included.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 31.
Typical current consumption in Run mode, code with data processing running
from Flash memory, regulator OFF (ART accelerator enabled except prefetch) (1)
VDD=3.3 V VDD=1.7 V
Symbol Parameter Conditions f
HCLK
(MHz)
168
I
DD12
77.8
I
DD
1.3
I
DD12
76.8
I
DD
1.0
Unit
I
DD12
/ I
DD
Supply current in
RUN mode from
V
12
and V
DD supply
All Peripherals enabled
All Peripherals disabled
33.4
30.3
23.2
18.0
12.5
6.9
6.1
26.8
15.4
13.5
37.0
69.8
63.6
49.3
38.7
1.3
1.3
1.2
1.4
1.2
1.2
1.2
1.2
1.2
1.2
1.3
1.3
1.3
1.2
1.3
34.6
31.3
24.0
18.1
12.9
7.2
6.3
27.2
15.6
13.6
38.2
70.8
64.5
49.9
39.2
150
144
120
90
60
30
25
60
30
25
168
150
144
120
90 mA
1.0
1.0
0.9
1.0
0.9
0.9
0.9
0.9
0.9
0.9
1.0
1.0
1.0
0.9
1.0
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included.
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Electrical characteristics STM32F437xx and STM32F439xx
Table 32. Typical current consumption in Sleep mode, regulator ON, V
DD
=1.7 V (1)
Symbol Parameter Conditions f
HCLK
(MHz) Typ
I
DD
Supply current in Sleep mode from V
DD
supply
All Peripherals enabled
All Peripherals disabled
168
150
144
120
90
60
30
25
90
60
30
25
168
150
144
120
15.7
13.7
12.7
9.7
7.7
5.7
4.7
2.8
31.6
21.7
9.8
8.8
65.5
55.5
53.5
39.0
Unit mA
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol
I
DD12
/I
DD
Table 33. Tyical current consumption in Sleep mode, regulator OFF (1)
VDD=3.3 V VDD=1.7 V
Parameter Conditions f
HCLK
(MHz)
180
I
DD12
61.5
I
DD
1.4
I
DD12
-
I
DD
-
Supply current in Sleep mode from V
12
V
DD
and
supply
All Peripherals enabled
All Peripherals disabled
1.4
1.3
1.3
1.3
1.2
1.4
1.2
1.2
1.2
1.4
1.2
1.2
1.2
1.3
1.3
1.3
1.2
14.9
14.0
12.6
11.5
8.7
7.1
29.3
20.2
11.9
10.4
59.4
53.9
49.0
38.0
5.0
3.1
2.8
180
168
150
144
120
90
60
30
25
90
60
30
25
168
150
144
120
-
14.0
12.6
11.5
8.7
7.1
29.3
20.2
11.9
10.4
59.4
53.9
49.0
38.0
5.0
3.1
2.8
-
1.0
1.0
1.0
0.9
1.1
0.9
0.9
0.9
1.1
0.9
0.9
0.9
1.0
1.0
1.0
0.9
Unit mA
1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC, or DAC) is not included.
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Electrical characteristics STM32F437xx and STM32F439xx
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in
Table 56: I/O static characteristics .
For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.
I/O dynamic current consumption
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:
I
SW
=
V
DD
×
f
SW
×
C where
I
SW
is the current sunk by a switching I/O to charge/discharge the capacitive load
V
DD
is the MCU supply voltage f
SW
is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = C
INT
+ C
EXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol
Table 34. Switching output I/O current consumption (1)
Parameter Conditions
I/O toggling
frequency
(fsw)
Typ Unit
I
I
DDIO
DDIO
I/O switching
Current
I/O switching
Current
V
DD
V
C
C = C
V
DD
C
EXT
= 3.3 V
INT
= 3.3 V
= 10 pF
C = C
INT
+ C
EXT
V
C
EXT
C = C
INT
+ C
EXT
V
C
C= C
DD
DD
DD
+ C
S
+ C
S
EXT
C = C
= 3.3 V
= 22 pF
= 3.3 V
= 33 pF
INT
+ Cext
+ C
S
(2)
= 3.3 V
EXT
= 0 pF
INT
+ C
+ C
S
EXT
8 MHz
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
8 MHz
25 MHz
50 MHz
60 MHz
2 MHz
8 MHz
25 MHz
50 MHz
2 MHz
8 MHz
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
2 MHz
2 MHz
8 MHz
25 MHz
50 MHz
60 MHz
84 MHz
90 MHz
1. C
S
is the PCB board capacitance including the pad pin. C
S
= 7 pF (estimated value).
2. This test is performed by cutting the LQFP176 package pin (pad removal).
0.26
1.01
3.14
6.39
10.68
0.33
0.67
2.09
3.6
4.5
7.8
9.8
1.29
4.23
11.02
0.1
0.4
1.23
2.43
2.93
3.86
4.07
0.18
1.1
1.3
1.8
1.9
0.0
0.2
0.6
mA mA
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Electrical characteristics STM32F437xx and STM32F439xx
On-chip peripheral current consumption
The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• I/O compensation cell enabled.
• The ART accelerator is ON.
• Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
• HCLK is the system clock. f
PCLK1
= f
HCLK
/4, and f
PCLK2
= f
HCLK
/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
– f
HCLK f
HCLK
= 180 MHz (Scale1 + over-drive ON), f
= 120 MHz (Scale 3)"
HCLK
= 144 MHz (Scale 2),
• Ambient operating temperature is 25 °C and V
DD
=3.3 V.
AHB1
(up to
180 MHz)
Peripheral
Table 35. Peripheral current consumption
I
DD
( Typ)
(1)
Scale 1 Scale 2 Scale 3
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIOH
GPIOI
GPIOJ
GPIOK
OTG_HS+ULPI
CRC
BKPSRAM
DMA1
DMA2
DMA2D
ETH_MAC
ETH_MAC_TX
ETH_MAC_RX
ETH_MAC_PTP
2.39
2.33
2.33
27.00
0.44
0.78
2.50
2.56
2.44
2.50
2.44
2.44
2.39
2.33
25.33
24.72
28.50
21.56
2.22
2.15
2.15
24.86
0.42
0.69
2.36
2.36
2.29
2.36
2.29
2.29
2.22
2.15
23.26
22.71
26.32
20.07
2.00
1.92
1.92
21.92
0.33
0.58
2.08
2.08
2.00
2.08
2.00
2.00
2.00
1.92
20.50
20.00
23.33
17.75
Unit
µA/MHz
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 35. Peripheral current consumption (continued)
I
DD
( Typ) (1)
Peripheral
Scale 1 Scale 2 Scale 3
AHB2
(up to
180 MHz)
OTG_FS
DCMI
RNG
Hash
Crypto
AHB3
(up to
180 MHz)
FMC
Bus matrix
(2)
25.67
3.72
2.28
4.39
3.00
21.39
14.06
26.67
3.40
2.36
4.03
2.78
19.79
13.19
23.58
3.00
2.17
3.58
2.42
17.50
11.75
Unit
µA/MHz
µA/MHz
µA/MHz
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
APB1
(up to
45 MHz)
2.89
3.33
6.89
6.67
2.89
0.89
3.78
4.00
4.00
4.00
3.11
3.56
4.89
5.56
11.11
4.22
4.44
4.00
4.00
4.00
17.56
14.22
14.89
17.33
2.89
3.11
7.33
Table 35. Peripheral current consumption (continued)
I
DD
( Typ) (1)
Peripheral
Scale 1 Scale 2 Scale 3
TIM13
TIM14
PWR
USART2
USART3
UART4
UART5
UART7
UART8
I2C1
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
TIM12
I2C2
I2C3
SPI2
(3)
SPI3
I2S2
I2S3
CAN1
CAN2
DAC
(4)
WWDG
2.81
3.08
6.42
6.14
2.25
0.86
3.92
3.92
3.92
3.92
3.08
3.36
4.47
5.31
10.31
3.92
4.19
3.92
3.92
3.92
16.42
13.36
13.64
16.42
2.53
2.81
6.97
2.47
2.80
5.80
5.47
2.13
0.80
3.47
3.47
3.47
3.47
2.80
3.13
4.13
4.80
9.13
3.47
3.80
3.47
3.47
3.47
14.47
11.80
12.13
14.47
2.47
2.47
6.13
Unit
µA/MHz
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 35. Peripheral current consumption (continued)
I
DD
( Typ) (1)
Peripheral
Scale 1 Scale 2 Scale 3
Unit
APB2
(up to
90 MHz)
SDIO
TIM1
TIM8
TIM9
TIM10
TIM11
ADC1
(5)
ADC2
(5)
ADC3
(5)
SPI1
USART1
USART6
SPI4
SPI5
SPI6
SYSCFG
LCD_TFT
SAI1
8.11
17.11
17.33
7.22
4.56
4.78
4.67
4.78
4.56
1.44
4.00
4.00
1.44
1.44
1.44
0.78
39.89
3.78
8.75
15.97
16.11
6.67
4.31
4.44
4.31
4.44
4.17
1.39
3.75
3.75
1.39
1.39
1.39
0.69
37.22
3.47
7.83
14.17
14.33
6.00
3.83
4.00
3.83
4.00
3.67
1.17
3.33
3.33
1.17
1.17
1.17
0.67
33.17
3.17
µA/MHz
1. When the I/O compensation cell is ON, I
DD
typical value increases by 0.22 mA.
2. The BusMatrix is automatically active when at least one master is ON.
3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.8 mA per DAC channel for the analog part.
5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.6 mA per ADC for the analog part.
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Electrical characteristics STM32F437xx and STM32F439xx
6.3.8
Symbol
Wakeup time from low-power modes
The wakeup times given in Table 36
are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and V
DD
=3.3 V.
Table 36. Low-power mode wakeup timings
Parameter Conditions Typ
(1)
Max
(1) t
WUSLEEP
(2)
Wakeup from Sleep 6 -
Unit
CPU clock cycle
Main regulator is ON 13.6
t
Wakeup from Stop mode with MR/LP regulator in normal mode
Main regulator is ON and Flash memory in Deep power down mode
Low power regulator is ON
93
22
111
32
Low power regulator is ON and Flash memory in Deep power down mode
103 126 t
Wakeup from Stop mode with MR/LP regulator in
Under-drive mode
Main regulator in under-drive mode
(Flash memory in Deep power-down mode)
Low power regulator in under-drive mode
(Flash memory in Deep power-down mode ) tWUSTDBY
Wakeup from Standby mode
105
125
318
128
155
412
1. Guaranteed by characterization results.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
3. t
WUSTDBY maximum value is given at –40 °C.
µ s
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 56: I/O static characteristics . However, the
recommended clock input waveform is shown in Figure 27 .
The characteristics given in
Table 37 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions summarized in
Symbol
Table 37. High-speed external user clock characteristics
Parameter f
HSE_ext
External user clock source frequency
(1)
V
HSEH
V
HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)
C in(HSE)
DuCy
(HSE)
I
L
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
OSC_IN high or low time
OSC_IN rise or fall time
(1)
(1)
OSC_IN input capacitance
Duty cycle
(1)
OSC_IN Input leakage current
1. Guaranteed by design.
Conditions
V
SS
≤ V
IN
≤ V
DD
Min
1
0.7V
DD
V
SS
5
-
-
45
-
Typ
5
-
-
-
-
-
-
-
Max Unit
50
V
DD
0.3V
DD
-
10
-
55
±1
MHz
V ns pF
%
µA
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 56: I/O static characteristics . However, the
recommended clock input waveform is shown in Figure 28 .
The characteristics given in
Table 38 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions summarized in
Symbol
Table 38. Low-speed external user clock characteristics
Parameter f
LSE_ext
V
LSEH
User External clock source frequency
(1)
OSC32_IN input pin high level voltage
V
LSEL t w(LSE) t f(LSE) t r(LSE) t f(LSE)
C in(LSE)
DuCy
(LSE)
I
L
OSC32_IN input pin low level voltage
OSC32_IN high or low time
OSC32_IN rise or fall time
(1)
(1)
OSC32_IN input capacitance
Duty cycle
(1)
OSC32_IN Input leakage current
1. Guaranteed by design.
Conditions
V
SS
≤ V
IN
≤ V
DD
Min
-
0.7V
DD
V
SS
450
-
-
30
-
Typ
32.768
-
-
-
-
5
-
-
Max
1000
V
DD
0.3V
DD
-
50
-
70
±1
Unit kHz
V ns pF
%
µA
Figure 27. High-speed external clock source AC timing diagram
6(3%(
6(3%,
TR(3%
4(3%
TF(3%
%XTERNAL
CLOCKSOURCE
F(3%?EXT
/3#?).
T7(3%
),
34-&
T7(3% T
AI
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 28. Low-speed external clock source AC timing diagram
9/6(+
9/6(/
WU/6(
7/6(
WI/6( W:/6(
W:/6( W
([WHUQDO
FORFNVRXUFH
I/6(BH[W
26&B,1
,/
670)
DL
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 39
. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
Table 39. HSE 4-26 MHz oscillator characteristics (1)
Parameter Conditions Min Typ Max Unit f
OSC_IN
R
F
Oscillator frequency
Feedback resistor
4
-
-
200
26 MHz
k Ω
I
DD
HSE current consumption
V
DD
=3.3 V,
ESR= 30 Ω ,
C
L
=5 pF@25 MHz
V
DD
=3.3 V,
ESR= 30 Ω ,
C
L
=10 pF@25 MHz
-
450
530 -
-
µA
ACC
HSE
(2)
HSE accuracy
G m
_crit_max Maximum critical crystal g m t
SU(HSE
(3)
Startup time
Startup
− 500
-
-
-
500
1 ppm mA/V
V
DD
is stabilized 2 ms
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. The minimum and maximum values must be respected to comply with USB standard specifications.
3. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is based on characterization and not tested in production. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
DocID024244 Rev 11
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Electrical characteristics
Note:
STM32F437xx and STM32F439xx
For C
L1
and C
L2
, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see
). C
L1
and C
L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C
L1
and C
L2
. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
C
L1
and C
L2
.
For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com
.
Figure 29. Typical application with an 8 MHz crystal
Note:
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&/
0+]
UHVRQDWRU
26&B,1
26&B28 7
5)
%LDV
FRQWUROOHG
JDLQ
I+6(
&/
5(;7 670)
DL
1. R
EXT
value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 40
. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).
Symbol
Table 40. LSE oscillator characteristics (f
LSE
= 32.768 kHz) (1)
Parameter Conditions Min Typ Max Unit
R
F
I
DD
ACC
LSE
(2)
Feedback resistor
LSE current consumption
LSE accuracy
G m
_crit_max Maximum critical crystal g m t
SU(LSE)
(3) startup time
Startup
−
-
500
-
18.4
-
-
-
-
1
500
0.56
M
V
DD
is stabilized 2 s
1. Guaranteed by design.
2. This parameter depends on the crystal used in the application. Refer to application note AN2867.
3. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is based on characterization and not tested in production. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Ω
µA ppm
µA/V
For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com
.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 30. Typical application with a 32.768 kHz crystal
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
&/
N+ ]
UHVRQDWRU
26&B,1
5)
%LDV
FRQWUROOHG
JDLQ
26&B28 7
&/
I/6(
670)
DL
6.3.10 Internal clock source characteristics
The parameters given in
Table 42 are derived from tests performed under
ambient temperature and V
DD
supply voltage conditions summarized in
.
High-speed internal (HSI) RC oscillator
Symbol
Table 41. HSI oscillator characteristics (1)
Parameter Conditions f
HSI
ACC
HSI
Frequency -
HSI user-trimming step
(2)
Accuracy of the HSI oscillator
HSI oscillator startup time
T
A
= –40 to 105 °C
(3)
T
A
= –10 to 85 °C
(3)
T
A
= 25 °C
(4)
-
t su(HSI)
(2)
I
DD(HSI)
(2)
HSI oscillator power consumption
1. V
DD
= 3.3 V, T
A
= –40 to 105 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Factory calibrated, parts not soldered.
-
Min Typ Max Unit
-
-
− 8
− 4
− 1
-
-
16
-
-
-
-
2.2
60
-
1
4.5
4
1
4
80 µA
MHz
%
%
%
%
µs
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Electrical characteristics STM32F437xx and STM32F439xx
Figure 31. ACCHSI accuracy versus temperature
7$&
0LQ 0D[ 7\SLFDO
06Y9
1. Guaranteed by characterization results.
Low-speed internal (LSI) RC oscillator
Symbol
Table 42. LSI oscillator characteristics (1)
Parameter f
LSI
(2) t su(LSI)
(3)
I
DD(LSI)
(3)
Frequency
LSI oscillator startup time
LSI oscillator power consumption
1. V
DD
= 3 V, T
A
= –40 to 105 °C unless otherwise specified.
2. Guaranteed by characterization results.
3. Guaranteed by design.
Min
17
-
-
Typ
32
15
0.4
Max
47
40
0.6
Unit kHz
µs
µA
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 32. ACC
LSI
versus temperature
MAX
AVG
MIN
4EMPERAT URE #
-36
The parameters given in
Table 44 are derived from tests performed under
temperature and V
DD
supply voltage conditions summarized in
Symbol f
PLL_IN f
PLL_OUT f
PLL48_OUT f
VCO_OUT t
LOCK
Table 43. Main PLL characteristics
Parameter
PLL input clock
(1)
PLL multiplier output clock
48 MHz PLL multiplier output clock
PLL VCO output
Conditions Min
0.95
(2)
24
-
PLL lock time
VCO freq = 100 MHz
VCO freq = 432 MHz
100
75
100
Typ
1
-
48
-
-
-
Max
2.10
180
75
432
200
300
Unit
MHz
MHz
MHz
MHz
µs
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Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 43. Main PLL characteristics (continued)
Parameter Conditions Min Typ Max Unit
I
I
Jitter
(3)
DD(PLL)
(4)
DDA(PLL)
(4)
Cycle-to-cycle jitter
Period Jitter
Main clock output (MCO) for
RMII Ethernet
Main clock output (MCO) for MII
Ethernet
System clock
120 MHz
RMS peak to peak
RMS peak to peak
Cycle to cycle at 50 MHz on 1000 samples
Cycle to cycle at 25 MHz on 1000 samples
Bit Time CAN jitter
PLL power consumption on VDD
Cycle to cycle at 1 MHz on 1000 samples
VCO freq = 100 MHz
VCO freq = 432 MHz
PLL power consumption on
VDDA
VCO freq = 100 MHz
VCO freq = 432 MHz
-
-
-
-
-
-
-
0.15
0.45
0.30
0.55
±
±
25
150
15
200
32
40
330
-
-
-
-
-
-
-
-
-
0.40
0.75
0.40
0.85
ps mA mA
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization results.
Symbol f
PLLI2S_IN f
PLLI2S_OUT f
VCO_OUT t
LOCK
Jitter
(3)
Table 44. PLLI2S (audio PLL) characteristics
Parameter Conditions Min
PLLI2S input clock
(1)
PLLI2S multiplier output clock
PLLI2S VCO output
PLLI2S lock time
Master I2S clock jitter
WS I2S clock jitter
VCO freq = 100 MHz
VCO freq = 432 MHz
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
Average frequency of
12.288 MHz
N = 432, R = 5 on 1000 samples
Cycle to cycle at 48 KHz on 1000 samples
RMS
peak to peak
0.95
(2)
-
100
75
100
-
-
-
± 280
90
400
Typ
-
-
1
-
-
90
Max
2.10
216
432
200
300
-
-
Unit
MHz
MHz
MHz
µs ps
-
ps ps
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol
Table 44. PLLI2S (audio PLL) characteristics (continued)
Parameter Conditions Min
I
I
DD(PLLI2S)
(4)
DDA(PLLI2S)
(4)
PLLI2S power consumption on
V
DD
PLLI2S power consumption on
V
DDA
VCO freq = 100 MHz
VCO freq = 432 MHz
VCO freq = 100 MHz
VCO freq = 432 MHz
0.15
0.45
0.30
0.55
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Typ
-
-
Max
0.40
0.75
0.40
0.85
Unit mA mA
Symbol
Table 45. PLLISAI (audio and LCD-TFT PLL) characteristics
Parameter Conditions Min Typ f f f
PLLSAI_IN
PLLSAI_OUT
VCO_OUT
PLLSAI input clock
(1)
PLLSAI multiplier output clock
PLLSAI VCO output
0.95
(2)
-
100
75 t
LOCK
Jitter
(3)
PLLSAI lock time
Main SAI clock jitter
FS clock jitter
I
DD(PLLSAI)
(4)
I
DDA(PLLSAI)
(4)
PLLSAI power consumption on
V
DD
PLLSAI power consumption on
V
DDA
VCO freq = 100 MHz
VCO freq = 432 MHz
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
Average frequency of
12.288 MHz
N = 432, R = 5 on 1000 samples
RMS
peak to peak
Cycle to cycle at 48 KHz on 1000 samples
VCO freq = 100 MHz
VCO freq = 432 MHz
VCO freq = 100 MHz
VCO freq = 432 MHz
100
-
-
-
-
0.15
0.45
0.30
0.55
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
-
90
± 280
90
400
-
-
-
-
1
-
Max
2.10
216
432
200
300
-
-
Unit
MHz
MHz
MHz
µs ps
-
-
0.40
0.75
0.40
0.85
ps ps mA mA
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Electrical characteristics STM32F437xx and STM32F439xx
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 52: EMI characteristics
). It is available only on the main PLL.
Symbol f
Mod md
MODEPER * INCSTEP
1. Guaranteed by design.
Table 46. SSCG parameters constraint
Parameter Min
Modulation frequency
Peak modulation depth
-
0.25
-
Typ
-
-
-
Max
(1)
10
2
2
15 − 1
Unit
KHz
%
-
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = [
PLL_IN
⁄ ( 4 × f
Mod
) ] f
PLL_IN and f
Mod must be expressed in Hz.
As an example:
If f
PLL_IN
= 1 MHz, and f
MOD
= 1 kHz, the modulation depth (MODEPER) is given by equation 1:
MODEPER = round 10
6
⁄ ( 4 × 10
3
) ] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
INCSTEP = round [ ( ( 2
15
– 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ] f
VCO_OUT must be expressed in MHz.
With a modulation depth (md) = ± 2 % (4 % peak to peak), and PLLN = 240 (in MHz):
INCSTEP = round [ ( ( 2
15
– 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ]
= 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized
% = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2
15
– 1 ) × PLLN )
As a result: md quantized
% =
( 250 × 126 × 100 × 5 ) ⁄ ( ( 2
15
– 1 ) × 240 )
= 2.002%(peak)
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
and
Figure 34 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is f
PLL_OUT
nominal.
T mode
is the modulation period.
md is the modulation depth.
Figure 33. PLL output clock waveforms in center spread mode
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MD
&
MD
TMODE XTMODE
4IME
Figure 34. PLL output clock waveforms in down spread mode
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[PG
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7LPH
DLE
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Electrical characteristics STM32F437xx and STM32F439xx
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Symbol
I
DD
Parameter
Table 47. Flash memory characteristics
Conditions Min
Supply current
Write / Erase 8-bit mode, V
DD
= 1.7 V
Write / Erase 16-bit mode, V
DD
= 2.1 V
Write / Erase 32-bit mode, V
DD
= 3.3 V
-
-
-
Typ
5
8
12
Max Unit
-
-
mA
Symbol
Table 48. Flash memory programming
Parameter Conditions t t t prog
ERASE16KB
ERASE64KB
Word programming time
Sector (16 KB) erase time
Sector (64 KB) erase time
Program/erase parallelism
(PSIZE) = x 8/16/32
Program/erase parallelism
(PSIZE) = x 8
Program/erase parallelism
(PSIZE) = x 16
Program/erase parallelism
(PSIZE) = x 32
Program/erase parallelism
(PSIZE) = x 8
Program/erase parallelism
(PSIZE) = x 16
Program/erase parallelism
(PSIZE) = x 32
Program/erase parallelism
(PSIZE) = x 8 t
ERASE128KB
Sector (128 KB) erase time
Program/erase parallelism
(PSIZE) = x 16 t
ME
Mass erase time
Program/erase parallelism
(PSIZE) = x 32
Program/erase parallelism
(PSIZE) = x 8
Program/erase parallelism
(PSIZE) = x 16
Program/erase parallelism
(PSIZE) = x 32
Min
(1)
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ Max
(1)
Unit
16 100
(2)
400
300
250
1200 2400
700 1400
550 1100
2
1.3
1
16
11
8
800
600
500
4
2.6
2
32
22
16
µs ms ms s s
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol
Table 48. Flash memory programming (continued)
Parameter Conditions
V t
BE prog
Bank erase time
Programming voltage
Program/erase parallelism
(PSIZE) = x 8
Program/erase parallelism
(PSIZE) = x 16
Program/erase parallelism
(PSIZE) = x 32
32-bit program operation
16-bit program operation
8-bit program operation
1. Guaranteed by characterization results.
2. The maximum programming time is measured after 100K erase operations.
Min (1)
-
-
-
2.7
2.1
1.7
Typ Max (1)
16
11
8
-
-
-
32
22
16
3.6
3.6
3.6
Unit s
V
V
V
Symbol
Table 49. Flash memory programming with V
PP
Parameter Conditions Min
(1)
Typ Max
(1)
16 100
(2) t prog t
ERASE16KB t
ERASE64KB t
ERASE128KB t
ME t
BE
V prog
V
PP
Double word programming
Sector (16 KB) erase time
Sector (64 KB) erase time
Sector (128 KB) erase time
Mass erase time
Bank erase time
Programming voltage
T
A
=
V
V
0 to +40 °C
DD
PP
= 3.3 V
= 8.5 V t
I
PP
VPP
(3)
V
PP
voltage range
Minimum current sunk on the V
PP
pin
Cumulative time during which V
PP is applied
1. Guaranteed by design.
2. The maximum programming time is measured after 100K erase operations.
3. V
PP
should only be connected during programming/erasing.
-
-
-
-
-
-
-
2.7
7
10
230
490
875
6.9
6.9
-
-
-
-
-
-
3.6
-
-
9
-
-
1
Unit
µs ms s s
V
V mA hour
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Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 50. Flash memory endurance and data retention
Value
Parameter Conditions
Min
(1)
N t
END
RET
Endurance
Data retention
T
A
= –40 to +85 °C (6 suffix versions)
T
A
= –40 to +105 °C (7 suffix versions)
1 kcycle
(2)
at T
A
= 85 °C
1 kcycle
(2)
at T
A
= 105 °C
10 kcycles
(2)
at T
A
= 55 °C
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.
10
30
10
20
Unit kcycles
Years
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB : A burst of fast transient voltage (positive and negative) is applied to V
DD
and V
SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in
. They are based on the EMS levels and classes defined in application note AN1709.
Symbol
Table 51. EMS characteristics
Parameter Conditions
Level/
Class
V
FESD
V
EFTB
Voltage limits to be applied on any I/O pin to induce a functional disturbance
Fast transient voltage burst limits to be applied through 100 pF on V
DD
and V pins to induce a functional disturbance
SS
V
DD
= 3.3 V, LQFP176, T
A
+25 °C, f
HCLK to IEC 61000-4-2
=
= 168 MHz, conforms f
V
DD
= 3.3 V, LQFP176, T
A
HCLK
IEC 61000-4-2
=+25 °C,
= 168 MHz, conforms to
2B
4A
When the application is exposed to a noisy environment, it is recommended to avoid pin exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,
PA2, PH2, PH3, PH4, PH5, PA3, PA4, PA5, PA6, PA7, PC4, and PC5.
As a consequence, it is recommended to add a serial resistor (1 k Ώ ) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB).
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC
?
code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.
S
EMI
Symbol Parameter
Peak level
Table 52. EMI characteristics
Conditions
Monitored frequency band
[f
Max vs.
HSE
/f
CPU
]
Max vs.
[f
HSE
/f
CPU
]
25/168 MHz 25/180 MHz
V
DD
= 3.3 V, T
A
= 25 °C, LQFP176 package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral clocks enabled, clock dithering disabled.
V
DD
= 3.3 V, T
A
= 25 °C, LQFP176 package, conforming to SAE J1752/3
EEMBC, ART ON, all peripheral clocks enabled, clock dithering enabled
0.1 to 30 MHz
30 to 130 MHz
130 MHz to
1GHz
SAE EMI Level
0.1 to 30 MHz
30 to 130 MHz
130 MHz to
1GHz
SAE EMI level
16
23
25
4
17
8
11
3.5
19
23
22
4
16
10
16
3.5
Unit dBµV
-
dBµV
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Electrical characteristics STM32F437xx and STM32F439xx
6.3.15 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards.
Symbol Ratings
Table 53. ESD absolute maximum ratings
Conditions Class
Maximum value
(1)
Unit
V
ESD(HBM)
Electrostatic discharge voltage (human body model)
2 2000
V
ESD(CDM)
Electrostatic discharge voltage (charge device model)
T
A
= +25 °C conforming to
ANSI/ESDA/JEDEC JS-001
T
A
= +25 °C conforming to ANSI/ESD S5.3.1,
LQFP100/144/176, UFBGA169/176,
TFBGA176 and WLCSP143 packages
T
A
= +25 °C conforming to ANSI/ESD S5.3.1,
LQFP208 package
C3
C3
250
250
V
1. Guaranteed by characterization results.
Symbol
LU
Static latchup
Two complementary static tests are required on six parts to assess the latchup performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Parameter
Static latch-up class
Table 54. Electrical sensitivities
Conditions
T
A
= +105 °C conforming to JESD78A
Class
II level A
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V
SS above V
DD
or
(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –
5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.
The test results are given in
.
Symbol
Table 55. I/O current injection susceptibility
(1)
Functional susceptibility
Description
Negative injection
− 0
− 0
Positive injection
NA
NA
Injected current on BOOT0 pin
Injected current on NRST pin
I
INJ
Injected current on PA0, PA1, PA2, PA3, PA6, PA7, PB0,
PC0, PC1, PC2, PC3, PC4, PC5, PH1, PH2, PH3, PH4, PH5
Injected current on TTa pins: PA4 and PA5
Injected current on any other FT pin
1. NA = not applicable .
− 0
− 0
− 5
NA
+5
NA
Unit mA
Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
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Electrical characteristics STM32F437xx and STM32F439xx
Symbol
General input/output characteristics
Unless otherwise specified, the parameters given in Table 56: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 17
.
All I/Os are
CMOS and TTL compliant.
Parameter
Table 56. I/O static characteristics
Conditions Min
FT, TTa and NRST I/O input low level voltage
1.7 V ≤ V
DD
≤ 3.6 V -
V
V
V
HYS
I
IL
IH lkg
BOOT0 I/O input low level voltage
1.75 V ≤ V
40 °C ≤ T
DD
A
≤
≤ 3.6 V, –
105 °C
1.7 V ≤ V
0 °C ≤ T
DD
A
≤
≤ 3.6 V,
105 °C
-
-
FT, TTa and NRST I/O input high level voltage
(5)
1.7 V ≤ V
DD
≤ 3.6 V
0.45V
DD
+0.3
(1)
0.7V
DD
(2)
BOOT0 I/O input high level voltage
1.75 V ≤ V
40 °C ≤ T
DD
A
≤
≤ 3.6 V, –
105 °C
1.7 V ≤ V
0 °C ≤ T
DD
A
≤
≤ 3.6 V,
105 °C
FT, TTa and NRST I/O input hysteresis
1.7 V ≤ V
DD
≤ 3.6 V
BOOT0 I/O input hysteresis
I/O input leakage current
(4)
I/O FT input leakage current
(5)
1.75 V ≤ V
40 °C ≤ T
DD
A
≤
≤ 3.6 V, –
105 °C
1.7 V ≤ V
0 °C ≤ T
DD
A
≤
≤ 3.6 V,
105 °C
V
SS
≤ V
IN
≤ V
DD
V
IN
= 5 V
0.17V
DD
+0.7
(1)
10%V
-
-
DD
(3)
0.1
Typ Max
0.35V
− 0.04
-
0.3V
DD
(2)
Unit
V
-
0.1V
DD
+0.1
(1)
-
-
-
-
-
-
-
-
-
-
-
± 1
3
V
V
µA
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol
Table 56. I/O static characteristics (continued)
Parameter Conditions Min Typ Max Unit
R
PU
All pins except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
V
IN
= V
SS
30 40 50
Weak pull-up equivalent resistor
(6)
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
7 10 14 k Ω
R
PD
Weak pulldown equivalent resistor
(7)
All pins except for
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
V
IN
= V
DD
30 40 50
PA10/PB12
(OTG_FS_ID,
OTG_HS_ID)
7 10 14
C
IO
(8)
I/O pin capacitance 5 -
1. Guaranteed by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to
Table 55: I/O current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
pF
All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in
.
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
Figure 35. FT I/O input characteristics
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or source up to ± 20 mA (with a relaxed V
OL
/V
OH
) except PC13, PC14, PC15 and PI8 which can sink or source up to ± 3mA. When using the PC13 to PC15 and PI8 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in
. In particular:
• The sum of the currents sourced by all the I/Os on V
DD, consumption of the MCU sourced on V
Σ I
VDD
(see
DD, plus the maximum Run cannot exceed the absolute maximum rating
• The sum of the currents sunk by all the I/Os on V
SS consumption of the MCU sunk on V
Σ I
VSS
(see
SS
plus the maximum Run
cannot exceed the absolute maximum rating
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 57
are derived from tests performed under ambient temperature and V
DD
supply voltage conditions summarized in
Table 17 . All I/Os are CMOS and TTL compliant.
Symbol
Table 57. Output voltage characteristics
Parameter Conditions Min Max Unit
V
V
V
V
OL
(1)
OH
(3)
OL
(1)
OH
(3)
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
CMOS port
(2)
I
IO
= +8 mA
2.7 V ≤ V
DD
≤
TTL port
(2)
I
IO
=+ 8mA
2.7 V ≤
DD
3.6 V
V
DD
-
-
−
2.4
0.4
0.4
-
-
0.4
V
V
V
OL
(1)
V
OH
(3)
V
OL
(1)
V
OH
(3)
V
OL
(1)
V
OH
(3)
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
I
2.7 V
I
1.8 V
I
IO
IO
IO
1.7 V
= +20 mA
≤
≤
≤
DD
DD
DD
3.6 V
= +6 mA
3.6 V
= +4 mA
3.6V
V
DD
V
DD
V
DD
-
− 1.3
(4)
-
− 0.4
(4)
-
− 0.4
(5)
1.3
0.4
-
-
0.4
-
(4)
(4)
(5)
1. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in Table 15
. and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VDD
.
4. Based on characterization data.
5. Guaranteed by design.
V
V
V
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
OSPEEDRy
[1:0] bit value
(1)
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in
Unless otherwise specified, the parameters given in Table 58
are derived from tests performed under the ambient temperature and V
DD in
supply voltage conditions summarized
Table 58. I/O AC characteristics (1)(2)
Symbol Parameter Conditions Min Typ Max Unit
00 f max(IO)out
Maximum frequency
(3) t f(IO)out
/ t r(IO)out
Output high to low level fall time and output low to high level rise time
C
L
= 50 pF, V
DD
≥ 2.7 V -
C
L
= 50 pF, V
DD
≥ 1.7 V -
C
L
= 10 pF, V
DD
≥ 2.7 V
C
L
= 10 pF, V
DD
≥ 1.8 V
C
L
= 10 pF, V
DD
≥ 1.7 V
-
-
C
L
= 50 pF, V
3.6 V
DD
= 1.7 V to
-
-
-
-
-
-
-
8
4
4
2
3
100
MHz ns
01
10 f max(IO)out
Maximum frequency
(3) t f(IO)out
/ t r(IO)out f max(IO)out
Maximum frequency
(3) t f(IO)out
/ t r(IO)out
Output high to low level fall time and output low to high level rise time
Output high to low level fall time and output low to high level rise time
C
L
= 50 pF, V
DD
≥ 2.7 V
C
L
= 50 pF, V
DD
≥ 1.8 V
C
L
= 50 pF, V
DD
≥ 1.7 V
C
L
= 10 pF, V
DD
≥ 2.7 V
C
L
= 10 pF, V
DD
≥ 1.8 V
C
L
= 10 pF, V
DD
≥ 1.7 V
C
L
= 50 pF, V
DD
≥ 2.7 V
C
L
= 10 pF, V
DD
≥ 2.7 V
C
L
= 50 pF, V
DD
≥ 1.7 V
C
L
= 10 pF, V
DD
≥ 1.7 V
C
L
= 40 pF, V
DD
≥ 2.7 V
C
L
= 10 pF, V
DD
≥ 2.7 V
C
L
= 40 pF, V
DD
≥ 1.7 V
C
L
= 10 pF, V
DD
≥ 1.8 V
C
L
= 10 pF, V
DD
≥ 1.7 V
C
L
= 40 pF, V
DD
≥ 2.7 V
C
L
= 10 pF, V
DD
≥ 2.7 V
C
L
= 40 pF, V
DD
≥ 1.7 V
C
L
= 10 pF, V
DD
≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12.5
10
6
20
10
50
(4)
25
50
25
12.5
10
50
20
42.5
6
4
10
6
MHz ns
MHz ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 58. I/O AC characteristics (1)(2) (continued)
OSPEEDRy
[1:0] bit value
(1)
Symbol Parameter Conditions Min Typ Max Unit
11
f max(IO)out t t f(IO)out r(IO)out
/ tEXTIpw
Maximum frequency
(3)
C
L
= 30 pF, V
DD
≥ 2.7 V
C
L
= 30 pF, V
DD
≥ 1.8 V
C
L
= 30 pF, V
DD
≥ 1.7 V
C
L
= 10 pF, V
DD
≥ 2.7 V
C
L
= 10 pF, V
DD
≥ 1.8 V
C
L
= 10 pF, V
DD
≥ 1.7 V
C
L
= 30 pF, V
DD
≥ 2.7 V
C
L
= 30 pF, V
DD
≥ 1.8 V
Output high to low level fall time and output low to high level rise time
Pulse width of external signals detected by the EXTI controller
-
C
L
= 30 pF, V
DD
≥ 1.7 V
C
L
= 10 pF, V
DD
≥ 2.7 V
C
L
= 10 pF, V
DD
≥ 1.8 V
C
L
= 10 pF, V
DD
≥ 1.7 V
-
-
-
-
-
-
-
-
-
-
-
-
10
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz ns ns
1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 36 .
4. For maximum frequencies above 50 MHz and V
DD
> 2.4 V, the compensation cell should be used.
4
6
7
2.5
3.5
4
50
42.5
100
72.5
Figure 36. I/O AC characteristics definition
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DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R
PU
(see
Table 56: I/O static characteristics ).
Unless otherwise specified, the parameters given in Table 59
are derived from tests performed under the ambient temperature and V
DD in
supply voltage conditions summarized
Symbol
Table 59. NRST pin characteristics
Parameter Conditions Min Typ Max
R
PU
V
F(NRST)
(2)
V
T
NRST_OUT
Weak pull-up equivalent resistor
(1)
NRST Input filtered pulse
NRST Input not filtered pulse
Generated reset pulse duration
V
IN
= V
SS
V
DD
> 2.7 V
Internal Reset source
30
-
300
20
40
-
-
-
50
100
-
-
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order)
.
2. Guaranteed by design.
Unit k Ω ns ns
µs
Figure 37. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the V
Table 59 . Otherwise the reset is not taken into account by the device.
IL(NRST)
max level specified in
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
The parameters given in
Table 60 are guaranteed by design.
Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Symbol
Table 60. TIMx characteristics
(1)(2)
Parameter Conditions
(3) Min Max Unit t res(TIM) f
EXT
Timer resolution time
AHB/APBx prescaler=1 or 2 or 4, f
TIMxCLK
=
180 MHz f
AHB/APBx prescaler>4,
TIMxCLK
= 90 MHz
Timer external clock frequency on CH1 to CH4 f
TIMxCLK
= 180 MHz
Timer resolution Res
TIM t
MAX_COUNT
Maximum possible count with 32-bit counter
1
1
0
-
f
-
-
TIMxCLK
16/32
65536 ×
65536
/2 t t t
TIMxCLK
TIMxCLK
MHz bit
TIMxCLK
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
2. Guaranteed by design.
3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK =
4x PCLKx.
I
2
C interface characteristics
The I
2
C interface meets the timings requirements of the I
2
C-bus specification and user manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
The I
2
C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0090 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V
DD
Section 6.3.17: I/O port characteristics
is disabled, but is still present. Refer to
for more details on the I
2 C I/O characteristics.
All I
2
C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 61. I2C analog filter characteristics (1)
Parameter t
AF
Maximum pulse width of spikes that are suppressed by the analog filter
1. Guaranteed by design.
2. Spikes with widths below t
AF(min) are filtered.
3. Spikes with widths above t
AF(max)
are not filtered
Min
50
(2)
Max
260
(3)
Unit ns
Symbol f
SCK
1/t c(SCK)
Duty(SCK)
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 62
for the SPI interface are derived from tests performed under the ambient temperature, f
PCLKx frequency and V
DD
supply voltage conditions summarized in Table 17 , with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Parameter
Table 62. SPI dynamic characteristics (1)
Conditions Min
SPI clock frequency
Master mode, SPI1/4/5/6,
2.7 V ≤ V
DD
≤ 3.6 V
Receiver
Slave mode,
SPI1/4/5/6,
2.7 V ≤ V
DD
≤ 3.6 V
Transmitter/ full-duplex
Master mode, SPI1/2/3/4/5/6,
1.7 V ≤ V
DD
≤ 3.6 V
Slave mode, SPI1/2/3/4/5/6,
1.7 V ≤ V
DD
≤ 3.6 V
Duty cycle of SPI clock frequency
Slave mode
-
-
30
Typ
-
-
50
Max
45
45
38
(2)
22.5
22.5
70
Unit
MHz
%
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol
Table 62. SPI dynamic characteristics (1) (continued)
Parameter Conditions Min Typ Max Unit t t w(SCKH) w(SCKL) t su(NSS) t h(NSS) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO
)
SCK high and low time
NSS setup time
NSS hold time
Data input setup time
Data input hold time
Master mode, SPI presc = 2,
2.7 V ≤ V
DD
≤ 3.6 V
Master mode, SPI presc = 2,
1.7 V ≤ V
DD
≤ 3.6 V
Slave mode, SPI presc = 2
Slave mode, SPI presc = 2
Master mode
Slave mode
Master mode
Slave mode
Data output access time Slave mode, SPI presc = 2
T
PCLK
T
PCLK
4 T
2 T
3
0
2
0
− 0.5
T
PCLK
0.5
− 2 T
PCLK
PCLK
PCLK
-
-
-
-
-
-
T
PCLK
+0.5
T
PCLK
-
-
-
-
-
+2
4 T
PCLK ns t t t dis(SO) t v(SO) h(SO) v(MO)
Data output disable time
Data output valid/hold time
Data output valid time
Slave mode, SPI1/4/5/6,
2.7 V ≤ V
DD
≤ 3.6 V
Slave mode, SPI1/2/3/4/5/6 and
1.7 V ≤ V
DD
≤ 3.6 V
Slave mode (after enable edge),
SPI1/4/5/6 and 2.7V ≤ V
DD
≤ 3.6V
Slave mode (after enable edge),
SPI2/3, 2.7 V ≤ V
DD
≤ 3.6 V
Slave mode (after enable edge),
SPI1/4/5/6, 1.7 V ≤ V
DD
≤ 3.6 V
Slave mode (after enable edge),
SPI2/3, 1.7 V ≤ V
DD
≤ 3.6 V
Master mode (after enable edge),
SPI1/4/5/6, 2.7 V ≤ V
DD
≤ 3.6 V
Master mode (after enable edge),
SPI1/2/3/4/5/6, 1.7 V ≤ V
DD
≤ 3.6 V
Master mode (after enable edge)
0
0
-
-
-
-
-
-
-
-
11
14
15.5
15.5
-
-
8.5
16.5
13
15
19
17.5
2.5
4.5
ns t h(MO)
Data output hold time 0 -
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of t having t su(MI)
= 0 while Duty(SCK) = 50% v(SO)
and t su(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
Figure 38. SPI timing diagram - slave mode and CPHA = 0
Figure 39. SPI timing diagram - slave mode and CPHA = 1
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Figure 40. SPI timing diagram - master mode
Electrical characteristics
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DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
I
2
S interface characteristics
Unless otherwise specified, the parameters given in Table 63
for the I 2 S interface are derived from tests performed under the ambient temperature, f
PCLKx frequency and V
DD
supply voltage conditions summarized in Table 17 , with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Symbol f
MCK f
CK
D
CK t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t h(SD_ST) t v(SD_MT)
Parameter
Table 63. I
2
S dynamic characteristics
(1)
Conditions
I2S Main clock output
I2S clock frequency
-
Master data: 32 bits
Slave data: 32 bits
I2S clock frequency duty cycle Slave receiver
WS valid time Master mode
WS hold time
WS setup time
WS hold time
Master mode
Slave mode
Slave mode
Data input setup time
Data input hold time
Master receiver
Slave receiver
Master receiver
Slave receiver
Data output valid time
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
7.5
2
0
0
0
1
0
Min Max
256x8K 256xFs (2)
30
0
-
64xFs
64xFs
70
6
-
-
-
-
-
-
-
-
27
20 t h(SD_MT)
Data output hold time Master transmitter (after enable edge) 2.5
-
Unit
MHz
MHz
% ns
1. Guaranteed by characterization results.
2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency).
Note: Refer to the I2S section of RM0090 reference manual for more details on the sampling frequency (F
S
). f
MCK
, f
CK
, and D
CK
values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. D
CK
depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F
S maximum value is supported for each mode/condition.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 41. I 2 S slave timing diagram (Philips protocol) (1)
1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
Figure 42. I 2 S master timing diagram (Philips protocol) (1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
SAI characteristics
Unless otherwise specified, the parameters given in
for SAI are derived from tests performed under the ambient temperature, f
PCLKx
frequency and VDD supply voltage
conditions summarized in Table 17
, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (SCK,SD,WS).
Table 64. SAI characteristics
(1)
Symbol Parameter Conditions Min Unit f
MCKL
F
SCK
SAI Main clock output
SAI clock frequency
-
Master data: 32 bits
Slave data: 32 bits
256 x 8K 256xFs (2)
-
64xFs
64xFs
MHz
MHz
D
SCK t v(FS) t su(FS)
SAI clock frequency duty cycle
FS valid time
FS setup time
Slave receiver 30 70 % t h(FS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t h(SD_ST)
FS hold time
Data input setup time
Data input hold time
Data output valid time
Master mode
Slave mode
Master mode
Slave mode
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter (after enable edge)
0
5
3
0
0
8
2
8
-
-
-
-
-
-
22
-
-
22 ns t v(SD_MT) t h(SD_MT)
Data output hold time
Master transmitter (after enable edge)
Master transmitter (after enable edge)
-
8
20
-
1. Guaranteed by characterization results.
2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency)
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 43. SAI master timing waveforms
F3#+
3!)?3#+?8
TH&3
3!)?&3?8
OUTPUT
3!)?3$?8
TRANSMIT
TV&3
3!)?3$?8
RECEIVE
TSU3$?-2
TV3$?-4
3LOTN
TH3$?-2
3LOTN
3LOTN
TH3$?-4
-36
Figure 44. SAI slave timing waveforms
F3#+
3!)?3#+?8
TW#+(?8
3!)?&3?8
INPUT
3!)?3$?8
TRANSMIT
TSU&3
3!)?3$?8
RECEIVE
TW#+,?8 TH&3
TSU3$?32
TV3$?34
3LOTN
TH3$?32
3LOTN
3LOTN
TH3$?34
-36
DocID024244 Rev 11
199
Electrical characteristics
Note:
STM32F437xx and STM32F439xx
USB OTG full speed (FS) characteristics
This interface is present in both the USB OTG HS and USB OTG FS controllers.
Symbol
Table 65. USB OTG full speed startup time
Parameter t
STARTUP
(1)
USB OTG full speed transceiver startup time
1. Guaranteed by design.
Max
1
Unit
µs
Symbol
Table 66. USB OTG full speed DC electrical characteristics
Parameter Conditions Min.
(1) Typ. Max.
(1) Unit
V
DD
USB OTG full speed transceiver operating voltage
Input levels
V
DI
(3)
Differential input sensitivity
Output levels
R
PD
V
CM
(3)
Differential common mode range
V
SE
V
(3)
OL
V
OH
Single ended receiver threshold
Static output level low
Static output level high
PA11, PA12, PB14, PB15
(USB_FS_DP/DM,
USB_HS_DP/DM)
PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
PA12, PB15 (USB_FS_DP,
USB_HS_DP)
R
PU PA9, PB13
(OTG_FS_VBUS,
OTG_HS_VBUS)
I(USB_FS_DP/DM,
USB_HS_DP/DM)
Includes V
DI range
R
L
of 1.5 k Ω to 3.6 V (4)
R
L
of 15 k Ω to V
SS
(4)
V
IN
= V
DD
V
IN
= V
SS
V
IN
= V
SS
3.0
(2)
0.2
0.8
1.3
-
2.8
17
0.65
1.1
1.5
-
-
-
-
-
-
21
1.8
3.6
-
2.5
2.0
0.3
3.6
24
2.0
2.1
0.25
0.37
0.55
k Ω
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V V
DD
voltage range.
3. Guaranteed by design.
4. R
L
is the load connected on the USB OTG full speed drivers.
V
V
V
When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 and PB13 when the feature is enabled.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 45. USB OTG full speed timings: definition of data signal rise and fall time
&URVVRYHU
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9 &56
9 66
W I W U
DLE
Table 67. USB OTG full speed electrical characteristics (1)
Driver characteristics
Symbol t r t f t rfm
V
CRS
Rise time
(2)
Fall time
(2)
Parameter
Rise/ fall time matching
Output signal crossover voltage
Conditions
C
L
C
L
= 50 pF
= 50 pF t r
/t f
Min
4
4
90
1.3
Max
20
20
110
2.0
Unit
Z
DRV
Output driver impedance
(3)
Driving high or low
28 44
1. Guaranteed by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver.
Ω ns ns
%
V
USB high speed (HS) characteristics
Unless otherwise specified, the parameters given in Table 70
for ULPI are derived from tests performed under the ambient temperature, f
HCLK and V
DD
frequency summarized in Table 69
supply voltage conditions summarized in
Table 68 , with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10, unless otherwise specified
• Capacitive load C = 30 pF, unless otherwise specified
• Measurement points are done at CMOS levels: 0.5V
DD
.
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Symbol
Table 68. USB HS DC electrical characteristics
Parameter
Input level V
DD
USB OTG HS operating voltage
1. All the voltages are measured from the local ground potential.
Min.
(1)
1.7
Max.
(1)
3.6
Unit
V
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 69. USB HS clock timing parameters (1)
Parameter t t t t
F
F
D
D
START_8BIT
STEADY
START_8BIT
STEADY
STEADY
START_DEV
START_HOST
PREP f
HCLK
value to guarantee proper operation of
USB HS interface
Frequency (first transition) 8-bit ±10%
Frequency (steady state) ±500 ppm
Duty cycle (first transition) 8-bit ±10%
Duty cycle (steady state) ±500 ppm
Time to reach the steady state frequency and duty cycle after the first transition
Clock startup time after the de-assertion of SuspendM
Peripheral
Host
PHY preparation time after the first transition of the input clock
1. Guaranteed by design.
Min
30
54
59.97
40
49.975
-
-
-
-
Typ
-
-
-
-
-
60
60
50
50
Figure 46. ULPI timing diagram
Max Unit
1.4
5.6
-
-
MHz
66 MHz
60.03
MHz
60
50.025
%
% ms ms
µs
#LOCK
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DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol t
SC t
HC t
SD t
HD
Table 70. Dynamic characteristics: USB ULPI (1)
Parameter
Control in (ULPI_DIR, ULPI_NXT) setup time
Control in (ULPI_DIR, ULPI_NXT) hold time
Data in setup time
Data in hold time
Conditions Min.
Typ.
Max.
Unit
2
0.5
1.5
2 -
-
-
-
-
-
-
t
DC
/t
DD
Data/control output delay
2.7 V < V
DD
C
L
< 3.6 V,
= 15 pF and
OSPEEDRy[1:0] = 11
2.7 V < V
DD
< 3.6 V,
C
L
= 20 pF and
OSPEEDRy[1:0] = 10
1.7 V < V
DD
< 3.6 V,
C
L
= 15 pF and
OSPEEDRy[1:0] = 11
-
-
9
12
9.5
15 ns
1. Guaranteed by characterization results.
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 71
,
SMI, RMII and MII are derived from tests performed under the ambient temperature, f
HCLK frequency summarized in
Table 17 with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF for 2.7 V < V
DD
< 3.6 V
• Capacitive load C = 20 pF for 1.71 V < V
DD
< 3.6 V
• Measurement points are done at CMOS levels: 0.5V
DD
.
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
shows the corresponding timing diagram.
Figure 47. Ethernet SMI timing diagram
W0'&
(7+B0'&
WG0',2
(7+B0',22
WVX0',2 WK0',2
(7+B0',2,
069
Symbol
Table 71. Dynamics characteristics: Ethernet MAC signals for SMI
(1)
Parameter Min Typ Max t
MDC
T d(MDIO) t su(MDIO) t h(MDIO)
MDC cycle time(2.38 MHz)
Write data valid time
Read data setup time
Read data hold time
1. Guaranteed by characterization results.
411
6
12
0
420
10
-
-
425
13
-
-
Unit ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 72 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the
corresponding timing diagram.
Figure 48. Ethernet RMII timing diagram
50,,B5()B&/.
WG7;(1
WG7;'
50,,B7;B(1
50,,B7;'>@
WVX5;'
WVX&56
50,,B5;'>@
50,,B&56B'9
WLK5;'
WLK&56
DLE
Symbol t su(RXD) t ih(RXD) t su(CRS) t ih(CRS) t d(TXEN) t d(TXD)
Table 72. Dynamics characteristics: Ethernet MAC signals for RMII
(1)
Parameter Condition Min Typ Max
Receive data setup time
Receive data hold time
Carrier sense setup time
Carrier sense hold time
Transmit enable valid delay time
Transmit data valid delay time
1.71 V < V
DD
< 3.6 V
2.7 V < V
DD
< 3.6 V
1.71 V < V
DD
< 3.6 V
2.7 V < V
DD
< 3.6 V
1.71 V < V
DD
< 3.6 V
8
8
8
8
1.5
0
1
1
10.5
10.5
11
11
-
-
-
-
12
14
12.5
14.5
-
-
-
-
1. Guaranteed by characterization results.
gives the list of Ethernet MAC signals for MII and Figure 48 shows the
corresponding timing diagram.
Unit ns
DocID024244 Rev 11
199
Electrical characteristics
0,,B5;B&/.
0,,B5;'>@
0,,B5;B'9
0,,B5;B(5
WVX5;'
WVX(5
WVX'9
STM32F437xx and STM32F439xx
Figure 49. Ethernet MII timing diagram
WLK5;'
WLK(5
WLK'9
0,,B7;B&/.
WG7;(1
WG7;'
0,,B7;B(1
0,,B7;'>@
AIB
Symbol
Table 73. Dynamics characteristics: Ethernet MAC signals for MII (1)
Parameter Condition t su(RXD) t ih(RXD) t su(DV) t ih(DV) t su(ER) t ih(ER)
Receive data setup time
Receive data hold time
Data valid setup time
Data valid hold time
Error setup time
Error hold time
1.71 V < V
DD
< 3.6 V t t d(TXEN) d(TXD)
Transmit enable valid delay time
Transmit data valid delay time
2.7 V < V
DD
< 3.6 V
1.71 V < V
DD
< 3.6 V
2.7 V < V
DD
< 3.6 V
1.71 V < V
DD
< 3.6 V
1. Guaranteed by characterization results.
Min
8
8
8
6
9
10
9
8
7.5
7.5
Typ
-
10
-
-
-
-
-
10
10
10
Max
-
14
-
-
-
-
-
16
15
17
Unit ns
CAN (controller area network) interface
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Unless otherwise specified, the parameters given in Table 74
are derived from tests performed under the ambient temperature, f
conditions summarized in Table 17
.
PCLK2 frequency and V
DDA
supply voltage
Symbol Parameter
Table 74. ADC characteristics
Conditions Min Typ Max
V
DDA
V
REF+
V
REFf
ADC
Power supply
Positive reference voltage
Negative reference voltage
ADC clock frequency
V
DDA
− V
REF+
< 1.2 V
-
V
DDA
= 1.7
to 2.4 V
V
DDA
= 2.4 to 3.6 V f
ADC
= 30 MHz,
12-bit resolution
1.7
(1)
-
0.6
0.6
-
-
0
15
30 f
TRIG
(2)
External trigger frequency
1764
V
AIN
Conversion voltage range
(3)
-
0
(V
SSA or V
REFtied to ground)
-
-
V
17
REF+
R
AIN
(2)
External input impedance
See Equation 1 for details
50
R
ADC
(2)(4)
Sampling switch resistance
C
ADC
(2)
Internal sample and hold capacitor t t t t t lat
(2) latr
(2)
S
(2)
STAB
(2)
CONV
(2)
1.5
-
-
4
6
7
Injection trigger conversion latency
Regular trigger conversion latency
Sampling time f f f
ADC
ADC
ADC
= 30 MHz
= 30 MHz
= 30 MHz
-
-
-
-
0.100
3
-
-
-
-
-
-
-
2 Power-up time
Total conversion time (including sampling time) f
ADC
= 30 MHz
12-bit resolution f
ADC
= 30 MHz
10-bit resolution f
ADC
= 30 MHz
8-bit resolution
0.50
0.43
0.37
-
-
16.40
16.34
16.27
f
ADC
= 30 MHz
6-bit resolution
0.30
16.20
9 to 492 (t
S
for sampling +n-bit resolution for successive approximation)
0.100
3 (5)
0.067
2
(5)
16
480
3
3.6
V
DDA
-
18
36
Unit
V
MHz
MHz kHz
1/f
ADC
V k Ω k Ω pF
µs
1/f
ADC
µs
1/f
ADC
µs
1/f
ADC
µs
µs
µs
µs
µs
1/f
ADC
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
Symbol Parameter
Table 74. ADC characteristics (continued)
Conditions Min Typ Max Unit f
S
(2)
Sampling rate
(f
ADC
= 30 MHz, and t
S
= 3 ADC cycles)
12-bit resolution
Single ADC
12-bit resolution
Interleave Dual ADC mode
12-bit resolution
Interleave Triple ADC mode
-
-
-
-
-
2
3.75
6
Msps
Msps
Msps
I
I
VREF+
(2)
VDDA
(2)
ADC V
REF
DC current consumption in conversion mode
ADC V
DDA
DC current consumption in conversion mode
-
300
1.6
500
1.8
1. V
DDA
2. Guaranteed by characterization results.
3. V
REF+
is internally connected to V
DDA
and V
REF-
is internally connected to V
SSA
.
4. R
ADC
maximum value is given for V
DD
=1.7 V, and minimum value for V
DD
=3.3 V.
5. For external triggers, a delay of 1/f
PCLK2
must be added to the latency specified in
.
µA mA
Equation 1: R
AIN
max formula
R
AIN
=
f
ADC
×
(
C k
–
ADC
0.5
× ln
)
( 2
N + 2
)
– R
ADC
The formula above ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.
Symbol
Table 75. ADC static accuracy at f
ADC
= 18 MHz
Parameter Test conditions Typ Max
(1)
Unit
ET Total unadjusted error
EO Offset error
EG
ED
EL
Gain error
Differential linearity error
Integral linearity error
1. Guaranteed by characterization results.
f
ADC
=18 MHz
V
DDA
= 1.7 to 3.6 V
V
REF
= 1.7 to 3.6 V
V
DDA
− V
REF
< 1.2 V
±3
±2
±1
±1
±2
±4
±3
±3
±2
±3
LSB
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol
a Table 76. ADC static accuracy at f
ADC
= 30 MHz
Parameter
ET
EO
EG
ED
EL
Total unadjusted error
Offset error
Gain error
Differential linearity error
Integral linearity error
1. Guaranteed by characterization results.
Test conditions f
ADC
= 30 MHz,
R
AIN
V
DDA
V
REF
V
DDA
< 10 k Ω ,
= 2.4 to 3.6 V,
= 1.7 to 3.6 V,
− V
REF
< 1.2 V
Typ
±2
±1.5
±1.5
±1
±1.5
Max
(1)
±5
±2.5
±3
±2
±3
Unit
LSB
Symbol
Table 77. ADC static accuracy at f
ADC
= 36 MHz
Parameter
ET Total unadjusted error
EO
EG
ED
EL
Offset error
Gain error
Differential linearity error
Integral linearity error
1. Guaranteed by characterization results.
Test conditions f
ADC
=36 MHz,
V
DDA
= 2.4 to 3.6 V,
V
REF
= 1.7 to 3.6 V
V
DDA
− V
REF
< 1.2 V
Typ
±4
±2
±3
±2
±3
Max (1)
±7
±3
±6
±3
±6
Unit
LSB
Symbol
Table 78. ADC dynamic accuracy at f
ADC
= 18 MHz - limited test conditions (1)
Parameter Test conditions Min Typ Max Unit bits ENOB
SINAD
SNR
THD
Effective number of bits
Signal-to-noise and distortion ratio
Signal-to-noise ratio
Total harmonic distortion
1. Guaranteed by characterization results.
f
ADC
=18 MHz
V
DDA
= V
REF+
= 1.7 V
Input Frequency = 20 KHz
Temperature = 25 °C
10.3
10.4
64 64.2
64 65
− 67 − 72
-
-
-
dB
Symbol
Table 79. ADC dynamic accuracy at f
ADC
= 36 MHz - limited test conditions
(1)
Parameter Test conditions Min Typ Max Unit
ENOB
SINAD
SNR
THD
Effective number of bits
Signal-to noise and distortion ratio
Signal-to noise ratio
Total harmonic distortion
1. Guaranteed by characterization results.
f
ADC
=36 MHz
V
DDA
= V
REF+
= 3.3 V
Input Frequency = 20 KHz
Temperature = 25 °C
10.6
10.8
66 67
64 68
− 70 − 72
-
-
-
bits dB
DocID024244 Rev 11
199
Electrical characteristics
Note:
STM32F437xx and STM32F439xx
ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I
INJ(PIN)
does not affect the ADC accuracy.
and Σ I
INJ(PIN)
in
Figure 50. ADC accuracy characteristics
;,3" )$%!,
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6$$!
2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. E
T
= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
AIC
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 51. Typical connection diagram using the ADC
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1. Refer to Table 74 for the values of R
AIN
, R
ADC
and C
ADC
.
2. C f pad capacitance (roughly 5 pF). A high C
ADC
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
should be reduced.
parasitic
value downgrades conversion accuracy. To remedy this,
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
General PCB design guidelines
Power supply decoupling should be performed as shown in
or
, depending on whether V
REF+
is connected to V
DDA
or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 52. Power supply and reference decoupling (V
REF+ not connected to V
DDA
)
670)
9
5()
)Q)
9
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9 66$ 9 5()
DLE
1. V
REF+
and V
REF– inputs are both available on UFBGA176. V
REF+
and V
REF–
REF+ is also available on LQFP100, LQFP144, are not available, they are internally connected to V
DDA and V
SSA
.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 53. Power supply and reference decoupling (V
REF+ connected to V
DDA
)
670)
9
5()
9
''$
)Q)
9
5()
9
66$
DLF
1. V
REF+
and V
REF– inputs are both available on UFBGA176. V
REF+
and V
REF–
REF+ is also available on LQFP100, LQFP144, are not available, they are internally connected to V
DDA and V
SSA
.
6.3.22 Temperature sensor characteristics
Table 80. Temperature sensor characteristics
Symbol Parameter Min Typ Max
T
L
(1)
V
t
START
(2)
T
S_temp
(2)
V
SENSE
linearity with temperature
Average slope
Voltage at 25 °C
Startup time
ADC sampling time when reading the temperature (1 °C accuracy)
1. Guaranteed by characterization results.
2. Guaranteed by design.
-
-
-
-
10
± 1
2.5
0.76
6
-
±
10
-
2
Unit
°C mV/°C
V
µs
µs
Symbol
Table 81. Temperature sensor calibration values
Parameter Memory address
TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, V
DDA
= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, V
DDA
= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
6.3.23 V
BAT
monitoring characteristics
Symbol
Table 82. V
BAT
monitoring characteristics
Parameter Min
T
R
Q
Er
(1)
S_vbat
(2)(2)
Resistor bridge for V
BAT
Ratio on V
BAT
measurement
Error on Q
ADC sampling time when reading the V
BAT
1 mV accuracy
1. Guaranteed by design.
2. Shortest sampling time can be determined in the application by multiple iterations.
–1
5
-
-
Typ
50
4
-
-
Max
-
-
+1
-
Unit
K Ω
%
µs
The parameters given in
Table 83 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in
Symbol Parameter
Table 83. internal reference voltage
Conditions Min Typ Max Unit
T
V
REFINT
S_vrefint
(1)
Internal reference voltage
ADC sampling time when reading the internal reference voltage
–40 °C < T
A
< +105 °C
V
RERINT_s
(2)
Internal reference voltage spread over the temperature range
V
DD
= 3V ± 10mV
T
Coeff
(2) t
START
(2)
Temperature coefficient
Startup time
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production
1.18
10
-
-
-
1.21
-
3
30
6
1.24
-
5
50
10
V
µs mV ppm/°C
µs
Symbol
V
REFIN_CAL
Table 84. Internal reference voltage calibration values
Parameter Memory address
Raw data acquired at temperature of 30 °C
VDDA
= 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol Parameter
Table 85. DAC characteristics
Conditions Min Typ Max Unit
1.7
(1)
3.6 V V
V
V
DDA
REF+
SSA
R
LOAD
(2)
Analog supply voltage
Reference supply voltage
Ground
Resistive load
-
-
-
R
LOAD connected to V
SSA DAC output buffer ON
R
LOAD connected to V
DDA
0
5
25
-
-
-
Comments
3.6
V V
REF+
V
DDA
0
-
V k Ω
-
-
R
O
(2)
Impedance output with buffer OFF
C
LOAD
(2)
Capacitive load -
-
-
-
-
15 k Ω
50 pF
When the buffer is OFF, the
Minimum resistive load between DAC_OUT and V
SS to have a 1% accuracy is
1.5 M Ω
Maximum capacitive load at
DAC_OUT pin (when the buffer is ON).
DAC_O
UT min
(2)
Lower DAC_OUT voltage with buffer ON
DAC_O
UT max
(2)
Higher DAC_OUT voltage with buffer ON
DAC_O
UT min (2)
Lower DAC_OUT voltage with buffer
OFF
DAC_O
UT max
(2)
Higher DAC_OUT voltage with buffer
OFF
I
VREF+
(4)
DAC DC V
REF
current consumption in quiescent mode
(Standby mode)
-
-
-
-
-
0.2
-
-
-
-
-
-
V
DDA
− 0.2
V
V
It gives the maximum output excursion of the DAC.
It corresponds to 12-bit input code (0x0E0) to (0xF1C) at
V
REF+
= 3.6 V and (0x1C7) to
(0xE38) at V
REF+
= 1.7 V
0.5
mV
-
170
50
V
REF+
−
1LSB
V
240
75
It gives the maximum output excursion of the DAC.
µA
With no load, worst code
(0x800) at V
REF+
= 3.6 V in terms of DC consumption on the inputs
With no load, worst code
(0xF1C) at V
REF+
= 3.6 V in terms of DC consumption on the inputs
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
Symbol Parameter
I
DDA
(4)
DAC DC VDDA current consumption in quiescent mode
(3)
Table 85. DAC characteristics (continued)
Conditions
-
-
Min Typ Max Unit
-
-
Comments
280 380 µA
With no load, middle code
(0x800) on the inputs
475 625 µA
With no load, worst code
(0xF1C) at V
REF+
= 3.6 V in terms of DC consumption on the inputs
DNL
(4)
Differential non linearity Difference between two consecutive code-
1LSB)
INL
(4)
Integral non linearity
(difference between measured value at
Code i and the value at Code i on a line drawn between Code
0 and last Code 1023)
-
-
-
-
-
-
-
-
-
-
-
±0.5 LSB
Given for the DAC in 10-bit configuration.
±2 LSB
Given for the DAC in 12-bit configuration.
±1 LSB
Given for the DAC in 10-bit configuration.
±4 LSB
Given for the DAC in 12-bit configuration.
Offset
(4)
Offset error
(difference between measured value at
Code (0x800) and the ideal value = V
REF+
/2)
-
-
-
-
-
-
-
±10 mV
Given for the DAC in 12-bit configuration
-
-
-
±3 LSB
Given for the DAC in 10-bit at
V
REF+
= 3.6 V
±12 LSB
Given for the DAC in 12-bit at
V
REF+
= 3.6 V
±0.5
%
Given for the DAC in 12-bit configuration
Gain error
(4)
Gain error t
G
Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when
DAC_OUT reaches final value ±4LSB
THD
(4)
Total Harmonic
Distortion
Buffer ON
Update rate
(2)
Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB)
-
-
-
-
-
3
-
-
6
-
1
µs
C
LOAD
R
LOAD
≤
≥ 5 k Ω dB
C
LOAD
R
LOAD
≤
≥ 5 k Ω
MS/ s
C
LOAD
R
LOAD
≤
≥ 5 k Ω
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol Parameter
Table 85. DAC characteristics (continued)
Conditions Min Typ Max Unit Comments t
4)
(
Wakeup time from off state (Setting the ENx bit in the DAC Control register)
PSRR+
(2)
Power supply rejection ratio (to V
DDA
) (static
DC measurement)
-
-
-
6.5
10
–67 –40
µs
C
LOAD
≤
LOAD
≥ 5 k Ω input code between lowest and highest possible ones.
dB No
LOAD
, C
LOAD
= 50 pF
1. V
DDA
2. Guaranteed by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.
4. Guaranteed by characterization.
Figure 54. 12-bit buffered /non-buffered DAC
%XIIHUHGQRQEXIIHUHG'$&
%XIIHU
5 /2$'
ELW
GLJLWDOWR
DQDORJ
FRQYHUWHU
'$&[B287
& /2$'
DLD
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
Unless otherwise specified, the parameters given in Table 86
for the FMC interface are derived from tests performed under the ambient temperature, f
HCLK and V
DD frequency
supply voltage conditions summarized in Table 17
, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10 except at V
DD
OSPEEDRy[1:0] = 11
range 1.7 to 2.1V where
• Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings
through Figure 58 represent asynchronous waveforms and
Table 93 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• For SDRAM memories, V
DD
FMC_SDCLK = 90 MHz
ranges from 2.7 to 3.6 V and maximum frequency
• For Mobile LPSDR SDRAM memories, V
DD frequency FMC_SDCLK = 84 MHz
ranges from 1.7 to 1.95 V and maximum
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
T
W.%
&-#?.%
T
V./%?.%
T
W./%
T
H.%?./%
&-#?./%
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V!?.%
T
V",?.%
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T
H!?./%
T
H",?./%
&-#?.",;=
T
H$ATA?.%
T
H$ATA?./%
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T
SU$ATA?.%
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-36
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Symbol
Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
(1)(2)
Parameter Min Max t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t v(BL_NE) t h(BL_NOE) t su(Data_NE) t su(Data_NOE)
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
Address hold time after FMC_NOE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NOE high
Data to FMC_NEx high setup time
Data to FMC_NOEx high setup time
Unit
2T
HCLK
− 0.5
2 T
HCLK
+0.5
ns
0 1 ns
2T
HCLK
0
-
2T
HCLK
-
2
+ 0.5
ns ns ns
0
-
0
T
HCLK
+ 2.5
T
HCLK
+2
-
-
-
2
ns ns ns ns ns
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 86. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)(2) (continued)
Parameter Min Max t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)
Data hold time after FMC_NOE high
Data hold time after FMC_NEx high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
-
-
0
0 -
-
0
T
HCLK
+1
Unit ns ns ns ns
Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
NWAIT timings (1)(2)
Symbol Parameter Min Max Unit t w(NE)
FMC_NE low time 7T
HCLK
+0.5
7T
HCLK
+1 t t t w(NOE) su(NWAIT_NE) h(NE_NWAIT)
FMC_NWE low time
FMC_NEx hold time after FMC_NWAIT invalid
5T
HCLK
− 1.5
5T
HCLK
+2
FMC_NWAIT valid before FMC_NEx high 5T
HCLK
4T
+1.5
HCLK
+1 -
-
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
TW.%
&-#?.%X
&-#?./%
&-#?.7%
T H.%?.7%
&-#?!;=
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TV!?.%
TV",?.%
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-36
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)(2)
Symbol Parameter
t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
Address hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
FMC_BL hold time after FMC_NWE high
Data to FMC_NEx low to Data valid
Data hold time after FMC_NWE high
FMC_NEx low to FMC_NADV low
FMC_NADV low time
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
Min Max
3T
HCLK
3T
HCLK
+1
T
HCLK
− 0.5
T
HCLK
+ 0.5
T
HCLK
T
HCLK
+1.5
T
HCLK
+ 0.5
-
0
T
HCLK
+0.5
-
T
HCLK
+0.5
T
1.5
-
HCLK
-
+ 2
T
HCLK
+0.5
-
-
0.5
T
HCLK
+ 0.5
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -
NWAIT timings (1)(2)
Symbol Parameter Min Max Unit t w(NE)
FMC_NE low time t t t w(NWE) su(NWAIT_NE) h(NE_NWAIT)
FMC_NWE low time
FMC_NWAIT valid before FMC_NEx high
FMC_NEx hold time after FMC_NWAIT invalid
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
8T
HCLK
+1
6T
HCLK
− 1
6T
HCLK
+1.5
4T
HCLK
+1
8T
HCLK
+2
6T
HCLK
+2
ns ns ns ns
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms
TW.%
&-#? .%
TV./%?.% T H.%?./%
&-#?./%
TW./%
&-#?.7%
TV!?.% TH!?./%
&-#? !;=
!DDRESS
TV",?.% TH",?./%
&-#? .",;= .",
TH$ATA?.%
&-#? !$;=
T V.!$6?.%
T V!?.%
!DDRESS
TH!$?.!$6
TW.!$6
TSU$ATA?.%
TSU$ATA?./%
$ATA
TH$ATA?./%
&-#?.!$6
&-#?.7!)4
TH.%?.7!)4
TSU.7!)4?.%
-36
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 90. Asynchronous multiplexed PSRAM/NOR read timings (1)(2)
Symbol Parameter Min Max t w(NE) t v(NOE_NE) t tw(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV)
FMC_NE low time
FMC_NEx low to FMC_NOE low
FMC_NOE low time
FMC_NOE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low t h(AD_NADV)
FMC_NADV low time
FMC_AD(address) valid hold time after
FMC_NADV high) t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)
Address hold time after FMC_NOE high
FMC_BL time after FMC_NOE high
FMC_NEx low to FMC_BL valid
Data to FMC_NEx high setup time
Data to FMC_NOE high setup time
Data hold time after FMC_NEx high
Data hold time after FMC_NOE high
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
3T
HCLK
− 1 3T
HCLK
+0.5
2T
HCLK
− 0.5
2T
HCLK
T
HCLK
− 1 T
HCLK
+1
1 -
2
0 2
T
HCLK
− 0.5
T
HCLK
+0.5
0
T
HCLK
− 0.5
0
-
T
HCLK
+1.5
T
HCLK
+1
0
0
-
2
-
-
-
-
-
ns ns ns ns ns ns ns ns
Unit ns ns ns ns ns ns ns
Table 91. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings (1)(2)
Symbol Parameter Min Max Unit t w(NE)
FMC_NE low time 8T
HCLK
+0.5
8T
HCLK
+2 t t t w(NOE) su(NWAIT_NE) h(NE_NWAIT)
FMC_NWE low time 5T
HCLK
− 1 5T
HCLK
+1.5
FMC_NWAIT valid before FMC_NEx high 5T
HCLK
FMC_NEx hold time after FMC_NWAIT invalid
4T
+1.5
HCLK
+1
-
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
ns ns ns ns
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms
TW.%
&-#? .%X
&-#?./%
TV.7%?.% TW.7% T H.%?.7%
&-#?.7%
&-#? !;=
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TV",?.%
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TH!?.7%
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-36
Symbol
Table 92. Asynchronous multiplexed PSRAM/NOR write timings (1)(2)
Parameter t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV) t h(AD_NADV) t h(A_NWE) t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)
FMC_NE low time
FMC_NEx low to FMC_NWE low
FMC_NWE low time
FMC_NWE high to FMC_NE high hold time
FMC_NEx low to FMC_A valid
FMC_NEx low to FMC_NADV low
FMC_NADV low time
FMC_AD(adress) valid hold time after FMC_NADV high)
Address hold time after FMC_NWE high
FMC_BL hold time after FMC_NWE high
FMC_NEx low to FMC_BL valid
FMC_NADV high to Data valid
Data hold time after FMC_NWE high
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
Min Max Unit
4T
HCLK
4T
HCLK
+0.5
ns
T
HCLK
− 1 T
HCLK
+0.5
ns
2T
T
HCLK
HCLK
2T
HCLK
+0.5
ns
ns
0 ns
T
HCLK
− 0.5
T
HCLK
+ 0.5
ns
T
HCLK
− 2 ns
T
0.5
HCLK
T
HCLK
− 2
1
-
ns ns ns
2 ns
-
T
HCLK
+0.5
T
HCLK
+1.5
ns
ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings (1)(2)
Symbol Parameter Min Max Unit t w(NE)
FMC_NE low time t t t w(NWE) su(NWAIT_NE) h(NE_NWAIT)
FMC_NWE low time
FMC_NWAIT valid before FMC_NEx high
FMC_NEx hold time after FMC_NWAIT invalid
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
9T
HCLK
7T
HCLK
6T
HCLK
+1.5
4T
HCLK
–1
9T
HCLK
+0.5
ns
7T
HCLK
-
-
+2 ns ns ns
Synchronous waveforms and timings
represent synchronous waveforms and Table 94
through
Table 97 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable;
• MemoryType = FMC_MemoryType_CRAM;
• WriteBurst = FMC_WriteBurst_Enable;
• CLKDivision = 1; (0 is not supported, see the STM32F4xx reference manual : RM0090)
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, the T
HCLK
FMC_CLK = 90 MHz).
is the HCLK clock period (with maximum
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
Figure 59. Synchronous multiplexed NOR/PSRAM read timings
TW#,+ TW#,+ "53452.
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-36
Table 94. Synchronous multiplexed NOR/PSRAM read timings (1)(2)
Symbol t w(CLK) t d(CLKL-NExL) t d(CLKH_NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV)
Parameter
FMC_CLK period
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
Min Max Unit
2T
HCLK
− 1
-
T
HCLK
-
0
-
0
-
T
HCLK
− 0.5
-
0
-
0
-
0
-
0 ns ns
ns
T
HCLK
+0.5
ns
ns
0.5
ns
ns ns ns ns ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 94. Synchronous multiplexed NOR/PSRAM read timings (1)(2) (continued)
Symbol Parameter Min Max Unit t su(ADV-CLKH)
FMC_A/D[15:0] valid data before FMC_CLK high t h(CLKH-ADV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)
FMC_A/D[15:0] valid data after FMC_CLK high
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
5
0
4
0
-
-
-
ns ns ns ns
&-#?#,+
Figure 60. Synchronous multiplexed PSRAM write timings
TW#,+ TW#,+ "53452.
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-36
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 95. Synchronous multiplexed PSRAM write timings (1)(2)
Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t
(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)
FMC_CLK period, VDD range= 2.7 to 3.6 V
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
FMC_CLK low to FMC_AD[15:0] valid
FMC_CLK low to FMC_AD[15:0] invalid
FMC_A/D[15:0] valid data after FMC_CLK low
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
2T
HCLK
− 1
-
T
HCLK
-
0
-
T
HCLK
-
T
HCLK
− 0.5
-
0
-
0
T
HCLK
− 0.5
4
0
3
-
-
-
-
-
3
-
-
0
-
0
-
1.5
-
0
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings
TW#,+ TW#,+
&-#?#,+
TD#,+,.%X,
&-#?.%X
TD#,+,.!$6,
$ATALATENCY
TD#,+,.!$6(
TD#,+(.%X(
&-#?.!$6
TD#,+,!6 TD#,+(!)6
&-#?!;=
TD#,+,./%, TD#,+(./%(
&-#?./%
&-#?$;=
TSU$6#,+(
TSU.7!)46#,+(
$
TH#,+($6
TSU$6#,+(
$
TH#,+(.7!)46
TH#,+($6
&-#?.7!)4
7!)4#&'B
7!)40/,B
&-#?.7!)4
7!)4#&'B
7!)40/,B
TSU.7!)46#,+( T H#,+(.7!)46
TSU.7!)46#,+( TH#,+(.7!)46
-36
Table 96. Synchronous non-multiplexed NOR/PSRAM read timings
(1)(2)
Symbol Parameter Min Max t w(CLK) t
(CLKL-NExL) t d(CLKH-
NExH) t d(CLKL-
NADVL) t d(CLKL-
NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-
NOEH) t su(DV-CLKH)
FMC_CLK period
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
FMC_CLK low to FMC_Ax valid (x=16…25)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NOE low
FMC_CLK high to FMC_NOE high
FMC_D[15:0] valid data before FMC_CLK high
2T
HCLK
− 1
-
T
HCLK
-
0
-
T
HCLK
− 0.5
-
T
HCLK
− 0.5
5
-
0.5
0
-
0
-
T
HCLK
+2
-
-
-
Unit ns ns ns ns ns ns ns ns ns ns
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Electrical characteristics STM32F437xx and STM32F439xx
Table 96. Synchronous non-multiplexed NOR/PSRAM read timings (1)(2) (continued)
Symbol Parameter Min Max Unit t h(CLKH-DV) t
(NWAIT-CLKH) t h(CLKH-
NWAIT)
FMC_D[15:0] valid data after FMC_CLK high
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
0
4
0
ns
Figure 62. Synchronous non-multiplexed PSRAM write timings
TW#,+
&-#?#,+
TD#,+,.%X,
&-#?.%X
TW#,+
$ATALATENCY
TD#,+(.%X(
TD#,+,.!$6,
&-#?.!$6
TD#,+,.!$6(
TD#,+,!6
TD#,+(!)6
&-#?!;=
TD#,+,.7%, TD#,+(.7%(
&-#?.7%
&-#?$;=
TD#,+,$ATA
$
TD#,+,$ATA
$
&-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
&-#?.",
TD#,+(.",(
TH#,+(.7!)46
Table 97. Synchronous non-multiplexed PSRAM write timings
(1)(2)
Symbol Parameter Min Max t
(CLK) t d(CLKL-NExL) t
(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV)
FMC_CLK period
FMC_CLK low to FMC_NEx low (x=0..2)
FMC_CLK high to FMC_NEx high (x= 0…2)
FMC_CLK low to FMC_NADV low
FMC_CLK low to FMC_NADV high
FMC_CLK low to FMC_Ax valid (x=16…25)
2T
HCLK
− 1
-
T
HCLK
-
0
-
0
-
0
-
0.5
-
-36
Unit ns ns ns ns ns ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 97. Synchronous non-multiplexed PSRAM write timings (1)(2) (continued)
Symbol Parameter Min Max Unit t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-Data) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)
FMC_CLK high to FMC_Ax invalid (x=16…25)
FMC_CLK low to FMC_NWE low
FMC_CLK high to FMC_NWE high
FMC_D[15:0] valid data after FMC_CLK low
FMC_CLK low to FMC_NBL low
FMC_CLK high to FMC_NBL high
FMC_NWAIT valid before FMC_CLK high
FMC_NWAIT valid after FMC_CLK high
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
0
-
T
HCLK
− 0.5
-
0
T
HCLK
− 0.5
4
0
-
0
-
2.5
-
ns ns ns ns ns ns
PC Card/CompactFlash controller waveforms and timings
through Figure 68 represent synchronous waveforms, and Table 98
and
provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration:
• COM.FMC_SetupTime = 0x04;
• COM.FMC_WaitSetupTime = 0x07;
• COM.FMC_HoldSetupTime = 0x04;
• COM.FMC_HiZSetupTime = 0x00;
• ATT.FMC_SetupTime = 0x04;
• ATT.FMC_WaitSetupTime = 0x07;
• ATT.FMC_HoldSetupTime = 0x04;
• ATT.FMC_HiZSetupTime = 0x00;
• IO.FMC_SetupTime = 0x04;
• IO.FMC_WaitSetupTime = 0x07;
• IO.FMC_HoldSetupTime = 0x04;
• IO.FMC_HiZSetupTime = 0x00;
• TCLRSetupTime = 0;
• TARSetupTime = 0.
In all timing tables, the T
HCLK
is the HCLK clock period.
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Electrical characteristics STM32F437xx and STM32F439xx
Figure 63. PC Card/CompactFlash controller waveforms for common memory read access
&-#?.#%?
&-#?.#%?
TV.#%X! TH.#%X!)
&-#?!;=
TD.2%'.#%X
TD.)/2$.#%X
TH.#%X.2%'
TH.#%X.)/2$
TH.#%X.)/72
&-#?.2%'
&-#?.)/72
&-#?.)/2$
&-#?.7%
TD.#%?./%
&-#?./%
TW./%
TSU$./% TH./%$
&-#?$;=
-36
1. FMC_NCE4_2 remains high (inactive during 8-bit access.
Figure 64. PC Card/CompactFlash controller waveforms for common memory write access
&-#?.#%?
&-#?.#%?
(IGH
TV.#%?!
&-#?!;=
&-#?.2%'
&-#?.)/72
&-#?.)/2$
TD.#%?.7%
&-#?.7%
TD.2%'.#%?
TD.)/2$.#%?
TW.7%
&-#?./%
-%-X():
TD$.7%
TV.7%$
TH.#%?!)
TH.#%?.2%'
TH.#%?.)/2$
TH.#%?.)/72
TD.7%.#%?
TH.7%$
&-#?$;=
-36
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access
&-#?.#%?
TV.#%?! TH.#%?!)
&-#?.#%?
(IGH
&-#?!;=
&-#?.)/72
&-#?.)/2$
&-#?.2%'
&-#?.7%
TD.#%?./%
&-#?./%
TD.2%'.#%?
TW./%
TSU$./%
&-#?$;=
TH.#%?.2%'
TH./%$
TD./%.#%?
-36
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
Figure 66. PC Card/CompactFlash controller waveforms for attribute memory
write access
&-#?.#%?
&-#?.#%?
(IGH
TV.#%?! TH.#%?!)
&-#?!;=
&-#?.)/72
&-#?.)/2$
TD.2%'.#%? TH.#%?.2%'
&-#?.2%'
TD.#%?.7%
&-#?.7%
TW.7%
TD.7%.#%?
&-#?./%
TV.7%$
&-#?$;=
-36
1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).
Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access
&-#?.#%?
&-#?.#%?
TV.#%X! TH.#%?!)
&-#?!;=
&-#?.2%'
&-#?.7%
&-#?./%
&-#?.)/72
TD.)/2$.#%?
&-#?.)/2$
TW.)/2$
TSU$.)/2$ TD.)/2$$
&-#?$;=
-36
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access
&-#?.#%?
&-#?.#%?
TV.#%X! TH.#%?!)
&-#?!;=
&-#?.2%'
&-#?.7%
&-#?./%
&-#?.)/2$
T D.#%?.)/72
&-#?.)/72
TW.)/72
!44X():
TV.)/72$
TH.)/72$
&-#?$;=
-36
Table 98. Switching characteristics for PC Card/CF read and write cycles
in attribute/common space
(1)(2)
Symbol t v(NCEx-A) t h(NCEx_AI) t d(NREG-NCEx) t h(NCEx-NREG) t d(NCEx-NWE) t w(NWE) t d(NWE_NCEx) t
V(NWE-D) t h(NWE-D) t d(D-NWE)
FMC_Ncex low to FMC_Ay valid
FMC_NCEx high to FMC_Ax invalid
FMC_NCEx low to FMC_NREG valid
FMC_NCEx high to FMC_NREG invalid
FMC_NCEx low to FMC_NWE low
FMC_NWE low width
FMC_NWE high to FMC_NCEx high
FMC_NWE low to FMC_D[15:0] valid
FMC_NWE high to FMC_D[15:0] invalid
FMC_D[15:0] valid before FMC_NWE high t d(NCEx-NOE) t w(NOE) t d(NOE_NCEx) t su (D-NOE) t h(NOE-D)
FMC_NCEx low to FMC_NOE low
FMC_NOE low width
FMC_NOE high to FMC_NCEx high
FMC_D[15:0] valid data before FMC_NOE high
FMC_NOE high to FMC_D[15:0] invalid
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
0 ns
0 ns
1 ns
T
HCLK
− 2 ns
5T
HCLK ns
8T
HCLK
− 0.5
8T
HCLK
+0.5
ns
5T
HCLK
+1 ns
0 ns -
9T
HCLK
− 0.5
13T
HCLK
− 3
ns ns
-
T
HCLK
5T
HCLK ns
8 T
HCLK
− 0.5
8 T
HCLK
+0.5
ns
5T
HCLK
− 1 ns
ns
0 ns
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Electrical characteristics STM32F437xx and STM32F439xx
Table 99. Switching characteristics for PC Card/CF read and write cycles
in I/O space (1)(2)
Symbol tw(NIOWR) tv(NIOWR-D)
FMC_NIOWR low width
FMC_NIOWR low to FMC_D[15:0] valid th(NIOWR-D) FMC_NIOWR high to FMC_D[15:0] invalid td(NCE4_1-NIOWR) FMC_NCE4_1 low to FMC_NIOWR valid th(NCEx-NIOWR) FMC_NCEx high to FMC_NIOWR invalid td(NIORD-NCEx) FMC_NCEx low to FMC_NIORD valid th(NCEx-NIORD) FMC_NCEx high to FMC_NIORD) valid tw(NIORD) FMC_NIORD low width tsu(D-NIORD) td(NIORD-D)
FMC_D[15:0] valid before FMC_NIORD high
FMC_D[15:0] valid after FMC_NIORD high
1. C
L
= 30 pF.
2. Guaranteed by characterization results.
8T
HCLK
− 0.5
-
9T
HCLK
− 2
-
5T
HCLK
-
6T
HCLK
+2
8T
HCLK
− 0.5
T
HCLK
0
-
0
-
5T
HCLK
-
5T
HCLK
-
8T
HCLK
+0.5
-
ns ns ns ns ns ns ns ns ns ns
NAND controller waveforms and timings
through Figure 72 represent synchronous waveforms, and Table 100 and
provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration:
• COM.FMC_SetupTime = 0x01;
• COM.FMC_WaitSetupTime = 0x03;
• COM.FMC_HoldSetupTime = 0x02;
• COM.FMC_HiZSetupTime = 0x01;
• ATT.FMC_SetupTime = 0x01;
• ATT.FMC_WaitSetupTime = 0x03;
• ATT.FMC_HoldSetupTime = 0x02;
• ATT.FMC_HiZSetupTime = 0x01;
• Bank = FMC_Bank_NAND;
• MemoryDataWidth = FMC_MemoryDataWidth_16b;
• ECC = FMC_ECC_Enable;
• ECCPageSize = FMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0.
In all timing tables, the T
HCLK
is the HCLK clock period.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 69. NAND controller waveforms for read access
&-#?.#%X
!,%&-#?!
#,%&-#?!
&-#?.7%
TD!,%./%
TH./%!,%
&-#?./%.2%
TSU$./% TH./%$
&-#?$;=
-36
Figure 70. NAND controller waveforms for write access
&-#?.#%X
!,%&-#?!
#,%&-#?!
&-#?.7%
TD!,%.7% TH.7%!,%
&-#?./%.2%
&-#?$;=
TV.7%$ TH.7%$
-36
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Electrical characteristics STM32F437xx and STM32F439xx
Figure 71. NAND controller waveforms for common memory read access
&-#?.#%X
!,%&-#?!
#,%&-#?!
TD!,%./% TH./%!,%
&-#?.7%
TW./%
&-#?./%
TSU$./% TH./%$
&-#?$;=
-36
Figure 72. NAND controller waveforms for common memory write access
&-#?.#%X
!,%&-#?!
#,%&-#?!
TD!,%./%
&-#?.7%
TW.7% TH./%!,%
&-#?. /%
TD$.7%
TV.7%$ TH.7%$
&-#?$;=
-36
Symbol
Table 100. Switching characteristics for NAND Flash read cycles (1)
Parameter t w(N0E) t su(D-NOE) t h(NOE-D) t d(ALE-NOE) t h(NOE-ALE)
1. C
L
= 30 pF.
FMC_NOE low width
FMC_D[15-0] valid data before FMC_NOE high
FMC_D[15-0] valid data after FMC_NOE high
FMC_ALE valid before FMC_NOE low
FMC_NWE high to FMC_ALE invalid
Min Max Unit
4T
HCLK
− 0.5 4T
HCLK
+0.5
ns
9 ns
0
-
3T
HCLK
− 2
ns
3T
HCLK
− 0.5
ns
ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Table 101. Switching characteristics for NAND Flash write cycles (1)
Symbol t w(NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t d(ALE-NWE) t h(NWE-ALE)
1. C
L
= 30 pF.
Parameter
FMC_NWE low width
FMC_NWE low to FMC_D[15-0] valid
FMC_NWE high to FMC_D[15-0] invalid
FMC_D[15-0] valid before FMC_NWE high
FMC_ALE valid before FMC_NWE low
FMC_NWE high to FMC_ALE invalid
Min
4T
HCLK
0
3T
HCLK
− 1
5T
HCLK
− 3
-
3T
HCLK
− 1
Max Unit
4T
HCLK
+1 ns
ns
ns
ns
3T
HCLK
− 0.5
ns
ns
SDRAM waveforms and timings
Figure 73. SDRAM read access waveforms (CL = 1)
&-#?3$#,+
TD3$#,+,?!DD2
&-#?!
>@ 2OWN
TD3$#,+,?!DD#
TH3$#,+,?!DD2
#OL #OL #OLI
TH3$#,+,?!DD#
#OLN
TD3$#,+,?3.$% TH3$#,+,?3.$%
&-#?3$.%;=
TD3$#,+,?.2!3
&-#?3$.2!3
TH3$#,+,?.2!3
TD3$#,+,?.#!3 TH3$#,+,?.#!3
&-#?3$.#!3
&-#?3$.7%
&-#?$;=
TSU3$#,+(?$ATA
$ATA
TH3$#,+(?$ATA
$ATA $ATAI $ATAN
-36
DocID024244 Rev 11
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Electrical characteristics STM32F437xx and STM32F439xx
Symbol
Table 102. SDRAM read timings (1)(2)
Parameter Min t w(SDCLK) t su(SDCLKH _Data)
FMC_SDCLK period
Data input setup time
2T
HCLK t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL- SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK .
2. Guaranteed by characterization results.
2
0
-
-
0
0
-
-
0
− 0.5
Symbol
Table 103. LPSDR SDRAM read timings (1)(2)
Parameter Min t
W(SDCLK) t su(SDCLKH_Data) t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL_SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)
FMC_SDCLK period
Data input setup time
Data input hold time
Address valid time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
1. CL = 10 pF .
2. Guaranteed by characterization results.
2T
HCLK
− 0.5
2.5
0
1
-
-
-
1
-
1
Max
2T
HCLK
+0.5
-
-
-
1
1
1
-
1
-
Max
2T
HCLK
+0.5
-
-
1.5
0.5
-
0.5
-
0.5
-
Unit ns
Unit ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 74. SDRAM write access waveforms
&-#?3$#,+
TD3$#,+,?!DD2
&-#?!
>@ 2OWN
TD3$#,+,?!DD#
TH3$#,+,?!DD2
#OL #OL #OLI
TH3$#,+,?!DD#
#OLN
TD3$#,+,?3.$% TH3$#,+,?3.$%
&-#?3$.%;=
TD3$#,+,?.2!3
&-#?3$.2!3
TH3$#,+,?.2!3
TD3$#,+,?.#!3 TH3$#,+,?.#!3
&-#?3$.#!3
TD3$#,+,?.7% TH3$#,+,?.7%
&-#?3$.7%
TD3$#,+,?$ATA
&-#?$;=
TD3$#,+,?.",
&-#?.",;=
$ATA $ATA $ATAI
TH3$#,+,?$ATA
$ATAN
-36
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Electrical characteristics STM32F437xx and STM32F439xx
Table 104. SDRAM write timings (1)(2) t w(SDCLK) t d(SDCLKL _Data
) t h(SDCLKL _Data) t d(SDCLKL_Add) t d(SDCLKL_SDNWE) t h(SDCLKL_SDNWE) t d(SDCLKL_ SDNE) t h(SDCLKL-_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t d(SDCLKL_SDNCAS) t d(SDCLKL_NBL) t h(SDCLKL_NBL)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time
NBL valid time
NBLoutput time
2T
HCLK
1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK .
2. Guaranteed by characterization results.
0
-
-
0
0
-
0
0
-
-
-
-
0
− 0.5
Table 105. LPSDR SDRAM write timings (1)(2)
2T
HCLK
+0.5
3.5
-
1.5
1
-
0.5
-
2
-
0.5
-
0.5
ns t w(SDCLK) t d(SDCLKL _Data
) t h(SDCLKL _Data) t d(SDCLKL_Add) t d(SDCLKL-SDNWE) t h(SDCLKL-SDNWE) t d(SDCLKL- SDNE) t h(SDCLKL- SDNE) t d(SDCLKL-SDNRAS) t h(SDCLKL-SDNRAS) t d(SDCLKL-SDNCAS) t d(SDCLKL-SDNCAS)
FMC_SDCLK period
Data output valid time
Data output hold time
Address valid time
SDNWE valid time
SDNWE hold time
Chip select valid time
Chip select hold time
SDNRAS valid time
SDNRAS hold time
SDNCAS valid time
SDNCAS hold time t d(SDCLKL_NBL) t h(SDCLKL-NBL)
NBL valid time
NBL output time
1. CL = 10 pF .
2. Guaranteed by characterization results.
2T
HCLK
− 0.5
-
2
-
-
1
-
1
-
1.5
-
1.5
-
1.5
2T
HCLK
+0.5
5
-
2.8
2
-
1.5
-
1.5
-
1.5
-
1.5
ns
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Unless otherwise specified, the parameters given in
Table 106
for DCMI are derived from tests performed under the ambient temperature, f
HCLK
frequency and V
DD
supply voltage summarized in
Table 17
, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
Symbol
Table 106. DCMI characteristics
Parameter
Frequency ratio DCMI_PIXCLK/f
HCLK
DCMI_PIXCLK Pixel clock input
D
Pixel t su(DATA) t h(DATA) t su(HSYNC) t su(VSYNC) t h(HSYNC) t h(VSYNC)
Pixel clock input duty cycle
Data input setup time
Data input hold time
DCMI_HSYNC/DCMI_VSYNC input setup time
DCMI_HSYNC/DCMI_VSYNC input hold time
Min
30
2
-
-
2.5
0.5
1
Max
0.4
54
70
-
-
-
-
Unit
MHz
% ns
Figure 75. DCMI timing diagram
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DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
Symbol f
CLK
D
CLK t w(CLKH) t w(CLKL) t v(DATA) t h(DATA) t v(HSYNC) t v(VSYNC) t v(DE) t h(HSYNC) t h(VSYNC)
Unless otherwise specified, the parameters given in
Table 107
for LCD-TFT are derived from tests
performed under the ambient temperature, f
HCLK
frequency and VDD supply voltage summarized in
Table 17
, with the following configuration:
• LCD_CLK polarity: high
• LCD_DE polarity : low
• LCD_VSYNC and LCD_HSYNC polarity: high
•
Pixel formats: 24 bits
Table 107. LTDC characteristics
Parameter
LTDC clock output frequency
LTDC clock output duty cycle
Clock High time, low time
Min
-
45
Max
83
55 tw(CLK)/2 − 0.5 tw(CLK)/2+0.5
Data output valid time 3.5
Unit
MHz
%
Data output hold time
HSYNC/VSYNC/DE output valid time
HSYNC/VSYNC/DE output hold time
1.5
-
2 -
-
2.5
ns th(DE)
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Figure 76. LCD-TFT horizontal timing diagram
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Figure 77. LCD-TFT vertical timing diagram
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069
DocID024244 Rev 11
199
Electrical characteristics STM32F437xx and STM32F439xx
6.3.29 SD/SDIO MMC card host interface (SDIO) characteristics
Unless otherwise specified, the parameters given in Table 108 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, f
PCLK2 frequency and V
DD
supply voltage conditions summarized in Table 17 , with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V
DD
Refer to Section 6.3.17: I/O port characteristics for more details on the input/output
characteristics.
Figure 78. SDIO high-speed mode
Figure 79. SD default mode
DocID024244 Rev 11
STM32F437xx and STM32F439xx Electrical characteristics
Symbol
Table 108. Dynamic characteristics: SD / MMC characteristics (1)(2)
Parameter Conditions f
PP
t
W(CKL) t
W(CKH)
Clock frequency in data transfer mode
SDIO_CK/fPCLK2 frequency ratio
Clock low time
Clock high time fpp =48 MHz fpp =48 MHz
CMD, D inputs (referenced to CK) in MMC and SD HS mode t
ISU t
IH
Input setup time HS
Input hold time HS fpp =48 MHz fpp =48 MHz
CMD, D outputs (referenced to CK) in MMC and SD HS mode t
OV t
OH
Output valid time HS
Output hold time HS fpp =48 MHz fpp =48 MHz
CMD, D inputs (referenced to CK) in SD default mode
Min
0
-
8.5
8.3
3.5
0
-
3
Typ
-
9
10
-
-
4.5
-
Max
-
-
7
-
-
-
48
8/3 tISUD Input setup time SD fpp =24 MHz tIHD Input hold time SD fpp =24 MHz
CMD, D outputs (referenced to CK) in SD default mode
1.5
0.5
-
-
-
tOVD Output valid default time SD tOHD Output hold default time SD
1. Guaranteed by characterization results.
2. V
DD
= 2.7 to 3.6 V.
fpp =24 MHz fpp =24 MHz
-
3.5
4.5
-
6.5
-
Unit
MHz
ns ns ns ns ns
Symbol
-
Parameter
Table 109. RTC characteristics
Conditions f
PCLK1
/RTCCLK frequency ratio
Any read/write operation from/to an RTC register
Min
4
Max
-
DocID024244 Rev 11
199
Package information STM32F437xx and STM32F439xx
7.1
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK ® is an ST trademark.
LQFP100 package information
Figure 80. LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline
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#
C
MM
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$
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)$%.4)&)#!4)/.
1. Drawing is not to scale.
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DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
Table 110. LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max e
L
L1
D3
E
E1
E3 k ccc
D
D1 b c
A
A1
A2
-
0.050
1.350
0.170
0.090
15.800
13.800
-
15.800
13.800
-
-
0.450
-
0.0°
-
3.5°
-
-
-
1.400
0.220
-
16.000
14.000
12.000
16.000
14.000
12.000
0.500
0.600
1.000
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
16.200
14.200
-
-
0.750
-
7.0°
0.080
1.600
0.150
1.450
0.270
0.200
16.200
14.200
-
0.6220
0.5433
-
-
0.0177
-
0.0°
-
-
0.0020
0.0531
0.0067
0.0035
0.6220
0.5433
0.4724
0.6299
0.5512
0.4724
0.0197
0.0236
0.0394
3.5°
-
-
-
0.0551
0.0087
-
0.6299
0.5512
-
0.6378
0.5591
-
-
0.0295
-
7.0°
0.0031
0.0630
0.0059
0.0571
0.0106
0.0079
0.6378
0.5591
DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Figure 81. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint
1. Dimensions are expressed in millimeters.
AIC
DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
Device marking for LQFP100
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below.
Figure 82. LQFP100 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Figure 83. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package outline
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1. Drawing is not to scale.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
Table 111. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
package mechanical data inches
(1)
Symbol millimeters
Min Typ Max Min Typ Max
F
G aaa e e1 e2
A
A1
A2
A3 (2) b
(3)
D
E bbb ccc ddd eee
0.525
0.155
-
-
0.220
4.486
5.512
-
-
-
-
-
-
-
-
-
-
0.555
0.175
0.380
0.025
0.250
4.521
5.547
0.400
4.000
4.800
0.2605
0.3735
-
-
-
-
-
0.585
0.195
-
-
0.280
4.556
5.582
-
-
-
-
-
0.100
0.100
0.100
0.050
0.050
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
-
-
-
-
-
-
-
0.0207
-
-
-
0.0087
0.1766
0.2170
-
-
-
0.0103
0.0147
-
-
-
-
-
0.0219
0.0069
0.0150
0.0010
0.0098
0.1780
0.2184
0.0157
0.1575
0.1890
-
-
0.0039
0.0039
0.0039
0.0020
0.0020
0.0230
-
-
-
0.0110
0.1794
0.2198
-
-
-
Figure 84. WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale
recommended footprint
'SDG
'VP
DocID024244 Rev 11
069
234
Package information STM32F437xx and STM32F439xx
Table 112. WLCSP143 recommended PCB design rules (0.4 mm pitch)
Dimension Recommended values
Pitch
Dpad
Dsm
PCB pad design
0.4
260 µm max. (circular)
220 µm recommended
300 µm min. (for 260 µm diameter pad)
Non-solder mask defined via underbump allowed.
Device marking for WLCSP143
The following figure gives an example of topside marking orientation versus ball A 1 identifier location.
Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below.
Figure 85. WLCSP143 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID024244 Rev 11
STM32F437xx and STM32F439xx
7.3 LQFP144 package information
Package information
Figure 86. LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline
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DocID024244 Rev 11
$B0(B9
234
Package information STM32F437xx and STM32F439xx
Table 113. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min e
L
L1
D3
E
E1
E3 k ccc
D
D1 b c
A
A1
A2
-
0.050
1.350
0.170
0.090
21.800
19.800
-
21.800
19.800
-
-
0.450
-
0°
-
3.5°
-
-
-
1.400
0.220
-
22.000
20.000
17.500
22.000
20.000
17.500
0.500
0.600
1.000
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
22.200
20.200
-
-
0.750
-
7°
0.080
1.600
0.150
1.450
0.270
0.200
22.200
20.200
-
0.8583
0.7795
-
-
0.0177
-
0°
-
-
0.0020
0.0531
0.0067
0.0035
0.8583
0.7795
Typ
0.689
0.8661
0.7874
0.6890
0.0197
0.0236
0.0394
3.5°
-
-
-
0.0551
0.0087
-
0.8661
0.7874
Max
-
0.8740
0.7953
-
-
0.0295
-
7°
0.0031
0.0630
0.0059
0.0571
0.0106
0.0079
0.874
0.7953
DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
Figure 87. LQPF144- 144-pin,20 x 20 mm low-profile quad flat package recommended footprint
1. Dimensions are expressed in millimeters.
DLH
DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Device marking for LQFP144
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below.
Figure 88. LQFP144 marking example (package top view)
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Samples to run qualification activity.
DocID024244 Rev 11
STM32F437xx and STM32F439xx
7.4 LQFP176 package information
Package information
Figure 89. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline
# 3EATINGPLANE
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Symbol
Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data millimeters inches
(1)
Min
-
0.050
1.350
0.170
0.090
23.900
25.900
Typ
-
-
-
-
-
-
-
Max
1.600
0.150
1.450
0.270
0.200
24.100
26.100
Min
-
0.0020
0.0531
0.0067
0.0035
0.9409
1.0197
Typ
-
-
-
-
-
-
-
Max
0.0630
0.0059
0.0571
0.0106
0.0079
0.9488
1.0276
DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Table 114. LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data (continued) millimeters inches (1)
Symbol
Min Typ Max Min
ZE e
L
(2)
L1 k ccc
ZD
E
HE
-
23.900
25.900
-
-
0.450
-
0°
-
1.250
-
-
1.250
0.500
-
1.000
-
-
-
24.100
26.100
-
-
0.750
-
7°
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
-
0.9409
1.0197
-
-
0.0177
-
0°
-
Typ
0.0492
-
-
0.0492
0.0197
-
0.0394
-
-
Max
-
0.9488
1.0276
-
-
0.0295
-
7°
0.0031
DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
Figure 90. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint
1. Dimensions are expressed in millimeters.
4?&0?6
DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Device marking for LQFP176
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below.
Figure 91. LQFP176 marking (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID024244 Rev 11
STM32F437xx and STM32F439xx
7.5 LQFP208 package information
Package information
Figure 92. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline
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3/$1(
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F
FFF &
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PP
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.
3,1
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1. Drawing is not to scale.
H
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DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Table 115. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ
D
D1 b c
A
A1
A2 e
L
L1
D3
E
E1
E3 k ccc
-
0.050
1.350
0.170
0.090
29.800
27.800
27.800
-
-
0.450
-
0°
-
-
-
1.400
0.220
-
30.000
28.000
- 25.500
29.800
30.000
28.000
25.500
0.500
0.600
1.000
3.5°
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
30.200
28.200
-
-
0.750
-
7.0°
0.080
1.600
0.150
1.450
0.270
0.200
30.200
28.200
--
0.0020
0.0531
0.0067
0.0035
1.1732
1.0945
- 1.0039
1.1732
1.1811
1.0945
-
1.1024
1.0039
-
0.0177
-
0°
-
0.0197
0.0236
0.0394
3.5°
-
-
-
0.0551
0.0087
-
1.1811
1.1024
Max
0.0630
0.0059
0.0571
0.0106
0.0079
1.1890
1.1102
-
1.1890
1.1102
-
-
0.0295
-
7.0°
0.0031
DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
Figure 93. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint
1. Dimensions are expressed in millimeters.
8+B)3B9
DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Device marking for LQFP208
The following figure gives an example of topside marking orientation versus pin 1 identifier location.
Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below.
Figure 94. LQFP208 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID024244 Rev 11
STM32F437xx and STM32F439xx
7.6 UFBGA169 package information
Package information
Figure 95. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline
= 6HDWLQJSODQH
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1. Drawing is not to scale.
Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max
A
A1
0.460 0.530 0.600 0.0181 0.0209 0.0236
0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
D
E e
6.950 7.000 7.050 0.2736 0.2756 0.2776
0.2362
0.2382
6.950 7.000 7.050 0.2736 0.2756 0.2776
0.2362
0.2382
0.500 - - 0.0197 -
DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Table 116. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) millimeters inches (1)
Symbol
Min Typ Max Min Typ Max ddd eee fff -
-
-
-
0.150
0.050
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
-
-
0.0039
0.0059
0.0020
Figure 96. UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array recommended footprint
Note:
'SDG
'VP
069
Pitch
Dpad
Dsm
Table 117. UFBGA169 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Solder paste
0.5
0.27 mm
0.35 mm typ. (depends on the soldermask registration tolerance)
0.27 mm aperture diameter.
Non-solder mask defined (NSMD) pads are recommended.
4 to 6 mils solder paste screen printing process.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
Device marking for UFBGA169
The following figure gives an example of topside marking orientation versus ball A1 identifier location.
Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below.
Figure 97. UFBGA169 marking example (package top view)
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Samples to run qualification activity.
DocID024244 Rev 11
234
Package information
7.7 UFBGA176+25 package information
STM32F437xx and STM32F439xx
Figure 98. UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline
&
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1. Drawing is not to scale.
Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data millimeters inches
(1)
Symbol
Min.
A -
A1 -
A2 -
A3 -
A4 -
Typ.
Max.
Min.
-
-
0.110 -
0.130 -
0.450
-
0.320 -
-
-
Typ.
-
-
0.0051
0.0177
Max.
0.0236
0.0043
-
-
D1 9.100
-
E1 ddd -
9.100
e -
Z -
-
-
0.080 -
-
-
0.3937
0.3583
0.3937
0.3583
-
0.3996
-
0.3996
-
0.0031
DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
Symbol
Table 118. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) millimeters inches (1)
Min.
Typ.
Max.
Min.
Typ.
Max.
eee fff -
-
-
0.150
0.050
-
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
0.0059
0.0020
Figure 99. UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package recommended footprint
'SDG
'VP
Ϭϳͺ&Wͺsϭ
Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension Recommended values
Pitch
Dpad
Dsm
Stencil opening
Stencil thickness
Pad trace width
0.65 mm
0.300 mm
0.400 mm typ. (depends on the soldermask registration tolerance)
0.300 mm
Between 0.100 mm and 0.125 mm
0.100 mm
DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Device marking for UFBGA176+25
The following figure gives an example of topside marking orientation versus ball A1 identifier location.
Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below.
Figure 100. UFBGA176+25 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
Figure 101. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline
= 6HDWLQJSODQH
GGG =
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1. Drawing is not to scale.
Table 120. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data millimeters inches
(1)
Symbol
Min Typ Max Min Typ Max b
D
D1
E
A
A1
A2
E1 e
F ddd
-
0.150
-
0.350
12.850
-
12.850
-
-
-
-
-
-
0.760
0.400
13.000
11.200
13.000
11.200
0.800
0.900
-
1.100
-
-
0.450
13.150
-
13.150
-
-
-
0.100
-
0.0059
-
0.0138
0.5118
-
0.5118
-
-
-
-
-
-
0.0299
0.0157
0.5118
0.4409
0.5118
0.4409
0.0315
0.0354
-
0.0433
-
-
0.0177
0.5177
-
0.5177
-
-
-
0.0039
DocID024244 Rev 11
234
Package information STM32F437xx and STM32F439xx
Table 120. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data (continued) millimeters inches (1)
Symbol
Min Typ Max Min Typ Max eee fff
-
-
-
-
0.150
0.080
1. Values in inches are converted from mm and rounded to 4 decimal digits.
-
-
-
0.0059
0.0031
Device marking for TFBGA176
The following figure gives an example of topside marking orientation versus ball A1 identifier location.
Other optional marking or inset/upset marks, which depend on assembly location, are not indicated below.
Figure 102. TFBGA176 marking example (package top view)
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Samples to run qualification activity.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Package information
The maximum chip-junction temperature, T
J using the following equation:
max, in degrees Celsius, may be calculated
T
J
max = T
A
max + (P
D
max x Θ
JA
)
Where:
• T
A
max is the maximum ambient temperature in ° C,
• Θ
JA
is the package junction-to-ambient thermal resistance, in ° C/W,
• P
D
max is the sum of P
INT
max and P
I/O max (P
D
max = P
INT
max + P
I/O max),
• P
INT
max is the product of I
DD and internal power.
V
DD
, expressed in Watts. This is the maximum chip
P
I/O
max represents the maximum power dissipation on output pins where:
P
I/O
max = Σ (V
OL
× I
OL
) + Σ ((V
DD
– V
OH
) × I
OH
), taking into account the actual V
OL application.
/ I
OL
and V
OH
/ I
OH of the I/Os at low and high level in the
Symbol
Θ
JA
Table 121. Package thermal characteristics
Parameter Value
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
Thermal resistance junction-ambient
WLCSP143
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP176 - 24 × 24 mm / 0.5 mm pitch
Thermal resistance junction-ambient
LQFP208 - 28 × 28 mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFBGA169 - 7 × 7mm / 0.5 mm pitch
Thermal resistance junction-ambient
UFBGA176 - 10× 10 mm / 0.5 mm pitch
Thermal resistance junction-ambient
TFBGA216 - 13 × 13 mm / 0.8 mm pitch
43
31.2
40
38
19
52
39
29
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DocID024244 Rev 11
234
Part numbering STM32F437xx and STM32F439xx
Table 122. Ordering information scheme
Example:
Device family
STM32 = Arm-based 32-bit microcontroller
STM32 F 439 V I T 6 xxx
Product type
F = general-purpose
Device subfamily
437= STM32F437xx, USB OTG FS/HS, camera interface,
Ethernet, cryptographic acceleration
439= STM32F439xx, USB OTG FS/HS, camera interface,
Ethernet, LCD-TFT, cryptographic acceleration
Pin count
V = 100 pins
Z = 143 and 144 pins
A = 169 pins
I = 176 pins
B = 208 pins
N = 216 pins
Flash memory size
G = 1024 Kbytes of Flash memory
I = 2048 Kbytes of Flash memory
Package
T = LQFP
H = BGA
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Recommendations when using internal reset OFF
Appendix A Recommendations when using internal reset
OFF
When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry must be disabled.
• The embedded programmable voltage detector (PVD) is disabled.
• V
BAT
functionality is no more available and VBAT pin should be connected to V
DD
.
• The over-drive mode is not supported.
Table 123. Limitations depending on the operating power supply range
Operating power supply range
ADC operation
Maximum
Flash memory access frequency with no wait states
(f
Flashmax
)
Maximum Flash memory access frequency with wait states
(1)(2)
I/O operation
Possible Flash memory operations
V
DD
=1.7 to
2.1 V
(3)
Conversion time up to
1.2 Msps
20 MHz
(4)
168 MHz with 8 wait states and over-drive OFF
– No I/O compensation
8-bit erase and program operations only
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution.
3. V
DD
/V
DDA
minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 3.17.1: Internal reset ON ).
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
DocID024244 Rev 11
234
Application block diagrams STM32F437xx and STM32F439xx
Appendix B Application block diagrams
B.1 USB OTG full speed (FS) interface solutions
Figure 103. USB controller configured as peripheral-only and used in Full speed mode
6
$$
6TO6
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33
-36
1. External voltage regulator only needed when building a V
BUS
powered device.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
Figure 104. USB controller configured as host-only and used in full speed mode
6
$$
%.
'0)/
#URRENTLIMITER
POWERSWITCH
60WR
/VERCURRENT
'0)/)21
34-&XX
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33
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0!0"
0!0"
-36
1. The current limiter is required only if the application has to support a V switch can be used if 5 V are available on the application board.
BUS
powered device. A basic power
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Application block diagrams
Figure 105. USB controller configured in dual mode and used in full speed mode
6
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6TO6
$$
VOLTAGEREGULATOR
6
$$
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33
-36
1. External voltage regulator only needed when building a V
BUS
powered device.
2. The current limiter is required only if the application has to support a V switch can be used if 5 V are available on the application board.
BUS
powered device. A basic power
3. The ID pin is required in dual role only.
4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
DocID024244 Rev 11
234
Application block diagrams
B.2
STM32F437xx and STM32F439xx
USB OTG high speed (HS) interface solutions
Figure 106. USB controller configured as peripheral, host, or dual-mode and used in high speed mode
53"(3
/4'#TRL
34-&XX
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5,0)
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"53
6
33
53"
CONNECTOR
-36
1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F43x with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection.
2. The ID pin is required in dual role only.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Application block diagrams
Figure 107. MII mode using a 25 MHz crystal
84!,
-(Z
34-
-#5
(#,+
%THERNET
-!#
4)-
)%%%040
4IMER
INPUT
TRIGGER 4IMESTAMP
COMPARATOR
/3#
0,,
-))?48?#,+
-))?48?%.
-))?48$;=
-))?#23
-))?#/,
-))?28?#,+
-))?28$;=
-))?28?$6
-))?28?%2
-$)/
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003?/54
(#,+
-#/-#/
0(9?#,+-(Z
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0(9
-))
PINS
-))-$#
PINS
84
-36
1. f
HCLK
must be greater than 25 MHz.
2. Pulse per second when using IEEE1588 PTP optional signal.
Figure 108. RMII with a 50 MHz oscillator
34-
-#5
(#,+
%THERNET
-!#
4)-
)%%%040
4IMER
INPUT
TRIGGER 4IMESTAMP
COMPARATOR
2-))?48?%.
2-))?48$;=
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2-))?#28?$6
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-$#
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0(9
2-))
PINS
2-))-$#
PINS
/3#
-(Z
OR-(Z
OR
SYNCHRONOUS
-(Z
0,, (#,+
0(9?#,+-(Z 84 -(Z
-36
1. f
HCLK
must be greater than 25 MHz.
DocID024244 Rev 11
234
Application block diagrams STM32F437xx and STM32F439xx
Figure 109. RMII with a 25 MHz crystal and PHY with PLL
34-&
%THERNET
0(9
-#5
(#,+
%THERNET
-!#
4)-
)%%%040
4IMER
INPUT
TRIGGER 4IMESTAMP
COMPARATOR
2-))?48?%.
2-))?48$;=
2-))?28$;=
2-))?#28?$6
2-))?2%&?#,+
-$)/
-$#
2-))
PINS
2%&?#,+ 2-))-$#
PINS
84!,
-(Z
OR-(Z
OR
SYNCHRONOUS
-(Z
/3#
0,, (#,+
-#/-#/ 0(9?#,+-(Z 84
0,,
1. f
HCLK
must be greater than 25 MHz.
2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block.
-36
DocID024244 Rev 11
STM32F437xx and STM32F439xx Revision history
Date
12-Aug-2013
10-Sep-2013
Revision
Table 124. Document revision history
Changes
1
2
Initial release.
Added STM32F439xx part numbers and related informations.
STM32F437xx part numbers:
Replaced FSMC by FMC added Chrom-ART Accelerator and SAI interface.
Increased core, timer, GPIOs, SPI maximum frequencies
Updated
Figure 4: STM32F437xx and STM32F439xx block diagram .
Updated
Figure 5: STM32F437xx and STM32F439xx Multi-AHB matrix .
Removed note in
Updated
Figure 14: STM32F43x LQFP176 pinout .
Updated
Table 10: STM32F437xx and STM32F439xx pin and ball definitions and
Table 12: STM32F437xx and STM32F439xx alternate function mapping ..
Modified
Updated
Table 17: General operating conditions ,
Table 18: Limitations depending on the operating power supply range . Removed note 1 in
Table 22: reset and power control block characteristics . Added
Table 23: Over-drive switching characteristics .
Updated
Section : Typical and maximum current consumption ,
Table 34: Switching output I/O current consumption
,
Peripheral current consumption and Section : On-chip peripheral current consumption
.
Updated
Table 36: Low-power mode wakeup timings .
Modified
Section : High-speed external user clock generated from an external source
,
Section : Low-speed external user clock generated from an external source
, and Section 6.3.10: Internal clock source characteristics
.
Updated
Table 43: Main PLL characteristics
(audio and LCD-TFT PLL) characteristics .
Updated
.
Updated
Table 57: Output voltage characteristics
and Table 58: I/O AC characteristics
.
Updated
Table 60: TIMx characteristics
, Table 61: I2C characteristics ,
Table 62: SPI dynamic characteristics
,
Section : SAI characteristics .
Updated Table 102: SDRAM read timings
and
Table 104: SDRAM write timings .
DocID024244 Rev 11
240
Revision history STM32F437xx and STM32F439xx
Date
24-Jan-2014
31-Jan-2014
Table 124. Document revision history (continued)
Revision Changes
3
4
Added STM32F437AI and STM32F439AI part numbers and
UFBGA169 package.
Changed INTN into INTR in
.
Updated
.
Updated for PA4 and PA5 in Table 10: STM32F437xx and
STM32F439xx pin and ball definitions .
Added V
IN
for BOOT0 pins in
Table 14: Voltage characteristics .
IN
in Table 17: General operating conditions
.
for B pins
Updated maximum Flash memory access frequency with wait states for V
DD
=1.8 to 2.1 V in
Table 18: Limitations depending on the operating power supply range .
Updated
.
Updated
ON (ART accelerator enabled except prefetch), VDD=1.7 V ,
Table 32: Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V .
Updated
Table 57: Output voltage characteristics .
Updated
Table 58: I/O AC characteristics
.
Updated t h(SDA)
, t characteristics .
r(SDA) and t r(SCL) and added t
SP in Table 61: I2C
Updated f
SCK
in
Table 62: SPI dynamic characteristics .
Updated
Table 70: Dynamic characteristics: USB ULPI .
Updated
Section 6.3.26: FMC characteristics conditions. Updated
Figure 73: SDRAM read access waveforms (CL = 1)
SDRAM write access waveforms . Added
Table 103: LPSDR SDRAM read timings and
Table 105: LPSDR SDRAM write timings . Updated
and Table 104: SDRAM write timings
and added note
2.Table 108: Dynamic characteristics: SD / MMC characteristics
.
In the whole document, minimum supply voltage changed to 1.7 V when external power supply supervisor is used.
Updated conditions in
Table 62: SPI dynamic characteristics .
Added Z
DRV
in
Table 67: USB OTG full speed electrical characteristics
DocID024244 Rev 11
STM32F437xx and STM32F439xx Revision history
Date
24-Apr-2014
Table 124. Document revision history (continued)
Revision Changes
5
Changed SVGA (800x600) into XGA1024x768) on cover page and in
Section 3.10: LCD-TFT controller (available only on STM32F439xx)
.
Added DCMI_VSYNC alternate function on PG9 and updated note 6.
in Table 10: STM32F437xx and STM32F439xx pin and ball definitions
and Table 12: STM32F437xx and STM32F439xx alternate function mapping . Added note
below
Figure 16: STM32F43x UFBGA169 ballout .
Updated
Section 3.18.2: Regulator OFF .
Updated signal corresponding to pin L5 in
Updated
Table 53: ESD absolute maximum ratings
.
Updated V
IH
V
DD
in
Table 56: I/O static characteristics
. Added condition
>1.7 V in Table 58: I/O AC characteristics
.
Removed notes 3 and 4 in Table 62: SPI dynamic characteristics .
Added ACC
HSE in
Table 39: HSE 4-26 MHz oscillator characteristics
and ACC
LSE
in Table 40: LSE oscillator characteristics (f
Removed note 3 in Table 80: Temperature sensor characteristics .
Added
Figure 82: LQFP100 marking example (package top view)
,
Figure 85: WLCSP143 marking example (package top view)
,
Figure 88: LQFP144 marking example (package top view)
,
LQFP176 marking (package top view)
,
Figure 94: LQFP208 marking example (package top view) ,
Figure 97: UFBGA169 marking example
and Figure 100: UFBGA176+25 marking example
.
Added
Appendix A: Recommendations when using internal reset OFF
and removed Internal reset OFF hardware connection appendix.
DocID024244 Rev 11
240
Revision history STM32F437xx and STM32F439xx
Date
19-Feb-2015
Table 124. Document revision history (continued)
Revision Changes
6
Update SPI/IS2 in Table 2: STM32F437xx and STM32F439xx features and peripheral counts .
Updated LQFP208 in
Table 4: Regulator ON/OFF and internal reset
Updated
.
Updated current consumption with all peripherals disabled in
Updated note
in Table 28: Typical and maximum current consumptions in Standby mode .
Updated t
WUSTOP in
Table 36: Low-power mode wakeup timings .
Updated ESD standards and Table 53: ESD absolute maximum ratings .
Updated
Table 56: I/O static characteristics
.
Section : I2C interface characteristics : updated section introduction,
removed Table I2C characteristics , Figure I2C bus AC waveforms and measurement circuit and Table SCL frequency
; added Table 61: I2C analog filter characteristics .
Updated measurement conditions in
Table 62: SPI dynamic characteristics
.
Updated
Figure 51: Typical connection diagram using the ADC .
Updated
Section : Device marking for LQFP100 .
Updated
Figure 83: WLCSP143 - 143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline
4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint and
Table 112: WLCSP143 recommended PCB design rules
(0.4 mm pitch) . Updated Figure 85: WLCSP143 marking example
(package top view) and related note. Updated Section : Device marking for WLCSP143 .
Updated
Section : Device marking for LQFP144 .
Updated
Section : Device marking for LQFP176 .
Updated
Figure 92: LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline
; Updated Section : Device marking for LQFP208
.
Modified UFBGA169 pitch, updated
updated
Section : Device marking for UFBGA169 ,
Section : Device marking for UFBGA176+25
and Section : Device marking for
Updated Z pin count in
Table 122: Ordering information scheme
.
DocID024244 Rev 11
STM32F437xx and STM32F439xx Revision history
Date
28-Sep-2015
30-Nov-2015
11-Jan-2016
Table 124. Document revision history (continued)
Revision Changes
7
8
9
Updated notes related to the minimum and maximum values guaranteed by design, characterization or test in production.
Updated I
DD_STOP_UDM
in Table 27: Typical and maximum current consumptions in Stop mode .
Removed note related to tests in production in
and Table 26: Typical and maximum current consumption in Sleep mode
.
Updated
Table 41: HSI oscillator characteristics .
renamed
ACCHSI accuracy versus temperature and updated.
Updated
Figure 38: SPI timing diagram - slave mode and CPHA = 0
.
Updated
Section : Ethernet characteristics .
Updated
Table 43: Main PLL characteristics
,
and Table 45: PLLISAI (audio and LCD-TFT PLL) characteristics
.
Removed note 1 in Table 75: ADC static accuracy at f
Table 76: ADC static accuracy at f
.
and
Updated t d(SDCLKL _Data
) and t h(SDCLKL _Data) in
Updated note below marking schematics.
UFBGA169 recommended PCB design rules (0.5 mm pitch BGA) .
Added
and
Table 119: UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
.
Updated |V
SSX
− V
SS
| in Table 14: Voltage characteristics to add V
REF-
.
Updated t d(TXEN) and t d(TXD)
minimum value in Table 72: Dynamics characteristics: Ethernet MAC signals for RMII
and Table 73: Dynamics characteristics: Ethernet MAC signals for MII
.
Added V
REF-
in Table 74: ADC characteristics
.
Added A1 minimum and maximum values in
143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data .
Updated
Figure 86: LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline
.Updated
Figure 98: UFBGA176+25 - ball 10 x
Updated
Updated
Figure 22: Power supply scheme
.
Added t d(TXD) values corresponding to 1.71 V < V
DD
< 3.6 V in
Table 72: Dynamics characteristics: Ethernet MAC signals for RMII
.
DocID024244 Rev 11
240
Revision history STM32F437xx and STM32F439xx
Date
18-Jul-2016
19-Jan-2018
Table 124. Document revision history (continued)
Revision Changes
10
11
Updated
Figure 1: Compatible board design
STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package .
Added mission profile compliance with JEDEC JESD47 in
Section 6.2: Absolute maximum ratings
.
Changed
HSI deviation versus temperature to ACCHSI versus temperature.
Updated R
LOAD
in Table 85: DAC characteristics
.
Added note
related to the position of the external capacitor below
Figure 37: Recommended NRST pin protection
.
Updated
Figure 40: SPI timing diagram - master mode .
Added reference to optional marking or inset/upset marks in all package device marking sections. Updated
Figure 85: WLCSP143 marking example (package top view)
,
Figure 88: LQFP144 marking example (package top view) ,
Figure 91: LQFP176 marking (package top view)
,
Figure 94: LQFP208 marking example (package top view) ,
Figure 97: UFBGA169 marking example (package top view) ,
Figure 102: TFBGA176 marking example (package top view) .
Updated
.
Updated Arm wordmark and added Arm logo in
Updated LDC-TFT feature on cover page.
Updated
and Table 26: Typical and maximum current consumption in Sleep mode .
R
ADC
minimum value added in Table 74: ADC characteristics
.
LTDC clock output frequency changed to 83 MHz in
Table 107: LTDC characteristics
.
DocID024244 Rev 11
STM32F437xx and STM32F439xx
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