STMicroelectronics STM32F479VI Datasheet

Table 78.

ADC static accuracy at f

Table 79.

ADC static accuracy at f

ADC dynamic accuracy at f

= 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

= 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

= 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Table 80.

ADC dynamic accuracy at f

Table 81.

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

= 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159

= 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 159

Table 82.

Table 83.

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 84.

BAT

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 85.

internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 86.

Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 87.

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Table 88.

Asynchronous non-multiplexed SRAM/PSRAM/NOR - read timings . . . . . . . . . . . . . . . . 167

Table 89.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 167

Table 90.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 168

Table 91.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 169

Table 92.

Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 93.

Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 170

Table 94.

Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Table 95.

Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 172

DS11118 Rev 7 7/220

List of tables STM32F479xx

Table 96.

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 97.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Table 98.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177

Table 99.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Table 100. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 101. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 102. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Table 103. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Table 104. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 105. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 106. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Table 107. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 108. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 109. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V . . . . . . . . . . . . . 190

Table 111. Dynamic characteristics: SD / MMC characteristics, VDD = 1.71 to 1.9 V . . . . . . . . . . . . 191

Table 112. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Table 113. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Table 114. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Table 115. WLCSP168 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 116. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Table 117. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . 201

Table 118. LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Table 119. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Table 120. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . 208

Table 121. LQFP208 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Table 122. TFBGA216 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Table 123. TFBGA216 - Recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . . 213

Table 124. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Table 125. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 217

Table 126. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

8/220 DS11118 Rev 7

STM32F479xx

List of figures

List of figures

Figure 1.

Incompatible board design for LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2.

Incompatible board design for LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3.

UFBGA176 port-to-terminal assignment differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 4.

TFBGA216 port-to-terminal assignment differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5.

STM32F479xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6.

STM32F479xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7.

VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 29

Figure 8.

Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30

Figure 9.

PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 10.

Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 11.

Startup in regulator OFF: slow V

slope

- power-down reset risen after V

CAP_1 ,

CAP_2

Figure 12.

Startup in regulator OFF mode: fast V

slope

- power-down reset risen before V

CAP_1 , stabilization . . . . . . . . . . . . . . . . . . . . . . . 34

CAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 35

Figure 13.

STM32F47x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 14.

STM32F47x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 15.

STM32F47x WLCSP168 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 16.

STM32F47x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 17.

STM32F47x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 18.

STM32F47x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19.

STM32F47x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 20.

STM32F47x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 21.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 22.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 23.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 24.

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 25.

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

current consumption

(RTC ON / backup SRAM ON and LSE in Low drive mode) . . . . . . . . . . . . . . . . . . . . . . 107

Figure 28.

Typical V

BAT

current consumption

(RTC ON / backup SRAM ON and LSE in High drive mode) . . . . . . . . . . . . . . . . . . . . . . 108

Figure 29.

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 30.

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 31.

Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 32.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 33.

ACCHSI vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 34.

ACC

LSI

versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 35.

PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 36.

PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 37.

MIPI D-PHY HS/LP clock lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 38.

MIPI D-PHY HS/LP data lane transition timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 39.

FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 40.

I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 41.

Figure 42.

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 43.

SPI timing diagram - slave mode and CPHA = 1

SPI timing diagram - master mode

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 44.

SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

DS11118 Rev 7 9/220

List of figures STM32F479xx

Figure 45.

2 S slave timing diagram (Philips protocol) (1)

Figure 46.

2 S master timing diagram (Philips protocol)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Figure 47.

Figure 48.

SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Figure 49.

USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 151

Figure 50.

ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 51.

Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 52.

Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 53.

Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Figure 54.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 55.

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Figure 56.

Power supply and reference decoupling (V

REF+

Figure 57.

Power supply and reference decoupling (V

REF+ not connected to V

DDA connected to V

DDA

). . . . . . . . . . . . . 161

). . . . . . . . . . . . . . . . 161

Figure 58.

12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 59.

Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 166

Figure 60.

Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 168

Figure 61.

Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 62.

Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 63.

Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 64.

Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 65.

Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 177

Figure 66.

Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Figure 67.

NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Figure 68.

NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Figure 69.

NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 180

Figure 70.

NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 181

Figure 71.

SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 72.

SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 73.

Quad-SPI SDR timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Figure 74.

Quad-SPI DDR timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 75.

DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 76.

LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Figure 77.

LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 78.

SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Figure 79.

SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Figure 80.

LQFP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 81.

LQFP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 82.

LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Figure 83.

LQFP144 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 84.

LQFP144 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 85.

LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 86.

WLCSP168 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 87.

UFBGA169 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 88.

UFBGA169 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Figure 89.

UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 90.

LQFP176 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Figure 91.

LQFP176 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 92.

LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Figure 93.

UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 94.

UFBGA(176+25) - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 95.

LQFP208 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Figure 96.

LQFP208 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

10/220 DS11118 Rev 7

STM32F479xx List of figures

Figure 97.

LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 98.

TFBGA216 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 99.

TFBGA216 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 100. TFBGA216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

DS11118 Rev 7 11/220

Description

1 Description

STM32F479xx

The STM32F479xx devices are based on the high-performance Arm ®(a) Cortex ® -M4 32-bit

RISC core operating at a frequency of up to 180 MHz. The Cortex ® -M4 core features a

Floating point unit (FPU) single precision which supports all Arm ® single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32F479xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbytes, up to 384 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose

16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, a true random number generator (RNG), and a cryptographic acceleration cell. They also feature standard and advanced communication interfaces:

 Up to three I

 Six SPIs, two I 2 Ss full duplex. To achieve audio class accuracy, the I 2 S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.

 Four USARTs plus four UARTs

 An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the

ULPI)

 Two CANs

 One SAI serial audio interface

 An SDMMC host interface

 Ethernet and camera interface

 LCD-TFT display controller

 Chrom-ART Accelerator™

 DSI Host.

Advanced peripherals include an SDMMC interface, a flexible memory control (FMC) interface, a Quad-SPI Flash memory, camera interface for CMOS sensors and a

cryptographic acceleration cell. Refer to Table 2

for the list of peripherals available on each part number.

The STM32F479xx devices operate in the –40 to +105 °C temperature range from a 1.7 to

3.6 V power supply. A dedicated supply input for USB (OTG_FS and OTG_HS) only in full speed mode, is available on all packages.

The supply voltage can drop to 1.7 V (refer to

). A comprehensive set of

power-saving mode allows the design of low-power applications.

12/220 a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS11118 Rev 7

STM32F479xx Description

The STM32F479xx devices are offered in eight packages, ranging from 100 to 216 pins.

The set of included peripherals changes with the device chosen, according to

Table 2

These features make the STM32F479xx microcontrollers suitable for a wide range of applications:

 Motor drive and application control

 Medical equipment

 Industrial applications: PLC, inverters, circuit breakers

 Printers, and scanners

 Alarm systems, video intercom, and HVAC

 Home audio appliances

Figure 5 shows the general block diagram of the device family.

Table 2. STM32F479xx features and peripheral counts

Peripherals

Flash memory in Kbytes

SRAM in

Kbytes

System

Backup

FMC memory controller

Quad-SPI

Ethernet

Timers

Generalpurpose

Advancedcontrol

Basic

Random number generator

SPI / I

USART/UART

1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048

384(160+32+128+64)

Yes

4/2(full duplex)

4/3

(1)

Yes

6/2(full duplex)

4/4

(1)

Communication interfaces

USB OTG FS

USB OTG HS

CAN

SAI

SDIO

Camera interface

Yes

DS11118 Rev 7 13/220

Description

Table 2. STM32F479xx features and peripheral counts (continued)

STM32F479xx

Peripherals

MIPI-DSI Host

12-bit ADC

Number of channels

Yes

LCD-TFT Yes

Chrom-ART Accelerator™

(DMA2D)

Yes

Cryptography

GPIOs 71 131 114

Yes

12-bit DAC

Number of channels

Maximum CPU frequency

Operating voltage

Operating temperatures

Package

131 161 161

14 20 24

Yes

180 MHz

1.7 to 3.6V

(2)

Ambient operating temperature: − 40 to 85 °C / − 40 to 105 °C

Junction temperature: − 40 to 105 °C / − 40 to 125 °C

LQFP100 LQFP144

UFBGA169

WLCSP168

LQFP176

UFBGA176

LQFP208 TFBGA216

1. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.

2. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.19.2

For information on the device errata with respect to the datasheet and reference manual refer to the errata sheet (ES0321), available from the STMicroelectronics website www.st.com

14/220 DS11118 Rev 7

STM32F479xx Description

STM32F479xx devices are not compatible with other STM32F4xx devices.

Figure 1

and Figure 2

show incompatible board designs, respectively, for LQFP176 and

LQFP208 packages (highlighted pins).

The UFBGA176 and TFBGA216 ballouts are compatible with other STM32F4xx devices, only few IO port pins are substituted, as shown in

Figure 3 and

Figure 4

The LQFP100, LQFP144 and UFBGA169 packages are incompatible with other

STM32F4xx devices.

DS11118 Rev 7 15/220

Description STM32F479xx

135 134 133

STM32F469xx/479xx

LQFP176

132 PI0

131 VDD

130 VSS

129 VCAP2

128 PA13

127 PA12

126

PA11

125

PA10

124

PA9

123

PA8

122 PC9

121 PC8

120 PC7

119 PC6

118 VDDUSB

117 VSS

116 PG8

115 PG7

114 PG6

113 PG5

112 PG4

111 PG3

110 PG2

109 VSSDSI

108 DSIHOST_D1N

107 DSIHOST_D1P

106 VDD12DSI

105 DSIHOST_CKN

104 DSIHOST_CKP

103 VSSDSI

102 DSIHOST_D0N

101 DSIHOST_D0P

100 VCAPDSI

99 VDDSI

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

90 PD9

89 PD8

84 85 86 87 88

Figure 1. Incompatible board design for LQFP176 package

135 134 133

132 PI1

131 PI0

130 PH15

129 PH14

128 PH13

STM32F4xx

LQFP176

84 85 86 87 88

127 VDD

126 VSS

125 VCAP2

124 PA13

123 PA12

122 PA11

121 PA10

120 PA9

119 PA8

118 PC9

117 PC8

116 PC7

115 PC6

114 VDD

113

112

VSS

PG8

111 PG7

110 PG6

109 PG5

108 PG4

107 PG3

106 PG2

105 PD15

104 PD14

103 VDD

102 VSS

101 PD13

100 PD12

99 PD11

98 PD10

97 PD9

96 PD8

95 PB15

94 PB14

93 PB13

92 PB12

91 VDD

90 VSS

89 PH12

MS38294V2

1. Pins from 85 to 133 are not compatible.

16/220 DS11118 Rev 7

STM32F479xx Description

Figure 2. Incompatible board design for LQFP208 package

STM32F469xx/479xx

LQFP208

138 PC6

137 VDDUSB

136 VSS

135 PG8

134 PG7

133 PG6

132 PG5

131 PG4

130 PG3

129 PG2

128 VSSDSI

127 DSIHOST_D1N

126 DSIHOST_D1P

125 VDD12DSI

124 DSIHOST_CKN

123 DSIHOST_CKP

122 VSSDSI

121 DSIHOST_D0N

120 DSIHOST_D0P

119 VCAPDSI

118 VDDDSI

117

116

PD15

PD14

STM32F42x/STM32F43x

LQFP208

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

PK0

VSS

VDD

PJ11

PJ10

PJ9

PJ8

PJ7

PJ6

PD15

PD14

PC6

VDD

VSS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PK2

PK1

MS38295V1

1. Pins from 118 to 128 and pin 137 are not compatible

DS11118 Rev 7 17/220

Description STM32F479xx

18/220

Figure 3. UFBGA176 port-to-terminal assignment differences

2 3 4 5 6 7 8 9 10 11 12 13 14 15

PE3 PE2

PE4 PE5

PE 1 PE0 PB8 PB5

PG14 PG13 PB 4 PB3 PD7 PC12 PA15 PA14 PA13

PE 6 PB9 PB7 PB6

PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12

VBA T

PC 13

PI7

PI8

PC 14 PF0

PC 15 VSS

PI6

PI9

PI10

VDD

PI5

PI4

PI11

PH2

VDD

PDR

_ON

VDD VDD VDD PG9 PD5 PD1 PI3 NC PA11

VSS BOO T0 VSS VSS

VSS VSS VSS

VSS

PD4

VSS

PD 3 PD2

VDD12

DSI

HOST_

D1P

DSI

HOST_

D1N

PI1

PI0

VSS VCAP2 PC 9

PA10

PA 9

PA 8

PH0

PH1

NR ST

PF7

PF10

VSSA

VSS

PF2

PF3

PF6

PF9

PC 0

VR EF-

PA1

VDD PH3

VSS VSS VSS VSS VSS

VSS VD D PC 8 PC 7

PF1

PF4

PH4

PH5

VSS

DSI

VDD_

USB

PG8

VDD

DSI

VDD PG7

PC 6

PG6

PF5 VDD

PF8

BYPASS

_REG

PC1

PA0

PC2

PA4

PC3

PC4

VSS

PB2

PF13

VSS

PG1

PG0

VSS

VSS VSS

VSS

VCAP

PH6

VCAP

DSI

PG5 PG4

DSI

HOST_

CKP

DSI

HOST_

D0P

DSI

HOST_

CKN

DSI

HOST_

D0N

PD15

PD14

PG3

PG2

PD13

VDD VDD VDD PE13 PH7 PD12 PD11 PD10

VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE 8 PE 9 PE11 PE14 PB 12 PB13 PD 9 PD 8

VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PF10 PE12 PE15 PB 10 PB11 PB14 PB15

STM32F42xx/3xx

STM32F40xx/41xx

PD1 PI3 PI2

PD2

PH15

PI1

PH13 PH14 PI0

STM32F469xx

STM32F479xx

NC PD1 PI3

PD2

VDD12

DSI

HOST_

D1P

DSI

HOST_

D1N

PI1

PI0

VSS VCAP2 PC9 VSS VCAP2 PC9

VSS VDD PC8

VSS VDD PG8

VDD VDD PG7

PH12

PG5 PG4

PH11 PH10

PD15

PH8 PH9

PD14

VSS VDD PC8

VSS

DSI

VDD_

USB

PG8

VDD

DSI

VDD PG7

VCAP

DSI

PG5 PG4

DSI

HOST_

CKP

DSI

HOST_

D0P

DSI

HOST_

CKN

DSI

HOST_

D0N

PD15

PD14

MS39403V1

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

DS11118 Rev 7

STM32F479xx Description

PE4

Figure 4. TFBGA216 port-to-terminal assignment differences

PE3

3 4 5

PE2 PG14 PE1

PE0

PB8

PB5

PB4

PB3

11 12 13 14 15

PD7 PC12 PA15 PA14 PA13

PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 PD6 PD0 PC11 PC10 PA12

C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 PD5 PD3 PD1 PI3 PI2 PA11

D PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 PJ15 PD4 PD2 PH15 PI1 PA10

PC14 PF1 PI12 PI9

PDR

BOOT0 VDD VDD VDD VDD VCAP2 PH13 PH14 PI0 PA9

F PC15 VSS PI11 VDD VDD VSS VSS VSS VSS VSS VDD PC9 PA8

G PH0 PF2 PI13 PI15 VDD VSS

H PH1 PF3 PI14

PH4

VDD VSS

J NRST PF4 PH5 PH3 VDD VSS

VSS

VSS VDD

PC8 PC7

PG8 PC6

PG7 PG6

K PF7 PF6 PF5 PH2 VDD VSS VSS VSS VSS VSS VDD PD15

PB13

PD10

PF10 PF9 PF8 PC3

BYPASS

-REG

VSS VDD VDD VDD VDD VCAP1 PD14 PB12 PD9 PD8

VSSA PC0 PC1 PC2 PB2 PF12 PG1 PF15 PJ4 PD12 PD13 PG3 PG2 PJ5 PH12

VREFPA1 PA0 PA4 PC4 PF13 PG0 PJ3 PE8 PD11 PG5 PG4 PH7 PH9 PH11

P VREF+ PA2 PA6 PA5 PC5 PF14 PJ2 PF11 PE9 PE11 PE14 PB10 PH6 PH8 PH10

R VDDA PA3 PA7 PB1 PB0 PJ0 PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15

STM32F42xx/3xx

STM32F40xx/41xx

VDD PK1 PL2

VDD PJ11 PK0

VDD PJ8 PJ10

VDD PJ7 PJ9

VDD PJ6 PD15

STM32F469xx

STM32F479xx

VDD

DSI

HOST_

D1P

DSI

HOST_

D1N

VDDD

USB

VDD

DSI

VDD

VSS

DSI

VDD12

DSI

HOST_

CKP

DSI

HOST_

CKN

DSI

HOST_

D0P

DSI

HOST_

D0N

VDD

VCAP

DSI

PD15

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

MSv39404V1

DS11118 Rev 7 19/220

Description STM32F479xx

Figure 5. STM32F479xx block diagram

JTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

TRACECK

TRACED(3:0)

CCM data RAM 64 KB

JTAG & SW

ETM

MPUFPU

NVIC

ARM

Cortex M4

180 MHz

D-BUS

I-BUS

S-BUS

EXT MEM CTRL (FMC)

SRAM, PSRAM, NOR Flash

NAND Flash, SDRAM

QuadSPI

CLK, NE[3:0], A[23:0], D[31:0],

NOE, NWEN, NBL[3:0],

SDCLKE[1:0], SDNE[1:0],

NRAS, NCAS, NADV,

NWAIT, INTR

CLK,

BK1_NCS, BK2_NCS,

D[7:0]

Flash 1MB

3DES,

AES256

D+, D-

VDDUSB = 3.0 to 3.6 V

ULPI : CLK, D(7:0),

DIR, STP, NXT

SCL/SDA, INT, ID, VBUS

USB

OTG HS

DMA/

FIFO

GP-DMA2

GP-DMA1

8 Streams

FIFO

8 Streams

FIFO

SRAM1 160KB

SRAM2 32KB

SRAM3 128KB

HASH

RNG

CAMERA

ITF

USB

OTG FS

HSYNC, VSYNC

PIXCK, D(13:0)

D+, D-,

VDDUSB = 3.0 to 3.6 V,

SCL, SDA, INT, ID, VBUS

LCD-TFT FIFO

AHB2 180 MHz

AHB1 180 MHz

DMA-2D FIFO

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

RESET&

@VDDA

RC HS

RC LS

PLL1,2,3

POR

Reset

Int

SUPPLY

SUPERVISION

POR/PDR/

BOR

PVD

@VDDA @VDD

XTAL OSC

4-26MHz

IWDG

Standbyinterface

@VBAT

VDDA, VSSA,

NRST

OSCIN

OSCOUT

VBAT = 1.8 to 3.6 V

PH[15:0]

PI[15:0]

PJ[15:0]

CRC

XTAL 32kHz

RTC

AWU

Backup Register

4KB BKPRAM

TIM2

TIM3

TIM4

TIM5

TIM12

TIM13

OSC32_IN

OSC32_OUT

RTC_TAMP1

RTC_TAMP2

RTC_OUT

RTC_REFIN

RTC_TS

4 Channels, ETR as AF

PK[7:0]

DSIHOST_D0 P/N

DSIHOST_D1 P/N

DSIHOST_CK P/N

VDD12DSI, VDDSI, VSSDSI

VCAPDSI

DSIHOST_TE

168 AF

D[7:0]

CMD, CK as AF

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4]ETR),

BKIN as AF

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4]ETR),

BKIN as AF

DSI Host

SDIO / MMC

16b

DMA2

AHB/APB2 AHB/APB1

DMA1

32b

16b

32b

16b

4 Channels, ETR as AF

4 Channels

2 Channels as AF

1 Channels as AF

2 channels as AF

1 channel as AF

RX, TX, SCK,

CTS, RTS as AF

RX, TX, SCK,

CTS, RTS as AF

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

USART 2MBps

16b

16b smcard irDA smcard irDA

USART 2MBps

16b

WWDG

16b

TIM14 16b

USART2 smcard irDA

USART3 smcard irDA

UART4

UART5

UART7

UART8

SPI2/I2S

1 CH as AF

RX, TX, SCK,

CTS, RTS as AF

RX, TX, SCK

CTS, RTS as AF

RX, TX as AF

MOSI, MISO, SCK

NSS/WS, MCK as AF TIMER6

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

SD, SCK, FS

MCLK as AF

TIMER7

16b

SPI3/I2S

I2C1/SMBUS

MOSI, MISO, SCK

NSS/WS, MCK as AF

SCL, SDA, SMBA as AF

@VDDA

SCL, SDA, SMBA as AF

@VDDA

DAC1

DAC2

I2C2/SMBUS

I2C3/SMBUS

SCL, SDA, SMBA as AF

DDREF_ADC

8 analog inputs common to the 3 ADCs

8 analog inputs common to the ADC1 & 2

ADC1

ADC2

ADC 3

ITF bxCAN1 bxCAN2

TX, RX

8 analog inputs to ADC3

DAC1 as AF DAC2 as AF

MS38297V1

1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to

APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.

20/220 DS11118 Rev 7

STM32F479xx Functional overview

2.1 Arm

®

Cortex

®

-M4 with FPU and embedded Flash and SRAM

The Arm

Cortex

-M4 with FPU processor is the latest generation of Arm

processors for embedded systems, developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm

Cortex

-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an Arm

core in the memory size usually associated with 8- and 16-bit devices.

Note:

The processor supports a set of DSP instructions that allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

The STM32F47x line is compatible with all Arm

tools and software.

Figure 5 shows the general block diagram of the STM32F47x line.

Cortex

-M4 with FPU core is binary compatible with the Cortex

-M3 core.

2.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard

Arm ® Cortex ® -M4 with FPU processors. It balances the inherent performance advantage of the Arm ® Cortex ® -M4 with FPU over Flash memory technologies, which normally require the processor to wait for the Flash memory at higher frequencies.

To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark ® benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz.

2.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 Gbytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

DS11118 Rev 7 21/220

Functional overview

2.4 Embedded Flash memory

STM32F479xx

The devices embed a Flash memory of up to 2 Mbytes available for storing programs and data.

2.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

All devices embed:

 Up to 384Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM

RAM is accessed (read/write) at CPU clock speed with 0 wait states.

 4 Kbytes of backup SRAM

This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or V BAT mode.

2.7 Multi-AHB matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB

HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

22/220 DS11118 Rev 7

STM32F479xx

64-Kbyte

CCM data RAM

ARM

Cortex-M4

Functional overview

Figure 6. STM32F479xx Multi-AHB matrix

DMA1

DMA2

MAC

Ethernet

USB OTG

LCD-TFT

Chrom ART

Accelerator(DMA2D)

Bus matrix-S

ICODE

DCODE

Flash memory

SRAM1

160 Kbyte

SRAM2

32 Kbyte

SRAM3

128 Kbyte

AHB2 peripherals

AHB1 peripherals

FMC external

MemCtl

QuadSPI

APB1

APB2

MS33862V1

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

DS11118 Rev 7 23/220

Functional overview

The DMA can be used with the main peripherals:

 SPI and I

 I 2 C

 USART

 General-purpose, basic and advanced-control timers TIMx

 DAC

 SDIO

 Camera interface (DCMI)

 ADC

 SAI1

 QUADSPI.

STM32F479xx

The Flexible memory controller (FMC) includes three memory controllers:

 The NOR/PSRAM memory controller

 The NAND/memory controller

 The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller

The main features of the FMC controller are the following:

 Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM

– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

 Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

 8-,16-,32-bit data bus width

 Independent Chip Select control for each memory bank

 Independent configuration for each memory bank

 Write FIFO

 Read FIFO for SDRAM controller

 The Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is

HCLK/2.

LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

24/220 DS11118 Rev 7

STM32F479xx Functional overview

All STM32F479xx devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can work in direct mode through registers, external flash status register polling mode and memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting

8, 16 and 32-bit access. Code execution is supported.

The opcode and the frame format are fully programmable. Communication can be either in

Single Data Rate or Dual Data Rate.

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to

XGA (1024x768) resolution with the following features:

 2 displays layers with dedicated FIFO (64x32-bit)

 Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer

 Up to 8 Input color formats selectable per layer

 Flexible blending between two layers using alpha value (per pixel or constant)

 Flexible programmable parameters for each layer

 Color keying (transparency color)

 Up to 4 programmable interrupt events.

2.12 DSI Host (DSIHOST)

The DSI Host is a dedicated peripheral for interfacing with MIPI



DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display.

These interfaces are as follows:

 LTDC interface:

– Used to transmit information in Video Mode, in which the transfers from the host processor to the peripheral take the form of a real-time pixel stream (DPI).

– Through a customized for mode, this interface can be used to transmit information in full bandwidth in the Adapted Command Mode (DBI).

 APB slave interface:

– Allows the transmission of generic information in Command mode, and follows a proprietary register interface.

– Can operate concurrently with either LTDC interface in either Video Mode or

Adapted Command Mode.

 Video mode pattern generator:

– Allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli.

DS11118 Rev 7 25/220

Functional overview STM32F479xx

The DSI Host main features:

 Compliant with MIPI



Alliance standards

 Interface with MIPI



D-PHY

 Supports all commands defined in the MIPI



Alliance specification for DCS:

– Transmission of all Command mode packets through the APB interface

– Transmission of commands in low-power and high-speed during Video Mode

 Supports up to two D-PHY data lanes

 Bidirectional communication and escape mode support through data lane 0

 Supports non-continuous clock in D-PHY clock lane for additional power saving

 Supports Ultra Low-Power mode with PLL disabled

 ECC and Checksum capabilities

 Support for End of Transmission Packet (EoTp)

 Fault recovery schemes

 3D transmission support

 Configurable selection of system interfaces:

– AMBA APB for control and optional support for Generic and DCS commands

– Video Mode interface through LTDC

– Adapted Command Mode interface through LTDC

 Independently programmable Virtual Channel ID in

– Video Mode

– Adapted Command Mode

– APB Slave

Video Mode interfaces features

 LTDC interface color coding mappings into 24-bit interface:

– 16-bit RGB, configurations 1, 2, and 3

– 18-bit RGB, configurations 1 and 2

– 24-bit RGB

 Programmable polarity of all LTDC interface signals

 Maximum resolution is limited by available DSI physical link bandwidth:

– Number of lanes: 2

– Maximum speed per lane: 500 Mbps

Adapted interface features

 Support for sending large amounts of data through the memory_write_start (WMS) and memory_write_continue (WMC) DCS commands

 LTDC interface color coding mappings into 24-bit interface:

– 16-bit RGB, configurations 1, 2, and 3

– 18-bit RGB, configurations 1 and 2

– 24-bit RGB

26/220 DS11118 Rev 7

STM32F479xx

Video mode pattern generator

 Vertical and horizontal color bar generation without LTDC stimuli

 BER pattern without LTDC stimuli

Functional overview

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions:

 Rectangle filling with a fixed color

 Rectangle copy

 Rectangle copy with pixel format conversion

 Rectangle composition with blending and pixel format conversion.

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables.

An interrupt can be generated when an operation is complete or at a programmed watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

2.14 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 93 maskable interrupt channels plus the 16 interrupt lines of the Cortex

M4 with FPU core.

 Closely coupled NVIC gives low-latency interrupt processing

 Interrupt entry vector table address passed directly to the core

 Allows early processing of interrupts

 Processing of late arriving, higher-priority interrupts

 Support tail chaining

 Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 159 GPIOs can be connected to the 16 external interrupt lines.

DS11118 Rev 7 27/220

Functional overview STM32F479xx

2.16 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is

90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.

The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio class performance. In this case, the I

S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

At startup, boot pins are used to select one out of three boot options:

 Boot from user Flash

 Boot from system memory

 Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to application note AN2606 for details.

Note:

 V

= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through V

pins.

 V

SSA

, V

DDA

= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. V

DDA

and V

SSA

must be connected to V

and V

, respectively.

DDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to

be aligned with the targeted maximum frequency. Refer to Operating conditions

). Refer to

Table 3

to identify the packages supporting this option.

 V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

is not present.

 V

DDUSB

can be connected either to V

or an external independent power supply (3.0 to 3.6 V) for USB transceivers.

For example, when device is powered at 1.8V, an independent power supply 3.3 V can be connected to V

DDUSB it is independent from V first to disappear.

. When the V

DDUSB

or V

DDA

is connected to a separated power supply,

but it must be the last supply to be provided and the

28/220 DS11118 Rev 7

STM32F479xx Functional overview

The following conditions must be respected:

– During power-on phase (V

< V

DD_MIN

), V

DDUSB

should be always lower than

– During power-down phase (V

< V

DD_MIN

), V

DDUSB

should be always lower than

– V

DDUSB

rising and falling time rate specifications must be respected.

– In operating mode phase, V

DDUSB

could be lower or higher than VDD:

– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by

DDUSB

are operating between V

DDUSB_MIN and V

DDUSB_MAX

.The V supplies both USB transceivers (USB OTG_HS and USB OTG_FS).

DDUSB

– If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by V

DDUSB

– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by V

DDUSB

are operating between V

DD_MIN

and V

DD_MAX

– If USB (USB OTG_HS/OTG_FS) is not used and the associated GPIOs powered by V

DDUSB

are not used, then V

must not be floating).

DDUSB

should be tied to V

or V

Figure 7. V

DDUSB

connected to an external independent power supply

DDUSB_MAX

USB functional area

DDUSB

DDUSB_MIN

USB non functional area

DD_MIN

= V

DDA

USB non functional area

Power-on Operating mode Power-down time

MS37590V1

The DSI (Display Serial Interface) sub-system uses several power supply pins that are independent from the other supply pins:

 VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI

D-PHY. This supply must be connected to global VDD.

 VCAPDSI pin is the output of DSI Regulator (1.2 V), which must be connected externally to VDD12DSI.

 VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes pins. An external capacitor of 2.2 µF must be connected on VDD12DSI pin.

 VSSDSI pin is an isolated supply ground used for DSI sub-system.

 If DSI functionality is not used at all, then:

– VDDDSI pin must be connected to global VDD.

DS11118 Rev 7 29/220

Functional overview STM32F479xx

– VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor is no more needed.

– VSSDSI pin must be grounded.

30/220

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On other packages the power supply supervisor is always enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when V

POR/PDR

or V

BOR

is below a specified threshold,

, without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors the V

DDA

power supply and compares it to the V

PVD generated when V

DDA higher than the V

PVD

drops below the V

PVD

threshold. An interrupt can be

threshold and/or when V

DDA message and/or put the MCU into a safe state. The PVD is enabled by software.

threshold. The interrupt service routine can then generate a warning

This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.

An external power supply supervisor should monitor V

DD the device in reset mode as long as V

DD connected to VSS, as shown in

Figure 8 .

and NRST and should maintain

is below a specified threshold. PDR_ON must be

Figure 8. Power supply supervisor interconnection with internal reset OFF

VDD

STM32F479xx

VBAT

PDR_ON

Application reset signal (optional)

VSS

PDR not active : 1.7 V < VDD < 3.6 V

MSv36589V1

DS11118 Rev 7

STM32F479xx Functional overview

The V

specified threshold, below which the device must be maintained under reset, is

1.7 V (see Figure 9

A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no more supported:

 The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled

 The brownout reset (BOR) circuitry must be disabled

 The embedded programmable voltage detector (PVD) is disabled

 V

BAT

functionality is no more available and V

BAT

pin should be connected to V

All packages allow to disable the internal reset through the PDR_ON signal when connected to V

Figure 9. PDR_ON control with internal reset OFF

V DD

PDR = 1.7 V time

Reset by other source than power supply supervisor

NRST

PDR_ON time

MS19009V7

PDR_ON

1. PDR_ON signal to be kept always low.

The regulator has four operating modes:

 Regulator ON

– Main regulator mode (MR)

– Low power regulator (LPR)

– Power-down

 Regulator OFF

DS11118 Rev 7 31/220

Functional overview STM32F479xx

On packages embedding the BYPASS_REG pin, the regulator is enabled by holding

BYPASS_REG low. On all other packages, the regulator is always enabled.

There are three power modes configured by software when the regulator is ON:

 MR mode used in Run/sleep modes or in Stop modes

– In Run/Sleep mode

The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption.

The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling.

– In Stop modes

The MR can be configured in two ways during stop mode:

MR operates in normal mode (default mode of MR in stop mode)

MR operates in under-drive mode (reduced leakage mode).

 LPR is used in the Stop modes:

The LP regulator mode is configured by software when entering Stop mode.

Like the MR mode, the LPR can be configured in two ways during stop mode:

– LPR operates in normal mode (default mode when LPR is ON)

– LPR operates in under-drive mode (reduced leakage mode).

 Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost.

Refer to Table 3

for a summary of voltage regulator modes versus device operating modes.

Two external ceramic capacitors should be connected on V

CAP_1

Section 2.18

and

Table 125 .

and V

CAP_2

pin. Refer to

All packages have the regulator ON feature.

Table 3. Voltage regulator configuration mode versus device operating mode

(1)

Voltage regulator configuration

Run mode Sleep mode Stop mode Standby mode

Normal mode

Over-drive mode

(2)

Under-drive mode

Power-down mode

1. ‘-’ means that the corresponding configuration is not available.

2. The over-drive mode is not available when V

= 1.7 to 2.1 V.

MR or LPR

Yes

32/220 DS11118 Rev 7

STM32F479xx Functional overview

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V

voltage source through V

CAP_1

and V

CAP_2

pins.

Since the internal voltage scaling is not managed internally, the external voltage value must

.The two

2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to

Section 2.18

When the regulator is OFF, there is no more internal monitoring on V

12 supply supervisor should be used to monitor the V

. An external power

of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V

power domain.

In regulator OFF mode, the following features are no more supported:

 PA0 cannot be used as a GPIO pin since it allows to reset a part of the V

12 domain which is not reset by the NRST pin.

logic power

 As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.

 The over-drive and under-drive modes are not available.

 The Standby mode is not available.

Figure 10. Regulator OFF

V12

External V

CAP_1/2

power supply supervisor

Ext. reset controller active when V

CAP_1/2

< Min V

Application reset signal (optional)

V12

PA0

NRST

BYPASS_REG

CAP_1

CAP_2 ai18498V3

DS11118 Rev 7 33/220

Functional overview

Note:

STM32F479xx

The following conditions must be respected:

 V

must always be higher than V

CAP_1

and V

CAP_2 to avoid current injection between power domains.

 If the time for V

CAP_1

and V and V

CAP_2 reach V

CAP_2 to reach V

12 minimum value is faster than the time for

to reach 1.7 V, then PA0 must be kept low to cover both conditions: until V

CAP_1 minimum value and until V

reaches 1.7 V (see Figure 11

 Otherwise, if the time for V

CAP_1 than the time for V

Figure 12

and V

CAP_2 to reach V

12 minimum value is slower

to reach 1.7 V, then PA0 can be asserted low externally (see

 If V

CAP_1

and V

CAP_2

go below V

12 minimum value and V reset must be asserted on PA0 pin.

is higher than 1.7 V, then a

The minimum value of V

(see Operating conditions ).

depends on the maximum frequency targeted in the application

Figure 11. Startup in regulator OFF: slow V

- power-down reset risen after V

slope

CAP_1

, V

CAP_2 stabilization

PDR = 1.7 or 1.8 V

Min V

CAP_1

, V

CAP_2 time

NRST

PA0 time ai18491g

1. This figure is valid whatever the internal reset mode (ON or OFF).

34/220 DS11118 Rev 7

STM32F479xx Functional overview

Figure 12. Startup in regulator OFF mode: fast V

- power-down reset risen before V

CAP_1

, V

slope

CAP_2 stabilization

PDR = 1.7 or 1.8 V

(2)

Min V

CAP_1

, V

CAP_2 time

NRST

PA0 time ai18492f

1. This figure is valid whatever the internal reset mode (ON or OFF).

2.20.3 Regulator ON/OFF and internal reset ON/OFF availability

Package

Table 4. Regulator ON/OFF and internal reset ON/OFF availability

Regulator ON Regulator OFF Internal reset ON Internal reset OFF

WLCSP168

UFBGA169

LQFP208

LQFP176

UFBGA176

TFBGA216

Yes

BYPASS_REG set to V

Yes

BYPASS_REG set to V

Yes

PDR_ON set to V

Yes

PDR_ON set to V

2.21 Real-time clock (RTC), backup SRAM and backup registers

The backup domain includes:

 The real-time clock (RTC)

 4 Kbytes of backup SRAM

 20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format.

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power

RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.

DS11118 Rev 7 35/220

Functional overview STM32F479xx

Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.

A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see

Section 2.22

). It can be enabled by software.

The backup registers are 32-bit registers used to store 80 bytes of user application data when V

power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see

Section 2.22

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the V

supply when present or from the V

BAT

pin.

36/220

The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

 Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

 Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of

SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled.

The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see

Table 5

– Normal mode (default mode when MR or LPR is enabled)

– Under-drive mode.

The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).

Voltage regulator configuration

Table 5. Voltage regulator modes in stop mode

Main regulator (MR) Low-power regulator (LPR)

Normal mode

Under-drive mode

MR ON

MR in under-drive mode

LPR ON

LPR in under-drive mode

 Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The

DS11118 Rev 7

STM32F479xx Functional overview

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs.

The standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power.

2.23 V

BAT

operation

The V

BAT

pin allows to power the device V supercapacitor, or from V present.

BAT

domain from an external battery, an external when no external battery neither an external supercapacitor are

Note:

BAT

operation is activated when V

is not present.

The V

BAT

pin supplies the RTC, the backup registers and the backup SRAM.

When the microcontroller is supplied from V

BAT do not exit it from V

BAT operation.

, external interrupts and RTC alarm/events

When PDR_ON pin is connected to V

SS more available and V

BAT

(Internal Reset OFF), the V pin should be connected to V DD .

BAT functionality is no

2.24 Timers and watchdogs

The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 6 compares the features of the advanced-control, general-purpose and basic timers.

DS11118 Rev 7 37/220

Functional overview STM32F479xx

Timer type

Table 6. Timer feature comparison

Timer

Counter resolution

Counter type

Prescaler factor

DMA request generation

Capture/ compare channels

Complementary output

Max interface clock

(MHz)

Max timer clock

(MHz)

(1)

Advanced control

TIM1,

TIM8

General purpose

Basic

TIM2,

TIM5

TIM3,

TIM4

TIM9

TIM10

TIM11

TIM12

TIM13

TIM14

TIM6,

TIM7

16-bit

32-bit

16-bit

Up,

Down,

Up/down

Up,

Down,

Up/down

Up,

Down,

Up/down

Any integer between 1 and 65536

Yes

1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the

RCC_DCKCFGR register.

180

90/180

180

90/180

38/220

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.

Their 4 independent channels can be used for:

 Input capture

 Output compare

 PWM generation (edge- or center-aligned modes)

 One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose

TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-

100%).

The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

TIM1 and TIM8 support independent DMA request generation.

DS11118 Rev 7

STM32F479xx Functional overview

There are ten synchronizable general-purpose timers embedded in the STM32F47x devices

(see Table 6 for differences).

 TIM2, TIM3, TIM4, TIM5

The STM32F47x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/down counter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit autoreload up/down counter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the

Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.

 TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base.

TIM6 and TIM7 support independent DMA request generation.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

DS11118 Rev 7 39/220

Functional overview STM32F479xx

This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:

 a 24-bit downcounter

 autoreload capability

 maskable system interrupt generation when the counter reaches 0

 programmable clock source.

circuit interface (I

2

C)

Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the

7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

The I²C bus interfaces can be served by DMA and support SMBus 2.0/PMBus.

The devices also include programmable analog and digital noise filters (see Table 7 ).

Filter

Table 7. Comparison of I2C analog and digital filters

Analog Digital

Pulse width of suppressed spikes  50 ns Programmable length, from one to fifteen I2C peripheral clocks

(USART)

The devices embed four universal synchronous/asynchronous receiver transmitters

(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, UART5, UART7, and UART8).

These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 bit/s.

USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller.

40/220 DS11118 Rev 7

STM32F479xx Functional overview

Name

USART1

USART2

USART3

UART4

UART5

USART6

UART7

UART8

Standard features

Modem

(RTS/CTS)

Table 8. USART feature comparison (1)

LIN

SPI master irDA

Smartcard

(ISO 7816)

Max. baud rate in Mbit/s

Oversampling by 16

Oversampling by 8

APB mapping

5.62

2.81

5.62

2.81

11.25

5.62

11.25

5.62

APB1

(max.

45 MHz)

APB2

(max.

90 MHz)

APB1

(max.

45 MHz)

APB1

(max.

45 MHz)

APB2

(max.

90 MHz)

APB1

(max.

45 MHz)

APB1

(max.

45 MHz)

APB1

(max.

45 MHz)

1. X = feature supported.

2.27 Serial peripheral interface (SPI)

The devices feature up to six SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s,

SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the

DMA controller.

The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode.

2.28 Inter-integrated sound (I

2

S)

Two standard I

S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel.

DS11118 Rev 7 41/220

Functional overview

Note:

STM32F479xx

Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I 2 S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

All I2Sx can be served by the DMA controller.

For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port

B and GPIO Port D.

2.29 Serial Audio interface (SAI1)

The serial audio interface (SAI1) is based on two independent audio sub-blocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks can be configured in master or in slave mode.

In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency.

The two sub-blocks can be configured in synchronous mode when full-duplex mode is required.

SAI1 can be served by the DMA controller.

The devices feature an additional dedicated PLL for audio I 2 S and SAI applications. It allows to achieve error-free I 2 S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I 2 S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the

2 S/SAI flow with an external PLL (or Codec output).

2.31 Audio and LCD PLL(PLLSAI)

An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the

PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or

11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.

The PLLSAI is also used to generate the LCD-TFT clock.

42/220

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

DS11118 Rev 7

STM32F479xx Functional overview

The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory

Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.

2.33 Ethernet MAC interface with dedicated DMA and IEEE 1588 support

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface

(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.

The devices include the following features:

 Supports 10 and 100 Mbit/s rates

 Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F4xx reference manual for details)

 Tagged MAC frame support (VLAN support)

 Half-duplex (CSMA/CD) and full-duplex operation

 MAC control sublayer (control frames) support

 32-bit CRC generation and removal

 Several address filtering modes for physical and multicast address (multicast and group addresses)

 32-bit status code for each transmitted or received frame

 Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes.

 Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008

(PTP V2) with the time stamp comparator connected to the TIM2 input

 Triggers interrupt when system time becomes greater than target time

2.34 Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1

Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 bytes of SRAM are allocated for each CAN.

DS11118 Rev 7 43/220

Functional overview STM32F479xx

2.35 Universal serial bus on-the-go full-speed (OTG_FS)

The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.

The main features are:

 Combined Rx and Tx FIFO size of 1.28 KB with dynamic FIFO sizing

 Supports the session request protocol (SRP) and host negotiation protocol (HNP)

 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints

 12 host channels with periodic OUT support

 Software configurable to OTG1.3 and OTG2.0 modes of operation

 USB 2.0 LPM (Link Power Management) support

 Internal FS OTG PHY support

 HNP/SNP/IP inside (no need for any external resistor)

For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

2.36 Universal serial bus on-the-go high-speed (OTG_HS)

The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.

The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG

2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.

The main features are:

 Combined Rx and Tx FIFO size of 4 KB with dynamic FIFO sizing

 Supports the session request protocol (SRP) and host negotiation protocol (HNP)

 8 bidirectional endpoints

 16 host channels with periodic OUT support

 Software configurable to OTG1.3 and OTG2.0 modes of operation

 USB 2.0 LPM (Link Power Management) support

 Internal FS OTG PHY support

 External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.

 Internal USB DMA

 HNP/SNP/IP inside (no need for any external resistor)

 for OTG/Host modes, a power switch is needed in case bus-powered devices are connected

44/220 DS11118 Rev 7

STM32F479xx Functional overview

The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:

 Programmable polarity for the input pixel clock and synchronization signals

 Parallel data communication can be 8-, 10-, 12- or 14-bit

 Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)

 Supports continuous mode or snapshot (a single frame) mode

 Capability to automatically crop the image black & white.

The devices embed a cryptographic accelerator. This cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to provide confidentiality, authentication, data integrity and non repudiation when exchanging messages with a peer.

 These algorithms consists of:

Encryption/Decryption

– DES/TDES (data encryption standard/triple data encryption standard): ECB

(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-

,128- or 192-bit key

– AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (counter mode) chaining algorithms, 128, 192 or 256-bit key

Universal hash

– SHA-1 and SHA-2 (secure hash algorithms)

– MD5

– HMAC

The cryptographic accelerator supports DMA request generation.

2.39 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit.

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.

DS11118 Rev 7 45/220

Functional overview STM32F479xx

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allowing maximum I/O toggling up to 90 MHz.

2.41 Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

 Simultaneous sample and hold

 Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,

TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as V

BAT

, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and V

BAT conversion are enabled at the same time, only V

BAT

conversion is performed.

As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.

46/220 DS11118 Rev 7

STM32F479xx Functional overview

This dual digital Interface supports the following features:

 two DAC converters: one for each output channel

 8-bit or 10-bit monotonic output

 left or right data alignment in 12-bit mode

 synchronized update capability

 noise-wave generation

 triangular-wave generation

 dual DAC channel independent or simultaneous conversions

 DMA capability for each channel

 external triggers for conversion

 input voltage reference V

REF+

Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.

2.44 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with

SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

2.45 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the

STM32F47x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

DS11118 Rev 7 47/220

Pinouts and pin description

3 Pinouts and pin description

Figure 13. STM32F47x LQFP100 pinout

STM32F479xx

PE2

VSS

VBAT

PC13

PC14

PC15

VSS

VDD

PH0

PH1

NRST

PC0

PC1

PC2

PC3

VSSA

VREF+

VDDA

PA0

PA1

PA2

PA3

VSS

VDD

PA4

LQFP100

1. The above figure shows the package top view.

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

VDDUSB

DSIHOST_D1N

DSIHOST_D1P

VDD12DSI

DSIHOST_CKN

DSIHOST_CKP

VSSDSI

DSIHOST_D0N

DSIHOST_D0P

VCAPDSI

VDDDSI

PD15

PD14

PD10

PD9

MS40560V1

48/220 DS11118 Rev 7

PF3

PF4

PF5

VSS

VDD

PF10

PH0

PH1

NRST

VSSA

VREF+

VDDA

PA0

PA1

PA2

PA3

VSS

VDD

PA4

PA5

PC0

PC1

PC2

PC3

VDD

PE3

PE4

PE5

PE6

VBAT

PC13

PC14

PC15

PF0

PF1

PF2

STM32F479xx

Figure 14. STM32F47x LQFP144 pinout

Pinouts and pin description

LQFP144

VCAP2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

VDDUSB

PG8

PG7

PG6

PG5

PG4

PG3

PG2

DSIHOST_D1N

DSIHOST_D1P

VDD12DSI

DSIHOST_CKN

DSIHOST_CKP

VSSDSI

DSIHOST_D0N

DSIHOST_D0P

VCAPDSI

VDDDSI

PD15

PD14

VDD

VSS

PD12

PD11

PD10

108

107

106

105

104

103

102

101

100

MS40561V2

1. The above figure shows the package top view.

DS11118 Rev 7 49/220

Pinouts and pin description

Figure 15. STM32F47x WLCSP168 pinout

12 11 10 9 8 7 6 5 4 3 2 1

PI7 VDD PE0 PB7 PB3 VDD PG12 PD7 VSS PD1 PA15 PI2

B PE5 PI6 VSS PB8 PB5 VSS PG11 VDD PD4 PC11 PI3 PH13

C VBAT PE4 PI5

D PC13 PE6

PE1 PB4 PG10 PD5 PD2 PC12 PI1 VDD VSS

PI4

PDR_

PG15 PG9 PD3 PC10 PA14 PH14 VCAP2 PA13

E PC15 PC14 PE3

PB9 PG13 PD6 PD0 PI0 PH15 PA10 PA9 PA8

VSS PI11 PI10 PE2 BOOT0 PA11 PA12 PC9 PC8 PC6 VSS

VDD

USB

PF2

PF5

VDD

PH1

PC1

VDD PF0 PI9 PB6 PC7 PG8 PG2 PG3 PG6 PG4 PG5

PF3

VSS

PH0 PF10

VSSA

PF1

PF4

PA0

NRST PF15

PC0

PA1

PA2

PA7

PH5

PA5

VSS

PF13

PF11

PG7

PG0

PE9

PF14 PE13

PB12 PD13

PE14

PB11

PH9

PD11

PB13

PD8

DSI

HOST

_D1P

DSI

HOST

_D0N

DSI

HOST

_D0P

DSI

HOST

_D1N

DSI

HOST

_CKN

VSS

DSI

HOST

_CKP

VDD12

DSI

VCAP

DSI

PD14 PD15

VDD

DSI

M VDDA PH2 PH4 PA4 PF12 PE8 PE12 PH8 PH10 PD10 PD12 VSS

N PH3 VSS PA3 PB1 VSS PE7 PE11 PB10 VCAP1 PH11 PB15 PD9

P VDD PA6 PB0 PB2 VDD PG1 PE10 PE15 VSS VDD PH12 PB14

STM32F479xx

MSv35729V2

1. The above figure shows the package bottom view.

50/220 DS11118 Rev 7

STM32F479xx

A PI6

PI5

PE1

Pinouts and pin description

Figure 16. STM32F47x UFBGA169 ballout

5 6 7 8 9 10 11 4

PE0 BOOT0 PG13 PG12 PD7 PC12 PA14 PA13

PA12

PA11

B PI7 PE2 PI4 PB7 PB3 PG11 PD5 PD2 PC11 PAI3 PA15 PI2 PI0

C PE3 PE4

PDR_

PB9 PB6 PD4 PD1 PD3 PD0 PC10 PI1 PH15 PH14

D PE5 PE6 VDD PB8 PB5 PB4 PD6 PA8 PH13 VDD VSS VCAP2 PG8

E PC14 PI9 VSS PI10 VBAT PG9 PG10 PA9 PA10 PC8 PG7 PG5 PG4

F PC15 PI11 PF0 VDD VSS PG15 VDD VSS PC6 PC7 PG6 PG3 PG2

PH1

PF10

VSS

PA1

PH0

NRST

PA2

PF1

PF5

PA3

PC13

PF3

VSSA VDDA VDD

PA7

PF2

PF14

PA0

PB1

PE8

PE9

VSS

VDD

VSS

PE10

VSS

PE11

VDD

PH8

PE13 PH10

PE14

VSS

PH9

PH11

PC9

PH12

VSS

VDD

USB

DSI

HOST_

D1P

VSSDSI

DSI

HOST_

CKP

VDD12

DSI

HOST_

D0P

DSI

HOST_

D1N

DSI_

HOST

CKN

DSI

HOST_

D0N

VDD VSSDSI

VCAP

DSI

VDD

DSI

L PH3 PH2 PH5 PF4 PB2 VDD PE12 PE15 VDD PD8 PD10 PD14 PD15

M PC0 PH4 PA5 PF13 PF11 PF15 PG1 PB10 VSS PD9 PD11 PD13 PD12

N PC1 PA4 PA6 PB0 PF12 PG0 PE7 PB11 VCAP1 PB12 PB13 PB14 PB15

MSv35730V2

1. The above figure shows the package top view.

DS11118 Rev 7 51/220

Pinouts and pin description STM32F479xx

Figure 17. STM32F47x UFBGA176 ballout

1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5

P E 3 P E 2 PE 1 P E 0 P B 8 P B 5

P G 1 4 P G 1 3 PB 4 P B 3 P D 7 P C 1 2 P A 1 5 P A 1 4 P A 13

B P E 4 P E 5 PE6 P B 9 P B 7 P B 6 P G 1 5 P G 1 2 P G 1 1 P G 1 0 P D 6 P D 0 P C 1 1 P C 1 0 P A 1 2

VBAT

P C 13

P I7

PI8

P C 14 P F 0

P C 15 V S S

P I 6 P I 5 VDD

PDR

_ON

VDD VDD VDD P G 9 P D 5 P D 1 P I3 NC PA11

P I 9

PI10 P I1 1

V D D

P I 4

P H 2

VSS BOOT0 V S S V S S

VSS VSS VSS

V S S P D 4 P D 3 P D 2

DSI

HOST_

D1P

VDD12

DSI

HOST_

D1N

PI1

P I0

VSS VSS V SS VCAP2 P C 9

PA10

PA 9

PA 8

P H 0 V S S

PH1 P F 2

NRST P F 3

P F 7

P F 6

P F 1 0

PF9

V S S A P C 0

V R E F -

PA1

V DD P H 3

VSS VSS VSS VSS VSS

V SS V D D P C 8 P C 7

PF1

P F4

P H 4

P H 5

VSS

DSI

VDD

DSI

VDD_

USB

P G 8

VDD P G 7

P C 6

P G 6

PF5

PF8

PC1

PA0

V DD

BYPASS

_REG

P C 2 P C 3

VSS

PB2

P A 4 P C 4

PF13

VSS

PG1

VSS

P G 0 V DD

VSS VSS

VSS

VCAP

V DD V DD

VCAP

DSI P G 5 P G 4 P G 3

P H 6

DSI

HOST_

CKP

DSI

HOST_

D0P

DSI

HOST_

CKN

DSI

HOST_

D0N

PD15

PD14

P G 2

PD13

PE13 P H 7 P D 1 2 P D 1 1 P D 10

VREF+ P A 2 PA6 P A 5 P C 5 PF12 P F 1 5 PE 8 PE 9 P E 1 1 PE14 PB 1 2 P B 1 3 P D 9 P D 8

PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 P B 1 1 P B 14 P B 15

VDDA PA3 PA7

MS39400V2

1. The above figure shows the package top view.

52/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

Figure 18. STM32F47x LQFP176 pinout

VSS

VDD

PF6

PF7

PF8

PF9

PF10

PH0

PH1

NRST

PC0

PC1

PC2

PC3

VDD

VSSA

VREF+

VDDA

PA0

PA1

PA2

PH2

PH3

VSS

VDD

PF0

PF1

PF2

PF3

PF4

PF5

PE2

PE3

PE4

PE5

PE6

VBAT

PI8

PC13

PC14

PC15

PI9

PI10

PI11

LQFP176

1. The above figure shows the package top view.

107

106

105

104

103

102

101

100

118

117

116

115

114

113

112

111

110

109

108

124

123

122

121

120

119

132

131

130

129

128

127

126

125

PI0

VDD

VSS

VCAP2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

VDDUSB

VSS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

VSSDSI

DSIHOST_D1N

DSIHOST_D1P

VDD12DSI

DSIHOST_CKN

DSIHOST_CKP

VSSDSI

DSIHOST_D0N

DSIHOST_D0P

VCAPDSI

VDDDSI

PD15

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

MS33870V4

DS11118 Rev 7 53/220

Pinouts and pin description

Figure 19. STM32F47x LQFP208 pinout

STM32F479xx

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

PF10

PH0

PH1

PC15

PI9

PI10

PI11

VSS

VDD

PF0

PF1

PF2

PI12

PI13

PI14

PE2

PE3

PE4

PE5

PE6

VBAT

PI8

PC13

PC14

NRST

PC0

PC1

PC2

PC3

VDD

VSSA

VREF+

VDDA

PA0

PA1

PA2

PH2

PH3

PH4

PH5

PA3

VSS

VDD

LQFP208

PI2

PI1

PI0

PH15

PH14

PH13

VDD

VSS

VCAP2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PD14

VDD

VSS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PC8

PC7

PC6

VDDUSB

VSS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

VSSDSI

DSIHOST_D1N

DSIHOST_D1P

VDD12DSI

DSIHOST_CKN

DSIHOST_CKP

VSSDSI

DSIHOST_D0N

DSIHOST_D0P

VCAPDSI

VDDDSI

PD15

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

135

134

133

132

131

130

129

128

127

126

125

124

147

146

145

144

143

142

141

140

139

138

137

136

156

155

154

153

152

151

150

149

148

MSv33876V5

1. The above figure shows the package top view.

54/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

PE4

PE3

3 4

PE2 PG14 PE1

Figure 20. STM32F47x TFBGA216 ballout

6 7 8 9 10 11 12

PE0 PB8 PB5 PB4 PB3

13 14 15

PD7 PC12 PA15 PA14 PA13

PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 PD6 PD0 PC11 PC10 PA12

C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 PD5 PD3 PD1

PI3 PI2 PA11

D PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 PJ15 PD4 PD2 PH15 PI1 PA10

PC14

PC15 VSS

PH0

PH1

NRST PF4 PH5

PF7

PF1

PF2

PF3

PF6

PI12

PI11

PI13

PI14

PF5

PI9

VDD

PI15

PH4

PH3

PH2

PDR

BOOT0 VDD

VDD

VSS

VDD

VSS

VDD

VSS

VDD VCAP2 PH13 PH14 PI0 PA9

VSS VDD

DSI

HOST_

D1P

DSI

HOST_

D1N

PC9

VSS

VDDD

USB

VDD

DSI

VDD

VSS

DSI

VDD12

DSI

HOST_

CKP

DSI

HOST_

CKN

DSI

HOST_

D0P

DSI

HOST_

D0N

PC8

PG8

PG7

VSS VDD

VCAP

DSI

PD15

PB13

PA8

PC7

PC6

PG6

PD10

PF10 PF9 PF8 PC3

BYPASS-

REG

VSS VDD VDD VDD VDD VCAP1 PD14 PB12 PD9 PD8

M VSSA PC0 PC1 PC2 PB2 PF12 PG1 PF15 PJ4 PD12 PD13 PG3 PG2 PJ5 PH12

VREFPA1 PA0 PA4 PC4 PF13 PG0 PJ3 PE8 PD11 PG5 PG4 PH7 PH9 PH11

P VREF+ PA2 PA6 PA5 PC5 PF14 PJ2 PF11 PE9 PE11 PE14 PB10 PH6 PH8 PH10

VDDA PA3 PA7 PB1 PB0 PJ0 PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15

MSv33871V4

1. The above figure shows the package top view.

DS11118 Rev 7 55/220

Pinouts and pin description STM32F479xx

Name

Pin name

Pin type

I/O structure

Table 9. Legend/abbreviations used in the pinout table

Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Supply pin

Input only pin

I/O

TTa

RST

Input / output pin

5 V tolerant I/O

3.3 V tolerant I/O directly connected to analog parts

Dedicated BOOT0 pin

Bidirectional reset pin with weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Notes

Alternate functions

Additional functions

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

56/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

Pin number

Table 10. STM32F479xx pin and ball definitions

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

(2)

144

E5 C12 C1

E2 G9 D3 11 11 E4

E10

C11

B12

D11

D12

E11

E12

F10

F11

F12

G11

PE2

PE3

PE4

PE5

PE6

VSS

VDD

VBAT

PI8

PC13

PC14-OSC32_IN

(PC14)

PC15-

OSC32_OUT

(PC15)

VDD

I/O

(3)

(4)

TRACECLK, SPI4_SCK,

SAI1_MCLK_A,

QUADSPI_BK1_IO2,

ETH_MII_TXD3, FMC_A23,

EVENTOUT

TRACED0, SAI1_SD_B,

FMC_A19, EVENTOUT

TRACED1, SPI4_NSS,

SAI1_FS_A, FMC_A20,

DCMI_D4, LCD_B0,

EVENTOUT

TRACED2, TIM9_CH1,

SPI4_MISO, SAI1_SCK_A,

FMC_A21, DCMI_D6,

LCD_G0, EVENTOUT

TRACED3, TIM9_CH2,

SPI4_MOSI, SAI1_SD_A,

FMC_A22, DCMI_D7,

LCD_G1, EVENTOUT

EVENTOUT

RTC_TAMP1/

RTC_TAMP2/

RTC_TS

RTC_TAMP1/

RTC_TS/

RTC_OUT

I/O FT

EVENTOUT OSC32_IN

I/O

EVENTOUT OSC32_OUT

PI9

PI10

PI11

VSS

VDD

I/O

CAN1_RX, FMC_D30,

LCD_VSYNC, EVENTOUT

ETH_MII_RX_ER,

FMC_D31, LCD_HSYNC,

EVENTOUT

LCD_G6,

OTG_HS_ULPI_DIR,

EVENTOUT

DS11118 Rev 7 57/220

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

STM32F479xx

Additional functions

G10

H10

G12

H11

J10

H12

J11

J12

K10

K11

K12

12 21 M1 J9 M2 32 35 M2

PF0

PF1

PF2

PI12

PI13

PI14

PF3

PF4

PF5

VSS

VDD

PF6

PF7

PF8

PF9

PF10

I/O

I/O FT

PH0-OSC_IN

(PH0)

PH1-OSC_OUT

(PH1)

NRST

I/O FT -

I/O RST -

I2C2_SDA, FMC_A0,

EVENTOUT

I2C2_SCL, FMC_A1,

EVENTOUT

I2C2_SMBA, FMC_A2,

EVENTOUT

LCD_HSYNC, EVENTOUT

LCD_VSYNC, EVENTOUT

(5)

LCD_CLK, EVENTOUT

FMC_A3, EVENTOUT

FMC_A4, EVENTOUT

FMC_A5, EVENTOUT

(5)

TIM10_CH1, SPI5_NSS,

SAI1_SD_B, UART7_Rx,

QUADSPI_BK1_IO3,

EVENTOUT

(5)

TIM11_CH1, SPI5_SCK,

SAI1_MCLK_B, UART7_Tx,

QUADSPI_BK1_IO2,

EVENTOUT

SPI5_MISO, SAI1_SCK_B,

TIM13_CH1,

QUADSPI_BK1_IO0,

EVENTOUT

SPI5_MOSI, SAI1_FS_B,

TIM14_CH1,

QUADSPI_BK1_IO1,

EVENTOUT

QUADSPI_CLK,

DCMI_D11, LCD_DE,

EVENTOUT

ADC3_IN9

ADC3_IN14

ADC3_IN15

ADC3_IN4

ADC3_IN5

ADC3_IN6

ADC3_IN7

ADC3_IN8

EVENTOUT

OSC_IN

OSC_OUT

PC0 I/O FT (5)

OTG_HS_ULPI_STP,

FMC_SDNWE, LCD_R5,

EVENTOUT

ADC123_

IN10

58/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

L12

M12

L10

M11

N12

M2 M10

16 26 J2 L11 M1 37 40 M1

PC1

PC2

PC3

VDD

VSS

VSSA

VREF-

VREF+

VDDA

PA1

PA2

PH2

PH3

PH4

I/O

PA0-WKUP(PA0) I/O

I/O

(5)

TRACED0,

SPI2_MOSI/I2S2_SD,

SAI1_SD_A, ETH_MDC,

EVENTOUT

SPI2_MISO, I2S2ext_SD,

OTG_HS_ULPI_DIR,

ETH_MII_TXD2,

FMC_SDNE0, EVENTOUT

ADC123_

IN11

ADC123_

IN12

(5)

SPI2_MOSI/I2S2_SD,

OTG_HS_ULPI_NXT,

ETH_MII_TX_CLK,

FMC_SDCKE0,

EVENTOUT

ADC123_

IN13

(6)

TIM2_CH1/TIM2_ETR,

TIM5_CH1, TIM8_ETR,

USART2_CTS, UART4_TX,

ETH_MII_CRS,

EVENTOUT

ADC123_IN0,

WKUP

(5)

TIM2_CH2, TIM5_CH2,

USART2_RTS, UART4_RX,

QUADSPI_BK1_IO3,

ETH_MII_RX_CLK/ETH_R

MII_REF_CLK, LCD_R2,

EVENTOUT

ADC123_IN1

(5)

TIM2_CH3, TIM5_CH3,

TIM9_CH1, USART2_TX,

ETH_MDIO, LCD_R1,

EVENTOUT

QUADSPI_BK2_IO0,

ETH_MII_CRS,

FMC_SDCKE0, LCD_R0,

EVENTOUT

QUADSPI_BK2_IO1,

ETH_MII_COL,

FMC_SDNE0, LCD_R1,

EVENTOUT

I2C2_SCL, LCD_G5,

OTG_HS_ULPI_NXT,

LCD_G4, EVENTOUT

ADC123_IN2

DS11118 Rev 7 59/220

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

STM32F479xx

Additional functions

N2 M9 N4 50 53 N4

26 36 M3 L8 P4 51 54 P4

27 37 N3 P11 P3 52 55 P3

23 33 J1 N11 -

24 34 J4 P12 K4 49 52 K5

N10

P10

P5 55 58 P5

PH5

PA3

VSS

BYPASS_REG

VDD

PA4

PA5

PA6

PA7

PC4

PC5

VDD

VSS

PB0

I/O

(5)

I2C2_SDA, SPI5_NSS,

FMC_SDNWE, EVENTOUT

TIM2_CH4, TIM5_CH4,

TIM9_CH2, USART2_RX,

LCD_B2,

OTG_HS_ULPI_D0,

ETH_MII_COL, LCD_B5,

EVENTOUT

I/O TTa -

SPI1_NSS,

SPI3_NSS/I2S3_WS,

USART2_CK,

OTG_HS_SOF,

DCMI_HSYNC,

LCD_VSYNC, EVENTOUT

I/O

TTa

(5)

TIM2_CH1/TIM2_ETR,

TIM8_CH1N, SPI1_SCK,

OTG_HS_ULPI_CK,

LCD_R4, EVENTOUT

TIM1_BKIN, TIM3_CH1,

TIM8_BKIN, SPI1_MISO,

TIM13_CH1,

DCMI_PIXCLK, LCD_G2,

EVENTOUT

(5)

TIM1_CH1N, TIM3_CH2,

TIM8_CH1N, SPI1_MOSI,

TIM14_CH1,

QUADSPI_CLK,

ETH_MII_RX_DV/ETH_RMI

I_CRS_DV, FMC_SDNWE,

EVENTOUT

I/O

(5)

ETH_MII_RXD0/ETH_RMII

_RXD0, FMC_SDNE0,

EVENTOUT

ETH_MII_RXD1/ETH_RMII

_RXD1, FMC_SDCKE0,

EVENTOUT

TIM1_CH2N, TIM3_CH3,

TIM8_CH2N, LCD_R3,

OTG_HS_ULPI_D1,

ETH_MII_RXD2, LCD_G1,

EVENTOUT

ADC123_IN3

ADC12_IN4,

DAC_OUT1

ADC12_IN5,

DAC_OUT2

ADC12_IN6

ADC12_IN7

ADC12_IN14

ADC12_IN15

ADC12_IN8

60/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

30 42 K5 N9 R4 57 62 R4

31 43 L5 P9 M6 58 63 M5

64 G4

68 N8

69 M9

44 M5 K7 R6 59 70 P8

45 N5 M8 P6 60 71 M6

J6 N8 M8 61 72 K7

46 K6 P8 N8 62 73 L8

47 M4 J7 N6 63 74 N6

48 H5 L7 R7 64 75 P6

49 M6 H8 P7 65 76 M8

50 N6 J6 N7 66 77 N7

51 M7 P7 M7 67 78 M7

32 52 N7 N7 R8 68 79 R8

33 53 G6 M7 P8 69 80 N9

34 54 H6 K6 P9 70 81 P9

55 J7

56 L6

M9 71 82 K8

N9 72 83 L9

35 57 H7 P6 R9 73 84 R9

DS11118 Rev 7 61/220

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

STM32F479xx

Additional functions

36 58 K7 N6 P10 74 85 P10

37 59 L7 M6 R10 75 86 R10

38 60 J8 L6 N11 76 87 R12

39 61 K8 J5 P11 77 88 P11

40 62 L8 P5 R11 78 89 R11

41 63 M8 N5 R12 79 90 P12

42 64 N8 K5 R13 80 91 R13

43 65 N9 N4 M10 81 92 L11

44 M9 P4 93 K9

45 66 L9 P3 N10 82 94 L10

95 M14

M11 83 96 P13

N12 84 97 N13

H8 M5 98 P14

H9 L5 99 N14

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VCAP1

VSS

VDD

PJ5

PH6

PH7

PH8

PH9

I/O FT -

S -

I/O FT -

TIM1_CH2, SPI4_NSS,

FMC_D8, LCD_G3,

EVENTOUT

TIM1_CH3N, SPI4_SCK,

FMC_D9, LCD_B4,

EVENTOUT

TIM1_CH3, SPI4_MISO,

FMC_D10, LCD_DE,

EVENTOUT

TIM1_CH4, SPI4_MOSI,

FMC_D11, LCD_CLK,

EVENTOUT

TIM1_BKIN, FMC_D12,

LCD_R7, EVENTOUT

TIM2_CH3, I2C2_SCL,

SPI2_SCK/I2S2_CK,

USART3_TX,

QUADSPI_BK1_NCS,

OTG_HS_ULPI_D3,

ETH_MII_RX_ER, LCD_G4,

EVENTOUT

TIM2_CH4, I2C2_SDA,

USART3_RX,

OTG_HS_ULPI_D4,

ETH_MII_TX_EN/ETH_RMI

I_TX_EN, DSIHOST_TE,

LCD_G5, EVENTOUT

LCD_R6, EVENTOUT

I2C2_SMBA, SPI5_SCK,

TIM12_CH1,

ETH_MII_RXD2,

FMC_SDNE1, DCMI_D8,

EVENTOUT

I2C3_SCL, SPI5_MISO,

ETH_MII_RXD3,

FMC_SDCKE1, DCMI_D9,

EVENTOUT

I2C3_SDA, FMC_D16,

DCMI_HSYNC, LCD_R2,

EVENTOUT

I2C3_SMBA, TIM12_CH2,

FMC_D17, DCMI_D0,

LCD_R3, EVENTOUT

62/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

J9 M4 100 P15

K9 N3 101 N15

H10 P2 -

102 M15

K10

103 K11

46 67 N10 H5 P12 85 104 L13

47 68 N11 K4 P13 86 105 K14

48 69 N12 P1 R14 87 106 R14

49 70 N13 N2 R15 88 107 R15

50 71 L10 L4 P15 89 108 L15

51 72 M10 N1 P14 90 109 L14

52 73 L11 M3 N15 91 110 K15

74 M11 J4 N14 92 111 N10

PH10

PH11

PH12

VSS

VDD

PB12

PB13

PB14

PB15

PD8

PD9

PD10

PD11

I/O FT -

TIM5_CH1, FMC_D18,

DCMI_D1, LCD_R4,

EVENTOUT

TIM5_CH2, FMC_D19,

DCMI_D2, LCD_R5,

EVENTOUT

TIM5_CH3, FMC_D20,

DCMI_D3, LCD_R6,

EVENTOUT

TIM1_BKIN, I2C2_SMBA,

SPI2_NSS/I2S2_WS,

USART3_CK, CAN2_RX,

OTG_HS_ULPI_D5,

ETH_MII_TXD0/ETH_RMII

_TXD0, OTG_HS_ID,

EVENTOUT

TIM1_CH1N,

SPI2_SCK/I2S2_CK,

USART3_CTS, CAN2_TX,

OTG_HS_ULPI_D6,

ETH_MII_TXD1/ETH_RMII

_TXD1, EVENTOUT

TIM1_CH2N, TIM8_CH2N,

SPI2_MISO, I2S2ext_SD,

USART3_RTS,

TIM12_CH1, OTG_HS_DM,

EVENTOUT

RTC_REFIN, TIM1_CH3N,

TIM8_CH3N,

SPI2_MOSI/I2S2_SD,

TIM12_CH2, OTG_HS_DP,

EVENTOUT

USART3_TX, FMC_D13,

EVENTOUT

USART3_RX, FMC_D14,

EVENTOUT

USART3_CK, FMC_D15,

LCD_B3, EVENTOUT

USART3_CTS,

QUADSPI_BK1_IO0,

FMC_A16/FMC_CLE,

EVENTOUT

OTG_HS_

VBUS

DS11118 Rev 7 63/220

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

STM32F479xx

Additional functions

M13 M2

M12

J10

K10

L12

L13

N13

M15

J13

M14

L14

112 M10

113 M11

114 J10

115 J11

116 L12

117 K13

PD12

PD13

VSS

VDD

PD14

PD15

I/O

55 80 K13 L1 J12 99 118 H11

H10

56 81 K12 K1 K12 100 119 K12

K2 D13 G13

VDDDSI

VSS

VCAPDSI

VDD12DSI

57 82 J12 K3 M12 101 120 J12 DSIHOST_D0P I/O

58 83 J13 J3 M13 102 121 J13 DSIHOST_D0N I/O

59 84 K11 H1 H12 103 122 G12 VSSDSI S

60 85 H12 J1 L12 104 123 H12 DSIHOST_CKP I/O

61 86 H13 J2 L13 105 124 H13 DSIHOST_CKN I/O

62 87 J11 D13 106 125 VDD12DSI S

63 88 G12 H3 E12 107 126 F12 DSIHOST_D1P I/O

64 89 G13 H2 E13 108 127 F13 DSIHOST_D1N I/O

H11

F13

F12

H12 109 128 -

L15 110 129 M13

K15 111 130 M12

VSSDSI

PG2

PG3

S -

I/O FT -

E13

E12

F11

E11

K14 112 131 N12

K13 113 132 N11

J15 114 133 J15

J14 115 134 J14

PG4

PG5

PG6

PG7

I/O

TIM4_CH1, USART3_RTS,

QUADSPI_BK1_IO1,

FMC_A17/FMC_ALE,

EVENTOUT

TIM4_CH2,

QUADSPI_BK1_IO3,

FMC_A18, EVENTOUT

TIM4_CH3, FMC_D0,

EVENTOUT

TIM4_CH4, FMC_D1,

EVENTOUT

FMC_A12, EVENTOUT

FMC_A13, EVENTOUT

FMC_A14/FMC_BA0,

EVENTOUT

FMC_A15/FMC_BA1,

EVENTOUT

DCMI_D12, LCD_R7,

EVENTOUT

SAI1_MCLK_A,

USART6_CK, FMC_INT,

DCMI_D13, LCD_CLK,

EVENTOUT

64/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

102

103

104

D13

G11

F10

100 E10

101 G10

105 A13

106 A12

H14 116 135 H14

G12 117 136 G10

H13 118 137 G11

H15 119 138 H15

G15 120 139 G15

G14 121 140 G14

F14 122 141 F14

F15 123 142 F15

E15 124 143 E15

D15 125 144 D15

C15 126 145 C15

B15 127 146 B15

PG8

VSS

VDDUSB

PC6

PC7

PC8

PC9

PA8

PA9

PA10

PA11

PA12

75 107 A11 D1 A15 128 147 A15

76 108 D12 D2 F13 129 148 E11

109 D11 C1 F12 130 149 F10

PA13(JTMS-

SWDIO)

VCAP2

VSS

I/O FT -

SPI6_NSS, USART6_RTS,

ETH_PPS_OUT,

FMC_SDCLK, LCD_G7,

EVENTOUT

TIM3_CH1, TIM8_CH1,

I2S2_MCK, USART6_TX,

SDIO_D6, DCMI_D0,

LCD_HSYNC, EVENTOUT

TIM3_CH2, TIM8_CH2,

I2S3_MCK, USART6_RX,

SDIO_D7, DCMI_D1,

LCD_G6, EVENTOUT

TRACED1, TIM3_CH3,

TIM8_CH3, USART6_CK,

SDIO_D0, DCMI_D2,

EVENTOUT

MCO2, TIM3_CH4,

TIM8_CH4, I2C3_SDA,

I2S_CKIN,

QUADSPI_BK1_IO0,

SDIO_D1, DCMI_D3,

EVENTOUT

MCO1, TIM1_CH1,

I2C3_SCL, USART1_CK,

OTG_FS_SOF, LCD_R6,

EVENTOUT

TIM1_CH2, I2C3_SMBA,

SPI2_SCK/I2S2_CK,

USART1_TX, DCMI_D0,

EVENTOUT

TIM1_CH3, USART1_RX,

OTG_FS_ID, DCMI_D1,

EVENTOUT

TIM1_CH4, USART1_CTS,

CAN1_RX, OTG_FS_DM,

LCD_R4, EVENTOUT

TIM1_ETR, USART1_RTS,

CAN1_TX, OTG_FS_DP,

LCD_R5, EVENTOUT

I/O FT JTMS-SWDIO, EVENTOUT

OTG_FS_

VBUS

DS11118 Rev 7 65/220

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

STM32F479xx

Additional functions

C13

C12

B12

156 C14

135 F9

136 158 E10

79 111 A10 D4 A14 137 159 A14

VSS

VDD

PA14(JTCK-

SWCLK)

110 D10

B13

C11

B10

112 B11

113 C10

114 B9

G13 131 150 F11

151 E12

152 E13

153 D13

E14 132 154 E14

D14 133 155 D14

C13 134 157 C13

A13 138 160 A13

B14 139 161 B14

B13 140 162 B13

VDD

PH13

PH14

PH15

PI0

PI1

PI2

PI3

PA15(JTDI)

PC10

PC11

I/O

TIM8_CH1N, CAN1_TX,

FMC_D21, LCD_G2,

EVENTOUT

TIM8_CH2N, FMC_D22,

DCMI_D4, LCD_G3,

EVENTOUT

TIM8_CH3N, FMC_D23,

DCMI_D11, LCD_G4,

EVENTOUT

TIM5_CH4,

SPI2_NSS/I2S2_WS (7) ,

FMC_D24, DCMI_D13,

LCD_G5, EVENTOUT

SPI2_SCK/I2S2_CK

(7)

FMC_D25, DCMI_D8,

LCD_G6, EVENTOUT

TIM8_CH4, SPI2_MISO,

I2S2ext_SD, FMC_D26,

DCMI_D9, LCD_G7,

EVENTOUT

TIM8_ETR,

SPI2_MOSI/I2S2_SD,

FMC_D27, DCMI_D10,

EVENTOUT

I/O FT JTCK-SWCLK, EVENTOUT

I/O FT -

JTDI,

TIM2_CH1/TIM2_ETR,

SPI1_NSS,

SPI3_NSS/I2S3_WS,

EVENTOUT

SPI3_SCK/I2S3_CK,

USART3_TX, UART4_TX,

QUADSPI_BK1_IO1,

SDIO_D2, DCMI_D8,

LCD_R2, EVENTOUT

I2S3ext_SD, SPI3_MISO,

USART3_RX, UART4_RX,

QUADSPI_BK2_NCS,

SDIO_D3, DCMI_D4,

EVENTOUT

66/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

83 115 A9 C4 A12 141 163 A12

84 116 C9 E6 B12 142 164 B12

85 117 C7 A3 C12 143 165 C12

86 118 B8 C5 D12 144 166 D12

87 119 C8 D6 D11 145 167 C11

88 120 C6 B4 D10 146 168 D11

89 121 B7 C6 C11 147 169 C10

122 F8 A4 D8 148 170 F8

123 F7 C8 149 171 E9

90 124 D7 E7 B11 150 172 B11

91 A8 A5 A11 151 173 A11

174 B10

175 B9

176 C9

177 D10

125 E6 D7 C10 152 178 D9

126 E7 C7 B10 153 179 C8

127 B6 B6 B9 154 180 B8

PC12

PD0

PD1

PD2

PD3

PD6

PD7

PJ12

PJ13

PJ14

PJ15

PD4

PD5

VSS

VDD

PG9

PG10

PG11

I/O

I/O FT -

I/O

I/O FT -

TRACED3,

SPI3_MOSI/I2S3_SD,

USART3_CK, UART5_TX,

SDIO_CK, DCMI_D9,

EVENTOUT

CAN1_RX, FMC_D2,

EVENTOUT

CAN1_TX, FMC_D3,

EVENTOUT

TRACED2, TIM3_ETR,

UART5_RX, SDIO_CMD,

DCMI_D11, EVENTOUT

SPI2_SCK/I2S2_CK,

USART2_CTS, FMC_CLK,

DCMI_D5, LCD_G7,

EVENTOUT

USART2_RTS, FMC_NOE,

EVENTOUT

USART2_TX, FMC_NWE,

EVENTOUT

SPI3_MOSI/I2S3_SD,

SAI1_SD_A, USART2_RX,

FMC_NWAIT, DCMI_D10,

LCD_B2, EVENTOUT

USART2_CK, FMC_NE1,

EVENTOUT

LCD_G3, LCD_B0,

EVENTOUT

LCD_G4, LCD_B1,

EVENTOUT

LCD_B2, EVENTOUT

LCD_B3, EVENTOUT

USART6_RX,

QUADSPI_BK2_IO2,

FMC_NE2/FMC_NCE,

DCMI_VSYNC, EVENTOUT

LCD_G3, FMC_NE3,

DCMI_D2, LCD_B2,

EVENTOUT

ETH_MII_TX_EN/ETH_RMI

I_TX_EN, DCMI_D3,

LCD_B3, EVENTOUT

DS11118 Rev 7 67/220

Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

STM32F479xx

Additional functions

129 -

130 -

B7 D7 158 184 F7

A7 C7 159 185 E8

186

187

188

189

190

92 132 B5 A8 A10 161 192 A10

128

131

133

134

135

155 181

156 182

157 183

160 191

162 193

163 194

164 195

PG12

PG13

PG14

VSS

VDD

PK3

PK4

PK5

PK6

PK7

PG15

PB3(JTDO/TRA

CESWO)

PB4(NJTRST)

PB5

PB6

I/O

I/O FT -

I/O

I/O FT -

I/O

SPI6_MISO,

USART6_RTS, LCD_B4,

FMC_NE4, LCD_B1,

EVENTOUT

TRACED0, SPI6_SCK,

USART6_CTS,

ETH_MII_TXD0/ETH_RMII

_TXD0, FMC_A24,

LCD_R0, EVENTOUT

TRACED1, SPI6_MOSI,

USART6_TX,

QUADSPI_BK2_IO3,

ETH_MII_TXD1/ETH_RMII

_TXD1, FMC_A25,

LCD_B0, EVENTOUT

LCD_B4, EVENTOUT

LCD_B5, EVENTOUT

LCD_B6, EVENTOUT

LCD_B7, EVENTOUT

LCD_DE, EVENTOUT

USART6_CTS,

FMC_SDNCAS,

DCMI_D13, EVENTOUT

JTDO/TRACESWO,

TIM2_CH2, SPI1_SCK,

SPI3_SCK/I2S3_CK,

EVENTOUT

NJTRST, TIM3_CH1,

SPI1_MISO, SPI3_MISO,

I2S3ext_SD, EVENTOUT

TIM3_CH2, I2C1_SMBA,

SPI1_MOSI,

SPI3_MOSI/I2S3_SD,

CAN2_RX,

OTG_HS_ULPI_D7,

ETH_PPS_OUT,

FMC_SDCKE1, DCMI_D10,

LCD_G7, EVENTOUT

TIM4_CH1, I2C1_SCL,

USART1_TX, CAN2_TX,

QUADSPI_BK1_NCS,

FMC_SDNE1, DCMI_D5,

EVENTOUT

68/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

Table 10. STM32F479xx pin and ball definitions (continued)

Pin number

Pin name

(function after reset)

(1)

Alternate functions

Additional functions

1. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.19

136

137

138

139

140

141

142

100 143

A10

B10

A11

D10

C10

B11

A12

165 196

166 197

167 198

168 199

169 200

170 201

202

171 203

172 204

173 205

174 206

175 207

176 208

PB7

BOOT0

PB8

PB9

PE0

PE1

VSS

PDR_ON

VDD

PI4

PI5

PI6

PI7

I/O

TIM4_CH2, I2C1_SDA,

USART1_RX, FMC_NL,

DCMI_VSYNC, EVENTOUT

TIM4_CH3, TIM10_CH1,

I2C1_SCL, CAN1_RX,

ETH_MII_TXD3, SDIO_D4,

DCMI_D6, LCD_B6,

EVENTOUT

TIM4_CH4, TIM11_CH1,

I2C1_SDA,

SPI2_NSS/I2S2_WS,

CAN1_TX, SDIO_D5,

DCMI_D7, LCD_B7,

EVENTOUT

TIM4_ETR, UART8_Rx,

FMC_NBL0, DCMI_D2,

EVENTOUT

UART8_Tx, FMC_NBL1,

DCMI_D3, EVENTOUT

TIM8_BKIN, FMC_NBL2,

DCMI_D5, LCD_B4,

EVENTOUT

TIM8_CH1, FMC_NBL3,

DCMI_VSYNC, LCD_B5,

EVENTOUT

TIM8_CH2, FMC_D28,

DCMI_D6, LCD_B6,

EVENTOUT

TIM8_CH3, FMC_D29,

DCMI_D7, LCD_B7,

EVENTOUT

VPP

1. Function availability depends on the chosen device.

2. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to “0” in the output data register to avoid extra current consumption in low power modes.

3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF.

- These I/Os must not be used as a current source (e.g. to drive an LED).

4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from www.st.com

5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

DS11118 Rev 7 69/220

Pinouts and pin description STM32F479xx

6. If the device is delivered in an WLCSP168, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the

BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low).

7. PI0 and PI1 cannot be used for I2S2 full-duplex mode.

70/220 DS11118 Rev 7

STM32F479xx Pinouts and pin description

A20

A21

A22

A23

A24

A25

A14

A15

A16

A17

A18

A19

A10

A11

A12

A13

Table 11. FMC pin definition

Pin name NOR/PSRAM/SRAM NOR/PSRAM Mux NAND16

PE4

PE5

PE6

PE2

PG13

PG14

PG4

PG5

PD11

PD12

PD13

PE3

PF14

PF15

PG0

PG1

PG2

PG3

PF0

PF1

PF2

PF3

PF4

PF5

PF12

PF13

PD14

PD15

PD0

PD1

PE7

PE8

PE9

PE10

PE11

A20

A21

A22

A23

A24

A25

A16

A17

A18

A19

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

DA8

CLE

ALE

BA0

BA1

SDRAM

A10

A11

A12

DS11118 Rev 7 71/220

Pinouts and pin description

NE2

NE3

NE4

CLK

NOE

D27

D28

D29

D30

D31

NE1

NWE

NWAIT

NADV

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D13

D14

D15

D16

D10

D11

D12

Table 11. FMC pin definition (continued)

Pin name NOR/PSRAM/SRAM NOR/PSRAM Mux NAND16

PG9

PG10

PG11

PG12

PD3

PD4

PI3

PI6

PI7

PI9

PI10

PD7

PD5

PD6

PB7

PF6

PF7

PH9

PH10

PH11

PH12

PH13

PH14

PH15

PI0

PI1

PI2

PE12

PE13

PE14

PE15

PD8

PD9

PD10

PH8

NE2

NE3

NE4

CLK

NOE

NE1

DA9

DA10

DA11

DA12

DA13

DA14

DA15

NWE

NWAIT

NADV

NCE

NOE

NWE

NWAIT

D13

D14

D15

D10

D11

D12

72/220 DS11118 Rev 7

STM32F479xx

SDRAM

D27

D28

D29

D30

D31

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D13

D14

D15

D16

D10

D11

D12

STM32F479xx Pinouts and pin description

Table 11. FMC pin definition (continued)

Pin name NOR/PSRAM/SRAM NOR/PSRAM Mux NAND16

NBL3

NBL0

NBL1

NBL2

PI5

PG8

PC0

PF11

PG15

PH2

PH3

PF8

PF9

PF10

PG6

PG7

PE0

PE1

PI4

PH6

PH7

PH5

PC2

PC3

PB5

PB6

NBL0

NBL1

INT

SDRAM

NBL3

SDCLK

SDNWE

SDNRAS

SDNCAS

SDCKE0

SDNE0

NBL0

NBL1

NBL2

SDNE1

SDCKE1

SDNWE

SDNE0

SDCKE0

SDCKE1

SDNE1

DS11118 Rev 7 73/220

AF0 AF1 AF2 AF3 AF4

Table 12. Alternate function

AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port

PA0

PA1

PA2

PA3

PA4

PA5

PA6

Port

PA7

PA8

PA9

PA10

PA11

PA12

SYS

MCO1

PA13

PA14

JTMS-

SWDIO

JTCK-

SWCLK

TIM1/2

TIM2_CH1/

TIM2_ETR

TIM1_BKIN TIM3_CH1

TIM8_BKI

TIM1_

CH1N

TIM1_CH1

TIM1_CH2

TIM1_CH3

TIM1_CH4

TIM1_ETR

TIM3/4/

TIM2_CH1/

TIM2_ETR

TIM5_CH1 TIM8_ETR

TIM2_CH2 TIM5_CH2

TIM3_CH2

TIM8_CH1

TIM8/9/

10/11

I2C1/2/3

TIM8_CH1

TIM2_CH3 TIM5_CH3 TIM9_CH1

TIM2_CH4 TIM5_CH4 TIM9_CH2

I2C3_SCL

I2C3_SMBA

SPI2_SCK/I

2S2_CK

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

SPI2/3/

USART

1/2/3

USART2_

CTS

USAR

T6/

UART

4/5/7/

UART4_

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

QUAD

SPI/OT

G2_HS

/OTG1

_FS

ETH

ETH_MII_CRS

USART2_

RTS

UART4_

QUADSPI_

BK1_IO3

ETH_MII_RX_

CLK/ETH_RMI

I_REF_CLK

SPI1_NSS

USART2_T

USART2_

SPI3_NSS/

I2S3_WS

USART2_

LCD_B2

OTG_HS

_ULPI_D0

ETH_MII_COL

ETH_MDIO

FMC/

SDIO/

OTG2_

DCMI/

DSI

HOST

OTG_HS_S

DCMI_HS

YNC

SPI1_SCK

OTG_HS

_ULPI_C

SPI1_

MISO

TIM13_CH1 -

DCMI_PIX

CLK

SPI1_

MOSI

TIM14_CH1

QUADSPI

_CLK

ETH_MII_RX_

DV/ETH_RMII

_CRS_DV

OTG_FS_

SOF

FMC_SDN

USART1_

USART1_T

USART1_

CTS

USART1_

RTS

CAN1_RX

CAN1_TX

OTG_FS_

DCMI_D0

DCMI_D1

LCD

LCD_R2

LCD_R1

LCD_B5

LCD_VSY

LCD_R4

LCD_G2

LCD_R6

LCD_R4

LCD_R5

PA15 JTDI

TIM2_CH1/

TIM2_ETR

SPI1_NSS

SPI3_NSS/

I2S3_WS

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

‘OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

AF0 AF1 AF2 AF3 AF4

Table 12. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14

Port

PB6

PB7

Port

PB8

SYS

TIM1/2

TIM3/4/

TIM8/9/

10/11

I2C1/2/3

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

PB0

PB1

PB2

TIM1_CH2N TIM3_CH3

TIM1_CH3N TIM3_CH4

TIM8_CH2

TIM8_CH3

PB3

JTDO /

TRACES

TIM2_CH2

PB4 NJTRST

TIM3_CH1

PB5

TIM3_CH2

SPI1_SCK

SPI3_SCK/

I2S3_CK

SPI1_MISO

SPI3_MIS

I2C1_SMBA SPI1_MOSI

SPI3_MOS

I/I2S3_SD

TIM4_CH1

TIM4_CH2

I2C1_SCL

I2C1_SDA

SPI2/3/

USART

1/2/3

USAR

T6/

UART

4/5/7/

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

LCD_R3

LCD_R6

QUAD

SPI/OT

G2_HS

/OTG1

_FS

OTG_HS

_ULPI_D1

OTG_HS

_ULPI_D2

I2S3ext

_SD

USART1

_TX

USART1_

CAN2_RX

CAN2_TX

CAN1_RX

OTG_HS

_ULPI_D7

QUADSPI

_BK1_NC

PB9

PB10

TIM2_CH3

TIM4_CH3

TIM4_CH4

TIM10_CH

TIM11_CH

I2C1_SCL

I2C1_SDA

I2C2_SCL

SPI2_NSS/I

2S2_WS

SPI2_SCK/I

2S2_CK

USART3

_TX

CAN1_TX

PB11

PB12

PB13

PB14

TIM2_CH4

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

PB15

RTC

_REFIN

TIM1_CH3N

TIM8_CH2

TIM8_CH3

I2C2_SDA

I2C2_SMBA

SPI2_NSS/I

2S2_WS

SPI2_SCK/I

2S2_CK

SPI2_MISO

I2S2ext_S

SPI2_MOSI

/I2S2_SD

USART3

_RX

USART3

_CK

USART3

_CTS

USART3

_RTS

ETH

ETH_MII_

RXD2

ETH_MII_

RXD3

ETH_MII_

TXD3

ETH_PPS

OUT

FMC/

SDIO/

OTG2_

FMC_

SDCKE1

FMC_

SDNE1

FMC_NL

SDIO_D4

SDIO_D5

DCMI/

DSI

HOST

DCMI_D10

DCMI_D5

DCMI_VS

YNC

DCMI_D6

DCMI_D7

QUADSPI_

BK1_NCS

CAN2_RX

CAN2_TX

OTG_HS

_ULPI_D3

ETH_MII_RX_

OTG_HS

_ULPI_D4

ETH_MII_TX_

EN/ETH_RMII

_TX_EN

OTG_HS

_ULPI_D5

ETH_MII_TXD

0/ETH_RMII_T

XD0

OTG_HS

_ULPI_D6

ETH_MII_TXD

1/ETH_RMII_T

XD1

OTG_HS_

TIM12_CH1

TIM12_CH2

OTG_HS_

‘DM

OTG_HS_

DSIHOST_

LCD

LCD_G1

LCD_G0

LCD_G7

LCD_B6

LCD_B7

LCD_G4

LCD_G5

AF15

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

‘OUT

Port

PC0

PC1

TRACE

PC2

PC3

PC4

PC5

PC10

AF0

SYS

PC6

Port

PC7

PC8

PC9

TRACE

MCO2

PC11 -

PC12

PC13

TRACE

PC14

PC15

AF1

TIM1/2

AF2 AF3 AF4

Table 12. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

TIM3/4/

TIM8/9/

10/11

I2C1/2/3

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

SPI2_MOSI

/I2S2_SD

SAI1_SD_

SPI2/3/

USART

1/2/3

USAR

T6/

UART

4/5/7/

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

QUAD

SPI/OT

G2_HS

/OTG1

_FS

OTG_HS

_ULPI_ST

SPI2_MISO

I2S2ext_S

SPI2_MOSI

/I2S2_SD

ETH

ETH_MDC

FMC/

SDIO/

OTG2_

FMC_SDN

OTG_HS

_ULPI_DI

OTG_HS

_ULPI_N

ETH_MII_TXD

ETH_MII_TX_

CLK

FMC_SDN

FMC_SDC

KE0

ETH_MII_RXD

0/ETH_RMII_R

XD0

ETH_MII_RXD

1/ETH_RMII_R

XD1

FMC_SDN

FMC_SDC

KE0

SDIO_D6 TIM3_CH1 TIM8_CH1

TIM3_CH2 TIM8_CH2

TIM3_CH3 TIM8_CH3

TIM3_CH4 TIM8_CH4 I2C3_SDA

I2S2_MCK

I2S_CKIN

I2S3_MCK

I2S3ext_SD

SPI3_SCK/

I2S3_CK

SPI3_MIS

SPI3_MOS

I/I2S3_SD

USART3_

USART6

_TX

USART6

_RX

USART6

_CK

UART4_

UART5_

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

QUADSPI_

BK2_NCS

SDIO_D7

SDIO_D0

SDIO_D1

SDIO_D2

SDIO_D3

SDIO_CK

DCMI/

DSI

HOST

LCD

DCMI_D0

LCD_HSY

DCMI_D1

DCMI_D2

DCMI_D3

DCMI_D8

DCMI_D4

DCMI_D9

LCD_R5

LCD_G6

LCD_R2

SYS

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

‘OUT

Port

AF0

SYS

PD0 -

PD1

PD2

PD3

TRACE

PD4

PD5

PD6

Port

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

AF1

TIM1/2

TIM3_ETR

AF2 AF3 AF4

Table 12. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF10

TIM3/4/

TIM8/9/

10/11

I2C1/2/3

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

SPI2/3/

USART

1/2/3

USAR

T6/

UART

4/5/7/

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

QUAD

SPI/OT

G2_HS

/OTG1

_FS

CAN1_RX -

TIM4_CH1

TIM4_CH2

TIM4_CH3

TIM4_CH4

CAN1_TX

SPI2_SCK/I

2S2_CK

SPI3_MOSI

/I2S3_SD

SAI1_SD_

USART2_

CTS

USART2_

RTS

USART2_T

USART2_

USART3_T

USART3_

CTS

USART3_

RTS

UART5_

QUADSPI_

BK1_IO0

QUADSPI_

BK1_IO1

QUADSPI_

BK1_IO3

AF11

ETH

AF12 AF13 AF14 AF15

FMC/

SDIO/

OTG2_

DCMI/

DSI

HOST

LCD SYS

FMC_D2

FMC_D3

SDIO_CMD

FMC_CLK DCMI_D5 LCD_G7

FMC_NOE

DCMI_D11

FMC_NWE

FMC_NWAI

DCMI_D10

FMC_NE1

FMC_D13

FMC_D14

FMC_D15

FMC_A16/F

MC_CLE

FMC_A17/F

MC_ALE

FMC_A18

FMC_D0

FMC_D1

LCD_B2

LCD_B3

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

‘OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

AF0 AF1 AF2 AF3 AF4

Table 12. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

Port

PE0

PE1

PE2

PE3

PE4

PE5

PE6

Port

PE7

PE8

PE9

PE10

PE11

SYS

TRACE

CLK

TRACE

TIM1/2

TIM1_ETR

TIM1_CH1N

TIM1_CH1

TIM1_CH2N

TIM1_CH2

TIM3/4/

TIM8/9/

10/11

I2C1/2/3

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

TIM4_ETR

SPI2/3/

USART

1/2/3

USAR

T6/

UART

4/5/7/

UART8_

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

QUADSPI_

BK1_IO2

QUAD

SPI/OT

G2_HS

/OTG1

_FS

ETH

ETH_MII_TXD

FMC/

SDIO/

OTG2_

DCMI/

DSI

HOST

FMC_NBL0 DCMI_D2

FMC_NBL1 DCMI_D3

FMC_A23

FMC_A19

TIM9_CH1

TIM9_CH2

SPI4_SCK

SPI4_NSS

SPI4_MISO

SPI4_MOSI

SAI1_

MCLK_A

SAI1

_SD_B

SAI1

_FS_A

SAI1

_SCK_A

SAI1

_SD_A

SPI4_NSS

UART7_

QUADSPI

_BK2_IO0

QUADSPI

_BK2_IO1

QUADSPI

_BK2_IO2

QUADSPI

_BK2_IO3

FMC_A20

FMC_A21

FMC_A22

FMC_D4

FMC_D5

FMC_D6

FMC_D7

FMC_D8

DCMI_D4

DCMI_D6

DCMI_D7

PE12

PE13

PE14

PE15

TIM1_CH3N

TIM1_CH3

TIM1_CH4

TIM1_BKIN

SPI4_SCK

SPI4_MISO

SPI4_MOSI

FMC_D9

FMC_D10

FMC_D11

FMC_D12

LCD SYS

LCD_B0

LCD_G0

LCD_G1

LCD_G3

LCD_B4

LCD_DE

LCD_CLK

LCD_R7

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

‘OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Port

PF4

PF5

PF6

Port

PF7

PF8

PF9

PF0

PF1

PF2

PF3

PF10

PF11

PF12

PF13

PF14

PF15 -

AF0

SYS

AF1

TIM1/2

AF2 AF3 AF4

Table 12. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF10

TIM3/4/

TIM8/9/

10/11

I2C1/2/3

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

I2C2_SDA -

SPI2/3/

USART

1/2/3

USAR

T6/

UART

4/5/7/

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

QUAD

SPI/OT

G2_HS

/OTG1

_FS

I2C2_SCL -

TIM10_CH

TIM11_CH

I2C2_SMBA

SPI5_NSS

SPI5_SCK

SPI5_MISO

SPI5_MOSI

SAI1_

SD_B

SAI1_

MCLK_B

SAI1_

SCK_B

SAI1_

FS_B

SPI5_MOSI -

UART7_

QUADSPI_

BK1_IO3

QUADSPI_

BK1_IO2

TIM13_CH1

QUADSPI

_BK1_IO0

TIM14_CH1

QUADSPI

_BK1_IO1

QUADSPI_

CLK

AF11

ETH

AF12 AF13 AF14 AF15

FMC/

SDIO/

OTG2_

DCMI/

DSI

HOST

LCD SYS

FMC_A0

FMC_A1

FMC_A2

FMC_A3

FMC_A4

FMC_A5

FMC_A7

FMC_A8

FMC_A9 -

FMC_SDN

RAS

DCMI_D12

FMC_A6

DCMI_D11 LCD_DE

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

‘OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Port

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

Port

PG8

PG9

PG10

PG11

PG12

PG15

AF0

SYS

PG13

TRACE

PG14

TRACE

AF1

TIM1/2

AF2 AF3 AF4

Table 12. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

TIM3/4/

TIM8/9/

10/11

I2C1/2/3

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

SPI2/3/

USART

1/2/3

USAR

T6/

UART

4/5/7/

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

QUAD

SPI/OT

G2_HS

/OTG1

_FS

SPI6_NSS

SAI1

_MCLK_A

SPI6_MISO

SPI6_SCK

SPI6_MOSI

USART6

_CK

USART6

_RTS

USART6

_RX

QUADSPI_

BK2_IO2

USART6

_RTS

USART6

_CTS

LCD_G3

LCD_B4

USART6

_TX

QUADSPI_

BK2_IO3

USART6

_CTS

ETH

FMC/

SDIO/

OTG2_

DCMI/

DSI

HOST

FMC_

SDNCAS

DCMI_D13

LCD SYS

ETH_PPS_OU

ETH_MII

_TX_EN /

ETH_RMII

_TX_EN

FMC_A10

FMC_A11

FMC_A12

FMC_A13

FMC_A14/F

MC_BA0

FMC_A15/F

MC_BA1

FMC_INT DCMI_D13 LCD_CLK

FMC_SDCL

FMC_NE2/

FMC_NCE

FMC_NE3

FMC_NE4

DCMI_D12

DCMI_VS

YNC

DCMI_D2

DCMI_D3

LCD_R7

LCD_G7

LCD_B2

LCD_B3

LCD_B1

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

ETH_MII

_TXD0 /

ETH_RMII

_TXD0

ETH_MII

_TXD1 /

ETH_RMII

_TXD1

FMC_A24

FMC_A25 -

LCD_R0

LCD_B0

EVENT

OUT

EVENT

OUT

EVENT

‘OUT

Port

PH0

PH1

PH2

PH3

PH4

PH5

PH6

Port

PH7

PH8

PH9

PH10

PH11

PH12

PH13

PH14

PH15

AF0

SYS

AF1

TIM1/2

AF2 AF3 AF4

Table 12. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF10

TIM3/4/

TIM8/9/

10/11

I2C1/2/3

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

SPI2/3/

USART

1/2/3

USAR

T6/

UART

4/5/7/

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

QUAD

SPI/OT

G2_HS

/OTG1

_FS

TIM5_CH1

TIM5_CH2 -

TIM5_CH3

TIM8_CH1

TIM8_CH2

TIM8_CH3

I2C2_SCL

I2C2_SDA SPI5_NSS

I2C2_SMBA SPI5_SCK

I2C3_SCL SPI5_MISO

I2C3_SDA

I2C3_SMBA

AF11

ETH

AF12

FMC/

SDIO/

OTG2_

AF13

DCMI/

DSI

HOST

AF14

LCD

AF15

SYS

QUADSPI_

BK2_IO0

QUADSPI_

BK2_IO1

LCD_G5

TIM12_CH1

ETH_MII_CRS

ETH_MII_COL

FMC_SDC

KE0

FMC_SDN

OTG_HS

_ULPI_N

ETH_MII_RXD

FMC_SDN

FMC_SDC

KE1

DCMI_D9

FMC_D16

DCMI_HS

YNC

TIM12_CH2

CAN1_TX

FMC_D17 DCMI_D0

FMC_D18

FMC_D19

FMC_D20

FMC_D21

FMC_D22

DCMI_D1

DCMI_D2

DCMI_D3

DCMI_D4

LCD_R0

LCD_R1

LCD_G4

LCD_R2

LCD_R3

LCD_R4

LCD_R5

LCD_R6

LCD_G2

LCD_G3

FMC_D23 DCMI_D11 LCD_G4

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

‘OUT

Port

PI4

PI5

PI6

PI7

Port I

PI8

PI9

PI10

PI0

PI1

PI2

PI3

PI11

PI12

PI13

PI14

PI15

AF0

SYS

AF1

TIM1/2

AF2 AF3 AF4

Table 12. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

TIM3/4/

TIM5_CH4

TIM8/9/

10/11

I2C1/2/3

TIM8_CH4

TIM8_ETR -

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

SPI2_NSS/I

2S2_WS

SPI2_SCK/I

2S2_CK

SPI2_MISO

I2S2ext_S

SPI2_MOSI

/I2S2_SD

SPI2/3/

USART

1/2/3

USAR

T6/

UART

4/5/7/

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

QUAD

SPI/OT

G2_HS

/OTG1

_FS

TIM8_BKI

TIM8_CH1

TIM8_CH2

TIM8_CH3

CAN1_RX

LCD_G6

LCD_G2

ETH

FMC/

SDIO/

OTG2_

DCMI/

DSI

HOST

LCD SYS

FMC_D24 DCMI_D13

FMC_D25

FMC_D26

FMC_D27

FMC_NBL2

FMC_NBL3

FMC_D28

FMC_D29

FMC_D30

DCMI_D8

DCMI_D9

DCMI_D10

DCMI_D5

DCMI_VS

YNC

DCMI_D6

DCMI_D7

LCD_G5

LCD_G6

LCD_G7

LCD_B4

LCD_B5

LCD_B6

LCD_B7

LCD_VSY

LCD_HSY

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

OTG_HS

_ULPI

_DIR

ETH_MII_RX_

FMC_D31

LCD_HSY

LCD_VSY

LCD_CLK

LCD_R0

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

‘OUT

Port

PJ0

PJ1

PJ2

PJ3

Port

PJ4

PJ5

PJ12

PJ13

PJ14

PJ15

PK3

PK4

Port

PK5

PK6

PK7

AF0

SYS

AF1

TIM1/2

AF2 AF3 AF4

Table 12. Alternate function (continued)

AF5 AF6 AF7 AF8 AF9 AF10

TIM3/4/

TIM8/9/

10/11

I2C1/2/3

SPI1/2/3

/4/5/6

SPI2/3/

SAI1

SPI2/3/

USART

1/2/3

USAR

T6/

UART

4/5/7/

CAN1/2/

TIM12/

13/14/

QUAD

SPI/LCD

QUAD

SPI/OT

G2_HS

/OTG1

_FS

LCD_R7 -

LCD_G3

LCD_G4

AF11

ETH

AF12 AF13 AF14 AF15

FMC/

SDIO/

OTG2_

DCMI/

DSI

HOST

LCD SYS

DSIHOST

_TE

LCD_R1

LCD_R2

LCD_R3

LCD_R4

LCD_R5

LCD_R6

LCD_B0

LCD_B1

LCD_B2

LCD_B3

LCD_B4

LCD_B5

LCD_B6

LCD_B7

LCD_DE

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

EVENT

OUT

Memory mapping STM32F479xx

The memory map is shown in

Figure 21

Figure 21. Memory map

0xFFFF FFFF 512-Mbyte

Block 7

Cortex

-4

Internal peripherals

0xE000 0000

0xDFFF FFFF

512-Mbyte

Block 6

FMC

0xD000 0000

0xCFFF FFFF

512-Mbyte

Block 5

FMC and

QUADSPI

0xA000 0000

0x9FFF FFFF

512-Mbyte

Block 4

FMC bank3 and

QUADSPI bank

0x8000 0000

0x7FFF FFFF

512-Mbyte

Block 3

FMC bank1 to

QUADSPI bank 2

0x6000 0000

0x5FFF FFFF

512-Mbyte

Block 2

Peripherals

0x4000 0000

0x3FFF FFFF

512-Mbyte

Block 1

SRAM

0x2000 0000

0x1FFF FFFF

512-Mbyte

Block 0

SRAM

0x0000 0000

Reserved

SRAM3

(128 KB aliased by bit-banding)

SRAM2

(32 KB aliased by bit-banding)

SRAM1

(160 KB aliased by bit-banding)

Reserved

Option Bytes

Reserved

System memory

Reserved

Option bytes

Reserved

CCM data RAM

(64 KB data SRAM)

Reserved

Flash memory

Reserved

Aliased to Flash, system memory or SRAM depending on the BOOT pins

0x2005 0000 - 0x3FFF FFFF

0x2003 0000 - 0x2004 FFFF

0x2002 8000 - 0x2002 FFFF

0x2000 0000 - 0x2002 7FFF

0x1FFF C008 - 0x1FFF FFFF

0x1FFF C000 - 0x1FFF C00 F

0x1FFF 7A10 - 0x1FFF 7FFF

0x1FFF 0000 - 0x1FFF 7A0F

0x1FFE C008 - 0x1FFE FFFF

0x1FFE C000 - 0x1FFE C00 F

0x1001 0000 - 0x1FFE BFFF

0x1000 0000 - 0x1000 FFFF

0x0820 0000 - 0x0FFF FFFF

0x0800 0000 - 0x081F FFFF

0x0020 0000 - 0x07FF FFFF

0x0000 0000 - 0x001F FFFF

Reserved

Cortex ® -M4 internal peripheral

AHB3

Reserved

0xE010 0000 - 0xFFFF FFFF

0xE000 0000 - 0xE00F FFFF

0x6000 0000 - 0xDFFF FFFF

0x5006 0C00 - 0x5FFF FFFF

0x5006 0BFF

AHB2

Reserved

0x5000 0000

0x4008 0000 - 0x4FFF FFFF

0x4007 FFFF

AHB1

Reserved

APB2

Reserved

APB1

0x4002 0000

0x4001 7400 - 0x4001 FFFF

0x4001 73FF

0x4001 0000

0x4000 8000 - 0x4000 FFFF

0x4000 7FFF

0x4000 0000

MSv33863V2

84/220 DS11118 Rev 7

STM32F479xx Memory mapping

Bus

Cortex

-M4

AHB3

AHB2

Table 13. STM32F479xx register boundary addresses (1)

Boundary address Peripheral

0xE00F FFFF - 0xFFFF FFFF

0xE000 0000 - 0xE00F FFFF

0xD000 0000 - 0xDFFF FFFF

0xC000 0000 - 0xCFFF FFFF

0xA000 1000 - 0xA0001FFF

0xA000 2000 - 0xBFFF FFFF

0xA000 0000- 0xA000 0FFF

0x9000 0000 - 0x9FFF FFFF

0x8000 0000 - 0x8FFF FFFF

0x7000 0000 - 0x7FFF FFFF

0x6000 0000 - 0x6FFF FFFF

0x5006 0C00- 0x5FFF FFFF

0x5006 0800 - 0x5006 0BFF

0x5006 0400 - 0x5006 07FF

0x5006 0000 - 0x5006 03FF

0x5005 0400 - 0x5005 FFFF

0x5005 0000 - 0x5005 03FF

0x5004 0000- 0x5004 FFFF

0x5000 0000 - 0x5003 FFFF

Reserved

Cortex

-M4 internal peripherals

FMC bank 6

FMC bank 5

Quad-SPI control register

Reserved

FMC control register

Quad-SPI bank

FMC bank 3

FMC bank 2 (reserved)

FMC bank 1

Reserved

RNG

HASH

CRYP

Reserved

DCMI

Reserved

USB OTG FS

DS11118 Rev 7 85/220

Memory mapping STM32F479xx

Table 13. STM32F479xx register boundary addresses (1) (continued)

Bus Boundary address Peripheral

AHB1

0x4008 0000- 0x4FFF FFFF

0x4004 0000 - 0x4007 FFFF

0x4002 BC00- 0x4003 FFFF

0x4002 B000 - 0x4002 BBFF

0x4002 9400 - 0x4002 AFFF

0x4002 9000 - 0x4002 93FF

0x4002 8C00 - 0x4002 8FFF

0x4002 8800 - 0x4002 8BFF

0x4002 8400 - 0x4002 87FF

0x4002 8000 - 0x4002 83FF

0x4002 6800 - 0x4002 7FFF

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0x4002 5000 - 0x4002 5FFF

0x4002 4000 - 0x4002 4FFF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0x4002 3400 - 0x4002 37FF

0x4002 3000 - 0x4002 33FF

0x4002 2C00 - 0x4002 2FFF

0x4002 2800 - 0x4002 2BFF

0x4002 2400 - 0x4002 27FF

0x4002 2000 - 0x4002 23FF

0x4002 1C00 - 0x4002 1FFF

0x4002 1800 - 0x4002 1BFF

0x4002 1400 - 0x4002 17FF

0x4002 1000 - 0x4002 13FF

0x4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

Reserved

USB OTG HS

Reserved

Chrom (DMA2D)

Reserved

ETHERNET MAC

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

Reserved

DMA2

DMA1

Reserved

BKPSRAM

Flash interface register

RCC

Reserved

CRC

Reserved

GPIOK

GPIOJ

GPIOI

GPIOH

86/220 DS11118 Rev 7

STM32F479xx Memory mapping

Table 13. STM32F479xx register boundary addresses (1) (continued)

Bus Boundary address Peripheral

APB2

0x4001 7400 - 0x4001 FFFF

0x4001 6C00 - 0x4001 73FF

0x4001 6800 - 0x4001 6BFF

0x4001 5C00 - 0x4001 67FF

0x4001 5800 - 0x4001 5BFF

0x4001 5400 - 0x4001 57FF

0x4001 5000 - 0x4001 53FF

0x4001 4C00 - 0x4001 4FFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2400 - 0x4001 2BFF

0x4001 2000 - 0x4001 23FF

0x4001 1800 - 0x4001 1FFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0800 - 0x4001 0FFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

Reserved

DSI Host

LCD-TFT

Reserved

SAI1

SPI6

SPI5

Reserved

TIM11

TIM10

TIM9

EXTI

SYSCFG

SPI4

SPI1

SDIO

Reserved

ADC1 - ADC2 - ADC3

Reserved

USART6

USART1

Reserved

TIM8

TIM1

DS11118 Rev 7 87/220

Memory mapping STM32F479xx

Table 13. STM32F479xx register boundary addresses (1) (continued)

Bus Boundary address Peripheral

APB1

0x4000 8000- 0x4000 FFFF

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1C00 - 0x4000 1FFF

0x4000 1800 - 0x4000 1BFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

1. The reserved boundary address are shown in grayed cells

Reserved

UART8

UART7

DAC

PWR

Reserved

CAN2

CAN1

Reserved

I2C3

I2C2

I2C1

UART5

UART4

USART3

USART2

I2S3ext

SPI3 / I2S3

TIM14

TIM13

TIM12

TIM7

TIM6

TIM5

SPI2 / I2S2

I2S2ext

IWDG

WWDG

RTC & BKP Registers

Reserved

TIM4

TIM3

TIM2

88/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

5.1.1

Unless otherwise specified, all voltages are referenced to V

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).

Unless otherwise specified, typical data are based on T

= 25 °C, V

1.7 V  tested.

= 3.3 V (for the

 3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 22

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 23 .

Figure 22. Pin loading conditions Figure 23. Pin input voltage

MCU pin

C = 50 pF VIN

MS19011V2

DS11118 Rev 7

MS19010V2

89/220

191

Electrical characteristics

5.1.6 Power supply scheme

Figure 24. Power supply scheme

BAT

= 1.65 to 3.6 V

Power switch

STM32F479xx

Backup circuitry

(OSC32K,RTC,

Wakeup logic

Backup registers, backup RAM)

OUT

GPIOs

Logic

20 × 100 nF

+ 1 × 4.7 μF

2 × 2.2 μF

CAP_1

CAP_2

1/2/...19/20

Voltage regulator

Kernel logic

(CPU, digital

& RAM)

DDUSB

BYPASS_REG

DDUSB

Flash memory

OTG-FS

PHY

100 nF

2.2 μF

DDDSI

CAPDSI

DD12DSI

SSDSI

DSI

Voltage regulator

DSI

PHY

100 nF

+ 1 μF

100 nF

+ 1 μF

REF

PDR_ON

DDA

REF+

REF-

SSA

Reset controller

ADC

Analog:

RCs, PLL,..

MS38256V1

and

Section 2.20

2. The two 2.2 µF ceramic capacitors on V capacitors when the voltage regulator is OFF.

and V

CAP_2

should be replaced by two 100 nF decoupling

3. The 4.7 µF ceramic capacitor must be connected to one of the V

pin.

4. V

DDA

and V

SSA

must be connected to V

and V

, respectively.

Caution: Each power supply pair (V

, V

DDA

SSA

...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.

This might cause incorrect operation of the device.

90/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 25. Current consumption measurement scheme

IDD_VBAT

VBAT

5.2

IDD

VDD

VDDA ai14126

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 14 ,

Table 15 , and Table 16

may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 14. Voltage characteristics

Ratings Min Max Unit

–V

External main supply voltage

(including V

DDA

, V

DDUSB

, V

DDDSI

and V

BAT

)

(1)

Input voltage on FT pins

(2)

Input voltage on TTa pins

Input voltage on any other pin

Input voltage on BOOT pin

|  V

DDx

| Variations between different V

power pins

SSX

 V

| Variations between all the different ground pins

(3)

ESD(HBM)

Electrostatic discharge voltage (human body model)

− 0.3

4.0

− 0.3 V

+4.0

− 0.3

4.0

V see

9.0

Section 5.3.18

1. All main power (V , V

DDA

, V , V

DDDSI

) and ground (V

, V

SSA

) pins must always be connected to

V mV

2. V

maximum value must always be respected. Refer to

Table 15

for the values of the maximum allowed injected current.

3. Including V

REF-

DS11118 Rev 7 91/220

191

Electrical characteristics STM32F479xx

Symbol

Table 15. Current characteristics

Ratings Max.

Unit

 I

VDD

 I

VSS

 I

VDDUSB

VDD

VSS

Total current into sum of all V

DD_x power lines (source)

(1)

Total current out of sum of all V

SS_x ground lines (sink)

Total current into V

DDUSB

power line (source)

Maximum current into each V

DD_x power line (source)

Maximum current out of each V

SS_x

Output current sunk by any I/O and control pin

(1) ground line (sink)

Output current sourced by any I/Os and control pin

Total output current sunk by sum of all I/O and control pins

(2)

−

290

100

− 100

−

120 mA

 I

Total output current sunk by sum of all USB I/Os

Total output current sourced by sum of all I/Os and control pins

Injected current on FT pins

(4)

−

120

Injected current on NRST and BOOT0 pins

3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.24

− 5/+0

INJ(PIN)

(3)

 I

INJ(PIN)

(5)

Injected current on TTa pins

(5)

Total injected current (sum of all I/O and control pins)

(6)

±5

±25

1. All main power (V , V ) and ground (V supply, in the permitted range.

, V

SSA

) pins must always be connected to the external power

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count

LQFP packages.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

5. A positive injection is induced by V never be exceeded. Refer to

Table 14

DDA

while a negative injection is induced by V <V

. I

INJ(PIN)

must

6. When several inputs are submitted to a current injection, the maximum positive and negative injected currents (instantaneous values).

Σ I

INJ(PIN)

is the absolute sum of the

Symbol

STG

Table 16. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

− 65 to +150

125

Unit

°C

92/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

5.3.1 General operating conditions

Symbol Parameter

Table 17. General operating conditions

Conditions

(1)

Min Typ Max Unit f

PCLK1

Internal APB1 clock frequency

Over-drive OFF

Over-drive ON

Over-drive OFF f

PCLK2

Internal APB2 clock frequency

Over-drive ON

DDA

(3)(4)

Standard operating voltage -

Analog operating voltage

(ADC limited to 1.2 M samples)

Must be the same potential as V

(5)

Analog operating voltage

(ADC limited to 2.4 M samples)

V f

HCLK

DDUSB

DDDSI

BAT

Internal AHB clock frequency

Power Scale 3 (VOS[1:0] bits in PWR_CR register = 0x01),

Regulator ON, over-drive OFF

Power Scale 2 (VOS[1:0] bits in PWR_CR register = 0x10),

Regulator ON

Over-drive

OFF

Over-drive

Power Scale 1 (VOS[1:0] bits in PWR_CR register= 0x11),

Regulator ON

Over-drive

OFF

Over-drive

USB supply voltage

(supply voltage for PA11, PA12,

PB14 and PB15 pins)

USB not used

USB used

DSI system operating voltage

Backup operating voltage

1.7

(2)

1.7

2.4

3.3

3.0

1.7

1.65

120

144

168

180

2.4

3.6

MHz

DS11118 Rev 7 93/220

191

Electrical characteristics STM32F479xx

Symbol

Table 17. General operating conditions (continued)

Parameter Conditions (1) Min Typ Max Unit

Regulator ON: 1.2 V internal voltage on V

CAP_1

CAP_2 pins

Regulator OFF: 1.2 V external voltage must be supplied from external regulator on

CAP_1

CAP_2 pins

(6)

Input voltage on RST and FT pins

(7)

Input voltage on TTa pins

Power Scale 3 ((VOS[1:0] bits in

PWR_CR register = 0x01), 120 MHz

HCLK max frequency

Power Scale 2 ((VOS[1:0] bits in

PWR_CR register = 0x10), 144 MHz

HCLK max frequency with over-drive OFF or 168 MHz with over-drive ON

Power Scale 1 ((VOS[1:0] bits in

PWR_CR register = 0x11), 168 MHz

HCLK max frequency with over-drive OFF or 180 MHz with over-drive ON

Max frequency 120 MHz

Max frequency 144 MHz

Max frequency 168 MHz

2 V  V

 3.6 V

 2 V

1.08 1.14

1.20 1.26

1.26 1.32

1.20

1.32

1.40

1.10 1.14

1.20

1.20 1.26

1.32

1.26 1.32

1.38

− 0.3

5.5

5.2

− 0.3

DDA

+0.3

Input voltage on BOOT0 pin

Power dissipation at T

= 85 °C for suffix 6 or T

= 105 °C for suffix 7

(8)

LQFP100

LQFP144

WLCSP168

UFBGA169

LQFP176

UFBGA176

LQFP208

465

500

645

385

526

513

1053 mW

Ambient temperature for 6 suffix version

Ambient temperature for 7 suffix version

Junction temperature range

TFBGA216

Maximum power dissipation

Low power dissipation

(9)

Maximum power dissipation

Low power dissipation

6 suffix version

7 suffix version

(9)

− 40 -

690

105

125

105

125

°C

1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.

2. V

DDA

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to

3. When the ADC is used, refer to

Table 76

4. If V

REF+

pin is present, it must respect the following condition: V

DDA

-V

REF+

< 1.2 V.

5. It is recommended to power V

DDA

DD and V from the same source. A maximum difference of 300 mV between V

DD and

6. The over-drive mode is not supported when the internal regulator is OFF.

94/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled

8. If T

is lower, higher P

values are allowed as long as T

does not exceed T

Jmax

9. In low power dissipation state, T

can be extended to this range as long as T

does not exceed T

Jmax

Operating power supply range

Table 18. Limitations depending on the operating power supply range

ADC operation

Maximum Flash memory access frequency with no wait states

Flashmax

)

Maximum HCLK frequency vs.

Flash memory wait states

(1)(2)

I/O operation

Possible Flash memory operations

1.7 to 2.1 V

(3)

2.1 to 2.4 V

2.4 to 2.7 V

2.7 to 3.6 V

(5)

Conversion time up to 1.2 Msps

Conversion time up to 2.4 Msps

20 MHz

(4)

22 MHz

24 MHz

30 MHz

168 MHz with 8 wait states and over-drive OFF

180 MHz with 8 wait states and over-drive ON

180 MHz with 7 wait states and over-drive ON

180 MHz with 5 wait states and over-drive ON

No I/O compensation

I/O compensation works

8-bit erase and program operations only

16-bit erase and program operations

32-bit erase and program operations

1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required.

2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution.

3. V

DDA

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to

Table 22 are derived from tests performed under ambient

4. Prefetch is not available.

5. When V

DDUSB

is connected to V

, the voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V.

5.3.2 VCAP1/VCAP2 external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor C the VCAP1/VCAP2 pins. C

EXT

is specified in

Table 19 .

EXT

Figure 26. External capacitor C

EXT

ESR

Leak

MS19044V2

1. Legend: ESR is the equivalent series resistance.

DS11118 Rev 7 95/220

191

Electrical characteristics STM32F479xx

Symbol

Table 19. VCAP1/VCAP2 operating conditions (1)

Parameter Conditions

CEXT

ESR

Capacitance of external capacitor

ESR of external capacitor

2.2 µF

< 2 

1. When bypassing the voltage regulator, the two 2.2 µF V replaced by two 100 nF decoupling capacitors.

CAP

capacitors are not required and should be

Subject to general operating conditions for T

Table 20. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit t

VDD

rise time rate

fall time rate



µs/V

5.3.5

Subject to general operating conditions for T

Table 21. Operating conditions at power-up / power-down (regulator OFF) (1)

Symbol Parameter Conditions Min Max Unit t t

VDD

VCAP

rise time rate

fall time rate

Power-up

Power-down

CAP_1

and V

CAP_2 rise time rate Power-up

CAP_1

and V

CAP_2

fall time rate Power-down

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V

1.08 V.

reach below



µs/V

Reset and power control block characteristics

The parameters given in

temperature and V

supply voltage conditions summarized in

The over-drive switching characteristics are given in Table 23

96/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 22. Reset and power control block characteristics

Parameter Conditions Min Typ Max Unit

PVD

PVDhyst

(1)

POR/PDR

PDRhyst

(1)

BOR1

BOR2

BOR3

Programmable voltage detector level selection

PVD hysteresis

Power-on/power-down reset threshold

PDR hysteresis

Brownout level 1 threshold

Brownout level 2 threshold

Brownout level 3 threshold

PLS[2:0]=000 (rising edge)

PLS[2:0]=000 (falling edge)

PLS[2:0]=001 (rising edge)

PLS[2:0]=001 (falling edge)

PLS[2:0]=010 (rising edge)

PLS[2:0]=010 (falling edge)

PLS[2:0]=011 (rising edge)

PLS[2:0]=011 (falling edge)

PLS[2:0]=100 (rising edge)

PLS[2:0]=100 (falling edge)

PLS[2:0]=101 (rising edge)

PLS[2:0]=101 (falling edge)

PLS[2:0]=110 (rising edge)

PLS[2:0]=110 (falling edge)

PLS[2:0]=111 (rising edge)

PLS[2:0]=111 (falling edge)

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

2.09

2.14

2.19

1.98

2.04

2.08

2.23

2.30

2.37

2.13

2.19

2.25

2.39

2.45

2.51

2.29

2.35

2.39

2.54

2.60

2.65

2.44

2.51

2.56

2.70

2.76

2.82

2.59

2.66

2.71

2.86

2.93

2.99

2.65

2.84

2.92

2.96

3.03

3.10

2.85

2.93

2.99

3.07

3.14

3.21

2.95

3.03

3.09

100 -

1.60

1.68

1.76

1.64

1.72

1.80

40 -

2.13

2.19

2.24

2.23

2.29

2.33

2.44

2.50

2.56

2.53

2.59

2.63

2.75

2.83

2.88

2.85

2.92

2.97

0.5

100

1.5

3.0

BORhyst

(1)

RSTTEMPO

(1)(2)

RUSH

(1)

RUSH

(1)

BOR hysteresis

POR reset temporization

InRush current on voltage regulator power-on (POR or wakeup from Standby)

InRush energy on voltage regulator power-on (POR or wakeup from Standby)

= 1.7 V, T

RUSH

= 105 °C,

= 171 mA for 31 µs

160

200

5.4

1. Guaranteed by design.

2. The reset temporization is measured from the power-on (POR reset or wakeup from V instruction is read by the user application code.

BAT

) to the instant when first

V mV

V mV ms mA

µC

DS11118 Rev 7 97/220

191

Electrical characteristics STM32F479xx

5.3.7

When the over-drive mode switches from enabled to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up.

. They are subject to general operating conditions for T

Symbol

Table 23. Over-drive switching characteristics

(1)

Parameter Conditions

T od_swen od_swdis

HSI

Over_drive switch enable time

HSE max for 4 MHz and min for 26 MHz

External HSE

50 MHz

HSI

Over_drive switch disable time

HSE max for 4 MHz and min for 26 MHz.

External HSE

50 MHz

1. Guaranteed by design.

Min

Typ

Max

100

Unit

µs

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 25

All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark

code.

98/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Typical and maximum current consumption

The MCU is placed under the following conditions:

 All I/O pins are in input mode with a static value at V

or V

(no load).

 All peripherals are disabled except if it is explicitly mentioned.

 The Flash memory access time is adjusted both to f

HCLK

frequency and V

(see Table 18: Limitations depending on the operating power supply range ).

range

 When the regulator is OFF, the V

General operating conditions .

is provided externally, as described in

Table 17:

 The voltage scaling and over-drive mode are adjusted to f

HCLK

frequency as follows:

– Scale 3 for f

HCLK

 

120 MHz

– Scale 2 for 120 MHz < f

HCLK

 144 MHz

– Scale 1 for 144 MHz < f

HCLK

 180 MHz. The over-drive is only ON at 180 MHz.

 The system clock is HCLK, f

PCLK1

= f

HCLK

/4, and f

PCLK2

= f

HCLK

/2.

 External clock frequency is 25 MHz and PLL is ON when f

HCLK

is higher than 25 MHz.

 The typical current consumption values are obtained for 1.7 V range and for ambient temperature T

= 25 °C unless otherwise specified.



 

 

3.6 V voltage



3.6 V voltage range and a  The maximum values are obtained for 1.7 V maximum ambient temperature (T





), unless otherwise specified.

 For the voltage range 1.7 V  

 

2.1 V the maximum frequency is 168 MHz.

DS11118 Rev 7 99/220

191

Electrical characteristics STM32F479xx

Table 24. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM, regulator ON

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz) Typ

25 °C

85 °C

105 °C

Unit

Supply current in

Run mode

All peripherals enabled

(2)(3)

180

168

150

144

120

180

168

150

144

120

103

109

(4)

142

124

114

104

175

149

140

127

124

102

63 mA

All peripherals

disabled

1. Guaranteed based on test during characterization.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

4. Guaranteed by test in production.

100/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Table 25. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled), regulator ON

Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz)

Typ

25 °C

85 °C

105 °C

Unit

Supply current in

Run mode

All peripherals enabled

(2)(3)

All peripherals disabled

168

150

144

120

168

150

144

120

102

128

118

108

1. Guaranteed based on test during characterization.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

105

100

154

143

131

108

DS11118 Rev 7 101/220

191

Electrical characteristics STM32F479xx

Table 26. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch), regulator OFF

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz)

DD12

= 25 °C T

= 85 °C T

= 105 °C

DD12

DD12

/ I

Supply current in Run mode from V

and

supply

All peripherals enabled

(2) (3)

All peripherals disabled

123

113

103

168

150

144

120

168

150

144

120

148

138

126

1. Guaranteed based on test during characterization.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, DSI regulator, an additional power consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

Unit mA

102/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Table 27. Typical and maximum current consumption in Sleep mode, regulator ON

Max

(1)(2)(3)

Symbol Parameter Conditions f

HCLK

(MHz) Typ

= 25 °C T

= 85 °C T

= 105 °C

180 78 88 (4) 118 151 (4)

Supply current in

Sleep mode

All peripherals enabled

All peripherals disabled

(4)

120

180

168

150

144

168

150

144

120

101

127

119

109

(4)

Unit mA

1. Guaranteed based on test during characterization.

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.

3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

4. Guaranteed by test in production.

DS11118 Rev 7 103/220

191

Electrical characteristics STM32F479xx

Table 28. Typical and maximum current consumption in Sleep mode, regulator OFF

Typ Max

(1)

Symbol Parameter Conditions f

HCLK

(MHz)

DD12

= 25 °C T

= 85 °C T

= 105 °C

DD12

DD12

/ I

Supply current in Run mode from V

and

supply

All peripherals enabled

All peripherals disabled

100

168

150

144

120

168

150

144

120

126

118

108

1. Guaranteed based on test during characterization.

Unit mA

104/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 29. Typical and maximum current consumption in Stop mode

Max

(1)

Parameter Conditions Typ

25 °C

85 °C

105 °C

Unit

DD_STOP_NM

(normal mode)

DD_STOP_UDM

(under-drive mode)

Supply current in Stop mode with voltage regulator in main regulator mode

Flash memory in Stop mode, all oscillators OFF, no independent watchdog

Flash memory in Deep power down mode, all oscillators OFF, no independent watchdog

Supply current in Stop mode with voltage regulator in Low Power regulator mode

Flash memory in Stop mode, all oscillators OFF, no independent watchdog

Flash memory in Deep power down mode, all oscillators OFF, no independent watchdog

Supply current in Stop mode with voltage regulator in main regulator and underdrive mode

Flash memory in Deep power down mode, main regulator in under-drive mode, all oscillators

OFF, no independent watchdog

Supply current in Stop mode with voltage regulator in Low Power regulator and underdrive mode

Flash memory in Deep power down mode, Low Power regulator in under-drive mode, all oscillators OFF, no independent watchdog

1. Data based on characterization, tested in production.

0.63

0.58

0.50

0.44

0.21

0.14

13 mA

DS11118 Rev 7 105/220

191

Electrical characteristics STM32F479xx

Table 30. Typical and maximum current consumption in Standby mode

Typ

(1)

Max

(2)

Symbol Parameter Conditions

= 25 °C

25 °C

85 °C

105 °C

1.7 V

2.4 V

3.3 V

= 3.3 V

Backup SRAM ON, RTC and

LSE oscillator OFF

Backup SRAM OFF, RTC and

LSE oscillator OFF

DD_STBY

Supply current in Standby mode

Backup SRAM OFF, RTC ON and LSE oscillator in Power

Drive mode

Backup SRAM ON, RTC ON and LSE oscillator in Power

Drive mode

Backup SRAM ON, RTC ON and LSE oscillator in High

Drive mode

Backup SRAM OFF, RTC ON and LSE oscillator in High

Drive mode

1.7

1.0

1.7

2.4

3.2

2.5

1.8

2.7

3.4

4.2

3.5

2.9

2.20

3.2

4.0

4.8

4.1

(3)

1. PDR is off for V additional 1.2 μ A

=1.7 V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by

2. Based on characterization, not tested in production unless otherwise specified.

3. Based on characterization, tested in production.

Unit

µA

106/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Table 31. Typical and maximum current consumption in V

BAT

mode

Typ Max

(2)

Symbol Parameter Conditions

(1)

= 25 °C

25 °C

85 °C

105 °C

BAT

1.7 V

BAT

2.4 V

BAT

3.3 V

Backup SRAM ON, RTC ON and LSE oscillator in Low

Power mode

Backup SRAM OFF, RTC ON and LSE oscillator in Low

Power mode

DD_VBAT

Backup domain supply current

Backup SRAM ON, RTC ON and LSE oscillator in High

Drive mode

Backup SRAM OFF, RTC ON and LSE oscillator in High

Drive mode

Backup SRAM ON, RTC and

LSE OFF

Backup SRAM OFF, RTC and

LSE OFF

1.431

0.720

2.212

1.499

0.710

0.018

1.577

0.849

2.368

1.637

0.720

0.020

1.825

1.060

2.630

1.862

0.760

0.024

1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a C

of 6 pF for typical values.

2. Based on characterization, tested in production.

3. Based on test during characterization.

1.9

1.1

2.80

2.0

0.8

0.2

(3)

BAT

= 3.3 V

12.0

7.0

17.3

12.3

5.0

2.0

24.0

13.9

34.6

24.5

10.0

4.0

Table 58: I/O static characteristics

Unit

µA

Figure 27. Typical V

BAT

current consumption

(RTC ON / backup SRAM ON and LSE in Low drive mode)

0 20 40 60

Temperature (°C)

80 100

1.65V

1.70V

1.80V

2.00V

2.40V

2.70V

3.00V

3.30V

3.60V

DS11118 Rev 7 107/220

191

Electrical characteristics STM32F479xx

Figure 28. Typical V

BAT

current consumption

(RTC ON / backup SRAM ON and LSE in High drive mode)

0 20 40 60

Temperature (°C)

80 100

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in

For the output pins, any external pull-down or external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 33

), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses

1.65V

1.70V

1.80V

2.00V

2.40V

2.70V

3.00V

3.30V

3.60V

108/220 DS11118 Rev 7

STM32F479xx Electrical characteristics the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin:

= V

 f

 C where

is the current sunk by a switching I/O to charge/discharge the capacitive load

is the MCU supply voltage f

is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C

INT

+ C

EXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

Symbol

DDIO

Table 32. Switching output I/O current consumption (1)

Parameter Conditions

I/O toggling

frequency

(fsw)

Typ Unit

I/O switching

Current

= 3.3 V

C= C

INT

(2)

= 3.3 V

EXT

= 0 pF

C = C

INT

+ C

EXT

+ C

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz mA

0.1

0.4

1.23

2.43

2.93

3.86

4.07

0.0

0.2

0.6

1.1

1.3

1.8

1.9

DS11118 Rev 7 109/220

191

Electrical characteristics STM32F479xx

Symbol

Table 32. Switching output I/O current consumption (1) (continued)

Parameter Conditions

I/O toggling

frequency

(fsw)

Typ Unit

DDIO

I/O switching

Current

EXT

= 3.3 V

= 10 pF

C = C

INT

+ C

EXT

C = C

INT

+ C

EXT

C = C

INT

= 3.3 V

= 22 pF

= 3.3 V

+ C

= 33 pF

+ Cext + C

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

84 MHz

90 MHz

2 MHz

8 MHz

25 MHz

50 MHz

60 MHz

2 MHz

8 MHz

25 MHz

50 MHz

1. C

is the PCB board capacitance including the pad pin. C

= 7 pF (estimated value).

2. This test is performed by cutting the LQFP176 package pin (pad removal).

0.26

1.01

3.14

6.39

10.68

0.33

0.18

0.67

2.09

3.6

4.5

7.8

9.8

1.29

4.23

11.02

On-chip peripheral current consumption

The MCU is placed under the following conditions:

 At startup, all I/O pins are in analog input configuration.

 All peripherals are disabled unless otherwise mentioned.

 I/O compensation cell enabled.

 The ART accelerator is ON.

 Scale 1 mode selected, internal digital voltage V12 = 1.32 V.

 HCLK is the system clock. f

PCLK1

= f

HCLK

/4, and f

PCLK2

= f

HCLK

/2.

The given value is calculated by measuring the difference of current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

– f

HCLK f

HCLK

= 180 MHz (Scale1 + over-drive ON), f

= 120 MHz (Scale 3)

HCLK

= 144 MHz (Scale 2),

 Ambient operating temperature is 25 °C and V

=3.3 V.

110/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Peripheral

AHB1

(up to

180 MHz)

GPIOA

GPIOB

GPIOC

GPIOD

GPIOE

GPIOF

GPIOG

GPIOH

GPIOI

GPIOJ

GPIOK

OTG_HS+ULPI

CRC

BKPSRAM

DMA1

(2)

DMA2

DMA2D

AHB2

(up to

180 MHz)

ETH_MAC

ETH_MAC_TX

ETH_MAC_RX

ETH_MAC_PTP

USB_OTG_FS

DVCMI

RNG

CRYP

HASH

AHB3

(up to

180 MHz)

QUADSPI

FMC

Bus matrix

(3)

Table 33. Peripheral current consumption

(Typ)

(1)

Scale 1

3.16

2.67

2.42

2.22

2.60

2.39

2.27

2.34

2.52

2.16

2.20

36.49

0.62

0.83

3.3 x N + 6.8

3.4 x N + 5.7

33.33

22.30

34.33

3.61

1.94

2.42

4.14

16.83

17.22

12.17

Scale 2

3.00

2.62

2.31

2.10

2.48

2.27

2.13

2.20

2.37

2.03

2.06

33.89

0.55

0.74

3 x N + 6.3

3.1 x N + 5.3

30.66

20.69

31.96

3.35

1.82

2.24

3.80

15.57

15.92

11.19

Scale 3

2.58

2.25

2.10

1.79

2.23

2.08

1.98

2.02

2.17

1.86

1.89

29.90

0.50

0.63

2.7 x N + 5.5

2.8 x N + 4.6

26.98

18.19

28.35

2.98

1.61

2.00

3.35

13.83

14.00

9.97

Unit

µA/MHz

DS11118 Rev 7 111/220

191

Electrical characteristics

APB1

(up to

45 MHz)

Table 33. Peripheral current consumption (continued)

(Typ) (1)

Peripheral

Scale 1 Scale 2 Scale 3

6.11

6.44

17.44

5.44

5.51

5.22

5.33

5.56

19.11

15.62

16.22

18.44

3.18

3.11

8.67

5.24

4.78

5.11

4.78

4.11

4.33

8.89

7.22

2.89

1.73

TIM13

TIM14

PWR

USART2

USART3

UART4

UART5

UART7

UART8

I2C1

TIM2

TIM3

TIM4

TIM5

TIM6

TIM7

TIM12

I2C2

I2C3

SPI2/I2S2

(4)

SPI3/I2S3

The wakeup times given in Table 34

CAN1

CAN2

DAC

(5)

WWDG

5.33

5.61

15.61

4.64

4.72

4.64

4.78

17.56

14.22

14.64

16.72

2.69

2.56

7.56

4.64

4.08

4.50

4.08

3.53

3.67

7.83

6.44

2.69

1.44

4.43

4.67

13.53

3.93

4.00

3.83

4.10

15.33

12.17

12.83

14.00

2.17

2.00

6.50

3.93

3.43

3.73

3.43

3.00

3.17

6.87

5.50

2.40

1.00

STM32F479xx

Unit

µA/MHz

112/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Table 33. Peripheral current consumption (continued)

(Typ) (1)

Peripheral

Scale 1 Scale 2 Scale 3

Unit

APB2

(up to

90 MHz)

USART1

USART6

SPI1

SPI4

SPI5

SPI6

SYSCFG

LTDC

SDIO

TIM1

TIM8

TIM9

TIM10

TIM11

ADC1

(6)

ADC2

(6)

ADC3

(6)

7.94

19.44

8.44

5.67

5.72

5.06

5.00

5.26

4.83

2.11

1.72

37.61

7.18

17.81

7.60

5.03

5.10

4.54

4.47

4.75

4.33

1.76

1.69

1.76

1.35

34.53

6.37

15.80

6.77

4.50

4.55

4.05

3.97

4.17

3.83

1.60

1.22

30.60

µA/MHz

SAI1

DSI

3.44

32.98

3.01

30.32

2.72

26.87

1. When the I/O compensation cell is ON, I

typical value increases by 0.22 mA.

2. DMA1/DMA2 current consumption is calculated by the equation. N: is the number of streams enabled,

N= [1..8]

3. The BusMatrix is automatically active when at least one master is ON.

4. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.

5. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of

0.8 mA per DAC channel for the analog part.

6. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of

1.6 mA per ADC for the analog part.

DS11118 Rev 7 113/220

191

Electrical characteristics STM32F479xx

5.3.8

Symbol t

WUSLEEP

(2)

Wakeup time from low-power modes

are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

 for Stop or Sleep modes the wakeup event is WFE

 WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and V

= 3.3 V.

Table 34. Low-power mode wakeup timings

Parameter Conditions

Wakeup from Sleep -

Main regulator is ON

Typ

(1)

Max

(1)

5 6

Unit

CPU clock cycles

12.9

15.0

Main regulator is ON and Flash memory in Deep power down mode

105 120 t

WUSTOP

Wakeup from Stop mode with MR/LP regulator in normal mode

Low power regulator is ON 22 28

Low power regulator is ON and Flash memory in Deep power down mode

114 130 t

WUSTOP

external clock signal has to respect the Table 58

Wakeup from Stop mode with MR/LP regulator in

Under-drive mode

Main regulator in under-drive mode

(Flash memory in Deep power-down mode)

Low power regulator in under-drive mode (Flash memory in Deep power-down mode)

107

115

114

121 t

WUSTDBY

(2)(3)

Wakeup from Standby mode 318 371

1. Based on test during characterization.

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first

3. t

WUSTDBY maximum value is given at –40 °C.

µ s

114/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The

. However, the recommended clock input

waveform is shown in Figure 29 .

The characteristics given in

Table 35 result from tests performed using an high-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

external clock signal has to respect the Table 58: I/O static characteristics . However, the

Symbol

Table 35. High-speed external user clock characteristics

Parameter Conditions Min f

HSE_ext

External user clock source frequency

(1)

HSEH

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

(1)

OSC_IN input capacitance

Duty cycle

(1)

OSC_IN Input leakage current

1. Guaranteed by design.

 V

0.7V

Typ

Max Unit

0.3V

±1

MHz

V ns pF

µA

Symbol f

LSE_ext

LSEH

LSEL t w(LSE) t f(LSE) t r(LSE) t f(LSE)

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The

The characteristics given in

Table 36 result from tests performed using an low-speed

external clock source, and under ambient temperature and supply voltage conditions summarized in

the requirements of the crystal or resonator (see Figure 31

Table 36. Low-speed external user clock characteristics

Parameter

User External clock source frequency

(1)

OSC32_IN input pin high level voltage

OSC32_IN input pin low level voltage

Conditions Min

0.7V

Typ

32.768

OSC32_IN high or low time

(1)

450 -

Max

1000

0.3V

Unit kHz

V ns

OSC32_IN rise or fall time

(1)

DS11118 Rev 7 115/220

191

Electrical characteristics STM32F479xx

Symbol

Table 36. Low-speed external user clock characteristics (continued)

Parameter

C in(LSE)

DuCy

(LSE)

OSC32_IN input capacitance

Duty cycle

(1)

OSC32_IN Input leakage current

1. Guaranteed by design.

Conditions

 V

Min

Typ

Max

±1

Figure 29. High-speed external clock source AC timing diagram

Unit pF

µA

VHSEH

90 %

VHSEL

10 % tr(HSE)

THSE tf(HSE)

External clock source fHSE_ext

OSC_IN tW(HSE)

STM32F tW(HSE) t ai17528

Figure 30. Low-speed external clock source AC timing diagram

VLSEH

VLSEL

90%

10 % tr(LSE)

TLSE tf(LSE) tW(LSE) tW(LSE) t

116/220

External clock source fLSE_ext

OSC32_IN

STM32F ai17529

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in

Table 37 . In

the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization

DS11118 Rev 7

STM32F479xx

Note:

Electrical characteristics time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 37. HSE 4-26 MHz oscillator characteristics (1)

Parameter Conditions Min Typ Max Unit f

OSC_IN

Oscillator frequency

Feedback resistor -

200

MHz k 

HSE current consumption

ACC

HSE

(2)

HSE accuracy

G m

_crit_max Maximum critical crystal g m t

SU(HSE)

(3)

Startup time

=3.3 V,

ESR= 30 Ω ,

=5 pF@25 MHz

=3.3 V,

ESR= 30 Ω ,

=10 pF@25 MHz

Startup

is stabilized

−

500

450

530

500

µA ppm mA/V ms

1. Guaranteed by design.

2. This parameter depends on the crystal used in the application. The minimum and maximum values must be respected to comply with USB standard specifications.

3. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is based on characterization and not tested in production. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For C

and C

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match

). C

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and C

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from www.st.com

Figure 31. Typical application with an 8 MHz crystal

Resonator with integrated capacitors

CL1

8 MHz resonator

OSC_IN

OSC_OU T

Bias controlled gain

CL2

REXT(1)

1. R

EXT

value depends on the crystal characteristics.

fHSE

STM32F ai17530

DS11118 Rev 7 117/220

191

Electrical characteristics STM32F479xx

Note:

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the informations given in this paragraph are based on characterization results obtained with typical external components specified in

Table 38 .

In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 38. LSE oscillator characteristics (f

LSE

= 32.768 kHz) (1)

Parameter Conditions Min Typ Max Unit

G m

ACC

LSE

(3)

Feedback resistor

LSE current consumption

LSE accuracy

_crit_max Maximum critical crystal g m

Low power mode

(2)

−

500

18.4

500

0.56

1.5

M t

SU(LSE)

(4)

Startup time V

is stabilized 2 s

1. Guaranteed by design.

2. LSE mode cannot be changed “on the fly” otherwise, a glitch can be generated on OSCIN pin.

3. This parameter depends on the crystal used in the application. Refer to application note AN2867.

4. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized

32.768 kHz oscillation is reached. This value is based on characterization and not tested in production. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.



µA ppm

µA/V

For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from www.st.com

Figure 32. Typical application with a 32.768 kHz crystal

Resonator with integrated capacitors

CL1

32.768 kH z resonator

OSC32_IN

Bias controlled gain

OSC32_OU T

CL2 fLSE

STM32F ai17531

118/220 DS11118 Rev 7

STM32F479xx

Min Max Typical

Electrical characteristics

5.3.10 Internal clock source characteristics

The parameters given in

Table 39 and

Table 40

are derived from tests performed under ambient temperature and V

High-speed internal (HSI) RC oscillator

Symbol

Table 39. HSI oscillator characteristics (1)

Parameter Conditions f

HSI

ACC

HSI

Frequency

HSI user trimming step

HSI oscillator accuracy

(2)

= –40 to 105 °C

(3)

= –10 to 85 °C (3)

= 25 °C

(4)

HSI oscillator startup time

HSI oscillator power consumption -

1. V

= 3.3 V, PLL off, T

= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design

3. Based on test during characterization.

4. Factory calibrated, parts not soldered.

Min Typ Max Unit

− 8

− 4

− 1

4.5

MHz

2.2

µs

60 80 µA

Figure 33. ACCHSI vs. temperature

-2

-40 0 25 55 85 105 125

TA (°C)

-4

-6

-8

MSv41055V1

1. Based on test during characterization.

DS11118 Rev 7 119/220

191

Electrical characteristics

Low-speed internal (LSI) RC oscillator

Table 40. LSI oscillator characteristics

(1)

Symbol Parameter f

LSI

(2) t su(LSI)

(3)

DD(LSI)

(3)

Frequency

Startup time

Power consumption

1. V

= 3 V, T

= –40 to 105 °C unless otherwise specified.

2. Based on test during characterization.

3. Guaranteed by design.

Min

Typ

0.4

Figure 34. ACC

LSI

versus temperature

STM32F479xx

Max

0.6

Unit kHz

µs

µA

-10

-20

-30

-40

-45 -35 -25 -15 -5 5 15 25 35

Temperat ure (°C)

45 55 65 75 85 95 105 max avg min

MS19013V1

Symbol f

PLL_IN f

PLL_OUT f

PLL48_OUT f

VCO_OUT

The parameters given in

Table 41 and

Table 42

are derived from tests performed under temperature and V

supply voltage conditions summarized in

interferences (see Table 54

Table 41. Main PLL characteristics

Parameter Conditions

PLL input clock

(1)

PLL multiplier output clock

48 MHz PLL multiplier output clock

PLL VCO output -

Min

0.95

(2)

192

Typ

Max Unit

2.10

180

432

MHz

120/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 41. Main PLL characteristics (continued)

Parameter Conditions Min Typ Max Unit t

LOCK

Jitter

(3)

DD(PLL)

(4)

DDA(PLL)

(4)

PLL lock time

Cycle-to-cycle jitter

Period jitter

Main clock output (MCO) for RMII

Ethernet

Main clock output (MCO) for MII

Ethernet

Bit time CAN jitter

PLL power consumption on V

DDA

VCO frequency = 192 MHz

VCO frequency = 432 MHz

System clock

120 MHz

RMS peak to peak

Cycle to cycle at 50 MHz on

1000 samples

Cycle to cycle at 25 MHz on

1000 samples

Cycle to cycle at 1 MHz on

1000 samples

VCO frequency = 192 MHz

VCO frequency = 432 MHz

VCO frequency = 192 MHz

VCO frequency = 432 MHz

100

0.15

0.45

0.30

0.55

 150

 200

330

200

300

0.40

0.75

0.40

0.85

µs ps mA

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S.

2. Guaranteed by design.

3. The use of two PLLs in parallel can degrade the jitter up to +30%.

4. Based on test during characterization.

Symbol f

PLLI2S_IN f

PLLI2S_OUT f

VCO_OUT t

LOCK

Jitter

(3)

Table 42. PLLI2S (audio PLL) characteristics

Parameter

PLLI2S input clock

(1)

PLLI2S multiplier output clock

PLLI2S VCO output

Conditions

PLLI2S lock time

Master I2S clock jitter

WS I2S clock jitter

VCO frequency = 192 MHz

VCO frequency = 432 MHz

Cycle to cycle at

12.288 MHz on 48KHz period, N=432, R=5

RMS

peak to peak

Average frequency of 12.288 MHz,

N=432, R=5 on 1000 samples

Cycle to cycle at 48 KHz on 1000 samples

Min

0.95

(2)

192

100

Typ Max Unit

 280

400

2.10

216

432

200

300

MHz

µs

ps ps ps

DS11118 Rev 7 121/220

191

Electrical characteristics STM32F479xx

Symbol

Table 42. PLLI2S (audio PLL) characteristics (continued)

Parameter Conditions Min

DD(PLLI2S)

(4)

DDA(PLLI2S)

(4)

PLLI2S power consumption on V

DDA

VCO frequency = 192 MHz

VCO frequency = 432 MHz

VCO frequency = 192 MHz

VCO frequency = 432 MHz

0.15

0.45

0.30

0.55

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Based on test during characterization.

Typ Max Unit

0.40

0.75

0.40

0.85

Symbol

Table 43. PLLSAI (audio and LCD-TFT PLL) characteristics

Parameter Conditions Min Typ f f f

PLLSAI_IN

PLLSAI_OUT

VCO_OUT t

LOCK

PLLSAI input clock

PLLSAI lock time

(1)

PLLSAI multiplier output clock

PLLSAI VCO output

VCO frequency = 192 MHz

VCO frequency = 432 MHz

0.95

192

(2)

Jitter

(3)

Main SAI clock jitter

FS clock jitter

DD(PLLSAI)

(4)

DDA(PLLSAI)

(4)

PLLSAI power consumption on

DDA

Cycle to cycle at

12.288 MHz on

48 KHz period,

N=432, R=5

Average frequency of

12.288 MHz

N = 432, R = 5 on 1000 samples

RMS

peak to peak

Cycle to cycle at 48 KHz on 1000 samples

VCO frequency = 192 MHz

VCO frequency = 432 MHz

VCO frequency = 192 MHz

VCO frequency = 432 MHz

100

0.15

0.45

0.30

0.55

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Based on test during characterization.

 280

400

0.40

0.75

0.40

0.85

Max

2.10

216

432

200

300

Unit

MHz

µs ps ps ps mA

122/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

5.3.12 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

). It is available only on the main PLL.

Symbol f

Mod md

MODEPER * INCSTEP

1. Guaranteed by design.

Table 44. SSCG parameters constraint

Parameter Min

Modulation frequency

Peak modulation depth

0.25

Typ

Max

(1)

15 − 1

Unit

KHz

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER = round f

PLL_IN

 

Mod

  f

PLL_IN and f

Mod must be expressed in Hz.

As an example:

If f

PLL_IN

= 1 MHz, and f

MOD

= 1 kHz, the modulation depth (MODEPER) is given by equation 1:

MODEPER = 

  

  = 250

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

INCSTEP = round    2

– 1   md PLLN    100 5  MODEPER   f

VCO_OUT must be expressed in MHz.

With a modulation depth (md) = ± 2 % (4 % peak to peak), and PLLN = 240 (in MHz):

INCSTEP = round    2

– 1   2 240    100 5  250   = 126md(quantitazed)%

An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and

INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized

% =   100  5     2

– 1   PLLN 

As a result: md quantized

% =   100  5     2

– 1   240  = 2.002%(peak)

DS11118 Rev 7 123/220

191

Electrical characteristics STM32F479xx

Figure 35

and

Figure 36 show the main PLL output clock waveforms in center spread and

down spread modes, where:

F0 is f

PLL_OUT

nominal.

T mode

is the modulation period.

md is the modulation depth.

Figure 35. PLL output clock waveforms in center spread mode

Frequency

(PLL_OUT)

F0

t

mode

2x t

mode

Figure 36. PLL output clock waveforms in down spread mode

Frequency

(PLL_OUT)

F0

2x md

Time

MS39983V1

t

mode

2x t

mode

Time

MS39982V1

5.3.13 MIPI D-PHY characteristics

The parameters given in

Table 45 and

Table 46

are derived from tests performed under temperature and V

supply voltage conditions summarized in

Table 47 are derived from tests performed under temperature and

Symbol

INST

Table 45. MIPI D-PHY characteristics (1)

Parameter Conditions Min

UI instantaneous

Hi-Speed Input/Output characteristics

Typ

Max

12.5

Unit ns

124/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 45. MIPI D-PHY characteristics (1) (continued)

Parameter Conditions Min

| ∆

V t

HSr

CMTX

∆

CMTX

OHHS

& t

IH hys

HSf

IL-ULPS

HS transmit common mode voltage

CMTX

mismatch when output is Differential-1 or Differential-0

HS transmit differential voltage

mismatch when output is

Differential-1 or Differential-0

HS output high voltage

150

140

Single ended output impedance

Single ended output impedance mismatch

20% - 80% rise and fall time -

LP receiver input characteristics

100

Logic 0 input voltage (not in

ULP State)

Logic 0 input voltage in ULP

State

Input high level voltage

Voltage hysteresis

LP emitter output characteristics

880

IL-ULPS

IH hys

Output low level voltage

Output high level voltage

Output impedance of LP transmitter

15%-85% rise and fall time

1.1

-50

110

LP contention detector characteristics

ILCD

IHCD

Logic 0 contention threshold

1. Guaranteed based on test during characterization.

450

Typ

200

1.2

Max

250

270

360

62.5

0.35*UI

550

300

1.2

200

Unit mV

Ω

% ps mV mV

V mV

Ω ns

DS11118 Rev 7 125/220

191

Electrical characteristics STM32F479xx

Table 46. MIPI D-PHY AC characteristics LP mode and HS/LP transitions (1)

Symbol Parameter Conditions Min Typ Max Unit

LPX

CLK-PREPARE

CLK-ZERO

CLK-PRE

CLK-POST

CLK-TRAIL

HS-PREPARE

HS-ZERO

HS-TRAIL

HS-EXIT

REOT

EOT

Transmitted length of any Low-

Power state period

Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the

HS-0 Line state starting the HS transmission.

Time that the transmitter drives the HS-0 state prior to starting the clock.

Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from

LP to HS mode.

Time that the transmitter continues to send HS clock after the last associated Data

Lane has transitioned to LP

Mode.

Time that the transmitter drives the HS-0 state after the last payload clock bit of an HS transmission burst.

Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0

Line state starting the HS transmission.

HS-PREPARE+

Time that the transmitter drives the HS-0 state prior to transmitting the

Sync sequence.

Time that the transmitter drives the flipped differential state after last payload data bit of a

HS transmission burst.

Time that the transmitter drives

LP-11 following a HS burst.

30% - 85% rise time and fall time

Transmitted time interval from the start of T

HS-TRAIL

CLK-TRAIL

, to the start of the

LP-11 state following a HS burst.

1. Guaranteed based on test during characterization.

300

62+52*UI

40+4*UI

145+10*UI

Max

(n*8*UI,

60+n*4*UI)

100

85+6*UI

105+ n*12UI ns

UI ns

126/220 DS11118 Rev 7

STM32F479xx

Clock

Lane

Electrical characteristics

Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram

CLK-POST

EOT

CLK-TRAIL

HS-EXIT

LPX

CLK-PREPARE

CLK-ZERO

CLK-PRE

LPX

HS-PREPARE

Data

Lane

Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram

MS38282V1

Clock

Lane

LPX

HS-PREPARE

HS-ZERO

Data

Lane

LP-11 LP-01 LP-00

EOT

HS-TRAIL

REOT

HS-EXIT

MS38283V1

The parameters given in

supply voltage conditions summarized in

Table 48 are derived from tests performed under temperature and

Symbol

Table 47. DSI-PLL characteristics (1)

Parameter f

PLL_IN f

PLL_INFIN f

PLL_OUT f

VCO_OUT t

LOCK

PLL input clock

PFD input clock

PLL multiplier output clock

PLL VCO output

PLL lock time

Conditions

Min Typ Max Unit

31.25

500

100

500

1000

200

MHz

µs

DS11118 Rev 7 127/220

191

Electrical characteristics STM32F479xx

Symbol

Table 47. DSI-PLL characteristics (1) (continued)

Parameter Conditions

DD(PLL)

PLL power consumption on V

DD12 f

VCO_OUT

= 500 MHz f

VCO_OUT

= 600 MHz f

VCO_OUT

= 1000 MHz

1. Based on test during characterization.

Min Typ Max Unit

0.55

0.70

0.65

0.80

0.95

1.20

5.3.15 MIPI D-PHY regulator characteristics

The parameters given in

supply voltage conditions summarized in

The test results are given in Table 53

Symbol

Table 48. DSI regulator characteristics

(1)

Parameter Conditions

DD12DSI

EXT

ESR

DDDSIREG

DDDSI

DDDSILP

1.2 V internal voltage on V

External capacitor on V

External Serial Resistor

DD12DSI

CAPDSI

Regulator power consumption

DSI system (regulator, PLL and

D-PHY) current consumption on V

DDDSI

DSI system current consumption on

DDDSI

in LP mode communication

(2)

Ultra Low Power Mode

(Reg. ON + PLL OFF)

Stop State

(Reg. ON + PLL OFF)

10 MHz escape clock

(Reg. ON + PLL OFF)

20 MHz escape clock

(Reg. ON + PLL OFF)

300 Mbps - 1 data lane

(Reg. ON + PLL ON)

DDDSIHS

DSI system (regulator, PLL and

D-PHY) current consumption on V

DDDSI in HS mode communication

(3)

300 Mbps - 2data lane

(Reg. ON + PLL ON)

500 Mbps - 1 data lane

(Reg. ON + PLL ON)

500 Mbps - 2data lane

(Reg. ON + PLL ON)

DSI system (regulator, PLL and

D-PHY) current consumption on V

DDDSI in HS mode with CLK like payload

500 Mbps - 2data lane

(Reg. ON + PLL ON) t

WAKEUP

Startup delay

EXT

= 2.2 µF

EXT

= 3.3 µF

External capacitor load at start I

INRUSH

Inrush current on V

DDDSI

1. Based on test during characterization.

2. Values based on an average traffic in LP Command Mode.

3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.

Min Typ Max Unit

1.15

1.20

1.30

1.1

2.2

3.3

μ F

0 25 600 m Ω

100 120 125 µA

290 600

4.3

5.0

4.3

5.0

8.0

8.8

11.4

12.5

13.5

14.7

18.0

19.6

21.4

23.3

µA mA mA

110

160

µs

60 200 mA

128/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Flash memory

The characteristics are given at TA = –40 to 105 °C unless otherwise specified.

The devices are shipped to customers with the Flash memory erased.

Symbol

Parameter

Table 49. Flash memory characteristics

Conditions Min

Supply current

Write / Erase 8-bit mode, V

= 1.7 V

Write / Erase 16-bit mode, V

= 2.1 V

Write / Erase 32-bit mode, V

= 3.3 V

Typ

Max Unit

Symbol

Table 50. Flash memory programming

Parameter Conditions t t t prog

ERASE16KB

ERASE64KB

Word programming time

Sector (16 KB) erase time

Sector (64 KB) erase time

Program/erase parallelism

(PSIZE) = x 8/16/32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8 t

ERASE128KB

Sector (128 KB) erase time

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Min

(1)

Typ Max

(1)

Unit

16 100

(2)

400

300

250

800

600

500

1200 2400

700 1400

550 1100

1.3

2.6

µs ms ms s

DS11118 Rev 7 129/220

191

Electrical characteristics STM32F479xx

Symbol

Table 50. Flash memory programming (continued)

Parameter Conditions

V t t

BE prog

Mass erase time

Bank erase time

Programming voltage

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

Program/erase parallelism

(PSIZE) = x 8

Program/erase parallelism

(PSIZE) = x 16

Program/erase parallelism

(PSIZE) = x 32

32-bit program operation

16-bit program operation

8-bit program operation

1. Based on test during characterization.

2. The maximum programming time is measured after 100K erase operations.

Min (1)

2.7

2.1

1.7

Typ Max (1)

3.6

Unit s

Symbol

Table 51. Flash memory programming with V

Parameter Conditions Min

(1)

Typ Max

(1)

16 100

(2) t prog t

ERASE16KB t

ERASE64KB t

ERASE128KB t

ME t

V prog

Double word programming

Sector (16 KB) erase time

Sector (64 KB) erase time

Sector (128 KB) erase time

Mass erase time

Bank erase time

Programming voltage



0 to +40 °C

= 3.3 V

= 8.5 V

VPP

(3)

voltage range

Minimum current sunk on the V

Cumulative time during which V

PP is applied

1. Guaranteed by design.

2. The maximum programming time is measured after 100K erase operations.

3. V

should only be connected during programming/erasing.

2.7

230

490

875

6.9

3.6

Unit

µs ms s s

V mA hour

130/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 52. Flash memory endurance and data retention

Value

Parameter Conditions

Min

(1)

N t

END

RET

Endurance

Data retention

= –40 to +85 °C (6 suffix versions)

= –40 to +105 °C (7 suffix versions)

1 kcycle

(2)

at T

= 85 °C

1 kcycle

(2)

at T

= 105 °C

10 kcycles

(2)

at T

= 55 °C

1. Based on test during characterization.

2. Cycling performed over the whole temperature range.

Unit kcycles

Years

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

 Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

 FTB : A burst of fast transient voltage (positive and negative) is applied to V

and V

SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

. They are based on the EMS levels and classes defined in application note AN1709.

Symbol

FESD

EFTB

Table 53. EMS characteristics

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

and V pins to induce a functional disturbance

 3.3 V, TFBGA216,

= +25 °C, f

HCLK

= 168 MHz, conforming to IEC 61000-4-2

 3.3 V, TFBGA216,

= +25 °C, f

HCLK

= 168 MHz, conforming to IEC 61000-4-2

Level/Class

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

DS11118 Rev 7 131/220

191

Electrical characteristics STM32F479xx

Software recommendations

The software flowchart must include the management of runaway conditions such as:

 Corrupted program counter

 Unexpected reset

 Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC

code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

EMI

Symbol Parameter

Table 54. EMI characteristics

Conditions

Monitored frequency band

Max vs. [f

HSE

CPU

]

8/168 MHz 8/180 MHz

Peak level

= 3.3 V, T

= 25 °C, TFBGA216 package, conforming to SAE J1752/3

EEMBC, ART ON, all peripheral clocks enabled, clock dithering disabled.

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

 3.3 V, T

 25 °C, TFBGA216 package, conforming to SAE J1752/3

EEMBC, ART ON, all peripheral clocks enabled, clock dithering enabled

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI level

-10

-15

Unit dBµV

dBµV

5.3.18 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESD S5.3.1 standards.

132/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Table 55. ESD absolute maximum ratings

Conditions Symbol Ratings

ESD(HBM)

ESD(CDM)

Electrostatic discharge voltage

(human body model)

Electrostatic discharge voltage

(charge device model)

 +25 °C conforming to ANSI/ESDA/JEDEC JS-001

 +25 °C conforming to ANSI/ESD S5.3.1,

LQFP176, LQFP208, UFBGA169, UFBGA176,

TFBGA216 and WLCSP148 packages

1. Guaranteed based on test during characterization.

Class

Maximum value

(1)

Unit

2000

250

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

 A supply overvoltage is applied to each power supply pin

 A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

Symbol Parameter

Table 56. Electrical sensitivities (1)

Conditions

LU Static latch-up class T

 +105 °C conforming to JESD78A

1. MSV on PA4 and PA5 is 5 V, versus 5.4 V on all IOs.

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS above V

(for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5

LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –

5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

The test results are given in Table 57

DS11118 Rev 7 133/220

191

Electrical characteristics

Note:

STM32F479xx

Symbol

INJ

Table 57. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

− 0

Positive injection

NA (1) Injected current on BOOT0 and NRST pins

Injected current on DSIHOST_D0P,

DSIHOST_D0N, DSIHOST_D1P, DSIHOST_D0N,

DSIHOST_CKP, DSIHOST_CKN pins

Injected current on PA0 and PC0 pins

Injected current on any other FT pin

Injected current on any other pin

− 0

− 5

Table 58 are derived from tests

+ 5

1. Injection is not possible.

Unit mA

It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

General input/output characteristics

Unless otherwise specified, the parameters given in

performed under the conditions summarized in Table 17

All I/Os are CMOS and TTL compliant.

Symbol Parameter

Table 58. I/O static characteristics

FT, TTa and NRST I/O input low level voltage

Conditions

1.7 V  V

 3.6 V

Min

BOOT0 I/O input low level voltage

FT, TTa and NRST I/O input high level voltage (5)

BOOT0 I/O input high level voltage

1.75 V  V

–40 °C  T



 3.6 V,

105 °C

1.7 V  V

0 °C  T



 3.6 V,

105 °C

1.7 V  V

 3.6 V

0.45V

+0.3

(1)

0.7V

(2)

1.75 V  V

–40 °C  T



 3.6 V,

105 °C

1.7 V  V

0 °C  T



 3.6 V,

105 °C

0.17V

+0.7

(1)

Typ Max

0.35V

− 0.04

(1)

0.3V

(2)

Unit

0.1V

+0.1

(1)

134/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 58. I/O static characteristics (continued)

Parameter Conditions Min Typ Max Unit

FT, TTa and NRST I/O input hysteresis

1.7 V  V

 3.6 V 10%V

(3)

HYS lkg

BOOT0 I/O input hysteresis

I/O input leakage current

(4)

I/O FT input leakage current (5)

1.75 V  V

–40 °C  T



 3.6 V,

105 °C

1.7 V  V

0 °C  T



 3.6 V,

105 °C

 V

 V

 5 V

0.1



µA

All pins except for

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

 V

30 40 50

Weak pull-up equivalent resistor

(6)

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

7 10 14 k 

Weak pulldown equivalent resistor

(7)

All pins except for

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

 V

30 40 50

PA10/PB12

(OTG_FS_ID,

OTG_HS_ID)

7 10 14

(8)

I/O pin capacitance 5 -

1. Guaranteed by design.

2. Tested in production.

3. With a minimum of 200 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 57

5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be

higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 57

6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10%).

7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10%).

8. Hysteresis voltage between Schmitt trigger switching levels. Based on test during characterization.

DS11118 Rev 7 135/220

191

Electrical characteristics STM32F479xx

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in

Figure 39

Figure 39. FT I/O input characteristics

VIL/VIH (V)

2.52

TTL requirement

VIHmin = 2V

2.0

1.92

1.7

1.22

1.19

1.065

Tested in production - CMOS requirement VIHmin = 0.7VDD

Area not

0.8

0.55

0.51

= 0.8V

Tested in production - CMOS requirement VILmax = 0.3VDD

VDD (V)

1.7

2.0

2.4

2.7

3.3

3.6

MS33746V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to  8 mA, and sink or source up to ±20 mA (with a relaxed V

) except PC13, PC14, PC15 and PI8 which can sink or source up to ±3mA. When using the PC13 to PC15 and PI8 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 5.2

. In particular:

 The sum of the currents sourced by all the I/Os on V

DD, consumption of the MCU sourced on V

DD,

 I

VDD

(see

Table 15 ).

plus the maximum Run cannot exceed the absolute maximum rating

 The sum of the currents sunk by all the I/Os on V

SS consumption of the MCU sunk on V

 I

VSS

(see Table 15

plus the maximum Run

cannot exceed the absolute maximum rating

136/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Output voltage levels

Unless otherwise specified, the parameters given in

Table 59 are derived from tests

performed under ambient temperature and V

Table 17 . All I/Os are CMOS and TTL compliant.

supply voltage conditions summarized in

Symbol

Table 59. Output voltage characteristics

Parameter Conditions Min Max Unit

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

= +8 mA

2.7 V  V

 3.6 V

TTL port

(2)

=+ 8mA

2.7 V  V

 3.6 V

−

2.4

0.4

(1)

(3)

(1)

(3)

(1)

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

2.7 V  V

1.8 V  V

= +20 mA

1.7 V  V



3.6 V

= +6 mA

3.6 V

= +4 mA

3.6V

− 1.3

(4)

− 0.4

(4)

− 0.4

(5)

1.3

0.4

(4)

(5)

1. The I

current sunk by the device must always respect the absolute maximum rating specified in Table 15

. and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

current sourced by the device must always respect the absolute maximum rating specified in

Table 15

and the sum of I

(I/O ports and control pins) must not exceed I

VDD

4. Based on characterization data.

5. Guaranteed by design.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 40

and

Table 60 , respectively.

Unless otherwise specified, the parameters given in

Table 60 are derived from tests

performed under the ambient temperature and V

DD in

3. The maximum frequency is defined in Figure 40 .

supply voltage conditions summarized

DS11118 Rev 7 137/220

191

Electrical characteristics STM32F479xx

Table 60. I/O AC characteristics (1)(2)

OSPEEDRy

[1:0] bit value (1)

Symbol

Parameter Conditions Min Typ Max Unit f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time f max(IO)out

Maximum frequency

(3) t f(IO)out

/ t r(IO)out

Output high to low level fall time and output low to high level rise time

= 50 pF, V

≥ 2.7 V -

= 50 pF, V

≥ 1.7 V -

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 50 pF, V

3.6 V

= 1.7 V to

= 50 pF, V

≥ 2.7 V

= 50 pF, V

≥ 1.8 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 50 pF, V

≥ 2.7 V

= 10 pF, V

≥ 2.7 V

= 50 pF, V

≥ 1.7 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.7 V

= 10 pF, V

≥ 2.7 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 40 pF, V

≥ 2.7 V

= 10 pF, V

≥ 2.7 V

= 40 pF, V

≥ 1.7 V

= 10 pF, V

≥ 1.7 V

100

MHz ns

12.5

(4)

100 (4)

42.5

MHz ns

138/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Table 60. I/O AC characteristics (1)(2) (continued)

OSPEEDRy

[1:0] bit value

(1)

Symbol Parameter Conditions Min Typ Max Unit

11 f max(IO)out t t f(IO)out r(IO)out

Maximum frequency level rise time

(3)

Output high to low level fall time and output low to high

= 30 pF, V

≥ 2.7 V

= 30 pF, V

≥ 1.8 V

= 30 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

= 30 pF, V

≥ 2.7 V

= 30 pF, V

≥ 1.8 V

= 30 pF, V

≥ 1.7 V

= 10 pF, V

≥ 2.7 V

= 10 pF, V

≥ 1.8 V

= 10 pF, V

≥ 1.7 V

MHz ns

tEXTIpw

Pulse width of external signals detected by the EXTI controller

10 ns

1. Guaranteed by design.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.

4. For maximum frequencies above 50 MHz and V

> 2.4 V, the compensation cell should be used.

2.5

3.5

42.5

100

72.5

Figure 40. I/O AC characteristics definition

90% 10%

50%

10%

50%

90%

EXTERNAL

OUTPUT

ON CL tr(IO)out tf(IO)out

Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%) when loaded by C L specified in the table “ I/O AC characteristics ”. ai14131d

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Electrical characteristics STM32F479xx

5.3.21 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

(see

Table 58 ).

Unless otherwise specified, the parameters given in

Table 61 are derived from tests

performed under the ambient temperature and V

DD in

supply voltage conditions summarized

Table 61. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

F(NRST)

(2)

NF(NRST)

Table 58 . Otherwise the reset is not taken into account by the device.

NRST_OUT

Weak pull-up equivalent resistor

NRST Input filtered pulse

NRST Input not filtered pulse

Generated reset pulse duration

(1)



> 2.7 V

Internal Reset source

300

100

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10%).

2. Guaranteed by design.

k  ns

µs

Figure 41. Recommended NRST pin protection

External reset circuit (1)

NRST(2)

VDD

RPU

0.1 μF

Filter

Internal Reset

STM32F ai14132c

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

IL(NRST)

max level specified in

140/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

The parameters given in

Table 62 are guaranteed by design. Refer to

Section 5.3.20

for

details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 62. TIMx characteristics

(1)(2)

Parameter Conditions

(3) Min Max Unit t res(TIM) f

EXT

Timer resolution time

AHB/APBx prescaler =

1 or 2 or 4, f

TIMxCLK

= 180 MHz

AHB/APBx prescaler > 4, f

TIMxCLK

= 90 MHz

Timer external clock frequency on CH1 to CH4 f

TIMxCLK

= 180 MHz

Timer resolution Res

TIM t

MAX_COUNT

Maximum possible count with 32-bit counter

TIMxCLK

16/32

65536 ×

65536

/2 t t t

TIMxCLK

MHz bit

TIMxCLK

1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.

2. Guaranteed by design.

3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the

RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK =

4x PCLKx.

I

C interface characteristics

The I

C interface meets the timings requirements of the I

C-bus specification and user manual rev. 03 for:

 Standard-mode (Sm): bit rate up to 100 kbit/s

 Fast-mode (Fm): bit rate up to 400 kbit/s.

The I

C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0386 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

Section 5.3.20

for more details on the I

is disabled, but is still present. Refer to

C I/O characteristics.

All I

C SDA and SCL I/Os embed an analog filter, whose characteristics are detailed in

Table 63 .

Symbol

Table 63. I2C analog filter characteristics (1)

Parameter t

Maximum pulse width of spikes suppressed by the analog filter

1. Guaranteed based on test during characterization.

Min

(2)

Max

150

(3)

Unit ns

DS11118 Rev 7 141/220

191

Electrical characteristics STM32F479xx

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

SPI interface characteristics

Unless otherwise specified, the parameters given in

Table 64 for the SPI interface are

derived from tests performed under the ambient temperature, f

PCLKx frequency and V

, with the following configuration:

 output speed set to OSPEEDRy[1:0] = 10

 capacitive load C = 30 pF

 measurement points at CMOS levels: 0.5 V

for more details on the input/output alternate function characteristics

(NSS, SCK, MOSI, MISO for SPI).

Symbol f

SCK

1/t c(SCK)

Duty(SCK)

Parameter

Table 64. SPI dynamic characteristics

(1)

Conditions Min

SPI clock frequency

Master mode,

2.7 V ≤ V

SPI1,4,5,6,

≤ 3.6 V,

Master mode,

1.71 V ≤ V

SPI1,4,5,6

≤ 3.6 V,

Master transmitter mode,

1.7 V ≤ V

SPI1,4,5,6

≤ 3.6 V,

Slave full duplex mode,

2.7 V ≤ V

SPI1,4,5,6

≤ 3.6 V,

Slave transmitter mode,

1.71 V ≤ V

SPI1,4,5,6

≤ 3.6 V,

Slave transmitter mode,

2.7 V ≤ V

SPI1,4,5,6

≤ 3.6 V,

Slave mode,

1.71 V ≤ V

SPI2,3

≤ 3.6 V, -

Duty cycle of SPI clock frequency

Slave mode 30

Typ

Max

(2)

22.5

Unit

MHz

142/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 64. SPI dynamic characteristics (1) (continued)

Parameter Conditions Min Typ Max (2) Unit t w(SCKH) t w(SCKL) t su(NSS) t h(NSS) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO

) t dis(SO)

SCK high and low time Master mode, SPI presc = 2

NSS setup time

NSS hold time

Data input setup time

Data input hold time

Slave mode, SPI presc = 2

Master mode

Slave mode

Master mode

Slave mode

Data output access time Slave mode, SPI presc = 2

Data output disable time Slave mode

PCLK

4 T

2 T

PCLK

− 1.5

PCLK

+1.5

12 t v(SO)

Data output valid time

Slave mode,

2.7 V ≤ V

≤ 3.6 V

Slave mode,

1.71 V ≤ V

≤ 3.6 V

Data output hold time Slave mode

11.5

t h(SO) t v(MO) t h(MO)

Data output valid time

Data output hold time

Master mode

4.5

1. Guaranteed based on test during characterization.

2. Maximum frequency in Slave transmitter mode is determined by the sum of t having t su(MI)

= 0 while Duty(SCK) = 50% v(SO)

and t su(MI)

, which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master ns

DS11118 Rev 7 143/220

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Electrical characteristics

Figure 42. SPI timing diagram - slave mode and CPHA = 0

STM32F479xx

NSS input tc(SCK) tSU(NSS)

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tw(SCKH) tw(SCKL) ta(SO)

MISO

OUT P UT tsu(SI)

MOSI

I NPUT tv(SO)

MS B O UT

M SB IN th(SI) th(SO)

BI T6 OUT

B I T1 IN tr(SCK) tf(SCK)

LSB OUT tdis(SO)

LSB IN th(NSS)

Figure 43. SPI timing diagram - slave mode and CPHA = 1

(1)

NSS input t

SU(NSS)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t a(SO)

MISO

OUTPUT

MOSI

INPUT t su(SI) t v(SO)

MSB OUT t h(SI)

MSB IN t c(SCK) t h(SO)

BIT6 OUT

BIT 1 IN t h(NSS) t r(SCK) t f(SCK) t dis(SO)

LSB OUT

LSB IN ai14134c ai14135b

144/220 DS11118 Rev 7

STM32F479xx

Figure 44. SPI timing diagram - master mode (1)

Electrical characteristics

NSS input

High

CPHA= 0

CPOL=0

CPHA= 0

CPOL=1 tc(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1

MISO

INP UT

MOSI

OUTUT tsu(MI) tw(SCKH) tw(SCKL)

MS BIN th(MI)

M SB OUT tv(MO)

BI T6 IN

B I T1 OUT th(MO) tr(SCK) tf(SCK)

LSB IN

LSB OUT ai14136

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191

Electrical characteristics STM32F479xx

I

S interface characteristics

Unless otherwise specified, the parameters given in

Table 65 for the I

2 S interface are derived from tests performed under the ambient temperature, f

PCLKx frequency and V

, with the following configuration:

 output speed set to OSPEEDRy[1:0] = 10

 capacitive load C = 30 pF

 measurement points at CMOS levels: 0.5 V

for more details on the input/output alternate function characteristics

(CK, SD, WS).

Symbol Parameter

Table 65. I

S dynamic characteristics

(1)

Conditions f

MCK

I2S main clock output f

I2S clock frequency

Master data

Slave data

CK t v(WS) t h(WS)

I2S clock frequency duty cycle Slave receiver

WS valid time Master mode

WS hold time Master mode

Slave mode t su(WS)

WS setup time

Slave mode

PCM short pulse mode

(3)

Slave mode t h(WS)

WS hold time

Slave mode

PCM short pulse mode

conditions summarized in Table 17

t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed based on test during characterization.

2. 128xFs maximum is 24.756 MHz (APB1 Maximum frequency).

3. Measurement done with respect to I2S_CK rising edge.

1.5

Min Max

256x8K 256xFs (2)

3.5

64xFs

3.5

0.5

1 -

2.50

Unit

MHz

% ns

Note: Refer to the I2S section of RM0386 reference manual for more details on the sampling frequency (F

). f

MCK

, f

, and D

values reflect only the digital peripheral behavior, source clock precision might slightly change the values. The values of these parameters might be slightly impacted by the source clock precision. D

depends mainly on the value of ODD bit. The digital

146/220 DS11118 Rev 7

STM32F479xx Electrical characteristics contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of

(I2SDIV+ODD)/(2*I2SDIV+ODD). F

maximum value is supported for each mode/condition.

Figure 45. I 2 S slave timing diagram (Philips protocol) (1) tc(CK)

CPOL = 0

CPOL = 1 tw(CKH) tw(CKL) th(WS)

WS input

SDtransmit tsu(WS)

LSB transmit

(2) tsu(SD_SR)

LSB receive

(2)

MSB transmit

MSB receive tv(SD_ST)

Bitn transmit th(SD_SR)

Bitn receive th(SD_ST)

LSB transmit

LSB receive SDreceive ai14881b

1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 46. I 2 S master timing diagram (Philips protocol) (1) tf(CK) tr(CK) tc(CK)

CPOL = 0 tw(CKH)

CPOL = 1 tv(WS) tw(CKL) th(WS)

WS output

SDtransmit

LSB transmit

(2) tsu(SD_MR)

LSB receive

(2)

MSB transmit

MSB receive tv(SD_MT)

Bitn transmit th(SD_MR)

Bitn receive th(SD_MT)

LSB transmit

LSB receive SDreceive ai14884b

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

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Electrical characteristics STM32F479xx

SAI characteristics

Unless otherwise specified, the parameters given in

Table 66

for SAI are derived from tests performed under the ambient temperature, f

PCLKx

frequency and V

, with the following configuration:

supply voltage

 output speed set to OSPEEDRy[1:0] = 10

 capacitive load C=30 pF

 measurement points at CMOS levels: 0.5 V

Table 72 for ULPI are derived from

for more details on the input/output alternate

characteristics (SCK, SD, WS).

function

Table 66. SAI characteristics

(1)

Symbol Parameter Conditions f

MCKL f

SAI main clock output

SAI clock frequency

(2)

Master data: 32 bits

Slave data: 32 bits t v(FS) t su(FS) t h(FS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR)

FS valid time

FS setup time

FS hold time

Data input setup time

Data input hold time

Master mode,

2.7 V ≤ V

≤ 3.6 V

Master mode,

1.71 V ≤ V

≤ 3.6 V

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver t h(SD_B_ST)

Data output valid time

Slave transmitter (after enable edge),

2.7 V ≤ V

≤ 3.6 V

Slave transmitter (after enable edge),

1.71 V ≤ V

≤ 3.6 V

Slave transmitter (after enable edge) t h(SD_B_ST)

Data output hold time t v(SD_A_MT)

Data output valid time

Master transmitter (after enable edge),

2.7 V ≤ V

≤ 3.6 V

Master transmitter (after enable edge),

1.71 V ≤ V

≤ 3.6 V

Data output hold time Master transmitter (after enable edge) t h(SD_A_MT)

1. Guaranteed based on test during characterization.

2. APB clock frequency must be at least twice SAI clock frequency.

3. With Fs = 192 kHz.

256 x 8K

256xFs

128xFs

(3)

128xFs

MHz ns

148/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 47. SAI master timing waveforms

1/fSCK

SAI_SCK_X th(FS)

SAI_FS_X

(output)

SAI_SD_X

(transmit) tv(FS)

SAI_SD_X

(receive) tsu(SD_MR) tv(SD_MT)

Slot n th(SD_MR)

Slot n+2

Slot n th(SD_MT)

MS32771V1

Figure 48. SAI slave timing waveforms

1/fSCK

SAI_SCK_X tw(CKH_X)

SAI_FS_X

(input)

SAI_SD_X

(transmit) tsu(FS)

SAI_SD_X

(receive) tw(CKL_X) th(FS) tsu(SD_SR) tv(SD_ST)

Slot n th(SD_SR)

Slot n

Slot n+2 th(SD_ST)

MS32772V1

DS11118 Rev 7 149/220

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Electrical characteristics

Note:

STM32F479xx

USB OTG full speed (FS) characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.

Symbol

Table 67. USB OTG full speed startup time

Parameter t

STARTUP

(1)

USB OTG full speed transceiver startup time

1. Guaranteed by design.

Max

Unit

µs

Symbol

Table 68. USB OTG full speed DC electrical characteristics

Parameter Conditions Min.

(1) Typ. Max.

(1) Unit

USB OTG full speed transceiver operating voltage

Input levels

(3)

Differential input sensitivity

Output levels

(3)

Differential common mode range

(3)

Single ended receiver threshold

Static output level low

Static output level high

PA11, PA12, PB14, PB15

(USB_FS_DP/DM,

USB_HS_DP/DM)

PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

PA12, PB15 (USB_FS_DP,

USB_HS_DP)

PU PA9, PB13

(OTG_FS_VBUS,

OTG_HS_VBUS)

I(USB_FS_DP/DM,

USB_HS_DP/DM)

Includes V

of 1.5 k Ω to 3.6 V (4)

of 15 k Ω to V

(4)

= V

= V range

3.0

0.2

0.8

1.3

2.8

(2)

0.65

1.5

0.25

1.1

1.8

0.37

3.6

2.5

2.0

0.3

3.6

2.0

2.1

0.55

1. All the voltages are measured from the local ground potential.

2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics, which are degraded in the 2.7 to 3.0 V V

voltage range.

3. Guaranteed by design.

4. R

is the load connected on the USB OTG full speed drivers.

Ω

When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state

(floating input), not as alternate function. A typical 200 µA current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 and PB13 when the feature is enabled.

150/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 49. USB OTG full speed timings: definition of data signal rise and fall time

Cross over points

Differential data lines

CRS

SS t f t r ai14137b

Table 69. USB OTG full speed electrical characteristics (1)

Driver characteristics

Symbol t r t f t rfm

CRS

DRV

Rise time

Fall time

(2)

Parameter

Rise/ fall time matching

Output signal crossover voltage

Output driver impedance

(3)

Conditions

= 50 pF

= 50 pF t r

/ t f

Driving high or low

Min

1.3

Max

110

2.0

Unit

1. Guaranteed by design.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver. ns



USB high speed (HS) characteristics

Unless otherwise specified, the parameters given in

tests performed under the ambient temperature, f

HCLK and V

frequency summarized in

Table 71

supply voltage conditions summarized in

Table 70 , with the following configuration:

 output speed set to OSPEEDRy[1:0] = 11, unless otherwise specified

 capacitive load C = 20 pF / 15 pF, unless otherwise specified

 measurement points at CMOS levels: 0.5 V

Table 17 , with the following

for more details on the input/output characteristics.

Symbol

Table 70. USB HS DC electrical characteristics

Parameter

Input level V

USB OTG HS operating voltage

1. All the voltages are measured from the local ground potential.

Min.

(1)

1.7

Max.

(1)

3.6

Unit

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191

Electrical characteristics STM32F479xx

Symbol

Table 71. USB HS clock timing parameters (1)

Parameter t t t t

START_8BIT

STEADY

START_8BIT

STEADY

START_DEV

START_HOST

PREP

STEADY f

HCLK

value to guarantee proper operation of

USB HS interface

Frequency (first transition) 8-bit ±10%

Frequency (steady state) ±500 ppm

Duty cycle (first transition) 8-bit ±10%

Duty cycle (steady state) ±500 ppm

Time to reach the steady state frequency and duty cycle after the first transition

Clock startup time after the de-assertion of SuspendM

Peripheral

Host

PHY preparation time after the first transition of the input clock

1. Guaranteed by design.

Min

59.97

49.975

Typ

Figure 50. ULPI timing diagram

Clock

Control In

(ULPI_DIR,

ULPI_NXT) data In

(8-bit) tSC tSD tHC tHD tDC tDC

Control out

(ULPI_STP) data out

(8-bit) tDD

Max Unit

1.4

5.6

60.03

50.025

MHz

% ms ms

µs ai17361c

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STM32F479xx Electrical characteristics

Symbol t

SC t

HC t

SD t

Table 72. Dynamic characteristics: USB ULPI (1)

Parameter Conditions Min.

Typ.

Max. Unit

Control in (ULPI_DIR, ULPI_NXT) setup time

Control in (ULPI_DIR, ULPI_NXT) hold time

Data in setup time

Data in hold time

2.0

1.5

1.0

Data/control output delay

2.7 V < V

< 3.6 V,

= 20 pF

2.7 V < V

< 3.6 V,

= 15 pF and

-40 < T < 125°C

1.7 V < V

< 3.6 V,

= 15 pF and

-40 < T < 90°C

7.5

9.0

12.0

11.5

1. Guaranteed based on test during characterization.

Ethernet characteristics

Unless otherwise specified, the parameters given in

Table 73 ,

Table 74 and Table 75

for

SMI, RMII and MII are derived from tests performed under the ambient temperature, f

HCLK frequency and V

DD configuration:

supply voltage conditions summarized in

 Output speed is set to OSPEEDRy[1:0] = 10

 Capacitive load C = 30 pF

 Measurement points are done at CMOS levels: 0.5 V

Table 73 gives the list of Ethernet MAC signals for the SMI (station management interface)

for more details on the input/output characteristics.

and Figure 51

shows the corresponding timing diagram.

Figure 51. Ethernet SMI timing diagram tMDC

ETH_MDC td(MDIO)

ETH_MDIO(O) tsu(MDIO) th(MDIO)

ETH_MDIO(I)

MS31384V1

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191

Electrical characteristics STM32F479xx

Symbol

Table 73. Dynamics characteristics: Ethernet MAC signals for SMI (1)

Parameter Min Typ Max t

MDC

T d(MDIO) t su(MDIO) t h(MDIO)

MDC cycle time(2.38 MHz)

Write data valid time

Read data setup time

Read data hold time

1. Guaranteed based on test during characterization.

400

HCLK

- 1

12.5

400

HCLK

403

HCLK

+ 1.5

Unit ns

Table 74

gives the list of Ethernet MAC signals for the RMII and Figure 52 shows the

corresponding timing diagram.

Figure 52. Ethernet RMII timing diagram

RMII_REF_CLK t d(TXEN) t d(TXD)

RMII_TX_EN

RMII_TXD[1:0] t su(RXD) t su(CRS)

RMII_RXD[1:0]

RMII_CRS_DV t ih(RXD) t ih(CRS) ai15667

154/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 74. Dynamics characteristics: Ethernet MAC signals for RMII (1)

Parameter Min Typ Max t su(RXD) t ih(RXD) t su(CRS) t ih(CRS) t d(TXEN) t d(TXD)

Receive data setup time

Receive data hold time

Carrier sense setup time

Carrier sense hold time

Transmit enable valid delay time

Transmit data valid delay time

1. Guaranteed based on test during characterization.

2.5

2.0

0.5

1.5

5.5

6.0

6.5

Unit ns

Table 75

gives the list of Ethernet MAC signals for MII and Figure 52 shows the

corresponding timing diagram.

Figure 53. Ethernet MII timing diagram

MII_RX_CLK

MII_RXD[3:0]

MII_RX_DV

MII_RX_ER t su(RXD) t su(ER) t su(DV)

MII_TX_CLK t ih(RXD) t ih(ER) t ih(DV) t t d(TXEN) d(TXD)

MII_TX_EN

MII_TXD[3:0] ai15668

Symbol

Table 75. Dynamics characteristics: Ethernet MAC signals for MII

(1)

Parameter Min Typ Max t su(RXD) t ih(RXD) t su(DV) t ih(DV) t su(ER) t ih(ER) t d(TXEN) t d(TXD)

Receive data setup time

Receive data hold time

Data valid setup time

Data valid hold time

Error setup time

Error hold time

Transmit enable valid delay time

Transmit data valid delay time

1. Guaranteed based on test during characterization.

2.5

Unit ns

DS11118 Rev 7 155/220

191

Electrical characteristics STM32F479xx

CAN (controller area network) interface

Table 76 are derived from tests

for more details on the input/output alternate function characteristics

(CANx_TX and CANx_RX).

Unless otherwise specified, the parameters given in

performed under the ambient temperature, f

conditions summarized in Table 17

PCLK2 frequency and V

DDA

supply voltage

Symbol

DDA

REF+

REFf

ADC f

TRIG

(2)

AIN

Parameter

Power supply

Positive reference voltage

Negative reference voltage

ADC clock frequency

External trigger frequency

Conversion voltage range

(3)

AIN

(2)

ADC

(2)(4)

External input impedance

Sampling switch resistance

ADC

(2)

Internal sample and hold capacitor

Table 76. ADC characteristics

Conditions Min

DDA

 V

REF+

< 1.2 V

DDA

= 1.7

to 2.4 V

DDA

= 2.4 to 3.6 V f

ADC

= 30 MHz,

12-bit resolution

1.7

(1)

1.7

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2

0.6

Details in Equation 1

SSA or V

REFtied to ground)

t lat

(2) t latr

(2) t

STAB

(2)

Injection trigger conversion latency

Regular trigger conversion latency

Sampling time

Power-up time f

ADC

= 30 MHz

ADC

= 30 MHz f

ADC

= 30 MHz

0.100

Typ

Max

3.6

DDA

1764

REF+

Unit

MHz kHz

1/f

ADC

7 k  k  pF

0.100

(5)

0.067

(5)

µs

1/f

ADC

µs

1/f

ADC

µs

480 1/f

ADC

3 µs

156/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol Parameter

Table 76. ADC characteristics (continued)

Conditions Min Typ Max Unit t

CONV

(2) f

(2)

Total conversion time

(including sampling time)

Sampling rate

ADC

= 30 MHz, and t

= 3 ADC cycles) f

ADC

= 30 MHz

12-bit resolution f

ADC

= 30 MHz

10-bit resolution f

ADC

= 30 MHz

8-bit resolution

0.50

0.43

0.37

16.40

16.34

16.27

ADC

= 30 MHz

6-bit resolution

0.30

16.20

9 to 492

for sampling +n-bit resolution for successive approximation)

12-bit resolution

Single ADC

12-bit resolution

Interleave Dual ADC mode

12-bit resolution

Interleave Triple ADC mode

3.75

1/f

µs

ADC

Msps

VREF+

(2)

VDDA

(2)

ADC V

REF

DC current consumption in conversion mode

ADC V

DDA

DC current consumption in conversion mode

300

1.6

500

1.8

1. V

DDA

2. Based on test during characterization.

3. V

REF+

is internally connected to V

DDA

and V

REF-

is internally connected to V

SSA

4. R

ADC

maximum value is given for V

=1.7 V, and minimum value for V

=3.3 V.

5. For external triggers, a delay of 1/f

PCLK2

must be added to the latency specified in Table 76 .

µA mA

Equation 1: R

AIN

max formula

RAIN =





 ln  2 

– RADC

The above formula ( Equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.

DS11118 Rev 7 157/220

191

Electrical characteristics STM32F479xx

Symbol

Table 77. ADC static accuracy at f

ADC

= 18 MHz (1)

Parameter Test conditions Typ Max

(2)

ET Total unadjusted error ±3 ±4

Offset error

Gain error

Differential linearity error f

ADC

=18 MHz

DDA

= 1.7 to 3.6 V

REF

= 1.7 to 3.6 V

DDA

 V

REF

< 1.2 V

±2

±1

EL Integral linearity error ±2 ±3

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Based on test during characterization.

±3

±2

Unit

LSB

Symbol

Table 78. ADC static accuracy at f

ADC

= 30 MHz (1)

Parameter Test conditions Typ Max

(2)

Total unadjusted error

Offset error

Gain error

Differential linearity error

Integral linearity error f

ADC

AIN

DDA

REF

= 30 MHz,

< 10 k  ,

DDA

= 2.4 to 3.6 V,

= 1.7 to 3.6 V,

 V

REF

< 1.2 V

±2

±1.5

±1

±1.5

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Based on test during characterization.

±5

±2.5

±3

±2

±3

Symbol

Table 79. ADC static accuracy at f

ADC

= 36 MHz

(1)

Parameter Test conditions Typ Max

(2)

ET Total unadjusted error ±4 ±7

Offset error

Gain error

Differential linearity error f

ADC

=36 MHz,

DDA

= 2.4 to 3.6 V,

REF

= 1.7 to 3.6 V

DDA

 V

REF

< 1.2 V

±2

±3

±2

±3

±6

±3

EL Integral linearity error ±3

1. Better performance could be achieved in restricted V

, frequency and temperature ranges.

2. Based on test during characterization.

±6

Unit

LSB

Unit

LSB

158/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 80. ADC dynamic accuracy at f

ADC

= 18 MHz - limited test conditions (1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to-noise and distortion ratio

Signal-to-noise ratio

Total harmonic distortion

1. Guaranteed based on test during characterization.

ADC

=18 MHz

DDA

= V

REF+

= 1.7 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.3

10.4

64 64.2

64 65

− 67 − 72

Symbol

Table 81. ADC dynamic accuracy at f

ADC

= 36 MHz - limited test conditions

(1)

Parameter Test conditions Min Typ Max Unit bits ENOB

SINAD

SNR

THD

Effective number of bits

Signal-to noise and distortion ratio

Signal-to noise ratio

Total harmonic distortion

1. Guaranteed based on test during characterization.

ADC

=36 MHz

DDA

= V

REF+

= 3.3 V

Input Frequency = 20 KHz

Temperature = 25 °C

10.6

10.8

66 67

64 68

− 70 − 72

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I

INJ(PIN)

Section 5.3.20

does not affect the ADC accuracy.

and  I

INJ(PIN)

DS11118 Rev 7 159/220

191

Electrical characteristics STM32F479xx

Figure 54. ADC accuracy characteristics

[1LSB IDEAL =

V REF+

4096

V DDA

(or depending on package)]

4096

4095

4094

4093

(2)

EO EL

1L SBIDEAL

(3)

(1)

VSSA

1 2 3 456 7 4093 4094 4095 4096

VDDA

1. See also Table 78 .

2. Example of an actual transfer curve.

3. Ideal transfer curve.

4. End point correlation line.

5. E

= Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset Error: deviation between the first actual transition and the first ideal one.

EG = Gain Error: deviation between the last ideal transition and the last actual one.

ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.

EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

Figure 55. Typical connection diagram using the ADC ai14395c

VAIN

RAIN(1)

AINx

Cparasitic

VDD

0.6 V

IL±1 μA

STM32F

Sample and hold ADC converter

RADC(1)

12-bit converter

CADC(1) ai17534

1. Refer to Table 76 for the values of R

AIN

, R

ADC

and C

ADC

2. C f pad capacitance (roughly 5 pF). A high C

ADC

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

should be reduced.

parasitic

value downgrades conversion accuracy. To remedy this,

160/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 56

Figure 57

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 56. Power supply and reference decoupling (V

REF+ not connected to V

DDA

)

STM32F

VREF+

(1)

1 μF // 10 nF

VDDA

1 μF // 10 nF

VSSA/VREF+

(1)

MS38278V1

1. V

REF+

and V

REF– inputs are both available on UFBGA176 and TFBGA216. V

LQFP176 and LQFP208. When V and V

SSA

REF+

and V

REF–

REF+

is also available on are not available, they are internally connected to V

DDA

Figure 57. Power supply and reference decoupling (V

REF+ connected to V

DDA

)

STM32F

VREF+/VDDA

(1)

1 μF // 10 nF

VREF-/VDDA

(1)

MS38279V1

1. V

REF+

and V

REF– inputs are both available on UFBGA176 and TFBGA216. V

LQFP176 and LQFP208. When V and V

SSA

REF+

and V

REF–

REF+

is also available on are not available, they are internally connected to V

DDA

DS11118 Rev 7 161/220

191

Electrical characteristics STM32F479xx

5.3.25 Temperature sensor characteristics

Symbol

Table 82. Temperature sensor characteristics

Parameter Min Typ Max

(1)

Avg_Slope

(1)

(1) t

START

(2)

S_temp

(2)

SENSE

linearity with temperature

Average slope

Voltage at 25 °C

Startup time

ADC sampling time when reading the temperature (1 °C accuracy)

1. Based on test during characterization.

2. Guaranteed by design.

 1

2.5

0.76

 2

Unit

°C mV/°C

µs

Symbol

Table 83. Temperature sensor calibration values

Parameter Memory address

TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, V

DDA

= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D

TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, V

DDA

= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F

5.3.26 V

BAT

monitoring characteristics

Symbol

Table 84. V

BAT

monitoring characteristics

Parameter Min

(1)

S_vbat

(2)(2)

Resistor bridge for V

BAT

Ratio on V

BAT

measurement

Error on Q

ADC sampling time when reading the V

BAT

1 mV accuracy

1. Guaranteed by design.

2. Shortest sampling time can be determined in the application by multiple iterations.

–1

Typ

Max

Unit

K 

µs

The parameters given in

Table 85 are derived from tests performed under ambient

temperature and V

supply voltage conditions summarized in

Symbol Parameter

Table 85. internal reference voltage

Conditions Min Typ Max

REFINT

S_vrefint

(1)

RERINT_s

(2)

Internal reference voltage

ADC sampling time when reading the internal reference voltage

Internal reference voltage spread over the temperature range

–40 °C < T

< +105 °C 1.18

1.21

1.24

= 3V  10mV

Unit

µs mV

162/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 85. internal reference voltage (continued)

Parameter Conditions Min Typ

Coeff

(2) t

START

(2)

Temperature coefficient

Startup time

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design

Max Unit

50 ppm/°C

10 µs

Symbol

REFIN_CAL

Table 86. Internal reference voltage calibration values

Parameter Memory address

Raw data acquired at temperature of 30 °C

VDDA

= 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B

Symbol

DDA

REF+

SSA

LOAD

(2)

LOAD

(2)

Parameter

Table 87. DAC characteristics

Min Typ

Analog supply voltage 1.7

(1)

Reference supply voltage 1.7

minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.19.2

Ground 0

Resistive load with buffer ON 5 -

Max Unit

3.6

Impedance output with buffer

OFF

Capacitive load -

Comments

V -

V V

REF+

 V

DDA

V k  k  pF

When the buffer is OFF, the Minimum resistive load between DAC_OUT and

to have a 1% accuracy is 1.5 M 

Maximum capacitive load at DAC_OUT pin (when the buffer is ON).

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer ON

0.2 -

DDA

0.2

−

It gives the maximum output excursion of the DAC.

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at V

REF+

= 3.6 V and

(0x1C7) to (0xE38) at V

REF+

= 1.7 V

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer ON

DAC_OUT min

(2)

Lower DAC_OUT voltage with buffer OFF

DAC_OUT max

(2)

Higher DAC_OUT voltage with buffer OFF

VREF+

(4)

DAC DC V

REF

current consumption in quiescent mode (Standby mode)

0.5

170

REF+

−

1LSB mV

It gives the maximum output excursion of the DAC.

240

µA

With no load, worst code (0x800) at

REF+

= 3.6 V in terms of DC consumption on the inputs

With no load, worst code (0xF1C) at

REF+

= 3.6 V in terms of DC consumption on the inputs

DS11118 Rev 7 163/220

191

Electrical characteristics STM32F479xx

Symbol

DDA

(4)

Parameter

Table 87. DAC characteristics (continued)

DAC DC VDDA current consumption in quiescent mode

(3)

Min Typ

280

475

Max Unit

380

625

µA

Comments

With no load, middle code (0x800) on the inputs

With no load, worst code (0xF1C) at

REF+

= 3.6 V in terms of DC consumption on the inputs

DNL

INL

(4)

Differential non linearity

Difference between two consecutive code-1LSB)

Integral non linearity

(difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)

±0.5

±2

±1

±4

LSB Given for the DAC in 10-bit configuration.

LSB Given for the DAC in 12-bit configuration.

LSB Given for the DAC in 10-bit configuration.

LSB Given for the DAC in 12-bit configuration.

Offset

(4)

Offset error

(difference between measured value at Code

(0x800) and the ideal value =

REF+

/2) -

±10

±3 mV Given for the DAC in 12-bit configuration

LSB

Given for the DAC in 10-bit at V

REF+

3.6 V

±12 LSB

Given for the DAC in 12-bit at V

REF+

3.6 V

Gain error

(4)

Gain error t

SETTLING

(4)

Settling time (full scale: for a

10-bit input code transition between the lowest and the highest input codes when

DAC_OUT reaches final value ±4LSB

THD

(4)

Update rate

(2)

Total Harmonic Distortion

Buffer ON

Max frequency for a correct

DAC_OUT change when small variation in the input code (from code i to i+1LSB)

±0.5

µs dB

MS/s

Given for the DAC in 12-bit configuration

LOAD









50 pF,

5 k



50 pF,



 50 pF,

 5 k  t

WAKEUP

(4)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

PSRR+

(2)

Power supply rejection ratio

(to V

DDA

) (static DC measurement)

6.5

–67 –40

µs

LOAD

 50 pF, R

LOAD

 5 k  input code between lowest and highest possible ones.

LOAD

, C

LOAD

= 50 pF

1. V

DDA

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.

4. Guaranteed based on test during characterization.

164/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 58. 12-bit buffered/non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

R

DAC_OUTx 12-bit digital to analog converter

C

L ai17157V2

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

Unless otherwise specified, the parameters given in Tables

88 through

101 for the FMC

interface are derived from tests performed under the ambient temperature, f

HCLK and V

DD frequency

supply voltage conditions summarized in

Table 17

, with the following configuration:

 Output speed is set to OSPEEDRy[1:0] = 11

 Measurement points are done at CMOS levels: 0.5 V

represent asynchronous waveforms, and Tables 88 through

for more details on the input/output characteristics.

Asynchronous waveforms and timings

Figures 59 through

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

 AddressSetupTime = 0x1

 AddressHoldTime = 0x1

 DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)

 BusTurnAroundDuration = 0x0

 Capacitive load C

= 30 pF

DS11118 Rev 7 165/220

191

Electrical characteristics STM32F479xx

Figure 59. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms t w(NE)

FMC_NE t v(NOE_NE) t w(NOE) t h(NE_NOE)

FMC_NOE

FMC_NWE

FMC_A[25:0] t v(A_NE) t v(BL_NE)

Address t h(A_NOE) t h(BL_NOE)

FMC_NBL[1:0] t h(Data_NE) t h(Data_NOE)

FMC_D[15:0] t su(Data_NOE) t su(Data_NE)

Data t v(NADV_NE) t w(NADV)

FMC_NADV (1)

FMC_NWAIT

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

th(NE_NWAIT) tsu(NWAIT_NE)

MS32753V1

166/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings (1)

Symbol Parameter Min Max Unit t w(NE) t v(NOE_NE) t w(NOE) t h(NE_NOE) t v(A_NE) t h(A_NOE) t v(BL_NE) t h(BL_NOE) t su(Data_NE) t su(Data_NOE) t h(Data_NOE) t h(Data_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NOE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NOE high

Data to FMC_NEx high setup time

Data to FMC_NOEx high setup time

Data hold time after FMC_NOE high

Data hold time after FMC_NEx high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. Based on test during characterization.

HCLK

− 0.5

2 T

HCLK

+0.5

0 1

HCLK

+ 0.5

HCLK

+ 2.5

HCLK

+1 ns

Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings

(1)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time 7T

HCLK

+0.5

HCLK

+1 t t t w(NOE) su(NWAIT_NE) h(NE_NWAIT)

FMC_NWE low time

FMC_NEx hold time after FMC_NWAIT invalid

HCLK

− 1.5

HCLK

FMC_NWAIT valid before FMC_NEx high 5T

HCLK

+1.5

HCLK

+1 -

1. Based on test during characterization.

DS11118 Rev 7 167/220

191

Electrical characteristics STM32F479xx

Figure 60. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE)

FMC_NEx

FMC_NOE

FMC_NWE

FMC_A[25:0]

FMC_NBL[1:0]

FMC_D[15:0] tv(NWE_NE) tw(NWE) tv(A_NE) tv(BL_NE) tv(Data_NE) th(A_NWE)

Address th(BL_NWE)

NBL th(Data_NWE)

Data t v(NADV_NE) tw(NADV) t h(NE_NWE)

FMC_NADV (1)

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32754V1

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings (1)

Symbol Parameter

t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t h(A_NWE) t v(BL_NE) t h(BL_NWE) t v(Data_NE) t h(Data_NWE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

Address hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_BL hold time after FMC_NWE high

Data to FMC_NEx low to Data valid

Data hold time after FMC_NWE high

FMC_NEx low to FMC_NADV low

FMC_NADV low time

1. Based on test during characterization.

Min Max

HCLK

− 0.5

HCLK

+ 0.5

HCLK

+1.5

HCLK

+ 0.5

HCLK

+0.5

HCLK

+0.5

1.5

HCLK

+ 2

HCLK

+0.5

0.5

HCLK

+ 0.5

Unit

168/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings (1)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time t w(NWE) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Based on test during characterization.

HCLK

+1 8T

HCLK

− 1 6T

HCLK

+1.5

HCLK

+1 ns

Figure 61. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE)

FMC_ NE tv(NOE_NE) t h(NE_NOE)

FMC_NOE tw(NOE)

FMC_NWE tv(A_NE) th(A_NOE)

FMC_ A[25:16]

Address tv(BL_NE) th(BL_NOE)

FMC_ NBL[1:0] NBL th(Data_NE)

FMC_ AD[15:0] t v(NADV_NE) t v(A_NE)

Address th(AD_NADV) tw(NADV) tsu(Data_NE) tsu(Data_NOE)

Data th(Data_NOE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32755V1

DS11118 Rev 7 169/220

191

Electrical characteristics STM32F479xx

Table 92. Asynchronous multiplexed PSRAM/NOR read timings (1)

Symbol Parameter Min Max t w(NE) t v(NOE_NE) t tw(NOE) t h(NE_NOE) t v(A_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NOE low

FMC_NOE low time

FMC_NOE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low t h(AD_NADV)

FMC_NADV low time

FMC_AD(address) valid hold time after

FMC_NADV high) t h(A_NOE) t h(BL_NOE) t v(BL_NE) t su(Data_NE) t su(Data_NOE) t h(Data_NE) t h(Data_NOE)

Address hold time after FMC_NOE high

FMC_BL time after FMC_NOE high

FMC_NEx low to FMC_BL valid

Data to FMC_NEx high setup time

Data to FMC_NOE high setup time

Data hold time after FMC_NEx high

Data hold time after FMC_NOE high

1. Based on test during characterization.

HCLK

− 1 3T

HCLK

+0.5

HCLK

− 0.5

HCLK

− 1 T

HCLK

1 -

0 2

HCLK

− 0.5

HCLK

+0.5

HCLK

− 0.5

HCLK

+1.5

HCLK

Unit ns

Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings

(1)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time 8T

HCLK

+0.5

HCLK

+2 t w(NOE) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Based on test during characterization.

HCLK

− 1 5T

HCLK

+1.5

HCLK

+1.5

HCLK

+1 -

170/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 62. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE)

FMC_ NEx

FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE)

FMC_NWE

FMC_ A[25:16]

FMC_ NBL[1:0]

FMC_ AD[15:0] t v(NADV_NE) tv(A_NE) tv(BL_NE) t v(A_NE)

Address th(A_NWE)

Address th(BL_NWE)

NBL tv(Data_NADV)

Data th(AD_NADV) tw(NADV) th(Data_NWE)

FMC_NADV

FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE)

MS32756V1

Symbol

Table 94. Asynchronous multiplexed PSRAM/NOR write timings (1)

Parameter Min Max t w(NE) t v(NWE_NE) t w(NWE) t h(NE_NWE) t v(A_NE) t v(NADV_NE) t w(NADV)

FMC_NE low time

FMC_NEx low to FMC_NWE low

FMC_NWE low time

FMC_NWE high to FMC_NE high hold time

FMC_NEx low to FMC_A valid

FMC_NEx low to FMC_NADV low

FMC_NADV low time t h(AD_NADV)

FMC_AD (address) valid hold time after FMC_NADV high t h(A_NWE) t h(BL_NWE) t v(BL_NE) t v(Data_NADV) t h(Data_NWE)

Address hold time after FMC_NWE high

FMC_BL hold time after FMC_NWE high

FMC_NEx low to FMC_BL valid

FMC_NADV high to Data valid

Data hold time after FMC_NWE high

1. Based on test during characterization.

HCLK

+0.5

HCLK

− 1 T

HCLK

+0.5

HCLK

+0.5

0.5

HCLK

− 0.5 T

HCLK

+ 0.5

HCLK

− 2 -

HCLK

− 2

HCLK

+0.5

HCLK

+1.5

Unit ns

DS11118 Rev 7 171/220

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Electrical characteristics STM32F479xx

Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings (1)

Symbol Parameter Min Max Unit t w(NE)

FMC_NE low time t w(NWE) t su(NWAIT_NE) t h(NE_NWAIT)

FMC_NWE low time

FMC_NWAIT valid before FMC_NEx high

FMC_NEx hold time after FMC_NWAIT invalid

1. Based on test during characterization.

HCLK

+1.5

HCLK

–1

HCLK

+0.5

HCLK

Synchronous waveforms and timings

Figures 63 through

represent synchronous waveforms and Table 96

through Table 99

provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

 BurstAccessMode = FMC_BurstAccessMode_Enable;

 MemoryType = FMC_MemoryType_CRAM;

 WriteBurst = FMC_WriteBurst_Enable;

 CLKDivision = 1;

 DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

 C

= 30 pF on data and address lines. C specified.

= 10 pF on FMC_CLK unless otherwise

In all timing tables, the T

HCLK

is the HCLK clock period:

 For 2.7 V ≤ V

≤ 3.6 V, maximum FMC_CLK = 90 MHz at C

= 30 pF (on FMC_CLK).

 For 1.71 V ≤ V

<1.9 V, maximum FMC_CLK = 60 MHz at C

= 10 pF (on FMC_CLK).

172/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 63. Synchronous multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx t d(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH)

AD[15:0] tsu(NWAITV-CLKH)

D1 th(CLKH-ADV) tsu(ADV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-ADV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-NWAITV) th(CLKH-NWAITV)

MS32757V1

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Electrical characteristics STM32F479xx

Symbol

Table 96. Synchronous multiplexed NOR/PSRAM read timings (1)

Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH_NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t d(CLKL-ADV) t d(CLKL-ADIV) t su(ADV-CLKH) t h(CLKH-ADV) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0..2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data before FMC_CLK high

FMC_A/D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Based on test during characterization.

HCLK

− 1

HCLK

− 0.5

HCLK

+0.5

0.5

Unit ns

174/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 64. Synchronous multiplexed PSRAM write timings tw(CLK) tw(CLK) BUSTURN = 0

FMC_CLK

Data latency = 0 td(CLKL-NExL) td(CLKH-NExH)

FMC_NEx td(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:16] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE td(CLKL-ADV)

FMC_AD[15:0] td(CLKL-ADIV) td(CLKL-Data)

AD[15:0] td(CLKL-Data)

D1 D2

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKH-NBLH)

FMC_NBL

MS32758V1

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Electrical characteristics STM32F479xx

Symbol

Table 97. Synchronous multiplexed PSRAM write timings (1)

Parameter Min Max t w(CLK) t d(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t

(CLKH-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-DATA) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period, V

range= 2.7 to 3.6 V

FMC_CLK low to FMC_NEx low (x=0…2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_CLK low to FMC_AD[15:0] valid

FMC_CLK low to FMC_AD[15:0] invalid

FMC_A/D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Based on test during characterization.

HCLK

− 1

HCLK

− 0.5

HCLK

− 0.5

1.5

Unit ns

176/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 65. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK)

FMC_CLK td(CLKL-NExL)

Data latency = 0 td(CLKH-NExH)

FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH)

FMC_NADV td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH)

FMC_NOE

FMC_D[15:0] tsu(DV-CLKH)

D1 th(CLKH-DV) tsu(DV-CLKH)

D2 th(CLKH-NWAITV) th(CLKH-DV)

FMC_NWAIT

(WAITCFG = 1b,

WAITPOL + 0b)

FMC_NWAIT

(WAITCFG = 0b,

WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV)

Table 98. Synchronous non-multiplexed NOR/PSRAM read timings (1)

Symbol Parameter Min Max t w(CLK) t

(CLKL-NExL) t d(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NOEL) t d(CLKH-NOEH) t su(DV-CLKH) t h(CLKH-DV) t

(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0…2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NOE low

FMC_CLK high to FMC_NOE high

FMC_D[15:0] valid data before FMC_CLK high

FMC_D[15:0] valid data after FMC_CLK high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Based on test during characterization.

HCLK

− 1

HCLK

− 0.5

HCLK

− 0.5

0.5

HCLK

MS32759V1

Unit ns

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Electrical characteristics STM32F479xx

Figure 66. Synchronous non-multiplexed PSRAM write timings tw(CLK)

FMC_CLK td(CLKL-NExL)

FMC_NEx tw(CLK)

Data latency = 0 td(CLKH-NExH) td(CLKL-NADVL)

FMC_NADV td(CLKL-NADVH) td(CLKL-AV) td(CLKH-AIV)

FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH)

FMC_NWE

FMC_D[15:0] td(CLKL-Data)

D1 td(CLKL-Data)

FMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH)

FMC_NBL td(CLKH-NBLH) th(CLKH-NWAITV)

178/220

Symbol

Table 99. Synchronous non-multiplexed PSRAM write timings

(1)

Parameter Min Max t

(CLK) t d(CLKL-NExL) t

(CLKH-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKH-AIV) t d(CLKL-NWEL) t d(CLKH-NWEH) t d(CLKL-Data) t d(CLKL-NBLL) t d(CLKH-NBLH) t su(NWAIT-CLKH) t h(CLKH-NWAIT)

FMC_CLK period

FMC_CLK low to FMC_NEx low (x=0…2)

FMC_CLK high to FMC_NEx high (x= 0…2)

FMC_CLK low to FMC_NADV low

FMC_CLK low to FMC_NADV high

FMC_CLK low to FMC_Ax valid (x=16…25)

FMC_CLK high to FMC_Ax invalid (x=16…25)

FMC_CLK low to FMC_NWE low

FMC_CLK high to FMC_NWE high

FMC_D[15:0] valid data after FMC_CLK low

FMC_CLK low to FMC_NBL low

FMC_CLK high to FMC_NBL high

FMC_NWAIT valid before FMC_CLK high

FMC_NWAIT valid after FMC_CLK high

1. Based on test during characterization.

HCLK

− 1

HCLK

− 0.5

HCLK

− 0.5

0.5

2.5

MS32760V1

Unit ns

DS11118 Rev 7

STM32F479xx Electrical characteristics

NAND controller waveforms and timings

Figures 67 through

70 represent synchronous waveforms, and Table 100 and Table 101

provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration:

 COM.FMC_SetupTime = 0x01;

 COM.FMC_WaitSetupTime = 0x03;

 COM.FMC_HoldSetupTime = 0x02;

 COM.FMC_HiZSetupTime = 0x01;

 ATT.FMC_SetupTime = 0x01;

 ATT.FMC_WaitSetupTime = 0x03;

 ATT.FMC_HoldSetupTime = 0x02;

 ATT.FMC_HiZSetupTime = 0x01;

 Bank = FMC_Bank_NAND;

 MemoryDataWidth = FMC_MemoryDataWidth_16b;

 ECC = FMC_ECC_Enable;

 ECCPageSize = FMC_ECCPageSize_512Bytes;

 TCLRSetupTime = 0;

 TARSetupTime = 0;

 Capacitive load C

= 30 pF.

In all timing tables, the T

HCLK

is the HCLK clock period.

Figure 67. NAND controller waveforms for read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE td(ALE-NOE) th(NOE-ALE)

FMC_NOE (NRE) tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32767V1

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Electrical characteristics STM32F479xx

Figure 68. NAND controller waveforms for write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE td(ALE-NWE) th(NWE-ALE)

FMC_NOE (NRE) tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32768V1

Figure 69. NAND controller waveforms for common memory read access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16)

FMC_NWE

FMC_NOE td(ALE-NOE) tw(NOE) th(NOE-ALE) tsu(D-NOE) th(NOE-D)

FMC_D[15:0]

MS32769V1

180/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 70. NAND controller waveforms for common memory write access

FMC_NCEx

ALE (FMC_A17)

CLE (FMC_A16) td(ALE-NOE)

FMC_NWE tw(NWE) th(NOE-ALE)

FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D)

FMC_D[15:0]

MS32770V1

Symbol t w(N0E) t su(D-NOE) t h(NOE-D) t d(ALE-NOE) t h(NOE-ALE)

Table 100. Switching characteristics for NAND Flash read cycles

Parameter

FMC_NOE low width

FMC_D[15-0] valid data before FMC_NOE high

FMC_D[15-0] valid data after FMC_NOE high

FMC_ALE valid before FMC_NOE low

FMC_NWE high to FMC_ALE invalid

Min Max

HCLK

− 0.5 4T

HCLK

+0.5

9 -

HCLK

− 2

HCLK

− 0.5

Unit ns

Table 101. Switching characteristics for NAND Flash write cycles

Symbol Parameter Min Max t w(NWE) t v(NWE-D) t h(NWE-D) t d(D-NWE) t d(ALE-NWE) t h(NWE-ALE)

FMC_NWE low width

FMC_NWE low to FMC_D[15-0] valid

FMC_NWE high to FMC_D[15-0] invalid

FMC_D[15-0] valid before FMC_NWE high

FMC_ALE valid before FMC_NWE low

FMC_NWE high to FMC_ALE invalid

HCLK

− 1

HCLK

− 3

HCLK

− 1

HCLK

− 0.5

Unit ns

SDRAM waveforms and timings

 C

= 30 pF on data and address lines.

 C

= 10 pF on FMC_SDCLK unless otherwise specified.

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Electrical characteristics STM32F479xx

In all timing tables, the T

HCLK

is the HCLK clock period.

 For 2.7 V ≤ V

FMC_SDCLK).

≤ 3.6 V, maximum FMC_SDCLK = 90 MHz, at C

= 30 pF (on

 For 1.71 V ≤ V

<1.9 V, maximum FMC_SDCLK = 75 MHz when CAS Latency = 3 and

60 MHz for CAS latency 1 or 2. C

= 10 pF (on FMC_SDCLK).

Figure 71. SDRAM read access waveforms (CL = 1)

FMC_SDCLK td(SDCLKL_AddR)

FMC_A[12:0] Row n td(SDCLKL_AddC) th(SDCLKL_AddR)

Col1 Col2 Coli th(SDCLKL_AddC)

Coln td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0] td(SDCLKL_NRAS)

FMC_SDNRAS th(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS

182/220

FMC_SDNWE

FMC_D[31:0] tsu(SDCLKH_Data)

Data1 th(SDCLKH_Data)

Data2 Datai Datan

MS32751V2

Symbol

Table 102. SDRAM read timings

(1)

Parameter Min t w(SDCLK) t su(SDCLKH _Data) t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL- SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)

FMC_SDCLK period

Data input setup time

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. Guaranteed based on test during characterization.

HCLK

− 0.5

Max

HCLK

+0.5

1.5

0.5

Unit ns

DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 103. LPSDR SDRAM read timings (1)

Parameter Min t

W(SDCLK) t su(SDCLKH_Data)

FMC_SDCLK period

Data input setup time t h(SDCLKH_Data) t d(SDCLKL_Add) t d(SDCLKL_SDNE) t h(SDCLKL_SDNE) t d(SDCLKL_SDNRAS t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t h(SDCLKL_SDNCAS)

Data input hold time

Address valid time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

1. Guaranteed based on test during characterization.

HCLK

− 0.5

2.5

Max

HCLK

+0.5

Figure 72. SDRAM write access waveforms

Unit ns

FMC_SDCLK td(SDCLKL_AddR)

FMC_A[12:0]

Row n td(SDCLKL_AddC) th(SDCLKL_AddR)

Col1 Col2 Coli th(SDCLKL_AddC)

Coln td(SDCLKL_SNDE) th(SDCLKL_SNDE)

FMC_SDNE[1:0] td(SDCLKL_NRAS)

FMC_SDNRAS th(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS)

FMC_SDNCAS td(SDCLKL_NWE) th(SDCLKL_NWE)

FMC_SDNWE td(SDCLKL_Data)

FMC_D[31:0] td(SDCLKL_NBL)

FMC_NBL[3:0]

Data1 Data2 Datai th(SDCLKL_Data)

Datan

MS32752V2

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Electrical characteristics STM32F479xx

Table 104. SDRAM write timings (1) t w(SDCLK) t d(SDCLKL _Data

) t h(SDCLKL _Data) t d(SDCLKL_Add) t d(SDCLKL_SDNWE) t h(SDCLKL_SDNWE) t d(SDCLKL_ SDNE) t h(SDCLKL-_SDNE) t d(SDCLKL_SDNRAS) t h(SDCLKL_SDNRAS) t d(SDCLKL_SDNCAS) t d(SDCLKL_SDNCAS) t d(SDCLKL_NBL) t h(SDCLKL_NBL)

FMC_SDCLK period

Data output valid time

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

NBL valid time

NBL output time

1. Guaranteed based on test during characterization.

Table 105. LPSDR SDRAM write timings (1)

HCLK

− 0.5

3.5

HCLK

+0.5

2.5

1.5

0.5

ns t w(SDCLK) t d(SDCLKL _Data

) t h(SDCLKL _Data) t d(SDCLKL_Add) t d(SDCLKL-SDNWE) t h(SDCLKL-SDNWE) t d(SDCLKL- SDNE) t h(SDCLKL- SDNE) t d(SDCLKL-SDNRAS) t h(SDCLKL-SDNRAS) t d(SDCLKL-SDNCAS) t d(SDCLKL-SDNCAS) t d(SDCLKL_NBL) t h(SDCLKL-NBL)

FMC_SDCLK period

Data output valid time

Data output hold time

Address valid time

SDNWE valid time

SDNWE hold time

Chip select valid time

Chip select hold time

SDNRAS valid time

SDNRAS hold time

SDNCAS valid time

SDNCAS hold time

NBL valid time

NBL output time

1. Guaranteed based on test during characterization.

HCLK

− 0.5

1.5

HCLK

+0.5

2.8

1.5

184/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Unless otherwise specified, the parameters given in Table 106 and

Table 107

for Quad-SPI are derived from tests performed under the ambient temperature, f

AHB

frequency and V

DD supply voltage conditions summarized in Table xx, with the following configuration:

 Output speed is set to OSPEEDRy[1:0] = 11

 Measurement points are done at CMOS levels: 0.5 V

, with the following configuration:

for more details on the input/output alternate function characteristics.

Symbol

F ck

1/t

(CK) t w(CKH) t w(CKL) t s(IN) t h(IN) t v(OUT)

Table 106. Quad-SPI characteristics in SDR mode

(1)

Parameter Test conditions Min

Quad-SPI clock frequency

2.7 V ≤ V

≤ 3.6 V, C

= 20 pF

1.71 V ≤ V

≤ 3.6 V, C

= 15 pF -

Quad-SPI clock high time t

(CK)

/2-1

Quad-SPI clock low time

(CK)

Data input set-up time

0.5

Data input hold time

Data output valid time t h(OUT)

Data output hold time

1. Guaranteed based on test during characterization.

2.5

Typ

Max

84 t

(CK)

/2 t

(CK)

/2+1

Unit

MHz ns t r(CK)

Figure 73. Quad-SPI SDR timing diagram t

(CK) t w(CKH) t w(CKL) t f(CK)

Clock

Data output t v(OUT)

D0 t h(OUT)

Data input

D0 t s(IN)

D1 t h(IN)

D1 D2

MSv36878V1

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Electrical characteristics STM32F479xx

Symbol

Table 107. Quad-SPI characteristics in DDR mode (1)

Parameter Test conditions Min Typ

F ck

1/t

(CK)

Quad-SPI clock frequency

2.7 V ≤ V

≤ 3.6 V,

= 20 pF

1.71 V ≤ V

≤

= 15 pF

3.6 V, t w(CKH) t w(CKL) t sr(IN) t sf(IN) t hr(IN) t hf(IN) t vr(OUT) t vf(OUT) t h(OUT) t f(OUT)

Quad-SPI clock high time

Quad-SPI clock low time

Data input set-up time

Data input hold time

Data output valid time

Data output hold time

2.7 V ≤ V

≤ 3.6 V

1.71 V ≤ V

≤ 3.6 V

2.7 V ≤ V

≤ 3.6 V

1.71 V ≤ V

≤ 3.6 V

DHHC=0

DHHC=1

Pres=1,2…

DHHC=0

DHHC=1

Pres=1,2…

1. Guaranteed based on test during characterization.

(CK)

/2-1 t

(CK)

0.5

4.5

T hclk

/2+0.5

8 t

(CK)

/2 t

(CK)

/2+1

10.5

T hclk

/2+2 T hclk

/2+2.5

Max

Unit

MHz ns t r(CK)

Figure 74. Quad-SPI DDR timing diagram t

(CK) t w(CKH) t w(CKL) t f(CK)

Clock

Data output

Data input t vf(OUT) t hr(OUT)

D0 t vr(OUT)

D1 t sf(IN) t hf(IN)

D1 D2

D3 t hf(OUT)

D4 t sr(IN) t hr(IN)

D4 D5

MSv36879V1

186/220

Unless otherwise specified, the parameters given in Table 108

for DCMI are derived from tests performed under the ambient temperature, f

HCLK

frequency and V voltage summarized in

Table 17 , with the following configuration:

supply

 DCMI_PIXCLK polarity: falling

 DCMI_VSYNC and DCMI_HSYNC polarity: high

 Data formats: 14 bits

 Capacitive load C = 30 pF

 Measurement points are done at CMOS levels: 0.5 V

DS11118 Rev 7

STM32F479xx Electrical characteristics

Symbol

Table 108. DCMI characteristics (1)

Parameter

Frequency ratio DCMI_PIXCLK/f

HCLK

DCMI_PIXCLK Pixel clock input

Pixel t su(DATA) t h(DATA) t su(HSYNC) t su(VSYNC) t h(HSYNC) t h(VSYNC)

Pixel clock input duty cycle

Data input setup time

Data input hold time

DCMI_HSYNC/DCMI_VSYNC input setup time

DCMI_HSYNC/DCMI_VSYNC input hold time

1. 1.Guaranteed based on test during characterization.

Min

3.5

Figure 75. DCMI timing diagram

1/DCMI_PIXCLK

DCMI_PIXCLK t su(HSYNC) t h(HSYNC)

DCMI_HSYNC t su(VSYNC) t h(HSYNC)

DCMI_VSYNC t su(DATA) t h(DATA)

DATA[0:13]

Max

0.4

Unit

MHz

% ns

MS32414V2

Unless otherwise specified, the parameters given in

Table 109

for LCD-TFT are derived from tests

performed under the ambient temperature, f

HCLK

frequency and VDD supply voltage summarized in

Table 17

 LCD_CLK polarity: high

 LCD_DE polarity: low

 LCD_VSYNC and LCD_HSYNC polarity: high

 Pixel formats: 24 bits

 Output speed is set to OSPEEDRy[1:0] = 11

 Capacitive load C

= 30 pF

 Measurement points are done at CMOS levels: 0.5 V

DS11118 Rev 7 187/220

191

Electrical characteristics STM32F479xx

Symbol

Table 109. LTDC characteristics (1)

Parameter f

CLK

CLK t w(CLKH) t w(CLKL) t v(DATA) t h(DATA) t v(HSYNC) t v(VSYNC) t v(DE) t h(HSYNC) t h(VSYNC) t h(DE)

LTDC clock output frequency

LTDC clock output duty cycle

Clock high time, low time

Data output valid time

Data output hold time

HSYNC/VSYNC/DE output valid time

HSYNC/VSYNC/DE output hold time

1. Based on test during characterization.

Min Max t w(CLK)

/ 2 - 0.5

t w(CLK)

/ 2 + 0.5

1.5

0.5

Unit

MHz

% ns

Figure 76. LCD-TFT horizontal timing diagram tCLK

LCD_CLK

LCD_VSYNC tv(HSYNC)

LCD_HSYNC tv(HSYNC) tv(DE) th(DE)

LCD_DE

LCD_R[0:7]

LCD_G[0:7]

LCD_B[0:7]

HSYNC width tv(DATA)

Pixel

Horizontal back porch th(DATA)

Active width

Pixel

Horizontal back porch

One line

MS32749V1

188/220 DS11118 Rev 7

STM32F479xx Electrical characteristics

Figure 77. LCD-TFT vertical timing diagram tCLK

LCD_CLK tv(VSYNC) tv(VSYNC)

LCD_VSYNC

LCD_R[0:7]

LCD_G[0:7]

LCD_B[0:7]

M lines data

VSYNC width

Vertical back porch

Active width Vertical back porch

One frame

MS32750V1

5.3.33 SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in

Table 110 for the SDIO/MMC interface

are derived from tests performed under the ambient temperature, f

PCLK2 frequency and V

, with the following configuration:

 Output speed is set to OSPEEDRy[1:0] = 11

 Capacitive load C = 30 pF

 Measurement points are done at CMOS levels: 0.5 V