STMicroelectronics ST72324K4 Datasheet

ST72324Jx ST72324Kx

5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH,

10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE

NOT FOR NEW DESIGN

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Memories

– 8 to 32K dual voltage High Density Flash (HD-

Flash) with read-out protection capability. In-

Application Programming and In-Circuit Programming for HDFlash devices

– 384 to 1K bytes RAM

– HDFlash endurance: 100 cycles, data retention: 20 years at 55°C

Clock, Reset And Supply Management

– Enhanced low voltage supervisor (LVD) for main supply with programmable reset thresholds and auxiliary voltage detector (AVD) with interrupt capability

– Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock

– PLL for 2x frequency multiplication

– Four Power Saving Modes: Halt, Active-Halt,

Wait and Slow

Interrupt Management

– Nested interrupt controller

– 10 interrupt vectors plus TRAP and RESET

– 9/6 external interrupt lines (on 4 vectors)

Up to 32 I/O Ports

– 32/24 multifunctional bidirectional I/O lines

– 22/17 alternate function lines

– 12/10 high sink outputs

4 Timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities

– Configurable watchdog timer

– 16-bit Timer A with: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes

– 16-bit Timer B with: 2 input captures, 2 output compares, PWM and pulse generator modes

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TQFP44

10 x 10

SDIP42

600 mil

TQFP32

7 x 7

SDIP32

400 mil

2 Communication Interfaces

– SPI synchronous serial interface

– SCI asynchronous serial interface

1 Analog Peripheral (low current coupling)

– 10-bit ADC with up to 12 robust input ports

Instruction Set

– 8-bit Data Manipulation

– 63 Basic Instructions

– 17 main Addressing Modes

– 8 x 8 Unsigned Multiply Instruction

Development Tools

– Full hardware/software development package

– In-Circuit Testing capability

Device Summary

Features

ST72324J6

ST72324K6

1

ST72324J4

ST72324K4

1

ST72324J2

ST72324JK2

1

Program memory - bytes

RAM (stack) - bytes

Voltage Range

Flash 32K

1024 (256)

Flash 16K

512 (256)

3.8V to 5.5V

Flash 8K

384 (256)

Temp. Range up to -40°C to +125°C

Packages SDIP42, TQFP44 10x10,SDIP32, TQFP32 7x7

1

For new designs in standard and industrial applications, use ST72324B(J/K) order codes, refer to separate datasheet

April 2008 Rev. 5

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1/164

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3

STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1

Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4

ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5

ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.6

IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7

RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7.1

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.3

CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.1

PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.2

MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3

RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.2

Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3.3

External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.4

Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.3.5

Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.4

SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.1

Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4.2

Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.3

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.4.4

Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.2

MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.3

INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.4

CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.5

INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.6

EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.6.1

I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.7

EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 38

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.1

164

8.2

SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8.3

WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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8.4

ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.4.1

ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.4.2

HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2.1

Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2.2

Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.2.3

Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.3

I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.4

LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.5

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

9.5.1

I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.1.4 How to Program the Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.6 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.1.9 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) . 56

10.2.1 Programmable CPU Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

10.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.4.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.4.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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10.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

10.4.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

10.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10.6 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

10.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

10.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

10.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.6.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.6.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

11.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

11.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

12.4 LVD/AVD CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.4.1 Operating Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . 119

12.4.2 Auxiliary Voltage Detector (AVD) Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

12.5 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

164

12.5.2 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

12.5.3 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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Table of Contents

12.6 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.6.1 General Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.6.2 External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

12.6.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

12.6.4 RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

12.6.5 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

12.7 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.7.1 RAM and Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.7.2 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.8 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

12.8.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . . 130

12.8.2 Electro Magnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

12.8.3 Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . 132

12.9 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.9.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.9.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.10 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

12.10.1Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

12.10.2ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.11 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.11.116-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.12 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 140

12.12.1SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

12.13 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.13.1Analog Power Supply and Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

12.13.2General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

12.13.3ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 150

14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

14.2 FLASH DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

14.3 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

14.4 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

14.4.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

14.5 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

15.1 ALL DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

15.1.1 External RC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

15.1.2 CSS Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

15.1.3 Safe Connection of OSC1/OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

15.1.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

15.1.5 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . 159

15.1.6 External Interrupt Missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

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15.1.7 16-bit Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15.1.8 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15.2 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15.2.1 Internal RC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

16 IMPORTANT NOTES ON ST72F324B FLASH DEVICES: . . . . . . . . . . . . . . . . . . . . . . . . . . 162

16.1 RESET PIN LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

16.2 WAKE-UP FROM ACTIVE HALT MODE USING EXTERNAL INTERRUPTS . . . . . . . 162

16.3 PLL JITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

16.4 ACTIVE HALT POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

16.5 TIMER A REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet.

Please also pay special attention to the Section

“KNOWN LIMITATIONS” on page 159 .

164

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ST72324Jx ST72324Kx

1 INTRODUCTION

The ST72324 devices are members of the ST7 microcontroller family designed for the 5V operating range.

– The 32-pin devices are designed for mid-range applications

– The 42/44-pin devices target the same range of applications requiring more than 24 I/O ports.

For a description of the differences between

ST72324 and ST72324B devices refer to

Section

14.2 on page 152

All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruc-

Figure 1. Device Block Diagram tion set and are available with FLASH program memory.

Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

8-BIT CORE

ALU

CONTROL

RESET

V

PP

V

SS

V

DD

LVD

PROGRAM

MEMORY

(8K - 32K Bytes)

RAM

(384 - 1024 Bytes)

WATCHDOG

OSC1

OSC2

OSC

MCC/RTC/BEEP

PORT A

PA7:3

(5 bits on J devices)

(4 bits on K devices)

PF7:6,4,2:0

(6 bits on J devices)

(5 bits on K devices)

PE1:0

(2 bits)

PD5:0

(6 bits on J devices)

(2 bits on K devices)

V

AREF

V

SSA

PORT F

TIMER A

BEEP

PORT E

SCI

PORT D

10-BIT ADC

PORT B

PORT C

TIMER B

SPI

PB4:0

(5 bits on J devices)

(3 bits on K devices)

PC7:0

(8 bits)

3

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ST72324Jx ST72324Kx

2 PIN DESCRIPTION

Figure 2. 42-Pin SDIP and 44-Pin TQFP Package Pinouts

RDI / PE1

PB0

PB1

PB2

PB3

(HS) PB4

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

AIN4 / PD4

2

3

1

44 43 42 41 40 39 38 37 36 35 34

33

4 ei2 ei0

32

31

30

5

6

7 ei3

8

9

26

25

10 ei1 24

11

12 13 14 15 16 17 18 19 20 21 22

23

29

28

27

V

SS_1

V

DD_1

PA3 (HS)

PC7 / SS / AIN15

PC6 / SCK / ICCCLK

PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13

PC0 / OCMP2_B / AIN12

8/164

(HS) PB4

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

AIN4 / PD4

AIN5 / PD5

V

AREF

V

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

AIN10 / OCMP1_A / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

AIN13 / OCMP1_B / PC1

ICAP2_B/ (HS) PC2

ICAP1_B / (HS) PC3

ICCDATA / MISO / PC4

AIN14 / MOSI / PC5 ei2 ei0

33

32

31

30

39

38

37

36

35

34

42

41

40

25

24

23

22

29

28

27

26

6

7

8

9

10

11

12

1

2

3

4

5

18

19

20

21

13

14

15

16

17 ei3 ei1

PB3

PB2

PB1

PB0

PE1 / RDI

PE0 / TDO

V

DD

_2

OSC1

OSC2

V

SS

_2

RESET

V

PP

/ ICCSEL

PA7 (HS)

PA6 (HS)

PA5 (HS)

PA4 (HS)

V

SS_1

V

DD_1

PA3 (HS)

PC7 / SS / AIN15

PC6 / SCK / ICCCLK

(HS) 20mA high sink capability eix associated external interrupt vector

ST72324Jx ST72324Kx

PIN DESCRIPTION (Cont’d)

Figure 3. 32-Pin SDIP Package Pinout

(HS) PB4

AIN0 / PD0

AIN1 / PD1

V

AREF

V

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

AIN13 / OCMP1_B / PC1

ICAP2_B / (HS) PC2

ICAP1_B / (HS) PC3

ICCDATA/ MISO / PC4

AIN14 / MOSI / PC5

7

8

9

5

6

1

2

3

4

10

11

12

13

14

15

16 ei3 ei1 ei2 ei0

25

24

23

22

28

27

26

21

20

19

18

17

32

31

30

29

PB3

PB0

PE1 / RDI

PE0 / TDO

V

DD

_2

OSC1

OSC2

V

SS

_2

RESET

V

PP

/ ICCSEL

PA7 (HS)

PA6 (HS)

PA4 (HS)

PA3 (HS)

PC7 / SS / AIN15

PC6 / SCK / ICCCLK

(HS) 20mA high sink capability eix associated external interrupt vector

Figure 4. 32-Pin TQFP 7x7 Package Pinout

V

AREF

V

SSA

MCO / AIN8 / PF0

BEEP / (HS) PF1

OCMP1_A / AIN10 / PF4

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN12 / OCMP2_B / PC0

4

5

1

2

32 31 30 29 28 27 26 25

24 ei3 ei2

23

3 ei1

22

21

6

7

20

19

8

18 ei0

9 10 11 12 13 14 15 16

17

OSC1

OSC2

V

SS

_2

RESET

V

PP

/ ICCSEL

PA7 (HS)

PA6 (HS)

PA4 (HS)

(HS) 20mA high sink capability eix associated external interrupt vector

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1

ST72324Jx ST72324Kx

PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 116.

Legend / Abbreviations for

Table 1 :

Type: I = input, O = output, S = supply

Input level: A = Dedicated analog input

In/Output level: C = CMOS 0.3V

C

T

DD

= CMOS 0.3V

DD

/0.7V

DD

/0.7V

DD

with input trigger

Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt

1)

, ana = analog ports

– Output: OD = open drain

2)

, PP = push-pull

Refer to “I/O PORTS” on page 45

for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.

Table 1. Device Pin Description

Pin n° Level

Pin Name Input

Port

Output

Main function

(after reset)

Alternate Function

6 1 30 1 PB4 (HS)

7 2 31 2 PD0/AIN0

8 3 32 3 PD1/AIN1

9 4

10 5

11 6

12 7

PD2/AIN2

PD3/AIN3

PD4/AIN4

PD5/AIN5

13 8 1 4 V

AREF

14 9 2 5 V

SSA

15 10 3

16 11 4

17 12

18 13 5

6

7

8

PF0/MCO/AIN8

PF1 (HS)/BEEP

PF2 (HS)

PF4/OCMP1_A/

AIN10

I/O C

T

I/O C

T

I/O C

T

I/O C

T

I/O C

T

I/O C

T

I/O C

T

S

S

I/O C

T

I/O C

T

I/O C

T

I/O C

T

19 14 6 9 PF6 (HS)/ICAP1_A I/O C

T

20 15 7 10

PF7 (HS)/

EXTCLK_A

I/O C

T

21

22

V

DD_0

V

SS_0

23 16 8 11

PC0/OCMP2_B/

AIN12

S

S

I/O C

T

HS X

X X ei3

X X

X X

X X

X X

X X

HS

HS

X

X

X

X X

HS X X

HS X X

X X ei1 ei1 ei1

X X Port B4

X X X Port D0 ADC Analog Input 0

X X X Port D1 ADC Analog Input 1

X X X Port D2 ADC Analog Input 2

X X X Port D3 ADC Analog Input 3

X X X Port D4 ADC Analog Input 4

X X X Port D5 ADC Analog Input 5

Analog Reference Voltage for ADC

Analog Ground Voltage

X X X Port F0

Main clock out (f

CPU

)

ADC Analog

Input 8

X X Port F1 Beep signal output

X X Port F2

X X X Port F4

Timer A Output Compare 1

ADC Analog

Input 10

X X Port F6 Timer A Input Capture 1

X X Port F7

Timer A External Clock

Source

Digital Main Supply Voltage

X X X

Digital Ground Voltage

Port C0

Timer B Output Compare 2

ADC Analog

Input 12

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1

ST72324Jx ST72324Kx

Pin n°

Pin Name

Level

Input

Port

Output

Main function

(after reset)

Alternate Function

24 17 9 12

32 25

33 26

35 28

3 40

4 41

PC1/OCMP1_B/

AIN13

I/O C

T

25 18 10 13 PC2 (HS)/ICAP2_B I/O C

T

26 19 11 14 PC3 (HS)/ICAP1_B I/O C

T

27 20 12 15

PC4/MISO/ICCDA-

TA

28 21 13 16 PC5/MOSI/AIN14

31 24 16 19 PA3 (HS)

V

DD_1

V

SS_1

34 27 17 20 PA4 (HS)

PA5 (HS)

36 29 18 21 PA6 (HS)

37 30 19 22 PA7 (HS)

38 31 20 23 V

43 36 25 28 V

PP

/ICCSEL

39 32 21 24 RESET

40 33 22 25 V

SS_2

41 34 23 26 OSC2

DD_2

44 37 26 29 PE0/TDO

1 38 27 30 PE1/RDI

2 39 28 31 PB0

PB1

PB2

5 42 29 32 PB3

I/O C

T

I/O C

T

29 22 14 17 PC6/SCK/ICCCLK I/O C

T

30 23 15 18 PC7/SS/AIN15

42 35 24 27 OSC1

I/O C

T

I/O C

T

S

S

I/O C

T

I/O C

T

I/O C

T

I/O C

T

I

I

I/O C

T

S

O

S

I/O C

T

I/O C

T

I/O C

T

I/O C

T

I/O C

T

I/O C

T

HS

HS

HS

HS

X X

X

X

X X

X X

X X

X X

X

X

X

X

X

X

HS X X

HS X

HS X

X

X

X

X

X

X

X ei0 ei2 ei2 ei2 ei2

X X X Port C1

Timer B Output Compare 1

ADC Analog

Input 13

X

X X Port C2 Timer B Input Capture 2

X X Port C3 Timer B Input Capture 1

X

X

X

X

Port C4

Port C5

SPI Master

In / Slave

Out Data

SPI Master

Out / Slave

In Data

ICC Data Input

ADC Analog

Input 14

X

X

X

X

X

Port C6

Port C7

SPI Serial

Clock

SPI Slave

Select (active low)

ICC Clock

Output

ADC Analog

Input 15

X X Port A3

Digital Main Supply Voltage

Digital Ground Voltage

X X Port A4

X X Port A5

T Port A6

1)

T Port A7

1)

Must be tied low. In the flash programming mode, this pin acts as the programming voltage input V

PP

. See

Section 12.10.2

for more details.

Top priority non maskable interrupt.

Digital Ground Voltage

Resonator oscillator inverter output

External clock input or Resonator oscillator inverter input

Digital Main Supply Voltage

X X Port E0 SCI Transmit Data Out

X X Port E1 SCI Receive Data In

X X Port B0

Caution: Negative current injection not allowed on this pin

5)

X X Port B1

X X Port B2

X X Port B3

Notes:

1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up

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ST72324Jx ST72324Kx column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.

2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V

DD

are not implemented). See See “I/O PORTS” on page 45. and Section 12.9 I/O PORT PIN CHARACTER-

ISTICS

for more details.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-

lator; see Section 1 INTRODUCTION

and Section 12.6 CLOCK AND TIMING CHARACTERISTICS

for more details.

4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

5. For details refer to Section 12.9.1 on page 133

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3 REGISTER & MEMORY MAP

As shown in

Figure 5

, the MCU is capable of addressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128 bytes of register locations, up to 1024 bytes of

RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

Figure 5. Memory Map

The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.

0000h

HW Registers

(see Table 2 )

007Fh

0080h

RAM

(1024,

512 or 384 Bytes)

047Fh

0480h

7FFFh

8000h

Reserved

Program Memory

(32K, 16K or 8K)

FFDFh

FFE0h

Interrupt & Reset Vectors

(see Table 8

)

FFFFh

0080h

Short Addressing

RAM (zero page)

00FFh

0100h

256 Bytes Stack

01FFh

0200h

027Fh or 047Fh

16-bit Addressing

RAM

8000h

C000h

32 KBytes

16 KBytes

E000h

8 Kbytes

FFFFh

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Table 2. Hardware Register Map

Address Block

Register

Label

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h to

0020h

0021h

0022h

0023h

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh to

0030h

Port A

2)

Port B

2)

Port C

Port D

2)

Port E

2)

Port F

2)

SPI

ITC

SPIDR

SPICR

SPICSR

ISPR0

ISPR1

ISPR2

ISPR3

EICR

FLASH FCSR

WATCHDOG WDGCR

SI

MCC

SICSR

MCCSR

MCCBCR

PADR

PADDR

PAOR

PBDR

PBDDR

PBOR

PCDR

PCDDR

PCOR

PDADR

PDDDR

PDOR

PEDR

PEDDR

PEOR

PFDR

PFDDR

PFOR

Register Name

Port A Data Register

Port A Data Direction Register

Port A Option Register

Port B Data Register

Port B Data Direction Register

Port B Option Register

Port C Data Register

Port C Data Direction Register

Port C Option Register

Port D Data Register

Port D Data Direction Register

Port D Option Register

Port E Data Register

Port E Data Direction Register

Port E Option Register

Port F Data Register

Port F Data Direction Register

Port F Option Register

Reserved Area (15 Bytes)

SPI Data I/O Register

SPI Control Register

SPI Control/Status Register

Interrupt Software Priority Register 0

Interrupt Software Priority Register 1

Interrupt Software Priority Register 2

Interrupt Software Priority Register 3

External Interrupt Control Register

Flash Control/Status Register

Watchdog Control Register

System Integrity Control Status Register

Main Clock Control / Status Register

Main Clock Controller: Beep Control Register

Reserved Area (3 Bytes)

00h

7Fh xxh

00h

00h xxh

0xh

00h

FFh

FFh

FFh

FFh

00h

Reset

Status

00h

1)

00h

00h

00h

1)

00h

00h

00h

1)

00h

00h

00h

1)

00h

00h

00h

1)

00h

00h

00h

1)

00h

00h

Remarks

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

2)

R/W

2)

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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ST72324Jx ST72324Kx

Address

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h to

006Fh

0070h

0071h

0072h

0073h

007Fh

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

0040h

Block

TIMER A

TIMER B

SCI

Register

Label

Register Name

Reset

Status

Remarks

TACR2

TACR1

TACSR

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

TACLR

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

TBCR2

TBCR1

TBCSR

TBIC1HR

TBIC1LR

TBOC1HR

TBOC1LR

TBCHR

TBCLR

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

SCISR

SCIDR

SCIBRR

SCICR1

SCICR2

SCIERPR

SCIETPR

Timer A Control Register 2

Timer A Control Register 1

Timer A Control/Status Register

3)4)

Timer A Input Capture 1 High Register

Timer A Input Capture 1 Low Register

Timer A Output Compare 1 High Register

Timer A Output Compare 1 Low Register

Timer A Counter High Register

Timer A Counter Low Register

Timer A Alternate Counter High Register

Timer A Alternate Counter Low Register

Timer A Input Capture 2 High Register

3)

Timer A Input Capture 2 Low Register

3)

Timer A Output Compare 2 High Register

4)

Timer A Output Compare 2 Low Register

4)

Reserved Area (1 Byte)

Timer B Control Register 2

Timer B Control Register 1

Timer B Control/Status Register

Timer B Input Capture 1 High Register

Timer B Input Capture 1 Low Register

Timer B Output Compare 1 High Register

Timer B Output Compare 1 Low Register

Timer B Counter High Register

Timer B Counter Low Register

Timer B Alternate Counter High Register

Timer B Alternate Counter Low Register

Timer B Input Capture 2 High Register

Timer B Input Capture 2 Low Register

Timer B Output Compare 2 High Register

Timer B Output Compare 2 Low Register

SCI Status Register

SCI Data Register

SCI Baud Rate Register

SCI Control Register 1

SCI Control Register 2

SCI Extended Receive Prescaler Register

Reserved area

SCI Extended Transmit Prescaler Register

00h

00h xxxx x0xxb xxh xxh

80h

00h

FFh

FCh

FFh

FCh xxh xxh

80h

00h

00h

00h xxxx x0xxb xxh xxh

80h

00h

FFh

FCh

FFh

FCh xxh xxh

80h

00h

R/W

R/W

R/W

Read Only

Read Only

R/W

R/W

Read Only

Read Only

Read Only

Read Only

Read Only

Read Only

R/W

R/W

C0h xxh

00h x000 0000h

00h

00h

---

00h

Read Only

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read Only

Read Only

R/W

R/W

Read Only

Read Only

Read Only

Read Only

Read Only

Read Only

R/W

R/W

ADC

ADCCSR

ADCDRH

ADCDRL

Reserved Area (24 Bytes)

Control/Status Register

Data High Register

Data Low Register

Reserved Area (13 Bytes)

00h

00h

00h

R/W

Read Only

Read Only

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Legend: x=undefined, R/W=read/write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

3. The Timer A Input Capture 2 pin is not available (not bonded).

– In Flash devices:

The TAIC2HR and TAIC2LR registers are not present. Bit 5 of the TACSR register (ICF2) is forced by hardware to 0. Consequently, the corresponding interrupt cannot be used.

4. The Timer A Output Compare 2 pin is not available (not bonded).

– The TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values.

Bit 4 of the TACSR register (OCF2) is forced by hardware to 0. Consequently, the corresponding interrupt cannot be used.

Caution: The TAIC2HR and TAIC2LR registers and the ICF2 and OCF2 flags are not present in Flash devices but are present in the emulator. For compatibility with the emulator, it is recommended to perform a dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.

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4 FLASH PROGRAM MEMORY

4.2 Main Features

■

■

■

■

4.1 Introduction

The ST7 dual voltage High Density Flash

(HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V

PP

supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or

IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

Three Flash programming modes:

– Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased.

– ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board.

– IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.

ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM

Read-out protection

Register Access Security System (RASS) to prevent accidental programming or erasing

Depending on the overall Flash memory size in the microcontroller device, there are up to three user

sectors (see Table 3

). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes

(see Figure 6 ). They are mapped in the upper part

of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000h-

FFFFh).

Table 3. Sectors available in Flash devices

Flash Size (bytes)

4K

8K

> 8K

Available Sectors

Sector 0

Sectors 0,1

Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased.

Read-out protection selection depends on the device type:

– In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option specified in the Option List.

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Figure 6. Memory Map and Sector Address

4K 8K 10K 16K

1000h

3FFFh

7FFFh

9FFFh

BFFFh

D7FFh

DFFFh

EFFFh

FFFFh

2 Kbytes

24K 32K 48K 60K

8 Kbytes 16 Kbytes

4 Kbytes

4 Kbytes

24 Kbytes 40 Kbytes 52 Kbytes

FLASH

MEMORY SIZE

SECTOR 2

SECTOR 1

SECTOR 0

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FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see

Figure 7

).

These pins are:

– RESET: device reset

– V

SS

: device power supply ground

Figure 7. Typical ICC Interface

PROGRAMMING TOOL

APPLICATION

POWER SUPPLY

(See Note 3)

C

L2

– ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input/output serial data pin

– ICCSEL/V

PP

: programming voltage

– OSC1(or OSCIN): main clock input for external source (optional)

– V

DD

: application board power supply (option-

al, see Figure 7

, Note 3)

ICC CONNECTOR

ICC Cable

APPLICATION BOARD

ICC CONNECTOR

HE10 CONNECTOR TYPE OPTIONAL

IN SOME CASES

(See Note 4)

9 7 5 3

10 8 6 4

1

2

APPLICATION

RESET SOURCE

See Note 2

10k

Ω

C

L1

See Note 1

APPLICATION

I/O

ST7

Notes:

1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming

Tool documentation for recommended resistor values.

2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K).

A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed.

In all cases the user must ensure that no external reset is generated by the application during the

ICC session.

3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming

Tool manual.

4. Pin 9 has to be connected to the OSC1 or OS-

CIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case.

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FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM,

Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the ap-

plication board (see Figure 7 ). For more details on

the pin locations, refer to the device pinout description.

possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual .

4.7.1 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 0000 0000 (00h)

4.6 IAP (In-Application Programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is

7

0 0 0 0 0 0 0

0

0

This register is reserved for use by Programming

Tool software. It controls the Flash programming and erasing operations.

Table 4. Flash Control/Status Register Address and Reset Value

Address

(Hex.)

0029h

Register

Label

FCSR

Reset Value

7

0

6

0

5

0

4

0

3

0

2

0

1

0

0

0

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5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■

■

■

■

■

■

■

■

Enable executing 63 basic instructions

Fast 8-bit by 8-bit multiply

17 main addressing modes (with indirect addressing mode)

Two 8-bit index registers

16-bit stack pointer

Low power HALT and WAIT modes

Priority maskable hardware interrupts

Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The 6 CPU registers shown in

Figure 8

are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL

(Program Counter Low which is the LSB) and PCH

(Program Counter High which is the MSB).

Figure 8. CPU Registers

7 0

RESET VALUE = XXh

7 0

RESET VALUE = XXh

7 0

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

15 PCH 8

RESET VALUE = XXh

7 PCL

0

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

RESET VALUE = 1

1 I1 H I0 N Z

1 1 X 1 X X X

0

C

15 8 7 0

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

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CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Reset Value: 111x1xxx

7

1 1 I1 H I0 N Z

0

C

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or

ADC instructions. It is reset by hardware during the same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7 th

bit.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

Interrupt Software Priority

Level 0 (main)

Level 1

Level 2

Level 3 (= interrupt disable)

I1

1

0

0

1

I0

0

1

0

1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET,

HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

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CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

15

0

7

0

SP7 SP6

0

SP5

0 0

SP4 SP3

0 0

8

1

0

SP2 SP1 SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.

It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see

Figure 9 ).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an

MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

Figure 9. Stack Manipulation Example

CALL

Subroutine

Interrupt

Event

@ 0100h

PUSH Y

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as

shown in Figure 9

.

– When an interrupt is received, the SP is decremented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

POP Y IRET RET or RSP

SP

SP

@ 01FFh

PCH

PCL

CC

A

X

PCH

PCL

PCH

PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

SP

Y

CC

A

X

PCH

PCL

PCH

PCL

SP

CC

A

X

PCH

PCL

PCH

PCL

SP

PCH

PCL

SP

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6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An

overview is shown in Figure 11 .

For more details, refer to dedicated parametric section.

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an f

OSC2

of 4 to 8

MHz. The PLL is enabled by option byte. If the PLL is disabled, then f

OSC2 =

f

OSC

/2.

Caution: The PLL is not recommended for applications where timing accuracy is required.

Caution: The PLL must not be used with the internal RC oscillator.

Main features

■ Optional PLL for multiplying the frequency by 2

(not to be used with internal RC oscillator in order to respect the max. operating frequency)

■

■

Reset Sequence Manager (RSM)

Multi-Oscillator Clock Management (MO)

■

– 5 Crystal/Ceramic resonator oscillators

– 1 Internal RC oscillator

System Integrity Management (SI)

– Main supply Low voltage detection (LVD)

– Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply

Figure 10. PLL Block Diagram f

OSC

PLL x 2

/ 2

0

1 f

OSC2

PLL OPTION BIT

Figure 11. Clock, Reset and Supply Block Diagram

OSC2

OSC1

RESET

MULTI-

OSCILLATOR

(MO) f

OSC

PLL

(option)

RESET SEQUENCE

MANAGER

(RSM) f

OSC2

MAIN CLOCK

CONTROLLER

WITH REALTIME

CLOCK (MCC/RTC) f

CPU

SYSTEM INTEGRITY MANAGEMENT

AVD Interrupt Request

SICSR

0

AVD AVD LVD

IE F RF

0 0 0

WDG

RF

WATCHDOG

TIMER (WDG)

V

SS

V

DD

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

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6.2 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by three different source types coming from the multioscillator block:

■

■

■ an external source

4 crystal or ceramic resonator oscillators an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware

configurations are shown in Table 5

. Refer to the electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure

Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an f

OSC

clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected.

External Clock Source

In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to

Section 14.1 on page 150 for more details on

the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

These oscillators are not stopped during the

RESET phase to avoid losing time in the oscillator start-up phase.

Internal RC Oscillator

This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing.

In this mode, the two oscillator pins have to be tied to ground.

In order not to exceed the max. operating frequency, the internal RC oscillator must not be used with the PLL.

Table 5. ST7 Clock Sources

Hardware Configuration

C

L1

OSC1

ST7

OSC2

EXTERNAL

SOURCE

OSC1

ST7

OSC2

LOAD

CAPACITORS

OSC1

ST7

OSC2

C

L2

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6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 13

:

■

■

■

External RESET source pulse

Internal LVD RESET (Low Voltage Detection)

Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 12

:

■ Active Phase depending on the RESET source

■

■

256 or 4096 CPU clock cycle delay (selected by option byte)

RESET vector fetch

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application.

Figure 13. Reset Block Diagram

The RESET vector fetch phase duration is 2 clock cycles.

Figure 12. RESET Sequence Phases

Active Phase

RESET

INTERNAL RESET

256 or 4096 CLOCK CYCLES

FETCH

VECTOR

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated R

ON

weak pull-up resistor.

This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See

Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t h(RSTL)in

in

order to be recognized (see Figure 14

). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.

V

DD

R

ON

RESET Filter

INTERNAL

RESET

PULSE

GENERATOR

WATCHDOG RESET

LVD RESET

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

6.3.3 External Power-On RESET

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V

DD

is over the minimum level specified for the selected f

OSC

frequency.

A proper reset signal for a slow rising V

DD

supply can generally be provided by an external RC network connected to the RESET pin.

6.3.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■

■

Power-On RESET

Voltage Drop RESET

The device RESET pin acts as an output that is pulled low when V

DD

V

DD

<V

IT-

<V

IT+

(rising edge) or

(falling edge) as shown in

Figure 14

.

The LVD filters spikes on V

DD avoid parasitic resets.

larger than t g(VDD) to

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter overflow is shown in Figure 14 .

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least t w(RSTL)out

.

Figure 14. RESET Sequences

V

DD

V

IT+(LVD)

V

IT-(LVD)

RUN

LVD

RESET

ACTIVE PHASE

RUN

EXTERNAL

RESET

ACTIVE

PHASE

WATCHDOG

RESET

RUN

ACTIVE

PHASE

RUN t h(RSTL)in t w(RSTL)out

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (256 or 4096 T

CPU

VECTOR FETCH

)

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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) generates a static reset when the V

DD below a V

IT-

supply voltage is

reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The V

IT-

reference value for a voltage drop is lower than the V

IT+

reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

V

DD

is below:

– V

IT+

when V

DD

is rising

– V

IT-

when V

DD

is falling

The LVD function is illustrated in Figure 15

.

The voltage threshold can be configured by option byte to be low, medium or high.

– under full software control

– in static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Notes:

The LVD allows the device to be used without any external RESET circuitry.

If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed.

The LVD is an optional function which can be selected by option byte.

It is recommended to make sure that the V

DD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.

Provided the minimum V

DD

value (guaranteed for the oscillator frequency) is above V

ITcan only be in two modes:

, the MCU

Figure 15. Low Voltage Detector vs Reset

V

DD

V hys

V

IT+

V

IT-

RESET

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a V

IT-(AVD)

V

IT+(AVD)

reference value and the V

DD ply. The V

IT-

reference value for falling voltage is lower than the V

IT+

and

main sup-

reference value for rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.

Caution: The AVD function is active only if the

LVD is enabled through the option byte (see

Section 14.1 on page 150 ).

6.4.2.1 Monitoring the V

DD

Main Supply

The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte

(see

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the V

IT+(AVD)

V

IT-(AVD)

threshold (AVDF bit toggles).

or

Figure 16. Using the AVD to Monitor V

DD

V

DD

Early Warning Interrupt

(Power has dropped, MCU not not yet in reset)

V hyst

V

IT+(AVD)

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See

Figure 16 .

The interrupt on the rising edge is used to inform the application that the V

DD

warning state is over.

If the voltage rise time t rv

is less than 256 or 4096

CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when V

IT+(AVD)

is reached.

If t rv

is greater than 256 or 4096 cycles then:

– If the AVD interrupt is enabled before the

V

IT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached.

– If the AVD interrupt is enabled after the V

IT+(AVD) threshold is reached then only one AVD interrupt will occur.

V

IT-(AVD)

V

IT+(LVD)

V

IT-(LVD) t rv

VOLTAGE RISE TIME

1 RESET VALUE 1 0 AVDF bit

AVD INTERRUPT

REQUEST

IF AVDIE bit = 1

0

LVD RESET

INTERRUPT PROCESS INTERRUPT PROCESS

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6.4.3 Low Power Modes

Mode Description

WAIT

HALT

No effect on SI. AVD interrupt causes the device to exit from Wait mode.

The CRSR register is frozen.

6.4.3.1 Interrupts

The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask in the

CC register is reset (RIM instruction).

Interrupt Event

AVD event

Event

Flag

Enable

Control

Bit

Exit from

Wait

AVDF AVDIE Yes

Exit from

Halt

No

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write

Reset Value: 000x 000x (00h)

Bits 3:1 = Reserved, must be kept cleared.

7

0

AVD

IE

AVD

F

LVD

RF

0 0

Bit 7 = Reserved, must be kept cleared.

0

0

WDG

RF

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles). The pending interrupt information is automatically cleared when software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generated by the Watchdog peripheral. It is set by hardware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).

Combined with the LVDRF flag information, the flag description is given by the following table.

RESET Sources

External RESET pin

Watchdog

LVD

LVDRF WDGRF

0

0

1

0

1

X

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the AVDIE bit is set, an interrupt request is generated when the AVDF bit changes value. Refer to

Figure 16

tails.

0: V

DD

1: V

DD

and to Section 6.4.2.1

over V

IT+(AVD)

threshold

under V

IT-(AVD)

threshold

for additional de-

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can not.

CAUTION: When the LVD is not activated with the associated option byte, the WDGRF flag can not be used in the application.

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See

WDGRF flag description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined.

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7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management provides the following features:

■ Hardware interrupts

■

■

Software interrupt (TRAP)

Nested or concurrent interrupt management with flexible interrupt priority and level management:

– Up to 4 software programmable nesting levels

– Up to 16 interrupt vectors fixed by hardware

– 2 non maskable events: RESET, TRAP

This interrupt management is based on:

– Bit 5 and bit 3 of the CPU CC register (I1:0),

– Interrupt software priority registers (ISPRx),

– Fixed interrupt vector addresses located at the high addresses of the memory map (FFE0h to

FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full upward compatibility with the standard (not nested) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx registers which give the interrupt software priority level of

each interrupt vector (see Table 6

). The process-

ing flow is shown in Figure 17

Figure 17. Interrupt Processing Flowchart

RESET

PENDING

INTERRUPT

N

FETCH NEXT

INSTRUCTION

When an interrupt request has to be serviced:

– Normal processing is suspended at the end of the current instruction execution.

– The PC, X, A and CC registers are saved onto the stack.

– I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx registers of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to

“Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the

IRET instruction which causes the contents of the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack and the program in the previous level will resume.

Table 6. Interrupt Software Priority Levels

Interrupt software priority Level

Level 0 (main) Low

Level 1

Level 2

Level 3 (= interrupt disable) High

I1

1

0

0

1

I0

0

1

0

1

Y

Interrupt has the same or a lower software priority than current one

TRAP

N

I1:0

THE INTERRUPT

STAYS PENDING

Y

RESTORE PC, X, A, CC

FROM STACK

Y

“IRET”

N

EXECUTE

INSTRUCTION STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

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INTERRUPTS (Cont’d)

Servicing Pending Interrupts

As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process:

– the highest software priority interrupt is serviced,

– if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first.

Figure 18

describes this decision process.

Figure 18. Priority Decision Process

Same

PENDING

INTERRUPTS

SOFTWARE

PRIORITY

HIGHEST HARDWARE

PRIORITY SERVICED

Different

HIGHEST SOFTWARE

PRIORITY SERVICED

When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one.

Note 1: The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt.

Note 2: RESET and TRAP can be considered as having the highest software priority in the decision process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the

ST7 interrupt controller: the non-maskable type

(RESET,TRAP) and the maskable type (external or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the state of the I1 and I0 bits of the CC register (see

Figure 17 ). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding vector is loaded in the PC register and the I1 and

I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit

HALT mode.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP instruction is executed. It will be serviced according to the flowchart in

Figure 17

.

■ RESET

The RESET source has the highest priority in the

ST7. This means that the first current routine has the highest software priority (level 3) and the highest hardware priority.

See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in ISPRx registers) is higher than the one currently being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt is latched and thus remains pending.

■ External Interrupts

External interrupts allow the processor to exit from

HALT low power mode. External interrupt sensitivity is software selectable through the External Interrupt Control register (EICR).

External interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.

If several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ORed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the MCU to exit from HALT mode except those mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register.

The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register.

Note: The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear sequence is executed.

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INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table). When several pending interrupts are present while exiting HALT mode, the first one serviced can only be an interrupt with exit from HALT mode capability and it is selected through the same decision process shown in

Figure 18 .

Note: If an interrupt, that is not able to Exit from

HALT mode, is pending with the highest priority when exiting HALT mode, this interrupt is serviced after the first one serviced.

Figure 19. Concurrent Interrupt Management

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 19 and Figure 20

show two different interrupt management modes. The first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in

Figure 20 . The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,

IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt.

Warning: A stack overflow may occur without notifying the software of the failure.

SOFTWARE

PRIORITY

LEVEL

I1 I0

RIM

MAIN

11 / 10

IT2

IT1

TRAP

IT1

IT0

IT3

IT4

10

MAIN

3

3

3

3

3

3

3/0

1 1

1 1

1 1

1 1

1 1

1 1

Figure 20. Nested Interrupt Management

SOFTWARE

PRIORITY

LEVEL

I1 I0

RIM

MAIN

11 / 10

IT2

IT1

IT4

TRAP

IT4

IT0

IT3

IT1

IT2

10

MAIN

3

3

2

1

3

3

3/0

1 1

1 1

0 0

0 1

1 1

1 1

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INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION

CPU CC REGISTER INTERRUPT BITS

Read/Write

Reset Value: 111x 1010 (xAh)

7 0

1 1 I1 H I0 N Z C

Bit 5, 3 = I1, I0 Software Interrupt Priority

These two bits indicate the current interrupt software priority.

Interrupt Software Priority Level

Level 0 (main)

Level 1

Low

Level 2

Level 3 (= interrupt disable*) High

I1

1

0

0

1

I0

0

1

0

1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx).

They can be also set/cleared by software with the

RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see “Interrupt Dedicated Instruction

Set” table).

*Note: TRAP and RESET events can interrupt a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGIS-

TERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only)

Reset Value: 1111 1111 (FFh)

7 0

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This correspondance is shown in the following table.

Vector address

FFFBh-FFFAh

FFF9h-FFF8h

...

FFE1h-FFE0h

ISPRx bits

I1_0 and I0_0 bits*

I1_1 and I0_1 bits

...

I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1 and I0 bits in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (example: previous=CFh, write=64h, result=44h)

The RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set.

Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behaviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the interrupt x).

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INTERRUPTS (Cont’d)

Table 7. Dedicated Interrupt Instruction Set

Instruction

HALT

IRET

JRM

JRNM

POP CC

RIM

SIM

TRAP

WFI

New Description

Entering Halt mode

Interrupt routine return

Jump if I1:0=11 (level 3)

Jump if I1:0<>11

Pop CC from the Stack

Enable interrupt (level 0 set)

Disable interrupt (level 3 set)

Software trap

Wait for interrupt

Function/Example

Pop CC, A, X, PC

I1:0=11?

I1:0<>11?

Mem => CC

Load 10 in I1:0 of CC

Load 11 in I1:0 of CC

Software NMI

I1

1

I1

H

H

I0

0

I0

N

N

I1

1

1

1

1

H I0

0

1

1

0

N

Z C

Z C

Z C

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current software priority up to the next IRET instruction or one of the previously mentioned instructions.

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INTERRUPTS (Cont’d)

Table 8. Interrupt Mapping

N°

4

5

2

3

6

0

1

7

8

9

10

11

Source

Block

Description

RESET

TRAP

Reset

Software interrupt

Not used

MCC/RTC Main clock controller time base interrupt ei0 ei1 ei2 ei3

External interrupt port A3..0

External interrupt port F2..0

External interrupt port B3..0

External interrupt port B7..4

Not used

SPI

TIMER A

TIMER B

SCI

AVD

SPI peripheral interrupts

TIMER A peripheral interrupts

TIMER B peripheral interrupts

SCI Peripheral interrupts

Auxiliary Voltage detector interrupt

Register

Label

N/A

MCCSR

N/A

SPICSR

TASR

TBSR

SCISR

SICSR

Priority

Order

Exit from

HALT/

ACTIVE

HALT

1) yes no

Higher

Priority

Lower

Priority yes yes yes yes yes yes no no no no

Address

Vector

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

Notes:

1. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register

(

Figure 21

). This control allows to have up to 4 fully independent external interrupt source sensitivities.

Each external interrupt source can be generated on four (or five) different events on the pin:

■ Falling edge

■

■

Rising edge

Falling and rising edge

■

■

Falling edge and low level

Rising edge and high level (only for ei0 and ei2)

To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity.

The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the

EICR.

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Figure 21. External Interrupt Control bits

PORT A3 INTERRUPT

PAOR.3

PADDR.3

PA3

IPA BIT

PORT F [2:0] INTERRUPTS

PFOR.2

PFDDR.2

PF2

EICR

IS20 IS21

SENSITIVITY

CONTROL

EICR

IS20 IS21

SENSITIVITY

CONTROL

PF2

PF1

PF0

PORT B [3:0] INTERRUPTS

PBOR.3

PBDDR.3

PB3

IPB BIT

PORT B4 INTERRUPT

PBOR.4

PBDDR.4

PB4

EICR

IS10 IS11

SENSITIVITY

CONTROL

PB3

PB2

PB1

PB0

EICR

IS10 IS11

SENSITIVITY

CONTROL ei0 INTERRUPT SOURCE ei1 INTERRUPT SOURCE ei2 INTERRUPT SOURCE ei3 INTERRUPT SOURCE

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Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts:

- ei2 (port B3..0)

IS11 IS10

0

0

1

1

INTERRUPTS (Cont’d)

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:

7 0

IS11 IS10 IPB IS21 IS20 IPA 0 0

0

1

0

1

External Interrupt Sensitivity

IPB bit =0 IPB bit =1

Falling edge & low level

Rising edge only

Rising edge

& high level

Falling edge only

Falling edge only Rising edge only

Rising and falling edge

- ei3 (port B4)

IS11 IS10

1

1

0

0

0

1

0

1

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 5 = IPB Interrupt polarity for port B

This bit is used to invert the sensitivity of the port B

[3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

- ei0 (port A3..0)

IS21 IS20

0

0

1

1

0

1

0

1

External Interrupt Sensitivity

IPA bit =0 IPA bit =1

Falling edge & low level

Rising edge only

Falling edge only

Rising edge

& high level

Falling edge only

Rising edge only

Rising and falling edge

- ei1 (port F2..0)

IS21 IS20

1

1

0

0

0

1

0

1

External Interrupt Sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3).

Bit 2 = IPA Interrupt polarity for port A

This bit is used to invert the sensitivity of the port A

[3:0] external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

Bits 1:0 = Reserved, must always be kept cleared.

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Table 9. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Register

Label

7 6 5 4

0024h

0025h

0026h

ISPR0

Reset Value

ISPR1

Reset Value

ISPR2

Reset Value ei1

I1_3

1

I0_3

1

SPI

I1_7

1

I0_7

1

I1_11

1

AVD

I0_11

1

I1_2

1 ei0

I0_2

1

I1_6

1

I0_6

1

I1_10

1

SCI

I0_10

1

0027h

0028h

ISPR3

Reset Value

EICR

Reset Value

1

IS11

0

1

IS10

0

1

IPB

0

1

IS21

0

3 2

MCC + SI

I1_1

1

I0_1

1 ei3

I1_5

1

TIMER B

I0_5

1

I1_9

1

I0_9

1

I1_13

1

IS20

0

I0_13

1

IPA

0

1 0

1 1 ei2

I1_4

1

TIMER A

I0_4

1

I1_8

1

I0_8

1

I1_12

1

0

I0_12

1

0

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8 POWER SAVING MODES

8.1 INTRODUCTION

To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7

(see Figure 22 ): SLOW, WAIT (SLOW WAIT), AC-

TIVE HALT and HALT.

After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided or multiplied by 2

(f

OSC2

).

From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 22. Power Saving Mode Transitions

High

RUN

8.2 SLOW MODE

This mode has two targets:

– To reduce power consumption by decreasing the internal clock in the device,

– To adapt the internal clock frequency (f

CPU the available supply voltage.

) to

SLOW mode is controlled by three bits in the

MCCSR register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f

CPU

).

In this mode, the master clock frequency (f

OSC2

) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency

(f

CPU

).

Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in

SLOW mode.

Figure 23. SLOW Mode Clock Transitions f

OSC2

/2 f

OSC2

/4 f

OSC2 f

CPU

SLOW

WAIT f

OSC2

CP1:0

SMS

00 01

SLOW WAIT

NORMAL RUN MODE

REQUEST

ACTIVE HALT

NEW SLOW

FREQUENCY

REQUEST

HALT

Low

POWER CONSUMPTION

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8.3 WAIT MODE

WAIT mode places the MCU in a low power consumption mode by stopping the CPU.

This power saving mode is selected by calling the

‘WFI’ instruction.

All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in

WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine.

The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 24 .

Figure 24. WAIT Mode Flow-chart

WFI INSTRUCTION

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

ON

OFF

10

N

RESET

Y

N

INTERRUPT

Y

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

OFF

ON

10

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

ON

ON

XX 1)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note:

1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

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8.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).

MCCSR

OIE bit

0

1

Power Saving Mode entered when HALT instruction is executed

HALT mode

ACTIVE-HALT mode

8.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is set (see

Section

10.2 on page 56

for more details on the MCCSR register).

The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific in-

terrupt (see Table 8, “Interrupt Mapping,” on page 36 ) or a RESET. When exiting ACTIVE-

HALT mode by means of an interrupt, no 256 or

4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see

Figure 26

).

When entering ACTIVE-HALT mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable interrupts. Therefore, if an interrupt is pending, the

MCU wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).

The safeguard against staying locked in ACTIVE-

HALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET.

This means that the device cannot spend more than a defined delay in this power saving mode.

CAUTION: When exiting ACTIVE-HALT mode following an interrupt, OIE bit of MCCSR register must not be cleared before t

DELAY

after the interrupt occurs (t

DELAY

= 256 or 4096 t

CPU

delay depending on option byte). Otherwise, the ST7 enters HALT mode for the remaining t

DELAY period.

Figure 25. ACTIVE-HALT Timing Overview

RUN

ACTIVE

HALT

256 OR 4096 CPU

CYCLE DELAY

1) RUN

HALT

INSTRUCTION

[MCCSR.OIE=1]

RESET

OR

INTERRUPT

FETCH

VECTOR

Figure 26. ACTIVE-HALT Mode Flow-chart

HALT INSTRUCTION

(MCCSR.OIE=1)

OSCILLATOR

PERIPHERALS

2)

CPU

I[1:0] BITS

ON

OFF

OFF

10

N

INTERRUPT

3)

Y

N

RESET

Y

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

OFF

ON

XX

4)

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

ON

ON

XX

4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripheral clocked with an external clock source can still be active.

3. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to

Table 8, “Interrupt Mapping,” on page 36

for more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped.

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POWER SAVING MODES (Cont’d)

8.4.2 HALT MODE

The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the

‘HALT’ instruction when the OIE bit of the Main

Clock Controller Status register (MCCSR) is

cleared (see Section 10.2 on page 56

for more details on the MCCSR register).

The MCU can exit HALT mode on reception of either a specific interrupt (see

Table 8, “Interrupt

Mapping,” on page 36 ) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see

Figure 28

).

When entering HALT mode, the I[1:0] bits in the

CC register are forced to ‘10b’to enable interrupts.

Therefore, if an interrupt is pending, the MCU wakes up immediately.

In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals.

All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with

HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see

Section 14.1 on page 150 ) for more details.

Figure 27. HALT Timing Overview

RUN HALT

256 OR 4096 CPU

CYCLE DELAY

RESET

OR

INTERRUPT HALT

INSTRUCTION

[MCCSR.OIE=0]

RUN

FETCH

VECTOR

Figure 28. HALT Mode Flow-chart

HALT INSTRUCTION

(MCCSR.OIE=0)

ENABLE

0

WATCHDOG

DISABLE

WDGHALT 1)

1

WATCHDOG

RESET

OSCILLATOR

PERIPHERALS 2)

CPU

OFF

OFF

OFF

I[1:0] BITS 10

N

RESET

Y

N

INTERRUPT 3)

Y OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

OFF

ON

XX 4)

256 OR 4096 CPU CLOCK

CYCLE DELAY

OSCILLATOR

PERIPHERALS

CPU

I[1:0] BITS

ON

ON

ON

XX 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. WDGHALT is an option bit. See option byte section for more details.

2. Peripheral clocked with an external clock source can still be active.

3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to

Table 8, “Interrupt Mapping,” on page 36 for

more details.

4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

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POWER SAVING MODES (Cont’d)

8.4.2.1 Halt Mode Recommendations

– Make sure that an external event is available to wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

– For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure.

– The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in

ROM with the value 0x8E.

– As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

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9 I/O PORTS

9.1 INTRODUCTION

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs and for specific pins:

– external interrupt generation

– alternate signal input/output for the on-chip peripherals.

An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:

– Data Register (DR)

– Data Direction Register (DDR) and one optional register:

– Option Register (OR)

Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the

OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is

shown in Figure 29

9.2.1 Input Modes

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1. Writing the DR register modifies the latch value but does not affect the pin status.

2. When switching from input to output mode, the

DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.

3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register

External interrupt function

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.

Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the

EICR register.

Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed.

The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the EICR register must be modified.

9.2.2 Output Modes

The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the

I/O pin through the latch. Then reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

DR register value and output pin status:

DR

0

1

Push-pull

V

SS

V

DD

Open-drain

Vss

Floating

9.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming.

When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.

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I/O PORTS (Cont’d)

Figure 29. I/O Port General Block Diagram

REGISTER

ACCESS

ALTERNATE

OUTPUT

1

0

ALTERNATE

ENABLE

DR

DDR

OR

OR SEL

If implemented

DDR SEL

DR SEL

1

0

EXTERNAL

INTERRUPT

SOURCE (ei x

)

PULL-UP

CONDITION

V

DD

P-BUFFER

(see table below)

PULL-UP

(see table below)

V

DD

PAD

N-BUFFER

CMOS

SCHMITT

TRIGGER

DIODES

(see table below)

ANALOG

INPUT

ALTERNATE

INPUT

Table 10. I/O Port Mode Options

Configuration Mode

Input

Output

Floating with/without Interrupt

Pull-up with/without Interrupt

Push-pull

Open Drain (logic level)

True Open Drain

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated

Pull-Up P-Buffer to V

DD

Diodes to V

SS

Off

On

Off

NI

Off

On

Off

NI

On

On

NI (see note)

Note: The diode to V

DD

is not implemented in the true open drain pads. A local protection between the pad and V

SS

is implemented to protect the device against positive stress.

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I/O PORTS (Cont’d)

Table 11. I/O Port Configurations

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

V

DD

R

PU

PAD

Hardware Configuration

PULL-UP

CONDITION

DR REGISTER ACCESS

DR

REGISTER

W

R

DATA BUS

ALTERNATE INPUT

EXTERNAL INTERRUPT

SOURCE (ei x

)

INTERRUPT

CONDITION

ANALOG INPUT

DR REGISTER ACCESS

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

V

DD

R

PU

PAD

DR

REGISTER

R/W

DATA BUS

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

V

DD

R

PU

PAD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

DR REGISTER ACCESS

DR

REGISTER

R/W

DATA BUS

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

Notes:

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

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I/O PORTS (Cont’d)

CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin.

WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings.

9.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transi-

tions are illustrated in Figure 30

Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Figure 30. Interrupt I/O Port State Transitions

01 00

INPUT floating/pull-up interrupt

INPUT floating

(reset state)

10

OUTPUT open-drain

11

OUTPUT push-pull

XX = DDR, OR

9.4 LOW POWER MODES

Mode Description

WAIT

HALT

No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.

No effect on I/O ports. External interrupts cause the device to exit from HALT mode.

9.5 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with

DDR and OR registers and the interrupt mask in the CC register is not active (RIM instruction).

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from

Wait

Exit from

Halt

External interrupt on selected external event

-

DDRx

ORx

Yes Yes

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I/O PORTS (Cont’d)

9.5.1 I/O Port Implementation

The I/O port register configurations are summarised as follows.

Standard Ports

PA5:4, PC7:0, PD5:0,

PE1:0, PF7:6, 4

MODE floating input pull-up input open drain output push-pull output

DDR

0

0

1

1

OR

0

1

0

1

Interrupt Ports

PB4, PB2:0, PF1:0 (with pull-up)

MODE floating input pull-up interrupt input open drain output push-pull output

DDR

0

0

1

1

Table 12. Port Configuration

Port

Port A

Port B

Port C

Port D

Port E

Port F

Pin name

PA7:6

PA5:4

PA3

PB3

PB4, PB2:0

PC7:0

PD5:0

PE1:0

PF7:6, 4

PF2

PF1:0

OR

0

1

0

1

PA3, PB3, PF2 (without pull-up)

MODE floating input floating interrupt input open drain output push-pull output

True Open Drain Ports

PA7:6

MODE floating input open drain (high sink ports) floating floating floating floating floating floating floating floating floating floating

OR = 0

Input

OR = 1 floating pull-up floating interrupt floating interrupt pull-up interrupt pull-up pull-up pull-up pull-up floating interrupt pull-up interrupt

DDR

0

0

1

1

Output

OR = 0 true open-drain

OR = 1 open drain open drain open drain open drain open drain open drain open drain open drain open drain open drain push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull push-pull

OR

0

1

0

1

DDR

0

1

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I/O PORTS (Cont’d)

Table 13. I/O Port Register Map and Reset Values

Address

(Hex.)

Register

Label

Reset Value of all I/O port registers

0000h PADR

0001h

0002h

0003h

0004h

0005h

0006h

PADDR

PAOR

PBDR

PBDDR

PBOR

PCDR

0007h

0008h

0009h

000Ah

PCDDR

PCOR

PDDR

PDDDR

000Bh PDOR

000Ch PEDR

000Dh PEDDR

000Eh PEOR

000Fh

0010h

0011h

PFDR

PFDDR

PFOR

7

0

MSB

MSB

MSB

MSB

MSB

MSB

6

0

5

0

4

0

3

0

2

0

1

0

0

0

LSB

LSB

LSB

LSB

LSB

LSB

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10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.

10.1.2 Main Features

■

■

■

■

■

Programmable free-running downcounter

Programmable reset

Reset (if watchdog activated) when the T6 bit reaches zero

Optional reset on HALT instruction

(configurable by option byte)

Hardware Watchdog selectable by option byte

10.1.3 Functional Description

The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is decremented every 16384 f

OSC2

cycles (approx.), and the length of the timeout period can be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically

500ns.

The application program must write in the

WDGCR register at regular intervals during normal operation to prevent an MCU reset. This downcounter is free-running: it counts down even if the watchdog is disabled. The value to be stored in the

WDGCR register must be between FFh and C0h:

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an immediate reset

– The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset (see

Figure 32. Approximate Timeout Duration

). The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WDGCR register (see

Figure 33

).

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction will generate a Reset.

Figure 31. Watchdog Block Diagram

RESET f

OSC2

MCC/RTC

DIV 64

WDGA

WATCHDOG CONTROL REGISTER (WDGCR)

T6 T5 T4 T3 T2 T1

6-BIT DOWNCOUNTER (CNT)

T0

11

12-BIT MCC

RTC COUNTER

MSB LSB

6 5 0

TB[1:0] bits

(MCCSR

Register)

WDG PRESCALER

DIV 4

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28

20

18

10

08

00

1.5

WATCHDOG TIMER (Cont’d)

10.1.4 How to Program the Watchdog Timeout

Figure 32

shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If

Figure 32. Approximate Timeout Duration

3F more precision is needed, use the formulae in

Figure 33

.

Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.

38

30

18 34 50 65 82

Watchdog timeout (ms) @ 8 MHz. f

OSC2

98 114 128

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WATCHDOG TIMER (Cont’d)

Figure 33. Exact Timeout Duration (t min

and t max

)

WHERE: t min0

= (LSB + 128) x 64 x t

OSC2 t max0

= 16384 x t

OSC2 t

OSC2

= 125ns if f

OSC2

=8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)

MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register

TB1 Bit

(MCCSR Reg.)

0

0

1

1

TB0 Bit

(MCCSR Reg.)

0

1

0

1

Selected MCCSR

Timebase

2ms

4ms

10ms

25ms

MSB LSB

4

8

20

49

59

53

35

54

To calculate the minimum Watchdog Timeout (t min

):

IF CNT <

4

THEN

ELSE t min

= t min0

+ 16384

×

CNT

× t osc2 t min

= t min0

+ 16384

×

⎛

⎝

CNT –

MSB

⎞

⎠

+

(

192 + LSB

×

MSB

× t osc2

To calculate the maximum Watchdog Timeout (t max

):

IF

CNT

≤

4

THEN t max

= t max0

+ 16384

×

CNT

× t osc2

ELSE t max

= t max0

+ 16384

×

⎛

CNT –

MSB

+

(

192 + LSB

×

MSB

× t osc2

Note: In the above formulae, division results must be rounded down to the next integer value.

Example:

With 2ms timeout selected in MCCSR register

Value of T[5:0] Bits in

WDGCR Register (Hex.)

00

3F

Min. Watchdog

Timeout (ms) t min

1.496

128

Max. Watchdog

Timeout (ms) t max

2.048

128.552

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WATCHDOG TIMER (Cont’d)

10.1.5 Low Power Modes

Mode Description

SLOW No effect on Watchdog.

WAIT No effect on Watchdog.

OIE bit in

MCCSR register

WDGHALT bit in Option

Byte

HALT

0

0

1

0

1 x

No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset.

If an external interrupt is received, the Watchdog restarts counting after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state) unless Hardware Watchdog is selected by option byte. For application recommendations see

Section 10.1.7

below.

A reset is generated.

No reset is generated. The MCU enters Active Halt mode. The Watchdog counter is not decremented. It stop counting. When the MCU receives an oscillator interrupt or external interrupt, the Watchdog restarts counting immediately. When the MCU receives a reset the Watchdog restarts counting after 256 or 4096 CPU clocks.

10.1.6 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WDGCR is not used. Refer to the Option Byte description.

10.1.7 Using Halt Mode with the WDG

(WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled.

– Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

10.1.8 Interrupts

None.

10.1.9 Register Description

CONTROL REGISTER (WDGCR)

Read/Write

Reset Value: 0111 1111 (7Fh)

7

WDGA T6 T5 T4

Bit 7 = WDGA Activation bit.

T3 T2 T1

0

T0

This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option byte.

Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog counter. It is decremented every 16384 f

OSC2

cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).

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Table 14. Watchdog Timer Register Map and Reset Values

Address

(Hex.)

002Ah

Register

Label

WDGCR

Reset Value

7

WDGA

0

6

T6

1

5

T5

1

4

T4

1

3

T3

1

2

T2

1

1

T1

1

0

T0

1

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10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)

The Main Clock Controller consists of three different functions:

■

■ a programmable CPU clock prescaler a clock-out signal to supply external devices

■ a real time clock timer with interrupt capability

Each function can be used independently and simultaneously.

10.2.1 Programmable CPU Clock Prescaler

The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See

Section 8.2 SLOW MODE

for more details).

The prescaler selects the f

CPU

main clock frequency and is controlled by three bits in the MCCSR register: CP[1:0] and SMS.

10.2.2 Clock-out Capability

The clock-out capability is an alternate function of an I/O port pin that outputs the f

CPU

clock to drive

Figure 34. Main Clock Controller (MCC/RTC) Block Diagram external devices. It is controlled by the MCO bit in the MCCSR register.

CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode.

10.2.3 Real Time Clock Timer (RTC)

The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on f

OSC2

are available. The whole functionality is controlled by four bits of the MCC-

SR register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the

HALT instruction is executed. See Section 8.4 AC-

TIVE-HALT AND HALT MODES for more details.

10.2.4 Beeper

The beep function is controlled by the MCCBCR register. It can output three selectable frequencies on the BEEP pin (I/O port alternate function). f

OSC2

BC1 BC0

MCCBCR

BEEP SIGNAL

SELECTION

BEEP

MCO

DIV 64

12-BIT MCC RTC

COUNTER

TO

WATCHDOG

TIMER

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

MCCSR

DIV 2, 4, 8, 16 1

0

MCC/RTC INTERRUPT f

CPU

CPU CLOCK

TO CPU AND

PERIPHERALS

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

10.2.5 Low Power Modes

Mode Description

WAIT

ACTIVE-

HALT

HALT

No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit from WAIT mode.

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.

MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode.

MCC/RTC counter and registers are frozen.

MCC/RTC operation resumes when the

MCU is woken up by an interrupt with “exit from HALT” capability.

Bit 6:5 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software f

CPU

in SLOW mode f

OSC2

/ 2 f

OSC2

/ 4 f

OSC2

/ 8 f

OSC2

/ 16

CP1

0

0

1

1

CP0

0

1

0

1

10.2.6 Interrupts

The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active

(RIM instruction).

Interrupt Event

Time base overflow event

Event

Flag

Enable

Control

Bit

Exit from

Wait

OIF OIE

Exit from

Halt

Yes No

1)

Bit 4 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. f

CPU

1: Slow mode. f

CPU

= f

OSC2

is given by CP1, CP0

See

Section 8.2 SLOW MODE

and

Section 10.2

MAIN CLOCK CONTROLLER WITH REAL TIME

CLOCK AND BEEPER (MCC/RTC)

for more details.

Note:

The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

10.2.7 Register Description

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write

Reset Value: 0000 0000 (00h

)

Bit 3:2 = TB[1:0] Time base control

These bits select the programmable divider time base. They are set and cleared by software.

Counter

Prescaler

16000

32000

80000

200000

Time Base f

OSC2

=4MHz f

OSC2

=8MHz

4ms

8ms

2ms

4ms

20ms

50ms

10ms

25ms

TB1 TB0

0

0

1

1

0

1

0

1

7 0

A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real time clock.

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

Bit 7 = MCO Main clock out selection

This bit enables the MCO alternate function on the

PF0 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for general-purpose I/O)

1: MCO alternate function enabled (f

CPU port) on I/O

Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode.

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from ACTIVE-

HALT mode.

When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode

.

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0).

0: Timeout not reached

1: Timeout reached

MCC BEEP CONTROL REGISTER (MCCBCR)

Read/Write

Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 BC1 BC0

CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.

Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

BC1

0

0

1

1

BC0

0

1

0

1

Beep mode with f

OSC2

=8MHz

Off

~2-KHz

~1-KHz

Output

Beep signal

~50% duty cycle

~500-Hz

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the consumption.

Table 15. Main Clock Controller Register Map and Reset Values

Address

(Hex.)

002Bh

002Ch

002Dh

Register

Label

SICSR

Reset Value

MCCSR

Reset Value

MCCBCR

Reset Value

7

0

MCO

0

0

6

AVDIE

0

CP1

0

0

5

AVDF

0

CP0

0

0

4

LVDRF x

SMS

0

0

3

0

TB1

0

0

2

0

TB0

0

0

1

0

OIE

0

BC1

0

0

WDGRF x

OIF

0

BC0

0

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10.3 16-BIT TIMER

■

■

■

■

10.3.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler.

It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.

Some ST7 devices have two on-chip 16-bit timers.

They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified.

This description covers one or two 16-bit timers. In

ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).

10.3.2 Main Features

■

■

Programmable prescaler: f

CPU

divided by 2, 4 or 8.

Overflow status flag and maskable interrupt

■

■

External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge

1 or 2 Output Compare functions each with:

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

■

– 1 dedicated maskable interrupt

1 or 2 Input Capture functions each with:

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

Pulse width modulation mode (PWM)

One pulse mode

Reduced Power Mode

5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in

Figure 35

.

*Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description.

When reading an input signal on a non-bonded pin, the value will always be ‘1’.

10.3.3 Functional Description

10.3.3.1 Counter

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most significant byte (MS Byte).

– Counter Low Register (CLR) is the least significant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte).

These two read-only 16-bit registers contain the same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR),

(see note at the end of paragraph titled 16-bit read sequence).

Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in

Control Bits

Table 16 Clock

. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits.

The timer frequency can be f

CPU or an external frequency.

/2, f

CPU

/4, f

CPU

/8

Caution: In Flash devices, Timer A functionality has the following restrictions:

– TAOC2HR and TAOC2LR registers are write only

– Input Capture 2 is not implemented

– The corresponding interrupts cannot be used

(ICF2, OCF2 forced by hardware to zero)

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16-BIT TIMER (Cont’d)

Figure 35. Timer Block Diagram

ST7 INTERNAL BUS

EXTCLK pin f

CPU

MCU-PERIPHERAL INTERFACE

8 high

8 low

8-bit buffer

1/2

1/4

1/8

EXEDG

16

COUNTER

REGISTER

ALTERNATE

COUNTER

REGISTER

16

CC[1:0]

8 8 8 8 8 8 8 8

OUTPUT

COMPARE

REGISTER

1

OUTPUT

COMPARE

REGISTER

2

INPUT

CAPTURE

REGISTER

1

INPUT

CAPTURE

REGISTER

2

16 16

TIMER INTERNAL BUS

16 16

OVERFLOW

DETECT

CIRCUIT

OUTPUT COMPARE

CIRCUIT

EDGE DETECT

CIRCUIT1

ICAP1 pin

6

EDGE DETECT

CIRCUIT2

ICAP2 pin

ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0

(Control/Status Register)

CSR

LATCH1

LATCH2

OCMP1 pin

OCMP2 pin

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

(Control Register 1) CR1

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

(Control Register 2) CR2

(See note)

TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)

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16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

Register or the Alternate Counter Register).

Beginning of the sequence

At t0

Read

MS Byte

LS Byte is buffered

Other instructions

At t0 +

∆t

Read

LS Byte

Returns the buffered

LS Byte value at t0

Sequence completed

The user must read the MS Byte first, then the LS

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the user reads the MS Byte several times.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read.

Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from

FFFFh to 0000h then:

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.

Clearing the overflow interrupt request is done in two steps:

1. Reading the SR register while the TOF bit is set.

2. An access (read or write) to the CLR register.

Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

10.3.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in the CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronized with the falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.

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16-BIT TIMER (Cont’d)

Figure 36. Counter Timing Diagram, internal clock divided by 2

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFD FFFE FFFF 0000 0001 0002 0003

Figure 37. Counter Timing Diagram, internal clock divided by 4

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

FFFC

TIMER OVERFLOW FLAG (TOF)

FFFD 0000 0001

Figure 38. Counter Timing Diagram, internal clock divided by 8

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

FFFC FFFD 0000

TIMER OVERFLOW FLAG (TOF)

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

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16-BIT TIMER (Cont’d)

10.3.3.3 Input Capture

In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer.

The two 16-bit input capture registers (IC1R and

IC2R) are used to latch the value of the free running counter after a transition is detected on the

ICAPi pin (see figure 5).

ICiR

MS Byte

ICiHR

LS Byte

ICiLR

ICiR register is a read-only register.

The active transition is software programmable through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running counter: ( f

CPU

/ CC[1:0]).

Procedure:

To use the input capture function select the following in the CR2 register:

– Select the timer clock (CC[1:0]) (see

Table 16

Clock Control Bits

).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available).

And select the following in the CR1 register:

– Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input or input with pullup without interrupt if this configuration is available).

When an input capture occurs:

– ICFi bit is set.

– The ICiR register contains the value of the free running counter on the active transition on the

ICAPi pin (see Figure 40

).

– A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Notes:

1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read.

2. The ICiR register contains the free running counter value which corresponds to the most recent input capture.

3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions.

4. In One pulse Mode and PWM mode only Input

Capture 2 can be used.

5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function.

Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.

This can be avoided if the input capture function i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh).

7. In Flash devices, the ICAP2 registers

(TAIC2HR, TAIC2LR) are not available on

Timer A. The corresponding interrupts cannot be used (ICF2 is forced by hardware to 0).

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16-BIT TIMER (Cont’d)

Figure 39. Input Capture Block Diagram

ICAP1 pin

ICAP2 pin

EDGE DETECT

CIRCUIT2

EDGE DETECT

CIRCUIT1

IC2R Register IC1R Register

16-BIT

16-BIT FREE RUNNING

COUNTER

ICIE

ICF1

(Control Register 1) CR1

IEDG1

ICF2

(Status Register) SR

0 0 0

(Control Register 2) CR2

CC1 CC0 IEDG2

Figure 40. Input Capture Timing Diagram

TIMER CLOCK

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

FF01 FF02

ICAPi REGISTER

Note: The rising edge is the a ctive edge.

FF03

FF03

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16-BIT TIMER (Cont’d)

10.3.3.4 Output Compare

In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer.

This function can be used to control an output waveform or indicate when a period of time has elapsed.

When a match is found between the Output Compare register and the free running counter, the output compare function:

– Assigns pins with a programmable value if the

OCiE bit is set

– Sets a flag in the status register

– Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.

OCiR

MS Byte

OCiHR

LS Byte

OCiLR

These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC i R value to 8000h.

Timing resolution is one count of the free running counter: ( f

CPU/ CC[1:0]

).

Procedure:

To use the output compare function, select the following in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i signal.

– Select the timer clock (CC[1:0]) (see

Table 16

Clock Control Bits

).

And select the following in the CR1 register:

– Select the OLVLi bit to applied to the OCMPi pins after the match occurs.

– Set the OCIE bit to generate an interrupt if it is needed.

When a match is found between OCRi register and CR register:

– OCFi bit is set.

– The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC).

The OC i R register value required for a specific timing application can be calculated using the following formula:

∆

OCiR =

∆t

*

f

CPU

PRESC

Where:

∆ t = Output compare period (in seconds) f

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see

Table 16

Clock Control Bits )

If the timer clock is an external clock, the formula is:

∆

OCiR =

∆t

*

f

EXT

Where:

∆ t = Output compare period (in seconds) f

EXT

= External timer clock frequency (in hertz)

Clearing the output compare interrupt request (i.e.

clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is set.

2. An access (read or write) to the OCiLR register.

The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OC i R register:

– Write to the OCiHR register (further compares are inhibited).

– Read the SR register (first step of the clearance of the OCFi bit, which may be already set).

– Write to the OCiLR register (enables the output compare function and clears the OCFi bit).

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16-BIT TIMER (Cont’d)

Notes:

1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written.

2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set.

3. When the timer clock is f

CPU

/2, OCFi and

OCMPi are set while the counter value equals

the OCiR register value (see Figure 42 on page

67

). This behaviour is the same in OPM or

PWM mode.

When the timer clock is f

CPU

/4, f

CPU

/8 or in external clock mode, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see

Figure 43 on page 67

).

4. The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used.

5. The value in the 16-bit OC i R register and the

OLVi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout.

6. In Flash devices, the TAOC2HR, TAOC2LR registers are “write only” in Timer A. The corresponding event cannot be generated (OCF2 is forced by hardware to 0).

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The OCFi bit is then not set by hardware, and thus no interrupt request is generated.

The FOLVLi bits have no effect in both one pulse mode and PWM mode.

Figure 41. Output Compare Block Diagram

16 BIT FREE RUNNING

COUNTER

16-bit

OUTPUT COMPARE

CIRCUIT

16-bit 16-bit

OC1R Register

OC2R Register

OC1E OC2E

OCIE

CC1 CC0

(Control Register 2) CR2

(Control Register 1) CR1

FOLV2 FOLV1 OLVL2 OLVL1

Latch

1

Latch

2

OCF1 OCF2 0 0 0

(Status Register) SR

OCMP1

Pin

OCMP2

Pin

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16-BIT TIMER (Cont’d)

Figure 42. Output Compare Timing Diagram, f

TIMER

=f

CPU

/2

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

2ED3

Figure 43. Output Compare Timing Diagram, f

TIMER

=f

CPU

/4

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

2ECF 2ED0 2ED1 2ED2 2ED3 2ED4

2ED3

OUTPUT COMPARE FLAG i (OCFi)

OCMPi PIN (OLVLi=1)

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16-BIT TIMER (Cont’d)

10.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1 function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).

2. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input).

3. Select the following in the CR2 register:

– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.

– Set the OPM bit.

– Select the timer clock CC[1:0] (see Table 16

Clock Control Bits

).

When event occurs on ICAP1

One pulse mode cycle

ICR1 = Counter

OCMP1 = OLVL2

Counter is reset to FFFCh

ICF1 bit is set

When

Counter

= OC1R

OCMP1 = OLVL1

Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The OC1R register value required for a specific timing application can be calculated using the following formula:

OCiR Value = t

* f

CPU

PRESC

- 5

Where: t = Pulse period (in seconds) f

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see

Table 16

Clock Control Bits )

If the timer clock is an external clock the formula is:

OCiR = t

* f

EXT

-5

Where: t = Pulse period (in seconds) f

EXT

= External timer clock frequency (in hertz)

When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 44 ).

Notes:

1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode.

6. In Flash devices, Timer A OCF2 bit is forced by hardware to 0.

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16-BIT TIMER (Cont’d)

Figure 44. One Pulse Mode Timing Example

IC1R

COUNTER

01F8 FFFC FFFD FFFE

ICAP1

OCMP1

OLVL2

01F8

2ED0 2ED1 2ED2

2ED3

2ED3

FFFC FFFD

OLVL2 compare1

OLVL1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

Figure 45. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions

COUNTER 34E2

FFFC FFFD FFFE

OLVL2

OCMP1 compare2

2ED0 2ED1 2ED2 34E2 FFFC compare1

OLVL1 OLVL2 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

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16-BIT TIMER (Cont’d)

10.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and

OC2R registers.

Pulse Width Modulation mode uses the complete

Output Compare 1 function plus the OC2R register, and so this functionality can not be used when

PWM mode is activated.

In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are taken into account only at the end of the PWM period

(OC2) to avoid spikes on the PWM output pin

(OCMP1).

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column.

2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the opposite column.

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register.

– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC2R register.

4. Select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.

– Set the PWM bit.

– Select the timer clock (CC[1:0]) (see

Table 16

Clock Control Bits

).

Pulse Width Modulation cycle

When

Counter

= OC1R

OCMP1 = OLVL1

When

Counter

= OC2R

OCMP1 = OLVL2

Counter is reset to FFFCh

ICF1 bit is set

If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the OC2R and

OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.

The OC i R register value required for a specific timing application can be calculated using the following formula: t

* f

CPU

OCiR Value =

- 5

PRESC

Where: t = Signal or pulse period (in seconds) f

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see

Table 16 )

If the timer clock is an external clock the formula is:

OCiR = t

* f

EXT

-5

Where: t = Signal or pulse period (in seconds) f

EXT

= External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter to be initialized to FFFCh (See

Figure 45 )

Notes:

1. After a write instruction to the OCiHR register, the output compare function is inhibited until the

OCiLR register is also written.

2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.

4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

6. In Flash devices, the TAOC2HR, TAOC2LR registers in Timer A are “write only”. A read operation returns an undefined value.

7. In Flash devices, the ICAP2 registers

(TAIC2HR, TAIC2LR) are not available in Timer A.

The ICF2 bit is forced by hardware to 0.

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16-BIT TIMER (Cont’d)

10.3.4 Low Power Modes

Mode Description

WAIT

No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

16-bit Timer registers are frozen.

HALT

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register.

10.3.5 Interrupts

Interrupt Event

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

Event

Flag

Enable

Control

Bit

ICF1

ICF2 *

OCF1

OCF2 *

TOF

ICIE

OCIE

TOIE

Exit from

Wait

Yes

Yes

Yes

Yes

Yes

Exit from

Halt

No

No

No

No

No

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

* In Flash devices, the ICF2 and OCF2 bits are forced by hardware to 0 in Timer A, hence there is no interrupt event for these flags.

10.3.6 Summary of Timer modes

MODES

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse Mode

PWM Mode

Input Capture 1

Yes

Yes

No

No

TIMER RESOURCES

Input Capture 2 Output Compare 1 Output Compare 2

Yes

2)5)

Yes Yes

4)

Yes

5)

Yes Yes

4)

Not

Recommended

1)5)

Not

Recommended

3)5)

No

No

Partially

No

2)

1) See note 4 in

Section 10.3.3.5 One Pulse Mode

2) See note 5 and 6 in Section 10.3.3.5 One Pulse Mode

3) See note 4 in

Section 10.3.3.6 Pulse Width Modulation Mode

4) In Flash devices, the TAOC2HR, TAOC2LR registers are write only in Timer A. Output Compare 2 event cannot be generated, OCF2 is forced by hardware to 0.

5) In Flash devices, Input Capture 2 is not implemented in Timer A. ICF2 bit is forced by hardware to 0.

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16-BIT TIMER (Cont’d)

10.3.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers

(16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter.

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1: Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison.

CONTROL REGISTER 1 (CR1)

Read/Write

Reset Value: 0000 0000 (00h)

7 0

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison.

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2 register.

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16-BIT TIMER (Cont’d)

CONTROL REGISTER 2 (CR2)

Read/Write

Reset Value: 0000 0000 (00h)

7 0

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active.

0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2 function of the timer remains active.

0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Note: In Flash devices, this bit is not available for

Timer A. It must be kept at its reset value.

Bit 5 = OPM One Pulse Mode.

0: One Pulse Mode is not active.

1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.

Bit 3, 2 = CC[1:0] Clock Control.

The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Timer Clock f

CPU

/ 4 f

CPU

/ 2 f

CPU

/ 8

External Clock (where available)

1

Note: If the external clock pin is not available, programming the external clock configuration stops the counter.

CC1

0

0

1

CC0

0

1

0

1

Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = EXEDG External Clock Edge.

This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

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16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Read Only (except bit 2 R/W)

Reset Value: xxxx x0xx (xxh)

7

ICF1 OCF1 TOF ICF2 OCF2 TIMD 0

0

0

Bit 7 = ICF1 Input Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the

IC1R (IC1LR) register.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR

(CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R

(IC2LR) register.

Note: In Flash devices, this bit is not available for

Timer A and is forced by hardware to 0.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.

Note: In Flash devices, this bit is not available for

Timer A and is forced by hardware to 0.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

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16-BIT TIMER (Cont’d)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).

7 0

MSB LSB

OUTPUT COMPARE 1 HIGH REGISTER

(OC1HR)

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

7 0

MSB LSB

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).

7 0

MSB LSB

OUTPUT COMPARE 1 LOW REGISTER

(OC1LR)

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

7 0

MSB LSB

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16-BIT TIMER (Cont’d)

OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part of the value to be compared to the CHR register.

7

MSB

0

LSB

COUNTER HIGH REGISTER (CHR)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

7 0

MSB LSB

Note: In Flash devices, the Timer A OC2HR register is write-only.

OUTPUT COMPARE 2 LOW REGISTER

(OC2LR)

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of the value to be compared to the CLR register.

7

MSB

0

LSB

COUNTER LOW REGISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit.

7 0

MSB LSB

Note: In Flash devices, the Timer A OC2LR register is write-only.

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ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part of the counter value.

7 0

MSB LSB

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred by the

Input Capture 2 event).

7 0

MSB LSB

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the

CSR register.

7 0

MSB LSB

Note: In Flash devices, this register is not implemented for Timer A.

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).

7 0

MSB LSB

Note: In Flash devices, this register is not implemented for Timer A.

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16-BIT TIMER (Cont’d)

Table 17. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

Timer A: 32

Timer B: 42

Timer A: 31

Timer B: 41

Timer A: 33

Timer B: 43

Timer A: 34

Timer B: 44

Timer A: 35

Timer B: 45

Timer A: 36

Timer B: 46

Timer A: 37

Timer B: 47

Timer A: 3E

3

Timer B: 4E

Timer A: 3F

3

Timer B: 4F

Timer A: 38

Timer B: 48

Timer A: 39

Timer B: 49

Timer A: 3A

Timer B: 4A

Timer A: 3B

Timer B: 4B

Timer A: 3C

4

Timer B: 4C

Timer A: 3D

4

Timer B: 4D

CR1

Reset Value

CR2

Reset Value

CSR

Reset Value

IC1HR

Reset Value

IC1LR

Reset Value

OC1HR

Reset Value

OC1LR

Reset Value

OC2HR

Reset Value

OC2LR

Reset Value

CHR

Reset Value

CLR

Reset Value

ACHR

Reset Value

ACLR

Reset Value

IC2HR

Reset Value

IC2LR

Reset Value

7

MSB

1

MSB

1

MSB

1

MSB x

MSB x

MSB x

MSB

1

MSB

0

MSB

1

ICIE

0

OC1E

0

ICF1 x

MSB x

MSB

0

MSB

1

6

OCIE

0

OC2E

1

0

OCF1 x x x

0

0

0

0

1

1

1

1 x x

5

TOIE

0

OPM

0

TOF x x x

0

0

0

0

1

1

1

1 x x

4

FOLV2

1

0

PWM

0

ICF2

2 x x x

0

0

0

0

1

1

1

1 x x

3

FOLV1

0

CC1

0

OCF2

2 x x x

0

0

0

0

1

1

1

1 x x

0

0 x

0

0

1

1 x x

1

1

2

OLVL2

0

CC0

0

TIMD

0 x

1

IEDG1

0

IEDG2

1

0

x x x

0

0

0

0

1

0

1

0 x x

0

LSB

0

LSB

1

LSB

0

LSB x

LSB x

LSB x

LSB

0

LSB

0

LSB

0

OLVL1

0

EXEDG

0

x

LSB x

LSB

0

LSB

1

1

In Flash devices, these bits are not used in Timer A and must be kept cleared.

2

In Flash devices, these bits are forced by hardware to 0 in Timer A

3

In Flash devices, the TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values

4

In Flash devices, the TAIC2HR and TAIC2LR registers are not present.

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10.4 SERIAL PERIPHERAL INTERFACE (SPI)

10.4.1 Introduction

The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system.

10.4.2 Main Features

■

■

■

■

■

■

■

■

■

Full duplex synchronous transfers (on 3 lines)

Simplex synchronous transfers (on 2 lines)

Master or slave operation

Six master mode frequencies (f

CPU

/4 max.) f

CPU

/2 max. slave mode frequency (see note)

SS Management by software or hardware

Programmable clock polarity and phase

End of transfer interrupt flag

Write collision, Master Mode Fault and Overrun flags

Figure 46. Serial Peripheral Interface Block Diagram

Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence.

10.4.3 General Description

Figure 46

shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

The SPI is connected to external devices through

4 pins:

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

– SCK: Serial Clock out by SPI masters and input by SPI slaves

Data/Address Bus

Read

SPIDR

Read Buffer

Interrupt request

MOSI

MISO

8-Bit Shift Register

7

SPIF WCOL OVR MODF 0

SPICSR 0

SOD SSM SSI

Write

SOD bit

SS

1

0

SCK

SPI

STATE

CONTROL

7 SPICR 0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

MASTER

CONTROL

SERIAL CLOCK

GENERATOR

SS

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– SS: Slave select:

This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master MCU.

10.4.3.1 Functional Description

A basic example of interconnections between a single master and a single slave is illustrated in

Figure 47

.

The MOSI pins are connected together and the

MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first).

Figure 47. Single Master/ Single Slave Application

The communication is always initiated by the master. When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex communication with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).

To use a single data line, the MISO and MOSI pins must be connected at each node (in this case only simplex communication is possible).

Four possible data/clock timing relationships may

be chosen (see Figure 50

) but master and slave must be programmed with the same timing mode.

MASTER

MSBit LSBit

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

MOSI

SLAVE

MSBit LSBit

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

SCK

SS

+5V

SCK

SS

Not used if SS is managed

by software

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10.4.3.2 Slave Select Management

As an alternative to using the SS pin to control the

Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see

Figure 49

)

In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the

SPICSR register.

In Master mode:

– SS internal must be held high continuously

In Slave Mode:

There are two cases depending on the data/clock

timing relationship (see Figure 48 ):

If CPHA=1 (data latched on 2nd clock edge):

– SS internal must be held low during the entire transmission. This implies that in single slave applications the SS pin either can be tied to

V

SS

, or made free for standard I/O by managing the SS function by software (SSM= 1 and

SSI=0 in the in the SPICSR register)

If CPHA=0 (data latched on 1st clock edge):

– SS internal must be held low during byte transmission and pulled high between each byte to allow the slave to write to the shift register. If SS is not pulled high, a Write Collision error will occur when the slave writes to the

shift register (see Section 10.4.5.3

).

Figure 48. Generic SS Timing Diagram

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Byte 1 Byte 2 Byte 3

Figure 49. Hardware/Software Slave Select Management

SSM bit

SSI bit

SS external pin

1

0

SS internal

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10.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the

SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not taken into account):

1. Write to the SPICR register:

– Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

50 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence.

3. Write to the SPICR register:

– Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if

SS is high).

The transmit sequence begins when software writes a byte in the SPIDR register.

10.4.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the

SPIF bit is set

2. A read to the SPIDR register.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR register is read.

10.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the

SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the following actions:

– Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see

Figure 50 ).

Note: The slave must have the same CPOL and CPHA settings as the master.

– Manage the SS pin as described in

Section

10.4.3.2

and

Figure 48

. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register.

2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.

10.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most significant bit first.

The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the

SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR register is read.

The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun

condition (see Section 10.4.5.2

).

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10.4.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See

Figure 50

).

Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

The combination of the CPOL clock polarity and

CPHA (clock phase) bits selects the data capture clock edge

Figure 50. Data Clock Timing Diagram

CPHA =1

Figure 50 , shows an SPI transfer with the four

combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device.

Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.

SCK

(CPOL = 1)

SCK

(CPOL = 0)

MISO

(from master)

MSBit Bit 6

MOSI

(from slave)

SS

(to slave)

CAPTURE STROBE

MSBit Bit 6

Bit 5 Bit 4

Bit 5 Bit 4

Bit3 Bit 2 Bit 1 LSBit

Bit3 Bit 2 Bit 1 LSBit

CPHA =0

SCK

(CPOL = 1)

SCK

(CPOL = 0)

MISO

(from master)

MOSI

(from slave)

MSBit

MSBit

Bit 6

Bit 6

Bit 5

Bit 5

Bit 4

Bit 4

Bit3

Bit3

Bit 2

Bit 2

Bit 1

Bit 1

SS

(to slave)

CAPTURE STROBE

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

LSBit

LSBit

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10.4.5 Error Flags

10.4.5.1 Master Mode Fault (MODF)

Master mode fault occurs when the master device has its SS pin pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral.

– The MSTR bit is reset, thus forcing the device into slave mode.

Clearing the MODF bit is done through a software sequence:

1. A read access to the SPICSR register while the

MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The

SPE and MSTR bits may be restored to their original state during or after this clearing sequence.

Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.

10.4.5.2 Overrun Condition (OVR)

An overrun condition occurs, when the master device has sent a data byte and the slave device has not cleared the SPIF bit issued from the previously transmitted byte.

When an Overrun occurs:

– The OVR bit is set and an interrupt request is generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the SPIDR register returns this byte. All other bytes are lost.

The OVR bit is cleared by reading the SPICSR register.

10.4.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to write to the SPIDR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful.

Write collisions can occur both in master and slave mode. See also

Section 10.4.3.2 Slave Select

Management

.

Note: a “read collision” will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation.

The WCOL bit in the SPICSR register is set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 51 ).

Figure 51. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

Read SPICSR

1st Step

2nd Step

Read SPIDR

RESULT

SPIF =0

WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

Read SPICSR

1st Step

2nd Step Read SPIDR

RESULT

WCOL=0

Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit

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10.4.5.4 Single Master Systems

A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see

Figure 52

).

The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices.

The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission.

For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written to its SPIDR register.

Other transmission security methods can use ports for handshake lines or data bytes with command fields.

Figure 52. Single Master / Multiple Slave Configuration

SCK

Slave

MCU

SS

MOSI MISO

SCK

Slave

MCU

SS

MOSI MISO

SCK

Slave

MCU

SS

MOSI MISO

SCK

Slave

MCU

SS

MOSI MISO

5V

MOSI MISO

SCK

Master

MCU

SS

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10.4.6 Low Power Modes

Mode Description

WAIT

HALT

No effect on SPI.

SPI interrupt events cause the device to exit from WAIT mode.

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching). If several data are received before the wakeup event, then an overrun error is generated.

This error can be detected after the fetch of the interrupt routine that woke up the device.

Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the

SPI from Halt mode state to normal state. If the

SPI exits from Slave mode, it returns to normal state immediately.

Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave selection is configured as external (see

Section

10.4.3.2

), make sure the master drives a low level on the SS pin when the slave enters Halt mode.

10.4.7 Interrupts

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from

Wait

Exit from

Halt

10.4.6.1 Using the SPI to wakeup the MCU from

Halt mode

In slave configuration, the SPI is able to wakeup the ST7 device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware.

SPI End of Transfer

Event

Master Mode Fault

Event

Overrun Error

SPIF

MODF

OVR

SPIE

Yes

Yes

Yes

Yes

No

No

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

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10.4.8 Register Description

CONTROL REGISTER (SPICR)

Read/Write

Reset Value: 0000 xxxx (0xh)

7 0

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Bit 7 = SPIE Serial Peripheral Interrupt Enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever

SPIF=1, MODF=1 or OVR=1 in the SPICSR register

Bit 3 = CPOL Clock Polarity.

This bit is set and cleared by software. This bit determines the idle state of the serial Clock. The

CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit.

Bit 2 = CPHA Clock Phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture edge.

1: The second clock transition is the first capture edge.

Note: The slave must have the same CPOL and

CPHA settings as the master.

Bit 6 = SPE Serial Peripheral Output Enable.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0

(see

Section 10.4.5.1 Master Mode Fault

(MODF) ). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the external pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider Enable.

This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to

Table 18 SPI Master mode SCK Frequency

.

0: Divider by 2 enabled

1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR Master Mode.

This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0

(see

Section 10.4.5.1 Master Mode Fault

(MODF) ).

0: Slave mode

1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.

Bits 1:0 = SPR[1:0] Serial Clock Frequency.

These bits are set and cleared by software. Used with the SPR2 bit, they select the baud rate of the

SPI serial clock SCK output by the SPI in master mode.

Note: These 2 bits have no effect in slave mode.

Table 18. SPI Master mode SCK Frequency

Serial Clock f

CPU

/4 f

CPU

/8 f

CPU

/16 f

CPU

/32 f

CPU

/64 f

CPU

/128

SPR2 SPR1 SPR0

1

0

0

0

0

1

0

0

0

1

1

1

0

0

0

1

1

0

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CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only)

Reset Value: 0000 0000 (00h)

7 0

SPIF WCOL OVR MODF SOD SSM SSI

Bit 7 = SPIF Serial Peripheral Data Transfer Flag

(Read only).

This bit is set by hardware when a transfer has been completed. An interrupt is generated if

SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the

SPIDR register).

0: Data transfer is in progress or the flag has been cleared.

1: Data transfer between the device and an external device has been completed.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR register is read.

Bit 6 = WCOL Write Collision status (Read only).

This bit is set by hardware when a write to the

SPIDR register is done during a transmit sequence. It is cleared by a software sequence (see

Figure 51

).

0: No write collision occurred

1: A write collision has been detected

Bit 5 = OVR SPI Overrun error (Read only).

This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1

(See Section 10.4.5.2

). An interrupt is generated if

SPIE = 1 in SPICR register. The OVR bit is cleared by software reading the SPICSR register.

0: No overrun error

1: Overrun error detected

Bit 4 = MODF Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is pulled low in master mode (see

Master Mode Fault (MODF)

0: No master mode fault detected

Section 10.4.5.1

). An SPI interrupt can be generated if SPIE=1 in the SPICSR register.

This bit is cleared by a software sequence (An access to the SPICR register while MODF=1 followed by a write to the SPICR register).

1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD SPI Output Disable.

This bit is set and cleared by software. When set, it disables the alternate function of the SPI output

(MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE=1)

1: SPI output disabled

Bit 1 = SSM SS Management.

This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See

Section

10.4.3.2 Slave Select Management

.

0: Hardware management (SS managed by external pin)

1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O)

Bit 0 = SSI SS Internal Mode.

This bit is set and cleared by software. It acts as a

‘chip select’ by controlling the level of the SS slave select signal when the SSM bit is set.

0: Slave selected

1: Slave deselected

DATA I/O REGISTER (SPIDR)

Read/Write

Reset Value: Undefined

7

D7 D6 D5 D4 D3 D2 D1

0

D0

The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte.

Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.

Warning: A write to the SPIDR register places data directly into the shift register for transmission.

A read to the SPIDR register returns the value located in the buffer and not the content of the shift

register (see Figure 46 ).

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Table 19. SPI Register Map and Reset Values

Address

(Hex.)

0021h

0022h

0023h

Register

Label

SPIDR

Reset Value

SPICR

Reset Value

SPICSR

Reset Value

7

MSB x

SPIE

0

SPIF

0

6 x

SPE

0

WCOL

0

5 x

SPR2

0

OR

0

4 x

MSTR

0

MODF

0

3 2 x

CPOL x

0 x

CPHA x

SOD

0

1 x

SPR1 x

SSM

0

0

LSB x

SPR0 x

SSI

0

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10.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

■

■

10.5.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard

NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.

10.5.2 Main Features

■

■

■

■

■

■

■

Full duplex, asynchronous communications

NRZ standard format (Mark/Space)

Dual baud rate generator systems

Independently programmable transmit and receive baud rates up to 500K baud

Programmable data word length (8 or 9 bits)

Receive buffer full, Transmit buffer empty and

End of Transmission flags

Two receiver wake-up modes:

■

– Address bit (MSB)

– Idle line

Muting function for multiprocessor configurations

Separate enable bits for Transmitter and

Receiver

Four error detection flags:

– Overrun error

■

■

■

– Noise error

– Frame error

– Parity error

Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error detected

Parity control:

– Transmits parity bit

– Checks parity of received data byte

Reduced power consumption mode

10.5.3 General Description

The interface is externally connected to another device by two pins (see Figure 2.

):

– TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port configuration. When the transmitter and/or the receiver are enabled and nothing is to be transmitted, the TDO pin is at high level.

– RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.

Through these pins, serial data is transmitted and received as frames comprising:

– An Idle Line prior to transmission or reception

– A start bit

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the frame is complete

This interface uses two types of baud rate generator:

– A conventional type for commonly-used baud rates

– An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies

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Figure 53. SCI Block Diagram

TDO

RDI

Write

Transmit Data Register (TDR)

Read

(DATA REGISTER) DR

Received Data Register (RDR)

Transmit Shift Register Received Shift Register

CR1

R8 T8 SCID M WAKE PCE PS PIE

TRANSMIT

CONTROL

WAKE

UP

UNIT

CR2

TIE TCIE RIE ILIE TE RE RWU SBK

SCI

INTERRUPT

CONTROL

TRANSMITTER

CLOCK f

CPU

/16 /PR

RECEIVER

CONTROL

RECEIVER

CLOCK

TDRE TC RDRF IDLE OR NF FE PE

SR

TRANSMITTER RATE

CONTROL

BRR

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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10.5.4 Functional Description

The block diagram of the Serial Control Interface, is shown in Figure 1.

It contains six dedicated registers:

– Two control registers (SCICR1 & SCICR2)

– A status register (SCISR)

– A baud rate register (SCIBRR)

– An extended prescaler receiver register (SCIER-

PR)

– An extended prescaler transmitter register (SCI-

ETPR)

Refer to the register descriptions in Section 0.1.7

for the definitions of each bit.

10.5.4.1 Serial Data Format

Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 1.

).

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data.

A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their own baud rate generator.

Figure 54. Word Length Programming

9-bit Word length (M bit is set)

Start

Bit Bit0 Bit1

Data Frame

Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Possible

Parity

Bit

Bit8

Next Data Frame

Stop

Bit

Next

Start

Bit

Idle Frame

Start

Bit

Break Frame Extra

‘1’

Start

Bit

8-bit Word length (M bit is reset)

Start

Bit Bit0

Data Frame

Bit1 Bit2 Bit3 Bit4 Bit5 Bit6

Possible

Parity

Bit

Bit7

Stop

Bit

Next Data Frame

Next

Start

Bit

Idle Frame

Break Frame

Start

Bit

Extra

‘1’

Start

Bit

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10.5.4.2 Transmitter

The transmitter can send data words of either 8 or

9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be stored in the T8 bit in the SCICR1 register.

Character Transmission

During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 1.

).

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR and the SCIETPR registers.

– Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission.

– Access the SCISR register and write the data to send in the SCIDR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.

Clearing the TDRE bit is always performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

The TDRE bit is set by hardware and it indicates:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the SCIDR register without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register.

When a transmission is taking place, a write instruction to the SCIDR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.

When no transmission is taking place, a write instruction to the SCIDR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.

When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the

CCR register.

Clearing the TC bit is performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note: The TDRE and TC bits are cleared by the same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 2.

).

As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI to send an idle frame before the first data frame.

Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.

Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte in the

SCIDR.

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10.5.4.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the

SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 1.

).

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR and the SCIERPR registers.

– Set the RE bit, this enables the receiver which begins searching for a start bit.

When a character is received:

– The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR.

– An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.

– The error flags can be set if a frame error, noise or an overrun error has been detected during reception.

Clearing the RDRF bit is performed by the following software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register.

The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error.

Break Character

When a break character is received, the SCI handles it as a framing error.

Idle Character

When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.

Overrun Error

An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the

RDR register as long as the RDRF bit is not cleared.

When an overrun error occurs:

– The OR bit is set.

– The RDR content is not lost.

– The shift register is overwritten.

– An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.

Noise Error

Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th).

Therefore, to prevent the NF flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples.

When noise is detected in a frame:

– The NF flag is set at the rising edge of the RDRF bit.

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.

The NF flag is reset by a SCISR register read operation followed by a SCIDR register read operation.

During reception, if a false start bit is detected (e.g.

8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the user). This NF flag is accessible along with the RDRF bit when a next valid frame is received.

Note: If the application Start Bit is not long enough to match the above requirements, then the NF

Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the application software when the first valid byte is received.

See also Section 0.1.4.10 .

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Figure 55. SCI Baud Rate and Extended Prescaler Block Diagram

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

SCIETPR

EXTENDED TRANSMITTER PRESCALER REGISTER

SCIERPR

EXTENDED RECEIVER PRESCALER REGISTER

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER

ST72324Jx ST72324Kx

TRANSMITTER

CLOCK

RECEIVER

CLOCK f

CPU

/16 /PR

TRANSMITTER RATE

CONTROL

SCIBRR

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

RECEIVER RATE

CONTROL

CONVENTIONAL BAUD RATE GENERATOR

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Framing Error

A framing error is detected when:

– The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise.

– A break is received.

When the framing error is detected:

– the FE bit is set by hardware

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.

The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation.

10.5.4.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows:

Tx = f

CPU

(16

*

PR)

*

TR f

CPU

Rx =

(16

*

PR)

*

RR with:

PR = 1, 3, 4 or 13 (see SCP[1:0] bits)

TR = 1, 2, 4, 8, 16, 32, 64,128

(see SCT[2:0] bits)

RR = 1, 2, 4, 8, 16, 32, 64,128

(see SCR[2:0] bits)

All these bits are in the SCIBRR register.

Example: If f

CPU

is 8 MHz (normal mode) and if

PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud.

Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled.

10.5.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility.

The extended baud rate generator block diagram is described in the Figure 3.

The output clock rate sent to the transmitter or to the receiver is the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCI-

ERPR or the SCIETPR register.

Note: the extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value other than zero. The baud rates are calculated as follows:

Tx = f

CPU

16

*

ETPR*(PR*TR)

Rx = f

CPU

16

*

ERPR*(PR*RR) with:

ETPR = 1,..,255 (see SCIETPR register)

ERPR = 1,.. 255 (see SCIERPR register)

10.5.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers.

The non addressed devices may be placed in sleep mode by means of the muting function.

Setting the RWU bit by software puts the SCI in sleep mode:

All the reception status bits can not be set.

All the receive interrupts are inhibited.

A muted receiver may be awakened by one of the following two ways:

– by Idle Line detection if the WAKE bit is reset,

– by Address Mark detection if the WAKE bit is set.

Receiver wakes-up by Idle Line detection when the Receive line has recognized an Idle Frame.

Then the RWU bit is reset by hardware but the

IDLE bit is not set.

Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the

RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.

CAUTION: In Mute mode, do not write to the

SCICR2 register. If the SCI is in Mute mode during the read operation (RWU = 1) and a address mark wake up event occurs (RWU is reset) before the write operation, the RWU bit is set again by this write operation. Consequently the address byte is lost and the SCI is not woken up from Mute mode.

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10.5.4.7 Parity Control

Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register.

Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in

Table 1 .

Table 20. Frame Formats

M bit

0

0

PCE bit

0

1

SCI frame

| SB | 8 bit data | STB |

| SB | 7-bit data | PB | STB |

1 0 | SB | 9-bit data | STB |

1 1 | SB | 8-bit data PB | STB |

Legend: SB = Start Bit, STB = Stop Bit,

PB = Parity Bit

Note: In case of wake up by an address mark, the

MSB bit of the data is taken into account and not the parity bit

Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).

Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to

0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is not transmitted but is changed by the parity bit.

Reception mode: If the PCE bit is set then the interface checks if the received data byte has an even number of “1s” if even parity is selected

(PS = 0) or an odd number of “1s” if odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register.

10.5.4.8 SCI Clock Tolerance

During reception, each bit is sampled 16 times.

The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value is “1”, but the

Noise Flag bit is set because the three samples values are not the same.

Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%.

Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge.

Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 Kbaud (bit length is 64µs), then the 8th,

9th and 10th samples are at 28µs, 32µs and 36µs respectively (the first sample starting ideally at

0µs). But if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by ~4us. This means the entire bit length must be at least 40µs

(36µs for the 10th sample + 4µs for synchronization with the internal sampling clock).

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10.5.4.9 Clock Deviation Causes

The causes which contribute to the total deviation are:

– D

TRA

: Deviation due to transmitter error (Local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate).

– D

QUANT

: Error due to the baud rate quantization of the receiver.

– D

REC

: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message.

– D

TCL

: Deviation due to the transmission line

(generally due to the transceivers)

All the deviations of the system should be added and compared to the SCI clock tolerance:

D

TRA

+ D

QUANT

+ D

REC

+ D

TCL

< 3.75%

10.5.4.10 Noise Error Causes

See also description of Noise error in Section

0.1.4.3 .

Start bit

The noise flag (NF) is set during start bit reception if one of the following conditions occurs:

1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a “1”.

2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a

“1”.

Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set.

Data Bits

The noise flag (NF) is set during normal data bit reception if the following condition occurs:

– During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same.

The majority of the 8th, 9th and 10th samples is considered as the bit value.

Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise

Flag getting set.

Figure 56. Bit Sampling in Reception Mode

RDI LINE

Sample

clock sampled values

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

7/16

6/16

7/16

One bit time

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10.5.5 Low Power Modes

Mode Description

No effect on SCI.

WAIT SCI interrupts cause the device to exit from

Wait mode.

SCI registers are frozen.

HALT In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

10.5.6 Interrupts

The SCI interrupt events are connected to the same interrupt vector.

These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit from

Wait

Transmit Data Register

Empty

Transmission Complete

TDRE TIE

TC TCIE

Yes

Yes

Received Data Ready to be Read

Overrun Error Detected

Idle Line Detected

Parity Error

RDRF

OR

IDLE

PE

RIE

ILIE

PIE

Yes

Yes

Yes

Yes

Exit from

Halt

No

No

No

No

No

No

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10.5.7 Register Description

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

Note: The IDLE bit is not set again until the RDRF bit has been set itself (that is, a new idle line occurs).

7

TDRE TC RDRF IDLE OR NF FE

Bit 7 = TDRE Transmit data register empty.

0

PE

This bit is set by hardware when the content of the

TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register).

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Note: Data is not transferred to the shift register unless the TDRE bit is cleared.

Bit 3 = OR Overrun error.

This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF = 1.

An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: No Overrun error

1: Overrun error is detected

Note: When this bit is set RDR register content is not lost but the shift register is overwritten.

Bit 6 = TC Transmission complete.

This bit is set by hardware when transmission of a frame containing Data is complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the

SCISR register followed by a write to the SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

Bit 2 = NF Noise flag.

This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: No noise is detected

1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt.

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when the content of the

RDR register has been transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the

SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

Bit 1 = FE Framing error.

This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: No Framing error is detected

1: Framing error or break character is detected

Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set.

Bit 4 = IDLE Idle line detect.

This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).

0: No Idle Line is detected

1: Idle Line is detected

Bit 0 = PE Parity error.

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.

0: No parity error

1: Parity error

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CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

7 0

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is set or cleared by software.

0: Idle Line

1: Address Mark

R8 T8 SCID M WAKE PCE PS PIE

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received word when M = 1.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmitted word when M = 1.

Bit 2 = PCE Parity control enable.

This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission).

0: Parity control disabled

1: Parity control enabled

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte.

0: Even parity

1: Odd parity

Bit 4 = M Word length.

This bit determines the word length. It is set or cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data transfer (both transmission and reception).

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hardware parity control when a parity error is detected

(PE bit set). It is set and cleared by software.

0: Parity error interrupt disabled

1: Parity error interrupt enabled.

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CONTROL REGISTER 2 (SCICR2)

Read/Write

Reset Value: 0000 0000 (00h)

7

TIE TCIE RIE ILIE TE RE RWU

0

SBK

Notes:

– During transmission, a “0” pulse on the TE bit

(“0” followed by “1”) sends a preamble (idle line) after the current word.

– When TE is set there is a 1 bit-time delay before the transmission starts.

CAUTION: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set).

Bit 7 = TIE Transmitter interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever

TDRE=1 in the SCISR register

Bit 6 = TCIE Transmission complete interrupt ena- ble

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in the SCISR register

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared by software.

0: Receiver is disabled

1: Receiver is enabled and begins searching for a start bit

Bit 5 = RIE Receiver interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SCISR register

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized.

0: Receiver in Active mode

1: Receiver in Mute mode

Note: Before selecting Mute mode (setting the

RWU bit), the SCI must receive some data first, otherwise it cannot function in Mute mode with wake-up by idle line detection.

Bit 4 = ILIE Idle line interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE=1 in the SCISR register.

Bit 3 = TE Transmitter enable.

This bit enables the transmitter. It is set and cleared by software.

0: Transmitter is disabled

1: Transmitter is enabled

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the transmitter sends a BREAK word at the end of the current word.

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DATA REGISTER (SCIDR)

Read/Write

Reset Value: Undefined

Contains the Received or Transmitted data character, depending on whether it is read from or written to.

Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.

7

(RDR).

0

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception

The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 1.

).

The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 1.

).

TR dividing factor

1

2

4

8

16

32

64

128

Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud

Rate Generator mode.

1

1

1

1

SCT2

0

0

0

0

1

1

0

0

SCT1

0

0

1

1

0

1

0

1

SCT0

0

1

0

1

BAUD RATE REGISTER (SCIBRR)

Read/Write

Reset Value: 0000 0000 (00h)

7 clock division ranges:

0

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

Bits 7:6 = SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard

RR Dividing factor

1

2

4

8

16

32

64

128

SCR2

0

0

0

0

1

1

1

1

SCR1

0

0

1

1

0

0

1

1

SCR0

0

1

0

1

0

1

0

1

PR Prescaling factor

1

3

4

13

SCP1

0

0

1

1

SCP0

0

1

0

1

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EXTENDED RECEIVE PRESCALER DIVISION

REGISTER (SCIERPR)

Read/Write

Reset Value: 0000 0000 (00h)

Allows setting of the Extended Prescaler rate division factor for the receive circuit.

EXTENDED TRANSMIT PRESCALER DIVISION

REGISTER (SCIETPR)

Read/Write

Reset Value:0000 0000 (00h)

Allows setting of the External Prescaler rate division factor for the transmit circuit.

7 0

ERPR

7

ERPR

6

ERPR

5

ERPR

4

ERPR

3

ERPR

2

ERPR

1

ERPR

0

7 0

ETPR

7

ETPR

6

ETPR

5

ETPR

4

ETPR

3

ETPR

2

ETPR

1

ETPR

0

Bits 7:0 = ERPR[7:0] 8-bit Extended Receive

Prescaler Register.

The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.

) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255).

The extended baud rate generator is not used after a reset.

Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit

Prescaler Register.

The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.

) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255).

The extended baud rate generator is not used after a reset.

Table 21. Baudrate Selection

Symbol f f

Tx

Rx

Parameter f

CPU

Communication frequency 8 MHz

Conditions

Accuracy vs

Standard

Prescaler

~0.16%

~0.79%

Conventional Mode

TR (or RR)=128, PR=13

TR (or RR)= 32, PR=13

TR (or RR)= 16, PR=13

TR (or RR)= 8, PR=13

TR (or RR)= 4, PR=13

TR (or RR)= 16, PR= 3

TR (or RR)= 2, PR=13

TR (or RR)= 1, PR=13

Extended Mode

ETPR (or ERPR) = 35,

TR (or RR)= 1, PR=1

Standard

Baud

Rate

300

1200

2400

4800

9600

10400

19200

38400

~300.48

~1201.92

~2403.84

~4807.69

~9615.38

~10416.67

~19230.77

~38461.54

Hz

14400 ~14285.71

Unit

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Table 22. SCI Register Map and Reset Values

Address

(Hex.)

0050h

0051h

0052h

0053h

0054h

0055h

0057h

Register

Label

SCISR

Reset Value

SCIDR

Reset Value

SCIBRR

Reset Value

SCICR1

Reset Value

SCICR2

Reset Value

SCIERPR

Reset Value

SCIPETPR

Reset Value

7

TDRE

1

MSB x

SCP1

0

R8 x

TIE

0

MSB

0

MSB

0

6

TC

1 x

SCP0

0

T8

0

TCIE

0

0

0

5

RDRF

0 x

SCT2

0

SCID

0

RIE

0

0

0

4

IDLE

0 x

SCT1

0

M

0

ILIE

0

0

0

3

OR

0 x

SCT0

0

WAKE

0

TE

0

0

0

2

NF

0 x

SCR2

0

PCE

0

RE

0

0

0

1

FE

0 x

SCR1

0

PS

0

RWU

0

0

0

0

PE

0

LSB x

SCR0

0

PIE

0

SBK

0

LSB

0

LSB

0

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10.6 10-BIT A/D CONVERTER (ADC)

10.6.1 Introduction

The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources.

The result of the conversion is stored in a 10-bit

Data Register. The A/D converter is controlled through a Control/Status Register.

Figure 57. ADC Block Diagram f

CPU DIV 4

0 f

ADC

DIV 2 1

10.6.2 Main Features

■ 10-bit conversion

■

■

Up to 16 channels with multiplexed input

Linear successive approximation

■

■

■

Data register (DR) which contains the results

Conversion complete status flag

On/off bit (to reduce consumption)

The block diagram is shown in

Figure 57 .

EOC SPEED ADON 0 CH3 CH2 CH1 CH0 ADCCSR

4

AIN0

AIN1

AINx

ANALOG

MUX

ANALOG TO DIGITAL

CONVERTER

ADCDRH D9 D8 D7 D6 D5 D4 D3 D2

ADCDRL 0 0 0 0 0 0 D1 D0

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.6.3 Functional Description

The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not.

If the input voltage (V

AIN

) is greater than V

AREF

(high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).

If the input voltage (V

AIN

) is lower than V

SSA

(lowlevel voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h.

The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and AD-

CDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section.

R

AIN

is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.

10.6.3.1 A/D Converter Configuration

The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input.

In the ADCCSR register:

– Select the CS[3:0] bits to assign the analog channel to convert.

10.6.3.2 Starting the Conversion

In the ADCCSR register:

– Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel.

To read the 10 bits, perform the following steps:

1. Poll the EOC bit

2. Read the ADCDRL register

3. Read the ADCDRH register. This clears EOC automatically.

Note: The data is not latched, so both the low and the high data register must be read before the next conversion is complete, so it is recommended to disable interrupts while reading the conversion result.

To read only 8 bits, perform the following steps:

1. Poll the EOC bit

2. Read the ADCDRH register. This clears EOC automatically.

10.6.3.3 Changing the conversion channel

The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel.

10.6.4 Low Power Modes

Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed.

Mode Description

WAIT No effect on A/D Converter

A/D Converter disabled.

HALT

After wakeup from Halt mode, the A/D

Converter requires a stabilization time t

STAB

(see Electrical Characteristics) before accurate conversions can be performed.

When a conversion is complete:

– The EOC bit is set by hardware.

– The result is in the ADCDR registers.

A read to the ADCDRH resets the EOC bit.

10.6.5 Interrupts

None.

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.6.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write (Except bit 7 read only)

Reset Value: 0000 0000 (00h)

7 0

EOC SPEED ADON 0 CH3 CH2 CH1 CH0

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register or writes to any bit of the ADCCSR register.

0: Conversion is not complete

1: Conversion complete

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software.

0: f

ADC

= f

CPU

1: f

ADC

= f

CPU

/4

/2

Bit 5 = ADON A/D Converter on

This bit is set and cleared by software.

0: Disable ADC and stop conversion

1: Enable ADC and start conversion

Bit 4 = Reserved. Must be kept cleared.

Bit 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They select the analog input to convert.

Channel Pin*

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

CH3

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

CH2

0

1

1

1

0

1

0

0

0

0

0

0

1

1

1

1

CH1

0

1

1

1

0

0

0

1

1

1

0

0

0

0

1

1

CH0

1

0

1

1

0

0

1

0

0

1

0

1

0

1

0

1

*The number of channels is device dependent. Refer to the device pinout description.

DATA REGISTER (ADCDRH)

Read Only

Reset Value: 0000 0000 (00h)

7

D9 D8 D7 D6 D5 D4 D3

0

D2

Bit 7:0 = D[9:2] MSB of Converted Analog Value

DATA REGISTER (ADCDRL)

Read Only

Reset Value: 0000 0000 (00h)

7 0

0 0 0 0 0 0 D1

Bit 7:2 = Reserved. Forced by hardware to 0.

D0

Bit 1:0 = D[1:0] LSB of Converted Analog Value

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10-BIT A/D CONVERTER (Cont’d)

Table 23. ADC Register Map and Reset Values

Address

(Hex.)

0070h

0071h

0072h

Register

Label

ADCCSR

Reset Value

ADCDRH

Reset Value

ADCDRL

Reset Value

7

EOC

0

D9

0

0

6

SPEED

0

D8

0

0

5

ADON

0

D7

0

0

4

0

D6

0

0

3

CH3

0

D5

0

0

2

CH2

0

D4

0

0

1

CH1

0

D3

0

D1

0

0

CH0

0

D2

0

D0

0

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11 INSTRUCTION SET

11.1 CPU ADDRESSING MODES

The CPU features 17 different addressing modes which can be classified in 7 main groups:

Addressing Mode

Inherent

Immediate

Direct

Indexed

Indirect

Relative

Bit operation

Bit

Bit

Bit

Bit

Inherent

Immediate

Short

Long

No Offset

Short

Long

Short

Long

Short

Long

Relative

Relative

Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5 so, most of the addressing modes may be subdivided in two sub-modes called long and short:

– Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles.

– Short addressing mode is less powerful because it can generally only access page zero (0000h -

00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only

(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,

INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and short addressing modes.

The CPU Instruction set is designed to minimize the number of bytes required per instruction: To do

Table 24. CPU Addressing Mode Overview

Mode Syntax Destination

Pointer

Address

(Hex.)

Direct

Direct

Direct

Direct

Direct

Indirect

Indirect

Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X)

Indexed ld A,($10,X)

Indexed ld A,($1000,X) ld A,[$10] ld A,[$10.w]

Indirect Indexed ld A,([$10],X)

Indirect Indexed ld A,([$10.w],X)

Direct

Indirect jrne loop jrne [$10]

00..FF

0000..FFFF

00..FF

00..1FE

0000..FFFF

00..FF

00..FF

0000..FFFF

00..FF

00..1FE

00..FF

0000..FFFF

00..FF

PC+/-127

PC+/-127 00..FF

Direct

Indirect bset $10,#7 bset [$10],#7

00..FF

00..FF

Direct Relative btjt $10,#7,skip 00..FF

Indirect Relative btjt [$10],#7,skip 00..FF

00..FF

00..FF

Pointer Size

(Hex.) byte word byte word byte byte byte

Length

(Bytes)

+ 2

+ 2

+ 1

+ 2

+ 1

+ 2

+ 2

+ 2

+ 1

+ 2

+ 2

+ 3

+ 0

+ 1

+ 1

+ 2

+ 0

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.1 Inherent

All Inherent instructions consist of a single byte.

The opcode fully specifies all the required information for the CPU to process the operation.

Inherent Instruction

NOP

TRAP

WFI

HALT

RET

IRET

SIM

RIM

SCF

RCF

RSP

LD

CLR

PUSH/POP

INC/DEC

TNZ

CPL, NEG

MUL

SLL, SRL, SRA, RLC,

RRC

SWAP

Function

No operation

S/W Interrupt

Wait For Interrupt (Low Power Mode)

Halt Oscillator (Lowest Power

Mode)

Sub-routine Return

Interrupt Sub-routine Return

Set Interrupt Mask (level 3)

Reset Interrupt Mask (level 0)

Set Carry Flag

Reset Carry Flag

Reset Stack Pointer

Load

Clear

Push/Pop to/from the stack

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Byte Multiplication

Shift and Rotate Operations

Swap Nibbles

11.1.2 Immediate

Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.

Immediate Instruction

LD

CP

Function

Load

Compare

BCP

AND, OR, XOR

Bit Compare

Logical Operations

ADC, ADD, SUB, SBC Arithmetic Operations

11.1.3 Direct

In Direct instructions, the operands are referenced by their memory address.

The direct addressing mode consists of two submodes:

Direct (short)

The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space.

Direct (long)

The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.

11.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three sub-modes:

Indexed (No Offset)

There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.

Indexed (Short)

The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space.

Indexed (long)

The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.

11.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (pointer).

The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes:

Indirect (short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.

Indirect (long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.6 Indirect Indexed (Short, Long)

This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.

The indirect indexed addressing mode consists of two sub-modes:

Indirect Indexed (Short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.

Indirect Indexed (Long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

Table 25. Instructions Supporting Direct,

Indexed, Indirect and Indirect Indexed

Addressing Modes

Long and Short

Instructions

LD

CP

AND, OR, XOR

ADC, ADD, SUB, SBC

BCP

Function

Load

Compare

Logical Operations

Arithmetic Additions/Substractions operations

Bit Compare

11.1.7 Relative mode (Direct, Indirect)

This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.

Available Relative

Direct/Indirect

Instructions

JRxx

CALLR

Function

Conditional Jump

Call Relative

The relative addressing mode consists of two submodes:

Relative (Direct)

The offset is following the opcode.

Relative (Indirect)

The offset is defined in memory, which address follows the opcode.

Short Instructions

Only

CLR

INC, DEC

TNZ

CPL, NEG

BSET, BRES

BTJT, BTJF

SLL, SRL, SRA, RLC,

RRC

SWAP

CALL, JP

Function

Clear

Increment/Decrement

Test Negative or Zero

1 or 2 Complement

Bit Operations

Bit Test and Jump Operations

Shift and Rotate Operations

Swap Nibbles

Call or Jump subroutine

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INSTRUCTION SET OVERVIEW (Cont’d)

11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may

Load and Transfer

Stack operation

Increment/Decrement

Compare and Tests

Logical operations

Bit Operation

Conditional Bit Test and Branch

Arithmetic operations

Shift and Rotates

Unconditional Jump or Call

Conditional Branch

Interruption management

Condition Code Flag modification

LD CLR

PUSH POP

INC DEC

CP

AND

BSET

TNZ

OR

BRES

BTJT

ADC

SLL

JRA

JRxx

TRAP WFI

SIM RIM

BTJF

ADD

SRL

JRT be subdivided into 13 main groups as illustrated in the following table:

RSP

BCP

XOR

SUB

SRA

JRF

CPL

SBC MUL

RLC

JP

RRC SWAP

CALL CALLR

HALT IRET

SCF RCF

NEG

SLA

NOP RET

Using a pre-byte

The instructions are described with one to four opcodes.

In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1

PC

Prebyte opcode

PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address

These prebytes enable instruction in Y as well as indirect addressing modes to be implemented.

They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:

PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one.

PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode.

It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.

PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo

ADC

ADD

AND

BCP

BRES

BSET

BTJF

BTJT

CALL

Description

Add with Carry

Addition

Jump if bit is false (0)

Jump if bit is true (1)

Call subroutine

Function/Example

A = A + M + C

A = A + M

Logical And A = A . M

Bit compare A, Memory tst (A . M)

Bit Reset

Bit Set bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1

CALLR Call subroutine relative

CLR Clear

CP

CPL

DEC

HALT

IRET

INC

JP

JRA

JRT

JRF

JRIH

Arithmetic Compare

One Complement tst(Reg - M)

A = FFH-A dec Y Decrement

Halt

Interrupt routine return

Increment

Absolute Jump

Pop CC, A, X, PC inc X jp [TBL.w]

Jump relative always

Jump relative

Never jump jrf *

Jump if ext. INT pin = 1 (ext. INT pin high)

JRIL

JRH

JRNH

JRM

JRNM

JRMI

JRPL

JREQ

JRNE

Jump if ext. INT pin = 0

Jump if H = 1

Jump if H = 0

Jump if I1:0 = 11

Jump if I1:0 <> 11

Jump if N = 1 (minus)

Jump if N = 0 (plus)

JRC

JRNC

Jump if C = 1

Jump if C = 0

JRULT Jump if C = 1

JRUGE Jump if C = 0

JRUGT Jump if (C + Z = 0)

(ext. INT pin low)

H = 1?

H = 0?

I1:0 = 11?

I1:0 <> 11?

N = 1?

N = 0?

Jump if Z = 1 (equal) Z = 1?

Jump if Z = 0 (not equal) Z = 0?

C = 1?

C = 0?

Unsigned <

Jmp if unsigned >=

Unsigned >

M

M

M

M

A

A

A

A

Dst reg, M reg reg, M reg, M reg, M

M

Src

M

M

M

M

I1 H I0 N Z C

H N Z C

H N Z C

N Z

N Z

0 1

N Z C

N Z 1

N Z

1 0

I1 H I0 N Z C

N Z

C

C

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description

JRULE Jump if (C + Z = 1)

LD Load

MUL

NEG

NOP

OR

Multiply

Negate (2's compl)

No Operation

OR operation

Function/Example

Unsigned <= dst <= src

X,A = X * A neg $10

POP Pop from the Stack

A = A + M pop reg pop CC push Y

C = 0

PUSH

RCF

RET

RIM

RLC

RRC

RSP

SBC

SCF

SIM

Push onto the Stack

Reset carry flag

Subroutine Return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Substract with Carry

Set carry flag

Disable Interrupts

SLA

SLL

SRL

SRA

Shift left Arithmetic

Shift left Logic

Shift right Logic

Shift right Arithmetic

SUB Substraction

SWAP SWAP nibbles

TNZ

TRAP

WFI

XOR

Test for Neg & Zero

S/W trap

Wait for Interrupt

Exclusive OR

I1:0 = 10 (level 0)

C <= A <= C

C => A => C

S = Max allowed

A = A - M - C

C = 1

I1:0 = 11 (level 3)

C <= A <= 0

C <= A <= 0

0 => A => C

A7 => A => C

A = A - M

A7-A4 <=> A3-A0 tnz lbl1

S/W interrupt

A = A XOR M

Dst

M

M

M reg, CC

M

M

M

Src reg, M M, reg

A, X, Y X, Y, A reg, M

A reg

CC

M reg, M reg, M

A reg, M reg, M reg, M reg, M

A reg, M

A

I1 H I0 N Z C

0

N Z

0

N Z C

N Z

I1 H I0 N Z C

1

1

1

1

0

1

1

0

N Z C

N Z C

N Z C

1

N Z C

N Z C

0 Z C

N Z C

N Z C

N Z

N Z

N Z

0

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12 ELECTRICAL CHARACTERISTICS

12.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are referred to V

SS

.

12.1.1 Minimum and Maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T

A and T

A range).

=T

A

=25°C max (given by the selected temperature

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 Σ).

12.1.2 Typical values

Unless otherwise specified, typical data are based on T

A

=25°C, V

DD

=5V. They are given only as design guidelines and are not tested.

12.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

12.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in

Figure 58

.

Figure 58. Pin loading conditions

12.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 59

.

Figure 59. Pin input voltage

V

IN

ST7 PIN

ST7 PIN

C

L

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12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi-

12.2.1 Voltage Characteristics tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol Ratings

V

DD

- V

SS

V

PP

- V

SS

Supply voltage

Programming Voltage

V

IN

1) & 2)

Input Voltage on true open drain pin

V

ESD(MM)

Input voltage on any other pin

|

∆V

DDx

| and |

∆V

SSx

| Variations between different digital power pins

|V

SSA

- V

SSx

| Variations between digital and analog ground pins

V

ESD(HBM)

Electro-static discharge voltage (Human Body Model)

Electro-static discharge voltage (Machine Model)

12.2.2 Current Characteristics

Maximum value

6.5

13

V

SS

-0.3 to 6.5

V

SS

-0.3 to V

DD

+0.3

50

50

Unit

V mV see

Section 12.8.3 on page 132

Symbol Ratings Maximum value Unit

I

I

VDD

VSS

Total current into V

(source)

3)

DD

Total current out of V

(sink)

3)

power lines

SS

ground lines

32-pin devices

44-pin devices

32-pin devices

44-pin devices

Output current sunk by any standard I/O and control pin

75

150

75

150

25 mA mA

I

IO

Output current sunk by any high sink I/O pin

Output current source by any I/Os and control pin

50

- 25

Injected current on V

PP

pin

Injected current on RESET pin

± 5

± 5 mA

I

INJ(PIN)

2) & 4)

Injected current on OSC1 and OSC2 pins ± 5

Injected current on Flash device pin PB0

Injected current on any other pin

5) & 6)

Total injected current (sum of all I/O and control pins)

5)

+5

± 5

ΣI

INJ(PIN)

2)

± 25

Notes:

1. Directly connecting the RESET and I/O pins to V

DD

or V

SS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k

Ω for

RESET, 10k

Ω for I/Os). For the same reason, unused I/O pins must not be directly tied to V

DD

2. I

INJ(PIN)

must never be exceeded. This is implicitly insured if V

IN

or V

SS

.

maximum cannot be respected, the injection current must be limited externally to the I while a negative injection is induced by V

IN

<V

SS

maximum must always be respected

maximum is respected. If V

IN

INJ(PIN)

value. A positive injection is induced by V

IN

>V

DD

. For true open-drain pads, there is no positive injection current, and the corresponding V

IN

3. All power (V

DD

) and ground (V

SS

) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 145 .

For best reliability, it is recommended to avoid negative injection of more than 1.6mA.

5. When several inputs are submitted to a current injection, the maximum

ΣI and negative injected currents (instantaneous values). These results are based on characterisation with

ΣI mum current injection on four I/O port pins of the device.

INJ(PIN)

is the absolute sum of the positive

INJ(PIN)

maxi-

6. True open drain I/O port pins do not accept positive injection.

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12.2.3 Thermal Characteristics

Symbol

T

STG

T

J

Ratings Value

Storage temperature range -65 to +150

Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS )

Unit

°C

12.3 OPERATING CONDITIONS

12.3.1 Operating Conditions

Symbol f

CPU

V

DD

T

A

Parameter

Internal clock frequency

Conditions

Operating voltage (except Flash Write/

Erase)

Operating Voltage for Flash Write/Erase V

PP

= 11.4 to 12.6V

1 Suffix Version

5 Suffix Version

Ambient temperature range 6 Suffix Versions

7 Suffix Versions

3 Suffix Version

Figure 60. f

CPU

Max Versus V

DD

Min

0

3.8

4.5

0

-10

-40

-40

-40

Max

8

5.5

5.5

70

85

85

105

125

Unit

MHz

V

°C f

CPU

[MHz]

8

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

6

4

2

1

0

3.5

3.8

4.0

4.5

SUPPLY VOLTAGE [V]

5.5

FUNCTIONALITY

GUARANTEED

IN THIS AREA

(UNLESS

OTHERWISE

SPECIFIED

IN THE TABLES

OF PARAMETRIC

DATA)

Note: Some temperature ranges are only available with a specific package and memory size. Refer to Ordering Information.

Warning: Do not connect 12V to V

PP

before V

DD

is powered on, as this may damage the device.

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OPERATING CONDITIONS (Cont’d)

12.4 LVD/AVD CHARACTERISTICS

12.4.1 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for T

A

V

Symbol

IT+(LVD)

V

IT-(LVD)

(V

DD

rise)

Parameter

Reset release threshold

Reset generation threshold

(V

DD

fall)

Conditions Min

VD level = High in option byte 4.0

1)

VD level = Med. in option byte

2)

VD level = Low in option byte

2)

3.55

2.95

1)

1)

Typ

4.2

3.75

3.15

4.0

3.55

3.0

Max

4.5

4.0

1)

3.35

1)

4.25

1)

3.75

1)

3.15

1)

Unit

V t

V

Vt hys(LVD)

POR g(VDD)

LVD voltage threshold hysteresis

1)

V

DD

rise time

1)

Filtered glitch delay on V

DD

1)

VD level = High in option byte

VD level = Med. in option byte

2)

VD level = Low in option byte

2)

V

IT+(LVD)

-V

IT-(LVD)

Not detected by the LVD

3.8

3.35

1)

2.8

1)

6

150

µs/V

200 250

100ms/V

40 mV ns

Notes:

1. Data based on characterization results, not tested in production.

2. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.

12.4.2 Auxiliary Voltage Detector (AVD) Thresholds

Subject to general operating conditions for T

A

V

V

V

Symbol

IT+(AVD)

IT-(AVD) hys(AVD)

∆V

IT-

1

(V

DD

0

⇒0 AVDF flag toggle threshold rise)

⇒1 AVDF flag toggle threshold

(V

DD

fall)

Parameter

AVD voltage threshold hysteresis

Voltage drop between AVD flag set and LVD reset activated

Conditions

VD level = High in option byte

VD level = Med. in option byte

VD level = Low in option byte

VD level = High in option byte

VD level = Med. in option byte

VD level = Low in option byte

V

IT+(AVD)

-V

IT-(AVD)

V

IT-(AVD)

-V

IT-(LVD)

1. Data based on characterization results not tested in production.

Min

4.4

1)

3.95

1)

3.4

1)

4.2

3.75

1)

3.2

1)

Typ

4.6

4.15

3.6

4.4

4.0

3.4

200

450

Max

4.9

4.4

1)

3.8

1)

4.65

1)

4.2

1)

3.6

1)

Unit

V mV mV

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12.5 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode for which the clock is stopped).

12.5.1 CURRENT CONSUMPTION

Flash Devices

Symbol Parameter Conditions Unit

I

I

DD

DD

Supply current in RUN mode

2)

Supply current in SLOW mode

Supply current in WAIT mode

Supply current in SLOW WAIT mode

Supply current in HALT mode

2)

2)

3)

2)

Supply current in ACTIVE-HALT mode

4) f

OSC f

OSC

=2MHz, f

CPU

=4MHz, f

CPU f

OSC

=8MHz, f

CPU

=1MHz

=2MHz

=4MHz f

OSC

=16MHz, f

CPU

=8MHz f

OSC f

OSC

=2MHz, f

CPU

=4MHz, f

CPU f

OSC

=8MHz, f

CPU

=62.5kHz

=125kHz

=250kHz f

OSC

=16MHz, f

CPU

=500kHz f

OSC f

OSC

=2MHz, f

CPU

=4MHz, f

CPU f

OSC

=8MHz, f

CPU

=1MHz

=2MHz

=4MHz f

OSC

=16MHz, f

CPU

=8MHz f

OSC f

OSC

=2MHz, f

CPU

=4MHz, f

CPU f

OSC

=8MHz, f

CPU

=62.5kHz

=125kHz

=250kHz f

OSC

=16MHz, f

CPU

=500kHz

-40°C

≤T

A

≤+85°C

-40°C

≤T

A

≤+125°C f f

OSC

OSC

=2MHz

=4MHz f

OSC

=8MHz f

OSC

=16MHz

1.3

2.0

3.6

7.1

600

700

800

1100

1.0

1.5

2.5

4.5

580

650

770

1050

<1

<1

80

160

325

650

3.0

5.0

8.0

15.0

2700

3000

3600

4000

3.0

4.0

5.0

7.0

1200

1300

1800

2000

10

50

No max. guaranteed mA

µA mA

µA

µA

Notes:

1. Data based on characterization results, tested in production at V

DD

max. and f

CPU

max.

2. Measurements are done in the following conditions:

- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash is 50%.

- All I/O pins in input mode with a static value at V

DD

or V

SS

(no load)

- All peripherals in reset state.

- LVD disabled.

- Clock input (OSC1) driven by external square wave.

- In SLOW and SLOW WAIT mode, f

CPU

is based on f

OSC

divided by 32.

To obtain the total current consumption of the device, add the clock source (

Section 12.6.3

) and the peripheral power

consumption ( Section 12.5.3

).

3. All I/O pins in push-pull 0 mode (when applicable) with a static value at V

DD on characterization results, tested in production at V

DD

max. and f

CPU

or V

max.

SS

(no load), LVD disabled. Data based

4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with a static value at V

DD

or V

SS

(no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain

the total current consumption of the device, add the clock source consumption ( Section 12.6.3

).

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.5.1.1 Power Consumption vs f

CPU

: Flash Devices

Figure 61. Typical I

DD

in RUN mode Figure 63. Typical I

DD

in WAIT mode

7

6

5

4

9

8

3

2

1

0

8MHz

4MHz

2MHz

1MHz

2

1

0

6

5

4

3

8MHz

4MHz

2MHz

1MHz

4 4.4

4.8

Vdd (V)

5.2

5.5

4 4.4

4.8

Vdd (V)

5.2

Figure 62. Typical I

DD

in SLOW mode

1.20

1.00

500kHz

250kHz

125kHz

62.5kHz

0.80

0.60

0.40

0.20

0.00

4 4.4

4.8

Vdd (V)

5.2

5.5

5.5

Figure 64. Typ. I

DD

in SLOW-WAIT mode

1.20

1.00

500kHz

250kHz

125kHz

62.5kHz

0.80

0.60

0.40

0.20

0.00

4 4.4

4.8

Vdd (V)

5.2

5.5

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.5.2 Supply and Clock Managers

The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).

Symbol

I

DD(RCINT)

I

DD(RES)

Parameter

Supply current of internal RC oscillator

Supply current of resonator oscillator

1) & 2)

Conditions Typ Max

625

see Section

12.6.3 on page

125

Unit

µA

µA

I

DD(PLL)

PLL supply current V

DD

= 5V 360

I

DD(LVD)

LVD supply current V

DD

= 5V 150 300

Notes:

1. Data based on characterization results done with the external components specified in

Section 12.6.3

, not tested in production.

2. As the oscillator is based on a current source, the consumption does not depend on the voltage.

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.5.3 On-Chip Peripherals

T

A

= 25°C f

CPU

=4MHz.

Symbol

I

DD(TIM)

I

DD(SPI)

I

DD(SCI)

I

DD(ADC)

Parameter

16-bit Timer supply current

1)

SPI supply current

2)

SCI supply current

3)

ADC supply current when converting

4)

Conditions

V

DD

=5.0V

V

DD

=5.0V

V

DD

=5.0V

V

DD

=5.0V

Typ

50

400

400

400

Unit

µA

Notes:

1. Data based on a differential I

DD

measurement between reset configuration (timer counter running at f

CPU

/4) and timer counter stopped (only TIMD bit set). Data valid for one timer.

2. Data based on a differential I

DD

measurement between reset configuration (SPI disabled) and a permanent SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the pad toggling consumption.

3. Data based on a differential I

DD mit sequence.

measurement between SCI low power state (SCID=1) and a permanent SCI data trans-

4. Data based on a differential I

DD

measurement between reset configuration and continuous A/D conversions.

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12.6 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for V

DD

, f

CPU

, and T

A

.

12.6.1 General Timings

Symbol Parameter Conditions t c(INST)

Instruction cycle time f

CPU

=8MHz t v(IT)

Interrupt reaction time

2) t v(IT)

=

∆t c(INST)

+ 10 f

CPU

=8MHz

12.6.2 External Clock Source

Symbol

V

OSC1H

V

OSC1L t w(OSC1H) t w(OSC1L) t r(OSC1) t f(OSC1)

I

L

Parameter

OSC1 input pin high level voltage

OSC1 input pin low level voltage

OSC1 high or low time

3)

OSC1 rise or fall time

3)

OSC1 Input leakage current

Conditions

see Figure 65

V

SS

≤V

IN

≤V

DD

Figure 65. Typical Application with an External Clock Source

V

OSC1H

90%

10%

V

OSC1L t r(OSC1) t f(OSC1) t w(OSC1H)

Min

2

250

10

1.25

Typ

1)

3

375

Max

12

1500

22

2.75

Min

V

DD

-1

V

SS

5

Typ t w(OSC1L)

Max

V

DD

V

SS

+1

Unit

V

15

±1 ns

µA

Unit t

CPU ns t

CPU

µs

EXTERNAL

CLOCK SOURCE

OSC2

OSC1

Not connected internally f

OSC

I

L

ST72XXX

Notes:

1. Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch.

∆t c(INST) the current instruction execution.

is the number of t

CPU

cycles needed to finish

3. Data based on design simulation and/or technology characteristics, not tested in production.

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

12.6.3 Crystal and Ceramic Resonator Oscillators

The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).

Symbol f

OSC

R

F

C

L1

C

L2

Parameter

Oscillator Frequency

1)

Conditions

LP: Low power oscillator

MP: Medium power oscillator

MS: Medium speed oscillator

HS: High speed oscillator

Feedback resistor

2)

Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (R

S

)

R

S

R

S

=200

Ω

=200

Ω

R

R

S

S

=200

Ω

=100

Ω

LP oscillator

MP oscillator

MS oscillator

HS oscillator

Min

20

22

22

18

15

1

>2

>4

>8

Max

40

56

46

33

33

2

4

8

16

Unit

MHz k

Ω pF

Unit i

2

Symbol Parameter

OSC2 driving current

V

IN

=V

SS

Conditions

LP oscillator

MP oscillator

MS oscillator

HS oscillator

Figure 66. Typical Application with a Crystal or Ceramic Resonator

WHEN RESONATOR WITH

INTEGRATED CAPACITORS i

2

Typ

80

160

310

610 f

OSC

C

L1 OSC1

Max

150

250

460

910

µA

RESONATOR R

F

C

L2

OSC2

ST72XXX

Notes:

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

S

Refer to crystal/ceramic resonator manufacturer for more details.

value.

2. Data based on characterisation results, not tested in production.

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

Oscil.

LP

MP

MS

HS

Typical Ceramic Resonators (information for guidance only)

Reference

CSA2.00MG

CSA4.00MG

CSA8.00MTZ

3)

CSA16.00MXZ040

4)

Freq.

Characteristic

1)

C

L1

[pF]

C

L2

[pF] t

SU(osc)

[ms]

2MHz ∆f

OSC

=[±0.5% tolerance

,±0.3% ∆Ta

,±0.3% aging

,±x.x%

4MHz ∆f

OSC

=[±0.5% tolerance

,±0.3%

∆Ta

,±0.3% aging

,±x.x%

8MHz ∆f

OSC

=[±0.5% tolerance

,±0.5%

∆Ta

,±0.3% aging

,±x.x%

16MHz ∆f

OSC

=[±0.5% tolerance

,±0.3% ∆Ta

,±0.3% aging

,±x.x% correl

] 22 22 correl

] 22 22 correl

] 33 33

4

2

1 correl

] 33 33 0.7

2)

Notes:

1. Resonator characteristics given by the ceramic resonator manufacturer.

2. t

SU(OSC) quick V

DD

is the typical oscillator start-up time measured between V

ramp-up from 0 to 5V (<50

µs).

DD

=2.8V and the fetch of the first instruction (with a

3. Resonators all have different characteristics. Contact the manufacturer to obtain the appropriate values of external components and to verify oscillator performance.

4. 3rd overtone resonators require specific validation by the resonator manufacturer.

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CLOCK CHARACTERISTICS (Cont’d)

12.6.4 RC Oscillators

Symbol f

OSC (RCINT)

Parameter

Internal RC oscillator frequency

See Figure 67

Figure 67. Typical f

OSC(RCINT)

vs T

A

Conditions

T

A

=25°C, V

DD

=5V

Min

2

Typ

3.5

Max

5.6

Unit

MHz

Note: To reduce disturbance to the RC oscillator, it is recommended to place decoupling capacitors between V

DD

and V

SS

as shown in

Figure 86

4

3.8

3.6

3.4

3.2

3

-45 0 25

T

A

(°C)

Vdd = 5V

Vdd = 5.5V

70 130

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CLOCK CHARACTERISTICS (Cont’d)

12.6.5 PLL Characteristics

Symbol f

OSC

Parameter

PLL input frequency range

∆ f

CPU

/

f

CPU

Instantaneous PLL jitter

1)

Conditions

Flash ST72F324, f

OSC

= 4 MHz.

Flash ST72F324, f

OSC

= 2 MHz.

Min

2

Typ

1.0

2.5

Max

4

2.5

4.0

Unit

MHz

%

Note:

1. Data characterized but not tested.

The user must take the PLL jitter into account in the application (for example in serial communication or sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several

CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the

PLL jitter.

Figure 68 shows the PLL jitter integrated on application signals in the range 125kHz to 2MHz. At frequen-

cies of less than 125KHz, the jitter is negligible.

Figure 68. Integrated PLL Jitter vs signal frequency

1

+/-Jitter (%)

1.2

1

0.8

0.6

0.4

0.2

0

FLASH typ

ROM max

ROM typ

4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz

Application Frequency

Note 1: Measurement conditions: f

CPU

= 8MHz.

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12.7 MEMORY CHARACTERISTICS

12.7.1 RAM and Hardware Registers

Symbol

V

RM

Parameter

Data retention mode

1)

Conditions

HALT mode (or RESET)

Min

1.6

Typ Max Unit

V

12.7.2 FLASH Memory

DUAL VOLTAGE HDFLASH MEMORY

Symbol f

CPU

Parameter

Operating frequency

Conditions

Read mode

Write / Erase mode

4.5V

≤

V

DD

≤

5.5V

Write / Erase

Min

2)

0

1

11.4

Typ Max

2)

8

8

12.6

Unit

MHz

V

I

I

PP

DD

PP

Programming voltage

Supply current

V

PP

current

4)

4)

3)

Read (V

PP

=12V)

Write / Erase

0

200

30

V mA

µA mA t

VPP t

RET

N

RW

T

PROG

T

ERASE

Data retention

Write erase cycles

Programming or erasing temperature range

T

T

A

A

=55°C

=25°C

20

100

-40

10

25 85

µs years cycles

°C

Notes:

1. Minimum V

DD

supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Not tested in production.

2. Data based on characterization results, not tested in production.

3. V

PP

must be applied only during the programming or erasing operation and not permanently for reliability reasons.

4. Data based on simulation results, not tested in production.

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12.8 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample basis during product characterization.

12.8.1 Functional EMS (Electro Magnetic

Susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).

■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.

■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

DD

and V

SS

through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-

4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

12.8.1.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It

.

should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies

EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations:

The software flowchart must include the management of runaway conditions such as:

– Corrupted program counter

– Unexpected reset

– Critical Data corruption (control registers...)

Prequalification trials:

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RE-

SET pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015)

Symbol

V

V

FESD

FFTB

Parameter Conditions

Voltage limits to be applied on any I/O pin to induce a functional disturbance

8 or 16K Flash device, V

DD

T

A

=+25°C, f

OSC

=5V,

=8MHz conforms to IEC

1000-4-2

Fast transient voltage burst limits to be applied through 100pF on V

DD

and V

DD pins to induce a functional disturbance

V

DD

=5V, T

A

=+25°C, f

OSC

=8MHz conforms to IEC 1000-4-4

Level/

Class

4B

4A

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EMC CHARACTERISTICS (Cont’d)

12.8.2 Electro Magnetic Interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/

3 which specifies the board and the loading of each pin.

Symbol

S

EMI

Parameter

Peak level

V

T

Conditions

DD

A

=5V,

=+25°C conforming to

SAE J 1752/3

Device/ Package

8/16K Flash/

TQFP44

32K Flash/TQFP44

Flash/TQFP32

Monitored

Frequency Band

0.1MHz to 30MHz

30MHz to 130MHz

130MHz to 1GHz

SAE EMI Level

0.1MHz to 30MHz

30MHz to 130MHz

130MHz to 1GHz

SAE EMI Level

0.1MHz to 30MHz

30MHz to 130MHz

130MHz to 1GHz

SAE EMI Level

Notes:

1. Data based on characterization results, not tested in production.

2. Refer to Application Note AN1709 for data on other package types.

Max vs. [f

OSC

/f

CPU

]

8/4MHz 16/8MHz

12

19

18

25

15

3

20

26

22

3.5

25

30

18

3.0

22

3.5

21

31

28

4.0

27

36

23

3.5

Unit dB

µV

-

-

dB

µV dB

µV

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EMC CHARACTERISTICS (Cont’d)

12.8.3 Absolute Maximum Ratings (Electrical

Sensitivity)

Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

12.8.3.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human

Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard.

Absolute Maximum Ratings

Symbol

V

ESD(HBM)

V

ESD(MM)

V

ESD(CD)

Ratings

Electro-static discharge voltage

(Human Body Model)

Electro-static discharge voltage

(Machine Model)

Electro-static discharge voltage

(Charged Device Model)

T

A

=+25°C

T

A

=+25°C

T

A

=+25°C

Conditions Maximum value

1)

Unit

2000

200

250

V

Notes:

1. Data based on characterization results, not tested in production.

12.8.3.2 Static and Dynamic Latch-Up

■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note

AN1181.

■ DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.

Electrical Sensitivities

Symbol

LU

DLU

Parameter

Static latch-up class

Dynamic latch-up class

Conditions

T

A

T

A

T

A

=+25°C

=+85°C

=+125°C

V

DD

=5.5V, f

OSC

=4MHz, T

A

=+25°C

Class

1)

A

A

A

A

Notes:

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the

JEDEC criteria (international standard).

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12.9 I/O PORT PIN CHARACTERISTICS

12.9.1 General Characteristics

Subject to general operating conditions for V

DD

, f

OSC

, and T

A

unless otherwise specified.

Symbol Parameter Conditions Min Typ Max

I

V

V

V

IL

IH hys

INJ(PIN)

3)

Input low level voltage (standard voltage devices)

1)

Input high level voltage

1)

Schmitt trigger voltage hysteresis

2)

Injected Current on Flash device pin PB0

Injected Current on other I/O pins

ΣI

INJ(PIN)

3)

I lkg

Total injected current (sum of all I/O and control pins)

Input leakage current t

R

C

I

S

PU

IO f(IO)out

Static current consumption induced by each floating input pin

Weak pull-up equivalent resistor

5)

I/O pin capacitance

Output high to low level fall time

1) t r(IO)out

Output low to high level rise time

1) t w(IT)in

External interrupt pulse time

6)

V

DD

=5V

V

SS

V

IN

≤

V

IN

=

V

SS

≤

V

DD

Floating input mode

4)

V

DD

=5V

C

L

=50pF

Between 10% and

90%

0.7xV

DD

0

50

1

0.7

200

120

5

25

25

0.3xV

DD

+4

±4

±25

±1

250

Unit

V

V mA

µA k

Ω pF ns t

CPU

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the V tion. A positive injection is induced by V

IN

on page 117 for more details.

>V

DD

IN

maximum must be respected, otherwise refer to I

INJ(PIN)

while a negative injection is induced by V

IN

<V

SS

specifica-

. Refer to Section 12.2.2

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see

Figure 69 ). Data

based on design simulation and/or technology characteristics, not tested in production.

5. The R

PU

pull-up equivalent resistor is based on a resistive transistor (corresponding I

scribed in Figure 70 ).

PU current characteristics de-

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.

Figure 69. Unused I/O Pins configured as input

V

DD ST7XXX

10k Ω

10k Ω

UNUSED I/O PORT

UNUSED I/O PORT

ST7XXX

Figure 70. Typical I

PU

vs. V

DD

with V

IN

=V

SS

9 0

8 0

7 0

6 0

T a = 1 4 0 ° C

T a = 9 5 ° C

T a = 2 5 ° C

T a = -4 5 ° C

5 0

4 0

3 0

2 0

1 0

0

2 2 .5

3 3 .5

4

V d d (V )

4 .5

5 5 .5

6

Note: I/O can be left unconnected if it is configured as output

(0 or 1) by the software. This has the advantage of

greater EMC robustness and lower cost.

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I/O PORT PIN CHARACTERISTICS (Cont’d)

12.9.2 Output Driving Current

Subject to general operating conditions for V

DD

, f

CPU

, and T

A

unless otherwise specified.

Symbol Min

V

OL

1)

V

OH

2)

Parameter

Output low level voltage for a standard I/O pin when 8 pins are sunk at same time

(see

Figure 71 )

Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time

(see

Figure 72 and

Figure 74

)

Output high level voltage for an I/O pin when 4 pins are sourced at same time

(see

Figure 73 and

Figure 76

)

Conditions

I

IO

=+5mA

I

IO

=+2mA

I

IO

=+20mA, T

A

T

A

≤85°C

>85°C

I

IO

=+8mA

I

IO

=-5mA, T

A

T

A

≤85°C

>85°C

I

IO

=-2mA

V

DD

V

DD

-1.4

-1.6

V

DD

-0.7

Max

1.2

0.5

1.3

1.5

0.6

Unit

V

Figure 71. Typical V

OL

at V

DD

=5V (std. ports) Figure 73. Typical V

OH

at V

DD

5 .5

=5V

1 .2

5

1

4 .5

0 .8

4

0 .6

3 .5

0 .4

0 .2

Ta = 1 4 0 ° C "

Ta = 9 5 ° C

Ta = 2 5 ° C

Ta = -4 5 °C

3

2 .5

V d d = 5 V 1 4 0 ° C m in

V d d = 5 v 9 5 ° C m in

V d d = 5 v 2 5 ° C m in

V d d = 5 v -4 5 ° C m i n

0

0

I

IO

2

-10 -8 -6 -4 -2

-0 .0 1 -0 .0 0 8 -0 .0 0 6 -0 .0 0 4 -0 .0 0 2

I

IO

(mA)

Ii o (A )

0

0

Figure 72. Typ. V

OL

at V

DD

=5V (high-sink ports)

1

0 .9

0 .8

0 .7

0 .6

0 .5

0 .4

0 .3

0 .2

0 .1

Ta = 1 4 0 °C

Ta = 9 5 °C

Ta = 2 5 °C

Ta = -4 5 ° C

0

0

10

0.01

20

0.0 2

I

IO

(mA)

Iio (A )

30

0 .0 3

Notes:

1. The I

IO

current sunk must always respect the absolute maximum rating specified in Section 12.2.2

and the sum of I

IO

(I/O ports and control pins) must not exceed I

VSS

.

2. The I

IO

current sourced must always respect the absolute maximum rating specified in

Section 12.2.2

and the sum of

I

IO

(I/O ports and control pins) must not exceed I

VDD

. True open drain I/O pins do not have V

OH

.

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 74. Typical V

OL

vs. V

DD

1

(std. ports)

Ta=-45°C

0.9

Ta=25°C

0.8

Ta=95°C

Ta=140°C

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

2 2.5

3 3.5

4 4.5

5 5.5

6

Vdd(V)

Figure 75. Typical V

OL

vs. V

DD

(high-sink ports)

0.6

0.5

0.4

0.3

0.2

0.1

Ta= 140°C

Ta=95°C

Ta=25°C

Ta=-45°C

0

2 2.5

3 3.5

4

Vdd(V)

4.5

Figure 76. Typical V

OH

vs. V

DD

5.5

5 5.5

6

5

4.5

4

3.5

3

2.5

Ta=-45°C

Ta=25°C

Ta=95°C

Ta=140°C

2

2 2.5

3 3.5

4

Vdd(V)

4.5

5 5.5

6

0.45

0.4

0.35

Ta=-45°C

Ta=25°C

Ta=95°C

Ta=140°C

0.3

0.25

0.2

0.15

0.1

0.05

0

2 2.5

3 3.5

4 4.5

5 5.5

6

Vdd(V)

1.6

1.4

1.2

1

Ta= 140°C

Ta=95°C

Ta=25°C

Ta=-45°C

0.8

0.6

0.4

0.2

0

2 2.5

3 3.5

4

Vdd(V)

4.5

5 5.5

6

4

3

2

6

5

Ta=-45°C

Ta=25°C

Ta=95°C

Ta=140°C

1

0

2 2.5

3 3.5

4 4.5

5 5.5

6

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ST72324Jx ST72324Kx

12.10 CONTROL PIN CHARACTERISTICS

12.10.1 Asynchronous RESET Pin

Subject to general operating conditions for V

DD

, f

CPU

, and T

A

unless otherwise specified.

Symbol

V hys

V

IL

V

IH

V

OL

I

IO

R

ON t w(RSTL)out t h(RSTL)in t g(RSTL)in

Parameter

Schmitt trigger voltage hysteresis

2)

Input low level voltage

1)

Input high level voltage

1)

Output low level voltage

3)

Driving current on RESET pin

Weak pull-up equivalent resistor

Generated reset pulse duration

External reset pulse hold time

4)

Filtered glitch duration

5)

Conditions

V

DD

=5V I

IO

=+2mA

V

DD

=5V

Internal reset sources

Min

0.85xV

DD

20

20

2.5

Typ

2.5

0.2

2

30

30

200

Max

0.16xV

DD

0.5

120

42

6)

Unit

V

V

V mA k

Ω

µs

µs ns

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The I

IO

current sunk must always respect the absolute maximum rating specified in Section 12.2.2

and the sum of I

IO

(I/O ports and control pins) must not exceed I

VSS

.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the RESET pin with a duration below t h(RSTL)in

can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments.

6. Data guaranteed by design, not tested in production.

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CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 77. RESET pin protection when LVD is enabled.

1)2)3)4)5)6)7)

V

DD

ST72XXX

EXTERNAL

RESET

Recommended Optional

(note 6)

0.01

µF

1M Ω

R

ON

Filter

INTERNAL

RESET

PULSE

GENERATOR

WATCHDOG

LVD RESET

Figure 78. RESET pin protection when LVD is disabled.

1)2)3)4)

Recommended

V

DD

V

DD ST72XXX

V

DD

USER

EXTERNAL

RESET

CIRCUIT

0.01

µF

4.7k

Ω

R

ON

Filter

INTERNAL

RESET

0.01

µF

PULSE

GENERATOR

WATCHDOG

Required

1. The reset network protects the device against parasitic resets.

2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the V

IL

max. level specified in

Section 12.10.1

. Otherwise the reset will not be taken into account internally.

4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for I

INJ(RESET)

in

Section 12.2.2 on page 117

.

5. When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-down capacitor is recommended to filter noise on the reset line.

6. In case a capacitive power supply is used, it is recommended to connect a1M

Ω pull-down resistor to the RESET pin to discharge any residual voltage induced by this capacitive power supply (this will add 5µA to the power consumption of the MCU).

7. Tips when using the LVD:

– 1. Check that all recommendations related to ICCCLK and reset circuit have been applied (see notes above)

– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709. If this cannot be done, it is recommended to put a 100nF + 1M

Ω pull-down on the RESET pin.

– 3. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.”

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ST72324Jx ST72324Kx

CONTROL PIN CHARACTERISTICS (Cont’d)

12.10.2 ICCSEL/V

PP

Pin

Subject to general operating conditions for V

DD

, f

CPU

, and T

A

unless otherwise specified.

Symbol

V

IL

V

IH

I

L

Parameter

Input low level voltage

1)

Input high level voltage

1)

Input leakage current

Conditions

V

IN

=V

SS

Figure 79. Two typical Applications with ICCSEL/V

PP

Pin

2)

Min Max

V

SS

0.2

V

DD

-0.1

12.6

±1

Unit

V

µA

V

PP

ICCSEL/V

PP

ST72XXX

PROGRAMMING

TOOL

10k Ω

ST72XXX

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

2. When ICC mode is not required by the application ICCSEL/V

PP

pin must be tied to V

SS

.

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12.11 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for V

DD

, f

OSC

, and T

A

unless otherwise specified.

Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).

Data based on design simulation and/or characterisation results, not tested in production.

12.11.1 16-Bit Timer

Symbol t w(ICAP)in

Parameter

Input capture pulse time t res(PWM)

PWM resolution time f

EXT f

PWM

Res

PWM

Timer external clock frequency

PWM repetition rate

PWM resolution

Conditions f

CPU

=8MHz

Min

1

2

250

0

0

Typ Max f

CPU

/4 f

CPU

/4

16

Unit t

CPU t

CPU ns

MHz

MHz bit

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ST72324Jx ST72324Kx t r(SCK) t f(SCK) t su(SS) t h(SS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO) t v(SO) t h(SO) t v(MO) t h(MO)

12.12 COMMUNICATION INTERFACE CHARACTERISTICS

12.12.1 SPI - Serial Peripheral Interface

Subject to general operating conditions for V

DD

, f

CPU

, and T

A

unless otherwise specified. Data based on design simulation and/or characterisation results, not tested in production.

When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO).

Symbol Parameter f

SCK

1/t c(SCK)

SPI clock frequency

SPI clock rise and fall time

Master

Slave

Conditions f

CPU

=8MHz f

CPU

=8MHz

Min f

CPU

/128

0.0625

0

Max f

CPU

/4

2 f

CPU

/2

4

Unit

MHz see I/O port pin description

SS setup time

SS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output disable time

Data output valid time

Data output hold time

Data output valid time

Data output hold time

Slave

Slave

Master

Slave

Master

Slave

Master

Slave

Slave

Slave

Slave (after enable edge)

Master (before capture edge)

120

120

100

90

100

100

100

100

0

0

0.25

0.25

120

240

90 ns t

CPU

Figure 80. SPI Slave Timing Diagram with CPHA=0 1)

SS

INPUT t su(SS) t c(SCK) t h(SS)

CPHA=0

CPOL=0

CPHA=0

CPOL=1 t a(SO) t w(SCKH) t w(SCKL) t v(SO) t h(SO) t r(SCK) t f(SCK) t dis(SO)

MISO

OUTPUT see note 2 t su(SI)

MSB OUT t h(SI)

BIT6 OUT LSB OUT see note 2

MOSI

INPUT

MSB IN BIT1 IN LSB IN

Notes:

1. Measurement points are done at CMOS levels: 0.3xV

DD

and 0.7xV

DD

.

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 81. SPI Slave Timing Diagram with CPHA=1 1)

SS

INPUT t su(SS) t c(SCK)

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t a(SO) t w(SCKH) t w(SCKL) t v(SO)

MISO

OUTPUT see note 2

HZ t su(SI)

MSB OUT t h(SI)

BIT6 OUT

MOSI

INPUT

MSB IN BIT1 IN t h(SS) t h(SO) t t r(SCK) f(SCK)

LSB OUT

LSB IN

Figure 82. SPI Master Timing Diagram 1)

SS

INPUT t c(SCK)

CPHA=0

CPOL=0

CPHA=0

CPOL=1

CPHA=1

CPOL=0

CPHA=1

CPOL=1 t w(SCKH) t w(SCKL) t su(MI) t h(MI)

MISO

INPUT t v(MO)

MSB IN t h(MO)

BIT6 IN

MOSI

OUTPUT see note 2 MSB OUT BIT6 OUT t r(SCK) t f(SCK)

LSB IN

LSB OUT t dis(SO) see note 2 see note 2

Notes:

1. Measurement points are done at CMOS levels: 0.3xV

DD

and 0.7xV

DD

.

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.

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ST72324Jx ST72324Kx

12.13 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for V

DD

, f

CPU

, and T

A

unless otherwise specified.

Symbol f

ADC

V

AREF

V

AIN

I lkg

R

AIN

C

AIN f

AIN

C

ADC t

ADC t

ADC

Parameter

Internal sample and hold capacitor

Conversion time (Sample+Hold) f

CPU

=8MHz, SPEED=0 f

ADC

=2MHz

- No of sample capacitor loading cycles

- No. of Hold conversion cycles

Conditions Min Typ

7.5

4

11

Max

ADC clock frequency

Analog reference voltage

Conversion voltage range

Positive input leakage current for analog input

2)

External input impedance

1)

External capacitor on analog input

Variation freq. of analog input signal

0.4

2

0.7*V

DD

≤V

AREF

≤V

DD

3.8

V

DD

V

SSA

V

AREF

-40°C

≤T

A

≤+85°C ±250

+85°C

≤T

A

≤+125°C ±1 see

Figure 83

and

Figure

84

2)3)4)

12

Unit

MHz

V nA

µA k

Ω pF

Hz pF

µs

1/f

ADC

Notes:

1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω). Data based on characterization results, not tested in production.

2.For Flash devices: injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. Analog pins of ST72F324 devices can be protected against negative injection by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for I

INJ(PIN)

and

ΣI

INJ(PIN)

in

Section 12.9

does not affect the ADC accuracy.

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ADC CHARACTERISTICS (Cont’d)

Figure 83. R

AIN

max. vs f

ADC

with C

AIN

=0pF

1)

45

40

35

2 MHz

30

25

20

1 MHz

15

10

5

0

0 10 30 70

C

PARASITIC

(pF)

Figure 85. Typical A/D Converter Application

Figure 84. Recommended C

AIN

& R

AIN values.

2)

1000

100

Cain 10 nF

Cain 22 nF

Cain 47 nF

10

1

0.1

0.01

0.1

f

AIN

(KHz)

1 10

V

DD

V

T

0.6V

ST72XXX

V

AIN

R

AIN

C

AIN

AINx

V

T

0.6V

2k

Ω(max)

10-Bit A/D

Conversion

I

L

±1

µA

C

ADC

12pF

Notes:

1. C

PARASITIC

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF). A high C

PARASITIC

value will downgrade conversion accuracy. To remedy this, f

ADC

should be reduced.

2. This graph shows that depending on the input signal variation (f

AIN decreased to allow the use of a larger serial resistor (R

AIN)

.

), C

AIN

can be increased for stabilization time and

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ST72324Jx ST72324Kx

ADC CHARACTERISTICS (Cont’d)

12.13.1 Analog Power Supply and Reference

Pins

Depending on the MCU pin count, the package may feature separate V

AREF

and V

SSA analog power supply pins. These pins supply power to the

A/D converter cell and function as the high and low reference voltages for the conversion. In some packages, V

AREF

and V

SSA

pins are not available

(refer to

Section 2 on page 8

). In this case the analog supply and reference pads are internally bonded to the V

DD

and V

SS pins.

Separation of the digital and analog power pins allow board designers to improve A/D performance.

Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see

Section

12.13.2 General PCB Design Guidelines

).

12.13.2 General PCB Design Guidelines

To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating

CMOS logic signals.

– Use separate digital and analog planes. The analog ground plane should be connected to the

Figure 86. Power Supply Filtering

1 to 10 µF

ST7

DIGITAL NOISE

FILTERING

V

DD

0.1

µF V

SS

V

DD digital ground plane via a single point on the

PCB.

– Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1µF and optionally, if needed 10pF capacitors as close as possible to the ST7 power supply pins and a 1 to 10µF capacitor close to the power source (see

Figure

86 ).

– The analog and digital power supplies should be connected in a star network. Do not use a resistor, as V

AREF is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy.

– Properly place components and route the signal traces on the PCB to shield the analog inputs.

Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs on the same I/O port as the A/D input being converted.

ST72XXX

POWER

SUPPLY

SOURCE

0.1

µF

V

AREF

EXTERNAL

NOISE

FILTERING

V

SSA

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10-BIT ADC CHARACTERISTICS (Cont’d)

12.13.3 ADC Accuracy

Conditions: V

DD

=5V 1)

Symbol Parameter Conditions

|E

T

| Total unadjusted error

1)

|E

O

| Offset error

1)

|E

G

| Gain Error

1)

|E

D

|

Differential linearity error

1)

|E

L

| Integral linearity error

1)

CPU in run mode @ f

ADC

2 MHz.

CPU in run mode @ f

ADC

2 MHz.

Flash Devices

Typ Max

2)

4 6

3

0.5

5

4.5

1.5

1.5

4.5

4.5

Unit

LSB

Notes:

1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion being performed on another analog input.

Any positive injection current within the limits specified for I

INJ(PIN) accuracy.

and

ΣI

INJ(PIN)

in Section 12.9

does not affect the ADC

2. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C to 125°C (± 3

σ distribution limits).

Figure 87. ADC Accuracy Characteristics

Digital Result ADCDR

1023

1022

1021

1LSB

IDEAL

=

V – V

SSA

1024

E

T

3

2

5

4

1

7

6

0

V

SSA

1

E

O

2 3 4

1 LSB

E

L

IDEAL

5 6 7

(2)

E

D

(3)

(1)

E

G

1021 1022 1023 1024

V

AREF

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

E

T

=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

E

O

=Offset Error: deviation between the first actual transition and the first ideal one.

E

G

=Gain Error: deviation between the last ideal transition and the last actual one.

E

D

=Differential Linearity Error: maximum deviation between actual steps and the ideal one.

E

L

=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

V in

(LSB

IDEAL

)

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13 PACKAGE CHARACTERISTICS

13.1 PACKAGE MECHANICAL DATA

Figure 88. 44-Pin Thin Quad Flat Package

D

D1

E1 E

L1

L

A1 b e

A

A2 h c

Dim.

mm inches

Min Typ Max Min Typ Max

A

A1 0.05

1.60

0.15 0.002

0.063

0.006

A2 1.35

1.40

1.45 0.053 0.055 0.057

b 0.30

0.37

0.45 0.012 0.015 0.018

C 0.09

D

0.20 0.004 0.000 0.008

12.00

0.472

D1

E

10.00

12.00

0.394

0.472

E1

L1

10.00

e

θ

0°

0.80

3.5° 7° 0°

0.031

3.5° 7°

L 0.45

0.60

0.75 0.018 0.024 0.030

1.00

0.394

0.039

Number of Pins

N 44

Figure 89. 32-Pin Thin Quad Flat Package

D

D1

E1 E e b

A1

L1

L

A

A2 c h

Dim.

mm inches

Min Typ Max Min Typ Max

A

A1 0.05

1.60

0.15 0.002

0.063

0.006

A2 1.35

1.40

1.45 0.053 0.055 0.057

b 0.30

0.37

0.45 0.012 0.015 0.018

C 0.09

D

0.20 0.004

9.00

0.354

0.008

D1

E

7.00

9.00

0.276

0.354

E1

L1

7.00

e

θ

0°

0.80

3.5° 7° 0°

0.031

3.5° 7°

L 0.45

0.60

0.75 0.018 0.024 0.030

1.00

0.276

0.039

Number of Pins

N 32

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PACKAGE MECHANICAL DATA (Cont’d) b2

D

A2 A b e

A1 L c

E

E1 eA eB

E eB eC

0.015

GAGE PLANE

Dim.

mm inches

Min Typ Max Min Typ Max

A

A1 0.51

5.08

0.020

0.200

A2 3.05

3.81

4.57 0.120 0.150 0.180

b 0.38

0.46

0.56 0.015 0.018 0.022

b2 0.89

1.02

1.14 0.035 0.040 0.045

c 0.23

0.25

0.38 0.009 0.010 0.015

D 36.58 36.83 37.08 1.440 1.450 1.460

E 15.24

16.00 0.600

0.630

E1 12.70 13.72 14.48 0.500 0.540 0.570

e eA

1.78

15.24

0.070

0.600

eB 18.54

0.730

eC 1.52 0.000

0.060

L 2.54

3.30

3.56 0.100 0.130 0.140

N

Number of Pins

42

Figure 91. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width b2

D b e

A2 A

A1

L

C

E

E1 eA eB eC

Dim.

mm inches

Min Typ Max Min Typ Max

A 3.56

3.76

5.08 0.140 0.148 0.200

A1 0.51

0.020

A2 3.05

3.56

4.57 0.120 0.140 0.180

b 0.36

0.46

0.58 0.014 0.018 0.023

b1 0.76

1.02

1.40 0.030 0.040 0.055

C 0.20

0.25

0.36 0.008 0.010 0.014

D 27.43

28.45 1.080 1.100 1.120

E 9.91 10.41 11.05 0.390 0.410 0.435

E1 7.62

8.89

9.40 0.300 0.350 0.370

e eA eB eC

1.78

10.16

0.070

0.400

12.70

0.500

1.40

0.055

L 2.54

3.05

3.81 0.100 0.120 0.150

N

Number of Pins

32

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13.2 THERMAL CHARACTERISTICS

Symbol

R thJA

P

D

T

Jmax

Ratings

Package thermal resistance (junction to ambient)

TQFP44 10x10

TQFP32 7x7

SDIP42 600mil

SDIP32 200mil

Power dissipation

1)

Maximum junction temperature

2)

Value

52

70

55

50

500

150

Unit

°C/W mW

°C

Notes:

1. The power dissipation is obtained from the formula P

D and P

PORT

=P

INT

+P

is the port power dissipation determined by the user.

PORT

where P

INT

is the chip internal power (I

DD xV

DD

)

2. The average chip-junction temperature can be obtained from the formula T

J

= T

A

+ P

D

x RthJA.

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13.3 SOLDERING INFORMATION

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.

These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard

JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK® specifications are available at www.st.com.

ST72324Jx ST72324Kx

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14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION

14.1 FLASH OPTION BYTES

STATIC OPTION BYTE 0

7

WDG VD

0 7

STATIC OPTION BYTE 1

OSCTYPE OSCRANGE

Default 1 1 1

1

0

0

0 1 1 1 1 1

1

1

0

0

2

1

1

1

0

1

The option bytes allows the hardware configuration of the microcontroller to be selected. They have no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh. To program directly the FLASH devices using ICP,

FLASH devices are shipped to customers with the internal RC clock source.

OPTION BYTE 0

OPT7= WDG HALT Watchdog reset on HALT

This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

OPT6= WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT5 = Reserved, must be kept at default value.

OPT4:3= VD[1:0] Voltage detection

These option bits enable the voltage detection block (LVD, and AVD) with a selected threshold for the LVD and AVD.

0

1

Selected Low Voltage Detector VD1 VD0

LVD and AVD Off 1

Lowest Voltage Threshold (V

DD

~3V) 1

Medium Voltage Threshold (V

DD

~3.5V) 0

Highest Voltage Threshold (V

DD

~4V) 0

1

0

1

0

Caution: If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below 3.8V, device operation is not guaranteed.

For details on the

AVD and LVD threshold levels refer to

Section

12.4.1 on page 119

OPT2:1 = Reserved, must be kept at default value.

OPT0= FMP_R Flash memory read-out protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory.

Erasing the option bytes when the FMP_R option is selected causes the whole user memory to be erased first, and the device can be reprogrammed.

Refer to Section 7.3.1 on page 37 and the ST7

Flash Programming Reference Manual for more details.

0: Read-out protection enabled

1: Read-out protection disabled

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ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

OPTION BYTE 1

OPT7= PKG1 Pin package selection bit

This option bit selects the package.

Version Selected Package PKG1 these option bits select the resonator oscillator current source corresponding to the frequency range of the used resonator. Otherwise, these bits are used to select the normal operating frequency range.

J TQFP44 / SDIP42 1

OSCRANGE

K TQFP32 / SDIP32 0

Typ. Freq. Range

2 1 0

Note: On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.

LP

MP

MS

1~2MHz

2~4MHz

4~8MHz

0

0

0

0

0

1

0

1

0

HS 8~16MHz 0 1 1

OPT6 = RSTC RESET clock cycle selection

This option bit selects the number of CPU cycles applied during the RESET phase and when exiting

HALT mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time.

0: Reset phase with 4096 CPU cycles

1: Reset phase with 256 CPU cycles

OPT5:4 = OSCTYPE[1:0] Oscillator Type

These option bits select the ST7 main clock source type.

Clock Source

Resonator Oscillator

Reserved

Internal RC Oscillator

External Source

OSCTYPE

0

1

1

1

0

1

0

1

0

0

OPT0 = PLL OFF PLL activation

This option bit activates the PLL which allows multiplication by two of the main input clock frequency.

The PLL must not be used with the internal RC oscillator. The PLL is guaranteed only with an input frequency between 2 and 4MHz.

0: PLL x2 enabled

1: PLL x2 disabled

CAUTION: the PLL can be enabled only if the

“OSC RANGE” (OPT3:1) bits are configured to

“MP - 2~4MHz”. Otherwise, the device functionality is not guaranteed.

OPT3:1 = OSCRANGE[2:0] Oscillator range

When the resonator oscillator type is selected,

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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

14.2 FLASH DEVICE ORDERING INFORMATiON

With the objective of continuous improvement, ST is developing new ST72F324B devices and is transferring the production to higher capacity fabs.

Refer to the following tables for guidance on ordering.

Standard and Industrial Versions

■ For new designs the ST72F324B devices from to the separate ST72324B datasheet.

■ For for running production orders select the

devices from Table 26

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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

Table 26. Standard and Industrial ST72F324 Flash Order Codes

Part Number

ST72F324K2B5

ST72F324K4B5

ST72F324K6B5

ST72F324J6B5

ST72F324K6T5

ST72F324K2T6

ST72F324K4T6

ST72F324K6T6

ST72F324K2T3

ST72F324K4T3

ST72F324K6T3

ST72F324J6T5

ST72F324J2T6

ST72F324J4T6

ST72F324J6T6

ST72F324J2T3

ST72F324J4T3

ST72F324J6T3

Package

SDIP32

SDIP42

TQFP32

TQFP44

Flash Memory (KBytes)

8

16

32

32

32

8

32

32

8

16

16

32

8

16

32

8

16

32

Temp. Range

-10°C +85°C

-10°C +85°C

-40°C +85°C

-40°C +125°C

-10°C +85°C

-40°C +85°C

-40°C +125°C

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14.3 SILICON IDENTIFICATION

The various ST72F324, ST72F324B and

ST72324B devices are identifiable both by the last letter of the Trace code marked on the device package and by the last 3 digits of the Internal

Sales Type printed on the box label.

Table 27. Silicon Identification (Standard and Industrial Versions)

Device Status Fab Memory

Trace Code marked on device

“xxxxxxxxx1”

Internal Sales Types on box label

72F324xxxx$x7

ST72F324xxxx

ST72F324Bxxxx

Current production Phoenix

End of production

Dec. 2005

Rousset

Current production.

Recommended for new designs

Rousset

8K to 32K

Flash “xxxxxxxxxW”

8K/16K Flash “xxxxxxxxxB”

72F324xxxx$x5

72F324Bxxxx$x4

ST72324Bxxxx Current production Phoenix

32K ROM “xxxxxxxxxA”

8K/16K ROM “xxxxxxxxxB”

72324Bxxxx$x1

72324Bxxxx$x3

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14.4 DEVELOPMENT TOOLS

STMicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site:

➟ http//:mcu.st.com.

Tools from these manufacturers include C compliers, emulators and gang programmers.

Emulators

Two types of emulators are available from ST for the ST72324 family:

■ ST7 DVP3 entry-level emulator offers a flexible and modular debugging and programming solution. SDIP42 & SDIP32 probes/adapters are included, other packages need a specific connection kit (refer to

Table 28

)

■ ST7 EMU3 high-end emulator is delivered with everything (probes, TEB, adapters etc.) needed to start emulating the ST72324 family. To configure it to emulate other ST7 subfamily devices, the active probe for the ST7EMU3 can be changed and the ST7EMU3 probe is designed for easy interchange of TEBs (Target

Emulation Board). See Table 28 .

In-circuit Debugging Kit

Two configurations are available from ST:

■

■

STXF521-IND/USB: Low-cost In-Circuit

Debugging kit from Softec Microsystems.

Includes STX-InDART/USB board (USB port) and a specific demo board for ST72521

(TQFP64)

STxF-INDART

Flash Programming tools

■ ST7-STICK ST7 In-circuit Communication Kit, a complete software/hardware package for programming ST7 Flash devices. It connects to a host PC parallel port and to the target board or socket board via ST7 ICC connector.

■ ICC Socket Boards provide an easy to use and flexible means of programming ST7 Flash devices. They can be connected to any tool that supports the ST7 ICC interface, such as ST7

EMU3, ST7-DVP3, inDART, ST7-STICK, or many third-party development tools.

Evaluation board

■ ST7232x-EVAL with ICC connector for programming capability. Provides direct connection to ST7-DVP3 emulator. Supplied with daughter boards (core module) for

ST72F321, ST72F324 & ST72F521 (the

ST72F321 & ST72F324 chips are not included)

Table 28. STMicroelectronics Development Tools

Supported

Products

ST7 DVP3 Series

Emulator

Emulation

Connection kit

ST7 EMU3 series

Emulator

Active Probe &

T.E.B.

ST72324BJ,

ST72F324J,

ST72F324BJ

ST72324BK,

ST72F324K,

ST72F324BK

ST7MDT20-DVP3

ST7MDT20-DVP3

ST7MDT20-T44/

DVP

ST7MDT20-T32/

DVP

ST7MDT20J-

EMU3

Programming

ICC Socket Board

ST7MDT20J-TEB ST7SB20J/xx

1

Note 1: Add suffix /EU, /UK, /US for the power supply of your region.

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14.4.1 Socket and Emulator Adapter

Information

For information on the type of socket that is supplied with the emulator, refer to the suggested list

of sockets in Table 29 .

Note: Before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device.

For footprint and other mechanical information about these sockets and adapters, refer to the manufacturer’s datasheet (www.yamaichi.de for

TQFP44 10 x 10 and www.ironwoodelectronics.com for TQFP32 7 x 7).

Table 29. Suggested List of Socket Types

Device

TQFP32 7 X 7

TQFP44 10 X10

Socket (supplied with

ST7MDT20J-EMU3)

IRONWOOD SF-QFE32SA-L-01

YAMAICHI IC149-044-*52-*5

Emulator Adapter (supplied with

ST7MDT20J-EMU3)

IRONWOOD SK-UGA06/32A-01

YAMAICHI ICP-044-5

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14.5 ST7 APPLICATION NOTES

Table 30. ST7 Application Notes

IDENTIFICATION DESCRIPTION

APPLICATION EXAMPLES

AN1658

AN1720

AN1755

SERIAL NUMBERING IMPLEMENTATION

MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS

A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555

EXAMPLE DRIVERS

AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC

AN 970

AN 972

SPI COMMUNICATION BETWEEN ST7 AND EEPROM

ST7 SOFTWARE SPI MASTER COMMUNICATION

AN 973

AN 974

AN 976

AN 979

SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER

REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE

DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION

DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC

AN 980

AN1041

AN1044

AN1046

AN1047

AN1048

AN1078

AN1445

ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE

USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD)

MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS

UART EMULATION SOFTWARE

MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS

ST7 SOFTWARE LCD DRIVER

PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE

EMULATED 16 BIT SLAVE SPI

AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER

GENERAL PURPOSE

AN1476

AN1709

LOW COST POWER SUPPLY FOR HOME APPLIANCES

EMC DESIGN FOR ST MICROCONTROLLERS

AN1752 ST72324 QUICK REFERENCE NOTE

PRODUCT EVALUATION

AN 910

AN 990

PERFORMANCE BENCHMARKING

ST7 BENEFITS VERSUS INDUSTRY STANDARD

AN1150

AN1151

BENCHMARK ST72 VS PC16

PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876

AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS

PRODUCT MIGRATION

AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324

AN2197

GUIDELINES FOR MIGRATING ST72F324 & ST72F321 APPLICATIONS TO ST72F324B,

ST72F321B OR ST72F325

PRODUCT OPTIMIZATION

AN 982

AN1014

AN1015

AN1070

USING ST7 WITH CERAMIC RESONATOR

HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE

ST7 CHECKSUM SELF-CHECKING CAPABILITY

AN1181

AN1502

ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT

EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY

AN1530

AN1636

ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-

TOR

UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS

PROGRAMMING AND TOOLS

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Table 30. ST7 Application Notes

IDENTIFICATION DESCRIPTION

AN 978

AN 983

ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES

KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE

AN 985

AN 986

AN 987

AN 988

EXECUTING CODE IN ST7 RAM

USING THE INDIRECT ADDRESSING MODE WITH ST7

ST7 SERIAL TEST CONTROLLER PROGRAMMING

STARTING WITH ST7 ASSEMBLY TOOL CHAIN

AN 989

AN1039

AN1064

AN1106

AN1446

AN1478

AN1575

AN1576

GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN

ST7 MATH UTILITY ROUTINES

WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7

TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7

USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION

PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE

ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS

IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS

AN1635

AN1754

ST7 CUSTOMER ROM CODE RELEASE INFORMATION

DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC

AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT

SYSTEM OPTIMIZATION

AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS

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15 KNOWN LIMITATIONS

15.1 ALL DEVICES

15.1.1 External RC option

The External RC clock source option described in previous datasheet revisions is no longer supported and has been removed from this specification.

15.1.2 CSS Function

The Clock Security System function has been removed from the datasheet.

15.1.3 Safe Connection of OSC1/OSC2 Pins

The OSC1 and/or OSC2 pins must not be left unconnected otherwise the ST7 main oscillator may start and, in this configuration, could generate an f

OSC

clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. Refer to

Section 6.2 on page

24

.

15.1.4 Unexpected Reset Fetch

If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the RESET vector address to the

CPU.

Workaround

To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction.

15.1.5 Clearing active interrupts outside interrupt routine

When an active interrupt request occurs at the same time as the related flag is being cleared, an unwanted reset may occur.

Note: clearing the related interrupt mask will not generate an unwanted reset

Concurrent interrupt context

The symptom does not occur when the interrupts are handled normally, i.e.

when:

– The interrupt flag is cleared within its own interrupt routine

– The interrupt flag is cleared within any interrupt routine

– The interrupt flag is cleared in any part of the code while this interrupt is disabled

If these conditions are not met, the symptom can be avoided by implementing the following sequence:

Perform SIM and RIM operation before and after resetting an active interrupt request.

Example:

SIM reset interrupt flag

RIM

Nested interrupt context:

The symptom does not occur when the interrupts are handled normally, i.e. when:

– The interrupt flag is cleared within its own interrupt routine

– The interrupt flag is cleared within any interrupt routine with higher or identical priority level

– The interrupt flag is cleared in any part of the code while this interrupt is disabled

If these conditions are not met, the symptom can be avoided by implementing the following sequence:

PUSH CC

SIM reset interrupt flag

POP CC

15.1.6 External Interrupt Missed

To avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either DDR and OR. Any input signal edge during this period will not be detected and will not generate an interrupt.

This case can typically occur if the application refreshes the port configuration registers at intervals during runtime.

Workaround

The workaround is based on software checking the level on the interrupt pin before and after writing to the PxOR or PxDDR registers. If there is a level change (depending on the sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction with three extra

PUSH instructions before executing the interrupt routine (this is to make the call compatible with the

IRET instruction at the end of the interrupt service routine).

But detection of the level change does ensure that edge occurs during the critical 1 cycle duration and the interrupt has been missed. This may lead to occurrence of same interrupt twice (one hardware and another with software call).

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KNOWN LIMITATIONS (Cont’d)

To avoid this, a semaphore is set to '1' before checking the level change. The semaphore is changed to level '0' inside the interrupt routine.

When a level change is detected, the semaphore status is checked and if it is '1' this means that the last interrupt has been missed. In this case, the interrupt routine is invoked with the call instruction.

There is another possible case, that is, if writing to

PxOR or PxDDR is done with global interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to '1' when the level change is detected. Detecting a missed interrupt is done after the global interrupts are enabled (interrupt mask bit reset) and by checking the status of the semaphore. If it is '1' this means that the last interrupt was missed and the interrupt routine is invoked with the call instruction.

To implement the workaround, the following software sequence is to be followed for writing into the

PxOR/PxDDR registers. The example is for Port

PF1 with falling edge interrupt sensitivity. The software sequence is given for both cases (global interrupt disabled/enabled).

Case 1: Writing to PxOR or PxDDR with Global Interrupts Enabled:

LD A,#01

LD sema,A

LD A,PFDR

AND A,#02

; set the semaphore to '1'

LD X,A

PxOR/PxDDR

; store the level before writing to

LD A,#$90

LD PFDDR,A ; Write to PFDDR

LD A,#$ff

LD PFOR,A ; Write to PFOR

LD A,PFDR

AND A,#02

LD Y,A

PxOR/PxDDR

; store the level after writing to

LD A,X ; check for falling edge cp A,#02 jrne OUT

TNZ Y jrne OUT

LD A,sema ; check the semaphore status if edge is detected

CP A,#01 jrne OUT call call_routine; call the interrupt routine

OUT:LD A,#00

LD sema,A

.call_routine

; entry to call_routine

PUSH A

PUSH X

PUSH CC

.ext1_rt

LD A,#00

; entry to interrupt routine

LD sema,A

IRET

Case 2: Writing to PxOR or PxDDR with Global Interrupts Disabled:

SIM

LD A,PFDR

; set the interrupt mask

AND A,#$02

LD X,A

PxOR/PxDDR

; store the level before writing to

LD A,#$90

LD PFDDR,A ; Write into PFDDR

LD A,#$ff

LD PFOR,A ; Write to PFOR

LD A,PFDR

AND A,#$02

LD Y,A

PxOR/PxDDR

LD A,X

; store the level after writing to

; check for falling edge cp A,#$02 jrne OUT

TNZ Y jrne OUT

LD A,#$01

LD sema,A detected

; set the semaphore to '1' if edge is

RIM

LD A,sema

CP A,#$01 jrne OUT

; reset the interrupt mask

; check the semaphore status call call_routine; call the interrupt routine

RIM

OUT: RIM

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JP while_loop

.call_routine

; entry to call_routine

PUSH A

PUSH X

PUSH CC

.ext1_rt

LD A,#$00

LD sema,A

; entry to interrupt routine

IRET

15.1.7 16-bit Timer PWM Mode

In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R register

(OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on the OLVL1 and

OLVL2 settings.

15.1.8 SCI Wrong Break duration

Description

A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected:

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1.

In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generate one break more than expected.

Occurrence

The occurrence of the problem is random and proportional to the baudrate. With a transmit frequency of 19200 baud (fCPU=8MHz and SCI-

BRR=0xC9), the wrong break duration occurrence is around 1%.

Workaround

If this wrong duration is not compliant with the communication protocol in the application, software can request that an Idle line be generated before the break character. In this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. This can be ensured by temporarily disabling interrupts.

The exact sequence is:

- Disable interrupts

- Reset and Set TE (IDLE request)

- Set and Reset SBK (Break Request)

- Re-enable interrupts

15.2 FLASH DEVICES ONLY

15.2.1 Internal RC Operation

In ST72F324J and ST72F324K devices, the internal RC oscillator is not supported if the LVD is disabled.

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16 IMPORTANT NOTES ON ST72F324B FLASH DEVICES:

With the objective of continuous improvement, ST has developed new ST72F324B devices. These devices are fully compatible with all ROM features and provide an improved price/performance ratio compared to the ST72F324 flash devices.

A summary of the technical improvements is given below.

Refer to separate ST72324B datasheet for the ordering information and full specifications.

16.5 Timer A Registers

In ST72F324B Flash devices, all Timer A registers are present and their functionality is the same as described for ROM devices in the ST72324B datasheet.

16.1 Reset Pin Logic levels

In ST72F324B Flash devices, the V

IH

/V

IL

levels for the reset pin are the same as specified for ROM devices

16.2 Wake-Up from Active Halt mode using external interrupts

In ST72F324B Flash devices, any external interrupt that capable of waking-up the MCU from Halt mode can also wake-up the MCU from Active Halt

mode. Consequently note 1 below Table 8 on page 36 does not apply to ‘B’ devices.

16.3 PLL Jitter

In ST72F324B Flash devices, PLL clock accuracy is improved and the jitter is the same as specified for ROM devices

16.4 Active Halt Power Consumption

In ST72F324B Flash devices, the power consumption in Active Halt mode is specified as

230µA max. See

Table 12.5.1 on page 120

for test conditions.

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17 REVISION HISTORY

Table 31. Revision History

Date

05-May-2004

30-Mar-2005

08-Nov-2005

04-Apr-2008

Revision

2.0

3

4

5

Description of Changes

Merged ST72F324 Flash with ST72324B ROM datasheet.

Vt POR max modified in Section 12.4 on page 119

Added Figure 78 on page 137

Modified V

AREF

min in

“10-BIT ADC CHARACTERISTICS” on page 142

Modified I INJ for PB0 in

Section 12.9

Added “Clearing active interrupts outside interrupt routine” on page 159

Modified “32K ROM DEVICES ONLY” on page 164

Removed Clock Security System (CSS) throughout document

Added notes on ST72F324B 8K/16K Flash devices in Table 1 and

Table 27

Corrected MCO description in Table 1 and

Section 10.2

Modified VtPOR in Section 12.4 on page 119

Static current consumption modified in

Section 12.9 on page 133

Updated footnote and Figure 77 and Figure 78 on page 137

Modified Soldering information in Section 13.3

Updated Section 14 on page 150

Added Table 27

Modified Figure 7

and note 4 in “FLASH PROGRAM MEMORY” on page 17

Added limitation on ICC entry mode with 39 pulses to

“KNOWN LIMITATIONS” on page 159

Added Section 16 on page 162 for ST72F324B 8K/16K Flash devices

Modified “Internal Sales Types on box label” in Table 29

Removed information on ST72F324B and ROM devices (now in separate datasheet)

Changed status to “Not for new design”

Added “External interrupt missed” in “KNOWN LIMITATIONS” on page 159

Removed information on automotive versions (now in separate datasheet)

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