STMicroelectronics 8-bit MCU Datasheet

ST7LITEUS2

ST7LITEUS5

8-bit MCU with single voltage Flash memory, ADC, timers

Features

■

■

■

■

Memories

– 1 Kbytes single-voltage Flash Program memory with readout protection, ICP and

IAP)

10 K write/erase cycles guaranteed data retention: 20 years at 55 °C

– 128 bytes RAM

Clock, Reset and Supply management

– 3-level low-voltage supervisor (LVD) and auxiliary voltage detector (AVD) for safe power-on/off

– Clock sources: internal trimmable 8 MHz

RC oscillator, internal low power, low frequency RC oscillator or external clock

– Five power saving modes: Halt, Autowakeup from Halt, Active-halt, Wait, Slow

Interrupt management

– 11 interrupt vectors plus TRAP and RESET

– 5 external interrupt lines (on 5 vectors)

I/O ports

– 5 multifunctional bidirectional I/O lines

– 1 additional Output line

– 6 alternate function lines

– 5 high sink outputs

Table 1.

Device summary

Features ST7LITEUS2

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■

■

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Plastic DIP8

SO8

150” DFN8

Plastic DIP16

2 Timers

– One 8-bit Lite timer (LT) with prescaler including: watchdog, one realtime base and one 8-bit input capture.

– One 12-bit auto-reload timer (AT) with output compare function and PWM

A/D Converter

– 10-bit resolution for 0 to V

DD

– 5 input channels

Instruction Set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode detection

– 17 main addressing modes

– 8x8 unsigned multiply instruction

Development Tools

– Full hardware/software development package

– Debug module

ST7LITEUS5

Program memory

RAM (stack)

1 Kbytes

Obsolete Product(s) - Obsolete Product(s)

Peripherals LT Timer w/ Wdg, AT Timer w/ 1 PWM

Obsolete Product(s) - Obsolete Product(s)

Operating Supply 2.4 to 3.3 V @f

CPU

=4 MHz, 3.3 to 5.5 V @f

CPU

=8 MHz

CPU Frequency up to 8 MHz RC

Operating Temperature

Packages

-40 to +85 °C / -40 to 125 °C

SO8 150”, Pastic DIP8, DFN8, Pastic DIP16

(1)

1.

For development or tool prototyping purposes only. Not orderable in production quantities.

February 2009 Rev 5 1/136 www.st.com

1

ST7LITEUS2, ST7LITEUS5 Contents

Contents

3

4

1

2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3

Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.1

In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3.2

In application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.4

I

2

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.5

Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.5.1

4.5.2

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Flash Write/Erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.6

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.7

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.7.1

Flash Control/Status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.1

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.2

5.3.3

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Obsolete Product(s) - Obsolete Product(s)

5.3.4

5.3.5

Condition Code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Obsolete Product(s) - Obsolete Product(s)

6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.2

Internal RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/136

ST7LITEUS2, ST7LITEUS5 Contents

7

6.3

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

Main Clock Control/Status register (MCCSR) . . . . . . . . . . . . . . . . . . . . 30

RC Control register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

System Integrity (SI) Control/status register (SICSR) . . . . . . . . . . . . . . 31

AVD Threshold Selection register (AVDTHCR) . . . . . . . . . . . . . . . . . . . 32

Clock Controller Control/Status register (CKCNTCSR) . . . . . . . . . . . . . 32

6.4

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

External Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 36

Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5.1

6.5.2

Multiplexed I/O Reset Control register 1 (MUXCR1) . . . . . . . . . . . . . . . 37

Multiplexed I/O Reset Control register 0 (MUXCR0) . . . . . . . . . . . . . . . 37

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.1

Non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.2

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.3

Peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.3.1

7.3.2

External Interrupt Control register 1 (EICR1) . . . . . . . . . . . . . . . . . . . . . 41

External Interrupt Control register 2 (EICR2) . . . . . . . . . . . . . . . . . . . . . 42

7.4

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.4.1

7.4.2

7.4.3

7.4.4

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Obsolete Product(s) - Obsolete Product(s)

8.2

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Obsolete Product(s) - Obsolete Product(s)

8.3

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.4

Active-halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.4.1

8.4.2

Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.5

Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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Contents ST7LITEUS2, ST7LITEUS5

9

8.5.1

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.2

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.2.1

9.2.2

9.2.3

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

9.3

Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.4

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.6

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1

Lite timer (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1.3

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

10.1.4

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.1.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10.1.6

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10.2

12-bit auto-reload timer (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.2.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.2.3

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.2.4

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

10.2.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.2.6

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10.3

10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Obsolete Product(s) - Obsolete Product(s)

10.3.2

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Obsolete Product(s) - Obsolete Product(s)

10.3.3

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

10.3.4

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.3.5

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.3.6

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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ST7LITEUS2, ST7LITEUS5 Contents

11 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.1

ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.1.1

Inherent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

11.1.2

Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11.1.3

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11.1.4

Indexed mode (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . 86

11.1.5

Indirect modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.1.6

Indirect indexed modes (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.1.7

Relative modes (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2

Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

11.2.1

Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1.1

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1.2

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1.3

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1.4

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1.5

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.2

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.3

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.3.1

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

12.3.2

Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . 95

12.3.3

Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . 96

12.3.4

Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

12.4

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

12.4.1

Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

12.4.2

Internal RC oscillator supply current characteristics . . . . . . . . . . . . . . 100

12.5

12.4.3

On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Obsolete Product(s) - Obsolete Product(s)

12.6

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Obsolete Product(s) - Obsolete Product(s)

12.7

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

12.7.1

Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 105

12.7.2

Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

12.7.3

Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 106

12.8

I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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14

15

16

ST7LITEUS2, ST7LITEUS5

12.8.1

General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

12.8.2

Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 109

12.9

Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.10 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

13.1

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

13.2

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Device configuration and ordering information . . . . . . . . . . . . . . . . . 123

14.1

Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

14.1.1

OPTION BYTE 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

14.1.2

OPTION BYTE 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14.2

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

14.3

Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.3.1

Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.3.2

Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.3.3

Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.3.4

Order codes for development and programming tools . . . . . . . . . . . . . 128

14.4

ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Device pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

FLASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Predefined RC oscillator calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Internal RC prescaler selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clock register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Multiplexed IO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 9.

Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 10.

Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 11.

Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 12.

Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 13.

System integrity register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 14.

Enabling/disabling Active-halt and Halt modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 15.

Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 16.

AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 17.

DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 18.

I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 19.

I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 20.

Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 21.

Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 22.

Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 23.

I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 24.

Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 25.

Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 26.

Lite timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 27.

Description of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 28.

Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 29.

Counter clock selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 30.

Register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 31.

Effect of low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 32.

Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 33.

Configuring the ADC clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 34.

ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 35.

Description of addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 36.

ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 37.

Instructions supporting inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 38.

Instructions supporting inherent immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . 86

Obsolete Product(s) - Obsolete Product(s)

Table 40.

Instructions supporting relative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 41.

ST7 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Obsolete Product(s) - Obsolete Product(s)

Table 43.

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 44.

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 45.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 46.

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 47.

Operating characteristics with LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 48.

Operating characteristics with AVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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Table 49.

Voltage drop between AVD flag set and LVD reset generation . . . . . . . . . . . . . . . . . . . . . 96

Table 50.

Internal RC oscillator characteristics (5.0 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 51.

Internal RC oscillator characteristics (3.3 V calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 52.

Supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 53.

Internal RC oscillator supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 54.

On-chip peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 55.

General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 56.

Auto-wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 57.

RAM and Hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 58.

Flash Program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 59.

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 60.

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 61.

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 62.

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 63.

General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 64.

Output driving current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 65.

Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 66.

10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 67.

ADC accuracy with VDD = 3.3 to 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 68.

ADC accuracy with VDD = 2.7 to 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 69.

ADC accuracy with VDD = 2.4V to 2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 70.

8-lead very thin fine pitch dual flat no-lead package mechanical data . . . . . . . . . . . . . . . 118

Table 71.

8-pin plastic small outline package, 150-mil width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 72.

8-pin plastic dual in-line package, 300-mil width package mechanical data. . . . . . . . . . . 120

Table 73.

16-pin plastic dual in-line package, 300-mil width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 74.

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 75.

Startup clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 76.

LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 77.

Definition of sector 0 size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 79.

Supported order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 80.

Development tool order codes for the ST7LITEUSx family . . . . . . . . . . . . . . . . . . . . . . . 129

Table 81.

ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 82.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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List of figures ST7LITEUS2, ST7LITEUS5

List of figures

Figure 1.

General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2.

8-pin SO and Plastic DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3.

8-pin DFN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4.

16-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5.

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6.

Typical I

2

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7.

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 8.

Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 9.

Clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 10.

Clock management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11.

Reset sequence phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 12.

Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13.

Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 14.

Interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 15.

Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 16.

Reset and supply management block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 17.

Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 18.

Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 19.

Slow mode clock transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 20.

Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 21.

Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 22.

Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 23.

Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 24.

Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 25.

AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 26.

AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 27.

AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 28.

I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 29.

Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 30.

Lite timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 31.

Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 32.

Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 33.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 34.

PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 35.

PWM signal example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 36.

ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 37.

Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 38.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Obsolete Product(s) - Obsolete Product(s)

Figure 40.

Typical accuracy with RCCR=RCCR0 vs VDD= 2.4-6.0 V and temperature . . . . . . . . . . . 98

Figure 41.

Typical accuracy with RCCR=RCCR1 vs VDD= 2.4-6.0V and temperature. . . . . . . . . . . . 98

Obsolete Product(s) - Obsolete Product(s)

Figure 43.

Typical IDD in WFI mode vs. internal clock frequency and VDD . . . . . . . . . . . . . . . . . . . 101

Figure 44.

Typical IDD in Slow, Slow-wait and Active-halt mode vs VDD & int

RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 45.

I

DD

vs temp @VDD 5 V & int RC = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 46.

I

DD

vs temp @VDD 5 V & int RC = 4 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 47.

I

DD

vs temp @VDD 5 V & int RC = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

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List of figures ST7LITEUS2, ST7LITEUS5

Figure 48.

Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 49.

Typical IPU vs. VDD with VIN=VSSl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 50.

Typical VOL at VDD = 2.4 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 51.

Typical VOL at VDD = 3 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 52.

Typical VOL at VDD = 5 V (standard pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 53.

Typical VOL at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 54.

Typical VOL at VDD = 3 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 55.

Typical VOL at VDD = 5 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 56.

Typical VDD-VOH at VDD = 2.4 V (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 57.

Typical VDD-VOH at VDD = 3 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 58.

Typical VDD-VOH at VDD = 5 V (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 59.

Typical VOL vs. VDD (HS pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 60.

Typical VDD-VOH vs. VDD (HS pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 61.

RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 62.

RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 63.

Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 64.

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 65.

8-lead very thin fine pitch dual flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 66.

8-pin plastic small outline package, 150-mil width package outline . . . . . . . . . . . . . . . . . 119

Figure 67.

8-pin plastic dual in-line package, 300-mil width package outline . . . . . . . . . . . . . . . . . . 120

Figure 68.

16-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 121

Figure 69.

Option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Obsolete Product(s) - Obsolete Product(s)

10/136

ST7LITEUS2, ST7LITEUS5

1 Introduction

Introduction

The ST7LITEUS2 and ST7LITEUS5 are members of the ST7 microcontroller family. All ST7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set.

The ST7LITEUS2 and ST7LITEUS5 feature FLASH memory with byte-by-byte In-Circuit

Programming (ICP) and In-Application Programming (IAP) capability.

Under software control, the ST7LITEUS2 and ST7LITEUS5 can be placed in Wait, Slow, or

Halt mode, reducing power consumption when the application is in idle or standby state.

The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

For easy reference, all parametric data are located in

Section 12 on page 92 .

The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD).

For a description of the DM registers, refer to the ST7 I

2

C protocol reference manual.

Figure 1.

General block diagram

Internal

Clock AWU RC OSC

8-MHz RC OSC

External

Clock

V

DD

V

SS

PA3 / RESET

LVD

POWER

SUPPLY

CONTROL

8-BIT CORE

ALU

1 KByte

FLASH

MEMORY

LITE TIMER with WATCHDOG

PORT A

12-BIT AUTO-

RELOAD TIMER

10-BIT ADC

PA5:0

(6 bits)

RAM

(128 Bytes)

Obsolete Product(s) - Obsolete Product(s)

11/136

Pin description ST7LITEUS2, ST7LITEUS5

Figure 2.

8-pin SO and Plastic DIP package pinout

V

DD

1

PA5 (HS) / AIN4 / CLKIN 2 ei4

PA4 (HS) / AIN3/MCO 3 ei3

PA3 / RESET 4

8 V

SS ei0 7 PA0 (HS) / AIN0 / ATPWM / ICCDATA ei1 6 PA1 (HS) / AIN1 / ICCCLK ei2 5 PA2 (HS) / LTIC / AIN2

1.

HS: High sink capability.

2.

eix : associated external interrupt vector

Figure 3.

8-pin DFN package pinout

V

DD

PA5 (HS) / AIN4 / CLKIN

1

2 ei4

PA4 (HS) / AIN3/MCO 3 ei3

PA3 / RESET 4

8 ei0 7

V

SS

PA0 (HS) / AIN0 / ATPWM / ICCDATA ei1 6 PA1 (HS) / AIN1 / ICCCLK ei2 5 PA2 (HS) / LTIC / AIN2

1.

HS: High sink capability.

2.

eix : associated external interrupt vector

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEUS2, ST7LITEUS5

Figure 4.

16-pin package pinout

Pin description

Reserved

1)

1

V

DD

2

RESET 3

4 ICCCLK

PA5 (HS) / AIN4 / CLKIN

PA4 (HS) / AIN3/MCO

5 ei4

6 ei3

PA3

NC

7

8

1 NC

1 V

SS ei0 1 PA0 (HS) / AIN0 / ATPWM ei1 1 PA1 (HS) / AIN1

12 NC

11 ICCDATA ei2 10 PA2 (HS) / LTIC / AIN2

9 NC

1.

Reserved pins must be tied to ground.

2.

The differences versus the 8-pin packages are listed below:

The I

2

C signals (ICCCLK and ICCDATA) are mapped on dedicated pins.

The RESET signal is mapped on a dedicated pin. It is not multiplexed with PA3.

PA3 pin is always configured as output. Any change on multiplexed IO reset control registers (MUXCR1 and MUXCR2) will have no effect on PA3 functionality. Refer to

Section 6.5: Register description on page 37 .

Obsolete Product(s) - Obsolete Product(s)

13/136

Pin description ST7LITEUS2, ST7LITEUS5

Table 2.

Pin no.

Legend/abbreviations for

Table 2

Type: I = input, O = output, S = supply

In/Output level: C

T

= CMOS 0.3 V

DD

/0.7 V

DD

with input trigger

Output level: HS = High sink (on N-buffer only)

●

●

Port and control configuration

Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog

Output: OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Device pin description

Level

Pin name

Port/control

Input Output

Main function

(after reset)

Alternate function

1

2

V

DD

PA5/AIN4/CLKIN

S

I/

O

C

T

HS X ei4 X X X

Main power supply

Port A5

Analog input 4 or External Clock

Input

3 PA4/AIN3/MCO

I/

O

C

T

HS X

O X ei3 X X X Port A4 Analog input 3 or main clock output

4

5

6

PA3/RESET

PA2/AIN2/LTIC

PA1/AIN1/

ICCCLK

PA0/AIN0/ATPW

M/ICCDATA

(1)

I/

O

I/

O

I/

O

C

C

T

T

HS

HS

HS

X

X

X ei2 ei1 ei0

X

X X

Port

X X Port A2

Analog input 2 or Lite Timer Input

Capture

X

X

X

X

X

X

Port A1

Port A0

Analog input 1 or In Circuit

Communication Clock

Caution: During normal operation this pin must be pulled-up, internally or externally (external pull-up of 10k mandatory in noisy environment).

This is to avoid entering I

2

C mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in pull-up

Analog input 0 or Auto-Reload

Timer PWM or In Circuit

Communication Data

V

SS

S Ground

1.

After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to

MUXCR0 and AAh to MUXCR1. For further details, please refer to

Section 6.5 on page 37

.

14/136

ST7LITEUS2, ST7LITEUS5

3 Register and memory map

Register and memory map

As shown in

Figure 5 , the MCU is capable of addressing 64K bytes of memories and I/O

registers.

The available memory locations consist of 128 bytes of register locations, 128 bytes of RAM and 1 Kbyte of user program memory. The RAM space includes up to 64 bytes for the stack from 00C0h to 00FFh.

The highest address bytes contain the user reset and interrupt vectors.

The Flash memory contains two sectors (see

Figure 5 ) mapped in the upper part of the ST7

addressing space so the reset and interrupt vectors are located in Sector 0 (FE00h-FFFFh).

The size of Flash Sector 0 and other device options are configurable by option byte.

Warning: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.

Figure 5.

Memory map

0000h

0080h HW registers

(1)

Short addressing

RAM (zero page) 007Fh

0080h

00C0h

RAM 64-byte stack

00FFh

00FFh

0100h

Reserved

DEE0h

DEE1h

DEE2h

DEE3h

RCCRH0

RCCRL0

RCCRH1

RCCRL1

1Kbytes FLASH

PROGRAM MEMORY

FBFFh

FC00h

FC00h

0.5 Kbytes

SECTOR 1

FDFFh

FE00h

0.5 Kbytes

Flash Memory

SECTOR 0

FFFFh

(1 Kbytes)

Obsolete Product(s) - Obsolete Product(s)

Interrupt & Reset vectors

(3)

1.

See

Table 3 .

2.

See

Section 6.2 on page 28

for the description of RCCRHx registers.

3.

See

Table 9

.

15/136

Register and memory map ST7LITEUS2, ST7LITEUS5

Table 3.

Hardware register map

(1)

Address Block

Register label

Register name Reset status Remarks

0000h

0001h

0002h

0003h-

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h to

0016h

Port A

PADR

PADDR

PAOR

LITE

TIMER

AUTO-

RELOAD

TIMER

LTCSR

LTICR

ATCSR

CNTRH

CNTRL

ATRH

ATRL

PWMCR

PWM0CSR

0017h

0018h

AUTO-

RELOAD

TIMER

DCR0H

DCR0L

0019h to

002Eh

0002Fh FLASH FCSR

0030h to

0033h

0034h

0035h

0036h

ADC

ADCCSR

ADCDRH

ADCDRL

0037h

0038h

ITC

MCC

EICR1

MCCSR

Port A Data register

Port A Data Direction register

Port A Option register

Reserved area (8 bytes)

Lite Timer Control/Status register

Lite Timer Input Capture register

Timer Control/Status register

Counter register High

Counter register Low

Auto-Reload register High

Auto-Reload register Low

PWM Output Control register

PWM 0 Control/Status register

Reserved area (3 bytes)

PWM 0 Duty Cycle register High

PWM 0 Duty Cycle register Low

Reserved area (22 bytes)

Flash Control/Status register

Reserved area (4 bytes)

A/D Control Status register

A/D Data register High

A/D Data register Low

External Interrupt Control register 1

Main Clock Control/Status register

00h

(2)

08h

02h

(3)

0xh

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h

00h xxh

00h

00h

00h

R/W

R/W

R/W

R/W

Read only

R/W

Read only

Read only

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Read only

R/W

R/W

R/W

0039h

003Ah

Clock and

Reset

RCCR

SICSR

RC oscillator Control register

System Integrity Control/Status register

FFh

0000 0x00b

R/W

R/W

003Bh to

003Ch

Reserved area (2 bytes)

003Dh ITC EICR2 External Interrupt Control register 2 00h R/W Obsolete Product(s) - Obsolete Product(s)

003Eh AVD AVDTHCR AVD Threshold Selection register 03h R/W

09h R/W CKCNTCSR Clock Controller Control/Status register

0040h to

0046h

0047h

0048h

MuxIOreset

MUXCR0

MUXCR1

Reserved area (7 bytes)

Mux IO-Reset Control register 0

Mux IO-Reset Control register 1

00h

00h

R/W

R/W

16/136

ST7LITEUS2, ST7LITEUS5 Register and memory map

Table 3.

Hardware register map (continued)

(1)

Address Block

Register label

Register name Reset status Remarks

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h to

007Fh

AWU

DM

(4)

AWUPR

AWUCSR

DMCR

DMSR

DMBK1H

DMBK1L

DMBK2H

DMBK2L

AWU Prescaler register

AWU Control/Status register

DM Control register

DM Status register

DM Breakpoint register 1 High

DM Breakpoint register 1 Low

DM Breakpoint register 2 High

DM Breakpoint register 2 Low

Reserved area (47 bytes)

FFh

00h

00h

00h

00h

00h

00h

00h

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

1.

Legend: x=undefined, R/W=read/write

2.

The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the

I/O pins are returned instead of the DR register contents.

3.

The bits associated with unavailable pins must always keep their reset value.

4.

For a description of the DM registers, see the ST7 I

2

C Protocol Reference Manual.

Obsolete Product(s) - Obsolete Product(s)

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Flash program memory

4 Flash program memory

ST7LITEUS2, ST7LITEUS5

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel.

The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using in-circuit programming or in-application programming.

The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

●

●

●

●

●

ICP (in-circuit programming)

IAP (in-application programming)

ICT (in-circuit testing) for downloading and executing user application test patterns in

RAM

Sector 0 size configurable by option byte

Readout and write protection

The ST7 can be programmed in three different ways:

● Insertion in a programming tool

In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased.

● In-circuit programming

In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board.

● In-application programming

In this mode, sector 1 can be programmed or erased without removing the device from the application board and while the application is running.

Obsolete Product(s) - Obsolete Product(s)

ICP uses a protocol called I C (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected Obsolete Product(s) - Obsolete Product(s)

● Switch the ST7 to I

2

C mode. This is done by driving a specific signal sequence on the

ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters I

2

C mode, it fetches a specific RESET vector which points to the ST7 system memory containing

18/136

ST7LITEUS2, ST7LITEUS5

4.3.2

Flash program memory

●

● the I

2

C protocol routine. This routine enables the ST7 to receive bytes from the I

2

C interface.

Download ICP driver code in RAM from the ICCDATA pin

Execute ICP driver code in RAM to program the FLASH memory

Depending on the ICP driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

In application programming (IAP)

This mode uses an IAP driver program previously programmed in Sector 0 by the user (in

ICP mode).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc).

IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.4 I

2

C interface

ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:

●

●

●

●

RESET: device reset

V

SS

: device power supply ground

ICCCLK: I

2

ICCDATA: I

C output serial clock pin

2

C input serial data pin

●

●

CLKIN: main clock input for external source

V

DD

: application board power supply

Refer to

Figure 6 for a description of the I

2

C interface.

If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal

I isolation is necessary. As soon as the programming tool is plugged to the board, even if an

2

C session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the programming tool documentation for recommended resistor values.

During the ICP session, the programming tool must control the RESET pin. This can lead to Obsolete Product(s) - Obsolete Product(s)

5 mA at high level (push pull output or pull-up resistor<1 k

Ω

). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with

R>1 k

Ω

or a reset management IC with open drain output and pull-up resistor>1 k

Ω

, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the I

2

C session.

The use of Pin 7 of the I

2

C connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual.

19/136

Flash program memory ST7LITEUS2, ST7LITEUS5

Pin 9 has to be connected to the CLKIN pin of the ST7 when I

2

C mode is selected with option bytes disabled (35-pulse I

2

C entry mode). When option bytes are enabled (38-pulse

I

2

C entry mode), the internal RC clock (internal RC or AWU RC) is forced. If internal RC is selected in the option byte, the internal RC is provided. If AWU RC or external clock is selected, the AWU RC oscillator is provided.

A serial resistor must be connected to I

2

C connector pin 6 in order to prevent contention on

PA3/RESET pin. Contention may occur if a tool forces a state on RESET pin while PA3 pin forces the opposite state in output mode. The resistor value is defined to limit the current below 2 mA at 5 V. If PA3 is used as output push-pull, then the application must be switched off to allow the tool to take control of the RESET pin (PA3). To allow the programming tool to drive the RESET pin below V

IL

, special care must also be taken when a pull-up is placed on

PA3 for application reasons.

Caution: During normal operation, ICCCLK pin must be pulled- up, internally or externally (external pull-up of 10 k

Ω

mandatory in noisy environment). This is to avoid entering I

2

C mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up.

Figure 6.

Typical I

2

C interface

APPLICATION

POWER SUPPLY

(See Note 3)

PROGRAMMING TOOL

I

2

C CONNECTOR

I

2

C Cable

I

2

C CONNECTOR

HE10 CONNECTOR TYPE

OPTIONAL

(See Note 4)

9 7 5 3

10 8 6 4

1

2

3.3k

Ω

(See Note 5)

APPLICATION BOARD

APPLICATION

RESET SOURCE

See Note 2

See Note 1 and Caution

See Note 1

APPLICATION

I/O

ST7

There are two different types of memory protection: readout protection and Write/Erase Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s)

Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Program memory is protected.

20/136

ST7LITEUS2, ST7LITEUS5 Flash program memory

In flash devices, this protection is removed by reprogramming the option. In this case, program memory is automatically erased, and the device can be reprogrammed.

●

●

Readout protection selection depends on the device type:

In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

In ROM devices it is enabled by mask option specified in the option list.

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content.

Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable.

Write/erase protection is enabled through the FMP_W bit in the option byte.

For details on Flash programming and I

2

C protocol, refer to the ST7 Flash programming reference manual and to the ST7 I

2

C protocol reference manual .

Obsolete Product(s) - Obsolete Product(s)

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Flash program memory ST7LITEUS2, ST7LITEUS5

This register controls the XFlash erasing and programming using ICP, IAP or other programming methods.

1st RASS Key: 0101 0110 (56h)

2nd RASS Key: 1010 1110 (AEh)

When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

Reset value: 000 0000 (00h)

7

0 0 0 0 0 OPT LAT

0

PGM

Read/write

Table 4.

Address

(Hex.)

FLASH register map and reset values

Register

Label

7 6 5 4

002Fh

FCSR

Reset value

0 0 0 0

3

0

2

OPT

0

1

LAT

0

0

PGM

0

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEUS2, ST7LITEUS5

5 Central processing unit

Central processing unit

5.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.

●

●

●

●

●

●

●

●

63 basic instructions

Fast 8-bit by 8-bit multiply

17 main addressing modes

Two 8-bit index registers

16-bit stack pointer

Low power modes

Maskable hardware interrupts

Non-maskable software interrupt

The six CPU registers shown in Figure 7 are not present in the memory mapping and are

accessed by specific instructions.

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

5.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The cross-assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the

Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Obsolete Product(s) - Obsolete Product(s)

5.3.3 Program counter (PC) the LSB) and PCH (program counter high which is the MSB).

23/136

Central processing unit ST7LITEUS2, ST7LITEUS5

Figure 7.

CPU registers

7 0

RESET VALUE = XXh

7 0

RESET VALUE = XXh

7 0

15 PCH 8

RESET VALUE = XXh

7 PCL 0

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7

1

RESET VALUE = 1

1 1 H I N Z

1 1 X 1 X X X

0

C

15 8 7 0

RESET VALUE = STACK HIGHER ADDRESS

1.

X = Undefined value

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Reset value: 111x1xxx

7

1 1 1 H I N Z

0

C

Read/Write

Obsolete Product(s) - Obsolete Product(s)

24/136

ST7LITEUS2, ST7LITEUS5 Central processing unit

Bit 7:5 Set to ‘1’

Bit 4 H Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 3 I Interrupt mask

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0: Interrupts are enabled.

1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the

JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 N Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th

bit of the result.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 Z Zero

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0: The result of the last operation is different from zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

This bit is driven by the SCF and RCF instructions and tested by the JRC and Obsolete Product(s) - Obsolete Product(s) instructions.

25/136

Central processing unit

5.3.5

Note:

ST7LITEUS2, ST7LITEUS5

Stack Pointer (SP)

Reset value: 00 FFh

15

0 0 0 0 0 0 0

8

0

Read/write

7

1 1 SP5 SP4 SP3 SP2 SP1

0

SP0

Read/write

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see

Figure 8

).

Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware.

Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in

Figure 8 .

● When an interrupt is received, the SP is decremented and the context is pushed on the stack.

● On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call is located at two locations and an interrupt five locations in the stack area.

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEUS2, ST7LITEUS5

Figure 8.

Stack manipulation example

CALL subroutine

Interrupt event

PUSH Y

@ 00C0h

POP Y

Central processing unit

IRET

SP

@ 00FFh

PCH

PCL

SP

CC

A

X

PCH

PCL

PCH

PCL

SP

Y

CC

A

X

PCH

PCL

PCH

PCL

SP

CC

A

X

PCH

PCL

PCH

PCL

SP

PCH

PCL

SP

RET or RSP

1.

Stack higher address = 00FFh.

2.

Stack lower address = 00C0h.

Obsolete Product(s) - Obsolete Product(s)

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Supply, reset and clock management

6 Supply, reset and clock management

ST7LITEUS2, ST7LITEUS5

The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components.

●

●

●

Clock management

– 8 MHz internal RC oscillator (enabled by option byte)

– External clock Input (enabled by option byte)

Reset sequence manager (RSM)

System integrity management (SI)

– Main supply low voltage detection (LVD) with reset generation (enabled by option byte)

– Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main supply

6.2 Internal RC oscillator adjustment

The ST7 contains an internal RC oscillator with a specific accuracy for a given device, temperature and voltage. It can be selected as the start up clock through the CKSEL[1:0] option bits (see

Section 14.1 on page 123 ). It must be calibrated to obtain the frequency

required in the application. This is done by software writing a 10-bit calibration value in the

RCCR (RC Control register) and in the bits [6:5] in the SICSR (SI Control Status register).

Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in Flash memory for 3.3 and 5 V V

DD supply voltages at 25°C, as shown in the following table.

Table 5.

RCCR

Predefined RC oscillator calibration values

Conditions ST7LITEUS2/ST7LITEUS5 address

RCCRH0 DEE0h

(1)

(CR[9:2] bits) V

DD

=5 V

T

A

=25 °C

RCCRL0

V

DD

=3.3 V

DEE1h

1)

(CR[1:0] bits) f

RC

=8 MHz

Obsolete Product(s) - Obsolete Product(s)

T

A

=25 °C

DEE2h

1)

(CR[9:2] bits)

RCCRL1 f

RC

=8 MHz

DEE3h

1)

(CR[1:0] bits)

Obsolete Product(s) - Obsolete Product(s) the RC calibration values which are read-accessible only in user mode. If all the Flash space (including the

RC calibration value locations) has been erased (after the readout protection removal), then the RC calibration values can still be obtained through these two addresses.

28/136

ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management

Note: 1 In I

2

C mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Refer to note 5 in

Section 4.4 on page 19

for further details.

2 See

Section 12: Electrical characteristics

for more information on the frequency and accuracy of the RC oscillator.

3 To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the V

DD

and V device.

SS

pins as close as possible to the ST7

Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated.

Refer to application note AN2326 for information on how to calibrate the RC frequency using an external reference signal.

The ST7LITEUS2 and ST7LITEUS5 also contain an Auto-wakeup RC oscillator. This RC oscillator should be enabled to enter Auto-wakeup from Halt mode.

The Auto-wakeup RC oscillator can also be configured as the startup clock through the

CKSEL[1:0] option bits (see Section 14.1 on page 123

).

This is recommended for applications where very low power consumption is required.

Switching from one startup clock to another can be done in run mode as follows (see

Figure 9 ):

Case 1

Switching from internal RC to AWU:

1.

Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator

2. The RC_FLAG is cleared and the clock output is at 1.

3. Wait 3 AWU RC cycles till the AWU_FLAG is set

4. The switch to the AWU clock is made at the positive edge of the AWU clock signal

5. Once the switch is made, the internal RC is stopped

Case 2

Switching from AWU RC to internal RC:

1.

Reset the RC/AWU bit to enable the internal RC oscillator

2. Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is running on internal RC clock.

3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC cycles)

4. The switch to the internal RC clock is made at the positive edge of the internal RC clock Obsolete Product(s) - Obsolete Product(s)

Note: 1

5. Once the switch is made, the AWU RC is stopped

Obsolete Product(s) - Obsolete Product(s)

2 When the internal RC is selected, the AWU RC is turned on by hardware when entering

Auto-wakeup from Halt mode.

3 When the external clock is selected, the AWU RC oscillator is always on.

29/136

Supply, reset and clock management ST7LITEUS2, ST7LITEUS5

Figure 9.

Clock switching

Internal RC

Set RC/AWU

Poll AWU_FLAG until set

AWU RC

AWU RC

Reset RC/AWU

Poll RC_FLAG until set

Internal RC

6.3.1 Main Clock Control/Status register (MCCSR)

Reset value: 0000 0000 (00h)

7

0 0 0 0 0

Read / Write

0 MCO

0

SMS

Bits 7:2 Reserved, must be kept cleared.

Bit 1 MCO Main Clock Out enable bit

This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock.

0: MCO clock disabled, I/O port free for general purpose I/O.

1: MCO clock enabled.

Bit 0 SMS Slow Mode select

This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock f

OSC

or f

OSC

/32.

0: Normal mode (f

CPU = f

OSC

)

1: Slow mode (f

CPU = f

OSC

/32)

Obsolete Product(s) - Obsolete Product(s)

30/136

ST7LITEUS2, ST7LITEUS5

6.3.2

Supply, reset and clock management

RC Control register (RCCR)

Reset value: 1111 1111 (FFh)

7

CR9 CR8 CR7 CR6

Read / Write

CR5 CR4 CR3

0

CR2

6.3.3

Bits 7:0 CR[9:2] RC Oscillator Frequency Adjustment Bits

These bits, as well as CR[1:0] bits in the SICSR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy. The application can store the correct value for each voltage range in Flash memory and write it to this register at startup.

00h = maximum available frequency

FFh = lowest available frequency

Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h.

System Integrity (SI) Control/status register (SICSR)

Reset value: 0000 0x00 (0xh)

7

0 CR1 CR0 0 LVDRF 0

Read / Write

AVDF

0

AVDIE

Bit 7 Reserved, must be kept cleared.

Bits 6:5 CR[1:0] RC Oscillator Frequency Adjustment bits

These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the

required accuracy. Refer to Section 6.2 on page 28 .

Bits 4:3 Reserved, must be kept cleared.

Bits 2:0 System Integrity bits. Refer to

Section 7.4 on page 43 .

Obsolete Product(s) - Obsolete Product(s)

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Supply, reset and clock management

6.3.4 AVD Threshold Selection register (AVDTHCR)

Reset value: 0000 0011 (03h)

7

CK2 CK1 CK0 0 0

Read / Write

0

ST7LITEUS2, ST7LITEUS5

AVD1

0

AVD0

Bits 7:5 CK[2:0] Internal RC Prescaler Selection

These bits are set by software and cleared by hardware after a reset. These bits

select the prescaler of the internal RC oscillator. See Figure 10 on page 34

and

Table 6 .

Bits 4:2 Reserved, must be kept cleared.

Bits 1:0 AVD Threshold Selection bits. Refer to

Section 7.4: System integrity management

(SI)

.

Table 6.

Internal RC prescaler selection bits

(1)

CK2 CK1 CK0 f

OSC

0

0

0

0

0

0

1

1

0

1

0

1 f

RC f

RC/2 f

RC/4 f

RC/8

1 0 0 f

RC/16

1.

If the internal RC is used with a supply operating range below 3.3 V, a division ratio of at least 2 must be enabled in the RC prescaler.

Read/Write

Reset value: 0000 1001 (09h)

7

0 0 0 0 AWU_FLAG

Read / Write

RC_

FLAG

0

0

RC/AWU

Bit 3 AWU_FLAG AWU Selection

Obsolete Product(s) - Obsolete Product(s)

0: No switch from AWU to RC requested

1: AWU clock activated and temporization completed

32/136

ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management

Bit 2 RC_FLAG RC Selection

This bit is set and cleared by hardware

0: No switch from RC to AWU requested

1: RC clock activated and temporization completed

Bit 1 = Reserved, must be kept cleared.

Bit 0 = RC/AWU RC/AWU Selection

0: RC enabled

1: AWU enabled (default value)

Table 7.

Address

(Hex.)

0038h

0039h

003Ah

003Eh

003Fh

Clock register map and reset values

Register label

7 6 5

MCCSR

Reset value

RCCR reset value

SICSR reset value

AVDTHCR reset value

CKCNTCSR reset value

0

CR9

1

0

CK2

0

0

0

CR8

1

CR1

CK1

0

0

0

CR7

1

CR0

CK0

0

0

4

0

CR6

1

0

0

0

3

0

CR5

1

0

0

2

0

CR4

1

LVDRF x

0

AWU_FLAG

1

RC_FLAG

0

1 0

MCO

0

CR3

1

AVDF

0

AVD1

1

0

SMS

0

CR2

1

AVDIE

0

AVD2

1

RC/AWU

1

Obsolete Product(s) - Obsolete Product(s)

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Supply, reset and clock management

Figure 10.

Clock management block diagram

CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2

RCCR

CR1 CR0 SICSR

ST7LITEUS2, ST7LITEUS5

Tunable internal RC Oscillator

RC/AWU

CKCNTCSR

CLKIN

8MHz(f

RC

)

Prescaler

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

RC OSC

Clock

Controller

AWU CK

33kHz

AWU

RC f

CLKIN

/2

DIVIDER

Ext Clock

CKSEL[1:0]

Option bits f

OSC f

OSC

/32 DIVIDER

13-BIT

LITE TIMER COUNTER f

OSC

0 f

OSC

/32

1 f

LTIMER

(1ms timebase @ 8 MHz f

OSC

) f

CPU

TO CPU AND

PERIPHERALS

MCO SMS MCCSR

MCO

Obsolete Product(s) - Obsolete Product(s)

34/136

ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management

6.4 Reset sequence manager (RSM)

6.4.1 Introduction

Note:

The reset sequence manager includes three reset sources as shown in

Figure 12

:

●

●

●

External RESET source pulse

Internal LVD reset (low voltage detection)

Internal WATCHDOG reset

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to

Figure 12

.

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

●

●

●

The basic reset sequence consists of 3 phases as shown in

Figure 11

:

Active phase depending on the reset source

64 CPU clock cycle delay

RESET vector fetch

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior.

The 64 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock cycles.

Figure 11.

Reset sequence phases

Active phase

RESET

INTERNAL RESET

64 CLOCK CYCLES

FETCH

VECTOR

Obsolete Product(s) - Obsolete Product(s)

35/136

Supply, reset and clock management

Figure 12.

Reset block diagram

V

DD

R

ON

RESET FILTER

PULSE

GENERATOR

ST7LITEUS2, ST7LITEUS5

INTERNAL

RESET

WATCHDOG RESET

ILLEGAL OPCODE RESET

1)

LVD RESET

6.4.2

6.4.3

1.

Section 11.2.1: Illegal opcode reset for more details on illegal opcode reset conditions

Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated R

ON

weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details.

A RESET signal originating from an external source must have a duration of at least t h(RSTL)in

in order to be recognized (see Figure 13

). This detection is asynchronous and therefore the MCU can enter reset state even in Halt mode.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

External Power-on reset

If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until V

DD

is over the minimum level specified for the selected f

CLKIN

frequency.

A proper reset signal for a slow rising V

DD

RC network connected to the RESET pin.

supply can generally be provided by an external

6.4.4 Internal low voltage detector (LVD) reset

Obsolete Product(s) - Obsolete Product(s)

●

●

Power-on reset

Obsolete Product(s) - Obsolete Product(s)

The device RESET pin acts as an output that is pulled low when V

DD

<V

IT+

(rising edge) or

V

DD

<V

IT-

(falling edge) as shown in

Figure 13

.

The LVD filters spikes on V

DD larger than t g(VDD) to avoid parasitic resets.

36/136

ST7LITEUS2, ST7LITEUS5

6.4.5

Supply, reset and clock management

Internal watchdog reset

The reset sequence generated by a internal watchdog counter overflow is shown in

Figure 13

.

Starting from the watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least t w(RSTL)out

.

Figure 13.

Reset sequences

V

DD

V

IT+(LVD)

V

IT-(LVD)

Run

LVD

RESET

ACTIVE PHASE

Run

EXTERNAL

RESET

ACTIVE

PHASE

WATCHDOG

RESET

Run

ACTIVE

PHASE

Run t h(RSTL)in t w(RSTL)out

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (64 T

CPU

)

VECTOR FETCH

6.5.1 Multiplexed I/O Reset Control register 1 (MUXCR1)

Reset value: 0000 0000 (00h)

7

MIR15 MIR14 MIR13 MIR12 MIR11 MIR10

Read / Write once

MIR9

0

MIR8

Multiplexed I/O Reset Control register 0 (MUXCR0)

Reset value: 0000 0000 (00h) Obsolete Product(s) - Obsolete Product(s)

7 0

MIR7 MIR6 MIR5 MIR4 MIR3 MIR2 MIR1 MIR0

Read / Write once

Bits 15:0 MIR[15:0]

37/136

Supply, reset and clock management ST7LITEUS2, ST7LITEUS5

This 16-bit register is read/write by software but can be written only once between two reset events. It is cleared by hardware after a reset; When both MUXCR0 and MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.

These registers are one-time writable only.

● To configure PA3 as general purpose output:

After power-on / reset, the application program has to configure the I/O port by writing to these registers as described above. Once the pin is configured as an I/O output, it cannot be changed back to a reset pin by the application code.

● To configure PA3 as RESET:

An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear the two registers and the pin will act again as a reset function. Otherwise, a power-down is required to put the pin back in reset configuration.

Table 8.

Address

(Hex.)

Multiplexed IO register map and reset values

Register label

7 6 5 4 3

0047h

0048h

MUXCR0 reset value

MUXCR1 reset value

MIR7

0

MIR15

0

MIR6

0

MIR14

0

MIR5

0

MIR4

0

MIR13

0

MIR12

0

MIR3

0

MIR11

0

2

MIR2

0

MIR10

0

1

MIR1

0

MIR9

0

0

MIR0

0

MIR8

0

Obsolete Product(s) - Obsolete Product(s)

38/136

ST7LITEUS2, ST7LITEUS5

7 Interrupts

Note:

Note:

Interrupts

The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt

(TRAP). The Interrupt processing flowchart is shown in

Figure 14

.

The maskable interrupts must be enabled by clearing the I bit in order to be serviced.

However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).

After reset, all interrupts are disabled.

●

●

●

●

When an interrupt has to be serviced:

Normal processing is suspended at the end of the current instruction execution.

The PC, X, A and CC registers are saved onto the stack.

The I bit of the CC register is set to prevent additional interrupts.

The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table for vector addresses).

The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack.

As a consequence of the IRET instruction, the I bit is cleared and the main program resumes.

Priority management

By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.

In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see

Table 9: Interrupt mapping ).

Interrupts and low power mode

All interrupts allow the processor to leave the Wait low power mode. Only external and specifically mentioned interrupts allow the processor to leave the Halt low power mode (refer to the “Exit from Halt” column in

Table 9: Interrupt mapping

).

7.1 Non maskable software interrupt

the I bit. It is serviced according to the flowchart in

Figure 14 .

39/136

Interrupts ST7LITEUS2, ST7LITEUS5

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the

Halt low power mode.

The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).

An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.

Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of rising-edge sensitivity.

Note:

●

●

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:

The I bit of the CC register is cleared.

The corresponding enable bit is set in the control register.

If any of these two conditions is false, the interrupt is latched and thus remains pending.

●

●

Clearing an interrupt request is done by:

Writing “0” to the corresponding bit in the status register or

Access to the status register while the flag is set followed by a read or write of an associated register.

The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear sequence is executed.

Figure 14.

Interrupt processing flowchart

FROM RESET

N

I BIT SET?

Y N

INTERRUPT

PENDING?

Y

FETCH NEXT INSTRUCTION

Obsolete Product(s) - Obsolete Product(s)

N

IRET?

STACK PC, X, A, CC

SET I BIT

Obsolete Product(s) - Obsolete Product(s)

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

40/136

ST7LITEUS2, ST7LITEUS5 Interrupts

Table 9.

Interrupt mapping

N° Source block Description

Register label

Priority order

Exit from

Halt

Address vector

3

4

5

6

2)

7

0

1

2

RESET

TRAP

AWU ei0 ei1 ei2 ei3 ei4

2)

SI

Reset

Software interrupt

Auto-wakeup interrupt

External interrupt 0

External interrupt 1

External interrupt 2

Not used

External interrupt 3

External interrupt 4

2)

AVD interrupt

N/A

AWUCSR

N/A

Highest priority yes no yes

(1) yes no yes no

(2) no

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

8

9

10

11

12

13

AT TIMER

LITE TIMER

AT TIMER Output Compare Interrupt

AT TIMER Overflow Interrupt

LITE TIMER Input Capture Interrupt

LITE TIMER RTC1 Interrupt

Not used

Not used

SICSR

PWMxCS

R or

ATCSR

ATCSR

LTCSR

LTCSR

Lowest priority no yes no no no

(3)

yes

(3)

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

FFE2h-FFE3h

FFE0h-FFE1h

1.

This interrupt exits the MCU from Auto-wakeup from Halt mode only.

2.

This interrupt exits the MCU from Wait and Active-halt modes only. Moreover, IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH mode

3.

These interrupts exit the MCU from Active-halt mode only.

7.3.1 External Interrupt Control register 1 (EICR1)

Reset value: 0000 0000 (00h)

7 0

0 0 IS21 IS20 IS11 IS10 IS01 IS00

Obsolete Product(s) - Obsolete Product(s)

Read/Write

Bits 5:4 IS2[1:0] ei2 sensitivity

These bits define the interrupt sensitivity for ei2 according to Table 10

.

Bits 3:2 IS1[1:0] ei1 sensitivity

These bits define the interrupt sensitivity for ei1 according to Table 10

.

Bits 1:0 IS0[1:0] ei0 sensitivity

These bits define the interrupt sensitivity for ei0 according to Table 10

.

41/136

Interrupts ST7LITEUS2, ST7LITEUS5

Note: 1 These 8 bits can be written only when the I bit in the CC register is set.

2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This

can be used to clear unwanted pending interrupts. Refer to Section : External interrupt function .

7.3.2 External Interrupt Control register 2 (EICR2)

Reset value: 0000 0000 (00h)

7

0 0 0 0

Read/Write

IS41 IS40 IS31

0

IS30

Bits 7:4 Reserved

Bits 3:2 IS4[1:0] ei4 sensitivity

These bits define the interrupt sensitivity for ei1 according to Table 10

.

Bits 1:0 IS3[1:0] ei3 sensitivity

These bits define the interrupt sensitivity for ei0 according to Table 10

.

Note: 1 These 8 bits can be written only when the I bit in the CC register is set.

2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This

can be used to clear unwanted pending interrupts. Refer to Section : External interrupt function .

3 IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH modes.

Table 10.

Interrupt sensitivity bits

ISx1 ISx0

0

0

1

1

0

1

0

1

External interrupt sensitivity

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

Obsolete Product(s) - Obsolete Product(s)

42/136

ST7LITEUS2, ST7LITEUS5 Interrupts

7.4

Note:

System integrity management (SI)

The System Integrity Management block contains the low voltage detector (LVD) and

Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to

Section 11.2.1: Illegal opcode reset

for further details.

7.4.1 Low voltage detector (LVD)

The low voltage detector function (LVD) generates a static reset when the V

DD

supply voltage is below a V

IT-(LVD)

reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.

The V

IT-(LVD)

reference value for a voltage drop is lower than the V

IT+(LVD)

reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when V

DD

is below:

● V

IT+(LVD)

when V

DD

is rising

● V

IT-(LVD)

when V

DD

is falling

The LVD function is illustrated in Figure 15 .

The voltage threshold can be configured by option byte to be low, medium or high. See

Section 14.1: Option bytes .

●

●

Provided the minimum V

DD

value (guaranteed for the oscillator frequency) is above V

IT-(LVD)

, the MCU can only be in two modes:

Under full software control

In static safe reset

In these conditions, secure operation is always ensured for the application without the need for external reset hardware.

During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Note: Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull V

DD

down to 0V to ensure optimum restart

conditions. Refer to circuit example in Figure 62

and note 4.

The LVD is an optional function which can be selected by option byte. See Section 14.1 on page 123

. It allows the device to be used without any external RESET circuitry. If the LVD is disabled, an external circuitry must be used to ensure a proper Power-on reset.

It is recommended to make sure that the V

DD supply voltage rises monotonously when the Obsolete Product(s) - Obsolete Product(s)

Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels

Obsolete Product(s) - Obsolete Product(s)

Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will clear the watchdog flag.

43/136

Interrupts

Figure 15.

Low voltage detector vs reset

V

DD

V hys

V

IT+ (LVD)

V

IT(LVD)

ST7LITEUS2, ST7LITEUS5

RESET

Figure 16.

Reset and supply management block diagram

WATCHDOG

TIMER (WDG)

STATUS FLAG

RESET

RESET SEQUENCE

MANAGER

(RSM)

SYSTEM INTEGRITY MANAGEMENT

AVD Interrupt Request

SICSR

7

0 1 1 0 0

LVD

RF

AVD

F

AVD

IE

0

V

SS

V

DD

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEUS2, ST7LITEUS5 Interrupts

7.4.2 Auxiliary voltage detector (AVD)

The voltage detector function (AVD) is based on an analog comparison between a V

IT-(AVD) and V

IT+(AVD)

reference value and the V

DD

main supply voltage (V

AVD

). The V

IT-(AVD) reference value for falling voltage is lower than the V

IT+(AVD)

reference value for rising voltage in order to avoid parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a real time status bit (AVDF) in the SICSR register. This bit is read only.

Note:

Monitoring the V

DD

main supply

The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register.

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the

V

IT+(AVD)

or V

IT-(AVD)

threshold (AVDF bit is set).

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing

software to shut down safely before the LVD resets the microcontroller. See Figure 17

.

The interrupt on the rising edge is used to inform the application that the V

DD

warning state is over

Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to

Table 47 on page 95

and

Table 48 on page 96

for more details.

Figure 17.

Using the AVD to monitor V

DD

V

DD

Early Warning Interrupt

(Power has dropped, MCU not not yet in reset)

V hyst

V

IT+(AVD)

V

IT-(AVD)

V

IT+(LVD)

V

IT-(LVD)

AVDF bit 0 1 RESET 1 0

AVD INTERRUPT

REQUEST

IF AVDIE bit = 1

INTERRUPT Cleared by reset

INTERRUPT Cleared by hardware

LVD RESET

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45/136

Interrupts

7.4.3

ST7LITEUS2, ST7LITEUS5

Low power modes

Table 11.

Description of low power modes

Mode Description

Wait

Halt

No effect on SI. AVD interrupts cause the device to exit from Wait mode.

The SICSR register is frozen.

The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode.

Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit

(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

Table 12.

Description of interrupt events

AVD event

Interrupt Event Event flag

AVDF

Enable control bit

AVDIE

Exit from

Wait

Yes

Exit from

Halt

No

System Integrity (SI) Control/Status register (SICSR)

Reset value: 0000 0x00 (0xh)

7

0 CR1 CR0 0 LVDRF 0

Read/write

AVDF

0

AVDIE

Bit 7 Reserved, must be kept cleared.

Bits 6:5 CR[1:0] RC Oscillator Frequency Adjustment bits

These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the

required accuracy. Refer to Section 6.2: Internal RC oscillator adjustment on page 28 .

Bits 4:3 Reserved, must be kept cleared.

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ST7LITEUS2, ST7LITEUS5 Interrupts

Bit 2 LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by hardware (LVD reset) and cleared when read. See WDGRF flag description in

Section 10.1.6 on page 69

for more details. When the LVD is disabled by OPTION

BYTE, the LVDRF bit value is undefined.

Note: If the selected clock source is one of the two internal ones, and if V

DD remains below the selected LVD threshold during less than T

AWU

(33us typ.), the LVDRF flag cannot be set even if the device is reset by the LVD.

If the selected clock source is the external clock (CLKIN), the flag is never set if the reset occurs during Halt mode. In run mode the flag is set only if f

CLKIN

is greater than 10 MHz.

Bit 1 AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an

interrupt request is generated when the AVDF bit is set. Refer to Figure 17

for additional details

0: V

DD

over AVD threshold

1: V

DD

under AVD threshold

Bit 0 AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automatically cleared when software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

AVD Threshold Selection register (AVDTHCR)

Refer to

Section 6.3.4: AVD Threshold Selection register (AVDTHCR) for a full description of

this register.

Application notes

The LVDRF flag is not cleared when another reset type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can not.

Table 13.

System integrity register map and reset values

Address

(Hex.)

Register label

7 6 5 4 3 2 1 0

003Ah

SICSR reset value

0 1 1 0 0

LVDRF x

AVDF

0

AVDIE

0

Obsolete Product(s) - Obsolete Product(s)

003Eh

AVDTHCR reset

CK2

0

CK1

0

CK0

0

0 0 0

AVD1

1

AVD2

1 value Obsolete Product(s) - Obsolete Product(s)

47/136

Power saving modes ST7LITEUS2, ST7LITEUS5

8.1 Introduction

●

●

●

●

●

To give a large measure of flexibility to the application in terms of power consumption, four

main power saving modes are implemented in the ST7 (see Figure 18 ):

Slow

Wait (and Slow-wait)

Active-halt

Auto-wakeup from Halt (AWUFH)

Halt

After a reset the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (f

OSC

).

From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 18.

Power saving mode transitions

High

Run

Slow

Wait

Slow wait

Active halt

Halt

Low

POWER CONSUMPTION

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEUS2, ST7LITEUS5 Power saving modes

Note:

This mode has two targets:

●

●

To reduce power consumption by decreasing the internal clock in the device,

To adapt the internal clock frequency (f

CPU

) to the available supply voltage.

Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables

Slow mode.

In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency.

Slow-wait mode is activated when entering Wait mode while the device is already in Slow mode.

Figure 19.

Slow mode clock transition f

OSC

/32 f

OSC f

CPU f

OSC

SMS

NORMAL RUN MODE

REQUEST

Wait mode places the MCU in a low power consumption mode by stopping the CPU.

This power saving mode is selected by calling the ‘WFI’ instruction.

All peripherals remain active. During Wait mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in Wait mode until an interrupt or reset occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine.

The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wakeup.

Refer to

Figure 20

for a description of the Wait mode flowchart.

Obsolete Product(s) - Obsolete Product(s)

49/136

ST7LITEUS2, ST7LITEUS5 Power saving modes

Figure 20.

Wait mode flowchart

WFI INSTRUCTION

OSCILLATOR

PERIPHERALS

CPU

I BIT

ON

ON

OFF

0

N

N

RESET

Y

INTERRUPT

Y

OSCILLATOR

PERIPHERALS

CPU

I BIT

ON

OFF

ON

0

64 CPU CLOCK CYCLE

DELAY

OSCILLATOR

PERIPHERALS

CPU

I BIT

ON

ON

ON

X

1)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1.

1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

8.4 Active-halt and Halt modes

Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Activehalt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following table:

Table 14.

Enabling/disabling Active-halt and Halt modes

LTCSR TBIE bit

ATCSR OVFIE bit

ATCSRCK1 bit ATCSRCK0 bit Meaning x x 0

0 0 x x Active-halt mode disabled

Obsolete Product(s) - Obsolete Product(s)

1 x x x

Active-halt mode enabled x 1 0 1

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ST7LITEUS2, ST7LITEUS5 Power saving modes

Active-halt mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ instruction when Active-halt mode is enabled.

The MCU can exit Active-halt mode on reception of a Lite Timer / AT Timer interrupt or a reset.

● When exiting Active-halt mode by means of a reset, a 64 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see

Figure 22

).

● When exiting Active-halt mode by means of an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see

Figure 22

).

When entering Active-halt mode, the I bit in the CC register is cleared to enable interrupts.

Therefore, if an interrupt is pending, the MCU wakes up immediately.

In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wakeup time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).

Caution: As soon as Active-halt is enabled, executing a HALT instruction while the watchdog is active does not generate a reset if the WDGHALT bit is reset.

This means that the device cannot spend more than a defined delay in this power saving mode.

Figure 21.

Active-halt timing overview

Run

Active halt

64 CPU

CYCLE DELAY

1)

HALT

INSTRUCTION

[Active-halt Enabled]

RESET

OR

INTERRUPT

Run

FETCH

VECTOR

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51/136

Power saving modes

Figure 22.

Active-halt mode flowchart

HALT INSTRUCTION

(Active-halt enabled)

OSCILLATOR

PERIPHERALS 2)

CPU

I BIT

ON

OFF

OFF

0

ST7LITEUS2, ST7LITEUS5

N

RESET

Y

N

INTERRUPT 3)

Y OSCILLATOR

PERIPHERALS 2)

CPU

I BIT

ON

OFF

ON

X 4)

64 CPU CLOCK CYCLE

DELAY

OSCILLATOR

PERIPHERALS

CPU

I BITS

ON

ON

ON

X 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1.

This delay occurs only if the MCU exits Active-halt mode by means of a reset.

2.

Peripherals clocked with an external clock source can still be active.

3.

Only the Lite Timer RTC and AT Timer interrupts can exit the MCU from Active-halt mode.

4.

Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

The Halt mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when Active-halt mode is disabled.

The MCU can exit Halt mode on reception of either a specific interrupt (see

Table 9:

Interrupt mapping ) or a reset. When exiting Halt mode by means of a reset or an interrupt,

the main oscillator is immediately turned on and the 64 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing the interrupt or by

fetching the reset vector which woke it up (see Figure 24 ).

When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.

Therefore, if an interrupt is pending, the MCU wakes immediately.

In Halt mode, the main oscillator is turned off causing all internal processing to be stopped, Obsolete Product(s) - Obsolete Product(s) ones which get their clock supply from another clock generator (such as an external or

Obsolete Product(s) - Obsolete Product(s)

The compatibility of watchdog operation with Halt mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the watchdog

system is enabled, can generate a watchdog reset (see Section 14.1: Option bytes

for more details).

52/136

ST7LITEUS2, ST7LITEUS5

Figure 23.

Halt timing overview

Run Halt

64 CPU CYCLE

DELAY

HALT

INSTRUCTION

[ Active-halt disabled ]

RESET

OR

INTERRUPT

Run

FETCH

VECTOR

1.

A reset pulse of at least 42µs must be applied when exiting from Halt mode.

Figure 24.

Halt mode flowchart

HALT INSTRUCTION

(Active-halt disabled)

ENABLE

0

WDGHALT 1)

1

WATCHDOG

RESET

CPU

I BIT

WATCHDOG

OSCILLATOR

PERIPHERALS

DISABLE

2)

OFF

OFF

OFF

0

N

RESET

Y

N

INTERRUPT 3)

Y OSCILLATOR

PERIPHERALS

CPU

I BIT

ON

OFF

ON

X

4)

64 CPU CLOCK CYCLE

DELAY

5)

OSCILLATOR

PERIPHERALS

CPU

I BITS

ON

ON

ON

X 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Power saving modes

2.

Peripheral clocked with an external clock source can still be active.

3.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Obsolete Product(s) - Obsolete Product(s)

4.

Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.

5.

The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.

53/136

Power saving modes ST7LITEUS2, ST7LITEUS5

Halt mode recommendations

●

●

●

●

●

Make sure that an external event is available to wakeup the microcontroller from Halt mode.

When using an external interrupt to wakeup the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.

For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure.

The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value

0x8E from memory. For example, avoid defining a constant in ROM with the value

0x8E.

As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction.

This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt).

8.5 Auto-wakeup from Halt mode

Auto-wakeup from Halt (AWUFH) mode is similar to Halt mode with the addition of a specific internal RC oscillator for wakeup (Auto-wakeup from Halt oscillator) which replaces the main clock which was active before entering Halt mode. Compared to Active-halt mode, AWUFH has lower power consumption (the main clock is not kept running), but there is no accurate realtime clock available.

It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set.

Figure 25.

AWUFH mode block diagram

AWU RC oscillator f

AWU_RC to 8-bit Timer input capture

/64 divider

AWUFH prescaler/1 .. 255

AWUFH interrupt

(ei0 source)

Obsolete Product(s) - Obsolete Product(s)

As soon as Halt mode is entered, and if the AWUEN bit has been set in the AWUCSR register, the AWU RC oscillator provides a clock signal (f

AWU_RC

). Its frequency is divided by Obsolete Product(s) - Obsolete Product(s) of this prescaler provides the delay time. When the delay has elapsed, the following actions are performed:

●

●

●

The AWUF flag is set by hardware,

An interrupt wakes-up the MCU from Halt mode,

The main oscillator is immediately turned on and the 64 CPU cycle delay is used to stabilize it.

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ST7LITEUS2, ST7LITEUS5 Power saving modes

After this startup delay, the CPU resumes operation by servicing the AWUFH interrupt. The

AWU flag and its associated interrupt are cleared by software reading the AWUCSR register.

To compensate for any frequency dispersion of the AWU RC oscillator, it can be calibrated by measuring the clock frequency f

AWU_RC and then calculating the right prescaler value.

Measurement mode is enabled by setting the AWUM bit in the AWUCSR register in Run mode. This connects f

AWU_RC

to the input capture of the 8-bit lite timer, allowing the f

AWU_RC

to be measured using the main oscillator clock as a reference timebase.

Similarities with Halt mode

The following AWUFH mode behavior is the same as normal Halt mode:

● The MCU can exit AWUFH mode by means of any interrupt with exit from Halt

capability or a reset (see Section 8.4: Active-halt and Halt modes

).

●

●

When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.

In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator).

● The compatibility of watchdog operation with AWUFH mode is configured by the

WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the watchdog system is enabled, can generate a watchdog reset.

Figure 26.

AWUF Halt timing diagram t

AWU

RUN MODE HALT MODE f

CPU f

AWU_RC

64 t

CPU

RUN MODE

Clear by software

AWUFH interrupt

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55/136

Power saving modes

Figure 27.

AWUFH mode flowchart

HALT INSTRUCTION

(Active-Halt disabled)

(AWUCSR.AWUEN=1)

ENABLE

0

WDGHALT

1)

1

WATCHDOG

RESET

WATCHDOG

DISABLE

AWU RC OSC ON

MAIN OSC OFF

PERIPHERALS 2)

OFF

CPU

I[1:0] BITS

OFF

10

ST7LITEUS2, ST7LITEUS5

N

INTERRUPT 3)

Y

N

RESET

Y

AWU RC OSC OFF

MAIN OSC ON

PERIPHERALS

CPU

I[1:0] BITS

OFF

ON

XX

4)

64 CPU CLOCK

CYCLE DELAY

AWU RC OSC OFF

MAIN OSC

PERIPHERALS

ON

ON

CPU

I[1:0] BITS

ON

XX

4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

1.

WDGHALT is an option bit. See option byte section for more details.

2.

Peripheral clocked with an external clock source can still be active.

3.

Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 9: Interrupt mapping for more details.

4.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered when the CC register is popped.

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEUS2, ST7LITEUS5 Power saving modes

AWUFH Control/ Status register (AWUCSR)

Reset value: 0000 0000 (00h)

7

0 0 0 0 0

Read/Write

AWU

F

AWUM

0

AWUEN

Bits 7:3 Reserved

Bit 2 AWUF Auto-wakeup Flag

This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value.

0: No AWU interrupt occurred

1: AWU interrupt occurred

Bit 1 AWUM Auto-wakeup Measurement

This bit enables the AWU RC oscillator and connects its output to the input capture of the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPRE register.

0: Measurement disabled

1: Measurement enabled

Bit 0 AWUEN Auto-wakeup From Halt Enabled

This bit enables the Auto-wakeup From Halt feature: once Halt mode is entered, the

AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software.

0: AWUFH (Auto-wakeup From Halt) mode disabled

1: AWUFH (Auto-wakeup From Halt) mode enabled

Note: Whatever the clock source, this bit should be set to enable the AWUFH mode once the HALT instruction has been executed.

AWUFH Prescaler register (AWUPR)

Reset value: 1111 1111 (FFh)

7 0

AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3

Read/Write

AWUPR2 AWUPR1 AWUPR0

Obsolete Product(s) - Obsolete Product(s)

Bits 7:0 AWUPR[7:0] Auto-wakeup Prescaler

These 8 bits define the AWUPR Dividing factor (see

Table 15: Configuring the dividing factor

)

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Power saving modes ST7LITEUS2, ST7LITEUS5

Table 15.

Configuring the dividing factor

AWUPR[7:0 ] Dividing

00h

01h

...

FEh

FFh

Forbidden

1

...

254

255

In AWU mode, the period that the MCU stays in Halt Mode (t

AWU

in

Figure 26

) is defined by

Note: t

AWU

= 64

×

AWUPR

× f

1

+ t

RCSTRT

AWURC

This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically.

If 00h is written to AWUPR, depending on the product, an interrupt is generated immediately after a HALT instruction, or the AWUPR remains unchanged.

Table 16.

AWU register map and reset values

Address

(Hex.)

Register label

7 6 5 4

0049h

004Ah

AWUPR

Reset value

AWUCSR

Reset value

AWUP

R7

1

0

AWUP

R6

1

0

AWUP

R5

1

0

AWUP

R4

1

0

3

AWUP

R3

1

AWUP

R2

1

AWUP

R1

1

AWUP

R0

1

0

2 1 0

AWUF AWUM

AWUE

N

Obsolete Product(s) - Obsolete Product(s)

58/136

ST7LITEUS2, ST7LITEUS5 I/O ports

9.1 Introduction

The I/O port offers different functional modes:

● Transfer of data through digital inputs and outputs

●

● and for specific pins:

External interrupt generation

Alternate signal input/output for the on-chip peripherals.

An I/O port contains up to 6 pins. Each pin (except PA3/RESET) can be programmed independently as digital input (with or without interrupt generation) or digital output.

Each port has 2 main registers:

●

●

Data register (DR)

Data Direction register (DDR) and one optional register:

● Option register (OR)

Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the

DR register.

The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block

diagram is shown in Figure 28

.

The input configuration is selected by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Note: 1 Writing the DR register modifies the latch value but does not affect the pin status.

2 PA3 cannot be configured as input.

When an I/O is configured as Input with Interrupt, an event on this I/O can generate an Obsolete Product(s) - Obsolete Product(s)

Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register.

External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts.

59/136

I/O ports ST7LITEUS2, ST7LITEUS5

Spurious interrupts

When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register.

To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again.

Caution: In case a pin level change occurs during these operations (asynchronous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts before and to reenable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge.

This corresponds to the following steps:

1.

To enable an external interrupt: a) Set the interrupt mask with the SIM instruction (in cases where a pin level change could occur) c) Enable the external interrupt through the OR register d) Select the desired sensitivity if different from rising edge e) Reset the interrupt mask with the RIM instruction (in cases where a pin level change could occur)

2. To disable an external interrupt: a) Set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) c) Disable the external interrupt through the OR register

The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.

Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.

Obsolete Product(s) - Obsolete Product(s)

Push-pull Open-drain DR

Obsolete Product(s) - Obsolete Product(s)

1 V

DD

Floating

1.

When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.

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ST7LITEUS2, ST7LITEUS5 I/O ports

When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming under the following conditions:

● When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

● When the signal is going to an on-chip peripheral, the I/O pin must be configured in floating input mode. In this case, the pin state is also digitally readable by addressing the DR register.

Note: 1 Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input.

2 When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.

Figure 28.

I/O port general block diagram

REGISTER

ACCESS

ALTERNATE

OUTPUT

1

0

ALTERNATE

ENABLE

DR

V

DD

P-BUFFER

(see table below)

PULL-UP

(see table below)

V

DD

DDR

PAD

PULL-UP

CONDITION

OR

If implemented

OR SEL

N-BUFFER

DIODES

(see table below)

DDR SEL

ANALOG

INPUT

DR SEL

1

CMOS

SCHMITT

TRIGGER

0

ALTERNATE

INPUT

EXTERNAL

FROM

INTERRUPT

OTHER

SOURCE (ei x

)

POLARITY

SELECTION

BITS

Obsolete Product(s) - Obsolete Product(s)

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I/O ports ST7LITEUS2, ST7LITEUS5

Table 18.

I/O port mode options

(1)

Diodes

Configuration mode Pull-up P-buffer to V

DD to V

SS

Input

Output

Floating with/without Interrupt

Pull-up with/without Interrupt

Push-pull

Open Drain (logic level)

Off

On

Off

Off

On

Off

On

1.

NI stands for not implemented; Off for implemented not activated; On for implemented and activated.

Table 19.

I/O port configurations

Hardware configuration

On

DR REGISTER ACCESS

V

DD

R

PU

PULL-UP

CONDITION

DR

REGISTER

DATA BUS

PAD

W

R

POLARITY

SELECTION

ALTERNATE INPUT

EXTERNAL INTERRUPT

SOURCE (ei x

)

ANALOG INPUT

DR REGISTER ACCESS

V

DD

R

PU

INTERRUPT

CONDITION

FROM

OTHER

PINS

PAD

DR

REGISTER

R/W

DATA BUS

V

DD

R

PU

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

DR REGISTER ACCESS

DR

REGISTER

R/W

DATA BUS

ALTERNATE

ENABLE OUTPUT

1.

When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status.

2.

When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.

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ST7LITEUS2, ST7LITEUS5 I/O ports

Caution: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin.

Warning: The analog input voltage level must be within the limits stated in the absolute maximum ratings.

9.3

9.4

Unused I/O pins

Unused I/O pins must be connected to fixed voltage levels. Refer to

Section 12.8

.

Low power modes

Table 20.

Effect of low power modes on I/O ports

Mode Description

Wait

Halt

No effect on I/O ports. External interrupts cause the device to exit from Wait mode.

No effect on I/O ports. External interrupts cause the device to exit from Halt mode.

9.5 Interrupts

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the interrupt mask in the CC register is not active

(RIM instruction).

Obsolete Product(s) - Obsolete Product(s)

Enable Exit from Exit from

Interrupt event Event flag Obsolete Product(s) - Obsolete Product(s)

External interrupt on selected DDRx

Yes Yes external event ORx

63/136

I/O ports

9.6

ST7LITEUS2, ST7LITEUS5

I/O port implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain.

Switching these I/O ports from one state to another should be done in a sequence that

prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 29 .

Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

Figure 29.

Interrupt I/O port state transitions

01 00

INPUT floating/pull-up interrupt

INPUT floating

(reset state)

10

OUTPUT open-drain

11

OUTPUT push-pull

XX = DDR, OR

The I/O port register configurations are summarized in

Table 22 .

Table 22.

Port configuration

Input (DDR=0) Output (DDR=1)

Port Pin name

OR = 0 OR = 1 OR = 0 OR = 1

Port A

PA0:2,

PA4:5

PA3 floating pull-up interrupt open drain push-pull

open drain push-pull

After reset, to configure PA3 as a general purpose output, the application has to program the MUXCR0 and MUXCR1 registers. See

Section 6.5: Register description on page 37

Table 23.

I/O port register map and reset values

Address

(Hex.)

Register label

7 6 5 4 3 2 1 0

0000h

PADR

Reset value

MSB

0 0 0 0 0 0 0

LSB

0

PADDR

MSB LSB

0001h Reset value

PAOR

0

MSB

0 0 0 1 0 0 Obsolete Product(s) - Obsolete Product(s) 0

LSB

0002h Reset

0 0 0 0 0 0 1 0 Obsolete Product(s) - Obsolete Product(s)

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ST7LITEUS2, ST7LITEUS5 On-chip peripherals

10.1 Lite timer (LT)

10.1.1 Introduction

The Lite Timer can be used for general-purpose timing functions. It is based on a freerunning 13-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watchdog function.

●

●

●

Real-time clock

– 13-bit upcounter

– 1 ms or 2 ms timebase period (@ 8 MHz f

OSC

)

– Maskable timebase interrupt

Input capture

– 8-bit input capture register (LTICR)

– Maskable interrupt with wakeup from Halt mode capability

Watchdog

– Enabled by hardware or software (configurable by option byte)

– Optional reset on HALT instruction (configurable by option byte)

– Automatically resets the device unless disable bit is refreshed

– Software reset (forced watchdog reset)

– Watchdog reset status flag

Obsolete Product(s) - Obsolete Product(s)

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On-chip peripherals ST7LITEUS2, ST7LITEUS5

Figure 30.

Lite timer block diagram f

LTIMER

To 12-bit AT TImer f

WDG f

OSC

13-bit UPCOUNTER

/2 f

LTIMER

1

0

Timebase

1 or 2 ms

(@ 8MHz f

OSC

)

WATCHDOG

WATCHDOG RESET

LTICR

8 MSB

LTIC

8-bit

INPUT CAPTURE

REGISTER

LTCSR

7

ICIE ICF TB TBIE TBF

WDG

RF

WDGE WDGD

0

LTTB INTERRUPT REQUEST

LTIC INTERRUPT REQUEST

The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of f

OSC

. A counter overflow event occurs when the counter rolls over from 1F39h to 00h. If f

OSC

= 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the

LTCSR register.

When the timer overflows, the TBF bit is set by hardware and an interrupt request is generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.

Watchdog

The watchdog is enabled using the WDGE bit. The normal watchdog timeout is 2 ms (@ fosc = 8 MHz), after which it then generates a reset.

To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is cleared by hardware after t

WDG

. This means that software must write to the WDGD bit at

regular intervals to prevent a watchdog reset occurring. Refer to Figure 31 .

Obsolete Product(s) - Obsolete Product(s) shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms period has already elapsed after the last MCU reset, the watchdog reset will take place as Obsolete Product(s) - Obsolete Product(s) immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog reset will not occur for at least 2 ms.

Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.

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ST7LITEUS2, ST7LITEUS5 On-chip peripherals

A watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the

WDGRF bit has to be set.

The WDGRF bit also acts as a flag, indicating that the watchdog was the source of the reset.

It is automatically cleared after it has been read.

Caution: When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or software), the microcontroller will be immediately reset.

Hardware watchdog option

If hardware watchdog is selected by option byte, the watchdog is always active and the

WDGE bit in the LTCSR is not used.

Refer to the option byte description in the "device configuration and ordering information" section.

Using Halt mode with the watchdog (option)

If the watchdog reset on Halt option is not selected by option byte, the Halt mode can be used when the watchdog is enabled.

In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite

Timer stops counting and is no longer able to generate a watchdog reset until the microcontroller receives an external interrupt or a reset.

If an external interrupt is received, the WDG restarts counting after 256 or 512 CPU clocks.

If a reset is generated, the watchdog is disabled (reset state).

If Halt mode with watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.

Figure 31.

Watchdog timing diagram

HARDWARE CLEARS

WDGD BIT t

WDG

(2ms @ 8 MHz f

OSC

) f

WDG

WDGD BIT

INTERNAL

WATCHDOG

RESET

SOFTWARE SETS

WDGD BIT

WATCHDOG RESET

Input capture

Obsolete Product(s) - Obsolete Product(s)

The 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and Obsolete Product(s) - Obsolete Product(s) generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.

The LTICR is a read only register and always contains the data from the last input capture.

Input capture is inhibited if the ICF bit is set.

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On-chip peripherals ST7LITEUS2, ST7LITEUS5

10.1.4 Low power modes

Table 24.

Description of low power modes

Mode Description

Wait

Active-Halt

Halt

No effect on Lite timer

No effect on Lite timer

Lite timer stops counting

10.1.5 Interrupts

Table 25.

Interrupt events

(1)

Interrupt event

Event flag

Enable control bit

Exit from

Wait

Exit from

Halt

Exit from

Active-halt

Timebase Event

IC Event

TBF

ICF

TBIE

ICIE

Yes

Yes

No

No

Yes

No

1.

The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter).

They generate an interrupt if the enable bit is set in the LTCSR register and the interrupt mask in the CC register is reset (RIM instruction).

Figure 32.

Input capture timing diagram

125 ns

(@ 8 MHz f

OSC

) f

CPU f

OSC

CLEARED

BY S/W

READING

LTIC REGISTER

13-bit COUNTER 0001h 0002h 0003h 0004h 0005h 0006h 0007h

LTIC PIN

ICF FLAG

LTICR REGISTER xxh 04h 07h t

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEUS2, ST7LITEUS5 On-chip peripherals

Lite timer control/status register (LTCSR)

Reset value: 0000 0x00 (0xh)

7

ICIE ICF TB TBIE TBF

Read / Write

WDGR WDGE

0

WDGD

Bit 7 ICIE Interrupt Enable.

This bit is set and cleared by software.

0: Input Capture (IC) interrupt disabled

1: Input Capture (IC) interrupt enabled

Bit 6 ICF Input Capture Flag.

This bit is set by hardware and cleared by software by reading the LTICR register.

Writing to this bit does not change the bit value.

0: No input capture

1: An input capture has occurred

Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register

Bit 5 TB Timebase period selection.

This bit is set and cleared by software.

0: Timebase period = t

OSC

* 8000 (1 ms @ 8 MHz)

1: Timebase period = t

OSC

* 16000 (2 ms @ 8 MHz)

Bit 4 TBIE Timebase Interrupt enable .

This bit is set and cleared by software.

0: Timebase (TB) interrupt disabled

1: Timebase (TB) interrupt enabled

Bit 3 TBF Timebase Interrupt Flag .

This bit is set by hardware and cleared by software reading the LTCSR register.

Writing to this bit has no effect.

0: No counter overflow

1: A counter overflow has occurred

Obsolete Product(s) - Obsolete Product(s)

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On-chip peripherals ST7LITEUS2, ST7LITEUS5

Bit 2 WDGRF Force Reset/ Reset Status Flag

This bit is used in two ways: it is set by software to force a watchdog reset. It is set by hardware when a watchdog reset occurs and cleared by hardware or by software. It is cleared by hardware only when an LVD reset occurs. It can be cleared by software after a read access to the LTCSR register.

0: No watchdog reset occurred.

1: Force a watchdog reset (write), or, a watchdog reset occurred (read).

Bit 1 WDGE Watchdog Enable

This bit is set and cleared by software.

0: Watchdog disabled

1: Watchdog enabled

Bit 0 WDGD Watchdog Reset Delay

This bit is set by software. It is cleared by hardware at the end of each t

WDG

period.

0: Watchdog reset not delayed

1: Watchdog reset delayed

Lite Timer Input Capture register (LTICR)

Reset value: 0000 0000 (00h)

7

ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1

0

ICR0

Read only

Table 26.

Lite timer register map and reset values

Address

(Hex.)

Register label 7 6 5

0B

0C

Bit 7:0 ICR[7:0] Input capture value

These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin.

LTCSR

Reset value

LTICR

Reset value

ICIE

0

ICR7

0

ICF

0

ICR6

0

TB

0

ICR5

0

4

TBIE

0

ICR4

0

3

TBF

0

ICR3

0

2 1

WDGRF x

ICR2

0

WDGE

0

ICR1

0

0

WDGD

0

ICR0

0

Obsolete Product(s) - Obsolete Product(s)

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ST7LITEUS2, ST7LITEUS5 On-chip peripherals

10.2 12-bit auto-reload timer (AT)

10.2.1 Introduction

The 12-bit auto-reload timer can be used for general-purpose timing functions. It is based on a free-running 12-bit upcounter with a PWM output channel.

●

●

●

●

12-bit upcounter with 12-bit auto-reload register (ATR)

Maskable overflow interrupt

PWM signal generator

Frequency range 2 kHz - 4 MHz (@ 8 MHz f

CPU

)

– Programmable duty-cycle

– Polarity control

– Maskable compare interrupt

Output compare function ●

Figure 33.

Block diagram

0

7 ATCSR

0 0

0

OVF INTERRUPT

REQUEST

CK1 CK0 OVF OVFIE CMPIE f

LTIMER

(1 ms timebase

@ 8 MHz) f

CPU

DCR0H

Preload

DCR0L

Preload on OVF Event

IF OE0=1

12-BIT DUTY CYCLE VALUE (shadow)

CMP INTERRUPT

REQUEST

CMPF0 f

COUNTER

CNTR

12-BIT UPCOUNTER

Update on OVF Event

ATR

12-BIT AUTO-RELOAD VALUE

OE0 bit

OE0 bit

CMPF0 bit

0

1

COMP-

PARE

OP0 bit f

PWM

POL-

ARITY

PWM0

Obsolete Product(s) - Obsolete Product(s)

Note:

This mode allows a pulse width modulated signals to be generated on the PWM0 output pin with minimum core processing overhead. The PWM0 output signal can be enabled or disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is configured as output push-pull alternate function.

CMPF0 is available in PWM mode (see

Section : PWM0 control/status register

(PWM0CSR) ).

71/136

On-chip peripherals ST7LITEUS2, ST7LITEUS5

PWM frequency and duty cycle

Note:

The PWM signal frequency (f

PWM value.

) is controlled by the counter period and the ATR register f

PWM

= f

COUNTER

/ (4096 - ATR)

Following the above formula, if f

CPU

is 8 MHz, the maximum value of f

PWM

is 4 MHz (ATR register value = 4094), and the minimum value is 2 kHz (ATR register value = 0).

The maximum value of ATR is 4094 because it must be lower than the DCR value which must be 4095 in this case.

At reset, the counter starts counting from 0.

Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The

DCR0H register must be written first. See caution below.

When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter, the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0 signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register must be greater than the contents of the ATR register.

The polarity bit can be used to invert the output signal.

The maximum available resolution for the PWM0 duty cycle is:

Note:

Resolution = 1 / (4096 - ATR)

To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by changing the polarity.

Caution: As soon as the DCR0H is written, the compare function is disabled and will start only when the DCR0L value is written. If the DCR0H write occurs just before the compare event, the signal on the PWM output may not be set to a low level. In this case, the DCRx register should be updated just after an OVF event. If the DCR and ATR values are close, then the

DCRx register should be updated just before an OVF event, in order not to miss a compare event and to have the right signal applied on the PWM output.

Figure 34.

PWM function

4095

DUTY CYCLE

REGISTER

(DCR0)

AUTO-RELOAD

REGISTER

Obsolete Product(s) - Obsolete Product(s)

000

WITH OE0=1

AND OP0=0 t

Obsolete Product(s) - Obsolete Product(s)

WITH OE0=1

AND OP0=1

72/136

ST7LITEUS2, ST7LITEUS5 On-chip peripherals

Figure 35.

PWM signal example f

COUNTER

COUNTER

FFDh FFEh

ATR= FFDh

FFFh FFDh

DCR0=FFEh

FFEh FFFh FFDh FFEh t

Output compare mode

To use this function, the OE bit must be 0, otherwise the compare is done with the shadow register instead of the DCRx register. Software must then write a 12-bit value in the DCR0H and DCR0L registers. This value will be loaded immediately (without waiting for an OVF event).

The DCR0H must be written first, the output compare function starts only when the DCR0L value is written.

When the 12-bit upcounter (CNTR) reaches the value stored in the DCR0H and DCR0L registers, the CMPF0 bit in the PWM0CSR register is set and an interrupt request is generated if the CMPIE bit is set.

The output compare function is only available for DCRx values other than 0 (reset value).

Note:

Caution: At each OVF event, the DCRx value is written in a shadow register, even if the DCR0L value has not yet been written (in this case, the shadow register will contain the new DCR0H value and the old DCR0L value), then:

– If OE=1 (PWM mode): the compare is done between the timer counter and the shadow register (and not DCRx)

– If OE=0 (OCMP mode): the compare is done between the timer counter and

DCRx. There is no PWM signal.

The compare between DCRx or the shadow register and the timer counter is locked until DCR0L is written.

10.2.4 Low power modes

Table 27.

Description of low power modes

Mode Description

Slow The input frequency is divided by 32

Wait

Active-halt

No effect on AT timer Obsolete Product(s) - Obsolete Product(s)

AT timer halted Halt Obsolete Product(s) - Obsolete Product(s)

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On-chip peripherals ST7LITEUS2, ST7LITEUS5

10.2.5 Interrupts

Table 28.

Interrupt events

Interrupt event

Overflow event

CMP event

(1)

Event flag

OVF

CMPFx

Enable control bit

OVFIE

CMPIE

Exit from

Wait

Yes

Yes

Exit from

Halt

No

No

Exit from

Active-halt

Yes

(2)

No

1.

The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).

They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction).

2.

Only if CK0=1 and CK1=0

Timer control status register (ATCSR)

Reset value: 0000 0000 (00h)

7

0 0 0 CK1

Read/write

CK0 OVF OVFIE

0

CMPIE

Bits 7:5 Reserved, must be kept cleared.

Bits 4:3 CK[1:0] Counter Clock Selection.

These bits are set and cleared by software and cleared by hardware after a reset.

They select the clock frequency of the counter (see Table 29: Counter clock selection

).

Bit 2 OVF Overflow flag.

This bit is set by hardware and cleared by software by reading the ATCSR register.

It indicates the transition of the counter from FFFh to ATR value.

0: No counter overflow occurred

1: Counter overflow occurred

When set, the OVF bit stays high for 1 f

COUNTER

cycle (up to 1ms depending on the clock selection) after it has been cleared by software.

Bit 1 OVFIE Overflow interrupt enable.

This bit is read/write by software and cleared by hardware after a reset.

0: OVF interrupt disabled Obsolete Product(s) - Obsolete Product(s)

Bit 0 CMPIE Compare interrupt enable .

Obsolete Product(s) - Obsolete Product(s) mask the interrupt generation when CMPF bit is set.

0: CMPF interrupt disabled

1: CMPF interrupt enabled

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ST7LITEUS2, ST7LITEUS5 On-chip peripherals

Table 29.

Counter clock selection

Counter clock selection

OFF f

LTIMER

(1 ms timebase @ 8 MHz) f

CPU

Reserved

Counter register high (CNTRH)

Reset value: 0000 0000 (00h)

15

0 0 0 0 CN11

CK1

0

0

1

1

CK0

0

1

0

1

CN10 CN9

Counter register low (CNTRL)

This 12-bit register is read by software and cleared by hardware after a reset. The counter is incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. As there is no latch, it is recommended to read LSB first. In this case, CNTRH can be incremented between the two read operations and to have an accurate result when f timer

= f

CPU

, special care must be taken when

CNTRL values close to FFh are read.

When a counter overflow occurs, the counter restarts from the value specified in the ATR register.

Reset value: 0000 0000 (00h)

Read only

7

CN7 CN6 CN5 CN4 CN3 CN2 CN1

0

CN0

Read only

8

CN8

Bits 15:12 Reserved, must be kept cleared.

Bits 11:0 CNTR[11:0] Counter value .

Auto reload register (ATRH)

Reset value: 0000 0000 (00h)

Obsolete Product(s) - Obsolete Product(s)

0 0 0 0 ATR11 ATR10 ATR9 ATR8

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On-chip peripherals ST7LITEUS2, ST7LITEUS5

Auto reload register (ATRL)

This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the

PWM frequency.

Reset value: 0000 0000 (00h)

7

ATR7 ATR6 ATR5 ATR2 ATR1

0

ATR0 ATR4

Read/Write

ATR3

Bits 15:12 Reserved, must be kept cleared.

Bits 11:0 ATR[11:0] Auto-reload Register.

PWM0 duty cycle register high (DCR0H)

Reset value: 0000 0000 (00h)

15

0 0 0 0 DCR11

Read/Write

DCR10 DCR9

8

DCR8

PWM0 duty cycle register low (DCR0L)

This 12-bit value is written by software. The high register must be written first.

In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWM0 output signal (see

Figure 34

). In Output Compare mode, (OE0=0 in the PWMCR register) they define the value to be compared with the 12-bit upcounter value.

Reset value: 0000 0000 (00h)

7

DCR7 DCR6 DCR5 DCR2 DCR1

0

DCR0 DCR4 DCR3

Read/Write

Bits 15:12 Reserved, must be kept cleared.

Bits 11:0 DCR[11:0] PWMx duty cycle value

Obsolete Product(s) - Obsolete Product(s)

76/136

ST7LITEUS2, ST7LITEUS5 On-chip peripherals

PWM0 control/status register (PWM0CSR)

Reset value: 0000 0000 (00h)

7

0 0 0 0 0

Read/Write

0 OP0

0

CMPF0

Bit 7:2 Reserved, must be kept cleared.

Bit 1 OP0 PWM0 output polarity.

This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM0 signal.

0: The PWM0 signal is not inverted.

1: The PWM0 signal is inverted.

Bit 0 CMPF0 PWM0 Compare Flag.

This bit is set by hardware and cleared by software by reading the PWM0CSR register. It indicates that the upcounter value matches the DCR0 register value.

0: Upcounter value does not match DCR value.

1: Upcounter value matches DCR value.

PWM output control register (PWMCR)

Reset value: 0000 0000 (00h)

7

0 0 0 0 0 0 0

0

OE0

Read/Write

Bits 7:1 Reserved, must be kept cleared.

Bit 0 OE0 PWM0 Output enable .

This bit is set and cleared by software.

0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O)

1: PWM0 output enabled

Table 30.

Register map and reset values

Address

(Hex.)

Register label

7 6 5

ATCSR

Reset value

0 0 0

4

CK1

0

3 2 1 0

0F

10

Reset value

CNTRL

Reset value

ATRH

Reset value

0

CN7

0

0

0

CN6

0

0

0

CN5

0

0

0

CN4

0

0

CK0

0

CN11

0

CN3

0

ATR11

0

OVF

0

CN10

0

CN2

0

ATR10

0

OVFIE

0

CN9

0

CN1

0

ATR9

0

CMPIE

0

CN8

0

CN0

0

ATR8

0

77/136

On-chip peripherals ST7LITEUS2, ST7LITEUS5

Table 30.

Register map and reset values (continued)

Address

(Hex.)

Register label

7 6 5 4 3

11

12

13

17

18

ATRL

Reset value

PWMCR

Reset value

PWM0CSR

Reset value

DCR0H

Reset value

DCR0L

Reset value

ATR7

0

0

0

0

DCR7

0

ATR6

0

0

0

0

DCR6

0

ATR5

0

0

0

0

DCR5

0

ATR4

0

0

0

0

DCR4

0

ATR3

0

0

0

2

ATR2

0

0

0

DCR11

0

DCR10

0

DCR3

0

DCR2

0

1 0

ATR1

0

0

OP

0

DCR9

0

DCR1

0

ATR0

0

OE0

0

CMPF0

0

DCR8

0

DCR0

0

Obsolete Product(s) - Obsolete Product(s)

78/136

ST7LITEUS2, ST7LITEUS5 On-chip peripherals

10.3 10-bit A/D converter (ADC)

10.3.1 Introduction

The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources.

The result of the conversion is stored in a 10-bit Data register. The A/D converter is controlled through a Control/Status register.

●

●

●

●

●

●

10-bit conversion

Up to 5 channels with multiplexed input

Linear successive approximation

Data register (DR) which contains the results

Conversion complete status flag

On/off bit (to reduce consumption)

The block diagram is shown in

Figure 36 .

Analog power supply

V

DDA

and V

SSA

are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the V

DD

and V

SS

pins.

Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines.

Obsolete Product(s) - Obsolete Product(s)

79/136

On-chip peripherals ST7LITEUS2, ST7LITEUS5

Figure 36.

ADC block diagram

DIV 4 f

CPU

DIV 2

0

1 f

ADC

EOC SPEED ADON 0 0 CH2 CH1 CH0 ADCCSR

3

1

0

SLOW bit

AIN0

AIN1

R

ADC

HOLD CONTROL

ANALOG

MUX

ANALOG TO DIGITAL

CONVERTER

AINx C

ADC

ADCDRH D9 D8 D7 D6 D5 D4 D3 D2

ADCDRL

0 0 0 0 SLOW 0 D1 D0

Digital A/D conversion result

The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not.

If the input voltage (V

AIN

) is greater than V

DDA

(high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).

If the input voltage (V

AIN

) is lower than V

SSA

(low-level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h.

The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical

Characteristics Section.

R

AIN

is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.

The A/D conversion is based on two conversion phases:

Obsolete Product(s) - Obsolete Product(s)

During this phase, the V

AIN

input voltage to be measured is loaded into the C

ADC sample capacitor.

● A/D conversion [duration: t

HOLD

]

During this phase, the A/D conversion is computed (8 successive approximations

80/136

ST7LITEUS2, ST7LITEUS5 On-chip peripherals

● cycles) and the C

ADC

sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy.

The total conversion time: t

CONV = t

SAMPLE

+ t

HOLD

While the ADC is on, these two phases are continuously repeated.

At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behavior is that it minimizes the current consumption on the analog pin in case of single input channel measurement.

A/D conversion

The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the “I/O ports” chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input.

In the ADCCSR register, select the CS[2:0] bits to assign the analog channel to convert.

ADC conversion mode

●

●

In the ADCCSR register, set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete:

The EOC bit is set by hardware.

The result is in the ADCDR registers.

A read to the ADCDRH resets the EOC bit.

To read the 10 bits, perform the following steps:

1.

Poll EOC bit

3. Read ADCDRH. This clears EOC automatically.

To read only 8 bits, perform the following steps:

1.

Poll EOC bit

1.

Read ADCDRH. This clears EOC automatically.

10.3.4 Low power modes

The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions.

Table 31.

Effect of low power modes

Obsolete Product(s) - Obsolete Product(s)

Wait No effect on A/D converter Obsolete Product(s) - Obsolete Product(s)

After wakeup from Halt mode, the A/D converter requires a stabilization time

Halt t

STAB

(see

Section 12: Electrical characteristics ) before accurate conversions

can be performed.

81/136

On-chip peripherals

10.3.5 Interrupts

None.

ST7LITEUS2, ST7LITEUS5

Note:

Control/Status register (ADCCSR)

Reset value: 0000 0000 (00h)

7

EOC SPEED ADON 0 0

Read/Write (Except bit 7 read only)

CH2 CH1

0

CH0

Bit 7 EOC End of Conversion

This bit is set by hardware. It is cleared by software reading the ADCDRH register.

0: Conversion is not complete

1: Conversion complete

Bit 6 SPEED ADC clock selection

This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit description.

Bit 5 ADON A/D Converter on

This bit is set and cleared by software.

0: A/D converter is switched off

1: A/D converter is switched on

Bits 4:3 Reserved. Must be kept cleared.

Bits 2:0 CH[2:0] Channel Selection

These bits are set and cleared by software. They select the analog input to convert.

A write to the ADCCSR register (with ADON set) aborts the current conversion, resets the

EOC bit and starts a new conversion.

Table 32.

Channel selection

Channel pin

AIN0

AIN1

AIN2

AIN4

0

0

0

0

1

CH2

0

0

1

1

0

CH1

0

1

0

1

0

CH0

82/136

ST7LITEUS2, ST7LITEUS5 On-chip peripherals

ADC data register high (ADCDRH)

Reset value: 0000 0000 (00h)

7

D9 D8 D7 D6 D5 D4 D3

0

D2

Read only

Bits 7:0 D[9:2] MSB of Analog Converted value

ADC control/data register Low (ADCDRL)

Reset value: 0000 0000 (00h)

7

0 0 0 0

Read/write

SLOW 0 D1

0

D0

Bits 7:4 Reserved. Forced by hardware to 0.

Bit 3 SLOW Slow mode

This bit is set and cleared by software. It is used together with the SPEED bit to configure the ADC clock speed as shown on the table below (see

Table 33:

Configuring the ADC clock speed

).

Bit 2 Reserved. Forced by hardware to 0.

Bits 1:0 D[1:0] LSB of Analog Converted value

Table 33.

Configuring the ADC clock speed f

ADC

f

CPU

/2

f

CPU

f

CPU

/4

Table 34.

ADC register map and reset values

Address

(Hex.)

Register label

7 6 5 4

0036h

ADCCSR

Reset value

ADCDRH

Reset value

ADCDRL

Reset value

EOC

0

D9

0

0

0

SPEED

0

D8

0

0

0

ADON

0

D7

0

0

0

0

0

D6

0

0

0

3

0

0

D5

0

SLOW

0

0

0

1

SLOW

2

CH2

0

D4

0

0

0

0

1 x

1

CH1

0

D3

0

D1

0

SPEED

0

CH0

0

D2

0

D0

0

83/136

Instruction set ST7LITEUS2, ST7LITEUS5

11.1 ST7 addressing modes

The ST7 Core features 17 different addressing modes which can be classified in seven main groups:

Table 35.

Description of addressing modes

Addressing mode

Inherent

Immediate

Direct

Indexed

Indirect

Relative

Bit operation

Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5

The ST7 instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two submodes called long and short:

● Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles.

● Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG,

BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and short addressing modes.

Table 36.

ST7 addressing mode overview

(1)

Mode Syntax

Destination/ source

Pointer address

Pointer size

Length

(bytes)

Inherent

Immediate nop ld A,#$55

+ 0

+ 1

Short Direct

Direct ld A,$10 ld A,$1000

00..FF

0000..FFFF

+ 1

+ 2

No Offset Direct Indexed ld A,(X) 00..FF

+ 0 (with X register)

+ 1 (with Y register) Obsolete Product(s) - Obsolete Product(s)

Short Direct Indexed ld A,($10,X) 00..1FE

+ 1

Long Direct Indexed ld A,($1000,X) 0000..FFFF

+ 2

Short

Long

Short

Indirect

Indirect ld A,[$10] ld A,[$10.w]

Indirect Indexed ld A,([$10],X)

00..FF

0000..FFFF

00..1FE

00..FF

00..FF

00..FF

byte word byte

+ 2

+ 2

+ 2

84/136

ST7LITEUS2, ST7LITEUS5 Instruction set

Table 36.

ST7 addressing mode overview (continued)

(1)

Long

Relative

Relative

Bit

Bit

Mode Syntax

Destination/ source

Indirect Indexed ld A,([$10.w],X) 0000..FFFF

Direct jrne loop PC-128/PC+127

1)

Indirect jrne [$10] PC-128/PC+127

1)

Direct

Indirect bset $10,#7 bset [$10],#7

00..FF

00..FF

Bit

Bit

Direct

Indirect

Relative btjt $10,#7,skip 00..FF

Relative btjt

[$10],#7,skip

00..FF

Pointer address

Pointer size

00..FF

word + 2

+ 1

00..FF

byte

00..FF

byte

+ 2

+ 1

+ 2

+ 2

00..FF

byte + 3

1.

At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.

Length

(bytes)

All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.

Table 37.

Instructions supporting inherent addressing mode

Inherent instruction Function

NOP

TRAP

WFI

HALT

RET

IRET

SIM

RIM

SCF

RCF

No operation

S/W Interrupt

Wait For Interrupt (low power mode)

Halt Oscillator (lowest power mode)

Subroutine return

Interrupt subroutine return

Set interrupt mask

Reset interrupt mask

Set carry flag

Reset carry flag

RSP Reset stack pointer

LD Load

CLR Clear Obsolete Product(s) - Obsolete Product(s)

PUSH/POP Push/Pop to/from the stack

Obsolete Product(s) - Obsolete Product(s)

TNZ Test Negative or Zero

CPL, NEG

MUL

SLL, SRL, SRA, RLC, RRC

SWAP

1 or 2 complement

Byte multiplication

Shift and rotate operations

Swap nibbles

85/136

Instruction set ST7LITEUS2, ST7LITEUS5

11.1.2 Immediate

Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value.

Table 38.

Instructions supporting inherent immediate addressing mode

Immediate instruction Function

LD

CP

BCP

AND, OR, XOR

ADC, ADD, SUB, SBC

Load

Compare

Bit compare

Logical operations

Arithmetic operations

11.1.3 Direct

In Direct instructions, the operands are referenced by their memory address.

The direct addressing mode consists of two submodes:

Direct (short) addressing mode

the address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF addressing space.

Direct (long) addressing mode

The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three submodes:

Indexed mode (no offset)

There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.

Indexed mode (short)

addressing space.

The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.

86/136

ST7LITEUS2, ST7LITEUS5 Instruction set

11.1.5 Indirect modes (short, long)

The required data byte to do the operation is found by its memory address, located in memory (pointer).

The pointer address follows the opcode. The indirect addressing mode consists of two submodes:

Indirect mode (short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.

Indirect mode (long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

11.1.6 Indirect indexed modes (short, long)

This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.

The indirect indexed addressing mode consists of two submodes:

Indirect indexed mode (short)

The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.

Indirect indexed mode (long)

The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.

Table 39.

Instructions supporting direct, indexed, indirect and indirect indexed addressing modes

Instructions Function

Long and short instructions

LD

CP

Load

Compare

Logical operations

ADC, ADD, SUB, SBC

BCP

Arithmetic addition/subtraction operations

Obsolete Product(s) - Obsolete Product(s)

Short instructions only

CLR

INC, DEC

TNZ

Clear

Increment/decrement

Test negative or zero

87/136

Instruction set ST7LITEUS2, ST7LITEUS5

Table 39.

Instructions supporting direct, indexed, indirect and indirect indexed addressing modes (continued)

Instructions Function

CPL, NEG

BSET, BRES

BTJT, BTJF

SLL, SRL, SRA, RLC, RRC

SWAP

CALL, JP

1 or 2 complement

Bit operations

Bit test and jump operations

Shift and rotate operations

Swap nibbles

Call or jump subroutine

11.1.7 Relative modes (direct, indirect)

This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.

Table 40.

Instructions supporting relative modes

Available relative direct/indirect instructions

JRxx

CALLR

The relative addressing mode consists of two submodes:

Function

Conditional jump

Call relative

Relative mode (Direct)

The offset follows the opcode.

Relative mode (Indirect)

The offset is defined in memory, of which the address follows the opcode.

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table:

Table 41.

ST7 instruction set

Load and Transfer

Stack operation

LD

PUSH

CLR Obsolete Product(s) - Obsolete Product(s)

Increment/Decrement

Compare and tests

INC

CP

DEC

TNZ BCP

Logical operations AND OR XOR CPL NEG

Bit operation BSET BRES

Conditional bit test and branch

Arithmetic operations

BTJT BTJF

ADC ADD SUB SBC MUL

88/136

ST7LITEUS2, ST7LITEUS5 Instruction set

Table 41.

ST7 instruction set (continued)

Shift and rotates

Unconditional jump or call

Conditional branch

Interruption management

Condition code flag modification

SLL

JRA

SRL

JRT

SRA RLC RRC SWAP SLA

JRF JP CALL CALLR NOP RET

JRxx

TRAP WFI HALT IRET

SIM RIM SCF RCF

Using a prebyte

The instructions are described with 1 to 4 bytes.

In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1 Prebyte

PC Opcode

PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address

These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:

PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one.

PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode.

It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.

PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, combined with the watchdog, allows the detection and recovery from an unexpected fault or interference.

A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset.

Table 42.

Obsolete Product(s) - Obsolete Product(s)

Mnemo Description Function/example Dst Src H I N Z C

ADC

ADD

AND

BCP

Add with carry

Addition

Logical and

Bit compare A, Memory

A = A + M + C

A = A + M

A = A . M tst (A . M)

A

A

A

A

M

M

M

M

H

H

-

-

-

-

-

-

N

N

N

N

Z

Z

Z

Z

C

C

-

-

89/136

Instruction set

Table 42.

Illegal opcode detection (continued)

Mnemo Description Function/example

CP

CPL

DEC

HALT

IRET

INC

JP

JRA

BRES

BSET

BTJF

Bit Reset

Bit Set

Jump if bit is false (0)

BTJT

CALL

Jump if bit is true (1)

Call subroutine

CALLR Call subroutine relative

CLR Clear

Arithmetic compare

One Complement

Decrement

Halt

Interrupt routine return

Increment

Absolute jump

Jump relative always

JRT

JRF

JRIH

JRIL

JRH

JRNH

Jump relative

Never jump

Jump if ext. interrupt = 1

Jump if ext. interrupt = 0

Jump if H = 1

Jump if H = 0

JRM

JRNM

JRMI

Jump if I = 1

Jump if I = 0

Jump if N = 1 (minus)

JRPL

JREQ

Jump if N = 0 (plus)

Jump if Z = 1 (equal)

JRNE Jump if Z = 0 (not equal)

JRNC

Jump if C = 1

Jump if C = 0 bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 tst(Reg - M)

A = FFH-A dec Y

Pop CC, A, X, PC inc X jp [TBL.w] jrf *

H = 1 ?

H = 0 ?

I = 1 ?

I = 0 ?

N = 1 ?

N = 0 ?

Z = 1 ?

Z = 0 ?

C = 1 ?

C = 0 ?

Dst

-

-

-

-

-

-

-

-

-

-

-

-

-

reg reg, M reg, M

-

reg, M

-

-

M

M

M

M

-

reg, M

Src

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

M

-

-

-

-

-

-

-

-

-

-

-

-

JRUGE

JRUGT

JRULE

LD

MUL

Jump if C = 0

Jump if (C + Z = 0)

Jump if (C + Z = 1)

Load

Multiply

ST7LITEUS2, ST7LITEUS5

N

-

-

-

-

-

-

-

-

-

-

-

-

-

-

N

-

N

N

N

N

-

-

-

0

-

-

-

-

-

I

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

0

-

-

I

-

-

-

-

-

-

-

-

-

-

H

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

H

-

-

-

-

-

-

-

-

-

-

C

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

C

1

C

-

-

-

-

-

C

-

-

-

C

Z

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Z

-

Z

Z

Z

Z

-

-

-

1

-

-

-

-

-

Jmp if unsigned

≥

Unsigned >

Unsigned

≤ dst

≤ src

X,A = X * A

-

-

-

-

-

reg, M M, reg

A, X, Y X, Y, A

-

0

-

-

-

-

-

-

-

-

N

-

-

-

-

Z

-

-

-

-

-

0

-

-

-

90/136

ST7LITEUS2, ST7LITEUS5

Table 42.

Illegal opcode detection (continued)

Mnemo

NEG

NOP

OR

POP

SLA

SLL

SRL

SRA

SUB

SWAP

TNZ

TRAP

WFI

XOR

PUSH

RCF

RET

RIM

RLC

RRC

RSP

SBC

SCF

SIM

Description

Negate (2's compl)

No operation

OR operation

Pop from the stack

Push onto the stack

Reset carry flag

Subroutine return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Subtract with carry

Set carry flag

Disable interrupts

Shift left arithmetic

Shift left logic

Shift right logic

Shift right arithmetic

Subtraction

SWAP nibbles

Test for Neg & Zero

S/W trap

Wait for interrupt

Exclusive OR

Function/example Dst neg $10

A = A + M pop reg pop CC push Y

C = 0

I = 0

C

≤

Dst

≤

C

C

≥

Dst

≥

C

S = Max allowed

-

reg, M reg, M

-

A = A - M - C

C = 1

A

-

I = 1

C

≤

Dst

≤

0

C

≤

Dst

≤

0

0

≥

Dst

≥

C

Dst7

≥

Dst

≥

C

reg, M reg, M reg, M reg, M

A = A - M A

Dst[7..4]

≤ ≥

Dst[3..0] reg, M tnz lbl1 -

S/W interrupt -

A = A XOR M

-

A reg, M

-

A reg

CC

M

-

Src

-

-

-

-

-

M

-

-

-

-

M

M

M reg, CC

-

-

M

-

-

-

-

M

-

-

-

H

-

-

-

-

-

-

-

-

-

-

-

H

-

-

-

-

-

-

-

-

-

-

-

-

-

Instruction set

I

-

-

-

0

-

-

-

1

-

-

-

I

-

-

-

-

-

-

-

1

0

-

-

-

-

-

N

N

N

N

-

-

-

N

-

-

-

-

-

N

N

-

N

N

N

N

N

N

N

0

C

C

C

-

-

-

C

1

-

-

0

-

C

C

-

-

C

C

-

-

-

-

-

C

C

C

Z

Z

Z

-

-

-

Z

-

-

-

-

-

Z

Z

-

Z

Z

Z

Z

Z

-

-

Z

Z

Z

Z

Obsolete Product(s) - Obsolete Product(s)

91/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

Unless otherwise specified, all voltages are referred to V

SS

.

12.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A

=25 °C and T

A

=T

A max (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3

Σ

).

Unless otherwise specified, typical data are based on T

A

=25 °C, V

DD

4.5 V

V

DD

≤

V

DD

≤

5.5 V voltage range), V

DD

=2.7 V (for the 2.4 V

≤

V

DD

=3.75 V (for the 3 V

≤

V

DD

=5 V (for the

≤

4.5 V voltage range) and

≤

3 V voltage range). They are given only as design guidelines and are not tested.

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

The loading conditions used for pin parameter measurement are shown in Figure 37 .

Figure 37.

Pin loading conditions

ST7 PIN

C

L

Obsolete Product(s) - Obsolete Product(s)

92/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

12.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 38

.

Figure 38.

Pin input voltage

ST7 PIN

V

IN

12.2 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

1. Directly connecting the I/O pins to V

DD

or V

SS could damage the device if an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10 k

Ω

for I/Os). Unused I/O pins must be tied in the same way to V

DD

or

V

SS

according to their reset configuration.

Table 43.

Voltage characteristics

Symbol Ratings Maximum value Unit

V

V

V

DD

- V

V

IN

SS

ESD(HBM)

ESD(MM)

Supply voltage

Input voltage on any pin

(1)

Electrostatic discharge voltage (Human Body

Model)

Electrostatic discharge voltage (Machine

Model)

V

SS

7.0

-0.3 to V

DD

+0.3

see see

Section 12.7.2

Section 12.7.2

V

1.

I

INJ(PIN)

must never be exceeded. This is implicitly insured if V

IN

maximum is respected. If V cannot be respected, the injection current must be limited externally to the I

INJ(PIN) injection is induced by V

IN

>V

DD

while a negative injection is induced by V

IN

<V

SS

.

IN

maximum

value. A positive

Obsolete Product(s) - Obsolete Product(s)

93/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

Table 44.

Current characteristics

Symbol

I

VDD

I

VSS

I

IO

Ratings

Total current into V

DD

power lines (source)

(1)

Total current out of V

SS

ground lines (sink)

(1)

Output current sunk by any standard I/O and control pin

Output current sunk by any high sink I/O pin

Output current source by any I/Os and control pin

I

INJ(PIN)

(2)(3)

Σ

I

INJ(PIN)

(2)

Injected current on RESET pin

Injected current on any other pin

(4)

Total injected current (sum of all I/O and control pins)

(4)

Maximum value

75

150

20

40

-25

± 5

± 5

± 20

Unit mA

1.

All power (V

DD

) and ground (V

SS

) lines must always be connected to the external supply.

2.

I

INJ(PIN)

must never be exceeded. This is implicitly insured if V

IN

maximum is respected. If V cannot be respected, the injection current must be limited externally to the I

INJ(PIN) injection is induced by V

IN

>V

DD

while a negative injection is induced by V

IN

<V

SS

.

IN

maximum

value. A positive

3.

Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:

- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits)

- Pure digital pins must have a negative injection less than 1.6 mA. In addition, it is recommended to inject the current as far as possible from the analog input pins.

4.

When several inputs are submitted to a current injection, the maximum positive and negative injected currents (instantaneous values). These results are based on characterisation with

Σ

I

INJ(PIN)

Σ

I

INJ(PIN)

is the absolute sum of the

maximum current injection on four I/O port pins of the device.

Table 45.

Thermal characteristics

Symbol Ratings value Unit

T

STG

T

J

Storage temperature range -65 to +150

Maximum junction temperature (see Section 13: Package characteristics

)

°C

12.3.1 General operating conditions

T

A

= -40 to +125 °C unless otherwise specified.

Obsolete Product(s) - Obsolete Product(s)

Table 46.

General operating conditions

Obsolete Product(s) - Obsolete Product(s) f

CPU

= 4 MHz max.

2.4

5.5

V

DD

Supply voltage V f

CPU

= 8 MHz max.

3.3

5.5

f

CPU

CPU clock frequency

3.3 V

≤

V

DD

≤

5.5 V

2.4 V

≤

V

DD

<

3.3 V up to 8 up to 4

MHz

94/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

Figure 39.

f

CPU

maximum operating frequency versus V

DD supply voltage f

CPU

[MHz]

8

FUNCTIONALITY

GUARANTEED

IN THIS AREA

(UNLESS OTHERWISE

STATED IN THE

TABLES OF

PARAMETRIC DATA)

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

4

2

0

2.0

2.4

2.7

3.3

3.5

4.0

4.5

5.0

5.5

SUPPLY VOLTAGE [V]

T

A

= -40 to 125 °C, unless otherwise specified

Table 47.

Operating characteristics with LVD

Symbol Parameter Conditions

V

IT+ (LVD)

V

IT(LVD)

Reset release threshold

(V

DD

rise)

Reset generation threshold

(V

DD

fall)

High threshold

Med. threshold

Low threshold

High threshold

Med. threshold

Low threshold

V hys

V tPOR

LVD voltage threshold hysteresis

V

DD

rise time rate

(1)(2)

I

DD(LVD)

(3)

LVD/AVD current consumption

V

IT+ (LVD)

-V

IT(LVD)

V

DD

= 5 V

Min Typ Max Unit

3.9

3.2

2.5

3.7

3.0

2.4

4.2

3.5

2.7

4.0

3.3

2.6

4.5

3.8

3.0

4.3

3.6

2.9

V

20

150

220

1.

Not tested in production. The V release. When the V

DD

DD

rise time rate condition is needed to ensure a correct device power-on and LVD reset

slope is outside these values, the LVD may not release properly the reset of the MCU

2.

Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull V

DD

page 114 .

down to 0V to ensure optimum restart conditions. Refer to circuit example in

Figure 61 on

3.

Not tested in production.

mV

μ s/V

μ

A

Obsolete Product(s) - Obsolete Product(s)

95/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

12.3.3 Auxiliary voltage detector (AVD) thresholds

T

A

=

−

40 to 125°C, unless otherwise specified.

Table 48.

Operating characteristics with AVD

(1)

Symbol Parameter Conditions

Min

(2)

Typ

(2)

Max

(2)

Unit

V

IT+ (AVD)

1 => 0 AVDF flag toggle threshold

(V

DD

rise)

High threshold

Med. threshold

Low threshold

4.0

3.4

2.6

4.4

3.7

2.9

4.8

4.1

3.2

V

V

IT(AVD)

0 => 1 AVDF flag toggle threshold

(V

DD

fall)

High threshold

Med. threshold

Low threshold

V hys

AVD voltage threshold hysteresis V

IT+ (AVD)

-V

IT(AVD)

1.

Refer to Section : Monitoring the VDD main supply

.

2.

Not tested in production, guaranteed by characterization.

3.9

3.3

2.5

4.3

3.6

2.8

150

Table 49.

Voltage drop between AVD flag set and LVD reset generation

Parameter Min

(1)

Typ

(1)

Max

(1)

4.7

4.0

3.1

mV

Unit

AVD med. threshold - AVD low. threshold

AVD high. threshold - AVD low threshold

AVD high. threshold - AVD med. threshold

AVD low threshold - LVD low threshold

AVD med. threshold - LVD low threshold

AVD med. threshold - LVD med. threshold

AVD high. threshold - LVD low threshold

AVD high. threshold - LVD med. threshold

1.

Not tested in production, guaranteed by characterization.

800

1400

600

100

950

250

1600

900

850

1450

650

200

1050

300

1700

1000

950

1550

750

250

1150

400

1800

1050 mV

To improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100 nF, between the V

DD device.

and V

SS

pins as close as possible to the ST7

Internal RC oscillator calibrated at 5.0 V

Obsolete Product(s) - Obsolete Product(s) byte).

Obsolete Product(s) - Obsolete Product(s)

96/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

Table 50.

Internal RC oscillator characteristics (5.0 V calibration)

Symbol Parameter Conditions f

RC

ACC

RC

Internal RC oscillator frequency

Accuracy of internal RC oscillator with

RCCR=RCCR0

(1)

RCCR = FF (reset value),

T

A

= 25 °C, V

DD

= 5 V

RCCR = RCCR0

(1)

, T

A

= 25 °C, V

DD

= 5 V

T

A

= 25 °C, V

DD

= 4.5 to 5.5 V

(2)

T

A

= 0 to +85 °C,

V

DD

= 4.5 to 5.5 V

(2)

T

A

= 0 to +125 °C,

V

DD

= 4.5 to 5.5 V

(2)

T

A

= -40 °C to 0 °C,

V

DD

= 4.5 to 5.5 V

(2)

T

A

= 25°C, V

DD

= 5 V t su(RC)

RC oscillator setup time

1.

See

Section 6.2: Internal RC oscillator adjustment

2.

Tested in production at 5.0 V only

Min

-2.0

-2.5

-3.0

-4.0

Typ

4.4

8

4

(2)

Max Unit

MHz

+2.0

%

+4.0

%

+5.0

%

+2.5

%

μ s

Internal RC oscillator calibrated at 3.3 V

The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte).

Table 51.

Internal RC oscillator characteristics (3.3 V calibration)

Symbol Parameter Conditions f

RC

ACC

RC

Accuracy of internal RC oscillator with

RCCR=RCCR1

(1) t su(RC)

Internal RC oscillator frequency

RC oscillator setup time

Min

RCCR = FF (reset value),

T

A

=25 °C,V

DD

= 3.3 V

RCCR = RCCR1

(1)

,

T

A

=25 °C,V

DD

= 3.3 V

T

A

=25°C, V

DD

= 3.0 to 3.6 V

(2)

T

A

=0 to +85 °C, V

DD

= 3.0 to 3.6 V

(2)

T

A

=0 to +125 °C, V

DD

= 3.0 to 3.6 V

(2)

T

A

= -40 °C to 0 °C,

V

DD

= 3.0 to 3.6 V

(2)

T

A

= 25 °C, V

DD

= 3.3 V

-1.0

-2.5

-3.0

-4.0

Typ

4.3

8

4

(2)

Max Unit

MHz

+1.0

%

+4.0

%

+5.0

%

+2.5

%

μ s

97/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

Figure 40.

Typical accuracy with RCCR=RCCR0 vs V

DD

= 2.4-6.0 V and temperature

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

-1.8

-2.0

-2.2

RC5V@-45C

RC5V@25C

RC5V@90C

RC5V@130C

RC5V@0C

Figure 41.

Typical accuracy with RCCR=RCCR1 vs V

DD

= 2.4-6.0V and temperature

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

3.0

2.8

2.6

2.4

2.2

2.0

1.8

RC3.3V@-45C

RC3.3V@25C

RC3.3V@90C

RC3.3V@130C

RC3.3V@0C

Obsolete Product(s) - Obsolete Product(s)

98/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

12.4 Supply current characteristics

The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for Halt mode

for which the clock is stopped). Refer to Section 12.4.2: Internal RC oscillator supply current characteristics .

T

A

= -40 to +125 °C unless otherwise specified.

Table 52.

Supply current characteristics

Symbol Parameter Conditions

Supply current in Run mode

(1)

Supply current in Wait mode

(3)

Supply current in Wait mode

(4)

Supply current in Slow-Wait mode

(5)

Supply current in AWUFH mode

(6)(7)

Supply current in Active-halt mode f

CPU

= 4 MHz f

CPU

= 8 MHz f

CPU

= 4 MHz f

CPU

= 8 MHz f

CPU

/32 = 250 kHz f

CPU

/32 = 250 kHz

Typ Max Unit

4.5

(2)

2.5

5.0

7.5

0.85

2.0

(2)

mA

1.2

600

450

45

100

3.5

950

750

100

(2)

250

μ

A

0.5

3.0

I

DD

Supply current in Halt mode

(8)

Supply current in Run mode

(1)

Supply current in Wait mode

(3)

Supply current in Slow mode

(4)

Supply current in Slow-wait mode

(5)

Supply current in AWUFH mode

(6)(7)

Supply current in Active-halt mode

T

A

= 85 °C

T

A

= 125 °C f

CPU

= 4 MHz f

CPU

= 4 MHz f

CPU

/32 = 250 kHz f

CPU

/32 = 250 kHz

0.5

5.0

1.30

2.0

(2)

0.36

0.5

(2)

300 400

(2)

250 350

(2)

20

90

50

(2)

150

(2)

0.25

2.5

(2)

0.25

4.5

(2)

mA

μ

A

Supply current in Halt mode

(8)

T

A

= 85 °C

T

A

= 125 °C

1.

CPU running with memory access, all I/O pins in input mode with a static value at V

DD reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

or V

SS

(no load), all peripherals in

Obsolete Product(s) - Obsolete Product(s)

3.

All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) Obsolete Product(s) - Obsolete Product(s)

4.

All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

5.

Slow-Wait mode selected with fCPU based on f

OSC

V

SS

divided by 32. All I/O pins in input mode with a static value at V

(no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

DD

or

6.

All I/O pins in input mode with a static value at V

DD

or V

SS

(no load). Data tested in production at V

DD

max. and f

CPU

max.

7.

This consumption refers to the Halt period only and not the associated run period which is software dependent.

8.

All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results, tested in production at V

DD

max and f

CPU

max.

99/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

Table 53.

Internal RC oscillator supply current

Symbol Parameter Conditions Min Typ Max

(1)

Unit

I

DD

Supply current in Run mode

Supply current in Wait mode

(2)

(3)

T

A

=25 °C, int RC = 4 MHz

T

A

=25 °C, int RC = 8 MHz

T

A

=25 °C, AWU RC

T

A

=25 °C, int RC = 4 MHz

T

A

=25 °C, int RC = 8 MHz

T

A

=25 °C, int RC/32 = 250 kHz

3.2

5.7

0.13

1.5

1.9

1.3

5.5

8.5

0.2

3.0

4.5

2.0

mA

Supply current in Slow mode

(4)

Supply current in Slow-Wait mode

(5)

Supply current in Active-halt mode

T

A

=25 °C, int RC/32 = 250 kHz 1.1

0.8

1.8

1.25

I

DD

Supply current in Run mode

Supply current in Wait mode

(2)

(3)

T

A

=25 °C, int RC = 4 MHz

T

A

=25 °C, int RC = 2 MHz

T

A

=25 °C, AWU RC

T

A

=25 °C, int RC = 4 MHz

T

A

=25 °C, int RC = 2 MHz

T

A

=25 °C, int RC/32 = 250 kHz

2.0

1.3

0.1

1.0

0.9

0.95

3.0

2.0

0.18

1.6

1.5

1.5

mA

Supply current in Slow mode

(4)

Supply current in Slow-Wait mode

(5)

Supply current in Active-halt mode

T

A

=25 °C, int RC/32 = 250 kHz 0.85

0.8

1.4

1.3

1.

Data based on characterization results, not tested in production.

2.

CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.

3.

All I/O pins in input mode with a static value at V

DD the internal RC, LVD disabled.

or V

SS

(no load), all peripherals in reset state; CPU clock provided by

4.

Slow mode selected with f

CPU

based on f

OSC

divided by 32. All I/O pins in input mode with a static value at V

DD load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.

or V

SS

(no

5.

Slow-Wait mode selected with f

CPU

based on f

OSC

divided by 32. All I/O pins in input mode with a static value at V

(no load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.

DD

or V

SS

Obsolete Product(s) - Obsolete Product(s)

100/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

Figure 42.

Typical I

DD

in run mode vs. internal clock frequency and V

DD

Idd RUN mode @amb vs int clock freq

RC 8 MHz

RC 4 MHz

RC 2 MHz

AWU

6.00

5.00

4.00

3.00

2.00

1.00

0.00

VDD [V]

Figure 43.

Typical I

DD

in WFI mode vs. internal clock frequency and V

DD

Idd WFI mode @amb vs int RC freq

2.200

8 MHz

4 MHz

2 MHz

1.700

1.200

0.700

VDD [V]

Figure 44.

Typical I

DD

in Slow, Slow-wait and Active-halt mode vs V

DD

& int

RC = 8 MHz

Idd slow, slowwait & acthalt mode, int Rc 8Mhz@amb

1.500

1.300

Slow slowwait acthlt

1.100

Obsolete Product(s) - Obsolete Product(s)

0.700

Obsolete Product(s) - Obsolete Product(s)

VDD [V]

101/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

Figure 45.

I

DD

vs temp @V

DD

5 V & int RC = 8 MHz

6.0

5.0

4.0

3.0

2.0

1.0

0.0

run wfi slow slowwait acthlt

Temp [°C]

Figure 46.

I

DD

vs temp @V

DD

5 V & int RC = 4 MHz

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

run wfi

Figure 47.

I

DD

vs temp @V

DD

5 V & int RC = 2 MHz

3.0

2.5

2.0

1.5

1.0

run wfi

0.5

0.0

Obsolete Product(s) - Obsolete Product(s)

Temp [°C] Obsolete Product(s) - Obsolete Product(s)

102/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

Table 54.

On-chip peripheral characteristics

Symbol Parameter Conditions Typ

(1)

Unit

I

I

DD(AT)

DD(ADC)

12-bit auto-reload timer supply current

ADC supply current when converting

(2)

(3) f

CPU

= 4 MHz V

DD

=

3.0 V f

CPU

= 8 MHz V

DD

=

5.0 V f

ADC

= 2 MHz V

DD

=

3.0 V f

ADC

= 4 MHz V

DD

=

5.0 V

15

30

450

750

μ

1.

Not tested in production, guaranteed by characterization.

2.

Data based on a differential I

DD mode at f cpu

= 8 MHz.

measurement between reset configuration (timer stopped) and the timer running in PWM

3.

Data based on a differential I

DD off.

measurement between reset configuration and continuous A/D conversions with amplifier

A

12.5 Clock and timing characteristics

Subject to general operating conditions for V

DD

, f

OSC

, and T

A

.

Table 55.

General timings

Symbol Parameter

(1)

Conditions Min Typ

(2)

Max Unit t c(INST) t v(IT)

Instruction cycle time

Interrupt reaction time

(3) t v(IT)

=

Δ t c(INST)

+ 10 f

CPU

=8 MHz f

CPU

=8 MHz

2

250

10

1.25

3

375

12

1500

22

2.75

1.

Data based on characterization. Not tested in production.

2.

Data based on typical application software.

3.

Time measured between interrupt event and interrupt vector fetch.

Δ t needed to finish the current instruction execution.

c(INST) is the number of t

CPU

cycles

Table 56.

Auto-wakeup RC oscillator

Parameter Typ Max Unit t

CPU ns t

CPU

μ s

Supply Voltage Range 2.4

5.0

5.5

V

Operating Temperature Range -40 25 125 °C

Current Consumption

Consumption

(1)

(1)

Without prescaler

AWU RC switched off

2.0

8.0

0

14.0

Obsolete Product(s) - Obsolete Product(s) µA

µA

(1) Obsolete Product(s) - Obsolete Product(s)

1.

Data guaranteed by design.

20 33 60 kHz

103/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

T

A

= -40 to 125 °C, unless otherwise specified;

Table 57.

RAM and Hardware registers

Symbol Parameter Conditions

V

RM

Data retention mode

1)

Halt mode (or Reset)

Min

1.6

Typ Max Unit

V

Table 58.

Flash Program memory

Symbol Parameter Conditions Min Typ Max Unit t t

V prog

RET

N

I

DD

RW

DD

Operating voltage for Flash write/erase

Programming time for 1~32 bytes

(2)

Programming time for 1 kByte

Data retention

(3)

Write erase cycles

Supply current

(6)

T

A

=−

40 to +125°C

2.4

(1)

T

A

=

+25°C

T

A

=

+55°C

(4)

T

A

=

+25°C

Read / Write / Erase modes, f

CPU

V

DD

= 5.5 V

= 8 MHz ,

No Read/No Write

Mode

20

10k

(5)

Power down mode /

Halt

5

0.16

0.32

0

5.5

10

V ms s years cycles

2.6 mA

100

0.1

1.

Minimum V

DD

supply voltage without losing data stored in RAM (in Halt mode or under reset) or in hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.

2.

Up to 32 bytes can be programmed at a time.

3.

Data based on reliability test results and monitored in production.

4.

The data retention time increases when the T

A

decreases.

5.

Design target value pending full product characterization.

6.

Guaranteed by Design. Not tested in production.

μ

μ

A

A

Obsolete Product(s) - Obsolete Product(s)

104/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

Susceptibility tests are performed on a sample basis during product characterization.

12.7.1 Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the

LEDs).

● ESD : Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.

● FTB : A Burst of Fast Transient voltage (positive and negative) is applied to V

DD

and

V

SS

through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

●

●

●

The software flowchart must include the management of runaway conditions such as:

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)

Pre-qualification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Level/ Obsolete Product(s) - Obsolete Product(s)

V

DD

=

5 V, T

A

=

+25 °C, f

OSC

=

8 MHz,

Voltage limits to be applied on any I/O pin to

V

FESD

SO8 package, 3B induce a functional disturbance conforms to IEC 1000-4-2

V

FFTB

Fast transient voltage burst limits to be applied through 100 pF on V

DD

and V

DD pins to induce a functional disturbance

V

DD

=

5 V, T

A

=

+25 °C, f

OSC

SO8 package,

=

8 MHz, conforms to IEC 1000-4-4

4B

105/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.

Table 60.

EMI characteristics

(1)

Symbol Parameter Conditions

Monitored frequency band

Max vs.

[f

OSC

/f

CPU

]

-/8 MHz

Unit

S

EMI

Peak level

V

DD

=

5 V, T

A

=

+25 °C,

SO8 package, conforming to SAE J

1752/3

0.1 MHz to

30 MHz

30 MHz to

130 MHz

130 MHz to

1 GHz

SAE EMI Level

1.

Data based on characterization results, not tested in production.

21

23

10

3 dB

μ

V

-

12.7.3 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.

For more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated: Human Body Model. This test conforms to the JESD22-A114A/A115A standard.

Table 61.

Absolute maximum ratings

Symbol Ratings Conditions

Maximum value

(1)

Unit

V

ESD(HBM)

Electrostatic discharge voltage

(human body model)

T

A

=

+25°C > 4000 V

Static and dynamic latchup

Obsolete Product(s) - Obsolete Product(s) performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latchup standard. For more details, refer to the application note AN1181.

● DLU : Electrostatic discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latchup performance in

106/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode.

This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.

Table 62.

Electrical sensitivities

Symbol Parameter Conditions Class

(1)

LU

DLU

Static latchup class

Dynamic latchup class

T

A

=

+125 °C

V

DD

T

A

=

5.5 V, f

=

+25 °C

OSC

=

4 MHz,

A

A

1.

Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B

Class strictly covers all the JEDEC criteria (international standard).

Obsolete Product(s) - Obsolete Product(s)

107/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

12.8 I/O port pin characteristics

Subject to general operating conditions for V

DD

, f

OSC

, and T

A

unless otherwise specified.

Table 63.

General characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

V

V

R

I

I

IL

IH hys

L

S

PU

Input low level voltage

Input high level voltage

-40°C to 125°C

0.7V

DD

Schmitt trigger voltage hysteresis

(1)

Input leakage current V

SS

≤ V

IN

≤ V

DD

Static current consumption induced by each floating input pin

(2)

Floating input mode

Weak pull-up equivalent resistor

(3)

(4)

V

IN

=

V

S

S

400

400

V

DD

=5 V 80 120

V

DD

=3 V 200

(1)

0.3V

±1

170

DD

V mV

μ k

A

Ω

C

IO t f(IO)out

I/O pin capacitance

Output high to low level fall time

1)

5

25 pF

C

L

=50 pF

Between 10% and 90% ns t r(IO)out

Output low to high level rise time

1)

25 t w(IT)in

External interrupt pulse time

(5)

1 t

CPU

1.

Data based on characterization results, not tested in production.

2.

Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see

Figure 48

). Static peak current value taken at a fixed V

IN

value, based on design simulation and technology characteristics, not tested in production. This value depends on V

DD and temperature values.

3.

The R

PU

pull-up equivalent resistor is based on a resistive transistor (corresponding I

PU current

characteristics described in Figure 49 ).

4.

R

PU

not applicable on PA3 because it is multiplexed on RESET pin

5.

To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.

Figure 48.

Two typical applications with unused I/O pin

Obsolete Product(s) - Obsolete Product(s)

V

DD

ST7XXX Obsolete Product(s) - Obsolete Product(s)

UNUSED I/O PORT

ST7XXX

1.

Caution : During normal operation the ICCCLK pin must be pulled- up, internally or externally (external pullup of 10k mandatory in noisy environment). This is to avoid entering I

2

C mode unexpectedly during a reset.

2.

I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC robustness and lower cost.

108/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

Figure 49.

Typical I

PU

vs. V

DD

with V

IN

=V

SS l

50

40

30

20

10

0

90

80

70

60

-45°C

25°C

90°C

VDD [V]

Subject to general operating conditions for V

DD

, f

CPU

, and T

A

unless otherwise specified.

Table 64.

Output driving current characteristics

Symbol Parameter

V

OL

(1)

V

OH

(2)

Output low level voltage for PA3/RESET standard

I/O pin (see Figure 52 )

Output low level voltage for a high sink I/O pin

when 4 pins are sunk at same time (see Figure 55

)

Output high level voltage for an I/O pin when 4 pins

are sourced at same time (see Figure 58

)

Conditions Min Max Unit

I

IO

= +5 mA,T

A

≤

125 °C

I

IO

= +2 mA,T

A

≤

125 °C

I

IO

=+20 mA,T

A

≤

125 °C

I

IO

= +8 mA,T

A

≤

125 °C

I

IO

= -5 mA,T

A

≤

125 °C V

DD

-1500

I

IO

= -2 mA,T

A

≤

125 °C V

DD

-800

1200

400

1300

750

Output low level voltage for PA3/RESET standard

I/O pin (see Figure 51 )

V

OL

(1)(3)

Output low level voltage for a high sink I/O pin

when 4 pins are sunk at same time (see Figure 54

)

I

IO

= +2 mA,T

A

≤

125 °C

I

IO

= +2 mA,T

A

≤

125 °C

I

IO

= +8 mA,T

A

≤

125 °C

500

180

600

V

OH

(2)(3)

Output high level voltage for an I/O pin when 4 pins

are sourced at same time (see Figure 57

)

I

IO

= -2 mA,T

A

≤

125 °C V

DD

-800

Output low level voltage for PA3/RESET standard

I/O pin (see Figure 53 )

Obsolete Product(s) - Obsolete Product(s)

Output low level voltage for a high sink I/O pin

I

IO

= +2 mA,T

A

≤

125 °C

I

IO

= +2 mA,T

A

≤

125 °C

700

200

V

OH

(2)(3)

800

when 4 pins are sunk at same time (see Figure 53

) Obsolete Product(s) - Obsolete Product(s)

Output high level voltage for an I/O pin when 4 pins

I

IO

=+8 mA,T

A

≤

125 °C

I

IO

=-2 mA,T

A

≤

125 °C V

DD

-900

are sourced at same time (see Figure 56

) mV

1.

The I

IO

current sunk must always respect the absolute maximum rating specified in Table 52 and the sum of I

must not exceed I

VSS

.

IO

(I/O ports and control pins)

2.

The I

IO

current sourced must always respect the absolute maximum rating specified in Table 52 and the sum of I

must not exceed I

VDD

. True open drain I/O pins do not have V

OH

.

IO

(I/O ports and control pins)

3.

Not tested in production, based on characterization results.

109/136

Electrical characteristics

Figure 50.

Typical V

OL

at V

DD

= 2.4 V (standard pins)

ST7LITEUS2, ST7LITEUS5

1400

1200

1000

800

600

400

200

0

-45°C

25°C

90°C

130°C

0 2

Iol [mA]

Figure 51.

Typical V

OL

at V

DD

= 3 V (standard pins)

4

1400

1200

1000

800

600

400

200

0

0

-45°C

25°C

90°C

130°C

2 4

Iol [mA]

6 8

Figure 52.

Typical V

OL

at V

DD

= 5 V (standard pins)

-45°C

25°C

1200

1000

Obsolete Product(s) - Obsolete Product(s)

800

90°C

130°C

Obsolete Product(s) - Obsolete Product(s)

400

200

0

0 2 4

Iol [mA]

6 8

110/136

ST7LITEUS2, ST7LITEUS5

Figure 53.

Typical V

OL

at V

DD

= 2.4 V (HS pins)

Electrical characteristics

1200

1000

800

600

400

200

0

0 2

-45°C

25°C

90°C

130°C

4 6 8

Iol [mA]

10 12 14 16

Figure 54.

Typical V

OL

at V

DD

= 3 V (HS pins)

1400

1200

1000

800

600

400

200

0

0 2 4

-45°C

25°C

90°C

130°C

6 8 10

Iol [mA]

12 14 16 18 20

Figure 55.

Typical V

OL

at V

DD

= 5 V (HS pins)

800

700

600

-45°C

25°C

90°C

130°C

400

200

100

0

0 2 4 6 8 10

Iol [mA]

12 14 16 18 20

111/136

Electrical characteristics

Figure 56.

Typical V

DD

-V

OH

at V

DD

= 2.4 V (HS pins)

1800

1600

1400

1200

1000

800

600

400

200

0

-45°C

25°C

90°C

130°C

0 2 4 6

Iol [mA]

Figure 57.

Typical V

DD

-V

OH

at V

DD

= 3 V (HS pins)

8

ST7LITEUS2, ST7LITEUS5

10 12

1800

1600

1400

1200

1000

800

600

400

200

0

0

-45°C

25°C

90°C

130°C

2 4 6 8

Iol [mA]

10 12 14 16 18

Figure 58.

Typical V

DD

-V

OH

at V

DD

= 5 V (HS pins)

1000

900

-45°C

25°C

90°C

130°C

600 Obsolete Product(s) - Obsolete Product(s)

400

300

200

100

0

0 2 4 6 8 10

Iol [mA]

12 14 16 18 20

112/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

Figure 59.

Typical V

OL

vs. V

DD

(HS pins)

100

90

80

-45°C

25°C

90°C

130°C

70

60

50

40

2.4

2.6 2.8

3 3.2

3.4 3.6

3.8

4 4.2 4.4

4.6

4.8

Vdd [V]

5 5.2

5.4

5.6 5.8

6

500

450

400

350

300

250

200

150

100

-45°C

25°C

90°C

130°C

2.4

2.6

2.8

3 3.2

3.4

3.6

3.8

4 4.2

4.4

4.6

4.8

Vdd [V]

5 5.2

5.4

5.6

5.8

6

900

800

700

600

500

400

-45°C

25°C

90°C

130°C

300

200

2.4

2.6 2.8

3 3.2

3.4

3.6 3.8

4 4.2

4.4

4.6 4.8

Vdd [V]

5 5.2

5.4

5.6 5.8

6

Figure 60.

Typical V

DD

-V

OH

vs. V

DD

(HS pins)

200

700

180

160

140

120

-45°C

25°C

90°C

130°C

600

500

400

100

300

80

200

60

40

2.4 2.6

2.8

3 3.2 3.4

3.6 3.8

4 4.2 4.4

4.6 4.8

Vdd [V]

5 5.2

5.4 5.6

5.8

6

-45°C

25°C

90°C

130°C

100

2.4

2.6

2.8

3 3.2

3.4

3.6

3.8

4 4.2

4.4

4.6

4.8

Vdd [V]

5 5.2

5.4

5.6

5.8

6

12.9 Control pin characteristics

The reset network protects the device against parasitic resets.

The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset

Obsolete Product(s) - Obsolete Product(s)

Whatever the reset source is (internal or external), the user must ensure that the level on the

RESET pin can go below the V

IL

max. level specified in

Table 65 . Otherwise the reset will

Because the reset circuit is designed to allow the internal reset to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for I

INJ(RESET)

in Table 44 .

Refer to

Figure 61

and

Figure 62

for a description of the RESET pin protection circuit with

LVD enabled and disabled.

113/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

Refer also to

Section 11.2.1: Illegal opcode reset for more details on illegal opcode reset

conditions.

Table 65.

Asynchronous RESET pin characteristics

(1)

Symbol Parameter Conditions Min Typ Max Unit

V

IL

Input low level voltage

V

SS

-

0.3

0.3V

DD

V

IH

Input high level voltage 0.7V

DD

V

V

DD

+

0.3

V hys

Schmitt trigger voltage hysteresis

(2)

Output low level voltage

(3)

V

R

OL

ON

Pull-up equivalent resistor

(4)

V

DD

=5 V I

IO

=+2 mA

V

DD

=5 V

V

IN

=

V

SS

V

DD

=3 V t w(RSTL)out

Generated reset pulse duration Internal reset sources t h(RSTL)in

External reset pulse hold time

(5) t g(RSTL)in

Filtered glitch duration

30

20

2

50

90

(2)

90

(2)

200

400 mV

70

V k

Ω

1.

T

A

= -40°C to 125°C, unless otherwise specified.

2.

Data based on characterization results, not tested in production.

3.

The I

IO

current sunk must always respect the absolute maximum rating specified in

Table 44 and the sum

of I

IO

(I/O ports and control pins) must not exceed I

VSS

.

4.

The R

ON

pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between V

ILmax

and V

DD.

5.

To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below t h(RSTL)in

can be ignored.

Figure 61.

RESET pin protection when LVD is enabled

μ s

μ s ns

EXTERNAL

RESET

Required Optional

(note 3)

0.01

μ F

1M Ω

V

DD

R

ON

Filter

PULSE

GENERATOR

ST7XXX

INTERNAL

RESET

WATCHDOG

ILLEGAL OPCODE

5)

LVD RESET

114/136 down capacitor is required to filter noise on the reset line.

- Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in

Table 2

and text above)

- Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M

Ω

pull-down on the RESET pin.

- The capacitors connected on the RESET pin and also the power supply are key to avoid any startup marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace

10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.”

3.

In case a capacitive power supply is used, it is recommended to connect a 1M

Ω

pull-down resistor to the

RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power consumption of the MCU).

ST7LITEUS2, ST7LITEUS5

Figure 62.

RESET pin protection when LVD is disabled

Electrical characteristics

USER

EXTERNAL

RESET

CIRCUIT

Required

0.01

μ F

V

DD

R

ON

Filter

PULSE

GENERATOR

ST7XXX

INTERNAL

RESET

WATCHDOG

ILLEGAL OPCODE

5)

Subject to general operating condition for V

DD

, f

OSC

, and T

A

unless otherwise specified.

Table 66.

10-bit ADC characteristics

Symbol Parameter Conditions f

ADC

V

AIN

ADC clock frequency

(2)

Conversion voltage range

(3)

R

AIN

External input resistor

V

DD

= 5 V, f

ADC

=4 MHz

V

DD

= 3.3 V, f

ADC

=4 MHz

2.7 V

≤

V

DD

≤

5.5 V, f

ADC

=2 MHz

2.4 V

≤

V

DD

≤

2.7 V, f

ADC

=1 MHz

C

ADC

Internal sample and hold capacitor

Min Typ

(1)

V

SSA

3

Max

4

V

DDA

8

(4)

7

(4)

10

(4)

TBD

(4)

Unit

MHz

V k

Ω pF

Stabilization time after ADC t

STAB

0

(5) enable

μ s

Conversion time f

CPU

=8 MHz, 3.5

(Sample+Hold) f

ADC

=4 MHz t

ADC - Sample capacitor loading Obsolete Product(s) - Obsolete Product(s)

- Hold conversion time

4

10

1/f

ADC

1.

Unless otherwise specified, typical data are based on T

A design guidelines and are not tested.

=25°C and V

DD

-V

SS

=5 V. They are given only as

2.

The maximum ADC clock frequency allowed within V

DD

= 2.4 to 2.7 V operating range is 1 MHz.

3.

When V

DDA and V

SSA pins are not available on the pinout, the ADC refers to V

DD and V

SS.

4.

Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than

10k

Ω

). Data based on characterization results, not tested in production.

5.

The stabilization time of the A/D converter is masked by the first t enable is then always valid.

LOAD

. The first conversion after the

115/136

Electrical characteristics ST7LITEUS2, ST7LITEUS5

Figure 63.

Typical application with ADC

V

DD

V

T

0.6V

R

AIN AINx

V

AIN

V

T

0.6V

10-Bit A/D

Conversion

C

ADC

I

L

±1

μ

A

ST7LITEUSx

Table 67.

ADC accuracy with V

DD

= 3.3 to 5.5 V

Symbol

(1)

Parameter Conditions

|E

T

|

|E

O

|

|E

G

|

|E

D

|

|E

L

|

Total unadjusted error

Offset error

Gain Error

Integral linearity error

Differential linearity error f f

CPU

ADC

=8 MHz,

=4 MHz

(1)

1.

Data based on characterization results over the whole temperature range.

Table 68.

ADC accuracy with V

DD

= 2.7 to 3.3 V

Symbol

(1)

Parameter Conditions

|E

T

| Total unadjusted error

|E

O

| Offset error

|E

G

| Gain Error

|E

D

| Differential linearity error

|E

L

| Integral linearity error f f

CPU

ADC

=4 MHz,

=2 MHz

(1)

1.

Data based on characterization results over the whole temperature range.

Table 69.

ADC accuracy with V

DD

= 2.4V to 2.7V

Symbol

(1)

Parameter Conditions

Typ

2.1

0.2

0.3

1.9

1.9

Typ

2.0

0.1

0.4

1.8

1.7

Typ

Max

5.0

2.5

1.5

3.5

4.5

Max

3.0

1.5

1.4

2.5

2.5

Max

Unit

LSB

Unit

LSB

Unit

|E

T

| Total unadjusted error 2.2

3.5

Obsolete Product(s) - Obsolete Product(s)

0.5

1.5

|E

O

| Offset error

|E

G

| Gain Error f

CPU

=2 MHz, f

ADC

=1 MHz

(1)

0.5

1.5

|E

D

| Differential linearity error 1.8

2.5

1.8

2.5

|E

L

| Integral linearity error

1.

Data based on characterization results at a temperature

≥

25°C.

116/136

ST7LITEUS2, ST7LITEUS5 Electrical characteristics

Figure 64.

ADC accuracy characteristics

Digital Result ADCDR

1023

1022

1021

1LSBIDEAL =

1024

4

3

2

7

6

5

1

0

V

SS

1

E

O

2 3

E

T

1 LSB

E

L

IDEAL

4 5 6 7

(2)

E

D

(3)

(1)

E

G

1021 1022 1023 1024

V

DD

V in

(LSB

IDEAL

)

1.

Example of an actual transfer curve

2.

The ideal transfer curve

3.

End point correlation line

4.

E

T

=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

5.

E

O

=Offset Error: deviation between the first actual transition and the first ideal one.

6.

E

G

=Gain Error: deviation between the last ideal transition and the last actual one.

7.

E

D

=Differential Linearity Error: maximum deviation between actual steps and the ideal one.

8.

E

L

=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

Obsolete Product(s) - Obsolete Product(s)

117/136

Package characteristics ST7LITEUS2, ST7LITEUS5

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status are available at: www.st.com

.

ECOPACK® is an ST trademark.

13.1 Package mechanical data

Figure 65.

8-lead very thin fine pitch dual flat no-lead package outline

D

INDEX AREA

(D/2 x E/2) e b E

TOP VIEW

L

E2

INDEX AREA

(D/2 x E/2)

A

D2

BOTTOM VIEW SIDE VIEW

Table 70.

8-lead very thin fine pitch dual flat no-lead package mechanical data mm inches

(1)

Dim.

Min Typ Max Min Typ Max

A

A1

A3 b

D

D2

0.80

0.00

0.25

0.90

0.02

0.20

0.30

4.50

3.65

1.00

0.05

0.35

0.0310

0.0000

0.0100

0.0350

0.0010

0.0080

0.0120

0.1770

0.1440

0.0390

0.0020

0.0140

3.50

3.75

0.1380

0.1480

E 3.50

0.1380

E2 e

1.96

2.11

0.80

2.21

0.0770

0.0830

0.0310

0.0870

Obsolete Product(s) - Obsolete Product(s)

0.30

0.40

0.50

0.0120

Number of pins

0.0160

0.0200

L Obsolete Product(s) - Obsolete Product(s)

N 8

1.

Values in inches are converted from mm and rounded to 4 decimal digits.

118/136

ST7LITEUS2, ST7LITEUS5 Package characteristics

Figure 66.

8-pin plastic small outline package, 150-mil width package outline

D h x 45°

A1

A2 A

α

B L

C

E H e

Table 71.

8-pin plastic small outline package, 150-mil width, package mechanical data mm inches

(1)

Dim.

Min Typ Max Min Typ Max

D

E

B

C

A

A1

A2 e

H

1.35

0.10

1.10

0.33

0.19

4.80

3.80

1.27

1.75

0.25

1.65

0.51

0.25

5.00

4.00

0.0530

0.0040

0.0430

0.0130

0.0070

0.1890

0.1500

0.0500

5.80

6.20

0.2280

0.2440

0.25

0d

0.50

8d

0.0100

0.0200

h

α

L 0.40

1.27

0.0160

Number of pins

0.0500

Obsolete Product(s) - Obsolete Product(s)

N 8

0.0690

0.0100

0.0650

0.0200

0.0100

0.1970

0.1580

119/136

Package characteristics ST7LITEUS2, ST7LITEUS5

Figure 67.

8-pin plastic dual in-line package, 300-mil width package outline

E b b2 e

A1

A2 A

L b3 eB c

D1

D

D

8

1

5

4

E1

Table 72.

8-pin plastic dual in-line package, 300-mil width package mechanical data mm inches

(1)

Dim.

Min Typ Max Min Typ Max b b2 b3 c

A

A1

A2

D

D1 e eB

0.76

0.20

9.02

0.13

0.38

2.92

0.36

1.14

3.30

0.46

1.52

0.99

0.25

9.27

2.54

5.33

4.95

0.56

1.78

1.14

0.36

10.16

0.0150

0.1150

0.0140

0.0450

0.0300

0.0080

0.3550

0.0050

0.1300

0.0180

0.0600

0.0390

0.0100

0.3650

0.1000

0.2100

0.1950

0.0220

0.0700

0.0450

0.0140

0.4000

10.92

0.4300

E 7.62

7.87

8.26

0.3000

0.3100

0.3250

E1 6.10

6.35

7.11

0.2400

0.2500

0.2800

Obsolete Product(s) - Obsolete Product(s)

L 2.92

3.30

3.81

0.1150

0.1300

0.1500

Obsolete Product(s) - Obsolete Product(s)

N 8

1.

Values in inches are converted from mm and rounded to 4 decimal digits.

120/136

ST7LITEUS2, ST7LITEUS5 Package characteristics

Figure 68.

16-pin plastic dual in-line package, 300-mil width, package outline b2

E

A2 A

A1 L e e1

D b eA eB c

8

E1

1

17_ME

Table 73.

16-pin plastic dual in-line package, 300-mil width, package mechanical data mm inches

(1)

Dim.

Min Typ Max Min Typ Max

5.33

0.2100

b b2 c

D

A

A1

A2

E

E1 e e1

0.38

2.92

0.36

1.14

0.20

18.67

7.62

6.10

3.30

0.46

1.52

0.25

19.18

7.87

6.35

2.54

17.78

4.95

0.56

1.78

0.36

19.69

8.26

7.11

0.0150

0.1150

0.0140

0.0450

0.0080

0.7350

0.3000

0.2400

0.1300

0.0180

0.0600

0.0100

0.7550

0.3100

0.2500

0.1000

0.7

0.1950

0.0220

0.0700

0.0140

0.7750

0.3250

0.2800

eA eB

7.62

10.92

0.3000

0.4300

2.92

3.30

3.81

0.1150

0.1300

0.1500

Number of pins

N

16

1.

Values in inches are converted from mm and rounded to 4 decimal digits.

121/136

Package characteristics ST7LITEUS2, ST7LITEUS5

Table 74.

Thermal characteristics

Symbol Ratings Value Unit

R thJA

Package thermal resistance

(junction to ambient)

Plastic DIP8

SO8

DFN8 (on 4-layer

PCB)

DFN8 (on 2-layer

PCB)

82

130

50

106

°C/W

T

Jmax

Maximum junction temperature

(1)

150 °C

P

Dmax

Power dissipation

(2)

Plastic DIP8

SO8

DFN8 (on 4-layer

PCB)

DFN8 (on 2-layer

PCB)

300

180

500

250 mW

1.

The maximum chip-junction temperature is based on technology characteristics.

2.

The maximum power dissipation is obtained from the formula P where P

INT

is the chip internal power (I

DD ports used in the application.

x V

DD

D

= (T

J

The power dissipation of an application can be defined by the user with the formula: P

) and P

PORT

-T

A

) / R thJA

.

D

=P

INT

+P

PORT

is the port power dissipation depending on the

Obsolete Product(s) - Obsolete Product(s)

122/136

ST7LITEUS2, ST7LITEUS5

14

Device configuration and ordering information

Device configuration and ordering information

Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). Refer to

Table 79

for the full list of supported part numbers:

● ST7FLITEUSA2xx and ST7FLITEUSA5xx XFlash devices are shipped to customers with a default program memory content (FFh).

● Factory Advanced Service Technique ROM (FASTROM) versions are also available: they are factory-programmed XFlash devices.

The FASTROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the

FASTROM devices are factory-configured.

The two option bytes allow the hardware configuration of the microcontroller to be selected.

The option bytes can be accessed only in programming mode (for example using a standard

ST7 programming tool).

Bit 7:6 CKSEL[1:0] Startup clock selection.

This bit is used to select the startup frequency. By default, the internal RC is selected (see

Table 75: Startup clock selection ).

Bit 5 Reserved, must always be 1.

Bit 4 Reserved, must always be 0.

Bits 3:2 LVD[1:0] Low Voltage Detection selection

These option bits enable the LVD block with a selected threshold as shown in

Table 76: LVD threshold configuration .

Bit 1 WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

Bit 0 WDG HALT Watchdog Reset on Halt

This option bit determines if a reset is generated when entering Halt mode while the

1: Reset generation when entering Halt mode

123/136

Device configuration and ordering information

Table 75.

Startup clock selection

Configuration

Internal RC as Startup Clock

Reserved

AWU RC as a Startup Clock

Reserved

External Clock on pin PA5

Table 76.

LVD threshold configuration

Configuration

LVD Off

Highest voltage threshold

Medium voltage threshold

Lowest voltage threshold

ST7LITEUS2, ST7LITEUS5

CKSEL1

0

0

0

1

1

CKSEL0

0

0

1

0

1

LVD1

0

0

1

1

LVD0

1

0

1

0

Bits 7:4 Reserved, must always be 1.

Bit 3 Reserved, must always be 0.

Bit 2 SEC0 Sector 0 size definition

This option bit indicates the size of sector 0 according to the following table (see

Table 77: Definition of sector 0 size

).

Bit 1 FMP_R Readout protection

Readout protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be

erased first, and the device can be reprogrammed. Refer to Section 4.5

and the

ST7 Flash Programming Reference Manual for more details.

0: Readout protection off

1: Readout protection on

Bit 0 FMP_W FLASH write protection

This option indicates if the FLASH program memory is write protected.

Warning: When this option is selected, the program memory (and the option bit itself) can never be erased or programmed again.

0: Write protection off Obsolete Product(s) - Obsolete Product(s)

Table 77.

Definition of sector 0 size

0.5k

1k

0

1

124/136

ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information

Default value

1

7

Table 78:

OPTION BYTE 0

0 7

OPTION BYTE 1

0

Reserved SEC0 FMPR FMPW

CKSEL

1

CKSEL

0

Res Res LVD1 LVD0

WDG

SW

WDG

HALT

1 1 1 0 0 0 0 0 0 1 0 1 1 1 1

Customer code is made up of the FASTROM contents and the list of the selected options (if any). The FASTROM contents are to be sent on diskette, or by electronic means, with the

S19 hexadecimal file generated by the development tool. All unused bytes must be set to

FFh. The selected options are communicated to STMicroelectronics using the correctly completed option list appended.

Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred.

The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.

Table 79.

Supported order codes

(1)

Order code

Program memory

(bytes)

RAM

(bytes)

ADC

Temperature range

Package Conditioning

ST7FLITEUSA2B6

ST7FLITEUSA2M6

ST7FLITEUSA2M6TR

ST7FLITEUSA2U6TR

ST7FLITEUSA5B6

ST7FLITEUSA5M6

ST7FLITEUSA5M6TR

ST7FLITEUSA5U6

ST7FLITEUSA5U6TR

1 Kbyte

FLASH

1 Kbyte

FLASH

128

128

-

-

-

-

10-bit

10-bit

10-bit

10-bit

10-bit

-40°C +85°C

-40°C +85°C

DIP8

SO8

SO8

DFN8

DIP8

SO8

SO8

DFN8

DFN8

Tube

Tube

Tape & Reel

Tape & Reel

Tube

Tube

Tape & Reel

Tray

Tape & Reel

ST7FLITEUSICD

1 Kbyte

128 -40°C +125°C DIP16

(2)

Tube Obsolete Product(s) - Obsolete Product(s)

ST7PLUSA2B6 DIP8 Tube

Obsolete Product(s) - Obsolete Product(s)

FASTROM

128 -40°C +85°C

SO8 Tube

ST7PLUSA2M6TR SO8 Tape & Reel

ST7PLUSA2U6TR DFN8 Tape & Reel

125/136

Device configuration and ordering information ST7LITEUS2, ST7LITEUS5

Table 79.

Supported order codes

(1)

(continued)

Order code

Program memory

(bytes)

RAM

(bytes)

ADC

Temperature range

Package

ST7PLUSA5B6

ST7PLUSA5M6

ST7PLUSA5M6TR

ST7PLUSA5U6

ST7PLUSA5U6TR

ST7PLUSA2B3

ST7PLUSA2M3

ST7PLUSA2M3TR

ST7PLUSA2U3TR

ST7PLUSA5B3

ST7PLUSA5M3

ST7PLUSA5M3TR

ST7PLUSA5U3

1 Kbyte

FASTROM

1 Kbyte

FLASH

1 Kbyte

FLASH

128

128

128

-

-

10-bit

10-bit

10-bit

10-bit

10-bit

10-bit

10-bit

10-bit

10-bit

-

-

-40°C +85°C

-40°C +125°C

-40°C +125°C

ST7PLUSA5U3TR

ST7PLUSA2B3

ST7PLUSA2M3

ST7PLUSA2M3TR

ST7PLUSA2U3TR

ST7PLUSA5B3

1 Kbyte

FASTROM

128

10-bit

-

-

-

-

10-bit

-40°C +125°C

ST7PLUSA5M3

ST7PLUSA5M3TR

ST7PLUSA5U3

1 Kbyte

FASTROM

128

10-bit

10-bit

10-bit

-40°C +125°C

SO8

SO8

DFN8

ST7PLUSA5U3TR 10-bit DFN8

1.

Contact ST sales office for product availability.

2.

For development or tool prototyping purposes only, not orderable in production quantities.

DFN8

DIP8

SO8

SO8

DFN8

DIP8

SO8

DFN8

DIP8

SO8

SO8

DFN8

DIP8

SO8

SO8

DFN8

DFN8

DIP8

SO8

Conditioning

Obsolete Product(s) - Obsolete Product(s)

Tube

Tube

Tape & Reel

Tray

Tape & Reel

Tube

Tube

Tape & Reel

Tape & Reel

Tube

Tube

Tape & Reel

Tray

Tape & Reel

Tube

Tube

Tape & Reel

Tape & Reel

Tube

Tube

Tape & Reel

Tray

Tape & Reel

126/136

Device configuration and ordering information ST7LITEUS2, ST7LITEUS5

Figure 69.

Option list

ST7LITEUS FASTROM MICROCONTROLLER OPTION LIST

(Last update: February 2009)

Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference/FASTROM Code*:. . . . . . . . . . . . . . . . . . . . . . . . . .

*FASTROM code name is assigned by STMicroelectronics.

FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.

Device Type/Memory Size/Package (check only one option):

------------------|-----------------------|

FASTROM DEVICE: | 1K FASTROM |

------------------|-----------------------|

PDIP8

SO8

DFN8

|

|

|

[ ] |

[ ]

[ ]

|

|

Conditioning (check only one option):

---------------------------------------------------------------------------

DIP package: [ ] Tube

SO package: [ ] Tape & Reel [ ] Tube

DFN package: [ ] Tape & Reel [ ] Tray (for ST7PLUSA5U6xxx and ST7PLUSA5U3xxx only)

Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _"

Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Maximum character count:

PDIP8/SO8/DFN8 (8 char. max) : _ _ _ _ _ _ _ _

Temperature range [ ] -40°C to +85°C [ ] -40°C to +125°C

Clock Source Selection: [ ] External Clock

[ ] AWU RC oscillator

Internal oscillator

Sector 0 size:

Readout protection:

[ ] 0.5K

[ ] Disabled

FLASH Write Protection: [ ] Disabled

LVD Reset [ ] Disabled

[ ] 1K

[ ] Enabled

[ ] Enabled

[ ] Highest threshold

Watchdog Selection: [ ] Software Activation [ ] Hardware Activation

Watchdog Reset on Halt: [ ] Disabled [ ] Enabled

Comments: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply Operating Range in the application:. . . . . . . . . . . . . . . . .

Notes:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Obsolete Product(s) - Obsolete Product(s)

Important note: Not all configurations are available. Refer to datasheet for authorized option byte combinations. Obsolete Product(s) - Obsolete Product(s) http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list

127/136

Device configuration and ordering information ST7LITEUS2, ST7LITEUS5

Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers.

ST offers complete, affordable starter kits . Starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application.

14.3.2 Development and debugging tools

Application development for ST7 is supported by fully optimizing C Compilers and the ST7

Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated development environments in order to facilitate the debugging and fine-tuning of your application. The Cosmic C Compiler is available in a free version that outputs up to

16 Kbytes of code.

The range of hardware tools includes full-featured ST7-EMU3 series emulators, cost effective ST7-DVP3 series emulators and the low-cost RLink in-circuit debugger/programmer. These tools are supported by the ST7 Toolset from

STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface.

During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the

RLink provide in-circuit programming capability for programming the Flash microcontroller on your application board.

ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK , as well as

ST7 Socket Boards which provide all the sockets required for programming any of the devices in a specific ST7 sub-family on a platform that can be used with any tool with incircuit programming capability for ST7.

For production programming of ST7 devices, ST’s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment.

Table 80

below lists the ordering codes for the ST7LITEUSx development and programming

Obsolete Product(s) - Obsolete Product(s) product selector at www.st.com/mcu.

128/136

ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information

Table 80.

Development tool order codes for the ST7LITEUSx family

In-circuit Debugger, RLink series

(1)

Emulator

Supported products Starter kit without demo board

Starter kit with

Demo Board

Programming tool

DVP series EMU series

In-circuit programmer

ST socket boards and

EPBs

ST7FLITEUS2

ST7FLITEUS5

STX-RLINK

(2)

STFLITE-

SK/RAIS

(2)

ST7MDT10-

DVP3

(3)

ST7MDT10-

EMU3

STX-RLINK

ST7-

STICK

(5)(4)

ST7SB10-

SU0

(5)

1.

Available from ST or from Raisonance, www.raisonance.com.

2.

USB connection to PC.

3.

Includes connection kit for Plastic DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide for connection kit ordering information.

4.

Parallel port connection to PC.

5.

Add suffix /EU, /UK or /US for the power supply for your region.

14.4 ST7 application notes

Table 81.

ST7 application notes

Identification Description

Application examples

AN1658

AN1720

AN1755

AN1756

AN1812

Example drivers

Serial numbering implementation

Managing the readout protection in flash microcontrollers

A high resolution/precision thermometer using ST7 and NE555

Choosing a DALI Implementation strategy with ST7DALI

A high precision, low cost, single supply ADC for positive and negative input voltages

AN 969

AN 970

AN 971

SCI communication between ST7 and PC

SPI communication between ST7 and EEPROM

I²C communication between ST7 and M24Cxx EEPROM

AN 972 ST7 software SPI master communication

AN 973

AN 974

SCI software communication with a PC using ST72251 16-bit timer

Obsolete Product(s) - Obsolete Product(s)

AN 976

AN 979

Driving a buzzer through ST7 timer PWM function Obsolete Product(s) - Obsolete Product(s)

AN 980 ST7 keypad decoding techniques, implementing wakeup on keystroke

AN1017

AN1041

AN1042

Using the ST7 universal serial bus microcontroller

Using ST7 PWM signal to generate analog output (sinusoïd)

ST7 routine for I²C slave mode management

129/136

Device configuration and ordering information ST7LITEUS2, ST7LITEUS5

AN1321

AN1325

AN1445

AN1475

AN1504

AN1602

AN1633

AN1712

AN1713

AN1753

AN1947

AN1083

AN1105

AN1129

AN1130

AN1148

AN1149

AN1180

AN1276

AN1044

AN1045

AN1046

AN1047

AN1048

AN1078

AN1082

Table 81.

ST7 application notes (continued)

Identification Description

Multiple interrupt sources management for ST7 MCUs

ST7 S/W implementation of I²C bus master

UART emulation software

Managing reception errors with the ST7 SCI peripherals

ST7 software LCD driver

PWM duty cycle switch implementing true 0% & 100% duty cycle

Description of the ST72141 motor control peripherals registers

ST72141 BLDC motor control software and flowchart example

ST7 pCAN peripheral driver

PWM management for BLDC motor drives using the ST72141

An introduction to sensorless brushless DC motor drive applications with the ST72141

Using the ST7263 for designing a USB mouse

Handling Suspend mode on a USB mouse

Using the ST7263 Kit to implement a USB game pad

BLDC motor start routine for the ST72141 microcontroller

Using the ST72141 motor control MCU in sensor mode

Using the ST7 USB low-speed firmware V4.x

Emulated 16-bit slave SPI

Developing an ST7265X mass storage application

Starting a PWM signal directly at high level using the ST7 16-bit timer

16-bit timing operations using ST7262 or ST7263B ST7 USB MCUs

Device firmware upgrade (DFU) implementation in ST7 non-USB applications

Generating a high resolution sinewave using ST7 PWMART

SMBus slave driver for ST7 I2C peripherals

Software UART using 12-bit ART

ST7MC PMAC sine wave motor control software library

General purpose

Low cost power supply for home appliances

AN1526

AN1709

ST7FLITE0 quick reference note

Obsolete Product(s) - Obsolete Product(s)

AN1752 ST72324 quick reference note

Product evaluation

AN 910

AN 990

Performance benchmarking

ST7 benefits vs industry standard

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ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information

Table 81.

ST7 application notes (continued)

Identification Description

AN1077

AN1086

AN1103

AN1150

AN1151

AN1278

Product migration

Overview of enhanced CAN controllers for ST7 and ST9 MCUs

U435 can-do solutions for car multiplexing

Improved B-EMF detection for low speed, low voltage with ST72141

Benchmark ST72 vs PC16

Performance comparison between ST72254 & PC16F876

LIN (local interconnect network) solutions

AN1131

AN1322

AN1365

AN1604

AN2200

Migrating applications from ST72511/311/214/124 to ST72521/321/324

Migrating an application from ST7263 Rev.B to ST7263B

Guidelines for migrating ST72C254 applications to ST72F264

How to use ST7MDT1-TRAIN with ST72F264

Guidelines for migrating ST7LITE1x applications to ST7FLITE1xB

Product optimization

AN 982

AN1014

AN1015

AN1040

AN1070

AN1181

AN1324

AN1502

AN1529

AN1530

AN1605

AN1636

AN1828

Using ST7 with ceramic resonator

How to Minimize the ST7 power consumption

Software techniques for improving microcontroller EMC performance

Monitoring the Vbus signal for USB Self-powered devices

ST7 checksum self-checking capability

Electrostatic Discharge sensitive measurement

Calibrating the RC oscillator of the ST7FLITE0 MCU using the mains

Emulated data EEPROM with ST7 HDFLASH memory

Extending the current & voltage capability on the ST7265 VDDF supply

Accurate timebase for low-cost ST7 applications with internal RC oscillator

Using an active RC to wakeup the ST7LITE0 from power saving mode

Understanding and minimizing ADC conversion errors

PIR (passive Infrared) detector using the ST7FLITE05/09/SUPERLITE

AN1946

AN1953

Sensorless BLDC motor control and BEMF sampling methods with ST7MC

Obsolete Product(s) - Obsolete Product(s)

ST7LITE0 microcontrolled ballast AN1971 Obsolete Product(s) - Obsolete Product(s)

Programming and tools

AN 978 ST7 Visual Develop software key debugging features

AN 983

AN 985

Key features of the Cosmic ST7 C-compiler package

Executing code In ST7 RAM

AN 986 Using the indirect addressing mode with ST7

131/136

Device configuration and ordering information ST7LITEUS2, ST7LITEUS5

AN1477

AN1527

AN1575

AN1576

AN1577

AN1601

AN1603

AN1635

AN 987

AN 988

AN1039

AN1071

AN1106

AN1179

AN1446

AN1754

AN1796

AN1900

AN1904

AN1905

Table 81.

ST7 application notes (continued)

Identification Description

ST7 serial test controller programming

Starting with ST7 assembly tool chain

ST7 math utility routines

Half duplex USB-to-serial bridge using the ST72611 USB microcontroller

Translating assembly code from HC05 to ST7

Programming ST7 Flash microcontrollers in remote ISP mode (In-situ programming)

Using the ST72521 emulator to debug an ST72324 target application

Emulated data EEPROM with Xflash memory

Developing a USB smartcard reader with ST7SCR

On-board programming methods for XFLASH and HDFLASH ST7 MCUs

In-application programming (IAP) drivers for ST7 HDFLASH or XFLASH MCUs

Device firmware upgrade (DFU) implementation for ST7 USB applications

Software implementation for ST7DALI-EVAL

Using the ST7 USB device firmware upgrade development kit (DFU-DK)

ST7 customer ROM code release information

Data logging program for testing ST7 applications via I

2

C

Field updates for FLASH based ST7 applications using a PC comm port

Hardware implementation for ST7DALI-EVAL

ST7MC three-phase AC induction motor control software library

ST7MC three-phase BLDC motor control software library

System optimization

AN1711

AN1827

AN2009

AN2030

Software techniques for compensating ST7 ADC errors

Implementation of SIGMA-DELTA ADC with ST7FLITE05/09

PWM Management for 3-phase BLDC motor drives using the ST7FMC

Back EMF detection during PWM on time by ST7MC

Obsolete Product(s) - Obsolete Product(s)

132/136

ST7LITEUS2, ST7LITEUS5 Known limitations

External interrupt 2 (ei2)

Whatever the external interrupt sensitivity configured through EICR1 register, ei2 cannot exit the MCU from Halt, Active-halt and AWUFH modes when a falling edge occurs.

Workaround

None

Obsolete Product(s) - Obsolete Product(s)

133/136

Revision history ST7LITEUS2, ST7LITEUS5

Table 82.

Document revision history

Date Revision Changes

06-Feb-06

18-Apr-06

1

2

Initial release

Removed references to 3% RC

Added note below

Figure 4

Modified presentation of

Section 4.3.1

Added notes to

Section 6.2

(above Figure 9 ), replaced 8-bit calibration value to

10-bit calibration value and changed application note reference (AN2326 instead of AN1324)

Modifed

Table 7: Clock register map and reset values and added bit 1 in the

description of CKCNTCSR register

Modified Figure 13 (added CKCNTCSR register)

Added note 2 to EICRx description

Modified caution in section 7.2 on page 25

Replaced V

IT+(LVD) by V

IT+(LVD)

in

Section : Monitoring the VDD main supply

Modified LVDRF bit description in

Section 7.4.4: Register description

Replaced “oscillator” by “main oscillator” in the second paragraph of

Section 8.4.2: Halt mode

Added note 1 to Figure 23

and added note 5 to

Figure 24

Modified Section 8.5: Auto-wakeup from Halt mode

Replaced bit 1 by bit 2 for AWUF bit in Section 8.5.1: Register description

Modified Section 9.1: Introduction . Modified Section : External interrupt function

.Updated Section 9.5: Interrupts . Modified

Section Table 47.: Operating conditions with low voltage detector (LVD) .

Modified Table 48: Auxiliary Voltage Detector (AVD) Thresholds . Modified

Table 49: Voltage drop between AVD flag set and LVD reset generation .

Modified Table 50: Internal RC oscillator calibrated at 5 V . Modified Table 53:

Supply current . Modified Table 54: On-chip peripherals

. Modified Table 63:

General characteristics

. Modified Table 64: Output driving current . Modified

Table 65: Asynchronous RESET pin characteristics

. Modified

Section 12.10:

ADC characteristics .

Added Figure 49

. Modified Figure 61

. Removed EMC protection circuitry in

Figure 62

(device works correctly without these components). Added

ECOPACK text in

Section 13: Package characteristics . Modified first paragraph

in

Section 14: Device configuration and ordering information . Modified

Table 79

. Modified conditioning option in option list. Modified

Section 14.3:

Development tools

. Added

Section 14.4: ST7 application notes . Added

Section : . Added erratasheet at the end of the document.

Obsolete Product(s) - Obsolete Product(s)

134/136

ST7LITEUS2, ST7LITEUS5 Revision history

Table 82.

Document revision history (continued)

Date Revision

18-Sep-06 3

26-Jan-07 4

5

Changes

Modified description of AVD[1:0] bits in the AVDTRH register in

Section 7.4.4

Modified description of CNTR[11:0] bits in Section 10.2.6: Register description

Modified values in

Table 44

LVD and AVD tables updated, Table 47 , Table 48 and Table 49

Internal RC oscillator data modified in Table 50 and new table added Table 51

Typical data in Table 54 (on chip peripherals) modified

EMC characteristics updated, Section 12.7

R

PU

data corrected in Table 63 including additional notes

Output driving current table updated, Table 64

R

ON

data corrected in Table 65

.

Modified ADC accuracy tables in

Section 12.10

Section : updated

Errata sheet removed from document

Notes modified for low voltage detector Section 7.4.1

Notes updated in Section 4.4

(I

2

C Interface)

Thermal characteristics table updated,

Table 74

Modified option list on

Section 14.2: Ordering information

Modified Section 14.3: Development tools

Modified text in

Section :

Added -40°C to 125°C temperature range

Modified note on ei4 in

Table 9: Interrupt mapping

Added note 3 to Section 7.3.2: External Interrupt Control register 2 (EICR2)

Added Figure 41 and Figure 40

Added a note to LVDRF in Section 7.4.4: Register description

Section 6.4.1: Introduction

Modified Table 47 and Table 48

Modified Table 50 Updated Table 53

Updated Table 64

Modified R

AIN and ADC accuracy tables in

Section 12.10: ADC characteristics

Modified Table 80

Modified Table 79

Modified option list on

Figure 69: Option list

Document reformatted.

Replaced ST7ULTRALITE by ST7LITEUS2 and ST7LITEUS5.

Removed limitations in user and in I

2

C mode from Section 15: Known limitations , and added External interrupt 2 (ei2) .

Added MCO on pin 3.

Updated Section 12.3.2: Operating conditions with low voltage detector (LVD)

,

Section 12.3.3: Auxiliary voltage detector (AVD) thresholds , Section 12.3.4:

Internal RC oscillator ,

Section 12.4: Supply current characteristics , and

Section 12.8.2: Output driving current characteristics .

Updated internal RC prescaler to add 500 KHz.

PDIP16 silhouette on cover page, and updated

Table 73: 16-pin plastic dual inline package, 300-mil width, package mechanical data and Figure 68: 16-pin plastic dual in-line package, 300-mil width, package outline

.

Changed order codes to die A version in Table 79: Supported order codes

.

Removed soldering information section.

Updated option list.

135/136

ST7LITEUS2, ST7LITEUS5

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