Intel Assembly Language Programming Manual

8080/8085 ASSEMBLY LANGUAGE
PROGRAMMING M.ANUAL
Order Number: 9800301-04
I
Copyright © 1977,1978,1979,1981 Intel Corporation
Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051
I
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PREFACE
This manual describes programming with Intel's assembly language. It will not teach you how to program a computer.
Although this manual is designed primarily for reference, it also contains some instructional material to help the beginning
programmer. The manual is organized as follows:
Chapter 1.
ASSEMBLY LANGUAGE AND PROCESSORS
Description of the assembler
Overview of 8080 hardware and instruction set
Description of 8080/8085 differences
Chapter 2.
ASSEMBLY LANGUAGE CONCEPTS
General assembly language coding rules
Chapter 3.
INSTRUCTION SET
Descriptions of each instruction (these are listed alphabetically
for quick reference)
Chapter 4.
ASSEMBLER DIRECTIVES
Data definition
Conditional assembly
Relocation
Chapter 5.
MACROS
Macro directives
Macro examples
Chapter 6.
PROGRAMMING TECHNIQUES
Programming examples
Chapter 7.
INTERRUPTS
Description of the interrupt system.
Chapters 3 dnd 4 will fill most of the experienced programmer's reference requirements. Use the table of contents or the
index to locate information quickly.
The beginning programmer should read Chapters 'I and 2 and then skip to the examples in Chapter 6. As these examples
raise questions, refer to the appropriate information in Chapter 3 or 4. Before writing a program, you will need to read
Chapter 4. The 'Programming Tips' in Chapter 4 arc intended especially for the beginning programmer.
iii
RELATED PUBLICATIONS
To usc your Intcllec development system effectively, you should be familiar with the following Intel
publications:
ISIS-II 8080/8085 MACRO ASSEMBLER OPERATOR'S MANUAL, 9800292
When you activate the assembler, you have the option of specifying a number of controls. The operator's
manudl describes the activation sequence for the assembler. The manual also describes the debugging tools
and the error messages suppl ied l?y the assembler.
ISIS-II SYSTEM USER'S GUIDE, 9800306
User programs Me commonly stored on diskette files. The ISIS-II User's Guide describes the usc of the text
editor for entering and maintaining programs. The manual also describes the procedures for linking and
locati ng relocatable program modules.
Hardware References
For additional information about processors and their related components, refer to the appropriate User's
Manual:
8080 MICROCOMPUTER SYSTEMS USER'S MANUAL, 9800153
8085 MICROCOMPUTER SYSTEMS USER'S MANUAL, 9800366
iv
TABLE OF CONTENTS
Chapter 1.
ASSEMBLY LANGUAGE AND PROCESSORS
1-1
Introduction
....... .
What Is An Assembler?
What the Assembler Does
Object Code . . . . . .
Program Listing
Symbol-Cross-Reference Listing
Do You Need the Assembler?
Overview of 8080/8085 Hardware
Memory
ROM
RAM
Program Counter
Work Registers
Internal Work Registers
Condition Flags
Carry Flag
Sign Flag
Zero Flag
Parity Flag
Auxiliary Carry Flag
1-1
1-1
1-1
Stack and Stack Pointer
Stack Operations
Saving Program Status
Input/Output Ports . .
Instruction Set
Addressing Modes
Impl ied Addressi ng
Register Addressing
Immediate Addressing
Direct Addressing
Register Indirect Addressing
Combined Addressing Modes
Timing Effects of Addressing Modes
Instruction Naming Conventions
Data Transfer Group
Arithmetic Group
Logical Group
Branch Group
Stack, I/O, and Mach ine Control Instructions
Hardware/I nstruct ion Summary
Accumulator Instructions
Register Pair (Word) Instructions
Brz.nching Instructions
Instruction Set Guide
1-2
1-2
1-3
1-3
1-5
1-5
1-5
1-5
1-6
1-7
1-9
1-9
1-10
1-10
1-11
1-11
1-11
1-12
1-13
1-13
1-14
1-15
1-15
1-15
1-15
1-15
1-15
1-16
1-16
1-16
1-16
1-16
1-17
1-17
1-18
1-19
1-19
1-19
1-21
1-22
1-23
v
8085 Processor Differences
Programming for the 8085
Cond itional Instructions
Chapter 2.
ASSEMBLY LANGUAGE CONCEPTS
2-1
Introduction
Source Line Format
Character Set
Delimiters
Label/Name Field
Opcode Field
Operand Field
Comment Field
Coding Operand Field Information
Hexadecimal Data
Decimal Data
Octal Data
Binary Data
Location Counter
ASCII Constant
Labels Assigned Values
Labels of Instruction or Data
Expressions
Instructions as Operands
Register-Type Operands
2-1
2-1
2-1
Two's Complement Representation of Data
Symbols and Symbol Tables
Symbolic Addressing
Symbolic Characteristics
Reserved, User-Defined, and Assembler-Generated Symbols
Global and Limited Symbols
Permanent and Redefinable Symbols
Absolute and Relocatable Symbols
Assembly-Time Expression Evaluation
Operators
Arithmetic Operators
Shift Operators
Logical Operators
Compare Operators
Byte Isolation Operators
Permissible Range of Values
Precedence of Operators
Relocatable Expressions
Chaining of Symbol Definitions
Chapter 3.
vi
1-24
1-24
1-25
2-2
2-3
2-4
2-4
2-4
2-4
2-5
2-5
2-5
2-5
2-6
2-6
2-6
2-6
2-6
2-7
2-7
2-7
2-9
2-9
2-9
2-9
2-10
2-11
2-11
2-11
2-11
2-12
2-12
2-13
2-13
2-14
2-15
2-15
2-16
2-18
INSTRUCTION SET
3-1
How to Use this Chapter
Timing Information
Instructions are listed in alphabetical order
3-1
3-1
Chapter 4.
ASSEMBLER DIRECTIVES
Symb.ol Definition
EQU Directive
SET Directive
Data Definition
DB Directive
DW Directive
Memory Reservation
DS Directive
Programming Tips:
Data Description and Access
Random Access Versus Read Only Memory
Data Description
Data Access
Add Symbols for Data Access
Conditional Assembly
IF, ELSE, ENDIF Directives
Assembler Termination
END Directive
Location Counter Control and Relocation
Location Counter Control (Non-Relocatable Mode)
ORG Directive
Introduction to Relocatability
Memory Management
Modular Program Development
Directives Used for Relocation . . . _ .
Location Counter Control (Relocatable Programs)
ASEG Directive
CSEG Directive
DSEG Directive
ORG Directive (Relocatable Mode)
Program Linkage Directives
PUBLIC Directive
EXTRN Directive
NAME Directive
STKLN Directive
STACK and MEMORY Reserved Words
Programming Tips:
Testing Relocatable Modules
Initialization Routines
Input/Output
Remove Coding Used for Testing
Chapter 5.
4-1
4-2
4-2
4-3
4-3
4-3
4-4
4-5
4-5
4-6
4-6
4-6
4-6
4-7
4-8
4-8
4-10
4-10
4-11
4-11
4-11
4-12
4-12
4-12
4-14
4-14
4-14
4-15
4-15
4--16
4-16
4-17
4-17
4-18
4-18
4-19
4-19
4-19
4-20
4-20
MACROS
5-1
Introd uction to Macros
Why Use Macros?
What Is A Macro?
Macros Vs. Subroutines
5-1
5-1
5-1
5·3
vii
Using Macros
Macro Definition
5-3
5-3
Macro Definition Directives
5-4
MACRO Directive
5-4
ENDM Directive
LOCAL Directive
5-5
5-5
REPT Directive
5-6
I RP Directive
5-8
5-8
5-9
I RPC Directive
EXITM Directive
5-10
Special Macro Operators
5-12
Nested Macro Definitions
Macros Calls
Macro Call
5-12
5-12
Format
Nested Macro Calls
5-14
Macro Expansion
5-15
Null Macros
5-16
Sample Macros
5-16
Chapter 6. PROGRAMMING TECHNIQUES
. . . . . . . . . . . . . . . . . . . . . . . 6-1
Branch Tables Pseudo-Subroutine
Transferring Data to Subroutine
6-1
6-3
Software Multiply and Divide
. 6-7
Multibyte Addition and Subtraction
6-11
Decimal
6-12
Addition
Decimal Subtraction
Chapter 7.INTERRUPTS
6-14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
I nterrupt Concepts
Writing Interrupt Subroutines
Appendix A
7-1
7-4
INSTRUCTION SUMMARY
A-1
Appendix C
ASSEMBLER DIRECTIVE SUMMARY
ASCII CHARACTER SET
B-1
C-1
Appendix D
BINARY-DECIMAL-HEXADECIMAL CONVERSION TABLES·
D-1
Appendix B
viii
LIST OF ILLUSTRATIONS
Figure
1-1
1-2
COMPARISON OF ASSEMBLY LANGUAGE WITH PL/M
1-2
1-4
1-3
1-4
8080/8085 INTERNAL REGISTERS
. . .
1-6
....... .
1-8
1-5
EXECUTION OF MOV M,C INSTRUCTION
ASSEMBLER OUTPUTS
INSTRUCTION FETCH
............ .
1-9
ix
1. ASSEMBLY LANGUAGE AND PROCESSORS
INTRODUCTION
Almost every line of source coding in an assembly language source program translates directly into a machine.
instruction for a particular processor. Therefore, the assembly language programmer must be familiar with both
the assembly language and the processor for which he is programming.
The first part of this chapter describes the assembler. The second part describes the features of the 8080 microprocessor from a programmer's point of view. Programming differences between the 8080 and the 8085 microprocessors are relatively minor. These differences are described in a short section at the end of this chapter.
WHAT IS AN ASSEMBLER?
An assembler is a software tool - a program -- designed to simplify the task of writing computer programs. If
you have ever written a computer program directly in a machine-recognizable form such as binary or hexadecimal
code, you will appreciate the advantages of programming in a symbolic assembly language.
Assembly language operation codes (opcodes) are easily remembered (MOV for move instructions, JMP for jump).
You can also symbolically express addresses and values referenced in the operand field of instructions. Since you
assign these names, you can make them as meaningful as the mnemonics for the instructions. For example, if your
program rrust manipulate a date as data, you can assign it the symbolic name DATE. If your program contains a
set of instructions used as a timing loop (a set of instructions executed repeatedly until a specific amount of time
has passed), you can name the instruction group TIMER.
What the Assembler Does
To use the assembler, you first need a source program. The source program consists of
programmer~written
assembly. language instructions. These instructions are written using mnemonic opcodes and labels as described
previously.
Assembly language source programs must be in a machine-readable form when passed to the assembler. The
Intellec development system includes a text editor that will help you maintain source programs as paper tape
files or diskette files. You can then pass the resulting source program file to the assembler. (The text editor is
described in the ISIS-II System User's Guide.)
The assembler program performs the clerical task of translating symbolic code into object code which can be
executed by the 8080 and 8085 microprocessors. Assembler output consists of three possible files: the object
file containing your program translated into object code; the list file printout of your source code, the assemblergenerated object code, and the symbol table; and the symbol-crass-reference file, a listing of the symbol-crossreference records.
1-1
Chapter 1. Assembly Language and Processors
OBJECT
FILE
SOURCE
PROGRAM
FILE
PROGRAM
PROGRAM
LISTING
CROSS
REFERENCE
LISTING
Figure ,.,. Assembler Outputs
Object Code
For most microcomputer applications, you probably will eventually load the object program into some form of
read only memory. However, do not forget that the Intellec development system is an 8080 microcomputer
system with random access memory. In most cases you can load and execute your object program on the
development system for testing and debugging. This allows you to test your program before your prototype
application system is fully developed.
A special feature of this assembler is that it allows you to request object code in a relocatable format. This frees
the programmer from worrying about the eventual mix of read only and random access memory in the application
system; individual portions of the program can be relocated as needed when the application design is final. Also,
a large program can be broken into a number of separately assembled modules. Such modules are both easier to
code and to test. See Chapter 4 of this manual for a more thorough description of the advantages of the relocation
feature.
Program Listing
The program listing provides a permanent record of both the source program and the object code. The assembler
also provides diagnostic messages for common programming errors in the program listing. For example, if you
specify a 16-bit value for an instruction that can use only an 8-bit value, the assembler tells you that the value
exceeds the permissible range.
1·2
Chapter 1. Assembly Language and Processors
Symbol-Cross-Reference Listing
The symbol-cross-reference listing is another of the diagnostic tools provided by the assembler. Assume, for
example, that your program manipulates a data field named DATE, and that testing reveals a program logic
error in the handling of this data. The symbol-cross-referenc:e listing simplifies debugging this error because it
points you to each instruction that references the symbol DATE.
Do You Need the Assembler?
The assembler is but one of several tools available for developing microprocessor programs. Typically, choosing
the most suitable tool is based on cost restraints versus the required level of performance. You or your company
must determine cost restraints; the required level of performance depends on a number of variables:
•
The number of programs to be written: The greater the number of programs to be written, the more
you need development support. Also, it must be pointed out that there can be penalties for not
writing programs. When your application has access to the power of a microprocessor, you may be
able to provide customers with custom features through program changes. Also, you may be able to
add features through programming.
•
The time allowed for programming: As the time allowed for programming decreases, the need for
programming support increases.
•
The level of support for existing programs: Sometimes programming errors are not discovered until
the program has been in use for quite a while. Your need for programming support increases if you
agree to correct such errors for your customers. The number of supported programs in use can
mUltiply this requirement. Also, program support is frequently subject to stringent time constraints.
If none of the factors described above apply to your situation, you may be able to get along without the
assembler. Intel's PROMPT-80, for example, allows you to enter programs directly into programmable read only
memory. You enter the program manually as a string of hexadecimal digits. Such manual programming is relatively
slow and more prone to human error than computer-assisted programming. However, manual systems are one of
the least expensive tools available for microprocessor programming. Manual systems may be suitable for limited
applications, hobbyists, and those who want to explore possible applications for microprocessors.
If most of the factors listed previously apply to you, you should explore the advantages of PL/M. PL/M IS
Intel's high-level language for program development. A high-level language is directed more to problem solving
than to a particular microprocessor. This allows you to write programs much more quickly than a hardwareoriented language such as assembly language. As an example, assume that a program must move five characters
from one location in memory to another. The following example illustrates the coding differences between
assembly language and PL/M. Since instructions have not yet been described, the assembly language instructions
are represented by a flowchart.
1-3
Chapter 1. Assembly Language and Processors
ASSEMBLY LANGUAGE CODING
PL/MCODING
LOAD REGISTER WITH NUMBER
OF CHARACTERS TO BE MOVED
I
LOAD REGISTER PAIR B WITH
ADDRESS OF SOURCE (FLD1)
I
LOAD REGISTER PAIR 0 WITH
ADDRESS OF DESTINATION
(FLD2)
I
- I
LOAD ACCUMULATOR WITH 1
BYTE FROM SOURCE FIELD
I
MOVE CHARACTER FROM
ACCUMULATOR TO DESTINATION FIELD
CALL MOVE(5,FLD2,FLD1);
I
INCREMENT SOURCE ADDRESS
I
CONTINUE
INCREMENT DESTINATION
ADDRESS
I
DECREMENT CHARACTER COUNT
NO
IS
CHARACTER
COUNT
=o?
YES
C
CONTINUE
Figure 1-2. Comparison of Assembly Language with PL/M
1-4
Chapter 1. Assembly language and Processors
OVERVIEW OF 8080/8085 HARDWARE
To the programmer, the computer comprises the following parts:
•
•
•
•
•
•
•
Memory
The program counter
Work registers
Condition flags
The stack and stack pointer
Input/output ports
The instruction set
Of the components listed above, memory is not part of the processor, but is of interest to the programmer.
Memory
Since the program required to drive a microprocessor resides in memory, all microprocessor applications require
some memory. There are two general types of memory: read only memory (ROM) and random access memory
(RAM).
ROM
As the name implies, the processor can only read instructions and data from ROM; it cannot alter the contents
of ROM. By contrast, the processor can both read from and write to RAM. Instructions and unchanging data
are permanently fixed into ROM and remain intact whether or not power is applied to the system. For this
reason, ROM is typically used for program storage in single-purpose microprocessor applications. With ROM you
can be certain that the program is ready for execution when power is applied to the system. With RAM a program
must be loaded into memory each time power is applied to the processor. Notice, however, that storing programs
in RAM allows a multi-purpose system since different programs can be loaded to serve different needs.
Two special types of ROM - PROM (Programmable Read Only Memory) and EPROM (Eraseable Programmable
Read Only Memory) - are frequently used during program development. These memories are useful during
program development since they can be altered by a special PROM programmer. In high-volume commercial
applications, these special memories are usually replaced by less expensive ROM's.
RAM
Even if your program resides entirely in ROM, your application is likely to require some random access memory.
Any time your program attempts to write any data to memory, that memory must be RAM. Also, if your program uses the stack, you need RAM. If your program modifies any of its own instructions (this procedure is
discouraged), those instructions must reside in RAM.
The mix of ROM and RAM in an application is important to both the system designer and the programmer.
Normally, the programmer must know the physical addresses of the RAM in the system so that data variables
1-5
Chapter 1. Assembly Language and Processors
can be assigned within those addresses. However, the relocation feature of this assembler allows you to code a
program 'without concern for the ultimate placement of data and instructions; these program elements can be
repositioned after the program has been tested and after the system's memory layout is final. The relocation
feature is fully explained in Chapter 4 of this manual.
Program Counter
With the program counter, we reach the first of the 8080's internal registers illustrated in Figure 1-3.
NOTE
Except for the differences listed at the end of this chapter,
the information in this chapter applies equally to the 8080
and the 8085.
The program counter keeps track of the next instruction byte to be fetched from memory (which may be either
ROM or RAM). Each time it fetches an instruction byte from memory, the processor increments the program
counter by one. Therefore, the program counter always indicates the next byte to be fetched. This process
continues as long as program instructions are executed sequentially . To alter the flow of program execution as
with a jump instruction or a call to a subroutine, the processor overwrites the current contents of the program
counter with the address of the new instruction. The next instruction fetch occurs from the new address.
IACCUMULATORI
INSTRUCTION
DECODER
DATA BUS LATCH
8080
8085
FLAGS
LOW
B
C
STACK
POINTER
D
E
PROGRAM
COUNTER
H
L
ADDRESS
BUS LATCH
8-bit
bidirectional
data bus
16-bit
address bus
ROM
RAM
INSTRUCTIONS
INSTRUCTIONS
CONSTANT
DATA
VARIABLE
DATA
STACK
INPUT
PORTS
Figure 1-3. 8080/8085 Internal Registers
1-6
HIGH
OUTPUT
PORTS
Chapter 1. Assembly Language and Processors
Work Registers
The 8080 provides an 8-bit accumulator and six other general purpose work registers, as shown in Figure 1-3.
Programs reference these registers by the letters A (for the accumulator), B, C, D, E, H, and L. Thus, the
instruction ADD B may be interpreted as 'add the contents of the B register to the contents of the accumulator.
Some instructions reference a pair of registers as shown in the following:
Symbolic Reference
B
D
H
M
PSW
Registers Referenced
Band C
D and E
Hand L
Hand L (as a memory reference)
A and condition flags (explained
later in this section)
The symbolic reference for a single register is often the same as for a register pair. The instruction to be executed
determines how the processor interprets the reference. For example, ADD B is an 8-bit operation. By contrast
PUSH B (which pushes the contents of the Band C registers onto the stack) is a 16-bit operation.
Notice that the letters Hand M both refer to the Hand L register pair. The choice of which to use depends on
the instruction. Use H when an instruction acts upon the Hand L register pair as in INX H (increment the
contents of Hand L by one). Use M when an instruction addresses memory via the Hand L registers as in ADD
M (add the contents of the memory location specified by the Hand L registers to the contents of the accumulator) .
The general purpose registers B, C, D, E, H, and L can provide a wide variety of functions such as storing 8-bit
data values, storing intermediate results in arithmetic operations, and storing 16-bit address pointers. Because of
the 8080's extensive instruction set, it is usually possible to achieve a common result with any of several
different instructions. A simple add to the accumulator, for example, can be accomplished by more than half a
dozen different instructions. When possible, it is generally desirable to select a register-to-register instruction
such as ADD B. These instructions typically require only one byte of program storage. Also, using data already
present in a register eliminates a memory access and thus reduces the time required for the operation.
The accumulator also acts as a general-purpose register, but it has some special capabilities not shared with the
other registers. For example, the input/output instructions IN and OUT transfer data only between the accumulator and external I/O devices. Also, many operations involving the accumulator affect the condition flags as explained in the next section.
Example:
The following figures illustrate the execution of a move instruction. The MOV M,C moves a copy of the contents
of register C to the memory location specified by the Hand L registers. Notice that this location must be in
RAM since data is to be written to memory.
1-7
Chapter 1. Assembly language and Processors
IACCUMULATORI
FLAGS
HIGH
INSTRUCTION
DECODER
I
I
Y
DATA BUS LATCH
I
~
I
ROM
•
B
I
C
D
I
E
H
I
L
I
I
I
LOW
STACK
!
POINTER
PROGRAM
Ii
COUNTER
ADDRESS
I
BUS LATCH
8080
8085
I
RAM
Figure 1-4. Instruction Fetch
The processor initiates the instruction fetch by latching the contents of the program counter on the address bus,
and then increments the program counter by one to indicate the address of the next instruction byte. When the
memory responds, the instruction is decoded into the series of actions shown in Figure 1-5.
NOTE
The following description of the execution of the
MOV M,C instruction is conceptually correct, but
does not account for normal bus control. For details
concerning memory interface, refer to the User's
Manual for your processor.
1-8
Chapter 1. Assembly Language and Processors
8080
8085
IACCUMULATORI
I
[
INSTRUCTION
DECODER
L.DAT A BUS LATCH
I
J.J I
FLAGS
I
B
C
I
I
I
D
H
E
L
I
I
I
LOW
HIGH
I
STACK
!
POINTER
I
PROGRAM
!
COUNTER
ADDRESS
:
BUS LATCH
I
I
I
f
t
ROM
RAM
•
Figure 1-5. Execution of MOV M,C Instruction
To execute the MOV M,C instruction, the processor latches the contents of the C register on the data bus and
the contents of the Hand L registers on the address bus. When the memory accepts the data, the processor
terminates execution of this instruction and initiates the next instruction fetch.
Internal Work Registers
Certain operations are destructive. For example, a compare is actually a subtract operation; a zero result indicates
that the opreands are equal. Since it is unacceptable to destroy either of the operands, the processor includes
several work registers reserved for its own use. The programmer cannot access these registers. These registers are
used for internal data transfers and for preserving operands in destructive operations.
Condition Flags
The 8080 provides five flip flops used as condition flags. Certain arithmetic and logical instructions alter one or
more of these flags to indicate the result of an operation. Your program can test the setting of four of these
flags {carry, sign, zero, and parity} using one of the conditional jump, call, or return instructions. This allows you
to alter the flow of program execution based on the outcome of a previous operation. The fifth flag, auxiliary
carry, is reserved for the use of the DAA instruction, as will be explained later in this section.
It is important for the programmer to know which flags are set by a particular instruction. Assume, for example,
that your program is to test the parity of an input byte and then execute one instruction sequence if parity is
even, a different instruction set if parity is odd. Coding a J PE (jump if parity is even) or J PO (jump if parity is
1-9
Chapter 1. Assembly Language and Processors
odd) instruction immediately following the IN (input) instruction produces false results since the IN instruction
does not affect the condition flags. The jump executed by your program reflects the outcome of some previous
operation unrelated to the IN instruction. For the operation to work correctly, you must include some instruction that alters the parity flag after the IN instruction, but before the jump instruction. For example, you can
add zero to the accumulator. This sets the parity flag without altering the data in the accumulator.
In other cases, you will want to set a flag with one instruction, but then have a number of intervening instructions before you use it. In these cases, you must be certain that the intervening instructions do not affect the
desired flag.
The flags set by each instruction are detailed in the individual instruction descriptions in Chapter 3 of this
manual.
NOTE
When a flag is 'set' it is set ON (has the value one);
when a flag is 'reset' it is reset OF F (has the value
zero).
Carry Flag
As its name implies, the carry flag is commonly used to indicate whether an addition causes a 'carry' into the
next higher order digit. The carry flag is also used as a 'borrow' flag in subtractions, as explained under 'Two's
Complement Representation of Data' in Chapter 2 of this manual. The carry flag is also affected by the logical
AND, OR, and exclusive OR instructions. These instructions set ON or OFF particular bits of the accumulator.
See the descriptions of the ANA, ANI, ORA, ORI, XRA, and XRI instructions in Chapter 3.
The rotate instructions, which move the contents of the accumulator one position to the left or right, treat the
carry bit as though it were a ninth bit of the accumulator. See the descriptions of the RAL, RAR, RLC, and RRC
instructions in Chapter 3 of this manual.
Example:
Addition of two one-byte numbers can produce a carry out of the high-order bit:
Bit Number:
AE=
+74=
7654 3210
10101110
0111 0100
0010 0010 = 22 carry flag = 1
An addition that causes a carry out of the high order bit sets the carry flag to 1; an addition that does not cause
a carry resets the flag to zero.
Sign Flag
As explained under 'Two's Complement Representation of Data' in Chapter 2, bit 7 of a result in the accumulator
can be interpreted as a sign. Instructions that affect the sign flag set the flag equal to bit 7. A zero in bit 7
1-10
Chapter 1. Assembly language and Processors
indicates a positive value; a one indicates a negative value. This value is duplicated in the sign flag so that
conditional jump, call, and return instructions can test for positive and negative values.
Zero Flag
Certain instructions set the zero flag to one to indicate that the result in the accumulator contains all zeros.
These instructions, reset the flag to zero if the result in the accumulator is other than zero. A result that has a
carry and a zero result also sets the zero bit as shown below:
10100111
+01 01 1001
Carry Flag = 1
Zero Flag = 'I
0000 0000
Parity Flag
Parity is determined by counting the number of one bits set in the result in the accumulator. Instructions that
affect the parity flag set the flag to one for even parity and reset the flag to zero to indicate odd parity.
Auxiliary Carry Flag
The auxiliary carry flag indicates a carry out of bit 3 of the accumulator. You cannot test this flag directly in
your program; it is present to enable the DAA (Decimal Adjust Accumulator) to perform its function.
The auxiliary carry flag and the DAA instruction allow you to treat the value in the accumulator as two 4-bit
binary coded decimal numbers. Thus, the value 0001 1001 is equivalent to 19. (If this value is interpreted as a
binary number, it has the value 25.) Notice, however, that adding one to this value produces a non-decimal
result:
00011001
+0000 0001
0001 1010 = 1 A
The DAA instruction converts hexadecimal values such as the A in the preceding example back into binary coded
decimal (BCD) format. The DAA instruction requires the auxiliary carry flag since the BCD format makes it
possible for arithmetic operations to generate a carry from the low-order 4-bit digit into the high-order 4-bit
digit. The DAA performs the following addition to correct the preceding example:
0001 1010
+0000 0110
0001 0000
+0001 0000 (auxiliary carry)
0010 0000
==
20
1-11
Chapter 1. Assembly Language and Processors
The auxiliary carry flag is affected by all add, subtract, increment, decrement, compare, and all logical AND,
OR, and exclusive OR instructions. (See the descriptions of these instructions in Chapter 3.) There is some
difference in the handling of the auxiliary carry flag by the logical AND instructions in the 8080 processor and
the 8085 processor. The 8085 logical AND instructions always set the auxiliary flag ON. The 8080 logical AND
instructions set the flag to reflect the logical OR of bit 3 of the values involved in the AND operation.
Stack and Stack Pointer
To understand the purpose and effectiveness of the stack, it is useful to understand the concept of a subroutine.
Assume that your program requires a multiplication routine. (Since the 8080 has no multiply instructions, this
can be performed through repetitive addition. For example, 3x4 is equivalent to 3+3+3+3.) Assume further that
your program needs this multiply routine several times. You can recode this routine inline each time it is needed,
but this can use a great deal of memory. Or, you can code a subroutine:
Inline Coding
1
inline routine
I
I
I
Subroutine
1
I
I
I
CALL
inline routine
CALL
inline routine
CALL
subroutine
The 8080 provides instructions that call and return from a subroutine. When the call instruction is executed, the
address of the next instruction (the contents of the program counter) is pushed onto the stack. The contents of
the program counter are replaced by the address of the desired subroutine. At the end of the subroutine, a
return instruction pops that previously-stored address off the stack and puts it back into the program counter.
Program execution then continues as though the subroutine had been coded inline.
The mechanism that makes this possible is, of course, the stack. The stack is simply an area of random access
memory addressed by the stack pointer. The stack pointer is a hardware register maintained by the processor.
However, your program must initialize the stack pointer. This means that your program must load the base
address of the stack into the stack pointer. The base address of the stack is commonly assigned to the highest
available address in RAM. This is because the stack expands by decrementing the stack pointer. As items are
1-12
Chapter 1. Assembly Language and Processors
added to the stack, it expands into memory locations with lower addresses. As items are removed from the
stack, the stack pointer is incremented back toward its base address. Nonetheless, the most recent item on the
stack is known as the 'top of the stack.' Stack is still a most descriptive term because you can always put
something else on top of the stack. In terms of programming, a subroutine can call a subroutine, and so on.
The only limitation to the number of items that can be added to the stack is the amount of RAM available for
the stack.
The amount of RAM allocated to the stack is important to the programmer. As you write your program, you
must be certain that the stack will not expand into areas reserved for other data. For most applications, this
means that you must assign data that requires RAM to the lowest RAM addresses available. To be more precise,
you must count up all instructions that add data to the stack. Ultimately, your program should remove from
the stack any data it places on the stack. Therefore, for any instruction that adds to the stack, you can subtract any intervening instruction that removes an item from the stack. The most critical factor is the maximum
size of the stack. Notice that you must be sure to remove data your program adds to the stack. Otherwise, any
left-over items on the stack may cause the stack to grow into portions of RAM you intend for other data.
Stack Operations
Stack operations transfer sixteen bits of data between memory and a pair of processor registers. The two basic
operations are PUSH, which adds data to the stack, and POP, which removes data from the stack.
A call instruction pushes the contents of the program counter (which contains the address of the next instruction)
onto the stack and then transfers control to the desired subroutine by placing its address in the program counter.
A return instruction pops sixteen bits off the stack and places them in the program counter. This requires the
programmer to keep track of what is in the stack. For example, if you call a subroutine and the subroutine
pushes data onto the stack, the subroutine must remove that data before executing a return instruction. Otherwise, the return instruction pops data from the stack and places it in the program counter. The results are
unpredictable, of course, but probably not what you want.
Saving Program Status
It is likely that a subroutine requires the use of one or more of the working registers. However, it is equally
likely that the main program has data stored in the registers that it needs when control returns to the main
program. As general rule, a subroutine should save the contents of a register before using it and then restore
the contents of that register before returning control to the main program. The subroutine can do this by
pushing the contents of the registers onto the stack and then popping the data back into the registers before
executing a return. The following instruction sequence saves and restores all the working registers. Notice that
the POP instructions must be in the opposite order of the PUSH instructions if the data is to be restored to its
original location.
1-13
Chapter 1. Assembly Language and Processors
SUBRTN:
PUSH
PUSH
PUSH
PUSH
PSW
B
D
H
subroutine coding
POP
H
POP
D
POP
B
POP
PSW
RETURN
The letters B, D, and H refer to the Band C, D and E, and Hand L register pairs, respectively. PSW refers to
the program status word. The program status word is a 16-bit word comprising the contents of the accumulator
and the five conpition flags. (PUSH PSW adds three bits of filler to expand the condition flags into a full
byte; POP PSW strips out these filler bits.)
Input/Output Ports
The 256 input/output ports provide communication with the outside world of peripheral devices. The IN and
OUT instructions initiate data transfers.
The IN instruction latches the number of the desired port onto the address bus. As soon as a byte of data is
returned to the data bus latch, it is transferred into the accumulator.
The OUT instruction latches the number of the desired port onto the address bus and latches the data in the
accumulator onto the data bus.
The specified port number is duplicated on the address bus. Thus, the instruction IN 5 latches the bit configuration 0000 0101 0000 0101 onto the address bus.
Notice that the IN and OUT instructions simply initiate a data transfer. It is the responsibility of the peripheral
device to detect that it has been addressed. Notice also that it is possible to dedicate any number of ports to
the same peripheral device. You might use a number of ports as control signals, for example.
Because input and output are almost totally application dependent, a discussion of design techniques is beyond
the scope of this manual.
For additional hardware information, refer to the 8080 or 8085 Microcomputer Systems User's Manual.
For related programming information, see the descriptions of the IN, OUT, DI, EI, RST, and RIM and SIM
instructions in Chapter 3 of this manual. (The RIM and SIM instructions apply only to the 8085.)
1~14
Chapter 1. Assembly Language and Processors
Instruction Set
The 8080 incorporates a powerful array of instructions. This section provides a general overview of the instruction set. The detailed operation of each instruction is described in Chapter 3 of this manual.
Addressing Modes
Instructions can be categorized according to their method of addressing the hardware registers and/or memory.
Implied Addressing. The addressing mode of certain instructions is implied by the instruction's function. For
example, the STC (set carry flag) instruction deals only with the carry flag; the DAA (decimal adjust accumuIa.tor) instruction deals with the accumulator.
Register Addressing. Quite a large set of instructions call for register addressing. With these instructions, you
must specify one of the registers A through E, H or L as well as the operation code. With these instructions,
the accumulator is implied as a second operand. For example, the instruction CMP E may be interpreted as
'compare the contents of the E register with the contents of the accumulator.'
Most of the instructions that use register addressing deal with 8-bit values. However, a few of these instructions
deal with 16-bit register pairs. For example, the PCHL instruction exchanges the contents of the program counter
with the contents of the Hand L registers.
Immediate Addressing. Instructions that use immediate addressing have data assembled as a part of the instruction
itself. For example, the instruction CPI 'e' may be interpreted as 'compare the contents of the accumulator with
the letter C.' When assembled, this instruction has the hexadecimal value FE43. Hexadecimal 43 is the internal
representation for the letter C. When this instruction is executed, the processor fetches the first instruction byte
and determines that it must fetch one more byte. The processor fetches the next byte into one of its internal
registers and then performs the compare operation.
Notice that the names of the immediate instructions indicate that they use immediate data. Thus, the name of an
add instruction is ADD; the name of an add immediate instruction is ADI.
All but two of the immediate instructions use the accumulator as an implied operand, as in the CPI instruction
shown previously. The MVI (move immediate) instruction can move its immediate data to any of the working
registers, including the accumulator, or to memory. Thus, the instruction MVI D,OFFH moves the hexadecimal
value FF to the 0 register.
The LXI instruction (load register pair immediate) is even more unusual in that its immediate data is a 16-bit
value. This instruction is commonly used to load addresses into a register pair. As mentioned previously, your
program must initialize the stack pointer; LXI is the instruction most commonly used for this purpose. For example, the instruction LXI SP,30FFH loads the stack pointer with the hexadecimal value 30FF.
Direct Addressing. Jump instructions include a 16-bit address as part of the instruction. For example, the
instruction J MP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the
program counter with the new value 1000.
1-15
Chapter 1. Assembly Language and Processors
Instructions that include a direct address require three bytes of storage: one for the instruction code, and two
for the 16-bit address.
Register indirect instructions reference memory via a register pair. Thus, the
instruction MOV M,C moves the contents of the C register into the memory address stored in the Hand L
register pair. The instruction LDAX B loads the accumulator with the byte of data specified by the address
in the Band C register pair.
Register Indirect Addressing.
Combined Addressing Modes. Some instructions use a combination of addressing modes. A CALL instruction,
for example, combines direct addressing and register indirect addressing. The direct address in a CALL instruction
specifies the address of the desired subroutine; the register indirect address is the stack pointer. The CALL
instruction pushes the current contents of the program counter into the memory location specified by the stack
pointer.
Timing Effects of Addressing Modes. Addressing modes affect both the amount of time required for executing
an instruction and the amount of memory required for its storage. For example, instructions that use implied or
register addressing execute very quickly since they deal directly with the processor hardware or with data already
present in hardware registers. More important, however, is that the entire instruction can be fetched with a
single memory access. The number of memory accesses required is the single greatest factor in determining
execution timing. More memory accesses require more execution time. A CALL instruction, for example, requires
five memory accesses: three to access the entire instruction, and two more to push the contents of the program
cou nter onto the stack.
The processor can access memory once during each processor cycle. Each cycle comprises a variable number of
states. (The individual instruction descriptions in Chapter 3 specify the number of cycles and states required for
each instruction.) The length of a state depends on the clock frequency specified for your system, and may
range from 480 nanoseconds to 2 microseconds. Thus, the timing of a four state instruction may range from
1.920 microseconds through 8 microseconds. (The 8085 has a maximum clock frequency of 5 MHz and therefore a
minimum state length of 200 nanoseconds.)
Instruction Naming Conventions
The mnemonics assigned to the instructions are designed to indicate the function of the instruction. The instructions fall into the following functional categories:
Data Transfer Group. The data transfer instructions move data between registers or between memory and
registers.
MOV
MVI
LDA
STA
LHLD
SHLD
Move
Move
Load
Store
Load
Store
Immediate
Accumulator Directly from Memory
Accumulator Directly in Memory
Hand L Registers Directly from Memory
Hand L Registers Directly in Memory
ALL MNEMONICS © 7974, 7975, 7976, 7977 INTEL CORPORA nON
1-16
Chapter 1. Assembly language and Processors
An 'X' in the name of a data transfer instruction implies that it deals with a register pair:
LXI
LDAX
STAX
XCHG
XTHL
Load Register Pair with Immediate data
Load Accumulator from Address in Register Pair
Store Accumulator in Address in Register Pair
Exchange Hand L with D and E
Exchange Top of Stack with Hand L
Arithmetic Group. The arithmetic instructions add, subtract, increment, or decrement data in registers or
memory.
ADD
ADI
ADC
ACI
SUB
SUI
SBB
SBI
INR
DCR
INX
DCX
DAD
Add to Accumulator
Add Immediate Data to Accumulator
Add to Accumulator Using Carry Flag
Add Immediate Data to Accumulator Using Carry Flag
Subtract from Accumulator
Subtract Immediate Data from Accumulator
Subtract from Accumulator Using Borrow ((:arry) Flag
Subtract Immediate from Accumulator Using Borrow
Increment Specified Byte by One
Decrement Specified Byte by One
Increment Register Pair by One
Decrement Register Pair by One
Add Contents of Register
Double Register Add:
Pair to Hand L Register Pair
l.ogical Group. This group performs logical (Boolean) operations on data in registers and memory and on
condition flags.
The logical AND, OR, and Exclusive OR instructions enable you to set specific bits in the accumulator ON or
OFF.
ANA
ANI
ORA
ORI
XRA
XRI
Logical AND with Accumulator
Logical AND with Accumulator Using Immediate Data
Logical OR with Accumulator
Logical OR with Accumulator Using Immediate Data
Exclusive Logical OR with Accumulator
Exclusive OR Using Immediate Data
The compare instructions compare the contents of an 8-bit value with the contents of the accumulator:
CMP
CPI
Compare
Compare Using Immediate Data
ALL MNEMONICS © 1974, 1975, 1976, 1977 INTEL CORPORATION
1-17
Chapter 1. Assembly Language and Processors
The rotate instructions shift the contents of the accumulator one bit position to the left or right:
RLC
RRC
RAL
RAR
Rotate
Rotate
Rotate
Rotate
Accumulator Left
Accumulator Right
Left Through Carry
Right Through Carry
Complement and carry flag instructions:
CMA
CMC
STC
Complement Accumulator
Complement Carry Flag
Set Carry Flag
Branch Group. The branching instructions alter normal sequential program flow, either unconditionally or
conditionally. The unconditional branching instructions are as follows:
JMP
CALL
RET
Jump
Call
Return
Conditional branching instructions examine the status of one of four condition flags to determine whether the
specified branch is to be executed. The conditions that may be specified are as follows:
NZ
Z
NC
C
PO
PE
P
M
Not Zero (Z = 0)
Zero (Z = 1)
No Carry (C = 0)
Carry (C = 1)
Parit y Odd (P = 0)
Parity Even (P = 1)
Plus (S = 0)
Minus (S = 1)
Thus, the conditional branching instructions are specified as follows:
jumps
Calls
Returns
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
CC
CNC
CZ
CNZ
CP
CM
CPE
CPO
RC
RNC
RZ
RNZ
RP
RM
RPE
RPO
(Carry)
(No Carry)
(Zero)
(Not Zero)
(Plus)
(Minus)
(Parity Even)
(Parity Odd)
Two other instructions can effect a branch by replacing the contents of the program counter:
PCHL
RST
Move Hand L to Program Counter
Special Restart Instruction Used with Interrupts
ALL MNEMONICS © 1974, 1975, 1976, 1977 INTEL CORPORA nON
<1-18
Chapter 1. Assembly Language and Processors
Stack, I/O, and Machine Control Instructions. The following instructions affect the stack and/or stack pointer:
PUSH
POP
XTHL
SPHL
Push Two Bytes of Data onto the Stack
Pop Two Bytes of Data off the Stack
Exchange Top of Stack with Hand L
Move contents of Hand L to Stack Pointer
The I/O instructions are as follows:
IN
OUT
Initiate Input Operation
Initiate Output Operation
The machine control instructions are as follows:
EI
01
HLT
NOP
Enable Interrupt System
Disable Interrupt System
Halt
No Operation
HARDWARE/INSTRUCTION SUMMARY
The following illustrations graphically summarize the instruction set by showing the hardware acted upon by
specific instructions. The type of operand allowed for each instruction is indicated through the use of a code.
When no code is given, the instruction does not allow operands.
Code
Meaning
REGM 8
The operand may specify one of the 8-bit registers A,B,C,D,E,H, or L or M
(a memory reference via the 16-bit address in the Hand L registers). The
MOV instruction, which calls for two operands, can specify M for only one
of its operands.
Designates 8-bit immediate operand.
Designates a 16-bit address.
Designates an 8-bit port number.
Designates a 16-bit register pair (B&C,D&E, H& L, or SP).
Designates a 16-bit immediate operand.
Accumulator Instructions
The following illustration shows the instructions that can affect the accumulator. The instructions listed above
the accumulator all act on the data in the accumulator, and all except CMA (complement accumulator) affect
one or more of the condition flags. The instructions listed below the accumulator move data into or out of the
accumulator, but do not affect condition flags. The STC (set carry) and CMC (complement carry) instructions
are also shown here.
ALL MNEMONICS © 1974, 1975, 1976, 1977 INTEL CORPORATION
1-19
Chapter 1. Assembly Language and Processors
ADD
AOC
SUB
SBB
ANA
REGM g
XRA
ORA
CMP
RLC
RAR
RAL
CMA
INR)
OCR
MOV REGM g ., REGM g
FLAGS
B
C
1 . . - 1_
_
LOAX}
STAX BC,OE
Og
REGM g
ACCUMULATOR
STC CMC
LOW
STACK
POINTER
L
MEMORY
AJ6
STACK
ALL MNEMONICS © 7974, 7975, 7976, 7977 INTEL CORPORATION
1-20
HIGH
I PROGRAM
E _ _--'
0_ _-----1._ _ _
_
H
LOA}
STA
AOI
ACI
SUI
SBI
ANI
XRI
ORI
CPI
RRC
OAA
I
I
IN Pg
OUT Pg
INPUT
PORTS
OUTPUT
PORTS
COUNTER
I
Chapter 1. Assembly Language and Processors
Register Pair (Word) Instructions
The following instructions all deal with 16-bit words. Except for DAD (which adds thecontents of the B&C or
D& E register pair to H& L), none of these instructions affect the condition flags. DAD affects only the carry
flag.
IACCUMULATORI
FLAGS
I
C
I
B
INX)
DCX
HIGH
REG
DAD
-~
D
E
H
L
I~XCHG
16
SPHL .... \ STACK
I
LOW
POINTER
PCHL .. PROGRAM! COUNTER
...--
I
XTHL
LHLD
SHLD
I
MEMORY
1--------STACK
I .....
~---
PUSH } B,D,H,PSW
POP
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Chapter 1. Assembly Language and Processors
Branching Instructions
The following instructions can alter the contents of the program counter, thereby altering the normal sequential
execution flow. Jump instructions affect only the program counter. Call and Return instructions affect the
program counter, stack pointer, and stack.
IACCUMULATORI
FLAGS
B
C
r----:-----,---:------,~---JI
HIGH
LOW
STACK
POINTER
PROGRAM
COUNTER
RST
PCHL
CALL
JMP
RET
~~ ~~~} ~~ ~~~} :~ :~~}
J P JM
J PE J PO
MEMORY
1----------STACK
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1-22
A
16 CP CM
CPE CPO
A
16 RP RM
RPE RPO
CONTROL INSTRUCTIONS
RST
NOP
HLT
EI
DI
SIM\
RIM} 8085 only
A
16
Chapter 1. Assembly Language and Processors
I nstruction Set Guide
The following is a summary of the instruction set:
ADD
ADI
ADC
SUB
SBB
ACI
SUI
SBI
REGM 8
ANA
ANI
XRI
ORI
CPI
XRA
ORA
CMP
RLC
RAR
RAL RRC
CMA DAA
INR} REGM
DCR
8
r--1ACCUMULATORI
MOV REGM 8 ,REGM 8 1
I
I
LXI REG 16 ,D l 6.
D8
FLAGS
B
I
C
D
I
E
H
L
ISTC CMC
HIGH
INX}
IDCX REG 16
STACK
~XCHG
RST
CALL
JMP
JC
JZ
JP
JPE
A
,r--
LDAX}
STAX
LDA}
STA
,
~~~}
A
JM
16
JPO
OUT P
8
BC,DE
INPUT
PORTS
OUTPUT
PORTS
A
16
MVI
D8
MOV REGM 8 ,REGM 8
CODE
REGM
RET
CC
CZ
CP
CNC}
RC
CNZ
A
RZ
CM
16 RP
CPE CPO
RPE
RNC}
RNZ A
RM
16
RPO
I
LHLD}
STHD
A 16
MEMORY
LOW
>---STAC"K--- I+~ ~~H }
B,D,H,P5W
CONTROL
INSTRUCTIONS
RST
NOP
HLT
EI
DI
SIM}
RIM
8085 ONLY
MEANING
8
The operand may specify one of the 8-bit registers A,B,C,D,E,H, or L or M (a memory
reference via the 16-bit address in the Hand L registers). The MOV instruction, which
calls for two operands, can specify M for only one of its operands.
Designates 8-bit immediate operand.
Designates a 16-bit address.
Designates an 8-bit port number.
Designates a 16-bit register pair (B&C,D&E,H&L,or SP).
Designates a 16 -bit immediate operand.
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Chapter 1.
Assembly Language and Processors
8085 PROCESSOR DIFFERENCES
The differences between the 8080 processor and the 8085 processor will be more obvious to the system designer
than to the programmer. Except for two additional instructions, the 8085 instruction set is identical to and fully
compatible with the 8080 instruction set. Most programs written for the 8080 should operate on the 8085 without modification. The only programs that may require changes are those with critical timing routines; the higher
system speed of the 8085 may alter the time values of such routines.
A partial listing of 8085 design features includes the following:
•
•
•
•
•
•
A single 5 volt power supply.
Execution speeds ap'proximately 50% faster than the 8080.
Incorporation in the processor of the features of the 8224 Clock Generator and Driver and the
8228 System Controller and Bus Driver.
A non-maskable TRAP interrupt for handling serious problems such as power failures.
Three separately maskable interrupts that generate internal RST instructions.
Input/output lines for serial data transfer.
Programming for the 8085
For the programmer, the new features of the 8085 arc summarized in the two new instructions SIM and RIM.
These instructions differ from 'the 8080 instructions in that each has multiple functions. The SIM instruction
sets the interrupt mask and/or writes out a bit of serial data. The programmer must place the desired interrupt
mask and/or serial output in the accumulator prior to execution of the SIM instruction. The RIM instruction
reads a bit of serial data if one is present dnd the interrupt mask into the accumulator. Details of these instructions arc covered in Chapter 3.
Despite the new interrupt features of the 8085, programming for interrupts is li11le changed. Notice, however, that
8085 hardware interrupt RESTART addresses fall between the existing 8080 RESTART addresses. Therefore,
only four bytes are available for certain RST instructions. Also, the TRAP interrupt input is non-maskable and
cannot be disabled. If your application uses this input, be certain to provide dn interrupt routine for it.
The interrupts have the following priority:
TRAP
RST7.5
RST6.5
RST5.5
INTR
highest
lowest
When more than one interrupt is pending, the processor always recognizes the higher priority interrupt first.
These priorities apply only to the sequence in which interrupts arc recognized. Program routines that service
interrupts have no special priority. Thus, an RST5.5 interrupt can interrupt the service routine for an RST7.5
interrupt. If you want to protect a service routine from interruption, either disable the interrupt system (DI
instruction), or mask out other potential interrupts (SIM instruction).
1-24
Chapter 1. Assembly Language and Processors
Conditional Instructions
Execution of conditional instructions on the 8085 differs from the 8080. The 8080 fetches all three instruction
bytes whether or not the condition is satisfied. The 8085 evaluates the condition while it fetches the second
instruction byte. If the specified condition is not satisfied, the 8085 skips over the third instruction byte and
immediately fetches the next instruction. Skipping the unnecessary byte allows for faster execution.
1-25
2. ASSEMBLY LANGUAGE CONCEPTS
INTRODUCTION
Just as the English language has its rules of grammar, assembly language has certain coding rules. The source line
is the assembly language equivalent of a sentence.
This assembler recognizes three types of source lines: instructions, directives, and controls. This manual describes
instructions and directives. Controls are described in the operator's manual for your version of the assembler.
This chapter describes the general rules for coding source lines. Specific instructions (see Chapter 3) and
directives (see Chapters 4 and 5) may have specific coding rules. Even so, the coding of such instructions and
directives must conform to the general rules in this chapter.
SOURCE LINE FORMAT
Assembly language instructions and assembler directives may consist of up to four fields, as follows:
Label:}
{ Name
Opcode
Operand
;Comment
The fields may be separated by any number of blanks, but must be separated by at least one delimiter. Each
instruction and directive must be entered on a single line terminated by a carriage return and a line feed. No
continuation lines are possible, but you may havc lines consisting entirely of comments.
Character Set
The following characters are legal in assembly language source statements:
•
The letters of the alphabet, A through Z. Both upper- and lower-case letters are allowed. Internally,
the assembler treats all lettcrs as though they were upper-case, but the characters are printed exactly
as they were input in the assembly listing.
•
The digits 0 through 9.
•
The following special characters:
2-1
Chapter 2. Assembly language Concepts
Character
+
*
&
$
@
<
>
%
blank
CR
FF
HT
•
Meaning
Plus sign
Minus sign
Asterisk
Slash
Comma
Left parenthesis
Right parenthesis
Single quote
Ampersand
Colon
Dollar sign
Commercial 'at' sign
Question mark
Equal sign
Less than sign
Greater than sign
Percent sign
Exclamation point
Blank or space
Semicolon
Period
Carriage return
Form feed
Horizontal tab
In addition, any ASCII character may appear in a string enclosed in single quotes or in a comment.
Delimiters
Certain characters have special meaning to the assembler in that they function as delimiters. Delimiters define
the end of a source statement, a field, or a component of a field. The following list defines the delimiters
recognized by the assembler. Notice that many delimiters are related to the macro feature explained in Chapter
5. Delimiters used for macros are shown here so that you will not accidentally use a delimiter improperly.
Refer to Chapter 5 for a description of macros.
2-2
Chapter 2. Assembly Language Concepts
Character(s)
blank
Meaning
Use
one or more
blanks
field separator or symbol terminator
comma
separate operands in the operands field,
including macro parameters
pair of single
quote characters
delimit a character string
pair of parentheses
delimit an expression
CR
carriage return
statement terminator
HT
horizontal tab
field separator or symbol terminator
semicolon
comment field delimiter
colon
delimiter for symbols used as labels
ampersand
delimit macro prototype text or formal
parameters for concatenation
pair of angle
brackets
delimit macro parameter text which
contains commas or embedded blanks;
also used to delimit a parameter list
(... )
&
<... >
%
percent sign
delimit a macro parameter that is to be
evaluated prior to substi.tution
..
"
exclamation
point
an escape character used to pass the
following character as part of a macro
parameter when the character might
otherwise be interpreted as a delimiter
double semicolon
delimiter for comments in macro definitions
when the comment is to be suppressed when
the macro is expanded
Label/Name Field
Labels are always optional. An instruction label is a symbol name whose value is the location where the instruction is assembled. A label may contain from one to six alphanumeric characters, but the first character must be
alphabetic or the special characters "?' or '@'. The label name must be terminated with a colon. A symbol used
as a label can be defined only once in your program. (See 'Symbols and Symbol TabJes' later in this chapter.)
2-3
Chapter 2. Assembly language Concepts
Alphanumeric characters include the letters of the alphabet, the question mark character, and the decimal
digits 0 through 9.
A name is required for the SET, EQU, and MACRO directives. Names follow the same coding rules as labels,
except that they must be terminated with a blank rather than a colon. The label/name field must be empty for
the LOCAL and ENDM directives.
Opcode Field
This required field contains the mnemonic operation code for the 8080/8085 instruction or assembler directive
to be performed.
Operand Field
The operand field identifies the data to be operated on by the specified opcode. Some instructions require no
operands. Others require one or two operands. As a general rule, when two operands are required (as in data
transfer and arithmetic operations), the first operand identifies the destination (or target) of the operation's
result, and the second operand specifies the source data.
Examples:
MOV
MVI
A,C
A,'B'
;MOVE CONTENTS OF REG C TO ACCUMULATOR
;MOVE B TO ACCUMULATOR
Comment Field
The optional comment field may contain any information you deem useful for annotating your program. The
only coding requirement for this field is that it be preceded by a semicolon. Because the semicolon is a delimiter,
there is no need to separate the comment from the previous field with one or more spaces. However, spaces are
commonly used to improve the readability of the comment. Although comments are always optional, you should
use them liberally since it is easier to debug and maintain a well documented program.
CODING OPERAND FIELD INFORMATION
There are four types of information (a through d in the following list) that may be requested as items in the
operand field; the information may be specified in nine ways, each of which is described below.
2-4
Chapter 2. Assembly Language Concepts
OPERAND FIELD INFORMATION
Information required
Ways of specifying
(a)
(b)
(c)
(d)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Register
Register Pair
Immediate Data
16-bit Address
Hexadecimal Data
Decimal Data
Octal Data
Binary Data
Location Counter ($)
ASCII Constant
Labels assigned values
Labels of instructions or data
Expressions
Each hexadecimal number must begin with a numeric digit (0 through 9) and must be
followed by the letter H.
Hexadecimal Data.
Label
Opcode
Operand
Comment
HERE:
MVI
C,OBAH
;LOAD REG C WITH HEX BA
Each decimal number may be identified by the letter D immediately after its last digit or may
stand alone. Any number not specifically identified as hexadecimal, octal, or binary is assumed to be decimal.
Thus, the following statements are equivalent:
Decimal Data.
Octal Data.
Binary Data.
Label
Opcode
Operand
Comment
ABC:
MVI
MVI
E,lS
E,15D
;LOAD E WITH 15 DECIMAL
Each octal number must be followed by the letter 0 or the letter Q.
Label
Opcode
Operand
Comment
LABEL:
MVI
A,72Q
;LOAD OCTAL 72 INTO ACCUM
Each binary number must be followed by the letter B.
Label
Opcode
Operand
Comment
NOW:
MVI
D,1111011 OB
;LOAD REGISTER D
;WITH OF6H
2-5
Chapter 2. Assembly Language Concepts
Location Counter. The $ character refers to the current location counter. The location counter contains the
address where the current instruction or data statement will be assembled.
Label
Opcode
Operand
Comment
GO:
JMP
$+6
;J UMP TO ADDRESS 6 BYTES BEYOND
;THE FIRST BYTE OF THIS
;INSTRUCTION
ASCII Constant. One or more ASCII characters enclosed in single quotes define an ASCII constant. Two
successive single quotes must be used to represent one single quote within an ASCII constant.
Label
Opcode
Operand
Comment
MVI
E,'*'
;LOAD E REG WITH 8-81T ASCII
;REPRESENT ATION OF
DATE:
DB
*
'TODAY"S DATE'
Labels Assigned Values. The SET and EQU directives can assign values to labels. In the following example,
assume that VALUE has been assigned the value 9FH; the two statements are equivalent:
Label
Opcode
Operand
Al:
A2:
MVI
MVI
D,9FH
D,VALUE
Comment
Labels of Instruction or Data. The label assigned to an instruction or a data definition has as its value the
address of the first byte of the instruction or data. Instructions elsewhere in the program can refer to this
address by its symbolic label name.
Label
Opcode
Operand
Comments
HERE:
JMP
THERE
;JUMP TO INSTRUCTION AT THERE
THERE:
MVI
D,9FH
Expressions. All of the operand types discussed previously can be combined by operators to form an expression.
In fact, the example given for the location counter {$+6} is an expression that combines the location counter
with the decimal number 6.
Because the rules for coding expressions are rather extensive, further discussion of expressions is deferred until
later in this chapter.
2-6
Chapter 2. Assembly Language Concepts
Instructions as Operands. One operand type was intentionally omitted from the list of operand field information: Instructions enclosed in parentheses may appear in the operands field. The operand has the value of
the left-most byte of the assembled instruction.
Label
Opcode
Operand
INS:
DB
(ADD C)
The statement above defines a byte with the value 81 H (the object code for an ADD C instruction). Such
coding is typically used where the object program modifies itself during execution, a technique that is strongly
discouraged.
Register-Type Operands. Only instructions that allow registers as operands may have register-type operands.
Expressions containing register-type operands are flagged as errors. Thus, an instruction like
JMP A
is flagged as an illegal use of a register.
The only assembler directives that may contain register-type operands are EQU, SET, and actual parameters in
macro calls. Registers can be assigned alternate names only by EQU or SET.
TWO'S COMPLEMENT REPRESENTATION OF DATA
Any 8-bit byte contains one of the 256 possible combinations of zeros and ones. Any particular combination may
be interpreted in a number of ways. For example, the code 1 FH may be interpreted as an instruction (Rotate
Accumuiator Right Through Carry), as the hexadecimal value 1 F, the decimal value 31, or simply the bit
pattern 00011111.
Arithmetic instructions assume that the data bytes upon which they operate are in the 'two's complement'
format. To understand why, let us first examine two examples of decimal arithmetic:
35
-12
35
+88
23
123
Notice that the results of the two examples are equal if we disregard the carry out of the high order position in
the second example. The second example illustrates subtraction performed by adding the ten's complement of
the subtrahend (the bottom number) to the minuend (the top number). To form the ten's complement of a
decimal number, first subtract each digit of the subtrahend from 9 to form the nine's complement; then add one
to the result to form the ten's complement. Thus, 99-12=87; 87+1 =88, the ten's complement of 12.
The ability to perform subtraction with a form of addition is a great advantage in a computer since fewer circuits are required. Also, arithmetic operations within the computer are binary, which simplifies matters even more.
2-7
Chapter 2. Assembly Language Concepts
The processor forms the two's complement of a binary value simply by reversing the value of each bit and then
adding one to the result. Any carry out of the high order b~t is ignored when the complement is formed. Thus,
the subtraction shown previously is performed as follows:
35 = 001 0 0011
- 1 2 = 0000 11 00
= 1111
+
23
0010 0011
+1111 01 00
0011
1 0001 0111
= 23
1111 01 00
Again, by disregarding the carry out of the high order position, the subtraction is performed through a form of
addition. However, if this operation were performed by the 8080 or the 8085, the carry flag would be set OFF
at the end of the subtraction. This is because the processors complement the carry flag at the end of a subtract
operation so that it can be used as a 'borrow' flag in multibyte subtractions. In the example shown, no borrow
is required, so the carry flag is set OFF. By contrast, the carry flag is set ON if we subtract 35 from 12:
1 2 = 0000 11 00
-35 = 0010 0011 = 1101
0000 1100
+11011101
1100
+
1110 1001
11 01
= 233
or --105
1101
In this case, the absence of a carry indicates that a borrow is required from the next higher order byte, if any.
Therefore, the processor sets the carry flag ON. Notice also that the result is stored in a complemented form.
If you want to interpret this result as a decimal value, you must again form its two's complement:
111 0 1 001 = 0001
+
011 0
0001
01 11
= 23
Two's complement numbers may also be signed. When a byte is interpreted as a signed two's complement number,
the high order bit indicates the sign. A zero in this bit indicates a positive number, a one a negative number. The
seven low order bits provide the magnitude of the number. Thus, 0111 1111 equals + 127.
At the beginning of this description of two's complement arithmetic, it was stated that any 8-bit byte may contain one of the 256 possible combinations of zeros and ones. It must also be stated that the proper interpretation
of data is a programming responsibility.
As an example, consider the compare instruction. The compare logic considers only the raw bit values of the
items being compared. Therefore, a negative two's complement number always compares higher than a positive
number, because the negative number's high order bit is always ON. As a result, the meanings of the flags set by
the compare instruction are reversed. Your program must account for this condition.
2-8
Chapter 2. Assembly Language Concepts
SYMBOLS AND SYMBOL TABLES
Symbolic Addressing
If you have never done symbolic programming before, the following analogy may help clarify the distinction
between a symbolic and an absolute address.
The locations in program memory can be compared to a cluster of post office boxes. Suppose Richard Roe
rents box 500 for two months. He can then ask for his letters by saying 'Give me the mail in box 500,' or
'Give me the mail for Roe.' If Donald Smith later rents box 500, he too can ask for his mail by either box
number 500 or by his name. The content of the post office box can be accessed by a fixed, absolute address
(500) or by a symbolic, variable name. The postal clerk correlates the symbolic names and their absolute values
in his log book. The assembler performs the same function, keeping track of symbols and their values in a
symbol table. Note that you do not have to assign values to symbolic addresses. The assembler references its
location counter during the assembly process to calculate these addresses for you. (The location counter does
for the assembler what the program counter does for the microcomputer. It tells the assembler where the next
instruction or operand is to be placed in memory.)
Symbol Characteristics
A symbol can contain one to six alphabetic (A-Z) or numeric (0-9) characters (with the first character alphabetic)
or the special character '?' or '@'. A dollar sign can be used as a symbol to denote the value currently in the
location cou nter. For example, the command
JMP
$+6
forces a jump to the instruction residing six memory locations higher than the JMP instruction. Symbols of the
form 'nnnn' are generated by the assembler to uniquely name symbols local to macros.
The assembler regards symbols as having the following attributes: reserved or user-defined; global or limited;
permanent or redefinable; and absolute or relocatablc.
Reserved, User-Defined, and Assembler-Generated Symbols
Reserved symbols are those that already have special meaning to the assembler and therefore cannot appear as
user-defined symbols. The mnemonic names for machine instructions and the assembler directives are all reserved
symbols.
2-9
Chapter 2. Assembly Language Concepts
The following instruction operand symbols are also reserved:
Symbol
Meaning
$
Location counter reference
Accumulator register
Register B or register pair Band C
Register C
Register D or register pair D and E
Register E
Register H or register pair Hand L
Register L
Stack pointer register
Program status word (Contents of A and status flags)
Memory reference code using address in Hand L
Special relocatability feature
Special relocatability feature
A
B
C
D
E
H
L
SP
PSW
M
STACK
MEMORY
NOTE
The STACK and MEMORY symbols are fully discussed
in Chapter 4.
User-defined symbols are symbols you create to reference instruction and data addresses. These symbols are
defined when they appear in the label field of an instruction or in the name field of EQU, SET, or MACRO
directives (see Ch~pters 4 and 5).
Assembler-generated symbols are created by the assembler to replace user-defined symbols whose scope is limited
to a macro definition.
Global and Limited Symbols
Most symbols are global. This means that they have meaning throughout your program. Assume, for example,
that you assign the symbolic name RTN to a routine. You may then code a jump or a call to RTN from any
point in your program. If you assign the symbolic name RTN to a second routine, an error results since you
have given multiple definitions to the same name.
Certain symbols have meaning only within a macro definition or within a call to that macro; these symbols are
'local' to the macro. Macros require local symbols because the same macro may be used many times in the
program. If the symbolic names within macros were global, each use of the macro (except the first) would cause
multiple definitions for those symbolic names.
See Chapter 5 for additional information about macros.
2-10
Chapter 2. Assembly Langtlage Concepts
Permanent and Redefinable Symbols
Most symbols are permanent since their val ue cannot change during the assembly operation. Only symbols
defined with the SET and MACRO assembler directives are redefinable.
Absolute and Relocatable Symbols
An important attribute of symbols with this assembler is that- of relocatability. Relocatable programs are
assembled relative to memory location zero. These programs are later relocated to some other set of memory
locations. Symbols with addresses that change during relocation are relocatable symbols. Symbols with
addresses that do not change during relocation are absolute symbols. This distinction becomes important when
the symbols are used within expressions, as will be explained later.
External and public symbols are special types of relocatable symbols. These symbols are required to establish
program linkage when several relocatable program modules are bound together to form a single application
program. External symbols are those used in the current program module, but defined in another module.
Such symbols must appear in an EXTRN statement, or the assembler will flag them as undefined.
Conversely, PUBLIC symbols are defined in the current program module, but may be accessed by other
modules. The addresses for these symbols are resolved'when the modules are bound together.
Absolute and relocatable symbols may both appear in a relocatable module. References to any of the assemblerdefined registers A through E, Hand L, PSW, SP, and M are absolute since they refer to hardware locations.
But these references are valid in any module.
ASSEMBLY-TIME EXPRESSION EVALUATION
An expression is a combination of numbers, symbols, and operators. Each element of an expression is a term.
Expressions, like symbols, may be absolute or relocatable. For the sake of readers who do not require the
relocation feature, absolute expressions are described first. However, users of relocation should read all the
following.
Operators
The assembler includes five groups of operators which permit the following assembly-time operations: arithmetic
operations, shift operations, logical operations, compare operations, and byte isolation operations. It is important
to keep in mind that these are all assembly-time operations. Once the assembler has evaluated an expression, it
becomes a permanent part of your program. Assume, for example, that your program defines a list of ten constants starting at the label LIST; the following instruction loads the address of the seventh item in the list into
the Hand L registers:
LXI
H,LlST +6
Notice that LIST addresses the first item, LIST + 1 the second, and so on.
2-11
Chapter 2. Assembly Language Concepts
Arithmetic Operators
The arithmetic operators are as follows:
Operator
Meaning
+
Unary or binary addition
Unary or binary subtraction
Multiplication
Division. Any remainder is discarded (7/2=3).
Division by zero causes an error.
Modulo. Result is the remainder caused by a
division operation. (7 MOD 3=1)
*
MOD
Examples:
The following expressions generate the bit pattern for the ASCII character A:
5+30*2
(25/5}+30*2
5+(-30*-2)
Notice that the MOD operator must be separated from its operands by spaces:
NUMBR
8
MOD
Assuming that NUMBR has the value 25, the previous expression evaluates to the value 1.
Shift Operators
The shift operators are as follows:
Operator
y
Meaning
SHR x
Shift operand 'y' to the right 'x' bit positions.
y SHL x
Shift operand 'y' to the left 'x' bit positions.
The shift operators do not wraparound any bits shifted out of the byte. Bit positions vacated by the shift
operation are zero-filled. Notice that the shift operator must be separated from its operands by spaces.
Example:
Assume that NUMBR has the value 0101 0101. The effects of the shift operators is as follows:
2-12
NUMBR
SHR
NUMBR
SHL
2
0001 01 01
1010 1010
Chapter 2. Assembly Language Concepts
Notice that, for non-negative values, a shift one bit position to the left has the effect of mUltiplying a value by two;
a shift one bit position to the right has the effect of dividing a value by two.
Logical Operators
The logical operators are as follows:
Meaning
Operator
NOT
Logical one's complement
AND
Logical AND (=1 if both ANDed bits are 1)
OR
Logical OR (=1 if either ORed bit is 1 )
XOR
Logical EXCLUSIVE OR (=1 if bits are different)
The logical operators act only upon the least significant bit of the result of the operation. Also, these operators are
commonly used in conditional IF directives. These directives are fully explained in Chapter 4.
Example:
The following I F directive tests the least significant bit of the evaluated expression. The assembly language code that
follows the I F is assembled only if the condition is TRUE. This means that the result must have a one bit in the least
significant bit position.
IF FLD1 AND FLD2 AND FLD3
Compare Operators
The compare operators are as follows:
Operator
EO
NE
LT
LE
GT
GE
NUL
Meaning
Equal
Not equal
Less than
Less than or equal
Greater than
Greater than or equal
Special operator used to test for null (missing) macro
parameters
2-13
Chapter 2. Assembly Language Concepts
The compare operators yield a yes-no result. Thus, if the evaluation of the relation is TRUE, the value of the
result is all ones. If false, the value of the result is all zeros. Relational operations are based strictly on magnitude comparisons of bit values. Thus, a two's complement negative number (which always has a one in its high
order bit) is greater than a two's complement positive number (which always has a zero in its high order bit).
Since the NUL operator applies only to the macro feature, NUL is described in Chapter 5.
The compare operators are commonly used in conditional IF directives. These directives are fully explained in
Chapter 4.
Notice that the compare operator must be separated from its operands by spaces.
Example:
The following IF directive tests the values of FLOl and FL02 for equality. If the result of the comparison is
TRUE, the assembly language coding following the I F directive is assembled. Otherwise, the code is skipped over.
IF FLOl EQ FL02
Byte Isolation Operators
The byte isolation operators are as follows:
Operator
Meaning
HIGH
Isolate high-order 8 bits of 16-bit value
LOW
Isolate low-order 8 bits of 16-bit value.
The assembler treats expressions as 16-bit addresses. In certain cases, you need to deal only with a part of an
address, or you need to generate an 8-bit value. This is the function of the HIGH and LOW operators.
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either the
HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the expression.
When neither operator is present, the assembler assumes the LOW operator and issues an error message.
NOTE
Any program segment containing a symbol used as the
argument of a HIGH operator should be located only on
a page boundary. This is done using the PAGE option
with the CSEG or OSEG directives described in Chapter
4. Carries are not propagated from the low-order byte
when the assembler object code is relocated and the
carry flag will be lost. Using PAGE ensures that this
flag is O.
2-14
Chapter 2. Assembly Language Concepts
Examples:
Assume that ADRS is an address manipulated at assembly-time for building tables or lists of items that must all
be below address 255 in memory. The following IF directive determines whether the high-order byte of ADRS
is zero, thus indicating that the address is still less than 256:
IF HIGH ADRS EQ 0
Permissible Range of Values
Internally, the assembler treats each term of an expression as a two-byte, 16-bit value. Thus, the maximum
range of values is OH through OFFFFH. All arithmetic operations are performed using unsigned two's complement arithmetic. The assembler performs no overflow detection for two-byte values, so these values are evaluated
modulo 64K.
Certain instructions require that their operands be an eight-bit value. Expressions for these instructions must
yield values in the range -256 through +255. The assembler generates an error message if an f'xpression for one
of these instructions yields an out-of-range value.
NOTE
Only instructions that allow registers as operands may have
register-type operands. Expressions containing register-type
operands are flagged as errors. The only assembler directives
that may contain register-type operands are EQU, SET, and
actual parameters in macro calls. Registers can be assigned
alternate names only by EQU or SET.
Precedence of Operators
Expressions are evaluated left to right. Operators with higher precedence are evaluated before other operators
that immediately precede or follow them. When two operators have equal precedence, the left-most is evaluated
fi rst.
Parentheses can be used to override normal rules of precedence. The part of an expression enclosed in parentheses is evaluated first. If parentheses are nested, the innermost are evaluated first.
15/3 + 18/9
15/(3 + 18/9)
=5 + 2 =7
= 15/(3 + 2) = 15/5 = 3
2-15
Chapter 2. Assembly Language Concepts
The following list describes the classes of operators in order of precedence:
•
Parenthesized expressions
•
•
•
•
•
•
•
•
NUL
HIGH, LOW
Multiplication/Division: *, /, MOD, SHL, SHR
Addition/Subtraction: +, - (unary and binary)
Relational Operators: EQ, LT, LE, GT, GE, NE
Logical NOT
Logical AND
Logical OR, XOR
The relational, logical, and HIGH/LOW operators must be separated from their operands by at least one blank.
WARNING
If NOT is immediately preceded by another operator, e.g.:
Y EQU 1 + NOT X
an error will result. To code the expression for correct assembly, parenthesize the expression to force NOT to be
evaluated first, e.g.:
Y EQU 1 + (NOT X)
Relocatable Expressions
Determining the relocatability of an expression requires that you understand the relocatability of each term used
in the expression. This is easier than it sounds since the number of allowable operators is substantially reduced.
But first it is necessary to know what determines whether a symbol is absolute or relocatable.
Absolute symbols can be defined two ways:
•
•
A symbol that appears in a label field when the ASEG directive is in effect is an absolute symbol.
A symbol defined as equivalent to an absolute expression using the SET or EQU directive is an
absolute symbol.
Relocatable symbols can be defined a number of ways:
•
•
•
•
•
A symbol that appears in a label field when the DSEG or CSEG directive is in effect is a relocatable
symbol.
A symbol defined as equivalent to a relocatable expression using the SET or EQU directive is
relocatable.
The special assembler symbols STACK and MEMORY are relocatable.
External symbols are considered relocatable.
A reference to the location counter (specified by the $ character) is relocatable when the CSEG or
DSEG directive is in effect.
The expressions shown in the following list are the only expressions that yield a relocatable result. Assume that
ABS is an absolute symbol and RELOC is a relocatable symbol:
2-16
Chapter 2. Assembly Language Concepts
Remember that numbers are absolute terms. Thus the expression RELOC - 100 is legal, but 100
is not.
RELOC
When two relocatable symbols have both been defined with the same type of relocatability, they may appear in
certain expressions that yield an absolute result. Symbols have the same type of relocatability when both are
relative to the CSEG location counter, both are relative to the DSEG location counter, both are relative to
MEMORY, or both are relative to STACK. The following expressions are val id and produce absolute results:
RELOCl - RELOC2
EQ
LT
RELOCl
LE
GT
GE
NE
RELOC2
Relocatable symbols may not appear in expressions with any other operators.
The following list shows all possible combinations of operators with absolute and relocatable terms. An A in the
table indicates that the resulting address is absolute; an R indicates a relocatable address; an I indicates an
illegal combination. Notice that only one term may appear with the last five operators in the list.
Operator
X +
X -
Y
Y
Y
X *
X /
Y
X MOD Y
X SHL
Y
X SHR Y
X EQ
Y
X LT
Y
X LE
Y
X GT
Y
X GE
Y
X NE
Y
X AND Y
X OR
Y
X XOR Y
NOT X
HIGH X
LOW X
unary+
X
unaryX
X absolute
Y absolute
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
X ab solu te
Y rei oca table
X relocatable
Y absolute
X relocatable
Y relocatable
R
R
R
I
A
I
I
I
I
I
A
A
A
A
A
A
I
I
I
A
--
A
A
A
R
R
R
-
A
I
-
--
2-1 i
Chapter 2. Assembly Language Concepts
Relocatability of Expressions Involving External Symbols
The only permissible expressions involving external symbols (EXTRNs) are:
•
•
•
•
External symbol ± absolute symbol
Absolute symbol + external symbol
HIGH (external symbol)
LOW (external symbol)
Chaining of Symbol Definitions
The ISIS-II 8080/8085 Macro Assembler is essentially a 2-pass assembler. All symbol table entries must be
resolvable in two passes. Therefore,
X
Y
EQU
EQU
Y
EQU
EQU
EQU
Y
is legal, but in the series
X
Y
z
z
the first line is illegal as X cannot be resolved in two passes and remains undefined.
2-18
3. INSTRUCTION SET
HOW TO USE THIS CHAPTER
This chapter is a dictionary of 8080 and 8085 instructions. The instruction descriptions are listed alphabetically
for quick reference. Each description is complete so that you are seldom required to look elsewhere for additional information.
This reference format necessarily requires repetitive information. If you are readinr this manual to learn about
the 8080 or the 8085, do not try to read this chapter from ACI (add immediate with Carry) to XTHL (exchange
top of stack with Hand L registers). Instead, read the description of the processor and instruction set in
Chapter 1 and the programming examples in Chapter 6. When you begin to have questions about particular
instructions, look them up in this chapter.
TIMING INFORMATION
The instruction descriptions in this manual do not explicitly state execution timings. This is because the basic
operating speed of your processor depends on the clock frequency used in your system.
The estate' is the basic unit of time measurement for the processor. A state may range from 480 nanoseconds
(320 nanoseconds on the 8085) to 2 microseconds, depending on the clock frequency. When you know the
length of a state in your system, you can determine an instruction's basic execution time by mUltiplying that
figure by the number of states required for the instruction.
Notice that two sets of cycle/state specifications are given for 8085 conditional call and jump instructions. This
is because the 8085 fetches the third instruction byte only if it is actually needed; i.e., the specified condition
is satisfied.
This basic timing factor can be affected by the operating speed of the memory in your system. With a fast
clock cycle and a slow memory, the processor can outrun the memory. In this case, the processor must wait
for the memory to deliver the desired instruction or data. In applications with critical timing requirements, this
wait can be significant. Refer to the appropriate manufacturer's literature for memory timing data.
3-1
Chapter 3. Instruction Set
ACI
ADD IMMEDIATE WITH CARRY
ACI adds the contents of the second instruction byte and the carry bit to the contents of the accumulator and
stores the result in the accumulator.
Opcode
Operand
ACI
data
The operand specifies the actual data to be added to the accumulator except, of course, for the carry bit. Data
may be in the form of a number, an ASCII constant, the label of a previously defined value, or an expression.
The data may not exceed one byte.
>
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either the
HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the expression.
When neither operator is present, the assembler assumes the LOW operator and issues an error message.
o
o
0
data
Cycles:
States:
Addressing:
Flags:
2
7
immediate
Z,S,P,CY,AC
Example:
Assume that the accumulator contains the value 14H and that the carry bit is set to one. The instruction ACI 66
has the following effect:
Accumulator = 14H
Immediate data = 42H
Carry
0001 0100
01000010
1
01010111
1\ DC
57H
ADD WITH CARRY
The ADC instruction adds one byte of data plus the setting of the carry flag to the contents of the accumulator.
The result is stored in the accumulator. ADC then updates the setting of the carry flag to indicate the outcome
of the operation.
The ADC instruction's use of the carry bit enables the program to add multi-byte numeric strings.
3-2
Chapter 3. Instruction Set
Add Register to Accumulator with Carry
Opccde
Operand
ADC
reg
The operand must specify one of the registers A through E, H or L. This instruction adds the contents of the
specified register and the carry bit to the accumulator and stores the result in the accumulator.
Cycles:
States:
Addressings:
Flags:
1
4
register
Z,S,P,CY,AC
Add Memory to Accumulator with Carry
Opcode
Operand
ADC
M
This instruction adds the contents of the memory location addressed by the Hand L registers and the carry
bit to the accumulator and stores the result in the accumulator. M is a symbolic reference to the Hand L
registers.
Cycles:
States:
Addressing:
Flags:
2
7
register indirect
Z,S,P,CY,AC
Example:
Assume that register C contains 3DH, the accumulator contains 42H, and the carry bit is set to zero. The
instruction ADC C performs the addition as follows:
3DH
42H
001111 01
01000010
o
CARRY
01111111 = 7FH
The condition flags are set as follows:
Carry
Sign
Zero
Parity
Aux. Carry
0
0
0
0
0
3-3
Chapter 3. Instruction Set
If the carry bit is set to one, the instruction has the following results:
00111101
01000010
1
10000000
3DH
42H
CARRY
Carry
Sign
Zero
Parity
Aux. Carry
80H
0
0
0
ADD
ADD
The ADD instruction adds one byte of data to the contents of the accumulator. The result is stored in the
accumulator. Notice that the ADD instruction excludes the carry flag from the addition but sets the flag to
indicate the outcome of the operation.
Add Register to Register
Opcode
Operand
ADD
reg
The operand must specify one of the registers A through E, H or L. The instruction adds the contents of the
specified register to the contents of the accumulator and stores the result in the accumulator.
11
0
0
0
0
Is
S
SI
1
Cycles:
States:
Addressing:
Flags:
4
register
Z,S,P,CY,AC
Add From Memory
Opcode
Operand
ADD
M
This instruction adds the contents of the memory location addressed by the Hand L registers to the contents of
the accumulator and stores the result in the accumulator. M is a symbolic reference to the Hand L registers.
11
0
0
Cycles:
States:
Addressing:
Flags:
34
0
0
2
7
register indirect
Z,S,P,CY,AC
Chapter 3. Instruction Set
Examples:
Assume that the accumulator contains 6CH and register D contains 2EH. The instruction ADD D performs the
addition as follows:
2 EH
6CH
001 0111 0
01101100
9 AH
1001 "1 01 0
The accumulator contains the value 9AH following execution of the ADD D instruction. The contents of the D
register remain unchanged. The condition flags are set as follows:
Carry
Sign
Zero
Parity
Aux. Carry
=
0
1
0
The following instruction doubles the contents of the accumulator:
ADD A
ADI
ADD IMMEDIATE
ADI adds the contents of the second instruction byte of the contents of the accumulator and stores the result
in the accumulator.
Opcode
Operand
ADI
data
The operand specifies the actual data to be added to the accumulator. This data may be in the form of a number,
an ASCII constant, the label of a previously defined value, or an expression. The data may not exceed one byte.
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either
the HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the expression.
When neither operator is present, the assembler assumes the LOW operator and issues an error message.
000
data
Cycles:
States:
Addressing:
Flags:
2
7
immediate
Z,S,P,CY,AC
3-5
Chapter 3. Instruction Set
Example:
Assume that the accumulator contains the value 14H. The illstruction ADI 66 has the following effect:
Accumulator
Immediate data
00010100
01000010
01010110 = 56H
14H
42H
Notice that the assembler converts the decimal value 66 into the hexadecimal value 42.
LOGICAL AND WITH ACCUMULATOR
ANA
ANA performs a logical AND operation using the contents of the specified byte and the accumulator. The result
is placed in the accumulator.
Summary of Logical Operations
AND produces a one bit in the result only when the corresponding bits in the test data and the mask data are
ones.
OR produces a one bit in the result when the corresponding bits in either the test data or the mask data are
ones.
Exclusive OR produces a one bit only when the corresponding bits in the test data and the mask data are
different; i.e., a one bit in either the test data or the mask data - but not both - produces a one bit in the
result.
AND
EXCLUSIVE OR
OR
1010 1010
0000 1111
0000 1010
1010 1010
0000 1111
10101111
1010
0000
1010
1010
1111
0101
AND Register with Accumulator
Opcode
Operand
ANA
reg
The operand must specify one of the registers A through E, H or L. This instruction ANDs the contents of the
specified register with the accumulator and stores the result in the accumulator. The carry flag is reset to zero.
11
0
Cycles:
States:
Addressing:
Flags:
3-6
0
0
I
S
S
sl
4
register
Z,S,P,CY,AC
Chapter 3. Instruction Set
AND Memory with Accumulator
Opcode
Operand
ANA
M
This instruction ANDs the contents of the specified memory location with the accumulator and stores the result
in the accumulator. The carry flag is reset to zero.
~_O____O__O______O~I
Cycles:
States:
Addressing:
Flags:
2
7
register indirect
Z,S,P,CY,AC
Example:
Since any bit ANDed with a zero produces a zero and any bit ANDed with a one remains unchanged, AND is
frequently used to zero particular groups of bits. The following example ensures that the high-order four bits of
the accumulator are zero, and the low-order four bits ar~ unchanged. Assume that the C register contains OFH:
Accumulator
C Register
1 1 1 1
o
o 000
000 0
0
1
o
0
OFCH
OFH
OCH
AND IMMEDIATE WITH ACCUMULATOR
ANI
AN I performs a logical AND operation using the contents of the second byte of the instruction and the accumulator. The result is placed in the accumulator. ANI also resets the carry flag to zero.
Op co de
Operand
ANI
data
The operand must specify the data to be used in the AND operation. This data may be in the form of a number,
an ASCII constant, the label of some previously defined value, or an expression. The data may not exceed one
byte.
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either the
HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the expression.
When neither operator is present, the assembler assumes the LOW operator and issues an error message.
3-7
Chapter 3. Instruction Set
o
0
data
Cycles:
States:
Addressing:
Flags:
2
7
immediate
Z,S,P,CY,AC
Summary of Logical Operations
AND produces a one bit in the result only when the corresponding bits in the test data and the mask data are
ones.
OR produces a one bit in the result when the corresponding bits in either the test data or the mask data are
ones.
Exclusive OR produces a one bit only when the corresponding bits in the test data and the mask data are
different; i.e., a one bit in either the test data or the mask data - but not both - produces a one bit in the
result.
AND
1010 1010
0000 1111
0000 '1010
OR
1010 1010
0000 1111
10101111
EXCLUSIVE OR
1010 1010
0000 1111
10100101
Example:
The following instruction is used to reset OFF bit six of the byte in the accumulator:
ANI
101111118
Since any bit ANDed with a one remains unchanged and a bit ANDed with a zero is rest to zero, the ANI
instruction shown above sets bit six OFF and leaves the others unchanged. This technique is useful when a
program uses individual bits as status flags.
CALL
CALL
The CALL instruction combines functions of the PUSH and J MP instructions. CALL pushes the contents of the
program counter (the address of the next sequential instruction) onto the stack and then jumps to the address
specified in the CALL instruction.
Each CALL instruction or one of its variants implies the use of a subsequent RET (return) instruction. When a
call has no corresponding return, excess addresses are built up in the stack.
3-8
Chapter 3. Instruction Set
Op co de
Operand
CALL
address
The address may be specified as a number, a label, or an expression. (The label is most common.) The assembler
inverts the high and low address bytes when it assembles the instruction.
1
1
0
0
1
1
0
1
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
5
17 (1 8 0 n 8085)
immediate/register indirect
none
Example:
When a given coding sequence is required several times in'a program, you can usually conserve memory by coding
the sequence as a subroutine invoked by the CALL instruction or one of its variants. For example, assume that
an application drives a six-digit LED display; the display is updated as a result of an operator input or because
of two different calculations that occur in the program. The coding required to drive the display can be included
in-line at each of the three points where it is needed, or it can be coded as a subroutine. If the label DISPL Y is
assigned to the first instruction of the display driver, the following CALL instruction is used to invoke the
display subroutine:
CALL
DISPLY
This CALL instruction pushes the address of the next program instruction onto the stack and then transfers
control to the DISPL Y subroutine. The DISPL Y subroutine must execute a return instruction or one of its
variants to resume normal program flow. The following is a graphic illustration of the effect of CALL and return
instructions:
CALL
-CA L L ~
_
~
DISPLY:
D ISPL Y - - - - ---------- ----- ....
RET
CALL
DISPLY
Consideration for Using Subroutines
The larger the code segment to be repeated and the greater the number of repetitions, the greater the potential
memory savings of using a subroutine. Thus, if the display driver in the previous example requires one hundred
3-9
Chapter 3. Instruction Set
bytes, coding it in-line would require three hundred bytes. Coded as a subroutine, it requires one hundred bytes
plus nine bytes for the three CALL instructions.
Notice that subroutines require the use of the stack. This requires the application to include random access
memory for the stack. When an application has no other need for random access memory, the system designer
might elect to avoid the use of subroutines.
CC
CALL IF CARRY
The CC instruction combines functions of the JC and PUSH instructions. CC tests the setting of the carry flag.
If the flag is set to one, CC pushes the contents of the program counter onto the stack and then jumps to the
address specified in bytes two and three of the CC instruction. If the flag is reset to zero, program execution
continues with the next sequential instruction.
Opcode
Operand
CC
address
Although the use of a label is most common, the address may also be specified as a number or expression.
1
1
0
1
1
1
0
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3 or 5 (2 or 5 on 8085)
11 or 17 (9 or 18 on 8085)
immediate/register indirect
none
Example:
For the sake of brevity, an example is given for the CALL instruction but not for each of its closely related
variants.
CALL IF MINUS
CM
The CM instruction combines functions of the J M and PUSH instructions. CM tests the setting of the sign flag.
If the flag is set to one (indicating that the contents of the accumulator are minus), CM pushes the contents
of the program counter onto the stack and then jumps to the address specified by the CM instruction. If the
flag is set to zero, program execution simply continues with the next sequential instruction.
3-10
Opcode
Operand
CM
address
Chapter 3. Instruction Set
Although the use of a label is most common, the address may also be specified as a number or an expression.
1
1
1
1
1
1
a a
lowaddr
high addr
Cycles:
3 or 5 (2 or 5 on 8085)
States:
Addressing:
Flags:
11 or 17 (9 or 18 on 8085)
immediate/register indirect
none
Example:
For the sake of brevity, an example is given for the CALL instruction but not for each of its closely related
variants.
CMA
COMPLEMENT ACCUMU LA TOR
CMA complements each bit of the accumulator to produce the one's complement. All condition flags remain
unchanged.
Opcode
Operand
CMA
Operands are not permitted with the CMA instruction.
a
Cycles:
States:
Flags:
4
none
To produce the two's complement, add one to the contents of the accumulator after the CMA instructions has
been executed.
Example:
Assume that the accumulator contains the value 51 H; when complemented by CMA, it becomes OAEH:
51H
OAEH
01 01 0001
10101110
3-11
Chapter 3. Instruction Set
CMC
COMPLEMENT CARRY
If the carry flag equals zero, CMC sets it to one. If the carry flag is one, CMC resets it to zero. All other flags
remain unchanged.
Opcode
Operand
CMC
Operands are not permitted with the CMC instruction.
10 0
Cycles:
States:
Flags:
4
CYonly
Example:
Assume that a program uses bit 7 of a byte to control whether a subroutine is called. To test the bit, the program loads the byte into the accumulator, rotates bit 7 into the carry flag, and executes a CC (Call if Carry)
instruction. Before returning to the calling program, the subroutine reinitializes the flag byte using the following
code:
CMC
RAR
RET
CMP
;SET BIT 7 OFF
;ROTATE BIT 7 INTO ACCUMULATOR
;RETURN
COMPARE WITH ACCUMULATOR
CMP compares the specified byte with the contents of the accumulator and indicates the result by setting the
carry and zero flags. The values being compared remain unchanged.
The zero flag indicates equality. No carry indicates that the accumulator is greater than or equal to the specified
byte; a carry indicates that the accumulator is less than the byte. However, the meaning of the carry flag is reversed
when the values have different signs or one of the values is complemented.
The program tests the condition flags using one of the conditional Jump, Call, or Return instructions. For
example, J Z (J ump if Zero) tests for equality.
Functional Description:
Comparisons are performed by subtracting the specified byte from the contents of the accumulator, which
is why the zero and carry flags indicate the result. This subtraction uses the processor's internal registers
so that source data is preserved. Because subtraction uses two's complement addition, the CMP instruction
recomplements the carry flag generated by the subtraction.
3-12
Chapter 3. Instruction Set
Compare Register with Accumulator
Opcode
Operand
CMP
reg
The operand must name one of the registers A through E, H or L.
o
S
Cycles:
States:
Addressing:
Flags:
S
sl
4
register
Z,S,P,CY,AC
Compare Memory with Accumulator
Opcode
Operand
CMP
M
This instruction compares the contents of the memory location addressed by the Hand L registers with the
contents of the accumulator. M is a symbolic reference to the Hand L register pair.
Cycles:
States:
Addressing:
Flags:
2
7
register indirect
Z,S,P,CY,AC
Example 1:
Assume that the accumulator contains the value OAH and register E contains the value OSH. The instruction
CMP E performs the following internal subtraction (remember that subtraction is actually two's complement
addition) :
Accumulator
+( -E Register)
= 00001010
11111011
000001 01 +(-carry)
After the carry is complemented to account for the subtract operation, both the zero and carry bits are zero,
thus indicating A greater than E.
Example 2:
Assume that the accumulator contains the value -1 BH and register E contains OSH:
Accumulator
+( -E Register)
111 00101
11111011
11100000 +( -carry)
3·13
Chapter 3. Instruction Set
After the CMP instruction recomplements the carry flag, both the carry flag and zero flag are zero. Normally
this indicates that the accumulator is greater than register E. However, the meaning of the carry flag is reversed
since the values have different signs. The user program is responsible for proper interpretation of the carry flag.
CALL IF NO CARRY
CNC
The CNC instruction combines functions of the JNC and PUSH instructions. CNC tests the setting of the carry
flag. If the flag is set to zero, CNC pushes the contents of the program counter onto the stack and then jumps
to the address specified by the CNC instruction. If the flag is set to one, program execution simply continues
with the next sequential instruction.
Opcode
Operand
CNC
address
Although the use of a label is most common, the address may also be specified as a number or an expression.
1
1
0
1
1
0
0
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3 or 5 (2 or 5 on 8085)
11 or "17 (9 or 18 on 8085)
immediate/register indirect
none
Example:
For the sake of brevity, an example is given for the CALL instruction but not for each of its closely related
variants.
CALL IF NOT ZERO
CNZ
The CNZ instruction combines functions of the J NZ and PUSH instructions. CNZ tests the setting of the zero
flag. If the flag is off (indicating that the contents of the accumulator are other than zero), CNZ pushes the
contents of the program counter onto the stack and then jumps to the address specified in the instruction's
second and third bytes. If the flag is set to one, program execution simply continues with the next sequential
instruction.
Opcode
Operand
CNZ
address
Although the use of a label is most common, the address may also be specified as a number or an expression.
3-14
Chapter 3. Instruction Set
1
1
0
0
1
0
0
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3 or 5 (2 or 5 on 8085)
1"1 or 17 (9 or 18 on 8085)
immediate/register indirect
none
Example:
For the sake of brevity, an example is given for the CALL instruction but not for each of its closely related
variants.
CP
CALL IF POSITIVE
The CP instruction combines features of the J P and PUSH instructions. CP tests the setting of the sign flag. If
the flag is set to zero (indicating that the contents of the accumulator are positive), CP pushes the contents of
the program counter onto the stack and then jumps to the address specified by the CP instruction. If the flag
is set to one, program execution simply continues with the next sequential instruction.
Opcode
Operand
CP
address
Although the use of a label is more common, the address may also be specified as a number or an expression.
1
1
1
1
1
0
0
0
low address
high addr
Cycles:
States:
Addressing:
Flags:
3 or 5 (2 or 5 on 8085)
11 or 17 (9 or 18 on 8085)
immediate/register indirect
none
Example:
For the sake of brevity, an example is given for the CALL instruction but not for each of its closely related
variants.
3-15
Chapter 3. Instruction Set
CPE
CALL IF PARITY EVEN
Parity is even if the byte in
indicate this condition. The
the IN instruction does not
adding OOH to the contents
the accumulator has an even number of one bits. The parity flag is set to one to
CPE and CPO instructions are useful for testing the parity of input data. However,
set any of the condition flags. The flags can be set without altering the data by
of the accumulator.
The CPE instruction combines functions of the JPE and PUSH instructions. CPE tests the setting of the parity
flag. If the flag is set to one, CPE pushes the contents of the program counter onto the stack and then jumps
to the address specified by the CPE instruction. If the flag is set to zero, program execution simply continues
with the next sequential instruction.
Opcode
Operand
CPE
address
Although the use of a label is more common, the address may also be specified as a number or an expression.
1
1
1
0
1
1
0
0
lowaddr
high addr
Cycles:
3 or 5 (2 or 5 on 8085)
States:
Addressing:
Flags:
11 or 17 (9 or 18 on 8085)
immediate/register indirect
none
Example:
For the sake of brevity, an example is given for the CALL instruction but not for each of its closely related
variants.
CPI
COMPARE IMMEDIATE
CPI compares the contents of the second instruction byte with the contents of the accumulator and sets the zero
and carry flags to indicate the result. The values being compared remain unchanged.
The zero flag indicates equality. No carry indicates that the contents of the accumulator are greater than the
immediate data; a carry indicates that the accumulator is less than the immediate data. However, the meaning
of the carry flag is reversed when the values have different signs or one of the values is complemented.
3-16
Opcode
Operand
CPI
data
Chapter 3. I nstruction Set
The operand must specify the data to be compared. This data may be in the form of a number, an ASCII
constant, the label of a previously defined value, or an expression. The data may not exceed one byte.
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either
the HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the
expression. When neither operator is present, the assembler assumes the LOW operator and issues an error
message.
o
data
Cycles:
States:
2
7
Addressing:
Flags:
register indirect
Z,S,P,CY,AC
Example:
The instruction CPI IC' compares the contents of the accumulator to the letter C (43H).
CPO
CALL IF PARITY ODD
Parity is odd if the byte in the accumulator has an odd number of one bits. The parity flag is set to zero to
indicate this condition. The CPO and ePE instructions are useful for testing the parity of input data. However,
the I N instruction does not set any of the condition flags. The flags can be set without altering the data by
adding OOH to the contents of the accumulator.
The CPO instruction combines functions of the J PO and PUSH instructions. CPO tests the setting of the parity
flag. If the flag is set to zero, CPO pushes the contents of the program counter onto the stack and then jumps
to the address specified by the CPO instruction. If the flag is set to one, program execution simply continues
with the next sequential instruction.
Opcode
Operand
CPO
address
Although the use of a label is more common, the address may also be specified as a number or an expression.
1
1
1
0
0
1
0
0
lowaddr
,
high addr
Cycles:
States:
Addressing:
Flags:
3 or 5 (2 or 5 on 8085)
11 or 17 (9 or 18 on 8085)
immediate/register indirect
none
3-17
Chapter 3. Instruction Set
Example:
For the sake of brevity, an example is given for the CALL instruction but not for each of its closely related
variants.
CZ
CALL IF ZERO
The CZ instruction combines functions of the JZ and PUSH instructions. CZ tests the setting of the zero flag.
If the flag is set to one (indicating that the contents of the accumulator are zero), CZ pushes the contents of
the program counter onto the stack and then jumps to the address specified in the CZ instruction. If the flag
is set to zero (indicating that the contents of the accumulator are other than zero), program execution simply
continues with the next sequential instruction.
Opcode
Operand
CZ
address
Although the usc of a label is most common, the address may also be specified as a number or an expression.
1
I
0
0
1
1
0
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3 or 5 (2 or 5 on 8085)
11 or "17 (9 or 18 on 8085)
immediate/register indirect
none
Example:
For the sake of brevity, an example is given for the CALL instruction but not for each of its closely related
variants.
DECIMAL ADJ UST ACCUMULATOR
DAA
The DAA instruction adjusts the eight-bit value in the accumulator to form two four-bit binary coded decimal
digits.
Opcode
Operand
DAA
Operands are not permitted with the DAA instruction.
DAA is used when adding decimal numbers. It is the only instruction whose function requires use of the auxiliary
carry flag. In multi-byte arithmetic operations, the DAA instruction typically is coded immediately after the arithmetic instruction so that the auxil iary carry flag is not altered unintentionally.
3-18
Chapter 3. Instruction Set
DAA operates as follows:
1.
If the least significant four bits of the accumulator have a value greater than nine, or if the auxiliary
carry flag is ON, DAA adds six to the accumulator.
2.
If the most significant four bits of the accumulator have a value greater than nine, or if the carry
flag is ON, DAA adds six to the most significant four bits of the accumulator.
a a
Cycles:
States:
Addressing:
Flags:
4
register
Z,S,P,CY,AC
Example:
Assume that the accumulator contains the value 9BH as a result of adding 08 to 93:
CY
AC
a
a
1001
0000
1001
0011
1000
1011
= 9BH
Since OBH is greater than nine, the instruction adds six to contents of the accumulator:
CY
AC
a
1001
0000
101 a
1011
0110
000 1
= A1 H
Now that the most significant bits have a value greater than nine, the instruction adds six to them:
CY
1010
0110
0000
AC
1
0001
0000
0001
When the DAA has finished, the accumulator contains the value 01 in a BCD format; both the carry and auxiliary
carry flags are set ON. Since the actual result of this addition is 101, the carry flag is probably significant to the
program. The program is responsible for recovering and using this information. Notice that the carry flag setting is
, lost as soon as the program executes any subsequent instruction that alters the flag.
3-19
Chapter 3. Instruction Set
DOUBLE REGISTER ADD
DAD
DAD adds the 16-bit value in the specified register pair to the contents of the Hand L register pair. The result
is stored in Hand L.
Opcode
Operand
DAD
DAD may add only the contents of the B&C, D&E, H&L, or the SP (Stack Pointer) register pairs to the contents
of H& L. Notice that the letter H must be used to specify that the H& L register pair is to be added to itself.
DAD sets the carry flag ON if there is a carry out of the Hand L registers. DAD affects none of the condition
flags other than carry.
10 0
R
o
P
Cycles:
States:
Addressing:
Flags:
0
1
I
3
10
register
CY
Examples:
The DAD instruction provides a means for saving the current contents of the stack pointer.
LXI
DAD
SHLD
H,OOH
SP
SAVSP
;CLEAR H& L TO ZEROS
;GET SP INTO H&L
;STORE SP IN MEMORY
The instruction DAD H doubles the number in the Hand L registers except when the operation causes a carry
ou t of the H register.
DCR
DECREMENT
DCR subtracts one from the contents of the specified byte. DCR affects all the condition flags except the carry
flag. Because DCR preserves the carry flag, it can be used within multi-byte arithmetic routines for decrementing
character counts and similar purposes.
Decrement Register
3-20
Opcode
Operand
DCR
reg
Chapter 3. Instruction Set
The operand must specify one of the registers A through E, H or L. Thp- instruction subtracts one from the
contents of the specified register.
EiIDDD
0
1
Cycles:
States:
Addressing:
Flags:
5 (4 on 8085)
register
Z,S,P,AC
Decrement Memory
Opcode
Operand
DCR
M
This instruction subtracts one from the contents of the memory location addressed by the Hand L registers.
M is a symbolic reference to the memory byte addressed by the Hand L registers.
o
Cycles:
States:
Addressing:
Flags:
o
3
10
register indirect
Z,S,P,AC
Example:
The DCR instruction is frequently used to control multi-byte operations such as moving a number of characters
from one area of memory to another:
LOOP:
MVI
LXI
LXI
MOV
STAX
DCX
DCX
DCR
XRA
CMP
JNZ
B,5H
H,250H
D,900H
A,M
D
D
H
B
A
B
LOOP
; set control counter
; load H & L with source address
; load D & E with destination address
; load byte to be moved
; store byte
; decrement destination address
; decrement source address
; decrement control counter
; clear accumulator
; compare control counter to zero
; move another byte if counter not zero
3-21
Chapter 3. Instruction Set
DECREMENT REGISTER PAIR
DCX
OCX decrements the contents of the specified register pair by one. OCX affects none of the condition flags.
Because OCX preserves all the flags, it can be used for address modification in any instruction sequence that
rei ies on the passing of the flags.
Opcode
Operand
OCX
OCX may decrement only the B&C, O&E, H&L, or the SP (Stack Pointer) register pairs. Notice that the letter
H must be used to specify the Hand L pair.
Exercise care when decrementing the stack pointer as this causes a loss of synchronization between the pointer
and the actual contents of the stack.
10 0
R
o
P
Cycles:
States:
Addressing:
Flags:
5 (6 on 8085)
register
none
Example:
Assume that the Hand L registers contain the address 9800H when the instruction OCX H is executed. OCX
considers the contents of the two registers to be a single 16-bit value and therefore performs a borrow from the
H register to produce the value 97FFH.
DISABLE INTERRUPTS
DI
The interrupt system is disabled when the processor recognizes an interrupt or immediately following execution
of a 01 instruction.
In applications that use interrupts, the 01 instruction is commonly
interrupted. For example, time-dependent code sequences become
the interrupt system by including a 01 instruction at the beginning
predict the occurrence of an interrupt, include an EI instruction at
Opcode
Operand
01
Operands are not permitted with the 01 instruction.
3-22
used only when a code sequence must not be
inaccurate when interrupted. You can disable
of the code sequence. Because you cannot
the end of the time-dependent code sequence.
Cha pter 3. I nstructi on Set
o
Cycles:
States:
Flags:
0
4
none
NOTE
The 8085 TRAP interrupt cannot be disabled. This special interrupt is
intended for serious problems that must be serviced regardless of the
interrupt flag such as power failure or bus error. However, no interrupt
including TRAP can interrupt the execution of the 01 or EI instruction.
EI
ENABLE INTERRUPTS
The EI instruction enables the interrupt system following execution of the next program instruction. Enabling
the interrupt system is delayed one instruction to allow interrupt subroutines to return to the main program
before;! subsequent interrupt is acknowledged.
In applications that use interrupts, the interrupt system is usually disabled only when the processor accepts an
interrupt or when a code sequence must not be interrupted. You can disable the interrupt system by including
a 01 instruction at the beginning of the code sequence. Because you cannot predict the occurrence of an
interrupt, incl ude an E I instruction at the end of the code sequence.
Opcode
Operand
EI
Operands are not permitted with the EI instruction.
o
Cycles:
States:
Flags:
1
4
none
NOTE
The 8085 TRAP interrupt cannot be disabled. This special interrupt is
_ intended for serious problems that must be serviced regardless of the
interrupt flag such as power failure or bus failure. However, no interrupt
including TRAP can interrupt the execution of the 01 or EI instruction.
Example:
The EI instruction is frequently used as part of a start-up sequence. When power is first applied, the processor
begins operating at some indeterminate address. Application of a RESET signal forces the program counter to
3·23
Chapter 3. Instruction Set
zero. A common instruction sequence at this point is EI, HL T. These instructions enable the interrupt system
(RESET also disables the interrupt system) and halt the processor. A subsequent manual or automatic interrupt
then determ ines the effective start-up address.
HLT
HALT
The HL T instruction halts the processor. The program counter contains the address of the next sequential
instruction. Otherwise, the flags and registers remain unchanged.
1
0
01
0
1
7 (5 on 8085)
none
Cycles:
States:
Flags:
Once in the halt state, the processor can be restarted only by an external event, typically an interrupt. Therefore,
you should be certain that interrupts are enabled before the HL T instruction is executed. See the description of
the EI (Enable Interrupt) instruction.
If an 8080 HL T instruction is executed while interrupts are disabled, the only way to restart the processor is
by application of a RESET signal. This forces the program counter to zero. The same is true of the 8085, except
for the TRAP interrupt, which is recognized even when the interrupt system is disabled.
The processor can temporarily leave the halt state to service a direct memory access request. However, the processor reenters the halt state once the request has been serviced.
A basic purpose for the HL T instruction is to allow the processor to pause while waiting for an interrupt from a
peripheral device. However, a halt wastes processor resources and should be used only when there is no useful
processing task available.
IN
INPUT FROM PORT
The IN instruction reads eight bits of data from the specified port and loads it into the accumulator.
NOTE
This description is restricted to the exact function of the IN instruction.
Input/output structures are described in the 8080 or 8085 Microcomputer
Systems User's Manual.
Opcode
Operand
IN
exp
The operand expression may be a number or any expression that yields a value in the range OOH through OFFH.
3-24
Chapter 3. Instruction Set
o
o
exp
Cycles:
3
States:
10
direct
Addressing:
Flags:
none
INR
INCREMENT
INR adds one to the contents of the specified byte. INR affects all of the condition flags except the carry flag.
Because INR preserves the carry flag, it can be used within multi-byte arithmetic routines for incrementing
character counts and similar purposes.
Increment Register
Opcode
Operand
INR
reg
The operand must specify one of the registers A through E, H or L. The instruction adds one to the contents of
the specified register.
Eo I
D
D
D
o
0
I
Cycles:
5 (4 on 8085)
register
States:
Addressing:
Flags:
Z,S,P,AC
Increment Memory
Opcode
Operand
INR
M
This instruction increments by one the contents of the memory location addressed by the Hand L registers. M
is a symbolic reference to the Hand L registers.
~_0______
0 ____0_ _0~1
Cycles:
3
States:
10
Addressing:
register indirect
Flags:
Z,S,P,AC
3-25
Chapter 3. Instruction Set
Example:
If register C contains 99H, the instruction INR C increments the contents of the register to 9AH.
INCREMENT REGISTER PAIR
INX
INX adds one to the contents of the specified register pair. INX affects none of the condition flags. Because
INX preserves all the condition flags, it can be used for address modification within multi-byte arithmetic
routines.
Opcode
Operand
INX
INX may increment only the B&C, D&E, H& L, or the SP (Stack Pointer) register pairs. Notice that the letter H
must be used to specify the Hand L register pair.
Exercise care when incrementing the stack pointer. Assume, for example, that INX SP is executed after a number
of items have been pushed onto the stack. A subsequent POP instruction accesses the high-order byte of the most
recent stack entry and the low-order byte of the next older entry. Similarly, a PUSH instruction adds the two
new bytes to the stack, but overlays the low-order byte of the most recent entry.
10 olR
Cycles:
States:
Addressing:
Flags:
PO
0
11
1
5 (6 on 8085)
register
none
Example:
Assume that the D and E registers contain the value 01 F FH. The instruction INX D increments the value to
0200H. By contrast, the INR E instruction ignores the carry out of the low-order byte and produces a result of
01 OOH. (This condition can be detected by testing the Zero condition flag.)
If the stack pointer register contains the value OFFFFH, the instruction INX SP increments the contents of SP
to OOOOH. The INX instruction sets no flags to indicate this condition.
JC
JUMP IF CARRY
The JC instruction tests the setting of the carry flag. If the flag is set to one, program execution resumes at the
address specified in the JC instruction. If the flag is reset to zero, execution continues with the next sequential
instruction.
3-26
Chapter 3. Instruction Set
Opcode
Operand
JC
address
The address may be specified as a number, a label, or an expression. The assembler inverts the high and low
address bytes when it assembles the instruction.
1
1
0
1
1
0
1
0
lowaddr
high addr
3 (2 or 3 on 8085)
10 (7 or lOon 8085)
immediate
none
Cycles:
States:
Addressing:
Flags:
Example:
Examples of the variations of the jump instruction appear in the description of the JPO instruction.
JUMP IF MINUS
JM
The JM instruction tests the setting of the sign flag. If the contents of the accumulator are negative (sign flag = 1),
program execution resumes at the address specified in the J M instruction. If the contents of the accumulator are
positive (sign flag = 0), execution continues with the next sequential instruction.
Opcode
Operand
JM
address
The address may be specified as a number, a label, or an expression. The assembler inverts the high and low
address bytes when it assembles the instructions.
1
1
1
1
1
0
1
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3 (2 or 3 on 8085)
10 (7 or lOon 8085)
immediate
none
Example:
Examples of the variations of the jump instruction appear in the description of the JPO instruction.
3-27
Chapter 3. Instruction Set
jMP
JUMP
The J MP instruction alters the execution sequence by loading the address in its second and third bytes into the
program counter.
Opcode
Operand
JMP
address
The address may be specified as a number, a label, or an expression. The assembler inverts the high and low
address bytes when it assembles the address.
1 . 1
0
0
0
0
1
1
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3
10
immediate
none
Example:
Examples of the variations of the jump instruction appear in the description of the JPO instruction.
jNC
JUMP IF NO CARRY
The JNC instruction tests the setting of the carry flag. If there is no carry (carry flag = 0), program execution
resumes at the address specified in the J NC instruction. If there is a carry (carry flag =1), execution continues
with the next sequential instruction.
Opcode
Operand
JNC
address
The address may be specified as a number, a label, or an expression. The assembler inverts the high and low
address bytes when it assembles the instruction.
1
1
0
1
0
0
1
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3-28
3 (2 or 3 on 8085)
10 (7 or 10 on 8085)
immediate
none
Chapter 3. Instruction Set
Example:
Examples of the variations of the jump instruction appear in the description of the J PO instruction.
JUMP IF NOT ZERO
JNZ
The J NZ instruction tests the setting of the zero flag. If the contents of the accumulator are not zero (zero
flag = 0), program execution resumes at the address specified in the JNZ instruction. If the contents of the
accumulator are zero (zero flag = 1), execution continues with the next sequential instruction.
Opcode
Operand
JNZ
address
The address may be specified as a number, a label, or an expression. The assembler inverts the high and low
address bytes when it assembles the instruction.
1
1
0
0
0
0
1
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3 (2 or 3 on 8085)
10 (7 or 10 on 8085)
immediate
none
Example:
Examples of the variations of the jump instruction appear in the description of the J PO instruction.
JUMP IF POSITIVE
JP
The J P instruction tests the setting of the sign flag. If the contents of the accumulator are positive (sign flag = 0),
program execution resumes at the address specified in the J P instruction. If the contents of the accumulator are
minus (sign flag = 1), execution continues with the next sequential instruction.
Opcode
Operand
JP
address
'"
The address may be specified as a nu'mber, a label, or an expression. The assembler inverts the high and low order
address bytes when it assembles the instruction.
3-29
Chapter 3. Instruction Set
1
1
1
1
0
0
1
0
lowaddr
high addr
Cycles:
3 (2 or 3 on 8085)
States:
10 (7 or 10 on 8085)
Addressing:
Flags:
immediate
none
Example:
Examples of the variations of the jump instruction appear in the description of the J PO instruction.
JUMP IF PARITY EVEN
JPE
Parity is even if the byte in the accumulator has an even number of one bits. The parity flag is set to one to
indicate this condition.
The J PE instruction tests the setting of the parity flag. If the parity flag is set to one, program execution resumes
at the address specified in the JPE instruction. If the flag is reset to zero, execution continues with the next
sequential instruction.
Opcode
Operand
JPE
address
The address may be specified as a number, a label, or an expression. The assembler inverts the high and low
address bytes when it assembles the instruction.
The J PE and J PO (jump if parity odd) instructions are especially useful for testing the parity of input data.
However, the IN instruction docs not set any of the condition flags. The flags can be set by adding OOH to the
contents of the accumulator.
1
I
1
0
1
0
1
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3 (2 or 3 on 8085)
10 (7 or lOon 8085)
immediate
none
Example:
Examples of the variations of the jump instruction appear in the description of the J PO instruction.
3-30
Chapter 3. Instruction Set
JUMP IF PARITY ODD
JPO
Parity is odd if the byte in the accumulator has an odd number of one bits. The parity flag is set to zero to
indicate this condition.
The J PO instruction tests the setting of the parity flag. If the parity flag is reset to zero, program execution
resumes at the address specified in the J PO instruction. If the flag is set to one, execution continues with the
next sequential instruction.
Opcode
Operand
JPO
address
The address may be specified as a number, a label, or an expression. The assembler inverts the high and low
address bytes when it assembles the instruction.
The J PO and J PE (jump if parity even) instructions are especially useful for testing the parity of input data.
However, the IN instruction does not set any of the condition flags. The flags can be set by adding OOH to the
contents of the accumulator.
1
1
1
0
0
0
-I
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
3 (2 or 3 on 8085)
10 (7 or 10 on 8085)
immediate
none
Example:
This example shows three different but equivalent methods for jumping to one of two points in a program hased
upon whether or not the Sign bit of a number is set. Assume that the byte to be tested is the C register.
Label
Code
Operand
ONE:
MOV
ANI
jZ
jNZ
MOV
RLC
jNC
JMP
MOV
ADI
JM
A,C
80H
PLUS
MINUS
A,C
TWO:
THREE:
PLUS:
MINUS:
PLUS
MINUS
A,C
0
MINUS
;SIGN BIT RESET
;SIGN BIT SET
3-31
Chapter 3. Instruction Set
The ANO immediate instruction in block ONE zeroes all bits of the data byte except the Sign bit; which remains unchanged. If the Sign bit was zero, the Zero condition bit will be set, and the JZ instruction will cause
program control .to be transferred to the instruction at PLUS. Otherwise, the J Z instruction will merely update
the program counter by three, and the JNZ instruction will be executed, causing control to be transferred to
the instruction at MINUS. (The Zero bit is unaffected by all jump instructions.)
The RLC instruction in block TWO causes the Carry bit to be set equal to the Sign bit of the data byte. If the
Sign bit was reset, the J NC instruction causes a jump to PLUS. Otherwise the J MP instruction is executed,
unconditionally transferring control to MINUS. (Note that, in this instance, a JC instruction could be substituted for the unconditional jump with identical results.)
The add immediate instruction in block THREE causes the condition bits to be set. If the sign bit was set, the
J M instruction causes program control to be transferred to MINUS. Otherwise, program control flows automatically into the PLUS routine.
JUMP IF ZERO
JZ
The J Z instruction tests the setting of the zero flag. If the flag is set to one, program execution resumes at the
address specified in the J Z instruction. If the flag is reset to zero, execution continues with the next sequential
instruction.
Opcode
Operand
JZ
address
The address may be specified as a number, a label, or an expression. The assembler inverts the high and low
address bytes when it assembles the instruction.
1
I
0
0
1
0
I
0
lowaddr
high addr
Cycles:
3 (2 or 3 on 8085)
States:
Addressing:
10 (7 orl 0 on 8085)
immediate
Flags:
none
Example:
Examples of the variations of the jump instruction appear in the description of the J PO instruction.
LDA
LOAD ACCUMULATOR DIRECT
LOA loads the accumulator with a copy of the byte at the location specified in bytes two and three of the
LOA instruction.
3-32
Chapter 3. Instruction Set
Opcode
Operand
LOA
address
The address may be stated as a number, a previously defined label, or an expression. The assembler inverts the
high and low address bytes when it builds the instruction.
0
0
1
1
1
0
1
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
4
13
direct
none
Examples:
The following instructions are equivalent. When executed, each replaces the accumulator contents with the byte
of data stored at memory location 300H.
LOAD:
LOA
LOA
LOA
300H
3*(16*16)
200H+256
LDAX
LOAD ACCUMULATOR INDIRECT
L OAX loads the accumulator with a copy of the byte stored at the memory location addressed by register pair
B or register pair O.
Op co de
Operand
LOA X
The operand B specifies the Band C register pair; 0 specifies the 0 and E register pair. This instruction may
specify only the B or 0 register pair.
~O
0
I rio
~
0
I
L_fo
= register pair B
~ = register pair 0
Cycles:
States:
Addressing:
Flags:
2
7
register indirect
none
3-33
Chapter 3. Instruction Set
Example:
Assume that register D contains 93H and register E contains BBH. The following instruction loads the accumulator
with the contents of memory location 93BBH:
LDAX
D
L.HLD
LOAD HAND L DIRECT
LHLD loads the L register with a copy of the byte stored at the memory location specified in bytes two and
three of the LHLD instruction. LHLD then loads the H register with a copy of the byte stored at the next
higher memory location.
Opcode
Operand
LHLD
address
The address may be stated as a number, a label, or an expression.
Certain instructions use the symbolic reference M to access the memory location currently specified by the Hand
L registers. LHLD is one of the instructions provided for loading new addresses into the Hand L registers. The
user may also load the current top of the stack into the Hand L registers (POP instruction). Both LH LD and
POP replace the contents of the Hand L registers. You can also exchange the contents of Hand L with the D
and E registers (XCHG instruction) or the top of the stack (XTHL instruction) if you need to save the current
Hand L registers for subsequent use. SHLD stores Hand L in memory.
0
0
1
0
1
0
1
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
5
16
direct
none
Example:
Assume that locations 3000 and 3001 H contain the address 064EH stored in the format 4E06. In the following
sequence, the MOV instruction moves a copy of the byte stored at address 064E into the accumulator:
LHLD
MOV
3·34
3000H
A,M
;SET UP ADDRESS
;LOAD ACCUM FROM ADDRESS
Chapter 3. Instruction Set
LOAD REGISTER PAIR IMMEDIATE
LXI
LXI is a three-byte instruction; its second and third bytes contain the source data to be loaded into a register
pair. LXI loads a register pair by copying its second and third bytes into the specified destination register pair.
Opcode
Operand
LXI
The first operand must specify the register pair to be loaded. LXI can load the Band C register pair, the D and
E register pair, the Hand L register pair, or the Stack Pointer.
The second operand specifies the two bytes of data to be loaded~ This data may be coded in the form of a number, an ASCII constant, the label of some previously defined value, or an expression. The data must not exceed
two bytes.
LXI is the only imnediate instruction that accepts a 16-bit value. All other immediate instructions require 8-bit
values.
Notice that the assembler inverts the two bytes of data to create the format of an address stored in memory.
LXI loads its third byte into the first register of the pair and its second byte into the second register of the
pair. This has the effect of reinverting the data into the format required for an address stored in registers. Thus,
the instruction LXI B,'AZ' loads A into register Band Z into register C.
0
0
IR
pE
0
0
1
low-order data
high-order data
Cycles:
States:
Addressing:
Flags:
3
-10
immediate
none
Examples:
A common use for LXI is to establish a memory address for use in subsequent instructions. In the following
sequence, the LXI instruction loads the address of STRNG into the Hand L registers. The MOV instruction then
loads the data stored at that address into the accumulator.
LXI
MOV
H,STRNG
A,M
;SET ADDRESS
;LOAD STRNG INTO ACCUMULATOR
The following LXI instruction is used to initialize the stack pointer in a relocatable module. The LOCATE program provides an address for the special reserved label STACK.
LX I
SP ,ST ACK
3-35
Chapter 3. Instruction Set
MOVE
MOV
The MOV instruction moves one byte of data by copying the source field into the destination field. Source data
remains unchanged. The instruction's operands specify whether the move is from register to register, from a
register to memory, or from memory to a register.
Move Register to Register
Opcode
Operand
MOV
regl,reg2
The instruction copies the contents of reg2 into regl. Each operand must specify one of the registers A, B, C, D,
E, H, or L.
When the same register is specified for both operands (as in MOV A,A), the MOV functions as a NOP (no operation) since it has no other noticeable effect. This form of MOV requires one more machine state than NOP, and
therefore has a slightly longer execution time than NOP. MOV M,M is not permitted.
0
1
1
I
D
D
DI
S
S
51
1
5 (4 on 8085)
register
none
Cycles:
States:
Addressing:
Flags:
Move to Memory
Opcode
Operand
MOV
M,r
This instruction copies the contents of the specified register into the memory location addressed by the Hand L
registers. M refers to the byte addressed by the Hand L register pair. The second operand must address one of the
registers. MOV M,M is not permitted.
oI5
2
7
register indirect
none
Cycles:
States:
Addressing:
Flags:
Move from Memory
3-36
5 51
Opcode
Operand
MOV
r,M
Chapter 3. Instruction Set
This instruction copies the contents of the memory location addressed by the Hand L registers into the specified
"register. The first operand must name the destination register. The second operand must be M. M is a symbolic
reference to the Hand L registers.
I
D
D
Cycles:
States:
Addressing:
Flags:
D
2
7
register indirect
none
Examples:
Label
Opcode
Operands
Comment
LDACC:
MOV
MOV
MOV
A,M
E,A
C,C
;LOAD ACCUM FROM MEMORY
;COPY ACCUM INTO E REG
;NULL OPERATION
NULOP:
MOVE IMMEDIATE
MVI
MVI is a two-byte instruction; its second byte contains the source data to be moved. MVI moves one byte of
data by copying its second byte into the destination field. The instruction's operands specify whether the move
is to a register or to memory.
Move Immediate to Register
Opcode
Operand
MVI
reg,data
The first operand must name one of the registers A through E, H or L as a destination for the move.
The second operand specifies the actual data to be moved. This data may be in the form of a number, an ASCII
constant, the label of some previously defined value, or an expression. The data must not exceed one byte.
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either the
HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the expression.
When neither operator is present, the assembler assumes the LOW operator and issues an error message.
0
D
1°
Cycles:
States:
Addressing:
Flags:
D
D
data
°1
2
7
immediate
none
3-37
Chapter 3. Instructhm Set
MOlle Immediate to Memory
Opcode
Operand
MVI
M,data
This instruction copies the data stored in its second byte into the memory location addressed by Hand L. M is
a symbolic reference to the Hand L register pair.
o
0
o
o
data
Cycles:
States:
Addressing:
Flags:
3
10
immediate/register indirect
none
Examples:
The following examples show a number of methods for defining immediate data in the MVI instruction. All of
the examples generate the bit pattern for the ASCII character A.
MVI
MVI
MVI
MVI
MVI
MVI
M,Ol 000001 B
M,IA'
M,41 H
M,101Q
M,65
M,5+30*2
NOP
NO OPERATION
NOP performs no operation and affects none of the condition flags. NOP is useful as filler in a timing loop.
Opcode
Operand
NOP
Operands are not permitted with the NOP instruction.
ORA
INCLUSIVE OR WITH ACCUMULATOR
ORA performs an inclusive OR logical operation using the contents of the specified byte and the accumulator. The
result is placed in the accumulator.
3-38
Chapter 3. Instruction Set
Summary of Logical Operations
AND produces a one bit in the result only when the corresponding bits in the test data and the mask data are
one.
OR produces a one bit in the result when the corresponding bits in either the test data or the mask data are
ones.
Exclusive OR produces a one bit only when the corresponding bits in the test data and the mask data are
different; i.e., a one bit in either the test data or the mask data - but not both - produces a one bit in the
result.
EXCLUSIVE OR
OR
AND
1010 1010
0000 1111
0000 1010
1010 1010
0000 1111
1010 1111
1010 1010
0000 1111
1.010 0101
OR Register with Accumulator
Opcode
Operand
ORA
reg
The operand must specify one of the registers A through E, H or L. This instruction ORs the contents of the
specified register and the accumulator and stores the result in the accumulator. The carry and auxiliary carry
flags are reset to zero.
o
o s s
Cycles:
States:
Addressing:
Flags:
s
I
1
4
register
Z,S,P,CY,AC
OR Memory with Accumulator
Opcode
Operand
ORA
M
The contents of the memory location specified by the Hand L registers are inciusive-ORed with the contents of
the accumulator. The result is stored in the accumulator. The carry and auxiliary carry flags are reset to zero.
o
Cycles:
States:
Addressing:
Flags:
o
2
7
register indirect
Z,S,P,CY,AC
3·39
Chapter 3. Instruction Set
Example:
Since any bit inclusive-ORed with a one produces a one and any bit ORed with a zero remains unchanged, ORA
is frequently used to set ON particular bits or groups of bits. The following example ensures that bit 3 of the
accumulator is set ON, but the remaining bits are not disturbed. This is frequently done when individual bits
are used as status flags in a program. Assume that register D contains the value 08H:
Accumulator
Register D
o
o
o
1 0 0 0 0 1
0 0 0
000
o
0
o
INCLUSIVE OR IMMEDIATE
ORI
ORI performs an inclusive OR logical operation using the contents of the second byte of the instruction and the
contents of the accumulator. The result is placed in the accumulator. ORI also resets the carry and auxiliary
carry flags to zero.
Opcode
Operand
ORI
data
The operand must specify the data to be used in the inclusive OR operation. This data may be in the form of a
number, an ASCII constant, the label of some previously defined value, or an expression. The data may not
exceed one byte.
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either the
HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the expression.
When neither operator is present, the assembler assume the LOW operator and issues an error message.
o
o
data
Cycles:
States:
Ad dressi ng:
Flags:
2
7
immediate
Z,S,P,SY,AC
Summary of Logical Operations
AND produces a one bit in the result only when the corresponding bits in both the test data and the mask data
are ones.
OR produces a one bit in the result when the corresponding bits in either the test data or the mask data are ones.
Exclusive OR produces a one bit only when the corresponding bits in the test data and the mask data are
different; i.e., a one bit in either the test data or the mask data - but not both - produces a one bit in the
result.
3-40
Chapter 3. Instruction Set
AND
OR
1010 1010
0000 1111
0000 1010
EXCLUSIVE OR
1010 1010
0000 1111
1010 1111
1010 1010
0000 1111
1010 0101
Example:
See the description of the ORA instruction for an example of the use of the inclusive OR. The following
examples show a number of methods for defining immediate data in the ORI instruction. All of the examples
generate the bit pattern for the ASCII character A.
01000001 B
'A'
41H
101Q
ORI
ORI
ORI
ORI
ORI
ORI
65
5+30*2
OUT
OUTPUT TO PORT
The OUT instruction places the contents of the accumulator on the eight-bit data bus and the number of the
selected port on the sixteen-bit address bus. Since the number of ports ranges from 0 through 255, the port
number is duplicated on the address bus.
It is the responsibility of external logic to decode the port number and to accept the output data.
NOTE
Because a discussion of input/output structures is beyond the scope of
this manual, th is description is restricted to the exact function of the
OUT instruction. Input/output structures are described in the 8080 or
8085 Microcomputer Systems User's Manual.
'
Opcode
Operand
OUT
exp
The operand must specify the number of the desired output port. This may be in the form of a number or an
expression in the range OOH through OFFH.
o
0
exp
Cycles:
States:
Addressing:
Flags:
g
3
10
direct
none
3-41
Chapter 3. Instruction Set
MOVE H&L TO PROGRAM COUNTER
PCHL
PCHL loads the contents of the Hand L registers into the program counter register. Because the processor
fetches the next instruction from the updated program counter address, PCHL has the effect of a jump instruction.
Opcode
Operand
PCHL
Operands are not permitted with the PCHL instruction.
PCHL moves the contents of the H register to the high-order eight bits of the program counter and the contents
of the L register to the low-order eight bits of the program counter.
The user program must ensure that the Hand L registers contain the address of an executable instruction when
the PCHL instruction is executed.
o
o
Cycles:
States:
Addressing:
Flags:
0
1
5 (6 on 8085)
register
none
Example:
One technique for passing data to a subroutine is to place the data immediately after the subroutine call. The
return address pushed onto the stack by the CALL instruction actually addresses the data rather than the next
instruction after the CALL. For this example, assume that two bytes of data follow the subroutine call. The
following coding sequence performs a return to the next instruction after the call:
GOBACK:
POP
POP
INR
INR
PCHL
H
L
L
;GET DATA ADDRESS
;ADD 2 TO FORM
;RETURN ADDRESS
;RETURN
POP
The POP instruction removes two bytes of data from the stack and copies them to a register pair or copies the
Program Status Word into the accumulator and the condition flags.
POP Register Pair
POP copies the contents of the memory location addressed by the stack pointer into the low-order register of the
register pair. POP then increments the stack pointer by one and copies the contents of the resulting address into
3-42
Chapter 3. Instruction Set
the high-order register of the pair. POP then increments the stack pointer again so that it addresses the next
older item on the stack.
Opcode
Operand
POP
The operand may specify the B&C, D&E, or the H&L register pairs. POP PSW is explained separately.
E1
IR
Cycles:
States:
Addressing:
Flags:
P
E
0
0
1
I
3
10
register indirect
none
POP PSW
POP PSW uses the contents of the memory location specified by the stack pointer to restore the condition flags.
POP PSW increments the stack pointer by one and restores the contents of that address to the accumulator.
POP then increments the stack pointer again so that it addresses the next older item on the stack.
000
Cycles:
States:
Addressing:
Flags:
3
10
register indirect
Z,S,P,CY,AC
Example:
Assume that a subroutine is called because of an external interrupt. In general, such subroutines should save and
restore any registers it uses so that main program can continue normally when it regains control. The following
sequence of PUSH and POP instructions save and restore the Program Status Word and all the registers:
343
Chapter 3. Instruction Set
PUSH
PUSH
PUSH
PUSH
PSW
B
D
H
subroutine coding
POP
POP
POP
POP
RET
H
D
B
PSW
Notice that the sequence of the POP instructions is the opposite of the PUSH instruction sequence.
PUSH
PUSH
The PUSH instruction copies two bytes of data to the stack. This data may be the contents of a register pair or
the Program Status Word, as explained below:
PUSH Register Pair
PUSH decrements the stack pointer register by one and copies the contents of the high-order register of the
register pair to the resulting address. PUSH then decrements the pointer again and copies the low-order register
to the resulting address. The source registers remain unchanged.
Opcode
Operand
PUSH
The operand may specify the B&C, D& E, or H& L register pairs. PUSH PSW is explained separately.
1
I
R
Cycles:
States:
Addressing:
Flags:
P
o
0
3
11 (130n8085)
register indirect
none
Example:
Assume that register B contains 2AH, the C register contains 4CH, and the stack pointer is set at 9AAF. The
instruction PUSH B stores the B register at memory address 9AAEH and the C register at 9AADH. The stack
pointer is set to 9AADH:
344
Chapter 3. Instruction Set
Stack
Before PUSH
SP before
..
Stack
After PUSH
Address
xx
xx
xx
xx
9AAF
9AAE
9AAD
9AAC
xx
2A
4C
xx
...
SP after
PUSH PSW
PUSH PSW copies the Program Status Word onto the stack. The Program Status Word comprises the contents
of the accumulator and the current settings of the condition flags. Because there are only five condition flags,
PUSH PSW formats the flags into an eight-bit byte as follows:
7
S
6
5
z
o
4
AC
3
2
o
P
o
Icy I
On the 8080, bits 3 and 5 are always zero; bit one is always set to one. These filler bits are undefined on the
8085.
PUSH PSW decrements the stack pointer by one and copies the contents of the accumulator to the resulting
address. PUSH PSW again decrements the pointer and copies the formatted condition flag byte to the resulting
address. The contents of the accumulator and the condition flags remain unchanged.
o
o
Cycles:
States:
Addressing:
Flags:
3
11 (12 on 8085)
register indirect
none
Example:
When a program calls subroutines, it is frequently necessary to preserve the current program status so the calling
program can continue normally when it regains control. Typically, the subroutine performs a PUSH PSW prior to
execution of any instruction that might alter the contents of the accumulator or the condition flag settings.
The subroutine then restores the pre-call system status by executing a POP PSW instruction just before returning
control to the calling program.
ROTATE LEFT THROUGH CARRY
RAL
RAL rotates the contents of the accumulator and the carry flag one bit position to the left. The carry flag, which
is treated as though it were part of the accumulator, transfers to the low-order bit of the accumulator. The highorder bit of the accumulator transfers into the carry flag.
Opcode
Operand
RAL
Operands are not J=.!rmitted with the RAL instruction.
345
Chapter 3. Instruction Set
10
0
o
0
Cycles:
States:
Flags:
4
CYonly
Example:
Assume that the accumulator contains the value OAAH and the carry flag is zero. The following diagrams illustrate the effect of the RAL instruction:
Before:
Carry
o
~--------------~
Accumulator
o
o
o
o
Carry
After:
CD
Accumulator
1
0
0
0
0
01
ROTATE RIGHT THROUGH CARRY
RAR
RAR rotates the contents of the accumulator and the carry flag one bit position to the right. The carry flag,
which is treated as though it were part of the accumulator, transfers to the high-order Qjt of the accumulator.
The low-order bit of the accumulator transfers into the carry flag.
Opcode
Operand
RAR
Operands are not permitted with the RAR instruction.
10
0
Cycles:
States:
Flags:
3-46
0
4
CYonly
Chapter 3. Instruction Set
Example:
Assume that the accumulator contains the value OAAH and the carry flag is zero. The following diagrams illustrate the effect of the RAR instruction:
Before:
Carry
o
Accumulator
o
o
After:
o
o
Carry
Accumulator
[0
o
o
o
RC
RETURN IF CARRY
The RC instruction tests the carry flag. If the flag is set to one to indicate a carry, the instruction pops two
bytes off the stack and places them in the program counter. Program execution resumes at the new address in
the program counter. If the flag is zero, program execution simply continues with the next sequential instruction.
Opcode
Operand
RC
Operands are not permitted with the RC instruction.
~1___0 _______0 __0__~01
Cycles:
States:
Addressing:
Flags:
1 or 3
5 or 11 (6 or 12 on 8085)
register indirect
none
Example:
For the sake of brevity, an example is given for the RET instruction but not for each of its closely related
variants.
347
Chapter 3. Instruction Set
RETURN FROM -SUBROUTINE
RET
The RET instruction pops two bytes of data off the stack and places them in the program counter register.
Program execution resumes at the new address in the program counter.
Typically, RET instructions are used in conjunction with CALL instructions. (The same is true of the variants
of these instructions.) In this case, it is assumed that the data the RET instruction pops off the stack is a
return address placed there by a previous CALL. This has the effect of returning control to the next instruction
after the CALL. The user must be certain that the RET instruction finds the address of executable code on the
stack. If the instruction finds the address of data, the processor attempts to execute the data as though it were
code.
Opcode
Operand
RET
Operands are not permitted with the RET instruction.
o
Cycles:
States:
Addressing:
Flags:
o
0
0
3
10
register indirect
none
Example:
As mentioned previously, subroutines can be nested. That is, a subroutine can call a subroutine that calls
another subroutine. The only practical limit on the number of nested calls is the amount of memory available
for stacking return addresses. A nested subroutine can even call the subroutine that called it, as shown in the
following example. (Notice that the program must contain logic that eventually returns control to the main
program. Otherwise, the two subroutines will call each other indefinitely.)
1 ~ 1·'--~----CALLSUBA
1
MAIN PROGRAM
SUBA:
CALL SUBA
SUBB:
CNZTSUBB
T
.",.
RET .....
RIM (8085 PROCESSOR ONLY)
~~
~~
~ ~~-
T
RET
READ INTERRUPT MASK
The RIM instruction loads eight bits of data into the accumulator. The resulting bit pattern indicates the current
setting of the interrupt mask, the setting of the interrupt flag, pending interrupts, and one bit of serial input data,
if any.
348
Chapter 3. Instruction Set
Operand
Opcode
RIM
Operands are not permitted with the RIM instruction.
The RIM instruction loads the accumulator with the following information:
7
6
5
4
3
2
1
0
SID
17
16
15
IE
7.5
6.5
5.5
LL
"-V~v~
Interrupt Masks:
Interrupt Enable Flag:
I.....---Pending Interrupts:
=
1
=
= masked
enabled
pending
'-----Serial Input Data Bit, if any
The mask and pending flags refer only to the RST5.5, RST6.5, and RST7.5 hdrdware interrupts. The IE flag
refers to the entire interrupt system. Thus, the IE flag is identical in function and level to the INTE pin on the
8080. A 1 bit in this flag indicates that the entire interrupt system is enabled.
E
0
0
0
Cycles:
States:
Flags:
0
0
01
4
none
ROTATE ACCUMULATOR LEFT
RLC
RLC sets the carry flag equal to the high-order bit of the accumulator, thus overwriting its previous setting. RLC
then rotates the contents of the accumulator one bit position to the left with the high-order bit transferring to
the low-order position of the accumulator.
Opcode
Operand
RLC
Operands are not allowed with the RLC instruction.
I0
0
Cycles:
States:
Flags:
0
0
11
0_ _ _---1
4
CYonly
349
Chapter 3. Instruction Set
Example:
Assume that the accumulator contains the value OAAH and the carry flag is zero. The following diagrams illustrate the effect of the RLC instruction.
Before:
Carry
GJ
Accumulator
0
0
After:
0
0
Carry
Accumulator
o
o
RM
RETURN IF MINUS
The RM instruction tests the sign flag. If the flag is set to one to indicate negative data in the accumulator, the
instruction pops two bytes off the stack and places them in the program counter. Program execution resumes at
the new address in the program counter. If the flag is set to zero, program execution simply continues with the
next sequential instruction.
Opcode
Operand
RM
Operands are not permitted with the RM instruction.
o
Cycles:
States:
Addressing:
Flags:
0 01
or 3
5 or 11 (6 or 12 on 8085)
register indirect
none
Example:
For the sake of brevity, an example is given for the RET instruction but not for each of its closely related
variants.
3-50
Chapter 3. Instruction Set
RNC
RETURN IF NO CARRY
The RNC instruction tests the carry flag. If the flag is set to zero to indicate that there has been no carry, the
instruction pops two bytes off the ~tack and places them in the program counter. Program execution resumes at
the new address in the program counter. If the flag is one, program execution simply continues with the next
sequential instruction.
Opcode
Operand
RNC
Operands are not permitted with the RNC instruction.
~1
0
0
0
Cycles:
0
01
States:
or 3
5 or 11 (6 or 12 on 8085)
Addressing:
register indirect
Flags:
none
Example:
For the sake of brevity, an example is given for the RET instruction but not for each of its closely related
variants.
RETURN IF NOT ZERO
RNZ
The RNZ instruction tests the zero flag. If the flag is set to zero to indicate that the contents of the accumulator
are other than zero, the instruction pops two bytes off the stack and places them in the program counter. Program execution resumes at the new address in the program counter. If the flag is set to one, program execution
simply continues with the next sequential instruction.
Opcode
Operand
RNZ
Operands are not permitted with the RNZ instruction.
11
0
Cycles:
States:
Addressing:
Flags:
0
0
0
0
01
or 3
5 or 11 (6 or 12 on 8085)
register indirect
none
Example:
For the sake of brevity, an example is given for the RET instruction but not for each of its closely related
variants.
3-51
Chapter 3. Instruction Set
RETURN IF POSITIVE
RP
The RP instruction tests the sign flag. If the flag is reset to zero to indicate positive data in the accumulator,
the instruction pops two bytes off the stack and places them in the program counter. Program execution
resumes at the new address in the program counter. If the flag is set to one, program execution simply continues
with the next sequential instruction.
Op co de
Operand
RP
Operands are not permitted with the RP instruction.
0
11
Cycles:
States:
Addressing:
Flags:
0
0
01
or 3
5 or 11 (6 or 12 on 8085)
register indirect
none
Example:
For the sake of brevity, an example is given for the RET instruction but not for each of its closely related
variants.
RPE
RETURN IF PARITY EVEN
Parity is even if the byte in
indicate this condition. The
the IN instruction does not
adding OOH to the contents
the accumulator has an even number of one bits. The parity flag is set to one to
RPE and RPO instructions are useful for testing the parity of input data. However,
set any of the condition flags. The flags can be set without altering the data by
of the accumulator.
The RPE instruction tests the parity flag. If the flag is set to one to indicate even parity, the instruction pops
two bytes off the stack and places them in the program counter. Program execution resumes at the new address
in the program counter. If the flag is zero, program execution simply continues with the next sequential instruction.
Opcode
Operand
RPE
Operands are not permitted with the RPE instruction.
11
Cycles:
States:
Addressing:
Flags:
3-52
0
0
0
01
or 3
5 or 11 (6 or 12 on 8085)
register indirect
none
Chapter 3. Instruction Set
Example:
For the sake of brevity, an example is given for the RET instruction but not for each of its closely related
variants.
RPO
RETURN IF PARITY ODD
Parity is odd if the byte in the accumulator has an odd number of one bits. The parity flag is reset to zero to
indicate this condition. The RPO and RPE instructions are useful for testing the parity of input data. However,
the IN instruction does not set any of the condition flags. The flags can be set without altering the data by
adding OOH to the contents of the accumulator.
The RPO instruction tests the parity flag. If the flag is reset to zero to indicate odd parity, the instruction pops
two bytes off the stack and places them in the program counter. Program execution resumes at the new address
in the program counter. If the flag is set to one, program execution simply continues with the next sequential
instruction.
Opeode
Operand
RPO
Operands are not permitted with the RPO instruction.
11
Cycles:
States:
Addressing:
Flags:
0
0
0
0
01
or 3
5 or 11 (6 or 12 on 8085)
register indirect
none
Example:
For the sake of brevity, an example is given for the RET instruction but not for each of its closely related
variants.
ROTATE ACCUMULATOR RIGHT
RRC
RRC sets the carry flag equal to the low-order bit of the accumulator, thus overwriting its previous setting. RRC
then rotates the contents of the accumulator one bit position to the right with the low-order bit transferring to
the high order position of the accumulator.
Opeode
Operand
RRC
Operands are not permitted with the RRC instruction.
3-53
Chapter 3. Instruction Set
10
0
0
0
Cycles:
States:
Flags:
4
CYonly
Example:
Assume that the accumulator contains the value OAAH and the carry flag is zero. The following diagrams illustrate the effect of the RRC instruction:
Carry
Before:
G
Accumulator
0
0
0
After:
Carry
Accumulator
o
o
RESTART
RST
RST is a special purpose CALL instruction designed primarily for use with interrupts. RST pushes the contents
of the program counter onto the stack to provide a return address and then jumps to one of eight predetermined
addresses. A three-bit code carried in the opcode of the RST instruction specifies the jump address.
The restart instruction is unique because it seldom appears as source code in an applications program: More often,
the peripheral devices seeking interrupt service pass this one-byte instruction to the processor.
When a device requests interrupt service and interrupts are enabled, the processor acknowledges the request and
prepares its data lines to accept anyone-byte instruction from the device. RST is generally the instruction of
choice because its special purpose CALL establishes a return to the main program.
The processor moves the three-bit address code from the RST instruction into bits 3, 4, and 5 of the program
counter. In effect, this multiplies the code by eight. Program execution resumes at the new address where eight
bytes are available for code to service the interrupt. If eight bytes are too few, the program can either jump to
or call a subroutine.
3-54
Chapter 3. Instruction Set
8085 NOTE
The 8085 processor includes four hardware inputs that generate internal RST
instructions. Rather than send a RST instruction, the interrupting device need
only apply a signal to the RST5.5, RST6.5, RST7.5, or TRAP input pin.
The processor then generates an internal RST instruction. The execution
depends on the input:
RESTART
ADDRESS
INPUT
NAME
24H
2CH
34H
3CH
TRAP
RST5.5
RST6.5
RST7.5
Notice that these addresses are within the same portion of memory used by the RST instruction, and therefore
allow only four bytes - enough for a call or jump and a return - for the interrupt service routine.
If included in the program code, the RST instruction has the following format:
Opcode
Operand
RST
code
The address code must be a number or expression within the range OOOB through 111 B.
IC
11
C
C
'---y-----/
-
I1
11
---
Program
Counter
15
14
13
12
11
10
9
8
7
6
5
4
3
2
After RST
10
0
0
0
0
0
0
0
0
0
C
C
C
0
~
Cycles:
States:
Addressing:
Flags:
RZ
-
0
0
01
3
11 (12 on 8085)
register indirect
none
RETURN IF ZERO
The RZ instruction tests the zero flag. If the flag is set to one to indicate that the contents of the accumulator are
zero, the instruction pops two bytes of data off the stack and places them in the program counter. Program
execution resumes at the new address in the program counter. If the flag is zero, program execution simply
continues with the next sequential instruction.
3-55
Chapter 3. Instruction Set
Opcode
Operand
RZ
Operands are not permitted with the RZ instruction.
o
o
0
Cycles:
States:
Addressing:
Flags:
0 01
or 3
5 or 11 (6 or 12 on 8085)
register indirect
none
Example:
For the sake of brevity, an example is given for the RET instruction but oot for each of its closely related
variants.
SUBTRACT WITH BORROW
SBB
SBB subtracts one byte of data and the setting of the carry flag from the contents of the accumulator. The
result is stored in the accumulator. SBB then updates the setting of the carry flag to indicate the outcome of
the operation.
SBB's use of the carry flag enables the program to subtract rrulti-byte strings. SBB incorporates the carry flag by
adding it to the byte to be subtracted from the accumulator. It then subtracts the result "from the accumulator
by using two's complement addition. These preliminary operations occur in the processor's internal work registel
so that the source data remains unchanged.
Subtract Register from A ccumulator with Borrow
Opcode
Operand
SBB
reg
The operand must specify one of the registers A through E, H or L. This instruction subtracts the contents of
the specified register and the carry flag from the accumulator and stores the result in the accumulator.
S
Cycles:
States:
Addressing:
Flags:
3-56
S
sl
1
4
register
Z,S,P ,CY ,AC
Chapter 3. Instruction Set
Subtract Memory from A ccumulator with Borrow
Opcode
Operand
SBB
M
This instruction subtracts the carry flag and the contents of the memory location addressed by the Hand L
registers from the accumulator and stores the result in the accumulator.
[0 0
Cycles:
States:
Addressing:
Flags:
2
7
register indirect
Z,S,P,CY,AC
Example:
Assume that register B contains 2, the accumulator contains 4, and the carry flag is set to 1. The instruction
SBB B operates as follows:
2H + carry = 3H
2's complement of 3H
= 11111101
Accumulator = 00000100
11111101
00000001
=
1H
Notice that this two's complement addition produces a carry. When SBB complements the carry bit generated
by the addition, the carry flag is reset OFF. The flag settings resulting from the SBB B instruction are as
follows:
Carry
Sign
Zero
Parity
Aux. Carry
SBI
0
0
0
0
SUBTRACT IMMEDIATE WITH BORROW
SBI subtracts the contents of the second instruction byte and the setting of the carry flag from the contents of
the accumulator. The result is stored in the accumulator.
SBI's use of the carry flag enables the program to subtract multi-byte strings. SBI incorporates the carry flag by
adding it to the byte to be subtracted from the accumulator. It then subtracts the result from the accumulator
by using two's complement addition. These preliminary operations occur in the processor's internal work registers
so that the immediate source data remains unchanged.
3-57
Chapter 3. Instruction Set
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either the
HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the expression.
When neither operator is present, the assembler assumes the LOW operator and issues an error message.
Opcode
Operand
SBI
data
The operand must specify the data to be subtracted. This data may be in the form of a number, an ASCII
constant, the label of some perviously defined value, or an expression. The data may not exceed one byte.
o
Cycles:
States:
Addressing:
Flags:
2
7
immediate
Z,S,P,CY,AC
Example:
This sequence of instructions replaces a 20·byte array at symbolic location AXLOTL with a logical array consisting
of zeros and ones, as follows:
•
•
If an element ofAXLOTL is 5 or greater in absolute value, it is replaced with 1.
If an element ofAXLOTL is less than 5 in absolute value, it is replaced with O.
Note that the program flow is governed by how the carry flag is set.
LOAD:
SMALL:
TEST:
DONE:
SHLD
MVI
XRA
LXI
MOV
SBI
JC
MVI
JMP
MVI
XRA
OCR
CMP
JZ
INX
JMP
B,20
A
H,AXLOTL
A,M
5
SMALL
M,l
TEST
M,O
A
B
B
DONE
H
LOAD
; initialize counter
; clear accumulator and carry
; (H,L) point to array AXLOTL
; load acc. with byte pointed to by (H,L)
; subtract 5, set carry if acc. less than 5
; jump to SMALL if acc. was less than 5
; store 1 where array element was
; jump down to test count
; store 0 where array element was
; clear accumulator and carry
; decrement count
; compare B to 0
; if accum. is zero, all done
; bump (H,L) to point to next array element
; go back and get another array element
; remainder of program
STORE HAND L DIRECT
SHLD stores a copy of the L register in the memory location specified in bytes two and three of the SHLD
instruction. SHLD then stores a copy of the H register in the next higher memory location.
3-58
Chapter 3. Instruction Set
SHLD is one of the instructions provided for saving the contents of the Hand L registers. Alternately, the H
and L data can be placed in the D and E registers (XCHG instruction) or placed on the stack (PUSH and XTHL
instructions).
0
0
1
0
0
0
1
0
low addr
high addr
Cycles:
States:
Addressing:
Flags:
5
16
direct
none
Example:
Assume that the Hand L registers contain OAEH and 29H, respectively. The following is an illustration of the
effect of the SH LD 10AH instruction:
MEMORY ADDRESS
109
00
00
Memory Before SHLD
Memory After SH LD
lOA
00
29
SIM (8085 PROCESSOR ON L Y)
lOB
00
AE
10C
00
00
SET INTERRUPT MASK
SIM is a mUlti-purpose instruction that uses the current contents of the accumulator to perform the following
functions: Set the interrupt mask for the 8085's RST5.5, RST6.5, and RST7.5 hardware interrupts; reset
RST7.5's edge sensitive input; and output bit 7 of the accumulator to the Serial Output Data latch.
Opcode
Operand
SIM
Operands are not permitted with the SIM instruction. However, you must be certain to load the desired bit
configurations into the accumulator before executing the SI M instruction. SI Minterprets the bits in the accumulator as follows:
3-59
Chapter 3. Instruction Set
{
o
= available
1
=
masked
If 0, bits 0 - 2 ignored
{ If 1, mask is set
RESET RST7.S: If 1, RST7.S flip flop is reset OFF
ignored
If 1, bit 7 is ou tput to Serial Output Data Latch
Serial Output Data: ignored if bit 6 = 0
Accumulator bits 3 and 6 function as enable switches. If bit 3 is set ON (set to 1), the set mask function is
enabled. Bits 0 through 2 then mask or leave available the corresponding RST interrupt. A 1 bit masks the
interrupt making it unavailable; a 0 bit leaves the interrupt available. If bit 3 is set OFF (reset to 0), bits 0
through 2 have no effect. Use this option when you want to send a serial output bit without affecting the
interrupt mask.
Notice that the 01 (Disable Interrupts) instruction overrides the SI M instruction. Whether masked or not, RST S.S,
RST6.S, and RST7.S are disabled when the 01 instruction is in effect. Use the RIM (Read Interrupt Mask)
instruction to determine the current settings of the interrupt flag and the interrupt masks.
If bit 6 is set to 1, the serial output data function is enabled. The processor latches accumulator bit 7 into the
SOD output where it can be accessed by a peripheral device. If bit 6 is reset to 0, bit 7 is ignored.
A 1 in accumulator bit 4 resets OFF the RST7.S input flip flop. Unlike RSTS.S and 6.S, RST7.S is sensed via a
processor flip flop that is set when a peripheral device issues a pulse with a rising edge. This edge triggered input
supports devices that cannot maintain an interrupt request until serviced. RST7.S is also useful when a device
does not require any explicit hardware service for each interrupt. For example, the program might increment and
test an event counter for each interrupt rather than service the device directly.
The RST7.S flip flop remains set \Jntil reset by 1) issuing a RESET to the 808S, 2) recognizing the interrupt, or
3) setting accumulator bit 4 and executing a SIM instruction. The Reset RST7.S feature of the SIM instruction
allows the program to override the interrupt.
The RST7.S input flip flop is not affected by the setting of the interrupt mask or the 01 instruction and therefore can be set at any time. However, the interrupt cannot be serviced when RST7.S is masked or a DI instruction
is in effect.
0
0
0
0
1
Cycles:
States:
Flags:
0 01
1
4
none
Example 1: Assume that the accumulator contains the bit pattern 00011100. The SIM instruction resets the
RST7.S flip flop and sets the RST7.S interrupt mask. If an RST7.S interrupt is pending when this SI M instruction
is executed, it is overridden without being serviced. Also, any subsequent RST7.S interrupt is masked and cannot
be serviced until the interrupt mask is reset.
3-60
Chapter 3. Instruction Set
Example 2: Assume that the accumulator contains the bit pattern 11001111. The SI M instruction masks out the
RST5.5, RST6.5, and RST7.5 level interrupts and latches a 1 bit into the SOD input. By contrast, the bit pattern
10000111 has no effect since the enable bits 3 and 6 are not set to ones.
MOVE H& L TO SP
SPHL
SPH L loads the contents of the Hand L registers into the SP (Stack Pointer) register.
Opcode
Operand
SPHL
Operands are not permitted with the SPHL instruction.
SP is a special purpose 16-bit register used to address the stack; the stack must be in random access memory
(RAM). Because different applications use different memory configurations, the user program must load the SP
register with the stack's beginning address. The stack is usually assigned to the highest available location in RAM.
The hardware decrements the stack pointer as items are added to the stack and increments the pointer as items
are removed.
The stack pointer must be initialized before any instruction attempts to access the stack. Typically, stack
initialization occurs very early in the program. Once established, the stack pointer should be altered with
caution. Arbitrary use of SPHL can cause the loss of stack data.
~1__________0__0__~11
Cycles:
States:
Addressing:
Flags:
1
5 (6 on 8085)
register
none
Example:
Assume that the Hand L registers contain 50H and OFFH, respectively. SPHL loads the stack pointer with the
value 50FFH.
STA
STORE ACCUMULATOR DIRECT
ST A stores a copy of the current accumulator contents into the memory location specified in bytes two and
three of the ST A instruction.
Opcode
Operand
STA
address
The address may be stated as a number, a previously defined label, or an expression. The assembler inverts the
high and low address bytes when it builds the instruction.
3-61
Chapter 3. Instruction Set
0
0
1
1
0
0
1
0
lowaddr
high addr
Cycles:
States:
Addressing:
Flags:
4
13
direct
none
Example:
The following instruction stores a copy of the contents of the accumulator at memory location 5B3H:
STA
5B3H
When assembled, the previous instruction has the hexadecimal value 32 B3 05. Notice that the assembler inverts
the high and low order address bytes for proper storage in memory.
STAX
STORE ACCUMULATOR INDIRECT
The STAX instruction stores a copy of the contents of the accumulator into the memory location addressed
by register pair B or register pair D.
Opcode
Operand
STAX
The operand B specifies the Band C register pair; D specifies the D and E register pair. This instruction may
specify only the B or D register pair.
10001100
01
'-v-/
l{o =
= register pair B
1
Cycles:
States:
Addressing:
Flags:
register pair D
2
7
register indirect
none
Example:
If register B contains 3FH and register C contains 16H, the following instruction stores a copy of the contents
of the accumulator at memory location 3F16H:
STAX
3·62
B
Chapter 3. Instruction Set
SET CARRY
STC
STC sets the carry flag to one. No other flags are affected.
Opcode
Operand
STC
Operands are not permitted with the STC instruction.
\0 0
o
Cycles:
States:
Flags:
4
CY
When used in combination with the rotate accumulator through the carry flag instructions, STC allows the program to modify individual bits.
SUBTRACT
SUB
The SUB instruction subtracts one byte of data from the contents of the accumulator. The result is stored in the
accumulator. SUB uses two's complement representation of data as explained in Chapter 2. Notice that the SUB
instruction excludes the carry flag (actually a 'borrow' flag for the purposes of subtraction) but sets the flag to
indicate the outcome of the operation.
Subtract Register from Accumulator
Op co de
Operand
SUB
reg
The operands must specify one of the registers A through E, H or L. The instruction subtracts the contents of
the specified register from the contents of the accumulator using two's complement data representation. The
result is stored in the accumulator.
o
Cycles:
States:
Addressing:
Flags:
S
S
S\
4
register
Z,S,P,CY,AC
Subtract Memory from Accumulator
Opcode
Operand
SUB
M
3-63
Chapter 3. Instruction Set
This instruction subtracts the contents of the memory location addressed by the Hand L registers from the
contents of the accumulator and stores the result in the accumulator. M is a symbolic reference to the Hand L
registers.
o
o
0
2
Cycles:
States:
Addressing:
Flags:
7
register indirect
Z,S,P,CY,AC
Example:
Assume that the accumulator contains 3EH. The instruction SUB A subtracts the contents of the accumulator
from the accumulator and produces a result of zero as follows:
3EH
+(-3EH)
001111"10
11000001
carry out = 1
00000000
1
one's complement
add one to produce two's complement
result = 0
The condition flags are set as follows:
o
o
Carry
Sign
Zero
Parity
Aux. Carry
Notice that the SUB instruction complements the carry generated by the two's complement addition to form a
'borrow' flag. The auxiliary carry flag is set because the particular value used in this example causes a carry out
of bit 3.
SUBTRACT IMMEDIATE
SUI
SU I subtracts the contents of the second instruction byte from the contents of the accumulator and stores the
result in the accumulator. Notice that the SUI instruction disregards the carry ('borrow') flag during the subtraction but sets the flag to indicate the outcome of the operation.
Opcode
Operand
SUI
data
The operand must specify the data to be subtracted. This data may be in the form of a number, an ASCII
constant, the label of some previously defined value, or an expression. The data must not exceed one byte.
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either the
3-64
Chapter 3. Instruction Set
HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the expression.
When neither operator is present, the assembler assumes the LOW operator and issues an error message.
cc=_1___
0 _____
0 _______0~
Cycles:
2
States:
Addressing:
']
Flags:
Z,S,P,CY,AC
immediate
Example:
Assume that the accumulator contains the value 9 when the instruction SUI 1 is executed:
Accumulator
Immediate data (2's comp)
00001001 = 9H
11111111 = -1 H
00001000 = 8H
Notice that this two's complement addition results in a carry. The SUI instruction complements the carry
generated by the addition to form a 'borrow' flag. The flag settings resulting from this operation are as follows:
a
a
a
a
Carry
Sign
Zero
Parity
Aux. Carry
XCHG
EXCHANGE HAND L WITH D AND E
XCHG exchanges the contents of the Hand L registers with the contents of the 0 and E registers.
Opcode
Operand
XCHG
Operands are not allowed with the XCHG instruction.
XCHG both saves the current Hand L and loads a new address into the Hand L registers. Since XCHG is a
register-to-register instruction, it provides the quickest means of saving and/or altering the Hand L registers.
~.__1 ______0 ______0 ______~
Cycles:
States:
Addressing:
Flags:
1
4
register
none
3-65
Chapter 3. Instruction Set
Example:
Assume that the Hand L registers contain 1234H, and the D and E registers contain OABCDH. Following
execution of the XCHG instruction, Hand L contain OABCDH, and D and E contain 1234H.
EXCLUSIVE OR WITH ACCUMULATOR
XRA
XRA performs an excl usive OR logical operation using the contents of the specified byte and the accumulator.
The result is placed in the accumulator.
Summary of Logical Operations
AND produces a one bit in the result only when the corresponding bits in the test data and the mask data are
ones.
OR produces a one bit in the result when the corresponding bits in either the test data or the mask data are
ones.
Exclusive OR produces a one bit only when the corresponding bits in the test data and the mask data are
different; i.e., a one bit in either the test data or the mask data - but not both - produces a one bit in the
result.
OR
AND
10101010
0000 1111
0000 1010
EXCLUSIVE OR
1010 1010
0000 11 n
10101111
1010 1010
0000 1111
10100101
XRA Register with Accumulator
Opcode
Operand
XRA
reg
The operand must specify one of the registers A through E, H or L. This instruction performs an exclusive OR
using the contents of the specified register and the accumulator and stores the result in the accumulator. The
carry and auxil iary carry flags are reset to zero.
o
Cycles:
States:
Addressing:
Flags:
3-66
o
S
S
S
4
register
Z,S,P,CY,AC
Chapter 3. Instruction Set
X RA Memory with Accumulator
Opcode
Operand
XRA
M
The contents of the memory location specified by the Hand L registers is exclusive-ORed with the contents of
the accumulator. The result is stored in the accumulator. The carry and auxiliary carry flags are reset to zero.
~_O_ _O_
Cycles:
States:
Addressing:
Flags:
o
2
"1
register indirect
Z ,S ,P ,CY ,AC
Examples:
Since any bit exclusive-ORed with itself produces zero, XRA is frequently used to zero the accumulator. The
following instructions zero the accumulator and the Band C registers.
XRA
MOV
MOV
A
B,A
C,A
Any bit exclusive-ORed with a one bit is complemented. Thus, if the accumulator contains all ones (OFFH),
the instruction XRA B produces the one's complement of the B register in the accumulator.
XRI
EXCLUSIVE OR IMMEDIATE WITH ACCUMULATOR
XRI performs an exclusive OR operation using the contents of the second instruction byte and the contents of
the accumulator. The result is placed in the accumulator. XRI also resets the carry and auxiliary carry flags to
zero.
Opcode
Operand
XRI
data
The operand must specify the data to be used in the OR operation. This data may be in the form of a number,
an ASCII constant, the label of some previously defined value, or an expression. The data may not exceed one
byte.
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in the operand expression of an immediate instruction, it must be preceded by either the
HIGH or LOW operator to specify which byte of the address is to be used in the evaluation of the expression.
When neither operator is present, the assembler assumes the LOW operator and issues an error message.
3-67
Chapter 3. Instruction Set
o
o
data
Cycles:
States:
Addressing:
Flags:
2
7
immediate
Z,S,P,CY,AC
Summary of Logical Operations
AND produces a one bit in the result only when the corresponding bits in the test data and the mask data are
ones.
OR produces a one bit in the result when the corresponding bits in either the test data or the mask data are
ones.
Exclusive OR produces a one bit only when the corresponding bits in the test data and the mask data are
different; i.e., a one bit in either the test data or the mask data - but not both - produces a one bit in the
resul t.
AND
1010 1010
0000 1111
0000 1010
OR
EXCLUSIVE OR
1010 1010
0000 1111
10101111
1010 1010
0000 11 n
10100101
Example:
Assume that a program uses bits 7 and 6 of a byte as flags that control the calling of two subroutines. The
program tests the bits by rotating the contents of the accumulator until the desired bit is in the carry flag; a
CC instruction (Call if Carry) tests the flag and calls the subroutine if required.
Assume that the control flag byte is positioned normally in the accumulator, and the program must set OFF bit
6 and set bit 7 ON. The remaining bits, which are status flags used for other purposes, must not be altered.
Since any bit exclusive-ORed with a one is complemented, and any bit exclusive-ORed with a zero remains
unchanged, the following instruction is used:
XRI
110000008
The instruction has the following results:
Accumulator
Immediate data
01 001100
11000000
10001100
3-68
Chapter 3. Instruction Set
XTHL
EXCHANGE H&L WITH TOP OF STACK
XTHL exchanges two bytes from the top of the stack with the two bytes stored in the Hand L registers. Thus,
XTHL both saves the current contents of the Hand L registers and loads new values into Hand L.
Opcode
Operand
XTHL
Operands are not allowed with the XTH L instruction.
XTHL exchanges the contents of the L register with the contents of the memory location specified by the SP
(Stack Pointer) register. The contents of the H register are exchanged with the contents of SP+ 1.
000
Cycles:
States:
Addressing:
Flags:
5
18 (16on8085)
register indirect
none
Example:
Assume that the stack pointer register contains 1OADH; register H contai ns OBH and L contains 3CH; and
memory locations 10ADH and 10AEH contain FOH and ODH, respectively. The following is an illustration of
the effect of the XTHL instruction:
Before XTHL
After XTHL
MEMORY ADDRESS
lOAD
10AC
10AE
lOAF
FO
3C
FF
FF
FF
FF
OD
OB
H
L
OB
OD
3C
FO
The stack pointer register remains unchanged following execution of the XTH L instruction.
3-69
4. ASSEMBLER DIRECTIVES
This chapter describes the assembler directives used to control the 8080/85 assembler in its generation of object
code. This chapter excludes the macro directives, which are discussed as a separate topic in Chapter 5.
Generally, directives have the same format as instructions and can be interspersed throughout your program.
Assembler directives discussed in this chapter are grouped as follows:
GENERAL DI RECTIVES:
•
Symbol Definition
EQU
SET
•
Data Definition
DB
DW
•
Memory Reservation
DS
•
Conditional Assembly
IF
ELSE
ENDIF
•
Assembler Termination
END
LOCATION COUNTER CONTROL AND RELOCATION:
•
Location Counter Control
ASEG
DSEG
CSEG
ORG
•
Program Linkage
PUBLIC
EXTRN
NAME
STKLN
4-1
Chapter 4. Assembler Directives
Three assembler directives - EQU, SET, and MACRO - have a slightly different format from assembly
language instructions. The EQU, SET, and MACRO directives require a name for the symbol or macro being
defined to be present in the label field. Names differ from labels in that they must not be terminated with a
colon (:) as labels are. Also, the LOCAL and ENDM directives prohibit the use of the label field.
The MACRO, ENDM, and LOCAL directives are explained in Chapter 5.
SYMBOL DEFINITION
The assembler automatically assigns values to symbols that appear as instruction labels. This value is the current
setting of the location counter when the instruction is assembled. (The location counters are explained under
'Address Control and Relocation,' later in this chapter.)
You may define other symbols and assign them values by using the EQU and SET directives. Symbols defined
using EQU cannot be redefined during assembly; those defined by SET can be assigned new values by subsequent
SET directives.
The name required in the label field of an EQU or SET directive must not be terminated with a colon.
Symbols defined by EQU and SET have meaning throughout the remainder of the program. This may cause the
symbol to have illegal multiple definitions when the EQU or SET directive appears in a macro definition. Use
the LOCAL directive (described in Chapter 5) to avoid this problem.
EQU Directive
EQU assigns the value of 'expression' to the name specified in the label field.
Label
Opcode
Operand
name
EQU
expression
The required name in the label field may not be terminated with a colon. This name cannot be redefined by a
subsequent EQU or SET directive. The EQU expression cannot contain any external symbol. (External symbols
are explained under 'Location Counter Control and Relocation,' later in this chapter.)
Assembly-time evaluation of EQU expressions always generates a modulo 64K address. Thus, the expression always
yields a value in the range 0 - 65535.
Example:
The following EQU directive enters the name ONES into the symbol table and assigns the binary value
11111111 to it:
ONES
4-2
EQU
OFFH
Chapter 4. Assembler Directives
The value assigned by the EQU directive can be recalled in subsequent source lines by referring to its assigned name
as in the following IF directive (where TYPE has been previously defined):
IF TYPE EQ ONES
ENDIF
SET Directive
SET assigns the value of 'expression' to the name specified in the label field.
Label
Opcode
Operand
name
SET
expression
The assembler enters the value of 'expression' into the symbol table. Whenever 'name' is encountered subsequently in the assembly, the assembler substitutes its value from the symbol table. This value remains unchanged
until altered by a subsequent SET directive.
The function of the SET directive is identical to EQU except that 'name' can appear in multiple SET directives
in the same program. Therefore, you can alter the value assigned to 'name' throughout the assembly.
Assembly-time evaluation of SET expressions always generates a modulo 64K address. Thus, the expression always
yields a value in the range 0 - 65535.
Examples:
Label
Opcode
Operand
Assembled Code
IMMED
SET
ADI
5
IMMED
C605
SET
ADI
lOH-6
IMMED
C60A
IMMED
DATA DEFINITION
The DB (define byte) and OW (define word) directives enable you to define data to be stored in your program.
Data can be specified in the form of 8-bit or 16-bit values, or as a string of text characters.
DB Directive
The DB directive stores the specified data in consecutive memory locations starting with the current setting of the
location counter.
4-3
Chapter 4. Assembler Directives
Label
optional:
Opcode
Operands
DB
expression(s) or string(s}
Each symbol in the expression(s) must be previously defined. The operand field of the DB directive can contain a
list of expressions and/or text strings. The list can contain up to eight total items; list items must be separated by
commas. Because of limited workspace, the assembler may not be able to handle a total of eight items when the list
includes a number of complex expressions. If you ever have this problem, it is easily solved: simply use two or more
directives to shorten the list.
Expressions must evaluate to l-byte (8-bit) numbers in the range -256 through 255. Text strings can consist of a
maximum of 128 ASCII characters enclosed in quotes.
The assembler's relocation feature treats all external and relocatable symbols as 16-bit addresses. When one of
these symbols appears in an operand expression of the DB directive, it must be preceded by either the HIGH or
LOW operator to specify which byte of the address is to be used in the evaluation of the expression. When
neither operator is present, the assembler assumes the LOW operator and issues an error message.
If the optional label is present, it is assigned the starting value of the location counter, and thus references
the first byte stored by the DB directive. Therefore, the label STR in the following examples refers to the letter
T of the string TIME.
Examples:
Label
Opcode
Operands
Assembled Code
STR:
DB
'TIME'
54494D45
HERE:
DB
OA3H
A3
WORDl :
DB
-03H,5*2
FDOA
OW Directive
The DW directive stores each 16-bit value from the expression list as an address. The values are stored starting
at the current setting of the location counter.
Label
optional:
Opcode
Operands
DW
expression list
Each symbol in the expression list must be previously defined. The least significant eight bits of the first value in the
expression list are stored at the current setting of the location counter; the most significant eight bits are stored at
the next higher location. This process is repeated for each item in the expression list.
Expressions evaluate to l--word (16-bit) numbers, typically addresses. If an expression evaluates to a single byte,
it is assumed to be the low order byte of a 16-bit word where the high order byte is all zeros.
44
Chapter 4. Assembler Directives
List items must be separated by commas. The list can contain up to eight total items. Because of limited workspace, the assembler may not be able to handle eight complex expressions. If you ever have this problem, simply
use two or more DW directives to shorten the list.
The reversed order for storing the high and low order bytes is the typical format for addresses stored in memory.
Thus, the DW directive is commonly used for storing address constants.
Strings containing one or two ASCII characters enclosed in quotation marks may also appear in the expression
list. When using such strings in your program, remember that the characters are stored in reversed order.
Specifying a string longer than two characters causes an error.
If the optional label is present, it is assigned the starting address of the location counter, and thus references the
first byte stored by the DW directive. (This is the low order byte of the first item in the expression list.)
Examples:
Assume that COMP and FI LL are labels defined elsewhere in the program. COMP addresses memory location
3B1 CH. FI LL addresses memory location 3EB4H.
Label
Op co de
Operands
Assembled Code
ADDR1 :
DW
COMP
1C3B
ADDR2:
DW
FILL
B43E
STRNG:
DW
'A','AB'
41004241
FOUR:
DW
4H
0400
MEMORY RESERVATION
DS Directive
The DS directive can be used to define a block of storage.
Label
optional:
Opcode
Operand
DS
expression
Each symbol in the expression must be previously defined. The value of 'expression' specifies the number of bytes to
be reserved for data storage. In theory, this value may range from OOH through OFFFFH; in practice, you will
reserve no more storage than will fit in your available memory and still leave room for the program.
Any symbol appearing in the operand expression must be defined before the assembler reaches the DS directive.
Unlike the DB and DW directives, DS assembles no data into your program. The contents of the reserved storage
are unpredictable when program execution is initiated.
4-5
Chapter 4. Assembler Directives
If the optional label is present, it is assigned the current value of the location counter, and thus references the
first byte of the reserved memory block.
If the value of the operand expression is zero, no memory is reserved. However, if the optional label is present,
it is assigned the current value of the location counter.
The DS directive reserves memory by incrementing the location counter by the value of the operand expression.
Example:
TIVBUF:
DS
72
;RESERVE 72 BVTES FOR
;A TERMINAL OUTPUT BUFFER
Programming Tips: Data Description and Access
Random Access Versus Read Only Memory
When coding data descriptions, keep in mind the mix of ROM and RAM in your application.
Generally, the DB and DW directives define constants, items that can be assigned to ROM. Vou can use these
items in your program, but you cannot modify them. If these items are assigned to RAM, they have an initial
value that your program can modify during execution. Notice, however, that these initial values must be reloaded
into memory prior to each execution of the program.
Variable data in memory must be assigned to RAM.
Data Description
Before coding your program, you must have a thorough understanding of its input and output data. But you'll
probably find it more convenient to postpone coding the data descriptions until the remainder of the program is
fairly well developed. This way you will have a better idea of the constants and workareas needed in your program.
Also, the organization of a typical program places instructions in lower memory, followed by the data, followed
by the stack.
Data Access
Accessing data from memory is typically a two-step process: First you tell the processor where to find the data,
then the processor fetches the data from memory and loads it into a register, usually the accumulator. Therefore,
the following code sequences have the identical effect of loading the ASCII character A into the accumulator.
AAA:
4-6
DB
'A'
LXI
LDAX
B,AAA
B
ALPHA:
DB
'ABC'
LXI
LDAX
B,ALPHA
B
Chapter 4. Assembler Directives
In the examples, the LXI instructions load the address of the desired data into the Band C registers. The LDAX
instructions then load the accumulator with one byte of data from the address specified in the Band C registers.
The assembler neither knows nor cares that only one character from the three-character field ALPHA has been
accessed. The program must account for the characters at ALPHA+ 1 and ALPHA+2, as in the following coding
sequence:
ALPHA:
DB
'ABC'
;DEFINE ALPHA
LXI
LDAX
B,ALPHA
B
;LOAD ADDRESS OF ALPHA
;FETCH 1ST ALPHA CHAR
INX
LDAX
B
B
;SET B TO ALPHA+l
;FETCH 2ND ALPHA CHAR
INX
LDAX
B
B
;SET B TO ALPHA+2
;FETCH 3RD ALPHA CHAR
The coding above is acceptable for short data fields like ALPHA. For longer fields, you can conserve memory
by setting up an instruction sequence that is executed repeatedly until the source data is exhausted.
Add Symbols for Data Access
The following example was presented earlier as an illustration of the DS directive:
Label
TTYBUF:
Opcode
Operand
Comment
DS
72
;RESERVE TTY BUFFER
To access data in this buffer using only expressions such as TTYBUF+l, TTYBUF+2, ... TTYBUF+72 can be
a laborious and confusing chore, especially when you want only selected fields from the buffer. You can simplifY
this task by subdivid.ing the buffer with the EQU directive:
Opcode
Operand
Comment
TTYBUF:
DS
72
;RESERVE TTY BUFFER
ID
EQU
TTYBUF
;RECORD IDENTIFIER
NAME
EQU
TTYBUF+6
;20-CHAR NAME FIELD
NUMBER
EQU
TTYBUF+26
;10-CHAR EMPLOYEE NUMBER
DEPT
EQU
TTYBUF+36
;5-CHAR DEPARTMENT NUMBER
SSNO
EQU
TTYBUF+41
;SOCIAL SEC. NUMBER
DOH
EQU
TTYBUF+50
;DATE OF HIRE
DESC
EQU
TTYBUF+56
;JOB DESCRIPTION
Label
4-7
Chapter 4. Assembler Directives
Subdividing data as shown in the example simplifies data access and provides useful documentation throughout
your program. Notice that these EQU directives can be inserted anywhere within the program as you need them,
but coding them as shown in the example provides a more useful record description.
CONDITIONAL ASSEMBLY
The IF, ELSE, and ENOIF directives enable you to assemble portions of your program conditionally, that is,
only if certain conditions that you specify are satisfied.
Each symbol within an IF-ENOl F block must be previously defined. Conditional assembly is especially useful when
your application requires custom programs for a number of common options. As an example, assume that a basic
control program requires customizing to accept input from one of six different sensing devices and to drive one of
five different control devices. Rather than code some thirty separate programs to account for all the possibilities,
you can code a single program. The code for the individual sensors and drivers must be enclosed by the conditional
directives. When you need to generate a custom program, you can insert SET directives near the beginning of the
source program to select the desired sensor and driver routines.
IF, ELSE, ENDIF Directives
Because these directives are used in conjunction, they are described together here.
Opcode
Operand
optional:
IF
expression
optional:
ELSE
optional:
ENOIF
Label
Each symbol in the expression must be previously defined. The assembler evaluates the expression in the operand
field of the I F directive. If bit 0 of the resulting value is one (TRUE), all instructions between the I F directive and
the next ELSE or ENOl F directive are assembled. When bit 0 is zero (FALSE) these instructions are ignored.
(A TRUE expression evaluates to OFFFFH and FALSE to OH; only bit zero need be tested.)
All statements included between an I F directive and its required associated ENOl F directive are defined as an
IF-ENOIF block. The ELSE directive is optional, and only one ELSE directive may appear in an IF-ENOIF
block. When included, ELSE is the converse of IF. When bit 0 of the expression in the IF directive is zero, all
statements between ELSE and the next ENOl F are assembled. If bit 0 is one, these statements are ignored.
Operands are not allowed with the ELSE and ENOIF directives.
An IF-ENOl F block may appear within another IF-ENOl F block. These blocks can be nested to eight levels.
Macro definitions (explained in the next chapter) may appear within an IF-ENOl F block. Conversely, IF-EN 01 F
blocks may appear within macro definitions. In either case, you must be certain to terminate the macro definition
4-8
Chapter 4. Assembler Directives
or I F-ENDI F block so that it can be assembled completely. For example, when a macro definition begins in an
IF block but terminates after an ELSE directive, only a portion of the macro can be assembled. Similarly, an
IF-ENDIF block begun within a macro definition must terminate within that same macro definition.
NOTE
Caution is required when symbols are defined in IF -ENDI F
blocks and referenced elsewhere within the program. These
symbols are undefined when the evaluation of the I F expression suppresses the assembly of the IF-ENDIF block.
Example 1.
Simple IF-ENDI F Block (where TYPE has been previously defined):
COND1:
IF TYPE EO 0
;ASSEMBLED IF TYPE = 0'
;15 TRUE
ENDIF
Example 2.
IF-ELSE-ENDIF Block:
COND2:
IF TYPE EO 0
;ASSEMBLED IF TYPE
;15 TRUE
= 0'
ELSE
;ASSEMBLED IF TYPE = 0'
;15 FALSE
ENDIF
4-9
Chapter 4. Assembler Directives
Example 3.
Nested IF's:
COND3:
IF TYPE EO 0
;ASSEMBLED IF TYPE = 0'
;15 TRUE
IF MODE EO 1
LEVEL
;ASSEMBLED IF 'TYPE = 0'
;AND 'MODE = l' ARE BOTH
;TRUE
ENDIF
ELSE
LEVEL
2
;ASSEMBLED IF TYPE = 0'
;15 FALSE
IF MODE EO 2
;ASSEMBLED IF 'TYPE = 0'
;15 FALSE AND 'MODE = 2'
;15 TRUE
LEVEL
ELSE
;ASSEMBLED IF 'TYPE = 0'
;AND 'MODE = 2' ARE BOTH
;FALSE
ENDIF
ENDIF
ASSEMBLER TERMINATION
END Directive
The END directive identifies the end of the source program and terminates each pass of the assembler.
Label
optional:
Opcode
Operand
END
expression
Only one END statement may appear in a source program, and it must be the last source statement.
If the optional expression is present, its value is used as the starting address for program execution. If no expression is given, the assembler assumes zero as the starting address.
When a number of separate program modules are to be joined together, only one may specify a program starting
address. The module with a starting address is the main module. When source files are combined using the INCLUDE control, there are no restrictions on which source file contains the END.
4-10
Chapter 4. Assembler Directives
END-OF-TAPE INDICATION
The EOT directive allows you to specify the physical end of paper tape to simplify assembly of mUltiple-tape source
programs.
EOT Directive
Label
Opcode
optional:
EOT
Operand
When EOT is recognized by the assembler, the message 'NEXT TAPE' is sent to the console and the assembler pauses.'
After the next tape is loaded, a 'space bar' character received at the console signals continuation of the assembly.
Data in the operand field causes an error.
LOCATION COUNTER CONTROL AND RELOCATION
All the directives discussed in the remainder of this chapter relate directly to program relocation except for the
ASEG and ORG directives. These directives are described first for the convenience of readers who do not use the
relocation feature.
Location Counter Control (Non-Relocatable Mode)
When you elect not to use the relocation feature, an assembler default generates an ASEG directive for you. The
ASEG directive specifies that the program is to be assembled in the non-relocatable mode and establishes a
location counter for the assembly.
The location counter performs the same function for the assembler as the program counter performs during
execution. It tells the assembler the next memory location available for instruction or data assembly.
Initially, the location counter is set to zero. The location counter can be altered by the ORG (origin) directive.
ORG Directive
The ORG directive sets the location counter to the value specified by the operand expression.
Label
optional:
Opcode
Operand
ORG
expression
The location counter is set to the value of the operand expression. Assembly-time evaluation of ORG expressions
always yields a modulo 64K address. Thus, the expression always yields an address in the range 0 through
65,535. Any symbol in the expression must be previously defined. The next machine instruction or data item is
assembled at the specified address.
4-11
Chapter 4. Assembler Directives
If no ORG directive is included before the first instruction or data byte in your program, assembly begins at
location zero.
Your program can include any number of ORG directives. Multiple ORG's need not specify addresses in
ascending sequence, but if you fail to do so, you may instruct the assembler to write over some previously
assembled portion of the program.
If the optional label is present, it is assigned the current value of the location counter before it is updated by the
ORG directive.
Example:
Assume that the current value of the location counter is OFH (decimal 15) when the following ORG directive is
encountered:
PAG1:
ORG
OFFH
;ORG ASSEMBLER TO LOCATION
;OFFH (decimal 225)
The symbol PAG1 is assigned the address OFH. The next instruction or data byte is assembled at location
OFFH.
Introduction to Relocatability
A major feature of this assembler is its system for creating relocatable object code modules. Support for this new
feature includes a number of new directives for the assembler and three new programs included in ISIS-II. The
three new programs - LIB, LINK, and LOCATE --- are described in the ISIS-II System User's Guide. The new
assembler directives are described later in this chapter.
Relocatability allows the programmer to code programs or sections of programs without worrying about the
final arrangement of the object code in memory. This offers developers of microcomputer systems major advantages in two areas: memory management and modular program development.
Memory Management
When developing, testing, and debugging a system on your Intcllec microcomputer develof}ment system, your
only concern with locating a program is that it doesn't overlap the resident routines of ISIS-II. Because the
Intellec system has 32K, 48K, or 64K of random access memory, the location of your future program is not a
great concern. However, the program you are developing will almost certainly usc some mix of random access
memory (RAM), read-only memory (ROM), and/or programmable read-only memory (PROM). Therefore, the
location of your program affects both cost and performance in your application. The relocatability feature allows
you to develop, test, and debug your program on the Intellec development system and then simply relocate the
object code to suit your application.
The relocatability feature also has a major advantage at assembly-time: often, large programs with many symbols
cannot be assembled because of limited work space for the symbol table. Such a program can be divided into a
number of modules that can be assembled separately and then linked together to form a single object program.
4-12
Chapter 4. Assembler Directives
Modular Program Development
Although 'relocatability' may seem to be a formidable term, what it really means is that you can subdivide a
complex program into a number of smaller, simpler programs. This concept is best illustrated through the use of
an example. Assume that a microcomputer program is to control the spark advance on an automobile engine.
This requires the program to sample the ambient air temperature, engine air intake temperature, coolant temperature, manifold vacuum, idle sensor, and throttle sensor.
Let us examine the approaches two different programmers might take to solve this problem. Both programmers
want to calculate the degree of spark advance or retardation that provides the best fuel economy with the lowest
emissions. Programmer A codes a single program that senses all inputs and calculates the correct spark advance.
Programmer B uses a modular approach and codes separate programs for each input plus one program to calculate
spark advance.
Although Programmer A avoids the need to learn to use the relocatability feature, the modular approach used
by Programmer B has a number of advantages you should consider:
•
Simplified Program Development
It is generally easier to code, test, and debug several simple programs than one complex program.
•
Sharing the Programming Task
If Programmer B finds that he is falling behind schedule, he can assign one or more of his subprograms to another programmer. Because of his single program concept, Programmer A will
probably have to complete the program himself.
•
Ease of Testing
Programmer B can test and debug most of his modules as soon as they are assembled; Programmer
A must test his program as a whole. Notice that Programmer B has an extra advantage if the
sensors are being developed at the same time as the program. If one of the sensors is behind
schedule, Programmer B can continue developing and testing programs for the sensors that are
ready. Because Programmer A cannot test h is program until all the sensors are developed, his
testing schedule is dependent on events beyond his control.
•
Programming Changes
Given the nature of automotive design, it is reasonable to expect some changes during system
development. If a change to one of the sensors requires a programming change, Programmer A
must search through his entire program to find and alter the coding for that sensor. Then he must
retest the entire program to be certain that those changes do not affect any of the other sensors.
By contrast, Programmer B need be concerned only with the module for that one sensor. This
advantage continues throughout the life of the program.
4-13
Chapter 4. Assembler Directives
DIRECTIVES USED FOR RELOCATION
Several directives have been added to the assembler to support the relocation feature. These fall into the general
categories of location counter control and program linkage.
Location Counter Control (Relocatable Programs)
Relocatable programs or program modules may use three location counters. The ASEG, DSEG, and CSEG
directives specify which location counter is to be used.
The ASEG directive specifies an absolute code segment. Even in a relocatable program module, you may want
to assign certain code segments to specific addresses. For example, restart routines invoked by the RST instruction require specific addresses.
The CSEG directive specifies a relocatable code segment. In general, the CSEG location counter is used for portions of the program that are to be in some form of read-only memory, such as machine instructions and program constants.
The DSEG location counter specifies a relocatable data segment. This location counter is used for program
elements that must be located in random access memory.
These directives allow you to control program segmentation at assembly time. The LOCATE program, described
in the ISIS-II System User's Guide, gives you control over program segment location. Therefore, the guidelines
given above are only general since they can be overridden by the LOCATE program.
Regardless of how many times the ASEG, CSEG, and DSEG directives appear in your program, the assembler
produces a single, contiguous module. This module comprises four segments: code, data, stack and memory.
The LIN K and LOCATE programs are used to combine segments from individual modules and relocate them in
memory. These programs are explained in the ISIS-II System User's Guide.
A SEG Directive
ASEG directs the assembler to use the location counter for the absolute program segment.
Label
optional:
Opcode
Operand
ASEG
Operands are not permitted with the ASEG directive.
All instructions and data following the ASEG directive are assembled in the absolute mode. The ASEG directive
remains in effect until a CSEG or DSEG directive is encountered.
The ASEG location counter has an initial value of zero. The ORG directive can be used to assign a new value to
the ASEG location counter.
4-14
Chapter 4. Assembler Directives
When assembly begins, the assembler assurr.es the ASEG directive to be in effect. Therefore, a CSEG or DSEG
must precede the first instruction or data definition in a relocatable module. If neither of these directives
appears in the program, the entire program is assembled in absolute mode and can be executed immediately
after assembly without using the LINK or LOCATE programs.
CSEG Directive
CSEG directs the assembler to assemble subsequent instructions and data in the relocatable mode using the code
segment location counter.
Label
optional:
Opcode
CSEG
Operand
blank }
PAGE
{ INPAGE
When a program contains multiple CSEG directives, all CSEG directives throughout the program must specify
the same operand. The operand of a CSEG directive has no effect on the current assembly, but is stored with
·the object code to be passed to the LINK and LOCATE programs. (These programs are described in the ISIS-II
System User's Guide.) The LOCATE program uses this information to determine relocation boundaries when it
joins this code segment to code segments from other programs. The meaning of the operand is as follows:
•
blank - This code segment may be relocated to the /lext available byte boundary.
•
PAGE - This code segment must begin on a page boundary when relocated. Page boundaries
occur in multiples of 256 bytes' beginning with zero (0, 256, 512, etc.).
•
INPAGE - This code segment must fit within a single page when relocated.
The CSEG directive
rema~ns
in effect until an ASEG or DSEG directive is encountered.
The code segment location counter has an initial value o,f zero. The ORG directive can be used to assign a new
value to the CSEG location counter.
DSEG Directive
DSEG directs the assembler to assemble subsequent instructions and data in the relocatable mode using the data
segment location counter.
Label
optional:
Opcode
DSEG
Operand
blank
}
PAGE
{
INPAGE
When multiple DSEG directives appear in a program, they must all specify the same operand throughout the
program. The operands for the DSEG directive have the same meaning as for the CSEG directive except that
they apply to the data segment.
4-15
Chapter 4. Assembler Directives
There is no interaction between the operands specified for the DSEG and CSEG directives. Thus, a code segment
can be byte relocatable while the data segment is page relocatable.
The DSEG directive remains in effect until an ASEG or CSEG directive is encountered.
The data segment location counter has an initial value of zero. The ORG directive can be used to assign a new
value to the DSEG location counter.
ORG Directive (Relocatable Mode)
The ORG directive can be used to alter the value of the location counter presently in use.
Label
optional:
Opcode
Operand
ORG
expression
There are three location counters, but only one location counter is in use at any given point in the program.
Which one depends on whether the ASEG, CSEG, or DSEG directive is in effect.
Any symbol used in the operand expression must have been previously defined. An exception causes phase
errors for all labels that follow the ORG and a label error if the undefined error is defined later.
When the ORG directive appears in a relocatable program segment, the value of its operand expression must be
either absolute or relocatable within the current segment. Thus, if the ORG directive appears within a data segment, the value of its expression must be relocatable within the data segment. An error occurs if the expression
evaluates to an address in the code segment.
If the optional label is present, it is assigned the current value of the location counter presently in use before
the ORG directive is executed.
Program Linkage Directives
Modular programming and the relocation feature enable you to assemble and test a number of separate programs
that are to be joined together and executed as a single program. Eventually, it becomes necessary for these
separate programs to communicate information among themselves. Establishing such communication is the
function of the program linkage directives.
A program may share its data addresses and instruction addresses with other programs. Only items having an
entry in the symbol table can be shared with other programs; therefore, the item must be assigned a name or a
label when it is defined in the program. Items to be shared with other programs must be declared in a PUBLIC
directive.
Your program can directly access data or instructions defined in another program if you know the actual
address of the item, but this is unlikely when both programs use relocation. Your program can also gain access
to data or instructions declared as PUBLIC in other programs. Notice, however, that the assembler normally
4-16
Chapter 4. Assembler Directives
flags as an error any reference to a name or label that has not been defined in your program. To avoid this,
you must provide the assembler with a list of items used in your program but defined in some other program.
These items must be declared in an EXTRN directive.
The two remaining program linkage directives, NAME and STKLN, are individually explained later in this chapter.
PUBLIC Directive
The PUBLIC directive makes each of the symbols listed in the operand field available for access by other programs.
Label
optional:
Opcode
Operands
PUBLIC
name--list
Each item in the operand name-list must be the name or label assigned to data or an instruction elsewhere in
this program. When multiple names appear in the list, they must be separated by commas. Each name may be
declared PUBLIC only once in a program module. Reserved words and external symbols (see the EXTRN
directive below) cannot be declared to be PUBLIC symbols.
PUBLIC directives may appear anywhere within a program.module.
If an item in the operand name-list has no corresponding entry in the symbol table (implying that it is undefined), it is flagged as an error.
Example:
PUBLIC
SIN,COS,TAN,SQRT
EXTRN Directive
The EXTRN directive provides the assembler with a list of symbols referenced in this program but defined in a
different program. Because of this, the assembler establishes linkage to the other program and does not flag the
undefi ned references as errors.
Label
Opcode
Operands
optional:
EXTRN
name---list
Each item in the name- -list identifies a symbol that may be referenced in this program but is defined in another
program. When multiple items appear in the list, they must be separated by commas.
If a symbol in the operand name-list is also defined in this program by the user, or is a reserved symbol, the effect
iis the same as defining the same symbol more than once in a program. The assembler flags this error.
EXTRN directives may appear anywhere within a program module.
A symbol may be declared to be external only once in a program module. Symbols declared to be PUBLIC cannot
also be declared to be EXTRN symbols.
4-17
Chapter 4. Assembler Directives
If you omit a symbol from the name-list but reference it in the program, the symbol is undefined. The assembler
flags this error. You may include symbols in the operand name-list that are not referenced in the program without causing an error.
Example:
EXTRN
ENTRY ,ADDRTN,BEG IN
NAME Directive
The NAME directive assigns a name to the object module generated by this assembly.
Label
optional:
Opcode
Operand
NAME
module-name
The NAME directive requires the presence of a module-name in the operand field. This name must conform to
the rules for defining symbols.
Module names are necessary so that you can refer to a module and specify the proper sequence of modules
when a number of modules are to be bound together.
The NAME directive must precede the first data or instruction coding in the source program, but may follow
comments and control lines.
If the NAME directive is missing from the program, the assembler supplies a default NAME directive with the
module-name MODULE. This will cause an error if you attempt to bind together several object program
modules and more than one has the name MODULE. Also, if you make an error coding the NAME directive,
the default name MODULE is assigned.
The module·-name assigned by the NAME directive appears as part of the page heading in the assembly listing.
Example:
NAME
MAIN
STK LN Directive
Regardless of the number of object program modules you may bind together, only one stack is generated. The
STKLN directive allows you to specify the number of bytes to be reserved for the stack for each module.
Label
Opcode
Operand
optional:
STKLN
expression
The operand expression must evaluate to a number which will be used as the maximum size of the stack.
4-18
Chapter 4. Assembler Directives
When the 5TKLN directive is omitted, the assembler provides a default 5TKLN of zero. This is useful when
multiple programs are bound together; only one stack will be generated, so only one program module need
specify the stack size. However, you should provide a 5TKLN if your module is to be tested separately and
uses the stack.
If your program includes more than one 5TKLN directive, only the last value assigned is retained.
Example:
5TKLN
100
5T ACK and MEMORY Reserved Words
The reserved words 5T ACK and MEMORY are not directives but are of interest to programmers using the
relocation feature. These reserved words are external references whose addresses are supplied by the LOCATE
program.
ST ACK is the symbolic reference to the stack origin address. You need this address to initialize the stack
pointer register. Also, you can base data structures on this address using symbolic references such as 5T ACK + 1,
STACK+2, etc.
MEMORY is the symbolic reference to the first byte of unused memory past the end of your program. Again,
you can base data structures on this address using symbolic referen~es such as MEMORY, MEMORY+l, etc.
Programming Tips: Testing Relocatable Modules
The ability to test individual program modules is a major advantage of modular programming. However, many
program modules are not logically self-sufficient and require some modification before they can be tested. The
following is a discussion of some of the more common modifications that may be required.
Initialization Routines
In most complete programs, a number of housekeeping or initialization procedures are performed when execution
first begins. If the program module you are testing relies on initialization procedures assigned to a different
module, you must duplicate those procedures in the module to be tested. (Notice, however, that you can link
any number of modules together for testing.)
One of the most important initialization procedures is to set the stack pointer. The LOCATE program determines
the origin of the stack.
Your program should include the following instruction to initialize the stack pointer:
LXI
5P,5TACK
4-19
Chapter 4. Assembler Directives
Input/Output
When testing program modules, it is likely that some input or output procedures appear in other modules. Your
program must simulate any of these procedures it needs to operate. Since your Intellec development system
probably has considerably more random access memory than you need to test a program module, you may be
able to simulate input and output data right in memory. The LOCATE program supplies an address for the
reserved word MEMORY; this is the address of the first byte of unused memory past the end of your program.
You can· access this memory using the symbolic reference MEMORY, MEMORY+l, and so on. This memory
can be used for storing test data or even for a program that generates test data.
Remove Coding Used for Testing
After testing your program, be certain to remove any code you inserted for testing. In particular, make certain
that only one module in the complete program initializes the stack pointer.
4-20
5. MACROS
INTRODUCTION TO MACROS
Why Use Macros?
A macro is essentially a facility for replacing one set of parameters with another. In developing your program,
you will frequently find that many instruction sequences are repeated several times with only certain parameters
changed.
As an example, suppose that you code a routine that moves five bytes of data from one memory location to
another. A little later, you find yourself coding another routine to move four bytes from a different source
field to a different destination field. If the two routines USE le same coding techniques, you will find that
they are identical except for three parameters: the character count, the source field starting address, and the
destination Held starting address. Certainly it would be handy if there were some way to regenerate that original
routine substituting the new parameters rather than rewrite that code yourself. The macro facility provides this
capability and offers several other advantages over writing code repetitiously:
•
The tedium of frequent rewrite {and the probability of error} is reduced.
•
Symbols used in macros can be restricted so that they have meaning only within the macro itself.
Therefore, as you code your program, you need not worry that you will accidentally duplicate a
symbol used in a macro. Also, a macro can be used any number of times in the same program
without duplicating any of its own symbols.
•
An error detected in a macro need be corrected only once regardless of how many times the macro
appears in the program. This reduces debugging time.
•
Duplication of effort between programmers can be reduced. Useful functions can be collected in a
library to allow macros to be copied into different programs.
In addition, macros can be used to improve program readability and to create structured programs. Using macros
to segment code blocks provides clear program notation and simplifies tracing the flow of the program.
What Is A Macro?
A macro can be described a~ a routine defined in a formal sequence of prototype instructions that, when called
within a program, results in the replacement of each such call with a code expansion consisting of the actual
instructions represented.
5-1
Chapter 5. Macros
The concepts of macro definition, call, and expansion can be illustrated by a typical business form letter, where
the prototype instructions consist of preset text. For example, we could define a macro CNF IRM with the text
Air Flight welcomes you as a passenger.
Your flight number FNO leaves at DTIME and arrives in DEST at ATIME.
This macro has four dummy parameters to be replaced, when the macro is called, by the actual flight number,
departure time, destination, and arrival time. Thus the macro call might look like
CNFIRM
123, '10:45', 'Ontario', '11 :52'
A second macro, CAR, could be called if the passenger has requested that a rental car be reserved at the destination airport. This macro might have the text
Your automobile reservation has been confirmed with MAKE rent-a-car agency.
Finally, a macro GREET could be defined to specify the passenger name.
Dear NAME:
The entire text of the business letter (source file) would then look like
GREET 'Ms. Scannel'
CN FI RM 123, '10:45', 'Ontario', '11: 52'
CAR 'Blotz'
We trust you will enjoy your flight.
Sincerely,
When this source file is passed through a macro processor, the macro calls are expanded to produce the following
letter.
Dear Ms. Scannel:
Air Flight welcomes you as a passenger. Your flight number 123 leaves at 10:45 and arrives
in Ontario at 11: 52. Your automobile reservation has been confirmed with Blotz rent-a-car
agency.
We trust you will enjoy your flight.
Sincerely,
While this example illustrates the substitution of parameters in a macro, it overlooks the relationship of the macro
processor and the assembler. The purpose of the macro processor is to generate source code which is then
assembled.
5-2
Chapter 5. Macros
Macros Vs. Subroutines
At this point, you may be wondering how macros differ from subroutines invoked by the CALL instruction.
Both aid program structuring and reduce the coding of frequently executed routines.
One distinction between the two is that subroutines necessarily branch to another part of your program while
macros generate in-line code. Thus, a program contains only one version of a given subroutine, but contains as
many versions of a given macro as there are calls for that macro.
Notice the emphasis on 'versions' in the previous sentence, for this is a major difference between macros and
subroutines. A macro does not necessarily generate the same source code each time it is called. By changing the
parameters in a macro call, you can change the source code the macro generates. In addition, macro parameters
can be tested at assembly-time by the conditional assembly directives. These two tools enable a general-purpose
macro definition to generate customized source code for a particular programming situation. Notice that macro
expansion and any code customization occur at assembly-time and at the source code level. By contrast, a
generalized subroutine resides in your program and requires execution time.
It is usually possible to obtain similar results using either a macro or a subroutine. Determining which of these
facilities to use is not always an obvious decision. In some cases, using a single subroutine rather than multiple
in-line macros can reduce the overall program size. In situations involving a large number of parameters, the use
of macros may be more efficient. Also, notice that macros can call subroutines, and subroutines can contain
macros.
USING MACROS
The assembler recognizes the following macro operations:
•
•
•
•
•
•
•
•
MACRO directive
ENDM directive
LOCAL directive
REPT directive
I RP directive
IRPC directive
EXITM directive
Macro call
All of the directives listed above are related to macro definition. The macro call initiates the parameter substitution (macro expansion) process.
Macro Definition
Macros must be defined in your program before they can be used. A macro definition is initiated by the MACRO
assembler directive, which lists the name by which the macro can later be called, and the dummy parameters to
be replaced during macro expansion. The macro definition is terminated by the ENDM directive. The prototype
instructions bounded by the MACRO and ENDM directives are called the macro body.
5-3
Chapter 5. Macros
When label symbols used in a macro body have 'global' scope, multiply-defined symbol errors result if the macro
is called more than once. A label can be given limited scope using the LOCAL directive. This directive assigns a
unique value to the symbol each time the macro is called and expanded. Dummy parameters also have limited
scope.
Occasionally you may wish to duplicate a block of code several times, either within a macro or in line with
other source code. This can be accomplished with minimal coding effort using the REPT (repeat block), IRP
{indefinite repeat}, and IRPC {indefinite repeat character} directives. Like the MACRO directive, these directives
are terminated by ENDM.
The EXITM directive provides an alternate exit from a macro. When encountered, it terminates the current macro
just as if ENDM had been encountered.
Macro Definition Directives
MA eRO Directive
Label
Opcode
Operand
name
MACRO
optional dummy parameter{s}
The name in the label field specifies the name of the macro body being defined. Any valid user-defined symbol
name can be used as a macro name. Note that this name must be present and must not be term inated by a colon.
A dummy parameter can be any valid user-defined symbol name or can be null. When mUltiple parameters are listed,
they must be separated by commas. The scope of a dummy parameter is limited to its specific macro definition. If a
reserved symbol is used as a dummy parameter, its reserved value is not recognized. For example, if you code
A,B,C as a dummy parameter list, substitutions will occur properly. However, you cannot use the accumulator
or the Band C registers within the macro. Because of the limited scope of dummy parameters, the use of these
registers is not affected outside the macro definition.
Dummy parameters in a comment are not recognized. No substitution occurs for such parameters.
Dummy parameters may appear in a character string. However, the dummy parameter must be adjacent to an
ampersand character (&) as explained later in this chapter.
Any machine instruction or applicable assembler directive can be included in the macro body. The distinguishing
feature of macro prototype text is that parts of it can be made variable by placing substitutable dummy parameters in instruction fields. These dummy parameters are the same as the symbols in the operand field of the
MACRO directive.
Example:
Define macro MACl with dummy parameters Gl, G2, and G3.
5-4
Chapter 5. Macros
NOTE
The following macro definition contains a potential error
that is clarified in the description of the LOCAL directive
later in this chapter.
MACl
MOVES:
MACRO
LHLD
MOV
LHLD
MOV
LHLD
MOV
ENDM
Gl,G2,G3
Gl
A,M
G2
B,M
G3
C,M
Label
Opcode
;MACRO DIRECTIVE
;MACRO BODY
;ENDM DIRECTIVE
ENDM Directive
Operand
ENDM
The ENDM directive is required to terminate a macro definition and follows the last prototype instruction. It is
also required to terminate code repetition blocks defined by the REPT, I RP, and IRPC directives.
Any data appearing in the label or operand fields of an ENDM directive causes an error.
NOTE
Because nested macro calls are not expanded during macro
definition, the ENDM directive to close an outer macro cannot be contained in the expansion of an inner, 'nested'
macro call. (See 'Nested Macro Definitions' later in this
chapter.)
L.OCA L Directive
Label
Opcode
Operand
LOCAL
label name{s)
The specified label names are defined to have meaning only within the current macro expansion. Each time the
macro is called and expanded, the assembler assigns each local symbol a unique symbol in the form ??nnnn.
I
The assembler assigns ??OOOl to the first local symbol, ??0002 to the second, and so on. The most recent symbol
name generated always indicates the total number of symbols created for all macro expansions. The assembler
never duplicates these symbols. The user should avoid coding symbols in the form ??nnnn so that there will not
be a conflict with these assembler-generated symbols.
5-5
Chapter 5. Macros
Dummy parameters included in a macro call cannot be operands of a LOCAL directive. The scope of a dummy
parameter is always local to its own macro definition.
Local symbols can be defined only within a macro definition. Any number of LOCAL directives may appear in
a macro definition, but they must all follow the macro call and must precede the first line of prototype code.
A LOCAL directive appearing outside a macro definition causes an error. Also, a name appearing in the label
field of a LOCAL directive causes an error.
Example:
The definition of MACl (used as an example in the description of the MACRO directive) contains a potential
error because the symbol MOVES has not been declared local. This is a potential error since no error occurs if
MACl is called only once in the program, and the program itself does not use MOVES as a symbol. However,
if MACl is called more than once, or if the program uses the symbol MOVES, MOVES is a multiply-defined
symbol. This potential error is avoided by naming MOVES in the operand field of a LOCAL directive:
MACl
MOVES:
MACRO
LOCAL
LHLD
MOV
LHLD
MOV
LHLD
MOV
ENDM
G-I,G2,G3
MOVES
Gl
A,M
G2
B,M
G3
C,M
Assume that MACl is the only macro in the program and that it is called twice. The first time MACl is expanded,
MOVES is replaced with the symbol ??OOOl; the second time, MOVES is replaced with ??0002. Because the
assembler encounters only these special replacement symbols, the program may contain the symbol MOVES
without causing a multiple definition.
REPT Directive
Label
optional:
Opcode
Operand
REPT
expression
The REPT directive causes a sequence of source code lines to be repeated 'expression' times. All lines appearing
between the REPT directive and a subsequent ENDM directive constitute the block to be repeated.
When 'expression' contains symbol ic names, the assembler must encounter the definition of the symbol prior to
encou nteri ng the expression.
The insertion of repeat blocks is performed in-line when the assembler encounters the REPT directive. No
explicit call is required to cause the code insertion since the definition is an implied call for expansion.
5-6
Chapter 5. Macros
Example 1:
Rotate accumulator right six times.
ROTR6:
REPT
RRC
ENDM
6
Example 2:
The following REPT directive generates the source code for a routine that fills a five-byte field with the character
stored in the accumulator:
PROGRAM CODE
LHLD
REPT
MOV
INX
ENDM
CNTRl
5
M,A
H
GENERATED CODING
LHLD
MOV
INX
MOV
INX
MOV
INX
MOV
INX
MOV
INX
CNTRl
M,A
H
M,A
H
M,A
H
M,A
H
M,A
H
Example 3:
The following example illustrates the use of REPT to generate a multiplication routine. The multiplication is
accomplished through a series of shifts. If this technique is unf';lmiliar, refer to the example of multiplication
in Chapter 6. The example in Chapter 6 uses a program loop for the multiplication. This example replaces the
loop with seven repetitions of the four instructions enclosed by the REPT -ENDM directives.
Notice that the expansion specified by this REPT directive causes the label SKIPAD to be generated seven times.
Therefore, SKIPAD must be declared local to this macro.
FSTMUL:
SKIPAD:
MVI
LXI
D,O
H,O
REPT
LOCAL
RLC
JNC
DAD
DAD
ENDM
-RLC
RNC
DAD
RET
7
;FAST MULTIPLY ROUTINE
;MULTIPL Y E*A - 16-BIT RESULT
;IN H&L
SKIPAD
SKIPAD
D
;;GET NEXT MULTIPLIER BIT
;;DON'T ADD IF BIT =
;;ADD MULTIPLICAND INTO ANSWER
°
H
D
5-7
Chapter 5. Macros
This example illustrates a classic programming trade-off: speed versus memory. Although this example executes
more quickly than the example in Chapter 6, it requires more memory.
IRP Directive
Label
optional:
Opcode
Operand
IRP
dummy param, <list>
The operand field for the IRP (indefinite repeat) directive must contain one macro dummy parameter followed
by a list of actual parameters enclosed in angle brackets. I RP expands its associated macro prototype code substituting the first actual parameter for each occurrence of the dummy parameter. IRP then expands the prototype code again substituting the second actual parameter from the list. This process continues until the list is
exhausted.
The list of actual parameters to be substituted for the dummy parameter must be enclosed in angle brackets
«
Individual items in the list must be separated by commas. The number of actual parameters in the list
controls the number of times the macro body is repeated; a list of n items causes n repetitions. An empty list
(one with no parameters coded) specifies a null operand list. IRP generates one copy of the macro body substituting a null for each occurrence of the dummy parameter. Also, two commas with no intervening character
create a null parameter within the list. (See 'Special Operators' later in this chapter for a description of null
operands.)
».
Example:
The following code sequence gathers bytes of data from different areas of memory and then stores them in
consecutive bytes beginning at the address of STORIT:
PROGRAM CODE
GENERA TED CODING
LXI
IRP
LOA
MOV
INX
EN OM
LXI
LOA
MOV
INX
LOA
MOV
INX
LOA
MOV
INX
H,STORIT
X,<FLO',3E20H,FL03>
X
M,A
H
H,STORIT
FLOl
M,A
H
3E20H
M,A
H
FL03
M,A
H
I RPC Directive
Label
optional:
5-8
Opcode
Operand
IRPC
dummy param,text
Chapter 5. Macros
The I RPC (indefinite repeat character) directive causes a sequence of macro prototype instructions to be repeated
for each text character of the actual parameter specified. If the text string is enclosed in optional angle brackets,
any delimiters appearing in the text string are treated simply as text to be substituted into the prototype code.
The assembler generates one iteration of the prototype code for each character in the text string. For each
iteration, the assembler substitutes the next character from the string for each occurrence of the dummy parameter. A list of n text characters generates n repetitions of the IRPC macro body. An empty string specifies a
null actual operand. IRPC generates one copy of the macro body substituting a null for each occurrence of the
dummy parameter.
Example:
PROGRAM CODE
MVDATE:
LHLD
IRPC
INX
MVI
ENDM
GENERA TED COEJING
DATE-1
X,1977
H
M,X
LHLD
INX
MVI
INX
MVI
INX
MVI
INX
MVI
DATE-l
H
M,l
H
M,9
H
M,7
H
M,7
IRPC provides the capability to treat each character of a string individually; concatenation (described later in this
chapter) provides the capability for building text strings from individual characters.
EXITM Directive
Label
Opcode
optional:
EXITM
Operand
EXITM provides an alternate method for terminating a macro expansion or the repetition of a REPT, IRP, or
I RPC code sequence. When EXITM is encountered, the assembler ignores all macro prototype instructions
located between the EXITM and ENDM directive for this macro. Notice that EXITM may be used in addition
to ENDM, but not in place of ENDM.
When used in nested macros, EXITM causes an exit to the previous level of macro expansion. An EXITM within
a REPT, I RP, or I RPC terminates not only the current expansion, but all subsequent iterations as well.
Any data appearing in the operand field of an EXITM directive causes an error.
Example:
EXITM is typically used to suppress unwanted macro expansion. In the following example, macro expansion is
terminated when the EXITM directive is assembled because the condition X EO 0 is true.
5·9
Chapter 5. Macros
MAC3
MACRO
X,Y
IF X EO 0
EXITM
ENDM
Special Macro Operators
In certain special cases, the normal rules for dealing with macros do not work. Assume, for example, that you
want to specify three actual parameters, and the second parameter happens to be the comma character. To the
assembler, the list PARMl ",PARM3 appears to be a list of four parameters where the second and third parameters are missing. The list can be passed correctly by enclosing the comma in angle brackets: PARM1,<,l,PARM3.
These special operators instruct the assembler to accept the enclosed character (the comma) as an actual parameter rather than a del im iter.
The assembler recognizes a number of operators that allow special operations:
&
Ampersand. Used to concatenate (link) text and dummy parameters. See the further
discussion of ampersands below.
<>
Angle brackets. Used to delimit text, such as lists, that contain other delimiters.
Notice that blanks are usually treated as delimiters. Therefore, when an actual
parameter contains blanks (passing the instruction MOY A,M, for example) the
parameter must be enclosed in angle brackets. This is also true for any other delimiter that is' to be passed as part of an actual parameter. To pass such text to
nested macro calls, use one set of angle brackets for each level of nesting. (See
'Nested Macro Definitions,' below.)
.,
"
Double semicolon. Used before a comment in a macro definition to prevent
inclusion of the comment in expansions of the macro and reduce storage
requirements. The comment still appears in the listing of the definition.
Exclamation point (escape character). Placed before a character (usually a
delimiter) to be passed as literalized text in an actual parameter. Used primarily
to pass angle brackets as part of an actual parameter. To pass a literal ized
exclamation point, issue!!. Carriage returns cannot be passed as actual parameters.
The '!' is always preserved while building an actual parameter. It is not
echoed when an actual parameter is substituted for a dummy parameter,
except when the substitution is being used to build another actual parameter.
5-10
Chapter 5. Macros
NUL
In certain cases it is not necessary to pass a parameter to a macro. It is
necessary, however, to indicate the omission of the parameter. The omitted
{or null} parameter can be represented by two consecutive delimiters as in
the list PARMl "PARM3. A null parameter can also be represented by two
consecutive single quotes: ",PARM2,PARM3. Notice that a null is quite
different from a blank: a blank is an ASCII character with the hexadecimal
representation 20H; a null has no character representation. In the assembly
listing a null looks the same as a blank, but that is only because no substitution has taken place. The programmer must decide the meaning of a null
parameter. Although the mechanism is somewhat different, the defaults taken
for assembler controls provide a good example of what a null parameter can
mean. For example, coding MOD85 as an assembler control specifies that
the assembler is to generate object code for the 8085. The absence of this
control {which in effect is a null parameter} specifies that the assembler
is to generate only 8080 object code.
Assembler controls are explained in the 1515-1/ 8080/8085 Macro Assembler
Operator's Manual, 9800292.
Example:
In a macro with the dummy parameters W,X,Y,Z it is acceptable for either
the X or Y parameter to be null, but not both. The following I F directive
tests for the error condition:
IF NUL X&Y
EXITM
When a macro is expanded, any ampersand preceding or following a dummy parameter in a macro definition is
removed and the substitution of the actual parameter occurs at that point. When it is not adjacent to a dummy
parameter, the ampersand is not removed and is passed as part of the macro expansion text.
NOTE
The ampersand must be immediately adjacent to the text being
concatenated; intervening blanks are not allowed.
If nested macro definitions (described below) contain ampersands, the only ampersands removed are those adjacent
to dummy parameters belonging to the macro definition currently being expanded. All ampersands must be removed by the time the expansion of the encompassing macro body is performed. Exceptions force illegal character
errors.
Ampersands placed inside strings are recognized as concatenation delimiters when adjacent to dummy parameters;
similarly, dummy parameters within character strings are recognized only when they are adjacent to ampersands.
Ampersands are not recognized as operators in comments.
5-11
Chapter 5. Macros
Nested Macro Definitions
A macro definition can be contained completely within the, body of another macro definition (that is, macro
definitions can be nested). The body of a macro consists of all text (including nested macro definitions)
bounded by matching MACRO and ENDM directives. The assembler allows any number of macro definitions to
be nested.
When a higher-level macro is called for expansion, the next lower-level macro is defined and eligible to be called
for expansion. A lower-level macro cannot be called unless all higher-level macro definitions have already been
called and expanded.
A new macro may be defined or an existing macro redefined by a nested macro definition depending on whether
the name of the nested macro is a new label or has previously been established as a dummy parameter in a
higher-level macro definition. Therefore, each time a higher-level macro is called, a lower-level definition can be
defined differently if the two contain common dummy parameters. Such redefinition can be costly, however, in
terms of assembler execution speed.
Since I RP, I RPC, and REPT blocks constitute macro definitions, they also can be nested within another definition
created by IRP, IRPC, REPT, or MACRO directives. In addition, an element in an IRP or IRPC actual parameter
list (enclosed in angle brackets) may itself be a list of bracketed parameters; that is, lists of parameters can contain
elements that are also lists.
Example:
LISTS
MACRO
PARAM1,PARAM2
ENDM
MACRO CALLS
Once a macro has been defined, it can be called any number of times in the program. The call consists of the
macro name and any actual parameters that are to replace dummy parameters during macro expansion. During
assembly, each macro call is replaced by the macro definition code; dummy parameters are replaced by actual
parameters.
Macro Call Format
Label
optional:
5-12
Opcode
macro name
Operand
optional actual
parameter(s)
Chapter 5. Macros
The assembler must encounter the macro definition before the first call for that macro. Otherwise, the macro
call is assumed to be an illegal opcode. The assembler inserts the macro body identified by the macro name
each time it encounters a call to a previously defined macro in your program.
The positioning of actual parameters in a macro call is critical since the substitution of parameters is based
solely on position. The first-listed actual parameter replaces each occurrence of the first-listed dummy parameter; the second actual parameter replaces the second dummy parameter, and so on. When coding a macro call,
you must be certain to list actual parameters in the appropriate sequence for the macro.
Notice that blanks are usually treated as delimiters. Therefore, when an actual parameter contains blanks
(passing the instruction MOV A,M, for example) the parameter must be enclosed in angle brackets. This is also
true for any other delimiter that is to be passed as part of an actual parameter. Carriage returns cannot be passed
as actual parameters.
If a macro call specifies more actual parameters than are listed in the macro definition, the extra parameters
are ignored. If fewer parameters appear in the call than in the definition, a null replaces each missing parameter.
Example:
The following example shows two calls for the macro LOAD. LOAD is defined as follows:
LOAD
MOVES:
MACRO
LOCAL
LHLD
MOV
LHLD
MOV
LHLD
MOV
ENDM
Gl,G2,G3
MOVES
Gl
A,M
G2
B,M
G3
C,M
LOAD simply loads the accumulator with a byte of data from the location specified by the first actual parameter,
the B register with a byte from the second parameter, and the C register with a byte from the third parameter.
The first time LOAD is called, it is used as part of a routine that inverts the order of three bytes in memory.
The second time LOAD is called, it is part of a routine that adds the contents of the B register to the accumulator and then compares the result with the contents of the C register.
5-13
Chapter 5. Macros
SUBSTITUTION
MAIN PROGRAM
JNZ NEXT
LOAD FLD,FLD+l,FLD+2
;INVERT BYTES
M,A
MOV
H
DCX
M,B
MOV
H
DCX
M,C
MOV
LOAD 3EOH,BYTE,CHECK
;CHECK DIGIT
B
ADD
C
CMP
DGTBAD
CNZ
??OOOl:
??OOO2:
JNZ
LHLD
MOV
LHLD
MOV
LHLD
MOV
MOV
DCX
MOV
DCX
MOV
LHLD
MOV
LHLD
MOV
LHLD
MOV
ADD
CMP
CNZ
NEXT
FLO
A,M
FLD+l
B,M
FLD+2
C,M
;INVERT BYTES
M,A
H
M,B
H
M,C
3EOH
A,M
BYTE
B,M
CHECK
C,M
;CHECK DIGIT
B
C
DGTBAD
Nested Macro Calls
Macro calls (including any combination of nested IRP, IRPC, and REPT constructs) can be nested within macro
definitions up to eight levels. The macro being called need not be defined when the enclosing macro is defined;
however, it must be defined before the enclosing macro is called.
A macro definition can also contain nested calls to itself (recursive macro calls) up to eight levels, as long as the
recursive macro exp~nsions can be terminated eventually. This operation can be controlled using the conditional
assembly directives described in Chapter 4 (I F, ELSE, ENOl F).
Example:
Have a macro call itself five times after it is called from elsewhere in the program.
PARAMl
RECALL
PARAMl
SET
MACRO
5
IF
SET
RECALL
ENDIF
PARAMl NE 0
PARAM1-l
ENDM
.5-14
;RECURSIVE CALL
Chapter 5. Macros
Macro Expansion
When a macro is called, the actual parameters to be substituted into the prototype code can be passed in one of
two modes. Normally, the substitution of actual parameters for dummy parameters is simply a text substitution.
The parameters are not evaluated until the macro is expanded.
If a percent sign (%) precedes the actual parameter in the macro call, however, the parameter is evaluated
immediately, before expansion occurs, and is passed as a decimal number representing the value of the parameter. In the case of I RPC, a '%' preceding the actual parameter causes the entire text string to be treated as a
single parameter. One I RPC iteration occurs for each digit in the decimal string passed as the result of immediate
evaluation of the text string.
The normal mechanism for passing actual parameters is adequate for most applications. Using the percent sign
to pre-evaluate parameters is necessary only when the value of the parameter is different within the local context of the macro definition as compared to its global value outside the macro definition.
Example:
The macro shown in this example generates a number of rotate instructions. The parameters passed in the macro
call determine the number of positions the accumulator is to be rotated and whether rotate right or rotate left
instructions are to be generated. Some typical calls for "this macro are as follows:
SHIFTR
SHIFTR
'R',3
L,%COUNT -1
The second call shows an expression used as a parameter. This expression is to be evaluated immediately rather
than passed simply as text.
The definition of the SHIFTR macro is shown below. This macro uses the conditional IF directive to test the
validity of the first parameter. Also, the REPT macro directive is nested within the SHIFTR macro.
SHIFTR
MACRO
IF X EO 'R'
REPT Y
RAR
ENDM
ENDIF
IF X NE 'L'
EXITM
ELSE
REPT Y
RAL
ENDM
ENDIF
ENDM
X,Y
The indentation shown in the definition of the SHIFTR macro graphically illustrates the relationships of the IF,
ELSE, END I F directives and the REPT, ENDM directives. Such indentation is not required in your program, but
may be desirable as documentation.
5-15
Chapter 5. Macros
The SHI FTR macro generates nothing if the first parameter is neither R nor L. Therefore, the following calls
produce'no code. The result in the object program is as though the SHIFTR macro does not appear in the
source program.
SHIFTR
SHIFTR
5
'6',2
The following call to the SHIFTR macro generates three RAR instructions:
SHIFTR
'R',3
Assume that a SET directive elsewhere in the source program has given COUNT the value 6. The following call
generates five RAL instructions:
SHIFTR
'L',%COUNT -1
The following is a redefinition of the SHIFTR macro. In this definition, notice that concatenation is used to
form the RAR or RAL operation code. If a call to the SHIFTR macro specifies a character other than R or L,
illegal operation codes are generated. The assembler flags all illegal operation codes as errors.
SHIFTR
MACRO
REPT
RA&X
ENDM
ENDM
X,Y
Y
NULL MACROS
A macro may legally comprise only the MACRO and ENDM directives. Thus, the following is a legal macro
definition:
NADA
MACRO
ENDM
P1,P2,P3,P4
A call to this macro produces no source code and therefore has no effect on the program.
Although there is no reason to write such a macro, the null (or empty) macro body has a practical application.
For example, all the macro prototype instructions might be enclosed with IF-END IF conditional directives.
When none of the specified conditions is satisfied, all that remains of the macro is the MACRO directive and
the ENDM directive.
SAMPLE MACROS
The following sample macros further demonstrate the use of macro directives and operators.
5-16
Chapter 5. Macros
Example 1: Nested IRPC
The following macro definition contains a nested IRPC directive. Notice that the third operand of the outer
macro becomes the character string for the IRPC:
MOVE
MACRO
IRPC
LHLD
SHLD
ENDM
ENDM
X,Y,Z
PARAM,Z
X&&PARAM
Y&&PARAM
Assume that the program contains the call MOVE SRC,DST,123. The third parameter of this call is passed to
the IRPC. This has the same effect as coding IRPC PARAM,123. When expanded, the MOVE macro generates
the following source code:
LHLD
SHLD
LHLD
SHLD
LHLD
SHLD
SRCl
DSTl
SRC2
DST2
SRC3
DST3
Notice the use of concatenation to form labels in this example.
Example 2: Nested Macros Used to Generate DB Directives
This example generates a number of DB 0 directives, each with its own label. Two macros are used for this
purpose: INC and BLOCK. The INC macro is defined as follows:
INC
$ SAVE GEN
Fl &F2:
$ RESTORE
MACRO
Fl,F2
DB
o
;GENERATE LABELS & DB's
ENDM
The BLOCK macro, which accepts the number of DB's to be generated (NUMB) and a label prefix (PREFIX), is
defined as follows:
$
$
BLOCK
MACRO
SAVE NOGEN
COUNT
SET
REPT
COUNT
SET
INC
ENDM
RESTORE
ENDM
NUMB,PREFIX
o
NUMB
COUNT+l
PREFIX,%COUNT ;NESTED MACRO CALL
5-17
Chapter 5. Macros
The macro call BLOCK 3,LAB generates the following source code:
LAB1:
LAB2:
LAB3:
BLOCK
DB
DB
DB
3,LAB
o
o
o
The assembler controls specified in these two macros (the lines beginning with $) are used to clean up the
assembly listing for easier reading. The source code shown for the call BLOCK 3,LAB is what appears in the
assembly listing when the controls are used. Without the controls, the assembly listing appears as follows:
COUNT
COUNT
COUNT
LAB1 :
COUNT
LAB2:
COUNT
LAB3:
BLOCK
SET
REPT
SET
INC
ENDM
SET
INC
DB
SET
INC
DB
SET
INC
DB
3,LAB
0
3
COUNT+l
LAB,%CQUNT
COUNT+l
LAB,%COUNT
0
COUNT+1
LAB,%CQUNT
0
CQUNT+l
LAB,%COUNT
0
Example 3: A Macro that Converts Itself into a Subroutine
In some cases, the in-line coding substituted for each macro call imposes an unacceptable memory requirement.
The next three examples show three different methods for converting a macro call into a subroutine call. The
first time the SBMAC macro is called, it generates a full in-line substitution which defines the SUBR subroutine.
Each subsequent call to the SBMAC macro generates only a CALL instruction to the SUBR subroutine.
Within the following examples, notice that the label SUBR must be global so that it can be called from outside
the first expansion. This is possible only when that part of the macro definition containing the global label is
called only once in the entire program.
Method #1: Nested Macro Definitions
Macros can be redefined during the course of a program. In the following example, the definition of SBMAC
contains its own redefinition as a nested macro. The first time SBMAC is called, it is full expanded, and the
redefinition of SBMAC replaces the original definition. The second time SBMAC is called, only its redefinition
(a CALL instruction) is expanded.
5-18
Chapter S. Macros
SBMAC
SBMAC
LINK:
SUBR:
MACRO
MACRO
CALL
ENDM
CALL
JMP
SUBR
;;REDEFINITION OF SBMAC
SUBR
DUN
RET
DUN:
ENDM
Notice that both versions of SBMAC contain CALL SUBR instructions. This is necessary to provide a return
address at the end of the SUBR routine. The jump instruction labelled LINK is required to prevent the SUBR
subroutine from executing a return to itself. Notice that the return address for the second CALL SUBR
instruction would be SUBR if the jump instruction were omitted. The J MP DUN instruction simply transfers
control past the end of the subroutine.
NOTE
The assembler allows the use of a source line consisting
only of a label. Such a label is assigned to the next source
line for which code or data is generated. Notice that
neither code nor data is generated for an ENDM directive,
so the label DUN is assigned to whatever instruction follows
the ENDM directive. This construct is required because the
ENDM directive itself may not be given a label.
Method #2: Conditional Assembly
The second method for altering the expansion of the SBMAC macro uses conditional assembly. In this example,
a switch (FIRST) is set TRUE just before the first call for SBMAC. SBMAC is defined as follows:
TRUE
FALSE
FIRST
SBMAC
FIRST
LINK:
SUBR:
EQU
EQU
SET
MACRO
CALL SUBR
IF
SET
JMP
OFFH
0
TRUE
FIRST
FALSE
DUN
RET
DUN:
ENDIF
ENDM
5·19
Chapter
s.
Macros
The first call to SBMAC expands the full definition, including the call to and definition of SUBR:
LINK:
SUBR:
SBMAC
CALL
IF
JMP
SUBR
FIRST
DUN
RET
DUN:
ENDIF
Because FI RST is TRUE when encountered during the first expansion of SBMAC, all the statements between
I F and ENDI F are assembled into the program. In subsequent calls, the conditionally-assembled code is skipped
so that the subroutine is not regenerated. Only the following expansion is produced:
SBMAC
CALL
IF
SUBR
FIRST
Method #3: Conditional Ass,embly with EXITM
The third method for altering the expansion of SBMAC also uses conditional assembly, but uses the EXITM
directive to suppress unwanted macro expansion after the first call. EXITM is effective when FI RST is FALSE,
which it is after the first call to SBMAC.
TRUE
FALSE
FIRST
SBMAC
FIRST
EQU
EQU
SET
MACRO
CALL
IF
EXITM
ENDIF
SET
JMP
SUBR:
RET
DUN:
ENDM
5-20
OFFH
o
TRUE
SUBR
NOT FIRST
FALSE
DUN
Ch~pter
S. Macros
Example 4: Computed GOTO Macro
This sample macro presents an implementation of a computed GOTO for the 8080 or 8085. The computed
GOTO, a common feature of many high level languages, allows the program to jump to one of a number of
different locations depending on the value of a variable. For example, if the variable has the value zero, the
program jumps to the first item in the list; if the variable has the value 3, the program jumps to the fourth
address in the list.
In this example, the variable is placed in the accumulator. The list of addresses is defined as a series of OW
directives starting at the symbolic address TABLE. This macro (T JUMP) also modifies itself with a nested
definition. Therefore, only the first call to the TJ UMP macro generates the calculated GOTO routine. Subsequent calls produce only the jump instruction JMP TJCODE.
TJUMP
TJCODE:
TJUMP
MACRO
ADD
MVI
MOV
DAD
MOV
INX
MOV
XCHG
PCHL
MACRO
JMP
ENDM
ENDM
A
0,0
E,A
0
E,M
H
D,M
TJCODE
;JUMP TO A-TH ADOR IN TABLE
;MULTIPL Y A BY 2
;CLEAR DREG
;GET TABLE OFFSET INTO D&E
;ADD OFFSET TO TABLE ADDR IN H&L
;GET 1ST ADDRESS BYTE
;GET 2ND ADDRESS BYTE
;J UMP TO ADDRESS
;REDEFINE TJUMP TO SAVE CODE
;NEXT CALL JUMPS TO ABOVE CODE
Notice that the definition of the T JUMP macro does not account for loading the address of the address table
into the Hand L registers; the user must load this address just before calling the T JUMP macro. The following
shows the coding for the address table (TABLE) and a typical call sequence for the TJ UMP macro:
TABLE:
MVI
LXI
TJUMP
A,2
H,TABLE
OW
OW
OW
LOCO
LOCl
LOC2
The call sequence shown above causes a jump to LOC2.
5-21
Chapter 5. Macros
Example 5: Using IRP to Define the Jump Table
The TJ UMP macro becomes even more useful when a second macro (GOTO) is used to define the jump table,
load the address of the table into the Hand L registers, and then call TJ UMP. The GOTO macro is defined as
follows:
MACRO
LOCAL
LDA
LXI
TJUMP
IRP
DW
ENDM
ENDM
GOTO
JTABLE:
INDEX,LlST
JTABLE
INDEX
H,JTABLE
;LOAD ACCUM WITH INDEX
;LOAD H& L WITH TABLE ADDRESS
;CALL TJUMP MACRO
FORMAL,(LlST>
FORMAL
;SET UP TABLE
A typical call to the GOTO macro would be as follows:
GOTO
CASE ,(COUNT ,TIMER,DATE ,PTDRVR>
This call to the GOTO macro builds a table of DW directives for the labels COUNT, TIMER, DATE, and
PTDRVR. It then loads the base address of the table into the Hand L registers and calls the T JUMP macro.
If the value of the variable CASE is 2 when the GOTO macro is called, the GOTO and T JUMP macros
together cause a jump to the address of the DATE routine.
Notice that any number of addresses may be specified in the list for the GOTO routine as long as they all fit
on a single source line. Also, the GOTO macro may be called any number of times, but only one copy of the
coding for the TJ UMP is generated since the T JUMP macro redefines itself to generate only a J MP T JCODE
instruction.
5-22
6. PROGRAMMING TECHNIQUES
This chapter describes some techniques that may be of help to the programmer.
BRANCH TABLES PSEUDO-SUBROUTINE
S~ppose
a program consists of several separate routines, any of which may be executed depending upon some
initial condition (such as a number passed in a register). One way to code this would be to check each condition
s(~quentially and branch to the routines accordingly as follows:
CONDITION = CONDITION 1?
IF YES BRANCH TO ROUTINE 1
CONDITION = CONDITION 2?
IF YES BRANCH TO ROUTINE 2
BRANCH TO ROUTINE N
A sequence as above is inefficient, and can be improved by using a branch table.
The logic at the beginning of the branch table program loads the starting address of the branch table into the H
and L registers. The branch table itself consists of a list of starting addresses for the routines to be branched to.
Using the Hand L registers as a pointer, the branch table program loads the selected routine's starting address
into the program counter, thus effecting a jump to the desired routine. For example, consider a program that
executes one of eight routines depending on which bit of the accumulator is set:
Jump to routine 1 if the accumulator holds 00000001
2" "
" 0000001 0
3 " "
" 00000100
4 " "
" 00001000
5" "
" 00010000
6 " "
" 00100000
7" "
" 01000000
8" "
" 10000000
A program that provides such logic follows. The program is termed a 'pseudo-subroutine' because it is treated as a
subroutine by the programmer (i.e., it appears just once in memory), but is entered via a regular JUMP instruction
rather than via a CALL instruction.
6-1
Chapter 6. Programming Techniques
Main Program
Branch Table
Program
~--
--
normal subroutine return
sequence not followed by
branch table program
6-2
Jump
Routines
Chapter 6. Programming Techniques
Label
Code
Operand
START:
LXI
H,BTBL
GTBIT:
RAR
JC
INX
INX
GETAD
H
H
JMP
MOV
INX
GTBIT
E,M
H
MOV
XCHG
D,M
GETAD:
OW
OW
OW
OW
OW
OW
DW
OW
;(H,L)=(H,L)+2 TO
;POINT TO NEXT ADDRESS
;IN BRANCH TABLE
;BIT FOUND
;LOAD JUMP ADDRESS
;INTO D AND E REGISTERS
;EXCHANGE D AND E
;WITH HAND L
;JUMP TO ROUTINE
;ADDRESS
PCHL
BTBL:
;REGISTERS HAND L WILL
;POINT TO BRANCH TABLE
ROUTl
ROUT2
ROUT3
ROUT4
ROUTS
ROUT6
ROUT7
ROUT8
;BRANCH TABLE. EACH
;ENTRY IS A TWO-BYTE
;ADDRESS
;HELD LEAST SIGNIFICANT
;BYTE FIRST
The control routine at START uses the Hand L registers as a pointer into the branch table (BTBL) corresponding
to the bit of the accumulator that is set. The routine at GETAD then transfers the address held in the corresponding branch table entry to the Hand L registers via the D and E registers, and then uses a PCHL instruction,
thus transferring control to the selected routine.
TRANSFERRING DATA TO SUBROUTINES
A subroutine typically requires data to perform its operations. In the simplest case, this data may be transferred
in one or more registers.
Sometimes it is more convenient and economical to let the subroutine load its own registers. One way to do this
is to place a list of the required data (called a parameter list) in some data area of memory, and pass the address
of this list to the subroutine in the Hand L registers.
6-3
Chapter 6.
Programming Techniques
For example, the subroutine ADSUB expects the address of a three-byte parameter list in the Hand L registers.
It adds the first and second bytes of the list, and stores the result in the third byte of the list:
Label
Code
Operand
Comment
LXI
H,PLlST
CALL
ADSUB
;LOAD HAND L WITH
;ADDRESSES OF THE PARAM;ETER LIST
;CALL THE SUBROUTINE
DB
DB
6
8
OS
LXI
CALL
H,L1ST2
ADSUB
RET1 :
PLlST:
;FIRST NUMBER TO BE ADDED
;SECOND NUMBER TO BE
;ADDED
;RESUL T WILL BE STORED HERE
;LOAD HAND L REGISTERS
;FOR ANOTHER CALL TO ADSUB
RET2:
L1ST2:
ADSUB:
DB
DB
OS
35
MOV
INX
A,M
H
MOV
ADD
INX
B,M
B
H
MOV
M,A
RET
10
;GET FIRST PARAMETER
;INCREMENT MEMORY
;ADDRESS
;GET SECOND PARAMETER
;ADD FIRST TO SECOND
;INCREMENT MEMORY
;ADDRESS
;STORE RESU L T AT TH I RD
;PARAMETER STORE
;RETURN UNCONDITIONALLY
The first time ADSUB is called, it loads the A and B registers from PLIST and PLIST +1 respectively, adds them,
and stores the result in PLIST +2. Return is then made to the instruction at RET1.
6-4
Chapter 6. Programming Techniques
First call to ADSUB:
ADSUB:
H
L
D
D
06
PLiST
08
PLlST+l
OEH
PLlST+2
The second time ADSUB is called, the Hand L registers point to the parameter list LlST2. The A and B
registers are loaded with 10 and 35 respectively, and the sum is stored at LlST2+2. Return is then made to
the inst~uction at RET2.
Note that the parameter lists PLiST and LlST2 could appear anywhere in memory without altering the results
produced by ADSUB.
This approach does have its limitations, however. As coded, ADSUB must receive a list of two and only two
numbers to be added, and they must be contiguous in memory. Suppose we wanted a subroutine (GENAD)
which would add an arbitrary number of bytes, located anywhere in memory, and leave the sum in the accumulator.
This can be done by passing the subroutine a parameter li'st which is a list of addresses of parameters, rather
than the parameters themselves, and signifying the end of the parameter list be a number whose first byte is
FFH (assuming that no parameters will be stored above address FFOOH).
Call to GENAD:
H
GENAD:
D
L
DO
~
l
PARMl
AORl
ADR2
ADR3
ADR4
FFFF
PARM4
PARM3
PARM2
As implemented below, GENAD saves the current sum (beginning with zero) in the C register. It then loads the
address of the first parameter into the 0 and E registers. If this address is greater than or equal to FFOOH, it
reloads the accumulator with the sum held in the C register and returns to the calling routine. Otherwise, it
6-5
Chapter 6. Programming Techniques
loads the parameter into the accumulator and adds the sum in the C register to the accumulator. The routine
then loops back to pick up the remaining parameters.
Lobel
Code
Operand
Comment
LXI
CALL
H,PlIST
GENAD
;LOAD ADDRESS OF
;PARAMETER ADDRESS LIST
HALT
OW
OW
DW
OW
OW
PARM1
PARM2
PARM3
PARM4
OFFFFH
;lIST OF PARAMETER ADDRESSES
PARM1 :
PARM4:
DB
DB
6
16
PARM3:
DB
13
PARM2:
DB
82
GENAD:
LOOP:
XRA
MOV
MOV
A
C,A
E,M
INX
MOV
H
A,M
CPI
OFFH
BACK
D,A
0
C
H
PlIST:
JZ
MOV
LDAX
ADD
INX
BACK:
JMP
MOV
RET
END
LOOP
A,C
;TERMINATOR
;CLEAR ACCUMULATOR
;SAVE CURRENT TOTAL IN C
;GET LOW ORDER ADDRESS BYTE
;OF FIRST PARAMETER
;GET HIGH ORDER ADDRESS BYTE
;OF FIRST PARAMETER
;COMPARE TO FFH
;IF EQUAL, ROUTINE IS COMPLETE
;0 AND E NOW ADDRESS PARAMETER
;LOAD ACCUMULATOR WITH PARAMETER
;ADD PREVIOUS TOTAL
;INCREMENT HAND L TO POINT
;TO NEXT PARAMETER ADDRESS
;GET NEXT PARAMETER
;ROUTINE DONE - RESTORE TOTAL
;RETURN TO CALLING ROUTINE
Chapter 6. Programming Techniques
Note that GENAO could add any combination of the parameters with no change to the parameters themselves.
The sequence:
PlIST:
lXI
CAll
H,PlIST
GENAO
OW
OW
OW
PARM4
PARMl
OFFFFH
would cause PARMl and PARM4 to be added, no matter where in memory they might be located (excluding
addresses above FFOOH).
Many variations of parameter passing are possible. For example, if it is necessary to allow parameters to be
stored at any address, a calling program can pass the total number of parameters as the first parameter; the
subroutine then loads this first parameter into a register and uses it as a counter to determine when all parameters had been accepted.
SOFTWARE MULTIPLY AND DIVIDE
The multiplication of two unsigned 8-bit data bytes may be accomplished by one of two techniques: repetitive
addition, or use of a register shifting operation.
Repetitive addition provides the simplest, but slowest, form of multiplication. For example, 2AH*74H may be
generated by adding 74H to the (initially zeroed) accumulator 2AH times.
Shift operations provide faster multiplication. Shifting a byte left one bit is equivalent to mUltiplying by 2, and
shifting a byte right one bit is equivalent to dividing by 2. The following process will produce the correct 2-byte
result of multiplying a one byte mUltiplicand by a one byte multiplier:
A.
Test the least significant bit of multiplier. If zero, go to step b. If one, add the
multiplicand to the most significant byte of the result.
B.
Shift the entire two-byte result right one bit position.
C.
Repeat steps a and b until all 8 bits of the multiplier have been tested.
For example, consider the multiplication: 2AH*3CH=9D8H
Step 1:
Test mUltiplier O-bit; it is 0, so shift l6-bit result right one bit.
Step 2:
Test multiplier l-bit; it is 0, so shift 16-bit result right one bit.
Step 3:
Test multiplier 2-bit; it is 1, so add 2AH to high-order byte of result and shift 16-bit
result right one bit.
6·7
Chapter 6. Programming Techniques
Step 4:
Test multiplier 3-bit; it is 1, so add 2AH to high-order byte of result and shift 16-bit
result right one bit.
Step 5:
Test multiplier 4-bit; it is 1, so add 2AH to high-order byte of result and shift 16-bit
result right one bit.
Step 6:
Test multiplier 5-bit; it is 1, so add 2AH to high-order byte of result and shift 16-bit
result right one bit.
Step 7:
Test multiplier 6-bit; it is 0, so shift 16-bit result right one bit.
Step 8:
Test multiplier 7-bit; it is 0, so shift 16-bit result right one bit.
The result produced is 0908.
Start
Step 1 a
b
Step 2 a
b
Step 3 a
b
Step 4 a
MULTIPLIER
MULTIPLICAND
00111100(3C)
00101010(2A)
.............................. .
HIGH-ORDER BYTE
OF RESULT
00000000
LOW-ORDER BYTE
OF RESULT
00000000
00000000
00000000
00000000
00101010
00010101
00111111
00011111
01001001
00100100
01001110
00100111
00000000
00000000
00000000
00000000
10000000
10000000
11000000
11000000
01100000
00010011
10110000
00001001
11011000(908)
.............................. .
.............................. .
.............................. .
b
Step 5 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b
Step 6 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b
Step 7 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b
Step 8 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
b
Since the multiplication routine described above uses a number of important programming techniques, a sample
program is given with comments.
The program uses the B register to hold the most significant byte of the result, and the C register to hold the
least significant byte of the result. The 16-bit right shift of the result is performed in the accumulator by two
rotate-right-through-carry instructions.
6-8
Chapter 6. Programming Techniques
Zero carry and then rotate B:
B
C
D
Then rotate C to complete the shift:
B
C
D
~~------------~~
Register D holds the multiplicand, and register C originally holds the mUltiplier.
MULT:
MULTO:
MUL Tl:
MVI
B,O
MVI
MOV
RAR
MOV
DCR
jZ
MOV
jNC
ADD
E,9
A,C
C,A
E
DONE
A,B
MULTl
D
RAR
MOV
jMP
;INITIALIZE MOST SIGNIFICANT BYTE
;OF RESULT
;BIT COUNTE R
;ROTATE LEAST SIGNIFICANT BIT OF
;MULTIPLIER TO CARRY AND SHIFT
;LOW-ORDER BYTE OF RESULT
;EXIT IF COMPLETE
;ADD MULTIPLICAND TO HIGH;ORDER BYTE OF RESULT IF BIT
;WAS A ONE
;CARRY=O HERE SHIFT HIGH;ORDER BYTE OF RESULT
B,A
MULTO
DONE:
An analogous procedure is used to divide an unsigned 16-bit number by an unsigned 16-bit number. Here, the
process involves subtraction rather than addition, and rotate-left instructions instead of rotate-right instructions.
6-9
Chapter 6. Programming Techniques
The following reentrant program uses the Band C registers to hold the dividend and quotient, and the D and E
register to hold the divisor and remainder. The Hand L registers are used to store data temporarily.
DIV:
MOV
A,D
CMA
MOV
MOV
D,A
A,E
CMA
MOV
INX
LXI
DVO:
MVI
PUSH
DAD
DVl :
JNC
XTHL
POP
PUSH
MOV
RAL
MOV
MOV
RAL
MOV
MOV
RAL
MOV
MOV
RAL
;NEGATE THE DIVISOR
E,A
D
;FOR TWO'S COMPLEMENT
H,O
A,17
;INITIAL VALUE FOR REMAINDER
;INITIALIZE LOOP COUNTER
H
D
DVl
;SAVE REMAINDER
;SUBTRACT DIVISOR (ADD NEGATIVE)
H
PSW
A,C
C,A
A,B
;UNDER FLOW, RESTORE HL
;SAVE LOOP COUNTER (A)
;4 REGISTER LEFT SHIFT
;WITH CARRY
;CY ->C->B->L ->H
B,A
A,L
L,A
A,H
MOV
POP
H,A
PSW
;RESTORE LOOP COUNTER (A)
DCR
A
DVO
;DECREMENT IT
;KEEP LOOPING
JNZ
;POST-DIVIDE CLEAN UP
;SHIFT REMAINDER RIGHT AND RETURN IN DE
ORA
A
MOV
A,H
RAR
MOV
MOV
RAR
MOV
RET
END
6-10
D,A
A,L
E,A
Chapter 6. Programming Techniques
MUL TIBYTE ADDITION AND SUBTRACTION
The carry flag and the ADC (add with carry) instructions may be used to add unsigned data quantities of
arbitrary length. Consider the following addition of two three-byte unsigned hexadecimal numbers:
32AF8A
+84BA90
B76Al A
To perform this addition, add to the low-order byte using an ADD instruction. ADD sets the carry flag for use
in subsequent instructions, but does not include the carry flag in the addition. Then use ADC to add to all
higher order bytes.
32
84
AF
BA
8A
90
B7
6A
lA
carry = 1
S
carry =
lS
The following routine will perform this multibyte addition, making these assumptions:
The E register holds the length of each number to be added (in this case, 3).
The numbers to be added are stored from low-order byte to high-order byte beginning at memory locations
FI RST and SECND, respectively.
The result will be stored from low-order byte to high-order byte beginning at memory location FIRST, replacing
the original contents of these locations.
MEMORY
LOCATION
after
before
~+
..
lA
~
carry
...
6A
~
carry
FIRST
8A
FIRST+l
AF
FIRSTt2
32
SECND
90
90
SECND+l
BA
BA
SECND+2
84
84
+
+ ...
B7
6-11
Chapter 6. Programming Techniques
The following routine uses an ADC instruction to add the low-order bytes of the operands. This could cause
the result to be high by one if the carry flag were left set by some previous instruction. This routine avoids
the problem by clearing the carry flag with the XRA instruction just before LOOP.
Label
MADD:
LOOP:
Code
Operand
Comment
LXI
LXI
XRA
LDAX
ADC
B,FIRST
H,SECND
A
B
M
STAX
DCR
JZ
INX
B
E
DONE
B
;B AND C ADDRESS FI RST
;H AND L ADDRESS SECND
;CLEAR CARRY FLAG
;LOAD BYTE OF FIRST
;ADD BYTE OF SECND
;WITH CARRY
;STORE RESULT AT FIRST
;DONE IF E = 0
INX
H
JMP
LOOP
DB
DB
DB
DB
DB
DB
90H
OBAH
84H
8AH
OAFH
32H
;POINT TO NEXT BYTE OF
;FIRST
;POINT TO NEXT BYTE OF
;SECND
;ADD NEXT TWO BYTES
DONE:
FIRST:
SECND:
Since none of the instructions in the program loop affect the carry flag except ADC, the addition with carry will
proceed correctly.
When location DONE is reached, bytes FIRST through FIRST+2 will contain lA6AB7, which is the sum shown
at the beginning of this section arranged from low-order to high-order byte.
In order to create a multibyte subtraction routine, it is necessary only to duplicate the multibyte addition routine
of this section, changing the ADC instruction to an SBB instruction. The program will then subtract the number
beginning at SECND from the number beginning at FIRST, placing the result at FIRST.
DECIMAL ADDITION
Any 4-bit data quantity may be treated as a decimal number as long as it represents one of the decimal digits
from 0 through 9, and does not contain any of the bit patterns representing the hexadecimal digits A through F.
In order to preserve this decimal interpretation when performing addition, the value 6 must be added to the
4-bit quantity whenever the addition produces a result between 10 and 15. This is because each 4-bit data
quantity can hold 6 more combinations of bits than there are decimal digits.
6-12
Chapter 6. Programming Techniques
Decimal addition is performed by letting each 8-bit byte represent two 4-bit decimal digits. The bytes are
summed in the accumulator in standard fashion, and the DAA (decimal adjust accumulator) instruction is then
used to convert the 8-bit binary result to the correct representation of 2 decimal digits. For multibyte strings,
you must perform the decimal adjust before adding the next higher-order bytes. This is because you need the
carry flag setting from the DAA instruction for adding the higher-order bytes.
To perform the decimal addition:
2985
+4936
7921
the process works as follows:
1.
Clear the Carry and add the two lowest-order digits of each number (remember that each 2
decimal digits are represented by .one byte).
carry
Carry
=0
85 = 100001 01 B
36 = 0011 011 OB
0
~
Q]10111011B
~
Auxiliary Carry
=0
The accumulator now contains OBBH.
2.
Perform a DAA operation. Since the rightmost four bits are greater than 9, a 6 is added to the
accumulator.
Accumulator = 10111011 B
6 =
0110B
1'1000001 B
Since the leftmost bits are greater than 9, a 6 is added to these bits, thus setting the carry flag.
Accumulator = 11000001 B
6=0110
B
/]001000018
Carry flag = 1
The accumulator now contains 21 H. Store these two digits.
6-13
Chapter 6. Programming Techniques
3.
Add the next group of two digits:
29 = 001 01 001 B
49 = 01001001B
carry
Carry: 0
/~
Q] 01110011 B
'AUXiliary Carry: 1
The accumulator now contains 73H.
4.
Perform a DAA operation. Since the auxiliary carry flag is set, 6 is added to the accumulator.
Accumulator = 01110011 B
0110B
6 =
/QJOllll001B
Carry flag = 0
Since the leftmost 4 bits are less than 10 and the carry flag is reset, no further action occurs.
Thus, the correct decimal result 7921 is generated in two bytes.
A routine which adds decimal numbers, then, is exactly analogous to the multibyte addition routine MADD of
the last section, and may be produced by inserting the instruction DAA after the ADC M instruction of that
example.
Each iteration of the program loop will add two decimal digits (one byte) of the numbers.
DECIMAL SUBTRACTION
Decimal subtraction is considerably more complicated than decimal addition. In general, the process consists of
generating the tens complement of the subtrahend digit, and then adding the result to the minuend digit. For
example, to subtract 34 from 56, form the tens complement of 34 (99-34=65+1 =66). Then, 56+66=122. By
truncating off the carry out of the high order digit, we get 22, the correct result.
The problem of handling borrows arises in multibyte decimal subtractions. When no borrow occurs from a subtract, you want to use the tens complement of the subtrahend for the next operation. If a borrow does occur,
you want to use the nines complement of the subtrahend.
Notice that the meaning of the carry flag is inverted because you are dealing with complemented data. Thus, a
one bit in the carry flag indicates no borrow; a zero bit in the carry flag indicates a borrow. This inverted carry
flag setting can be used in an add operation to form either the nines or tens complement of the subtrahend.
6-14
Chapter 6. Programming Techniques
The detailed procedure for subtracting multi-digit decimal numbers is as follows:
1.
Set the carry flag = 1 to indicate no borrow.
2.
Load the accumulator with 99H, representing the number 99 decimal.
3.
Add zero to the accumulator with carry, producing either 99H or 9AH, and resetting the
carry flag.
4.
Subtract the subtrahend digits from the accumulator, producing either the nines or tens
complement.
5.
Add the minuend digits to the accumulator.
6.
Use the OAA instruction to make sure the result in the accumulator is in decimal format, and
to indicate a borrow in the carry flag if one occurred.
7.
If there are more digits to subtract, go to step 2. Otherwise, stop.
Example:
Perform the decimal subtraction:
43580
-13620
29960
= 1.
1.
Set carry
2.
Load accumulator with 99H.
3.
Add zero with carry to the accumulator, producing 9AH.
Accumulator
= 10011001 B
= OOOOOOOOB
Carry
10011010B
4.
= 9AH
Subtract the subtrahend digits 62 from the accumulator.
Accumulator = 1001101 OB
62 = 1001111 OB
]] 00111 OOOB
6-15
Chapter 6. Programming Techniques
5.
Add the minuend digits 58 to the accumulator.
Accumulator = 001110008
58 = 01 0110008
Carry = 0
~
g 100100008 = 90H
'AUXiliary Carry = 1
= 1) and
6.
DAA converts accumulator to 96 (since Auxiliary Carry
indicating that a borrow occurred.
7.
Load accumulator with 99H.
8.
Add zero with carry to accumulator, leaving accumulator = 99H.
9.
Subtract the subtrahend digits 13 from the accumulator.
leaves carry flag
=0
Accumulator = 10011001 B
13 = 111011 01 B
I110000110B
10.
Add the minuend digits 43 to the accumulator.
Accumulator = 1000011 OB
43 = 01 0000 11 B
~:g 110010018
'AUXiliary Carry
=0
DAA converts accumulator to 29 and sets the carry flag
= 1,
Carry
11.
=0
=C9H
indicating no borrow occurred.
Therefore, the result of subtracting 1362 from 4358 is 2996.
The following subroutine will subtract one 16-digit decimal number from another using the following assumptions:
The minuend is stored least significant (2) digits first beginning at location MINU.
The subtrahend is stored least significant (2) digits first beginning at location SBTRA.
The result will be stored least significant (2) digits first, replacing the minuend.
6-16
Chapter 6. Programming Techniques
Label
Code
Operand
Comment
DSUB:
LXI
LXI
D,MINU
H,SBTRA
MVI
C,8
;0 AND E ADDRESS MINUEND
;H AND L ADDRESS SUBTRA;HEND
;EACH LOOP SUBTRACTS 2
;DIGITS (ONE BYTE),
;THEREFORE PROGRAM WILL
;SUBTRACT 16 DIGITS.
;SET CARRY INDICATING
;NO BORROW
;LOAD ACCUMULATOR
;WITH 99H.
;ADD ZERO WITH CARRY
;PRODUCE COMPLEMENT
;OF SUBTRAHEND
;SWITCH D AND E WITH
;H AND L
;ADD MINUEND
;DECIMAL ADJ UST
;ACCUMULATOR
;STORE RESULT
;RESWITCH 0 AND E
;WITH HAND L
;DONE IF C = 0
STC
LOOP:
MVI
A,99H
ACI
SUB
0
M
XCHG
ADD
DAA
M
MOV
M,A
XCHG
OCR
DONE:
JZ
INX
C
DONE
0
INX
H
JMP
NOP
LOOP
;ADDRESS NEXT BYTE
;OF MINUEND
;ADDRESS NEXT BYTE
;OF SUBTRAHEND
;GET NEXT 2 DECIMAL DIGITS
6-17
7. INTERRUPTS
INTERRUPT CONCEPTS
The following is a general description of interrupt handling and applies to both the 8080 and 8085 processors.
However, the 8085 processor has some additional hardware features for interrupt handling. For more information on these features, see the description of the 8085 processor in Chapter 1 and the descriptions of the
RIM, SIM, and RST instructions in Chapter 3.
Often, events occur external to the central processing unit which require immediate action by the CPU. For
example, suppose a device is sending a string of 80 characters to the CPU, one at a time, at fixed intervals.
There are two ways to handle such a situation:
A.
A program could be written which accepts the first character, waits until the next character is
ready (e.g., executes a timeout by incrementing a sufficiently large counter), then accepts the
next character, and proceeds in this fashion until the entire 80 character string has been received.
This method is referred to as programmed Input/Output.
B.
The device controller could interrupt the CPU when a character is ready to be input, forcing a
branch from the executing program to a special interrupt service routine.
The interrupt sequence may be illustrated as follows:
INTERRUPT
Normal
Program
Execution
Program
xecutlon
Continues
Interrupt Service
Routine
7-1
Chapter 7. I nterru pts
The 8080 contains a bit named INTE w:,ich may be set or reset by the instructions E I and D I described in
Chapter 3. Whenever INTE is equal to 0, the entire interrupt handling system is disabled, and no interrupts
will be accepted.
When the 8080 recognizes an interrupt request from an external device, the following actions occur:
1.
The instruction currently being executed is completed.
2.
The interrupt enable bit, INTE, is reset
3.
The interrupting device supplies, via hardware, one instruction which the CPU executes. This
instruction does not appear anywhere in memory, and the programmer has no control over it,
since it is a function of the interrupting device's controller design. The program counter is not
incremented before this instruction.
= O.
The instruction supplied by the interrupting device is normally an RST instruction (see Chapter 3), since this
is an efficient one byte call to one of 8 eight-byte subroutines located in the first 64 words of memory. For
instance, the device may supply the instruction:
RST OH
with each input interrupt. Then the subroutine which processes data transmitted from the device to the CPU
will be called into execution via an eight-byte instruction sequence at memory locations OOOOH to 0007H.
A digital input device may supply the instruction:
RST 1H
Then the subroutine that processes the digital input signals will be called via a sequence of instructions
occupying memory locations 0008H to OOOFH.
Device 'a'
Transfers
control to
• 0000
0007
supplies RST OH
Device Ib'
supp/ ies RST 1 H
7-2
Transfers
control to
•
0008
OOOF
}
Beginning of
subroutine for
device la'
}
Beginning of
subroutine for
device 'b'
Chapter 7. Interrupts
Device 'x'
Transfers
control to
supplies RST 7H
0038
003F
~
}
Beginning of
subroutine for
device 'x'
Note that any of these 8-byte subroutines may in turn call longer subroutines to process the interrupt, if
necessary.
Any device may supply an RST instruction (and indeed may supply anyone-byte 8080 instruction).
The following is an example of an Interrupt sequence:
ARBITRARY
MEMORY ADDRESS
3COB
3COC
INSTRUCTION
~~~ ~:! ~
{Interrupt from Device 1
Device 1 suppl ies
RST OH
Program Counter =
3COC pushed onto
the stack.
A
B
Control transferred to
to 0000
0000
Instruction 1 /
Instruction 2
RET----------------------~,
Stack popped into
program counter
C
Device 1 signals an interrupt as the CPU is executing the instruction at 3COB. This instruction is completed.
The program counter remains set to 3COC, and the instruction RST OH supplied by device 1 is executed.
Since this is a call to location zero, 3COC is pushed onto the stack and program control is transferred to
location OOOOH. (This subroutine may perform jumps, calls, or any other operation.) When the RETURN is
executed, address 3COC is popped off the stack and replaces the contents of the program counter, causing
execution to continue at this point.
7-3
Chapter 7. Interrupts
WRITING INTERRUPT SUBROUTINES
In general, any registers or condition bits changed by an interrupt subroutine must be restored before returning
to the interrupted program, or errors will occur.
For example, suppose a program is interrupted just prior to the instruction:
JC LOC .
and the carry bit equals 1. If the interrupt subroutine happens to reset the carry bit before returning to the
interrupted program, the jump to LOC which should have occurred will not, causing the interrupted program
to produce erroneous results.
Like any other subroutine then, any interrupt subroutine should save at least the condition bits and restore them
before performing a RETURN operation. (The obvious and most convenient way to do this is to save the data
in the stack, using PUSH and POP operations.)
Further, the interrupt enable system is automatically disabled whenever an interrupt is acknowledged. Except in
special cases, therefore, an interrupt subroutine should include an EI instruction somewhere to permit detection
and handling of future interrupts. One instruction after an EI is executed, the interrupt subroutine may itself be
interrupted. This process may continue to any level, but as long as all pertinent data are saved and restored,
correct program execution will continue automatically.
A typical interrupt subroutine, then, could appear as follows:
Code
Operand
Comment
PUSH
EI
PSW
;SAVE CONDITION BITS AND ACCUMULATOR
;RE-ENABLE INTERRUPTS
;PERFORM NECESSARY ACTIONS TO SERVICE
;THE INTERRUPT
POP
RET
74
PSW
;RESTORE MACHINE STATUS
;RETURN TO INTERRUPTED PROGRAM
APPENDIX A.
INSTRUCTION SUMMARY
This appendix summarizes the bit patterns and number of time states associated with every 8080 CPU
instruction. The instructions are listed in both mnemonic (alphabetical) and operation code (numerical)
sequence.
When using this summary, note the following symbology.
DDD represents a destination register. SSS represents a source register. Bot.h DDD and SSS are interpreted
as follows:
Interpretation
DDD or SSS
000
Register
Register
Register
Register
Register
Register
001
010
011
100
101
B
C
D
E
H
l
110
A memory register or stack pointer or PSW
(flags + accumulator)
111
The accumulator
Instruction execution time equals number of time periods multiplied by the duration of a time period.
A time period may vary from 480 nanoseconds to 2 microseconds on the 8080 or 320 nanoseconds to 2
microseconds on the 8085. Where two numbers of time periods are shown (eq.5/11), it means that the
smaller number of time periods is required if a condition is not met, and the larger number of time periods
is required if the condition is met.
NUMBER OF TIME PERIODS
MNEMONIC
D7
D6
D5
D4
D3
D2
D1
DO
8080
8085
17
11/17
11/17
11/17
11/17
11/17
11/17
11/17
11/17
10
5/11
5/11
5/11
18
9/18
9/18
9/18
9/18
9/18
9/18
9/17
9/18
10
_.
i
CALL
CC
CNC
CZ
CNZ
CP
CM
CPE
CPO
RET
RC
RNC
RZ
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
6/12
6/12
6/12
ALL MNEMONICS© 1974, 1975, 1976, 1977 INTEL CORPORATION
A-l
Appendix A. Instruction Summary
MNEMONIC
D7
D6
D5
D4
D3
D2
D1
DO
RNZ
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
A
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
"I
0
1
0
1
1
1
1
A
0
0
0
0
1
1
0
0
1
1
RP
RM
RPE
RPO
RST
IN
OUT
LXI B
LXI D
LXI H
LXI SP
PUSH B
PUSH D
PUSH H
PUSH PSW
POP B
POP D
POP H
POP PSW
STA
LDA
XCHG
XTHL
SPHL
PCHL
DAD B
DAD D
DAD H
DAD SP
STAX B
STAX D
LDAX B
LDAX D
INX B
INX D
INX H
INX SP
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
A
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
"I
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
0
D
D
D
MOV Q,r2
S
S
MOV M,r
0
1
1
1
0
S
S
MOV r,M
1
0
D
D
D
1
1
HLT
0
1
1
1
0
1
1
MVI r
0
0
D
D
D
1
1
MVIM
1
0
0
1
0
1
1
INR
D
0
0
D
D
1
0
DCR
0
D
D
0
1
D
0
ALL MNEMONICS© 1974,1975,1976, 1977 INTEL CORPORATION
A-2
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
- 1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
S
S
0
0
0
0
0
1
NUMBER OF TIME PERIODS
8080
8085
5/11
5/11
5/11
5/11
5/11
11
10
10
10
10
10
10
11
11
11
11
10
10
10
10
13
13
4
18
5
5
10
10
10
10
7
7
7
7
5
5
5
5
5
7
7
7
7
10
5
5
6/12
6/12
6/12
6/12
6/12
12
10
10
10
10
10
10
12
12
12
12
10
10
10
10
13
13
4
16
6
6
10
10
10
10
7
7
7
7
6
6
6
6
4
7
7
5
7
10
4
4
Appendix A. Instruction Summary
NUMBER OF TIME PERIODS
MNEMONIC
INR A
OCR A
INR M
OCR M
ADD r
ADC r
SUB r
SBB r
AND r
XRA r
ORA r
CMPr
ADD M
ADC M
SUB M
SBB M
AND M
XRA M
ORA M
CMP M
ADI
ACI
SUI
SBI
ANI
XRI
ORI
CPI
RLC
RRC
RAL
RAR
jMP
jC
JNC
jZ
JNZ
JP
JM
jPE
JPO
DCX B
DCX 0
DCX H
DCX SP
07
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
06
05
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
04
03
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
1
1
1
0
1
O2
1
1
1
1
S
S
S
S
S
S
S
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
01
0
0
0
0
S
S
S
S
S
S
S
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ALL MNEMONICS©7974, 7975, 7976, 7977 INTEL CORPORATION
DO
0
1
0
1
S
S
S
S
S
S
S
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
8080
8085
5
5
10
10
4
4
10
10
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
4
4
4
4
4
4
4
4
10
10
10
10
10
10
10
10
10
5
5
5
10
7/10
7/10
7/10
7/10
7/10
7/10
7/10
7/10
5
6
6
6
6
A-3
Appendix A. Instruction Summary
NUMBER OF TIME PERIODS
MNEMONIC
CMA
STC
CMC
DAA
SHLD
LHLD
RIM
SIM
07
0
0
0
0
0
0
0
0
06
0
0
0
0
0
0
0
0
05
04
03
1
0
1
1
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
0
0
EI
1
1
1
1
1
01
1
1
1
1
NOP
0
0
0
0
0
0
O2
01
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
8080
8085
4
4
4
4
4
4
4
4
0
0
0
0
16
16
16
16
-
1
1
1
1
0
0
4
4
4
4
4
4
4
4
1
0
0
A LL MNEMONICS ©1974, 1975, 1976, 1977 INTEL CORPORA TION
A-4
DO
-
Appendix A. Instruction Summary
The following is a summary of the instruction set:
8080/85 CPU INSTRUCTIONS IN OPERATION CODE SEQUENCE
OP
CODE
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
lC
10
1E
1F
20
21
22
23
24
25
26
27
liL
29
2A
MNEMONIC
NOP
LXI
STAX
INX
INR
OCR
MVI
RLC
B,DI6
B
B
B
B
B,D8
DAD B
LDAXB
DCX B
INR C
DCR C
MVI C,D8
RRC
-"-
LXI
STAX
INX
INR
OCR
MVI
RAL
D,D16
D
0
D
D
D,D8
---
DAD 0
LDAXD
DCX D
INR E
DRC E
MVI E,D8
RAR
RIM
LXI H,D16
SH LD Adr
lNX H
INR H
DCR H
MVI H,D8
DAA
--
DAD H
LHLD Adr
OP
OP
CODE MNEMONIC CODE MNEMONIC
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
DCX
INR
DCR
MVI
CMA
SIM
LXI
STA
INX
INR
DCR
MVI
STC
DAD SP
LOA Adr
DCX SP
INR A
DCR A
MVI A,D8
CMC
MOV B,B
MOV B,C
MOV B,D
MOV B,E
MOV B,H
MOV B,L
MOV B,M
MOV B,A
MOV C,B
MOV C,C
MOV C,D
MOV C,E
MOV C,H
MOV C,L
MOV C,M
MOV C,A
MOV D,B
MOV D,C
MOV D,D
53
54
55
MOV D,E
MOV D,H
MOV D,L
--
H
L
L
L,D8
SPD16
Adr
SP
M
M
M,D8
---
56
57
58
59
SA
5B
5C
5D
5E
SF
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
HLT
MOV
MOV
MOV
MOV
MOV
MOV
MOV
D,M
D,A
E,B
E,C
E,D
E,E
E,H
E,L
E,M
E,A
H,B
H,C
H,D
H,E
H,H
H,L
H,M
H,A
L,B
L,C
L,D
L,E
L,H
L,L
L,M
L,A
M,B
M,C
M,D
M,E
M,H
M,L
M,A
A,B
A,C
A,D
A,E
A,H
A,L
MOV A,M
MOV A,A
ADD B
D8 := constant, or logical/arithmetic expression that evaluates
to an 8 bit data quantity.
Adr= 16-bit address
OP
OP
OP
CODE MNEMONIC CODE MNEMONIC CODE MNEMONIC
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F
8G
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
D"16
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SBB
SBB
SBB
SBB
SBB
SBB
SBB
SBB
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
XRA
XRA
XRA
XRA
C
0
E
H
L
M
A
B
C
D
E
H
L
M
A
B
C
D
E
H
L
M
A
8
C
D
E
H
L
M
A
B
C
D
E
H
L
M
A
B
C
D
E
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CFDO
D1
D2
D3
D4
D5
D6
XRA
XRA
XRA
XRA
ORA
ORA
ORA
ORA
ORA
ORA
ORA
ORA
CMP
CMP
CMP
CMP
CMP
CMP
CMP
CMP
RNZ
POP
jNZ
jMP
CNZ
PUSH
ADI
RST
RZ
RET
jZ
H
L
M
A
B
C
D
E
H
L
M
A
B
C
D
E
H
L
M
A
B
Adr
Adr
Adr
B
D8
0
Adr
- --.-
CZ
CALL
ACI
RST
RNC
POP
jNC
Adr
Adr
D8
1
0
Adr
OUT
CNC
PUSH
SUI
D8
Adr
D
D8
D7
D8
D9
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RST
RC
2
-
jC
IN
CC
Adr
D8
Adr
SBI 08
RST 3
RPO
POP H
jPO Adr
XTHL
CPO Adr
PUSH H
ANI D8
RST 4
RPE
PCHL
jPE Adr
XCHG
CPE Adr
--
XRI
RST
RP
POP
jP
DI
CP
PUSH
ORI
RST
RM
SPHL
jM
EI
CM
D8
5
PSW
Adr
Adr
PSW
08
6
Adr
Adr
---
CPI
RST
D8
7
constant, or logical/arithmetic expression that evaluates
to a 16 bit data quantity
ALL MNEMONICS © 7974, 7975, 7976, 7977 INTEL CORPORA TlON
A-5
Appendix A.
Instruction Summary
I nstruction Set Guide
Illl' full()wing i.., d '>Ul1ltlldry of the in..,tructioll ,>et:
ADD
ADI
ADC
ACI
SUB
SUI
SBB
REGM
ANA
SBI
S
XRA
XRI
ORA
ORI
CMP
CPI
RLC
RAR
D8
RAL RRC
CMA DAA
INR}
DCR REGM 8
~ACCUMULAT<2L
MOV
ANI
FLAGS
~STC
CMC
REGM8'REGM8~~ __+_ c_~g~}
I
_
D
LXI REG16,D161
_
H
REG 16
~
E
HIGH
SPH~.j
PCHL
LOW
STACK
f..
: POINTER
PROGRAM
I
COUNTER
RST
\.../XC~_~
L
,---JC
JZ
JP
JPE
A
/
LDAX'L
STAXf
LOA}
STA
\.
cc
INC}
JNZ
JM
JPO
CNC}
CNZ
CM
RC
A
RZ
16 RP
CPE CPO
RNC}
RNZ
RM
RPE RPO
CONTROL
Be,DE
A
CZ
A-16
CP
LHLDj
STHD
A 16
MEMORY
RET
CALL
JMP
INPUT
OUTPUT
PORTS
PORTS
INSTRUCTIONS
RST
NOP
16
HLT
EI
MVI
D8
MOV REGM ,REGM 8
8
CODE
REGM
DI
~---------
STACK
..-
PUSH}
POP
B,D,H,PSW
SIM}
RIM
8085 ONLY
MEANING
8
The operand may specify one of the 8-bit registers A,B,C,D,E,H, or L or M (a memory
reference via the 16-bit address in the Hand L registers). The MOV instruction, which
calls for two operands, can specify M for only one of its operands.
D8
Designates 8-bit immediate operand.
AI 6
P8
Designates at") 8-bit port number.
Designates a 16-bit address.
RE~-I(:;
Designates .Ii 6-bit register pair (B&C,D& E .H& L,or SP).
D16
Designates a 16 -bit immediate operand.
ALL MNEMONICS © 7974, 7975, 7976, 7977 INTEL CORPORA TlON
A-6
A
16
APPENDIX B. ASSEMBLER DIRECTIVE SUMMARY
Assembler directives are summarized alphabetically in this appendix. The following terms are used to describe
the contents of directive fields.
NOTATION
Term
Interpretation
Expression
Numerical expression evaluated during assembly; must evaluate
to 8 or 16 bits depending on directive issued.
List
Series of symbolic values or expressions, separated by commas.
Name
Symbol name terminated by a space.
Null
Field must be empty or an error results.
Oplab
Optional label; must be terminated by d colon.
Parameter
Dummy parameters are symbols holding the place of actual
parameters (symbolic values or expressions) specified elsewhere
in the program.
String
Series of any ASCII characters, surrounded by single quote marks.
Single quote within string is shown as two consecutive single quotes.
Text
Series of ASCII characters.
Macro definitions and calls allow the use of the special characters listed below.
Character
Function
&
Ampersand. Used to concatenate symbols.
( )
Angle brackets. Used to delimit text, such as lists, that contain
other del im iters.
..
"
Double semicolon. Used before a comment in a macro definition
to prevent inclusion of the comment in each macro expansion.
Exclamation point (escape character). Placed before a delimiter
to be passed as a literal in an actual parameter. To pass a literal
exclamation point, issue '!!.'
%
Percent sign. Precedes actual parameters to be evaluated immedidtely
when the macro is called.
ALL MNEMONICS © 7974, 7975, 7976, 7977 INTEL CORPORA TlON
B-1
Appendix B. Assembler Directive Summary
SUMMARY OF DIRECTIVES
FORMAT
FUNCTION
Label
Opcode
Operand(s)
oplab:
DB
exp(s} or string(s}
Define 8-bit data byte(s}. Expressions must evaluate
to one byte.
oplab:
OS
expression
Reserve data storage area of specified length.
oplab:
OW
exp(s} or string(s}
Define 16-bit data word(s}. Strings limited to 1-2
characters.
oplab:
ELSE
null
Conditional assembly. Code between ELSE and
ENDIF directives is assembled if expression in IF
clause is FALSE. (See IF.)
oplab:
END
expression
Terminate assembler pass. Must be last statement of
program. Program execution starts at 'exp,' if present;
otherwise, at location O.
oplab:
ENDIF
null
Terminate conditional assembly block.
name
EQU
expression
Define symbol 'name' with value 'exp.' Symbol is not
redefinable.
oplab:
IF
expression
Assemble code between IF and following ELSE or
ENDIF directive if 'exp' is true.
oplab:
ORG
expression
Set location counter to 'expression.'
name
SET
expression
Define symbol 'name' with value 'expression.'
Symbol can be redefined.
MACRO DIRECTIVES
FORMAT
FUNCTION
Label
Opcode
Operand(s)
null
ENDM
null
Terminate macro definition.
oplab:
EXITM
null
Alternate terminator of macro definition. (See ENDM.)
oplab:
IRP
dummy param,<list>
Repeat instruction sequence, substituting one character
form 'list' for 'dummy param' in each iteration.
ALL MNEMONIC5©7974, 7975, 7976, 7977 INTEL CORPORA TlON
8-2
Appendix B. Assembler Directive Summary
FORMAT
FUNCTION
Label
Opcode
Operand(s)
oplab:
IRPC
dummy param,text
Repeat instruction sequence, substituting one
character from 'text' for 'dummy param' in each
iteration.
null
LOCAL
label name{s)
name
MACRO
dummy param{s)
Specify label{s) in macro definition to have local
scope.
Define macro 'name' and dummy parameter{s) to be
used in macro definition.
oplab:
REPT
expression
Repeat REPT block 'expression' times.
RELOCATION DIRECTIVES
FUNCTION
FORMAT
l.abel
Opcode
Operand(s)
oplab:
ASEG
null
Assemble subsequent instructions and data in the
absolute mode.
oplab:
CSEG
boundary specification
Assemble subsequent instructions and data in the
relocatable mode using the code location counter.
oplab:
DSEG
boundary specification
Assemble subsequent instructions and data in the
relocatable mode using the data location counter.
oplab:
EXTRN
name{s)
Identify symbols used in this program module but
defined in a different module.
oplab:
NAME
module-name
Assigns a name to the program module.
oplab:
PUBLIC
name{s)
Identify symbols defined in this module that are to
be available to other modules.
oplab:
STKLN
expression
Specify the number of bytes to be reserved for the
stack for this module.
ALL MNEMONICS©7974, 7975, 7976, 7977 INTEL CORPORATION
8-3
APPENDIX
C. ASCII CHARACTER SET
ASCII CODES
The 8080 and 8085 use the seven-bit ASCII code, with the high-order eighth bit
(parity bit) always reset.
GRAPHIC OR
CONTROL
NUL
SOH
STX
ETX
EOT
ENO
ACK
BEL
BS
HT
IF
VT
FF
CR
SO
SI
DLE
DC1 (X-ON)
DC2 (TAPE)
DC3 (X-OFF)
DC4 (=F-Afl8
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US
SP
#
$
%
L
ASCII
(HEXADECIMAL)
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
GRAPHIC OR
CONTROL
+
0
1
2
3
4
5
6
7
8
9
<
>
?
@
A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
P
0
R
S
T
U
ASCII
(HEXADECIMAL)
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
GRAPHIC OR
CONTROL
ASCII
(HEXADECIMAL)
V
W
X
Y
Z
[
\
1
/\(t)
-(~)
a
b
c
d
e
9
h
j
k
m
n
0
p
q
u
v
w
x
y
z
(AL T MODE)
DEL (RUB OUT)
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
C-1
APPENDIX
D.
BI NARY -DECI MAL-H EXADECIMAL CONVERSION TABLES.
0-1
Appendix D. Binary-Decimal-Hexadecimal Conversion Tables
POWERS OF TWO
1
2
4
8
a
16
32
64
128
4
5
6
7
1.0
1 0.5
2 0.25
3 0.125
0.062
0.031
0.015
0.007
256 8 0.003
512 9 0.001
1 024 10 0.000
2 048 11 0.000
906
953
976
488
25
125
562 5
281 25
4
8
16
32
096
192
384
768
12
13
14
15
0.000
0.000
0.000
0.000
244
122
061
030
140
070
035
517
625
312 5
156 25
578 125
65
131
262
524
536
072
144
288
16
17
18
19
0.000
0000
0.000
0.000
015
007
003
001
258
629
814
907
789
394
697
348
062
531
265
632
5
25
625
812 5
1
2
4
8
048
097
194
388
576
152
304
608
20
21
22
23
0000
0.000
0000
0.000
000
000
000
000
953
476
238
119
674
837
418
209
316
158
579
289
406
203
101
550
25
125
562 5
781 25
16
33
67
134
777
554
108
217
0.000
0.000
0000
0.000
0000
0.000
0.000
a 000
000
000
000
000
000
000
000
000
059
029
014
007
003
001
000
000
604
802
901
450
725
862
931
465
644
322
161
580
290
645
322
661
390
695
847
923
435
870
741
483
24
25
26
27
28
29
30
31
775
387
193
596
268
536
1 073
2 147
216
432
864
728
456
912
824
648
298
149
574
287
461
230
615
307
625
312 5
656 25
828 125
914 062
957 031
478 515
739 257
5
25
625
812 5
4
8
17
34
294
589
179
359
967
934
869
738
296
592
184
368
32
33
34
35
0000
0000
0000
0000
000
000
000
000
000
000
000
000
232
116
058
029
830
415
207
103
643
321
660
830
653
826
913
456
869
934
467
733
628
814
407
703
906
453
226
613
25
125
562 5
281 25
68
137
274
549
719
438
877
755
476
953
906
813
736
472
944
888
36
37
38
39
0000
0000
0000
0000
000
000
000
000
000
000
000
000
014
007
003
001
551
275
637
818
915
957
978
989
228
614
807
403
366
183
091
545
851
425
712
856
806
903
951
475
640
320
660
830
625
312 5
156 25
078 125
099
199
398
796
511
023
046
093
627
255
511
022
776
552
104
208
40
41
42
43
0.000
0.000
0000
0000
000
000
000
000
000
000
000
000
000 909 494 701 772
000 4~4 747 350 886
000 227 373 675 443
000 113 686 837 721
928
464
232
616
237
118
059
029
915
957
478
739
039
519
759
379
062
531
765
882
5
25
625
812 5
17 592 186 044
35 184 372 088
70 368 744 177
140 737 488 355
416
832
664
328
44
45
46
47
0.000
0000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
056
028
014
007
843
421
210
105
418
709
854
427
860
430
715
357
808
404
202
601
014
007
003
001
869
434
717
858
689
844
422
711
941
970
485
242
406
703
351
675
25
125
562 5
781 25
1
2
4
8
281
562
1 125
2 251
1
2
4
9
5
25
625
812 5
474
949
899
799
976
953
906
813
710
421
842
685
656
312
624
248
48
49
50
51
0.000
0000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
003
001
000
000
552
776
888
444
713
356
178
089
678
839
419
209
800
400
700
850
500
250
125
062
929
464
232
616
355
677
338
169
621
810
905
452
337
668
334
667
890
945
472
236
625
312 5
656 25
328 125
4
9
18
36
503
007
014
028
599
199
398
797
627
254
509
018
370
740
481
963
496
992
984
968
52
53
54
55
0000
0.000
0.000
0000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
222
111
055
027
044
022
511
755
604
302
151
575
925
462
231
615
031
515
257
628
308
654
827
913
084
042
021
510
726
363
181
590
333
166
583
791
618
809
404
702
164
082
541
270
062
031
015
507
5
25
625
812 5
72
144
288
576
057
115
230
460
594
188
376
752
037
075
151
303
927
855
711
423
936
872
744
488
56
57
58
59
0000
0000
0000
0000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
013
006
003
901
877
938
469
734
787
893
446
723
807
903
951
475
814
907
953
976
456
228
614
807
755
377
188
094
295
647
823
411
395
697
848
924
851
925
962
481
135
567
783
391
253
676
813
906
906
950
476
738
25
125
562 5
281 25
152
305
611
223
921
843
686
372
504
009
018
036
606
213
427
854
846
693
387
775
976
952
904
808
60
61
62
63
0000
0.000
0000
0000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
867
433
216
108
361
680
840
420
737
868
434
217
988
994
497
248
403
201
100
550
547
773
886
443
205
602
801
400
962
981
490
745
240
120
560
280
695
347
173
086
953
976
988
994
369
684
342
171
140
570
285
142
0-2
625
312 5
156 25
578 125
Appendix D. Binary-Decimal-Hexadecimal Conversion Tables
POWERS OF 16 (IN BASE 10)
16
17
281
4 503
72 057
1 152 921
4
68
099
592
474
599
594
504
16
268
294
719
511
186
976
627
037
606
4
65
048
777
435
967
476
627
044
710
370
927
846
n
1
16
256
096
536
576
216
456
296
736
776
416
656
496
936
976
16· n
n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0.10000
0.62500
0.39062
0.24414
0.15258
0.95367
0.59604
0.37252
0.23283
0.14551
0.90949
0.56843
0.35527
0.22204
0.13877
0.86736
00000
00000
50000
06250
78906
43164
64477
90298
06436
91522
47017
41886
13678
46049
78780
17379
00000
00000
00000
00000
25000
06250
53906
46191
53869
83668
72928
08080
80050
25031
78144
88403
00000
x 10
00000
00000
00000
00000
00000
25000
40625
62891
51807
23792
14.870
09294
30808
56755
54721
X
X
x
x
x
x
x
x
x
x
x
x
x
x
x
10- 1
10- 2
10- 3
10- 4
10-6
10- 7
10- 8
10-9
10- 10
10- 12
10- 13
10- 14
10- 15
10- 16
10- 18
POWERS OF 10 (IN BASE 16)
10
3
23
163
DEO
8AC7
2
17
E8
918
5AF3
8D7E
8652
4578
B6B3
2304
1
F
98
5F5
3B9A
540B
4876
D4A5
4E72
107A
A4C6
6FCl
5D8A
A764
89E8
n
A
64
3E8
2710
86AO
4240
9680
El00
CAOO
E400
E800
1000
AOOO
4000
8000
0000
0000
0000
0000
10· n
n
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1.0000
0.1999
0.28F5
0.4189
0.68DB
0.A7C5
0.10C6
0.lAD7
0.2AF3
0.44B8
0.6DF3
O.AFEB
0.1197
0.lC25
0.2D09
0.480E
0.734A
0.B877
0.1272
0.1 D83
0000
9999
C28F
374B
8BAC
AC47
F7AO
F29A
lDC4
2FAO
7F67
FFOB
9981
C268
370D
BE7B
CA5F
AA32
5DDl
C94F
0000
9999
5C28
C6A7
710C
lB47
B5ED
BCAF
6118
9B5A
SEF6
CB24
2DEA
4976
4257
9D58
6226
36A4
D243
B6D2
0000
999A
F5C3
EF9E
B296
8423
8D37
4858
73BF
52CC
EADF
AAFF
1119
81C2
3604
566D
FOAE
B449
ABAl
AC35
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16 -I
16 -2
16 -)
16 -4
16 -4
16 -s
16 -6
16 -7
16 -8
16- 9
16-9
16 -10
16 -II
16 -12
16 -13
16 -14
16 -14
16 -IS
0-3
Appendix D. Binary-Decimal-Hexadecimal Conversion Tables
HEXADECIMAL-DECIMAL INTEGER CONVERSION
The table below provides for direct conversions between hexadecimal integers in the range O-FFF and decimal integers in the
range 0-4095. For conversion of larger integers, the table values may be added to the following figures:
Decimal
Hexadecimal
0
1
2
3
4
Hexadecimal
4096
8 192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49 152
53248
57344
61 440
65536
69632
73728
77824
81 920
86016
90 112
94208
98304
102400
106496
110592
114 688
118 784
122880
126976
01 000
02000
03000
04000
05000
06000
07000
08000
09000
OAOOO
DB 000
DC 000
00 000
DE 000
OF 000
10000
11 000
12000
13000
14000
15000
16000
17000
18000
19000
lA 000
lB 000
lC 000
10000
lE 000
1FOOD
5
6
20000
30000
40000
50000
60000
70000
80000
90000
AD 000
BO 000
CO 000
DO 000
EO 000
FO 000
100000
200000
300000
400000
500000
600000
700000
800000
900000
ADO 000
BOO 000
COO 000
000000
EOO 000
FOO 000
1 000000
2000000
7
8
9
Decimal
131 072
196608
262 144
327680
393216
458752
524288
589824
655360
720896
786432
851 968
917504
983040
1 048576
2097 152
3 145 728
4 194304
5242880
6291 456
7 340032
8388608
9437 184
10485760
11 534 336
12582912
13631 488
14 680064
15728640
16777216
33554432
A
B
C
0
0012 0013
0028 0029
0044 0045
0060 0061
E
F
0015
0031
0047
0063
000
010
020
030
0000
0016
0032
0048
0001
0017
0033
0049
0002
0018
0034
0050
0003
0019
0035
0051
0004 0005
0020 0021
0036 0037
0052 0053
0006
0022
0038
0054
0007
0023
0039
0055
0008
0024
0040
0056
040
050
060
070
0064
0080
0096
0112
0065 0066
0081 0082
0097 0098
0113 0114
0067
0083
0099
0115
0068 0069
0084 0085
0100 0101
0116 0117
0070
0086
0102
0118
0071
0087
0103
0119
0072
0088
0104
0120
0073
0089
0105
0121
0074
0090
0106
0122
0075
0091
0107
0123
0076
0092
0108
0124
0077
0093
0109
0125
0078 0079
0094 0095
0110 0111
0126 0127
080 0128
090 0144
OAO 0160
OBO 0176
0129
0145
0161
0177
0130
0146
0162
0178
0131
0147
0163
0179
0132 0133
0148 0149
0164 0165
0180 0181
0134
0150
0166
0182
0135
0151
0167
0183
0136
0152
0168
0184
0137 0138
0153 0154
0169 0170
0185 0186
0139
0155
0171
0187
0140 0141
0156 0157
0172 0173
0188 0189
0142 0143
0158 0159
0174 0175
0190 0191
OCO 0192
000 0208
OEO 0224
OFO 0240
0193 0194
0209 0210
0225 0226
0241 0242
0195
0211
0227
0243
0196 0197
0212 0213
0228 0229
0244 0245
0198 0199
0214 0215
0230 0231
0246 0247
0200
0216
0232
0248
0201 0202
0217 0218
0233 0234
0249 0250
0203
0219
0235
0251
0204 0205
0220 0221
0236 0237
0252 0253
0206 0207
0222 0223
0238 0239
0254 0255
0-4
0011
0027
0043
0059
0014
0030
0046
0062
0009 0010
0025 0026
0041 0042
0057 0058
Appendix D. Binary-Decimal-Hexadecimal Conversion Tables
HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont'd)
r--'
C
0
E
F
0267
0283
0299
0315
0268
0284
0300
0316
0269
0285
0301
0317
0270
0286
0302
0318
0271
0287
0303
0319
0330
0346
0362
0378
0331
0347
0363
0379
0331
0348
0364
0380
0333
0349
0365
0381
0334
0350
0366
0382
0335
0351
0367
0383
0393
0409
0425
0441
0394
0410
0426
0442
0395
0411
0427
0443
0396
0412
0428
0444
0397
0413
0429
0445
0398
0414
0430
0446
0399
0415
0431
0447
0456
0472
0488
0504
0457
0473
0489
0505
0458
0474
0490
0506
0459
0475
0491
050"/
0460
0476
0492
0508
0461
0477
0493
0509
0462
0478
0494
0510
0463
0479
0495
0511
0519
0535
0551
0567
0520
0536
0552
0568
0521
0537
0553
0569
0522
0538
0554
0570
0523
0539
0555
0571
0524
0540
0556
0572
0525
0541
0557
0573
0526
0542
0558
0574
0527
0543
0559
0575
0582
0598
0614
0630
0583
0599
0615
0631
0584
0600
0616
0632
0585
0601
0617
0633
0586
0602
0618
0634
0587
0603
0619
0635
0588
0604
0620
0636
0589
0605
0621
0637
0590
0606
0622
0638
0591
0607
0623
0639
0645
0661
0677
0693
0646
0662
0678
0694
0647
0663
0679
0695
0648
0664
0680
0696
0649
0665
0681
0697
0650
0666
0682
0698
0651
0667
0683
0699
0652
0668
0684
0700
0653
0669
0685
0701
0654
0670
0686
0702
0655
0671
0687
0703
0708
0724
0740
0756
0709
0725
0741
0757
0710
0726
0742
0758
0711
0727
0743
0759
0712
0728
0744
0760
0713
0729
0745
0761
0714
0730
0746
0762
0715
0731
0747
0763
0716
0732
0748
0764
0717
0733
0749
0765
0718
0734
0750
0766
0719
0735
0751
0767
0771
0787
0803
0819
0772
0788
0804
0820
0773
0789
0805
0821
0774
0790
0806
0822
0775
0791
0807
0823
0776
0792
0808
0824
0777
0793
0809
0825
0778
0794
0810
0826
0779
0795
0811
0827
0780
0796
0812
0828
0781
0797
0813
0829
0782
0798
0814
0830
0783
0799
0815
0831
0834
0850
0866
0882
0835
0851
0867
0883
0836
0852
0868
0884
0837
0853
0869
0885
0838
0854
0870
0886
0839
0855
0871
0887
0840
0856
0872
0888
0841
0857
0873
0889
0842
0858
0874
0890
0843
0859
0875
0891
0844
0860
0876
0892
0845
0861
0877
0893
0846
0862
0878
0894
0847
0863
0879
0895
0898
0914
0930
0946
0899
0915
0931
0947
0900
0916
0932
0948
0901
0917
0933
0949
0902
0918
0934
0950
0903
0919
0935
0951
0904
0920
0936
0952
0905
0921
0937
0953
0906
0922
0938
0954
0907
0923
0939
0955
0908
0924
0940
0956
0909
0925
0941
0957
0910
0926
0942
0958
0911
0927
0943
0959
0962 0963
0978 0979
0994 0995
1010 1011
0964
0980
0996
1012
0965
0981
0997
1013
0966
0982
0998
1014
0967
0983
0999
1015
0968 0969 0970
0984 0985 0986
1000 1001 1002
1016 1017 1018
0971
0987
1003
1019
0972
0988
1004
1020
0973
0989
1005
1021
0974
0990
1006
1022
0975
0991
1007
1023
100
110
120
130
0256
0272
0288
0304
1
0257
0273
0289
0305
2
0258
0274
0290
0306
3
0259
0275
0291
0307
4
0260
0276
0292
0308
5
0261
0277
0293
0309
6
0262
0278
0294
0310
7
0263
0279
0295
0311
8
0264
0280
0296
0312
9
0265
0281
0297
0313
0266
0282
0298
0314
140
150
160
170
0320
0336
0352
0368
0321
0337
0353
0369
0322
0338
0354
0370
0323
0339
0355
0371
0324
0340
0356
0372
0325
0341
0357
0373
0326
0342
0358
0374
0327
0343
0359
0375
0328
0344
0360
0376
0329
0345
0361
0377
180
190
lAO
180
0384
0400
0416
0432
0385
0401
0417
0433
0386
0402
0418
0434
0387
0403
0419
0435
038d
0404
0420
0436
0389
0405
0421
0437
0390
0406
0422
0438
0391
0407
0423
0439
0392
0408
0424
0440
lCO
100
lEO
1 FO
0448
0464
0480
0496
0449
0465
0481
0497
0450
0466
0482
0498
0451
0467
0483
0499
0452
0468
0484
0500
0453
0469
0485
0501
0454
0470
0486
0502
0455
0471
0487
0503
200
210
220
230
0512
0528
0544
0560
0513
0529
0545
0561
0514
0530
0546
0562
0515
0531
0547
0563
0516
0532
0548
0564
0517
0533
0549
0565
0518
0534
0550
0566
240
250
260
270
0576
0592
0608
0624
0577
0593
0609
0625
0578
0594
0610
0626
0579
0595
0611
0627
0580
0596
0612
0628
0581
0597
0613
0629
280
290
2AO
280
0640
0656
0672
0688
0641
0657
0673
0689
0642
0658
0674
0690
0643
0659
0675
0691
0644
0660
0676
0692
2CO
200
2EO
2FO
0704
0720
0736
0752
0705
0721
0737
0753
0706
0722
0738
0754
0707
0723
0739
0755
300
310
320
330
0768
0784
0800
0816
0769
0785
0301
0817
0770
0786
0802
0818
340
350
360
370
0832
0848
0864
0880
0833
0849
0865
0881
380
390
3AO
380
0896
0212
0928
0944
0897
0913
0929
0945
3CO
300
3EO
3FO
0960 0961
0976 0977
0992 0993
1008 1009
0
A
B
0-5
Appendix D. Binary-Decimal-Hexadecimal Conversion Tables
HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cant'd)
,
0
1024
1040
1056
1072
1
1025
1041
1057
1073
2
1026
1042
1058
1074
3
1027
1043
1059
1075
4
5
1028 102~
1044 1045
1060 1061
1076 1077
6
1030
1046
1062
1078
7
1031
1047
1063
1079
8
1032
1048
1064
1080
9
1033
1049
1065
1081
1036
1052
1068
1084
0
1037
1053
1069
1085
F
1034
1050
1066
1082
8
1035
1051
1067
1083
E
400
410
420
430
1038
1054
1070
1086
1039
1055
1071
1087
440
450
460
470
1088
1104
1120
1136
1089
1105
1121
1137
1090
1106
1122
1138
1091
1107
1123
1139
1092
1108
1124
1140
1093
1109
1125
1141
1094
i 110
1126
1142
1095
1111
1127
1143
1096
1112
1128
1144
1097
1113
1129
1145
1098
1114
1130
1146
1099
1115
1131
1147
1100
1116
1132
1148
1101
1117
1133
1149
1102
1118
1134
1150
1103
1119
1135
1151
480
490
4AO
480
1152
1168
1184
1200
1153
1169
1185
1201
1154
1170
1186
1202
1155
1171
1187
1203
1156
1172
1188
1204
1157
1173
1189
1205
1158
1174
1190
1206
1159
1175
1191
1207
1160
1176
1192
1208
1161
1177
1193
1209
1162
1178
1194
1210
1163
1179
1195
1211
1164
1180
1196
1212
1165
1181
1197
1213
1166
1182
1198
1214
1167
1183
1199
1215
4CO
400
4EO
4FO
1216
1232
1248
1264
1217
1233
1249
1265
1218
1234
1250
1266
1219
1235
1251
1267
1220
1236
1252
1268
1221
1237
1253
1269
1222
1238
1254
1270
1223
1239
1255
1271
1224
1240
1256
1272
1225
1241
1257
1273
1226
1242
1258
1274
1227
1243
1259
1275
1228
1244
1260
1276
1229
1245
1261
1277
1230
1246
1262
1278
1231
1247
1263
1279
500
510
520
530
1280
1296
1312
1328
1281
1297
1313
1329
1282
1298
1314
1330
1283
1299
1315
1331
1284
1300
1316
1332
1285
1301
1317
1333
1286
1302
1318
1334
1287
1303
1319
1335
1288
1304
1320
1336
1289
1305
1321
1337
1290
1'306
1322
1338
1291
1307
1323
1339
1292
1308
1324
1340
1293
1309
1325
1341
1294
1310
1326
1342
1295
1311
1327
1343
540
550
560
570
1344
1360
1376
1392
1345
1361
1377
1393
1346
1362
1378
1394
1347
1363
1379
1395
1348
1364
1380
1396
1349
1365
1381
1397
1350
1366
1382
1398
1351
1367
1383
1399
1352
1368
1384
1400
1353
1369
1-385
1401
1354
1370
1386
1402
1355
1371
1387
1403
1356
1372
1388
1404
1357
1373
1389
1405
1358
1374
1390
1406
1359
1375
1391
1407
580
590
SAO
580
1408
1424
1440
1456
1409
1425
1441
1457
1410
1426
1442
1458
1411
1427
1443
1459
1412
1428
1444
1460
1413
1429
1445
1461
1414
1430
1446
1462
1415
1431
1447
1463
1416
1432
1448
1464
1417
1433
1449
1465
1418
1434
1450
1466
1419
1435
1451
1467
1420
1436
1452
1468
1421
1437
1453
1469
1422
1438
1454
1470
1423
1439
1455
1471
5CO
500
5EO
5FO
1472
1488
1504
1520
1473
1489
1505
1521
1474
1490
1506
1522
1475
1491
1507
1523
1476
1492
1508
1524
1477
1493
1509
1525
1478
1494
1510
1526
1479
1495
1511
1527
1480
1496
1512
1528
1481
1497
1513
1529
1482
1498
1514
1530
1483
1499
1515
1531
1484
1500
1516
1532
1485
1501
1517
1533
1486
1502
1518
1534
1487
1503
1519
1535
600
610
620
630
1536
1552
1568
1584
1537
1553
1569
1585
1538
1554
1570
1586
1539
1555
1571
1587
1540
1556
1572
1588
1541
1557
1573
1589
154~
1543
1558 1559
1574 1575
1590 1591
1544
1560
1576
1592
1545
1561
1577
1593
1546
1562
1578
1594
1547
1563
1579
1595
1548
1564
1580
1596
1549
1565
1581
1597
1550
1566
1582
1598
1551
1567
1583
1599
640
650
660
670
1600
1616
1632
1648
1601
1617
1633
1649
1602
1618
1634
1650
1603
1619
1635
1651
1604
1620
1636
1652
1605
1621
1637
1653
1606
1622
1638
1654
1607
1623
1639
1655
1608
1624
1640
1656
1609
1625
1641
1657
1610
1626
1642
1658
1611
1627
1643
1659
1612
1628
1644
1660
1613
1629
1645
1661
1614
1630
1646
1662
1615
1631
1647
1663
680
690
6AO
680
1664
1680
1696
1712
1665
1681
1697
1713
1666
1682
1698
1714
1667
1683
1699
1715
1668
1684
1700
1716
1669
1685
1701
1717
1670
1686
1702
1?18
1671
1687
1703
1719
1672
1688
1704
1720
1673
1689
1705
1721
1674
1690
1706
1722
1675
1691
1707
1723
1676
1692
1708
1724
1677
1693
1709
1725
1678
1694
1710
1726
1679
1695
1711
1727
6CO
600
6EO
6FO
1728
1744
1760
1776
1729
1745
1761
1777
1730
1746
1762
1778
1731
1747
1763
1779
1732
1748
1764
1780
1733
1749
1765
1781
1734
1750
1766
1782
1735
1751
1767
1783
1736
1752
1768
1784
1737
1753
1769
1785
1738
1754
1770
1786
1739
1755
1771
1787
1740
1756
1772
1788
1741
1757
1773
1789
1742
1758
1774
1790
1743
1759
1775
1791
A
1
D-6
C
Appendix D. Binary-Decimal-Hexadecimal Conversion Tables
HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont'd)
0
1
2
3
4
6
1798
1814
1830
1846
7
1799
1815
1831
1847
8
1800
1816
1832
1848
9
1801
1817
1833
1849
A
1802
1818
1834
1850
8
1803
1819
1835
1851
C
1804
1820
1836
1852
0
E
F
1805
1821
1837
1853
1806
1822
1838
1854
1807
1823
1839
1855
700
710
720
730
1792
1808
1824
1840
1793
1809
1825
1841
1794
1810
1826
1842
1795
1811
1827
1843
1796
1812
1828
1844
5
1797
1813
1829
1845
740
750
760
770
1856
1872
1888
1904
1857
1873
1889
1905
1858
1874
1890
1906
1859
1875
1891
1907
1860
1876
1892
1908
1861
1877
1893
1909
1862
1878
1894
1910
1863
1879
1895
1911
1864
1880
1896
1912
1865
1881
1897
1913
1866
1882
1898
1914
1867
1883
1899
1915
1868 1869
1884 1885
1900 1901
191~ 1917
1870
1886
1902
1918
1871
1887
1903
1919
780
790
7AO
780
1920
1936
1952
1968
1921
1937
1953
1969
1922
1938
1954
1970
1923
1939
1955
1971
1924
1940
1956
1972
1925
1941
1957
1973
1926
1942
1958
1974
1927
1943
1959
1975
1928
1944
1960
1976
1929
1945
1961
1977
1930
1946
1962
1978
1931
1947
1963
1979
1932
1948
1964
1980
1933
1949
1965
1981
1934
1950
1966
1982
1935
1951
1967
1983
7CO
700
7EO
7FO
1984
2000
2016
2032
1985
2001
2017
2033
1986
2002
2018
2034
1987
2003
2019
2035
1988
2004
2020
2036
1989
2005
2021
2037
1990
2006
2022
2038
1991
2007
2023
2039
1992
2008
2024
2040
1993
2009
2025
2041
1994
2010
2026
2042
1995
2011
2027
2043
1996
2012
2028
2044
1997
2013
2029
2045
1998
2014
2030
2046
1999
2015
2031
2047
800
2048
810
820
830
2080
2096
2049
2065
2081
2097
2050
2066
2082
2098
2051
2067
2083
2099
2052
2068
2084
2100
2053
2069
2085
2101
2054
2070
2086
2102
2055
2071
2087
2103
2056
2072
2088
2104
2057
2073
2089
2105
2058
2074
2090
2106
2059
2075
2091
2107
2060
2076
2092
2108
2061
2077
2093
2109
2062
2078
2094
2110
2063
2079
2095
2111
840
850
860
870
2112
2128
2144
2160
2113
2129
2145
2161
2114
2130
2146
2162
2115
2131
2147
2163
2116
2132
2148
2164
2117
2133
2149
2165
2118
2134
2150
2166
2119
2135
2151
2167
2120
2136
2152
2168
2121
2137
2153
2169
2122
2138
2154
2170
2123
2139
2155
2171
2124
2140
2156
2172
2125
2141
2157
2173
2126
2142
2158
2174
2127
2143
2159
2175
880
890
8AO
880
2176
2192
2208
2224
2177
2193
2209
2225
2178
2194
2210
2226
2179
2195
2211
2227
2180
2196
2212
2228
2181
2197
2213
2229
2182
2198
2214
2230
2183
2199
2215
2231
2184
2200
2216
2232
2185
2201
2217
2233
2186
2202
2218
2234
2187
2203
2219
2235
2188
2204
2220
2236
2189
2205
2221
2237
2190
2206
2222
2238
2191
2207
2223
2239
8CO
800
8EO
8FO
2240
2256
2272
2288
2241
2257
2273
2289
2242
2258
2274
2290
2243
2259
2275
2291
2244
2260
2276
2292
2245
2261
2277
2293
2246
2262
2278
2294
2247
2263
2279
2295
2248
2264
2280
2296
2249
2265
2281
2297
2250
2266
2282
2298
2251
2267
2283
2299
2252
2268
2284
2300
2253
2269
2285
2301
2254
2270
2286
2302
2255
2271
2287
2303
900
910
920
930
2304
2320
2336
2352
2305
2321
2337
2353
2306
2322
2338
2354
2307
2323
2339
2355
2308
2324
2340
2356
2309
2325
2341
2357
2310
2326
2342
2358
2311
2327
2343
2359
2312
2328
2344
2360
2313
2329
2345
2361
2314
2330
2346
2362
2315
2331
2347
2363
2316
2332
2348
2364
2317
2333
2349
2365
2318
2334
2350
2366
2319
2335
2351
2367
940
950
960
970
2368
2384
2400
2416
2369
2385
2401
2417
2370
2386
2402
2418
2371
2387
2403
2419
2372
2388
2404
2420
2373
2389
2405
2421
2374
2390
2406
2422
2375
2391
2407
2423
2376
2392
2408
2424
2377
2393
2409
2425
2378
2394
2410
2426
2379
2395
2411
2427
2380
2396
2412
2428
2381
2397
2413
2429
2382
2398
2414
2430
2383
2399
2415
2431
980
990
9AO
980
2432
2448
2464
2480
2433
2449
2465
2481
2434
2450
2466
2482
2435
2451
2467
2483
2436
2452
2468
2484
2437
2453
2469
2485
2438
2454
2470
2486
2439
2455
2471
2487
2440
2456
2472
2488
2441
2457
2473
2489
2442
2458
2474
2490
2443
2459
2475
2491
2444
2460
2476
2492
2445
2461
2477
2493
2446
2462
2478
2494
2447
2463
2479
2495
9CO
2496
2512
2528
2544
2497
2513
2529
2545
2498
2514
2530
2546
2499
2515
2531
2547
2500
2516
2532
2548
2501
2517
2533
2549
2502
2518
2534
2550
2503
2519
2535
2551
2504
2520
2536
2552
2505
2521
2537
2553
2506
2522
2538
2554
2507
2523
2539
2555
2508
2524
2540
2556
2509
2525
2541
2557
2510
2526
2542
2558
2511
2527
2543
2559
900
9EO
9FO
2064
D-7
Appendix D_
Binary-Decimal-Hexadecimal Conversion Tables
HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont'd)
8
2568
2584
2600
2616
9
A
B
C
0
E
F
2565
2581
2597
2613
7
6
2566 2567
2582 2583
2598 2599
2614 2615
2569
2585
2601
2617
2570
2586
2602
2618
2571
2587
2603
2619
2572
2588
2604
2620
2573
2589
2605
2621
2574
2590
2606
2622
2575
2591
2607
2623
2628
2644
2660
2676
2629
2645
2661
2677
2630
2646
2662
2678
2631
2647
2663
2679
2632
2648
2664
2680
2633 2634 2635
2649 2650 2651
2665 2666 2667
2681 2682 2683
2636
2652
2668
2684
2637
2653
2669
2685
2638
2654
2670
2686
2639
2655
2671
2687
2691
2707
2723
2739
2692
2708
2724
2740
2693
2709
2725
2741
2694 2695
2710 2711
2726 2727
2742 2743
2696
2712
2728
2744
2697 2698 2699
2713 2714 2715
2729 2730 2731
2745 2746 2747
2700
2716
2732
2748
2701
2717
2733
2749
2702
2718
2734
2750
2703
2719
2735
2751
2754
2770
2786
2802
2755
2771
2787
2803
2756
2772
2788
2804
2757
2773
2789
2805
2758
2774
2790
2806
2759
2775
2791
2807
2760
2776
2792
2808
4761
2777
2793
2809
2762
2778
2794
2810
2763
2779
2795
2811
2764
2780
2796
2812
2765
2781
2797
2813
2766
2782
2798
2814
2767
2783
2799
2815
2817
2833
2849
2865
2818
2834
2850
2866
2819
2835
3851
2867
2820
2836
2852
2868
2821
2837
2853
2869
2822
2838
2854
2870
2823
2839
2855
2871
2824
2840
2856
2872
2825
2841
2857
2873
2826
2842
2858
2874
2827
2843
2859
2875
2828
2844
2860
2876
2829
2845
2861
2877
2830
2846
2862
2878
2831
2847
2863
2879
2880
2896
2912
2928
2881
2897
2913
2929
2882
2898
2914
2930
2883
2899
2915
2931
2884
2900
2916
2932
2885
2901
2917
2933
2866
2902
2918
2934
2887
2903
2919
2935
2888
2904
2920
2936
2889
2905
2921
2937
2890
2906
2922
2938
2891
2907
2923
2939
2892
2908
2924
2940,
2893
2909
2925
2941
2894
2910
2926
2942
2895
2911
2927
2943
B80
890
8AO
BBO
2944
2960
2976
2992
2945
2961
2977
2993
2946
2962
2978
2994
2947
2963
2979
2995
2948
2964
2980
2996
2949
2965
2981
2997
2950 2951
2966 2967
2982 2983
2998 2999
2952
2968
2984
3000
2953 2954
2969 2970
2985 2986
3001 3002
2955
2971
2987
3003
2956
2972
2988
3004
2957
2973
2989
3005
2958
2974
2990
3006
2959
2975
2991
3007
BCO
BOO
BEO
BFO
3008
3024
3040
3056
3009 3010
3025 3026
3041 3042
3057 30~;8
3011
3027
3043
3059
3012
3028
3044
3060
3013
3029
3045
3061
3014
3030
3046
3062
3015
3031
3047
3063
3016
3032
3048
3064
3017
3033
3049
3065
3018
3034
3050
3066
3019
3035
3051
3067
3020
3036
3052
3068
3021
3037
3053
3069
3022
3038
3054
3070
3023
3039
3055
3071
COO
C10
C20
C30
3072 3073 3074
3088 3089 3090
3104 3105 3106
3120 3121 3122
3075
3091
3107
3123
3076
3092
3108
3124
3077
3093
3109
3125
3078
3094
3110
3126
3079
3095
3111
3127
3080
3096
3112
3128
3081
3097
3113
3129
3082
3098
3114
3130
3083
3099
3115
3131
3084
3100
3116
3132
3085
3101
3117
3133
3086
3102
3118
3134
3087
3103
3119
3135
C40
C50
C60
C70
3136
3152
3168
3184
3137
3153
3169
3185
3138
3154
3170
3186
3139
3155
3171
31H7
3140
3156
3172
3188
3141
3157
3173
3189
3142
3158
3174
3190
3143
3159
3175
3191
3144
3160
3176
3192
3145
3161
3177
3193
3146
3162
3178
3194
3147
3163
3179
3195
3148
3164
3180
3196
3149
3165
3181
3197
3150
3166
3182
3198
3151
3167
3183
3199
C80
C90
CAO
CBO
3200
3216
3232
3248
3201
3217
3233
3249
3202
3218
3234
3250
3203
3219
3235
3251
3204
3220
3236
3252
3205
3221
3237
3253
3206
3222
3238
3254
3207
3223
3239
3255
3208
3224
3240
3256
3209
3225
3241
3257
3210
3226
3242
3258
3211
3227
3243
3259
3212
3228
3244
3260
3213
3229
3245
3261
3214
3230
3246
3262
3215
3231
3247
3263
CCO
COO
CEO
CFO
3264
3280
3296
3312
3265
3281
3297
3313
3266
3282
3298
3314
3267
3283
3299
3315
3268
3284
3300
3316
3269
3285
3301
3317
3270
3286
3302
3318
3271
3287
3303
3319
3272
3288
3304
3320
3273
3289
3305
3321
3274
3290
3306
3322
3275
3291
3307
3323
3276
3292
3308
3324
3277
3293
3309
3325
3278
3294
3310
3326
3279
3295
3311
3327
2
~561 2562
2577 2578
2593 2594
2609 2610
3
2563
2579
2595
2611
4
5
ADO
Al0
A20
A30
0
2560
2576
2592
2608
2564
2580
2596
2612
A40
A50
A60
A70
2624
2640
2656
2672
2625
2641
2657
2673
2626
2642
2658
2674
2627
2643
2659
2675
A80
A90
AAO
ABO
2688
2704
2720
2736
2689
2705
2721
2737
2690
2706
2722
2738
ACO
ADO
AEO
AFO
2752
2768
2784
2800
2753
2769
2785
2801
BOO
Bl0
820
830
2816
2832
2848
2864
B40
B50
B60
B70
D-8
1
Appendix D. Binary-Decimal-Hexadecimal Conversion Tables
HEXADECIMAL-DECIMAL INTEGER CONVERSION (Cont'd)
~
I
1
3329
3345
3361
3377
2
3330
3346
3362
3378
3
3331
3347
3363
3379
4
5
6
7
8
9
A
B
C
0
E
F
000
010
020
030
0
332 8
3344
336o
337 6
3332
3348
3364
3380
3333
3349
3365
3381
3334
3350
3366
3382
3335
3351
3367
3383
3336
3352
3368
3384
3337
3353
3369
3385
3338
3354
3370
3386
3339
3355
3371
3387
3340
3356
3372
3388
3341
3357
3373
3389
3342
3358
3374
3390
3343
3359
3375
3391
040
050
060
070
339 2
340 8
3424
344 o
3393
3409
3425
3441
3394
3410
3426
3442
3395
3411
3427
3443
3396
3412
3428
3444
3397
3413
3429
3445
3398
3414
3430
3446
3399
3415
3431
3447
3400
3416
3432
3448
3401
3417
3433
3449
3402 3403
3418 3419
3434 3435
3450 3451
3404
3420
3436
3452
3405
3421
3437
3453
3406
3422
3438
3454
3407
3423
3439
3455
080
090
OAO
OBO
34 56
347 2
34 88
3 504
3457
3473
3489
3505
3458
3474
3490
3506
3459
3475
3491
3507
3460
3476
3492
3508
3461
3477
3493
3509
3462
3478
3494
3510
3463
3479
3495
3511
3464
3480
3496
3512
3465
3481
3497
3513
3466
3482
3498
3514
3467
3483
3499
3515
3468
3484
3500
3516
3469
3485
3501
3517
3470
3486
3502
3518
3471
3487
3503
3519
OCO
000
DEO
DFO
352o
353 6
355 2
356 8
3521
3537
3553
3569
3522
3538
3554
3570
3523
3539
3555
3571
3524
3540
3556
3572
3525
3541
3557
3573
3526
3542
3558
3574
3527
3543
3559
3575
3528
3544
3560
3576
3529
3545
3561
3577
3530
3546
3562
3578
3531
3547
3563
3579
3532
3548
3564
3580
3533
3549
3565
3581
3534
3550
3566
3582
3535
3551
3567
3583
EOO
El0
E20
E30
35 84
36 00
361 6
363 2
3585
3601
3617
3633
3586
3602
36'8
3634
3587
3603
3619
3635
3588
3604
3620
3636
3589
3605
3621
3637
3590
3606
3622
3638
3591
3607
3623
3639
3592
3608
3624
3640
3593
3609
3625
3641
3594
3610
3626
3642
3595
3611
3627
3643
3596
3612
3628
3644
3597
3613
3629
3645
3598
3614
3630
3646
3599
3615
3631
3647
E40
E50
E60
E70
364 8
3664
36 80
36 96
3649
3665
3681
3697
3650
3666
3682
3698
3651
3667
3683
3699
3652
3668
3684
3700
3653
3669
3685
3701
3654
3670
3686
3702
3655
3671
3687
3703
3656
3672
3688
3704
3657
3673
3689
3705
3658
3674
3690
3706
3659
3675
3691
3707
3660
3676
3692
3708
3661
3677
3693
3709
3662
3678
3694
3710
3663
3679
3695
3711
E80
E90
EAO
EBO
371 2
372 8
3744
376o
3713
3729
3745
3761
3714
3730
3746
3762
3715
3731
3747
3763
3716
3732
3748
3764
3717
3733
3749
3765
3718
3734
3750
3766
3719
3735
3751
3767
3720
3736
3752
3768
3721
3737
3753
3769
3722
3738
3754
3770
3723
3739
3755
3771
3724
3740
3756
3772
3725
3741
3757
3773
3726
3742
3758
3774
3727
3743
3759
3775
ECO
EDO
EEO
EFO
377 6
379 2
380 8
3824
3777
3793
3809
3825
3778
3794
3810
3826
3779
3795
3811
3827
3780
3796
3812
3828
3781
3797
3813
3829
3782
3798
3814
3830
3783
3799
3815
3831
3784
3800
3816
3832
3785
3801
3817
3833
3786
3802
3818
3834
3787
3803
3819
3835
3788
3804
3820
3836
3789
3805
3821
3837
3790
3806
3822
3838
3791
3807
3823
3839
Foo
FlO
F20
F30
384 o
38 56
387 2
3888
3841
3857
3873
3889
3842
3858
3874
3890
3843
3859
3875
3891
3844
3860
3876
3892
3845
3861
3877
3893
3846
3862
3878
3894
3847
3863
3879
3895
3848
3864
3880
3896
3849
3865
3881
3897
3850
3866
3882
3898
3851
3867
3883
3899
3852
3868
3884
3900
3853
3869
3885
3901
3854
3870
3886
3902
3855
3871
3887
3903
F40
F50
F60
F70
3904
392o
3936
395 2
3905
3921
3937
3953
3906
3922
3938
3954
3907
3923
3939
3955
3908
3924
3940
3956
3909
3925
3941
3957
3910
3926
3942
3958
3911
3927
3943
3959
3912
3928
3944
3960
3913
3929
3945
3961
3914
3930
3946
3962
3915
3931
3947
3963
3916
3932
3948
3964
3917
3933
3949
3965
3918
3934
3950
3966
3919
3935
3951
3967
FSO
F90
FAO
FBO
396 8
39 84
40 00
401 6
3969
3985
4001
4017
3970
3986
4002
4018
3971
3987
4003
4019
3972
3988
4004
4020
3973
3989
4005
4021
3974
3990
4006
4022
3975
3991
4007
4023
3976
3992
4008
4024
3977
3993
4009
4025
3978
3994
4010
4026
3979
3995
4011
4027
3980
3996
4012
4028
3981
3997
4013
4029
3982
3998
4014
4030
3983
3999
4015
4031
FCO
FDO
FEO
FFO
403 2
404 8
4064
40 80
4033
4049
4065
4081
4034
4050
4066
4082
4035
4051
4067
4083
4036
4052
4068
4084
4037
4053
4069
4085
4038
4054
4070
4086
4039
4055
4071
4087
4040
4056
4072
4088
4041
4057
4073
4089
4042
4058
4074
4090
4043
4059
4075
4091
4044
4060
4076
4092
4045
4061
4077
4093
4046
4062
4078
4094
4047
4063
4079
4095
0-9
INDEX
Absolute symbols
Accumulator
Accumulator Instructions
ACI Instruction
ADC Instruction
ADD Instruction
ADI Instruction
Addressing Modes
Addressing Registers
ANA (AND) Instruction
AN D Operator
ANI (AND Immediate) Instruction
Arithmetic Expression Operators
Arithmetic Instructions
ASCII Constant
ASEG (Absolute Segment) Directive
Assembler, Need for
Assembler Character Set
Assembler Compared with PL/M
Assembler Function . . .
Assembler Termination
Assembly-Time Expression Evaluation
Auxiliary Carry Flag
Auxiliary Carry Flag Setting - 8080/8085 Differences
l3i nary Data (Coding Rules)
blank (character)
Branching Instructions
Branch Table
Byte Isolation Operations
CALL Instruction
.... .
Carry Flag . . .
.... .
CC (Call if Carry) Instruction
eM (Call if Minus) Instruction
CMA (Complement Accumulator) Instruction
CMC (Complement Carry) Instruction
CMP (Compare) Instruction
CNC (Call if no carry) Instruction
CNZ (Call if not Zero) Instruction
Combined Addressing Modes
Comment Field . . . . .
Compare Operators
Comparing Complemented Data
Comparisons in Expressions
Complement Used for Subtraction
Complemented Data
Concatenation
2-11, 2-16
1-6, 1-7
.1-79
3-2
3-2
3-4
3-5
.7 -75
1-7
· 3-6
.2-73
· 3-7
2-12
7-77
· 2-6
.4-74
1-3
2-1
1-3
1-1
.4-70
.2-11
.7-77
.7 -7 2
· 2-6
· 2-3
7-78, 7-22
· 6-1
.2-74
· 3-8
.7 -7 0
.3-70
.3-70
.3-77
.3-72
.3-72
.3-74
.3-74
.7-16
· 2-4
.2-73
· 2-8
.2-13
· 2-7
· 2-8
5-10,5-11,5-15,5-16
1-1
Condition Flags
Conditional Assembly . . . . .
CP (Call if Positive) Instruction
CPE (Call if Parity Even) Instruction
CPI (Compare Immediate) Instruction
CPO (Call if Parity Odd) Instruction
CSEG (Code Segment) Directive
CZ (Call if Zero) Instruction . . .
DAA (Decimal Adjust Accumulator) Instruction
DAD (Double Register Add) Instruction
Data Access Example . .
Data Definition . . . . .
Data Description Example
Data for Subroutines . .
Data Label
..... .
Data Transfer Instructions
DB (Define Byte) Directive
DCR (Decrement) Instruction
DCX (Decrement Register Pair)
Decimal Addition Routine . .
Decimal Data (Coding Rules)
Decimal Subtraction Routine'
Delimiters
........ .
DI (Disable Interrupts) Instruction
Direct Addressing
Divide (Software Example)
Division in Expressions
DS (Define Storage) Directive
DSEG (Data Segment) Directive
Dummy Parameters
DW (Define Word) Directive
EI (Enable Interrupts) Instruction
ELSE Directive .
EN D Directive
ENDIF Directive
ENDM {End Macro} Directive
EOT Directive
EPROM
EQ Operator
EQU Directive
EXITM (Exit Macro) Directive
Expression Evaluation
Expression Operators
Expressions
Expressions, Precedence of Operators
Expressions, Range of Val ues
EXTRN Directive . . . . . . . . .
1-2
1-9
· 4-8
3-75
3-76
3-76
3-77
4-75
3-78
3-78
3-20
4-7
4-3
4-6
6-3
2-5
7-7 6
4-3
3-20
3-22
6-12
· 2-5
6-14
· 2-2
. 3-22,3-60
7-7 5
· 6-9
2-12
· 4-5
4-75
· 5-4
· 4-4
3-23
· 4-8
4-70
· 4-8
5-5,5-6,5-7,5-12
4-77
. 1-5
2-73
4-2
5-9
2-11
2-11
2-6
2-75
2-75
4-77
GE Operator
General Purpose Registers
GT Operator
Hardware Overview
Hexadecimal Data (Coding Rules)
HIGH Operator
HL T (Halt) Instruction
I F Directive
Irnmediate Addressing
Irnpl ied Addressi ng
IN (Input) Instruction
INPAGE Reserved Word
Input/Output Ports
INR (Increment) Instruction
Instruction Addressing Modes
Instruction Execution
Instruction Fetch
Instruction Label
Instruction Naming Conventions
Instruction Set Guide
Instruction Summary
Instruction Timing
Instructions as Operands
INTE Pin
Internal Registers
Interrupt Subroutines
Interrupts
.....
Interrupts (8085) . .
INX (Increment Register Pair) Instructions
I RP (I ndefinite Repeat) Directive
IRPC (Indefinite Repeat Character)
JC (J ump if Carry) Instruction
J M (J ump if Minus) Instruction
JMP (jump) Instruction
J NC (J ump if no carry) Instruction
J NZ (J ump if not zero) Instruction
J P (J ump if Positive) Instruction
J PE (J ump if parity Even) . .
J PO (J ump if parity Odd)
J Z (J ump if Zero) Instruction
Label Field
Labels
. . . . . . . . . . . . . . .
LDA (Load Accumulator Direct) Instruction
LDAX (Load Accumulator Indirect)
2-73
7-7
2-73
1-5
2-5
2-74, 3-2, 3-5, 3-7, 404
........
3-24
4-8
7-75
7-75
.7-74,3-24
.4-74,4-75
7-74
3-25
7-75
1-9
1-8
2-6
1-16
7-23
. 1-19, 7-23
3-7
2-7
3-49
1-6
7-4
7-1
1-24
3-26
. 5-8, 5-12, 5-22
. 5-8, 5-12, 5-17
3-26
3-27
3-28
3-28
3-29
3-29
3-30
3-37
3-32
2-3
2-6
3-32
3-33
1-3
LE Operator
LI B Program
. . . . . .
LHLD (Load L Direct) Instruction
LIN K Program
Linkage
List File
LOCAL Directive
LOCAL Symbols
LOCATE Program
Location Counter (Coding Rules)
Location Counter Control (Absolute Mode)
Location Counter Control (Relocatable Mode)
Logical Instructions
Logical Instructions, Summary
Logical Operators
LOW Operator
LT Operator . .
LXI (Load Register Pair Immediate)
Macros
Macro Calls
Macro Definition
MACRO Directive
Macro Expansion
Macro Parameters
Macros versus Subroutines
Manual Programming. . .
Memory
...... .
Memory Management with Relocation
Memory Reservation
MEMORY Reserved Word
MOD Operator
Modular Programming
MODULE Default Name
MOV (Move) Instruction
Multibyte Addition Routines
Multibyte Subtraction Routine
Multipl ication in Expressions
Multiply (Software Example)
MVI (Move Immediate)
NAME Directive
NE Operator
Nested Macro Calls
Nested Macro Definitions
Nested Subroutines
Nine's Complement
NOP (No Operation) Instruction
1-4
2-73
4-'12
3-34
4-12,4-14,4-15
4-16
1-1
5-5
5-6
.4-'12,4-13,4-14,4-19
2-6
4-77
4·-74
7-77
3-6
2-73
2-74, 3-2, 3-5, 3-7, 4-4
2-73
3-35
5-1
5-72
5-4
5-4
5-15
5-5
5-3
1-3
1-5
4-72
4-5
4-79
2-12
4-72
4-17
3-36
6-11
6-11
2-12
6-7
3-37
4-78
2-13
5-'14
5-'12
3-48
2-7
3-38
NOP
NOT
NUL
Null
Null
via MOV
Operator
Operator
Macros
Parameter
Object Code
Object File
Octal Data {Coding Rules}
One's Complement
Opcode
Opcode Field
Operand Field
Operand Field {Coding Rules}
Operands
Operators, Expression
OR Operator
ORG {Origin} Directive (Absolute Mode)
ORG {Origin} Directive (Relocatable Mode)
ORA (Inclusive OR) Instruction
ORI {Inclusive OR Immediate}
OUT Instruction
PAG E Reserved Word
.............. .
Parity Flag
. . . . . . . . . . . . . . .
PCHL (Move H & L to Program Counter) Instruction
Permanent Symbols
PL/M
PL/M Compared with Assembler
POP Instruction
POP PSW instruction
Precedence of Expression Operators
Processor Registers
Program Counter
Program Linkage Directives
Program Listing
Program Status
Program Status Word (PSW)
Programming the 8085
PROM
PSW
PUBLIC Directive
PUSH Instruction
PUSH PSW Instruction
RAM
................ .
RAM versus ROM . . . . . . . . . . . . .
RAL (Rotate Left through Carry) Instruction
3-36
2-73
.2-13,5-77
5-16
5-11
7-2
1-1
2-5
2-7
1-1
2-4
2-4
2-4
2-5
2-11
2-73
4-77
4-76
3-38
.. 3-40
1-14, 3-47
.4.-74,4-75
7-77
3-42
2-11
1-3
1-3
3-42
3-43
2-75
1-9
1-6
4-76
1-2
1-13
7-74
1-24
1-5
. 7-7 4, 3-45
4-77
3-44
345
1-5
4-6
3-45
1-5
RAR (Rotate Right through Carry) Instruction
RC (Return if Carry) Instruction
Redefinable Symbols
Register Addressing
Register Indirect Addressing
Register Pair Instructions
Register Pairs
Relocatability Defined
Relocatable Expressions
Relocatable Symbols
Relocation Feature
Reserved Symbols
RESET Signal
RET (Return) Instruction
REPT Directive
RIM (Read Interrupt Mask) 8085 Instruction
RLC (Rotate Accumulator Left) Instruction
RM (Return if Minus) Instruction
RNC (Return if no Carry) Instruction
RNZ (Return if not Zero) Instruction
ROM
............ .
RP (Return if Positive) Instruction
RPE (Return if Parity Even) Instruction
RPO (Return if Parity Odd) Instruction
RRC (Rotate Accumulator Right) Instruction
RST (Restart) Instruction
RST5.5
RST6.5
RST7.5
RZ (Return if Zero) Instruction
Savings Program Status
........... .
SBB (Subtract with Borrow) Instruction
SBI (Subtract Immediate with Borrow) Instruction
Scope of Symbols
SET Directive
Shift Expression Operators
Shift Operations in Expressions
SHL Operator
SHLD (Store H & L Direct) Instruction
SHR Operator
. . . . .
Sign Flag
.....
SIM (Set Interrupt Mask) 8085 Instruction
Software Divide Routine
Software Multiply Routine
Source Code Format
Source Line Fields
Source Program File
SPHL (Move H & L to Stack Pointer) Instruction
1-6
3-46
3-47
2·11
7-75
7-7 6
7·27
1-7
4-72
.2-76, 2-79
2-11
1-2
2-9
3-24
3-48
5-6,5-12,5-15,5-16,5-17,5-18
3-48
3-49
3-50
3-57
3-57
1-5
3-52
3-52
3-53
3-53
3-54
·
·
·
·
3-49, 3-55, 3-59,
3-49, 3-55, 3-59,
3-49, 3·55; 3-59,
.......
3-60
3-60
3-60
3-55
7-7 3
3-56
3-57
2-10
4-3
2-12
2-12
2-72
3-58
2-72
7-10
3-59
6-7
6-7
2-1
2-1
1-1
3-67
SP (Stack Pointer Register)
. . . . . .
ST A (Store Accumulator Direct) Instruction
Stack
Stack and Machine Control Instructions
Stack Operations
Stack Pointer
ST ACK Reserved Word
Start Execution Address
ST AX (Store Accumulator Indirect) Instruction
STC (Set Carry) Instruction
STKLN Directive
SUB (Subtract) Instruction
Subroutine Data
Subroutines
Subroutines versus Macros
Subtraction for Comparison
SUI (Subtract Immediate) Instruction
Symbol-Cross-Reference File
Symbol Definition
Symbol Table
Symbolic Addressing
Symbols
Symbols, Absolute
Symbols (Coding Rules)
Symbols, Global
Symbols, Limited
Symbols, Permanent
Symbols, Redefinable
Symbols, Relocatable
Symbols, Reserved
TRAP Interrupt
Ten's Complement
Testing Relocatable Modules
Timing Effects of Addressing Modes
TRAP (8085)
.....
Two's Complement Data
Use of Macros
...... .
Using Symbols for Data Access
Value of Expressions
What
Word
Word
Work
is a Macro?
Instructions
Storage in Memory
Registers
3-35
3-61
1-12
1-19
1-13
1-12
4-19, 3-35
4-10
3-62
3-63
4-18
3-63
6-3
1;12, 3-9
5-3
3-12
3-64
.1-1,1-3
4-2
2-9
2-9
2-9
2-11
2-9
2-10
2-10
2-11
2-11
2-11
2-9
3-54
2-7
4-19
1-16
3-23
2-7
5-1
4-7
2-15
5-2
1-21
4-4
1-7
1-7
XCHG (Exchange H & L with
XOR Operator . . . . . . . .
XRA (Exclusive OR) Instruction
XRI (Exclusive OR Immediate)
XTHL (Exchange H & L with
Zero Flag
(ampersand) . . . . . . .
<> (angle brackets) . . . . .
CR (carriage return character)
(colon)
(comma)
..
(double semicolon)
"
(division) Operator
(exclamation point)
HT (horizontal tab character)
(minus) Operator
(multiplication)
Operator
*
( ) (parentheses)
(plus) Operator
+
??nnnn Symbols
(semicolon)
(single quote)
(character)
space
&
8080/8085 Differences
8085 Features
8085 Processor
8085 Programming
1-8
D & E) Instruction
.
Instruction
Top of Stack) Instruction
3-65
2-73
3-66
3-67
3-69
7-77
5-10
5-10
2-2
2-2
2-2
5-10
2-12
5-10
2-2
2-12
2-12
2-2
2-12
5-5
2-2
2-2
2-2
7-24
1-24
7-24
1-24
8080/8085 Assembly Langua!
Programming Manu
9800301-
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