AMS AS3517 Datasheet
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Annonce
austriamicrosystems AG is now ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0 e-Mail: [email protected]
Please visit our website at
www.ams.com
AS3517 V17
Data Sheet, Confidential
Data Sheet, Confidential
AS3517
Stereo Audio Codec with enhanced System Power Management
The AS3517 is a low power stereo audio codec and is designed for Portable Digital Audio Applications. It allows playback and recording in CD quality. It has a variety of audio inputs and outputs to directly connect electret microphones,
16
Ω/32Ω headsets and auxiliary signal sources via a 10channel mixer. It only consumes 20mW in playback mode.
Further the device offers advanced power management functions. All necessary ICs and peripherals in a Digital Audio
Player with flash or harddisk memory are supplied by the
AS3517. The different regulated supply voltages are programmable via the serial control interface. The power management block generates 11 different supply voltages out of a single battery supply. CPU, NAND flash, SRAM, memory cards, harddisk, LCD, LCD backlight, USB-HOST and USB-
OTG can be powered. AS3517 also contains a charger. The single supply voltage may vary from 3.0V to 5.5V.
The AS3517 has an on-chip, phase locked loop (PLL) controlled, clock generator. It generates 44.1kHz, 48kHz and other sample rates defined in MP3, AAC, WMA, OGG VORBIS etc. No additional external crystal or PLL is needed in slave mode. Further the AS3517 has an independent 32kHz real time clock (RTC) on chip which allows a complete power down of the system CPU.
• Multi-bit Sigma Delta Converters
– DAC: 94dB SNR (‘A’ weighted) @ 2.9V
– ADC: 90dB SNR (‘A’ weighted) @ 2.9V
ams
– Sampling Frequency: 8-48kHz
• 2 Microphone Inputs
– 3 gain pre-setting (28dB/34dB/40dB) and AGC
– 32 gain steps @1.5dB and MUTE
– supply for electret microphone
– microphone detection
– remote control by switch
• 2 Line Inputs
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– stereo or 2x mono or mono differential
• Audio Mixer
– 10 channel input/output mixer with AGC
– mixes line inputs and microphones with DAC
– left and right channels independent
• 2 Line Outputs
Technical
– Differential 10mW to 32ohm (earpiece)
• High Efficiency Headphone Amplifier
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– 2x60mW @16
Ω driver capability
– headphone and over-current detection
– phantom ground eliminates large capacitors
• Power Management
– step down for CPU core (0.65V-3.4V, 250mA)
– step down for peripheral (0.65V-3.4V, 250mA)
– step down for harddisk (0.65V-3.4V, 500mA)
– step up for backlight (15V (25V), 38mA),
– LDO for digital supply (2.9V, 200mA)
– LDO for analog supply (2.9V, 200mA)
– LDO for peripherals (1.2V-3.5V, 200mA)
– LDO for peripherals (1.2V-3.5V, 200mA)
– LDO for RTC (1.0V-2.5V, 2mA)
– power supply supervision
– hibernation modes
• Battery Charger
– automatic trickle charge (50mA)
still
– prog. constant current charging (50-460mA)
valid
• Real Time Clock
– ultra low power 32kHz oscillator
– 32bit RTC sec counter, 96 days auto wake-up
– selectable alarm (seconds or minutes)
– 128bit free SRAM for random settings
– 32kHz clock output to peripheral
• Auxiliary Oscillator (only for master clock mode)
– low power 12-24MHz oscillator
• General Purpose ADC
– 10bit resolution
– 21 inputs analog multiplexer
• Interfaces
– I²S digital audio interface and SPDIF
– 2 wire serial control interface
– reset pin, watchdog, power good pin
– PWM output
– 128bit unique ID (OTP)
– 30 different interrupts
• Package CTBGA81 [9.0x9.0x1.15mm] 0.8mm pitch
3 Application
Portable Digital Audio Player and Recorder
PDA, Smartphone
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision
1
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93
AS3517 V17
Data Sheet, Confidential
USB
Host / OTG
Keys
LCD
AS3517
PMU = Voltage Supply + Supply Supervision + Power-up + Hibernation
Flash
SD-
RAM
MMC,
SD etc
HD
SPDIF Out
PWM Out
µController
De/Encoder
Application Processor
DRM ID
Reset & WD
RTC
OSC/PLL
I²S
2w Interface
Audio DAC
Headphone
Amplifier
Line
Outputs
Audio ADC
Microphone
Amplifier
still valid
FM-
Radio
DC/DCs - LDOs Charger
Voltage Supply
Digital Interface
Audio Signal
3V-5V Battery 5V Charger
Technical
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3517 V17
Data Sheet, Confidential
Figure 1 AS3517 Block Diagram
AG still valid
Technical
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3517 V17
Data Sheet, Confidential
Contents
Technical
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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1.0
1.1
1.2
1.3
AS3517 V17
Data Sheet, Confidential
Revision History
Revision Date Owner Description
Changed block diagram of DCDC15 12.10.2006 pkm
26.1.2007 pkm
6.4.2007 pkm
24.9.2008 pkm
Corrected some typos
Corrected block diagram (DAC mute)
Corrected start-up sequence (VPROG1 and VPROG2 exchange)
Added Typical Application Information
Changed chip version for V17
RTCT register reset corrected to RVDD-POR
USB & CHGIN 0ms de-bounce time changed to 8ms
Updated marking and ordering information
AG still valid
Technical
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3517 V17
Data Sheet, Confidential
6 Pinout and Packaging
Table 1 Pinlist CTBGA81
Ball PinName
G7 AGND
H7 AVDD
J9 AVSS
E2 BATTEMP
D3 BVDD
E3 BVDD
B8 BVDDH
A8 BVDDC1
A4 BVDDC2
B4 BVDDC3
F2 BVDDR
F1 CHG_IN
E1 CHG_OUT
C1 CN_GEXT
Type
Analog I/O
Supply
Supply
Analog I/O
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Analog Input
Analog Output
Digital output
Digital output
Digital input with pull up
Digital I/O with pull up
Analog Input
Analog Input
Function
Analog Reference Voltage (AVDD/2) buffer cap terminal
Analog Circuit VDD, connected to LDO1 on BGA substrate
Analog Circuit VSS
Charger Battery Temperature Sensor input (100kΩ NTC)
Positive (Battery) Supply Terminal, 5.5V max.
Positive (Battery) Supply Terminal, 5.5V max.
Positive (Battery) Supply Terminal of Headphone Amplifier, 5.5V max.
Positive (Battery) Supply Terminal of DCDC1, 5.5V max.
Positive (Battery) Supply Terminal of DCDC2, 5.5V max.
Positive (Battery) Supply Terminal of DCDC3, 5.5V max.
valid
RTC Positive (Battery) Supply terminal, 5.5V max
Charger Positive Supply Terminal, 5.5V max
USB charge pump CN of flying cap / Output to control USB-Host
DCDC N-Switch
AG
CVDD1 and Feedback pin
CVDD2 and Feedback Pin
still
C2 CP_CP
G3 CSCL
H3 CSDA
B7 CVDD1
B5 CVDD2
B3 CVDD3
A6 CVSS1
B6 CVSS2
A2 CVSS3
B2 CVSS15
G1 DVDD
J2 DVSS
H2 FVDD
F3 HBT
C8 HPCM
D9 HPGND
A9 HPL
C9 HPR
B1 ISINK
Analog I/O
Analog Output
Analog Output
Analog Output
D7 LIN1L
D6 LIN1R
F8 LIN2L
F7 LIN2R
Analog Input
Analog Input
Analog Input
Analog Input
C7 LOUT1L
C6 LOUT1R
D8 LOUT2L
Analog Output
Analog Output
E7 LOUT2R
G4 LRCLK
A7 LXC1
A5 LXC2
A3 LXC3
Analog Input
Supply
Supply
Supply
Supply
Supply
Supply
Supply
CVDD3 and Feedback Pin
CVDD1 StepDown Neg. Supply terminal
ams
Digital Circuit VDD, connected to LDO2 on BGA substrate
Digital Circuit VSS
Heartbeat Input for CPU supervision Digital input with pull down
Analog Output Headphone Common GND Output for DC-coupled speakers
Analog Output
Digital I/O with pull down
Digital output
Digital output
Digital output
Headphone Amplifier reference buffer cap terminal
Headphone Amplifier Output Left Channel
Headphone Amplifier Output Right Channel
DCDC15V Load Current Sink terminal (e.g. white LED)
Line Input 1 Left Channel
Line Input 1 Right Channel
Line Input 2 Left Channel
Line Input 2 Right Channel
Line Output Left Channel
Line Output Right Channel
Line Output Left Channel
Line Output Right Channel
I2S Left/Right Clock
CVDD1 StepUp switch output to coil
CVDD2 StepUp switch output to coil
CVDD3 StepUp switch output to coil
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3517 V17
Data Sheet, Confidential
Ball PinName Type Function
H9 MIC1N
G9 MIC1P
G8 MIC1S
E9 MIC2N
F9 MIC2P
E8 MIC2S
D2 PVDD1
Analog Input
Analog Input
Analog I/O
Analog Input
Analog Input
Analog I/O
Analog Output
Microphone Input 1N
Microphone Input 1P
Microphone Supply 1 (2.95V) / Remote Input 1
Microphone Input 2N
Microphone Input 2P
Microphone Supply 2 (2.95V) / Remote Input 2
LDO3 Regulator Output
D1 PVDD2
F6 PWGD
Analog Output
Digital I/O multiplexed
LDO4 Regulator Output
Power Good, SPDIF, PLL clock, PWM digital output.
Configurable as open drain or push pull.
Master CLK digital input (e.g. from CPU)
Power Up input J6 PWRUP Digital input with pull down
J4 Q24M
J3 Q32K
G2 RVDD
F4 SCLK
H4 SDI
G5 SDO
A1 SW15
Digital output multiplexed
Digital output multiplexed
Analog Output
Digital I/O with pull down
Digital input with pull down
Digital output
Analog Output
D4 USBH_CSN Analog Input
C4 USBH_CSP Analog Input
C5 USBH_PG
G6 VPRG1
H6 VPRG2
H8 VREF
C3 VBUS
B9 VSSH
J7 XIN24
H1 XIN32
H5 XIRQ
J8 XOUT24
Digital output
Analog Input
Analog Input
Analog I/O
Analog I/O
Supply
Analog I/O
Analog I/O
Digital output
Analog I/O
12-24MHz Clock output, PLL clock. Configurable as open drain or push pull.
32kHz Clock output, SPDIF, PLL clock, PWM. Configurable as open drain or push pull.
RTC Supply Regulator Output prog. to 1.0-2.5V
valid
I2S Shift Clock
I2S Data Input to DAC
I2S Data output from ADC
DCDC15V switch terminal
USB-Host Step Up neg. Current sense terminal to 100mΩ resistor
(BVDD)
AG still
Output to control USB-Host DCDC high Side P-Switch
5 State Prog Input to define power up sequence
5 State Prog Input to define default regulator voltages
Analog Reference ( filtered AVDD) decoupling cap terminal
ams
Interrupt Request Output. Configurable as open drain or push
24MHz Oscillator Crystal terminal
32kHz RTC Oscillator Crystal terminal J1 XOUT32 Analog I/O
J5 XRES Digital output open drain Reset Output
Technical
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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AS3517 V17
Data Sheet, Confidential
6.2.1 CTBGA81
Figure 2 Ball Assignment CTBGA81
1 2 3 4 5 6 7 8 9
B ISINK CVSS15 CVDD3 BVDDC3 CVDD2 CVSS2 CVDD1 BVDDH VSSH B
C CN_GEXT CP_CP VBUS USBH_CSP USBH_PG LOUT1R LOUT1L HPCM HPR C
D PVDD2 PVDD1 BVDD USBH_CSN
E CHG_OUT BATTEMP BVDD nc nc nc LOUT2R MIC2S MIC2N E valid
F CHG_IN BVDDR HBT SCLK nc PWGD LIN2R LIN2L MIC2P F
H XIN32 FVDD CSDA SDI
AG still
J XOUT32 DVSS Q32K Q24M XRES PWRUP XIN24 XOUT24 AVSS J
1 2 3 6 7 4 ams
5 content
8 9
Technical
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AS3517 V17
Data Sheet, Confidential
6.3.1 CTBGA81
Marking
Figure 3 CTBGA81 Marking
Table 2 Package Code AYWWZZZ
A Y WWW ZZZ
A … for PB free Year Working week assembly/packaging Free choice
Dimensions
Figure 4 CTBGA81 9x9mm 0.8mm pitch
AG still valid
Technical
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AS3517 V17
Data Sheet, Confidential
Device ID
AS3517H-ECTP
AS3517H-ECTS
Version Temperature Range
V17 -20 to +85 °C
V17 -20 to +85 °C
Package Type
CTBGA81; 9x9mm package size,
0.8mm ball pitch
CTBGA81; 9x9mm package size,
0.8mm ball pitch
Delivery Form
Tape & Reel
DryPack
Tray
DryPack
AG still valid
Technical
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AS3517 V17
Data Sheet, Confidential
8 Absolute Maximum Ratings (Non-Operating)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions.
Table 3 Absolute Maximum Ratings
Symbol
V
IN_5V
Parameter
5V pins
Min
-0.5
Max
7.0
Unit
V
T body
Package Body Temperature
Note
Applicable for pins BVDD, BVDDH,
BVDDC1, BVDDC2, BVDDC3, BVDDR,
CHG_IN, VBUS
Applicable for pin SW15 V
IN_SW15
15V pin -0.5 17 V
V
IN_VSS
Voltage difference at VSS terminals
V
IN_DVDD
3.3V pins with diode to DVDD
V
IN_xDVDD
V
IN_AVDD
3.3V pins with diode to AVDD
V
IN_REG
V
IN_RVDD pins with no diode to DVDD voltage regulator pins with diodes to BVDD voltage regulator pin with diode to BVDD
-0.5
-0.5
-0.5
-0.5
0.5
5.0
DVDD+0.5
7.0V
5.0
AVDD+0.5
V
V
V
V
AG
-0.5 3.6
BVDD+0.5
V
Applicable for pins CVSS3, CVSS15,
CVSS1, CVSS2, VSSH, AVSS, DVSS
Applicable for pins LRCK, SCLK, SDI,
VPRG1, VPRG2, BATTEMP, ISINK,
valid
XRES, PWGD, Q32K, Q24M, HBT
Applicable for pins
CSCL, CSDA, PWRUP
LOUT1L/R, LOUT2L/R, VREF, AGND,
LIN1L/R, LIN2L/R, MIC1P/N, MIC2P/N,
MIC1S, MIC2S
still
Applicable for pins AVDD, DVDD,
PVDD1/2, CVDD1/2/3, UVDD
Applicable for pins RVDD
V
IN_BVDD
I scr
ESD
P t
V Applicable for pins HPR/L, CHG_OUT pins with diode to BVDD
Input Current (latchup immunity)
Electrostatic Discharge HBM
Total Power Dissipation (all supplies and outputs)
-0.5
ams
7.0
BVDD+0.5
+/-1 kV
1000
Norm: JEDEC JESD22-A114C
content
amb
=70°C
Table 4 Soldering Conditions
Symbol Parameter Min Max Unit Note
260 °C Norm IPC/JEDEC J-STD-020C, reflects moisture sensitivity level only
235 245 °C T peak
D well
Solder Profile*
* austriamicrosystems AG strongly recommends to use underfill.
Technical
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Table 5 Operating conditions for supply voltages
Symbol Parameter Min Max Unit
3.0 5.5 V
BVDD, BVDDH, BVDDC1,
BVDDC2, BVDDC3, BVDDR
Note
DVDD
AVDD
Digital Supply Voltage
Analogue Supply Voltage
2.8
2.8
V
DELTA
Negative
Supplies
CVSS1, CVSS2, CVSS3,
CVSS15, VSSH, AVSS, DVSS
-0.1
V
DELTA
+ Difference of Positive Supplies -0.25
3.6
3.6
0.1
0.25
V
V
V
V
Digital Audio Supply Voltage (LDO2)
Analog Audio Supply Voltage (LDO1)
To achieve good performance, the negative supply terminals should be connected to low impedance ground
valid
plane.
AVDD-DVDD
Table 6 Electrical Specification of other function blocks
Symbol
V
POR_ON
V
POR_OFF
V
POR_HY f
LRCLK_WD t
ON_DELAY
V
DO_L
V
DO_H
I
PU
V
PWRUP_L
Parameter
Power-on Reset Activation
Level
Min Typ
AG
Unit
level when DVDD decreases
Power-on Reset Release
Level when DVDD increases
Power-on Hysterisis
LRCLK Frequency
Watchdog
Delay Time of pin PWRUP
Digital Output Driver
Capability (drive LOW)
Digital Output Driver
Capability (drive HIGH)
Internal Pull-up Current
2 4.1 8 kHz
ams
2.6
100
10 mV
0.3 ms
V
V
Minimum key press time
Pins XRES, XIRQ, push/pull mode only, SDO
PWGD @ 8mA, SDO
Pins XRES, XIRQ @ 8mA,
Source
Digital Input Level LOW,
BVDD>3V
V
V
PWRUP_H
PWRUP_H
Digital Input Level HIGH,
BVDD>3V
Digital Input Level HIGH,
BVDD<=3V
BVVD/3 V Pin
1 V PWRUP
R
PWRUP
V
DI_L
Internal Pull-down resistor
Digital Input Level LOW
360
DVDD/2
*0.3
0.42 k
Ω
V
Pin PWRUP
Pin HBT, SDI, SCLK,
MCLK, LRCK
V
DI_H
I
PD f
CLK
Digital Input Level HIGH 1.02 DVDD/2 source
Audio Clock Frequency
V Pin HBT, SDI, SCLK,
MCLK, LRCK
10 µA HBT
8
*0.7
48 kHz LRCK according to streamed audio data
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Data Sheet, Confidential
Table 7 Supply currents
Symbol
I
HPH
I
DAC->HP
I
Line->HP
Parameter
Headphone current from BVDDH
DAC playback current
Line Input playback current
Typ Max Unit Note
1 mA quiescent current, no load
6.4 mA no load, including PMU
1.9 mA no load, including PMU
Symbol
T amb
T j
Table 8 Temperature Range
Parameter
Operating temperature range
Junction temperature range
R th
Min Typ Max Unit Note
-20
0
25 85
110
°C
°C
39 For CTBGA81 package
valid
AG still
Technical
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Table 9 Audio Parameters
Symbol
Parameter
Min Typ Max
Unit Note
DAC Input to Line Output
FS
SNR
Full Scale Output
Signal to Noise Ratio
DR
THD
SINAD
Dynamic Range
0.97
91
88
-90
V
RMS dB dB dB
1kHz FS input
A-weighted, no load, silence input
A-weighted, no load,
-60dB FS 1kHz input
1kHz FS input
A-weighted, input
Total Harmonic Distortion
Signal to Noise and
Distortion
Line Input to Line Output
FS
SNR
Full Scale Output
Signal to Noise Ratio
SINAD
DAC Input to HP Output
FS Full Scale Output
SNR
DR
SINAD
Signal to Noise and
Distortion
Signal to Noise Ratio
Dynamic Range
Signal to Noise and
Distortion
0.96
92
V
RMS dB
1kHz 1V
RMS
(FS) input
A-weighted, no load, silence input
valid
A-weighted, input
89 dB
0.895 V
RMS
94
90
-95
AG
RMS dB dB dB
R
R
L
L
= 32
= 16
still
silence input
A-weighted, no load,
-60dB FS 1kHz input no load, 1kHz FS input
-75 dB
L
= 32
Ω,
ams
f=1kHz FS input
-60 dB
L
= 16
Ω, f=1kHz FS input
A-weighted, 1kHz
FS input
R
L
= 32 Ω, f=1kHz FS input
R
L
= 16
Ω, f=1kHz FS input
74 dB Ω
68 dB Ω
Line Input to HP Output
FS
SNR
Full Scale Output
Signal to Noise Ratio
0.875 V
RMS
0.87 V
RMS
95 dB
R
L
= 32
Ω, 1kHz 1V
RMS
(FS) input
R
L
= 16
Ω, 1kHz 1V
RMS
(FS) input
A-weighted, no load, silence input
DR Dynamic Range
Technical
95
-91 dB dB
A-weighted, no load,
-60dB FS 1kHz (FS) input no load, 1kHz 1V
RMS input
-75 dB Ω, 1kHz
1V
RMS
(FS) input
-60 dB Ω, 1kHz
1V
RMS
(FS) input
SINAD Signal to Noise and
Distortion
A-weighted, 1kHz
1V
RMS input
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Symbol
Parameter
MIC Input to Line Output
FS
SNR
Full Scale Output
Signal to Noise Ratio
DR Dynamic Range
SINAD Signal to Noise and
Distortion
Line Input to ADC Output
SNR Signal to Noise Ratio
DR Dynamic Range
SINAD Signal to Noise and
Distortion
Min Typ Max
Unit Note
R=32
Ω, 1kHz 1V
RMS
(FS) input
R=16
Ω, 1kHz 1V
RMS
(FS) input
75 dB Ω
70 dB Ω
0.97
81
83
90
90
AG
dB
V
RMS dB dB dB
1kHz FS input
A-weighted, no load, silence input
A-weighted, no load,
-60dB FS 1kHz input
1kHz (-3dB FS) input
A-weighted,
RMS
(-3dB FS) input
valid
input
A-weighted, no load, silence input
still
A-weighted, (-
3dB FS) input
Technical
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9 Detailed Functional Description
9.1.1 Audio Line Inputs (2x)
General
The chip features includes two identical line inputs. The blocks can work in mono differential, 2x mono single ended or in stereo single ended mode.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each and MUTE. The gain can be set from –34.5dB to +12dB. The stage is set to mute by default. If the line input is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input.
Figure 5 Line Inputs
Stereo Mode
AG
Mono Single Ended Mode
ams content still valid
Mono Differential Mode
Technical
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Parameter
Table 10 Line Input Parameter
Symbol Parameter Min Typ Max Unit Note
V
LIN
R
LIN
Δ
RLIN
C
LIN
A
LIN
Input Signal Level
Input Impedance Tolerance
1.0 V
PEAK
Pls observe gain settings.
Max. peak levels at any node within the circuit shall not exceed AVDD
20-100 kΩ depending on gain setting
±15 %
5 pF
-34.5 +12 dB Programmable Gain
1.5 dB discrete logarithmic gain
A
LINMUTE
Gain Step Accuracy
Mute Attenuation
Register Description
BVDD = 3.3V, T
A
= 25 o C, fs=48kHz unless otherwise mentioned
±0.25
100 dB dB steps
Table 11 Line Input Related Register
Name
LINE_IN1_R
LINE_IN1_L
LINE_IN2_R
LINE_IN2_L
AudioSet_1
AudioSet_3
Base
2-wire serial
2-wire serial
2-wire serial
2-wire serial
2-wire serial
2-wire serial
Offset Description
0Ah
0Bh
0Ch
0Dh
14h
16h
Right Line Input 1 settings
AG
Enable/disable mixer input
still
Line Inputs have to be enabled in register 14h first before other settings in register 0Ah to 0Dh can be programmed.
valid
Technical
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9.1.2 Microphone Inputs (2x)
General
The AFE offers two microphone inputs and 2 low noise microphone voltage supply (microphone bias), voice activation, microphone connect detection and push button remote control.
Figure 6 Microphone Input
Microphone Preamplifier and Gain Stage
Gain Stage & Limiter
a microphone register bit.
still valid
gain steps and MUTE. All gains and MUTE are independently programmable. The gain can be set from –40.5dB to +6dB.
The stage is set to mute by default. If the microphone input is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input.
Supply & Detection
Each microphone input generates a supply voltage of 1.5V above HPHCM. The supply is designed for
≤2mA and has a 10mA current limit. In OFF mode the MICS terminal is pulled to AVDD with 30kOhm. A current of typically 50uA generates an interrupt to inform the
Remote Control
ams
CPU, that a circuit is connected. When using HPCM as headset ground the HP–stage gives the interrupt. After enabling the HP-stage through the CPU the microphone detection interrupt will follow.
content
Fast changes of the supply current of typically 500uA are detected as a remote button press, and an interrupt is generated. Then the CPU can start the measurement of the microphone supply current with the internal 10-bit ADC to distinguish which button was pressed. As the current measurement is done via an internal resistor, only two buttons generating a current of about 0.5mA and 1mA can be detected.
With this 1mA as microphone bias is still available.
Voice Activation
Further a built-in voice activation comparator can actuate an interrupt if microphone input voltage of about 5mVRMS is detected.
Technical
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Parameter
Table 12 Microphone Inputs Parameter
Symbol Parameter Min Typ Max Unit Note
V
MICIN
0
V
MICIN
1
V
MICIN
2
R
MICIN
Δ
MICIN
Input Impedance Tolerance
C
MICIN
A
MICPRE
Microphone Preamplifier Gain
40
PEAK
A
MICPRE
= 28dB; A
MIC
= 0dB
20
PEAK
A
MICPRE
= 34dB; A
MIC
= 0dB
10
PEAK
A
MICPRE
= 40dB; A
MIC
= 0dB
15 kΩ
±15 %
MICP, MICN to AGND
5 pF
28
34
40 dB dB selectable (fixed) gain settings
A
MIC
V
MICLIMIT
A
MICLIMIT t
ATTACK t
DECAY
A
MICMUTE
V
MICSUP
I
MICMAX
V
NOISE
Max. Microphone Supply
Current dB dB
Programmable Gain
Gain Step Precision
Limiter Gain Overdrive
Limiter Decay Time
Mute Attenuation
Microphone Supply Voltage
-40.5
Activation V
PEAK
±0.25
15*2 dB dB discrete logarithmic gain steps
valid
120
100
2.9
AG
dB
V ms/6dB
still
need a bias current of
0.5mA-1mA
5 µV Microphone Supply Voltage
Noise
+6
1.5
I
MICDET
I
REMDET
Microphone Detection
Current
Max. Remote Detection
Current
BVDD = 3.3V, T
A
= 25 o C unless otherwise mentioned
50 µA
ams
Register Description
Table 13 Microphone Related Register
content
Offset Description
Right Microphone Input 1 volume settings, AGC control 06h
Name
MIC1_R
Base
2-wire serial
MIC1_L
MIC2_R
MIC2_L
AudioSet_1
AudioSet_3
IRQ_ENRD_1
IRQ_ENRD_3
IRQ_ENRD_4
2-wire serial
2-wire serial
2-wire serial
2-wire serial
2-wire serial
2-wire serial
2-wire serial
2-wire serial
07h
08h
09h
14h
16h
24h
26h
27h
Left Microphone Input 1 volume settings, MIC 1 supply control
Right Microphone Input 2 volume settings, AGC control
Left Microphone Input 2 volume settings, MIC 2 supply control
Enable/disable driver stage
Enable/disable mixer input
Interrupt settings for microphone voice activation
Interrupt settings for microphone detection
Interrupt settings for remote button press detection
Microphone inputs have to be enabled in register 14h first before other settings in register 06h to 09h can be programmed.
Technical
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9.1.3 Audio Line Outputs (2x)
General
The line outputs are designed to provide the audio signal with typical 1V
PEAK
at a load of minimum 10k Ω, which is a minimum value for line inputs. If the limiters (N20/N21) are deactivated the peak output voltage is 1.45V
PEAK
. The load however can decrease to 64Ohm. In addition these line output can be configured as mono differential to drive 1V
PEAK
@ 32
Ω load (e.g. an earpiece of a mobile phone).
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from
-40.5dB to +6dB. A zero cross detection allows to control the actual execution of new gain settings.
If the line output is not enabled, the volume settings are set to their default values. Changing of volume and mute control can only be done after enabling the output.
If using the output in mono differential mode, the volume setting for the right channel should be set to 0dB.
Figure 7 Line Output
Stereo Mode
AG still
Mono Differential Mode (please observe that gain of right channel amplifier has to best to 0dB)
valid
Parameter
Table 14 Line Output Characteristics
Symbol
R
L_LO
C
L_LO
A
LO
Parameter
Load Impedance
(Stereo Mode)
Load Capacitance
(Stereo Mode)
Programmable Gain
A
LOMUTE
Gain Step Accuracy
Mute Attenuation
BVDD = 3.3V, T
A
= 25 o
C unless otherwise mentioned
Note
-40.5
Typ Max Unit content
+6
1.5 dB dB line inputs nominally have
10kΩ discrete logarithmic gain steps
±0.25
100 dB dB
Register Description
Table 15 Line Output Related Register
Name
LINE_OUT1_R
LINE_OUT1_L
LINE_OUT2_R
Base
2-wire serial
2-wire serial
2-wire serial
Offset Description
00h
01h
04h
Right Line Output 1 volume settings, MUX control
Left Line Output 1 volume settings
Right Line Output 2 volume settings, MUX control
LINE_OUT2_L
AudioSet_1
AudioSet_3
2-wire serial
2-wire serial
2-wire serial
05h
14h
16h
Left Line Output 2 volume settings
Enable/disable driver stage
Enable/disable mixer input
Line output have to be enabled in register 14h first before other settings in register 00h and 01h can be programmed.
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General
The headphone output is designed to provide the audio signal with 2x40mW @ 16 Ω or 2x20mW @32Ω, which are typical values for headphones. If the limiters (N20/N21) are disabled a maximum output of 2x60mW@16Ω or 2x30mW@32Ω can be achieved.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
43.43dB to +1.07dB. A zero cross detection allows to control the actual execution of new gain settings.
Figure 8 Headphone Output
still valid
Headphones connected via decoupling capacitors
(Common Mode)
Phantom Ground
There are 2 ways to connect a headphone to the AFE. In order to spare the bulky ac/dc decoupling capacitors at pins HPR/HPL a buffered ground (Phantom Ground) is provided. This Common Mode Buffer needs to be switched on if utilized. If form factor considerations are less stringent, the headphones can be conventionally connected via 2x100µF capacitors.
No-Pop Function
content
observe that pin HPGND is a high impedance node which must not be connected to any other external device than the 100nF buffer capacitor. To avoid Pop-Click noise one has to wait for 150ms in between a power-down (switch-off) and a power-up (switch-on) of the headphone amplifier.
The output is automatically set to mute when the output stage is disabled.
Figure 9 HP POP-Click Suppression
HPGND [V]
AGND
Technical
70ms
MUTE OFF
Operation
HP Amps powered down
70ms t
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Over-current Protection
The headphone amplifier has an over-current protection (e.g. HPR/HPL is shorted). This over-current protection will power the headphone amplifier down for a programmable timeout period (512ms, 256ms, 128ms). The current threshold is at 150mA for HPR/HPL and 300mA for HPCM. There is a corresponding interrupt available to be enabled.
Headphone Detection
When the headphone amplifier is powered down, one can detect the connection of a headset. It only work if the headset is connected between pins HPR/HPL and HPCM. As long as the headphone amplifier is powered down, HPCM is biased to 150mV and acting as the sense pin. There is a corresponding interrupt available to be enabled.
Power Save Options
To save power, especially when driving 32 Ohm loads, a reduction of the bias current can be selected. Together with switching off the phantom ground this gives 4 possible operating modes.
Table 16 Headphone Power-Save Options
BVDD = 3.3V, T
A
= 25 o C unless otherwise mentioned
P
HP
A
LO
HPCM_OFF IBR_HPH IDD_HPH (typ.)
Parameter
Table 17 Power Amplifier Block Characteristics
Symbol
R
L_HP
C
L_LO
P
HP_MAX
Parameter
Load Impedance
Load Capacitance
Nominal Output Power
Max. Output Power
Programmable Gain
Gain Step Accuracy
Min
16
Load
Typ
AG
40mW
100
Unit
pF
still
Note
stereo mode
RL=16Ω, limiter enabled
ams
20mW
60mW
30mW
RL=32Ω, limiter enabled
RL=16Ω
RL=32Ω
+1
1.5
±0.25
300 dB dB dB mA discrete logarithmic gain steps
HPCM pin
valid
P
SRRHP
Power Supply Rejection Ratio 90 dB 200Hz-20kHz, 720mVpp,
RL=16Ω
A
LOMUTE
Mute Attenuation 100 dB
BVDD = 3.3V, T
A
= 25 o C unless otherwise mentioned
Register Description
Table 18 Headphone Related Register
Name Base
HPH_OUT_R 2-wire serial
Offset Description
02h
HPH_OUT_L
AudioSet_3
IRQ_ENRD_3
2-wire serial
2-wire serial
2-wire serial
03h
16h
26h
Right HP Output volume and over-current settings
Left HP Output volume settings, enable and detection control
Power save options, common mode buffer
Interrupt settings for over current and HP detection
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9.1.5 DAC, ADC and I2S Digital Audio Interface
Input
The AFE receives serialized audio data for the DAC via pin SDI. The output of the DAC is fed through a volume control to the mixer stage and to the multiplexers of line output and headphone amplifiers.
This serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one bit-stream. Via pin
LRCLK the alignment clock is input to the DAC digital filters. LRCLK (Left Right Clock) indicates whether the serial bit-stream received via pin SDI, represents right channel or left channel audio data. Via pin SCLK the bit clock for the serial bit-stream is signalled. SDI and
LRCLK are synchronous with SCLK. SDI is an inputs; LRCLK and SCLK are either inputs or outputs depending on the master/slave operation mode. SDO is not used.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
Output
This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a volume control to the 20 bit ADC. The digital output is done via an I2S interface.
The AFE sends serialized audio data from the ADC via pin SDO. This serialized audio data is a digital audio data stream with the left and
valid
the right audio channels multiplexed into one bit-stream. Via pin LRCLK the alignment clock is signalled to the connected devices (e.g.
CPU). LRCLK (Left Right Clock) indicates whether the serial bit-stream sent via pin SDI, presents right channel or left channel audio data.
Via pin SCLK the bit clock for the serial bit-stream is signalled. SDO and LRCLK are synchronous with SCLK. SDO is an output; LRCLK and SCLK are either inputs or outputs depending on the master/slave operation mode. SDI is not used.
still
The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate.
I2S Modes
The AFE can be operated either in Master Mode, Slave Mode or additionally in Slave Mode with the master clock directly signalled via pin
PWGD (pin PWGD is multiplexed for I2S Direct Mode). The difference between Master and Slave Mode is whether the AFE or the externally attached decoder/encoder device is generating the interface clocks. The master clock (MCLK) is the necessary internal over-
Due to the internal structure left and right audio samples are exchanged in I2S Direct Mode.
In Slave Mode the PLL generates the master clock based on LRCLK. Thus the PLL needs to be preset to the expected sampling frequency. The ranges are 8kS-12kS (8kHz-12kHz) and 16kS-48kS (16kHz-48kHz). Please refer to register 0x1Dh.
Table 19 I2S Modes
content
Master Mode
Technical
Slave Mode, internal PLL of the AFE generates MCLK
Slave Mode with I2S direct, the master clock is signalled
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Power Save Options
The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption.
Clock Supervision
The digital audio interface automatically checks the LRCLK. An interrupt can be generated when the state of the LRCLK input changes. A bit in the interrupt register represents the actual state (present or not present) of the LRCLK.
Signal Description
The digital audio interface uses the standard I2S format:
• left justified
• MSB first
• one additional leading bit
The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than
18 bits sampled, the data sample is completed with “0”s. In I2S direct mode the data length has to be minimum 18 bits.
The ADC output is always 20 bit. If more SCLK pulses are provided, only the first 20 will be significant. All following bits will be “0”.
SCLK has not to be necessarily synchronous to LRCLK but the high going edge has to be separate from LRCLK edges. The LRCK signal has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always in correct phase lock condition to the external LRCLK.
valid
Please observe that in slave mode LRCLK has to be activated before enabling the ADC.
In Master Mode operation SCLK has 32 clock cycles for each sample word.
SCLK
=
MCLK
4
=
LRCLK
4
*
AG
LRCK
* 64
still
Sample Rates
frequencies from 8kHz to 48kHz can be selected. For certain division ratios between master clock and sample ratio a certain deviation is system inherent.
LRCLK
=
f
OSC
1
*
(
PLLMode
+
1 ) * 2
*
RD
+
f
osc
..........
PLLMode
......
......
Quarzoscil lator
PLL factor
RD
..........
.......
RateDivide r frequency
( 1 , 2 )
( 0
−
511 )
Technical
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Table 20Table 21 I2S Master clock PLL settings
f
OSC fsample (LRCK)
24MHz 48.00kS
24MHz 44.10kS
24MHz 32.00kS
24MHz 24.00kS
24MHz 22.05kS
24MHz 16.00kS
24MHz 12.00kS
24MHz 11.025kS
24MHz 8.00kS
PLL-Mode RD (Rate Divider)
1
1
1
1
1
1
2
2
2
123
134
Deviation
0.00%
0.04%
186 -0.27%
248
270
0.00%
0.04%
373
248
0.00%
0.00%
270 0.04%
373 0.00%
fsample (LRCK) PLL-Mode RD (Rate Divider) Deviation f
OSC
16MHz 48.00kS 1 81 0.40%
16MHz 44.10kS
16MHz 32.00kS
16MHz 24.00kS
16MHz 22.05kS
16MHz 16.00kS
16MHz 12.00kS
16MHz 11.025kS
16MHz 8.00kS
f
OSC fsample (LRCK)
12MHz 48.00kS
12MHz 44.10kS
12MHz 32.00kS
12MHz 24.00kS
12MHz 22.05kS
12MHz 16.00kS
1
1
1
1
1
2
2
2
PLL-Mode
179 0.22%
248 0.00%
RD (Rate Divider)
1
AG
1
179 -0.33%
123
165
179
248
valid
165 -0.20%
61
66
92
123
134
185
still
0.27%
0.00%
0.04%
0.27%
12MHz 12.00kS 2 123 0.00%
0.04% 12MHz 11.025kS
12MHz 8.00kS
Parameter
2
ams
Figure 10 I2S Left Justified Mode
134
185 0.27%
content
Technical
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Figure 11 I2S Timing
Table 22 Audio Converter Parameter
Symbol
t
SCLK t
SCLKH t
SCLKL
T
LRSU
T
LRHD t
SDSU t
SDHD t
SDOD
Parameter
SCLK Cycle Time
SCLK Pulse Width High
SCLK Pulse Width Low
LRCLK Setup Time before
SCLK rising edge
LRCLK Hold Time after SCLK rising edge
SDI setup time before SCLK rising edge
SDI hold time after SCLK rising edge
SDO Delay from SCLK falling edge
Min
160
80
80
Typ Max Unit
ns ns ns
80 ns
Note
80 ns
-20
25 ns
AG
20 ns
still
internal PLL generates
valid
t
JITTER
Jitter of LRCLK
I2S Direct mode
T
SCD
T
LRD
SCLK delay after MCLK rising edge
LRLCK delay after SCLK rising edge
ams
MCLK from LRCLK t
SDSU t
SDHD
SDI setup time before SCLK rising edge
SDI hold time after SCLK
0.5 1.5 ns
content
t
SDOD rising edge
SDO Delay from SCLK falling edge
V
I2SH
V
I2SL
V
SDOH
V
SDOL
SCLK, LRCLK, SDI, MCLK
High Input Level
SCLK, LRCLK, SDI, MCLK
Low Input Level
SDO High Output Level
SDO Low Output Level
2.6
0.3
V
I2SOH
SCLK, LRCLK, High Output 2.6
V
I2SOL
Level
Technical
0.3
BVDD=3.3V, T
A
=25°C, Slave Mode, f
S
=48kHz, MCLK = 256*f
S, unless otherwise specified
V
V
V
V at 2mA at 2mA at 8mA master mode only at 8mA master mode only
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Register Description
Table 23 Audio Converter Related Register
Name Base Offset Description
DAC_L
ADC_R
ADC_L
I2S
2-wire serial
2-wire serial
2-wire serial
2-wire serial
0Fh
10h
11h
1Eh
DAC input volume settings
ADC output volume settings, source multiplexer settings
ADC output volume settings
I2S master mode settings
I2S_PLL_OSC 2-wire serial 1Dh I2S master mode and PLL settings
AudioSet_1 2-wire 14h
AudioSet_2 2-wire serial 15h Enable/disable DAC and power save options
AudioSet_3 2-wire serial 16h Enable/disable mixer input
IRQ_ENRD_1 2-wire serial 25h Interrupt settings for LRCK changes
DAC and ADC have to be enabled in register 14h first before other settings in register 0Eh to 11h can be programmed.
AG still valid
Technical
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9.1.6 Audio Output Mixer
General
The mixer stage sums up the audio signals of the following stages
• Microphone Input 1 & 2 (stereo microphone)
• Line Input 1
• Line Input 2
• Digital Audio Input (DAC)
The mixing ratios have to be with the volume registers of the corresponding input stages. Please be sure that the input signals of the mixer stage are not higher than 1Vp. If summing up several signals, each individual signal has of course to be accordingly lower. This shall insure that the output signal is also not higher than 1Vp to get a proper signal for the output amplifier.
This stage features an automatic gain control (AGC), which automatically avoids clipping.
Register Description
Audio Mixer Related Register
Name
AudioSet_2
AudioSet_3
Base
2-wire serial
2-wire serial
Offset Description
15h
16h
Enable/disable mixer stage and AGC
Enable/disable DAC, MIC or Line Inputs to mixer stage
AG still valid
Technical
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9.1.7 2-Wire-Serial Control Interface
General
There is an I2C slave block implemented to have access to 64 byte of setting information.
The I2C address is: Adr_Group8 - audio processors
• 8Ch_write
• 8Dh_read
Protocol
Table 24 I2C Symbol Definitions
Symbol Definition R/W (AS3517 Slave) Note
S
DW
DR
A Acknowledge
N reg_data data (n)
WA++
Figure 12 Byte Write
Start condition after stop
Device address for write
Device address for read
No Acknowledge
Register data/write
Register data/read
Increment word address internally
AS3517 (=slave) receives data
AS3517 (=slave) transmits data
R
R
R
R
1 bit
R 1
1000 1100b (8Ch)
1000 1101b 8Dh)
R 8
1 bit
valid
R
W
AG
R
R
8 bit
8 bit
still
Figure 13 Page Write
ams content
Byte Write and Page Write formats are used to write data to the slave.
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally.
Technical
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Figure 14 Random Read
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
Figure 15 Sequential Read
valid
to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behaviour of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
Figure 16 Current Address Read
ams
To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition.
Technical
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Parameter
Figure 17 I2C timing
Table 25 I2C Operating Conditions
Symbol
V
CSL
V
CSH
HYST
V
OL
T
H
T
L
T
SU
T
HD
Parameter
CSCL, CSDA Low Input Level
Min
0
CSCL, CSDA High Input Level 2.03
CSCL, CSDA Input Hysteresis
CSDA Low Output Level
Clock high time
Clock low time
200
-
500
500
250
0
Typ
-
-
450
-
-
-
Max
0.87
5.5
800
0.4
AG
-
-
Unit
V
V
V ns ns ns ns mV
70%DVDD)
Notes
(max 30%DVDD)
CSCL, CSDA (min at 3mA
still
before rising edge of CSCL
No hold time needed for
valid
CSDA relative to rising edge of CSCL
TS
T
PD
DVDD =2.9V, T amb
=25ºC; unless otherwise specified
200
ams
-
50
- ns ns
content
CSDA H hold time relative to
CSDA edge for start/stop/rep_start
CSDA prop delay relative to lowgoing edge of CSCL
Technical
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9.2 Power Management Functions
9.2.1 Low Drop Out Regulators
General
These LDO’s are designed to supply sensitive analogue circuits, audio devices, AD and DA converters, micro-controller and other peripheral devices.The design is optimised to deliver the best compromise between quiescent current and regulator performance for battery powered devices.
Stability is guaranteed with ceramic output capacitors of 1μF +/-20% (X5R) or 2.2μF +100/-50% (Z5U). The low ESR of these caps ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output.
The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance.
Figure 18 LDO Block Diagram
AG still valid
LDO1
This LDO generates the analog supply voltage used for the AFE itself.
• Input voltage is BVDD
• Output voltage is AVDD (typ. 2.9V)
• Driver strength: 200mA
It is set to a fixed output voltage of 2.9V, 200mA max
. It supplies the analog part of the AFE. Additional external loads are possible but most not exceed the supply ratings in total together with the operating internal blocks. Further the external load must not induce noise to the sensitive AVDD supply pin.
content
LDO2
This LDO generates the digital supply voltage used for the AFE itself.
• Input Voltage is BVDD
• Output Voltage is DVDD (typ. 2.9V)
• Driver strength: 200mA
It is set to a fixed output voltage of 2.9V, 200mA max
. It supplies the digital part of the AFE. Additional external loads are possible but most not exceed the supply ratings in total together with the operating internal blocks. Further the external load must not induce noise to the
DVDD supply pin but is not as critical as AVDD.
These LDO can used to generate the periphery voltage for the digital processor or other external components (e.g. ext. DAC, USB-PHY,
SD-Cards, NAND-Flashes, FM-Tuner …)
• Input Voltage BVDD
• Output Voltage is PVDD1 & PVDD2 (1.2 to 3.5V)
• Default value at start-up is defined by VPROG1 and VPROG2 pins
• Driver strength: 200mA
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Parameter
Table 26 LDOs Block Characteristics
Symbol
R
ON
Parameter
On resistance
PSRR Power supply rejection ratio
I
OFF
I
VDD
Shut down current
Noise Output t start
V out_tol
Startup time
Output voltage tolerance
Min Typ
100
Max
1
Unit
Ω nA
Notes
50 μV rms
10Hz < f < 100kHz
-50
200
50
μs mV
V
LineReg
V
LoadReg
Line regulation
Load regulation
I
LIMIT
Current limitation 400
BVDD=4V; I
LOAD
=150mA; T amb
=25ºC; C
LOAD
=2.2μF (Ceramic); unless otherwise specified
Figure 19 Typical Performance Characteristics
Load regulation Output noise
AG
t r
=10μs t r
=10μs mA LDO1, LDO2, LDO3, LDO4
valid still ams
transient load: 1mA – 100mA
Output load: 150mA slope: 1μs
Technical
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Load Regulation Load Regulation output load: 10mA transient input voltage ripple: 500mV
Register Description
Table 27 LDO Related Register
Name
PMU PVDD1
PMU PVDD2
PMU ENABLE
Base
2-wire serial
2-wire serial
2-wire serial
Offset
17h-1
17h-2
18h
AG
output load: 150mA transient input voltage ripple: 500mV
valid
Technical
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9.2.2 DCDC Step-Down Converter (3x)
General
These converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage requirements for microprocessors.
• Input Voltage BVDDC1, BVDDC2 & BVDDC3 (usually connected to the battery)
• Output Voltage CVDD1, CVDD2 & CVDD3
• output voltage levels can be programmed independently form 0.65V to 3.4V
• the default value at start-up is defined by VPROG1 and VPROG2 pins
• driver strength 250mA (500mA for DCDC 3)
Figure 20 DCDC Step-Down Block Diagram
still valid
Functional Description
The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches efficiency up to 97% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of 250mA, with an output capacitor of only 10
μF. The implemented current limitation protects the DCDC and the coil during overload condition.
To achieve optimised performance in different applications, adjustable settings allow to compromise between high efficiency and low input, output ripple:
Technical
very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. Especially in the case of an inverted coil current the regulator will not operate in pulse skip mode.
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Figure 21 –DCDC buck with disabled current force / pulse skip mode
1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage
High efficiency operation:
In this mode there is a minimum coil current necessary before switching off the PMOS. As result, fewer pulses at low output loads are necessary, and therefore the efficiency at low output load is increased. On the other hand the output voltage ripple increases, and the noisy pulse skip operation is on up to a higher output current.
Figure 22 –DCDC buck with enabled current force / pulse skip mode
AG still valid ams
1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage
It’s also possible to switch between these two modes dynamically during operation:
100% PMOS ON mode for low dropout regulation:
For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO mode. This feature is enabled if the output voltage drops by more than 4%.
Technical
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Typ Max
5.5
3.4
50
Unit
V
V mV
BVDD
Notes
AS3517 V17
Data Sheet, Confidential
Parameter
Table 28 DCDC Buck Typical Performance Parameter
Symbol
V
IN
V
OUT
V
OUT_tol
Parameter
Input voltage
Regulated output voltage
Output voltage tolerance
Min
3.0
0.65
-50
I
LOAD
Maximum Load current
I
LIMIT
Current limit f
SW f
SWsc
C out
V
LineReg
Switching frequency
Switching frequency
Output capacitor
Line regulation
1.2
0.6
10
BVDD=3.0V; DCDC 1&2
R
PSW
R
NSW
P-Switch ON resistance
N-Switch ON resistance
Lx Inductor 3.3 4.7
η eff
I
VDD t
MIN_ON
Current consumption
Minimum on time
Vout=3.0V ns ns
μA
still
t
MIN_OFF
Minimum off time
220
100
0.1
80
40
10
AG
μF
MHz
BVDD=3.0V; DCDC 3
BVDD=3.0V; DCDC 1&2
BVDD=3.0V; DCDC 3
MHz in shortcut case
Ceramic, +/- 10% tolerance
valid
mV Transient; Slope: t r
=10μs,
100mV step, 200mA load
V
LoadReg
BVDD=3.6V; T amb
Load regulation
ams
Figure 23 DCDC Step-down Performance Characteristics
50 mV Transient; Slope: t r
=10μs,
content
100mA step
Technical
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AG ams content still valid
Register Description
Table 29 DCDC Buck Related Register
Name
Technical
Description
CVDD1 (DCDC1) control and voltage settings
CVDD2 (DCDC2) control and voltage settings
PMU CVDD3
PMU ENABLE
2-wire serial
2-wire serial
17h-5
18h
CVDD2 (DCDC2) control and voltage settings
Enables writings to extended registers 17h-3, 17h-4
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9.2.3 Charger
General
This block can be used to charge a 4V Li-Io accumulator. It supports constant current and constant voltage charging modes with adjustable charging currents (50 to 400mA) and maximum charging voltage (3.9 to 4.25V).
Figure 24 Charger States
still valid
AG
Trickle Charge
If BVDD is below 3V in systems where the battery is not separated from BVDD, the charger goes automatically in trickle charge mode with
content
If the battery (CHGOUT) voltage is below 2.9V the charging current cannot be set higher than 50mA, also when using a battery separation circuit to supply the AFE (BVDD) from USB or another voltage source.
Temperature Supervision
This charger block also features a 15uA supply for an external 100k NTC resistor to measure the battery temperature while charging. If the temperature is too high (>45°C), an interrupt can be generated. If the battery temperature drops below 42°C the charger will start charging again. The temperature supervision is not enabled in trickle charge mode.
If the NTC resistor does not have 100kΩ its value can be corrected with a resistor in series or in parallel.
Technical
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Parameter
Table 30 Charger Parameter
Min
37
Typ Max Unit
68 111
Notes
mA BVDD<=3V, CHGIN = 5.5V
Symbol Parameter
I
CHG_trick
Charging Current
(trickle charge)
V
CHG_trick
Charger Endpoint Voltage (trickle charge)
I
CHG
(0-7) Charging
V
CHG
(0-7) Charging Voltage
0.70*
CHGIN
I
NOM
-20%
V
NOM
-50mV
0.72*
CHGIN
I
NOM
V
NOM
0.74*
CHGIN
I
NOM
+20%
V
NOM
+30mV
4.0
V BVDD<=3V, CHGIN = 4.4V mA BVDD > 3V
V BVDD > 3V, end of charge is true
V
ON_ABS
Charger On Voltage IRQ 3.1 V BVDD = 3V
V
ON_REL
Charger On Voltage IRQ
V
OFF_REL
Charger Off Voltage IRQ
V
BATEMP_ON
Battery Temp. high level (45°C)
I
CHG_OFF
End Of Charge current level
I
REV_OFF
Reverse current shut down
BVDD=3.6V; T amb
=25ºC; unless otherwise specified
Register Description
Table 31 Charger Related Register
40
5%
I
NOM
170
77
610
10%
I
NOM
<1
240
15%
I
NOM mV CHGIN-CHGOUT mV CHGIN-CHGOUT mV BVDD >3V
V
BATEMP_OFF
Battery Temp. low level (42°C) 700 mV >3V uA BVDD = 5V, CHGIN open
still valid
Name
CHARGER
Base
2-wire serial
Offset
AG
22h
25h
Charger voltage, current and temp. supervision control
Enable/disable EOC and battery over-temperature interrupt IRQ_ENRD_2 2-wire serial
Read out charger status
content
Technical
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9.2.4 15V Step-Up Converter
General
The integrated Step-Up DC/DC Converter is a high efficiency current-mode PWM regulator, providing an output voltage up to 15V. A constant switching-frequency results in a low noise on supply and output voltages. When using an additional transistor the output voltage can be up to 25V to drive 6 white LED in series.
It has an adjustable sink current (1.25 to 37.5mA) to provide e.g. dimming function when driving white LEDs as back-light.
Figure 25 DCDC15 Block Diagram
AG still
Parameter
Table 32 15V Step-Up Converter Parameter
Symbol
V
SW
I
VDD
Parameter
High Voltage Pin
Quiescent Current
ams
V
FB
Feedback Voltage, Transient 0
Typ Max Unit
140
15
5.5
V Pin SW15
V Pin ISINK
Notes
µA Pulse Skipping mode
V
FB
Feedback Voltage, during
Regulation
Current Limit I
SW_MAX
350 510 750 mA V15_ON = 1
R
SW
I
LOAD
V
PULSESKIP
F
IN
Switch Resistance
Load Current
Pulse-skip Threshold
Fixed Switching Frequency
0
1.2
0.5
0.85
1.33
0.55
1.54
45
Ω V15_ON = 0 mA @ 15V output voltage
1.5 V Voltage at pin ISINK, pulse skips are introduces when load current becomes too low.
0.6 MHz
C
OUT
Output 1
I
LOAD
> 20mA
L (Inductor) t
MIN_ON
MDC Maximum
BVDD=3.6V; T amb
I
LOAD
< 20mA
Minimum On-Time
Technical
8
90
17 22
10
27
27
180
µH Use inductors with small C
PARASITIC
(<100pF) for high efficency ns Guaranteed per design
valid
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Figure 26 15V Step-Up Performance Characteristics
80
75
70
65
60
55
50
1
Efficiency vs Output Current
100
95
V
IN
=3,6V
Load: 3 LED's
90
85
DCDC stepup
Current controlled 0..15V
10
OUTPUT CURRENT [mA]
100
Register Description
Table 33 15V Step-Up Related Register
Name Base Offset Description
AG still valid
Technical
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9.2.5 USB VBUS Supply
The VBUS voltage converter consists out of a charge pump and a DCDC converter. These 2 blocks share common pins. The charge pump (CP) and is used as USB-OTG (on the go) supply (5V/8mA) and the DCDC step-up converter provides the USB-HOST supply (5V
/500mA). Depending on the external configuration either CP mode or DCDC mode is selected. Be aware that only one block can be used in one application. The following description shows how each block operates and how the circuit should be configured.
Additional the USB VBUS generation block features a VBUS comparator to detect different VBUS levels thus complies to SRP (session request protocol) and HNP (host negotiation protocol).
VBUS DCDC (USB Host Supply)
With the pin USBH_CSP connected to the battery voltage the mode USB-HOST mode is selected. This means the DCDC converter supplies 5V and up to 500mA.
For device safety an external PMOS switch is necessary in the case of a short-circuit condition on the VBUS pin. With this PMOS the device can shut off the path between battery and output. During start-up the PMOS switch will be opened very slowly by discharging his gate with a small current sink. Depending on the value of the Gate-Source Capacitance and the start-up time, different current values for the current sink can be programmed.
During start-up and operation the DCDC also monitors the current over the sense resistor. If the current limit will be reached during startup the DCDC will generate an interrupt signal after 5.3usec de-bounce time. If this over-current condition is still present after 85µs the
DCDC converter will be shut off by resetting its register. During start-up, however, an interrupt will be masked until pin USBH_PG is lower than 1V.
Figure 27 VBUS DCDC Block Diagram
valid
AG still
Technical
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VBUS Charge Pump (USB OTG Supply)
With the pin USBH_CSN and USBH_CSP connected to ground the USB-OTG mode is selected. In this mode the charge pump supplies
5V and 8mA. The charge pump uses the QLDO2 voltage as input and doubles its voltage with the help of the flying capacitor between
CP_CP and CN_GEXT to its output VBUS. If the pulse skip bit is set in the related register, the charge pump switches to pulse skip mode for improved efficiency. Enabled pulse skip mode, however, compromises with a higher output voltage ripple.
Figure 28 VBUS CP Block Diagram
Parameter
Table 34 VBUS Generation Parameter
Symbol
CP Mode
I
CPOUT
I
VDD
V
CPOUT
Parameter
Output Current
Quiescent Current
Output Voltage
V
Rsense_max
Current Limit at R sense
Min
4.7
600
5.0
Typ
AG
5.3 mA
µA
V
Unit Note still
@ 4.7V output voltage
C
FLY
=100nF,I
CPOUT
=0..8mA
F
IN
C
FLY
C
STORE
DCDC Mode
Switching frequency
External flying capacitor
External storage capacitor
ams
375
100 kHz nF ceramic, low ESR capacitor between CP_CP
2.2
140 uF
µA and CN_GEXT ceramic, low ESR capacitor between VBUS and VSS
Pulse Skipping mode I
VDD
Quiescent Current
valid
I
LOAD f
IN t
MIN_ON
C
OUT
Load Current
Fixed Switching Frequency
Minimum On-Time
Output Capacitor
0
100
750
500 mV mA
KHz e.g.: 1A for 0.1 Ohm sense resistor
@ 5V output voltage
130 ns
91 %
4.7 µF Ceramic, +/-20%
C
PARASITIC
(<100pF) for high efficiency
R
N
SW
P
SW sense
Technical
Current Limit Sense Resistor 100 mΩ switching transistor max.
1
Ω
PMOS transistor as low as possible, because of efficiency e.g.: 1A for 0.1 Ohm sense resistor
BVDD=3.3V, T
A
=25°C, unless otherwise specified
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Figure 29 15V Step-Up Performance Characteristics
75
70
65
60
100
Efficiency vs Output Current
95
V
IN
=3.6V
DCDC stepup
5V USB Host supply
90
100mA
85
80
500mA
OUTPUT CURRENT [mA]
Register Description
Table 35 USB VBUS Related Registers
Name
PMU VBUS
Base
2-wire serial
Offset Description
1Ah DCDC and CP control, VBUS comparator settings
AG still valid
Technical
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9.3.1 SYSTEM
General
The system block handles the power up, power down and regulator voltage settings of the AFE.
Power Up Conditions
The chip powers up when on of the following condition is true:
• High signal on the PWR_UP pin (>80ms, >1V & >1/3 BVDD)
• Rising edge on the VBUS pin (USB plug in: >80ms, BVDD>3V, VBUS>4.5V)
• Rising edge on the CHGIN pin (charger plug in: >80ms, BVDD>3V, CHGIN>4.0V)
• Rising edge on the RTCSUP and consequently on RVDD pin (RTCSUP > 1.35V, BVDD >3V)
• RTC wake-up: The auto wake-up timer is internally connected to the Power-up and Hibernation Control block.
To hold the chip in power up mode the PWR_HOLD bit in the SYSTEM register (0x20h) is set.
Power Down Conditions
valid
The chip automatically shuts off if one of the following conditions arises:
• Clearing the PWR_HOLD bit in SYSTEM register (0x20h)
• I2C watchdog power down(no serial reading for >1s, has to be enabled)
• Heartbeat watchdog via pin HBT(no watchdog reset via HBT pin for > 500ms, has to be enabled)
Please note, that when using power-up sequence 16 to 25 no power down is performed but a reset puls (86us typ,
60us min) will be performed.
• BVDD drops below the minimum threshold voltage (<2.7V)
AG
• Junction temperature reaches maximum threshold, set in SUPERVISOR register (0x24h)
• High signal on the PWR_UP pin for more than (>5.4s, >1V & >1/3 BVDD).
still
With setting SD_TIME bit in register 24h the time can be doubled.
content
Technical
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Start-up Sequence
The AFE offers 25 different power-up sequences. The specific start-up sequence can be selected via VPRG1 and VPROG2 pin. Each pin detects 5 logical input states which shall come from an external resistor divider network.
At first, LDO1 (AVDD) and LDO2 (DVDD) is powering up. This cannot be influenced with the selection of specific sequences below. LDO1 and LDO2 are necessary for the internal supply of the AFE.
After power-up sequence selected by pin VPRG1, all voltage settings and power on/off conditions of the described regulators can be programmed via the serial interface.
Table 36 Start-up Modes
# VPRG2 VPRG1 DCDC2
CVDD2
DCDC3
CVDD3
DCDC4 DCDC15 LDO3 LDO4
VBUS VLED PVDD1 PVDD2
XRES/
PWGD
DCDC1
CVDD1
1 open open
1,2V 3rd 3,3V 2nd 3,3V 1st x x x x
10 150k-vdd vss
11 vdd
15 vdd
16
2 open
5 open vdd
3 open
150k-vdd 1,2V 3rd 2,5V 2nd
4 open
150k-vss 1,2V 3rd 1,8V 2nd
vss
1,2V 3rd x
6 150k-vdd open
1,5V 3rd 3,3V 2nd 3,3V 1st x x x x
valid
7 150k-vdd vdd
8 150k-vdd 150k-vdd 1,5V 3nd 2,5V 2nd
9 150k-vdd 150k-vss 1,5V 3rd 1,8V 2nd
12 vdd vss vdd vss
1,5V 3rd
open still
1,8V 3rd x
13 vdd
150k-vdd 1,8V 3nd 2,5V 2nd
14 vdd
150k-vss 1,8V 3rd 1,8V 2nd x
AG open
1,2V 1st 1,8V 2nd 3,3V 3rd 5,0V 5th 5mA 5th 3,0V 6th 3,0V 7th * 8th
17
18
19
20 vss vss
150k-vdd 1,2V 1st 2,5V 2nd 3,3V 3rd 5,0V 5th 5mA 5th 3,0V 6th 3,0V 7th * 8th
vss vss
21 150k-vss vdd vss open
22 150k-vss vdd
1,2V 1st 1,8V 2nd 3,0V 3rd 5,0V 5th 5mA 5th 3,0V 6th 3,0V 7th * 8th
1,8V 1st
ams
* 8th
* 8th
* 8th
1,2V 3rd 1,8V 2nd 3,0V 1st 5,0V 5th 5mA 5th 3,0V 6th 3,0V 7th * 8th
23 150k-vss 150k-vdd 1,2V 3rd 2,5V 2nd 3,3V 1st 5,0V 5th 5mA 5th 3,0V 6th 3,0V 7th * 8th
25 150k-vss vss
* 8th
1,8V 3rd 3,3 2nd 3,3V 1st 5,0V 5th 5mA 5th 3,0V 6th 3,0V 7th * 8th
*… in Special Mode the XRES is going High 85us (min 60us) after PwrUp key is released x … means that this regulator is not started with the start-up sequencer but has to be turned on by the 2-wire serial interface when needed.
Technical
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Figure 30 Power Up Timing
Register Description
Table 37 System Related Register
Name
SYSTEM
IRQ_ENRD_1
IRQ_ENRD_3
Base
2-wire serial
2-wire serial
2-wire serial
AG still ams
Offset
20h
24h
26h
Watchdog and Over-temperature control, Power down enable
Enable/disable wake-up interrupts, set shut-down time
Enable/disable junction temperature interrupt
valid
Technical
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9.3.2 Hibernation
General
Hibernation allows shutting down a part or the complete system. Hibernation can be terminated by every possible interrupt of the AFE. E.g. one can use the RTC for a time triggered wake-up. The interrupt has to be enabled before going to hibernation
Table 38 Hibernation Modes
Modes VPRG2 Action KeepBit LDOs DCDCs VBUS DCDC15V
1-15 VDD
150k-
VDD
OPEN
Hib. with Default
Cancel Hibernation
Hib. with Modif Settings
Cancel Hibernation
OFF
OFF
OFF
OFF
OFF
Default
OFF
As Before
OFF
Default
OFF
OFF
OFF No Change
As Before No Change
OFF
OFF
No Change
No Change
16-25 VSS
150k-
VSS
Hib. with Modif Settings
Cancel Hibernation
Hib. with Default
Hib. with Modif Settings
Cancel Hibernation
Hib. with Modif Settings
ON
ON
OFF
OFF
OFF
ON
No Change No Change No Change
No Change No Change No Change
OFF
OFF
As Before
OFF
OFF
As Before
Stays ON
No Change
ON
No Change No Change No Change
No Change
No Change
OFF
OFF
valid
No Change
No Change No Change No Change
“Hibernation with Default” means that, the voltage of the power supply is determined by VPROG1 pin.
“Hibernation with Modified Settings” means, that the voltage of the power supply is controlled by register settings.
Figure 31 Hibernate Timing
Cancel Hibernation ON
AG still
No Change
Table 39 Hibernation Related Register
Name
PMU Hibernate
PMU ENABLE
Base
2-wire serial
2-wire serial
Offset Description
17h-6
18h
Hibernation control
Enables writings to extended register 17h-6
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9.3.3 Supervisor
General
This supervisor function can be used for automatic detection of BVDD brown out or junction over-temperature condition.
BVDD Supervision
The supervision level can be set in 8 steps @ 60mV from 2.74 to 3.16V. If the level is reached an interrupt can be generated. If BVDD reaches 2.7V the AFE shuts down automatically.
Junction Temperature Supervision
The temperature supervision level can also be set by 5 bits (120 to –15 o
C). If the temperature reaches this level, an interrupt can be generated. The over-temperature shutdown level is always 20 o C higher.
Power Rail Monitoring
The 4 main regulators have an extra monitor which measures the output voltage of the regulator. This power rail monitors are independent from the 10bit ADC. To activate these please see related registers.
Register Description
valid
Table 40 Supervisor Related Register
Name Base Offset Description
SUPERVISOR 2-wire serial 21h
IRQ_ENRD_2
IRQ_ENRD_3
2-wire serial
2-wire serial
25h
26h Enable/disable junction temperature interrupt
Technical
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General
All interrupt sources can get enabled or disabled by corresponding bits in the 5 IRQ-bytes. By default no interrupt source is enabled.
The XIRQ output can get configured to be PUSH/PULL or OPEN_DRAIN and ACTIVE_HIGH or ACTIVE LOW with 2 bits in IRQ_ENRD_4 register (27h). Default state is open drain and active_low.
IRQ Source Interpretation
There are 3 different modules to process interrupt sources:
LEVEL
The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled
EDGE
The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-Register gets read.
STATUS CHANGE
The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which interrupt was the source.
valid
The IRQ stays active until the corresponding interrupt register gets read.
De-bouncer
There is a de-bounce function implemented for USB and CHARGER. Since these 2 signals can be unstable for the phase of plug-in or unplug, a de-bounce time of 512ms/256ms/128ms can be selected by 2 bits in the IRQ_ENRD_4 register (27h).
Interrupt Sources
18 IRQ events will activate the XIRQ pin:
AG
• headphone connected
• Microphone 1 connected
still
• Microphone 2 connected
• Microphone 1 remote control
• Microphone 2 remote control
• Voice activation threshold reached
• RTC sec/min elapsed
ams
• 10bit ADC end of conversion
• I²S changed
• USB changed
content
• Charger changed
• End of charge (at 10% of programmed current )
• Battery temperature high (at 42°C and 45°C with 100kΩ NTC)
• RVDD low (e.g. after battery was changed)
• Battery low (Brown-out voltage reached)
• wake-up from hibernation
• power-up key (pin PWRUP) pressed
• power rail monitor: PVDD1, PVDD2, CVDD1, CVDD2
Technical
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9.3.5 Real Time Clock
General
The real time clock block is an independent block, which is still working even when the chip is shut down. The only condition for this operation is that BVDDR has a voltage of above 1.0V. The block uses a standard 32kHz crystal that is connected to a low power oscillator. The total power consumption is typ. 12µA. (Q32k clock buffer not operating)
The RTC seconds counter is 32bit wide and can be programmed via the 2-wire serial interface. The RTC can deliver a seconds or minutes interrupt.
Another 23bit wide counter allows auto wake-up (max. after 96 days). This counter is internally connected to the power-up and hibernation control block.
The RTC voltage regulator (RVDD) further supplies a 128bit SRAM. It can be used to store settings or data before shutdown.
Clock adjustment
The RTC clock is adjustable in steps of 7.6ppm which allows the use of inexpensive 32kHz crystals. The nominal frequency shall be
32.768Hz. This frequency is divided down to 0.25Hz: f = 32.768 / (4*32*1024)
At the input of this divider one can add corrective counts, which allow to correct an inaccurate crystal in a range from –64 counts (=-
488ppm) to +63 counts (=+480ppm): f corrected
= f crystal
/ [(4*32*1024)-64+RTC_TBC]
valid
Register Description
Table 41 RTC Related Register
Name
RTCV
Base
2-wire serial
Offset
28h RTC oscillator and counter enable
RTC interrupt and time correction settings
still
29h
2Ah to 2Dh RTC time-base seconds registers
RTCT 2-wire serial
RTC_0 to RTC_3 2-wire serial
RTC_WakeUp
IRQ_ENRD_2
IRQ_ENRD_4
2-wire serial
2-wire serial
2-wire serial
19h
25h
RTC wake-up settings and SDRAM access
Interrupt settings for RVDD under-voltage detection
27h Interrupt settings for getting a second or minute interrupt
content
Technical
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General
This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature supervision, button press detection, etc..
Input Sources
Table 42 ADC10 Input Sources
Nr.
0
1
Source
CHGOUT
BVDDR
2
5
6
3
4
7
8
9
10
11
12
13..15
CHGIN
VBUS
BatTemp
MIC1S
MIC2S
VBE_1uA
VBE_2uA
I_MIC1S
I_MIC2S
RVDD
Reserved
Range LSB Description
5.120V 5mV check battery voltage of 4V LiIo accumulator
5.120V 5mV check RTC backup battery voltage (connected to BVDD inside the package)
5.120V
5.120V
5.120V
2.560V
2.560V
2.560V
1.024
1.024
2.560V
2.5mV check voltage on MIC1S for remote control or external voltage measurement
Tj = 0.5*[ADC_bit0:bit9] – 565/2
AG
2.5mV check RTC supply voltage
1mV for testing purpose only
still
1.024mA typ. 2.0uA check current of MIC1S for remote control detection
1.024mA typ. 2.0uA check current of MIC2S for remote control detection
1.024V
5mV Source defined by DC_TEST in register 0x18
5mV check charger input voltage
5mV check USB input voltage
2.5mV check battery charging temperature
2.5mV check voltage on MIC1S for remote control or external voltage
valid
measurement
Reference
+/-1%.
Parameter
Table 43 ADC10 Parameter
Symbol
R
DIV
ADC
FS
Ratio1
Ratio2
Gain
T
CON
I_MIC
FS
Parameter
Input Divider Resistance
ADC Full Scale Range
Division Factor 1
Division Factor 2
ADC Gain Stage
Conversion Time
I_MICS Full Scale Range
BVDD=3.6V; T amb
=25ºC; unless otherwise specified
Min
138k 180k 234k
2.534 2.56 2.586
0.198
0.396
0.2
0.4
0.202
0.404
2.475
-
0.7
2.5
34
1.0
2.525
50
1.4
Notes
Ω CHGOUT, BVDDR, VBUS, CHGIN
V
1 CHGOUT, BVDDR, VBUS, CHGIN
1 RVDD, BATTEMP, MIC1S, MIC2S
V
µs mA
Register Description
Table 44 ADC10 Related Register
Name
ADC_0
ADC_1
Technical
Description
ADC source selection, ADC result<9:8>
ADC result <7:0>
IRQ_ENRD_4
PMU_ENABLE
2-wire serial
2-wire serial
27h
18h
Interrupt settings for end of conversion interrupt
Extended ADC source selection
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9.3.7 Unique ID Code (64 bit OTP ROM)
General
This fuse array is used to store a unique identification number, which can be used for DRM issues. The number is generated and programmed during the production process.
Register Description
Table 45 UID Related Register
Name Base
UID_0 to UID_7 2-wire serial
Offset Description
38h to 3Fh Unique ID register 0 to 7
AG still valid
Technical
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Table 46 I2C Register Overview
D<5>
-
D<4> D<3> D<2> D<1>
LO1R_VOL
Gain from MUX_B to LOUT1R= (-40.5dB … +6dB)
D<0> Addr Name
00h LINE_OUT1_R
01h LINE_OUT1_L
D<7> D<6>
LO1_MUX_B
0:SUM_Stereo;1:SUM_MDiff
2:ADC_IN; 3:DAC_OUT
0 0
- MUTE_OFF
_J
0
-
0 0
LO1L_VOL
0 0 0
Gain from MUX_B to LOUT1L= (-40.5dB … +6dB)
02h HPH_OUT_R
0 0 0
HP_OVC_TO
0: 256ms; 1: 128ms
2: 512ms; (3: 0ms)
04h LINE_OUT2_R
05h LINE_OUT2_L
06h MIC1_R
07h MIC1_L
08h MIC2_R
09h MIC2_L
0Ah Line_IN1_R
0Bh Line_IN1_L
1:MIC1_MDiff; 3: Stereo_MIC
0
0 0 0 0 0 0 0 0
K
LO2_MUX_D
HP_ON HPDET_ON HPL_VOL
0: MIC1; 2: MIC2
Gain from MUX_C to HPL= (-45.43dB … +1.07dB)
valid
0
_OFF _E OFF
0
M1R_VOL
M1L_VOL
0
AG
0
Gain from MicAmp (N6) to Mixer (N14) = (-40.5dB … +6.0dB)
0 0 0 0 0 0 0 0
M2R_VOL MIC2_AGC PRE2_GAIN
-
0
LO2R_VOL
Gain from MUX_D to LOUT2R= (-40.5dB … +6dB)
0 0 0 0 0
-
0
MIC1_AGC
_OFF
MUTE_OFF
_L
0
PRE1_GAIN
-
0
0: 28dB; 1: 34dB
2: 40dB
LO2L_VOL
Gain from MUX_D to LOUT2L= (-40.5dB … +6dB)
0
still
0
0 0 0 0 0 0 0 0
M1SUP MUTE_OFF RDET1_
_OFF
0
M2SUP
_OFF
0
LI1_MODE
0: 28dB; 1: 34dB
2: 40dB
0
_D
0
ams
- - MUTE_OFF
_B
MUTE_OFF
Gain from MicAmp (N4) to Mixer (N12) = (-40.5dB … +6.0dB)
0
M2L_VOL
0 0 0 0
Gain from MicAmp (N4) to Mixer_In (N13)= (-40.5dB … +6.0dB)
0
LI1R_VOL
LI1L_VOL
0 0 0 0
0 0 0 0 0 0 0 0
00: SE_Sterep; 01: MonoDiff
10: SE_Mono
_G Gain from LIN1L to Mixer (N17)= (-34.5dB … +12dB)
0 0 0 0 0 0 0 0
- - MUTE_OFF
_C
LI2R_VOL
Gain from LIN2R to Mixer (N11)= (-34.5dB … +12dB)
0Ch Line_IN2_R
0
DAC_
DIRECT
0
HPR_VOL
0 0 0
Gain from MUX_C to HPR= (-45.43dB … +1.07dB)
0Dh Line_IN2_L
0Eh DAC_R
0
LI2_MODE
0
00: SE_Sterep; 01: MonoDiff
10: SE_Mono
0
MUTE_OFF
_F
0
LI2L_VOL
0 0 0 0
Gain from LIN2L to Mixer (N16)= (-34.5dB … +12dB)
0 0 0 0 0
- - - DAR_VOL
0 0 0
Gain from DAC (N19) to Mixer/MUX (N23)= (-40.5dB … +6dB)
0Fh DAC_L
10h ADC_R
0 0 0 0 0 0 0 0
- MUTE_OFF
0 0 0 0 0 0 0 0
ADC_MUX_A
0: Stereo_Mic; 1:LineIN_1
2: LineIN_2; 3: AudioSUM
- DAL_VOL
-
Gain from DAC (N22) to Mixer/MUX (N26) = (-40.5dB … +6dB)
ADR_VOL
Gain from MUX_A to ADC (N9) = (-34.5dB … +12dB)
0 0 0 0 0 0 0 0
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12h-1 OutContr1
12h-2 OutContr2_SP
DIF
12h-3 PWM
14h AudioSet_1
15h AudioSet_2
16h AudioSet_3
D<6> D<5> D<4> D<3> D<2> D<1> D<0>
AS3517 V17
Data Sheet, Confidential
Addr Name
11h ADC_L
D<7>
- MUTE_OFF
_A
- ADL_VOL
Gain from MUX_A to ADC (N18) = (-34.5dB … +12dB)
0 0
DRIVE_PWGD
0
MUX_PWGD
0 0 0
DRIVE_Q32K
0
MUX_Q32K
0
0: 12mA OD; 1: 12mA PP
2: 4mA PP; 3: 2mA PP
0: PWGD; 1: PWM
2: SPDIF; 3: PLL clock
0: 12mA PP; 1: 12mA OD
2: 4mA PP; 3: 2mA PP
0: Q32K; 1: PWM
2: SPDIF; 3: PLL clock
0 0 0 0 0 0 0 0
DRIVE_Q24M
0: 12mA PP; 1: 12mA OD
2: 4mA PP; 3: 2mA PP
MUX_Q24M
0: Q24
1: PLL clock
SPDIF_
COPY_OK
SPDIF_
MCLK_INV
SPDIF_
INVALID
SPDIF_CNTR
0: OFF; 1: 32kS
2: 44.1kS; 3: 48kS
0 0 0 0 0 0 0 0
PWM_ PWM_CYCLE
INVERTED 0: no pulses; DytyCycle = PWM_CYCLE * 0.3937%
0 0 0 0 0 0 0 0
0
ADC_R_ON ADC_L_ON LOUT2_ON LOUT1_ON LIN2_ON LIN1_ON MIC2_ON MIC1_ON
0
BIAS_OFF SUM_OFF AGC_OFF IBR_DAC
0
LIN1MIX_O
FF
0
0
LIN2MIX_O
FF
0
0
MIC1MIX_O
FF
0
0
MIC2MIX_O
FF
0
0
DACMIX_O
FF
0
0
0
DAC_ON -
0
ZCU_OFF IBR_HPH
0
0
valid
LDO_PVDD
1_OFF
0 0
PVDD1
0 0 0 0
0h – Fh:1.2V+VSEL*50mV (1.2V – 1.95V)
10h – 1Fh: 2.0V+(VSEL-10h)*100mV (2.0V – 3.5V)
0
18h PMU Enable
LDO_PVDD
2_OFF PVDD2 0h – Fh:1.2V+VSEL*50mV (1.2V – 1.95V)
10h – 1Fh: 2.0V+(VSEL-10h)*100mV (2.0V – 3.5V)
VSEL_CVDD1
0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV Î 0.65V – 3.40V; (38h – 3Fh …. 3.4V)
SKIP_OFF_
CVDD1
PROG_
CVDD1
0 0 0 0 0 0 0 0
-
SKIP_OFF_
CVDD2
SKIP_OFF_
CVDD3
PROG_
CVDD2
PVDD2
VSEL_CVDD2
0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV Î 0.65V – 3.40V; (38h – 3Fh …. 3.4V)
0 0 0 0 0 0 0 0
PROG_
CVDD3
ams
KEEP_
CVDD2
KEEP_
CVDD1
0 0 0 0 0 0 0 0
DC_TEST
PVDD1
KEEP_ KEEP_ KEEP_
content
0: unused; 1: AVDD; 2: DVDD; 3: PVDD1
4: PVDD2; 5: CVDD1; 6; CVDD2; 7: CVDD3
1: prog 17h-1 / 12h-1 (PVDD1, OutContr1)
2: prog 17h-2 / 12h-2 (PVDD2, OutContr2)
3: prog 17h-3 / 12h-3 (CVDD1, PWM)
4: prog 17h-4 (CVDD2); 5: prog 17h-5 (CVDD3)
6: prog 17h-6 (Hibernate); 0,7: unused
0 0 0 0 0 0 0 0
1 st
write/read: WAKEUP_BYTE_1
128s 64s 32s 16s 8s 4s 2s 1s
2 nd
write/read: WAKEUP_BYTE_2
32ks 16ks 8ks 4ks 2ks 1ks 512s 256s
3 rd wirte/read: WAKEUP_BYTE_3
4 th to 19 th write/read: SRAM_128
1Ah USB_UTIL_DC
DC
1Bh DCDC15
I_PMOS_GATE
0: 1µA; 1: 2µA
2: 3µA; 3: 4µA
0
DIM_UP_D
0
DIM_RATE
DCDC_PS_
OFF
0
OWN 0: no dimming; 1: 150ms
2: 300ms; 3: 500ms
DCDC_
PMOS_OFF
0
VBUS_COMP_TH
0: 4.5V; 1: 3.18V
2: 1.5V; 3: 0.6V
0
I_BACKLIGHT
0
VBUS_SKIP
_ON
0
VBUS_ON
0
0 … OFF
1-31 … LED current = 1.25mA*I_BACKLIGHT (1.25mA … 38.75mA)
0 0 0 0 0 0 0 0
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Addr Name D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0>
1Ch I2S
1Dh I2S_PLL_OSC
20h SYSTEM
21h SUPERVISOR
22h CHARGER
23h IRQ_ENRD_0
24h IRQ_ENRD_1
25h IRQ_ENRD_2
Please see master clock divider table
0 0 0 0 0 0 0 0
I2S_MASTE OSC24_PD I2S_ Q24M_DIVIDER PLL_MODE I2S_DIVIDE
R_8 R_ON DIRECT 0: /1; 1: /2
2: /4; 3:OFF
0 0 0 0 0
Design_Version<3:0> HEARTBEA
T_ON
0: reserved; 1: 16-48kS
2: 8-12kS; 3: reserved
0 0
JTEMP_
OFF
WATCHDO
G_ON
0
PWR_HOLD
1 1 1 1 0 0 0 1
BVDD_SUP JTEMP_SUP
V_BrownOut = 2..74V+BVDD_SUP*60mV
(2.74V .. 3.16V)
0
BAT_TEMP
0
CHG_I
1
Temp_ShutDown = 140C – JTEMP_SUP*5C (+140C..—15C)
Temp_IRQ = 120C – JTEMP_SUP*5C (+120C .. –35C)
0 0
CHG_V
0 0 0
CHG_OFF
0
SD_TIME
0: 5.4s
1: 10.9s
0
_OFF
0 0 0 0 0 0 0 0
CVDD2_
EN_SD
CVDD2_
UNDER
CVDD2_
EN_IRQ
CVDD2_
OVER
CVDD1_
EN_SD
CVDD1_
UNDER
CVDD1_
EN_IRQ
CVDD1_
OVER
Vchg=3.9V+50mV*CHG_V
(3.9V … 4.25V)
PDD2_
EN_SD
PDD2_
UNDER
PDD2_
EN_IRQ
PDD2_
OVER
PDD1_
EN_SD
PDD1_
UNDER
PDD1_
EN_IRQ
PDD1_
OVER
valid
BATTEMP_
0
HIGH
Ichg=50mA+50mA*CHG_I
(50mA … 400mA)
0
-
0
CHG_
EOC
0
0
PWRUP_
IRQ
0
CHG_
STATUS
0
0
WAKEUP_
IRQ
0
VOXM2_
IRQ
0
CHG_
CHANGED STATUS
0 0
0 0 0
0
VOXM1_
IRQ
0
USB_CHAN
GED
CVDD3_
EN_SD
0
still
CVDD3_
EN_IRQ
CVDD3_
OVER
0
RVDD_LOW BVDD_LOW
0 0
- JTEMP_HI
GH
HPH_
OVC
I2S_
STATUS
I2S_
CHANGED
MIC2_
CONNECT
MIC1_
CONNECT
HPH_
CONNECT
26h IRQ_ENRD_3
27h IRQ_ENRD_4
28h RTCV
29h RTCT
2Ah RTC_0
0
T_DEB
0
V_RVDD
Default is 1.2V.
IRQ_MIN TRTC<6:0>
0 0
content
0 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0
QRTC<7:0>
0
0: 512ms; 1: 256ms
2: 128ms; 3: 0ms
0
V(RVDD)=1V+V_RVDD*0.1V
0
0
0
0
0 0 0
XIRQ_AH XIRQ_PP REM2_DET REM1_DET RTC_
UPDATE
0
0
ADC_EOC
0
0 0 1 0 0 0 1 1
QRTC<15:8> 2Bh RTC_1
2Ch RTC_2
0 0 0 0 0 0 0 0
QRTC<23:16>
0 0 0 0 0 0 0 0
QRTC<31:24> 2Dh RTC_3
2Eh ADC_0
0 0 0 0 0 0 0 0
ADC_Source<3:0>
0: CHGOUT; 1: BVDDR; 2: DC_TEST; 3: CHG_IN; 4: VBUS;
5: BatTemp; 6: MSUP1; 7: MSUP2; 8: VBE_1uA; 9: VBE_2uA;
10: I_MSUP1; 11: I_MSUP2; 12; RVDD; 13, 14, 15: reserved
0
2Fh ADC_1
..
0
ADC<7:0>
X
ID<7:0>
…
0
X
0
X X
ID<63:56>
-
0
X
-
0
X
ADC<9:8>
X
X
X
X
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Table 47 LINE_OUT1_R Register
Name Base Default
Offset: 00h
Right Line Output 1 Register
Configures MUX_B and the audio gain from MUX_B output to LOUT1R output.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default Access Bit Description Bit Bit Name
7:6 LO1_MUX_B
5
4:0 LO1R_VOL
Table 48 LINE_OUT1_L Register
Name
Offset: 01h
Bit Bit Name
7
6 MUTE_OFF_J
5
4:0 LO1L_VOL
00 R/W Multiplexes the analog audio inputs of MUX_B to LOUT1R and at LOUT1L
00: SUM Stereo
01: SUM mono differential (The gain of LOUT1R shall be 0dB
0
00000 n/a
R/W to hold signals in symmetry)
10: ADC (N9/N18)
11: DAC (N23/N26) volume settings for right line output 1, adjustable in
32 steps @ 1.5dB; gain from MUX_B to LOUT1R
11111: 6 dB gain
11110: 4.5 dB gain
..
Base
00001: -39 dB gain
00000: -40.5 dB gain
Left Line Output 1 Register
AG
Default still
Configures the audio gain from MUX_B output to LOUT1L output and controls
valid
MUTE switch J
This register is reset when the stage is disabled in AudioSet1 register (14h) or at a
Default
0
0b
0
ams
R/W n/a
R/W volume settings for left line output 1, adjustable in 00000
32 steps @ 1.5dB; gain from MUX_B to LOUT1L
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Technical
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Table 49 HPH_OUT_R Register
Name Base Default
Offset: 02h
Right Headphone Output Register
Configures MUX_C and the audio gain from MUX_C output to HPR output.
This register is reset at a DVDD-POR.
Bit Bit Name
7:6 HP_OVC_TO
5
Name
DAC_DIRECT
4:0 HPR_VOL
Table 50 HPH_OUT_L Register
Default Access Bit Description
00 R/W Headphone amplifier over current time out. The headphone amplifier is powered down if an over-current is detected. The current thresholds are 150mA at pins HPR / HPL pin or 300mA at pin HPCM (e.g. shorted headphone outputs)
11: 0 ms ( no power down)
0
00000
R/W
R/W
Base
11110: -0.43 dB gain
..
10: 512ms
01: 128ms
00: 256 ms
0: MUX_C output connected to limiter (N24/N25)
1: MUX_C output connected to DAC (N23/N26) volume settings for right headphone output, adjustable in 32
valid
steps @ 1.5dB; gain from MUX_C to HPR output
11111: 1.07 dB gain
00001: -43.93 dB gain
AG
Left Headphone Output Register
Default still
Offset: 03h
Bit Bit Name
7 MUTE_ON_K
6 HP_ON
5 HPDET_ON
4:0 HPL_VOL
0
0
Configures the audio gain from MUX_C output to HPL output and controls
MUTE switch K
Default ams
0
R/W
Access Bit Description
R/W Control of MUTE switch K
content
1: power up headphone stage
Enables the detection when a headset gets connected. HPCM is used as a sense pin and is biased to 150mV
0: no headphone detection
1: enable headphone detection
00000 R/W volume settings for left headphone output, adjustable in 32 steps @ 1.5dB; gain from MUX_C output to HPL output
11111: 1.07 dB gain
11110: -0.43 dB gain
..
00001: -43.93 dB gain
00000: -45.43 dB gain
Technical
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Table 51 LINE_OUT2_R Register
Name Base Default
Offset: 04h
Right Line Output 2 Register
Configures MUX_B and the audio gain from MUX_B output to LOUT2R output.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default Access Bit Description Bit Bit Name
7:6 LO2_MUX_D
5
4:0 LO2R_VOL
Table 52 LINE_OUT2_L Register
Name
Offset: 05h
Bit Bit Name
7
6 MUTE_OFF_L
5
4:0 LO2L_VOL
00 R/W Multiplexes the analog audio inputs of MUX_D to LOUT2R and at LOUT2L
00: MIC1
01: MIC1 mono differential (The gain of LOUT2R shall be 0dB
0
00000 n/a
R/W to hold signals in symmetry)
10: MIC2
11: Stereo MIC volume settings for right line output 2, adjustable in
32 steps @ 1.5dB; gain from MUX_D to LOUT2R
11111: 6 dB gain
11110: 4.5 dB gain
..
Base
00001: -39 dB gain
00000: -40.5 dB gain
Left Line Output 2 Register
AG
Default still
Configures the audio gain from MUX_B output to LOUT2L output and controls
valid
MUTE switch J
This register is reset when the stage is disabled in AudioSet1 register (14h) or at a
Default
0
0b
0
ams
R/W n/a
R/W volume settings for left line output 2, adjustable in 00000
32 steps @ 1.5dB; gain from MUX_D to LOUT2L
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Technical
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Table 53 MIC1_R Register
Name Base Default
Offset: 06h
Bit Bit Name
7 MIC1_AGC_OFF
6:5 PRE1_Gain
4:0 M1R_VOL
Table 54 MIC1_L Register
Right Microphone Input 1 Register
Configures the gain from microphone 1 amplifier output up to mixer input (Σ).
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
0
00
00000
R/W
R/W
Access Bit Description
R/W Control of limiter AGC (automatic gain control). Limits high dynamic range of electrete/MEMS microphone (e.g. user shouts or blows into microphone)
0: automatic gain control enabled
1: automatic gain control disabled
Sets the gain of the microphone 1 preamplifier (gain from microphone inputs to N5)
00: gain set to 28 dB
01: gain set to 34 dB
10: gain set to 40 dB
11: reserved, do not use. volume settings for right microphone input 1, adjustable in 32 steps @ 1.5dB; gain from microphone amplifier (N6) to mixer input (N15)
11111: 6 dB gain
..
AG still valid
Name
Offset: 07h
Bit Bit Name
7 M1SUP_OFF
6
5
MUTE_OFF_E
RDET1_OFF
4:0 M1L_VOL
0
0
Base
Configures the gain from microphone 1 amplifier output up to mixer input (Σ) and controls MUTE switch D.
DVDD-POR. The register cannot be written when the block is disabled.
Default Access
Default
0
content
R/W 0: microphone 1 supply enabled
1: microphone supply disabled
R/W
00000
R/W
R/W
Technical
Control of MUTE switch E
0: microphone input 1 set to mute
1: normal operation
Disables the microphone 1 detect function (30kOhm pull-up from MIC1S to AVDD) to use the terminal as ADC-10 input
0: microphone 1 detection enabled
1: microphone detection disabled volume settings for left microphone 1 input, adjustable in 32 steps @ 1.5dB; gain from microphone amplifier (N6) to mixer input (N14)
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
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Table 55 MIC2_R Register
Name Base Default
Offset: 08h
Bit Bit Name
7 MIC2_AGC_OFF
6:5 PRE2_Gain
4:0 M2R_VOL
Table 56 MIC2_L Register
Right Microphone Input 2 Register
Configures the gain from microphone 2 amplifier output up to mixer input (Σ).
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
0
00
00000
R/W
R/W
Access Bit Description
R/W Control of limiter AGC (automatic gain control). Limits high dynamic range of electrete/MEMS microphone (e.g. user shouts or blows into microphone)
0: automatic gain control enabled
1: automatic gain control disabled
Sets the gain of the microphone 2 preamplifier (gain from microphone inputs to N5)
00: gain set to 28 dB
01: gain set to 34 dB
10: gain set to 40 dB
11: reserved, do not use. volume settings for right microphone input 2, adjustable in 32 steps @ 1.5dB; gain from microphone amplifier (N4) to mixer input (N12)
11111: 6 dB gain
..
AG still valid
Name
Offset: 09h
Bit Bit Name
7 M1SUP_OFF
6
5
MUTE_OFF_D
RDET2_OFF
4:0 M2L_VOL
0
0
Base
Configures the gain from microphone 2 amplifier output up to mixer input (Σ) and controls MUTE switch E.
DVDD-POR. The register cannot be written when the block is disabled.
Default Access
Default
0
content
R/W 0: microphone 2 supply enabled
1: microphone supply disabled
R/W
00000
R/W
R/W
Technical
Control of MUTE switch D
0: microphone input 2 set to mute
1: normal operation
Disables the microphone 2 detect function (30kOhm pull-up from MIC1S to AVDD) to use the terminal as ADC-10 input
0: microphone 1 detection enabled
1: microphone detection disabled volume settings for left microphone 2 input, adjustable in 32 steps @ 1.5dB; gain from microphone amplifier (N4) to mixer input (N13)
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
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Table 57 LINE_IN1_R Register
Name Base Default
Offset: 0Ah
Bit Bit Name
7:6
5 MUTE_OFF_B
4:0 LI1R_VOL
Table 58 LINE_IN1_L Register
Name
Offset: 0Bh
Bit Bit Name
7:6 LI1_MODE
5 MUTE_OFF_G
4:0 LI1L_VOL
Right Line Input 1 Registers
Configures the gain from analog line input pin LIN1R to mixer input (Σ) and controls
MUTE switch B.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default Access Bit Description
00
0 n/a
R/W Control of MUTE switch B
0: right line input is set to mute
00000 R/W
..
1: normal operation volume settings for right line input 1, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN1R) to mixer input (N10)
11111: 12 dB gain
11110: 10.5 dB gain
valid
00001: -33 dB gain
00000: -34.5 dB gain
Left Line Input 1 Registers
MUTE switch G.
Base
AG
Default still
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
00
0
Access Bit Description ams
R/W
Configures Line Input 1 (right and left channel) in accordance with the connected input sources
0: left line input is set to mute
1: normal operation
00000 R/W volume settings for right line input 1, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN1L) to mixer input (N17)
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
Technical
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Table 59 LINE_IN2_R Register
Name Base Default
Offset: 0Ch
Bit Bit Name
7:6
5 MUTE_OFF_C
4:0 LI2R_VOL
Table 60 LINE_IN2_L Register
Name
Offset: 0Dh
Bit Bit Name
7:6 LI2_MODE
5 MUTE_OFF_F
4:0 LI2L_VOL
Right Line Input 2 Register
Configures the gain from analog line input pin LIN2R to mixer input (Σ) and controls
MUTE switch C.
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default Access Bit Description
00
0 n/a
R/W Control of MUTE switch C
0: right line input is set to mute
00000 R/W
..
1: normal operation volume settings for right line input, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN2R) to mixer input (N11)
11111: 12 dB gain
11110: 10.5 dB gain
valid
00001: -33 dB gain
00000: -34.5 dB gain
Left Line Input 2 Registers
MUTE switch F.
Base
AG
Default still
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
00
0
Access Bit Description ams
R/W
Configures Line Input 2 (right and left channel) in accordance with the connected input sources
0: left line input is set to mute
1: normal operation
00000 R/W volume settings for right line input, adjustable in 32 steps @
1.5dB; gain from line input pin (LIN2L) to mixer input (N16)
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
Technical
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Offset: 0Eh
Bit Bit Name
7:5
4:0 DAR_VOL
Table 62 DAC_L Register
Name
Offset: 0Fh
Bit Bit Name
7
6 MUTE_OFF_H
5
4:0 DAL_VOL
AS3517 V17
Data Sheet, Confidential
Table 61 DAC_R Register
Name Base Default
Right DAC Output Registers
Configures the gain from DAC output to mixer input (Σ) / MUX input.
This register is reset when the block is disabled in AudioSet2 register (15h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default Access Bit Description
000 n/a
00000 R/W
Base
Volume settings for right DAC output, adjustable in 32 steps @
1.5dB; gain from DAC output (N19) to mixer/MUX input (N23).
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Default valid
Left DAC output Registers
Configures the gain from DAC output to mixer input (Σ) / MUX input and controls MUTE switch H.
Default
0
0
AG still
DVDD-POR. The register cannot be written when the block is disabled.
Access Bit Description
n/a
R/W Control of MUTE switch H
0
00000 n/a
R/W
0: DAC output is set to mute
1: normal operation
ams
Volume settings for left DAC output, adjustable in 32 steps @
1.5dB: gain from DAC output (N22) to mixer/MUX input (N26).
11111: 6 dB gain
11110: 4.5 dB gain
..
00000: -40.5 dB gain
Technical
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Offset: 10h
Bit Bit Name
7:6 ADC_MUX_A
5
4:0 ADR_VOL
Table 64 ADC_L Register
Name
Offset: 11h
Bit Bit Name
7
6 MUTE_OFF_A
5
4:0 ADL_VOL
AS3517 V17
Data Sheet, Confidential
Table 63 ADC_R Register
Name Base Default
Right ADC input Registers
Configures MUX_A and the gain from MUX_A output to the ADC input
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default Access Bit Description
00 R/W Connect MUX A output to following inputs
00: Microphone (N4/N6)
01: Line_IN1 (N1/N8)
10: Line_IN2 (N2/N7)
0
00000
11: Audio SUM (N24/N25) n/a
R/W Volume settings for right ADC input, adjustable in 32 steps @
1.5dB; gain from MUX_A output to ADC input (N9).
11111: 12 dB gain
11110: 10.5 dB gain
valid
..
00001: -33 dB gain
Base
00000: -34.5 dB gain
Default still
Left ADC input Registers
This register is reset when the block is disabled in AudioSet1 register (14h) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Default
0
0
0
00000
Access Bit Description ams
R/W
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
Technical
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Offset: 12h-1
Bit Bit Name
7:6 DRIVE_PWGD
5:4 MUX_PWGD
3:2 DRIVE_Q32K
1:0 MUX_Q32K
AS3517 V17
Data Sheet, Confidential
Table 65 Output Control Register
Name Base Default
00
00
00
Q32k and PWGD Output Control Register
Configures PWGD pin (Power Good) and Q32k pin (output of 32kHz oscillator).
This is an extended register and needs to be enabled by writing 001b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default
00
R/W
R/W
R/W
Access Bit Description
R/W Enables the PWGD output pin either to open-drain or push-pull and sets various driving strengths
00: 12mA push-pull output
01: 12mA open-drain output
10: 4mA push-pull output
11: 2mA push-pull output
Multiplexes various digital signals to the PWGD output pin
00: PowerGood control signal
01: PWM signal to dim LEDs etc.
10: SPDIF converted from SDI to DAC
11: PLL output clock
Enables the Q32k output pin either to open-drain or push-pull
valid
and sets various driving strengths
00: 12mA push-pull output
01: 12mA open-drain output
10: 4mA push-pull output
AG
10: SPDIF converted from SDI to DAC
11: PLL output clock
Technical
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Table 66 SPDIF Register
Name Base Default
Offset: 12h-2
Bit Bit Name
7:6 DRIVE_Q24M
5
4
3
2
MUX_Q24M
SPDIF_COPY_OK
SPDIF_MCLK_INV
SPDIF_INVALID
1:0 SPDIF_CNTR
SPDIF and Q24M Output Control Register
Adds status bits to the SPDIF bit-stream, configures the SPDIF output and the Q24M pin (output of 24MHz oscillator)
This is an extended register and needs to be enabled by writing 010b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default Access Bit Description
00 R/W
0
0
0
0
00
R/W
R/W
Enables the Q24M output pin either to open-drain or push-pull and sets various driving strengths
00: 12mA push-pull output
01: 12mA open-drain output
10: 4mA push-pull output
11: 2mA push-pull output
Multiplexes various digital signals to the Q24M output pin
0: 24MHz oscillator clock
1: PLL output clock
SPDIF copy control bit
0: copy not permitted
1: copy permitted
SPDIF master clock control bit
0: master clock
AG still
SPDIF output ON/OFF control and sample rate status bits
00: SPDIF output OFF valid
01: SPDIF output ON (32kS)
10: SPDIF output ON (44.1kS)
content
Technical
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Table 67 PWM Register
Name Base Default
Offset: 12h-3
PWM Output Control Register
Sets the PWM output duty cycle and signal polarity.
This is an extended register and needs to be enabled by writing 011b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default Access Bit Description Bit Bit Name
7 PWM_INVERTED 0
6:0 PWM_CYCLE
Table 68 AudioSet_1 Register
Name
Offset: 14h
Bit Bit Name
7 ADC_R_ON
6 ADC_L_ON
5 LOUT2_ON
4 LOUT1_ON
3 LIN2_ON
2 LIN1_ON
1 MIC2_ON
0: not inverted
1: inverted
Sets the PWM duty cycle 0000000 R/W
Attention: This control register resets and holds microphone, line out, and ADC related registers in reset. After activation the required register settings need to be re-
0
Base
Duty Cycle = PWM_CYCLE * 0.3937%
PWM_CYCLE = 0 means no pulse
First Audio Set Register
Access Bit Description
Default
Powers the various audio inputs and outputs UP or DOWN. programmed.
Default
0
AG
1: ADC right channel enabled for recording
R/W 0: ADC left channel powered down
still valid
0
0
0
0
1: ADC left channel enabled for recording
R/W 0: Line output 2 powered down
1: Line output enabled
R/W 0: Line input 2 powered down
content
R/W 0: Microphone input 2 powered down
1: Microphone input 1 enabled
0
0 R/W 0: Microphone input 1 powered down
1: Microphone input 1 enabled
0 MIC1_ON
Technical
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Offset: 15h
Bit Bit Name
7 BIAS_OFF
6 SUM_OFF
5 AGC_OFF
4:3 IBR_DAC<1:0>
2 DAC_ON
1:0
AS3517 V17
Data Sheet, Confidential
Table 69 AudioSet_2 Register
Name Base Default
Second Audio Set Register
Powers various internal audio blocks UP or DOWN and controls bias current.
Attention: This control register resets and holds DAC related registers in reset. After activation the required register settings need to be re-programmed.
This register is reset at a DVDD-POR.
Default Access Bit Description
0 R/W
0
0
00
0
R/W
R/W
Power-down of the AGND bias. This bit can be set, if the AFE is used for digital data transfer and PMU functions only and all the analog audio blocks are not used.
0: bias enabled
1: bias disabled, for power saving in non audio mode
0: Mixer stage enabled (limits output signal to 1Vp)
1: Mixer stage powered down
Switches the signal limiter OFF (N20/N21)
0: automatic gain control for summing stage enabled
1: automatic gain control for summing stage disabled
Bias current settings for DAC:
00: 50%
01: 60%
10: 75%
11: 100%
AG still valid
Technical
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Offset: 16h
Bit Bit Name
7 LIN1MIX_OFF
6
5
4
3
2
1
0
LIN2MIX_OFF
MIC1MIX_OFF
MIC2MIX_OFF
DACMIX_OFF
ZCU_OFF
IBR_HPH
HPCM_ON
AS3517 V17
Data Sheet, Confidential
Table 70 AudioSet_3 Register
Name Base Default
Third Audio Set Register
Sets headphone output bias currents and operation modes and enables audio signal inputs to ΣR and ΣL.
This register is reset at a DVDD-POR.
0
0
0
0
0
0
0
Access Bit Description Default
0 R/W
R/W
R/W
R/W
Input from line input 1 to ΣR and ΣL
0: ON
1: OFF
Input from line input 2 to ΣR and ΣL
0: ON
1: OFF
Input from microphone 1 to ΣR and ΣL
0: ON
1: OFF
Input from microphone 2 to ΣR and ΣL
0: ON
1: OFF
R/W Input from DAC to ΣR and ΣL
R/W
0: ON
1: OFF zero
AG
1: zero cross update disabled
Bias current increase for the headphone amplifier depending R/W
R/W on load conditions
0: 100%
ams
Power-up of the headphone common mode buffer:
0: headphone CM buffer is switched off
content valid
Technical
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Table 71 PMU PVDD1 Register
Name
PMU PVDD1
Offset: 17h-1
Bit Bit Name
7 LDO_PVDD1_OFF
6
5 PROG_PVDD1
4:0 VSEL_PVDD1
Table 72 PMU PVDD2 Register
Name
PMU PVDD2
Offset: 17h-2
Bit Bit Name
7 LDO_PVDD2_OFF
6
5 PROG_PVDD2
4:0 VSEL_PVDD2
Default
00h
Base
2-wire serial
PVDD1 Low Drop-Out Regulator (LDO3) Control Register
This is an extended register and needs to be enabled by writing 001b to Reg. 18h first.
This register is reset at a DVDD-POR.
Default Access Bit Description
0 R/W Power-down of LDO for PVDD1
0: PVDD1 (LDO3) enable
1: PVDD1 (LDO3) power-down n/a 0
0 R/W Enables settings either selected by external pins (VPRGx) or
00000 R/W
Base
settings stored in the 17h-1 register
0: VPRGx pins controlled
1: Register controlled
The voltage select bits set the LDO output in 2 different resolution ranges
Range: 00h until 0Fh in 50mV steps
PVDD1=1.2V+VSEL_PVDD1*50mV
(1.2V until 1.95V)
Range: 10h until 1Fh in 100mV steps
PVDD1=2.0V+VSEL_PVDD1*100mV
(2.0V until 3.5V)
2-wire serial
AG
Default
00h
PVDD2 Low Drop-Out Regulator (LDO4) Control Register still
This is an extended register and needs to be enabled by writing 010b to Reg. 18h first.
valid
This register is reset at a DVDD-POR.
Default
0
0
0
Access Bit Description ams
R/W
0: VPRGx pins controlled
1: Register controlled
00000 R/W The voltage select bits set the LDO output in 2 different resolution ranges
Range: 00h until 0Fh in 50mV steps
PVDD2=1.2V+VSEL_PVDD1*50mV
(1.2V until 1.95V)
Range: 10h until 1Fh in 100mV steps
PVDD2=2.0V+VSEL_PVDD1*100mV
(2.0V until 3.5V)
Technical
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Table 73 PMU CVDD1 Register
Base
2-wire serial
Default
00h
Name
PMU CVDD1
Offset: 17h-3
CVDD1 DC/DC Buck Regulator Control Register
This is an extended register and needs to be enabled by writing 011b to Reg. 18h first.
This register is reset at a DVDD-POR.
Bit Bit Name Default Access Bit Description
7
6
5:0 VSEL_CVDD1
Table 74 PMU CVDD2 Register
Name
SKIP_OFF_CVDD1 0
PROG_CVDD1
PMU CVDD2
R/W Disables pulse skip mode
0: 170mA current force / pulse skip mode enabled
1: current force / pulse skip mode disabled (only ON without load)
Enables settings either selected by external pin (VPRGx) or 0 R/W
00000 R/W settings stored in the 17h-3 register
0: VPRGx pins controlled
1: Register controlled
The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down.
00000: DC/DC powered down valid
01h until 38h in 50mV steps
CVDD1=0.6V+VSEL_CVDD1*50mV
(0.65V until 3.4V)
Base
38h until 3Fh = 3.4V (no change)
2-wire serial
AG
Default
0x00 still
This is an extended register and needs to be enabled by writing 100bto Reg. 18h first.
This register is reset at a DVDD-POR.
Offset: 17h-4
Bit Bit Name
7
6
SKIP_OFF_CVDD2 0
PROG_CVDD2
Default
0
Access Bit Description ams
R/W
1: current force / pulse skip mode disabled (only ON without load)
content
1: Register controlled
The voltage select bits set the DC/DC output voltage level and 5:0 VSEL_CVDD2 00000 R/W power the DC/DC converter down.
00000: DC/DC powered down
01h until 38h in 50mV steps
CVDD2=0.6V+VSEL_CVDD1*50mV
(0.65V until 3.4V)
38h until 3Fh = 3.4V (no change)
Technical
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Table 75 PMU CVDD3 Register
Base
2-wire serial
Default
0x00
Name
PMU CVDD3
Offset: 17h-5
CVDD3 DC/DC Buck Regulator Control Register
This is an extended register and needs to be enabled by writing 101bto Reg. 18h first.
This register is reset at a DVDD-POR.
Bit Bit Name Default Access Bit Description
7 SKIP_OFF_CVDD3 0 R/W
4
1: current force / pulse skip mode disabled (only ON without load)
Enables settings either selected by external pin (VPRGx) or 6 PROG_CVDD3 0 R/W
5:0 VSEL_CVDD3
Table 76 PMU Hibernate Register
Name
PMU Hibernate
00000 R/W settings stored in the 17h-5 register
0: VPRGx pins controlled
1: Register controlled
The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down.
00000: DC/DC powered down valid
01h until 38h in 50mV steps
CVDD2=0.6V+VSEL_CVDD1*50mV
(0.65V until 3.4V)
Base
38h until 3Fh = 3.4V (no change)
2-wire serial
AG
Default
00h
Hibernation is started when writing to this register.
still
This is an extended register and needs to be enabled by writing 110b to Reg. 18h first.
Offset: 17h-6
Bit Bit Name
7
This register is reset at a DVDD-POR.
Default
0
6 KEEP_PVDD2 0
Access Bit Description ams
5 KEEP_PVDD1 0
0: power down PVDD1
1: keep PVDD1
KEEP_VLED 0 R/W
Disables pulse skip mode
0: 170mA current force / pulse skip mode enabled
Keeps the 15V DC/DC step-up for backlight switched on
0: power down CVDD1
1: keep CVDD1
3 KEEP_VBUS 0
0: power down CVDD2
1: keep CVDD2
2 KEEP_CVDD3 0
0: power down CVDD3
1: keep CVDD3
1 KEEP_CVDD2 0
0: power down CVDD2
1: keep CVDD2
0: power down CVDD1
1: keep CVDD1
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Table 77 PMU ENABLE Register
Base
2-wire serial
Default
00h
Name
PMU ENABLE
Offset: 18h
PMU Extension Enable Register
Enables 12h and 17h to write into extended registers and allows multiplexing supply voltages for monitoring via ADC10. This register is reset at a DVDD-POR.
Bit Bit Name Default Access Bit Description
7
6:4 DC_TEST
3 PMU_GATE 0
0:2 PMU_WR_ENABLE 000 n/a 0
000 R/W Allows multiplexing internal and external supply voltages to one DC test node which can be further multiplexed to ADC10.
The accuracy is 5mV/LSB (see reg. 2Eh)
000: not used
R/W
R/W
001: AVDD
010: DVDD
011: PVDD1
100: PVDD2
101: CVDD1
110: CVDD2
111: CVDD3
Enables all settings made in registers 0x17-x at once. If this bit is set, changes are activated as soon as they are written to the related register.
0: no change
AG
enables 12h-1 for OutCntr1 settings
010: enables 17h-2 for PVDD2 settings
still valid ams
enables 12h-2 for OutCntr2_SPDIF settings
011: enables 17h-3 for CVDD1 settings enables 12h-3 for PWM settings
100: enables 17h-4 for CVDD2 settings
101: enables 17h-5 for CVDD3 settings
content
Technical
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Table 78 RTC_WakeUp Register
Name Base Default
Offset: 19h
Adr. Byte Name
RTC Wake-Up and SRAM Register
Sets and enables the RTC wake-up counter and programs the 128bit SRAM. 3 bytes need to be written in a sequence to set the counter. The 3-byte sequence allows to set the counter to every value between 1sec and 8388608sec (=97 days). The MSB of the
3 rd byte enables the wake-up counter. Byte 4 …19 will program the static 128bit SRAM which is supplied by RVDD. This register is reset at a RVDD-POR.
Default Access Bit Description
(1 st write to 0x19 is byte 0)
0000 0010: 2sec
0000 0100: 4sec
0000 1000: 8sec
0001 0000: 16sec
0010 0000: 32sec
0100 0000: 64sec
1000 0000: 128sec
(2 nd write to 0x19 is byte 1)
(3 rd write to 0x19 is byte 2)
7:0 SRAM_128
(4 th … 19 th write to
0x19 programs the
128bit static SRAM)
R/W
0000 0010: 512sec
0000 0100: 1 024sec
0000 1000: 2 048sec
0001 0000: 4 096sec
AG
000 0010: 131 072sec
000 0100: 262 144sec
000 1000: 524 288sec
001 0000: 1 048 576sec
ams
00000000 R/W xxxx xxxxb = byte 4
: xxxx xxxxb = byte 19
still valid
Technical
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Table 79 USB_UTIL Register
Name Base Default
Offset: 1Ah
USB Utility Register
Controls VBUS output voltage and the external transistor as well as special mode bits for the DCDC step-down converters
This register is reset at a DVDD-POR.
Default Access Bit Description Bit Bit Name
7:6 I_PMOS_GATE 00 R/W Sets the gate current level into the external PMOS transistor to control the inrush current to VBUS
00: 1µA
01: 2µA
5 DCDC_PS_OFF 0
3:2 VBUS_COMP_TH
1
0
VBUS_SKIP_ON
VBUS_ON
00
0
0
R/W
R/W Disables 200uA power saving in skip mode
R/W
10: 3µA
11: 4µA
0: Power savings ON
1: Power savings OFF switched fully on, if the regulator cannot achieve the programmed output voltage anymore.
0: PMOS fully ON
1: PMOS switching
Sets the threshold for the VBUS comparator. The output can
00: 4.5V
01: 3.18V
10: 1.5V
11: 0.6V
AG still
Enables the skip mode for the VBUS 1:2 charge pump which
valid
R/W increases efficiency for small loads connected to VBUS supply, but increases VBUS supply ripple
ams
Switches the VBUS output voltage ON and OFF
0: VBUS output voltage disabled
1: VBUS output voltage enabled
content
Technical
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Offset: 1Bh
Bit Bit Name
7 DIM_UP_DOWN
6:5 DIM_RATE
4:0 I_BACKLIGHT
Table 81 I2S Register
Name
Offset: 1Ch
Bit Bit Name
7:0 I2S_DIVIDER
AS3517 V17
Data Sheet, Confidential
Table 80 DCDC15 Register
Name Base Default
15V DCDC Step-up Control Register
Controls the back-light current and back-light dim rate.
This register is reset at a DVDD-POR.
Default
0
00
00000
R/W
R/W
Access Bit Description
R/W Starts dimming UP/DOWN or switches LED back-light ON/OFF when DIM_RATE = 00b
0: dim DOWN
1: dim UP
Sets the dim rate of the LED back-light current from 0mA to
I_BACKLIGHT and vice versa
00: no dimming (immediate ON/OFF)
01: 150ms
10: 300ms
11: 500ms
Sets the current into pin ISINK in 1.25mA steps (internal current source to control LED backlight current). Setting
11111b enables the voltage feedback mode to supply e.g.
OLEDs with a constant voltage supply.
00000: DCDC15 switched off
00001: 1.25mA
..
AG still valid
Base ams
Default
Contains lower 8 bits for I2S master mode clock generation divider.
This register is reset at a DVDD-POR.
Default
00h
Access
R/W
content
Technical
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Table 82 I2S_PLL_OSC Register
Name Base Default
Offset: 1Dh
I2S, PLL and Oscillator Mode Control Registers
This register is reset at a DVDD-POR.
Bit Bit Name Default
7 I2S_MASTER_ON 0
6
5
OSC24_PD
I2S_DIRECT
4:3 Q24M_DIVIDER
2:1 PLL_MODE
0 I2S_DIVIDER_8
0
0
00
00
0
Access Bit Description
R/W Switched the I2S master mode on
0: I2S slave mode operation
1: I2S master mode
R/W Powers the 12-24MHz oscillator down. For operation a 12-
24MHz crystal needs to be connected to pins XIN24/XOUT24.
0: 12-24MHz oscillator enabled
R/W
R/W
R/W
1: powered down
Switches the PWGD pin to an input for an external master clock (e.g. coming form the CPU). This bit overwrites prior setting for the PWGD pin. Only valid fro I2S slave mode operation.
0: disabled
valid
1: enabled
Sets the divider for Q24M clock output or powers Q24M clock output buffer down
00: divide by 1
01:divide by 2
11: OFF
AG still
Preset of PLL bias for the following sampling frequencies
00: reserved
01:16-48kS
10: 8-12kS
R/W
11: reserved
Bit 8 of I2S_DIVIDER (Reg. 1Ch)
content
Technical
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Offset: 20h
Bit Bit Name
7:4 Version <3:0>
3 HEARTBEAT_ON
2
1
0
JTEMP_OFF
WATCHDOG_ON
PWR_HOLD
AS3517 V17
Data Sheet, Confidential
Table 83 System Register
Name Base Default
System Settings Register
Controls the powering down conditions of the AFE. The IC can also be emergency shut down by a high level for 5.4sec (or 10.9sec see reg. 24h) at the PWRUP input pin
This register is reset at a DVDD-POR.
0
0
0
1
Access Bit Description Default
1111 R AFE number to identify the design version
R/W
1111: revision 7
Heartbeat (HBT) Watchdog
The watchdog counter will be reset by a rising edge at the HBT
R/W
R/W input pin which has to occur at least every 500ms. If the watchdog counter is not reset, the AFE will be powered down.
When start-up sequence #16-#25 is selected, no power down is performed but a reset invoked via the XRES output pin
(pulse duration = 86µs typ., 60µs min)
0: HBT watchdog is disabled valid
1: HBT watchdog is enabled
Junction temperature supervision (level can be set in register
21h)
0: temperature supervision enabled
1: temperature supervision disabled
AG still
counter is not reset, the AFE will be powered down.
0: watchdog is disabled
1: watchdog is enabled
R/W
ams
0: power up hold is cleared and AFE is powered down
1: set to on after power on content
Technical
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Table 84 Supervisor Register
Name Base Default
Offset: 21h
Bit Bit Name
7:5 BVDD_SUP
4:0 JTEMP_SUP
Table 85 Charger Register
Supervisor Register
Sets the threshold levels of battery supply and junction temperature supervision.
This register is reset at a DVDD-POR.
Default
000
00000 R/W
Access Bit Description
R/W Sets the threshold (brown-out voltage) at the BVDD input pin for an interrupt at low battery condition
V_BrownOut=2.74+BVDD_Sup*60mV
000: 2.74V
001: 2.80V
…
110: 3.10V
111: 3.16V
Sets the threshold for junction temperature emergency shutdown and junction temperature interrupt
Invoke shutdown at: JTemp_SD=140-JTEMP_Sup*5
°C
Invoke interrupt at: JTemp_IRQ=120-JTEMP_Sup*5
°C
AG still valid
Name
Offset: 22h
Bit Bit Name
6:4 CHG_I
Sets the charging current, end of charge voltage and battery temp. supervision.
This register is reset at a DVDD-POR.
000
Access
R/W
content
111: 400 mA
110: 350 mA
Default Base ams
Default
7 BAT_TEMP_OFF 0 R/W 0: enables 15uA supply for external 100k NTC resistor
101: 300 mA
100: 250 mA
011: 200 mA
3:1 CHG_V 000 R/W
010: 150 mA
001: 100 mA
000: 50 mA
set maximum charger voltage in 50mV steps
111: 4.25 V
110: 4.2 V
..
001: 3.95 V
000: 3.9 V
R/W 0: enables Charger
1: disables Charger
0
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Table 86 First Interrupt Register
Name Base Default
Offset: 23h
6
5
4
3
2
1
0
First Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.
Default Access Bit Description Bit Bit Name
7 CVDD2_EN_SD
CVDD2_UNDER
CVDD2_EN_IRQ
CVDD2_OVER
CVDD1_EN_SD
CVDD1_UNDER
CVDD1_EN_IRQ
CVDD1_OVER
PVDD2_EN_SD
PVDD2_UNDER
PVDD2_EN_IRQ
PVDD2_OVER
PVDD1_EN_SD
PVDD1_UNDER
PVDD1_EN_IRQ
0 x
0 x
0 x
0 x
0 x
0 x
0 x
0
W
R
W
R
W
R
W
R
W
ams
W
Invokes shut-down of AFE when a –10% under-voltage spike at
This bit is set when a –5% under-voltage at PVDD2 occurs
PVDD2
1: enable
This bit is set when a +5% over-voltage at PVDD2 occurs R
W Invokes shut-down of AFE when a –10% under-voltage spike at
PVDD1 occurs
0: disable
1: enable
This bit is set when a –5% under-voltage at PVDD1 occurs R
W
PVDD1_OVER x R
Technical
Invokes shut-down of AFE when a –10% under-voltage spike at
CVDD2 occurs
0: disable
1: enable
This bit is set when a –5% under-voltage at CVDD1 occurs
Enables interrupt for over-voltage/under-voltage supervision of
CVDD2
0: disable
1: enable
valid
This bit is set when a +8% over-voltage at CVDD1 occurs
Invokes shut-down of AFE when a –10% under-voltage spike at
CVDD1 occurs
0: disable
1: enable
Enables interrupt for over-voltage/under-voltage supervision of
CVDD1
0: disable
1: enable
AG still
This bit is set when a +8% over-voltage at CVDD1 occurs
Enables interrupt for over-voltage/under-voltage supervision of
PVDD1
0: disable
1: enable
This bit is set when a +5% over-voltage at PVDD1 occurs
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Table 87 Second Interrupt Register
Name Base Default
Offset: 24h
Second Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.
Default Access Bit Description Bit Bit Name
7
1
0
SD_TIME
6
5 PWRUP_IRQ
4 WAKEUP_IRQ
3 VOXM2_IRQ
2 VOXM1_IRQ
CVDD3_EN_SD
CVDD3_UNDER
CVDD3_EN_IRQ
0
0
0 x
0
X
0 x
0 x
0 x
0 W
R
W
R/W Control bit which sets the emergency shut-down time from
5.4sec to 10.9sec. The shut-down of AS3517 is invoked by a high signal at the PWRUP input pin.
W
R
W
R
0: 5.4sec
1: 10.9sec n/a
W Enables interrupt which is invoked whenever a high signal at the PWRUP input pin occurs
0: disable
valid
1: enable
This bit is set whenever a high level of min. BVDD/3 at the
PWRUP input pin occurs (PWRUP pin is commonly connected to the power-up button)
Enables interrupt which is invoked whenever a wake-up from
0: disable
1: enable
AG still
This bit is set when a wake-up has been invoked by the RTC wake-up counter.
Enables interrupt which is invoked by reaching a voltage
R
R
W threshold at MIC2 input (voice activation)
0: disable
This bit is set when a voltage threshold of 5mV
RMS
(unfiltered) at MIC2 has been reached (voice activation)
content
This bit is set when a voltage threshold of 5mV
RMS
(unfiltered) at MIC1 has been reached (voice activation)
Invokes shut-down of AFE when a –10% under-voltage spike at
CVDD2 occurs
0: disable
1: enable
This bit is set when a –5% under-voltage at CVDD1 occurs
Enables interrupt for over-voltage/under-voltage supervision of
CVDD2
0: disable
1: enable
This bit is set when a +8% over-voltage at CVDD1 occurs CVDD3_OVER x R
Technical
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Table 88 Third Interrupt Register
Name Base Default
Offset: 25h
Third Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.
Default Access Bit Description Bit Bit Name
7 BATTEMP_HIGH
(level)
6 CHG_EOC
(level)
5
4 CHG_CHANGED
(status change)
3
2 USB_CHANGED
(status change)
CHG_STATUS
USB_STATUS
0 x
0 x x
0 x x
0 x
W Battery over-temperature interrupt setting.
0: disable
1: enable interrupt if battery temperature exceeds 45°C
R
W
R
The interrupt must not be enabled if the charger block and battery temperature supervision is disabled
Battery over-temperature interrupt reading
0: battery temperature below 45°C
1: battery temperature was too high and the charger was turned off. The charger will be turned on again, when the
valid
temperature gets below 42°C
Battery end of charge interrupt setting
0: disable
1: enable
The interrupt must not be enabled if the charger block is disabled
AG still
1: charging is complete, charging current is below 10% of nominal current, turn off charger
To check end of charge again the charger has to be turned on.
R
ams
R
0: no charger input source connected
1: charger input source connected, also valid if charger is
Charger input status change interrupt setting
0: disable
Charger input status change interrupt reading
1: charger input status changed, check CHG_STATUS
0: no USB input connected R
1: USB input connected, also valid if USB is connected during wakeup. The threshold can be set in the USB_UTIL register
(1Ah)
W
R
Technical
USB input status change interrupt setting
0: disable
1: enables an interrupt on a low to high or high to low change of VBUS pin. The threshold can be set in the USB_UTIL register (1Ah)
USB input status change interrupt reading
0: USB input status not changed
1: USB input status changed, check USB_STATUS
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Name
Offset: 25h
Bit Bit Name
1 RVDD_LOW
(level)
0 BVDD_LOW
(level)
Base Default
x
0 x
Third Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.
Default
0
R
W
R
Access Bit Description
W Real time clock supply (RVDD) under-voltage interrupt setting
0: disable
1: enable
Real time clock supply interrupt reading
0: RTC supply o.k.
1: RTC supply (RVDD) was low, RTC not longer valid
The interrupt gets set in hibernation or during power-up even if the interrupt is not enabled thus allowing to recognise a change of the battery connected to BVDDR during hibernation or shutdown. For a valid reading, the interrupt has to be enabled first.
valid
BVDD under-voltage supervisor interrupt setting
0: disable
1: enable
BVDD supervisor interrupt setting
0: BVDD is above brown out level
AG
Technical
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Table 89 Fourth Interrupt Register
Name Base Default
Offset: 26h
Fourth Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.
Default Access Bit Description Bit Bit Name
7 JTEMP_HIGH
(level)
6
5 HPH_OVC
(level)
4 I2S_STATUS
3 I2S_CHANGED
(status change)
2 MIC2_CONNECT
(level)
1 MIC1_CONNECT
(level) x
0
0 W Supervisor junction over-temperature interrupt setting
0: disable
1: enable x
0 x x
0 x
0 x
0
R
R
R n/a
W
Supervisor junction over-temperature interrupt reading
0: chip temperature below threshold
1: chip temperature has reached the threshold
The threshold can be set in the SUPERVISOR register (21h)
Headphone over-current interrupt setting
valid
0: disable
1: enable
The interrupt must not be enabled if the headphone block is disabled
Headphone over-current interrupt reading
AG still
pin or 300mA at HPCM pin. The shut-down time can be set in
HPH_OUT_R register (0x02)
0: no LRCK on I2S interface detected
W
ams
W
1: LRCK on I2S interface present
I2S input status change interrupt setting
1: enable
I2S input status change interrupt reading
Microphone 2 connect detection interrupt setting
1: enable
Microphone 2 connect detection interrupt reading R
0: no microphone connected to MIC input
1: microphone connected at MIC input.
This interrupt is only invoked when the microphone stage is powered down. The IRQ will be released after enabling the microphone stage.
Detecting a microphone during operation has to be done by measuring the supply current.
W
R
Technical
Microphone 1 connect detection interrupt setting
0: disable
1: enable
Microphone 1 connect detection interrupt reading
0: no microphone connected to MIC input
1: microphone connected at MIC input.
This interrupt is only invoked when the microphone stage is powered down. The IRQ will be released after enabling the microphone stage.
Detecting a microphone during operation has to be done by measuring the supply current.
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Name Base Default
Offset: 26h
Bit Bit Name
0 HPH_CONNECT
(level) x
Fourth Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.
Default
0
R
Access Bit Description
W Headphone connect detection interrupt setting
0: disable
1: enable
Headphone connect detection interrupt reading
0: no headphone connected
1: headphone connected
This interrupt is only invoked when the headphone stage is powered down. The IRQ will be released after enabling the headphone stage.
Detecting a headphone during operation is not possible.
valid
AG still
Technical
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Table 90 Fifth Interupt Register
Name Base Default
Offset: 27h
Bit Bit Name
7:6 T_DEB<1:0>
5
4
XIRQ_AH
XIRQ_PP
3 REM2_DET
(edge)
2 REM1_DET
(edge)
1 RTC_UPDATE
(edge)
0 ADC_EOC
(edge)
0
0
0 x
0 x
0 x
0 x
Fifth Interrupt Register
Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.
Default Access Bit Description
00
R
W
R/W
R/W
R/W
W
R
W
Sets the USB and Charger connect de-bounce time:
00: 340ms
01: 170ms
10: 85ms
11: 4ms
Sets the active output state of the XIRQ line:
0: IRQ is active low
1: IRQ is active high
Sets the XIRQ output buffer type:
0: IRQ output is open drain
1: IRQ output is push pull
Microphone 2 remote key press detection interrupt setting
0: disable
1: enable
still
1: Microphone 2 supply current got increased, remote key press detected -> measure MICS supply current
Microphone 1 remote key press detection interrupt setting
0: disable
AG valid
R
R
W
1: enable
Microphone 1 remote key press detection interrupt reading
1: Microphone 1 supply current got increased, remote key press detected -> measure MICS supply current
content
0: no RTC interrupt occurred
1: RTC timer interrupt occurred. Selecting minute or second interrupt can be done via RTCT register (29h)
ADC end of conversion interrupt setting
0: disable
1: enable
ADC end of conversion interrupt reading
0: ADC conversion not finished
1: ADC conversion finished. Read out ADC_0 and ADC_1 register to get the result (2Eh & 2Fh)
Technical
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
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Table 91 RTCV Register
Name Base Default
Offset: 28h
Bit Bit Name
7:4 V_RVDD
3:2
1 RTC_ON
0
Name
OSC32_ON
Table 92 RTCV Register
Offset: 29h
Bit Bit Name
7 IRQ_MIN
6:0 RTC_TBC<6:0>
Table 93 RTC_0 to RTC_3 Register
RTC Voltage Register
This register is reset at a DVDD-POR.
Default Access Bit Description
0010 R/W Selects the RVDD output voltage level (1V to 2.5V)
Default: 1.2V
RVDD= 1V + V_RVDD*0.1V
1 R/W RTC counter clock control:
0: Disable clock for RTC counter
1 R/W
1: Enables clock for RTC counter
Switches the 32kHz oscillator ON A 32kHz watch crystal need to be connected to pins XIN32/XOUT32
0: Disable 32kHz oscillator
1: Enables 32kHz oscillator
valid
Default
0
Base
RTC Timing Register
This register is reset at a RVDD-POR.
Access
R/W 0: generates an interrupt every second
1000000 R/W
AG
Default
1: generates an interrupt every minute
still
The interrupt has to be enable in IRQ_ENRD_4 (27h)
These bits are used to correct the inaccuracy of the used
32kHz crystal.
ams
…
111110: 126 (960.8ppm)
111111: 127 (968.4ppm)
Base
2-wire serial
Default
00 00 00 00h
Name
RTC_0 to RTC_3
Offset: 2Ah to 2Dh
RTC Time-base Seconds Register
This register is reset at a RVDD-POR.
Adr. Byte Name Default
2Ah RTC_0
2Bh RTC_1
00h
00h
Access Bit Description
R/W
R/W
2Ch RTC_2
2Dh RTC_3
00h
00h
R/W
R/W
Technical
QRTC<7:0>; RTC seconds bits 0 to 7
QRTC<15:8>; RTC seconds bits 8 to 15
QRTC<23:9>; RTC seconds bits 9 to 23
QRTC<31:24>; RTC seconds bits 24 to 31
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
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Table 94 ADC_0 Register
Name
ADC_0
Base
2-wire serial
Default
0000 00xx
Offset: 2Eh
Bit Bit Name
7:4 ADC_Source
3:2
1:0 ADC<9:8>
Table 95 ADC_1 Register
First 10-bit ADC Register
Writing to this register will start the measurement of the selected source.
This register is reset at a DVDD-POR, exception are bit 8 and 9.
Default Access Bit Description
00000000 R/W
00 xx
Selects ADC input source
0000: CHGOUT
0001: BVDDR
0010: defined by DC_TEST in register 0x18
0011: CHGIN
0100: VBUS
0101: BatTemp
0110: MIC1S
0111: MIC2S
1000: VBE_1uA
1001: VBE_2uA
1010: I_MIC1S
1011: I_MIC1S
1100: RVDD
1101: reserved
1110: reserved
1101: reserved n/a
R/W
Base
AG still valid
Default Name
Name xxxx xxxx ADC_1
Offset: 2Fh
Bit Bit Name
7:0 ADC<7:0>
Table 96 UID_0 to UID_7 Register
Second 10-bit ADC Register
Default
xxxx xxxx
2-wire serial
Access Bit Description
R/W
Base
ADC result bit 7 to 0
content
2-wire serial
Unique ID Register n/a UID_0 to UID_7
Offset: 38h to 3Fh
This register is read only and is not reset.
Adr. Byte Name Default Access Bit Description
38h UID_0
39h UID_1
3Ah UID_2
3Bh UID_3
3Ch UID_4 n/a n/a n/a n/a n/a
R
R
R
R
R
3Dh UID_5 n/a R
3Eh UID_6
3Fh UID_7 n/a n/a
R
R
Technical
Unique ID byte 0
Unique ID byte 1
Unique ID byte 2
Unique ID byte 3
Unique ID byte 4
Unique ID byte 5
Unique ID byte 6
Unique ID byte 7
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
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10 Typical Application
Figure 32 Typical Application Schematic 1
AG still valid
Technical
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
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Figure 33 Typical Application Schematic 2
AG still valid
Technical
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
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11 Copyright
Copyright © 2008, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks of their respective companies.
12 Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifesupport or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of
valid
profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
13 Contact Information
still
Headquarters:
AG
austriamicrosystems AG
Business Unit Communications
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 500 0
F. +43 (0) 3136 5692 [email protected] www.austriamicrosystems.com
Technical
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www.austriamicrosystems.com
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