AMS AS3518 Datasheet

austriamicrosystems AG is now ams AG

The technical content of this austriamicrosystems datasheet is still valid.

Contact information:

Headquarters:

ams AG

Tobelbaderstrasse 30

8141 Unterpremstaetten, Austria

Tel: +43 (0) 3136 500 0 e-Mail: [email protected]

Please visit our website at

www.ams.com

AS3518 V23

Data Sheet, Confidential tsU wan

AS3518

Stereo Audio Codec with enhanced System Power Management

Data Sheet

1 General Description 2 Key Features

2.1 Audio

The AS3518 is an ultra low power stereo audio codec and is designed for Portable Digital Audio

Applications.



Audio power consumption:

It allows playback and recording in CD quality. With one microphone (including pre-amplifier and supply for an electret microphone) and three line inputs, it allows connecting a variety of audio inputs. The different audio signals can be mixed via an

8-channel mixer and fed to either a headphone output for 16

Ω

/32

Ω

headsets or a line output.

Further the device offers advanced power management functions. All necessary ICs and peripherals in a Digital Audio Player are supplied by the AS3518. It features 2 DCDC converters for core and memory/periphery supply as well as 4 LDOs.

The different regulated supply voltages are programmable via the serial control interface.

The step-up converter for the backlight can operate up to 15V (with an external transistor even higher) in voltage and current control mode. An internal

- 17mW: 95dB DAC to Headphone @ 2.9V, 32

Ω



Sigma Delta Converters

- DAC:



95dB SNR (‘A’ weighted) @ 2.9V

- ADC:



92dB SNR (‘A’ weighted) @ 2.9V

valid

- Sampling Frequency:



DAC: 8-48kHz



ADC: 8-48kHz



1 Microphone Input

- 3 gain pre-setting (28dB/34dB/40dB) and AGC

AG still

- supply for electret microphone

- remote control by switch



3 Line Inputs voltage protection is limiting the output voltage in the case of external component failures.

AS3518 also contains a Li-Ion battery charger with charging. The maximum charging current is 460mA.

(PLL) which generates the needed internal CODEC master clock. I2S Frame and shift-clock have to be applied from the processor for playback and recording.

Further the AS3518 has an independent 32kHz real

- volume control via serial interface

- 32 steps @1.5dB and MUTE

- stereo or 2x mono or mono differential



Audio Mixer



- 8 channel input/output mixer with AGC

- volume control via serial interface

- 32 steps @1.5dB and MUTE

- 1Vp @10k

Ω time clock (RTC) on chip which allows a complete power down of the system CPU while only

- Stereo 2*5mW to 16ohm consuming less than 1µA. An internal switch

- Differential 10mW to 32ohm (earpiece) automatically switches between the RTC backup-



High Efficiency Headphone Amplifier battery and main battery supply.

The single supply voltage may vary from 1.0V to

5.5V. For operations below 3.0V the integrated step-up converter is used to generate a 3V supply rail.

Technical

- volume control via serial interface

- 32 steps @1.5dB and MUTE

- 2x60mW @16

Ω

driver capability@ 2.9V supply

- THD -72dB @32

Ω

; 2.9V

- headphone and over-current detection

- phantom ground eliminates large capacitors

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

1

-

84

AS3518 V23

Data Sheet, Confidential

2.2 Power Management



Voltage Generation

- step up for system supply (3.0-3.6V, 150mA)

- step down for CPU core (0.65V-3.4V, 250mA)

- step down for peripheral (0.65V-3.4V, 250mA)

- LDO1 for AFE supply (2.9V, 100mA)

- LDO2 for AFE supply (2.9V, 100mA)

- LDO3 for peripherals (1.2V-3.5V, 100/200mA)

- LDO4 for peripherals (1.2V-3.5V, 100/200mA)

- VBUS comparator

- separate input for LDO3

- power supply supervision

- hibernation modes

- 5sec and 10sec emergency shut-down



Backlight Driver

- step up for backlight (15V (25V))

- current control mode (1.2-36mA)

- voltage control mode

- 1 current sink

- automatic dimming

- over-voltage protection



Battery Charger

- automatic trickle charge (55mA)

- prog. constant current charging (55-460mA)

- prog. constant voltage charging (3.9V-4.25V)

- current limitation for USB mode

2.3 General



Supervisor

- automatic battery monitoring with interrupt generation and selectable warning level

- automatic temperature monitoring with interrupt generation and selectable warning and shutdown levels



Real Time Clock

- ultra low power 32kHz oscillator

- 32bit RTC sec counter, 96 days auto wake-up

- selectable alarm (seconds or minutes)

- 128bit free SRAM for random settings

- 32kHz clock output to peripheral

- voltage generation

- trim able oscillator

- <1uA total power consumption



General Purpose ADC

valid

- 10bit resolution

- 19 inputs analog multiplexer



Interfaces



- reset pin with selectable delay, power good pin

AG

3 Applications

Portable Digital Audio/Video Player and Recorder

PDA, Smartphone

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

2

-

84

AS3518 V23

Data Sheet, Confidential

Figure 1 AS3518 Block Diagram

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

3

-

84

AS3518 V23

Data Sheet, Confidential

Contents

1 General Description ......................................................................................................................................... 1

2 Key Features .................................................................................................................................................... 1

2.1

Audio......................................................................................................................................................... 1

2.2

Power Management .................................................................................................................................. 2

2.3

General ..................................................................................................................................................... 2

3 Applications ...................................................................................................................................................... 2

4 Pinout ............................................................................................................................................................... 6

4.1

Pin Assignment CTBGA64 ........................................................................................................................ 6

4.2

Pin Description .......................................................................................................................................... 7

5 Absolute Maximum Ratings (Non-Operating)................................................................................................... 9

6 Electrical Characteristics ................................................................................................................................ 10

6.1

General Parameter ................................................................................................................................. 10

6.2

Operating Currents ................................................................................................................................. 11

6.3

Temperature Range ................................................................................................................................ 11

6.4

Audio Specification ................................................................................................................................. 12

7 Typical Operating Characteristics .................................................................................................................. 13

8 Detailed Description ....................................................................................................................................... 14

8.1

Audio Functions ...................................................................................................................................... 14

8.1.1

Audio Line Inputs (3x) ...................................................................................................................... 14

8.1.2

Microphone Input ............................................................................................................................. 16

8.1.7

8.2

valid

8.1.3

Audio Line Output ............................................................................................................................ 18

8.1.4

Headphone Output .......................................................................................................................... 19

8.1.5

DAC, ADC and I2S Digital Audio Interface ...................................................................................... 21

8.1.6

Audio Output Mixer .......................................................................................................................... 24

8.2.1

8.2.2

8.2.3

2-Wire-Serial Control Interface ........................................................................................................ 25

AG still

8.2.4

Charger ............................................................................................................................................ 37

8.2.5

15V Step-Up Converter ................................................................................................................... 39

8.3

SYSTEM Functions................................................................................................................................. 41

8.3.1

SYSTEM .......................................................................................................................................... 41

8.3.2

Hibernation ...................................................................................................................................... 43

8.3.3

8.3.4

8.3.5

8.3.6

ams

8.3.7

Unique ID Code (64 bit OTP ROM) ................................................................................................. 48

8.4

Register Description................................................................................................................................ 49

9 Application Information .................................................................................................................................. 78

10 Package Drawings and Marking ................................................................................................................. 79

10.1

CTBGA64 ............................................................................................................................................ 79

10.2

Wafer & Die ......................................................................................................................................... 82

11 Ordering Information .................................................................................................................................. 83

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

4

-

84

AS3518 V23

Data Sheet, Confidential

Revision History

Revision

1.0

1.1

1.11

Date Owner

5.10.2007 pkm

13.8.2007 pkm

24.4.2012 pkm

Description

changed chip version to V22, in system register and ordering information changed PVDD1 start-up voltage to 3.3V added audio block typical current consumptions extended features description added PMOS description for DCDC3V extended ordering information for tray delivery updated application information changed chip version to V23, in system register and ordering information corrected ordering information

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

5

-

84

AS3518 V23

Data Sheet, Confidential

4 Pinout

4.1 Pin Assignment CTBGA64

Figure 2 Ball Assignment CTBGA64

1 2 3 4

A

SW15V VSS3V SW3V BVDD3V

5

HPL

6

VSSH

7

HPCM

8

LOUTR

A

B

BVDDC1 VSS15V VB1V

C

LXC1 CVDD1 ISINK

CRES

VBUS

HPR

LIN1R

BVDDH HPGND LOUTL

B valid

C

MICN MICP MICS

D

CVSS12 HBT Q32K PWGD LIN2R AGND

D

E

LXC2

F

BVDDC2

G

PVDD2

CVDD2

BVDD

PVDD1

XIRQ LRCK SDI LIN2L LIN3L

BVDDP1 ams

BATTEMP DVDD

SDO

CSDA

VPRG1 content

AVDD

RVDD

VREF

E

AVSS

F

BVDDR

G

H

CHGOUT CHGIN

1 2

DVSS

3

FVDD

4

CSCL

5

PWRUP XIN32K XOUT32K

H

6 7 8

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

6

-

84

AS3518 V23

Data Sheet, Confidential

4.2 Pin Description CTBGA64

Table 1 Pinlist CTBGA64

Ball PinName Type Function

D8 AGND

F7 AVDD

F8 AVSS

G3 BATTEMP

A4 BVDD3V

F2 BVDD

B6 BVDDH

B1 BVDDC1

F1 BVDDC2

F3 BVDDP1

G8 BVDDR

H2 CHGIN

H1 CHGOUT

B4 CRES

H5 CSCL

G5 CSDA

C2 CVDD1

E2 CVDD2

D1 CVSS12

G4 DVDD

H3 DVSS

H4 FVDD

D2 HBT

A7 HPCM

B7 HPGND

A5 HPL

B5 HPR

C3 ISINK

D5 LIN1L

C5 LIN1R

E6 LIN2L

D6 LIN2R

E7 LIN3L

D7 LIN3R

B8 LOUTL

A8 LOUTR

E4 LRCLK

Analog Input

Analog Output

Analog Output

Digital input with pull down

C1 LXC1

E1 LXC2

Digital output

Digital output

C8 MICN Analog Input

C7 MICP

C6 MICS

G2 PVDD1

G1 PVDD2

Analog Input

Analog I/O

Analog Output

D4 PWGD Digital I/O multiplexed

H6 PWRUP

D3 Q32K

Analog I/O

Supply

Supply

Analog I/O

Supply

Supply

Supply

Supply

Supply

Supply

Supply

Analog Input

Analog Output

Analog I/O

Digital input with pull up

Digital I/O with pull up

Analog Input

Analog Input

Supply

Supply

Supply

Supply

Digital input with pull down

Analog Output

Analog I/O

Analog Output

Analog Output

Analog Output

Analog Input

Analog Input

Analog Input

Analog Input

Analog Input

Digital input with pull down

Digital output multiplexed

Analog Reference Voltage (AVDD/2) buffer cap terminal

Analog Circuit VDD, connected to LDO1 on BGA substrate

Analog Circuit VSS

Charger Battery Temperature Sensor input (100kΩ NTC)

Positive (Battery) Supply Terminal, 5.5V max.

Positive (Battery) Supply Terminal, 5.5V max.

Positive (Battery) Supply Terminal of HP Amplifier, 5.5V max.

Positive (Battery) Supply Terminal of DCDC1, 5.5V max.

Positive (Battery) Supply Terminal of DCDC2, 5.5V max.

Positive (Battery) Supply Terminal of LDO3, 5.5V max.

RTC Positive (Battery) Supply terminal, 5.5V max

Charger Positive Supply Terminal, 5.5V max

Charger Output prog. for Ichg 50-480mA or Vchg 3.9-4.25V

valid

Capacitor input for setting detect delay

Clock Input of two wire interface

Data I/O of two wire interface

CVDD1 and Feedback pin

AG still

Digital Circuit VDD, connected to LDO2 on BGA substrate

ADC&DAC Digital Circuit VDD (1.8-3.6V)

Heartbeat Input for CPU supervision

Headphone Common GND Output for DC-coupled speakers

ams

Line Input 1 Right Channel

Line Input 2 Right Channel

Line Input 3 Left Channel

Line Input 3 Right Channel

Line Output Left Channel

Line Output Right Channel

I2S Left/Right Clock

CVDD1 StepDown switch output to coil

CVDD2 StepDown switch output to coil

Microphone Input N

Microphone Input P

Microphone Supply (2.95V) / Remote Input

LDO3 Regulator Output

LDO4 Regulator Output

Power Good, SPDIF, PLL clock, PWM digital output.

Configurable as open drain or push pull.

Master CLK digital input (e.g. from CPU)

Power Up input

32kHz Clock output, SPDIF, PLL clock, PWM. Configurable as

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

7

-

84

AS3518 V23

Data Sheet, Confidential

Ball PinName Type

G7 RVDD

F4 SCLK

E5 SDI

F5 SDO

A1 SW15V

A3 SW3V

B3 VB1V

F6 VPRG1

E8 VREF

C4 VBUS

B2 VSS15V

A2 VSS3V

A6 VSSH

H7 XIN32K

E3 XIRQ

H8 XOUT32K

G6 XRES

Analog Output

Digital input with pull down

Digital input with pull down

Digital output

Analog Output

Aout

Supply

Analog Input

Analog I/O

Analog I/O

Supply

Supply

Supply

Analog I/O

Digital output

Analog I/O

Digital output open drain

Function

open drain or push pull.

RTC Supply Regulator Output prog. to 1.0-2.5V

I2S Shift Clock

I2S Data Input to DAC

I2S Data output from ADC

DCDC15V switch terminal

DCDC3V Switch terminal

Battery supply input for single cell application

5 State Prog Input to define power up sequence

Analog Reference ( filtered AVDD) decoupling cap terminal

USB supply terminal for supervision

DCDC15V Neg. Supply terminal

DCDC3V Neg. Supply terminal

Headphone Amplifier Neg. Supply terminal

32kHz RTC Oscillator Crystal terminal

Interrupt Request Output. Configurable as open drain or push pull, active high or active low

32kHz RTC Oscillator Crystal terminal

valid

Reset Output

AG still

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

8

-

84

AS3518 V23

Data Sheet, Confidential

5 Absolute Maximum Ratings (Non-Operating)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Electrical Characteristics” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions.

Table 2 Absolute Maximum Ratings

Symbol Parameter Min Max Unit Comments

V

IN_VB1V single cell supply voltage -0.5 5.0 V Applicable for pin VB1V

V

V

V

V

IN_5V

IN_3V

IN_SW15

V

IN_VSS

5V pins

3V pins

15V pin

Voltage difference at VSS terminals

IN_DVDD

3.3V pins with diode to DVDD

V

IN_xDVDD pins with no diode to DVDD

V

IN_AVDD

3.3V pins with diode to AVDD

-0.5

-0.5

-0.5

-0.5

-0.5

-0.5

-0.5

7.0

5.0

17

V

V

V

Applicable for pins BVDD, BVDDH,

BVDDC1, BVDDC2, BVDDR, BVDDP1,

CHGIN, CHGOUT, VBUS

Applicable for pin FVDD

Applicable for pin SW15V

0.5

5.0

DVDD+0.5

V

V

7.0V

5.0

AVDD+0.5

V

AG

V

Applicable for pins CVSS15V, CVSS12,

VSSH, AVSS, DVSS

Applicable for pins LRCK, SCLK, SDI,

VPRG1, BATTEMP, XIRQ, XRES,

PWGD, Q32K, HBT

Applicable for pins

still

LOUTL/R, VREF, AGND, LIN1L/R,

LIN2L/R, LIN3L/R, MICP/N,

MICS

Applicable for pins AVDD, DVDD,

PVDD1/2, CVDD1/2

valid

V

V

V

IN_REG

IN_RVDD

3.3V pins with diode to RVDD

IN_BVDD

I scr

ESD voltage regulator pins with diodes to BVDD pins with diode to BVDD

Input Current (latchup immunity)

Electrostatic Discharge HBM

-0.5

-0.5

ams

-100

5.0

BVDD+0.5

5.0

RVDD+0.5

7.0

BVDD+0.5

100

+/-1

V

V kV

Applicable for pins XIN32K, XOUT32K

Applicable for pins HPR/L, SW3, ISINK,

RVDD

Norm: JEDEC JESD22-A114C

P t

Total Power Dissipation (all supplies and outputs)

Humidity non-condensing

640 mW Valid for CTBGA64 package

H 5 85 %

Table 3 Soldering Conditions

Symbol Parameter Min Max

T body

T peak

D well

Package Body Temperature

Solder Profile*

235

30

260

245

45

3 MSL Moisture Sensitive Level

Technical

Unit Comments

°C

°C

Norm IPC/JEDEC J-STD-020C, reflects moisture sensitivity level only s

1 above 217 °C

Represents a max. floor live time of

168h

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

9

-

84

AS3518 V23

Data Sheet, Confidential

6 Electrical Characteristics

6.1 General Parameter

Table 4 Operating conditions for supply voltages

Symbol Parameter Contition Min

VB1V

BVDDx

BVDDR

FVDD

VBUS

CHGIN

DCDC Supply Voltage

Battery Supply Voltage

BVDD, BVDDH, BVDDC1,

BVDDC2, BVDDP1

RTC Supply Voltage

Filter Supply Voltage

USB VBUS Voltage

Charger Supply Voltage

1.0

3.0

1.35

1.8

4.5

DVDD

AVDD

Digital Supply Voltage

Analogue Supply Voltage

Digital Audio Supply Voltage (LDO2)

Analog Audio Supply Voltage (LDO1) 2.8

V

AGND

DELTA

-

Analogue Ground Voltage

Difference of Negative Supplies

VSS3V, VSS15V, VSSH, AVSS,

DVSS

Internally generated

To achieve good performance, the negative supply terminals should be connected to low impedance ground plane.

V

DELTA

+ Difference of Positive Supplies

2.8

-0.1

-0.25

Typ

1.5

3.6

Max Unit

3.6 V

5.5 V

3.6 5.5 V

5.0

2.9

2.9

3.6

5.5

5.5

3.6

3.6

AVDD/2

still

0.25

V

V

V

V

V

V

valid

V

Table 5 Electrical Specification of other function blocks

Symbol

V

POR_ON

V

POR_OFF

V

POR_HY f

LRCLK_WD t

ON_DELAY

V

DO_DL

V

DO_DH

I

PU

V

PWRUP_L

V

PWRUP_H

R

PWRUP

Parameter Note

Power-on Reset Activation

Level

Power-on Reset Release

Level

Power-on Hysteresis

LRCLK Watchdog

Delay Time of pin PWRUP

Digital Output Driver

Capability (drive LOW)

Digital Output Driver

Capability (drive HIGH)

Internal Pull-up Current

Source

Input Level LOW,

Power-on Reset activation level

ams

Minimum key press time

Pins XRES, XIRQ,

PWGD @ 8mA, SDO

Pins XRES, XIRQ @ 8mA, push/pull mode only, SDO

Pins XRES, XIRQ, PWGD, Q32K;

@0V

Pin PWRUP, BVDD>3V

2

2.6

6

Input Level HIGH

Pin PWRUP, BVDD>3V

BVVD/

3

1

Internal Pull-down Current

Source

Pin PWRUP, BVDD<=3V

Pin PWRUP; @2.9V 2.5

Min

V

DI_L

V

I

DI_H

PD f

CLK

Digital Input Level LOW

Digital Input Level HIGH

Internal Pull-down current source

Audio Clock Frequency

Pin HBT, SDI, SCLK, MCLK, LRCK

Pin HBT, SDI, SCLK, MCLK, LRCK 1.02

Pin HBT; @2.9V 7

8

LRCK according to streamed audio data

18

0.5

19

0.42

30

48

Max Unit

V

8

0.3

V mV kHz ms

V

V

V

V

µA

V

V

V uA

µA kHz

Typ

2.15

2.0

100

4.1

80

10

7

DVDD

/2*0.3

DVDD

/2*0.7

10

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

10

-

84

AS3518 V23

Data Sheet, Confidential

6.2 Operating Currents

Table 6 Supply currents

Symbol

T

T j amb

R th

Parameter Conditions

I

I

I

I

REF

BIAS

I

SUM

I

I

I

I

LIN

MIC

MICS

LOUT

I

DAC_GS

I

ADC_GS

I

HPH

DAC

ADC

I

I

DAC->HP

Line->HP

I

RTC

BVDD = 3.3V, T

A

Table 7 Temperature Range

Symbol

Reference supply current

Audio Bias current

Summing stage current

Line input stage current

Mic input stage current

Mic Supply stage current

Line output stage current

DAC gain stage current

ADC gain stage current

Headphone stage current

DAC supply current

ADC supply current

DAC playback current

Line Input playback current

RTC supply current

= 25 o

Parameter

all blocks off, only LDO1 & 2 on no signal no signal no load no load no signal no signal no load

Bias reduction on, no load

CM buffer off, no load

Bias reduction on, CM buffer off, no load

LRCK=48kHz

LRCK=44.1kHz

LRCK=32kHz

LRCK=16kHz

LRCK=8kHz

LRCK=48kHz, mono

LRCK=48kHz, stereo

LRCK=44.1kHz

LRCK=32kHz

LRCK=16kHz

ams

AG

LRCK=8kHz no load, 44.1kHz, including PMU no load, including PMU

Conditions Min

Operating temperature range

Junction temperature range

Thermal Resistance For CTBGA64 package

Min

-20

0

Typ Max Unit

350

130

135

140

715

215

450

143

143

1.65

1.12

1.12 uA uA uA uA uA uA uA uA uA

0.77

still

5.64

4.52

3.96

6.1

1.7

650

4.25

4.24

3.77

3.17

2.88

4.24

6.77

6.50 mA mA mA mA nA mA

valid

Typ

25

39

Max Unit

85

110

°C

°C

°C/W

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

11

-

84

AS3518 V23

Data Sheet, Confidential

6.4 Audio Specification

Table 8 Audio Parameters

Symbol Parameter Conditions

DAC Input to Line Output

FS

SNR

Full Scale Output

Signal to Noise Ratio

DR Dynamic Range

THD Total Harmonic Distortion

Line Input to Line Output

FS

SNR

THD

CS

Full Scale Output

Signal to Noise Ratio

Total Harmonic Distortion

Channel Separation

DAC Input to HP Output

1kHz FS input

A-weighted, no load, silence input

A-weighted, no load,

-60dB FS 1kHz input

1kHz -1dB FS input

1kHz 1V

RMS

(-3dB FS) input

A-weighted, no load, silence input

1kHz 1V

RMS

(-3dB FS) input

FS

SNR

DR

THD

CS

Full Scale Output

Signal to Noise Ratio

Dynamic Range

Total Harmonic Distortion

Channel Separation

R

L

= 32

Ω

R

L

= 16

Ω

A-weighted, no load, silence input

A-weighted, no load,

-60dB FS 1kHz input no load, 1kHz FS input

Pout=20mW, R

-1dB FS input

Pout=40mW, R

L

= 16 Ω , f=1kHz

-1dB FS input

R

L

= 32 Ω

R

L

= 16 Ω

L

= 32

AG

CS

Line Input to HP Output

FS

SNR

THD

Full Scale Output

Signal to Noise Ratio

Total Harmonic Distortion

R

L

= 32 Ω , 1kHz 1V

RMS

(FS) input

ams

RMS

(FS) input

RMS input

Pout=20mW, R=32

Ω

, 1kHz 1V

(FS) input

Channel Separation

Pout=40mW, R=16

Ω

, 1kHz 1V

(-3dB FS) input

R

L

= 32

Ω

RMS

R

L

= 16

Ω

MIC Input to Line Output

FS

SNR

THD

Full Scale Output

Signal to Noise Ratio

Total Harmonic Distortion

Line Input to ADC Output

1kHz FS input

A-weighted, no load, silence input

1kHz 27mV

RMS

(-3dB FS) input

SNR

DR

THD

Signal to Noise Ratio

Dynamic Range

BVDD = 3.3V, T

A

= 25 o

A-weighted, no load, silence input

A-weighted, no load,

-60dB FS 1kHz input

Technical

RMS

(-3dB FS) input

Typ Max Unit Min

-60

0.93

84

-83

94

92

-70

-70

77

71

0.84

0.83

96

-92

-75

0.85

93

91

-90

V

RMS dB dB dB

75

60

0.88

92

-92

90

0.79

0.78

95

93

-91

-72

still

-68 -60

V

RMS dB dB dB dB dB

V

RMS dB dB dB

V

RMS

valid

dB dB

V

RMS dB dB dB dB dB

V

RMS

V

RMS dB dB dB dB dB dB

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

12

-

84

AS3518 V23

Data Sheet, Confidential

7 Typical Operating Characteristics

Figure 3 Typical Frequency Response

DAC to HP output, no load

Figure 4 Typical THD

AG still valid

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

13

-

84

AS3518 V23

Data Sheet, Confidential

8 Detailed Description

8.1 Audio Functions

8.1.1 Audio Line Inputs (3x)

General

The chip features two identical line inputs. The blocks can work in mono differential, 2x mono single ended or in stereo single ended mode. An additional third line input features a stereo single ended mode only.

The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each and

MUTE. The gain can be set from –34.5dB to +12dB. The stage is set to mute by default. If the line input is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input.

Line Input 3 has no dedicated gain stage but is multiplexed with Line input 1 for playback.

Figure 5 Line Inputs

valid

AG still

Stereo Mode

ams

Mono Single Ended Mode (not supported for LineIn 3)

content

Mono Differential Mode (not supported for LineIn 3)

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

14

-

84

AS3518 V23

Data Sheet, Confidential

Parameter

Table 9 Line Input Parameter

Symbol Parameter Conditions Min Typ Max Unit

V

LIN

Input Signal Level 1.0 V

PEAK

R

LIN

A

Δ

RLIN

C

LIN

LIN

LINE_IN1_R

LINE_IN1_L

LINE_IN2_R

LINE_IN2_L

AudioSet_1

AudioSet_3

Input Impedance

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

Pls observe gain settings. Max. peak levels at any node within the circuit shall not exceed AVDD depending on gain setting

0Ah

0Bh

0Ch

0Dh

14h

16h kΩ

Input Impedance Tolerance

Input Capacitance

Programmable Gain

Gain Steps

Gain Step Accuracy

A

LINMUTE

Mute Attenuation discrete logarithmic gain steps

BVDD = 3.3V, T

A

= 25 o

C, fs=48kHz unless otherwise mentioned

Register Description

Table 10 Line Input Related Register

Name Base Offset

-34.5

20-

100

±30

5

1.5

±0.25

100

+12

Description

Right Line Input 1 settings, Line Input 3 selection

Left Line Input 1 settings

Right Line Input 2 settings

Left Line Input 2 settings

Enable/disable driver stage

Enable/disable mixer input

still

% pF dB dB dB dB

valid

Line inputs have to be enabled in register 14h first before other settings in register 0Ah to 0Dh can be programmed.

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

15

-

84

AS3518 V23

Data Sheet, Confidential

8.1.2 Microphone Input

General

The AFE offers one microphone input and one low noise microphone voltage supply (microphone bias), voice activation, microphone connect detection and push button remote control.

Figure 6 Microphone Input

valid

Microphone Preamplifier and Gain Stage

Gain Stage & Limiter

still

signals from e.g. electret microphones signal to 1Vp. The AGC has 15 steps with a dynamic range of about 29dB.

The AGC is ON by default but can be disabled by a microphone register bit.

Apart from the microphone pre-amplifier the microphone input signal can further be amplified with 32 @1.5dB programmable logarithmic gain steps and MUTE. All gains and MUTE are independently programmable. The gain can be set from –40.5dB to +6dB.

The stage is set to mute by default. If the microphone input is not enabled, the volume settings are set to their

Supply & Detection

content

≤

2mA and has a 10mA current limit. In OFF mode the MICS terminal is pulled to AVDD with 30kOhm. A current of typically

50uA generates an interrupt to inform the CPU, that a circuit is connected. When using HPCM as headset ground the HP–stage gives the interrupt. After enabling the HP-stage through the CPU the microphone detection interrupt will follow.

ams

When using the MICS terminal as ADC-10 input to monitor external voltages the 30kOhm pull-up can be disabled.

Remote Control

Fast changes of the supply current of typically 500uA are detected as a remote button press, and an interrupt is generated. Then the CPU can start the measurement of the microphone supply current with the internal 10-bit

ADC to distinguish which button was pressed. As the current measurement is done via an internal resistor, only two buttons generating a current of about 0.5mA and 1mA can be detected. With this 1mA as microphone bias is still available.

Voice Activation

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

16

-

84

AS3518 V23

Data Sheet, Confidential

Parameter

Table 11 Microphone Input Parameter

Symbol

V

MICIN

0

V

MICIN

1

V

MICIN

2

R

MICIN

Δ

MICIN

C

MICIN

A

MICPRE

A

MIC

Parameter

Input Signal Level

Input Impedance

Input Impedance Tolerance

Input Capacitance

Microphone Preamplifier

Gain

Programmable Gain

Gain Steps

Conditions

A

MICPRE

= 28dB; AMIC = 0dB

A

MICPRE

= 34dB; AMIC = 0dB

A

MICPRE

= 40dB; AMIC = 0dB

MICP, MICN to AGND

Preamplifier has 3 selectable

(fixed) gain settings discrete logarithmic gain steps

I

I

V

MICLIMIT

Gain Step Precision

Limiter Activation Level

A

MICLIMIT

Limiter Gain Overdrive t

ATTACK t

DECAY

A

MICMUTE

Limiter Attack Time

Limiter Decay Time

Mute Attenuation

V

MICSUP

I

MICMAX

V

NOISE

MICDET

REMDET

Microphone Supply Voltage

Max. Microphone Supply

Current

Microphone Supply Voltage

Noise

Microphone Detection

Current

Max. Remote Detection

Current

AG

BVDD = 3.3V, T

A

= 25 o

C unless otherwise mentioned

Register Description

Table 12 Microphone Related Register

ams

Min

-40.5

Typ

±15

5

28

34

40

20

10

15

40

1.5

±0.25

1

15*2

50

120

100

2.9

10

5

50

500

Max

+6

still

Unit

Name

MIC_R

MIC_L

AudioSet_1

AudioSet_3

IRQ_ENRD_1

IRQ_ENRD_3

IRQ_ENRD_4

Base

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

Offset

06h

07h

14h

16h

24h

26h

27h

Right Microphone Input volume settings, AGC control

Left Microphone Input volume settings, MIC supply control

Enable/disable driver stage

Enable/disable mixer input

Interrupt settings for microphone voice activation

Interrupt settings for microphone detection

Interrupt settings for remote button press detection

Microphone input has to be enabled in register 14h first before other settings in register 06h and 07h can be programmed. dB

V

PEAK dB

µs/6dB ms/6dB dB

V mA

µV

µA

µA mV

P mV

P mV

P kΩ

% pF dB dB dB dB dB

valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

17

-

84

AS3518 V23

Data Sheet, Confidential

8.1.3 Line Output

General

The line output is designed to provide the audio signal with typical 1V

PEAK

at a load of minimum 10k

Ω

, which is a minimum value for line inputs. If the limiters (N20/N21) are deactivated the peak output voltage is 1.45V

PEAK

. The load however can decrease to 64Ohm. In addition these line output can be configured as mono differential to drive 10mW @ 32

Ω

load (e.g. an earpiece of a mobile phone).

This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from -40.5dB to +6dB. A zero cross detection allows to control the actual execution of new gain settings.

If the line output is not enabled, the volume settings are set to their default values. Changing of volume and mute control can only be done after enabling the output.

If using the output in mono differential mode, the volume setting for the right channel should be set to 0dB.

Figure 7 Line Output

AG still valid

R

L_LO

C

L_LO

A

LO

Stereo Mode

Parameter

Table 13 Line Output Characteristics

ams

Conditions Symbol Parameter

Mono Differential Mode (please observe that gain of right channel amplifier has to best to 0dB)

Typ Max Unit

A

LOMUTE

Load Impedance

(Stereo Mode)

Load Capacitance

(Stereo Mode)

Programmable Gain

Gain Steps

Gain Step Accuracy

Mute Attenuation line inputs nominally have 10kΩ discrete logarithmic gain steps

64

-40.5

1.5

±0.25

100

100

+6

Ω pF dB dB dB dB

BVDD = 3.3V, T

A

= 25 o

C unless otherwise mentioned

Register Description

Table 14 Line Output Related Register

Name

Technical

AudioSet_1

AudioSet_3

2-wire serial

2-wire serial

2-wire serial

2-wire serial

00h

01h

14h

16h

Description

Right Line Output volume settings, MUX control

Left Line Output volume settings

Enable/disable driver stage

Enable/disable mixer input

Line output has to be enabled in register 14h first before other settings in register 00h and 01h can be programmed.

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

18

-

84

AS3518 V23

Data Sheet, Confidential

8.1.4 Headphone Output

General

The headphone output is designed to provide the audio signal with 2x40mW @ 16

Ω

or 2x20mW @32

Ω

, which are typical values for headphones. If the limiters (N20/N21) are disabled a maximum output of 2x60mW@16Ω or

2x30mW

@32Ω can be achieved.

This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –43.43dB to +1.07dB. A zero cross detection allows to control the actual execution of new gain settings.

Figure 8 Headphone Output

Headphones connected via decoupling capacitors

AG still

Headphones connected to Phantom Ground

(Common Mode)

valid

Phantom Ground

There are 2 ways to connect a headphone to the AFE. In order to spare the bulky ac/dc decoupling capacitors at pins HPR/HPL a buffered ground (Phantom Ground) is provided. This Common Mode Buffer needs to be connected via 2x100µF capacitors.

No-Pop Function

content

The output is automatically set to mute when the output stage is disabled.

To avoid Pop-Click noise during power-up and shut-down of the headphone amplifier, a charge/discharge control of HPGND (0V-1.45V-0V) at pins HPR/HPL is incorporated into the AFE. The 470nF capacitor at pin HPGND is used to form the charge/discharge slope. Pls observe that pin HPGND is a high impedance node which must not be connected to any other external device than the 470nF buffer capacitor. To avoid Pop-Click noise one has to wait for 750ms in between a power-down (switch-off) and a power-up (switch-on) of the headphone amplifier.

The output is automatically set to mute when the output stage is disabled.

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

19

-

84

AS3518 V23

Data Sheet, Confidential

Figure 9 HP POP-Click Suppression

HPGND [V]

MUTE OFF

AGND

Operation

HP Amp powered down t

250ms

500ms

Over-current Protection

The headphone amplifier has an over-current protection (e.g. HPR/HPL is shorted). This over-current protection is at 150mA for HPR/HPL and 300mA for HPCM. There is a corresponding interrupt available to be enabled.

valid

Headphone Detection

When the headphone amplifier is powered down, one can detect the connection of a headset. It only work if the headset is connected between pins HPR/HPL and HPCM. As long as the headphone amplifier is powered down,

HPCM is biased to 150mV and acting as the sense pin. There is a corresponding interrupt available to be enabled.

Power Options loads the bias current can be increased.

AG still

Parameter

Symbol

R

L_HP

C

L_LO

P

HP

P

HP_MAX

A

HP

Parameter

Load Impedance

Load Capacitance

Nominal Output Power

Max. Output Power

Programmable Gain

Gain Steps

Gain Step Accuracy

Over current limit

Conditions

stereo mode stereo mode

RL=16Ω, limiter enabled

RL=32Ω, limiter enabled

RL=16Ω

RL=32Ω discrete logarithmic gain steps

HPR/HPL pins

HPCM pin

Min

16

content

-45.5

Typ

40

20

60W

30W

1.5

±0.25

150

300

Max Unit

100

Ω pF

+1 mW mW dB dB dB mA mA

P

A

SRRHP

HPMUTE

Power Supply Rejection

Ratio

Mute Attenuation

200Hz-20kHz, 720mVpp, RL=16Ω

BVDD = 3.3V, T

A

= 25 o

C unless otherwise mentioned

90

100 dB dB

Register Description

Name

Technical

HPH_OUT_L

AudioSet_3

IRQ_ENRD_3

2-wire serial

2-wire serial

2-wire serial

2-wire serial

02h

03h

16h

26h

Description

Right HP Output volume and over-current settings

Left HP Output volume settings, enable and detection control

Power save options, common mode buffer

Interrupt settings for over current and HP detection

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

20

-

84

AS3518 V23

Data Sheet, Confidential

8.1.5 DAC, ADC and I2S Digital Audio Interface

Input

The AFE receives serialized audio data for the DAC via pin SDI. The output of the DAC is fed through a volume control to the mixer stage and to the multiplexers of line output and headphone amplifiers.

This serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one bit-stream. Via pin LRCK the alignment clock is input to the DAC digital filters. LRCK (Left Right Clock) indicates whether the serial bit-stream received via pin SDI, represents right channel or left channel audio data.

Via pin SCLK the bit clock for the serial bit-stream is signalled. SDI and LRCK are synchronous with SCLK. SDI,

LRCK and SCLK are inputs; SDO is not used.

The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each.

The gain can be set from –40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be done after enabling the input.

Output

This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a volume control to the audio ADC. The digital output is done via an I2S interface.

The AFE sends serialized audio data from the ADC via pin SDO. This serialized audio data is a digital audio data

valid

stream with the left and the right audio channels multiplexed into one bit-stream. Via pin LRCK the alignment clock is signalled to the connected devices (e.g. CPU). LRCLK (Left Right Clock) indicates whether the serial bitstream sent via pin SDI, presents right channel or left channel audio data. Via pin SCLK the bit clock for the serial bit-stream is signalled. SDO and LRCK are synchronous with SCLK. SDO is an output; LRCK and SCK are inputs; SDI is not used.

AG

done after enabling the input.

still

The gain can be set from –34.5dB to +12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume settings are set to their default values. Changing the volume and mute control can only be

The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate.

I2S Modes

PWGD (pin PWGD is multiplexed for I2S Direct Mode). The master clock (MCLK) is the necessary internal over-

content

expected sampling frequency. The ranges are 8kS-12kS (8kHz-12kHz) and 16kS-48kS (16kHz-48kHz). Please refer to register 1Ah.

Table 17 I2S Modes

Slave Mode, internal PLL of the AS3518 generates MCLK Slave Mode with I2S direct, the master clock is signalled via pin PWGD

The digital audio interface automatically checks the LRCK. An interrupt can be generated when the state of the

LRCK input changes. A bit in the interrupt register represents the actual state (present or not present) of the

LRCK.

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

21

-

84

AS3518 V23

Data Sheet, Confidential

Signal Description

The digital audio interface uses the standard I2S format:

• left justified

•

MSB first

• one additional leading bit

The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit.

When there are less than 18 bits sampled, the data sample is completed with “0”s. In I2S direct mode the data length has to be minimum 18 bits.

The ADC output is always 20 bit. If more SCLK pulses are provided, only the first 20 will be significant. All following bits will be “0”.

SCLK has not to be necessarily synchronous to LRCK but the high going edge has to be separate from LRCK edges. The LRCK signal has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always in correct phase lock condition to the external LRCK.

Please observe that LRCK has to be activated before enabling the ADC.

Figure 10 I2S Left Justified Mode

AG still valid

Figure 11 I2S Timing

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

22

-

84

AS3518 V23

Data Sheet, Confidential

Parameter

Table 18 I2S Timing

Symbol

t

SCLK t

SCLKH t

SCLKL

T

LRSU t t t t

T

LRHD

SDSU

SDHD

SDOD

JITTER

Parameter

SCLK Cycle Time

SCLK Pulse Width High

SCLK Pulse Width Low

LRCK Setup Time before

SCLK rising edge

LRCK Hold Time after SCLK rising edge

SDI setup time before SCLK rising edge

SDI hold time after SCLK rising edge

SDO Delay from SCLK falling edge

Jitter of LRCK

I2S Direct mode

t t t

T

SCD

T

LRD

SDSU

SDHD

SDOD

SCLK delay after MCLK rising edge

LRLCK delay after SCLK rising edge

SDI setup time before SCLK rising edge

SDI hold time after SCLK rising edge

SDO Delay from SCLK falling edge

Conditions

internal PLL generates MCLK from

LRCK

AG

Register Description

Min

160

80

80

80

80

25

25

-20

0.5

0.5

5

5

Typ

15

25

20

Max Unit

ns ns ns ns ns ns ns ns ns ns

valid

ns ns ns ns

Name

DAC_R

DAC_L

ADC_R

ADC_L

MISC

AudioSet_1

AudioSet_2

AudioSet_3

IRQ_ENRD_1

Base

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

Offset

0Eh

0Fh

10h

11h

1Ah

14h

15h

16h

25h

DAC input volume settings

DAC input volume settings

ADC output volume settings, source multiplexer settings

ADC output volume settings

I2S MCLKand PLL settings

Enable/disable ADC

Enable/disable DAC and power save options

Enable/disable mixer input

Interrupt settings for LRCK changes

DAC and ADC have to be enabled in register 14h first before other settings in register 0Eh to 11h can be programmed.

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

23

-

84

AS3518 V23

Data Sheet, Confidential

8.1.6 Audio Output Mixer

General

The mixer stage sums up the audio signals of the following stages

•

Microphone Input 1

•

Line Input 1/3

•

Line Input 2

•

Digital Audio Input (DAC)

The mixing ratios have to be set within the volume registers of the corresponding input stages. Please be sure that the input signals of the mixer stage are not higher than 1Vp. If summing up several signals, each individual signal has of course to be accordingly lower. This shall insure that the output signal is also not higher than 1Vp to get a proper signal for the output amplifier.

This stage features an automatic gain control (AGC), which automatically avoids clipping.

Register Description

Audio Mixer Related Register

Name

AudioSet_2

AudioSet_3

Base

2-wire serial

2-wire serial

Offset

15h

16h

Description

Enable/disable mixer stage and AGC

Enable/disable DAC, MIC or Line Inputs to mixer stage

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

24

-

84

AS3518 V23

Data Sheet, Confidential

8.1.7 2-Wire-Serial Control Interface

General

There is an I2C slave block implemented to have access to 64 byte of setting information.

The I2C address is: Adr_Group8 - audio processors

•

8Ch_write

•

8Dh_read

Protocol

Symbol

S

Sr

DW

DR

WA

A

N reg_data data (n)

P

WA++

Table 20 2-Wire Serial Symbol Definitions

Definition

Start condition after stop

Repeated start

Device address for write

Device address for read

Word address

Acknowledge

No Acknowledge

Register data/write

Register data/read

Stop condition

Increment word address internally

AS3518 (=slave) receives data

AS3518 (=slave) transmits data

Figure 12 Byte Write

R/W

AG

R

W

R

R

R

R

R

R

W

R

R

Note

1 bit

1 bit

1000 1100b (8Ch)

1000 1101b 8Dh)

8 bit

1 bit

1 bit

8 bit

still valid

Figure 13 Page Write

ams content

Byte Write and Page Write formats are used to write data to the slave.

The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations.

For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

25

-

84

AS3518 V23

Data Sheet, Confidential

Figure 14 Random Read

Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master.

The word address transfer is initiated with a START condition issued by the master while the bus is idle. The

START condition is followed by the device-write address and the word address.

In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.

Figure 15 Sequential Read

valid

subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behaviour of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently.

Figure 16 Current Address Read

ams

in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-

Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the

1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition.

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

26

-

84

AS3518 V23

Data Sheet, Confidential

Parameter

Figure 17 I2C timing

Table 21 I2C Operating Conditions

Symbol

V

CSL

V

CSH

HYST

V

OL

Tsp

T

T

H

L

T

SU

T

HD

T

TS

PD

DVDD =2.9V, T amb

Parameter Conditions Min

CSCL, CSDA Low Input

Level

CSCL, CSDA High Input

Level

CSCL, CSDA Input

Hysteresis

CSDA Low Output Level

Spike insensitivity

Clock high time

Clock low time

(max 30%DVDD)

CSCL, CSDA (min 70%DVDD) at 3mA

AG

No hold time needed for CSDA relative to rising edge of CSCL

CSDA H hold time relative to

CSDA edge for start/stop/rep_start

CSDA prop delay relative to lowgoing edge of CSCL

0

2.03

200

-

50

500

500

250

0

200

=25ºC; unless otherwise specified

content

-

-

50

Typ

-

-

0.87

5.5

Max Unit

V

V mV

valid

450

-

100

-

800

still

-

V ns ns ns ns

-

- ns ns ns

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

27

-

84

AS3518 V23

Data Sheet, Confidential

8.2 Power Management Functions

8.2.1 3V Step-Up Converter

General

•

Output voltage 3V to 3.6V (BVDD) programmable in 4 steps via DCDC3p bit to save power

•

Input voltage 1V (1.2V) to 3V, voltages higher than that can be connected to BVDD directly

•

Maximum output current to BVDD: 150mA

•

On chip 300m

Ω

NMOS switch

•

On chip 700m

Ω

PMOS switch

•

PW M mode with 1.2MHz switching frequency, Pulse skipping capability

•

Inductor current limitation 850mA

•

On-chip PMOS switch

•

Low quiescent current: 40

µ

A in PFMmode, 300μA in PWM mode

• ≤1μA shutdown current

• uses external coil (6.8

µ

H) and Schottky diode (500mA)

Figure 18 DCDC 3V Block Diagram

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

28

-

84

AS3518 V23

Data Sheet, Confidential

Parameter

Table 22 DCDC Boost Parameter

Symbol Parameter Conditions Min Typ Max Unit

I

VDD2.9

Quiescent Current

V

STARTUP

Startup Voltage

V

HOLD

R

SWN_on

R

SWP_on f

SW t t

ON_min

OFF_min

η eff

I

I

SW_LIM

OUT

Hold-on Voltage

Internal N-Switch R

DS_ON

Internal P-Switch R

DS_ON

Switching Frequency

Minimum On-time

Minimum Off-time

Efficiency

Current Limit

Load Current

Power down mode

PFM mode operation

PWM mode

R

Load

>220Ω

I

OUT

0V

=1mA, VBAT falling from 1.5 to

Start-up, X3VOK=1

PWM mode operation, X3VOK=0

I

OUT

=20mA, Vin=1.35

I

OUT

=50mA, Vin=1.5

1.0V ≤ VB1V ≤ 3.0V

VB1V=1.0V

1.0

100

0.60

40

300

0.5

5 μA

μA

μA

V

V

Vin=1.0..2.0V, C(VBAT_1V) = 2.2

µ

F ceramic || 2000

µ

F Elko, C(BVDD) = 3 x 2.2

µ

F ceramic, L=DS1608 6.8

µ

H,

Temp = 25deg

Figure 19 DCDC Boost Typical Performance Characteristics

100

Efficiency vs. Output Current

AG

100

250

1.2

100

100

85

87

0.85

500

900

500

1.10

150

still

mΩ mΩ kHz

MHz ns ns

%

%

A mA

valid

Efficiency vs. Output Current

95

90

85

80

75

95

ams

V

IN

=1.5V

90

content

75

V

IN

=1.3V

V

IN

=0.9V

V

IN

=1.5V

V

IN

=1.3V

V

IN

=0.9V

V

OUT

=3.6V

V

IN

=3.0V

70

70

1 10 100

OUTPUT CURRENT [mA]

1000

1 10 100

OUTPUT CURRENT [mA]

1000

L=DS1608 6.8

µ

H, Temp = 25deg

Register Description

Table 23 DCDC3V Related Register

Name

DCDC3V

PMU ENABLE

Base

2-wire serial

2-wire serial

Offset

17h-7

18h

Description

DCDC3 output voltage settings

Enables writings to extended register 17h-7

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

29

-

84

AS3518 V23

Data Sheet, Confidential

8.2.2 Low Drop Out Regulators

General

These LDO’s are designed to supply sensitive analogue circuits, audio devices, AD and DA converters, microcontroller and other peripheral devices. The design is optimised to deliver the best compromise between quiescent current and regulator performance for battery powered devices.

Stability is guaranteed with ceramic output capacitors of 1μF +/-20% (X5R) or 2.2μF +100/-50% (Z5U). The low

ESR of these caps ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output. The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance.

Figure 20 LDO Block Diagram

AG still valid

LDO1

•

Input voltage is BVDD

•

Output voltage is AVDD (typ. 2.9V)

•

Driver strength: 100mA

It is set to a fixed output voltage of 2.9V, 100mA max

content

loads are possible but most not exceed the supply ratings in total together with the operating internal blocks.

Further the external load must not induce noise to the sensitive AVDD supply pin.

LDO2

This LDO generates the digital supply voltage used for the AFE itself.

•

Input Voltage is BVDD

•

Output Voltage is DVDD (typ. 2.9V)

•

Driver strength: 100mA

It is set to a fixed output voltage of 2.9V, 100mA max

. It supplies the digital part of the AFE. Additional external loads are possible but most not exceed the supply ratings in total together with the operating internal blocks.

Further the external load must not induce noise to the DVDD supply pin but is not as critical as AVDD.

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

30

-

84

AS3518 V23

Data Sheet, Confidential

LDO3 & LDO4

These LDOs can used to generate the periphery voltage for the digital processor or other external components

(e.g. ext. DAC, USB-PHY, SD-Cards, NAND-Flashes, FM-Tuner …)

LDO3 has a separate input pin (BVDDP1) which can be connected to either the battery or a DCDC converter output.

•

Input Voltage BVDDP1 or BVDD

•

Output Voltage is PVDD1 & PVDD2 (1.2 to 3.5V)

•

Default value at start-up is defined by VPRG1 pin

•

Driver strength: 100mA, can be programmed to 200mA

Parameter

Table 24 LDOs Block Characteristics

Symbol Parameter Conditions Min

V

R

ON

PSRR

I

OFF

I

VDD

Noise t start

V out_tol

LineReg

V

LoadReg

I

LIMIT

BVDD=4V; I

LOAD

On resistance

Shut down current

Supply current

Output noise

Startup time

Output voltage tolerance

=150mA; T amb

Load regulation

Line regulation

Load regulation

Current limitation without load

10Hz < f < 100kHz minimum +/- 50mV

LDO1, Static

LDO1, Transient;Slope: t

LDO1, Static

AG

LDO1, LDO2, LDO3, LDO4

LDO 3 and LDO4, has to be enabled via register 17h-1, 17h-2

-2.5%

=25ºC; C

LOAD

=2.2μF (Ceramic); unless otherwise specified

ams

Output noise

content

350

Typ

70

40

100

50

50

200

<1

<10

<1

<10

200

still

nA

μA

μV rms

μs mV mV mV

2.5%

1

Max Unit

Ω dB

valid

mA

Output load: 150mA

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

31

-

84

AS3518 V23

Data Sheet, Confidential

Load Regulation Load Regulation output load: 10mA transient input voltage ripple: 500mV

Register Description

Table 25 LDO Related Register

Name

PMU PVDD1

PMU PVDD2

PMU ENABLE

Base

2-wire serial

2-wire serial

2-wire serial

Offset

17h-1

17h-2

18h output load: 150mA transient input voltage ripple: 500mV

valid still

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

32

-

84

AS3518 V23

Data Sheet, Confidential

8.2.3 DCDC Step-Down Converter (2x)

General

These converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage requirements for microprocessors.

•

Input Voltage BVDDC1/2 (usually connected to the battery)

•

Output Voltage CVDD1 & CVDD2

• output voltage levels can be programmed independently form 0.65V to 3.4V

• the default value at start-up is defined by VPRG1 pin

• driver strength 250mA

Figure 22 DCDC Step-Down Block Diagram

AG still valid

Functional Description

The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches efficiency up to 97% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of

250mA, with an output capacitor of only 10

µ

F. The implemented current limitation protects the DCDC and the coil during overload condition.

Technical

In this mode there is no minimum coil current necessary before switching off the PMOS. As result, the ON time of the PMOS will be reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil current is inverted. This results in a very low ripple and noise, but decreased efficiency, at light loads,

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

33

-

84

AS3518 V23

Data Sheet, Confidential especially at low input to output voltage differences. In the case of an inverted coil current the regulator will not operate in pulse skip mode.

Figure 23 DCDC buck with disabled current force / pulse skip mode

1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage

High efficiency operation:

In this mode there is a minimum coil current necessary before switching off the PMOS. As result, fewer pulses at low output loads are necessary, and therefore the efficiency at low output load is increased. On the other hand

AG still valid

1: LXC1 voltage, 2:coil current (1mV=1mA) 3: output voltage

It’s also possible to switch between these two modes dynamically during operation:

100% PMOS ON mode for low dropout regulation:

For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is than in LDO mode. This feature is enabled if the output voltage drops by more than 4%.

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

34

-

84

AS3518 V23

Data Sheet, Confidential

Parameter

Table 26 DCDC Buck Typical Performance Parameter

Symbol Parameter Conditions

V

OUT_tol

I load

I

V

IN

V

OUT

LIMIT

R

PSW

Input voltage

Regulated output voltage

Output voltage tolerance

Maximum Load current

Current limit

P-Switch ON resistance

BVDD minimum +/- 50mV

BVDD=3.0V

R

NSW f

SW f

SWsc

C out

Lx

η eff t

MIN_ON t

MIN_OFF

V

LineReg

V

I

VDD

LoadReg

N-Switch ON resistance

Switching frequency

Switching frequency

Output capacitor

Inductor

Efficiency

Current consumption

Minimum on time

Minimum off time

Line regulation

Load regulation

BVDD=3.0V in shortcut case

Ceramic, +/- 10% tolerance

+/- 10% tolerance

Iout=100mA, Vout=3.0V

Operating current without load

Low power mode current

Shutdown current

Static

Transient; Slope: t step, 200mA load

Static

Transient; Slope: t r

=10μs,

100mA step r

=10μs, 100mV

AG

BVDD=3.6V; T amb

=25ºC; unless otherwise specified

Figure 25 DCDC Step-down Performance Characteristics

100

95

90

85

Efficiency vs. Output Current

V

OUT

=3.0V

V

OUT

=1.8V

content

V

OUT

=1.2V

Min

3.0

0.65

-3%

3.3

Typ Max Unit

250

450

0.5

5.5

3.4

3%

0.7

V

V mV mA mA

Ω

0.5

1.2

0.6

10

97

220

100

0.1

80

40

2

10

5

50

4.7

0.7

still

mV

Ω

MHz

MHz

μF

μH

% ns ns

μA

valid

mV

80

75

70

0,1 1 10

OUTPUT CURRENT [mA]

100

V

IN

=3.6V

1000

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

35

-

84

AS3518 V23

Data Sheet, Confidential

Output voltage vs. Output Current

1,225

Line Regulation

1,215

1,215

1,21

I

OUT

=0mA

1,205

1,205

1,195

I

OUT

=125mA

1,2

I

OUT

=250mA

1,185

200

V

IN

=3.6V

250

1,175

0 50 100 150

OUTPUT CURRENT [mA]

1,195

3 3,4

AG

Register Description

Table 27 DCDC Buck Related Register

ams

Offset Description Name

PMU CVDD1

PMU CVDD2

PMU ENABLE

Base

2-wire serial

2-wire serial

2-wire serial

17h-3

17h-4

18h

content

CVDD2 (DCDC2) control and voltage settings

Enables writings to extended registers 17h-3, 17h-4

V

OUT

=1.2V

3,8 4,2

INPUT VOLTAGE [V]

4,6

still

5

valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

36

-

84

AS3518 V23

Data Sheet, Confidential

8.2.4 Charger

General

This block can be used to charge a 4V Li-Ion accumulator. It supports constant current and constant voltage charging modes with adjustable charging currents (55 to 460mA) and maximum charging voltage (3.9 to 4.25V).

An internal protection circuit will limit the charging current when a CHGIN voltage drop is detected.

Figure 26 Charger Block Diagram

AG still valid

Figure 27 Charger States

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

37

-

84

AS3518 V23

Data Sheet, Confidential

Trickle Charge

If BVDD is below 3V in systems where the battery is not separated from BVDD, the charger goes automatically in trickle charge mode with 50mA charging current and 3.9V endpoint voltage. In this mode charging current and voltage are not precise, but provide a charger function also for deep discharged batteries. The temperature supervision is not enabled in trickle charge mode.

As soon as BVDD reaches 3V the AFE switches on and starts-up the regulators with the power-up sequence selected by pin VPRG1. Afterwards the CPU can set the modes and the charging currents via the 2-wire serial interface.

If the battery (CHGOUT) voltage is below 3V the charging current cannot be set higher than 55mA, this is also true when using a battery separation circuit to supply the AFE (BVDD) from USB or another voltage source.

Temperature Supervision

This charger block also features a 15uA supply for an external 100k NTC resistor to measure the battery temperature while charging. If the temperature is too high (>45°C), an interrupt can be generated. If the battery temperature drops below 42°C the charger will start charging again. The temperature supervision is not enabled in trickle charge mode.

If the NTC resistor does not have 100kΩ its value can be corrected with a resistor in series or in parallel.

valid

Parameter

Table 28 Charger Parameter

V

I

Symbol

I

CHG_trick

V

CHG_trick

I

CHG

Parameter

Charging Current

(trickle charge)

Charger Endpoint Voltage

(trickle charge)

(0-7) Charging Current

CHG

(0-7) Charging Voltage

V

V

V

ON_ABS

ON_REL

OFF_REL

Charger On Voltage IRQ

Charger On Voltage IRQ

Charger Off Voltage IRQ

REV_OFF

Reverse current shut down

Min Conditions

BVDD<=3V, CHGIN = 5.5V

BVDD<=3V, CHGIN = 4.0V

BVDD > 3V, I

CHG

AG

> 60mA

BVDD > 3V, end of charge is true

BVDD = 3V

CHGIN-CHGOUT

CHGIN-CHGOUT

37

17

0.70*

CHGIN

I

NOM

-8%

V

NOM

-50mV

40

V

BATEMP_ON

V

BATEMP_OF

F

Battery Temp. low level

(42°C)

BVDD >3V

I

CHG_OFF

End Of Charge current level BVDD >3V

content

610

700

BVDD = 5V, CHGIN open

5%

I

NOM

3.1

170

77

10%

I

NOM

<1

Typ

68

32

0.72*

CHGIN

I

V

NOM

NOM

still

0.74*

CHGIN

I

NOM

+8%

V

NOM

+30mV

4.0

240

Unit

mA

V mA

V

V mV mV

15%

I

NOM mV mV mA uA

BVDD=3.6V; T amb

=25ºC; unless otherwise specified

Register Description

Table 29 Charger Related Register

Name Base Offset

CHARGER

IRQ_ENRD_2

2-wire serial

2-wire serial

22h

25h

Technical

Description

Charger voltage, current and temp. supervision control

Enable/disable EOC and battery over-temperature interrupt

Read out charger status

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

38

-

84

AS3518 V23

Data Sheet, Confidential

8.2.5 15V Step-Up Converter

General

The integrated Step-Up DC/DC Converter is a high efficiency current-mode PWM regulator, providing an output voltage up to 15V. A constant switching-frequency results in a low noise on supply and output voltages. When using an additional transistor the output voltage can be up to 25V to drive 6 white LED in series.

It has an adjustable sink current (1.2 to 36mA) to provide e.g. dimming function when driving white LEDs as back-light.

A voltage feedback mode allows generating constant supply voltages for e.g. OLEDs by using an external Zener diode. To bias the diode ISINK is sinking about 10uA in this voltage feedback mode.

An internal protection circuit will shut down the regulator if the voltage on SW15 exceeds 15V. No more external protection has to be used to avoid an exceeding of the operation conditions in a no load situation.

Figure 28 DCDC15 Block Diagram

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

39

-

84

AS3518 V23

Data Sheet, Confidential

Parameter

Table 30 15V Step-Up Converter Parameter

Symbol Parameter Conditions

V

SW

I

VDD

V

FB

V

FB

I

SW_MAX

R

SW

High Voltage Pin

Quiescent Current

Feedback Voltage,

Transient

Feedback Voltage, during

Regulation

Current Limit

Switch Resistance

Pin SW15

Pulse Skipping mode

Pin ISINK

Pin ISINK

V15_ON = 1

V15_ON = 0

I

LOAD

I

FB

V

PULSESKIP

C

F

IN

OUT

L

(Inductor) t

MIN_ON

MDC

Load Current

Current into ISINK during voltage feedback mode

Pulse-skip Threshold

@ 15V output voltage

Voltage at pin ISINK, pulse skips are introduces when load current

Fixed Switching Frequency becomes too low.

Ceramic Output Capacitor

I

LOAD

> 20mA

I

LOAD

< 20mA

Minimum On-Time

Maximum Duty Cycle

BVDD=3.6V; T amb

=25ºC; unless otherwise specified

Figure 29 15V Step-Up Performance Characteristics

Efficiency vs. output current

Use inductors with small C

(<100pF) for high efficency

Guaranteed per design

PARASITIC

AG

95

Min

0

0

0.65

350

0

1.2

0.45

17

8

90

85

Typ

140

Max Unit

15 V

µA

5.5 V

0.83 1.0 V mA 510

0.85

10

1.33

750

1.54

45

1.5

0.6

1

22

10

91

0.75

27

still

MHz

µF

µH ns

%

Ω mA uA

V

valid

90

85

80

75

V

IN

=3.6V

Load = 3 LEDs

70

1 100 10

OUTPUT CURRENT [mA]

Register Description

Table 31 15V Step-Up Related Register

Name

DCDC15

Base

2-wire serial

Offset

1Bh

Technical

Description

DCDC15 current and dimming control

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

40

-

84

AS3518 V23

Data Sheet, Confidential

8.3 SYSTEM Functions

8.3.1 SYSTEM

General

The system block handles the power up, power down and regulator voltage settings of the AFE.

The PWGD output is able to drive also the PLL clock, the SPDIF output or a PWM signal. The output can be configured to be push/pull (3 different driver strengths) or open-drain.

Power Up Conditions

The chip powers up when one of the following condition is true:

•

High signal on the PW R_UP pin (>80ms, >1V & >1/3 BVDD)

•

Rising edge on the VBUS pin (USB plug in: BVDD>3V or VB1V >1V, VBUS>4.5V)

•

Rising edge on the CHGIN pin (charger plug in: BVDD>3V or VB1V >1V, CHGIN>4.0V)

•

RTC wake-up: The auto wake-up timer is internally connected to the Power-up and Hibernation

Control block.

valid

To hold the chip in power up mode the PWR_HOLD bit in the SYSTEM register (0x20h) is set.

Power Down Conditions

The chip automatically shuts off if one of the following conditions arises:

•

Clearing the PW R_HOLD bit in SYSTEM register (0x20h)

•

•

AG still

•

Heartbeat watchdog via pin HBT(no watchdog reset via HBT pin for > 500ms, has to be enabled)

•

LDO or step down converter output voltage drop below a programmable level (has to be enabled)

•

Junction temperature reaches maximum threshold, set in SUPERVISOR register (0x24h)

•

High signal on the PW R_UP pin for more than (>6s, >1V & >1/3 BVDD).

Start-up Sequence

ams

These pin detects 5 logical input states which shall come from an external resistor divider network.

At first, LDO1 (AVDD) and LDO2 (DVDD) is powering up. This cannot be influenced with the selection of specific sequences below. LDO1 and LDO2 are necessary for the internal supply of the AFE.

After power-up sequence selected by pin VPRG1, all voltage settings and power on/off conditions of the described regulators can be programmed via the serial interface.

Table 32 Start-up Modes

# VPRG1 DCDC1 DCDC2 LDO3 LDO4 DCDC3V XRES/

1 vss

CVDD1 CVDD2 PVDD1 PVDD2 BVDD

1,2V 2nd 2,8V 3rd 1,8V 4th

PWGD

x 3,6V 1st 5th 6th

2 vdd

1,2V 4th 1,8V 3rd 3,3V 2nd

3 150k-PU

1,2V 2nd 1,8V 3rd 3,3V 4th x 3,6V 1st 5th 6th x 3,6V 1st 5th 6th

4 reserved

5 reserved

Technical

x … means that this regulator is not started with the start-up sequencer but has to be turned on by the 2-wire serial interface when needed.

PWGD delay with CRES pin

With using an external capacitor on CRES, the PWGD signal can be delayed. This delay can be calculated with the 5uA pull-up current and a comparator threshold of 1.5V. Using a 33nF capacitance will give a delay of 10ms.

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

41

-

84

AS3518 V23

Data Sheet, Confidential

Figure 30 Power Up Timing

Power up

from PwrUp, CHG_IN, or VBUS pin

BVDD rising with VBAT1 supply (DCDC3V)

VREF, IREF rising with vdd_bandgap

QLDO1 & 2

AVDD & DVDD for internal supply

EN LDO2 + DCDC QLDO2=ok

Sequence 2

Sequence 3

Sequence 4

XRES

PWGD

VREF=ok start sequencer with 1.2 MHz clock

+50ms

+51.3ms

AG

+52.5ms

+53.8ms

still valid

+55.8 to +63.8ms

depending on external C

Register Description

Table 33 System Related Register

Name Base ams

OutContr

PMU ENABLE

SYSTEM

IRQ_ENRD_1

IRQ_ENRD_3

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

12h-1

18h

20h

24h

26h

content

Enable/disable wake-up interrupts, set shut-down time

Enable/disable junction temperature interrupt

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

42

-

84

AS3518 V23

Data Sheet, Confidential

8.3.2 Hibernation

General

Hibernation allows shutting down a part or the complete system. Hibernation can be terminated by every possible interrupt of the AFE. E.g. one can use the RTC for a time triggered wake-up. The interrupt has to be enabled before going to hibernation

Table 34 Hibernation Modes

Action

Hib. with Default

Cancel Hibernation

Hib. with Modif Settings

Cancel Hibernation

Hib. with Modif Settings

Cancel Hibernation

KeepBit

OFF

OFF

OFF

OFF

ON

ON

LDO3

OFF

Default

OFF

As Before

DCDC1/2

OFF

Default

OFF

As Before

No Change No Change

No Change No Change

“Hibernation with Default” means that, the voltage of the power supply is determined by VPRG1 pin.

Register Description

Table 35 Hibernation Related Register

Name

PMU Hibernate

PMU ENABLE

Base

2-wire serial

2-wire serial

Offset

17h-6

18h

Description

Hibernation control

AG still

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

43

-

84

AS3518 V23

Data Sheet, Confidential

8.3.3 Supervisor

General

This supervisor function can be used for automatic detection of BVDD brown out or junction over-temperature condition.

BVDD Supervision

The supervision level can be set in 8 steps @ 60mV from 2.74 to 3.16V. If the level is reached an interrupt can be generated. If BVDD reaches 2.7V the AFE shuts down automatically.

Junction Temperature Supervision

The temperature supervision level can also be set by 5 bits (120 to –15 o

C). If the temperature reaches this level, an interrupt can be generated. The over-temperature shutdown level is always 20 o

C higher.

Pls note that the temp supervision might be influenced by a VBE reading of the general purpose ADC.

Power Rail Monitoring

The 4 main regulators have an extra monitor which observes the output voltage of the regulators. This power rail

valid

monitors are independent from the 10bit ADC. To activate these please see related registers.

Register Description

Table 36 Supervisor Related Register

Name

SUPERVISOR

IRQ_ENRD_0

IRQ_ENRD_1

IRQ_ENRD_2

IRQ_ENRD_3

Base

2-wire serial

2-wire serial

2-wire serial

2-wire serial

2-wire serial

Offset

21h

23h

24h

25h

26h

Description

AG still

Enable/disable PVDD/CVDD monitoring interrupt and shutdown

Enable/disable PVDD/CVDD monitoring interrupt and shutdown

Enable/disable battery brown out interrupt

Enable/disable junction temperature interrupt

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

44

-

84

AS3518 V23

Data Sheet, Confidential

8.3.4 Interrupt Generation

General

All interrupt sources can get enabled or disabled by corresponding bits in the 5 IRQ-bytes. By default no interrupt source is enabled.

The XIRQ output can get configured to be PUSH/PULL or OPEN_DRAIN and ACTIVE_HIGH or ACTIVE LOW with 2 bits in IRQ_ENRD_4 register (27h). Default state is open drain and active_low.

IRQ Source Interpretation

There are 3 different modules to process interrupt sources:

LEVEL

The IRQ output is kept active as long as the interrupt source is present and this IRQ-Bit is enabled

EDGE

The IRQ gets active with a high going edge of this source. The IRQ stays active until the corresponding IRQ-

Register gets read.

valid

STATUS CHANGE

The IRQ gets active when the source-state changes. The change bit and the status can be read to notice which

De-bouncer

still

the phase of plug-in or unplug, a de-bounce time of 512ms/256ms/128ms/8ms can be selected.

Interrupt Sources

25 IRQ events will activate the XIRQ pin:

•

Headphone connected

•

Headphone over-current

•

Microphone connected

•

Microphone remote control

•

ams

Voice activation threshold reached

•

RTC sec/min elapsed

•

10bit ADC end of conversion

content

•

I²S changed

•

USB changed

•

Charger changed

•

End of charge (at 10% of programmed current )

•

Battery temperature high (at 45°C with 100k

Ω

NTC)

•

Junction temperature high

•

RVDD low (e.g. after battery was changed)

•

Battery low (Brown-out voltage reached)

•

Wake-up from hibernation

•

Power-up key (pin PW RUP) pressed

•

Power rail monitor: over-voltage PVDD1, PVDD2, CVDD1, CVDD2

•

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

45

-

84

AS3518 V23

Data Sheet, Confidential

8.3.5 Real Time Clock

General

The real time clock block is an independent block, which is still working even when the chip is shut down. The only condition for this operation is that BVDDR has a voltage of above 1.0V. The block uses a standard 32kHz crystal that is connected to a low power oscillator. The total power consumption is typ. 650nA. (Q32k clock buffer not operating)

An internal supply switch will supply the RTC as long as possible form the single-cell or Li-Ion battery and only switch to BVDDR if the main battery is empty or has been removed.

The RTC seconds counter is 32bit wide and can be programmed via the 2-wire serial interface. The RTC can deliver a second or minute interrupt.

Another 23bit wide counter allows auto wake-up (max. after 96 days). This counter is internally connected to the power-up and hibernation control block.

The RTC voltage regulator (RVDD) further supplies a 128bit SRAM. It can be used to store settings or data before shutdown.

The Q32K output is able to drive also the PLL clock, the SPDIF output or a PWM signal. The output can be configured to be push/pull (3 different driver strengths) or open-drain.

Clock adjustment

The RTC clock is adjustable in steps of 7.6ppm which allows the use of inexpensive 32kHz crystals. The nominal frequency shall be 32.768Hz. This frequency is divided down to 0.25Hz: f = 32.768 / (4*32*1024) from –64 counts (=-488ppm) to +63 counts (=+480ppm): f corrected

= f crystal

/ [(4*32*1024)-64+RTC_TBC]

Register Description

AG still valid

Table 37 RTC Related Register

Name Base

OutContr

PMU ENABLE

RTC_WakeUp

IRQ_ENRD_2

2-wire serial

2-wire serial

2-wire serial

2-wire serial

IRQ_ENRD_4

RTCC

2-wire serial

2-wire serial

RTCT 2-wire serial

RTC_0 to RTC_3 2-wire serial

Offset

12h-1

18h

19h

25h

Description ams

27h

28h

Control of Q32K signal and drive

Enables writings to extended registers 12h-1

RTC wake-up settings and SDRAM access

content

29h RTC interrupt and time correction settings

2Ah to 2Dh RTC time-base seconds registers

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

46

-

84

AS3518 V23

Data Sheet, Confidential

8.3.6 10-Bit ADC

General

This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature supervision, button press detection, etc..

Input Sources

Table 38 ADC10 Input Sources

Nr. Source Range LSB Description

4

5

2

3

6

7

8

0

1

9

CHGOUT

BVDDR

CHGIN

BatTemp

MICS

VBE_1uA

VBE_2uA

5.120V 5mV check battery voltage of 4V Li-Ion accumulator

5.120V

5.120V

5.120V

2.560V

5mV check RTC backup battery voltage (connected to BVDD inside the package)

5mV Source defined by DC_TEST in register 0x18

5mV check charger input voltage reserved

2.5mV check battery charging temperature

valid

2.560V

1.024

1.024

1mV measuring basis-emitter voltage of temperature sense transistor;

Tj = (674 - [ADC_bit0:bit9]) / 2

1mV measuring basis-emitter voltage of temperature sense transistor;

Tj = (694 - [ADC_bit0:bit9]) / 2

1.024mA typ. 2.0uA check current of MICS for remote control detection

2.560V reserved

AG

2.5mV check single cell battery voltage

5mV check USB input voltage 5.120V

2.5mV check voltage on MICS for remote control or external voltage measurement reserved

still

10

11

12

13

I_MICS

VB1V

VBUS

14..15

Reference

Reserved 1.024V 1mV for testing purpose only the absolute accuracy is +/-1%. Including divider and gain stages an overall accuracy of 3% is achieved.

Parameter

Table 39 ADC10 Parameter

Symbol

R

DIV

ADC

FS

Ratio1

Ratio2

Gain

T

CON

I_MIC

FS

Parameter ams

Conditions

Input Divider Resistance CHGOUT, BVDDR, VBUS, CHGIN

Min Typ Max Unit

138k 180k 234k

ADC Full Scale Range

Division Factor 1

Division Factor 2

ADC Gain Stage

Conversion Time

I_MICS Full Scale Range

VB1V, RVDD, BATTEMP, MICS

2.534 2.56 2.586

CHGOUT, BVDDR, VBUS, CHGIN 0.198

0.396

2.475

-

0.7

0.2

0.4

2.5

34

1.0

0.202

0.404

2.525

50

1.4

Ω

V

1

1

µs mA

BVDD=3.6V; T amb

=25ºC; unless otherwise specified

Register Description

Name

Technical

ADC_0

ADC_1

2-wire serial

2-wire serial

2-wire serial

2 wire serial

18h

27h

2Eh

2Fh

Description

Extended ADC source selection

Interrupt settings for end of conversion interrupt

ADC source selection, ADC result<9:8>

ADC result <7:0>

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

47

-

84

AS3518 V23

Data Sheet, Confidential

8.3.7 Unique ID Code (64 bit OTP ROM)

General

This fuse array is used to store a unique identification number, which can be used for DRM issues. The number is generated and programmed during the production process.

Register Description

Table 41 UID Related Register

Name

UID_0 to UID_7

Base

2-wire serial

Offset Description

38h to 3Fh Unique ID register 0 to 7

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

48

-

84

AS3518 V23

Data Sheet, Confidential

8.4 Register Description

Table 42 I2C Register Overview

D<5>

-

D<4> D<3> D<2> D<1>

LOR_VOL

Gain from MUX_B to LOUT1R= (-40.5dB … +6dB)

D<0> Addr Name D<7>

0

01h LINE_OUT_L -

D<6>

00h LINE_OUT_R LO_MUX_B

0:SUM_Stereo;1:SUM_MDiff

2:ADC_IN; 3:DAC_OUT

0

MUTE_OFF

_J

0

-

0 0

HP_MUTE_C

0:SUM_Stereo;1: DAC_OUT

2:LineIn 1/3; 3: LineIn 2

0

HPR_VOL

0 0 0

Gain from MUX_C to HPR= (-45.43dB … +1.07dB)

0 0

02h HPH_OUT_R HP_OVC_

TO_OFF

0: 256ms

0

03h HPH_OUT_L MUTE_ON_

K

06h MIC_R

07h MIC_L

0Ah LINE_IN1_R -

0

0

MIC_AGC

_OFF

0

MSUP

_OFF

0

HP_ON

0 0

PRE_GAIN

0: 28dB; 1: 34dB

2: 40dB

0

MUTE_OFF

_D

0

RDET_

OFF

0

LI_MUX_E

0: LI1; 1: LI3

0

0Bh LINE_IN1_L LI1_MODE

0

00: SE_Sterep; 01: MonoDiff

10: SE_Mono

0 0

0Ch LINE_IN2_R - -

0

0Dh LINE_IN2_L LI2_MODE

0

00: SE_Sterep; 01: MonoDiff

10: SE_Mono

0Eh DAC_R

0

-

0

-

0

0

-

0 0

HPDET_ON HPL_VOL

0 0 0

Gain from MUX_C to HPL= (-45.43dB … +1.07dB)

MUTE_OFF

_B

0

MUTE_OFF

_G

0

MUTE_OFF

_C

0

MUTE_OFF

_F

0

0

ML_VOL

Gain from MicAmp (N6) to Mixer (N13) = (-40.5dB … +6.0dB)

0

LI1R_VOL

0

MR_VOL

Gain from MicAmp (N6) to Mixer (N12) = (-40.5dB … +6.0dB)

0

AG

0

0

0

0

0

0

still

0

0

0

0

Gain from LIN1R to Mixer (N10)= (-34.5dB … +12dB)

0 0 0 0 0

LI1L_VOL

Gain from LIN1L to Mixer (N17)= (-34.5dB … +12dB)

0

LI2R_VOL

0 0 0 0

Gain from LIN2R to Mixer (N11)= (-34.5dB … +12dB)

0 0 0 0 0

LI2L_VOL

Gain from LIN2L to Mixer (N16)= (-34.5dB … +12dB)

valid

0

DAR_VOL

0 0 0 0

Gain from DAC (N19) to Mixer/MUX (N23)= (-40.5dB … +6dB)

0Fh DAC_L

10h ADC_R

11h

0

-

0

-

Technical

0

-

0

ADC_MUX_A

-

0

0

MUTE_OFF

_H

0

0: Stereo_Mic; 1:LineIN_1/3

2: LineIN_2; 3: AudioSUM

0 0

MUTE_OFF

_A

0

0

-

0

LOL_VOL

0 0 0

Gain from MUX_B to LOUT1L= (-40.5dB … +6dB)

0

0

DAL_VOL

0 0 0 0

Gain from DAC (N22) to Mixer/MUX (N26) = (-40.5dB … +6dB)

0 0 0 0 0

ADR_VOL

Gain from MUX_A to ADC (N9) = (-34.5dB … +12dB)

0

ADL_VOL

0 0 0 0

Gain from MUX_A to ADC (N18) = (-34.5dB … +12dB)

0 0 0 0 0

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

49

-

84

AS3518 V23

Data Sheet, Confidential

Addr Name D<7>

0

16h AudioSet_3 LIN1MIX_O

FF

0

17h-1 PMU PVDD1 LDO_PVDD

1_OFF

0

17h-2 PMU PVDD2 LDO_PVDD

2_OFF

0

17h-3 PMU CVDD1 SKIP_OFF_

CVDD1

0

17h-4 PMU CVDD2 SKIP_OFF_

CVDD2

0

0

17h-6 PMU Hibernate -

D<6>

0

LIN2MIX_O

FF

0

ILIM_HIGH

_PVDD1

0

ILIM_HIGH

_PVDD2

0

PROG_

CVDD1

0

0

PROG_

CVDD2

D<5>

12h-1 OutContr

12h-2 SPDIF

12h-3 PWM

14h AudioSet_1

DRIVE_PWGD

0: 12mA OD; 1: 12mA PP

2: 4mA PP; 3: 2mA PP

0 0

-

0

PWM_

INVERTED

0

0

MUX_PWGD

0: PWGD; 1: PWM

2: SPDIF; 3: PLL clock

0 0

-

0

PWM_CYCLE

ADC_R_ON ADC_L_ON -

SPDIF_

COPY_OK

0

DRIVE_Q32K

0: 12mA PP; 1: 12mA OD

2: 4mA PP; 3: 2mA PP

0

SPDIF_

MCLK_INV

0

0: no pulses; DytyCycle = PWM_CYCLE * 0.3937%

0

SPDIF_

INVALID

0

0 0

0 0 0 0

15h AudioSet_2 BIAS_OFF SUM_OFF AGC_OFF -

0 0 0 0

LOUT_ON LIN2_ON LIN1_ON -

0 0 0

DAC_ON -

MUX_Q32K

0: Q32K; 1: PWM

2: SPDIF; 3: PLL clock

0 0

SPDIF_CNTR

0: OFF; 1: 32kS

2: 44.1kS; 3: 48kS

0 0

0

MIC_ON

0

0

MICMIX_O

FF

0

PROG_

PVDD1

D<4> D<3>

0

D<2> D<1>

0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV



0.65V – 3.40V; (38h – 3Fh …. 3.4V)

0

0

-

0 0

VSEL_CVDD2

0

DACMIX_O

FF

0

AG

0

0

-

0

0

0

still

D<0>

0

IBR_HPH HPCM_ON

0

VSEL_PVDD1

0 0

0h – Fh:1.2V+VSEL*50mV (1.2V – 1.95V)

10h – 1Fh: 2.0V+(VSEL-10h)*100mV (2.0V – 3.5V)

0 0 0

PROG_

PVDD2

0 0

VSEL_PVDD2

0h – Fh:1.2V+VSEL*50mV (1.2V – 1.95V)

10h – 1Fh: 2.0V+(VSEL-10h)*100mV (2.0V – 3.5V)

0 0

VSEL_CVDD1

0 0 0

0h: OFF; 1h - 38h …. 0.6V+VSEL*50mV



0.65V – 3.40V; (38h – 3Fh …. 3.4V)

0

0

0 0 0

0

0

0

valid

17h-7 DCDC

0

18h PMU Enable -

0

-

0

-

0

0

KEEP_

ams

0

0

0 0

DC_TEST_MUX

0

0: unused; 1: AVDD; 2: DVDD; 3: PVDD1

4: PVDD2; 5: CVDD1; 6; CVDD2; 7:RVDD

0

0

0

-

0

content

0

KEEP_

CVDD2

0

DCDC3p

0: 3.6V; 1: 3.2V

2: 3.1V; 3: 3.0V

0

0

KEEP_

CVDD1

0

0 0

PMU_GATE PMU_WR_ENABLE

0

0: unused

1: prog 17h-1 / 12h-1 (PVDD1, OutContr1)

2: prog 17h-2 / 12h-2 (PVDD2, OutContr2)

3: prog 17h-3 / 12h-3 (CVDD1, PWM)

4: prog 17h-4 (CVDD2)

5: unsused

6: prog 17h-6 (Hibernate)

7: prog 17h-7 (DCDC3);

0 0 0

19h RTC_WakeUp 1 st

write/read: WAKEUP_BYTE_1

128s 64s 32s

2 nd

write/read: WAKEUP_BYTE_2

1Ah

1Bh

32ks 16ks 8ks

3 rd

wirte/read: WAKEUP_BYTE_3

WAKEUP_ON 4k*1ks 2k*1ks 1k*1Ks 512ks

4 th

to 19 th

write/read: non volatile memory bytes<0:15> (128bit)

256ks

Technical

xDOWN

0

0

DIM_RATE

0

0: no dimming; 1: 150ms

2: 300ms; 3: 500ms

0 0

0

16s

4ks

-

0

8s

2ks

0

4s

1ks

0

2s

512s

128ks

VBUS_COMP_TH

0: 4.5V; 1: 3.18V

2: 1.5V; 3: 0.6V

0 0

I2S_

DIRECT

0

I_BACKLIGHT

0

0 … OFF

1-30 … LED current = 1.25mA*I_BACKLIGHT (1.2mA … 36mA)

31 … voltage feedback mode

0 0 0 0

1s

256s

64ks

0

PLL_MODE

0: 16-48kS;

1: 8-12kS

0

0

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

50

-

84

AS3518 V23

Data Sheet, Confidential

Addr Name D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0>

20h SYSTEM Design_Version<3:0> PWR_HOLD

38-3F UID_0 .. 7

X X X

ID<7:0>

…

ID<63:56>

Technical

HBT_WD_

ON

JTEMP_

OFF

I2C_WD_

ON

1

21h SUPERVISOR BVDD_SUP

22h CHARGER

V_BrownOut = 2..74V+BVDD_SUP*60mV

(2.74V .. 3.16V)

0

BAT_TEMP

_OFF

0

23h IRQ_ENRD_0 CVDD2_

EN_SD

CVDD2_

UNDER

0

24h IRQ_ENRD_1 SD_TIME

0: 5.4s

1: 10.9s

1

0

CHG_I

0

1

0..3: 55, 70, 140, 210mA

4..7: 280, 350, 420, 460mA

0 0

0

-

CVDD2_

EN_IRQ

CVDD2_

OVER

CVDD1_

EN_SD

CVDD1_

UNDER

0

PWRUP_

IRQ

0

JTEMP_SUP

0 0 0

Temp_ShutDown = 140C – JTEMP_SUP*5C (+140C..-15C)

Temp_IRQ = 120C – JTEMP_SUP*5C (+120C .. -35C)

0 0 0

0

CVDD1_

EN_IRQ

CVDD1_

OVER

0

WAKEUP_

IRQ

0

-

0

CHG_V

Vchg=3.9V+50mV*CHG_V

(3.9V … 4.25V)

0 0

PDD2_

EN_SD

PDD2_

UNDER

PDD2_

EN_IRQ

PDD2_

OVER

0

VOXM_

IRQ

-

0

PDD1_

EN_SD

PDD1_

UNDER

0

content

0

0

-

0

0

-

1

0

CHG_OFF

0

PDD1_

EN_IRQ

PDD1_

OVER

0

-

valid

0

25h IRQ_ENRD_2 BATTEMP_

HIGH

26h IRQ_ENRD_3

0

JTEMP_

HIGH

0

0

-

CHG_EOC CHG_CON CHG_ changed

0

-

0

27h IRQ_ENRD_4 T_DEB

0: 512ms; 1: 256ms

2: 128ms; 3: 0ms

0 0

28h RTC_Cntr

29h RTC_Time

2Ah

2Bh

2Dh

2Eh

2Fh

RTC_0

RTC_1

2Ch RTC_2

RTC_3

ADC10_0

ADC10_1

-

0 0

IRQ_MIN TRTC<6:0>

0 1

QRTC<7:0>

0

QRTC<15:8>

0

0

-

0

HP_

OVC

0

XIRQ_AH XIRQ_PP

0

1

0

0

0

0

I2S_

STATUS

0

0

0

0

0

0 0

QRTC<23:16>

0 0

QRTC<31:24>

0

0

0

0

0 0

ADC10_MUX<3:0>

0 0

0: CHGOUT; 1: BVDDR; 2: DC_TEST; 3: CHG_IN; 4:reserved;

5: BatTemp; 6: MICS; 7: reserved; 8: VBE_1uA; 9: VBE_2uA;

10: I_MICS; 11: reserved; 12: VB1V; 13: VBUS; 14, 15: reserved

0 0 0 0

ADC10<7:0>

0

CHG_IRQ -

USB_CON USB_ changed

0

0

-

0

0

0

0

0 0

USB_IRQ RVDD_LOW BVDD_LOW

0

0

REM_DET RTC_

0

0

0

0

0

0

MIC_

CONNECT

0

UPDATE

0

0

HPH_

CONNECT

0

ADC_EOC

0

RTC_ON OSC32_ON

1

0

0

0

0

0

ADC10<9:8>

X

0

1

0

0

0

0

0

X

X X X X X

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

51

-

84

AS3518 V23

Data Sheet, Confidential

Table 43 LINE_OUT_R Register

Base

2-wire serial

Default

00h

Name

LINE_OUT_R

Offset: 00h

Right Line Output Register

Configures MUX_B and the audio gain from MUX_B output to LOUTR output.

This register is reset when the block is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default Access Bit Description Bit Bit Name

7:6 LO_MUX_B

5

4:0 LOR_VOL

Name

LINE_OUT_L

00

0

00000

Table 44 LINE_OUT_L Register

R/W n/a

R/W

Base

Multiplexes the analog audio inputs to MUX_B output at

LOUTR and at LOUTL

00: SUM Stereo: ΣR to LOUT1R and ΣL to LOUT1L

01: SUM Mono Differential: ΣR+ ΣL to LOUT1L and -LOUT1L to LOUT1R. The gain of LOUT1R shall be 0dB to hold signals in symmetry

10b = ADC (N9/N18)

11b = DAC (N23/N26) volume settings for right line output, adjustable in

32 steps @ 1.5dB; gain from MUX_B to LOUTR

11111: 6 dB gain

11110: 4.5 dB gain

..

00001: -39 dB gain

00000: -40.5 dB gain

still

Default valid

2-wire serial

AG

00h

Left Line Output Register

Offset: 01h

Bit Bit Name

7

6 MUTE_OFF_J

5

4:0 LOL_VOL

Configures the audio gain from MUX_B output to LOUTL output and controls

MUTE switch J

This register is reset when the stage is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default

0

0b

0

00000

ams

n/a

R/W n/a

R/W

Control of MUTE switch J

0:line output set to mute

1: normal operation volume settings for left line output, adjustable in

32 steps @ 1.5dB; gain from MUX_B to LOUTL

11111: 6 dB gain

11110: 4.5 dB gain

..

00001: -39 dB gain

00000: -40.5 dB gain

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

52

-

84

AS3518 V23

Data Sheet, Confidential

Table 45 HPH_OUT_R Register

Base

2-wire serial

Default

00h

Name

HPH_OUT_R

Offset: 02h

Right Headphone Output Register

Configures MUX_C and the audio gain from MUX_C output to HPR output.

This register is reset at a DVDD-POR.

Default Access Bit Description Bit Bit Name

7

6:5 HP_MUX_C

4:0 HPR_VOL

Table 46 HPH_OUT_L Register

Name

HP_OVC_TO_OFF

HPH_OUT_L

00

00

00000

R/W

R/W

R/W

Base

Headphone amplifier over current time out. The headphone amplifier is powered down if a over-current is detected. The current thresholds are 150mA at pins HPR / HPL pin or 300mA at pin HPCM (e.g. shorted headphone outputs)

1: 0 ms ( no power down)

0: 256 ms

00: MUX_C output connected to limiter (N24/N25)

01: MUX_C output connected to DAC (N23/N26)

10: MUX_C output connected to LineIn 1/3 (N10/N17)

11: MUX_C output connected to LineIn 2 (N11/N16) volume settings for right headphone output, adjustable in 32 steps @ 1.5dB; gain from MUX_C to HPR output

11111: 1.07 dB gain

11110: -0.43 dB gain

..

00001: -43.93 dB gain

00000: -45.43 dB gain

still

Default valid

2-wire serial

AG

00h

Left Headphone Output Register

Offset: 03h

Bit Bit Name

7

6

5

MUTE_ON_K

HP_ON

HPDET_ON

4:0 HPL_VOL

Configures the audio gain from MUX_C output to HPL output and controls

MUTE switch K

This register is reset at a DVDD-POR.

Default

0

0

0

00000

ams

R/W

R/W

R/W

Technical content

1: power up headphone stage

Enables the detection when a headset gets connected. HPCM is used as a sense pin and is biased to 150mV

0: no headphone detection

1: enable headphone detection volume settings for left headphone output, adjustable in 32 steps @ 1.5dB; gain from MUX_C output to HPL output

11111: 1.07 dB gain

11110: -0.43 dB gain

..

00001: -43.93 dB gain

00000: -45.43 dB gain

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

53

-

84

AS3518 V23

Data Sheet, Confidential

Table 47 MIC_R Register

Name

MIC_R

Offset: 06h

Bit Bit Name

7 MIC_AGC_OFF

6:5 PRE_Gain

4:0 MR_VOL

Table 48 MIC_L Register

Default

00h

Base

2-wire serial

Right Microphone Input Register

Configures the gain from microphone amplifier output up to mixer input (Σ).

This register is reset when the block is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default

0

00

00000

R/W

R/W

Access Bit Description

R/W Control of limiter AGC (automatic gain control). Limits high dynamic range of electrete/MEMS microphone (e.g. user shouts or blows into microphone)

0: automatic gain control enabled

1: automatic gain control disabled

Sets the gain of the microphone preamplifier (gain from microphone inputs to N3)

00: gain set to 28 dB

01: gain set to 34 dB

10: gain set to 40 dB

11: reserved, do not use. volume settings for right microphone input, adjustable in 32 steps @ 1.5dB; gain from microphone amplifier (N4) to mixer input (N12)

11111: 6 dB gain

11110: 4.5 dB gain

..

AG still valid

Name

MIC_L

Offset: 07h

Bit Bit Name

7

6

5

MSUP_OFF

MUTE_OFF_D

RDET_OFF

4:0 ML_VOL

Base

2-wire serial ams

Default

00h

Configures the gain from microphone amplifier output up to mixer input (Σ) and controls

MUTE switch D.

This register is reset when the block is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default

0

0

0

00000

R/W

R/W

R/W

R/W

Access content

Technical

0: microphone supply enabled

1: microphone supply disabled

Control of MUTE switch D

0: microphone input set to mute

1: normal operation

Disables the microphone detect function (30kOhm pull-up from

MICS to AVDD) to use the terminal as ADC-10 input

0: microphone detection enabled

1: microphone detection disabled volume settings for left microphone input, adjustable in 32 steps @ 1.5dB; gain from microphone amplifier (N4) to mixer input (N13)

11111: 6 dB gain

11110: 4.5 dB gain

..

00001: -39 dB gain

00000: -40.5 dB gain

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

54

-

84

AS3518 V23

Data Sheet, Confidential

Table 49 LINE_IN1_R Register

Base

2-wire serial

Default

00h

Name

LINE_IN1_R

Offset: 0Ah

Right Line Input 1 Registers

Configures the gain from analog line input pin LIN1R to mixer input (Σ) and controls

MUTE switch B.

This register is reset when the block is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default Access Bit Description Bit Bit Name

7

6

5

LI_MUX_E

MUTE_OFF_B

4:0 LI1R_VOL

0

0

0

00000 n/a

R/W

R/W

R/W

0: MUX_E output connected to Line Input 1

1: MUX_E output connected to Line Input 3

Control of MUTE switch B

0: right line input is set to mute

1: normal operation volume settings for right line input 1, adjustable in 32 steps @

1.5dB; gain from line input pin (LIN1R) to mixer input (N10)

11111: 12 dB gain

11110: 10.5 dB gain

..

00001: -33 dB gain

00000: -34.5 dB gain

Table 50 LINE_IN1_L Register

Name

LINE_IN1_L

Base

2-wire serial

Left Line Input 1 Registers

AG

Default

00h still valid

Offset: 0Bh

Bit Bit Name

7:6 LI1_MODE

5 MUTE_OFF_G

4:0 LI1L_VOL

Configures the gain from analog line input pin LIN1L to mixer input (Σ) and controls

MUTE switch G.

This register is reset when the block is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default

00

0

00000

R/W

R/W

Configures Line Input 1 (right and left channel) in accordance

content

11: reserved, do not use.

Control of MUTE switch G

0: left line input is set to mute

1: normal operation volume settings for right line input 1, adjustable in 32 steps @

1.5dB; gain from line input pin (LIN1L) to mixer input (N17)

11111: 12 dB gain

11110: 10.5 dB gain

..

00001: -33 dB gain

00000: -34.5 dB gain

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

55

-

84

AS3518 V23

Data Sheet, Confidential

Table 51 LINE_IN2_R Register

Base

2-wire serial

Default

00h

Name

LINE_IN2_R

Offset: 0Ch

Right Line Input 2 Register

Configures the gain from analog line input pin LIN2R to mixer input (Σ) and controls

MUTE switch C.

This register is reset when the block is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default Access Bit Description Bit Bit Name

7:6

5 MUTE_OFF_C

4:0 LI2R_VOL

Table 52 LINE_IN2_L Register

Name

LINE_IN2_L

Offset: 0Dh

00

0

00000 n/a

R/W

R/W

Base

Control of MUTE switch C

0: right line input is set to mute

1: normal operation volume settings for right line input, adjustable in 32 steps @

1.5dB; gain from line input pin (LIN2R) to mixer input (N11)

11111: 12 dB gain

11110: 10.5 dB gain

..

00001: -33 dB gain

00000: -34.5 dB gain

valid

2-wire serial

Left Line Input 2 Registers

AG

Default

00h still

Configures the gain from analog line input pin LIN2L to mixer input (Σ) and controls

MUTE switch F.

This register is reset when the block is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Bit Bit Name

7:6 LI2_MODE

5 MUTE_OFF_F

4:0 LI2L_VOL

Default

00

0

00000

Access Bit Description

R/W

R/W

Configures Line Input 2 (right and left channel) in accordance with the connected input sources

00: inputs switched to single ended stereo content

0: left line input is set to mute

1: normal operation volume settings for right line input, adjustable in 32 steps @

1.5dB; gain from line input pin (LIN2L) to mixer input (N16)

11111: 12 dB gain

11110: 10.5 dB gain

..

00001: -33 dB gain

00000: -34.5 dB gain

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

56

-

84

AS3518 V23

Data Sheet, Confidential

Table 53 DAC_R Register

Name

DAC_R

Offset: 0Eh

Bit Bit Name

7:5

4:0 DAR_VOL

Table 54 DAC_L Register

Name

DAC_L

Offset: 0Fh

Bit Bit Name

7

6 MUTE_OFF_H

5

4:0 DAL_VOL

Default

00h

Base

2-wire serial

Right DAC Output Registers

Configures the gain from DAC output to mixer input (Σ) / MUX input.

This register is reset when the block is disabled in AudioSet2 register (15h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default Access Bit Description

000

00000 n/a

R/W

Base

Volume settings for right DAC output, adjustable in 32 steps @

1.5dB; gain from DAC output (N19) to mixer/MUX input (N23).

11111: 6 dB gain

11110: 4.5 dB gain

..

00001: -39 dB gain

00000: -40.5 dB gain

valid

Default

0

0

2-wire serial

Left DAC output Registers

00h

Configures the gain from DAC output to mixer input (Σ) / MUX input and controls MUTE switch H.

still

DVDD-POR. The register cannot be written when the block is disabled.

Default

0

00000 n/a

R/W

Access

AG

Control of MUTE switch H

0: DAC output is set to mute

1: normal operation

Volume settings for left DAC output, adjustable in 32 steps @

1.5dB: gain from DAC output (N22) to mixer/MUX input (N26).

11111: 6 dB gain

11110: 4.5 dB gain

..

00001: -39 dB gain

00000: -40.5 dB gain

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

57

-

84

AS3518 V23

Data Sheet, Confidential

Table 55 ADC_R Register

Name

ADC_R

Offset: 10h

Bit Bit Name

7:6 ADC_MUX_A

5

4:0 ADR_VOL

Table 56 ADC_L Register

Name

ADC_L

Offset: 11h

Bit Bit Name

7

6 MUTE_OFF_A

5

4:0 ADL_VOL

Default

00h

Base

2-wire serial

Right ADC input Registers

Configures MUX_A and the gain from MUX_A output to the ADC input

This register is reset when the block is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default Access Bit Description

00

0

00000

R/W n/a

R/W

Connect MUX A output to following inputs

00: Microphone (N4/N4)

01: Line_IN1/3 (N1/N8)

10: Line_IN2 (N2/N7)

11: Audio SUM (N24/N25)

Volume settings for right ADC input, adjustable in 32 steps @

1.5dB; gain from MUX_A output to ADC input (N9).

11111: 12 dB gain

11110: 10.5 dB gain

..

00001: -33 dB gain

00000: -34.5 dB gain

Default

00h still valid

Base

2-wire serial

Left ADC input Registers

AG

Configures the gain from MUX_A output to the ADC input and controls MUTE switch A.

This register is reset when the block is disabled in AudioSet1 register (14h) or at a

DVDD-POR. The register cannot be written when the block is disabled.

Default

0

0

Access Bit Description ams

0

00000 n/a

R/W

Control of MUTE switch A

0: ADC input is set to mute content

11111: 12 dB gain

11110: 10.5 dB gain

..

00001: -33 dB gain

00000: -34.5 dB gain

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

58

-

84

AS3518 V23

Data Sheet, Confidential

Table 57 Output Control Register

Name

OutContr

Offset: 12h-1

Bit Bit Name

7:6 DRIVE_PWGD

5:4 MUX_PWGD

3:2 DRIVE_Q32K

1:0 MUX_Q32K

Default

00h

Base

2-wire serial

00

00

00

Q32k and PWGD Output Control Register

Configures PWGD pin (Power Good) and Q32k pin (output of 32kHz oscillator).

This is an extended register and needs to be enabled by writing 001b to Reg. 18h first.

This register is reset at a DVDD-POR.

Default

00

R/W

R/W

R/W

Access Bit Description

R/W Enables the PWGD output pin either to open-drain or push-pull and sets various driving strengths

00: 12mA push-pull output

01: 12mA open-drain output

10: 4mA push-pull output

11: 2mA push-pull output

Multiplexes various digital signals to the PWGD output pin

00: PowerGood control signal

01: PWM signal to dim LEDs etc.

10: SPDIF converted from SDI to DAC

11: PLL output clock

Enables the Q32k output pin either to open-drain or push-pull and sets various driving strengths

00: 12mA push-pull output

01: 12mA open-drain output

AG

01: PWM signal to dim LEDs etc.

10: SPDIF converted from SDI to DAC

11: PLL output clock

still valid

Table 58 SPDIF Register

Name

SPDIF

Offset: 12h-2

Bit Bit Name

7:5

4 SPDIF_COPY_OK

3

2

SPDIF_MCLK_INV

SPDIF_INVALID

1:0 SPDIF_CNTR

000

0

0

0

00

Adds status bits to the SPDIF bitstream and configures the SPDIF output.

This is an extended register and needs to be enabled by writing 010b to Reg. 18h first.

This register is reset at a DVDD-POR.

Default

2-wire serial

SPDIF Output Control Register

Default

00h content

Access Bit Description

n/a

R/W

Technical

SPDIF copy control bit

0: copy not permitted

1: copy permitted

SPDIF master clock control bit

0: master clock

1: master clock inverted

SPDIF sample status bit

0: sample valid

1: sample invalid

SPDIF output ON/OFF control and sample rate status bits

00: SPDIF output OFF

01: SPDIF output ON (32kS)

10: SPDIF output ON (44.1kS)

11: SPDIF output ON (48kS)

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

59

-

84

AS3518 V23

Data Sheet, Confidential

Table 59 PWM Register

Base

2-wire serial

Default

00h

Name

PWM

Offset: 12h-3

PWM Output Control Register

Sets the PWM output duty cycle and signal polarity.

This is an extended register and needs to be enabled by writing 011b to Reg. 18h first.

This register is reset at a DVDD-POR.

Default Access Bit Description Bit Bit Name

7 PWM_INVERTED

6:0 PWM_CYCLE

7

6

5

4

3

2

1

0

ADC_L_ON

LOUT_ON

LIN2_ON

LIN1_ON

MIC_ON

0

0

0

0

0

0

0

0

R/W

0000000 R/W

Table 60 AudioSet_1 Register

Name

AudioSet_1

Offset: 14h

Bit Bit Name

Base

2-wire serial

First Audio Set Register

Default

00h

Powers the various audio inputs and outputs UP or DOWN.

Attention: This control register resets and holds microphone, line out, and ADC related registers in reset. After activation the required register settings need to be reprogrammed.

This register is reset at a DVDD-POR.

still

Default

0

valid

ADC_R_ON

PWM output polarity

0: not inverted

1: inverted

Sets the PWM duty cycle

Duty Cycle = PWM_CYCLE * 0.3937%

PWM_CYCLE = 0 means no pulse n/a

R/W

R/W n/a

R/W

R/W

R/W

Access

AG

0: ADC right channel powered down

1: ADC right channel enabled for recording

0: ADC left channel powered down

1: ADC left channel enabled for recording

0: Line output powered down

1: Line output enabled

0: Line input 2 powered down

content

0: Microphone input powered down

1: Microphone input 1 enabled

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

60

-

84

AS3518 V23

Data Sheet, Confidential

Table 61 AudioSet_2 Register

Name

AudioSet_2

Offset: 15h

Bit Bit Name

7 BIAS_OFF

6

5

4:3

2 DAC_ON

1:0

SUM_OFF

AGC_OFF

Default

00h

Base

2-wire serial

0

0

00

0

00

Second Audio Set Register

Powers various internal audio blocks UP or DOWN and controls bias current.

Attention: This control register resets and holds DAC related registers in reset. After activation the required register settings need to be re-programmed.

This register is reset at a DVDD-POR.

Default

0

R/W

R/W n/a

R/W n/a

Access Bit Description

R/W Power-down of the AGND bias. This bit can be set, if the AFE is used for digital data transfer and PMU functions only and all the analog audio blocks are not used.

0: bias enabled

1: bias disabled, for power saving in non audio mode

Power-down of ΣR and ΣL

0: Mixer stage enabled (limits output signal to 1Vp)

1: Mixer stage powered down

Switches the signal limiter OFF (N20/N21)

0: automatic gain control for summing stage enabled

1: automatic gain control for summing stage disabled

0: DAC powered down

1: DAC enabled

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

61

-

84

AS3518 V23

Data Sheet, Confidential

Table 62 AudioSet_3 Register

Base

2-wire serial

Default

00h

Name

AudioSet_3

Offset: 16h

Bit Bit Name

7 LIN1MIX_OFF

6

5

2

1

4

3

0

LIN2MIX_OFF

MICMIX_OFF

DACMIX_OFF

IBR_HPH

HPCM_ON

0

0

0

0

0

0

0

Third Audio Set Register

Sets headphone output bias currents and operation modes and enables audio signal inputs to ΣR and ΣL.

This register is reset at a DVDD-POR.

Default

0

R/W

R/W n/a

R/W n/a

R/W

R/W

Access Bit Description

R/W Input from line input 1 to ΣR and ΣL

0: ON

1: OFF

Input from line input 2 to ΣR and ΣL

0: ON

1: OFF

Input from microphone 1 to ΣR and ΣL

0: ON

1: OFF

Input from DAC to ΣR and ΣL

0: ON

1: OFF

Bias current increase for the headphone amplifier depending on load conditions

0: 100%

1: 150%

AG

0: headphone CM buffer is switched off

1: headphone CM buffer is switched on

still valid

6

5

Table 63 PMU PVDD1 Register

Name

PMU PVDD1

Offset: 17h-1

Bit Bit Name

7 LDO_PVDD1_OFF

ams

This is an extended register and needs to be enabled by writing 001b to Reg. 18h first.

This register is reset at a DVDD-POR.

Default

0

Access Bit Description

R/W

Default

00h

PVDD1 Low Drop-Out Regulator (LDO3) Control Register content

ILIM_HIGH_PVDD1 0

PROG_PVDD1

4:0 VSEL_PVDD1

0

00000

R/W

R/W

R/W

Technical

Power-down of LDO for PVDD1

0: PVDD1 (LDO3) enable

1: PVDD1 (LDO3) power-down

Sets the current limit for PVDD1

0: 200mA current limit

1: 350mA current limit

Enables settings either selected by external pin (VPRG1) or settings stored in the 17h-1 register

0: VPRG1 pin controlled

1: Register controlled

The voltage select bits set the LDO output in 2 different resolution ranges

Range: 00h until 0Fh in 50mV steps

PVDD1=1.2V+VSEL_PVDD1*50mV

(1.2V until 1.95V)

Range: 10h until 1Fh in 100mV steps

PVDD1=2.0V+VSEL_PVDD1*100mV

(2.0V until 3.5V)

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

62

-

84

AS3518 V23

Data Sheet, Confidential

Table 64 PMU PVDD2 Register

Name

PMU PVDD2

Base

2-wire serial

Default

00h

Offset: 17h-2

Bit Bit Name

7 LDO_PVDD2_OFF

6

5

4:0 VSEL_PVDD2

Name

ILIM_HIGH_PVDD2 0

PROG_PVDD2

PMU CVDD1

PVDD2 Low Drop-Out Regulator (LDO4) Control Register

This is an extended register and needs to be enabled by writing 010b to Reg. 18h first.

This register is reset at a DVDD-POR.

Default

0

Access Bit Description

0

00000

Table 65 PMU CVDD1 Register

R/W

R/W

R/W

R/W

Base

Power-down of LDO for PVDD2

0: PVDD2 (LDO4) enable

1: PVDD2 (LDO4) power-down

Sets the current limit for PVDD2

0: 200mA current limit

1: 350mA current limit

Enables settings either selected by external pin (VPRG1) or settings stored in the 17h-2 register

0: VPRG1 pin controlled

1: Register controlled

The voltage select bits set the LDO output in 2 different resolution ranges

Range: 00h until 0Fh in 50mV steps

PVDD2=1.2V+VSEL_PVDD2*50mV

(1.2V until 1.95V)

Range: 10h until 1Fh in 100mV steps

PVDD2=2.0V+VSEL_PVDD2*100mV

(2.0V until 3.5V)

still valid

2-wire serial

AG

Default

00h

Offset: 17h-3

Bit Bit Name

7 SKIP_OFF_CVDD1

6 PROG_CVDD1

5:0 VSEL_CVDD1

CVDD1 DC/DC Buck Regulator Control Register

This is an extended register and needs to be enabled by writing 011b to Reg. 18h first.

This register is reset at a DVDD-POR.

Default

0

0

00000

R/W

R/W

content

Enables settings either selected by external pin (VPRG1) or settings stored in the 17h-3 register

0: VPRG1 pin controlled

1: Register controlled

The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down.

00000: DC/DC powered down

01h until 38h in 50mV steps

CVDD1=0.6V+VSEL_CVDD1*50mV

(0.65V until 3.4V)

38h until 3Fh = 3.4V (no change)

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

63

-

84

AS3518 V23

Data Sheet, Confidential

Table 66 PMU CVDD2 Register

Base

2-wire serial

Default

0x00

Name

PMU CVDD2

Offset: 17h-4

CVDD2 DC/DC Buck Regulator Control Register

This is an extended register and needs to be enabled by writing 100bto Reg. 18h first.

This register is reset at a DVDD-POR.

Default Access Bit Description Bit Bit Name

7

6

5:0 VSEL_CVDD2

Bit Bit Name

7:6

5 KEEP_PVDD1

4:2

1 KEEP_CVDD2

0

SKIP_OFF_CVDD2

PROG_CVDD2

KEEP_CVDD1

0

0

00000

R/W

R/W

R/W

Table 67 PMU Hibernate Register

Name

PMU Hibernate

Base

2-wire serial

AG

Offset: 17h-6

Disables pulse skip mode

0: 170mA current force / pulse skip mode enabled

1: current force / pulse skip mode disabled (only ON without load)

Enables settings either selected by external pin (VPRG1) or settings stored in the 17h-4 register

0: VPRG1 pin controlled

1: Register controlled

The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down.

00000b: DC/DC powered down

01h until 38h in 50mV steps

CVDD2=0.6V+VSEL_CVDD2*50mV

(0.65V until 3.4V)

38h until 3Fh = 3.4V (no change)

Default still

00h valid

0

0

Hibernation is started when writing to this register.

This is an extended register and needs to be enabled by writing 110b to Reg. 18h first.

This register is reset at a DVDD-POR.

0

Default

0

0

ams

n/a

R/W

R/W

Keeps the programmed PVDD1 level during hibernation

content

0: power down CVDD2

1: keep CVDD2

Keeps the programmed CVDD1 level during hibernation

0: power down CVDD1

1: keep CVDD1

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

64

-

84

AS3518 V23

Data Sheet, Confidential

Table 68 PMU DCDC 3V Register

Base

2-wire serial

Default

00h

Name

PMU Hibernate

Offset: 17h-7

BVDD DC/DC Boost Regulator Control Register

This is an extended register and needs to be enabled by writing 111b to Reg. 18h first.

This register is reset at a DVDD-POR.

Default Access Bit Description Bit Bit Name

7:2

1:0 DCDC3p

Name

PMU ENABLE

Offset: 18h

Bit Bit Name

7

6:4 DC_TEST

3 PMU_GATE

0

00

Table 69 PMU ENABLE Register

n/a

R/W

Technical

Base

2-wire serial

PMU Extension Enable Register

Enables 12h and 17h to write into extended registers and allows multiplexing supply voltages for monitoring via ADC10. This register is reset at a DVDD-POR.

Default

0

000

0

0:2 PMU_WR_ENABLE 000

Access Bit Description

n/a

R/W

R/W

DCDC 3V output voltage programming (BVDD)

00: 3.6V

01: 3.2V

10: 3.1V

11: 3.0V

Default

00h

Allows multiplexing internal and external supply voltages to one DC test node which can be further multiplexed to ADC10.

The accuracy is 5mV/LSB (see reg. 2Eh)

000: not used

001: AVDD

AG

010: DVDD

011: PVDD1

100: PVDD2

101: CVDD1

110: CVDD2

111: RVDD

Enables all settings made in registers 0x17-x at once. If this bit is set, changes are activated as soon as they are written to the related register.

0: no change

1: change at once

Enables extended registers 12h-x and 17h-x

000: not used

001: enables 17h-1 for PVDD1 settings enables 12h-1 for OutCntr settings

010: enables 17h-2 for PVDD2 settings enables 12h-2 for SPDIF settings

011: enables 17h-3 for CVDD1 settings enables 12h-3 for PWM_Cntr settings

100: enables 17h-4 for CVDD2 settings

101: not used

110: enables 17h-6 for hibernation settings

111: enables 17h-7 for BVDD settings

valid

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

65

-

84

AS3518 V23

Data Sheet, Confidential

Table 70 RTC_WakeUp Register

Name

RTC_WakeUp

Offset: 19h

Adr. Byte Name

7:0 WAKE_UP_BYTE0

(1 st

write to 0x19 is byte 0)

7:0

7:0

7:0

WAKE_UP_BYTE1

(2 nd

write to 0x19 is byte 1)

WAKE_UP_BYTE2

(3 rd

write to 0x19 is byte 2)

SRAM_128

(4 th

… 19 th

write to

0x19 programs the

128bit static SRAM)

Default n/a

Base

2-wire serial

RTC Wake-Up and SRAM Register

Sets and enables the RTC wake-up counter and programs the 128bit SRAM. 3 bytes need to be written in a sequence to set the counter. The 3-byte sequence allows to set the counter to every value between 1sec and 8388608sec (=97 days). The MSB of the

3 rd

byte enables the wake-up counter. Byte 4 …19 will program the static 128bit SRAM which is supplied by RVDD. This register is reset at a RVDD-POR.

Default Access Bit Description

00h

00h

00h

R/W

R/W

R/W

ams

00000000 R/W

0000 0001: 1sec

0000 0010: 2sec

0000 0100: 4sec

0000 1000: 8sec

0001 0000: 16sec

0010 0000: 32sec

0100 0000: 64sec

1000 0000: 128sec

0000 0001: 256sec

0000 0010: 512sec

0000 0100: 1 024sec

0000 1000: 2 048sec

0001 0000: 4 096sec

AG

000 0010: 131 072sec

000 0100: 262 144sec

000 1000: 524 288sec

001 0000: 1 048 576sec

010 0000: 2 097 152sec

100 0000: 4 194 304sec

0xxx xxxxxb = wake-up disabled

1xxx xxxxxb = wake-up enabled xxxx xxxxb = byte 4

: xxxx xxxxb = byte 19

still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

66

-

84

AS3518 V23

Data Sheet, Confidential

Table 71 USB_UTIL Register

Base

2-wire serial

Default

00h

Name

MISC

Offset: 1Ah

Miscellaneous Register

Comparator settings to read back VBUS voltage levels for supporting USB OTG and

USB Host protocols. I2S mode settings

This register is reset at a DVDD-POR.

Default Access Bit Description Bit Bit Name

4:7

3:2 VBUS_COMP_TH

1

0

I2S_DIRECT

PLL_MODE

0000

00

0

0 n/a

R/W

R/W

R/W

Sets the threshold for the VBUS comparator. The output can be read in register 25h.

00: 4.5V

01: 3.18V

10: 1.5V

11: 0.6V

Switches the PWGD pin to an input for an external master clock (e.g. coming form the CPU). This bit overwrites prior setting for the PWGD pin.

0: disabled

1: enabled

Preset of PLL bias for the following sampling frequencies

0: 16-48kS

1: 8-12kS

Table 72 DCDC15 Register

Name

DCDC15

Base

2-wire serial

AG

15V DCDC Step-up Control Register

Default

00h still valid

Offset: 1Bh

Bit Bit Name

7 DIM_UP_xDOWN

6:5 DIM_RATE

4:0 I_BACKLIGHT

Controls the back-light current and back-light dim rate.

This register is reset at a DVDD-POR.

00

Default

0

ams

00000

R/W

R/W

Technical

Starts dimming UP/DOWN or switches LED back-light ON/OFF when DIM_RATE = 00b

content

00: no dimming (immediate ON/OFF)

01: 150ms

10: 300ms

11: 500ms

Sets the current into pin ISINK in 1.20mA steps (internal current source to control LED backlight current). Setting

11111b enables the voltage feedback mode to supply e.g.

OLEDs with a constant voltage supply.

00000: DCDC15 switched off

00001: 1.2mA

00010: 2.4mA

..

11110: 36mA

11111: voltage feedback mode

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

67

-

84

AS3518 V23

Data Sheet, Confidential

Table 73 System Register

Base

2-wire serial

Default

C1h

Name

System

Offset: 20h

Bit Bit Name

7:4 Version <3:0>

3

2

1

0

HBT_WD_ON

JTEMP_OFF

I2C_WD_ON

PWR_HOLD

0

0

0

1

System Settings Register

Controls the powering down conditions of the AFE. The IC can also be emergency shut down by a high level for 5.4sec (or 10.9sec see reg. 24h) at the PWRUP input pin

This register is reset at a DVDD-POR.

Default

1100

R/W

R/W

R/W

R/W

Access Bit Description

R AFE number to identify the design version

1011: revision 4

Heartbeat (HBT) Watchdog

The watchdog counter will be reset by a rising edge at the HBT input pin which has to occur at least every 500ms. If the watchdog counter is not reset, the AFE will be powered down.

0: HBT watchdog is disabled

1: HBT watchdog is enabled

Junction temperature supervision (level can be set in register

21h)

0: temperature supervision enabled

1: temperature supervision disabled

2-wire serial interface watchdog

To reset the watchdog counter a 2-wire serial read operation has to be performed at least every 500ms. If the watchdog

AG still

1: is automatically set to on after power on valid

Table 74 Supervisor Register

Name

SUPERVISOR

Offset: 21h

Bit Bit Name

7:5 BVDD_SUP<2:0>

4:0 JTEMP_SUP<4:0>

Supervisor Register

Default

Base ams

Default

00h

Sets the threshold levels of battery supply and junction temperature supervision.

This register is reset at a DVDD-POR.

000

00000

Access

R/W

R/W

content

for an interrupt at low battery condition

V_BrownOut=2.74+BVDD_Sup*60mV

000: 2.74V

001: 2.80V

…

110: 3.10V

111: 3.16V

Sets the threshold for junction temperature emergency shutdown and junction temperature interrupt

Invoke shutdown at: JTemp_SD=140-JTEMP_Sup*5 ° C

Invoke interrupt at: JTemp_IRQ=120-JTEMP_Sup*5

°

C

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

68

-

84

AS3518 V23

Data Sheet, Confidential

Table 75 Charger Register

Name

CHARGER

Offset: 22h

Bit Bit Name

7 BAT_TEMP_OFF

6:4 CHG_I

3:1 CHG_V

0 CHG_OFF

Default

00h

Base

2-wire serial

000

000

0

Charger Control Register

Sets the charging current, end of charge voltage and battery temp. supervision.

This register is reset at a DVDD-POR.

Default

0

R/W

R/W

R/W

Access Bit Description

R/W

0: enables 15uA supply for external 100k NTC resistor

1: disables supply set maximum charging current

111: 460 mA

110: 420 mA

101: 350 mA

100: 280 mA

011: 210 mA

010: 140 mA

001: 70 mA

000: 55 mA

set maximum charger voltage in 50mV steps

111: 4.25 V

110: 4.2 V

..

001: 3.95 V

000: 3.9 V

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

69

-

84

AS3518 V23

Data Sheet, Confidential

Table 76 First Interrupt Register

Base

2-wire serial

Default

00h

Name

IRQ_ENRD_0

Offset: 23h

First Interrupt Register

Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.

6

5

4

3

2

1

0

Default Access Bit Description Bit Bit Name

7 CVDD2_EN_SD

CVDD2_UNDER

CVDD2_EN_IRQ

CVDD2_OVER

CVDD1_EN_SD

CVDD1_UNDER

CVDD1_EN_IRQ

CVDD1_OVER

PVDD2_EN_SD

PVDD2_UNDER

PVDD2_EN_IRQ

PVDD2_OVER

PVDD1_EN_SD

PVDD1_UNDER

PVDD1_EN_IRQ

0 x

0 x

0 x

0 x

0 x

0 x

0 x

0

W

R

W

R

W

R

W

Invokes shut-down of AFE when a –10% under-voltage spike at

CVDD2 occurs

0: disable

1: enable

This bit is set when a –5% under-voltage at CVDD1 occurs

Enables interrupt for over-voltage/under-voltage supervision of

CVDD2

0: disable

1: enable

This bit is set when a +8% over-voltage at CVDD1 occurs

valid

Invokes shut-down of AFE when a –10% under-voltage spike at

CVDD1 occurs

0: disable

1: enable

AG still

Enables interrupt for over-voltage/under-voltage supervision of

CVDD1

0: disable

1: enable

This bit is set when a +8% over-voltage at CVDD1 occurs R

W

R

W

R

Invokes shut-down of AFE when a –10% under-voltage spike at

ams

W

content

1: enable

This bit is set when a +5% over-voltage at PVDD2 occurs

Invokes shut-down of AFE when a –10% under-voltage spike at

PVDD1 occurs

0: disable

1: enable

This bit is set when a –5% under-voltage at PVDD1 occurs

W Enables interrupt for over-voltage/under-voltage supervision of

PVDD1

0: disable

1: enable

This bit is set when a +5% over-voltage at PVDD1 occurs PVDD1_OVER x R

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

70

-

84

AS3518 V23

Data Sheet, Confidential

Table 77 Second Interrupt Register

Name

IRQ_ENRD_1

Offset: 24h

Bit Bit Name

7 SD_TIME_5

4

3

2

6

5

0:1

PWRUP_IRQ

WAKEUP_IRQ

VOXM_IRQ

Default

00h

Base

2-wire serial

Second Interrupt Register

Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.

0

0 x

0

X

0

0 x

00

Access Bit Description Default

0 R/W n/a

W

R

W

R

Control bit which sets the emergency shut-down time from

5.4sec to 10.9sec. The shut-down of AS3518 is invoked by a high signal at the PWRUP input pin.

0: 5.4sec

1: 10.9sec

Enables interrupt which is invoked whenever a high signal at the PWRUP input pin occurs

0: disable

1: enable

This bit is set whenever a high level of min. BVDD/3 at the

PWRUP input pin occurs (PWRUP pin is commonly connected to the power-up button)

Enables interrupt which is invoked whenever a wake-up from

RTC wake-up counter occurs

0: disable

1: enable

AG

wake-up counter.

still valid

n/a

W

ams

n/a

Enables interrupt which is invoked by reaching a voltage threshold at the MIC input (voice activation)

0: disable

1: enable

This bit is set when a voltage threshold of 5mV

RMS

(unfiltered)

content

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

71

-

84

AS3518 V23

Data Sheet, Confidential

Table 78 Third Interrupt Register

Name

IRQ_ENRD_2

Offset: 25h

Bit Bit Name

7 BATTEMP_HIGH

(level)

6

5

4

3

2

CHG_EOC

CHG_CON

CHG_CHANGED

(status change)

USB_CON

USB_CHANGED

(status change)

Default

00h

Base

2-wire serial

x x x

0 x x

0 x

Third Interrupt Register

Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.

Default

0

R

R

R

W

W

R

Access Bit Description

W Battery over-temperature interrupt setting.

0: disable

1: enable interrupt if battery temperature exceeds 45°C

The interrupt must not be enabled if the charger block and battery temperature supervision is disabled

Battery over-temperature interrupt reading

0: battery temperature below 45°C

1: battery temperature was too high and the charger was turned off. The charger will be turned on again, when the temperature gets below 42°C

Battery end of charge interrupt reading

0: battery charging in progress

1: charging is complete, charging current is below 10% of nominal current, turn off charger

still

1: USB input connected, also valid if USB is connected during wakeup. The threshold can be set in the USB_UTIL register

(1Ah)

USB input status change interrupt setting

0: disable

AG

0: disable

1: enables an interrupt on a low to high or high to low change of CHGIN pin or on an EOC condition

Charger input status change interrupt reading

0: charger status not changed

1: charger status changed, check CHG_CON and CHG_EOC

0: no USB input connected

content

1: enables an interrupt on a low to high or high to low change of VBUS pin. The threshold can be set in the USB_UTIL register (1Ah)

USB input status change interrupt reading

0: USB input status not changed

1: USB input status changed, check USB_CON

valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

72

-

84

AS3518 V23

Data Sheet, Confidential

6

5

4

3

2

7

1

0

Name

RVDD_LOW

(level)

BVDD_LOW

(level)

IRQ_ENRD_3

Offset: 0x26

0 x

0 x

Table 79 Fourth Interrupt Register

W

R

W

R

Real time clock supply (RVDD) under-voltage interrupt setting

0: disable

1: enable

Real time clock supply interrupt reading

0: RTC supply o.k.

1: RTC supply (RVDD) was low, RTC not longer valid

The interrupt gets set in hibernation or during power-up even if the interrupt is not enabled thus allowing to recognise a change of the battery connected to BVDDR during hibernation or shutdown. For a valid reading, the interrupt has to be enabled first.

BVDD under-voltage supervisor interrupt setting

0: disable

1: enable

BVDD supervisor interrupt setting

0: BVDD is above brown out level

1: BVDD has reached brown out level

The threshold can be set in the SUPERVISOR register (21h)

valid

Base

2-wire serial

Default

0x00 still

register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.

Bit Bit Name

0

Fourth Interrupt Register

Default

W

AG

Access Bit Description

JTEMP_HIGH

(level)

HP_OVC

(level)

I2S_status x

0

0 x x n/a

W

R

R

I2S_changed

(status change)

0 x

W

Technical

0 n/a

Supervisor junction over-temperature interrupt setting

0: disable

1: enable

Supervisor junction over-temperature interrupt reading

0: chip temperature below threshold

1: chip temperature has reached the threshold

content

1: enable

The interrupt must not be enabled if the headphone block is disabled

Headphone over-current interrupt reading

0: no over-current detected

1: headphone over-current detected, headphone amplifier was shut down. The current thresholds are 150mA at HPR / HPL pin or 300mA at HPCM pin. The shut-down time can be set in

HPH_OUT_R register (0x02)

0: no LRCK on I2S interface detected

1: LRCK on I2S interface present

I2S input status change interrupt setting

0: disable

1: enable

I2S input status change interrupt reading

0: I2S input status not changed

1: I2S input status changed, check I2S_status

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

73

-

84

AS3518 V23

Data Sheet, Confidential

Name

IRQ_ENRD_3

Offset: 0x26

Bit Bit Name

1 MIC_CONNECT

(level)

0 HPH_CONNECT

(level)

Default

0x00

Base

2-wire serial

Fourth Interrupt Register

Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.

Default Access Bit Description

0 W x

0 x

R

W

R

Microphone connect detection interrupt setting

0: disable

1: enable

Microphone connect detection interrupt reading

0: no microphone connected to MIC input

1: microphone connected at MIC input.

This interrupt is only invoked when the microphone stage is powered down. The IRQ will be released after enabling the microphone stage.

Detecting a microphone during operation has to be done by measuring the supply current.

Headphone connect detection interrupt setting

0: disable

1: enable

Headphone connect detection interrupt reading

0: no headphone connected

AG still

Detecting a headphone during operation is not possible.

valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

74

-

84

AS3518 V23

Data Sheet, Confidential

Offset: 0x27

3

2

Table 80 Fifth Interupt Register

Name

IRQ_ENRD_4

Bit Bit Name

7:6 T_DEB<1:0>

5

4

1

0

XIRQ_AH

XIRQ_PP

REM_DET

(edge)

RTC_UPDATE

(edge)

ADC_EOC

(edge)

Default

0x00

Base

2-wire serial

Fifth Interrupt Register

Please be aware that writing to this register will enable/disable the corresponding interrupts, while with reading you get the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a DVDD-POR.

0

0

0

0 x

0 x

0 x

Access Bit Description Default

00 R/W

R/W

R/W n/a

W

R

W

0: no key press detected

1: Microphone supply current got increased, remote key press detected -> measure MICS supply current

RTC timer interrupt setting

ams

W

R

Sets the USB and Charger connect de-bounce time:

00: 512ms

01: 256ms

10: 128ms

11: 0ms

Sets the active output state of the XIRQ line:

0: IRQ is active low

1: IRQ is active high

Sets the XIRQ output buffer type:

0: IRQ output is open drain

1: IRQ output is push pull

Microphone remote key press detection interrupt setting

0: disable

1: enable

0: disable

1: enable

AG

1: RTC timer interrupt occurred. Selecting minute or second interrupt can be done via RTCT register (29h)

ADC end of conversion interrupt setting

0: disable

1: enable

ADC end of conversion interrupt reading

0: ADC conversion not finished

1: ADC conversion finished. Read out ADC_0 and ADC_1 register to get the result (2Eh & 2Fh)

valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

75

-

84

AS3518 V23

Data Sheet, Confidential

Table 81 RTC_Cntr Register

Base

2-wire serial

Default

03h

Name

RTC_Cntr

Offset: 28h

RTC Control Register

This register is reset at a DVDD-POR.

Default Access Bit Description Bit Bit Name

7:2

1 RTC_ON

0 OSC_ON

000000

1

1 n/a

R/W

RW

RTC counter clock control:

0: Disable clock for RTC counter

1: Enables clock for RTC counter

RTC oscillator control:

0: Disable RTC oscillator

1: Enable RTC oscillator

Table 82 RTC_Time Register

Name

RTC_Time

Offset: 29h

Bit Bit Name

7 IRQ_MIN

6:0 RTC_TBC<6:0>

RTC Timing Register

This register is reset at a RVDD-POR.

Default

0

1000000 R/W

Table 83 RTC_0 to RTC_3 Register

Name

RTC_0 to RTC_3

Offset: 2Ah to 2Dh

Base

2-wire serial

Access Bit Description

R/W

ams

Base

Default

40h

0: generates an interrupt every second

1: generates an interrupt every minute

AG still

Trimming register for RTC, 128 steps @ 7.6ppm

000000: 1 (7.6ppm)

000001: 2 (15.2ppm)

…

100000: 64 (488ppm)

…

111110: 126 (960.8ppm)

111111: 127 (968.4ppm)

2-wire serial

RTC Time-base Seconds Register

This register is reset at a RVDD-POR.

00 00 00 00h valid

Adr. Byte Name

2Ah RTC_0

2Bh RTC_1

2Ch RTC_2

2Dh RTC_3

Default

00h

00h

00h

00h

Access Bit Description

R/W

R/W

R/W

R/W

QRTC<7:0>; RTC seconds bits 0 to 7

QRTC<15:8>; RTC seconds bits 8 to 15

QRTC<23:9>; RTC seconds bits 9 to 23

QRTC<31:24>; RTC seconds bits 24 to 31

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

76

-

84

AS3518 V23

Data Sheet, Confidential

Table 84 ADC10_0 Register

Base

2-wire serial

Default

0000 00xx

Name

ADC10_0

Offset: 2Eh

First 10-bit ADC Register

Writing to this register will start the measurement of the selected source.

This register is reset at a DVDD-POR, exception are bit 8 and 9.

Bit Bit Name

7:4 ADC10_MUX

3:2

1:0 ADC10<9:8>

Name

Default Access Bit Description

00000000 R/W

00 xx

Table 85 ADC10_1 Register

n/a

R/W

Base

Selects ADC input source

0000: CHGOUT

0001: BVDDR

0010: defined by DC_TEST in register 0x18

0011: CHGIN

0100: reserved

0101: BatTemp

0110: MICS

0111: reserved

1000: VBE_1uA

1001: VBE_2uA

1010: I_MICS

1011: reserved

1100: VB1V

1101: VBUS

1110: reserved

AG

Default still valid

Name xxxx xxxx ADC10_1

Offset: 2Fh

Bit Bit Name

7:0 ADC10<7:0>

Second 10-bit ADC Register

Default

xxxx xxxx R/W

Table 86 UID_0 to UID_7 Register

2-wire serial

Access

Base

Bit Description content

2-wire serial

Unique ID Register n/a UID_0 to UID_7

Offset: 38h to 3Fh

This register is read only and is not reset.

Adr. Byte Name Default

38h UID_0

39h UID_1

3Ah UID_2

3Bh UID_3

3Ch UID_4

3Dh UID_5

3Eh UID_6

3Fh UID_7 n/a n/a n/a n/a n/a n/a n/a n/a

R

R

R

R

R

R

R

R

Access Bit Description

Unique ID byte 0

Unique ID byte 1

Unique ID byte 2

Unique ID byte 3

Unique ID byte 4

Unique ID byte 5

Unique ID byte 6

Unique ID byte 7

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

77

-

84

AS3518 V23

Data Sheet, Confidential

9 Application Information

Figure 31 Typical Application Schematic

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

78

-

84

AS3518 V23

Data Sheet, Confidential

10 Package Drawings and Marking

10.1 CTBGA64

Figure 32 CTBGA64 Marking

Table 87 Package Code AYWWZZZ

A Y WW ZZZ

A … for PB free Year Working week assembly/packaging Free choice

Figure 33 CTBGA64 7x7mm 0.8mm pitch

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

79

-

84

AS3518 V23

Data Sheet, Confidential

Figure 34 Reel Specification

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

80

-

84

AS3518 V23

Data Sheet, Confidential

Figure 35 Tape Specification

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

81

-

84

AS3518 V23

Data Sheet, Confidential

10.2 Wafer & Die

Figure 36 Die Orientation

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

82

-

84

AS3518 V23

Data Sheet, Confidential

11 Ordering Information

Table 88 Ordering Information

Device ID

AS3518-ECTP

Version

V23

Temperature Range

-20 to +85 °C

AS3518-ECTS V23 -20 to +85 °C

Package Type

CTBGA64; 7x7mm package size,

0.8mm ball pitch

CTBGA64; 7x7mm package size,

0.8mm ball pitch

Delivery Form

Tape & Reel

(Dry Pack)

Tray

(Dry Pack)

AG still valid

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

83

-

84

AS3518 V23

Data Sheet, Confidential

Copyright

Copyright © 1997-2012, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-

Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.

All products and companies mentioned are trademarks or registered trademarks of their respective companies.

Disclaimer

Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.

This product is intended for use in normal commercial applications. Applications requiring extended temperature

valid

austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.

The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,

AG still

Contact Information

Headquarters

austriamicrosystems AG

A-8141 Schloss Premstätten, Austria

T. +43 (0) 3136 500 0

F. +43 (0) 3136 5692

Technical

© austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.

www.austriamicrosystems.com

Revision 1.11

84

-

84