NXP TFA9872 High-Efficiency Class-D Audio Amplifier Data Sheet
Reklama
Reklama
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-
Microphone
Rev. 1 — 12 April 2017 Product short data sheet
COMPANY PUBLIC
1 General description
The TFA9872 is a 9.5 V boosted class-D audio amplifier featuring Speaker-as-
Microphone (SaM) and Receiver-as-Microphone (RaM) modes. It can deliver up to
10.0 W peak output power into an 8 Ω speaker and up to 11.8 W peak output power into a 6 Ω speaker, at a supply voltage of 4.0 V. The internal adaptive DC-to-DC converter raises the supply voltage to 9.5 V, providing ample headroom for major improvements in sound quality.
Internal adaptive DC-to-DC conversion boosts the supply rail to provide additional headroom and power output. The supply voltage is only raised when necessary, maximizing the output power of the class-D audio amplifier while limiting quiescent power consumption.
The device can be configured to drive either a hands-free speaker (4 Ω to 8 Ω) for audio playback, or a receiver speaker (32 Ω) for handset playback, allowing it to be embedded in platforms that support either or both options. The maximum output power, gain, and noise levels are lower in the Handset Call use case than in the Hands-free Call use case.
The SaM feature allows the speaker to be used as an additional microphone when not configured for audio playback. This function performs best in high sound pressure environments (like concert recording or wind noise calls) and is targeted at such use cases.
The TFA9872 also incorporates battery protection. By limiting the supply current when the battery voltage is low, the device is prevented from switching off unexpectedly due to excessive load currents (excessive load currents can lead to a system undervoltage).
Because it has a digital input interface that is insensitive to clock jitter, the TFA9872 features low RF susceptibility. The second order closed loop architecture used in a class-
D audio amplifier provides excellent audio performance and high supply voltage ripple rejection. The audio input interface is I S and the control settings are communicated via an I
2
C-bus interface.
The TFA9872 is available in a 42-bump WLCSP (Wafer Level Chip-Size Package) with a
400 mm pitch.
NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
2 Features and benefits
• High output power: 5.1 W (average) into 8 W at 4.0 V supply voltage (THD = 1 %)
• Supports handset (16 Ω or 32 Ω) and hands-free (4 Ω or 8 Ω) speaker configurations
• High efficiency, low power dissipation and low-noise speaker driver
• Adaptive DC-to-DC converter increases the supply voltage smoothly when switching between fixed boost and adaptive boost modes, preventing large battery supply spikes and limiting quiescent power consumption.
• Wide supply voltage range (fully operational from 2.7 V to 5.5 V)
• Very low noise output <20×mV (with null data input at F s
= 48 kHz)
= 380 mW, average music power)
•
• Low battery current consumption <130 mA (P o
I
2
C-bus control interface (400 kHz)
• Speaker current and voltage monitoring (via the I
2
S-bus) for Acoustic Echo
•
•
Cancellation (AEC) at the host
• 16 kHz /44.1 kHz/48 kHz sample frequencies supported
Ultrasonic support (limited) via TDM/I
Configurable full-duplex 4-wire TDM/I
2
2
S running at 96 kHz/192 kHz
S input interface supporting up to 16 slots
• Low-latency input path supporting side tone mixing via dedicated PDM input interface
• Speaker-as-Microphone feedback path on dedicated PDM output interface or TDM interface
• Programmable interrupt control via a dedicated interrupt pin
• Low RF susceptibility
• Thermal foldback and overtemperature protection
• 15 kV system-level ESD protection without external components on amplifier output
3 Applications
• Mobile phones & Tablets
• Portable Navigation Devices (PND)
• Notebooks/Netbooks
• Internet of Things applications embedding high-quality audio
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
V
BAT battery supply voltage
Conditions on pin VBAT
V
BAT
must not be lower than V
DDD
or V
DDE application
in
Min
2.7
I
I
V
V
DDD
DD(IO)
BAT
DDD
P o(AVG)
SaM S/N digital supply voltage on pin VDDD input/output supply voltage on pin VDDE battery supply current Active state on pin VBAT; Operating mode with load; R
L
= 6 Ω; DC-to-DC converter in Adaptive Boost mode; P
V
BAT o
= 380 mW (average music power);
= 4.0 V; V
DDP
= 8.5 V
Idle state on pin VBAT; Operating mode with load; R
L
= 6 Ω and no output signal (idle); DC-to-DC converter in Adaptive Boost mode; V
4.0 V; V
DDP
= 8.5 V
BAT
=
Power-down state on pin VBAT; DC-to-DC converter in powerdown mode; T j
= 25 °C; no clock digital supply current average output power speaker-as-microphone signal-to-noise ratio
Active state on pin VDDD; Operating mode with load;
R
L
=6 Ω; DC-to-DC converter in Adaptive
Boost mode, P power), V
BAT o
= 380 mW (average music
= 4.0 V; V
DDP
= 8.5 V
Idle state on pin VDDD; Operating mode with load;
R
L
=6 Ω and no output signal (idle); DC-to-
DC converter in Adaptive Boost mode; V
BAT
= 4.0 V; V
DDP
= 8.5 V
Power down state on pin VDDD; DC-to-DC converter in powerdown mode; T j
= 25 °C; no clock
THD+N = 1 %; L
L
V
DDD
= 1.8 V
= 44 µH; V
BAT
= 4.0 V;
V
BST
= 9.5 V; R
L
= 8 Ω
V
BST
= 8.5 V; R
L
= 8 Ω
V
BST
= 9.5 V; R
L
= 6 Ω
V
BST
= 8.5 V; R
L
= 6 Ω
A-weighted; PDM output; full scale input;
PGA gain setting GAIN_10
-
-
-
-
-
-
1.65
1.65
-
-
-
-
-
-
Typ
1.8
1.8
122
1.8
1
6.8
4.1
10
5.1
4.0
5.9
5.1
78.6
-
-
-
-
-
-
-
-
-
-
Max
5.5
-
1.95
1.95
Unit
V
V
V mA mA
µA mA mA
µA
W
W
W
W dB
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
5 Ordering information
Table 2. Ordering information
Type number Package
Name Description
TFA9872AUK/N1 WLCSP42 wafer level chip-scale package; 42 bumps; 3.13 × 2.46 × 0.50 mm
TFA9872CUK/N1 WLCSP42 wafer level chip-scale package; 42 bumps; 3.13 × 2.46 × 0.525 mm
Version
SOT1459-2
SOT1459-2
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
6 Block diagram
ADS1 ADS2 VBAT VDDE INB
SCL
SDA
RST
INT
I 2 C
INTERFACE
INTERRUPT
HANDLER
MTP REGISTERS
MAX ChL OR ChR
INTELLIGENT
DC-DC
CONVERTER
DATAI
BCK
FS
PDMDAT
PDMCLK
DATAO
INTERFACE
PDM
INTERFACE
I
I 2
2
S/TDM
INPUT
S/TDM
OUTPUT
INTERFACE
GAIN low latency speaker as mic
1ch INT
2x DEC
I/V SENSE
PROCESSING
AND
DATA
SELECTOR
GAIN AND
SIGN
SIGN
+
HPF
GAIN
CLIPPER
PWM
DEC
CARDEC
(2ch) voltage sensing
FRACTIONAL
DELAY
ALIGN (I/V)
A
D
C
TEMP SENSE
Vbat SENSE
Vddp SENSE
FS
BCK
PLL
OSC1M
MANAGER
CGU
CLASS-D
SPK AMP current sensing
A
D
C
PGA speaker as mic.
PROTECTIONS:
OTP
OVP
UVP
OCP
TEST1 TEST2 TRSTN
Figure 1. Block diagram
VBST
GNDB
VDDP
OUTA
OUTB
GNDP
AUXSAMP
AUXSAMN
VDDD
GNDD aaa-021841
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
7 Pinning information
7.1 Pinning
1 2 3 4
G
F
E
D
C
B
A bump A1 index area
Bottom view
Figure 2. Bump configuration
5 6 aaa-021938 bump A1 index area
A
D
E
B
C
F
G
1 2 3 4
Transparent top view
5 6 aaa-021939
E
F
G
C
D
A
B
1
FS
BCK
PDMCLK
SCL
SDA
VDDD
VDDE
2
DATAI
INT
PDMDAT
AUXSAMP
AUXSAMN
ADS1
ADS2
3
DATAO
RST
TRSTN
TEST2
TEST1
GNDD
VBAT
Figure 3. Bump mapping
Transparent top view
GNDD
GNDB
GNDB
GNDB
4
GNDD
GNDP
GNDD
OUTA
INB
INB
INB
5
OUTB
GNDP
OUTA
6
VDDP
VDDP
VDDP
VBST
VBST
VBST
VBST aaa-021936
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
7.2 Pin description
Table 3. Pinning
Symbol Pin Type Description
FS A1 I digital audio frame sync for TDM/I
2
S interface
DATAI
DATAO
A2
A3
I
O digital audio data input for TDM/I 2 S interface digital audio data output for TDM/I 2 S interface
I
I/O
I/O
P
O
P
O
I
I
P
I
P
P
I
P
I
P
P
O
O
I
P
P
O
P
I
O
I/O
I/O
P
P
GNDD
OUTB
VDDP
BCK
INT
RST
GNDP
GNDP
VDDP
PDMCLK
PDMDAT
TRSTN
GNDD
OUTA
VDDP
SCL D1
AUXSAMP D2
TEST2
GNDD
OUTA
D3
D4
D5
C2
C3
C4
C5
C6
B3
B4
B5
B6
C1
A4
A5
A6
B1
B2
VBST
SDA
D6
E1
AUXSAMN E2
TEST1 E3
GNDB E4
INB
VBST
VDDD
ADS1
GNDD
GNDB F4
E5
E6
F1
F2
F3 digital ground inverting output power supply voltage digital audio bit clock input for TDM/I 2 S interface digital interrupt output digital reset input power ground power ground power supply voltage digital audio clock for PDM interface digital audio data for PDM interface test reset signal (for JTAG); connect to PCB ground digital ground non-inverting output power supply voltage digital I
2
C-bus clock input auxiliary speaker-as-microphone non-inverting input test signal input 2; for test purposes only, connect to PCB ground digital ground non-inverting output boosted supply voltage output digital I
2
C-bus data input auxiliary speaker-as-microphone inverting input test signal input 1; for test purposes only, connect to PCB ground boosted ground
DC-to-DC boost converter input boosted supply voltage output digital supply voltage digital address select input 1 digital ground boosted ground
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NXP Semiconductors
Symbol
INB
VBST
VDDE
ADS2
VBAT
GNDB
INB
VBST
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
G1
G2
G3
G4
G5
G6
Pin Type Description
F5
F6
P
O
DC-to-DC boost converter input boosted supply voltage output
P
P
I
P
P
O digital IO supply voltage digital address select input 2 battery supply voltage boosted ground
DC-to-DC boost converter input boosted supply voltage output
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
8 Functional description
The TFA9872 is a highly efficient Bridge Tied Load (BTL) class-D audio amplifier embedding Speaker-as-Microphone (SaM) support, as depicted in the block diagram of
Figure 1 .
The TFA9872 contains a TDM/I
(I
2
2
S input/output interface for communicating with the audio host. The maximum number of slots is 16 (at f
S mode). The interface is compliant with all I s
2
= 48 kHz) and the minimum number is 2
S interface configurations and supports a wide range of TDM interface configurations. It also features an optional ultrasonic path to the speaker.
The TFA9872 features a slave-configurable IN or OUT PDM interface. This audio interface can be connected to the audio host to provide a low-latency path (for side tone mixing) to the speaker. The 1-bit PDM stream is decimated and applied to the
TDM interface. The PDM stream can, optionally, be attenuated or amplified by the gain module. Soft mute control prevents pop and click noise occurring when this signal path is switched on or off. The PDM output also provides a SaM stream back to the host.
At low battery voltage levels, the gain is automatically reduced to limit battery current
(when battery safeguard is enabled).
The digital audio stream is converted into two PWM signals which are then injected into the class-D audio amplifier. The 3-level PWM scheme supports filterless speaker drive.
An adaptive DC-to-DC converter boosts the battery supply voltage when the audio stream crosses two programmable voltage thresholds. It switches automatically to
Follower mode (V battery voltage.
BST
= V
BAT
; no boost) when the audio output voltage is lower than the
The SaM feature is available in both PDM and I
2
S modes. This function can be used to turn the speaker into a dynamic microphone, providing an output audio stream on the digital interfaces. Due to the nature of the speaker membrane, the microphone equivalent characteristics perform best in high Sound Pressure Level (SPL) environments.
Consequently, this feature is targeted at specific use cases such as concert recording or calls affected by wind noise. It is not intended to replace a primary/standard microphone but rather to complement it in such use cases by providing a signal that is less sensitive to saturation.
For SaM, a dedicated PGA is used to amplify the weak signal coming from the main speaker or receiver speaker. The result is a microphone that can handle high SPL environments.
SaM can be enabled on the main speaker connected to OUTA/OUTB, when the amplifier is off. Alternatively, SaM can be enabled on auxiliary inputs AUXSAMP/AUXSAMN, with the receiver speaker connected as input.
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
9 Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V x voltage on pin x
Conditions Min on pin VBAT -0.3
on pins VBST, VDDP, AUXSAMP, AUXSAMN -0.3
on pin INB, OUTA, OUTB -0.3
on pins VDDD, VDDE, TEST1, TEST2
T j
T stg
T amb
V
ESD junction temperature storage temperature ambient temperature electrostatic discharge voltage according to Human Body Model (HBM) according to Charge Device Model (CDM)
-0.3
-40
-55
-40
-2
-500
Max
+6
+12
+12
+2.5
+150
+150
+85
+2
+500
V
°C
°C
°C kV
V
Unit
V
V
V
[1] Using an NXP demo board with a 1 mm wire/PCB track length on pin INB, AC pulses up to 18 V and -9 V can be observed without causing any damage as these spikes only partly penetrate the device (which is protected by internal clamp circuits).
10 Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter
R th(j-a) thermal resistance from junction to ambient
Conditions
4-layer application board
Typ
36
Unit
K/W
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
11 Characteristics
11.1 DC Characteristics
Table 6. DC characteristics
All parameters guaranteed for V
Ω
; L
L
= 44 μH
; f i
= 1 kHz; f s
BAT
= 3.6 V; V
DDD
= 48 kHz; T amb
= 1.8 V; V
DDP
= V
BST
= 9.0 V; Adaptive Boost mode; L
BST
= 1 μH
; R
L
= 8
= 25 °C; default settings, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
2.7
5.5
V
I
V
BAT
BAT battery supply voltage battery supply current on pin V
V
BAT
BAT
must not be lower than V
DDD
or V
DDE
in application
Active state on pin V
R
L mode; P
BAT
; Operating mode with load
= 6 Ω; DC-to-DC in Adaptive Boost o
= 380 mW, (average music power), V
BAT
= 4.0 V, V
DDP
= 8.5 V
Idle state on pin V
BAT
; Operating mode with load
R
L
= 6 Ω and no output signal (idle);
DC-to-DC converter in Adaptive Boost mode; V
BAT
= 4.0 V, V
DDP
= 8.5 V
Power-down state on pin VBAT; DC-to-DC in power down mode; T j
= 25 °C, no clock.
on pin VDDP on pin VDDE
I
V
DDP
V
DD(IO)
V
DDD
DDD power supply voltage input/output supply voltage digital supply voltage digital supply current on pin VDDD
Active state on pin VDDD; Operating mode with load R
L
= 6 Ω; DC-to-DC in Adaptive
Boost mode; P o
= 380 mW, (average music power); V
8.5 V
BAT
= 4.0 V;V
DDP
=
Idle state on pin V
R
L
DDD
; Operating mode with load
= 6 Ω and no output signal (idle);
DC-to-DC converter in Adaptive Boost mode; V
BAT
= 4.0 V, V
DDP
= 8.5 V
Power-down state on pin VDDD; DC-to-DC in power down mode; T j
= 25 °C, no clock.
Pins FS, BCK, DATAI, ADS1, ADS2, SCL, SDA, PDMCLK, PDMDAT, RST, TRSTN
-
-
-
-
-
2.7
1.65
-
1.65
122 -
1.8
-
1 -
10
1.8
1.95
1.8
1.95
6.8
-
4.1
-
10 mA mA
μA
V
V
V mA mA
μA
V
IH
V
IL
C i
HIGH-level input voltage
LOW-level input voltage input capacitance
-
-
0.7V
DDD
-
-
-
3.6
0.3V
DDD
3
V
V pF
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
Symbol Parameter Conditions
I
LI input leakage current 1.8 V on input pin
Pins DATAO, INT, PDMDAT, push-pull output stages
V
OH
HIGH-level output voltage I
OH
= 4 mA
-
Min
-
Typ Max
0.1
V
DDD
0.4
-
400 V
OL
LOW-level output voltage I
OL
= 4 mA
Pins SDA, open drain outputs, external 10 kΩ resistor to V
DDD
V
OH
HIGH-level output voltage I
OH
= 4 mA
-
V
DDD
0.4
-
400 V
OL
LOW-level output voltage
Pins OUTA, OUTB
R
DSon drain-source on-state resistance
Protection
T
V act(th_prot) uvp(VBAT) thermal protection activation temperature undervoltage protection voltage on pin VBAT
I
O(ocp) overcurrent protection output current
DC-to-DC converter
V bst boost voltage
I
OL
= 4 mA
PMOS + NMOS transistors -
-
130
2.3
2
DCVOS = 111; Boost mode (after trimming)
9.32
[1] L
BST
= boost converter inductance; R
L
= load resistance; L
L
= load inductance (speaker).
[2] This parameter is not tested during production; the value is guaranteed by design and checked during product validation.
-
-
-
-
510 -
-
150
2.5
9.5
9.68
V
A
Unit
μA
V mV
V mV mΩ
°C
V
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
11.2 AC characteristics
Table 7. AC characteristics
All parameters guaranteed for V
8 Ω
; L
L
= 44 μH
BAT
= 3.6 V; V
DDD
= 1.8 V; V
DDP
= V
BST
= 9.0 V; Adaptive Boost mode; L
BST
= 1 μH
L
=
; f i
= 1 kHz; f s
= 48 kHz; T amb
= 25 °C; default settings, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Amplifier output power
P o(AV) average output power Hands-free speaker, THD+N = 1 %
R
L
= 8 Ω; f s
9.5 V, V
BAT
= 48 kHz, V
= 4.0 V
BST
=
R
L
= 6 Ω; f s
9.5 V, V
BAT
= 48 kHz, V
= 4.0 V
BST
=
R
L
= 4 Ω; f s
= 48 kHz, V
BST
= 9.5
V, V
BAT
= 4.0 V
R
L
= 8 Ω; f s
8.5 V, V
BAT
= 48 kHz, V
= 3.6 V
BST
=
R
L
= 6 Ω; f s
8.5 V, V
BAT
= 48 kHz, V
= 3.6 V
BST
=
R
L
= 4 Ω; f s
8.5 V, V
BAT
= 48 kHz, V
= 3.6 V
BST
=
Receiver speaker.THD+N = 1 %;
V
BST
= 9.5 V,
R
L
= 32 Ω; Voice mode
R
L
= 32 Ω; Audio mode -
-
-
-
-
-
3.6
3.6
5.1
5.9
6.0
4.0
5.1
5.2
0.2
1.2
-
-
-
-
-
-
-
W
W
W
W
W
W
W
W
Amplifier output pins (OUTA and OUTB)
|V
O(offset)
| output offset voltage absolute value after trimming; V
DDP
3.4 V to 9.5 V, V
BAT
= 3.4 V to 5 V
= 1.0
mV
Amplifier performances
η po output power efficiency
THD+N
V n(o) total harmonic distortion-plus-noise output noise voltage on pin VBAT; Operating mode with load; R
L
= 6 Ω; DC-to-DC in Adaptive
Boost mode, P o music power), V
8.5 V
= 380 mW, (average
BAT
= 4.0 V, V
DDP
= on pin VBAT; input: 100 Hz sine wave, R
Adaptive Boost mode, V
BAT
V
DDP
L
= 8 Ω; DC-to-DC in
= 8.5 V,P o
= 700 mW
= 4.0 V, on pin VBAT; input: 100 Hz sine wave, R
Adaptive Boost mode, V
BAT
V
DDP
L
= 8 Ω; DC-to-DC in
= 8.5 V,P o
= 4 W
= 4.0 V,
V
DDP
> 9 V, P o
= 2.0 W, R
L
= 8 Ω
V
DDP
> 9 V, P o
= 2.0 W, R
L
= 4 Ω
A-weighted; DATAI = 0 V; Low Noise mode (ISTLA = 1); f s
= 8 kHz
-
-
-
-
-
-
80
90
84 -
-
%
%
%
-
0.04
0.09
%
0.09
%
19 24 μV
TFA9872_SDS
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
Symbol Parameter
S/N signal-to-noise ratio
Conditions
A-weighted; DATAI = 0 V; Low Noise mode (ISTLA = 1); f s
= 16 kHz
A-weighted, V
BAT
= 3.4 V to 5 V, maximum signal at THD = 1 %
PSRR
∆G/Δf power supply rejection ratio gain variation with frequency from V
(V
DDP
4.0 V
BAT
= V wave, V
; booster in follower mode
BAT ripple
); f ripple
= 217 Hz square
= 50 mV(p-p), V
BAT
= from V
BAT
(V
DDP
= V
; booster in follower mode
BAT
); f ripple
= 20 Hz to 1 kHz sine wave, V ripple
V
BAT
= 200 mV (RMS),
= 3.4 V to 5.0 V; Low Power and Low Noise modes on from V
BAT
; f sine wave, V ripple
= 20 Hz to 1 kHz ripple
= 200 mV (RMS),
V
BAT
= 3.4 V to 5.0 V; DC-DC in follower OR booster; Low Power and
Low Noise modes off from V
(V
DDP
BAT
= V
; booster in follower mode
BAT
(RMS), V
BAT
); f ripple
= 1 kHz to 20 kHz sine wave, V ripple
= 200 mV
= 3.4 V to 5.0 V
BW = 20 Hz to 15 kHz, V
BAT to 5 V
= 3.4 V
V
POP
R
L
C
L f sw pop noise voltage load resistance load capacitance switching frequency at mode transition and gain change.
G v voltage gain directly coupled to the I 2 S input frequency
I 2 S/TDM to V
O
; INPLEV = 0 (0 dB) t t t
Amplifier power-up, power-down and propagation delays d(on)PLL d(on)amp t d(off) t d(alarm)
PLL turn-on delay time amplifier turn-on delay time turn-off delay time alarm delay time
PLL locked on BCK, f f s
= 48 kHz s
= 48 kHz
PD propagation delay f s
= 16 kHz (I
2
S/TDM) f s
= 48 kHz (I
2
S/TDM) f s
= 96/192 kHz (I
2
S/TDM) f s
= 48 kHz (PDM)
Booster Inductance
L bst boost inductance
Current-sensing performance
L
L(spk) speaker load inductance
-
Min Typ Max Unit
55 60 μV
100 -
-
-
-
-
-
-
-
-
-
-
-
60
-0.1
-
6
0.7
30 -
-
80
80
75
70
-
4
256 -
-
8
2
1
32
200 -
-
-
-
1750 -
600 -
320 -
70 -
1.0
-
-
-
-
-
-
0.7
2
32 mV
Ω
200 pF
384 kHz
21
2.2
dB dB dB dB dB dB dB
μH
μH
μs
μs
μs
μs ms ms
μs ms
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
Symbol Parameter Conditions
S/N
ΔI sense signal-to-noise ratio current sense mismatch
I
O
= 1.1A (peak); A-weighted over frequency; 20 Hz to 4 kHz
THD+N over temperature; f i
-20 °C to 85 °C
= 1 kHz; T j
= over V
DDP
9.5 V
; f i
= 1 kHz, V
DDP
= 2.7 V to total harmonic distortion-plus-noise f i
= 20 Hz to 20 kHz; V i
= -6 dBFS;
TDMSPKG = 0110
B bandwidth
Speaker-as-microphone performance; pins OUTA, OUTB
GPGA PGA gain PGAGAIN = 30 dB (± 1.5 dB accuracy)
V i(max)
V n(i)(eq)
S/N
THD+N maximum input voltage equivalent input noise voltage signal-to-noise ratio total harmonic distortion-plus-noise
PGAGAIN = 24 dB (± 1.5 dB accuracy)
PGAGAIN = 18 dB (± 1.5 dB accuracy)
PGAGAIN = 16 dB (± 1.5 dB accuracy)
PGAGAIN = 18 dB; RMS value
PGAGAIN = 30 dB; RMS value
A-weighted, PGAGAIN: 30 dB; TDM
Output; RMS value
A-weighted, PGAGAIN: 16 dB; TDM
Output; RMS value
A-weighted, PGAGAIN: 30 dB; PDM
Output; RMS value
A-weighted, PGAGAIN: 16 dB; PDM
Output; RMS value
A-weighted; PDM output; full scale input; PGAGAIN: 18 dB;
A-weighted; PPDM Output
Full scale input, PGA gain setting
GAIN_00
A-weighted; PTDM output; full scale input; PGAGAIN: 18 dB;
TDM output; full scale input;
PGAGAIN: 30 dB f i
= 1 kHz, V i
= 0.5ΩmV (RMS), maximum PGA gain setting (30 dB), on pin OUTA/OUTB f i
= 1 kHz, V i
= 0. 5 mV (RMS), maximum PGA gain setting (30 dB), on pin AUXSAMN/AUXSAMP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min Typ Max Unit
-
62
-
65 -
3 dB
%
0.02
-
-
2
1
27.6
-
22.2
-
16.8
-
14.9
-
10.5
-
3.0
-
1.05
-
2.35
-
1.20
-
1.35
-
78.6
-
70.3
-
76.9
-
69.6
-
0.3
0.45
-
-
-
-
%
%
0.75
%
20 kHz dB dB dB dB mV mV
μV
μV
μV
μV dB dB dB dB
%
%
TFA9872_SDS
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
Symbol Parameter
PSRR
V
O(offset) power supply rejection ratio output offset voltage
Conditions square wave on VDDD, f ripple
Hz, V ripple
PGA gain setting ( 30 dB)
= 217
= 50 mV (p-p), maximum sine wave on VDDD, f ripple
= 20 Hz to
1 kHz, V ripple
= 100 mV (RMS), maximum PGA gain setting (30 dB) sine wave on VDDD, f ripple
= 1 kHz to
20 kHz, V ripple
= 100 mV (RMS), maximum PGA gain setting (30 dB)
% of Full Scale; PDM output only
(offset is removed on TDM output)
-
-
-
Min Typ Max Unit
-10 -
70
70
60 -
-
-
10 dB dB dB
%
[1] L
BST
= boost converter inductance; R
L
= load resistance; L
L
= load inductance (speaker).
[2] This parameter is not tested during production; the value is guaranteed by design and checked during product validation.
[3] Overload level at input; output is specified at 0 dBFS for TDM/PDM output max, or output limited at THD+N =1 % if reached before 0 dBFS; THD = 1 %.
[4] Overload level at input; output is specified at 0 dBFS for TDM/PDM output max, or output limited at THD+N = 1 % if reached before 0 dBFS; THD = 1 %.
[5] When using PDM output for Speaker-as-Microphone, PDM stream decimation shall be done in codec or AP running SAM software and it must include a
DC offset remover.
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
11.3 I
2
S timing characteristics
Table 8. I 2
S bus interface characteristics; see Figure 4
All parameters are guaranteed for V
= 8 Ω
; L
L
= 44 μH
; f i
= 1 kHz; f
BAT
= 3.6 V; V s
= 48 kHz; T amb
DDD
= 1.8 V; V
DDP
= V
BST
= 9.0 V, Adaptive Boost mode; L
= 25 °C; default settings, unless otherwise specified.
BST
= 1 μH
;R
L
Symbol Parameter Conditions Min Typ Max Unit f s sampling frequency on pin WS, audio mode
16 48 kHz on pin WS, ultrasonic mode 96 192 kHz f clk clock frequency on pin BCK, audio mode on pin BCK, ultrasonic mode
-
32f s
-
384f s
96f s kHz
MHz t su set-up time WS edge to BCK HIGH
10 ns
DATA edge to BCK HIGH 10 ns t h hold time BCK HIGH to WS edge
10 ns
BCK HIGH to DATA edge 10 ns
[1] L
BST
[2] The I
= boost converter inductance; R
L
= load resistance; L
L
= load inductance.
S bit clock input (BCK) is used as a clock input for the amplifier and the DC-to-DC converter. Note that both the BCK and WS signals must be present for the clock to operate correctly.
[3] This parameter is not tested during production; the value is guaranteed by design and checked during product validation.
BCK t h t su
FS
DATA
Figure 4. I 2 S timing
010aaa750
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
11.4 I
2
C timing characteristics
Table 9. I 2 C-bus interface characteristics; see
All parameters are guaranteed for V
= 8 Ω
; L
L
= 44 μH
; f i
= 1 kHz; f
BAT
= 3.6 V; V s
= 48 kHz; T amb
DDD
= 1.8 V; V
DDP
= V
BST
= 9.0 V, Adaptive Boost mode; L
= 25 °C; default settings, unless otherwise specified.
BST
= 1 μH
;R
L
Symbol Parameter Conditions Min Typ Max Unit f
SCL t
LOW t
HIGH t r t f t
HD;STA t
SU;STA t
SU;STO t
BUF
SCL clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock rise time fall time hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition bus free time between a STOP and START condition
SDA and SCL signals
SDA and SCL signals
-
1.3
0.6
20 + 0.1 C b
20 + 0.1 C b
0.6
0.6
0.6
1.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400 ns
μs
μs
μs
μs kHz
μs
μs ns t
SU;DAT t
HD;DAT t
SP
C b data set-up time data hold time pulse width of spikes that must be suppressed by the input filter capacitive load for each bus line
100
0
0
-
-
-
-
-
-
50
400 ns
μs ns pF
[1] L
[2] C
BST b
= boost converter inductance; R
L
= load resistance; L
[3] After this period, the first clock pulse is generated.
[4] To be suppressed by the input filter.
L
= load inductance.
is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
SDA t
BUF t
LOW t r t f
SCL
P S t
HD;STA t
HD;DAT t
HIGH t
SU;DAT t
SU;STA
Sr
Figure 5. I
2
C timing t
HD;STA t
SP t
SU;STO
P
010aaa225
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
11.5 PDM timing characteristics
Table 10. PDM interface characteristics; see
All parameters are guaranteed for V
= 8 Ω
; L
L
= 44 μH
; f i
= 1 kHz; f
BAT
= 3.6 V; V s
= 48 kHz; T amb
DDD
= 1.8 V; V
DDP
= V
BST
= 9.0 V, Adaptive Boost mode; L
= 25 °C; default settings, unless otherwise specified.
BST
= 1 μH
;R
L
Symbol Parameter clock frequency
Conditions
-
Min Typ
3.072
-
Max Unit
MHz f clk
δ clk t h clock duty cycle hold time after clock HIGH
45
30 -
-
-
55 % ns after clock LOW 30 ns t su set-up time after clock HIGH after clock LOW
30
30 -
-
-
ns ns
[1] L
BST
= boost converter inductance; R
L
= load resistance; L
L
= load inductance.
[2] PDM Clock is 64xfs, with fs selected by AUDFS. Typical 3.072 Mhz is corresponding to f s
= 48 kHz.
CLK t su(CLKH) t h(CLKH) t su(CLKL) t h(CLKL)
DATA
Figure 6. PDM timing
010aaa711
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
12 Application information
12.1 Application diagrams
1.8 V
RFVBAT
5.1 Ω
CFVBAT
1 µF
LBST
1 µH
CVBAT
22 µF
CBST
1 nF
CVDDD
100 nF
SPK l 2 S
BASEBAND
PROCESSOR l 2 C
CTRL (I 2 C) SDA
SCL
AUDIO IN (TDM)
SPKBST (TDM)
DATAIN
FS
BCK
DATAO
RST
INT
PDMCLK
PDMDAT
TFA9872
VDDP
VBST
CVDDP
33 µF
OUTA
OUTB speaker
+
aaa-021842
Figure 7. Typical mono application
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
CTRL (I 2 C) l 2 C
AUDIO IN (TDM)
SPK l 2 S
SPKBST (TDM)
BASEBAND
PROCESSOR
CVDDD
100 nF
SDA
SCL
DATAIN
FS
BCK
DATAO
RST
INT
PDMCLK
PDMDAT
1.8 V
CFVBAT
1 µF
RFVBAT
5.1 Ω
TFA9872
LBST 1 µH
CVBAT
22 µF
CBST
1 nF
VDDP
VBST
CVDDP
33 µF
OUTA
OUTB speaker
+
-
CVDDD
100 nF
1.8 V
CFVBAT
1 µF
RFVBAT
5.1 Ω
SDA
SCL
DATAIN
FS
BCK
DATAO
RST
INT
PDMCLK
PDMDAT
TFA9872
LBST 1 µH
CVBAT
22 µF
CBST
1 nF
V
DDP
VBST
CVDDP
33 µF
OUTA
OUTB speaker
+
-
1.8 V
Figure 8. Typical stereo application (using separated coils)
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
CTRL (I 2 C) l 2 C
AUDIO IN (TDM)
SPK l 2 S
SPKBST (TDM)
BASEBAND
PROCESSOR
CVDDD
100 nF
SDA
SCL
DATAIN
FS
BCK
DATAO
RST
INT
PDMCLK
PDMDAT
1.8 V
CFVBAT
1 µF
RFVBAT
5.1 Ω
TFA9872
LBST 1 µH
CVBAT
22 µF
CBST
1 nF
V
DDP
VBST
CVDDP
33 µF
OUTA
OUTB speaker
+
-
CVDDD
100 nF
1.8 V
CFVBAT
1 µF
RFVBAT
5.1 Ω
SDA
SCL
DATAIN
FS
BCK
DATAO
RST
INT
PDMCLK
PDMDAT
TFA9872
RHVBAT
1 MΩ
V
DDP
VBST
CVDDP
33 µF
OUTA
OUTB speaker
+
-
1.8 V
Figure 9. Typical stereo application (using a single coil)
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
CVDDD
100 nF l 2 C
SPK l 2 S
BASEBAND
PROCESSOR
CTRL (I 2 C) SDA
SCL
AUDIO IN (TDM) DATAIN
SPKBST (TDM)
FS
BCK
DATAO
RST
INT
PDM SaM (PDM)
PDMCLK
PDMDAT
1.8 V
RFVBAT
5.1 Ω
CFVBAT
1 µF
TFA9872
LBST
1 µH
CVBAT
22 µF
CBST
1 nF
VDDP
VBST
CVDDP
33 µF
OUTA
OUTB speaker
+
-
AUXSAMN
CAUX1
CAUX2
AUXSAMP
FAUX1 RAUX1
100 pF
100 pF
CAUX3
33 nF speaker
+
-
FAUX2 RAUX2 aaa-021844
The configuration shown also supports speaker playback
Figure 10. Typical SaM application
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
13 Package outline
WLCSP42: wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.50 mm SOT1459-2 ball A1 index area
E B A
D
A
A 2
A
1 detail X e
1 C e b
Ø v
Ø w
C
C
A B
Z
D1
G
F
E
D
C
B
A ball A1 index area
1 2
Z
E1
3 4 5 6
Z e
D2 e
2
X
Z
E2
0 3 mm scale
Dimensions (mm are the original dimensions) mm
Unit max nom min
A
0.54
0.50
0.46
A
1
0.23
0.20
0.17
A
2
0.325
0.300
0.275
b D E e
0.29 3.16 2.49
0.26 3.13 2.46 0.4
0.23 3.10 2.43
e
1
2.0
e
2
Z
D1
Z
D2
Z
E1
Z
E2 v w y
2.4
0.365 0.365
0.245
0.215
0.05
0.02
0.03
y
Outline version
SOT1459-2
IEC JEDEC
References
JEITA
- - -
Figure 11. Package outline TFA9872AUK/N1 (WLSCP42)
European projection sot1459-2_po
Issue date
16-02-25
16-03-01
TFA9872_SDS
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
WLCSP42: wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.525 mm (backside coating included) SOT1459-3 ball A1 index area
E B A
D
A
A
2
A
1 detail X e
1 C e b
Ø v
Ø w
C
C
A B
Z
D1
G
F
E
D
C
B
A ball A1 index area
1 2
Z
E1
3 4 5 6
Z e
D2 e
2
X
Z
E2
0 3 mm scale
Dimensions (mm are the original dimensions)
Unit A A
1
A
2 mm max nom min
0.565
0.525
0.485
0.20
0.33
Note: Backside coating 25 µm
Outline version
SOT1459-3
IEC b D E e
3.16 2.49
0.26 3.13 2.46 0.4
3.10 2.43
JEDEC
- - e
1
2.0
References e
2
2.4
JEITA
Z
D1
Z
D2
Z
E1
0.365 0.365
0.245
Z
E2
0.215
v w
European projection y
0.05
0.02
0.03
y
Figure 12. Package outline TFA9872CUK/N1 (WLCSP42) sot1459-3_po
Issue date
16-03-01
16-05-09
TFA9872_SDS
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
14 Soldering of WLCSP packages
14.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
14.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
14.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 1) than a SnPb process, thus reducing the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature), and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with
Table 11. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm
3
)
< 1.6
1.6 to 1.5
< 350
260
260
350 to 2000
260
250
> 2.5
250 245
> 2000
260
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.
Studies have shown that small packages reach higher temperatures during reflow soldering, see
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NXP Semiconductors temperature
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone maximum peak temperature
= MSL limit, damage level minimum peak temperature
= minimum soldering temperature peak temperature time
001aac844
MSL: Moisture Sensitivity Level
Figure 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
14.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
14.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after reflow can be done with X-ray to monitor defects such as bridging, open circuits and voids.
14.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip will be damaged. In that case it is recommended not to re-use the chip again.
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NXP Semiconductors TFA9872_SDS
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Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. Removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. The surface of the substrate should be carefully cleaned and all solder and flux residues and/ or underfill removed. When a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
14.3.4 Cleaning
Cleaning can be done after reflow soldering.
TFA9872_SDS
Product short data sheet
COMPANY PUBLIC
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
15 Revision history
Table 12. Revision history
Document ID
TFA9872_SDS v.1
Release date Data sheet status Change notice Supersedes
20170412 Product data sheet -
TFA9872_SDS
Product short data sheet
COMPANY PUBLIC
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NXP Semiconductors TFA9872_SDS
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16 Legal information
16.1 Data sheet status
Document status
Objective [short] data sheet
Preliminary [short] data sheet
Product [short] data sheet
Product status
Development
Qualification
Production
Definition
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
TFA9872_SDS
Product short data sheet
COMPANY PUBLIC
Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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NXP Semiconductors TFA9872_SDS
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Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
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Product short data sheet
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NXP Semiconductors TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
Contents
General description ............................................ 1
Features and benefits .........................................2
Applications .........................................................2
Quick reference data .......................................... 3
Ordering information .......................................... 4
Block diagram ..................................................... 5
Pinning information ............................................ 6
Pinning ...............................................................6
Pin description ................................................... 7
Functional description ........................................9
Limiting values ..................................................10
Thermal characteristics ....................................10
Characteristics .................................................. 11
DC Characteristics ...........................................11
AC characteristics ............................................13
I2S timing characteristics .................................17
I2C timing characteristics ................................ 18
PDM timing characteristics .............................. 19
Application information ....................................20
Application diagrams ....................................... 20
Package outline .................................................24
Soldering of WLCSP packages ........................26
Introduction to soldering WLCSP packages .....26
Board mounting ............................................... 26
Reflow soldering .............................................. 26
Stand off .......................................................... 27
Quality of solder joint .......................................27
Rework .............................................................27
Cleaning ...........................................................28
Revision history ................................................ 29
Legal information ..............................................30
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'.
© NXP B.V. 2017.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 April 2017
Document identifier: TFA9872_SDS
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