NXP TFA8200HN Highly power-efficient DSP embedded class-D audio amplifier Data Sheet

The key functional blocks of the TFA8200 are shown in

5 15 μA P o(RMS) RMS output power on pin V DDD ; power down mode R L = 8 Ω THD+N = 1 % THD+N = 10 % 0.65

0.7

0.85

W W η po output power efficiency R L = 4 Ω THD+N = 1 % THD+N = 10 % R L = 8 Ω; V DDP = 4.2 V THD+N = 1 % THD+N = 10 % R L = 4 Ω; V DDP = 4.2 V THD+N = 1 % THD+N = 10 % R L = 8 Ω; V DDP = 5.0 V THD+N = 1 % THD+N = 10 % R L = 4 Ω; V DDP = 5.0 V THD+N = 1 % THD + N = 10 % P o(RMS) = 850 mW 1.2

1.5

0.9

1.1

1.6

1.95

1.35

1.6

2.35

2.75

92 W W W W W W W W W W % [1] After switching from off/amplifier mode to power-down mode.

TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

5 Ordering information

Table 2. Ordering information Type number Package

TFA8200HN

Name

HVQFN24

Description

plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm

6 Block diagram

V DDD 23 SDA 1 SCL 2 I 2 C CONTROL

TFA8200

SDI1 SCK1 LRCK1 20 21 22 n.c.

6, 14 STABA 13 PROTECTION CIRCUITS: OCP OTP OFP UFP IBP TEST1 3 TEST2 15 TEST3 5 SDI2 SCK2 LRCK2 17 18 19 MUX DIGITAL AUDIO RECEIVER PLL 2nd ORDER LOOP HIGH PASS FILTER DSP VOLUME CONTROL DRC 5 BAND EQUALIZER ADSEL1 16 ADSEL2 4

Figure 1. Block diagram

24 GNDD BASS TREBLE BOOST DAP POWER LIMITER PWM 2nd ORDER LOOP H-BRIDGE

Version

SOT616_3 7, 8 V DDP 10 OUTA 9 OUTB 11, 12 GNDP

aaa-032537

TFA8200

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NXP Semiconductors

7 Pinning information

7.1 Pinning TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

terminal 1 index area SDA SCL TEST1 ADSEL2 TEST3 n.c.

1 2 5 6 3 4

TFA8200

DAP (1) 18 17 16 15 14 13 SCK2 SDI2 ADSEL1 TEST2 n.c.

STABA TFA8200

Product data sheet

aaa-032538

Transparent top view 1. Exposed die attach paddle (DAP)

Figure 2. Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Pin Type Description

SDA 1 IO I 2 C-bus data input/output SCL 2 I I 2 C-bus bit clock input TEST1 ADSEL2 4 TEST3 n.c.

V DDP OUTB OUTA GNDP STABA n.c

3 5 6 9 10 11, 12 P 13 O 14 O O test signal input 1; for test purposes only; connect to PCB ground address selection input 2 test signal input 3; for test purposes only; connect to PCB ground not connected; connect to PCB ground analog supply voltage (2.5 V to 5.5 V) output B (negative) output A (positive) analog ground, PCB ground reference 1.8 V analog stabilizer output not connected; connect to PCB ground TEST2 15 ADSEL1 16 SDI2 SCK2 LRCK2 17 18 19 SDI1 20 I I I I I I test signal input 2; for test purposes only; connect to PCB ground address selection input 1 digital audio data input 2 digital audio bit clock input 2 digital audio word select input 2 digital audio data input 1 All information provided in this document is subject to legal disclaimers.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Symbol

SCK1 LRCK1 V DDD GNDD DAP -

Pin

21 22 23 24 I

Pin Type Description

digital audio bit clock input 1 I P P digital audio word select input 1 digital supply voltage (1.8 V) digital ground, PCB ground reference P exposed Die Attached Paddle (DAP); connect to PCB ground TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

8 Functional description

The TFA8200 is a high-efficiency mono bridge tied load (BTL) class-D amplifier with digital audio inputs. It supports all commonly used formats.

second order feedback loop.

Figure 1

. In the digital domain, the audio signal is processed and converted into a pulse width modulated (PWM) signal using a 3-level modulation. In the analog domain, the PWM signal is amplified using a The audio signal-processing path is described below: 1. The MUX selects the serial interface input to be used.

2. The digital audio receiver translates the serial input signal into a standard internal mono audio stream.

3. The programmable high-pass filter blocks DC signals and low frequency signals.

4. The volume control provides gain and attenuation functionality. The user can adjust it or it can be adjusted dynamically via the dynamic range compressor (DRC). The volume control can be used to adjust the signal level between −70 dB and +24 dB.

5. The 5-band parametric equalizer can be used to equalize the mono audio stream.

It can be used for speaker transfer curve compensation to optimize the audio performance of the speakers.

6. The bass and treble boost function provides another way to adjust the sound.

7. The power limiter limits the maximum output signal of the TFA8200. The power limiter settings are 0 dB to −124 dB in steps of 0.5 dB. This function can be used to limit the maximum output power delivered to the speakers at a fixed supply voltage and speaker impedance.

8. The PWM controller block converts the audio signal into a 3-level modulated PWM signal. The 3-level modulation provides a high signal-to-noise performance and eliminates clock jitter noise.

9. The second-order feedback loop ensures excellent audio performance and high power supply rejection ratio.

10.The H-BRIDGE allows the TFA8200 to deliver the required output power between terminals OUTA and OUTB.

The internal clocks of the TFA8200 are derived from the digital audio interface (SCK1 and SCK2) using a PLL. The reference input for the PLL is selected via the digital input MUX.

The audio signal path can be selected via the I 2 C-bus interface.

• • • • • •

The PLL block generates the system clock.

The following protection circuits are built into the TFA8200: Overtemperature protection (OTP) Overcurrent protection (OCP) Underfrequency protection (UFP) Overfrequency protection (OFP) Invalid bit-clock protection (IBP) DC-blocking TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 8.1 Operating modes

The TFA8200 supports the following operating modes, which are controlled via the I 2 C bus interface:

• Power-down mode

minimum; the I 2 , used to switch off the device; current consumption is reduced to a C-bus remains operational; the PWM outputs are disabled.

• Off mode

, in which the class-D amplifier is switched off; the TFA8200 is completely biased and the PWM outputs are disabled.

• Amplifier mode,

in which the digital inputs are used to generate a signal between OUTA and OUTB.

The TFA8200 device control settings are detailed in

Table 21 .

8.1.1 Power-up/power-down

The power-up and power-down timing of the TFA8200 is illustrated in Figure 3

. Before the operating mode is selected, the external power supply levels, V bits OPMODE, bit POWERUP in the device control register ( DDP

Table 21

and V DDD , must be within the specified operating ranges. Before the operating mode can be selected via

) must be set to 1.

After the turn-on delay (t d(on) ), the device automatically generates a soft unmute function.

When OPMODE is set to 0, a soft mute function is generated. The TFA8200 must be set to power-down mode before the power supplies are disconnected or turned off.

V DDP , V DDD I 2 C POWERUP (00h, bit 0) I 2 C OPMODE (00h, bit 3) serial interface input signals OUTA, OUTB TFA8200

Product data sheet

filtered BTL output signal t d(on) operating t d(mute_off)

Figure 3. Power-up/power-down timing

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t d(soft_mute)

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 8.1.2 Supported digital audio data formats

The TFA8200 supports a commonly used range of I data formats. The I 2 S, PCM, and IOM2 digital audio S formats, selected via bits I2S_SET in the serial interface control

), are listed in

Table 4 . The PCM/IOM2 formats are listed in

Table 5

The TFA8200 automatically detects the number of slots by measuring the ratio between

the sync frequency (8 kHz) and the data clock. Table 24 details the I

C settings for the PCM/IOM2 formats.

Table 4. I 2 S-supported digital audio data formats SCK frequency Interface format (MSB first)

32 f s I 2 S (Philips) standard MSB-justified 32 f s 32 f s 64 f s 64 f s 64 f s I LSB-justified - 16 bits 2 S (Philips) standard MSB-justified LSB-justified - 16 bits 64 f s 64 f s 64 f s LSB-justified - 18 bits LSB-justified - 20 bits LSB-justified - 24 bits

Supported data format

up to 16-bit data up to 16-bit data 16-bit data up to 24-bit data up to 24-bit data 16-bit data 18-bit data 20-bit data 24-bit data TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

WS LEFT RIGHT 1 2 3 1 2 3 BCK DATA MSB B2 MSB B2 I 2 S-BUS FORMAT MSB WS 1 BCK DATA MSB B2 2 LEFT 3 1 2 RIGHT 3 WS LSB MSB B2 MSB-JUSTIFIED FORMAT LEFT 16 15 2 1 LSB MSB B2 RIGHT 16 15 BCK DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS MSB B2 WS LEFT RIGHT 18 17 16 15 2 1 18 17 16 15 BCK DATA MSB B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18 BITS MSB B2 B3 B4 WS LEFT 20 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 BCK DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 WS BCK 24 23 22 21 LEFT 20 19 18 17 16 15 2 1 24 23 22 21 RIGHT 20 19 18 17 16 15 DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB

Figure 4. I 2 S-supported digital audio data formats

LSB-JUSTIFIED FORMAT 24 BITS MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 2 1 B15 LSB 2 1 B17 LSB 2 1 B19 LSB 2 1 B23 LSB

010aaa458

TFA8200

Product data sheet

2 4 4 6 8

Table 5. PCM/IOM2-supported audio data formats Number of slots f s (kHz) Sync frequency (kHz) on LRCK pin

2 8 or 16 8 8 or 16 8 or 16 8 or 16 8 or 16 8 or 16 8 8 8 8 8 12 16 reserved 2 8 or 16 8 or 16 8 or 16 8 8 8

Supported data formats

8-bit data 8-bit data 8-bit data 8-bit data 8-bit data 8-bit data 8-bit data 8-bit data 16-bit data

Data clock (kHz) on SCK pin

128 128 256 256 384 512 768 1024 256 All information provided in this document is subject to legal disclaimers.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Number of slots f s (kHz)

3 4 6 8 12 12 8 or 16 8 or 16 8 or 16 8 or 16 8 or 16 8 or 16 8 8 8 8

Sync frequency (kHz) on LRCK pin

8 8

Supported data formats

16-bit data 16-bit data 16-bit data 16-bit data 16-bit data 16-bit data

Data clock (kHz) on SCK pin

384 512 768 1024 1536 1536 LRCK SCK SDI MSB B2 Slot 0 LSB MSB B2 Slot 1 LSB MSB B2 Slot 2 SHORT SYNC PCM/IOM2 FORMAT Slot N - 1 LSB MSB B2 Slot N LSB LRCK SCK SDI MSB B2 LSB MSB B2 LSB MSB B2 Slot 0 Slot 1 Slot 2 LONG SYNC PCM/IOM2 FORMAT

Figure 5. PCM/IOM2-supported digital audio data formats

Slot N - 1 LSB MSB B2 Slot N LSB

010aaa652

8.2 Digital signal processor (DSP) features 8.2.1 Serial interface selection • • •

The TFA8200 contains two serial interfaces. The active interface is selected via bit INPUT_SEL in the device control register (see

Table 21

). When this bit is toggled, the following sequence is initiated: Soft mute is activated for 128/f s seconds The TFA8200 switches to off mode and the serial interface input is toggled The TFA8200 switches back to operating mode and soft mute is released TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 8.2.2 Mono selection

Mono selection is used to select the digital audio input channel to be amplified. The options are:

• • •

Left channel Right channel Left + right channels (sum divided by two) Separate mono selection is provided for the two serial interfaces via bits MONO_SEL in the serial interface control registers (addresses 01h and 03h; see

The high-pass filter control setting (bits HP_CTRL, see Table 30 )

8.2.3 Programmable high-pass filter

To block DC and low frequency signals, the TFA8200 features a first-order high-pass filter on the digital audio input. DC values at the output can damage the speaker.

The high-pass filter cut-off frequency is determined by:

• •

The sample frequency, f s The relationship between these parameters and the cut-off frequency is defined in

Equation 1 :

(1) HP_CTRL can be programmed to any integer value between 0 and 511 (see

Table 30

). If

HP_CTRL = 0 or bit HPF_BP in the bypass control register is set to 1 (see Table 27 ), the

high-pass filter is bypassed.

8.2.4 De-emphasis

Digital de-emphasis is sometimes required. To achieve good SNR over the complete audio band, the high frequency components of the audio signal were amplified prior to transmission (= emphasis).

The de-emphasis filter is a simple first order filter. The cut-off frequency of the de emphasis low-pass filter is approximately 3.5 kHz. The TFA8200 de-emphasis filter is

supported for four sample frequencies, as detailed in Table 6

Table 6. De-emphasis control [1:0] Control value

[1]

Value selected via bits DE_PHAS in the de-emphasis, soft/hard mute and power limiter control register (see Table 32 ).

01 10 11

f s (kHz)

de-emphasis inactive 32 44.1

48 [1] [2]

Default value.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 8.2.5 Equalizer

The equalizer can be used for speaker curve compensation or for customer equalizer settings, such as jazz, pop, rock, or classical music. The equalizer function can be bypassed or configured as 5-band.

8.2.5.1 Equalizer band function •

The following three filter parameters determine the shape of each parametric equalizer band: (Relative) center frequency (2)

• •

Quality factor Q Gain factor G In

Equation 2

, f c is the center frequency and f s is the sample frequency.

The definition of the quality factor is the center frequency divided by the 3 dB bandwidth

(see Equation 3

). In parametric equalizers, it is only valid when the gain is set very low (−30 dB).

(3) TFA8200

Product data sheet

Each band filter can be programmed to perform a band-suppression (G <⅛1) or a band amplification (G > 1) function around the center frequency.

Each band of the TFA8200 equalizer has a second order regalia-mitra all-pass filter

structure. The structure is shown in Figure 6

+ ½ + Y(z) + X(z) s K 0 /2 A(z)

010aaa406

Figure 6. Regalia-mitra filter flow diagram

The transfer function of this all-pass filter is given in

Equation 4 :

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

A(z) is the second-order filter structure. The transfer function of A(z) is given in

Equation 5 :

(5) Z −1 equals one f s delay period. The relationship between the programmable parameters K 0 , K 1 , and K 2 and the filter parameters G, ω, and Q is shown in

Equation 6

and

Equation 7 .

Equation 6 can be used to calculate band suppression (G < 1) functions.

(6)

Equation 7 can be used to calculate band amplification (G ≥ 1) functions.

(7) The ranges of the parametric equalizer settings for each band are:

• • •

The gain, G, is from −30 dB to +12 dB.

The center frequency, f c , is from 0.0004 ´ f The quality factor, Q, is from 0.001 to 8.

s to 0.49 ´ f s .

Filter coefficients must be entered for each filter stage via the I 2 C-bus interface to

configure the filters (see Section 9.4.3

Figure 7 , Figure 8

, and

Figure 9 illustrate some possible equalizer band transfer

functions. The relationships are symmetrical for the suppression and amplification functions. A skewing effect can be observed at higher frequencies.

For optimum numerical noise performance, different configurations are available for a given filter transfer function. The binary filter configuration parameters t 1 and t 2 control the actual configuration. They must be chosen according to

Equation 8

(8) TFA8200

Product data sheet

A maximum of 12 dB amplification, regarding the input signal, can be achieved per equalizer stage. The equalizer band signals are processed in sequence from the highest (Band A) to the lowest (Band E). Each band can attenuate the signal by 6 dB. So, to All information provided in this document is subject to legal disclaimers.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

prevent numerical clipping at filter settings of over 6 dB amplification, band filters can be scaled by 0 dB or −6 dB. For optimum numerical noise performance, steps of −6 dB amplification must be applied to the bands in sequence, starting with B and A, as long as they are able to amplify the signal without clipping.

A filter scale factor, s, is associated with each of the equalizer bands. It is set via the

relevant EQx_s control bit (see Table 25

Table 7. Equalizer filter scale factor settings s

0 1

scale factor (dB)

0 −6

8.2.5.2 Equalizer band control

For compact representation with positive signed parameters, parameters k 1 ’ and k 2 ’ are introduced in

Equation 9 .

(9) TFA8200

Product data sheet

Parameters K 0 , k 1 ', k 2 ', t 1 , t 2 , and s must be combined in two 16-bit control words, word1 and word2 (see

Table 24 and Table 25 ), using the format shown in

Table 8 . Parameters

k 1 ' and k 2 ' are unsigned floating-point representations in

Equation 9 .

(10) In

Equation 10 , M is the unsigned mantissa and E the negative signed exponent. For

example, in word2 bits [14:8] = [0111 010] represent k 2 ' = (7 / 2 4 ) × 2 −2 = 1.09375 × 10 −1 .

Table 8. Equalizer control word construction Word Section Data

word1 word1 word1 word2 word2 15 [14:4] [3:0] 15 [14:11] t 1 11 mantissa bits of k 1 ’ four exponent bits of k 1 ’ t 2 four mantissa bits of k 2 ’ word2 word2 word2 [10:8] [7:1] 0 three exponent bits of k 2 ’ k 0 ’ s All information provided in this document is subject to legal disclaimers.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

010aaa222

12 G (dB) Q1 = 0.27

8 Q2 = 0.61

Q3 = 1.65

4 0 10 10 2 10 3 10 4 f (Hz) 10 5

Figure 7. Transfer functions for selected values of Q, the quality factor

010aaa223

12 G (dB) 8 4 0 10 10 2 10 3 10 4 f (Hz)

Figure 8. Transfer functions for selected values of f c , the center frequency

10 5 TFA8200

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NXP Semiconductors

12 G (dB) 6

TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

010aaa224

0 -6 -12 10 10 2 10 3 10 4

Figure 9. Transfer functions for selected values of G, the gain factor

f (Hz) 10 5

8.2.6 Bass and treble control

The TFA8200 contains first-order shelving filters for bass and treble control. The device can attenuate or boost the bass and high frequency signals independently in 2 dB steps within a −18 dB to +18 dB range. Attenuation and boosting depend on the audio signal

zero crossing settings (see Section 8.2.9

for further details). The bass and treble corner

frequencies are adjustable.

The bass and treble corner frequencies, as a function of the I 2 C control settings and the

sample rate, are given in Table 9

Table 9. Corner frequency settings for bass and treble control Control value f s (kHz) Corner frequency (Hz) Bass

[1]

Treble

[2]

00 8, 16, 32, 64 11.025, 22.05, 44.1, 88.2

181 250 1090 1500 01

[3]

12, 24, 48, 96 8, 16, 32, 64 272 218 1630 2180 10 11 11.025, 22.05, 44.1, 88.2

12, 24, 48, 96 8, 16, 32, 64 11.025, 22.05, 44.1, 88.2

12, 24, 48, 96 reserved 300 326 300 413 450 3000 3260 3000 4130 4500 [1] [2] [3]

Value selected via bits F_BASS in the bass and treble control register (see Table 29

Value selected via bits F_TREBLE in the bass and treble control register (see Table 29 ).

Default value.

Figure 10

shows the bass function for a range of attenuation and boost settings with a sample rate of 48 kHz and a corner frequency of 272 Hz.

TFA8200

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NXP Semiconductors

dB 20 10

TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

010aaa650

0 - 10 - 20 10 10 2 10 3 10 4 f (Hz) V DDP = 3.7 V, 2 × 8 Ω BTL configuration, treble control = 0 dB, clip control on

Figure 10. Bass function in 2 dB steps; the treble control is set to flat

10 5

Figure 11

shows the treble function for a range of attenuation and boost settings with a sample rate of 48 kHz and a corner frequency of 1630 Hz.

010aaa649

dB 20 10 0 - 10 - 20 10 10 2 10 3 10 4 f (Hz) V DDP = 3.7 V, 2 × 8 Ω BTL configuration, bass control = 0 dB, clip control on

Figure 11. Treble function in 2 dB steps; the bass control is set to flat

10 5

8.2.7 Muting

The TFA8200 support two muting options, which are controlled via the I 2 C-bus interface:

• •

Soft muting Hard muting Soft muting prevents audible pops. The function smoothly reduces the gain setting of the audio channel to the mute level according to a raised cosine shape. Soft muting is performed in 128 / f s steps. Soft unmute results in a similar gain increase. Bit S_MUTE in

Table 32

enables and disables the soft mute function.

TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

The hard mute function immediately switches the outputs to 50 % duty cycle pulses. As a result, the input signals are abruptly blocked. Hard mute takes priority over soft mute.

Hard mute is enabled and disabled via bit H_MUTE in

Table 32

8.2.8 Digital volume control

The digital volume control has a range of −70 dB to +24 dB, programmable in 0.5 dB steps. The default setting is mute (0 × BD). Attenuation and boosting behavior is affected

by the zero crossing volume setting (see Section 8.2.9

for further details).

The volume control settings, and the resulting amplification or suppression factors, are

detailed in Table 10 .

Table 10. Volume control amplification and suppression Control value

[1]

Gain (dB)

00h +24 01h ...

BBh +23.5

steps of 0.5 dB −69.5

BCh BDh

The DRC can be bypassed via bit DRC_BP in Table 27 .

...

FFh −70 mute mute mute [1] [2] Control value is selected via bits VOL in the volume control register (see

Table 31

Default value.

8.2.9 Zero-crossing volume control

To minimize pop noise when the volume or bass/treble control is changing, the TFA8200 employs zero-crossing volume control.

When zero-crossing volume control is enabled (ZR_CRSS = 1; see crossing.

Table 31 ), the

TFA8200 increases or decreases the gain only when the audio signal passes a zero

8.2.10 Dynamic range compressor (DRC)

The TFA8200 provides a DRC to adjust power levels automatically according to programmable attack and release levels. The attack level is related to the peak value of the signal. The release level is related to the RMS value of the signal. The attack level is programmable using 16 available levels in the range −12 dB to +10 dB. The release level is programmable using 16 available levels in the range −29 dB to 0 dB relative to the attack level. The signal level is measured after equalizer, bass, and treble processing, but before it reaches the power limiter.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 8.2.10.1 Functional description

The DRC compresses the dynamic range of the audio stream. The volume control, equalizer, or bass/treble controls can be set so that the audio stream exceeds the 0 dBFS clip level. The DRC can be programmed to compress the louder audio content when the audio stream exceeds the 0 dBFS clip level, while quieter sounds remain unaffected, i.e. the DRC soft clips the audio stream. It is useful when background noise overpowers quiet audio passages. Increasing the volume using the volume control can make quiet audio passages audible but can cause louder audio passages to be distorted by clipping. The DRC prevents that this distortion happens by reducing the volume during loud audio passages and increasing it again for quiet passages.

The design of the DRC feedback loop, incorporating the equalizer and bass and treble controls, is illustrated in

Figure 12

DRC RMS volume control setting DRC volume LIMITER audio in PARAMETRIC 5-BAND EQUALIZER BASS AND TREBLE CONTROL

010aaa550

Figure 12. DRC feedback design 8.2.10.2 DRC control

The DRC has four programmable control settings:

• • • •

Attack level Attack rate Release level Release rate When the audio signal level exceeds the attack level, the DRC reduces the volume.

The attack level is based on the audio peak value. When the audio signal level drops below the attack level, the DRC stops reducing the volume. The rate of decrease is programmable via the attack rate. when the audio signal level drops to below the release level, the DRC increases it again. This level is based on the audio RMS-value and is related to the attack level. The rate of increase is programmable via the release level.

When the audio signal level reaches the release level or the DRC volume drops to 0 dB, the DRC stops increasing the volume.

Figure 13

shows the attack and release behavior of the DRC.

TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

audio in audio out attack level (peak value) release level (RMS-value) RMS value attack level (peak value) attack rate (dB/ms)

Figure 13. DRC attack and release behavior

TFA8200

Product data sheet Table 11. DRC attack and release levels Control value: attack level Attack level based on peak value; absolute value (dBFS) Control value: release level

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

[4]

1010 1011 −12 −10 −8 −6 −5 −4 −3 −2 −1 0 +1 +2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011

[4]

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release rate (dB/ms)

010aaa654

Release level based on RMS value (relative to the attack level ) (dB)

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Control value: attack level Attack level based on peak value; absolute value (dBFS) Control value: release level

1100 1101 1110 1111 +4 +6 +8 +10 1100 1101 1110 1111 [1] [2] [3] [4]

The control value is selected via bits AT_LVL in the DRC control register (see Table 28 ).

The control value is selected via bits RL_LVL in the DRC control register (see Table 28 ).

0 dB (RMS) release level equals 0 dB (peak) attack level.

Default value.

Release level based on RMS value (relative to the attack level ) (dB)

−3 −2 −1 0

Table 12. DRC attack and release rates Control value: attack rate Attack rate (dB/ms)

0000 3 0001 0010

[3]

0011 0100 0101 0110 2.7

2.25

1.8

1.35

0.9

0.45

0111 1000 1001 1010 1011 0.225

0.15

0.11

0.09

0.075

1100 1101 1110 1111 0.065

0.06

0.055

0.05

0111 1000 1001 1010

[3]

1011 1100 1101 1110 1111

Control value: release rate

0000 0001 0010 0011 0100 0101 0110 [1] [2] [3]

The control value is selected via bits AT_RATE in the DRC control register (see Table 28

The control value is selected via bits RL_RATE in the DRC control register (see Table 28

Default value.

Release rate (dB/ms)

0.5

0.137

0.075

0.05

0.036

0.03

0.026

0.021

0.020

0.017

0.015

0.014

0.013

0.012

0.011

0.01

TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 8.2.11 Power limiter

The power limiter controls the maximum output voltage in amplifier mode. This feature makes it possible to limit the output voltage across a peripheral (speaker) when necessary.

The TFA8200 output voltage depends on:

• • •

The analog supply voltage on pin V DDP The gain of the power limiter (G) The power limiter input signal (X i ) The bass/treble output signal is connected to the power limiter input and is relative to the fraction of full scale (FFS), from −1 to +1.

Equation 11

shows the relationship between these settings and the output voltage between pins OUTA and OUTB in the audio bandwidth: (11)

Equation 11

only applies with no load and with clip control off (see

Section 8.3

). Clip

control and the R dB.

DSon of the power switches reduce the maximum clipped output signal.

The power limiter gain can be reduced in 249 steps of 0.5 dB in the range 0 dB to −124 The maximum peak output voltage for the first ten power limiter gain settings is given in

Table 13

Table 13. Power limiter control settings

All parameters are guaranteed for V DDP = 5 V; no load; f i = 1 kHz; f s = 48 kHz; clip control off; T amb = 25 °C unless otherwise specified.

Control value

[1]

Power limiter gain (dB) Maximum peak output voltage (V)

00h

If smooth clipping is selected (CLIPCTRL = 0; see

0.0

V DDP 01h 02h 03h 04h 05h −0.5

−1.0

−1.5

−2.0

−2.5

V DDP V DDP V DDP 4.7

4.4

06h 07h 08h 09h −3.0

−3.5

−4.0

−4.5

4.2

4.0

3.7

3.5

[1] [2] The control value is selected via bits P_LIM in the De-emphasis, soft/hard mute and power limiter control register (see

Table 32 ).

Default value.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 8.4 Protections

The TFA8200 incorporates a wide range of protection circuits to facilitate optimal and safe application.

The following protection circuits are included in the TFA8200:

• • • • • •

Overtemperature protection (OTP) Overcurrent protection (OCP) Underfrequency protection (UFP) Overfrequency protection (OFP) Invalid bit-clock protection (IBP) DC-blocking via high-pass filter (see

Section 8.2.3

) The reaction of the device to fault conditions differs depending on the protection circuit involved.

8.4.1 Overtemperature protection (OTP) • • •

OTP is a ‘hard’ protection to prevent that heat damages the TFA8200. When the junction temperature exceeds 130 °C, overtemperature protection is triggered. When OTP is triggered, the output stages are set floating. OTP can be cleared automatically via a programmable timer or via the I bypass control register (

Table 27

C-bus interface, after which the output stages start to operate normally again. The programmable timer settings, selected via bits L_OTP in the ), are: 4.5 μs 100 ms 1 s OTP can also be set to no recovery. When no recovery is selected, setting the TFA8200 to off mode and then to amplifier mode clears the OTP.

TFA8200

Product data sheet 8.3 Class-D amplification and clip control

A fourth order sigma delta PWM converter converts the digital audio streams into 3-level modulated PWM signals. The analog back end amplifies the two PWM signals in a BTL configuration with complementary output stages.

One of two clip control configurations can be selected:

• •

Smooth clipping, clip control on Maximum power, clip control off

power.

Table 27 ), the clipping behavior has

no artifacts. To obtain the maximum output power, the device can be set to maximum The PWM frequency is related to the I 2 S input sample rate as detailed in

Table 4 .

Table 14. Power limiter control settings PWM frequency (kHz) Sample rate (kHz)

256 8, 16, 32, 64 352.8

384 11.025, 22.05, 44.1, 88.2

12, 24, 48, 96

SCK relative to sample rate

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 8.4.2 Overcurrent protection (OCP)

The output current of the class-D amplifiers is current limited. When an output stage exceeds a current in the range 1.3 A to 2.3 A, the output stages are set floating. OCP can be cleared automatically via a programmable timer or via the I settings, selected via bits L_OCP in the bypass control register ( C-bus interface, after which the output stages start to operate normally again. The programmable timer

Table 27

), are:

• • •

4.5 μs 27.5 μs 10 ms The OCP can also be set to no recovery. When no recovery is selected, setting the TFA8200 to off mode and then to amplifier mode clears the OCP.

8.4.3 Underfrequency protection (UFP)

When the clock input source is too low (< f UFP ), UFP sets the output stages floating. It can happen if, for example, the selected sample frequency (bits I2S_FS in low. Without UFP, peripheral devices in an application may be damaged.

C status register ( Table 33 ). When the

) is not in line with the applied sample rate. When the frequency of the input clock is lower than the selected sample frequency, the PWM switching frequency can become critically The UFP status can be monitored by polling the I 2

input sample rate is too low, the alarm is raised.

8.4.4 Overfrequency protection (OFP)

When the clock input source is too high (> f OFP ), OFP sets the output stages floating. It can happen if, for example, the selected sample frequency (bits I2S_FS in OFP, peripheral devices in an application may be damaged.

C status register ( Table 33 ). When the

) is not in line with the applied sample rate. When the frequency of the input clock is higher than the selected sample frequency, the PWM controller can become unstable. Without The OFP status can be monitored by polling the I 2

input sample rate is too high, the alarm is raised.

8.4.5 Invalid bit-clock protection (IBP)

If the SCK-to-LRCK ratio is not supported, the audio signal is distorted. The reason it occurs is that the sound processing blocks are operating at frequencies out of synchronization with the sample rate.

If the IBP alarm is raised for the selected channel, IBP prevents that the audio signal becomes distorted by shutting down the TFA8200. It disconnects the digital audio path.

Valid SCK-to-LRCK ratios for PCM interface formats are 16, 32, 48, 64, 96, 128, and 192. For I S interface formats, valid SCK-to-LRCK ratios are 32 and 64.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Table 15. Overview of protection circuits Protection circuits Symbol Conditions

OTP T j > 130 °C OCP UFP OFP IBP

8.4.6 Overview of protection circuits

Table 15

provides an overview of the protection circuits implemented.

I O > I O(ocp) PWM frequency < 96 kHz PWM frequency > 1031 kHz SCK/WS is not 16 ± 1, 32 ± 1, 48 ± 1, 64 ± 1, or 128 ± 1

I 2 C flag

OTP OCP UFP OFP IBP

Output

floating floating floating floating floating

Recovery

automatic when timer set to 4.5 μs,

100 ms, or 1 s (via bits L_OTP in Table 27 )

and T j < 130 °C; when no recovery is selected, via I C-bus automatic when timer set to 4.5 μs, 27.5 μs, or 10 μs (via bits L_OCP in

Table 27 ) and I

O < I O(ocp) recovery is selected, via I ; when no C-bus restart (when PWM frequency > 96 kHz, fault to operating) restart (when PWM frequency < 1031 kHz, fault to operating) restart (when SCK/WS is 16 ± 1, 32 ± 1, 48 ± 1, 64 ± 1, or 128 ± 1, fault to operating) TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

9 I

C-bus interface and register settings

9.1 I 2 C-bus interface

The TFA8200 supports the 400 kHz I The I 2 C-bus microcontroller interface mode standard.

C-bus is used to control the TFA8200 and to transmit and receive data.

The TFA8200 can operate only in I 2 C slave mode, as a slave receiver or as a slave transmitter.

The TFA8200 is accessed via an 8-bit code (see

Table 16

). Bits 1 to 7 contain the device address. Bit 0 (R/W) indicates whether a read (1) or a write (0) operation has been requested. Four separate addresses are supported for multichannel applications.

Applying the appropriate voltage to pins ADSEL1 (A1) and ADSEL2 (A2) select the required I C address as detailed in

Table 16 .

Table 16. I 2 C-bus device address Bit 7 (MSB) Bit 6 Bit 5 Bit 4

1 1 0 1

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

R/W

Table 17. I 2 C pin voltages in I 2 C control mode Logic value Voltage on pins ADSEL1 and ADSEL2

0 1 < V IL > V IH

9.2 I 2 C-bus write cycle

The sequence of events that must be followed when writing data to the I 2 C-bus registers of the TFA8200 is detailed in MSB first.

Table 18

. One byte is transmitted at a time. Each register stores two bytes of data. Data is always written in byte pairs. Data transfer is always The write cycle sequence using SDA is as follows: 1. The microcontroller asserts a start condition (S).

2. The microcontroller transmits the 7-bit device address of the TFA8200, followed by the R/W bit set to 0.

3. The TFA8200 asserts an acknowledge (A).

4. The microcontroller transmits the 8-bit TFA8200 register address to which the first data byte is written.

5. The TFA8200 asserts an acknowledge.

6. The microcontroller transmits the first byte (the most significant byte).

7. The TFA8200 asserts an acknowledge.

8. The microcontroller transmits the second byte (the least significant byte).

9. The TFA8200 asserts an acknowledge.

10.The microcontroller can either assert the stop condition (P) or continue transmitting data by sending another pair of data bytes, repeating the sequence from step 6. In the latter case, the TFA8200 auto-increments the targeted register address.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Table 18. I 2 C-bus write cycle Start TFA8200 Address R/W

S 11011A 2 A 1 0 A

TFA8200 first register address

ADDR A

MSB

MS1 A

LSB

LS1 A

More data...

<....>

Stop

9.3 I 2 C-bus read cycle

The sequence of events that must be followed when reading data from the I 2 C-bus registers of the TFA8200 is detailed in transfer is always MSB first.

Table 19 . One byte is transmitted at a time.

Each of the registers stores two bytes of data. Data is always written in byte pairs. Data The read cycle sequence using SDA is as follows: 1. The microcontroller asserts a start condition (S).

2. The microcontroller transmits the 7-bit device address of the TFA8200, followed by the R/W bit set to 0.

3. The TFA8200 asserts an acknowledge (A).

4. The microcontroller transmits the 8-bit TFA8200 register address from which the first data byte is read.

5. The TFA8200 asserts an acknowledge.

6. The microcontroller asserts a repeated start (Sr).

7. The microcontroller retransmits the device address followed by the R/W bit set to 1.

8. The TFA8200 asserts an acknowledge.

9. The TFA8200 transmits the first byte (the MSB).

10.The microcontroller asserts an acknowledge.

11.The TFA8200 transmits the second byte (the LSB).

12.The microcontroller asserts either an acknowledge or a negative acknowledge (NA).

•

If the microcontroller asserts an acknowledge, the TFA8200 auto-increases the target register address and steps 9 to 12 are repeated.

•

If the microcontroller asserts a negative acknowledge, the TFA8200 frees the I 2 C bus and the microcontroller generates a stop condition (P).

Table 19. I 2 C-bus read cycle Start TFA8200 address R/W First register address

S 11011A 2 A 1 0 A ADDR

TFA8200 address R/W

A Sr 11011A 2 A 1 1 A

MSB

MS1 A

LSB

LS1 A

More data...

<....>

Stop

NA P TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 9.4 Top-level register map

Table 20

describes the top-level assignment of register addresses to the functional control and status areas. There are 21 control registers and 1 status register.

10h 11h 12h 13h 14h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

Table 20. Top-level register map Register address (hex) Default (hex) Access Description

00h 0x0000 R/W

device control; see Table 21

01h 02h 03h 04h 05h 0x0A18 0x0007 0x0A18 0x0007 0x59DD R/W R/W R/W R/W R/W

serial Interface input 1; see serial Interface input 2; see

equalizer_A word_1; see

equalizer_A word_2; see equalizer_B word_1; see equalizer_B word_2; see

PCM/IOM2 format input 1; see PCM/IOM2 format input 2; see

15h 0xC63E 0x651A 0xE53E 0x4616 0xD33E 0x4DF3 0xEA3E 0x5EE0 0xF93E 0x0093 0x92BA 0x12A5 0x0004 0x10BD 0x0000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R

equalizer_C word_1; see equalizer_C word_2; see

bass and treble; see

high-pass filter; see volume control; see

see Table 32

Table 25 Table 24 Table 25 Table 24 Table 25

equalizer_D word_1; see

Table 24

equalizer_D word_2; see

Table 25 equalizer_E word_1; see Table 24 equalizer_E word_2; see Table 25

bypass control; see

Table 27

dynamic range compressor; see

Table 29

Table 30 Table 31

Table 28

de-emphasis, soft/hard mute and power limiter;

miscellaneous status; see Table 33

The following subsections provide details of the bits in these registers and the control and status functionality assigned to each.

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 9.4.1 Device control Table 21. Device control register (address 00h) bit description Bit Symbol Access Default Description

15:5 reserved 0x000 4 INPUT_SEL R/W 0 serial interface input selection 0: serial interface input 1 1: serial interface input 2 3 OPMODE R/W 0 operating mode selection 0: off mode 1: amplifier mode 2 1 reserved RESET R/W 0 0 0 POWERUP R/W 0 I 2 C reset activation 0: reset inactive 1: reset active; 1 is written to generate a reset, after which the RESET bit is automatically reset to 0 Power-down mode selection 0: Power-down mode 1: operating mode (dependent on OPMODE) TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 9.4.2 Serial interface control Table 22. Serial interface control registers (addresses 01h and 03h

[1]

) bit description Bit Symbol Access Default Description

15:12 reserved 11:10 MONO_SEL R/W 0000 10 mono selection 00: left channel; left channel content is amplified in amplifier mode 01: right channel; right channel content is amplified in amplifier mode 10: left + right channels; sum of left and right channels, divided by two, is amplified in amplifier mode 9:6 I2S_FS R/W 1000 11: reserved sample frequency (f s ) of digital-in signal 0000: 8 kHz 0001: 11.025 kHz 0010: 12 kHz 0011: 16 kHz 0100: 22.05 kHz 0101: 24 kHz 0110: 32 kHz 0111: 44.1 kHz 5:3 2 I2S_SET SCK_POL R/W R/W 011 0 1000: 48 kHz 1001: 64 kHz 1010: 88.2 kHz 1011: 96 kHz 1100 to 1111: reserved I 2 S format selection 000: reserved 001: reserved 010: MSB-justified data up to 24 bits 011: I 2 S data up to 24 bits 100: LSB-justified 16-bit data 101: LSB-justified 18-bit data 110: LSB-justified 20-bit data 111: LSB-justified 24-bit data enable SCK signal polarity inversion 0: no SCK signal polarity inversion 1: SCK signal polarity inversion enabled TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Bit

1:0

Symbol

I_MODE

Access Default Description

R/W 00 input audio mode selection 00: I 2 S mode 01: PCM/IOM2 Short Frame Sync Format 10: PCM/IOM2 Long Frame Sync Format 11: reserved [1] Serial interface 1 settings are controlled via register 01h; serial interface 2 settings are controlled via register 03h.

3:0

Table 23. PCM/IOM2 format control registers (addresses 02h and 04h

[1]

) bit description Bit Symbol Access Default Description

15:12 11 reserved PCM_FS R/W 0000 0 PCM sample frequency 0: 8 kHz 1: 16 kHz 10 A_LAW R/W 0 9 PCM_COMP R/W 0 U-LAW/A-LAW decoding selection (depending on PCM_COMP) 0: U-law decoding; default value 1: A-law decoding companded PCM data 8 7:4 PCM_DL D1_SLOT R/W R/W 0 0000 0: linear 1: companded (U/A-law) PCM data length (number of bits per slot) 0: 8-bit; default value 1: 16-bit slot number position of the first sample (at 8 kHz and 16 kHz) 0000: slot 0 0001: slot 1 .. ..

D2_SLOT R/W 0111 1111: slot 15 slot number position of the second sample (16 kHz) 0000: slot 0 0001: slot 1 .. ..

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Bit

3:0 (continued)

Symbol Access Default Description

0111: slot 7 .. ..

1111: slot 15 [1] PCM/IOM2 format settings of serial interface 1 are controlled via register 02h; PCM/IOM2 format settings of serial interface 2 are controlled via register 04h.

9.4.3 Equalizer configuration Table 24. Equalizer word1 control registers (addresses 05h, 07h, 09h, 0Bh, and 0Dh for equalizer bands A, B, C, D, and E respectively) bit description

‘x’ represents the equalizer band A, B, C, D, or E

Bit Symbol Access Default

[1]

Description

15 EQx_t1 R/W filter configuration parameter t 1

(see Section 8.2.5.1

) 14:4 3:0 EQx_k1m EQx_k1e R/W R/W 11 mantissa bits of filter parameter k 1

) four exponent bits of filter parameter k 1

Default settings are given in Table 20

) [1]

. The corresponding equalizer configuration is shown in

Table 26 .

Table 25. Equalizer word2 control register (addresses 06h, 08h, 0Ah, 0Ch, and 0Eh for equalizer bands A, B, C, D, and E respectively) bit description

x’ represents the equalizer band A, B, C, D, or E

Bit Symbol Description

15 10:8 7:1 0 EQx_t2 14:11 EQx_k2m EQx_k2e EQx_K0 EQx_s R/W R/W R/W R/W R/W filter configuration parameter t 2

(see Section 8.2.5.1

) four mantissa bits of filter parameter k 2

) three exponent bits of filter parameter k 2

filter scale-factor (s) (see Section 8.2.5.1

) seven-bit of filter gain parameter K 0

(see Section 8.2.5.1

)

) 0: no scaling applied 1: −6 dB amplification enabled [1]

Default settings are given in Table 20

. The corresponding equalizer configuration is shown in

Table 26 .

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Table 26. Default equalizer configuration for f s = 48 kHz Band A B

frequency (Hz) 100 300 Q-factor gain (dB) 1.65

0 1.65

1000 1.65

3000 1.65

10000 1.65

9.4.4 Bypass control Table 27. Bypass control register (addresses 0Fh) bit description Bit Symbol Access Default Description

15:8 reserved 0x00 7:6 L_OCP R/W 10 overcurrent protection timer setting 00: 4.5 μs floating when an overcurrent is detected 01: 27.5 μs floating when an overcurrent is detected 10: 10 ms floating when an overcurrent is detected 5:4 L_OTP R/W 01 11: no recovery (stays floating) when an overcurrent is detected overtemperature protection timer setting 00: 4.5 μs floating when an overtemperature is detected 3 2 1 0 CLIPCTRL HPF_BP DRC_BP EQ_BP R/W R/W R/W R/W 0 0 1 1 01: 100 ms floating when an overtemperature is detected 10: 1 s floating when an overtemperature is detected 11: no recovery (stays floating) when an overtemperature is detected clip control bypass setting (see

Section 8.3

) 0: clip control on (smooth clipping) 1: clip control off (maximum power) high-pass filter bypass setting 0: high-pass filter active 1: high-pass filter bypassed dynamic range compressor bypass setting 0: dynamic range compression active 1: dynamic range compression bypassed equalizer bypass setting: 0: equalizer active 1: equalizer bypassed TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications 9.4.5 Dynamic range compressor Table 28. DRC control register (addresses 10h) bit description Bit Symbol Access Default Description

15:12 AT_LVL R/W 1001 dynamic range compressor attack level; see

Table 11 for the attack level as a function of the

value of AT_LTV.

11:8 AT_RATE R/W 0010 37:4 RL_LVL R/W 1011 dynamic range compressor attack rate; see

Table 12 for the attack rate as a function of the

value of AT_RATE dynamic range compressor release level; see

Table 11 for the release level as a function of

the value of RL_LTV.

3:0 RL_RATE R/W 1010 dynamic range compressor release rate; see

Table 12 for the release rate as a function of

the value of RL_RATE

9.4.6 Bass and treble control Table 29. Bass and treble control register (addresses 11h) bit description Bit Symbol Access Default Description

15:14 reserved 13:9 G_TRBLE R/W 01001 treble gain (2 dB steps) 00000: −18 dB 00001: −16 dB .. ..

8:7 6:2 F_TRBLE G_BASS R/W R/W 01 01001 01001: 0 dB .. ..

10001: +16 dB 10010: +18 d8 10011 to 11111: reserved

treble control corner frequency (see

of F_TREBLE)

Table 9

for the corner frequency as a function of the value bass gain (2 dB steps) −18 dB −16 dB .. ..

01001: 0 dB .. ..

+16 dB +16 d8 reserved TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Bit

1:0

Symbol

F_BASS

Access Default Description

R/W 01 bass control corner frequency (see of F_BASS)

Table 9 for

the corner frequency as a function of the value

9.4.7 High-pass filter Table 30. High-pass filter control register (addresses 12h) bit description Bit Symbol Access Default Description

15:9 reserved 8:0 HP_CTRL R/W 0x04

high-pass filter control (see Section 8.2.3

discussion of the high pass corner frequency as a function of the value of HP_CTRL)

for a

[1]

Default value is 04h. From Equation 1 , giving a high-pass cut-off frequency of approximately 1.6 × f

s .

9.4.8 Volume control Table 31. Volume control register (address 13h) bit description Bit Symbol Access Default Description

15:13 reserved 000 12 ZR_CRSS R/W 1 volume update at zero crossing audio stream 0: zero-crossing volume control disabled 1: zero-crossing volume control enabled; default value 11:8 7:0 reserved VOL R/W R/W 0000 0xBD volume control (see

Table 10

for the amplification and suppression factors as a function of the value of bits VOL)

9.4.9 De-emphasis, soft/hard mute, and power limiter Table 32. De-emphasis, soft/hard mute and power limiter control register (address 14h) bit description Bit Symbol Access Default Description

15:12 reserved 0000 11:10 DE_PHAS 9 H_MUTE R/W R/W 00 0 de-emphasis settings (see hard mute

Table 6 for the de-

emphasis configuration for four sample rates as a function of the value of DE_PHASE) 8 S_MUTE R/W 0 0: no hard mute; default value 1: hard mute enabled; implemented by PWM signal with 50 % duty cycle soft mute; default value 0: soft mute disabled using raised cosine 1: soft mute enabled using raised cosine TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Bit

7:0

Symbol

P_LIM

Access Default Description

R/W 0xBD power limiter control settings (see of P_LIM)

Table 13

for suppressions factors as a function of the value

9.4.10 Miscellaneous status Table 33. Miscellaneous status register (address 15h) bit description Bit Symbol Access Description

15 reserved 14 PS R power stage status 0: class-D audio amplifier power stage floating 13 PORA R 1: class-D audio amplifier power stage switching; PWM signals on pins OUTA and OUTB analog 1V8 regulator status 0: 1V8 analog regulator is off or output voltage level is too low 1: 1V8 analog regulator output is available and correct 12:11 reserved 10:9 AMP R 8 IBP(2) R amplifier mode status 00: amplifier is off 01: startup 10: startup 11: amplifier is functional invalid bit clock protection on serial interface input 2 0: the ratio in frequency between the signal on pin SCK2 and the signal on pin LRCK2 is valid for the selected interface format 7 6 OFP(2) UFP(2) R R 1: the ratio in frequency between the signal on pin SCK2 and the signal on pin LRCK2 is invalid for the selected interface format overfrequency protection on serial interface input 2 0: the frequency of the signal on pin LRCK2 is in line with (or lower than) the selected interface format 1: the frequency of the signal on pin LRCK2 is higher than the selected interface format underfrequency protection on serial interface input 2 0: the frequency of the signal on pin LRCK2 is in line with (or higher than) the selected interface format 1: the frequency of the signal on pin LRCK2 is lower than the selected interface format TFA8200

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Bit

5 4 3 2 1 0

Symbol

IBP(1) OFP(1) UFP(1) OCPOKA OCPOKB OTPOK

Access

R R R R R R

Description

invalid bit clock protection on serial interface input 1 0: the ratio in frequency between the signal on pin SCK1 and the signal on pin LRCK1 is valid for the selected interface format 1: the ratio in frequency between the signal on pin SCK1 and the signal on pin LRCK1 is invalid for the selected interface format overfrequency protection on serial interface input 1 0: the frequency of the signal on pin LRCK1 is in line with (or lower than) the selected interface format 1: the frequency of the signal on pin LRCK1 is higher than the selected interface format underfrequency protection on serial interface input 1 0: the frequency of the signal on pin LRCK1 is in line with (or higher than) the selected interface format 1: the frequency of the signal on pin LRCK1 is lower than the selected interface format overcurrent protection on pin OUTA 0: overcurrent protection on pin OUTA active 1: overcurrent protection on pin OUTA inactive overcurrent protection on pin OUTB 0: overcurrent protection on pin OUTB active 1: overcurrent protection on pin OUTB inactive overtemperature protection 0: overtemperature protection active 1: overtemperature protection inactive TFA8200

Product data sheet

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Rev. 1 — 19 August 2019

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

10 Internal circuitry

Table 34. Internal circuitry Pin Symbol

1 SDA

Equivalent circuit

1 ESD 11, 12, 24

010aaa632

2 3 4 5 16 17 18 19 20 21 22 7; 8 SCL TEST1 ADSEL2 TEST3 ADSEL1 SDI2 SCK2 LRCK2 SDI1 SCK1 LRCK2 V DDP 2 to 5 16 to 22 11, 12, 24 ESD

010aaa633

7, 8 ESD 11, 12, 24

010aaa634

9 10 OUTB OUTA 7, 8 9, 10 11, 12, 24

010aaa635

TFA8200

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 19 August 2019

39 / 63

NXP Semiconductors Pin

13 15

TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications Symbol

STABA

Equivalent circuit

7,8 13 11, 12, 24 ESD

010aaa636

TEST2 7, 8 15 11, 12, 24 ESD

010aaa637

TFA8200

Product data sheet

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Rev. 1 — 19 August 2019

40 / 63

NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

11 Limiting values

Table 35. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

V V DDA DDD T j T stg T amb V x analog supply voltage digital supply voltage junction temperature storage temperature ambient temperature voltage on pin x on pin V DDP on pin V DDD pins LRCKx, SCKx, SDIx, SDA, SCL, ADSEL1, ADSEL2, TEST1, and TEST3 pin TEST2 pins OUTA and OUTB V ESD electrostatic discharge voltage pin STABA according to human body model (HBM) according to charge device model (CDM)

Min

−0.3

−55 −20 −0.3

−0.3

−0.6

−0.3

−2 −500

12 Thermal characteristics

Table 36. Thermal characteristics Symbol Parameter

R th(j-a) thermal resistance from junction to ambient

Conditions

in free air with natural convection JEDEC test board

Typ

49 2-layer application board 67 23 Ψ Ψ R j-lead j-top th(j-c) thermal characterization parameter from junction to lead thermal characterization parameter from junction to top of package thermal resistance from junction to case in free air with natural convection [1] [2] Measured on a JEDEC high K-factor test board (standard EIA/JESD 51-7).

Value depends on where measurement is taken on package.

6 5

Max

+5.5

+1.95

150 +150 +85 +3.6

V DDP + 0.3 V V DDP + 0.6 V +1.95

+2 V kV +500 V

Unit

V V °C °C °C V

Unit

K/W K/W K/W K/W K/W TFA8200

Product data sheet

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Rev. 1 — 19 August 2019

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NXP Semiconductors TFA8200 Mono BTL class-D audio amplifier with digital inputs for IOT applications

13 Characteristics

13.1 DC characteristics Table 37. DC characteristics

All parameters are guaranteed for V DDD = 1.8 V; V DDP = 3.7 V; R L = 8 Ω; L L = 44 μH; f i = 1 kHz; f s = 48 kHz; clip control off; T amb = 25 °C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

V DDP V DDD I P power supply voltage digital supply voltage supply current on pin V on pin V on pin V DDP DDD DDP ; amplifier mode with load; soft mute on 2.5

1.65

1.8

5.7

5.5

1.95

V V mA I DDD digital supply current on pin V DDP ; power-down mode on pin V DDD ; amplifier mode on pin V DDD ; power-down mode