STMicroelectronics VIPER53E-E Datasheet
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VIPer53EDIP - E
VIPer53ESP - E
OFF-line Primary Switch
Features
■
■
■
■
■
■
■
■
■
■
Switching frequency up to 300kHz
Current mode control with adjustable limitation
Soft start and shut-down control
Automatic burst mode in standby condition
(“Blue Angel“ compliant )
Undervoltage lockout with Hysteresis
Integrated start-up current source
Over-temperature protection
Overload and short-circuit control
Overvoltage protection
In compliance with the 2002/95/EC European
Directive
Description
The VIPer53E combines an enhanced current mode PWM controller with a high voltage
MDMesh Power MOSFET in the same package.
Block diagram
OSC
VDD
ON/OFF
OSCILLATOR
8.4/
11.5V
UVLO
COMPARATOR
125k
8V
4V
OVERTEMP.
DETECTOR
PWM
LA TCH
R1
S
FF Q
R2
R3 R4 R5
PowerSO-10 DIP-8
Typical applications cover offline power supplies with a secondary power capability ranging up to
30W in wide range input voltage, or 50W in single
European voltage range and DIP-8 package and
40W in wide range input voltage, or 65W in single
European voltage range and PowerSO-10 package, with the following benefits:
– Overload and short-circuit events controlled by feedback monitoring and delayed device reset;
– Efficient standby mode by enhanced pulse skipping.
– Integrated start-up current source is disabled during normal operation to reduce the input power.
DRAIN
BLANKING TIME
SELECTION
1V
150/400ns
BLANKING
PWM
COMPARATOR
STANDBY
COMPARATOR
0.5V
0.5V
OVERLOAD
COMPARATOR
4.4V
CURRENT
AMPLIFIER
Vcc
I
C OMP
January 2006
18V
OVERVOLTAGE
COMPARATOR
TOVL
DocRev1
4.5V
COMP SOURCE
1/31 www.st.com
31
Contents
Contents
VIPer53EDIP - E / VIPer53ESP - E
Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Rectangular U-I Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Secondary Feedback Configuration Example . . . . . . . . . . . . . . . . . . . . 9
Current Mode Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
High Voltage Start-up Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Short-Circuit and Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . 15
Regulation Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Special Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Electrical data
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 1.
Absolute maximum rating
Symbol Parameter
V
DS
Continuous Drain Source Voltage (T
J
= 25 ... 125°C)
(1)
-0.3 ... 620 V
I
D
V
DD
V
OSC
I
COMP
I
TOVL
Continuous Drain Current
Supply Voltage
OSC Input Voltage Range
COMP and TOVL Input Current Range
(1)
Internally limited
0 ... 19
0 ... V
DD
-2 ... 2
A
V
V mA
V
ESD
Electrostatic Discharge:
Machine Model (R = 0
Ω
; C = 200pF)
Charged Device Model
200
1.5
V kV
T
J
T
C
Junction Operating Temperature
Case Operating Temperature
Internally limited
°
C
-40 to 150
°
C
T
STG
Storage Temperature -55 to 150
°
C
1.
In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1k
Ω should be inserted in series with the TOVL pin.\
Table 2.
Thermal data
Symbol Parameter PowerSO-10
(1)
DIP-8
(2) Unit
R
R thJC thJA
Thermal Resistance Junction-case
Thermal Resistance Ambient-case
Max
Max
2
60
20
80
°
C/W
°
C/W
1.
When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected to the DRAIN pin.
2.
When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected to the device tab.
DocRev1 3/31
Electrical characteristics VIPer53EDIP - E / VIPer53ESP - E
T
J
= 25°C, V
DD
= 13V, unless otherwise specified
Table 3.
Power section
Symbol Parameter
BV
I
DSS
DSS
R
DS(on)
C
C t t fv rv oss
Eon
Drain-Source
Voltage
Off State Drain
Current
I
D
= 1mA; V
V
DS
COMP
= 0V
= 500V; V
COMP
= 0V; T j
= 125°C
Static Drain-Source
On State Resistance
Fall Time
I
D
= 1A; V
COMP
= 4.5V; V
TOVL
= 0V
T
J
= 25°C
T
J
= 100°C
I
D
= 0.2A; V
IN
= 300V
(1)
Rise Time
Drain Capacitance
I
D
= 1A; V
IN
= 300V
(1)
V
DS
= 25V
Effective Output
Capacitance
200V < V
DSon
< 400V
(2)
620
0.9
100
50
170
60
150
1
1.7
1.
On clamped inductive load
2.
This parameter can be used to compute the energy dissipated at turn on E ton to source voltage V
DSon
and the following formula:
according to the initial drain
E to n
=
1
---
2
⋅
C
Eon
⋅
300
2
⋅
⎛
⎝
V
DSon
----------------
300
⎞
⎠
1.5
V
µA
Ω
Ω ns ns pF pF
Table 4.
Oscillator Section
Symbol
F
OSC1
F
OSC2
Parameter
Oscillator Frequency
Initial Accuracy
Oscillator Frequency
Total Variation
Test Conditions
R
T
= 8k
Ω
; C
T
= 2.2nF
R
T
= 8k
Ω
; C
T
= 2.2nF
V
DD
= V
DDon
... V
DDovp
;
T
J
= 0 ... 100°C
V
OSChi
Oscillator Peak
Voltage
V
OSClo
Oscillator Valley
Voltage
Min.
Typ.
Max.
Unit
95 100 105 kHz
93 100 107 kHz
9
4
V
V
4/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Electrical characteristics
Table 5.
Supply Section
Symbol Parameter Test Conditions
V
DSstart
I
I
I
DDch1
DDch2
DDchoff
I
DD0
Drain Voltage Starting
Threshold
V
DD
= 5V; I
DD
= 0mA
Startup Charging Current
V
DD
= 0 ... 5V; V
DS
= 100V
Startup Charging Current V
DD
= 10V; V
DS
= 100V
Startup Charging Current in Thermal Shutdown
V
DD
= 5V; V
DS
T
J
> T
SD
- T
HYST
Operating Supply Current
Not Switching
F sw
= 0kHz; V
COMP
= 0V
V
V
V
V
I
DD1
DDoff
DDon
DDhyst
DDovp
Operating Supply Current
Switching
F sw
=100kHz
V
DD
Undervoltage
Shutdown Threshold
V
DD
Startup Threshold
V
DD
Threshold
Hysteresis
V
DD
Overvoltage
Shutdown Threshold
Min.
Typ.
Max.
Unit
0
7.5
9.3
V mA mA mA
11 mA mA
V
10.2
11.5
12.8
V
2.6
17
34
-12
-2
8
9
8.4
3.1
18
50
19
V
V
Table 6.
Pwm Comparator Section
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
V
H
COMP
COMPos
I
I
Dlim
Dmax
∆
V
COMP
V
COMP
/
∆
I
Offset
Peak Drain Current
Limitation
Drain Current
Capability
DPEAK
V
COMP
= 1 ... 4 V
dI
D
/dt = 0 1.7
2 dI
D
/dt = 0
I
COMP
= 0mA; V
TOVL
= 0V
dI
D
/dt = 0
V
COMP
= V
COMPovl
; V
TOVL
= 0V dI
D
/dt = 0
1.7
1.6
2
1.9
t d
Current Sense Delay to Turn-Off
I
D
= 1A
V
COMPbl
V
COMP
Blanking Time
Change Threshold
t b1 t b2 t
ONmin1
Blanking Time
Blanking Time
Minimum On Time
V
V
V
COMP
COMP
COMP
< V
> V
< V
COMPBL
300
100
450
250
1
400
150
600
2.3
2.3
2.3
500
200
750
V/A
V
A
A ns
V ns ns ns
DocRev1 5/31
Electrical characteristics VIPer53EDIP - E / VIPer53ESP - E
Table 6.
Pwm Comparator Section
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit t
V
COMPoff
V
ONmin2
COMPhi
Minimum On Time V
COMP
> V
COMPBL
V
COMP
Shutdown
Threshold
V
COMP
High Level I
COMP
=0mA
(1)
I
COMP
COMP Pull Up Current V
COMP
= 2.5V
250 350
0.5
4.5
0.6
450 mA
1.
In order to ensure a correct stability of the internal current source, a 10nF capacitor (minimum value 8nF) should always be present on the COMP pin.
ns
V
V
Table 7.
Overload Protection Section
Symbol Parameter Test Conditions
V
COMPovl
V
COMP
Overload
Threshold
I
TOVL
(1)
= 0mA
V
DIFFovl
V
COMPhi
to V
COMPovl
Voltage Difference
V
DD
= V
DDoff
... V
DDreg
;
I
TOVL
= 0mA
(1)
V
OVLth
V
TOVL
Overload
Threshold
t
OVL
Overload Delay C
1.
V
COMPovl
is always lower than V
COMPhi
OVL
= 100nF
Min.
Typ.
Max.
Unit
50
4.35
V
150 250 mV
4
8
V ms
Table 8.
Over temperature Protection Section
Symbol
T
SD
T
HYST
Parameter
Thermal Shutdown
Temperature
Thermal Shutdown
Hysteresis
Test Conditions
Min.
Typ.
Max.
Unit
140 160 °C
40 °C
Table 9.
Typical Output Power Capability
Type
European
(195 - 265Vac)
VIPer53EDIP-E 50W
VIPer53ESP-E 65W
US / Wide range
(85 - 265Vac)
30W
40W
6/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E
3 Pin connections and function
Pin connections and function
Figure 1.
Pin connection (top view)
COMP 1
OSC 2
SOURCE 3
SOURCE 4
8 TOVL
7 VDD
6 NC
5 DRAIN
DIP-8
Figure 2.
Current and voltage conventions
I
DD
DRAIN
NC
NC
NC
VDD
TOVL
3
4
5
1
2
PowerSO-10
I
D
10
9
8
7
6
SOURCE
NC
NC
OSC
COMP
V
DD
VDD
V
OSC
I
OSC
OSC
15V
I
TOVL
TOVL
V
TOVL
V
COMP
COMP
I
COMP
DRAIN
SOURCE
V
DS
Table 10.
Pin function
Pin Name Pin Function
V
DD
Power supply of the control circuits. Also provides the charging current of the external capacitor during start-up.
The functions of this pin are managed by four threshold voltages:
- VDDon: Voltage value at which the device starts switching (Typically 11.5 V).
- VDDoff: Voltage value at which the device stops switching (Typically 8.4 V).
- VDDovp: Triggering voltage of the overvoltage protection (Trimmed to 18 V).
SOURCE Power MOSFET source and circuit ground reference.
DRAIN
COMP
Power MOSFET drain. Also used by the internal high voltage current source during the start-up phase, to charge the external V
DD
capacitor.
Allows the setting of the dynamic characteristic of the converter through an external passive network. The useful voltage range extends from 0.5V to 4.5V. The Power
MOSFET is always off below 0.5V, and the overload protection is triggered if the voltage exceeds 4.35V. This action is delayed by the timing capacitor connected to the
TOVL pin.
TOVL
OSC
Allows the connection of an external capacitor for delaying the overload protection, which is triggered by a voltage on the COMP pin higher than 4.4V.
Allows the setting of the switching frequency through an external Rt-Ct network.
DocRev1 7/31
Rectangular U-I Output characteristics
4
VIPer53EDIP - E / VIPer53ESP - E
Rectangular U-I Output characteristics
Figure 3.
Off Line Power Supply With Optocoupler Feedback
AC IN
F1
C1
R1
T1
D1
C2
C3
R2
D2
T2
D3
D4
C8
L1
C9 DC OUT
R4
C4
R3
OSC
COMP
VDD DRAIN
CONTROL
TOVL SOURCE
C5
C12
10nF
R5
C7
R9
1k
C6
U2
C10
R8
U3
C11
R7
R6
8/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E
5
Secondary Feedback Configuration Example
Secondary Feedback Configuration Example
The secondary feedback is implemented through an optocoupler driven by a programmable zener diode (TL431 type) as shown in
The optocoupler is connected in parallel with the compensation network on the COMP pin which delivers a constant biasing current of 0.6mA to the optotransistor. This current does not depend on the compensation voltage, and so it does not depend on the output load either. Consequently, the gain of the optocoupler ensures a constant biasing of the TL431 device (U3), which is responsible for secondary regulation. If the optocoupler gain is sufficiently low, no additional components are required to a minimum current biasing of U3.
Additionally, the low biasing current protects the optocoupler from premature failure.
The constant current biasing can be used to simplify the secondary circuit: instead of a
TL431, a simple zener and resistance network in series with the optocoupler diode can insure a good secondary regulation. Current flowing in this branch remains constant just as it does by using a TL431, so typical load regulation of 1% can be achieved from zero to full output current with this simple configuration.
Since the dynamic characteristics of the converter are set on the secondary side through components associated to U3, the compensation network has only a role of gain stabilization for the optocoupler, and its value can be freely chosen. R5 can be set to a fixed value of 2.2k
Ω , offering the possibility of using C7 as a soft start capacitor: When starting up the converter, the VIPer53E device delivers a constant current of 0.6mA on the COMP pin, creating a constant voltage of 1.3V in R5 and a rising slope across C7. This voltage shape, together with the operating range of 0.5V to 4.5V provides a soft startup of the converter.
The rising speed of the output voltage can be set through the value of C7. The C4 and C6 values must be adjusted accordingly in order to ensure a correct startup.
DocRev1 9/31
Current Mode Topology VIPer53EDIP - E / VIPer53ESP - E
The VIPer53E implements the conventional current mode control method for regulating the output voltage. This kind of feedback includes two nested regulation loops:
The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage. When V S reaches V
COMP
, the power switch is turned off. This structure is completely integrated as shown on the Block
Diagram of
, with the current amplifier, the PWM comparator, the blanking time function and the PWM latch. The following formula gives the peak current in the Power
MOSFET according to the compensation voltage:
I
Dpe ak
=
V – V
--------------------------------------------------
H
COM P
The outer loop defines the level at which the inner loop regulates peak current in the power switch. For this purpose, V
COMP
is driven by the feedback network (TL431 through an
optocoupler in secondary feedback configuration, see Figure 3 on page 8 ) and is sets
accordingly the peak drain current for each switching cycle.
As the inner loop regulates the peak primary current in the primary side of the transformer, all input voltage changes are compensated for before impacting the output voltage. This results in an improved line regulation, instantaneous correction to line changes, and better stability for the voltage regulation loop.
Current mode topology also provides a good converter start-up control. The compensation voltage can be controlled to increase slowly during the start-up phase, so the peak primary current will follow this soft voltage slope to provide a smooth output voltage rise, without any overshoot. The simpler voltage mode structure which only controls the duty cycle, leads generally to high current at start-up with the risk of transformer saturation.
An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side transformer capacitance or secondary side rectifier reverse recovery time when working in continuous mode.
10/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Standby Mode
The device offers a special feature to address the low load condition. The corresponding function described hereafter consists of reducing the switching frequency by going into burst mode, with the following benefits:
– It reduces the switching losses, thus providing low consumption on the mains lines.
The device is compliant with “Blue Angel” and other similar standards, requiring less than 0.5 W of input power when in standby.
– It allows the regulation of the output voltage, even if the load corresponds to a duty cycle that the device is not able to generate because of the internal blanking time, and associated minimum turn on.
For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM latch and the Power MOSFET in the Off state as long as V
COMP
remains below 0.5V (See
Block Diagram on page 2). If the output load requires a duty cycle below the one defined by the minimum turn on of the device, the V
COMP
net decreases its voltage until it reaches this
0.5V threshold (V
COMPoff
). The Power MOSFET can be completely Off for some cycles, and resumes normal operation as soon as V
COMP
is higher than 0.5V. The output voltage is regulated in burst mode. The corresponding ripple is not higher than the nominal one at full load.
In addition, the minimum turn on time which defines the frontier between normal operation and burst mode changes according to V
COMP value. Below 1.0V (V
COMPbl
), the blanking time increases to 400ns, whereas for higher voltages, it is 150ns
minimum turn on times resulting from these values are respectively 600 ns and 350 ns, when taking into account internal propagation time. This brutal change induces an hysteresis between normal operation and burst mode as shown on
When the output power decreases, the system reaches point 2 where V
COMP
equals
V
COMPbl
. The minimum turn-on time passes immediately from 350ns to 600ns, exceeding the effective turn-on time that should be needed at this output power level. Therefore the regulation loop will quickly drive V
COMP
to V
COMPoff
(Point 3) in order to pass into burst mode and to control the output voltage. The corresponding hysteresis can be seen on the switching frequency which passes from F
SWnom
which is the normal switching frequency set by the components connected to the OSC pin and to FSWstby. Note: This frequency is actually an equivalent number of switching pulses per second, rather than a fixed switching frequency since the device is working in burst mode.
As long as the power remains below P
RST
the output of the regulation loop remains stuck at
V
COMPsd
and the converter works in burst mode. Its “density” increases (i.e. the number of missing cycles decreases) as the power approaches P
RST
and finally resumes normal operation at point 1. The hysteresis cannot be seen on the switching frequency, but it can be seen in the sudden surge of the COMP pin voltage from point 3 to point 1 at that power level.
The power points value P
RST
and P
STBY
are defined by the following formulas:
P
R ST
=
1
---
2
•
F
SWnom
• ( tb
1
+ td
)
2
•
V
2
IN
•
1
-------
Lp
P
STBY
=
1
---
2
•
F
SWn om
•
Ip
2
(
V
COM Pb l
) •
Lp
DocRev1 11/31
Standby Mode VIPer53EDIP - E / VIPer53ESP - E
Where Ip(V
COMPbl2
) is the peak Power MOSFET current corresponding to a compensation voltage of V
COMPbl
(1V). Note: The power point PSTBY where the converter is going into burst mode does not depend on the input voltage.
The standby frequency F
SWstby
is given by:
P
SWstb y
=
P
-----------------
P
RST
•
F
SWn om
The ratio between the nominal and standby switching frequencies can be as high as 4, depending on the Lp value and input voltage.
Figure 4.
.Standby Mode Implementation ton
3
600ns
Minimum turn on
350ns
2
1
V
COMP
V
COMPsd
V
COMPoff
V
COMPbl
P
IN
P
RST
1
3
P
STBY
2
F
SW
F
SWstby
F
SWnom
12/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E
8
High Voltage Start-up Current Source
High Voltage Start-up Current Source
An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits in standby mode with reduced consumption, and also supplies the external capacitor connected to the
V
DD
pin. As soon as the voltage on this pin reaches the high voltage threshold V
DDon
of the
UVLO logic, the device turns into active mode and starts switching. The start-up current generator is switched off, and the converter should normally provide the needed current on the V
DD
pin through the auxiliary winding of the transformer, as shown on
The external capacitor C
VDD
on the V
DD
pin must be sized according to the time needed by the converter to start-up, when the device starts switching. This time tss depends on many parameters, including transformer design, output capacitors, soft start feature, and compensation network implemented on the COMP pin and possible secondary feedback circuit. The following formula can be used for defining the minimum capacitor needed:
C
VD D
>
I
D D1
V
⋅ tss
------------------------
DDh yst
Figure 9 on page 22 shows a typical start-up event. V
current I
DDch1
at about 9 mA. When about V
DDoff
DD
starts from 0V with a charging
is reached, the charging current is reduced down to I
DDch2
which is about 0.6mA. This lower current leads to a slope change on the V
DD rise. Device starts switching for V
DD
equal to V
DDon
, and the auxiliary winding delivers some energy to V
DD
capacitor after the start-up time tss.
The charging current change at V
DDoff
allows a fast complete start-up time t
SDU
, and maintains a low restart duty cycle. This is especially useful for short circuits and overloads conditions, as described in the following section.
DocRev1 13/31
High Voltage Start-up Current Source
Figure 5.
Start-up Waveforms
I
DD
I
DD1
I
DDch2
I
DDch1
V
DD
V
DDreg
V
DDst
V
DDsd tSU tSS
VIPer53EDIP - E / VIPer53ESP - E t t
14/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E
9
Short-Circuit and Overload Protection
Short-Circuit and Overload Protection
A V
COMPovl
threshold of about 4.4V has been implemented on the COMP pin. When V
COMP goes above this level, the capacitor connected on the TOVL pin begins to charge. When reaching typically V
OVLth
(4V), the internal MOSFET driver is disabled and the device stops switching. This state is latched because of to the regulation loop which maintains the COMP pin voltage above the V
COMPovl threshold. Since the V
DD
pin does not receive any more energy from the auxiliary winding, its voltage drops down until it reaches V
DD off and the device is reset, recharging the V
DD
capacitor for a new restart cycle. Note: If VCOMP drops below the VCOMPovl threshold for any reason during the VDD drop, the device resumes switching immediately.
The device enters an endless restart sequence if the overload or short circuit condition is maintained. The restart duty cycle D
RST
is defined as the time ratio for which the device tries to restart, thus delivering its full power capability to the output. In order to keep the whole converter in a safe state during this event, D
RST
must be kept as low as possible, without compromising the real start-up of the converter. A typical value of about 10% is generally sufficient. For this purpose, both V
DD
and TOVL capacitors can be used to satisfy the following conditions:
C
OVL
> ⋅ – 6 ⋅ tss
C
VDD
> ⋅ 4 ⋅
⎛
⎝
1
-------------– 1
D
RST
⎞
⎠
⋅
C
------------------------------------
V
⋅
I
D Dch2
DDh yst
Refer to the previous start-up section for the definition of tss, and C
VDD
must also be checked against the limit given in this section. The maximum value of the two calculus will be adopted.
All this behavior can be observed on Figure 2 on page 7 . In
the value of the drain current Id for V
COMP
= V
COMPovl
is shown. The corresponding parameter I
Dmax
is the drain current to take into account for design purposes. Since I
Dmax
represents the maximum value for which the overload protection is not triggered, it defines the power capability of the power supply.
DocRev1 15/31
Regulation Loop Stability VIPer53EDIP - E / VIPer53ESP - E
16/31
The complete converter open loop transfer function can be built from both power cell and the feedback network transfer functions. A theoretical example can be seen in
Figure 11 on page 22 for a discontinuous mode flyback loaded by a simple resistor.
A typical schematic corresponding to this situation can be seen on
transfer function of the power cell is represented as G(s) in .
It exhibits a pole which depends on the output load and on the output capacitor value. As the load of a converter may change, two curves are shown for two different values of output resistance value, R
L1
and R
L2
. A zero at higher frequency values then appears, due to the output capacitor ESR. Note: The overall transfer function does not depend on the input voltage because of the current mode control. A typical regulation loop is shown on
and has a fixed behavior represented by F(s) on Figure 11 on page 22
. A double zero due to the R
1
-C
1
network on the COMP pin and to the integrator built around the TL431 and R
2
-C
2
is set at the same value as the maximum load R
L2
pole.
The total transfer function is shown as F(s). G(s) at the bottom of
. For maximum load (plain line), the load pole begins exactly where the zeros of the COMP pin and the TL431 stop, and this results in a first order decreasing slope until it reaches the zero of the output capacitor ESR. The point where the complete transfer function has a unity gain is known as the regulation bandwidth and has a double interest:
– The higher it is, the faster the reaction will be to an eventual load change, and the smaller the output voltage change will be.
– The phase shift in the complete system at this point has to be less than 135° to ensure good stability. Generally, a first-order slope gives 90° of phase shift, and a second-order gives 180°.
, the unity gain is reached in a first order slope, so the stability is ensured.
The dynamic load regulation is improved by increasing the regulation bandwidth, but some limitations have to be respected:
1. As the transfer function above zero due the ESR capacitor is not reliable (the ESR itself is not well specified, and other parasitic effects may take place), the bandwidth should always be lower than the minimum of FC and ESR zero
2. As the highest bandwidth is obtained with the highest output power (plain line with RL2
, the above criteria will be checked for this condition and allows the value of R4 if R1 is set to a fixed value (e.g., (2.2k
Ω ).
As the highest bandwidth is obtained with the highest output power (Plain line with R
L2
load in
Figure 3 ), the above criteria will be checked for this condition and allows to define the
value of R
4
, if R1 is set fixed (2.2k
Ω , for instance). The following formula can be derived:
R
4
=
P
MA X
---------------------
P
O UT2
⋅
F
BW 2
G
⋅
O
R
⋅ R
L2
⋅
1
C
OUT with: P
O UT2
=
V
2
OUT
-----------------
R
L2 and:
P
MA X
=
1
2
⋅ L
P
⋅
2
I
LIM
⋅ F
SW
Go is the current transfer ratio of the optocoupler.
DocRev1
VIPer53EDIP - E / VIPer53ESP - E Regulation Loop Stability
The lowest load gives another condition for stability: The frequency F
BW1
must not encounter the third order slope generated by the load pole, the R1-C1 network on the
COMP pin and the R2-C2 network at the level of the TL431 on secondary side. This condition can be met by adjusting both C
1
and C2 values:
C
1
>
R
L 1
6.3
⋅
⋅ C
OUT
G
O
R
4
⋅
2
--------R
1
⋅
P
---------------------
P
MAX
R
C
2
>
6.3
⋅
L 1
G
R
⋅
O
4
C
⋅
OUT
R
1
⋅
R
2
⋅
P
---------------------
P
MAX with: P
OUT1
=
V
2
OUT
R
L1
The above formula gives a minimum value for C1. It can be then increased to provide a natural soft start function as this capacitor is charged by the current I
COMP
at start-up.
DocRev1 17/31
Special Recommendations VIPer53EDIP - E / VIPer53ESP - E
Note:
10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to ensure correct stability of the internal current source
.
In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1k Ω should be inserted in series with the TOVL pin, as shown on
This resistance does not impact the overload delay, as its value is negligible prior to the internal pull-up resistance (about 125k
Ω
).
18/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Software Implementation
All the above considerations and some others are included included in ST design software which provides all of the needed components around the VIPer device for specified output configurations, and is available on www.st.com.
DocRev1 19/31
Operation pictures VIPer53EDIP - E / VIPer53ESP - E
Figure 6.
Rise and Fall time
I
D
C<<C
OSS
C L D t
V
DS
90% t fv t rv
10%
Figure 7.
Overloaded Event
V
DD
Normal operation
V
DDon
V
DDoff t
VDD DRAIN
OSC
CONTROL
COMP TOVL SOURCE
Abnormal operation
V
COMP
V
DIFFovl
300V
20/31
V
TOVL
V
OVLth t
OVL
V
DS
Not switching
Switching
DocRev1
VIPer53EDIP - E / VIPer53ESP - E
Figure 8.
Complete Converter Transfer Function
π ⋅ R
L1
1
⋅ C
O UT
3.2
⋅
P
M AX
---------------------
P
O U T1
3.2
⋅
P
M A X
---------------------
P
O UT2
π ⋅ R
L 2
1
⋅ C
O UT
1
2 π
1
ESR C
O UT
Operation pictures
F S
G
O
⋅
R
R
1
-------
4
1
F S . G S
2 π R
1
CO M P
⋅ C
CO M P F
C
1
F
BW
1
F BW 2
DocRev1 21/31
Operation pictures VIPer53EDIP - E / VIPer53ESP - E
Figure 9.
Start-up V
DD current
I
DD
I
DD0
V
DDhyst
V
DDoff
V
DDon
I
DDch2
V
DS
= 100 V
F
SW
= 0 kHz
I
DDch1
V
DD
Figure 10. Blanking Time t b t b1 t b2
V
COMPbl
V
COMPhi
V
COMP
Figure 11. Thermal Shutdown
T j
T
SD
T
SD
-T
HYST
V
DD
V
DDon
Automatic startup
Figure 12. Overvoltage Event
V
DD
V
DDovp
V
COMP
Abnormal operation
V
COMP
V
DS
Not switching
Switching
22/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E
Figure 13. Shutdown Action
V
OSC
V
OSChi
V
OSClo
V
COMP
V
COMPoff
I
D
Figure 15. Oscillator Schematic
Vcc
VDD
Rt
Ct
OSC
320
Ω
SOURCE
Operation pictures
Figure 14. Comp Pin Gain and Offset t t t
I
Dpeak
I
Dlim
I
Dmax
Slope = 1 / H
COMP
V
COMPos
V
COMP
V
COMPovl
V
COMPhi
PWM section
DocRev1 23/31
Operation pictures VIPer53EDIP - E / VIPer53ESP - E
The switching frequency settings shown on the graphic here below is valid within the following boundaries:
R t
> 2k Ω
F
SW
= 300kHz
Figure 16. Oscillator Settings
Frequency (kHz)
300
2.2nF
4.7nF
1nF
100
10nF
22nF
10
1 10
R
T
(K
Ω
)
100
Figure 17. Typical Frequency Variation vs. Junction Temperature
Normalised Frequency
1.04
1.02
0.98
1
0.96
-20 0 20 40 60 80
Temperature (°C)
100 120
24/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E
Figure 18. Typical Current Limitation vs. Junction Temperature
Normalised IDlim
Operation pictures
1.04
1.02
0.98
1
0.96
-20 0 20 40 60 80
Temperature (°C)
100 120
DocRev1 25/31
Mechanical Data VIPer53EDIP - E / VIPer53ESP - E
In order to meet environmental requirements, ST offers these devices in ECOPACK
® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
.
26/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E
Table 11.
DIP8 Mechanical Data
Ref.
Nom.
Dimensions
Databook (mm)
Min b2 c
D
E
A
A1
A2 b
E1 e eA eB
L
Package Weight
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
2.92
3.30
Gr. 470
9.27
7.87
6.35
2.54
7.62
3.30
0.46
1.52
0.25
Figure 19. Package Dimensions
Mechanical Data
Max
5.33
4.95
0.56
1.78
0.36
10.16
8.26
7.11
10.92
3.81
DocRev1 27/31
Mechanical Data VIPer53EDIP - E / VIPer53ESP - E
Table 12.
PowerSO-10 Mechanical Data
Dimensions
Databook (mm)
Ref.
Nom.
Min Max
A 3.35
A1 0.00
B 0.40 c 0.35
D 9.40
D1 7.40
E 9.30
E1 7.20
3.65
0.10
0.60
0.55
9.60
7.60
9.50
7.40
E2 7.20
E3 6.10
7.60
6.35
E4 5.90 6.10 e 1.27
F 1.25
H 13.80
1.35
14.40 h 0.50
L 1.20 1.80 q 1.70
α
0° 8°
Figure 20. Package Dimensions
28/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E
Table 13.
Order codes
Part Number
VIPer53ESPTR - E
VIPer53ESP - E
VIPer53EDIP - E
Package
PowerSO-10
PowerSO-10
DIP-8
Order codes
Shipment
Tape and reel
Tube
Tube
DocRev1 29/31
Revision history VIPer53EDIP - E / VIPer53ESP - E
Table 14.
Document revision history
Date Revision
12-Jan-2006 1 Initial release.
Changes
30/31 DocRev1
VIPer53EDIP - E / VIPer53ESP - E Revision history
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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DocRev1 31/31
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