STMicroelectronics VIPER26K Datasheet
Advertentie
Advertentie
VIPER26K
1050 V high voltage converter for ultra-wide input
Features
1050 V avalanche-rugged power MOSFET
allowing ultra-wide VAC input range to be covered
Embedded HV startup and sense-FET
Current mode PWM controller
Drain current limit protection:
-500 mA (VIPER265K)
-700 mA (VIPER267K)
Jittered switching frequency reduces the EMI filter cost: 60 kHz ± 4kHz
Standby power < 30 mW at 230 VAC
Embedded E/A with 3.3 V reference
Safe auto-restart after a fault condition
Hysteretic thermal shutdown
Built-in soft-start for improved system reliability
Applications
SMPS for energy metering
Auxiliary power supplies for 3-phase input industrial systems
LED lighting
Air conditioning
Datasheet - production data
Description
The device is a high voltage converter smartly integrating a 1050 V avalanche-rugged power section, with a PWM current mode control. The
1050 V-BV power MOSFET allows to extend input voltage range, and reduce the size of the DRAIN snubber circuit. This IC meets the most stringent energy-saving standards as it has very low consumption and operates in burst mode under light load.
The integrated HV startup, sense-FET, error amplifier and oscillator with jitter allow a complete application to be designed with the minimum number of components.
The VIPer26K supports the most common SMPS topologies such as: isolated flyback with optocoupler, primary-side regulation, non-isolated flyback with resistive feedback, buck, and buck boost.
May 2019
This is information on a product in full production.
DS12978 Rev 1 1/28 www.st.com
Figure 1. Basic application schematic
VIPER26K
2/28 DS12978 Rev 1
7
3
VIPer26K
Contents
4
Contents
Electrical and thermal ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FB pin and COMP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Automatic auto restart after overload or short-circuit . . . . . . . . . . . . . . . . 18
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Layout guidelines and design recommendations . . . . . . . . . . . . . . . . . . . 22
SO16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DS12978 Rev 1 3/28
28
Pin setting
1 Pin setting
Figure 2. Connection diagram
VIPER26K
4/28
SO16
N
1
2, 3
4
5
6
7
8
9-12
Name
GND
N.C
N.A.
VDD
N.C.
FB
COMP
N.C.
13-16 DRAIN
Table 1. Pin description
Function
Ground.
Connected to the source of the internal power MOSFET and controller ground reference.
Not internally connected.
It can be connected to GND (pin 1) or left floating.
Not available for user.
This pin is mechanically connected to the controller die pad of the frame. It is highly recommended to connect it to GND (pin 1).
Supply voltage of the control section.
This pin provides the charging current of the external capacitor.
Not available for user.
It is highly recommended to connect it to GND (pin
1).
Inverting input of the internal trans-conductance error amplifier.
Connecting the converter output to this pin through a single resistor results in an output voltage equal to the error amplifier reference voltage. An external resistors divider is required for higher output voltages.
Output of the internal trans conductance error amplifier.
The compensation network has to be placed between this pin and GND to achieve stability and good dynamic performance of the voltage control loop.
The pin is used also to directly control the PWM with an optocoupler. The linear voltage range extends from V
COMPL
to V
COMPH
.
Not internally connected.
It has to be left floating.
High voltage drain pin.
The built-in high voltage switched start-up bias current is drawn from this pin too. Pins connected to the metal frame to facilitate heat dissipation.
DS12978 Rev 1
VIPer26K
2 Electrical and thermal ratings
Electrical and thermal ratings
Table 2. Absolute maximum ratings
Parameter
(1)
,
(2)
Value
Symbol
V
DRAIN
Pin
13-16 Drain-to-source (ground) voltage
Min. Max.
1.05
I
DRAIN
Pulse drain current (limited by
T
J
= 150 °C)
3
V
DD
5 Supply voltage -0.3
Internally limited
I
DD
V
FB
V
COMP
P
TOT
5
7
8
Input current
Feedback pin voltage
Input pin voltage
-0.3
-0.3
20
4.8
3.5
Power dissipation at T
A
< 60 °C 1.05
(3)
T
J
Operating junction temperature range -40 150
T
STG
Storage temperature -55 150
1. Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device.
2. Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability.
3. When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 μm thick).
Unit
KV
A
V mA
V
V
W
°C
°C
Symbol
Table 3. Thermal data
Parameter
R
R
TH-JC
TH-JC
Thermal resistance junction to case (1)
(Dissipated power = 1 W)
Thermal resistance junction to case (2)
(Dissipated power = 1 W)
R
TH-JA
Thermal resistance junction ambient (1)
(Dissipated power = 1 W)
R
TH-JA
Thermal resistance junction ambient
(2)
(Dissipated power = 1 W)
1. When mounted on a standard, single side FR4 board with minimum copper area.
2. When mounted on a standard, single side FR4 board with 100 mm2 of Cu (35 μm thick).
Max. value
10
5
120
85
Unit
°C/W
°C/W
°C/W
°C/W
DS12978 Rev 1 5/28
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Electrical and thermal ratings
Figure 3. R thJA
VIPER26K
Symbol
I
AR
E
AV
Pin
Table 4. Avalanche characteristics
Parameter
Repetitive avalanche current (limited by T
J
= 150 °C)
Repetitive avalanche energy (limited by T
J
= 150 °C)
Min.
Value
Max.
1
3
Unit
A mJ
6/28 DS12978 Rev 1
VIPer26K
3 Electrical characteristics
Electrical characteristics
( T
J
= -40 to 125°C, VDD = 14V; unless otherwise specified.)
Symbol
V
I
BVDSS
DSS
Breakdown voltage
Drain-source leakage current
Parameter
R
DS(on)
Drain-Source ON state resistance
Table 5. Power section
Test conditions
I
D
= 1 mA,
V
COMP
= GND,
T
J
= 25°C
V
DRAIN
= 1050V,
V
COMP
= GND,
T
J
= 25°C
I
DRAIN
= 0.2 A;
T
J
= 25 °C
I
DRAIN
= 0.2 A;
T
J
= 125 °C
Min.
1.05
Typ.
Max.
29
7
14
Unit.
kV
μA
Symbol Parameter
High voltage start-up current source
Table 6. Supply section
Test conditions
V
VDSS_SU
Startup breakdown drainsource voltage
I
D
= 1 mA,
V
COMP
= GND,
T
J
= 25°C
V
HV_START
Drain-source start voltage
I
DDch1
I
DDch2
Charging current during startup
Charging current in selfsupply
V
DRAIN
= 50 V to
1.05 kV,
V
DD
= 4 V
V
DRAIN
= 50 V to
1.05 kV,
V
DD
= 9 V falling edge
IC supply and consumptions
V
DD
V
DDclamp
V
DDon
Operating voltage range
V
DD
clamp voltage
V
DD
start up threshold
I
DD
= 15 mA
Min.
1.05
38
-0.6
-7
11.5
23.5
12
Typ.
Max.
Unit
13 kV
60
-1.8
V mA
-13
23.5
14 mA
V
V
V
DS12978 Rev 1 7/28
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Electrical characteristics
Symbol
V
DDCSon
V
DDoff
I
DD0
I
DD1
I
DDoff
I
DDol
Table 6. Supply section (continued)
Parameter Test conditions Min.
V
DDon
internal high voltage current generator threshold
V
DD
under voltage shutdown threshold
Operating supply current, not switching
Operating supply current, switching
F
OSC
= 0 kHz,
V
COMP
= GND
V
DRAIN
= 120 V,
F
OSC
= 60 kHz
Operating supply current with VDD < VDDoff
V
DD
< V
DDoff
Open loop failure current threshold
V
DD
= V
DDclamp
V
COMP
= 3.3 V
9.5
7
4
VIPER26K
Typ.
10.5
Max.
11.5
Unit
V
8 9 V
0.6
2 mA mA
0.35
mA mA
Symbol Parameter
E/A
V
REF_FB
I
FB_PULL UP
Input voltage
Pull-up current
G
M
R
COMP(DYN)
Transconductance
Compensation pin (Comp)
V
COMPH
Upper saturation limit
V
COMPL
V
HYS
H
COMP
Burst mode threshold
Burst mode hysteresis
ΔVCOMP/ΔIDRAIN
Dynamic resistance
Source / sink Current
I
COMP
Max. source current
Table 7. Controller section
Test conditions
T
J
= 25°C
T
J
= 25°C
T
J
= 25°C
V
FB
= GND
V
FB
> 100mV
V
COMP
= GND,
V
FB
= GND
Min.
3.2
1
1.9
Typ.
3
1.1
40
2.35
15
150
220
3.3
-1
2
Max.
Unit
3.4
1.2
2.8
V
μA mA/V
V
V mV
V/A kΩ
μA
μA
8/28 DS12978 Rev 1
VIPer26K
Symbol
Current limitation
Table 7. Controller section (continued)
Parameter Test conditions
I
DLIM
Drain current limitation
VIPER267K
V
COMP
= 3.3V,
T
J
= 25°C
VIPER265K
V
COMP
= 3.3V,
T
J
= 25°C t
SS
T
ON-MIN
I
DLIM-BM
Overload t
OVL t
RESTART
Oscillator
Soft-start time
Minimum turn ON time
Burst mode current limitation
Overload time
Restart time after fault
V
COMP
= V
COMPL
F
OSC
Switching frequency
F
D
F
M
Modulation depth
Modulating frequency
D
MAX
Maximum duty cycle
Thermal shutdown
T
SD
T
HYST
Thermal shutdown temperature
Thermal shutdown hysteresis
T
J
= -25 to 125°C
T
J
= -40 to 125°C
Min.
0.66
0.47
54
44
70
150
Electrical characteristics
Typ.
0.7
0.5
8.5
127
50
1
60
60
±4
240
160
30
Max.
0.74
0.53
480
66
66
80
Unit
A kHz kHz
Hz
% ms ns mA ms s
°C
°C
DS12978 Rev 1 9/28
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Electrical characteristics
3.1 Typical electrical characteristics
Figure 4. I
DLIM vs. T j
Figure 5. F
OSC
vs. T j
VIPER26K
10/28
Figure 6. V
HV_START
vs. T j
Figure 7. V
REF_FB
vs. T j
Figure 8. I
DD0 vs. T j
Figure 9. I
DD1
vs. T j
DS12978 Rev 1
VIPer26K
Figure 10. G
M
vs. T j
Electrical characteristics
Figure 11. H
COMP
vs. T j
Figure 12. I
COMP(source/sink)
vs. T j
Figure 13. I
COMP(max source)
vs. T j
Figure 14. Power MOSFET capacitances variation vs. V
DS
@ V
GS
=0, f=1MHz
Figure 15. V
BVDSS
vs. T
J
....................................................
DS12978 Rev 1 11/28
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Electrical characteristics
Figure 16. R
DS(on)
vs. T j
VIPER26K
Figure 17. Maximum avalanche energy vs. T j
Figure 18. SOA SSOP10 package
12/28 DS12978 Rev 1
VIPer26K
4 General description
4.1 Block diagram
Figure 19. Block diagram
General description
4.2 Typical power capability
Vin: 230 Vac
Adapter
(1)
Open frame
(2)
Table 8. Typical power
Vin: 85-265Vac
Vin: 85-440Vac
Adapter
16W 20W 10W 12W 10W
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heatsinking.
12W
4.3 Primary MOSFET
The power section is implemented with an N-channel power MOSFET with a breakdown voltage of 1050 V min. and a maximum R
DS(ON)
of 7 Ω. It includes a sense-FET structure to allow a virtually lossless current sensing and the thermal sensor.
The gate driver of the power MOSFET is designed to supply a controlled gate current during both turn-ON and turn-OFF in order to minimize common mode EMI. During UVLO conditions, an internal pull-down circuit holds the gate low in order to ensure that the power
MOSFET cannot be turned ON accidentally.
DS12978 Rev 1 13/28
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General description
4.4 High voltage startup
VIPER26K
The high voltage current generator is supplied by the DRAIN pin. At the first startup of the converter, it is enabled when the voltage across the input bulk capacitor reaches the
V
DRAIN_START
threshold, sourcing the I
DDch1
current; as the V
DD
voltage reaches the V
DDon start-up threshold, the power section starts switching and the high voltage current generator is turned OFF. The VIPer26K is powered by the external source. After the startup, the auxiliary winding or the diode connected to the output voltage have to power the V
DD capacitor with voltage higher than the V
DDCSon
threshold. During the switching, the internal current source is disabled and the consumptions are minimized.
In case of fault, the switching is stopped and the device is self-biased by the internal high voltage current source; it is activated between the levels V
DDCSon current I
DDch2
and V
to the VDD capacitor during the MOSFET OFF time.
DDon
, delivering the
If a very low main input voltage is applied to the converter, it is strongly recommended to choose the V
DD
capacitor value by the following formula:
Equation 1
C
VDD
=
I
V
DD
t
OVL
- V
DDoff
At converter power-down, the V
DD below the V
DDoff
threshold.
voltage drops and the converter activity stops as it falls
Figure 20. Timing diagram: normal power-up and power-down sequences
14/28 DS12978 Rev 1
VIPer26K
4.5
General description
Oscillator
The switching frequency is internally fixed at 60 kHz.
The switching frequency is modulated by approximately ±4 kHz at 230 Hz (typical) rate, so that the resulting spread spectrum action distributes the energy of each harmonic of the switching frequency over a number of sideband harmonics having the same energy on the whole but smaller amplitudes.
4.6 Soft-start
During the converters' start-up phase, the soft-start function progressively increases the cycle-by-cycle drain current limit, up to the default value I
DLIM
. In this way, the drain current is further limited and the output voltage is progressively increased reducing the stress on the secondary diode. The soft-start time is internally fixed to t
SS any attempt of converter startup and after a fault event.
, and the function is activated for
This function helps prevent transformer saturation during startup and short-circuit.
4.7
4.8
Current limit set point
The VIPer26K includes a current mode PWM controller: cycle by cycle the drain current is sensed through the integrated resistor R
SENSE
and the voltage is applied to the noninverting input of the PWM comparator. As soon as the sensed voltage is equal to the voltage derived from the COMP pin, the power MOSFET is switched OFF.
In parallel with the PWM operations, the comparator OCP checks the level of the drain current and switches OFF the power MOSFET in case the current is higher than the threshold I
Dlim
.
The IC is available with two different drain current limitations: the VIPer267K has a 700 mA
(typical value), whereas the VIPer265K is available with 500 mA current limitation.
Both values are ensured with tolerance reported in Table 3 .
FB pin and COMP pin
The device can be used both in non-isolated and in isolated topology. In the case of nonisolated topology, the feedback signal from the output voltage is applied directly to the FB pin as inverting input of the internal error amplifier having the reference voltage, V
REF_FB
.
The output of the error amplifier sources and sinks the current, I
COMP
, respectively to and from the compensation network connected on the COMP pin. This signal is then compared, in the PWM comparator, with the signal coming from the sense-FET; the power MOSFET is switched off when the two values are the same on a cycle-by-cycle basis.
When the power supply output voltage is equal to the error amplifier reference voltage,
V
REF_FB
, a single resistor has to be connected from the output to the FB pin. For higher output voltages the external resistor divider is needed. If the voltage on the FB pin is accidentally left floating, an internal pull-up protects the controller.
The output of the error amplifier is externally accessible through the COMP pin and it's used for the loop compensation: usually an RC network.
DS12978 Rev 1 15/28
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General description VIPER26K
In the case of isolated power supply, the internal error amplifier has to be disabled (FB pin shorted to GND). In this case an internal resistor is connected between an internal reference voltage and the COMP pin.
The current loop has to be closed on the COMP pin through the optocoupler in parallel with the compensation network. The V
COMP
dynamics range is between V
COMPL
and V
COMPH
.
When the voltage V
COMP burst mode.
drops below the voltage threshold V
COMPL
, the converter enters
When the voltage V
COMP
rises above the V
COMPH
threshold, the peak drain current will reach its limit, as well as the deliverable output power.
Figure 21. Feedback circuit
Figure 22. COMP pin vs. I
DLIM
16/28 DS12978 Rev 1
VIPer26K
4.9
General description
Burst mode
When the voltage V
COMP delivery stop, the V
COMP
+ V
COMPL_HYS
drops below the threshold, V
COMPL the OFF state and the consumption is reduced to I
DD0
, the power MOSFET is kept in
current. As a reaction at the energy
voltage increases and as soon as it exceeds the threshold V
COMPL
, the converter starts switching again with consumption level equal to I
DD1
current. This ON-OFF operation mode, referred to as “burst mode” and reported in Figure 4 ,
reduces the average frequency, which can go down even to a few hundred hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulations. During burst mode, the drain current limit is reduced to the value I
DLIM_bm order to avoid the audible noise issue.
in
Figure 23. Load-dependent operating modes: timing diagram
4.10 Automatic auto restart after overload or short-circuit
The overload protection is implemented in an automatic way using the integrated up-down counter. Every cycle, it is incremented or decremented depending on whether the current logic detects the limit condition or not. The limit condition is the peak drain current, I
DLIM
.
After the reset of the counter, if the peak drain current is continuously equal to the level I
Dlim the counter will be incremented till the fixed time, t
OVL
ON is disabled. It is activated again, through the soft-start, after the t
RESTART
time.
,
, after that the power MOSFET switch
In the case of overload or a short-circuit event, the power MOSFET switching is stopped after a time that depends from the counter and that can be as maximum equal to t
OVL protection occurs in the same way until the overload condition is removed.
. The
This protection ensures restart attempts of the converter with low repetition rate, so that it works safely with extremely low power throughput and avoiding the IC overheating in case of repeated overload events.
If the overload is removed before the protection tripping, the counter is decremented cycle- by-cycle down to zero and the IC is not stopped.
DS12978 Rev 1 17/28
28
General description
Figure 24. Timing diagram: OLP sequence
VIPER26K
4.11 Open loop failure protection
In case the power supply is built in flyback topology and the VIPer26K is supplied by an auxiliary winding, the converter is protected against feedback loop failure or accidental disconnections of the winding.
If R
H
is opened or R
L
is shorted, the VIPer26K works at its drain current limitation. The output voltage, V
OUT
, increases and also the auxiliary voltage, V the output through the secondary-to-auxiliary turns ratio.
AUX
, which is coupled with
As the auxiliary voltage increases up to the internal V
DD clamp current injected on the V internally generated.
DD
active clamp, V
DDclamp
and the
pin exceeds the latch threshold, I
DDol
, a fault signal is
In order to distinguish an actual malfunction from a bad auxiliary winding design, both the above conditions (drain current equal to the drain current limitation and current higher than
I
DDol
through V
DD
clamp) have to be verified to reveal the fault.
If R
L
is opened or R
H voltage V
REF_FB
is shorted, the output voltage, V case of isolated flyback).
OUT
, is clamped to the reference
(in case of non-isolated flyback) or to the external TL voltage reference (in
4.12 Thermal shutdown
When the controller temperature exceeds the shutdown threshold, T
SD
, the device is shut down to prevent any dangerous overheating for the system and the VDD pin is continuously recycled between V
DDon
and V
DDoff to keep the controller alive.
Once the t
RESTART
time is elapsed, when temperature falls T the IC starts once it has reached again the V
DDon
.
HYST
below the OTP threshold,
The OTP timing diagram is shown in
.
18/28 DS12978 Rev 1
VIPer26K
9
''
9
''RQ
9
''RII
7
M
7
6'
7
6'
7
+<67
General description
Figure 25. Timing diagram: OLP sequence
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,&UHVWDUWVKHUH 273LVWULJJHUHGKHUH
273LVUHVHWKHUH
W
W
DS12978 Rev 1 19/28
28
Application information
5 Application information
VIPER26K
Figure 26. Typical isolated flyback configuration with secondary regulation
Figure 27. Typical isolated flyback configuration with primary regulation
20/28 DS12978 Rev 1
VIPer26K Application information
Figure 28. Typical non isolated flyback configuration
Figure 29. Ultra wide range Buck configuration
DS12978 Rev 1 21/28
28
Application information
5.1 Layout guidelines and design recommendations
VIPER26K
A proper printed circuit board layout ensures the correct operation of any switch-mode converter and this is also true for the VIPer. The main reasons to have a proper PCB layout are:
Provides clean signals to the IC, ensuring good immunity against external and switching noises.
Reduces the electromagnetic interferences, both radiated and conducted, to pass the
EMC tests more easily.
If the VIPer is used to design an SMPS, the following basic rules should be considered:
Separate signal from power tracks . Generally, traces carrying signal currents should run far from others carrying pulsed currents or with fast swinging voltages. Signal ground traces should be connected to the IC signal ground, GND, using a single “star point”, placed close to the IC. Power ground traces should be connected to the IC power ground,
GND. The compensation network should be connected to the COMP, maintaining the trace to GND as short as possible. In the case of two-layer PCB, it is good practice to route signal traces on one PCB side and power traces on the other side.
Filter sensitive pins . Some crucial points of the circuit need or may need filtering. A small high-frequency bypass capacitor to GND might be useful to get a clean bias voltage for the signal part of the IC and protect the IC itself during EFT/ESD tests. A low ESL ceramic capacitor (a few hundreds pF up to 0.1 μF) should be connected across VCC and GND, placed as close as possible to the IC. With flyback topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on the auxiliary return and then to the main GND using a single track.
Keep power loops as confined as possible . The area circumscribed by current loops where high pulsed current flow should be minimized to reduce its parasitic self-inductance and the radiated electromagnetic field. As a consequence, the electromagnetic interferences produced by the power supply during the switching are highly reduced. In a flyback converter the most critical loops are: the one including the input bulk capacitor, the power switch, the power transformer, the one including the snubber, the one including the secondary winding, the output rectifier and the output capacitor. In a buck converter the most critical loop is the one including the input bulk capacitor, the power switch, the power inductor, the output capacitor and the freewheeling diode.
Reduce line lengths . Any wire acts as an antenna. With the very short rise times exhibited by EFT pulses, any antenna can receive high voltage spikes. By reducing line lengths, the level of received radiated energy is reduced, and the resulting spikes from electrostatic discharges are lower. This also keeps both resistive and inductive effects to a minimum. In particular, all traces carrying high currents, especially if pulsed (tracks of the power loops) should be as short and wide as possible.
Optimize track routing . As levels of pickup from static discharges are likely greater near the edges of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon as possible where applicable. Since vias are to be considered inductive elements, it is recommended to minimize their number in the signal path and avoid them in the power path.
Improve thermal dissipation . An adequate copper area has to be provided under the
DRAIN pins as heatsink, while it is not recommended to place large copper areas on the
GND.
22/28 DS12978 Rev 1
VIPer26K Application information
Figure 30. Recommended routing for flyback converter
Figure 31. Recommended routing for Buck converter
DS12978 Rev 1 23/28
28
Package information
6 Package information
VIPER26K
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK® is an ST trademark.
6.1 SO16N package information
Figure 32. SO16N package outline
24/28 DS12978 Rev 1
VIPer26K
Dim.
c
D
E
E1
A
A1
A2 b
L k e h ccc
Table 9. SO16N mechanical data mm
Min.
Typ.
0.1
1.25
.31
0.17
9.8
5.8
3.8
0.25
0.4
0
9.9
6
3.9
1.27
Package information
Max.
1.75
0.25
0.51
0.25
10
6.2
4
0.5
1.27
8
1.1
DS12978 Rev 1 25/28
28
Order code
7 Order code
Order Code
VIPER265KDTR
VIPER267KDTR
Package
Table 10. Order codes
IDLIM
500 mA
SO16N
700 mA
Packaging
Tape & Reel
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8 Revision history
Date
23-Apr-2019
Table 11. Document history
Revision Changes
1 Initial release.
Revision history
DS12978 Rev 1 27/28
28
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