advertisement
5 4 3 2 1
D
C
NOTES:
1) UNLESS OTHERWISE SPECIFIED RESISTORS HAVE 5% TOLERANCE.
2) UNLESS OTHERWISE SPECIFIED CAPACITORS HAVE 20% TOLERANCE.
AMD Geode™ LX EPIC RDK Reference
Schematic
Page Index
------- ------------------------
1 COVER PAGE
8
9
6
7
4
5
2
3
10
11
12
13
REVISION HISTORY
BLOCK DIAGRAM
POWER ON & RESET SEQUENCE
PCI & JTAG BLOCK DIAGRAM
LX PROCESSOR DDR MEMORY
DDR SODIMM CONNECTOR
LX PROCESSOR VGA
LX PROCESSOR PCI / SYSTEM
LX PROCESSOR POWER
CS5536 PCI / SYSTEM / PM / FWH
CS5536 IDE / USB / AC97 / LPC
CS5536 POWER & CLOCK GENERATOR
Page Index
------- ------------------------
14 VGA CONNECTOR
19
20
21
22
15
16
17
18
23
24
25
26
ETHERNET - 10 / 100 MICREL KSZ8842
AUDIO CODEC REALTEK ALC655
SUPER IO ITE IT8712F & SPI BOOT FLASH
ETHERNET CONN / USB CONN & PWR / uDOC
MINI PCI
C
PCI TO ISA BRIDGE ITE IT8888G
IDE CONNECTOR
UART & FLOPPY CONNECTORS
PARALLEL PORT, KEYBOARD, & MOUSE
PC104 CONNECTORS
POWER SUPPLIES
TFT & LVDS CONNECTORS
B
D
B
A
IMPORTANT NOTICE:
1. THIS DOCUMENT MAY NOT REFLECT THE MOST RECENT CHANGES IN BOARD DEVELOPMENT
AND DEBUG. ANY DEVELOPER INTENDING TO USE THIS SCHEMATIC AS A REFERNCE SHOULD
CONTACT THEIR LOCAL FIELD APPLICATIONS ENGINEER, REGIONAL SALES OFFICE, OR
PROGRAM MANAGER FOR SCHEMATIC UPDATES, DESIGN RECOMMENDATIONS AND PCB LAYOUT
GUIDELINES. AMD ALSO RECOMMENDS A DESIGN REVIEW OF BOTH THE SCHEMATIC DIAGRAM
AND PCB LAYOUT BEFORE CONSIDERING PRODUCTION.
2. AMD RESERVES THE RIGHT TO CHANGE DESIGNS OR SPECIFICATIONS WITHOUT NOTICE.
CUSTOMERS ARE ADVISED TO OBTAIN THE LATEST VERSIONS OF PRODUCT SPECIFICATIONS,
WHICH SHOULD BE CONSIDERED IN EVALUATING A PRODUCT'S APPROPRIATENESS FOR A
PARTICULAR USE.
3. AMD MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, FOR MERCHANTABILITY OR FITNESS
FOR A PARTICULAR APPLICATION. IN NO EVENT SHALL AMD BE LIABLE FOR ANY INDIRECT,
SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES AS A RESULT OF THE PERFORMANCE,
OR FAILURE TO PEFORM, OF ANY AMD PRODUCT OR DOCUMENTATION.
© 2007 ADVANCED MICRO DEVICES, INC. ALL RIGHTS RESERVED. AMD, THE AMD ARROW LOGO,
AMD GEODE, AND COMBINATIONS THEREOF ARE TRADEMARKS OF ADVANCED MICRO DEVICES,
INC. OTHER NAMES USED IN THIS PUBLICATION ARE FOR IDENTIFICATION PURPOSES ONLY
AND MAY BE TRADEMARKS OF THEIR RESPECTIVE COMPANIES.
5 4
IMPORTANT NOTES ABOUT
THIS SCHEMATIC
DESIGN NOTE: Example text for the design note to show the note inside the colored box.
1) DESIGN NOTES in grey are information notes.
DESIGN NOTE: Example text for the design note to show the note inside the colored box.
DESIGN NOTE: Example text for the design note to show the note inside the colored box.
2) DESIGN NOTES in yellow are notes of caution.
3) DESIGN NOTES in red are critical, and must be understood and followed.
3 2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
1
of
26
1
A
B
A
5 4
C
D
REVISION HISTORY:
REV DATE NOTES
------- ------------------ ---------------------------------------------------------------------------------------
A
B
C
D
07-09-2006
12-04-2006
01-19-2007
04-10-2007
*
*
*
*
*
Initial Release
Page 8 - Changed LX symbol - DRGB6 pin from Y32 to AH8
Page 10 - Connected C102-C108 to Ground
Page 13 - Connected C133-C137 and C149-C152 to Ground
Page 13 - Added design note regarding USB VCORE supply.
3
5 4 3
2 1
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
2
of
26
1
A
B
D
C
1
A
D
C
5 4 3 2
CRT
MONITOR
LVDS
TFT
HD/CD
X2
HOST
X1 uDOC FLASH
STORAGE
CLIENT
X1
PRIMARY IDE ATA-100
USB2.0
AMD Geode™
LX Processor
MEMORY BUS
SODIMM200
DDR
PCI TO ISA
BRIDGE
FULL ISA
PCI BUS (33MHz)
10 / 100
ETHERNET
2 PORT
AMD Geode™
CS5536
Companion
Device
AC97
AUDIO CODEC
5.1 SUPPORT
B
14.318 MHz
Crystal
Clock
Synthesizer
(MK1491-09F)
PCI(33 MHz)
66 MHz
48 MHz
REFCLK
SIO
SPI
BIOS
FLASH
LEGACY
PARALLEL
SERIAL
KB/MS
5
VCC5
VCC5SB DC/DC
VCORE(1.25V)
VMEM (2.6V)
VCC3 (3.3V)
VCORESB (1.225V)
VCC3SB (3.3V)
4
BASEBOARD ONLY
3 2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
3
of
26
1
A
D
C
B
1
D
C
5
5VSB
WORKING
DC/DC
AOZ1012
EN
5V
WORK AUX
DC/DC
AOZ1012
EN
5V
WORK AUX
DC/DC
AOZ1012
EN
VMEM @ 2A Max
4
VCC3 @ 2A Max
VCORE @ 2A Max
3
AMD
Geode™ LX
Processor
DESIGN NOTE: This design uses
LVD to generate system reset.
Since LVD only monitors Vcore, the designer must guarantee that
Vio and other required voltages are valid at or before Vcore. If this cannot be guaranteed, then
RESET_WORK# must be used to hold system in reset until Vio and
Vcore and any other required voltages are valid.
AMD
Geode™
CS5536
LVD_EN#
PCIRST#
WORKING
PWRBTN#
2
5VSB
LINEAR
LM317
VCC3SB
B
A
VCC3SB
470
VCCMEM
10K
MVREF
10K
VCORESB
LM4041
5VSB
Power On and Reset Sequence - Cold start
3.3VSB
1.225VSB
PWRBTN# 5V WORKING
VCC3
VCORE
VMEM
LVD
SYS_RST#
PCIRST#
SYSTEM POWER
VCC=+5.0V
VCC3=+3.30V - BASEBOARD
VCC3_EXT=+3.30V - PC104 SLOTS
AMD Geode™ LX
Processor
VCORE=+1.25V
VCCMEM=+2.60V
MVREF=+1.3V
VIO=+3.30V
AMD Geode™
CS5536
VCORE=+1.25V
VCORESB=+1.225V
VIO=+3.30V
MEMORY
VMEM=+2.60V
MVREF=+1.3V
D
C
B
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
4
of
26
1
A
5 4 3
A
5 4 3 2 1
D
C
B
PCI MASTER SETTING
REQ2#/GNT#2
AMD
Geode™ LX
Processor
REQ1#/GNT#1
REQ0#/GNT#0
Expander
Expander
AMD Geode™ CS5536
REQ_EXT0#/GNT_EXT0#
PCI to ISA Bridge
REQ_EXT1#/GNT_EXT1#
REQ_EXT2#/GNT_EXT2#
Mini PCI
Ethernet Controller
PC104 Slot 3
PC_REQ0#/PC_GNT0#
PC104 Slot 0
PC_REQ1#/PC_GNT1#
PC104 Slot 1
PC_REQ2#/PC_GNT2#
PC104 Slot 2
PCI CLOCK SETTING
SEL66_33#
CLOCK
GENERATOR
CLK_EXT
MK1491-09
PC_CLK
CLK_CPU
CLK_IOC
Expander
Expander
CLK_EXT0
CLK_EXT1
CLK_EXT2
CLK_EXT3
PC_CLK0
PC_CLK1
PC_CLK2
PC_CLK3
AMD Geode™ LX Processor
AMD Geode™ CS5536
PCI to ISA Bridge
Mini PCI
Ethernet Controller
Not Used
PC104 Slot 0
PC104 Slot 1
PC104 Slot 2
PC104 Slot 3
Jumpers to select
2 of the 3 devices
JTAG DAISY CHAIN MODE WITH AMD GEODE™
CS5536 COMPANION DEVICE
TCK
TMS
TDI
TDO
TDEBUG_OUT
TDEBUG_IN
FS2 HEADER
TCK
TMS
TDI
TDO
TDEBUG_OUT
TDEBUG_IN
AMD GEODE™ LX PROCESSOR
TCK
TMS
TDI
TDO
TDEBUG_OUT
TDEBUG_IN
AMD GEODE™ CS5536
B
D
C
SEL66_33#
1
0
Function
PCI 66 MHz
PCI 33 MHz
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
5
of
26
1
A
5 4 3
D
C
B
A
DESIGN NOTE: See LX layout guidelines for latest recommendations on memory routing.
5
DESIGN NOTE:
Use SDCLK pairs that are most convient for clean routing.
7 SDCLK0
7 SDCLK2
7 SDCLK4
7 SDCLK0#
7 SDCLK2#
7 SDCLK4#
MCAS#
MRAS#
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MDQM0
MDQM1
MDQM2
MDQM3
MDQM4
MDQM5
MDQM6
MDQM7
MCS0#
MCS1#
MCKE0
MWE#
MDQS0
MDQS1
MDQS2
MDQS3
MDQS4
MDQS5
MDQS6
MDQS7
M1
G2
A6
B10
A19
C24
H29
N30
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
U1A
B28
F28
F29
D30
E4
F4
C27
A28
E28
E29
C26
D27
M4
J4
M28
J28
D23
D20
L4
H4
L28
H28
D24
D21
C16
C17
C15
C13
D13
D11
D12
D8
D9
D6
D19
D5
C5
F30
M2
H3
C6
A10
C19
B23
J29
N31
CS0#
CS1#
CS2#
CS3#
CKE0
CKE1
WE0#
WE1#
CAS0#
CAS1#
RAS0#
RAS1#
SDCLK0P
SDCLK1P
SDCLK2P
SDCLK3P
SDCLK4P
SDCLK5P
SDCLK0N
SDCLK1N
SDCLK2N
SDCLK3N
SDCLK4N
SDCLK5N
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
AMD GEODE™
LX PROCESSOR
MVREF
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
A26
C22
C23
B25
B26
D31
A17
B20
A20
A22
A23
A25
A13
A15
B17
B19
B22
B16
C10
A12
B12
A9
C9
C11
J30
M31
M30
R30
R31
L29
F31
K30
K31
G30
G31
J31
M29
P30
R29
C8
D1
A4
A7
B7
B9
G1
F2
F1
D2
B4
B6
K1
J2
J1
F3
E3
J3
P2
N2
M3
K2
P3
N1
L3
MVREF
BA0
BA1
TLA0
TLA1
4
DESIGN NOTE: BA0,BA1 must be trace length matched to within 50 mils.
D26
C20
MBA0
MBA1
RN1
33
MD5
MD1
MD4
MD0
B15
B13
TLA0
TLA1
RN2
33
MD6
MD2
MDQM0
MDQS0
RN3
33
RN4
33
RN5
33
RN6
33
RN7
33
RN8
33
RN9
33
RN10
33
RN11
33
MD21
MD17
MD20
MD16
MD22
MD18
MDQM2
MDQS2
MD28
MD24
MD23
MD19
MDQM3
MDQS3
MD29
MD25
MD31
MD27
MD30
MD26
TLA0
TLA1
MD12
MD8
MD7
MD3
MDQM1
MDQS1
MD13
MD9
MD15
MD11
MD14
MD10
RN12
33
RN13
33
RN15
33
RN17
33
RN19
33
MD37
MD33
MD36
MD32
MD38
MD34
MDQM4
MDQS4
MD44
MD40
MD39
MD35
MDQM5
MDQS5
MD45
MD41
MD47
MD43
MD46
MD42
P1
C2
100nF
DGND
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
5 4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
3
3
RMD37 7
RMD33 7
RMD36 7
RMD32 7
RMD38 7
RMD34 7
RMDQM4 7
RMDQS4 7
RMD44 7
RMD40 7
RMD39 7
RMD35 7
RMDQM5 7
RMDQS5 7
RMD45 7
RMD41 7
RMD47 7
RMD43 7
RMD46 7
RMD42 7
RMD5 7
RMD1 7
RMD4 7
RMD0 7
RMD6 7
RMD2 7
RMDQM0 7
RMDQS0 7
RMD12 7
RMD8 7
RMD7 7
RMD3 7
RMDQM1 7
RMDQS1 7
RMD13 7
RMD9 7
RMD15 7
RMD11 7
RMD14 7
RMD10 7
RMD21 7
RMD17 7
RMD20 7
RMD16 7
RMD22 7
RMD18 7
RMDQM2 7
RMDQS2 7
RMD28 7
RMD24 7
RMD23 7
RMD19 7
RMDQM3 7
RMDQS3 7
RMD29 7
RMD25 7
RMD31 7
RMD27 7
RMD30 7
RMD26 7
RTLA0 7
RTLA1 7
DESIGN NOTE:
Swap series resistors on the
DQS lines in order minimize the number of vias.
RN21
33
MD53
MD49
MD52
MD48
RN23
33
MD54
MD50
MDQM6
MDQS6
RN24
33
MD60
MD56
MD55
MD51
DESIGN
NOTE: Swap series resistors on the address lines in order minimize the number of vias.
RN26
33
MDQM7
MDQS7
MD61
MD57
RN27
33
MD63
MD59
MD62
MD58
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
DESIGN NOTE:
Do not swap series resistors on the DQS,
DQM or Data lines with the
Address or control lines.
DESIGN
NOTE: Swap series resistors on the data lines in order minimize the number of vias.
RN14
22
MA11
MA12
MCKE0
RN16
22
MA6
MA7
MA8
MA9
RN18
22
MA2
MA3
MA4
MA5
RN20
22
MBA1
MA10
MA0
MA1
RN22
22
MCAS#
MWE#
MRAS#
MBA0
RN25
22
MCS1#
MCS0#
MA13
DESIGN
NOTE: Place data bus series resistors as close to the memory devices as possible.
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
2
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
2
1
RMD53 7
RMD49 7
RMD52 7
RMD48 7
RMD54 7
RMD50 7
RMDQM6 7
RMDQS6 7
RMD60 7
RMD56 7
RMD55 7
RMD51 7
RMDQM7 7
RMDQS7 7
RMD61 7
RMD57 7
RMD63 7
RMD59 7
RMD62 7
RMD58 7
DESIGN NOTE: Place DQS and
DQM series resistors as close to the SODIMM connector as possible.
DESIGN NOTE: This schematic shows a non-parallel terminated DDR solution.
There may be restrictions as to the total number of DRAMS and the number of banks supported on the SODIMM. See LX layout guidelines for current restrictions.
D
C
RMA11 7
RMA12 7
RMCKE0 7
RMA6 7
RMA7 7
RMA8 7
RMA9 7
RMA2 7
RMA3 7
RMA4 7
RMA5 7
RMBA1 7
RMA10 7
RMA0 7
RMA1 7
RMCAS# 7
RMWE# 7
RMRAS# 7
RMBA0 7
RMCS1# 7
RMCS0# 7
RMA13 7
DESIGN NOTE: Place address and control series resistors as close to the processor as possible.
VCCMEM
R1
10K
R2
10K
DGND
Vout = 1.30
MVREF
C1
100nF
DGND
B
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
6
of
26
1
A
D
C
B
A
5
6
6
6
6
SDCLK0
SDCLK0#
SDCLK2
SDCLK2#
6 RMCKE0
6
6
6
RMRAS#
RMCAS#
RMWE#
6
6
RMCS0#
RMCS1#
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
RMDQS0
RMDQS1
RMDQS2
RMDQS3
RMDQS4
RMDQS5
RMDQS6
RMDQS7
RMA0
RMA1
RMA2
RMA3
RMA4
RMA5
RMA6
RMA7
RMA8
RMA9
RMA10
RMA11
RMA12
RMDQM0
RMDQM1
RMDQM2
RMDQM3
RMDQM4
RMDQM5
RMDQM6
RMDQM7
RMBA0
RMBA1
12
12
SMB_SDA
SMB_SCL
6 RTLA1
6 RTLA0
6
6
SDCLK4
SDCLK4#
VCCMEM
6 RMA13
1
R3 10K
5
J1A
35
37
160
158
CK0
CK0#
CK1
CK1#
4
96
95
CKE0
CKE1
118
120
119
RAS#
CAS#
WE#
121
122
S0#
S1#
11
25
47
61
133
147
169
183
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
105
102
101
115
100
99
112
111
110
109
108
107
106
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
134
148
170
184
12
26
48
62
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
117
116
BA0
BA1
194
196
198
SA0
SA1
SA2
DGND
193
195
SDA
SDL
123
124
199
200
80
83
84
89
91
97
98
85
86
71
72
73
74
77
78
79
DM8
CB2
CB6
CB3
CB7
CK2
CK2
RFU
RFU/RESET
CB0
CB4
CB1
CB5
DQS8
RFU
RFU
RFU/A13
RFU
VddID
RFU
SODIMM
DDR-SODIMM-200P-RVS
4
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ00
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
DQ07
DQ08
DQ09
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
151
153
142
146
152
154
128
130
136
140
141
145
66
68
127
129
135
139
55
59
65
67
56
60
172
176
177
181
187
189
163
165
171
175
164
166
178
182
188
190
49
53
42
44
50
54
20
24
30
32
41
43
14
18
19
23
29
31
5
7
13
17
6
8
3
RMD37
RMD38
RMD39
RMD40
RMD41
RMD42
RMD43
RMD44
RMD45
RMD46
RMD47
RMD48
RMD49
RMD50
RMD51
RMD52
RMD53
RMD54
RMD25
RMD26
RMD27
RMD28
RMD29
RMD30
RMD31
RMD32
RMD33
RMD34
RMD35
RMD36
RMD0 6
RMD1 6
RMD2 6
RMD3 6
RMD4 6
RMD5 6
RMD6 6
RMD7 6
RMD8 6
RMD9 6
RMD10 6
RMD11
RMD12
RMD13
RMD14
RMD15
RMD16
6
6
6
6
6
6
RMD17
RMD18
RMD19
RMD20
RMD21
RMD22
RMD23
RMD24
6
6
6
6
6
6
6
6
RMD55
RMD56
RMD57
RMD58
RMD59
RMD60
RMD61
RMD62
RMD63
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
MVREF
VCCMEM
J1B
1
2
VREF
VREF
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
132
143
144
155
156
157
92
93
94
113
114
131
167
168
179
180
191
192
46
57
58
69
70
81
82
9
10
21
22
33
34
36
45
197
VDDSPD
SODIMM
DDR-SODIMM-200P-RVS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
2
VCCMEM
C3
22uF
C4
22uF
C5
100pF
C6
100pF
C7
100pF
C8
100pF
C9
1nF
1
C10
22uF
C11
22uF
C12
100pF
C13
100pF
C14
100pF
C15
100pF
C16
1nF
C17
1nF
C18
1nF
C19
1nF
C20
10nF
C21
10nF
C22
10nF
C23
10nF
C24
1nF
C25
1nF
C26
1nF
C27
10nF
C28
10nF
C29
10nF
C30
10nF
149
150
159
161
162
173
174
185
186
DGND
DGND
DESIGN NOTE: This schematic shows a non-parallel terminated
DDR solution. There may be restrictions as to the total number of DRAMS and the number of banks supported on the SODIMM. See LX layout guidelines for current restrictions.
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
7
of
26
1
A
2
D
C
B
3
5 4 3 2 1
D
C
B
A
VCC5 VCC3
J3
DESIGN NOTE: 8-bit Data Streaming
Mode is the simplest data input mode, but is limited to 8-bits.
U26C
HSIP_CLK
HSIP_D0
HSIP_D1
HSIP_D2
HSIP_D3
HSIP_D4
HSIP_D5
HSIP_D6
HSIP_D7
HSIP_D8
HSIP_D9
HSIP_D10
HSIP_D11
HSIP_D12
HSIP_D13
HSIP_D14
HSIP_D15
LDEMOD_HSIP_VSYNC
High Speed
PFL-2x20-2M0-SMD-S
DGND
Input Port
DESIGN NOTE: When using 16 data capture mode (Mode 4 - BT.601), the TFT interface cannot be used due to pin sharing conflicts.
24-bit LVDS Transmitter
5
23
25
27
29
31
33
35
37
39
11
13
15
17
19
21
5
7
9
1
3
24
26
28
30
32
34
36
38
40
12
14
16
18
20
22
2
4
6
8
10
DESIGN NOTE: There are two conventions for connecting 24 bit panels. One is backward compatible with 18 bit panels. The connections defined here are backwards compatible.
TFT_R2
TFT_R3
TFT_R4
TFT_R5
TFT_R6
TFT_R1
TFT_R7
TFT_G2
TFT_G3
TFT_G4
TFT_G0
TFT_G1
TFT_G5
TFT_G6
TFT_G7
TFT_B2
TFT_B0
TFT_B1
TFT_B3
TFT_B4
TFT_B5
TFT_B6
TFT_B7
HSYNC_C
VSYNC_C
LDEMOD_HSIP_VSYNC
TFT_R0
TFTCLK
R_F_CLK
DISPEN
18
19
20
22
23
24
10
11
12
14
15
16
25
27
28
30
50
6
7
8
2
3
4
51
52
54
55
56
31
17
32
U2
IN12
IN13
IN14
IN15
IN16
IN17
IN18
IN19
IN20
IN21
IN22
IN23
IN24
IN25
IN26
IN27
IN00
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
VCC
VCC
VCC
LVCC
PVCC
CLKO-
CLKO+
OUT0-
OUT0+
OUT1-
OUT1+
OUT2-
OUT2+
OUT3-
OUT3+
LGND
LGND
LGND
CLKIN
R_FB
PD
PGND
PGND
GND
GND
GND
GND
GND
1
9
26
44
34
40
39
48
47
46
45
42
41
38
37
36
43
49
33
35
5
13
21
29
53
DS90C385
TSSOP56 Package
HSIP_SYNC
HSIP_HSYNC
VCC3
LVDS_AVCC3
TXCLKOUT-
TXCLKOUT+
TXOUT0-
TXOUT0+
TXOUT1-
TXOUT1+
TXOUT2-
TXOUT2+
TXOUT3-
TXOUT3+
DGND
LVDS_PVCC3
26
26
26
26
26
26
26
26
26
26
26
26
26
TFT_R4
TFT_R3
TFT_R2
26
26
26
26
TFT_B6
TFT_B7
TFT_R6
TFT_R5
26
26
26
TFT_B3
TFT_B4
TFT_B5
26
26
TFT_B2
TFT_G7
26 TFT_G5
26
26
26
TFT_G4
TFT_G3
TFT_G6
26
26
TFT_G2
TFT_R7
DESIGN NOTE: The LSB's for each color (R0,R1,G0,G1,B0,B1) are not used in by 18-bit panels.
LDVS_AGND
LVDS_PGND
R_F_CLK
1
R10 0_NL
4
TFT_R4
TFT_R3
TFT_R2
TFT_R0
TFT_B6
TFT_B7
TFT_R6
TFT_R5
TFT_B0
TFT_B3
TFT_B4
TFT_B5
TFT_B2
TFT_G7
TFT_B1
TFT_G5
TFT_G1
TFT_G4
TFT_G3
TFT_G6
TFT_G2
TFT_R7
TFT_G0
TFT_R1
VCC3
RN69
8
7
6
5
RN70
8
7
6
5
RN71
8
7
6
5
RN72
8
7
6
5
RN73
8
7
6
5
RN74
8
7
6
5
22
1
2
3
4
22
1
2
3
4
22
1
2
3
4
22
1
2
3
4
22
1
2
3
4
22
1
2
3
4
T_R4
T_R3
T_R2
T_R0
T_B6
T_B7
T_R6
T_R5
T_B0
T_B3
T_B4
T_B5
T_B2
T_G7
T_B1
T_G5
T_G1
T_G4
T_G3
T_G6
T_G2
T_R7
T_G0
T_R1
26 TFTCLK
HSIP_CLK
HSIP_SYNC
TFTCLK
T_B0
T_B1
T_B2
T_B3
T_B4
T_B5
T_B6
T_B7
T_G0
T_G1
T_G2
T_G3
T_G4
T_G5
T_G6
T_G7
T_R0
T_R1
T_R2
T_R3
T_R4
T_R5
T_R6
T_R7
HSIP_D8
HSIP_D9
HSIP_D10
HSIP_D11
HSIP_D12
HSIP_D13
HSIP_D14
HSIP_D15
HSIP_D0
HSIP_D1
HSIP_D2
HSIP_D3
HSIP_D4
HSIP_D5
HSIP_D6
HSIP_D7
DESIGN NOTE: For 18-bit panels use OUT0,
OUT1, and OUT2. For 24-bit panels use
OUT0, OUT1, OUT2, and OUT3.
VCC3
FB1
1
BLM18PG600SN1
2
DGND
1
R8 0
C36
10uF
C38 C39
100nF 10nF
3
AL12
AL14
AE1
AH7
AK6
AL6
AJ7
AK7
AL4
AK4
AJ5
AF2
AF1
AG3
AG4
AL7
AH8
AJ8
AJ2
AK3
AL3
AH5
AJ4
AH1
AH2
AH3
AJ1
AH11
AJ11
AK10
AL10
AJ10
AH10
AL9
AK9
AJ15
AK15
AL15
AH13
AJ13
AK13
AL13
AK12
VIPCLK
VIPSYNC
DOTCLK/VOPCLK
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
DRGB0/VOP7
DRGB1/VOP6
DRGB2/VOP5
DRGB3/VOP4
DRGB4/VOP3
DRGB5/VOP2
DRGB6/VOP1
DRGB7/VOP0
DRGB8/VOP15
DRGB9/VOP14
DRGB10/VOP13
DRGB11/VOP12
DRGB12/VOP11
DRGB13/VOP10
DRGB14/VOP9
DRGB15/VOP8
DRGB16_VOP23
DRGB17_VOP22
DRGB18_VOP21
DRGB19_VOP20
DRGB20_VOP19
DRGB21_VOP18
DRGB22_VOP17
DRGB23_VOP16
DRGB24/VID8
DRGB25/VID9
DRGB26/VID10
DRGB27/VID11
DRGB28/VID12
DRGB29/VID13
DRGB30/VID14
DRGB31/VID15
LVDS_PVCC3
LVDS_PGND
LDEMOD/VIP_VSYNC
DISPEN/VOP_BLANK
VDDEN/VIP_HSYNC
VSYNC/VOP_VSYNC
HSYNC/VOP_HSYNC
AMD GEODE™
LX PROCESSOR
VCC3
FB2
1
BLM18PG600SN1
2
DGND
1
R9 0
RED
GREEN
BLUE
DAVDD
DAVDD
DAVDD
DAVDD
DAVSS
DAVSS
DAVSS
DAVSS
DVREF
DRSET
AD4
AE4
AE2
AD3
AE3
W3
V2
U2
W4
V4
U1
V1
W2
Y2
U3
V3
W1
Y1
LDEMOD_HSIP_VSYNC
DISPEN
HSIP_HSYNC
R6
1.2K
R601
10
AGND_VGA
LVDS_AVCC3
C37
10uF
C40 C41
100nF 10nF
1
R30
1
R29
C34
10nF
LDVS_AGND
2
VSYNC_C
22
HSYNC_C
22
RED 14
GREEN 14
BLUE 14
DACVDD
1
R7
C33
10uF
AGND_VGA
LDEMOD_HSIP_VSYNC
DISPEN 26
HSIP_HSYNC 26
VSYNC_C
HSYNC_C
R5
10K
D1
3
C35
LM4041AIM3-1.2
10nF
0
1
R4
AGND_VGA
DGND
1
26
26
VCC3
26
VSYNC_C
HSYNC_C
2
2 long as above condition is met.
VCC3
DGND
VCC3
DGND
Zero ohm resistor can be removed as
DGND
4
VSYNC
U22
NC7SZ125/SC70
DGND
4
HSYNC
U23
NC7SZ125/SC70
DESIGN NOTE: AGND_VGA should be an island with single point connection to the full ground plane to reduce noise content.
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
8
of
26
1
14
14
D
C
B
A
D
5
DESIGN NOTE: There are 8 PCI devices in this design requireing REQ
/ GNT pairs. Two 1 to 3 expanders are provided, giving a total of 7 pairs.
Two pairs are mapped to the following three devices: Ethernet, MiniPCI and
PC104 slot 3. Jumpers are provided to select.
24
11
24
11
GNT0#
GNT2#
REQ0#
REQ2#
GNT0#
GNT1#
GNT2#
REQ0#
REQ1#
REQ2#
C
11,15,19,20,24
11,15,19,20,24
11,15,19,20,24
11,15,19,20,24
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
11,15,19,20,24 PCI_DEVSEL#
11,15,19,20,24 PCI_FRAME#
11,15,19,20,24
11,15,19,20,24
PCI_IRDY#
PCI_TRDY#
11,15,19,20,24
11,12,15,16,17,19,20,24,25
PCI_STOP#
PCI_RST#
U1B
AA28
AB30
AC30
GNT0#
GNT1#
GNT2#
AA29
AB31
AB28
REQ0#
REQ1#
REQ2#
AJ22
AL26
AH27
AH31
CBE0#
CBE1#
CBE2#
CBE3#
PCI_DEVSEL#
AK25
PCI_FRAME#
AL28
DEVSEL#
FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_RST#
AH25
AK26
IRDY#
TRDY#
4
AJ25
Y30
STOP#
RESET#
AMD GEODE™
LX PROCESSOR
PAR
AJ27
AH22
AL23
AL25
AH24
AJ24
AJ28
AK28
AL29
AJ30
AK29
AJ31
AH30
AH29
AG29
AG28
AF30
AE28
AF31
AE30
AE31
AD29
AJ19
AH19
AL20
AK20
AK19
AH21
AJ21
AL19
AK22
AL22
AK23
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
VCC3
20 REQ_EXT0#
REQ_EXT0#
REQ_EXT1#
REQ_EXT2#
PW1
RN68
1
2
3
4
U1D
10K
8
7
6
5
VCC3
DGND
PCI_DEVSEL#
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
REQ0#
REQ1#
REQ2#
RN44
1
2
3
4
RN54
1
2
3
4
10K
8
7
6
5
10K
8
7
6
5
PW0
PW1
AL18
AJ17
PW0
PW1
B
12
13
CLK_48_DOT
CLK_CPU
CLPF
MLPF
VLPF
W29
V29
AA3
AB1
Y31
DOTREF
SYSREF
C45
220pF
C46
220pF
C47
220pF
CAVDD
CAVSS
W31
W30
COREPLLVDD
A
11 IRQ13
11,19,24 PCI_INTA#
IRQ13
AB29
AD28
IRQ13
INTA# MAVDD
MAVSS
V31
V30
GLPLLVDD
CPLLGND
11 CIS
11 SUSPA#
17
17
TDP
TDN
AE29
SUSPA#
AC31
TDBGI_CPU
TDBGO_CPU
AL17
AK17
AB2
AB4
CIS
SUSPA#
AMD GEODE™
LX PROCESSOR
TDP
TDN
VAVDD
VAVSS
TDI
TMS
TDO
TCLK
TDBGI
TDBGO
AA1
AA2
AB3
AA4
AC1
AC2
DOTPLLVDD
JTAGTDI
JTAGTMS
JTAGTCK
GLPLLGND
DPLLGND
TDO_CPU 12
CPLLGND
1
R35 0
1
R36 0
DPLLGND
1
R38 0
GLPLLGND
5 4
13 CLK_EXT
3
PCI_PAR 11,15,19,20,24
PCI_AD[31:0] 11,15,19,20,24
5 4 3 2 1 CORE MEM
--- --- --- --- --- --- ---
Off On Off Off Off 500 400
Off On Off Off On 500 333
Off On On On On 433 333
On On On On On Bypass Bypass
VCC3
VCC3_EXT1
REQ_EXT0#
REQ_EXT1#
REQ_EXT2#
GNT1#
PCI_FRAME#
PCI_STOP#
PCI_RST#
U3
13
NC
5
8
11
4
REQ1
REQ2
REQ3
S_GNT
1
2
FRAME
STOP
26
27
RESET
CLKIN
NC
GNT1
GNT2
GNT3
S_REQ
CLKFB
CLK1
CLK2
CLK3
CLK4
16
23
22
20
19
18
7
10
12
3
2
5
4
3
2
1
PW0
SUSPA#
GNT2#
GNT1#
GNT0#
1
R11 10K_NL
1
R12 1K
1
R13 10K_NL
1
R14 1K
1
R15 10K_NL
1
R16 1K
1
R17 10K_NL
1
R18 1K
1
R19 10K_NL
1
R20 1K
Debug
Stall
JP-1x2_NL
J4
IRQ13
1
R21 1K_NL
1
R22 10K
Normal
Setting
GNT_EXT1#
GNT_EXT2#
REQ1#
GNT_EXT0# 20
CLKFB_EXT
CLK_EXT0 20
CLK_EXT1 19
CLK_EXT2 15
VCC3
Off
On
Off
On
Off
On
Off
On
Off
On
DGND
JTAGTCK
TDBGI_CPU
JTAGTDI
JTAGTMS
REQ_EXT1#
REQ_EXT2#
GNT_EXT1#
GNT_EXT2#
1
3
5
7
9
11
J5
1
1
2
3
4
RN28
4.7K
8
7
6
5
2
4
6
8
10
12
PFL-2x6-2M0-SMD-S
J6
1
3
5
7
9
11
2
4
6
8
10
12
VCC3
REQ#_LAN
REQ#_MPCI
REQ#_PC3
15
19
24
GNT#_LAN 15
GNT#_MPCI 19
GNT#_PC3 24
PFL-2x6-2M0-SMD-S
DESIGN NOTE: Two REQ/GNT pairs are mapped to the following three devices: Ethernet, MiniPCI and PC104 slot 3. Jumpers are provided to select.
DESIGN NOTE: CLKFB output is used internally by the 8209 to produce the zero delay.
CLKFB_EXT
14
NC
1
R31 10K
DGND
DGND
DGND
COREPLLVDD
C48
10nF
1
R33 1
CPLLGND
DOTPLLVDD
1
R34 1
C51
10nF
GLPLLVDD
DPLLGND
1
R37 1
C54
10nF
GLPLLGND
3
DGND
C49
10nF
C52
10nF
C55
10nF
NC
15
IT8209R
GND_EXT1
VCC3
C50
10uF
VCC3
C53
10uF
VCC3
C56
10uF
VCC3
FB3
1
BLM18PG600SN1
2
C42
10uF
DGND
1
R32 0
VCC3_EXT1
C43 C44
100nF 10nF
DESIGN NOTE:
COREPLLGND, DOTPLLGND and GLPLLGND should each be an island with single point connection to the full ground plane to reduce noise content.
Zero ohm resistor can be removed as long as above condition is met.
J7 VCC3
GND_EXT1
TDBGI_CPU
TDBGO_CPU
5
7
9
1
3
11
13
2
4
6
8
10
12
14
JTAGTDI
JTAGTCK 12
JTAGTMS 12
JTAGTDO 12
SYS_RST# 11,17,25
PFL-7X2 DGND DGND
JTAG HEADER
DESIGN NOTE: Add
"JTAG HEADER" to the silkscreen
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
9
of
26
1 2
B
A
D
C
D
C
B
5
VCORE
VCCMEM
VCC3
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VMEM
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
AG1
AF29
AJ14
AJ18
AJ20
AJ23
AJ26
Y3
AK1
AJ29
AF3
AK31
AL11
AG31
AA31
AC29
AD31
AJ3
AD1
AC3
AJ6
AJ9
AJ12
AL2
AL8
AL24
AL21
AL5
AL27
AL30
D28
E30
G29
B21
H31
K29
K3
C18
A18
B24
C25
B27
L31
A30
N29
C3
A2
B1
E2
G3
A14
B31
C29
P29
B5
C14
D4
C7
N4
B11
H1
L1
B8
A
5
4
U1E
AMD GEODE™
LX PROCESSOR
4
3
AH4
AH6
AG30
R19
AH20
C2
C4
A8
W16
W15
D25
B18
P17
H2
A11
R16
R17
R18
AH12
Y29
AA30
AD30
AG2
AH9
D16
D7
N17
N28
P15
P16
P28
L2
N16
A31
A27
N15
B14
A16
D18
AJ16
V17
AK2
V16
V15
R15
R14
R13
C30
C31
D29
E31
G28
K28
AH14
A24
A29
B29
B30
C28
P31
W28
AC28
D3
A5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
DGND
2
VCORE
C57
22uF
C58
22uF
C59
22uF
C60
10nF
C61
10nF
C62
10nF
C63
10nF
1
C64
1nF
C65
1nF
C66
1nF
C67
1nF
C68
100pF
C69
100pF
C70
100pF
C71
100pF
C72
22uF
C73
22uF
C74
22uF
C75
10nF
C76
10nF
C77
10nF
C78
10nF
VCC3
C79
1nF
C80
1nF
C81
1nF
C82
1nF
C83
100pF
C84
100pF
C85
100pF
C86
100pF
C87
22uF
C88
22uF
C89
22uF
C90
10nF
C91
10nF
C92
10nF
C93
10nF
VCCMEM
C94
100pF
C95
100pF
C96
100pF
C97
100pF
C98
100pF
C99
100pF
C100
10nF
C101
10nF
C102
22uF
C103
22uF
C104
22uF
C105
10nF
C106
10nF
C107
10nF
C108
10nF
C109
100pF
C110
100pF
C111
100pF
C112
100pF
C113
100pF
C114
100pF
C115
10nF
C116
10nF
DGND
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
Size
B
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Date:
Wednesday, April 11, 2007
Rev
Sheet
10
D
of
26
1
A
D
C
B
A
5 4 3
D
C
9,15,19,20,24 PCI_AD[31:0]
DESIGN NOTE: Any
GPIO can be used as an IRQx or INT#x.
There are significant bootloader configuration changes required if selection is different than shown. Changes are highly discouraged.
9,15,19,20,24 PCI_PAR
9,15,19,20,24
9,15,19,20,24
9,15,19,20,24
9,15,19,20,24
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
9,15,19,20,24
9,15,19,20,24
PCI_FRAME#
PCI_IRDY#
9,15,19,20,24
9,15,19,20,24
9,19,24
9,15,19,20,24
PCI_DEVSEL#
PCI_TRDY#
PCI_INTA#
PCI_STOP#
9
9
GNT2#
REQ2#
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
R8
U7
T7
R7
U6
T6
R13
U12
T12
R12
U8
T8
U5
T5
R5
T4
R4
U3
T3
U1
R15
P15
T14
R14
U13
T13
R17
T17
R16
T16
P16
T15
PCI_INTA#
U9
R10
R11
T10
R2
T11
R1
T1
U10
U14
U11
T9
R6
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PAR
C/BE0#
C/BE1#
C/BE2#
C/BE3#
FRAME#
IRDY#
DEVSEL#
TRDY#
GPIO0
STOP#
GNT#
REQ#
U4A
PCI_CLK
U4
WORKING
C5
GPIO28/PWR_BUT#
GPIO5/MFGPT1_RS/MFGPT0_C1
RESET_OUT#
RESET_STAND#
RESET_WORK#
A8
D3
GPIO6/MFGPT0_RS/MFGPT1_C1/MFGPT2_C2
GPIO7/MFGPT2_C1/SLEEP_X
GPIO13/SLEEP_BUT
GPIO12/AC_S_IN2/SLEEP_Y
D2
C2
GPIO8/UART1_TX/UART1_IR_TX
GPIO9/UART1_RX/UART1_IR_RX
GPIO26/MFGPT7_RS
GPIO27/MFGPT7_C1/32KHZ
E3
D1
GPIO10/THRM_ALRM#
GPIO11/SLP_CLK_EN#/MFGPT1_C2
C3
A1
GPIO24/WORK_AUX
GPIO25/LOW_BAT#/MFGPT7_C2
C9
A9
B7
C8
F2
J3
A5
B8
C6
SUSP#/CIS
SUSPA#
P3
N1
AMD GEODE™
CS5536
COMPANION
DEVICE
IRQ13
K2
MHZ14_CLK
KHZ32_XCI
KHZ32_XCO
C1
A4
B3
USB_PTEST
G15
TEST_MODE
LVD_TEST
A6
B9
FUNC_TEST
F3
TEST_MODE
FUNC_TEST
CLK_IOC 13
WORKING
PWRBTN#
IDE_CABLEID#
5536_GPIO6
PCI_INTB#
WORKING 25
PWRBTN# 25
IDE_CABLEID# 21
PCI_INTB# 15,19,24
CS5536_GPIO8 17
CS5536_GPIO9 17
OT_ALARM 17
SLP_CLK# 13
WORK_AUX
CS5536_GPIO25
PME#
MFGPT7_C1
PCI_INTD#
PCI_INTC#
RST_STB#
SYS_RST#
WORK_AUX
PME#
25
CS5536_GPIO25
15,17,19,25
17
PCI_INTD#
PCI_INTC#
24
24
PCI_RST# 9,12,15,16,17,19,20,24,25
RST_STB# 25
SYS_RST# 9,17,25
CIS 9
SUSPA# 9
5536_GPIO6
IRQ13 9
RTCXIN
RTCXOUT
CLK_14_IOC 13
B
WORK_AUX
PME#
MFGPT7_C1
PWRBTN#
WORKING
CS5536_GPIO25
RST_STB#
SLP_CLK#
IDE_CABLEID#
SYS_RST#
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
2
RN30
1
2
3
4
RN31
1
2
3
4
1
2
3
4
1
R39
1
R40
1
R41
RN29
1K
5.6K
10K
8
7
6
5
10K
8
7
6
5
5.6K
10K
8
7
6
5
VCC3SB
VCC3
TEST_MODE
FUNC_TEST
1
R94
1
R95
0_NL
0
1
R42
1
R43
1K
1K
DGND
LAN_PD# 15
CS5536_GPIO6 17
DESIGN NOTE:
LED is optional.
MFGPT7_C1
PWR MANAGEMENT
RED
D2
2 1
VCC5SB
1
R46 560
LTST-C190EKT
1
RTCXIN
RTCXOUT
1M
1
R44
C117
1
1pF
22M
1
1
R45
4
C119
22pF
DGND
Y1
32.768KHz
ABS13-32.768KHz-12.5pF - T
C118
22pF
DGND
VCC3
DESIGN NOTE: GPIO24/WORK_AUX is an open drain output, which requires a pullup resistor to achieve a high state. At initial standby power application the
GPIO24/WORK_AUX pin defaults to GPIO24 and the GPIO24 defaults as an input. This default combination will leave the pin in a high state due to the pullup which is normally connected to VCC3SB. This circuit works aournd that behaviour so that Save to
RAM will function correctly.
5
VCC3SB
C120
100nF
DGND
WORK_AUX
WORKING
VCC3SB
SAVE TO RAM SUPPORT
1
2
U5
4
DGND
NC7SZ08/SC70
1
R48 10K
INVERTER
R47
10K
Q1
BSS138/SOT
C121
100nF
PS_ON# 25
C122
4.7uF
DGND
DGND
4 3 2
25
MFGPT7_C1
21 IDE_LED
EXT_PWRBTN#
25 EXT_RST#
R91
330R
J31
1
3
5
7
2
4
6
8
PFL-2x4-2M0-SMD-S
DGND
R93
330R
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
11
of
26
1
A
D
C
B
5 4 3 2 1
D
C
B
A
21 IDE_RST#
21 IDE_D[15:0]
21
21
21
IDE_DRQ#
IDE_IOW#
IDE_IOR#
21
21
21
21
IDE_RDY#
IDE_ACK#
IDE_IRQ
IDE_A1
21
21
21
21
IDE_A0
IDE_A2
IDE_CS0#
IDE_CS1#
IDE_D7
IDE_D8
IDE_D6
IDE_D9
IDE_D5
IDE_D10
IDE_D4
IDE_D11
IDE_D3
IDE_D12
IDE_D2
IDE_D13
IDE_D1
IDE_D14
IDE_D0
IDE_D15
IDE_DRQ#
IDE_RDY#
IDE_IRQ
RN32
1
2
3
4
RN34
1
2
3
4
RN36
1
2
3
4
RN37
1
2
3
4
RN38
1
2
3
4
RN39
1
2
3
4
RN40
1
2
3
4
22
8
7
6
5
22
8
7
6
5
22
8
7
6
5
22
8
7
6
5
22
8
7
6
5
22
8
7
6
5
22
8
7
6
5
I_RST#
I_D7
I_D8
I_D6
U4B
I_D9
I_D5
I_D10
I_D4
I_D11
I_D3
I_D12
I_D2
I_D13
I_D1
I_D14
I_D0
I_D15
I_DRQ#
I_IOW#
I_IOR#
I_RDY#
I_ACK#
I_IRQ
I_A1
I_A0
I_A2
I_CS0#
I_CS1#
13
I_IRQ
I_RST#
CLK_IDE
I_A0
I_A1
I_A2
I_ACK#
I_DRQ#
I_IOR#
I_IOW#
I_RDY#
I_CS0#
I_CS1#
BITCLK
16
SYNC_BOS0
SDATA_IN
SDATA_OUT_BOS1
PCBEEP
9 CLK_48_DOT
18
18
USB_PWR_EN1
USB_PWR_EN2
18 USB_OC#
18
18
18
18
18
18
18
18
USB0+
USB0-
USB1+
USB1-
USB2+
USB2-
USB3+
USB3-
I_D0
I_D1
I_D2
I_D3
I_D4
I_D5
I_D6
I_D7
I_D8
I_D9
I_D10
I_D11
I_D12
I_D13
I_D14
I_D15
B12
F15
A10
GPIO2/IDE_IRQ0
IDE_RESET#
MHZ66_CLK
A11
A12
B11
C12
A14
B13
C13
A13
B10
C10
B14
A15
C15
C16
B17
D15
E15
E16
E17
D17
D16
C17
A17
B16
B15
C14
IDE_AD0/FLASH_AD25/AD0/FLASH_CLE
IDE_AD1/FLASH_AD26/AD1
IDE_AD2/FLASH_AD27/AD2
IDE_DACK0#/FLASH_CS3#/FLASH_CE3#
IDE_DREQ0/FLASH_CS2#/FLASH_CE2#
IDE_IOR0#/FLASH_RE#
IDE_IOW0#/FLASH_WE#
IDE_RDY0/FLASH_IOCHRDY/FLASH_RDY/BUSY#
IDE_CS0#/FLASH_CS0#/FLASH_CE0#
IDE_CS1#/FLASH_CS1#/FLASH_CE1#
IDE_DATA0/FLASH_AD10/IO0
IDE_DATA1/FLASH_AD11/IO1
IDE_DATA2/FLASH_AD12/IO2
IDE_DATA3/FLASH_AD13/IO3
IDE_DATA4/FLASH_AD14/IO4
IDE_DATA5/FLASH_AD15/IO5
IDE_DATA6/FLASH_AD16/IO6
IDE_DATA7/FLASH_AD17/IO7
IDE_DATA8/FLASH_AD18/AD3
IDE_DATA9/FLASH_AD19/AD4
IDE_DATA10/FLASH_AD20/AD5
IDE_DATA11/FLASH_AD21/AD6
IDE_DATA12/FLASH_AD22/AD7
IDE_DATA13/FLASH_AD23/AD8
IDE_DATA14/FLASH_AD24/AD9
IDE_DATA15/FLASH_ALE
LPC_CLK
LPC_AD0/GPIO16
LPC_AD1/GPIO17
LPC_AD2/GPIO18
LPC_AD3/GPIO19
LPC_DRQ#/GPIO20
LPC_FRAME#/GPIO22
LPC_SERIRQ/GPIO21/MFGPT2_RS
H1
H2
J2
J1
K1
G1
H3
G2
GPIO14/SMB_CLK
GPIO15/SMB_DATA
GPIO3/UART2_RX
GPIO4/UART2_TX
G3
F1
E1
E2
K3
M1
GPIO1/AC_BEEP/MFGPT0_C2
AC_CLK
L3
L1
L2
AC_S_SYNC/BOS0
AC_S_IN
AC_S_OUT/BOS1
TCK
TDI
TDO
TMS
T_DEBUG_IN
T_DEBUG_OUT
N2
P1
P2
N3
M2
M3
N17
MHZ48_CLK
P17
N16
N15
USB_PWR_EN1
USB_PWR_EN2
USB_OC_SENS#
K16
K17
L16
L17
H17
H16
G17
G16
USB1_DATPOS
USB1_DATNEG
USB2_DATPOS
USB2_DATNEG
USB3_DATPOS
USB3_DATNEG
USB4_DATPOS
USB4_DATNEG
AMD GEODE™
CS5536
COMPANION
DEVICE
LVD_EN#
USB_REXT
USB_VBUS
MHZ48_XCO
MHZ48_XCI
MHZ48_XCEN
C7
K15
M15
J15
H15
F17
VCC3
CLK_LPC_IOC
LAD0
LAD1
LAD2
LAD3
LDRQ#
LFRAME#
SERIRQ
SMB_SCL
SMB_SDA
CRT_SCL
CRT_SDA
TDBGI_IOC
LVD_EN#
USB_REXT
XTALO_48
XTALI_48
XCEN
LPC Header
DGND
11
13
15
17
19
5
7
9
1
3
J8
PFL-2x10
CLK_LPC_IOC
LAD0 17
LAD1
LAD2
17
17
LAD3 17
LDRQ# 17
LFRAME# 17
SERIRQ 17,20
13
SMB_SCL 7
SMB_SDA 7
12
14
16
18
20
2
4
6
8
10
CRT_SCL 14,26
CRT_SDA 14,26
JTAGTCK 9
TDO_CPU 9
JTAGTDO 9
JTAGTMS 9
R62
3.4K,1%
VCC3
PCI_RST# 9,11,15,16,17,19,20,24,25
CLK_LPC_IOC
LAD3
LAD2
LAD1
LAD0
LFRAME#
SERIRQ
LDRQ#
LAD0
LAD1
LAD2
LAD3
LDRQ#
SERIRQ
LFRAME#
CRT_SCL
CRT_SDA
DESIGN NOTE: This design uses LVD (LVD_EN# tied low) to generate system reset. Since LVD only monitors
Vcore in the working domain, the designer must guarantee that Vio and other required voltages are valid at or before Vcore. If this cannot be guaranteed, then RESET_WORK# must be used to hold system in reset until Vio and Vcore and any other required voltages are valid.
XTALO_48
XTALI_48
XCEN
SMB_SCL
SMB_SDA
TDBGI_IOC
IDE_RDY#
IDE_IRQ
USB_OC#
PCBEEP
IDE_D7
IDE_DRQ#
LVD_EN#
DGND
DESIGN NOTE: Place series R near the audio CODEC.
SDATA_IN
BITCLK
1
R65
1
R63
22
22
AC97_DATA_IN 16
AC97_BITCLK 16
AC97_DATA_OUT 16
AC97_SYNC 16
DGND
RN33 10K
1
2
3
4
8
7
6
5
RN35 10K
1
2
3
4
8
7
6
5
1
R49
1
R50
1
R51
1
R52
1
R53
1
R54
1
R55
1
R56
1
R57
1
R58
1
R59
1K
2.2K
2.2K
4.7K
10K
10K
10K
10K_NL
10K
10K
10K
1
R60
1
R61
2.2K
2.2K
DGND
VCC3
DGND
1
Y2
2
48.0000MHz
C123 C124
18pF 18pF
DESIGN NOTE: USBPWR_EN1/2 and
USB_OC# are used for a fully compliant
USB design. See Option Schematics for fully compliant USB design.
5
SDATA_OUT_BOS1
SYNC_BOS0
1
R64 22
1
R66 22
DESIGN NOTE: Place series R near the IOC.
BOS1
BOS0
1
R67 10K_NL
1
R68 1K
1
R69 10K_NL
1
R70 1K
4
VCC3
DGND
BOS1
0
1
0
1
3
BOS0
0
0
1
1
BOOT STRAP OPTIONS
LPC ROM OFF LPC
NOR FLASH OFF IDE INTERFACE
RESERVED
SST FWH OFF LPC (DEFAULT)
2
*AMD CONFIDENTIAL*
VCC5
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
12
of
26
1
D
C
B
A
B
A
C
5 4
D
DESIGN NOTE: Without UL approval of the internal VBAT circuity, a 47 ohm resistor (R1) is required. UL approval is in process and is expected. With
UL approval R1 can be removed.
BT1
DESIGN NOTE: If this schematic is used for future designs, R72 should be replaced with a 220_2A ferrite bead.
R1
1
R71 47
J9
J1
1
2
3
PFL-1x3 R73
1K
J1
1-2 Normal
VBH2032-1
2-3 Clear CMOS
DGND
DGND
VBAT
C127
100nF
VCC3SB
VCC5
1
330_NL
R213
1
330_NL
R214
D19
1
BAS40_NL
2
R215
1K_NL
D17
1
BAS40_NL
2
D18
1
BAS40_NL
2
C222
220M_NL
3 2
VCC3SB
C128
22uF
DGND
VCORESB
VCORE
1
R72 4.7R
C129
10nF
VCC3USB
VCC3
1
FB4
HI1206N101R-00
C143
22uF
DGND
C130
10nF
C144
10nF
C131
1uF
C132
100nF
VCORE
C145
10nF
C146
100pF
VBAT
VCC3
U4C
A3
VBAT
A7
VCORE_VSB
B6
VIO_VSB
K14
H14
VDDC_USB1
VDDC_USB0
D10
D8
H4
K4
P8
P10
VCORE
VCORE
VCORE
VCORE
VCORE
VCORE
P14
M14
F14
D14
VDDIO_USB0
VDDIO_USB1
VDDIO_USB2
VDDIO_USB3
D12
D9
D6
D4
F4
M4
P4
P6
P9
P12
VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO
AMD GEODE™
CS5536
COMPANION
DEVICE
VSSIO_USB0
VSSIO_USB1
VSSIO_USB2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
L14
J14
G14
G4
J4
L4
N4
P5
P7
P11
P13
N14
E14
D13
D11
D7
D5
E4
J17
B5
B4
B1
T2
U2
A2
C4
B2
L15
R9
U17
U16
F16
J16
M16
U15
C11
A16
R3
M17
DGND DGND
VCC3
DGND
C157
22uF
C158
100nF
C159
100nF
C160
100nF
C161
100nF
DGND
11 SLP_CLK#
DGND
U6
17
PD#
10
SEL66/33#
CLKX1
Y3
1 2
14.31818MHz
1
R75
C162
18pF
10M_NL
CLKX2
C163
18pF
2
XTALIN
3
XTALOUT
DGND DGND
REFCLK1
REFCLK0/SP#
26
27
48MHz
48MHz/TS#
13
14
66MHz
16
LCLK2
LCLK1
LCLK0
9
6
5
PCICLK0
PCICLK1
PCICLK2
PCICLK3
18
20
23
24
14_318MHZ0
14_318MHZ1
48MHZ
IDE_CLK
LCLK0
LCLK1
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
MK1491-09F
14_318MHZ0
14_318MHZ1
IDE_CLK
PCI_CLK3
PCI_CLK2
PCI_CLK1
PCI_CLK0
DESIGN NOTE: Enables spread spectrum. EMI mitigation technique
1
2
3
4
RN41
1
2
3
4
22
1
R23 22
RN42
8
7
6
5
22
8
7
6
5
1
R74 10K
DGND
CLK_14_CODEC
CLK_14_ISA
CLK_14_IOC
24
11
16
CLK_IDE 12
PC_CLK 24
CLK_EXT 9
CLK_IOC 11
CLK_CPU 9
48MHZ
LCLK0
LCLK1
1
2
3
4
RN43
22
8
7
6
5
SIO_CLK_48 17
CLK_LPC_SIO_EXT 17
CLK_LPC_IOC 12
DESIGN NOTE: Swap series resistors on the clock lines in order minimize the number of vias.
DGND
4 5 3 2
VCC3
C125
22uF
C126
22uF
1
C133
10nF
C134
10nF
C135
10nF
C136
10nF
C137
10nF
C138
100pF
C139
100pF
C140
100pF
C141
100pF
C142
100pF
VCORE
C147
22uF
C148
22uF
C149
10nF
C150
10nF
C151
10nF
C152
10nF
C154
100pF
C155
100pF
C156
100pF
D
C
DGND
B
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
13
of
26
1
A
A
5 4 3 2 1
D
C
B
8 RED
8 GREEN
8 BLUE
R80
75
R81
75
R82
75
VCC3
D3 D4 D5
C164
4.7pF
L1
1
22nH
INDUCTOR, 22NH, 5%, 0603, 0.48A
C165
4.7pF
BAV99/SOT BAV99/SOT
DGND
1
MRED
L2
MGREEN
22nH
INDUCTOR, 22NH, 5%, 0603, 0.48A
1
L3
MBLUE
22nH
INDUCTOR, 22NH, 5%, 0603, 0.48A
C166
4.7pF
C167
4.7pF
C168
4.7pF
BAV99/SOT
C169
4.7pF
DESIGN NOTE: Place the ESD protection components as close to the VGA connector as possible.
D6
C3
C9
C4
C10
C5
C6
C1
C7
C2
C8
P1C
VCC3
BAV99/SOT
D7
BAV99/SOT
DGND
C11
C12
C13
C14
C15
CON-COMBO-DB9-15-25-TRIPLEPORT
AGND_VGA
VCC5
F1
1.10A, 16V
VGA_CHASSIS
VGA
1
DGND
1
C170
100nF
FB5
BLM18PG600SN1
VGA_CHASSIS
D8
BAV99/SOT
D9
BAV99/SOT
MDDAT_UART_TX
MCRT_HSYNC
MCRT_VSYNC
MDDCLK_UART_RX
R76 0
R77 0
R78 0
R79 0
C171
100nF
DGND
CRT_SDA
HSYNC 8
12,26
VSYNC 8
CRT_SCL 12,26
C
D
B
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
14
of
26
1
A
5 4 3
5
D
C
B
V_LAN_12
C180
22uF
DGND
VCC3
C181
100nF
V_LAN_12
C182
100nF
FB7
FB8
1 2
BLM18PG600SN1 C190
22uF
DGND
V_LAN_12A
FB6
BLM18PG600SN1
1 2
V_LAN_12A_PLL
1 2
BLM18PG600SN1 C187
22uF
VCC3V_LAN
DGND
9,11,19,20,24
C183
22uF
C188
100nF
VCC3
PCI_AD[31:0]
C184
100nF
C185
100nF
C186
100nF
R87
10K
R88
10K
9,11,19,20,24
9,11,19,20,24
9,11,19,20,24
9,11,19,20,24
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
C191
100nF
C192
100nF
9,11,19,20,24
9 GNT#_LAN
9 REQ#_LAN
PCI_DEVSEL#
9,11,19,20,24
9,11,19,20,24
9,11,19,20,24
PCI_STOP#
PCI_TRDY#
PCI_IRDY#
9,11,19,20,24 PCI_FRAME#
9,11,19,20,24 PCI_PAR
11,17,19,25 PME#
11,19,24
9,11,12,16,17,19,20,24,25
9
PCI_INTC#
PCI_RST#
CLK_EXT2
U7
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_AD24
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
PAD8
PAD9
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PAD16
PAD17
PAD18
PAD19
PAD20
PAD21
PAD22
PAD23
PAD24
PAD25
PAD26
PAD27
PAD28
PAD29
PAD30
PAD31
106
105
104
103
102
101
114
113
112
111
110
109
128
127
126
122
121
120
119
118
117
116
115
100
99
98
97
96
95
94
93
89
88
87
86
85
CBE0#
CBE1#
CBE2#
CBE3#
1
R90 100
71
70
69
68
14
80
77
76
75
74
73
72
SERR#
PERR#
GNT#
REQ#
DEVSEL#
IDSEL
STOP#
TRDY#
IRDY#
FRAME#
PAR
PME#
16
67
12
INTR
RST#
PCLK
65
X1
25MHZ Crystal
Y4
66
X2
A
C194
22pF
C195
22pF
DGND
2 1 3
V_LAN_12A
V_LAN_12A_PLL
V_LAN_12 VCC3
VCC3V_LAN
VCC3
C172
22uF
C173
100nF
C174
100nF
C175
100nF
C176
100nF
C177
100nF
C178
100nF
C179
100nF
TXP1
48
TXM1
RXP1
49
45
RXM1
46
TXP2
56
TXM2
RXP2
55
53
RXM2
52
FXSD1/NC
ISET
44
61
NC
NC
TESTEN
SCANEN
NC
NC
59
60
1
2
40
41
P1LED0
P1LED1
P1LED2
P1LED3
P2LED0
P2LED1
P2LED2
P2LED3
8
7
6
22
5
4
3
27
EEEN
EECS
EEDO
EESK
EEDI
26
19
28
29
30
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
18
20
21
25
31
81
82
83
84
11
13
15
17
PWRDN
36
TXP1 18
TXM1 18
RXP1 18
RXM1 18
TXP2 18
TXM2 18
RXP2 18
RXM2 18
R83 1K
R84 3K,1%
R85 1K
R86 1K
VCC3
DGND
R89 10K
EECS
EEDO
EESK
EEDI
VCC3
R92
10K
PWRDN
L
H
Definition
Powerdown
Normal
LAN_PD# 11
P1LED2 18
P1LED3 18
P2LED2 18
P2LED3 18
DGND
EECS
EESK
EEDO
EEDI
U8
1
2
3
4
CS
SK
DI
DO
VCC
NC
ORG
GND
8
7
6
5
AT93LC46 MSOP8
VCC3
DGND
C193
100nF
KSZ88XX-PMQL
DGND
3 2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
15
of
26
1
A
D
C
B
5
4
4
2 1
D
C
B
5 4 3
VCC5
1
FB9
FERR
2
FB/120
C197
100nF
C198
22uF
Red Mic In
J10A
L1
L2
R1
R2
AJ3595
1
2
3
4
MIC1
JD0
MIC2
JD2
JD1
JD0
1
R197 10K
1
R198 10K
1
R199 10K
C201
3.3uF
C202
3.3uF
C203
3.3uF
JD_2
JD_1
JD_0
1
DGND
GND_AUD
J10B
Green Line Out
L1
L2
R1
R2
AJ3595
6
7
8
9
FRONT_OUT_L
JD2
FRONT_OUT_R
Blue Line In
1
AUD_CHASSIS
J10C
L1
L2
R1
R2
AJ3595
AUD_CHASSIS
C189
100nF
FB34
BLM18PG600SN1
10
11
12
13
AUD_CHASSIS
JD1
GND_AUD
LINE_IN_R
LINE_IN_L
C207
100pF
1
FERR
2
1
FB10 FB/120
FERR
2
FB11 FB/120
C208
100pF
R96
R97
1
0
1
0
C204
C205
1
1uF
1
1uF
R127
22K
R126
22K
GND_AUD GND_AUD
JD_1
JD_2
VREFOUT
MIC2
MIC1
C214
220pF
1
FERR
2
1
FB14 FB/120
FERR
2
FB15 FB/120
C215
220pF
R102
4.7K
R103
4.7K
R104
R105
1
0
1
0
C212
C213
1
1uF
1
1uF
R106
22K
R107
22K
C338
100nF
GND_AUD
GND_AUD GND_AUD
VREFOUT
GND_AUD
24
23
LINE-IN-R
LINE-IN-L
22
MIC2
21
20
MIC1
CD-R
19
CD-GND
18
17
CD-L
JD1
16
JD2
15
14
AUX-R
AUX-L
13
PHONE
C337
100nF
AC97_PCBEEP
VCC3
VCC_AUD
C196
C199
1
1nF
1
1nF
C200
1uF
GND_AUD
U9
MONO-O
37
38
AVDD2
SURR-OUT -L/HP-OUT-L
39
40
NC
SURR-OUT -L/HP-OUT-R
REALTEK
ALC655
AVSS2
CENTER-OUT
LFE-OUT
41
42
43
44
JD0/GPIO0
XTLSEL/ID1#
45
46
SPDIFI/EAPD
47
SPDIFO
48
GND_AUD
JD_0
DGND
C206
1
1uF
C209
1
1uF
1
FERR
2
FB12 FB/120
FRONT_OUT_L
R100
22K
1
FERR
2
FB13 FB/120
R101
22K
C210
100pF
FRONT_OUT_R
C211
100pF
GND_AUD
GND_AUD
DGND
R196 0
1
GND_AUD
ALC655
Ground
Left Channel
A
12 PCBEEP
VCC3
Buzzer
R109
10K_NL
R130
10K
Q2
BSS138/SOT NL
R108 22_NL
R202 10K
C341
100nF
R203
1K
DGND
C342
1
100nF
AC97_PCBEEP
VCC3
C216
22uF
C217
100nF
DGND DGND
BUZ1
DET801H_NL
9,11,12,15,17,19,20,24,25 PCI_RST#
12 AC97_SYNC
12
12 AC97_DATA_IN
AC97_DATA_OUT
12 AC97_BITCLK
DGND
C218
22pF
DGND DGND
13 CLK_14_CODEC
DESIGN NOTE: Use
14.318MHz external clock
DGND
5 4 3 2
Right Channel
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
16
of
26
1
A
D
C
B
5 4 3 2 1
VCC5
VCC3
VCC3SB
D
C
B
13 CLK_LPC_SIO_EXT
13 SIO_CLK_48
9,11,12,15,16,19,20,24,25
12
PCI_RST#
LDRQ#
12,20
12
SERIRQ
LFRAME#
12 LAD0
12
12
12
LAD1
LAD2
LAD3
SIO_GPIO45
SIO_GPIO44
11,15,19,25 PME#
SIO_GPIO43
SIO_GPIO42
SIO_GPIO53
DESIGN NOTE: The 8 bit ADC has a conversion rate of 8Hz. Use of the ADC feature is limited to applications that can accept this frequency.
SIO_BOARDTEMP
TDP
SIO_ADC_VREF
SIO_ADC7
SIO_ADC6
SIO_ADC5
SIO_ADC4
SIO_ADC3
SIO_ADC2
SIO_ADC1
SIO_ADC0
DESIGN NOTE: The 8 bit ADC has a 16mV
LSB, with a 0V to 4.096V input range. If negative voltage is to be measured use
VREF in a divider to produce a positive range. A seperate low impedance ground plane should be used to achieve accurate measurements.
VCC3
22
22
RS485_EN2
RS485_EN1
SIO_GPIO62
SIO_GPIO50
SIO_GPIO41
SIO_GPIO40
SIO_GPIO10/WD_ACTIVE
11 OT_ALARM
R209 10K
S_FLASH_DIN
S_FLASH_CLK
SIO_GPIO21
SIO_GPIO20
SIO_GPIO17
S_FLASH_DOUT
S_FLASH_CE#
SIO_GPIO14
SIO_GPIO13
A
SIO_GPIO10
WD_ACTIVE
VCC5
R28
10K
C153
1uF
R211
R212
0
SIO_GPIO10/WD_ACTIVE
0_NL
22 DSA#
22 WDATA#
22 DIR#
22
22
STEP#
HDSEL#
22
22
22
22
WGATE#
RDATA#
TRK0#
INDEX#
22
22 WP#
DSKCHG#
VCC5SB
VCC5SB
U24
SIO_GPIO62
2
1
6
7
D
CLK
VCC
Q
Q#
CL#
PR# GND
NC7SZ74
8
5
3
4
WD_ACTIVE
DGND
DGND
5
22 MOT0#
56
57
58
59
60
61
62
63
64
65
51
52
53
54
55
31
32
33
34
45
46
48
78
79
84
85
68
24
25
26
27
28
29
30
94
95
96
97
98
90
91
92
93
71
72
73
75
76
77
41
42
43
44
37
38
39
40
47
49
U11
PCICLK
CLKIN
LRESET#
LDRQ#
SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3
SUSB#/GP45
PWRON#/GP44
PME#/GP54
PANSWH#/GP43
PSON#/GP42
SUSC#/GP53
87
88
89
TMPIN3/SO1
TMPIN2
TMPIN1
VREF
VIN7/PCIRSTIN#
VIN6
VIN5
VIN4
VIN3/ATXPG
VIN2
VIN1
VIN0
JSAB2/GP23/SI
JSAB1/GP22/SCK
JSACY/GP21
JSACX/GP20
MIDI_OUT/GP17
MIDI_IN/GP16/SO2
RESETCON#/CIRTX/GP15/CE_N
PCIRST1#/SCRRST/GP14
PWROK1/SCRPFET#/GP13
PCIRST2#/SCRIO/GP12
PCIRST3#/SCRCLK/GP11
KRST#/GP62
GA20
PCIRST5#/GP50
PWROK2/GP41
3VSBSW#/GP40
VID0/GP30
VID1/GP31
VID2/GP32
VID3/GP33
VID4/GP34
VID5/GP35
PCIRST4#/SCRPSNT#/GP10
RSMRST#/CIRRX/GP55
COPEN#
DENSEL#
MTRA#
ETS_DAT/MTRB#
FAN_TAC1
FAN_TAC2/GP52
FAN_TAC3/GP37
FAN_TAC4/JSBCY/GP25
DRVA#
EST_CLK/DRVB#
WDATA#
FAN_TAC5/JSBCX/GP24
FAN_CTL1
FAN_CTL2/GP51
FAN_CTL3/GP36
FAN_CTL4/JSBB2/GP27
FAN_CTL5/JSBB1/GP26
DIR#
STEP#
HDSEL#
WGATE#
RDATA#
TRK0#
MCLK/GP56
MDAT/GP57
KCLK/GP60
KDAT/GP61 INDEX#
WPT#
DSKCHG#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SIN1
SOUT1/JP3
DSR1#
RTS1#/JP2
DTR1#/JP1
CTS1#
DCD1#
RI1#
SIN2/GP63
SOUT2/JP6
DSR2#/GP64
RTS2/JP5
DTR2#/JP4
CTS2#/GP65
DCD2#/GP67
RI2#/GP67
IRRX/GP46
IRTX/GP47
70
66
SLCT
PE
BUSY
ACK#
SLIN#
INIT#
ERR#
AFD#
STB#
100
101
102
103
104
105
106
107
108
3
2
1
6
5
128
126
127
125
124
123
122
121
120
118
119
83
82
81
80
19
18
17
16
14
13
109
110
111
112
113
114
115
116
7
9
11
22
23
8
10
12
20
21
IT8712F
128 pin QFP
SIO_GPIO62
DGND SIO_AGND
D16
C
MMBD4148
A
SYS_RST#
WATCHDOG OUT
4
9,11,25
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
RI1#
RXD1 22
TXD1 22
DSR1# 22
RTS1# 22
DTR1# 22
CTS1# 22
DCD1# 22
RXD2 22
TXD2 22
DSR2# 22
RTS2# 22
DTR2# 22
CTS2# 22
DCD2# 22
RI2#
SIO_GPIO46
SIO_GPIO47
SIO_GPIO30
SIO_GPIO31
SIO_GPIO32
SIO_GPIO33
SIO_GPIO34
SIO_GPIO35
FAN_TAC
SIO_GPIO52
SIO_GPIO37
SIO_GPIO25
SIO_GPIO24
FAN_CNTL
SIO_PWM2
SIO_PWM3
SIO_PWM4
SIO_PWM5
SLCT 23
PE 23
BUSY 23
ACK# 23
SLIN# 23
PRNINIT# 23
ERR# 23
AFD# 23
STB# 23
PD[0:7] 23
MSCLK 23
MSDAT 23
KBCLK 23
KBDAT 23
3
12V
VCC5
1
3
J27
9 TDP
9 TDN
PFL-1x3
FAN_CNTL
Q5
BSS138/SOT
SIO_ADC_VREF
R195 30K
SIO_BOARDTEMP
C336
1.5nF
SIO_PWM2
SIO_PWM3
SIO_PWM4
SIO_PWM5
SIO_ADC0
SIO_ADC1
SIO_ADC2
SIO_ADC3
SIO_ADC4
SIO_ADC5
SIO_ADC6
SIO_ADC7
SIO_ADC_VREF
VCC3
C335
1uF
DGND
Q11
MMBT3904/SOT
C219
1
220pF
1
FB16
2
BLM18PG600SN1
DGND SIO_AGND
SIO_ADC_VREF
2
R190
0
Fan Control
R194
470
DGND
SIO_AGND
R125 30K
C220
1nF
C221
1nF
Q6
SI2307DS
VCC5
TDP
FAN_TAC
23
25
27
29
31
33
35
37
39
11
13
15
17
19
21
5
7
9
1
3
SIO_AGND
DGND
R193
10K
FAN_TAC
J12
S1
S2
S3
S4
S5
S6
2
3
2
1
J11
AMP-640456-3
VCC5
24
26
28
30
32
34
36
38
40
12
14
16
18
20
22
2
4
6
8
10
VCC5
PFL-2x20-2M0-SMD-S
DGND SIO_AGND DGND
RI1#
RI2#
DTR1#
RTS1#
TXD1
DTR2#
RTS2#
TXD2
D15
MMBD4148
SIO STRAPING
1
R192 10K
1
R191 10K
1
R128
1
1K
R113
1
R114
1
10K
10K_NL
R115
1
R116
1
R117
1
R118
10K_NL
10K_NL
10K_NL
10K_NL
VCC3
R110 10K
R111 10K
S_FLASH_DIN
S_FLASH_DOUT
S_FLASH_CE#
S_FLASH_CLK
DGND
SIO_GPIO10
SIO_GPIO13
SIO_GPIO14
SIO_GPIO17
SIO_GPIO20
SIO_GPIO21
SIO_GPIO24
SIO_GPIO25
SIO_GPIO30
SIO_GPIO31
SIO_GPIO32
SIO_GPIO33
SIO_GPIO34
SIO_GPIO35
SIO_GPIO37
VCC5
DGND
R112 10K_NL
VCC3SB
VCC3
23
25
27
29
31
33
35
37
39
11
13
15
17
19
21
5
7
9
1
3
5
2
1
6
3
7
J13
S4 - Not used, Default=1
S6 - Not used, Default=1
24
26
28
30
32
34
36
38
40
12
14
16
18
20
22
2
4
6
8
10
U10
Vcc
8
SI
SO
CE#
CLK
WP#
HLD# GND
SST25LF080A
4
SPI FLASH
DGND
VCC5
DGND
PFL-2x20-2M0-SMD-S
DGND
DRB
JP-1x2_NL
J18
VCC5
VCC3
SIO_GPIO40
SIO_GPIO41
SIO_GPIO42
SIO_GPIO43
SIO_GPIO44
SIO_GPIO45
SIO_GPIO46
SIO_GPIO47
SIO_GPIO50
SIO_GPIO52
SIO_GPIO53
CS5536_GPIO25 11
CS5536_GPIO9 11
CS5536_GPIO8 11
CS5536_GPIO6 11
DESIGN NOTE: Install DRB jumper when booting from Disaster Recovery
Board. Install the DRB into J8, LPC
Header.
DESIGN NOTE: Explanation of straps on SIO
S1 - SPI Flash - 0=enable, 1=disable, Default=0
S2 - SPI Flash Data out - 0=SD1, 1=SD2, Default=1
S3 - See chip ID Byte 2, Not used, Default=1
S5 - Fan Control EC index - 0=00h, 1=40h, Default=1
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number Rev
40744 D
Size Date: Sheet
B Wednesday, April 11, 2007
17
of
26
1
D
C
B
A
D
C
B
A
15
15
TXP1
TXM1
15
15
RXP1
RXM1
5
R119
49.9,1%
R120
49.9,1%
R122
49.9,1%
R121
49.9,1%
12 USB0+
C224
100nF
L4
CMF-3216-0090A-N2
1 2
DGND
C225
100nF
VCC3
R1001
DGND
VCC_USB0
R1002
220
15 P1LED2
220
15 P1LED3
12 USB0-
12 USB1+
4 3
L5
CMF-3216-0090A-N2
1 2
VCC_USB1
12 USB1-
4 3 SS2 SS1 SS4
SS3
DESIGN NOTE: Place
ESD protection components as close to the USB/Ethernet connector as possible.
DGND
FB19
HI1206N101R-00
DESIGN NOTE: When uDOC is used USB2 is not available.
15
15
TXP2
TXM2
15
15
RXP2
RXM2
R131
49.9,1%
R132
49.9,1%
R133
49.9,1%
R134
49.9,1%
FB20
HI1206N101R-00
DGND
C237
USB2_CON+
100nF
L6
CMF-3216-0090A-N2
1 2
DGND
C238
100nF
VCC3
R1003
DGND
VCC_USB2
R1004
220
15
220
P2LED2
15 P2LED3
12
USB2_CON-
USB3+
4 3
L7
CMF-3216-0090A-N2
1 2
VCC_USB3
12 USB3-
4 3
SS6 SS5 SS8 SS7
4 3
J14
10
9
11
+TX
TCT
-TX
12
14
13
+RX
RCT
-RX
16
15
+LED1
-LED1
18
17
+LED2
-LED2
1
3
2
4
5
7
6
8
VCC1
+DATA1
-DATA1
GND1
VCC2
+DATA2
-DATA2
GND2
SHD
SHD
SHD
SHD
SHD
SHD
SHD
SHD
CON-COMBO-USB2-ETH1
26
25
24
23
22
21
20
19
VCC3V_LAN
DESIGN NOTE:
Reg. SGCR5 bit [15,9] =[1,0]
LED3 = Act
LED2 = Link
FB1000
MLB-201209-0120P-N2
C1000
100nF_NL
DGND
1
C230
220pF
FB21
MLB-201209-0120P-N2
1 2
12 USB_PWR_EN1
12 USB_OC#
DGND LAN_CHASSIS
LAN_CHASSIS
VCC3V_LAN
J15
10
9
11
+TX
TCT
-TX
12
14
13
+RX
RCT
-RX
16
15
+LED1
-LED1
18
17
+LED2
-LED2
1
3
2
4
5
7
6
8
VCC1
+DATA1
-DATA1
GND1
VCC2
+DATA2
-DATA2
GND2
SHD
SHD
SHD
SHD
SHD
SHD
SHD
SHD
CON-COMBO-USB2-ETH1
26
25
24
23
22
21
20
19
FB1001
MLB-201209-0120P-N2
C1002
100nF_NL
DGND
LAN_CHASSIS
12 USB_PWR_EN2
5
DGND
FB24
HI1206N101R-00
FB25
HI1206N101R-00
DGND
4 3
VCC3
R123
10K
R124
10K
C223
100nF
DGND
7
U12
IN
4
3
ENB
FLGB
1
2
ENA
FLGA
LM3526H
OUTB
5
OUTA
8
GND
6
1
FB18
HI1206N101R-00 VCC_USB1
FB17
HI1206N101R-00 VCC_USB0
1
D
DGND
C226
100uF
C227
470pF
C228
100uF
C229
470pF
VCC3
R129
10K
2
VCC5
VCC5 DGND
C231
100nF
DGND
1
2
4
3
7
U13
IN
ENB
FLGB
ENA
FLGA
LM3526H
OUTB
OUTA
5
8
GND
6
1
FB23
HI1206N101R-00
C233
100uF
VCC_USB3
1
FB22
HI1206N101R-00
C234
470pF
C235
100uF
VCC_USB2
C236
470pF
DGND
C
DGND
1
DESIGN NOTE: Do not violate USB 2.0 routing requirements when routing USB2.
VCC5
12
12
USB2-
USB2+
J16
1
3
5
7
9
VCC5
I
I
USB-
USB+
NC
O
O
GND
KEY
NC
NC
2
4
6
8
10
USB2_CON-
USB2_CON+ uDOC
DGND
M-Systems uDOC Connector
DESIGN NOTE: Jumper pins 3 & 4, 5 & 6 when uDOC is not used.
DESIGN NOTE: Pin 9 on header should be cut off.
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
18
of
26
1
A
B
D
C
B
A
5
DESIGN NOTE: Route PCI CLOCK trace 1.5
inches shorter than other PCI clocks. Length of PCI clock on MiniPCI cards will typically be 1.5 inches. Confirm with card manufacturer.
9,11,15,20,24 PCI_AD[31:0]
5
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
4
9,11,24 PCI_INTA#
9 CLK_EXT1
9 REQ#_MPCI
9,11,15,20,24 PCI_C/BE3#
9,11,15,20,24
9,11,15,20,24
PCI_C/BE2#
PCI_IRDY#
9,11,15,20,24 PCI_C/BE1#
4
3 2 1
VCC5 VCC3 VCC3
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25
PCI_AD23
PCI_AD21
PCI_AD19
PCI_AD17
PCI_SERR#
PCI_PERR#
PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1
DGND
J17
1
TIP
87
89
91
93
95
97
75
77
79
81
83
85
63
65
67
69
71
73
51
53
55
57
59
61
111
113
115
117
119
121
123
99
101
103
105
107
109
39
41
43
45
47
49
27
29
31
33
35
37
15
17
19
21
23
25
9
11
13
3
5
7
AD23
GND
AD21
AD19
GND
AD17
C/BE2#
IRDY#
3.3V
CLKRUN#
SERR#
GND
PERR#
C/BE1#
AD14
GND
AD12
AD10
GND
AD8
AD7
3.3V
AD5
RESERVED
RD+
RD-
TERMINATION
TERMINATION
LED1_GRNP
LED1_GRNN
CHSGND
INTB#
3.3V
RESERVED
GND
CLK
GND
REQ#
3.3V
AD31
AD29
GND
AD27
AD25
RESERVED
C/BE3#
AD3
5V
AD1
GND
AC_SYNC
AC_SDATA_IN
AC_BIT_CLK
AC_CODEC_ID1#
MOD_AUDIO_MON
AUDIO_GND
SYS_AUDIO_OUT
SYS_AUDIO_OUT_GND
AUDIO_GND
RESERVED
VCC5VA
RING
2
88
90
92
94
96
98
76
78
80
82
84
86
64
66
68
70
72
74
52
54
56
58
60
62
112
114
116
118
120
122
124
100
102
104
106
108
110
40
42
44
46
48
50
28
30
32
34
36
38
16
18
20
22
24
26
4
6
8
10
12
14
AD0
RESERVED_WIP
RESERVED_WIP
GND
M66EN
AC_SDATA_OUT
AC_CODEC_ID0#
AC_RESET#
RESERVED
GND
SYS_AUDIO_IN
SYS_AUDIO_IN_GND
AUDIO_GND
MPCIACT#
3.3VAUX
IDSEL
GND
AD22
AD20
PAR
AD18
AD16
GND
FRAME#
TRDY#
STOP#
3.3V
DEVSEL#
GND
AD15
AD13
AD11
GND
AD9
C/BE0#
3.3V
AD6
AD4
AD2
TD+
TD-
TERMINATION
TERMINATION
LED2_YELP
LED2_YELN
RESERVED
5V
INTA#
RESERVED
3.3VAUX
RESET#
3.3V
GNT#
GND
PME#
RESERVED
AD30
3.3V
AD28
AD26
AD24
PCITYPEIII
DGND
VCC3SB
PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24
R135 100
PCI_AD22
PCI_AD20
PCI_AD18
PCI_AD16
PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
VCC3SB
PCI_INTB# 11,15,24
PCI_RST# 9,11,12,15,16,17,20,24,25
C244
22uF
GNT#_MPCI 9
PME# 11,15,17,25
PCI_AD23
PCI_PAR
PCI_FRAME#
PCI_TRDY#
9,11,15,20,24
9,11,15,20,24
9,11,15,20,24
PCI_STOP# 9,11,15,20,24
PCI_DEVSEL#
PCI_C/BE0#
9,11,15,20,24
9,11,15,20,24
C239
22uF
C240
100nF
PCI_PERR#
PCI_SERR#
C241
100nF
C242
100nF
C245
100nF
C246
100nF
R136 10K
R137 10K
C243
100nF
DGND
VCC5
C247
100nF
DGND
VCC3
DESIGN NOTE: Consult MiniPCI card manufacturer for any special design or layout considerations of MiniPCI slot to accomidate a particular MiniPCI card.
3 2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
19
of
26
1
D
C
B
A
National Semiconductor Confidential
5 4
VCC3 VCC5
9,11,15,19,24 PCI_AD[31:0]
D
C
VCC3
DESIGN NOTE: Install in order to disable the bridge. This is a temporary measure.
R208
10K_NL
PCI_AD22
R139 33
B
9,11,15,19,24
9,11,15,19,24
9,11,15,19,24
9,11,15,19,24
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
9
9
REQ_EXT0#
GNT_EXT0#
9,11,15,19,24
9,11,15,19,24
9,11,15,19,24
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
9,11,15,19,24
9,11,15,19,24
PCI_TRDY#
PCI_STOP#
9,11,15,19,24
9,11,12,15,16,17,19,24,25
PCI_PAR
PCI_RST#
9 CLK_EXT0
24
12,17 SERIRQ
ISA_IRQ[7:3]
24 ISA_IRQ[12:9]
24 ISA_IRQ[15:14]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
H3
E1
B2
A4
CBE0#
CBE1#
CBE2#
CBE3#
C8
B8
IREQ#
IGNT#
D3
C2
B1
E4
D2
E2
B9
A9
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PCIRST
PCICLK
C9
SERIRQ
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
IDSEL
C3
B3
A2
A3
C4
C5
G2
G3
F1
F2
F3
A1
J3
J2
J1
H2
H1
G1
M1
L1
K3
K2
K1
B7
A7
A8
B5
B4
A5
C6
B6
A6
C7
ISA_IRQ3
ISA_IRQ4
ISA_IRQ5
ISA_IRQ6
ISA_IRQ7
ISA_IRQ9
ISA_IRQ10
ISA_IRQ11
ISA_IRQ12
ISA_IRQ14
ISA_IRQ15
P7
M7
P6
N6
M6
P5
P9
M8
N8
P8
N7
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
L2
K4
SDATA
SCLK
A
U14
IT8888G
3
DACK7# 24
DACK6# 24
DACK5# 24
DACK3# 24
DACK2# 24
DACK1# 24
DACK0# 24
ISA_SA0
ISA_SA1
ISA_SA2
ISA_SA3
ISA_SA4
ISA_SA5
ISA_SA6
ISA_SA7
ISA_SA8
ISA_SA9
ISA_SA10
ISA_SA11
ISA_SA12
ISA_SA13
ISA_SA14
ISA_SA15
ISA_SA16
ISA_SA17
ISA_SA18
ISA_SA19
ISA_LA20
ISA_LA21
ISA_LA22
ISA_LA23
ISA_SD0
ISA_SD1
ISA_SD2
ISA_SD3
ISA_SD4
ISA_SD5
ISA_SD6
ISA_SD7
ISA_SD8
ISA_SD9
ISA_SD10
ISA_SD11
ISA_SD12
ISA_SD13
ISA_SD14
ISA_SD15
ISA_MEMR#
ISA_MEMW#
ISA_SMEMR#
ISA_SMEMW#
ISA_SBHE#
ISA_IOR#
ISA_IOW#
ISA_MEMCS16#
ISA_IOCS16#
ISA_IOCHRDY
ISA_BALE
ISA_AEN
ISA_IOCHCK#
ISA_MASTER#
ISA_REFRESH#
ISA_RSTDRV
ISA_NOWS#
ISA_TC
ISA_BCLK
DRQ7
DRQ6
DRQ5
DRQ3
DRQ2
DRQ1
DRQ0
MEMR#
MEMW#
SMEMR#
SMEMW#
SBHE#
IOR#
IOW#
MEMCS16#
IOCS16#
IOCHRDY
BALE
AEN
IOCHK#
MASTER#
REFRESH#
RSTDRV
NOWS#
TC
BCLK
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD0
SD1
SD2
SD3
SD4
SD5
LA20
LA21
LA22
LA23
K14
J12
J13
J14
H12
H13
L12
L13
M14
L14
K12
K13
H14
G14
G13
G12
E12
B14
C14
E11
DRQ7
DRQ6
DRQ5
DRQ3
DRQ2
DRQ1
DRQ0
F14
F13
F12
E14
E13
D14
F11
D13
A14
C12
B12
A13
A12
C11
C10
B11
D12
B13
C13
D11
M12
M9
N10
P12
P13
N12
P11
N11
P10
N1
N13
N9
M10
P14
N14
L11
M11
K11
M13
M4
N3
N4
P3
P4
M5
N5
DGND
3
ISA_SD[15:0] 24
ISA_SA[19:0] 24
ISA_AEN
ISA_BALE
ISA_TC
ISA_LA[23:20] 24
ISA_MEMR# 24
ISA_MEMW# 24
ISA_SMEMR# 24
ISA_SMEMW# 24
ISA_SBHE# 24
ISA_IOR# 24
ISA_IOW# 24
ISA_MEMCS16# 24
ISA_IOCS16#
ISA_IOCHRDY
ISA_BALE 24
ISA_AEN 24
24
24
ISA_IOCHCK# 24
ISA_MASTER# 24
ISA_REFRESH#
ISA_RSTDRV 24
24
ISA_TC
ISA_BCLK
24
24
DRQ[7:5] 24
DRQ[3:0] 24
2 1
VCC5
VCC3
C254
22uF
VCC5
C249
22uF
C255
10nF
C250
10nF
DRQ1
DRQ3
DRQ0
DRQ5
DRQ7
DRQ6
DRQ2
2
C256
10nF
C251
10nF
C257
10nF
C252
10nF
C258
10nF
DGND
C253
10nF
DGND
R138 10K
R140 10K
R141 10K
DGND
DESIGN NOTE: Configuration Straps
AEN - 1 = Factory Test
0 = Normal operation
BALE - 1 = Positive decode on BIOS address range
0 = BIOS address range disabled
TC - 1 = Enable SMB Boot ROM Configuration
0 = Disabe SMB Boot ROM Configuration
ISA_SA1
ISA_SA0
ISA_SA3
ISA_SA2
ISA_SA5
ISA_SA4
ISA_SA7
ISA_SA6
ISA_SA9
ISA_SA8
ISA_SA11
ISA_SA10
ISA_SA12
ISA_MEMW#
ISA_MASTER#
ISA_MEMR#
ISA_SA14
ISA_SA13
ISA_SA16
ISA_SA15
ISA_LA20
ISA_SA17
ISA_IOR#
ISA_IOW#
ISA_SA18
ISA_LA21
ISA_LA22
ISA_SA19
ISA_SMEMR#
ISA_IOCS16#
ISA_LA23
ISA_SMEMW#
ISA_MEMCS16#
ISA_SBHE#
ISA_IOCHRDY
ISA_IOCHCK#
1
2
3
4
10K
1
2
3
4
10K
1
2
3
4
10K
1
2
3
4
10K
1
2
3
4
10K
1
2
3
4
10K
1
2
3
4
10K
1
2
3
4
10K
1
2
3
4
10K
RN47
8
7
6
5
RN46
8
7
6
5
RN45
8
7
6
5
RN49
8
7
6
5
RN48
8
7
6
5
RN55
8
7
6
5
RN51
8
7
6
5
RN57
8
7
6
5
RN52
8
7
6
5
ISA_NOWS#
R210 10K
1
2
3
4
10K
1
2
3
4
10K
RN50
8
7
6
5
RN53
8
7
6
5
BRDG_SERR#
BRDG_PERR#
BRDG_LOCK#
BRDG_CLKRUN#
BRDG_PPREQ#
BRDG_PPGNT#
1
2
3
4
10K
1
2
3
4
10K
RN56
8
7
6
5
RN58
8
7
6
5
VCC3
R149 10K
DGND
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
20
of
26
1
D
C
B
A
5 4
A
5 4 3 2
D
C
B
12 IDE_D[15:0]
VCC3 VCC5
R142
0_NL
R143
0
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
12 IDE_RST#
12
12
12
12
12
IDE_DRQ#
IDE_IOW#
IDE_IOR#
IDE_RDY#
IDE_ACK#
12
12
IDE_IRQ
IDE_A1
12
12 IDE_A0
IDE_CS0#
IDE CONNECTOR
IDE_LED
JHDD1
27
29
31
33
35
37
39
41
43
15
17
19
21
23
25
9
11
13
1
3
5
7
GND
GND
ALE
GND
IOCS16
NC
A2
CS1
GND
VCC
NC
GND
D8
D9
D10
D11
D12
D13
D14
D15
NC
GND
IOW
IOR
NC
DACK
IRQ
A1
A0
CS0
LED
VCC
GND
RST
D7
D6
D5
D4
D3
D2
D1
D0
GND
DRQ
PFL-2x22-2M0-SMD-S
28
30
32
34
36
38
40
42
44
16
18
20
22
24
26
2
4
6
8
10
12
14
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
R188 470
IDE_A2 12
IDE_CS1# 12
R144
10K_NL
C259
47nF_NL
DGND
IDE_CABLEID# 11
DGND DGND
UDMA
YELLOW
VCC5
R189
560
D11
LTST-C190YKT
IDE_LED 11
1
D
C
B
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
21
of
26
1
A
5 4 3
D
C
B
A
5
VCC5
17 RS485_EN1
C263
100nF
C260
100nF
NRX1
NDSR1#
DGND
NCTS1#
NDCD1#
17
17
TXD1
RTS1#
17 DTR1#
C264
100nF
R187
10K
U15
VCC5
1
2
28
27
3
15
21
20
8
9
13
12
4
5
A1
B1
A2
B2
22
23
DY1
DZ1/DE1
19
18
DY2
DZ2/DE2
C1+
C1-
C2+
C2-
VDD
VEE
LB
ON/OFF
SEL1
SEL2
RA1
RB1
RA2
RB2
Y1
Z1
Y2
Z2
6
7
11
10
24
25
17
16
C262
100nF
C261
100nF
LTC1334
DGND
DGND
VCC5
4
RXD1
DSR1#
CTS1# 17
DCD1# 17
NTX1
NRTS1#
NDTR1#
NRTS11#
17
17
17 RS485_EN2
C284
100nF
C285
100nF
C273
100nF
NRX2
NDSR2#
DGND
17
17
17
R186
10K
NCTS2#
NDCD2#
TXD2
RTS2#
DTR2#
U16
VCC5
1
2
28
27
3
15
21
20
8
9
4
5
A1
B1
13
12
A2
B2
22
23
DY1
DZ1/DE1
19
18
DY2
DZ2/DE2
C1+
C1-
C2+
C2-
VDD
VEE
LB
ON/OFF
SEL1
SEL2
RA1
RB1
RA2
RB2
Y1
Z1
Y2
Z2
24
25
17
16
6
7
11
10
LTC1334
C275
100nF
C274
100nF
DGND
VCC5
DGND
RXD2 17
DSR2# 17
CTS2# 17
DCD2# 17
NTX2
NRTS2#
NDTR2#
NRTS22#
NTX1
NRX1
NTX2
NRX2
5
R145
1K
DGND
R182 120
R183 120
R184 120
R185 120
R146
1K
1
3
5
7
J26
2
4
6
8
R147
1K
R148
1K
NRTS1#
NDSR1#
NRTS2#
NDSR2#
PFL-2x4-2M0-SMD-S
DESIGN NOTE: Jumpers for RS485 termination
Install jumpers on 1-2 and 3-4 for COM1
Install jumpers on 5-6 and 7-8 for COM2
4
VCC5
R154 4.7K
R153 4.7K
R152 4.7K
R151 4.7K
R150 4.7K
17 INDEX#
17 DSA#
17 DSKCHG#
17 MOT0#
17 DIR#
17 STEP#
17 WDATA#
17 WGATE#
17 TRK0#
17 WP#
17 RDATA#
17 HDSEL#
3
3
1
DGND
1
C339
220pF
FB35
BLM18PG600SN1
C_CHASSIS
2 1
COM1
NRTS11#
NDTR1#
NCTS1#
NTX1
NRTS1#
NRX1
NDSR1#
NDCD1#
B5
B9
B4
B8
B3
B7
B2
B6
B1
P1B
CON-COMBO-DB9-15-25-TRIPLEPORT
D
C265
220pF
C266
220pF
C267
220pF
C268
220pF
C269
220pF
C270
220pF
C271
220pF
C272
220pF
DGND C_CHASSIS
DGND
VCC5
COM2
NRTS22#
NDTR2#
NCTS2#
NTX2
NRTS2#
NRX2
NDSR2#
NDCD2#
5
7
9
1
3
J19
2
4
6
8
10
PFL-5x2-2M54-SMD-S
C
C276
220pF
C277
220pF
C278
220pF
C279
220pF
C280
220pF
C281
220pF
C282
220pF
C283
220pF
DGND
DGND
FDD CNT
VCC5
J20
20
21
22
23
24
25
26
14
15
16
17
18
19
8
9
10
11
12
13
5
6
7
1
2
3
4
HRS-FH10-26
DGND
2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
Size
B
Date:
Wednesday, April 11, 2007
Sheet
22
D
1 of
26
A
B
D
5 4 3
DESIGN NOTE:
Place these three series resistor components close to the Super IO.
VCC5
D12
1 2
MBRS340T3
A
C
B
SUPER I/O
KEYBOARD/MOUSE
VCC5SB
VCC5 VCCKB
FB26
HI1206N101R-00
R156 0
R157 0_NL
F2 1.10A, 33V
1 1
C286
22uF
R27 R26 R25 R24
17 KBDAT
17 KBCLK
17 MSDAT
17 MSCLK
FB27 BLM18PG600SN1
1
FB28 BLM18PG600SN1
1
FB29 BLM18PG600SN1
1
FB30 BLM18PG600SN1
1
4.7K
4.7K
4.7K
4.7K
DGND
C287
100nF
C294
220pF
C293
220pF
C292
220pF
C291
220pF
DGND
17 PD[0:7]
PD[0:7]
17
17
17
17
SLCT
PE
BUSY
ACK#
17 SLIN#
17 PRNINIT#
17 ERR#
17
17
AFD#
STB#
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
4
3
2
1
RN65
33
4
3
2
1
RN64
33
4
3
2
1
RN63
33
5
6
7
8
5
6
7
8
5
6
7
8
1
2
3
4
5
6
7
8
9
10
11
12
P2 violet
4
5
6
1
2
3
7
8
9
10
11
12 green
SHLD
SHLD
SHLD
SHLD
SHLD
CON-MINI-6P/2-C
13
14
15
16
17
KB_CHASSIS
1
DGND
1 C290
220pF
FB32
BLM18PG600SN1
KB_CHASSIS
DGND
1
DGND
1 C289
220pF
FB31
BLM18PG600SN1
P_CHASSIS
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number Rev
40744
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
23
of
26
1 2
A
B
5 4 3
2 1
RN59
4.7K
RN60
4.7K
RN61
4.7K
RN62
R155
4.7K
4.7K
DGND
D
A13
A25
A12
A24
A11
A23
A10
A22
A9
A21
A8
A20
A7
A19
A6
A18
A5
A17
A4
A16
A3
A15
A2
A14
A1
P1A
P_CHASSIS
C
D
C
B
A
20 ISA_IOCHCK#
20 ISA_SD[15:0]
20 ISA_IOCHRDY
20 ISA_AEN
20 ISA_SA[19:0]
20 ISA_LA[23:20]
20 ISA_SBHE#
ISA_SA[19:0]
20
20
ISA_MEMR#
ISA_MEMW#
ISA_SD[15:0]
20 ISA_IRQ[7:3]
20 ISA_IRQ[12:9]
20 ISA_IRQ[15:14]
5
ISA_SD[15:0]
ISA_IRQ3
ISA_IRQ4
ISA_IRQ5
ISA_IRQ6
ISA_IRQ7
ISA_IRQ9
ISA_IRQ10
ISA_IRQ11
ISA_IRQ12
ISA_IRQ14
ISA_IRQ15
5
ISA_SD7
ISA_SD6
ISA_SD5
ISA_SD4
ISA_SD3
ISA_SD2
ISA_SD1
ISA_SD0
ISA_SA19
ISA_SA18
ISA_SA17
ISA_SA16
ISA_SA15
ISA_SA14
ISA_SA13
ISA_SA12
ISA_SA11
ISA_SA10
ISA_SA9
ISA_SA8
ISA_SA7
ISA_SA6
ISA_SA5
ISA_SA4
ISA_SA3
ISA_SA2
ISA_SA1
ISA_SA0
DGND
ISA_LA23
ISA_LA22
ISA_LA21
ISA_LA20
ISA_SA19
ISA_SA18
ISA_SA17
ISA_SD8
ISA_SD9
ISA_SD10
ISA_SD11
ISA_SD12
ISA_SD13
ISA_SD14
ISA_SD15
A18
A19
A20
A21
A22
A23
A12
A13
A14
A15
A16
A17
A6
A7
A8
A9
A10
A11
A0
A1
A2
A3
A4
A5
A24
A25
A26
A27
A28
A29
A30
A31
A32
J21B
SD10
SD11
SD12
SD13
SD14
SD15
KEY reserved reserved reserved reserved reserved
GND
SBHE#
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MEMR#
MEMW#
SD8
SD9 reserved reserved reserved reserved reserved reserved reserved reserved
PC-104
C18
C19
C20
C21
C22
C23
C12
C13
C14
C15
C16
C17
C6
C7
C8
C9
C10
C11
C0
C1
C2
C3
C4
C5
C24
C25
C26
C27
C28
C29
C30
C31
C32
20 DRQ[7:5]
20 DRQ[3:0]
J21A
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
GND reserved
IOCHCHK#
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19 reserved
GND
RESETDRV
VCC5
IRQ9
VCC5NEG
DRQ2
V12NEG
ENDXFR#
V12POS
KEY
SMEMW#
SMEMR#
IOW#
IOR#
DACK3#
DRQ3
DACK1#
DRQ1
REFRESH#
SYSCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2#
TC
BALE
VCC5
OSC
GND
GND
PC-104
DRQ7
DRQ6
DRQ5
DRQ3
DRQ2
DRQ1
DRQ0
GND
MEMCS16#
IOCS16#
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DACK0#
DRQ0
DACK5#
DRQ5
DACK6#
DRQ6
DACK7#
DRQ7
VCC5
MASTER#
GND
GND reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
B18
B19
B20
B21
B22
B23
B12
B13
B14
B15
B16
B17
B6
B7
B8
B9
B10
B11
B0
B1
B2
B3
B4
B5
B24
B25
B26
B27
B28
B29
B30
B31
B32
D18
D19
D20
D21
D22
D23
D12
D13
D14
D15
D16
D17
D6
D7
D8
D9
D10
D11
D0
D1
D2
D3
D4
D5
D24
D25
D26
D27
D28
D29
D30
D31
D32
4
VCC5
-12V
DGND
12V
ISA_IRQ9
DACK3#
DRQ3
DACK1#
DRQ1
ISA_IRQ7
ISA_IRQ6
ISA_IRQ5
ISA_IRQ4
ISA_IRQ3
DACK2#
DRQ2
ISA_IRQ10
ISA_IRQ11
ISA_IRQ12
ISA_IRQ15
ISA_IRQ14
DACK0#
DRQ0
DACK5#
DRQ5
DACK6#
DRQ6
DACK7#
DRQ7
ISA_RSTDRV 20
ISA_SMEMW# 20
ISA_SMEMR# 20
ISA_IOW# 20
ISA_IOR# 20
ISA_REFRESH#
ISA_BCLK 20
ISA_TC 20
ISA_BALE 20
CLK_14_ISA 13
ISA_MEMCS16# 20
ISA_IOCS16# 20
ISA_MASTER# 20
20
3 2
9
13
1
FB33
BLM18PG600SN1
PC_REQ0#
PC_REQ1#
PC_REQ2#
GNT0#
PCI_FRAME#
PCI_STOP#
PCI_RST#
PC_CLK
PC_CLKFB
VCC3
DGND
13
5
8
11
4
1
2
26
27
DESIGN NOTE: PC_CLK3 trace must be ~17mm less than PC_CLK2.
PC_CLK2 trace must be ~17mm less than PC_CLK1. PC_CLK1 trace must be ~17mm less than PC_CLK0.
R158 0
U17
R159 10K
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI104_LOCK#
PCI104_PERR#
PCI104_SERR#
PC_REQ2#
PC_REQ1#
PC_REQ0#
14
VCC3 VCC3_EXT2
NC
REQ1
REQ2
REQ3
S_GNT
FRAME
STOP
RESET
CLKIN
NC
2
DGND
1
2
3
4
1
2
3
4
C295
10uF
33
10K
C296
100nF
GNT1
GNT2
GNT3
S_REQ
CLKFB
CLK1
CLK2
CLK3
CLK4
8
7
6
5
8
7
6
5
R207 10K
R180 10K
NC
NC
GND_EXT2
RN66
RN67
VCC3_EXT2
GND_EXT2
16
7
10
12
3
23
22
20
19
18
15
C297
100nF
ITE IT8209R
PC_GNT0#
PC_GNT1#
PC_GNT2#
REQ0# 9
PC_CLKFB
PC_CLK0
PC_CLK1
PC_CLK2
PC_CLK3
PC_IDSEL0
PC_IDSEL1
PC_IDSEL2
PC_IDSEL3
VCC3
9,11,15,19,20
9,11,15,19,20
9,11,15,19,20
-12V
12V
PCI_AD5
PCI_C/BE0#
PCI_AD11
PCI_AD14
PCI104_SERR#
PCI_STOP#
PCI_FRAME#
PCI_AD18
PCI_AD21
PC_IDSEL0
PCI_AD24
PCI_AD29
PC_REQ0#
PC_GNT1#
PC_CLK2
VCC5
VCC3_EXT
J22A
GND
VI/O
AD05
C/BE0#
GND
AD11
AD14
VCC3
SERR#
GND
STOP#
VCC3
FRAME#
GND
AD18
AD21
VCC3
IDSEL0
AD24
GND
AD29
VCC5
REQ0#
GND
GNT1#
VCC5
CLK2
GND
V12POS
V12NEG
PCI-104
A18
A19
A20
A21
A22
A23
A12
A13
A14
A15
A16
A17
A24
A25
A26
A27
A28
A29
A30
A6
A7
A8
A9
A10
A11
A1
A2
A3
A4
A5
GND
AD16
VCC3
AD20
AD23
GND
C/BE3#
AD26
VCC5
AD30
GND
REQ2# reserved
AD02
GND
AD07
AD09
VI/O
AD13
C/BE1#
GND
PERR#
VCC3
TRDY#
VI/O
CLK0
VCC5
INTD#
INTA#
REQ3#
9,11,15,19,20
11,15,19
9
PCI_AD1
PCI_AD4
PCI_AD8
PCI_AD10
PCI_AD15
PCI104_LOCK#
PCI_IRDY#
PCI_AD17
PCI_AD22
PC_IDSEL1
PCI_AD25
PCI_AD28
PC_REQ1#
PC_GNT2#
PC_CLK3
PCI_INTB#
GNT#_PC3
J22B
C18
C19
C20
C21
C22
C23
C12
C13
C14
C15
C16
C17
C24
C25
C26
C27
C28
C29
C30
C6
C7
C8
C9
C10
C11
C1
C2
C3
C4
C5
AD00
VCC5
AD03
AD06
GND
M66EN
AD12
VCC3
PAR reserved
GND
DEVSEL#
VCC3
C/BE2#
GND
AD19
VCC3
IDSEL2
IDSEL3
GND
AD27
AD31
VI/O
GNT0#
GND
CLK1
GND
RST#
INTC#
GND
IRDY#
VCC3
AD17
GND
AD22
IDSEL1
VI/O
AD25
AD28
GND
REQ1#
VCC5
VCC5
AD01
AD04
GND
AD08
AD10
GND
AD15 reserved
VCC3
LOCK#
GND
GNT2#
GND
CLK3
VCC5
INTB#
GNT3#
PCI-104
R181 10K
DGND
9,11,15,19,20 PCI_AD[31:0]
20
20
20
20
20
20
20
DACK7#
DACK6#
DACK5#
DACK3#
DACK2#
DACK1#
DACK0#
4
DACK7#
DACK6#
DACK5#
DACK3#
DACK2#
DACK1#
DACK0#
3
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
2
D18
D19
D20
D21
D22
D23
D12
D13
D14
D15
D16
D17
D24
D25
D26
D27
D28
D29
D30
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
B18
B19
B20
B21
B22
B23
B12
B13
B14
B15
B16
B17
B24
B25
B26
B27
B28
B29
B30
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
VCC3_EXT
DGND
1
PCI_AD2
PCI_AD7
PCI_AD9
PCI_AD13
PCI_C/BE1#
PCI104_PERR#
PCI_TRDY#
PCI_AD16
PCI_AD20
PCI_AD23
PCI_C/BE3#
PCI_AD26
PCI_AD30
PC_REQ2#
PC_CLK0
PCI_INTD#
PCI_INTA#
11
9,11,19
REQ#_PC3 9
VCC5
PCI_AD0
PCI_AD3
PCI_AD6
PCI_AD12
PCI_PAR 9,11,15,19,20
PCI_DEVSEL# 9,11,15,19,20
PCI_C/BE2#
PCI_AD19
PC_IDSEL2
PC_IDSEL3
PCI_AD27
PCI_AD31
PC_GNT0#
PC_CLK1
9,11,15,19,20
9,11,15,19,20
9,11,15,19,20
9,11,15,19,20
PCI_RST#
PCI_INTC#
9,11,12,15,16,17,19,20,25
11
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Rev Document Number
Size
B
40744
Date:
Wednesday, April 11, 2007
Sheet
24
D
of
26
1
D
C
B
A
D
C
B
A
11 WORK_AUX
5
VCC5
WORK_AUX
R160 10K
C303
1uF
C304
100nF
C300
47uF
4
R161 75K
C305
1nF
U18
1
VIN
6
EN
5
COMP
3
AGND
AOZ1012
LX
LX
THRM
FB
PGND
4
2
8
7
9
DGND DGND
L8
1
4.7uH
C301
NL
3
3.30V@3A
VCC3
R162
30K
C298
100uF
R176
1.1K
R164 10K
2
VCC5SB
C302
1uF
DGND
1
5
8
U19
LM317L
VIN
NC
VIN
VOUT
VOUT
VOUT
VOUT
2
3
6
7
1
R179
270
R163
1K
3.30V
VCC3SB
C299
22uF
DGND
DESIGN NOTE: For TFT support, VCORE must power up before VCC3. With this design, a simple RC is on the enable to the VCC3 regulator
delays VCC3 relative to
VCORE.
WORK_AUX
VCC5
C309
100nF
R1009
C307
47uF
10K
R166 27K
C310
1.5nF
1
U20
VIN
6
EN
5
COMP
3
AGND
AOZ1012
LX
LX
THRM
8
7
9
FB
PGND
4
2
DGND DGND
L9
1
4.7uH
C308
NL
DGND
1.25V@3A
VCORE
R167
5.6K
R177
22
R168 10K
C306
100uF
DESIGN NOTE: OPN's for the LX processor have a specified Vcore voltage of 1.25V or 1.20V. If using an OPN that has a Vcore of 1.2V
then R3 should be 10K ohms.
DGND
POWER
GREEN
VCC5
R170
560
DESIGN NOTE:
LED is optional.
VCC3SB
R169
470
R165
2K
DGND
1.225V
VCORESB
11 PS_ON#
VCC3_EXT
12V
5
11 WORKING
VCC5SB
C315
100nF
C313
47uF
R171 24K
C316
2.2nF
1
U21
VIN
6
EN
5
COMP
3
AGND
AOZ1012
LX
LX
THRM
FB
PGND
4
2
8
7
9
J25
3
4
5
1
2
PS_ON
GND
GND
+12V
+3.3V
1 6
2 7
3 8
4 9
5 10
MINI-ATX POWER
+5VSB
+5V
+5V
-12V
GND
6
7
8
9
10
DGND DGND
10 Pin ATX Type Power Connector
DGND
4
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
DGND
1
1
1
1
1
1
1
1
1
L10
1
4.7uH
2.6V@2A
VCCMEM D14
LTST-C190GKT
D13
3
LM4041AIM3-1.2
DGND
C311
1uF
DGND
C314
NL
VCORESB
TP10
VCORE
TP11
VCCMEM
TP12
VCC3SB
TP13
VCC3
TP14
VCC5SB
TP15
VCC5
TP16
VBAT
TP17
MVREF
TP18
1
1
1
1
1
1
1
1
1
R172
22K
R178
470
R173 10K
C312
100uF
3
DGND
DGND
DGND
TP19
1
TP20
1
TP21
1
TP22
1
TP23
1
TP24
1
WORKING
WORK_AUX
SYS_RST#
RST_STB# 11
11 EXT_PWRBTN#
11 PWRBTN#
11 EXT_RST#
9,11,17 SYS_RST#
C317
1uF
R174 22
PWRBTN
SW1
1
2
3
4
PTS453SL38
DGND
DGND
C318
1uF
R175 22
1
2
RESET
SW2
3
4
PTS453SL38
DGND
DGND
B
PCI_RST# 9,11,12,15,16,17,19,20,24
PME# 11,15,17,19
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
25
of
26
1 2
A
C
D
B
A
2 1
D
VCC_LCD
C32
100nF
C31
22uF
8
8
8 TFTCLK
HSYNC_C
VSYNC_C
8
8
8
8
8
8
TFT_R2
TFT_R3
TFT_R4
TFT_R5
TFT_R6
TFT_R7
DGND
8
8
8
8
8
8
TFT_G2
TFT_G3
TFT_G4
TFT_G5
TFT_G6
TFT_G7
8
8
8
8
8
8
TFT_B2
TFT_B3
TFT_B4
TFT_B5
TFT_B6
TFT_B7
8 LDEMOD_HSIP_VSYNC
C
5
TFT Connector
4
20
21
22
23
24
25
14
15
16
17
18
19
26
27
28
29
30
8
9
10
11
12
13
5
6
7
1
2
3
4
J2
DGND
HIROSE-DF14-30PIN-1M25
VCC_LCD
J28
8
8
TXOUT3-
TXOUT3+
8
8
TXCLKOUT-
TXCLKOUT+
8
8
TXOUT2-
TXOUT2+
8
8
TXOUT1-
TXOUT1+
12,14
12,14
8 TXOUT0-
8 TXOUT0+
CRT_SCL
CRT_SDA
10
11
12
7
8
9
4
5
6
1
2
3
13
14
15
16
17
18
19
20
DGND
LVDS Connector
HIROSE-DF14-20PIN-1M25
3
VCC5 12V
1
3
5
J29
2
4
6
VCC5 VCC3
PFL-2x3-2M0-SMD-S
DESIGN NOTE: J29: SET
VOLTAGES FOR LCD AND
BACKLIGHT:
DEFAULT LCD: JUMPER
PIN2 TO PIN4 = VCC
DEFAULT BACKLIGHT:
JUMPER PIN1 TO PIN3 = 12V
ROUTE WIDTH=20mil
8 HSIP_HSYNC
R201 10K
1
R200
47K
Q7
SI2305DS
Q8
BC846B
ROUTE WIDTH=20mil
C343
100nF
VCC_LCD
C344
10uF
ROUTE WIDTH=20mil
OPTIONAL: ON-BOARD SWITCHING OF VBKL
8 DISPEN
R206 10K
1
R205
47K
DGND
Q9
SI2307DS
DGND
ROUTE WIDTH=20mil
DGND
R204 0
1
C345
100nF
C346
10uF
Q10
BC846B
VCC5 12V
ROUTE WIDTH=20mil
8 DISPEN
DGND
4
5
6
1
2
3
7
8
J30
HIROSE-DF13-8PIN-1M25
5 4
DGND DGND DGND
3 2
*AMD CONFIDENTIAL*
Advanced Micro Devices
1351 South Sunset St.
Longmont CO 80501
Title
AMD GEODE™ LX EPIC RDK Reference Schematic
Document Number
40744
Rev
D
Size
B
Date:
Wednesday, April 11, 2007
Sheet
26
of
26
1
A
B
D
C
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