Analog Devices ADSP-21020 User's Manual

a

32/40-Bit IEEE Floating-Point

DSP Microprocessor

ADSP-21020

FUNCTIONAL BLOCK DIAGRAM FEATURES

Superscalar IEEE Floating-Point Processor

Off-Chip Harvard Architecture Maximizes Signal

Processing Performance

30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

Execution

100 MFLOPS Peak, 66 MFLOPS Sustained Performance

1024-Point Complex FFT Benchmark: 0.58 ms

Divide (y/x): 180 ns

Inverse Square Root (1/

√ x): 270 ns

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats

32-Bit Fixed-Point Formats, Integer and Fractional, with 80-Bit Accumulators

IEEE Exception Handling with Interrupt on Exception

Three Independent Computation Units: Multiplier,

ALU, and Barrel Shifter

Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse Addressing Modes

Two Off-Chip Memory Transfers in Parallel with

Instruction Fetch and Single-Cycle Multiply & ALU

Operations

Multiply with Add & Subtract for FFT Butterfly

Computation

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

Single-Cycle Register File Context Switch

15 (or 25) ns External RAM Access Time for Zero-Wait-

State, 30 (or 40) ns Instruction Execution

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation Circuitry

223-Pin PGA Package (Ceramic)

GENERAL DESCRIPTION

The ADSP-21020 is the first member of Analog Devices’ family of single-chip IEEE floating-point processors optimized for digital signal processing applications. Its architecture is similar to that of Analog Devices’ ADSP-2100 family of fixed-point

DSP processors.

Fabricated in a high-speed, low-power CMOS process, the

ADSP-21020 has a 30 ns instruction cycle time. With a highperformance on-chip instruction cache, the ADSP-21020 can execute every instruction in a single cycle.

The ADSP-21020 features:

• Independent Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier and shifter perform single-cycle instructions. The units are architecturally arranged in parallel, maximizing computational throughput. A single multifunction instruction executes parallel ALU and

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

DATA ADDRESS

GENERATORS

DAG 1 DAG 2

REGISTER FILE

INSTRUCTION

CACHE

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

ALU

ARITHMETIC UNITS

MULTIPLIER SHIFTER

JTAG TEST

& EMULATION

TIMER

EXTERNAL

ADDRESS

BUSES

EXTERNAL

DATA

BUSES multiplier operations. These computation units support IEEE

32-bit single-precision floating-point, extended precision

40-bit floating-point, and 32-bit fixed-point data formats.

• Data Register File

A general-purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. This 10-port (16-register) register file, combined with the ADSP-21020’s Harvard architecture, allows unconstrained data flow between computation units and off-chip memory.

• Single-Cycle Fetch of Instruction and Two Operands

The ADSP-21020 uses a modified Harvard architecture in which data memory stores data and program memory stores both instructions and data. Because of its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch an operand from data memory, an operand from program memory, and an instruction from the cache, all in a single cycle.

• Memory Interface

Addressing of external memory devices by the ADSP-21020 is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for simplified addressing of page-mode

DRAM.

The ADSP-21020 provides programmable memory wait states, and external memory acknowledge controls allow interfacing to peripheral devices with variable access times.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700 Fax: 617/326-8703

ADSP-21020

• Instruction Cache

The ADSP-21020 includes a high performance instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with program memory data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiplyaccumulates and FFT butterfly processing.

• Hardware Circular Buffers

The ADSP-21020 provides hardware to implement circular buffers in memory, which are common in digital filters and

Fourier transform implementations. It handles address pointer wraparound, reducing overhead (thereby increasing performance) and simplifying implementation. Circular buffers can start and end at any location.

• Flexible Instruction Set

The ADSP-21020’s 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21020 can conditionally execute a multiply, an add, a subtract and a branch in a single instruction.

DEVELOPMENT SYSTEM

The ADSP-21020 is supported with a complete set of software and hardware development tools. The ADSP-21000 Family

Development System includes development software, an evaluation board and an in-circuit emulator.

• Assembler

Creates relocatable, COFF (Common Object File Format) object files from ADSP-21xxx assembly source code. It accepts standard C preprocessor directives for conditional assembly and macro processing. The algebraic syntax of the

ADSP-21xxx assembly language facilitates coding and debugging of DSP algorithms.

• Linker/Librarian

The Linker processes separately assembled object files and library files to create a single executable program. It assigns memory locations to code and to data in accordance with a user-defined architecture file that describes the memory and

I/O configuration of the target system. The Librarian allows you to group frequently used object files into a single library file that can be linked with your main program.

• Simulator

The Simulator performs interactive, instruction-level simulation of ADSP-21xxx code within the hardware configuration described by a system architecture file. It flags illegal operations and supports full symbolic disassembly. It provides an easy-to-use, window oriented, graphical user interface that is identical to the one used by the ADSP-21020

EZ-ICE Emulator. Commands are accessed from pull-down menus with a mouse.

• PROM Splitter

Formats an executable file into files that can be used with an industry-standard PROM programmer.

• C Compiler and Runtime Library

The C Compiler complies with ANSI specifications. It takes advantage of the ADSP-21020’s high-level language architectural features and incorporates optimizing algorithms to speed up the execution of code. It includes an extensive runtime library with over 100 standard and DSP-specific functions.

–2–

• C Source Level Debugger

A full-featured C source level debugger that works with the simulator or EZ-ICE emulator to allow debugging of assembler source, C source, or mixed assembler and C.

• Numerical C Compiler

Supports ANSI Standard (X3J11.1) Numerical C as defined by the Numeric C Extensions Group. The compiler accepts C source input containing Numerical C extensions for array selection, vector math operations, complex data types, circular pointers, and variably dimensioned arrays, and outputs ADSP-21xxx assembly language source code.

• ADSP-21020 EZ-LAB® Evaluation Board

The EZ-LAB Evaluation Board is a general-purpose, standalone ADSP-21020 system that includes 32K words of program memory and 32K words of data memory as well as analog I/O. A PC RS-232 download path enables the user to download and run programs directly on the EZ-LAB. In addition, it may be used in conjunction with the EZ-ICE

Emulator to provide a powerful software debug environment.

• ADSP-21020 EZ-ICE® Emulator

This in-circuit emulator provides the system designer with a

PC-based development environment that allows nonintrusive access to the ADSP-21020’s internal registers through the processor’s 5-pin JTAG Test Access Port. This use of on-chip emulation circuitry enables reliable, full-speed performance in any target. The emulator uses the same graphical user interface as the ADSP-21020 Simulator, allowing an easy transition from software to hardware debug. (See “Target System

Requirements for Use of EZ-ICE Emulator” on page 27.)

ADDITIONAL INFORMATION

This data sheet provides a general overview of ADSP-21020 functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-21020 User’s

Manual. For development system and programming reference information, refer to the ADSP-21000 Family Development

Software Manuals and the ADSP-21020 Programmer’s Quick

Reference. Applications code listings and benchmarks for key

DSP algorithms are available on the DSP Applications BBS; call

(617) 461-4258, 8 data bits, no parity, 1 stop bit, 300/1200/

2400/9600 baud.

ARCHITECTURE OVERVIEW

Figure 1 shows a block diagram of the ADSP-21020. The processor features:

• Three Computation Units (ALU, Multiplier, and Shifter) with a Shared Data Register File

• Two Data Address Generators (DAG 1, DAG 2)

• Program Sequencer with Instruction Cache

• 32-Bit Timer

• Memory Buses and Interface

• JTAG Test Access Port and On-Chip Emulation Support

Computation Units

The ADSP-21020 contains three independent computation units: an ALU, a multiplier with fixed-point accumulator, and a shifter. In order to meet a wide variety of processing needs, the computation units process data in three formats: 32-bit fixed-point, 32-bit floating-point and 40-bit floating-point. The floating-point operations are single-precision IEEE-compatible

(IEEE Standard 754/854). The 32-bit floating-point format is

EZ-LAB and EZ-ICE are registered trademarks of Analog Devices, Inc.

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DAG 1

8 x 4 x 32

CACHE

MEMORY

32 x 48

DAG 2

8 x 4 x 24

PMD BUS 48

PMA BUS

24

DMA BUS 32

BUS CONNECT

DMD BUS 40

PROGRAM

SEQUENCER

JTAG TEST &

EMULATION

FLAGS

TIMER

ADSP-21020

PMA

DMA

PMD

DMD

FLOATING & FIXED-POINT

MULTIPLIER, FIXED-POINT

ACCUMULATOR

REGISTER

FILE

16 x 40

32-BIT

BARREL

SHIFTER

FLOATING-POINT

& FIXED-POINT

ALU

Figure 1. ADSP-21020 Block Diagram the standard IEEE format, whereas the 40-bit IEEE extendedprecision format has eight additional LSBs of mantissa for greater accuracy.

The multiplier performs floating-point and fixed-point multiplication as well as fixed-point multiply/add and multiply/ subtract operations. Integer products are 64 bits wide, and the accumulator is 80 bits wide. The ALU performs 45 standard arithmetic and logic operations, supporting both fixed-point and floating-point formats. The shifter performs 19 different operations on 32-bit operands. These operations include logical and arithmetic shifts, bit manipulation, field deposit, and extract and derive exponent operations.

The computation units perform single-cycle operations; there is

no computation pipeline. The three units are connected in parallel rather than serially, via multiple-bus connections with the 10-port data register file. The output of any computation unit may be used as the input of any unit on the next cycle. In a

multifunction computation, the ALU and multiplier perform independent, simultaneous operations.

Data Register File

The ADSP-21020’s general-purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. The register file has two sets (primary and alternate) of sixteen 40-bit registers each, for fast context switching.

With a large number of buses connecting the registers to the computation units, data flow between computation units and from/to off-chip memory is unconstrained and free from bottlenecks. The 10-port register file and Harvard architecture of the ADSP-21020 allow the following nine data transfers to be performed every cycle:

• Off-chip read/write of two operands to or from the register file

• Two operands supplied to the ALU

• Two operands supplied to the multiplier

• Two results received from the ALU and multiplier (three, if the ALU operation is a combined addition/subtraction)

The processor’s 48-bit orthogonal instruction word supports fully parallel data transfer and arithmetic operations in the same instruction.

Address Generators and Program Sequencer

Two dedicated address generators and a program sequencer supply addresses for memory accesses. Because of this, the computation units need never be used to calculate addresses.

Because of its instruction cache, the ADSP-21020 can simultaneously fetch an instruction and data values from both off-chip program memory and off-chip data memory in a single cycle.

The data address generators (DAGs) provide memory addresses when external memory data is transferred over the parallel memory ports to or from internal registers. Dual data address generators enable the processor to output two simultaneous addresses for dual operand reads and writes. DAG 1 supplies

32-bit addresses to data memory. DAG 2 supplies 24-bit addresses to program memory for program memory data accesses.

Each DAG keeps track of up to eight address pointers, eight modifiers, eight buffer length values and eight base values. A pointer used for indirect addressing can be modified by a value

REV. C –3–

ADSP-21020 in a specified register, either before (premodify) or after

(postmodify) the access. To implement automatic modulo addressing for circular buffers, the ADSP-21020 provides buffer length registers that can be associated with each pointer. Base values for pointers allow circular buffers to be placed at arbitrary locations. Each DAG register has an alternate register that can be activated for fast context switching.

The program sequencer supplies instruction addresses to program memory. It controls loop iterations and evaluates conditional instructions. To execute looped code with zero overhead, the ADSP-21020 maintains an internal loop counter and loop stack. No explicit jump or decrement instructions are required to maintain the loop.

The ADSP-21020 derives its high clock rate from pipelined

fetch, decode and execute cycles. Approximately 70% of the machine cycle is available for memory accesses; consequently,

ADSP-21020 systems can be built using slower and therefore less expensive memory chips.

Instruction Cache

The program sequencer includes a high performance, selective instruction cache that enables three-bus operation for fetching an instruction and two data values. This two-way, set-associative cache holds 32 instructions. The cache is selective—only the instructions whose fetches conflict with program memory data accesses are cached, so the ADSP-21020 can perform a program memory data access and can execute the corresponding instruction in the same cycle. The program sequencer fetches the instruction from the cache instead of from program memory, enabling the

ADSP-21020 to simultaneously access data in both program memory and data memory.

Context Switching

Many of the ADSP-21020’s registers have alternate register sets that can be activated during interrupt servicing to facilitate a fast context switch. The data registers in the register file, DAG registers and the multiplier result register all have alternate sets.

Registers active at reset are called primary registers; the others are called alternate registers. Bits in the MODE1 control register determine which registers are active at any particular time.

The primary/alternate select bits for each half of the register file

(top eight or bottom eight registers) are independent. Likewise, the top four and bottom four register sets in each DAG have independent primary/ alternate select bits. This scheme allows passing of data between contexts.

Interrupts

The ADSP-21020 has four external hardware interrupts, nine internally generated interrupts, and eight software interrupts.

For the external interrupts and the internal timer interrupt, the

ADSP-21020 automatically stacks the arithmetic status and mode (MODE1) registers when servicing the interrupt, allowing five nesting levels of fast service for these interrupts.

An interrupt can occur at any time while the ADSP-21020 is executing a program. Internal events that generate interrupts include arithmetic exceptions, which allow for fast trap handling and recovery.

Timer

The programmable interval timer provides periodic interrupt generation. When enabled, the timer decrements a 32-bit count register every cycle. When this count register reaches zero, the

ADSP-21020 generates an interrupt and asserts its TIMEXP

–4– output. The count register is automatically reloaded from a

32-bit period register and the count resumes immediately.

System Interface

Figure 2 shows an ADSP-21020 basic system configuration.

The external memory interface supports memory-mapped peripherals and slower memory with a user-defined combination of programmable wait states and hardware acknowledge signals.

Both the program memory and data memory interfaces support addressing of page-mode DRAMs.

The ADSP-21020’s internal functions are supported by four internal buses: the program memory address (PMA) and data memory address (DMA) buses are used for addresses associated with program and data memory. The program memory data

(PMD) and data memory data (DMD) buses are used for data associated with the two memory spaces. These buses are extended off chip. Four data memory select (DMS) signals select one of four user-configurable banks of data memory.

Similarly, two program memory select (PMS) signals select between two user-configurable banks of program memory. All banks are independently programmable for 0-7 wait states.

The PX registers permit passing data between program memory and data memory spaces. They provide a bridge between the

48-bit PMD bus and the 40-bit DMD bus or between the 40-bit register file and the PMD bus.

The PMA bus is 24 bits wide allowing direct access of up to

16M words of mixed instruction code and data. The PMD is 48 bits wide to accommodate the 48-bit instruction width. For access of 40-bit data the lower 8 bits are unused. For access of

32-bit data the lower 16 bits are ignored.

The DMA bus is 32 bits wide allowing direct access of up to 4

Gigawords of data. The DMD bus is 40 bits wide. For 32-bit data, the lower 8 bits are unused. The DMD bus provides a path for the contents of any register in the processor to be transferred to any other register or to any external data memory location in a single cycle. The data memory address comes from one of two sources: an absolute value specified in the instruction code (direct addressing) or the output of a data address generator (indirect addressing).

External devices can gain control of the processor’s memory buses from the ADSP-21020 by means of the bus request/grant signals (BR and BG). To grant its buses in response to a bus request, the ADSP-21020 halts internal operations and places its program and data memory interfaces in a high impedance state. In addition, three-state controls (DMTS and PMTS) allow an external device to place either the program or data memory interface in a high impedance state without affecting the other interface and without halting the ADSP-21020 unless it requires a memory access from the affected interface. The three-state controls make it easy for an external cache controller to hold the ADSP-21020 off the bus while it updates an external cache memory.

JTAG Test and Emulation Support

The ADSP-21020 implements the boundary scan testing provisions specified by IEEE Standard 1149.1 of the Joint

Testing Action Group (JTAG). The ADSP-21020’s test access port and on-chip JTAG circuitry is fully compliant with the IEEE 1149.1 specification. The test access port enables boundary scan testing of circuitry connected to the

ADSP-21020’s I/O pins.

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ADSP-21020

PROGRAM

MEMORY

SELECTS

OE

WE

ADDR

DATA

1

×

CLOCK

4

2

24

48

CLKIN RESET IRQ3-0

PMS1-0

PMRD

PMWR

PMA

PMD

DMS3-0

DMRD

DMWR

DMA

DMD

ADSP-21010

4

32

PMTS

PMPAGE

PMACK

DMTS

DMPAGE

DMACK

32

SELECTS

OE

WE

ADDR

DATA

MEMORY

DATA

SELECTS

OE

PERIPHERALS

WE

ACK

ADDR

DATA

4 5

PIN DESCRIPTIONS

This section describes the pins of the ADSP-21020. When groups of pins are identified with subscripts, e.g. PMD

47–0

, the highest numbered pin is the MSB (in this case, PMD

47

). Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI, and TRST). Those that are asynchronous (A) can be asserted asynchronously to CLKIN.

O = Output; I = Input; S = Synchronous; A = Asynchronous;

P = Power Supply; G = Ground.

Pin

Name Type Function

PMA

PMD

PMS

23–0

47–0

1–0

PMRD

PMWR

O

I/O

O

O

O

PMACK I/S

Program Memory Address. The ADSP-21020 outputs an address in program memory on these pins.

Program Memory Data. The ADSP-21020 inputs and outputs data and instructions on these pins. 32-bit fixed-point data and 32-bit single-precision floating-point data is transferred over bits 47-16 of the PMD bus.

Program Memory Select lines. These pins are asserted as chip selects for the corresponding banks of program memory. Memory banks must be defined in the memory control registers. These pins are decoded program memory address lines and provide an early indication of a possible bus cycle.

Program Memory Read strobe. This pin is asserted when the ADSP-21020 reads from program memory.

Program Memory Write strobe. This pin is asserted when the ADSP-21020 writes to program memory.

Program Memory Acknowledge. An external device deasserts this input to add wait states to a memory access.

Figure 2. Basic System Configuration

The ADSP-21020 also implements on-chip emulation through the JTAG test access port. The processor’s eight sets of breakpoint range registers enable program execution at full speed until reaching a desired break-point address range. The processor can then halt and allow reading/writing of all the processor’s internal registers and external memories through the

JTAG port.

Pin

Name Type

PMPAGE O

PMTS

DMACK

I/S

I/S

Function

Program Memory Page Boundary. The

ADSP-21020 asserts this pin to signal that a program memory page boundary has been crossed. Memory pages must be defined in the memory control registers.

Program Memory Three-State Control.

PMTS places the program memory address, data, selects, and strobes in a highimpedance state. If PMTS is asserted while a PM access is occurring, the processor will halt and the memory access will not be completed. PMACK must be asserted for at least one cycle when PMTS is deasserted to allow any pending memory access to complete properly. PMTS should only be asserted (low) during an active memory access cycle.

DMA

DMD

DMS

31–0

39–0

3–0

DMRD

O Data Memory Address. The ADSP-21020 outputs an address in data memory on these pins.

I/O Data Memory Data. The ADSP-21020 inputs and outputs data on these pins.

32-bit fixed point data and 32-bit single-precision floating point data is transferred over bits 39-8 of the DMD bus.

O

O

Data Memory Select lines. These pins are asserted as chip selects for the corresponding banks of data memory. Memory banks must be defined in the memory control registers. These pins are decoded data memory address lines and provide an early indication of a possible bus cycle.

Data Memory Read strobe. This pin is asserted when the ADSP-21020 reads from data memory.

DMWR O Data Memory Write strobe. This pin is asserted when the ADSP-21020 writes to data memory.

Data Memory Acknowledge. An external device deasserts this input to add wait states to a memory access.

REV. C –5–

ADSP-21020

Pin


Pin


DMPAGE

DMTS

CLKIIN

RESET

IRQ

3–0

FLAG

3–0

O

I

I/S

Data Memory Page Boundary. The ADSP-

21020 asserts this pin to signal that a data memory page boundary has been crossed.

Memory pages must be defined in the memory control registers.

Data Memory Three-State Control. DMTS places the data memory address, data, selects, and strobes in a high-impedance state. If DMTS is asserted while a DM access is occurring, the processor will halt and the memory access will not be completed. DMACK must be asserted for at least one cycle when DMTS is deasserted to allow any pending memory access to complete properly. DMTS should only be asserted (low) during an active memory access cycle.

External clock input to the ADSP-21020.

The instruction cycle rate is equal to

CLKIN. CLKIN may not be halted, changed, or operated below the specified frequency.

I/A Sets the ADSP-21020 to a known state and begins execution at the program memory location specified by the hardware reset vector (address). This input must be asserted (low) at power-up.

I/A Interrupt request lines; may be either edge triggered or level-sensitive.

I/O/A External Flags. Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals.

BR

BG

TIMEXP

I/A Bus Request. Used by an external device to request control of the memory interface.

When BR is asserted, the processor halts execution after completion of the current cycle, places all memory data, addresses, selects, and strobes in a high-impedance state, and asserts BG. The processor continues normal operation when BR is released.

O

O

Bus Grant. Acknowledges a bus request

(BR), indicating that the external device may take control of the memory interface.

BG is asserted (held low) until BR is released.

Timer Expired. Asserted for four cycles when the value of TCOUNT is decremented to zero.

RCOMP

EVDD

EGND

P

G

Compensation Resistor input. Controls compensated output buffers. Connect

RCOMP through a 1.8 k

Ω ±

15% resistor to EVDD. Use of a capacitor (approximately 100 pF), placed in parallel with the

1.8 k

Ω

resistor is recommended.

Power supply (for output drivers), nominally +5 V dc (10 pins).

Power supply return (for output drivers);

(16 pins).

IVDD P

IGND G

TCK I

TMS I/S

TDI

NC

VS

TDO O

TRST I/A

Power supply (for internal circuitry), nominally +5 V dc (4 pins).

Power supply return (for internal circuitry); (7 pins).

Test Clock. Provides an asynchronous clock for JTAG boundary scan.

Test Mode Select. Used to control the test state machine. TMS has a 20 k

Ω

internal pullup resistor.

Test Data Input. Provides serial data for the boundary scan logic. TDI has a 20 k

Ω


Test Data Output. Serial scan output of the boundary scan path.

Test Reset. Resets the test state machine.

TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21020. TRST has a 20 k

Ω


No Connect. No Connects are reserved pins that must be left open and unconnected.

INSTRUCTION SET SUMMARY

The ADSP-21020 instruction set provides a wide variety of programming capabilities. Every instruction assembles into a single word and can execute in a single processor cycle.

Multifunction instructions enable simultaneous multiplier and

ALU operations, as well as computations executed in parallel with data transfers. The addressing power of the ADSP-21020 gives you flexibility in moving data both internally and externally. The ADSP-21020 assembly language uses an algebraic syntax for ease of coding and readability.

The instruction types are grouped into four categories:

Compute and Move or Modify

Program Flow Control

Immediate Move

Miscellaneous

The instruction types are numbered; there are 22 types. Some instructions have more than one syntactical form; for example,

Instruction 4 has four distinct forms. The instruction number itself has no bearing on programming, but corresponds to the opcode recognized by the ADSP-21020 device.

Because of the width and orthogonality of the instruction word, there are many possible instructions. For example, the ALU supports 21 fixed-point operations and 24 floating-point operations; each of these operations can be the compute portion of an instruction.

The following pages provide an overview and summary of the

ADSP-21020 instruction set. For complete information, see the

ADSP-21020 User’s Manual. For additional reference information, see the ADSP-21020 Programmer’s Quick Reference.

–6–

This section also contains several reference tables for using the instruction set.

• Table I describes the notation and abbreviations used.

• Table II lists all condition and termination code mnemonics.

• Table III lists all register mnemonics.

• Tables IV through VII list the syntax for all compute

(ALU, multiplier, shifter or multifunction) operations.

• Table VIII lists interrupts and their vector addresses.

REV. C

COMPUTE AND MOVE OR MODIFY INSTRUCTIONS

1.

compute, | DM(Ia, Mb) = dreg1 | ,

| dreg1 = DM(Ia, Mb)

|

2.

IF condition compute;

3a.

IF condition

3b.

IF condition

3c.

IF condition

3d.

IF condition

4a.

IF condition

4b.

IF condition

4c.

IF condition

4d.

IF condition

compute,

compute,

compute,

compute,

compute,

compute,

compute,

compute,

| DM(Ia, Mb) | = ureg ;

|

PM(Ic, Md)

|

| DM(Mb, Ia) | = ureg ;

|

PM(Md, Ic)

| ureg = | DM(Ia, Mb) | ;

|

PM(Ic, Md)

| ureg = | DM(Mb, Ia) | ;

|

PM(Md, Ic)

|

| DM(Ia, <data6>) | = dreg ;

|

PM(Ic, <data6>)

|

| DM(<data6>, Ia) | = dreg ;

|

PM(<data6>, Ic)

| dreg = | DM(Ia, <data6>) | ;

|

PM(Ic, <data6>)

| dreg = | DM(<data6>, Ia) | ;

|

PM(<data6>, Ic)

|

5.

IF condition

6a.

IF condition

6b.

IF condition

7.

IF condition

7.

IF condition

compute, shiftimm, shiftimm,

compute,

compute, ureg1 = ureg2 ;

| DM(Ia, Mb) | = dreg ;

|

PM(Ic, Md)

|

dreg = | DM(Ia, Mb) | ;

|

PM(Ic, Md)

|

MODIFY | (Ia, Mb) | ;

MODIFY | (Ic, Md)

|

|

|

PM(Ic, Md) = dreg2 dreg2 = PM(Ic, Md)

PROGRAM FLOW CONTROL INSTRUCTIONS

8.

IF condition |

|

|

JUMP

CALL

CALL

|

|

|

|

|

|

<addr24>

(PC, <reladdr6>)

(PC, <reladdr6>)

| ( | DB | ) ;

|

|

(

(

|

|

LA

,

DB, LA

|

|

9.

IF condition | JUMP | | (Md, Ic) | ( | DB | ) , compute ;

|

CALL

| |

(PC, <reladdr6>)

|

(

|

LA

,

|

|

CALL

| |

(PC, <reladdr6>)

|

(

|

DB, LA

|

|

|

;

11.

IF condition

12.

LCNTR =

12.

LCNTR =

13.

LCNTR =

| RTS | ( | DB , | ) , compute ;

|

RTI | (

|

LA ,

|

|

RTI | (

|

DB, LA

|

| <data16> | , DO | <addr24>

| ureg

|

, DO

| UNTIL LCE ;

|

(<PC, <reladdr24>)

(

|

UNTIL LCE ;

| <data16> | , DO | <addr24>

| ureg

|

, DO

|

(

|

(PC, <reladdr24>)

| UNTIL termination ;

|

12.

LCNTR =

(DB) Delayed branch

(LA) Loop abort (pop loop PC stacks on branch)

ADSP-21020

REV. C –7–

ADSP-21020

IMMEDIATE MOVE INSTRUCTIONS

14a. DM(<addr32>) = ureg ;

PM(<addr24>)

14b. ureg = DM(<addr32>)

PM(<addr24>)

;

15a. DM(<data32>, Ia) = ureg;

PM(< data24>, Ic)

15b. ureg = DM(<data32>, Ia)

PM(<data24>, Ic)

;

16.

DM(Ia, Mb) = <data32>;

PM(Ic, Md)

17.

ureg = <data32>;

MISCELLANEOUS INSTRUCTIONS

18. BIT

19a. MODIFY

19b. BITREV

SET

CLR

TGL

TST

XOR sreg <data32>;

(Ia, <data32>) | ;

(Ic, <data32>) |

(Ia, <data32>) ;

20.

|

|

PUSH

POP

21. NOP ;

22. IDLE ;

LOOP , PUSH

POP

STS ;

Table I. Syntax Notation Conventions

Notation Meaning

UPPERCASE Explicit syntax—assembler keyword (notation only; assembler is not case-sensitive and lowercase is the preferred programming

,

; convention)

Instruction terminator

Separates parallel operations in an italics instruction

Optional part of instruction

| between lines | List of options (choose one)

<datan> n-bit immediate data value

<addrn>

<reladdrn> compute

n-bit immediate address value

n-bit immediate PC-relative address value

ALU, multiplier, shifter or multifunction shiftimm condition termination ureg sreg dreg

Ia

Mb

Ic

Md operation (from Tables IV-VII)

Shifter immediate operation

(from Table VI)

Status condition (from Table II)

Termination condition (from Table II)

Universal register (from Table III)

System register (from Table III)

R15-R0, F15-F0; register file location

I7-I0; DAG1 index register

M7-M0; DAG1 modify register

I15-I8; DAG2 index register

M15-M8; DAG2 modify register

Table II. Condition and Termination Codes

Name Description eq ne ge lt le gt ac not ac av not av mv not mv ms not ms sv not sv sz not sz flag0_in not flag0_in flag1_in not flag1_in flag2_in not flag2_in flag3_in not flag3_in tf not tf lce not lce forever true

ALU equal to zero

ALU not equal to zero

ALU greater than or equal to zero

ALU less than zero

ALU less than or equal to zero

ALU greater than zero

ALU carry

Not ALU carry

ALU overflow

Not ALU overflow

Multiplier overflow

Not multiplier overflow

Multiplier sign

Not multiplier sign

Shifter overflow

Not shifter overflow

Shifter zero

Not shifter zero

Flag 0

Not Flag 0

Flag 1

Not Flag l

Flag 2

Not Flag 2

Flag 3

Not Flag 3

Bit test flag

Not bit test flag

Loop counter expired (DO UNTIL)

Loop counter not expired (IF)

Always False (DO UNTIL)

Always True (IF)

In a conditional instruction, the execution of the entire instruction is based on the specified condition.

–8– REV. C

ADSP-21020

Table III. Universal Registers Table IV. ALU Compute Operations

Name Function

Register File

R15–R0 Register file locations

Program Sequencer

PC*

PCSTK

PCSTKP

FADDR*

Program counter; address of instruction currently executing

Top of PC stack

PC stack pointer

Fetch address

DADDR*

LADDR

Decode address

Loop termination address, code; top of loop address stack

CURLCNTR Current loop counter; top of loop count stack

LCNTR Loop count for next nested counter-controlled loop

Data Address Generators

I7–I0

M7–M0

L7–L0

DAG1 index registers

DAG1 modify registers

DAG1 length registers

B7–B0

I15–I8

M15–M8

L15–L8

B15–B8

Bus Exchange

PX1

PX2

PX

Timer

DAG1 base registers

DAG2 index registers

DAG2 modify registers

DAG2 length registers

DAG2 base registers

PMD-DMD bus exchange 1 (16 bits)

PMD-DMD bus exchange 2 (32 bits)

48-bit PX1 and PX2 combination

TPERIOD

TCOUNT

Timer period

Timer counter

Memory Interface

DMWAIT Wait state and page size control for data memory

DMBANK1 Data memory bank 1 upper boundary



DMADR* Copy of last data memory address

PMWAIT Wait state and page size control for program

PMBANK1

PMADR*

System Registers

MODE1 memory

Program memory bank 1 upper boundary

Copy of last program memory address

MODE2

Mode control bits for bit-reverse, alternate registers, interrupt nesting and enable, ALU saturation, floating-point rounding mode and boundary

Mode control bits for interrupt sensitivity, cache disable and freeze, timer enable, and I/O

IRPTL

IMASK

IMASKP

ASTAT

STKY

USTAT1

USTAT2 flag configuration

Interrupt latch

Interrupt mask

Interrupt mask pointer (for nesting)

Arithmetic status flags, bit test, I/O flag values, and compare accumulator

Sticky arithmetic status flags, circular buffer overflow flags, stack status flags (not sticky)

User status register l

User status register 2

*read-only

Refer to User’s Manual for bit-level definitions of each register.

REV. C –9–

Fixed-Point Floating-Point

Rn = Rx + Ry

Rn = Rx – Ry

Rn = Rx + Ry, Rm = Rx – Ry

Rn = Rx + Ry + CI

Rn = Rx – Ry + CI – l

Rn = (Rx + Ry)/2

COMP(Rx, Ry)

Rn = –Rx

Rn = ABS Rx

Rn = PASS Rx

Rn = MIN(Rx, Ry)

Rn = MAX(Rx, Ry)

Rn = CLIP Rx BY Ry

Rn = Rx + CI

Rn = Rx + CI – 1

Rn = Rx + l

Rn = Rx – l

Rn = Rx AND Ry

Rn = Rx OR Ry

Rn = Rx XOR Ry

Rn = NOT Rx

Fn = Fx + Fy

Fn = Fx – Fy

Fn = Fx + Fy, Fm = Fx – Fy

Fn = ABS (Fx + Fy)

Fn = ABS (Fx – Fy)

Fn = (Fx + Fy)/2

COMP(Fx, Fy)

Fn = –Fx

Fn = ABS Fx

Fn = PASS Fx

Fn = MIN(Fx, Fy)

Fn = MAX(Fx, Fy)

Fn = CLIP Fx BY Fy

Fn = RND Fx

Fn = SCALB Fx BY Ry

Rn = MANT Fx

Rn = LOGB Fx

Rn = FIX Fx BY Ry

Rn = FIX Fx

Fn = FLOAT Rx BY Ry

Fn = FLOAT Rx

Fn = RECIPS Fx

Fn = RSQRTS Fx

Fn = Fx COPYSIGN Fy

Rn, Rx, Ry R15–R0; register file location, fixed-point

Fn, Fx, Fy F15–F0; register file location, floating point

ADSP-21020

Table V. Multiplier Compute Operations

Rn = Rx * Ry ( S S F )

MRF = Rx * Ry ( U U I

MRB = Rx * Ry ( U U FR

Rn

Rn

= MRF + Rx * Ry ( S S F )

= MRB + Rx * Ry ( U U I

MRF = MRF + Rx * Ry ( U U FR

MRB = MRB

Rn = SAT MRF (SI)

Rn = SAT MRB (UI)

MRF = SAT MRF (SF)

MRB = SAT MRB (UF)

MRF = 0

MRB

MRxF = Rn

MRxB

Fn

Rn

Rn

Rn

= Fx * Fy

= MRF

= MRB

MRF = MRF

MRB = MRB

Rn = MRxF

Rn = MRxB

S

U

I

F

FR

Rn, Rx, Ry

Fn, Fx, Fy

MRxF

MRxB

R15–R0; register file location, fixed-point

F15–F0; register file location, floating-point

MR2F, MR1F; MR0F; multiplier result accumulators, foreground

MR2B, MR1B, MR0B; multiplier result accumulators, background

( x-input y-input data format, )

( x-input y-input rounding

Signed input

Unsigned input

Integer input(s)

Fractional input(s)

Fractional inputs, Rounded output

(SF) Default format for 1-input operations

(SSF) Default format for 2-input operations

– Rx * Ry ( S

= Rx * Ry

= Rx * Ry

= RND MRF

(

( U U I

(SF)

Rn = RND MRB (UF)

MRF = RND MRF

MRB = RND MRB

S F

U U I

FR

)

Table VI. Shifter and Shifter Immediate Compute Operations

Shifter Shifter Immediate

Rn = LSHIFT Rx BY Ry

Rn = Rn OR LSHIFT Rx BY Ry

Rn = ASHIFT Rx BY Ry

Rn = Rn OR ASHIFT Rx BY Ry

Rn = ROT Rx BY RY

Rn = BCLR Rx BY Ry

Rn = BSET Rx BY Ry

Rn = BTGL Rx BY Ry

BTST Rx BY Ry

Rn = FDEP Rx BY Ry

Rn = Rn OR FDEP Rx BY Ry

Rn = FDEP Rx BY Ry (SE)

BTST Rx BY<data8>

Rn = FDEP Rx BY <bit6>: <len6>

Rn = Rn OR FDEP Rx BY <bit6>:<1en6>

Rn = FDEP Rx BY <bit6>:<1en6> (SE)

Rn = Rn OR FDEP Rx BY Ry (SE) Rn = Rn OR FDEP Rx BY <bit6>:<1en6> (SE)

Rn = FEXT Rx BY Ry Rn = FEXT Rx BY <bit6>:<1en6>

Rn = FEXT Rx BY Ry (SE)

Rn = EXP Rx

Rn = FEXT Rx BY <bit6>:<1en6> (SE)

Rn = EXP Rx (EX)

Rn = LEFTZ Rx

Rn = LEFTO Rx

Rn = LSHIFT Rx BY<data8>

Rn = Rn OR LSHIFT Rx BY<data8>

Rn = ASHIFT Rx BY<data8>

Rn = Rn OR ASHIFT Rx BY<data8>

Rn = ROT Rx BY<data8>

Rn = BCLR Rx BY<data8>

Rn = BSET Rx BY<data8>

Rn = BTGL Rx BY<data8>

Rn, Rx, Ry R15-R0; register file location, fixed-point

<bit6>:<len6> 6-bit immediate bit position and length values (for shifter immediate operations)

–10– REV. C

Table Vll. Multifunction Compute Operations

Fixed-Point

Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12

Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12

Rm=R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2

MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12

MRF=MRF + R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12

MRF=MRF + R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2

Rm=MRF + R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12

Rm=MRF + R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12

Rm=MRF + R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2

MRF=MRF – R3-0 * R7-4 (SSF), Ra=R11-8 + R15-12

MRF=MRF – R3-0 * R7-4 (SSF), Ra=R11-8 – R15-12

MRF=MRF – R3-0 * R7-4 (SSF), Ra=(R11-8 + R15-12)/2

Rm=MRF – R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12

Rm=MRF – R3-0 * R7-4 (SSFR), Ra=R11-8 – R15-12

Rm=MRF – R3-0 * R7-4 (SSFR), Ra=(R11-8 + R15-12)/2

Rm=R3-0 * R7-4 (SSFR), Ra=R11-8 + R15-12,

Rs=R11-8 – R15-12

Floating-Point

Fm=F3-0 * F7-4, Fa=F11-8 + F15-12

Fm=F3-0 * F7-4, Fa=F11-8 – F15-12

Fm=F3-0 * F7-4, Fa=FLOAT R11-8 by R15-12

Fm=F3-0 * F7-4, Fa=FIX R11-8 by R15-12

Fm=F3-0 * F7-4, Fa=(F11-8 + F15-12)/2

Fm=F3-0 * F7-4, Fa=ABS F11-8

Fm=F3-0 * F7-4, Fa=MAX (F11-8, F15-12)

Fm=F3-0 * F7-4, Fa=MIN (F11-8, F15-12)

Fm=F3-0 * F7-4, Fa=F11-8 + F15-12,

Fs=F11-8 – F15-12

Ra, Rm Any register file location (fixed-point)

R3-0

R7-4

R3, R2, R1, R0

R7, R6, R5, R4

R11-8 R11, R10, R9, R8

R15-12 R15, R14, R13, R12

Fa, Fm Any register file location (floating-point)

F3-0 F3, F2, F1, F0

F7-4 F7, F6, F5, F4

F11-8 F11, F10, F9, F8

F15-12 F15, F14, F13, F12

(SSF) X-input signed, Y-input signed, fractional inputs

(SSFR) X-input signed, Y-input signed, fractional inputs, rounded output

ADSP-21020

Table VIII. Interrupt Vector Addresses and Priorities

No.

Vector

Address

(Hex) Function

0

1*

2

3

8

9

10

11

12

13

4

5

6

7

0x00

0x08

0xl0

0xl8

0x20

0x28

0x30

0x38

0x40

0x48

0x50

0x58

0x60

0x68

Reserved

Reset

Reserved

Status stack or loop stack overflow or

PC stack full

Timer=0 (high priority option)

IRQ3

IRQ2

IRQ1

IRQ0

asserted

asserted

asserted

asserted

Reserved

Reserved

DAG 1 circular buffer 7 overflow

DAG 2 circular buffer 15 overflow

Reserved

14

15

16

0x70

0x78

0x80

Timer=0 (low priority option)

Fixed-point overflow

Floating-point overflow

17

18

0x88

0x90

19–23 0x98-0xB8

Floating-point underflow

Floating-point invalid operation

Reserved

24–31 0xC0–OxF8 User software interrupts

*Nonmaskable

REV. C –11–

ADSP-21020–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter

K Grade

Min Max

V

DD

T

AMB

Supply Voltage

Ambient Operating Temperature

4.50

0

Refer to Environmental Conditions for information on thermal specifications.

5.50

+70

B Grade

Min Max

4.50

–40

5.50

+85

T Grade

Min Max

4.50

–55

5.50

+125

Unit

V

°

C

ELECTRICAL CHARACTERISTICS

Parameter Test Conditions Min Max Unit

V

IH

V

IHCR

V

IL

V

ILC

V

OH

V

OL

I

IH

I

IL

I

ILT

I

OZH

I

OZL

I

DDIN

I

DDIDLE

C

IN

Hi-Level Input Voltage

Hi-Level Input Voltage

Lo-Level Input Voltage

Lo-Level Input Voltage

1

2, 12

1, 12

2

Hi-Level Output Voltage

Lo-Level Output Voltage

Hi-Level Input Current

Lo-Level Input Current

Lo-Level Input Current

Supply Current (Idle)

Input Capacitance 9, 10

8

3, 11

3, 11

4, 5

4

5

Tristate Leakage Current

6

Tristate Leakage Current 6

Supply Current (Internal)

7

V

DD

= max

V

DD

= max

V

DD

= min

V

DD

= max

V

DD

= min, I

OH

= –1.0 mA

V

DD

= min, I

OL

= 4.0 mA

V

DD

= max, V

IN

= V

DD

max

V

DD

= max, V

IN

= 0 V

V

DD

= max, V

IN

= 0 V

V

DD

= max, V

IN

= V

DD

max

V

DD

= max, V

IN

= 0 V t

CK

= 30–33 ns, V

DD

= max, V

IHCR

= 3.0 V,

V

IH

= 2.4 V, V

IL

= V

ILC

= 0.4 V

V

DD f

IN

= max, V

IN

= 1 MHz, T

= 0 V or V

CASE

DD

max

= 25

°

C, V

IN

= 2.5 V

2.0

3.0

2.4

0.8

0.6

0.4

10

10

350

10

10

490

150

10

V

V

V

V

V

V

µ

A

µ

A

µ

A

µ

A

µ

A mA mA pF

NOTES l

Applies to: PMD47–0, PMACK, PMTS, DMD39–0, DMACK, DMTS, IRQ3–0. FLAG3–0, BR, TMS, TDI.

2

Applies to: CLKIN, TCK.

3

Applies to: PMA23–0, PMD47–0, PMS1–0, PMRD, PMWR, PMPAGE, DMA31–0, DMD39–0, DMS3–0, DMRD, DMWR, DMPAGE, FLAG3–0,

TIMEXP, BG.

4

Applies to: PMACK, PMTS, DMACK, DMTS, IRQ3–0, BR, CLKIN, RESET, TCK.

5

Applies to: TMS, TDI, TRST.

6

Applies to: PMA23–0, PMD47–0, PMS1–0, PMRD, PMWR, PMPAGE, DMA31–0, DMD39–0, DMS3–0, DMRD, DMWR, DMPAGE, FLAG3–0, TDO.

7

Applies to IVDD pins. At t

CK

= 30–33 ns, I

DDIN

(typical) = 230 mA; at t

CK

= 40 ns, I

DDIN

(max) = 420 mA and I

DDIN

(typical) = 200 mA; at t

CK

= 50 ns,

I

DDIN

(max) = 370 mA and I

DDIN

(typical) = 115 mA. See “Power Dissipation” for calculation of external (EVDD) supply current for total supply current.

8

Applies to IVDD pins. Idle refers to ADSP-21020 state of operation during execution of the IDLE instruction.

9

Guaranteed but not tested.

10

Applies to all signal pins.

11

Although specified for TTL outputs, all ADSP-21020 outputs are CMOS-compatible and will drive to V

12

Applies to RESET, TRST.

DD

and GND assuming no dc loads.

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V

DD

+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . –0.3 V to V

DD

+ 0.3 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Operating Temperature Range (Ambient) . . –55

°

C to +125

°

C

Storage Temperature Range . . . . . . . . . . . . –65

°

C to +150

°

C

Lead Temperature (10 seconds) CPGA . . . . . . . . . . . +300

°

C

*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD SENSITIVITY

The ADSP-21020 features proprietary input protection circuitry to dissipate high energy discharges

(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-21020 has been classified as a Class 3 device, with the ability to withstand up to 4000 V ESD.

Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. Charges readily accumulate on the human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.

WARNING!

ESD SENSITIVE DEVICE

–12– REV. C

ADSP-21020

TIMING PARAMETERS

General Notes

See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive other specifications.

Clock Signal

K/B/T Grade

20 MHz

Min Max

K/B/T Grade

25 MHz

Min Max

B/T Grade

Min

30 MHz

Max

K Grade

33.3 MHz

Min Max Unit Parameter t

Timing Requirement:

CK t

CKH t

CKL

CLKIN Period

CLKIN Width High

CLKIN Width Low

50

10

10

150 40

10

10

150 33

10

10

150 30

10

10

150 ns ns ns t

CK

CLKIN t

CKH t

CKL

Figure 3. Clock

Reset

K/B/T Grade K/B/T Grade B/T Grade K Grade

Parameter

20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*

Min Max Min Max Min Max Min Max Min Max Unit

Timing Requirement: t

WRST

1 t

SRST

2

RESET Width Low 200

RESET Setup before CLKIN High 29 50

160

24 40

132

21 33

120

19 30

4t

CK

29 + DT/2 30 ns ns

NOTES

DT = t

CK

–50 ns

1

Applies after the power-up sequence is complete. At power up, the Internal Phase Locked Loop requires no more than 1000 CLKIN cycles while RESET is low, assuming stable V

DD

and CLKIN (not including clock oscillator start-up time).

2

Specification only applies in cases where multiple ADSP-21020 processors are required to execute in program counter lock-step (all processors start execution at location 8 in the same cycle). See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for reset sequence information.

CLKIN

RESET t

WRST t

SRST

Figure 4. Reset

REV. C –13–

ADSP-21020

Interrupts



Min Max Min Max Min Max Min Max Min Max Unit Parameter

Timing Requirement: t

SIR t

HIR t

IPW

IRQ

IRQ

IRQ

3-0 Setup before CLKIN High 38

3-0 Hold after CLKIN High

3-0 Pulse Width

0

55

31

0

45

25

0

38

23

0

35

38 + 3DT/4 ns ns t

CK

+ 5 ns

NOTE

*DT = t

CK

– 50 ns

Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting the pulse width is not necessary if the setup and hold is met. Likewise, meeting the setup and hold is not necessary if the pulse width is met. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for interrupt servicing information.

CLKIN t

HIR t

SIR

IRQ3-0 t

IPW

Figure 5. Interrupts

Timer

Parameter t

Switching Characteristic:

DTEX

CLKIN High to TIMEXP

NOTE

*DT = t

CK

– 50 ns



Min Max Min Max Min Max Min Max Min Max Unit

24 24 24 24 ns

CLKIN t

DTEX t

DTEX

TIMEXP

Figure 6. TIMEXP

–14– REV. C

ADSP-21020

Flags


Parameter

20 MHz

Min


1 t

SFI t

HFI t

DWRFI t

HFIWR

FLAG3-0

IN

FLAG3-0

FLAG3-0

IN

FLAG3-0

IN

IN

Deasserted

Setup before CLKIN High 19

Hold after CLKIN High

Delay from xRD, xWR Low

Hold after xRD, xWR

0

0

Max

12

25 MHz

Min

16

0

0

8

14

0

0

30 MHz 33.3 MHz Frequency Dependency*

Max Min Max

5

Min Max

13

0

0

3

Min Max

19 + 5DT/16

Unit ns ns

12 + 7DT/16 ns ns

Switching Characteristic: t

DFO t

HFO t

DFOE t

DFOD

FLAG3-0

FLAG3-0

OUT

OUT

Delay from CLKIN High

Hold after CLKIN High

CLKIN High to FLAG3-0

CLKIN High to FLAG3-0

OUT

OUT

Enable

Disable

5

1

24

24

5

1

24

24

5

1

24

24

5

1

24

24

NOTES

*DT = t

CK

– 50 ns

1 Flag inputs meeting these setup and hold times will affect conditional operations in the next instruction cycle. See the Hardware Configuration chapter of the

ADSP-21020 User’s Manual for additional flag servicing information.

x = PM or DM.

ns ns ns ns

CLKIN

FLAG3-0

OUT t

DFOE t

DFO t

HFO t

DFO t

DFOD

FLAG OUTPUT

CLKIN t

HFI t

SFI

FLAG3-0

IN t

DWRFI t

HFIWR xRD, xWR

FLAG INPUT

Figure 7. Flags

REV. C –15–

ADSP-21020

Bus Request/Bus Grant



Min Max Min Max Min Max Min Max Min Max Unit Parameter t


HBR t

SBR

BR Hold after CLKIN High

BR Setup before CLKIN High

0

18 t


DMDBGL t

DME

Memory Interface Disable to BG Low –2

CLKIN High to Memory Interface

DBGL t

DBGH

Enable

CLKIN High to BG Low

CLKIN High to BG High

25

22

22

0

15

–2

20

22

22

0

13

–2

16

22

22

0

12

–2

15

22

22

18 + 5DT/16

25 + DT/2

NOTES

*DT = t

CK

– 50 ns.

Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.

Buses are not granted until completion of current memory access.

See the Memory Interface chapter of the ADSP-21020 User’s Manual for BG, BR cycle relationships.

ns ns ns ns ns ns

CLKIN t

HBR t

SBR t

HBR t

SBR

BR t

DME

MEMORY

INTERFACE t

DBGL t

DMDBGL t

DBGH

BG

Figure 8. Bus Request/Bus Grant

–16– REV. C

ADSP-21020

External Memory Three-State Control





STS t

DADTS t

DSTS xTS , Setup before CLKIN High xTS xTS

Delay after Address, Select

Delay after XRD, XWR Low

14 t t


DTSD

Memory Interface Disable before

DTSAE

CLKIN High 0 xTS High to Address, Select Enable 0

50

28

16

12

–2

0

40

19

11

10

–4

0

33

13

7

9

–5

0

30 14 + DT/4 t

10

6

DT/4

CK

28 + 7DT/8 ns

16 + DT/2

NOTES

*DT = t

CK

– 50 ns.

xTS should only be asserted (low) during an active memory access cycle.

Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.

Address = PMA23-0, DMA31-0. Select = PMS1-0, DMS3-0.

x = PM or DM.

ns ns ns ns

CLKIN t

STS t

STS

PMTS, DMTS t

DADTS t

DSTS t

DTSD xRD, xWR t

DTSAE

ADDRESS,

SELECTS

DATA

Figure 9. External Memory Three-State Control

REV. C –17–

ADSP-21020

Memory Read


20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependence*



DAD t

DRLD t

HDA

Address, Select to Data Valid xRD Low to Data Valid

Data Hold from Address, Select t

HDRH t

DAAK t

DRAK t

SAK t

HAK

Data Hold from xRD High xACK Delay from Address xACK Delay from xRD Low xACK Setup before CLKIN High xACK Hold after CLKIN High


DARL t

DAP t

DCKRL t

RW t

RWR

Address, Select to xRD Low xPAGE Delay from Address, Select

CLKIN High to xRD Low xRD xRD

Pulse Width

High to xRD, xWD Low

0

–1

14

0

8

16

26

17

37

24

27

15

1

26

0

–1

12

0

4

13

20

13

27

18

18

10

1

24

0

–1

10

0

2

20

13

12

6

NOTES

*DT = t

CK

– 50 ns x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0, DMS3-0.

0

–1

9

0

0

17

11

9

5

14 + DT/4

8 + 3DT/8

37 + DT ns

24 + 5DT/8 ns ns ns

27 + 7DT/8 ns

15 + DT/2 ns ns

1 1

12 22 11 21 16 + DT/4 26 + DT/4

15 13 26 + 5DT/8

11 9 17 + 3DT/8 ns ns ns ns ns ns

–18– REV. C

CLKIN

ADDRESS,

SELECT

DMPAGE,

PMPAGE

DMRD,

PMRD

DATA

DMACK,

PMACK

DMWR,

PMWR t

DAP t

DCKRL t

DARL t

DAAK t

DRAK t

DRLD t

DAD t

RW t

SAK t

HAK t

HDA t

HDRH t

RWR

Figure 10. Memory Read

ADSP-21020

REV. C –19–

ADSP-21020

Memory Write





DAAK t

DWAK t

SAK xACK Delay from Address, Select xACK Delay from xWR Low xACK Setup before CLKIN High t

HAK xACK Hold after CLKIN High

14

0 t t t t t


DAWH

DAWL t

WW t

DDWH t

DWHA

Address, Select to xWR Deasserted 37

Address, Select to xWR Low 11 xWR Pulse Width

Data Setup before xWR High

26

23

HDWH

DAP t

DCKWL t

WWR t

DDWR

WDE

Address, Select Hold after xWR

Deasserted

Data Hold after xWR Deasserted

1 xPAGE Delay from Address, Select

CLKIN High to xWR Low xWR

Data Disable before xWR or xRD

Low xWR

High to xWR or xRD Low

Low to Data Enabled

1

0

16

17

13

0

27

15

1

26

12

0

28

7

20

18

0

–1

13

13

9

–1

18

10

1

24

10

0

21

5

16

14

0

–1

12 22

10

7

–1

12

6

1

9

0

18

3

15

13

0

–1

5

–1

9

5

NOTES

*DT = t

C

– 50 ns

See “System Hold Time Calculation” in “Test Conditions” section for calculating hold times given capacitive and DC loads.

x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0, DMS3-0.

14 + DT/4

11 + 3DT/8

26 + 9DT/16

23 + DT/2

1 + DT/16

DT/16

13 + 3DT/8

DT/16

27 + 7DT/8 ns

15 + DT/2 ns ns

37+ 15DT/16 ns

1

11 21 16 + DT/4 26 + DT/4 ns

8 17 + 7DT/16 ns ns ns ns ns ns ns ns ns ns

–20– REV. C

ADSP-21020

CLKIN

ADDRESS,

SELECT

DMPAGE,

PMPAGE

DMWR,

PMWR

DATA

DMACK,

PMACK

DMRD,

PMRD t

DAP t

DAWL t

DCKWL t

WDE t

DAAK t

DWAK t

DAWH t

WW t

SAK t

DDWH t

HAK t

DWHA t

WWR t

HDWH t

DDWR

Figure 11. Memory Write

REV. C –21–

ADSP-21020

IEEE 1149.1 Test Access Port



Min Max Min Max Min Max Min Max Min Max Unit Parameter t t


TCK

STAP t

HTAP t

SSYS t

HSYS t

TRSTW

TCK Period 50

TDI, TMS Setup before TCK High 5

TDI, TMS Hold after TCK High

System Inputs Setup before TCK High 7

System Inputs Hold after TCK High

TRST Pulse Width

6

9

200 t


DTDO

TDO Delay from TCK Low t

DSYS

System Outputs Delay from TCK Low

15

26

40

5

6

7

9

160

15

26

33

5

6

7

9

132

15

26

30

5

6

7

9

120

15

26 t

CK ns ns

NOTES

*DT = t

C

– 50 ns

System Inputs = PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, CLKIN, IRQ3 0, RESET, FLAG3-0, BR.

System Outputs = PMA23-0, PMS1-0, PMRD, PMWR, PMD47-0, PMPAGE, DMA31-0, DMS1-0, DMRD, DMWR, DMD39-0, DMPAGE, FLAG3-0, BG,

TIMEXP.

See the IEEE 1149.1 Test Access Port chapter of the ADSP-21020 User’s Manual for further detail.

ns ns ns ns ns ns

–22– REV. C

TCK

TMS,TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS t

TCK t

STAP t

HTAP t

DTDO t

SSYS t

HSYS t

DSYS

Figure 12. IEEE 1149.1 Test Access Port

ADSP-21020

REV. C –23–

ADSP-21020

TEST CONDITIONS

Output Disable Time

Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by

∆

V is dependent on the capacitive load, C

L

, and the load current, I

L

. It can be approximated by the following equation: t

DECAY

=

C

L

I

L

∆

V t

The output disable time (t

DIS

) is the difference between

MEASURED

and t

DECAY

as shown in Figure 13. The time t

MEASURED

) is the interval from when the reference signal switches to when the output voltage decays

∆

V from the measured output high or output low voltage. t

DECAY

is calculated with

∆

V equal to 0.5 V, and test loads C

L

and I

L

.

Output Enable Time

Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (t

ENA

) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular system, first calculate t

DECAY

using the above equation. Choose

∆

V to be the difference between the ADSP-21020’s output voltage and the input threshold for the device requiring the hold time. A typical

∆

V will be 0.4 V. C

L

is the total bus capacitance (per data line), and I

L

is the total leakage or three-state current (per data line). The hold time will be t

DECAY

plus the minimum disable time (i.e. t

HDWD

for the write cycle).

I

OL

TO

OUTPUT

PIN

50pF

*

+1.5V

I

OH

*AC TIMING SPECIFICATIONS ARE CALCULATED FOR 100pF

DERATING ON THE FOLLOWING PINS: PMA23–0, PMS1–0, PMRD,

PMWR, PMPAGE, DMA31–0, DMS3–0, DMRD, DMWR, DMPAGE

Figure 14. Equivalent Device Loading For AC

Measurements (Includes All Fixtures)

INPUT OR

OUTPUT

1.5V

1.5V

Figure 15. Voltage Reference Levels For AC

Measurements (Except Output Enable/Disable)

REFERENCE

SIGNAL t

MEASURED t

DIS t

ENA

V

OH (MEASURED)

V

OH (MEASURED) –

∆

V

2.0V

OUTPUT

V

OL (MEASURED) + ∆ V

1.0V

V

OL (MEASURED) t

DECAY

OUTPUT STOPS DRIVING

HIGH-IMPEDANCE STATE. TEST CONDITIONS

CAUSE THIS VOLTAGE LEVEL TO BE

APPROXIMATELY 1.5 V.

Figure 13. Output Enable/Disable

V

OH (MEASURED)

V

OL (MEASURED)

OUTPUT STARTS DRIVING

–24– REV. C

Capacitive Loading

Output delays are based on standard capacitive loads: 100 pF on address, select, page and strobe pins, and 50 pF on all others

(see Figure 14). For different loads, these timing parameters should be derated. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for further information on derating of timing specifications.

Figures 16 and 17 show how the output rise time varies with capacitance. Figures 18 and 19 show how output delays vary with capacitance. Note that the graphs may not be linear outside the ranges shown.

10

9

8

1

7

6

5

4

3

2

1.46

1

1.31

0

25 50

2

75 100 125 150

LOAD CAPACITANCE – pF

NOTES:

(1) OUTPUT PINS BG, TIMEXP

(2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0

175

9.18

3.95

200

Figure 16. Typical Output Rise Time vs. Load

Capacitance (at Maximum Case Temperature)

4

3.59

1

3

3.00

2

1.33

1

0.85

0

25

2

50 75 100 125 150


175 200

NOTES:

(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO

(2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR

π

Figure 17. Typical Output Rise Time vs. Load


ADSP-21020

12

10

11.19

8

1

6

5.34

4

2

2

NOMINAL

– 0.89

–2

25

–1.86

50 75 100 125 150


NOTES:

(1) OUTPUT PINS BG, TIMEXP

(2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0

175

Figure 18. Typical Output Delay or Hold vs. Load


200

1

NOMINAL

3

2

1

2

2.99

2.27

–1

– 1.70

–2

– 2.24

–3

25 50 75 100 125 150 175 200


NOTES:

(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO

(2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR

Figure 19. Typical Output Delay or Hold vs. Load


REV. C –25–

ADSP-21020

ENVIRONMENTAL CONDITIONS

The ADSP-21020 is available in a Ceramic Pin Grid Array

(CPGA). The package uses a cavity-down configuration which gives it favorable thermal characteristics. The top surface of the package contains a raised copper slug from which much of the die heat is dissipated. The slug provides a surface for mounting a heat sink (if required).

The commercial grade (K grade) ADSP-21020 is specified for operation at T

AMB

of 0

°

C to +70

°

C. Maximum T

CASE

(case temperature) can be calculated from the following equation:

T

CASE

=

T

AMB

+

(

PD

× θ

CA

) where PD is power dissipation and

θ

CA

is the case-to-ambient thermal resistance. The value of PD depends on your application; the method for calculating PD is shown under

“Power Dissipation” below.

θ

CA

varies with airflow and with the presence or absence of a heat sink. Table IX shows a range of

θ

CA

values.

Table IX. Maximum

θ

CA

for Various Airflow Values

Airflow (Linear ft./min.) 0 100 200 300

CPGA with No Heat Sink 12.8

°

C/W 9.2

°

C/W 6.6

°

C/W 5.5

°

C/W

NOTES

θ

JC

is approximately 1

°

C/W.

Maximum recommended T

J

is 130

°

C.

As per method 1012 MIL-STD-883. Ambient temperature: 25

°

C. Power:

3.5 W.

Power Dissipation

Total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data values involved.

Internal power dissipation is calculated in the following way:

P

INT

= I

DDIN

3 V

DD

The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on:

1) the number of output pins that switch during each cycle (O),

2) the maximum frequency at which they can switch (f),

3) their load capacitance (C), and

4) their voltage swing (V

DD

).

It is calculated by:

P

EXT

= O 3 C 3 V

DD

2 3 f

The load capacitance should include the processor’s package capacitance (C

IN

). The switching frequency includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2t

CK

). The write strobes can switch every cycle at a frequency of 1/t

CK

. Select pins switch at 1/(2t

CK

), but 2 DM and 2 PM selects can switch on each cycle. If only one bank is accessed, no select line will switch.

Example:

Estimate P

EXT

with the following assumptions:

• A system with one RAM bank each of PM (48 bits) and DM

(32 bits).

• 32K 3 8 RAM chips are used, each with a load of 10 pF.

• Single-precision mode is enabled so that only 32 data pins can switch at once.

• PM and DM writes occur every other cycle, with 50% of the pins switching.

• The instruction cycle rate is 20 MHz (t

CK

= 50 ns) and

V

DD

= 5.0 V.

The P

EXT

equation is calculated for each class of pins that can drive:

Pin

Type

# %

Pins Switch

3 C 3 f 3 V

DD

2

P

EXT

PMA

PMS

15 50

2 0

PMWR 1

PMD 32

—

50

DMA

DMS

15 50

2 0

DMWR 1

DMD 32

—

50

68 pF 5 MHz 25 V

68 pF 5 MHz 25 V

68 pF 10 MHz 25 V

18 pF 5 MHz 25 V

48 pF 5 MHz 25 V

48 pF 5 MHz 25 V

48 pF 10 MHz 25 V

18 pF 5 MHz 25 V

0.064 W

0.000 W

0.017 W

0.036 W

0.045 W

0.000 W

0.012 W

0.036 W

P

EXT

=0.210 W

A typical power consumption can now be calculated for this situation by adding a typical internal power dissipation:

P

TOTAL

= P

EXT

+ (5 V

3 I

DDIN

(typ)) = 0.210 + 1.15

= 1.36 W

Note that the conditions causing a worst case P

EXT

are different from those causing a worst case P

INT

. Maximum P

INT

cannot occur while 100% of the output pins are switching from all ones to all zeros. Also note that it is not common for a program to have 100% or even 50% of the outputs switching simultaneously.

Power and Ground Guidelines

To achieve its fast cycle time, including instruction fetch, data access, and execution, the ADSP-21020 is designed with high speed drivers on all output pins. Large peak currents may pass through a circuit board’s ground and power lines, especially when many output drivers are simultaneously charging or discharging their load capacitances. These transient currents can cause disturbances on the power and ground lines. To minimize these effects, the ADSP-21020 provides separate supply pins for its internal logic (IGND and IVDD) and for its external drivers

(EGND and EVDD).

To reduce system noise at low temperatures when transistors switch fastest, the ADSP-21020 employs compensated output drivers. These drivers equalize slew rate over temperature extremes and process variations. A 1.8 k

Ω

resistor placed between the RCOMP pin and EVDD (+5 V) provides a reference for the compensated drivers. Use of a capacitor

(approximately 100 pF), placed in parallel with the 1.8 k

Ω resistor, is recommended.

–26– REV. C

All GND pins should have a low impedance path to ground. A ground plane is required in ADSP-21020 systems to reduce this impedance, minimizing noise.

The EVDD and IVDD pins should be bypassed to the ground plane using approximately 14 high-frequency capacitors (0.1

µ

F ceramic). Keep each capacitor’s lead and trace length to the pins as short as possible. This low inductive path provides the

ADSP-21020 with the peak currents required when its output drivers switch. The capacitors’ ground leads should also be short and connect directly to the ground plane. This provides a low impedance return path for the load capacitance of the

ADSP-21020’s output drivers.

If a V

DD

plane is not used, the following recommendations apply. Traces from the +5 V supply to the 10 EVDD pins should be designed to satisfy the minimum V while carrying average dc currents of [I

DDEX

DD

specification

/10

3 (number of

EVDD pins per trace)]. I

DDEX

is the calculated external supply current. A similar calculation should be made for the four

IVDD pins using the I

DDIN

specification. The traces connecting

+5 V to the IVDD pins should be separate from those connecting to the EVDD pins.

A low frequency bypass capacitor (20

µ

F tantalum) located near the junction of the IVDD and EVDD traces is also recommended.

Target System Requirements For Use Of EZ-ICE Emulator

The ADSP-21020 EZ-ICE uses the IEEE 1149.1 JTAG test access port of the ADSP-21020 to monitor and control the target board processor during emulation. The EZ-ICE probe requires that CLKIN, TMS, TCK, TRST, TDI, TDO, and

GND be made accessible on the target system via a 12-pin connector (pin strip header) such as that shown in Figure 20.

The EZ-ICE probe plugs directly onto this connector for chip-on-board emulation; you must add this connector to your target board design if you intend to use the ADSP-21020

EZ-ICE. Figure 21 shows the dimensions of the EZ-ICE probe; be sure to allow enough space in your system to fit the probe onto the 12-pin connector.

KEY (NO PIN 1) X CLKIN

BTMS

BTCK

BTRST

TMS

TCK

TRST

BTDI TDI

GND TDO

TOP VIEW

Figure 20. Target Board Connector for EZ-ICE Emulator

(Jumpers In Place)

RIBBON CABLE LENGTH = 60.0 INCHES

2.435 (61.9)

ADSP-21020

0.590

(15.0)

0.2 (5.1)

0.128 (3.25)

0.408 (10.4)

BOTTOM

VIEW

0.92

(23.4)

0.6

(15.2)

2.435

(61.9)

RIBBON

CABLE

ALL DIMENSIONS IN INCHES AND (mm)

Figure 21. EZ-ICE Probe

The 12-pin, 2-row pin strip header is keyed at the Pin 1 location

–you must clip Pin 1 off of the header. The pins must be 0.025

inch square and at least 0.20 inch in length. Pin spacing is

0.1

3 0.1 inches.

The tip of the pins must be at least 0.10 inch higher than the tallest component under the probe to allow clearance for the bottom of the probe. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec.

The length of the traces between the EZ-ICE probe connector and the ADSP-21020 test access port pins should be less than 1 inch. Note that the EZ-ICE probe adds two TTL loads to the

CKIN pin of the ADSP-21020.

The BMTS, BTCK, BTRST, and BTDI signals are provided so that the test access port can also be used for board-level testing.

When the connector is not being used for emulation, place jumpers between the BXXX pins and the XXX pins as shown in

Figure 20. If you are not going to use the test access port for board test, tie BTRST to GND and tie or pull up BTCK to

VDD. The TRST pin must be asserted (pulsed low) after power up (through BTRST on the connector) or held low for proper operation of the ADSP-21020.

REV. C –27–

ADSP-21020

18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

U PMA17 PMA20 TMS EGND TCK EVDD RCOMP EGND PMACK EVDD PMWR EGND PMD44 EGND PMD40 PMD39 PMD35 PMD31 U

T EGND PMA19 PMA23 PMS1 TRST DMWR DMACK CLKIN NC NC PMTS PMD45 PMD42 NC PMD37 PMD32 PMD30 PMD27 T

S PMA11 PMA14 PMA18 PMA22 PMPAGE TDI DMTS DMRD NC PMRD PMD47 PMD43 PMD41 PMD36 PMD34 PMD28 PMD26 PMD21 S

R EGND PMA10 PMA15 PMA16 PMA21 PMS0 TDO IGND RESET IVDD PMD46 IGND PMD38 PMD33 PMD29 PMD25 PMD23 EGND R

P PMA8 PMA9 PMA13 PMA12 PMD24 PMD22 PMD19 PMD18 P

N EVDD PMA5 PMA6 PMA7 PMD20 PMD17 PMD16 EVDD N

M PMA1 PMA4 PMA3 PMA2

L EGND PMA0 TIMEXP IGND

PMD15 PMD14 PMD13 PMD12 M

IGND PMD10 PMD11 EGND L

K EVDD NC IRQ2 IRQ3

J EVDD IRQ0 IRQ1 IVDD

ADSP-21020

TOP VIEW

(PINS DOWN)

PMD6

IVDD

PMD7 PMD8

PMD2 PMD5

PMD9 K

EVDD J

H EGND FLAG2 FLAG0 FLAG1

G FLAG3 DMA1 DMA0 IGND

DMD1 DMD0 PMD3 PMD4 H

IGND DMD3 NC EGND G

DMD9 DMD6 PMD0 PMD1 F F DMA2 DMA3 DMA4 DMA5

E

DMA6 DMA7 DMA8 DMA10

DMD13 DMD10 DMD2 EGND E

D DMA9 DMA11 DMA12 DMA15 DMA19 DMA23 DMA27 IGND DMS0 IVDD DMD36 DMD31 DMD27 DMD22 DMD17 DMD11 DMD5 DMD4 D

C DMA13 DMA14 DMA18 DMA20 DMA24 DMA28 DMA31 DMS1 NC DMD38 DMD35 DMD30 DMD28 DMD24 DMD20 DMD15 DMD8 DMD7 C

B DMA16 DMA17 DMA21 DMA25 DMA26 DMA30 DMPAGE DMS3 DMD39 DMD37 DMD33 DMD32 DMD26 DMD25 DMD21 DMD18 DMD14 DMD12 B

A BR

18

BG DMA22 EGND DMA29 EVDD DMS2 EGND DMD34 EVDD DMD29 EGND DMD23 EVDD DMD19 EGND DMD16

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A

–28– REV. C

ADSP-21020

1 2 3 4 5 6 7 8 9 10 11 12 13

U PMD31 PMD35 PMD39 PMD40 EGND PMD44 EGND PMWR EVDD PMACK EGND RCOMP EVDD

14

TCK

15

EGND

16 17 18

TMS PMA20 PMA17

U

T PMD27 PMD30 PMD32 PMD37 NC PMD42 PMD45 PMTS NC NC CLKIN DMACK DMWR TRST PMS1 PMA23 PMA19 EGND

T

S PMD21 PMD26 PMD28 PMD34 PMD36 PMD41 PMD43 PMD47 PMRD NC DMRD DMTS TDI PMPAGE PMA22 PMA18 PMA14 PMA11 S

R EGND PMD23 PMD25 PMD29 PMD33 PMD38 IGND PMD46 IVDD RESET IGND TDO PMS0 PMA21 PMA16 PMA15 PMA10 EGND R

P PMD18 PMD19 PMD22 PMD24 PMA12 PMA13 PMA9 PMA8 P

N EVDD PMD16 PMD17 PMD20

M PMD12 PMD13 PMD14 PMD15

L EGND PMD11 PMD10 IGND

K PMD9 PMD8 PMD7 PMD6

J EVDD PMD5 PMD2 IVDD

H PMD4 PMD3 DMD0 DMD1

ADSP-21020

BOTTOM VIEW

(PINS UP)

PMA7

PMA2

PMA6 PMA5

IRQ3 IRQ2

IVDD IRQ1

EVDD N

PMA3 PMA4 PMA1 M

IGND TIMEXP PMA0 EGND L

NC EVDD K

IRQ0 EVDD J

FLAG1 FLAG0 FLAG2 EGND H

G

F

E

EGND

PMD1

EGND

NC

PMD0

DMD2

DMD3

DMD6

IGND

DMD9

DMD10 DMD13

IGND DMA0 DMA1 FLAG3 G

DMA5 DMA4 DMA3 DMA2 F

DMA10 DMA8 DMA7 DMA6 E

D DMD4 DMD5 DMD11 DMD17 DMD22 DMD27 DMD31 DMD36 IVDD DMS0 IGND DMA27 DMA23 DMA19 DMA15 DMA12 DMA11 DMA9 D

C DMD7 DMD8 DMD15 DMD20 DMD24 DMD28 DMD30 DMD35 DMD38 NC DMS1 DMA31 DMA28 DMA24 DMA20 DMA18 DMA14 DMA13

C

B

DMD12 DMD14 DMD18 DMD21 DMD25 DMD26 DMD32 DMD33 DMD37 DMD39 DMS3 DMPAGE DMA30 DMA26 DMA25 DMA21 DMA17 DMA16

B

A

1

DMD16 EGND DMD19 EVDD DMD23 EGND DMD29 EVDD DMD34 EGND DMS2 EVDD DMA29 EGND DMA22 BG

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

BR

18

A

REV. C –29–

ADSP-21020

B3

A4

C4

B4

B2

C3

A2

D4

D5

A6

C5

E3

D3

B1

E4

F3

C1

C2

F4

E2

G3

D1

D2

B13

C12

H3

H4

A16

D13

C14

B15

B14

D12

C13

A14

C17

D15

B18

B17

C16

D14

C15

B16

E18

E17

E16

D18

E15

D17

D16

C18

PGA

LOCATION

G16

G17

F18

F17

F16

F15

DMD14

DMD15

DMD16

DMD17

DMD18

DMDl9

DMD20

DMD21

DMD22

DMD23

DMD24

DMA30

DMA31

DMD0

DMD1

DMD2

DMD3

DMD4

DMD5

DMD6

DMD7

DMD8

DMD9

DMD10

DMD11

DMD12

DMD13

DMA14

DMA15

DMA16

DMA17

DMA18

DMA19

DMA20

DMA21

DMA22

DMA23

DMA24

DMA25

DMA26

DMA27

DMA28

DMA29

PIN

NAME

DMA0

DMA1

DMA2

DMA3

DMA4

DMA5

DMA6

DMA7

DMA8

DMA9

DMA10

DMA11

DMA12

DMA13

PMA22

PMA23

PMD0

PMD1

PMD2

PMD3

PMD4

PMD5

PMD6

PMD7

PMD8

PMA14

PMA15

PMA16

PMA17

PMA18

PMA19

PMA20

PMA21

PMA6

PMA7

PMA8

PMA9

PMA10

PMA11

PMA12

PMA13

DMD39

DMS0

DMS1

DMS2

DMS3

DMWR

DMRD

DMPAGE

DMTS

DMACK

PMA0

PMA1

PMA2

PMA3

PMA4

PMA5

PIN

NAME

DMD25

DMD26

DMD27

DMD28

DMD29

DMD30

DMD31

DMD32

DMD33

DMD34

DMD35

DMD36

DMD37

DMD38

J3

H2

H1

J2

S15

T16

F2

F1

K4

K3

K2

S17

R16

R15

U18

S16

T17

U17

R14

N16

N15

P18

P17

R17

S18

P15

P16

S12

T12

L17

M18

M15

M16

M17

N17

B10

D10

C11

A12

B11

T13

S11

B12

C8

D8

B9

C9

D7

B7

B8

A10

D6

C6

A8

C7

PGA

LOCATION

B5

B6

–30–

BG

BR

FLAG0

FLAG1

FLAG2

FLAG3

IRQ0

IRQ1

IRQ2

IRQ3

RESET

PMD39

PMD40

PMD41

PMD42

PMD43

PMD44

PMD45

PMD46

PMD47

PMS0

PMS1

PMWR

PMRD

PMPAGE

PMTS

PMACK

PMD31

PMD32

PMD33

PMD34

PMD35

PMD36

PMD37

PMD38

PMD23

PMD24

PMD25

PMD26

PMD27

PMD28

PMD29

PMD30

PMD15

PMD16

PMD17

PMD18

PMD19

PMD20

PMD21

PMD22

PIN

NAME

PMD9

PMD10

PMD11

PMD12

PMD13

PMD14

A17

A18

H16

H15

H17

G18

J17

J16

K16

K15

R10

S8

R13

T15

U8

S9

S14

T8

U10

S7

U6

T7

R8

U3

U4

S6

T6

U2

S5

T4

R6

U1

T3

R5

S4

T1

S3

R4

T2

R2

P4

R3

S2

P2

N4

S1

P3

M4

N2

N3

P1

L2

M1

M2

M3

PGA

LOCATION

K1

L3

NC

NC

NC

NC

NC

NC

EVDD

EVDD

EVDD

IVDD

IVDD

IVDD

IVDD

NC

IGND

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EVDD

EGND

EGND

IGND

IGND

IGND

IGND

IGND

IGND

EGND

EGND

EGND

EGND

EGND

EGND

EGND

EGND

TMS

TCK

EGND

EGND

EGND

EGND

EGND

EGND

PIN

NAME

TIMEXP

RCOMP

CLKIN

TRST

TD0

TDI

U9

U13

K18

D9

J4

J15

R9

C10

R11

A5

A9

A13

J1

J18

N1

N18

S10

T10

T9

K17

T5

G2

U11

U15

D11

G4

G15

L4

L15

R7

G1

L1

L18

R1

R18

T18

U5

U7

U16

U14

H18

A3

A7

A11

A15

E1

PGA

LOCATION

L16

U12

T11

T14

R12

S13

REV. C

REV. C

D j

2

L

3

A

φ b

D j

1

ADSP-21020

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

223-Pin Ceramic Pin Grid Array h

A

1 e

1 e

1

TOP VIEW

A B C D E F G H J K L M N P R S T U

18

17

16

15

14

13

12

11

8

7

10

9

6

5

4

3

2

1 e

φ b

1

SYMBOL MIN

INCHES

MAX

A 0.084

MILLIMETERS

MIN

0.102

2.11

MAX

2.59

A

1

φ b

φ b

1

D e

1 e

L

3 h

0.40

1.844

0.60

0.018 TYP

0.050 TYP

1.876

1.700 TYP

0.100 TYP

0.172

0.188

1.02

46.84

4.37

1.52

0.46 TYP

1.27 TYP

47.64

43.18 TYP

2.54 TYP

4.77

0.020 TYP 0.500 TYP j

1

1.125

1.147

28.56

29.14

j

2

1.065

1.186

27.05

27.61

NOTE

When socketing the CPGA package, use of a low insertion force socket is recommended.

–31–

ADSP-21020

Part Number*

ADSP-21020KG-80

ADSP-21020KG-100

ADSP-21020KG-133

ADSP-21020BG-80

ADSP-21020BG-100

ADSP-21020BG-120

ADSP-21020TG-80

ADSP-21020TG-100

ADSP-21020TG-120

ADSP-21020TG-80/883B

ADSP-21020TG-100/883B

ADSP-21020TG-120/883B

*G = Ceramic Pin Grid Array.

ORDERING GUIDE

Ambient Temperature

Range

0

°

C to +70

°

C

0

°

C to +70

°

C

0

°

C to +70

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–40

°

C to +85

°

C

–55

°

C to +125

°

C

–55

°

C to +125

°

C

–55

°

C to +125

°

C

–55

°

C to +125

°

C

–55

°

C to +125

°

C

–55

°

C to +125

°

C

Instruction

Rate (MHz)

20

25

33.3

20

25

30

20

25

30

20

25

30

Cycle Time

(ns)

50

40

33.3

50

40

33.3

50

40

30

50

40

33.3

Package

223-Lead Ceramic Pin Grid Array












–32– REV. C

Analog Devices ADSP-21020 User's Manual

32/40-Bit IEEE Floating-Point

DSP Microprocessor

ADSP-21020

WARNING!

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Table of contents

Analog Devices ADSP-21020 User's Manual

32/40-Bit IEEE Floating-Point

DSP Microprocessor

ADSP-21020

WARNING!

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Table of contents