TIMING PARAMETERS. Analog Devices ADSP-21020, SHARC ADSP-21020

ADSP-21020

TIMING PARAMETERS

General Notes

See Figure 15 on page 24 for voltage reference levels. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive other specifications.

Clock Signal

K/B/T Grade

20 MHz

Min Max

K/B/T Grade

25 MHz

Min Max

B/T Grade

Min

30 MHz

Max

K Grade

33.3 MHz

Min Max Unit Parameter t

Timing Requirement:

CK t

CKH t

CKL

CLKIN Period

CLKIN Width High

CLKIN Width Low

50

10

10

150 40

10

10

150 33

10

10

150 30

10

10

150 ns ns ns t

CK

CLKIN t

CKH t

CKL

Figure 3. Clock

Reset

K/B/T Grade K/B/T Grade B/T Grade K Grade

Parameter

20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*

Min Max Min Max Min Max Min Max Min Max Unit

Timing Requirement: t

WRST

1 t

SRST

2

RESET Width Low 200

RESET Setup before CLKIN High 29 50

160

24 40

132

21 33

120

19 30

4t

CK

29 + DT/2 30 ns ns

NOTES

DT = t

CK

–50 ns

1

Applies after the power-up sequence is complete. At power up, the Internal Phase Locked Loop requires no more than 1000 CLKIN cycles while RESET is low, assuming stable V

DD

and CLKIN (not including clock oscillator start-up time).

2

Specification only applies in cases where multiple ADSP-21020 processors are required to execute in program counter lock-step (all processors start execution at location 8 in the same cycle). See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for reset sequence information.

CLKIN

RESET t

WRST t

SRST

Figure 4. Reset

REV. C –13–

ADSP-21020

Interrupts

K/B/T Grade K/B/T Grade B/T Grade K Grade

20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*

Min Max Min Max Min Max Min Max Min Max Unit Parameter

Timing Requirement: t

SIR t

HIR t

IPW

IRQ

IRQ

IRQ

3-0 Setup before CLKIN High 38

3-0 Hold after CLKIN High

3-0 Pulse Width

0

55

31

0

45

25

0

38

23

0

35

38 + 3DT/4 ns ns t

CK

+ 5 ns

NOTE

*DT = t

CK

– 50 ns

Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting the pulse width is not necessary if the setup and hold is met. Likewise, meeting the setup and hold is not necessary if the pulse width is met. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for interrupt servicing information.

CLKIN t

HIR t

SIR

IRQ3-0 t

IPW

Figure 5. Interrupts

Timer

Parameter t

Switching Characteristic:

DTEX

CLKIN High to TIMEXP

NOTE

*DT = t

CK

– 50 ns

K/B/T Grade K/B/T Grade B/T Grade K Grade

20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*

Min Max Min Max Min Max Min Max Min Max Unit

24 24 24 24 ns

CLKIN t

DTEX t

DTEX

TIMEXP

Figure 6. TIMEXP

–14– REV. C

ADSP-21020

Flags

K/B/T Grade K/B/T Grade B/T Grade K Grade

Parameter

20 MHz

Min

Timing Requirement:

1 t

SFI t

HFI t

DWRFI t

HFIWR

FLAG3-0

IN

FLAG3-0

FLAG3-0

IN

FLAG3-0

IN

IN

Deasserted

Setup before CLKIN High 19

Hold after CLKIN High

Delay from xRD, xWR Low

Hold after xRD, xWR

0

0

Max

12

25 MHz

Min

16

0

0

8

14

0

0

30 MHz 33.3 MHz Frequency Dependency*

Max Min Max

5

Min Max

13

0

0

3

Min Max

19 + 5DT/16

Unit ns ns

12 + 7DT/16 ns ns

Switching Characteristic: t

DFO t

HFO t

DFOE t

DFOD

FLAG3-0

FLAG3-0

OUT

OUT

Delay from CLKIN High

Hold after CLKIN High

CLKIN High to FLAG3-0

CLKIN High to FLAG3-0

OUT

OUT

Enable

Disable

5

1

24

24

5

1

24

24

5

1

24

24

5

1

24

24

NOTES

*DT = t

CK

– 50 ns

1 Flag inputs meeting these setup and hold times will affect conditional operations in the next instruction cycle. See the Hardware Configuration chapter of the

ADSP-21020 User’s Manual for additional flag servicing information.

x = PM or DM.

ns ns ns ns

CLKIN

FLAG3-0

OUT t

DFOE t

DFO t

HFO t

DFO t

DFOD

FLAG OUTPUT

CLKIN t

HFI t

SFI

FLAG3-0

IN t

DWRFI t

HFIWR xRD, xWR

FLAG INPUT

Figure 7. Flags

REV. C –15–

ADSP-21020

Bus Request/Bus Grant

K/B/T Grade K/B/T Grade B/T Grade K Grade

20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*

Min Max Min Max Min Max Min Max Min Max Unit Parameter t

Timing Requirement:

HBR t

SBR

BR Hold after CLKIN High

BR Setup before CLKIN High

0

18 t

Switching Characteristic: t

DMDBGL t

DME

Memory Interface Disable to BG Low –2

CLKIN High to Memory Interface

DBGL t

DBGH

Enable

CLKIN High to BG Low

CLKIN High to BG High

25

22

22

0

15

–2

20

22

22

0

13

–2

16

22

22

0

12

–2

15

22

22

18 + 5DT/16

25 + DT/2

NOTES

*DT = t

CK

– 50 ns.

Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.

Buses are not granted until completion of current memory access.

See the Memory Interface chapter of the ADSP-21020 User’s Manual for BG, BR cycle relationships.

ns ns ns ns ns ns

CLKIN t

HBR t

SBR t

HBR t

SBR

BR t

DME

MEMORY

INTERFACE t

DBGL t

DMDBGL t

DBGH

BG

Figure 8. Bus Request/Bus Grant

–16– REV. C

ADSP-21020

External Memory Three-State Control

K/B/T Grade K/B/T Grade B/T Grade K Grade

20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*

Min Max Min Max Min Max Min Max Min Max Unit Parameter t

Timing Requirement:

STS t

DADTS t

DSTS xTS , Setup before CLKIN High xTS xTS

Delay after Address, Select

Delay after XRD, XWR Low

14 t t

Switching Characteristic:

DTSD

Memory Interface Disable before

DTSAE

CLKIN High 0 xTS High to Address, Select Enable 0

50

28

16

12

–2

0

40

19

11

10

–4

0

33

13

7

9

–5

0

30 14 + DT/4 t

10

6

DT/4

CK

28 + 7DT/8 ns

16 + DT/2

NOTES

*DT = t

CK

– 50 ns.

xTS should only be asserted (low) during an active memory access cycle.

Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.

Address = PMA23-0, DMA31-0. Select = PMS1-0, DMS3-0.

x = PM or DM.

ns ns ns ns

CLKIN t

STS t

STS

PMTS, DMTS t

DADTS t

DSTS t

DTSD xRD, xWR t

DTSAE

ADDRESS,

SELECTS

DATA

Figure 9. External Memory Three-State Control

REV. C –17–

ADSP-21020

Memory Read

K/B/T Grade K/B/T Grade B/T Grade K Grade

20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependence*

Min Max Min Max Min Max Min Max Min Max Unit Parameter t

Timing Requirement:

DAD t

DRLD t

HDA

Address, Select to Data Valid xRD Low to Data Valid

Data Hold from Address, Select t

HDRH t

DAAK t

DRAK t

SAK t

HAK

Data Hold from xRD High xACK Delay from Address xACK Delay from xRD Low xACK Setup before CLKIN High xACK Hold after CLKIN High

Switching Characteristic: t

DARL t

DAP t

DCKRL t

RW t

RWR

Address, Select to xRD Low xPAGE Delay from Address, Select

CLKIN High to xRD Low xRD xRD

Pulse Width

High to xRD, xWD Low

0

–1

14

0

8

16

26

17

37

24

27

15

1

26

0

–1

12

0

4

13

20

13

27

18

18

10

1

24

0

–1

10

0

2

20

13

12

6

NOTES

*DT = t

CK

– 50 ns x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0, DMS3-0.

0

–1

9

0

0

17

11

9

5

14 + DT/4

8 + 3DT/8

37 + DT ns

24 + 5DT/8 ns ns ns

27 + 7DT/8 ns

15 + DT/2 ns ns

1 1

12 22 11 21 16 + DT/4 26 + DT/4

15 13 26 + 5DT/8

11 9 17 + 3DT/8 ns ns ns ns ns ns

–18– REV. C

CLKIN

ADDRESS,

SELECT

DMPAGE,

PMPAGE

DMRD,

PMRD

DATA

DMACK,

PMACK

DMWR,

PMWR t

DAP t

DCKRL t

DARL t

DAAK t

DRAK t

DRLD t

DAD t

RW t

SAK t

HAK t

HDA t

HDRH t

RWR

Figure 10. Memory Read

ADSP-21020

REV. C –19–

ADSP-21020

Memory Write

K/B/T Grade K/B/T Grade B/T Grade K Grade

20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*

Min Max Min Max Min Max Min Max Min Max Unit Parameter t

Timing Requirement:

DAAK t

DWAK t

SAK xACK Delay from Address, Select xACK Delay from xWR Low xACK Setup before CLKIN High t

HAK xACK Hold after CLKIN High

14

0 t t t t t

Switching Characteristic:

DAWH

DAWL t

WW t

DDWH t

DWHA

Address, Select to xWR Deasserted 37

Address, Select to xWR Low 11 xWR Pulse Width

Data Setup before xWR High

26

23

HDWH

DAP t

DCKWL t

WWR t

DDWR

WDE

Address, Select Hold after xWR

Deasserted

Data Hold after xWR Deasserted

1 xPAGE Delay from Address, Select

CLKIN High to xWR Low xWR

Data Disable before xWR or xRD

Low xWR

High to xWR or xRD Low

Low to Data Enabled

1

0

16

17

13

0

27

15

1

26

12

0

28

7

20

18

0

–1

13

13

9

–1

18

10

1

24

10

0

21

5

16

14

0

–1

12 22

10

7

–1

12

6

1

9

0

18

3

15

13

0

–1

5

–1

9

5

NOTES

*DT = t

C

– 50 ns

See “System Hold Time Calculation” in “Test Conditions” section for calculating hold times given capacitive and DC loads.

x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0, DMS3-0.

14 + DT/4

11 + 3DT/8

26 + 9DT/16

23 + DT/2

1 + DT/16

DT/16

13 + 3DT/8

DT/16

27 + 7DT/8 ns

15 + DT/2 ns ns

37+ 15DT/16 ns

1

11 21 16 + DT/4 26 + DT/4 ns

8 17 + 7DT/16 ns ns ns ns ns ns ns ns ns ns

–20– REV. C

ADSP-21020

CLKIN

ADDRESS,

SELECT

DMPAGE,

PMPAGE

DMWR,

PMWR

DATA

DMACK,

PMACK

DMRD,

PMRD t

DAP t

DAWL t

DCKWL t

WDE t

DAAK t

DWAK t

DAWH t

WW t

SAK t

DDWH t

HAK t

DWHA t

WWR t

HDWH t

DDWR

Figure 11. Memory Write

REV. C –21–

ADSP-21020

IEEE 1149.1 Test Access Port

K/B/T Grade K/B/T Grade B/T Grade K Grade

20 MHz 25 MHz 30 MHz 33.3 MHz Frequency Dependency*

Min Max Min Max Min Max Min Max Min Max Unit Parameter t t

Timing Requirement:

TCK

STAP t

HTAP t

SSYS t

HSYS t

TRSTW

TCK Period 50

TDI, TMS Setup before TCK High 5

TDI, TMS Hold after TCK High

System Inputs Setup before TCK High 7

System Inputs Hold after TCK High

TRST Pulse Width

6

9

200 t

Switching Characteristic:

DTDO

TDO Delay from TCK Low t

DSYS

System Outputs Delay from TCK Low

15

26

40

5

6

7

9

160

15

26

33

5

6

7

9

132

15

26

30

5

6

7

9

120

15

26 t

CK ns ns

NOTES

*DT = t

C

– 50 ns

System Inputs = PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, CLKIN, IRQ3 0, RESET, FLAG3-0, BR.

System Outputs = PMA23-0, PMS1-0, PMRD, PMWR, PMD47-0, PMPAGE, DMA31-0, DMS1-0, DMRD, DMWR, DMD39-0, DMPAGE, FLAG3-0, BG,

TIMEXP.

See the IEEE 1149.1 Test Access Port chapter of the ADSP-21020 User’s Manual for further detail.

ns ns ns ns ns ns

–22– REV. C

TCK

TMS,TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS t

TCK t

STAP t

HTAP t

DTDO t

SSYS t

HSYS t

DSYS

Figure 12. IEEE 1149.1 Test Access Port

ADSP-21020

REV. C –23–