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PRELIMINARY
CY14B104K, CY14B104M
4 Mbit (512K x 8/256K x 16) nvSRAM with
Real Time Clock
Features
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 512K x 8 (CY14B104K) or 256K x 16
(CY14B104M)
■ Hands off automatic STORE on power down with only a small capacitor
■ STORE to QuantumTrap
®
nonvolatile elements is initiated by software, device pin, or AutoStore
®
on power down
■ RECALL to SRAM initiated by software or power up
■ High reliability
■ Infinite Read, Write, and RECALL cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3V +20%, –10% operation
■ Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock
■ Watchdog timer
■ Clock alarm with programmable interrupts
■ Capacitor or battery backup for RTC
■ Commercial and industrial temperatures
■ 44 and 54-pin TSOP II package
■ Pb-free and RoHS compliance
Functional Description
The Cypress CY14B104K/CY14B104M combines a 4-Mbit nonvolatile static RAM with a full featured Real Time Clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM is read and written infinite number of times, while independent nonvolatile data resides in the nonvolatile elements.
The Real Time Clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator.
The alarm function is programmable for periodic minutes, hours, days or months alarms. There is also a programmable watchdog timer for process control.
Logic Block Diagram
A
A
A
0
1
A
A
2
3
A
A
A
A
A
4
5
6
7
8
17
A
18
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
D
E
R
D
E
C
O
R
O
W
T
B
U
F
I
N
P
U
F
E
R
S
STATIC RAM
ARRAY
2048 X 2048
Quatrum
Trap
2048 X 2048
STORE
RECALL
COLUMN I/O
COLUMN DEC
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
V
CC
V
CA
P
POWER
CONTROL
STORE/RECALL
CONTROL
SOFTWARE
DETECT
V
RTCbat
V
RTCcap
HSB
A
14
- A
2
RTC
MUX
X
1
X
2
INT
A
18
- A
0
OE
WE
CE
BLE
BHE
Notes
1. Address A
0
- A
2. Data DQ
0
- DQ
18
for x8 configuration and Address A
7
for x8 configuration and Data DQ
0
0
- A
17
- DQ
3. BHE and BLE are applicable for x16 configuration only.
15
for x16 configuration.
for x16 configuration.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-07103 Rev. *K
• San Jose
,
CA 95134-1709 • 408-943-2600
Revised January 29, 2009
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PRELIMINARY
CY14B104K, CY14B104M
Pinouts
INT
NC
WE
A
5
A
6
A
7
A
8
A
9
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
A
3
A
4
CE
A
0
A
1
A
2
X1
X2
6
7
8
4
5
9
10
11
12
1
2
3
13
14
15
16
17
18
19
20
21
22
44 - TSOP II
(x8)
Top View
(not to scale)
41
40
39
38
37
36
35
44
43
42
34
33
32
31
27
26
25
24
23
30
29
28
A
16
A
15
OE
DQ
7
DQ
6
V
SS
V
CC
DQ5
HSB
NC
NC
A
18
A
17
DQ4
V
CAP
A
14
A
13
A
12
A
11
A
10
V
RTCcap
V
RTCbat
Figure 1. Pin Diagram - 44-PIn and 54-Pin TSOP II
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
NC
X1
X2
6
7
8
4
5
1
2
3
15
16
17
18
9
10
11
12
13
14
19
20
21
22
23
24
25
26
27
54 - TSOP II
(x16)
Top View
(not to scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
54
53
52
51
50
49
34
33
32
31
30
29
28
NC
A
17
A
16
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
V
V
RTCcap
RTCbat
Table 1. Pin Definitions
Pin Name
A
0
– A
18
A
0
– A
17
DQ
0
– DQ
7
DQ
0
– DQ
15
NC
WE
CE
OE
BHE
BLE
X
1
X
2
V
RTCcap
V
RTCbat
I/O Type
Input
Description
Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
Input/Output Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on operation.
No Connect No Connects. This pin is not connected to the die.
Input
Input
Input
Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input
Input
Output
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tri-state.
Byte High Enable, Active LOW. Controls DQ
15
- DQ
8
.
Byte Low Enable, Active LOW. Controls DQ
7
- DQ
0
.
Crystal Connection. Drives crystal on start up.
Input Crystal Connection. For 32.768 KHz crystal.
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if V
RTCbat
is used.
Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if V
RTCcap
is used.
Notes
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
Document #: 001-07103 Rev. *K Page 2 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Table 1. Pin Definitions (continued)
Pin Name
INT
V
V
SS
CC
HSB
V
CAP
I/O Type
Output
Description
Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
Ground for the Device. Must be connected to ground of the system.
Ground
Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation
HSB is driven HIGH for short time with standard output high current.
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements.
Device Operation
The CY14B104K/CY14B104M nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations SRAM read and write operations are inhibited. The
CY14B104K/CY14B104M supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations. See the
“Truth Table For SRAM Operations” on page 23
for a complete description of read and write modes.
SRAM Read
The CY14B104K/CY14B104M performs a read cycle whenever
CE and OE are LOW, and WE and HSB are HIGH. The address specified on pins A
0-18
or A
0-17
determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of t
AA
(read cycle 1). If the read is initiated by CE or OE, the outputs are valid at t
ACE
or at t t
DOE
, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the
AA
access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DO are written into the memory if it is valid t
SD
0-15
before the end of a
WE controlled write or before the end of a CE controlled write.
The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers t
HZWE after WE goes LOW.
AutoStore Operation
The CY14B104K/CY14B104M stores data to the nvSRAM using one of three storage operations. These three operations are:
Hardware STORE, activated by the HSB; Software STORE, activated by an address sequence; AutoStore, on device power down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B104K/CY14B104M.
During normal operation, the device draws current from V charge a capacitor connected to the V charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
CAP
pin. This stored
pin drops below V automatically disconnects the V
CAP
SWITCH
pin from V
CC
CC
to
, the part operation is initiated with power provided by the V
. A STORE
CAP
capacitor.
Figure 2. AutoStore Mode
Vcc
WE
Vcc
V
SS
V
CAP
0.1uF
V
CAP
shows the proper connection of the storage capacitor
(V
CAP
) for automatic STORE operation. Refer to DC Electrical
on the V
CAP
on page 14 for the size of the V
pin is driven to V
CC
CAP
. The voltage by a regulator on the chip. A pull up should be placed on WE to hold it inactive during power up.
This pull up is only effective if the WE signal is tri-state during power up. Many MPUs tri-state their controls on power up. Verify this when using the pull up. When the nvSRAM comes out of
Document #: 001-07103 Rev. *K Page 3 of 31
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PRELIMINARY
CY14B104K, CY14B104M power-on-recall, the MPU must be active or the WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore cycle is in progress.
Hardware STORE (HSB) Operation
The CY14B104K/CY14B104M provides the HSB pin to control and acknowledge the STORE operations. The HSB pin is used to request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B104K/CY14B104M conditionally initiates a
STORE operation after t
DELAY
. An actual STORE cycle begins only if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress.
SRAM read and write operations, that are in progress when HSB is driven LOW by any means, are given time t
DELAY to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until
HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B104K/CY14B104M but any SRAM read and write cycles are inhibited until HSB is returned HIGH by
MPU or external source.
During any STORE operation, regardless of how it is initiated, the CY14B104KA/CY14B104MA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the
CY14B104K/CY14B104M remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used.
Hardware RECALL (Power Up)
During power up or after any low power condition
(V
V
CC
CC
< V
SWITCH
), an internal RECALL request is latched. When
again exceeds the V
SWITCH
on powerup, a RECALL cycle is automatically initiated and takes t
HRECALL
to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B104K/CY14B104M
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE or OE controlled reads. Both CE and OE must be toggled for the sequence to be executed. After the sixth address in the sequence is entered, the
STORE cycle starts and the chip is disabled. It is important to use read cycles and not write cycles in the sequence. The SRAM is activated again for read and write operations after the t
STORE cycle time.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, perform the following sequence of CE or OE controlled read operations:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
RECALL
cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
Document #: 001-07103 Rev. *K Page 4 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Table 2. Mode Selection
CE
H
L
L
L
WE
X
H
L
H
L
L
L
H
H
H
OE, BHE, BLE
X
L
X
L
L
L
L
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a
A
15
- A
X
X
X
0
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Mode
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
I/O
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Standby
Active
Active
Active
Active
Active I
CC2
Active
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) issued to save the
AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
Notes
6. While there are 19 address lines on the CY14B104K (18 address lines on the CY14B104M), only the 13 address lines (A
14
- A
2
) are used to control software modes.
Rest of the address lines are don’t care.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-07103 Rev. *K Page 5 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Data Protection
The CY14B104K/CY14B104M protects data from corruption during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is detected when V
CC
is less than V
SWITCH
. If the
CY14B104K/CY14B104M is in a write mode (both CE and WE are LOW) at power up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after t or brown out conditions.
LZHSB
(HSB to output active). This protects against inadvertent writes during power up
Noise Considerations
Refer to CY application note AN1064 .
Real Time Clock Operation nvTIME Operation
The CY14B104K/CY14B104M offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions.
RTC registers use the last 16 address locations of the SRAM.
Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation. Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. Clock and alarm registers store data in BCD format.
RTC functionality is described with respect to CY14B104K in the following sections. The same description applies to
CY14B104M, except for the RTC register addresses. The RTC register addresses for CY14B104K range from 0x7FFF0 to
0x7FFFF, while those for CY14B104M range from 0x3FFF0 to
on page 10 and Table 5 on page 11
for a detailed Register Map description.
Clock Operations
The clock registers maintain time up to 9,999 years in one second increments. The time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits defined as ‘0’ are currently not used and are reserved for future use by Cypress.
Reading the Clock
The double buffered RTC register structure reduces the chance of reading incorrect data from the clock. The user must stop internal updates to the CY14B104K time keeping registers before reading clock data, to prevent reading of data in transition.
Stopping the register updates does not affect clock accuracy.
The updating process is stopped by writing a ‘1’ to the read bit
‘R’ (in the flags register at 0x7FFF0), and does not restart until a
‘0’ is written to the read bit. The RTC registers are then read while the internal clock continues to run. After a ‘0’ is written to the read bit (‘R’), all RTC registers are simultaneously updated within
20 ms
Document #: 001-07103 Rev. *K
Setting the Clock
Setting the write bit ‘W’ (in the flags register at 0x7FFF0) to a ‘1’ stops updates to the time keeping registers and enables the time to be set. The correct day, date, and time is then written into the registers and must be in 24 hour BCD format. The time written is referred to as the “Base Time”. This value is stored in nonvolatile registers and used in the calculation of the current time.
Resetting the write bit to ‘0’ transfers the values of timekeeping registers to the actual clock counters, after which the clock resumes normal operation.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue counting to 0xF before rolling over to 0x0 after which RTC resumes normal operation.
Note The values entered in the timekeeping, alarm, calibration, and interrupt registers need a STORE operation to be saved in nonvolatile memory. Therefore, while working in AutoStore disabled mode, the user must perform a STORE operation after writing into the RTC registers for the RTC to work correctly.
Backup Power
The RTC in the CY14B104K is intended for permanently powered operation. The V
RTCcap
or V application. When the primary power, V
V
SWITCH
RTCbat
pin is connected depending on whether a capacitor or battery is chosen for the
CC
, fails and drops below
the device switches to the backup power supply.
The clock oscillator uses very little current, which maximizes the backup time available from the backup source. Regardless of the clock operation with the primary source removed, the data stored in the nvSRAM is secure, having been stored in the nonvolatile elements when power was lost.
During backup operation, the CY14B104K consumes a maximum of 300 nanoamps at room temperature. User must choose capacitor or battery values according to the application.
Backup time values based on maximum current specifications are shown in the following table. Nominal backup times are approximately two times longer.
Table 3. RTC Backup Time
Capacitor Value
0.1F
0.47F
1.0F
Backup Time
72 hours
14 days
30 days
Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3V lithium is recommended and the CY14B104K sources current only from the battery when the primary power is removed. However the battery is not recharged at any time by the CY14B104K. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FFF8 controls the enable and disable of the oscillator. This bit is nonvolatile and is shipped to customers in the “enabled” (set to 0) state. To preserve the battery life when the system is in storage, OSCEN
Page 6 of 31
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PRELIMINARY
CY14B104K, CY14B104M must be set to ‘1’. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start.
While system power is off, If the voltage on the backup supply
(V
RTCcap
or V
RTCbat
) falls below their respective minimum level, the oscillator may fail.The CY14B104K has the ability to detect oscillator failure when system power is restored. This is recorded in the OSCF (Oscillator Failed bit) of the flags register at the address 0x7FFF0. When the device is powered on (V
CC
goes above V
SWITCH
) the OSCEN bit is checked for “enabled” status.
If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms, the OSCF bit is set to “1”. The system must check for this condition and then write ‘0’ to clear the flag. Note that in addition to setting the OSCF flag bit, the time registers are reset to the “Base Time” (see
Setting the Clock on page 6), which is
the value last written to the timekeeping registers. The control or calibration registers and the OSCEN bit are not affected by the
‘oscillator failed’ condition.
The value of OSCF must be reset to ‘0’ when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on.
To reset OSCF, set the write bit “W” (in the Flags register at
0x7FFF0) to a “1” to enable writes to the Flag register. Write a
“0” to the OSCF bit and then reset the write bit to “0” to disable writes.
Calibrating the Clock
The RTC is driven by a quartz controlled crystal with a nominal frequency of 32.768 kHz. Clock accuracy depends on the quality of the crystal and calibration. The crystals available in market typically have an error of +20 ppm to +35 ppm. However,
CY14B104K employs a calibration circuit that improves the accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5
seconds to -5 seconds per month.
The calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy. The number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in Calibration register at 0x7FFF8. The calibration bits occupy the five lower order bits in the Calibration register. These bits are set to represent any value between ‘0’ and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign.
Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once per minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12 are affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm of adjustment per calibration step in the Calibration register.
To determine the required calibration, the CAL bit in the Flags register (0x7FFF0) must be set to ‘1’. This causes the INT pin to toggle at a nominal frequency of 512 Hz. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.01024 Hz indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset this error.
Note Setting or changing the Calibration register does not affect the test output frequency.
To set or clear CAL, set the write bit “W” (in the flags register at
0x7FFF0) to “1” to enable writes to the Flag register. Write a value to CAL, and then reset the write bit to “0” to disable writes.
Alarm
The alarm function compares user programmed values of alarm time and date (stored in the registers 0x7FFF1-5) with the corresponding time of day and date values. When a match occurs, the alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set.
There are four alarm match fields - date, hours, minutes, and seconds. Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. Setting the match bit to ‘0’ indicates that the corresponding field is used in the match process. Depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. Selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date match.
There are two ways to detect an alarm event: by reading the AF flag or monitoring the INT pin. The AF flag in the flags register at
0x7FFF0 indicates that a date or time match has occurred. The
AF bit is set to “1” when a match occurs. Reading the flags register clears the alarm flag bit (and all others). A hardware interrupt pin may also be used to detect an alarm event.
To set, clear or enable an alarm, set the ‘W’ bit (in Flags Register
- 0x7FFF0) to ‘1’ to enable writes to Alarm Registers. After writing the alarm value, clear the ‘W’ bit back to “0” for the changes to take effect.
Note CY14B104K requires the alarm match bit for seconds
(0x7FFF2 - D7) to be set to ‘0’ for proper operation of Alarm Flag and Interrupt.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator must be running for the watchdog to function. It begins counting down from the value loaded in the Watchdog
Timer register.
The timer consists of a loadable register and a free running counter. On power up, the watchdog time out value in register
0x7FFF7 is loaded into the Counter Load register. Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is compared to the terminal value of ‘0’. If the counter reaches this value, it causes an internal flag and an optional interrupt output.
You can prevent the time out interrupt by setting WDS bit to ‘1’ prior to the counter reaching ‘0’. This causes the counter to reload with the watchdog time out value and to be restarted. As long as the user sets the WDS bit prior to the counter reaching the terminal value, the interrupt and WDT flag never occur.
Document #: 001-07103 Rev. *K Page 7 of 31
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PRELIMINARY
CY14B104K, CY14B104M
New time out values are written by setting the watchdog write bit to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified. A logical diagram of the
watchdog timer is shown in Figure 3
. Note that setting the watchdog time out value to ‘0’ disables the watchdog function.
The output of the watchdog timer is the flag bit WDF that is set if the watchdog is allowed to time out. If the Watchdog Interrupt
Enable (WIE) bit in the Interrupt register is set, a hardware interrupt on INT pin is also generated on watchdog timeout.
The flag and the hardware interrupt are both cleared when user reads the Flags registers.
Figure 3. Watchdog Timer Block Diagram
Oscillator
32,768 KHz
Clock
Divider
32 Hz
1 Hz
Counter
Zero
Compare
WDF
WDS
Load
Register
D Q
WDW
Q write to
Watchdog
Register
Watchdog
Register
.
Power Monitor
The CY14B104K provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low
V
CC
access. The power monitor is based on an internal band gap reference circuit that compares the V threshold.
CC
voltage to V
SWITCH
As described in the section “AutoStore Operation” on page 3,
when V
SWITCH
is reached as V
CC
decays from power loss, a data
STORE operation is initiated from SRAM to the nonvolatile elements, securing the last SRAM data state. Power is also switched from V
CC
to the backup supply (battery or capacitor) to operate the RTC oscillator.
t
When operating from the backup source, read and write operations to nvSRAM are inhibited and the clock functions are not available to the user. The clock continues to operate in the background. The updated clock data is available to the user
HRECALL
delay after V
CC
is restored to the device (see
“AutoStore/Power Up RECALL” on page 20)
Interrupts
The CY14B104K has Flags register, Interrupt register, and
Interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register (0x7FFF6). In addition, each has an associated flag bit in the Flags register (0x7FFF0) that the host processor uses to
Document #: 001-07103 Rev. *K determine the cause of the interrupt. The INT pin driver has two bits that specify its behavior when an interrupt occurs.
An Interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in Interrupts register is enabled (set to ‘1’). After an interrupt source is active, two programmable bits, H/L and P/L, determine the behavior of the output pin driver on INT pin. These two bits are located in the
Interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller. In the level mode, the pin goes to its active polarity until the Flags register is read by the user. This mode is used as an interrupt to a host microcontroller. The control bits are summarized in the following section.
Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode.
Note CY14B104K generates valid interrupts only after the
Powerup Recall sequence is completed. All events on INT pin must be ignored for t
HRECALL
duration after powerup.
Interrupt Register
Watchdog Interrupt Enable - WIE. When set to ‘1’, the watchdog timer drives the INT pin and an internal flag when a watchdog time out occurs. When WIE is set to ‘0’, the watchdog timer only affects the WDF flag in Flags register.
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match drives the INT pin and an internal flag. When AIE is set to ‘0’, the alarm match only affects the AF Flags register.
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power fail monitor drives the pin and an internal flag. When PFE is set to ‘0’, the power fail monitor only affects the PF flag in Flags register.
High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH and the driver mode is push pull. The INT pin drives high only when V
CC is greater than V
SWITCH
. When set to a ‘0’, the INT pin is active LOW and the drive mode is open drain. The INT pin must be pulled up to Vcc by a 10k resistor while using the interrupt in active LOW mode.
Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
Flags or Control register is read.
When an enabled interrupt source activates the INT pin, an external host reads the Flags registers to determine the cause.
Remember that all flags are cleared when the register is read. If the INT pin is programmed for Level mode, then the condition clears and the INT pin returns to its inactive state. If the pin is programmed for Pulse mode, then reading the flag also clears the flag and the pin. The pulse does not complete its specified duration if the Flags register is read. If the INT pin is used as a host reset, the Flags register is not read during a reset
Flags Register
The Flag register has three flag bits: WDF, AF, and PF, which can be used to generate an interrupt. They are set by the watchdog timeout, alarm match, or power fail monitor respectively.
The processor can either poll this register or enable interrupts when a flag is set. These flags are automatically reset once the register is read. The flags register is automatically loaded with the value
0x00 on power up (except for the OSCF bit. See “Stopping and
Starting the Oscillator” on page 6.)
Page 8 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Figure 4. RTC Recommended Component Configuration
Recommended Values
Y
1
= 32.768 KHz (6 pF)
C
1
= 21 pF
C
2
= 21 pF
Note: The recommended values for C1 and C2 include
board trace capacitance.
C1
C2
Y1
X1
X2
Watchdog
Timer
WDF
WIE
PF
PFE
Power
Monitor
VINT
Clock
Alarm
AF
AIE
Figure 5. Interrupt Block Diagram
P/L
Pin
Driver
H/L
V
CC
V
SS
INT
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
Enable
PF - Power Fail Flag
PFE - Power Fail Enable
AF - Alarm Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
Document #: 001-07103 Rev. *K Page 9 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Table 4. RTC Register Map
Register
CY14B104K CY14B104M
0x7FFFF
0x7FFFE
0x7FFFD
0x7FFFC
0x7FFFB
0x7FFFA
0x7FFF9
0x7FFF8
0x7FFF7
0x7FFF6
0x7FFF5
0x3FFFF
0x3FFFE
0x3FFFD
0x3FFFC
0x3FFFB
0x3FFFA
0x3FFF9
0x3FFF8
0x3FFF7
0x3FFF6
0x3FFF5
D7
0
0
0
0
0
0
OSCEN
(0)
0
0
0
D6
10s Years
D5
BCD Format Data
D4 D3
0 0 10s
Months
10s Day of Month
0 0 0
10s Hours
10s Minutes
0
10s Seconds
Cal Sign
(0)
WDS
(0)
WDW (0)
WIE (0) AIE (0) PFE (0) 0 H/L
(1)
D2
Years
Months
Day Of Month
Day of week
Hours
Minutes
Seconds
Calibration (00000)
WDT (000000)
P/L (0)
D1
0
M (1) 0 10s Alarm Date Alarm Day
D0
0
0x7FFF4
0x7FFF3
0x7FFF2
0x7FFF1
0x7FFF0
0x3FFF4
0x3FFF3
0x3FFF2
0x3FFF1
0x3FFF0
M (1)
M (1)
M (1)
WDF
0 10s Alarm Hours
10 Alarm Minutes
10 Alarm Seconds
10s Centuries
AF PF OSCF 0
Function/Range
Years: 00–99
Months: 01–12
Day of Month: 01–31
Day of week: 01–07
Hours: 00–23
Minutes: 00–59
Seconds: 00–59
Calibration Values
Watchdog
Interrupts
Alarm Hours
Alarm Minutes
Alarm, Seconds
Centuries
CAL (0) W (0) R (0)
Alarm, Day of Month:
01–31
Alarm, Hours: 00–23
Alarm, Minutes:
00–59
Alarm, Seconds:
00–59
Centuries: 00–99
Flags
Note
8. Upper Byte D
15
-D
8
(CY14B104MA) of RTC registers are reserved for future use
9. ( ) designates values shipped from the factory.
10. This is a binary value, not a BCD value.
Document #: 001-07103 Rev. *K Page 10 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Table 5. Register Map Detail
Register
CY14B104K CY14B104M
0x7FFFF 0x3FFFF
0x7FFFE
0x7FFFD
0x7FFFC
0x7FFFB
0x7FFFA
0x7FFF9
0x3FFFE
0x3FFFD
0x3FFFC
0x3FFFB
0x3FFFA
0x3FFF9
Description
D7 D6 D5
10s Years
Time Keeping - Years
D4 D3 D2
Years
D1 D0
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
Time Keeping - Months
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 10s Month Months
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.
D7
0
D6
0
D5
Time Keeping - Date
D4
10s Day of Month
D3 D2 D1
Day of Month
D0
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3.
The range for the register is 1–31. Leap years are automatically adjusted for.
D7
0
D6
0
D5
0
Time Keeping - Day
D4
0
D3
0
D2 D1
Day of Week
D0
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated with the date.
D7
0
D6
0
D5
Time Keeping - Hours
10s Hours
D4 D3 D2
Hours
D1 D0
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from
0 to 2. The range for the register is 0–23.
D7
0
D6 D5
10s Minutes
Time Keeping - Minutes
D4 D3 D2
Minutes
D1 D0
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5.
The range for the register is 0–59.
D7
0
D6 D5
Time Keeping - Seconds
10s Seconds
D4 D3 D2
Seconds
D1 D0
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0–59.
Document #: 001-07103 Rev. *K Page 11 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Table 5. Register Map Detail (continued)
Register
CY14B104K CY14B104M
0x7FFF8
OSCEN
0x3FFF8
Calibration
Calibration
0x7FFF7
0x7FFF6
Sign
WDS
WDW
WDT
0x3FFF7
0x3FFF6
Description
D7
OSCEN
D6
0
D5
Calibration
Sign
Calibration/Control
D4 D3 D2
Calibration
D1 D0
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs.
Disabling the oscillator saves battery or capacitor power during storage.
Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.
These five bits control the calibration of the clock.
WatchDog Timer
D7
WDS
D6
WDW
D5 D4 D3
WDT
D2 D1 D0
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to
0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0.
Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value
(D5–D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value.
Setting this bit to 0 allows bits D5–D0 to be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is
31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle.
Interrupt Status/Control
D7 D6 D5 D4 D3 D2 D1 D0
0x7FFF5
WIE
AIE
PFE
0
H/L
P/L
M
0x3FFF5
WIE AIE PFE 0 H/L P/L 0 0
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin and the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the alarm match only affects the AF flag.
Power Fail Enable. When set to 1, the power fail monitor drives the INT pin and the PF flag. When set to 0, the power fail monitor affects only the PF flag.
Reserved for future use
High/Low. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW.
Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L) until the flags register is read.
D7
M
D6
0
D5
Alarm - Day
D4
10s Alarm Date
D3 D2 D1
Alarm Date
D0
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the date value.
Document #: 001-07103 Rev. *K Page 12 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Table 5. Register Map Detail (continued)
Register
CY14B104K CY14B104M
0x7FFF4
0x7FFF3
0x7FFF2
0x7FFF1
0x7FFF0
M
M
M
WDF
AF
PF
OSCF
CAL
W
R
0x3FFF4
0x3FFF3
0x3FFF2
0x3FFF1
0x3FFF0
Description
D7
M
D5
10s Alarm Hours
D2 D1
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value.
D7
M
D6
D6
Alarm - Hours
D4 D3
D5
10s Alarm Minutes
Alarm - Minutes
D4 D3 D2 D1
Alarm Minutes
D0
D0
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the minutes value.
D7
M
D6 D5
10s Alarm Seconds
Alarm - Seconds
D4 D3 D2 D1
Alarm Seconds
D0
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to
1 causes the match circuit to ignore the seconds value.
D7 D6 D5
10s Centuries
Time Keeping - Centuries
D4 D3 D2 D1
Centuries
D0
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is
0-99 centuries.
Flags
D7
WDF
D6
AF
D5
PF
D4
OSCF
D3
0
D2
CAL
D1
W
D0
R
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach
0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power up
Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is cleared when the Flags register is read or on power up.
Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold
V
SWITCH
. It is cleared to 0 when the Flags register is read or on power up.
Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation. This indicates that RTC backup power failed and clock value is no longer valid.
This bit survives power cycle and is never cleared internally by the chip. The user must check for this condition and write '0' to clear this flag.
Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up.
Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write to RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting the W bit to 0 causes the contents of the RTC registers to be transferred to the time keeping counters if the time has been changed (a new base time is loaded). This bit defaults to 0 on power up.
Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates are not seen during the reading process. Set R bit to 0 to resume clock updates to the holding register. Setting this bit does not require W bit to be set to 1. This bit defaults to 0 on power up.
Document #: 001-07103 Rev. *K Page 13 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature ................................. –65 °C to +150°C
Maximum Accumulated Storage Time
At 150 °C Ambient Temperature................................... 1000h
At 85 °C Ambient Temperature..................... ........... 20 Years
Ambient Temperature with
Power Applied ............................................ –55 °C to +150°C
Supply Voltage on V
CC
Relative to GND ..........–0.5V to 4.1V
Voltage Applied to Outputs in High-Z State....................................... –0.5V to V
CC
+ 0.5V
Input Voltage...........................................–0.5V to Vcc + 0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to V
CC
+ 2.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................................... 1.0W
Surface Mount Pb Soldering
Temperature (3 Seconds) .......................................... +260 °C
DC Output Current (1 output at a time, 1s duration).....15 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current ................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0 °C to +70°C
–40 °C to +85°C
V
CC
2.7V to 3.6V
2.7V to 3.6V
DC Electrical Characteristics
Over the Operating Range (V
CC
= 2.7V to 3.6V)
Parameter
I
CC1
Description Test Conditions
Average V cc
Current t
RC t
RC
= 20 ns
= 25 ns t
RC
= 45 ns
Values obtained without output loads (I
OUT
= 0 mA)
Commercial
Industrial
I
CC2
I
CC3
I
CC4
I
SB
I
IX
I
OZ
V
IH
V
IL
V
OH
V
V
OL
CAP
Min Max
65
65
50
70
70
52
10
Unit mA mA mA mA
Average V
CC
Current during STORE
Average V
CC at t
RC
25°C typical
Current
= 200 ns, 3V,
Average V
Cycle
CAP
Current during AutoStore
All Inputs Don’t Care, V
All Inputs Don’t Care, V
CC
CC
= Max.
Average current for duration t
Average current for duration t
STORE
All I/P cycling at CMOS levels.
Values obtained without output loads (I
= Max.
STORE
OUT
= 0 mA).
V
CC
Standby Current CE > (V
CC
– 0.2V). All others V
IN
< 0.2V or > (V
CC current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
– 0.2V). Standby
Input Leakage Current
(except HSB)
V
CC
= Max, V
SS
< V
IN
< V
CC
Input Leakage Current
(for HSB)
Off State Output
Leakage Current
Input HIGH Voltage
Input LOW Voltage
V
V
CC
CC
= Max, V
= Max, V or WE < V
IL
SS
SS
< V
< V
IN
< V
OUT
CC
< V
CC
, CE or OE > V
Output HIGH Voltage I
OUT
= –2 mA
Output LOW Voltage I
OUT
= 4 mA
Storage Capacitor Between V
CAP
pin and V
SS
, 5V Rated
IH or BHE/BLE > V
IH
–1
–100
–1
2.0
V
SS
– 0.5
2.4
61
35
5
5
+1
+1
+1 mA mA mA mA
μA
μA
μA
V
CC
+ 0.5
V
0.8
V
0.4
180
V
V
μF
Notes
11. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V
12. The HSB pin has I
OUT
CC
= -2 uA for V
OH
of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard V
OH
= 3V. Not 100% tested.
and V
OL
are valid. This parameter is characterized but not tested.
13. V
CAP
(Storage capacitor) nominal value is 68uF.
Document #: 001-07103 Rev. *K Page 14 of 31
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Data Retention and Endurance
DATA
R
NV
C
Parameter Description
Data Retention
Nonvolatile STORE Operations
Capacitance
In the following table, the capacitance parameters are listed.
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
V
CC
= 25 °C, f = 1 MHz,
= 0 to 3.0V
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.
Min
20
200
Max
7
7
Unit
Years
K
Unit pF pF
44 TSOP II 54 TSOP II Unit
31.11
30.73
°C/W
5.56
6.08
°C/W
Figure 6. AC Test Loads
3.0V
OUTPUT
577 Ω
R1
3.0V
OUTPUT
577 Ω
R1
30 pF
R2
789 Ω
5 pF
R2
789 Ω
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%) ........................ <3 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
14. These parameters are only guaranteed by design and are not tested.
Document #: 001-07103 Rev. *K Page 15 of 31
[+] Feedback
Table 6. RTC Characteristics
Parameters
I
BAK
Description
RTC Backup Current
V
RTCbat
V
RTCcap tOCS
RTC Battery Pin Voltage
RTC Capacitor Pin Voltage
RTC Oscillator Time to Start
PRELIMINARY
CY14B104K, CY14B104M
Test Conditions
Room Temperature (25 o
C)
Hot Temperature (85 o
C)
Min
1.8
1.5
Typ Max Units
300 nA
3.0
3.0
1
450
3.3
3.6
2 nA
V
V sec
Notes
15. From either V
RTCcap
or V
RTCbat.
Document #: 001-07103 Rev. *K Page 16 of 31
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
AC Switching Characteristics
Parameters
Cypress
Parameters
Alt
Parameters
SRAM Read Cycle t t t
ACE
RC
AA
t t t t t t t t
DOE
OHA
LZCE
HZCE
LZOE
HZOE
PU
PD
t t t t t t t t t
ACS
RC t
AA
OE
OH
LZ
HZ
OLZ
OHZ
PA t t t
DBE
LZBE
HZBE
-
-
SRAM Write Cycle
t
PS t
WC t
PWE t
SCE t
SD t
HD t
AW t
SA t t t
HA
HZWE
LZWE
t
BW t
WC t
WP t
CW t
DW t
DH t
AW t
AS t
WR t
WZ
t
OW
Description
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Byte Enable to Data Valid
Byte Enable to Output Active
Byte Disable to Output Inactive
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
Byte Enable to End of Write
Switching Waveforms
20 ns 25 ns 45 ns
Min Max Min Max Min Max
20
3
3
0
0
0
20
15
15
8
0
15
0
0
3
15
20
20
10
8
8
20
10
8
8
25
3
3
0
0
0
25
20
20
10
0
20
0
0
3
20
Figure 7. SRAM Read Cycle 1: Address Controlled
25
25
12
10
10
25
12
10
10
45
3
3
0
0
0
45
30
30
15
0
30
0
0
3
30
45
45
20
15
15
45
20
15
15
Address t
RC
Address Valid t
AA
Data Output Previous Data Valid t
OHA
Output Data Valid
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
16. WE must be HIGH during SRAM read cycles.
17. Device is continuously selected with CE, OE and BHE / BLE LOW.
18. Measured ±200 mV from steady state output voltage.
19. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
20. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-07103 Rev. *K Page 17 of 31
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Switching Waveforms
Address
CE
OE
BHE, BLE
Data Output
High Impedance
I
CC
Figure 8. SRAM Read Cycle 2: CE Controlled
Standby t
PU
Address Valid t
RC t
ACE t
LZCE t
AA t
DOE t
LZOE t
DBE t
LZBE
Active t
HZCE t
HZOE t
HZBE
Output Data Valid t
PD
Address
CE
BHE, BLE
WE
Data Input
Data Output
Figure 9. SRAM Write Cycle 1: WE Controlled
t
WC
Address Valid t
SCE t
HA
Previous Data t
SA t
BW t
AW t
PWE t
HZWE t
SD t
HD
Input Data Valid t
LZWE
High Impedance
Notes
21. CE or WE must be >V
IH
during address transitions.
Document #: 001-07103 Rev. *K Page 18 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Switching Waveforms
Address
Figure 10. SRAM Write Cycle 2: CE Controlled
t
SA t
WC
Address Valid t
SCE t
HA
CE
BHE, BLE
WE
Data Input
Data Output t
BW t
PWE t
SD
Input Data Valid
High Impedance t
HD
Address
CE
BHE, BLE
WE
Data Input
Data Output
Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled
(Not applicable for RTC register writes) t
SA t
SCE t
WC
Address Valid t
BW t
HA t
AW t
PWE t
SD t
HD
Input Data Valid
High Impedance
Note
22. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.
Document #: 001-07103 Rev. *K Page 19 of 31
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PRELIMINARY
CY14B104K, CY14B104M
AutoStore/Power Up RECALL
20 ns
1.9
5
500
Min
25 ns
Parameters Description t t t
HRECALL
STORE
DELAY
V
SWITCH t
VCCRISE
V
HDIS
t
LZHSB t
HHHD
Power Up RECALL Duration
STORE Cycle Duration
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
VCC Rise Time
HSB Output Driver Disable Voltage
HSB To Output Active Time
HSB High Active Time
Switching Waveforms
Min
150
Max
20
8
20
2.65
150
Figure 12. AutoStore or Power Up RECALL
Max
20
8
25
2.65
1.9
5
500
Min
45 ns
Max
20
8
25
2.65
150
1.9
5
500
Unit ms ms ns
V
μs
V
μs ns
V
SWITCH
V
HDIS
HSB OUT
V
VCCRISE t
HHHD
Note 24 t
STORE t
HHHD t
LZHSB t
DELAY
Note 24 t
STORE
Note 27
Autostore
POWER-
UP
RECALL
Read & Write
Inhibited
(
RWI
) t
LZHSB t
HRECALL t
DELAY t
HRECALL
POWER-UP
RECALL
Read & Write BROWN
OUT
Autostore
POWER-UP
RECALL
Read & Write POWER
DOWN
Autostore
Notes
23. t
HRECALL starts from the time V
CC
rises above V
SWITCH.
24. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
25. On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
DELAY
.
26. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
27. HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.
Document #: 001-07103 Rev. *K Page 20 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Software Controlled STORE and RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.
Parameters t
RC t
SA t
CW t
HA t t
RECALL
SS
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Soft Sequence Processing Time
Min
20 ns
Max
20
0
15
0
200
100
Min
25 ns
Max
25
0
20
0
200
100
Switching Waveforms
Figure 13. CE and OE Controlled Software STORE and RECALL Cycle
Min
45 ns
Max
45
0
30
0
200
100
Address t
RC t
SA
Address #1 t
CW t
RC
Address #6 t
CW
CE t
SA t
HA t
HA t
HA t
HA
OE t
DELAY t
HHHD
HSB (STORE only) t
LZCE t
HZCE t
LZHSB
DQ (DATA)
High Impedance t
STORE
/t
RECALL
Unit ns ns ns ns
μs
μs
RWI
Address t
SA
Figure 14. Autostore Enable and Disable Cycle t
RC
Address #1 t
CW t
RC
Address #6 t
CW
CE t
SA t
HA t
HA t
HA t
HA
OE t
SS t
LZCE t
HZCE t
DELAY
DQ (DATA)
Notes
28. The software sequence is clocked with CE controlled or OE controlled reads.
29. The six consecutive addresses must be read in the order listed in Table 1 . WE must be HIGH during all six consecutive cycles.
30. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
31. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-07103 Rev. *K Page 21 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Hardware STORE Cycle
Parameters Description t
DHSB t
PHSB
HSB To Output Active Time when write latch not set
Hardware STORE Pulse Width
Switching Waveforms
Min
20 ns
Max
20
15
Figure 15. Hardware STORE Cycle
Min
25 ns
Max
25
15
Write latch set
t
PHSB
HSB (IN) t
DELAY
HSB (OUT)
DQ (Data Out)
RWI
Write latch not set
t
PHSB
HSB (IN) t
STORE t
HHHD t
LZHSB
Min
45 ns
Max
25
15
Unit ns ns
HSB pin is driven high to V
CC
100kOhm resistor, only by Internal
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
HSB (OUT)
RWI t
DELAY t
DHSB t
DHSB
Figure 16. Soft Sequence Processing
Address
CE
V
CC
Soft Sequence
Command
Address #1 t
SA
Address #6 t
CW t
SS
Soft Sequence
Command
Address #1 Address #6 t
CW t
SS
Notes
32. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
33. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-07103 Rev. *K Page 22 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
CE WE OE
L
L
H
L
H
L
X
H
H
X
X
L
Inputs and Outputs
High Z
Data Out (DQ
0
–DQ
7
);
High Z
Data in (DQ
0
–DQ
7
);
For x16 Configuration
CE WE OE
L
L
H
L
H
H
X
X
L
L
X
X
BHE
X
H
L
H
BLE
X
H
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
X
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
Mode
Deselect/Power down
Read
Output Disabled
Write
Inputs and Outputs
High-Z
High-Z
Data Out (DQ
0
–DQ
15
)
Data Out (DQ
DQ
8
–DQ
0
–DQ
7
);
15 in High-Z
Data Out (DQ
DQ
0
–DQ
8
–DQ
15
);
7 in High-Z
High-Z
High-Z
High-Z
Data In (DQ
0
–DQ
15
)
Data In (DQ
0
–DQ
7
DQ
8
–DQ
15
); in High-Z
Data In (DQ
8
–DQ
15
DQ
0
–DQ
7 in High-Z
);
Mode
Deselect/Power down
Output Disabled
Read
Read
Read
Output Disabled
Output Disabled
Output Disabled
Write
Write
Write
Power
Standby
Active
Active
Active
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Document #: 001-07103 Rev. *K Page 23 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Part Numbering Nomenclature
CY14 B 104 K ZS P 20 X C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Pb-Free
P - 54 Pin
Blank - 44 Pin
Package:
ZS - TSOP II
Speed:
20 - 20 ns
25 - 25 ns
45 - 45 ns
Data Bus:
K - x8 + RTC
M - x16 + RTC
Density:
104 - 4 Mb
Voltage:
B - 3.0V
NVSRAM
14 - AutoStore + Software STORE + Hardware STORE
Cypress
Document #: 001-07103 Rev. *K Page 24 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Ordering Information
Speed
(ns)
20
25
45
Ordering Code
CY14B104K-ZS20XCT
CY14B104K-ZS20XC
CY14B104K-ZS20XIT
CY14B104K-ZS20XI
CY14B104M-ZSP20XCT
CY14B104M-ZSP20XC
CY14B104M-ZSP20XIT
CY14B104M-ZSP20XI
CY14B104K-ZS25XCT
CY14B104K-ZS25XC
CY14B104K-ZS25XIT
CY14B104K-ZS25XI
CY14B104M-ZSP25XCT
CY14B104M-ZSP25XC
CY14B104M-ZSP25XIT
CY14B104M-ZSP25XI
CY14B104K-ZS45XCT
CY14B104K-ZS45XC
CY14B104K-ZS45XIT
CY14B104K-ZS45XI
CY14B104M-ZSP45XCT
CY14B104M-ZSP45XC
CY14B104M-ZSP45XIT
CY14B104M-ZSP45XI
Package
Diagram
51-85087 44-pin TSOPII
51-85087 44-pin TSOPII
Package Type
51-85087 44-pin TSOPII
51-85087 44-pin TSOPII
51-85160 54-pin TSOPII
51-85160 54-pin TSOPII
51-85160 54-pin TSOPII
51-85160 54-pin TSOPII
51-85087 44-pin TSOPII
51-85087 44-pin TSOPII
51-85087 44-pin TSOPII
51-85187 44-pin TSOPII
51-85160 54-pin TSOPII
51-85160 54-pin TSOPII
51-85160 54-pin TSOPII
51-85160 54-pin TSOPII
51-85087 44-pin TSOPII
51-85087 44-pin TSOPII
51-85087 44-pin TSOPII
51-85187 44-pin TSOPII
51-85160 54-pin TSOPII
51-85160 54-pin TSOPII
51-85160 54-pin TSOPII
51-85160 54-pin TSOPII
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-07103 Rev. *K Page 25 of 31
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Package Diagrams
PRELIMINARY
CY14B104K, CY14B104M
Figure 17. 44-Pin TSOP II (51-85087)
1
PIN 1 I.D.
DIMENSION IN MM (INCH)
MAX
MIN.
22
23
TOP VIEW
0.800 BSC
(0.0315)
0.400(0.016)
0.300 (0.012)
18.517 (0.729)
18.313 (0.721)
44
BASE PLANE
0.10 (.004)
SEATING
PLANE
K
O
R
X
S G
E
A
EJECTOR PIN
BOTTOM VIEW
0°-5°
10.262 (0.404)
10.058 (0.396)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
51-85087 *A
Document #: 001-07103 Rev. *K Page 26 of 31
[+] Feedback
PRELIMINARY
Package Diagrams
(continued)
Figure 18. 54-Pin TSOP II (51-85160)
CY14B104K, CY14B104M
51-85160 **
Document #: 001-07103 Rev. *K Page 27 of 31
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Document History Page
Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Orig. of
Change
Description of Change
**
*A
*B
*C
*D
*E
431039
489096
499597
517793
825240
914280
See ECN
See ECN
See ECN
See ECN
See ECN
See ECN
TUP
TUP
PCI
TUP
UHA
UHA
New Data Sheet
Removed 48 SSOP Package
Added 44 TSOPII and 54 TSOPII Packages
Updated Part Numbering Nomenclature and Ordering Information
Added Soft Sequence Processing Time Waveform
Added RTC Characteristics Table
Added RTC Recommended Component Configuration
Removed 35ns speed bin
Added 55ns speed bin. Updated AC table for the same
Changed “Unlimited” read/write to “infinite” read/write
Features section: Changed typical I
CC
at 200-ns cycle time to 8 mA
Changed STORE cycles from 500K to 200K cycles.
Shaded Commercial grade in operating range table.
Modified Icc/Isb specs.
Changed V
CAP
value in DC table
Added 44 TSOP II in Thermal Resistance table
Modified part nomenclature table. Changes reflected in the ordering information table.
Removed 55ns speed bin
Changed pinout for 44TSOPII and 54TSOPII packages
Changed I
Changed I
SB
to 1mA
CC4
to 3mA
Changed V
Changed V
CAP
IH
min to 35 μF
max to Vcc + 0.5V
Changed t
STORE
Changed t
PWE to 15ns
to 10ns
Changed t
Changed t
SCE
SD
Changed t
AW
to 15ns
to 5ns
to 10ns
Removed t
HLBL
Added Timing Parameters for BHE and BLE - t
DBE
, t
Removed min. specification for Vswitch
Changed t
GLAX
to 1ns
Added t
DELAY
Changed t
SS
LZBE
max. of 70us
specification from 70us min. to 70us max.
, t
HZBE
, t
BW
Changed the data sheet from Advance information to Preliminary
Changed t
DBE
to 10ns in 15ns part
Changed t
Changed t
BW
Changed t
HZBE in 15ns part to 15ns and in 25ns part to 20ns
GLAX in 15ns part to 7ns and in 25ns part to10ns
to t
GHAX
Changed the value of I
Changed the value of t
CC3
AW
to 25mA
in 15ns part to 15ns
Changed the figure-14 title from 54-Pb to 54 Pin
Included all the information for 45ns part in this data sheet
Document #: 001-07103 Rev. *K Page 28 of 31
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Orig. of
Change
Description of Change
*F 1890926 See ECN
*G
*H
2267286
2483627
See ECN
See ECN vsutmp8/AE-
SA
Added Footnote 1, 2 and 3.
Updated Logic Block diagram
Updated Pin definition Table
Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8) package.
Corrected typo in V
IL
min spec
Changed the value of I
Changed I
SB
CC3
from 25mA to 13mA
value from 1mA to 2mA
Updated ordering information table
Rearranging of Footnotes.
Changed Package diagrams title.
The pins X1 and X2 interchanged in 44TSOP II(x8) and 54TSOP II(x16) pinout diagram.
GVCH/PYRS Rearranging of “Features”
Added BHE and BLE Information in Pin Definitions Table
Updated Figure 2 (Autostore mode)
Updated footnote 6
RTC Register Map:Register 0x1FFF6:Changed D4 from ABE to 0
Register Map Detail:0x1FFF6:Changed D4 from ABE to 0 and removed ABE information
Changed I
CC2
& I
CC4
from 3mA to 6mA
Changed I
CC3
Changed I
SB value
from 13mA to 15mA
from 2mA to 3mA
Added input leakage current (I
Corrected typo in t
IX
) for HSB in DC Electrical Characteristics table
Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max
Corrected typo in t
DBE
value from 22ns to 20ns for 45ns part
HZBE
Corrected typo in t
AW
value from 22ns to 15ns for 45ns part
value from 15ns to 10ns for 15ns part
Changed Vrtccap max from 2.7V to 3.6V
Changed tRECALL from 100 to 200us
Added footnote 10, 29
Reframed footnote 18, 25
Added footnote 18 to figure 8 (SRAM WRITE Cycle #1)
Added footnote 18, 26 and 27 to figure 9 (SRAM WRITE Cycle #2)
GVCH/PYRS Removed 8 mA typical I
Changed I
CC3
CC
Referenced footnote 9 to I
at 200 ns cycle time in Feature section
CC3
in DC Characteristics table
from 15 mA to 35 mA
Changed Vcap minimum value from 54 uF to 61 uF
Changed t
AVAV
to t
RC
Changed V
RTCcap minimum value from 1.2V to 1.5V
Figure 12:Changed t
SA
to t
AS and t
SCE to t
CW
Document #: 001-07103 Rev. *K Page 29 of 31
[+] Feedback
PRELIMINARY
CY14B104K, CY14B104M
Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Orig. of
Change
Description of Change
*I 2519319
*J 2600941
06/20/08
11/04/08
GVCH/PYRS Added 20 ns access speed in “Features”
Added I
CC1
for tRC=20 ns for both industrial and Commercial temperature Grade
Updated Thermal resistance values for 44-TSOP II and 54-TSOP II packages
Added AC Switching Characteristics specs for 20 ns access speed
Added Software controlled STORE/RECALL cycle specs for 20 ns access speed
Updated ordering information and Part numbering nomenclature
GVCH/PYRS Removed 15 ns access speed from “Features”
Changed part number from CY14B104K/CY14B104M to
CY14B104KA/CY14B104MA
Updated Logic block diagram
Updated footnote 1
Added footnote 2
Pin definition: Updated WE, HSB and NC pin description
Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description
Page 4: Updated Hardware store operation and Hardware RECALL (Power up) description
Footnote 1 and 8 referenced for Mode selection Table
Updated footnote 6
Page 6: updated Data protection description
Page 6: Updated Starting and stopping the oscillator description
Page 7: Updated Calibrating the clock description
Page 7: Updated Alarm description
Page 8: Added Flags register
Added footnote 10 and 11
Updated Figure 4: Removed RF register and Changed C
2
value from 56pF to
12pF
Updated Register Map Table 3
Updated Register map detail Table 4
Maximum Ratings: Added Max. Accumulated storage time
Changed Output short circuit current parameter name to DC output current
Changed I
CC2
from 6mA to 10mA
Changed I
CC4
Changed I
SB
Updated I
from 6mA to 5mA
from 3mA to 5mA
CC1,
I
CC3,
I
SB and I
Changed V
CAP
Updated footnote 12 and 13
Added footnote 14
OZ
Test conditions
voltage max value from 82uF to 180uF
Added Data retention and Endurance Table
Updated Input Rise and Fall time in AC test Conditions
Changed tOCS value for minimum temperature from 10 to 2 sec updated tOCS value for room temperature from 5 to 1sec
Referenced footnote 20 to t
OHA
parameter
Updated All switching waveforms
Updated footnote 20
Added Figure 11 (SRAM WRITE CYCLE:BHE and BLE controlled)
Updated t
DELAY
value
HHHD
and t
LZHSB
parameters Added V
HDIS
, t
Updated footnote 27
Added footnote 29
Software controlled STORE/RECALL Table: Changed t
AS
to t
Changed t
GHAX
to t
HA
Changed t
HA
Added t
DHSB
Changed t value from 1ns to 1ns
parameter
HLHX
Updated t
SS
to t
PHSB
from 70us to 100us
Added truth table for SRAM operations
SA
Updated ordering information and part numbering nomenclature
Document #: 001-07103 Rev. *K Page 30 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Orig. of
Change
Description of Change
*K 2653928 02/04/09 GVCH/PYRS Changed Part number from CY14B104KA/CY14B104MA to
CY14B104K/CY14B104M
Updated Real Time Clock operation description
Added factory default values to register map table 3
Added footnote 9
Updated Flag register description in Table 4
Updated C1, C2 values to 21uF, 21uF respectively
Changed I
BAK
value from 350 nA to 450 nA at hot temperature
Changed V
RTCcap
Referenced Note 15 to parameters t and t
HZBE
Added footnote 22
Updated Figure 13 typical value from 2.4V to 3.0V
LZCE
, t
HZCE
, t
LZOE, t
HZOE, t
LZBE, t
LZWE, t
HZWE-
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-07103 Rev. *K Revised January 29, 2009 Page 31 of 31
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
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