Hardware STORE Cycle. Cypress CY14B104K, CY14B104M

PRELIMINARY

CY14B104K, CY14B104M

Hardware STORE Cycle

Parameters Description t

DHSB t

PHSB

HSB To Output Active Time when write latch not set

Hardware STORE Pulse Width

Switching Waveforms

Min

20 ns

Max

20

15

Figure 15. Hardware STORE Cycle

[24]

Min

25 ns

Max

25

15

Write latch set

t

PHSB

HSB (IN) t

DELAY

HSB (OUT)

DQ (Data Out)

RWI

Write latch not set

t

PHSB

HSB (IN) t

STORE t

HHHD t

LZHSB

Min

45 ns

Max

25

15

Unit ns ns

HSB pin is driven high to V

CC

100kOhm resistor, only by Internal

HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven low.

HSB (OUT)

RWI t

DELAY t

DHSB t

DHSB

Figure 16. Soft Sequence Processing

[32, 33]

Address

CE

V

CC

Soft Sequence

Command

Address #1 t

SA

Address #6 t

CW t

SS

Soft Sequence

Command

Address #1 Address #6 t

CW t

SS

Notes

32. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

33. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Document #: 001-07103 Rev. *K Page 22 of 31

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