Cypress CY7C1302DV25 User's Manual

CY7C1302DV25

Configurations

CY7C1302DV25 – 512K x 18

9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

Functional Description Features

• Separate independent Read and Write data ports

— Supports concurrent transactions

• 167-MHz clock for high bandwidth

— 2.5 ns Clock-to-Valid access time

• 2-word burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 333 MHz) @ 167 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JTAG Interface

The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Accesses to the CY7C1302DV25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock

(K). In order to maximize data throughput, both Read and

Write ports are equipped with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C, or K and K in a single clock domain) thereby maximizing performance while simplifying system design. Each address location is associated with two

18-bit words that burst sequentially into or out of the device.

Depth expansion is accomplished with a Port Select input for each port. Each Port Select allows each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Logic Block Diagram (

CY7C1302DV25

)

D

[17:0]

18

Write

Data Reg

Write

Data Reg

A

(17:0)

18

Address

Register

Address

Register 18

A

(17:0)

256Kx18

Memory

Array

256Kx18

Memory

Array

K

K

CLK

Gen.

Read Data Reg.

36

18

Control

Logic

RPS

C

C

Vref

WPS

BWS

0

BWS

1

Control

Logic 18

Reg.

Reg.

Reg.

18

18

18

Q

[17:0]

Cypress Semiconductor Corporation

Document #: 38-05625 Rev. *A

• 198 Champion Court • San Jose

,

CA 95134-1709 • 408-943-2600

Revised March 23, 2006

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CY7C1302DV25

Selection Guide

Maximum Operating Frequency

Maximum Operating Current

Pin Configuration

G

H

J

K

E

F

A

B

C

D

L

M

N

P

R

NC

NC

NC

NC

NC

NC

NC

NC

TDO

1

NC

NC

NC

NC

NC

NC

CY7C1302DV25-167

167

500

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1302DV25 (512K x 18)

2 3 4

Gnd/144M NC/36M WPS

Q9 D9 A

NC

D11

NC

Q12

D10

Q10

Q11

D12

VSS

VSS

VDDQ

VDDQ

D13

VREF

NC

NC

Q15

NC

D17

NC

TCK

Q13 VDDQ

VDDQ VDDQ

D14

Q14

D15

D16

Q16

Q17

A

VDDQ

VDDQ

VDDQ

VSS

VSS

A

A

VDD

VDD

VDD

VDD

VSS

VSS

A

A

A

5

BWS

1

NC

A

VSS

VSS

VDD

VSS

VSS

VSS

VSS

VSS

VSS

A

C

C

6

K

K

A

VSS

VSS

VSS

VDD

VDD

VDD

VDD

VSS

VSS

A

A

A

7

NC

BWS

0

A

VSS

VSS

VDD

Unit

MHz mA

8 9 10

RPS NC/18M Gnd/72M

A NC NC

VSS

VSS

VDDQ

VDDQ

NC

NC

NC

NC

Q7

NC

D6

NC

VDDQ NC

VDDQ VDDQ

VDDQ

VDDQ

NC

NC

VDDQ

VSS

VSS

A

A

NC

NC

NC

NC

A

NC

VREF

Q4

D3

NC

Q1

NC

D0

TMS

Pin Definitions

Name

D

[17:0]

WPS

BWS

0

,

BWS

1

A

Q

[17:0]

RPS

I/O

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Outputs-

Synchronous

Input-

Synchronous

Description

Data input signals, sampled on the rising edge of K and K clocks during valid Write opera-

tions.

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D

[17:0]

to be ignored.

Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during

Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered.

BWS

0

controls D

[8:0]

and BWS

1

controls D

[17:9].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write

Select will cause the corresponding byte of data to be ignored and not written into the device.

Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks for active Read and Write operations. These address inputs are multiplexed for both Read and

Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x 18).

These inputs are ignored when the appropriate port is deselected.

Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q

[17:0] three-stated.

are automatically

Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers.

Q2

D2

D1

Q0

TDI

D5

ZQ

D4

Q3

11

NC

Q8

D8

D7

Q6

Q5

Document #: 38-05625 Rev. *A Page 2 of 18

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CY7C1302DV25

Pin Definitions

(continued)

Name

C

C

K

K

ZQ

TDO

TCK

TDI

TMS

NC/18M

NC/36M

GND/72M

GND/144M

NC

V

REF

V

DD

V

SS

V

DDQ

I/O Description

Input-

Clock

Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details.

Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board cack to the controller. See application example for further details.

Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q

[17:0] when in single clock mode. All accesses are initiated on the rising edge of K.

Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q

[17:0]

when in single clock mode.

Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q

[17:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V

DDQ

, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

Output

Input

Input

Input

N/A

TDO for JTAG.

TCK pin for JTAG.

TDI pin for JTAG.

TMS pin for JTAG.

Address expansion for 18M. This is not connected to the die and so can be tied to any voltage level.

N/A

Input

Input

N/A

Input-

Reference

Address expansion for 36M. This is not connected to the die and so can be tied to any voltage level.

Address expansion for 72M. This must be tied LOW.

Address expansion for 144M. This must be tied LOW.

Not connected to the die. Can be tied to any voltage level.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points.

Power Supply Power supply inputs to the core of the device.

Ground Ground for the device.

Power Supply Power supply inputs for the outputs of the device.

Introduction

Functional Overview

The CY7C1302DV25 is a synchronous pipelined Burst SRAM equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-I completely eliminates the need to

“turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. 38-05625

Accesses for both ports are initiated on the rising edge of the

Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C, or K and K when in single clock mode).

All synchronous data inputs (D

[17:0]

) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q

[17:0]

) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode).

All synchronous control (RPS, WPS, BWS

[1:0]

) inputs pass through input registers controlled by the rising edge of input clocks (K and K).

Read Operations

The CY7C1302DV25 is organized internally as 2 arrays of

256K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address is latched on the rising edge of the K clock. Following the next K clock rise the corresponding lower order 18-bit word of data is driven onto the Q

[17:0]

using C as the output timing reference. On the subsequent rising edge of

C the higher order data word is driven onto the Q

[17:0]

. The requested data will be valid 2.5 ns from the rising edge of the output clock (C and C, or K and K when in single clock mode,

167-MHz device).


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Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the same K clock rise the data presented to D

[17:0]

is latched into the lower 18-bit

Write Data register provided BWS

[1:0]

are both asserted active. On the subsequent rising edge of the negative input clock (K), the address is latched and the information presented to D

[17:0]

BWS

[1:0]

is stored into the Write Data register provided

are both asserted active. The 36 bits of data are then written into the memory array at the specified location.

When deselected, the Write port will ignore all inputs after the pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1302DV25.

A Write operation is initiated as described in the Write

Operation section above. The bytes that are written are determined by BWS

0

and BWS

1

which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write

Select input during the data portion of a write will allow the data being presented to be latched and written into the device.

Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify

Read/Modify/Write operations to a Byte Write operation.

38-05625

Single Clock Mode

The CY7C1302DV25 can be used with a single clock mode.

In this mode the device will recognize only the pair of input clocks (K and K) that control both the input and output

Application Example

[1]

CY7C1302DV25 registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-up.This function is a strap option and not alterable during device operation.

Concurrent Transactions

The Read and Write ports on the CY7C1302DV25 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise.

Depth Expansion

The CY7C1302DV25 has a Port Select input for each port.

This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K).

Each port select input can deselect the specified port.

Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175

Ω and 350Ω

, with V

DDQ

=1.5V. The output impedance is adjusted every 1024 cycles to account for drifts in supply voltage and temperature.

Note:

1. The above application shows 4 QDR-I being used.


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CY7C1302DV25

Truth Table

[2, 3, 4, 5, 6, 7]

Operation

Write Cycle:

Load address on the rising edge of K clock; input write data on K and K rising edges.

Read Cycle:

Load address on the rising edge of K clock; wait one cycle; read data on 2 consecutive C and C rising edges.

NOP: No Operation

K

L-H

L-H

RPS

X

L

WPS

L

X

DQ

D(A+0) at K(t)

↑

Q(A+0) at C(t+1)

↑

DQ

D(A+1) at K(t)

↑

Q(A+1) at C(t+1)

↑

L-H H H D = X

Q = High-Z

Previous State

D = X

Q = High-Z

Previous State Standby: Clock Stopped

Write Cycle Descriptions

[2,8]

Stopped X X

BWS

L

L

L

L

H

H

0

BWS

1

L

L

H

H

L

L

K

L-H

–

L-H

–

L-H

–

K Comments

– During the Data portion of a Write sequence, both bytes (D

[17:0]

) are written into the device.

L-H During the Data portion of a Write sequence, both bytes (D

[17:0]

) are written into the device.

– During the Data portion of a Write sequence, only the lower byte (D

[8:0] device. D

[17:9]

remains unaltered.

) is written into the

L-H During the Data portion of a Write sequence, only the lower byte (D

[8:0] device. D

[17:9]

remains unaltered.

) is written into the

– During the Data portion of a Write sequence, only the byte (D

[17:9]

D

[8:0]

remains unaltered.

) is written into the device.

L-H During the Data portion of a Write sequence, only the byte (D

[17:9]

D

[8:0]

remains unaltered.

) is written into the device.

– No data is written into the device during this portion of a Write operation.

L-H No data is written into the device during this portion of a Write operation.

H

H

H

H

L-H

–

Notes:

2. X = Don't Care, H = Logic HIGH, L = Logic LOW,

↑ represents rising edge.

3. Device will power-up deselected and the outputs in a three-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.

5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 38-05625

8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS

0 as the set-up and hold requirements are achieved. 38-05625

, BWS

1

can be altered on different portions of a Write cycle, as long


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IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using

JEDEC standard 2.5V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW

(V

SS

) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to V

DD

through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V

DD

) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the

CY7C1302DV25

TDI and TDO pins as shown in TAP Controller Block Diagram.

Upon power-up, the instruction register is loaded with the

IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(V

SS

) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and

Output ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register

Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction


[+] Feedback

is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (t

CS

and t

CH

). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in.

CY7C1302DV25

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.

EXTEST Output Bus Three-state

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a three-state mode.

The boundary scan register has a special bit located at bit #47.

When this scan cell, called the “extest output bus three-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the

“Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.


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CY7C1302DV25

TAP Controller State Diagram

[9]

1

0

TEST-LOGIC

RESET

0

TEST-LOGIC/

IDLE

1

1

SELECT

DR-SCAN

0

CAPTURE-DR

0

SHIFT-DR

1

0

1

EXIT1-DR

0

1

0 PAUSE-DR

1

0

EXIT2-DR

1

UPDATE-DR

1

0

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

1

SELECT

IR-SCAN

0

1

CAPTURE-DR

0

SHIFT-IR

1

EXIT1-IR

0

PAUSE-IR

1

0

EXIT2-IR

1

UPDATE-IR

1

0

0

1

0


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CY7C1302DV25

TAP Controller Block Diagram

TDI

Selection

Circuitry

0

Bypass Register

2 1 0

Instruction Register

31 30 29 .

.

2 1

Identification Register

0

106 .

.

.

.

2 1

Boundary Scan Register

0

Selection

Circuitry

TDO

TCK

TMS

TAP Controller

TAP Electrical Characteristics

Over the Operating Range

[10, 13, 15]

Parameter

V

OH1

V

OH2

V

OL1

V

OL2

V

IH

V

IL

I

X

Description

Output HIGH Voltage

Output HIGH Voltage

Output LOW Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input and Output Load Current

Test Conditions

I

OH

=

−2.0 mA

I

OH

=

−100 µA

I

OL

= 2.0 mA

I

OL

= 100

µA

GND

≤ V

I

≤ V

DDQ

TAP AC Switching Characteristics


[11, 12]

Min.

1.7

2.1

1.7

–0.3

–5

Max.

0.7

0.2

V

DD

+ 0.3

0.7

5

Parameter t

TCYC t

TF t

TH t

TL

Set-up Times

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH

TCK Clock LOW

Description Min.

50

20

20

Max.

20 t

TMSS t

TDIS t

CS

Hold Times

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

10

10

10 t

TMSH t

TDIH t

CH

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

Capture Hold after Clock Rise

10

10

10

Notes:

10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11. T

CS

and T

CH

refer to the set-up and hold time requirements of latching data from the boundary scan register.

12. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.

Unit ns

MHz ns ns ns ns ns ns ns ns

V

V

V

µA

Unit

V

V

V


[+] Feedback

CY7C1302DV25

TAP AC Switching Characteristics

Over the Operating Range (continued)

[11, 12]

Description Parameter

Output Times t

TDOV t

TDOX

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TAP Timing and Test Conditions

[12]

1.25V

50

Ω

TDO

Z

0

= 50

Ω

C

L

= 20 pF

0V

Min.

0

2.5V

ALL INPUT PULSES

1.25V

Max.

20

Unit ns ns

(a)

GND t

TH t

TL

Test Clock

TCK

t

TCYC t

TMSS t

TMSH

Test Mode Select

TMS

t

TDIS t

TDIH

Test Data-In

TDI

Test Data-Out

TDO

t

TDOX t

TDOV

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Cypress Device ID (28:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

Value

CY7C1302DV25

000

01011010010010110

00000110100

1

Description

Version number.

Defines the type of SRAM.

Allows unique identification of SRAM vendor.

Indicate the presence of an ID register.


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CY7C1302DV25

Scan Register Sizes

Register Name

Instruction

Bypass

ID

Boundary Scan

Instruction Codes

Instruction

EXTEST

IDCODE

Code

000

001

SAMPLE Z

RESERVED

SAMPLE/PRELOAD

RESERVED

RESERVED

BYPASS

010

011

100

101

110

111

Bit Size

3

1

32

107

Description

Captures the Input/Output ring contents.

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

Captures the Input/Output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.

Do Not Use: This instruction is reserved for future use.

Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation.



Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.


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Boundary Scan Order

19

20

21

22

15

16

17

18

23

24

25

26

11

12

13

14

7

8

9

10

5

6

3

4

Bit #

0

1

2

9M

9N

11L

11M

9L

10L

11K

10K

9J

9K

10J

11J

8P

9R

11P

10P

10N

9P

10M

11N

Bump ID

6R

6P

6N

7P

7N

7R

8R

11B

11C

9B

10B

11A

Internal

9A

8B

7C

6C

8A

7A

11E

10E

10D

9E

10C

11D

9C

9D

Bump ID

11H

10G

9G

11F

11G

9F

10F

46

47

48

49

42

43

44

45

50

51

52

53

38

39

40

41

34

35

36

37

30

31

32

33

Bit #

27

28

29

3E

2D

2E

1E

3D

3C

1D

2C

2F

3F

1G

1F

2B

3B

1C

1B

4B

3A

1H

1A

Bump ID

7B

6B

6A

5B

5A

4A

5C

73

74

75

76

69

70

71

72

77

78

79

80

65

66

67

68

61

62

63

64

57

58

59

60

Bit #

54

55

56

CY7C1302DV25

1P

3R

4R

4P

2M

3P

2N

2P

5P

5N

5R

1L

3N

3M

1N

1K

2L

3L

1M

Bump ID

3G

2G

1J

2J

3K

3J

2K

100

101

102

103

96

97

98

99

104

105

106

92

93

94

95

88

89

90

91

84

85

86

87

Bit #

81

82

83


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CY7C1302DV25

Maximum Ratings

(Above which the useful life may be impaired.)

Storage Temperature ................................. –65°C to + 150°C

Ambient Temperature with

Power Applied............................................ –55°C to + 125°C

Supply Voltage on V

DD

Relative to GND....... –0.5V to + 3.6V

Supply Voltage on V

DDQ

Relative to GND ..... –0.5V to + V

DD

DC Applied to Outputs in High-Z......... –0.5V to V

DDQ

+ 0.5V

DC Input Voltage

[13

................................–0.5V to V

DD

+ 0.5V

Current into Outputs (LOW) .........................................20 mA

Electrical Characteristics


[15]

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

Com’l

Ind’l

Ambient

Temperature (T

A

)

0°C to +70°C

–40°C to +85°C

V

DD

[14]

V

DDQ

[14]

2.5 ± 0.1V

1.4V to 1.9V

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min.

V

DD

V

DDQ

V

V

OH

OL

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Output LOW Voltage

Note 16

Note 17

2.4

1.4

V

DDQ

/2 – 0.12

V

DDQ

/2 – 0.12

V

OH(LOW)

V

OL(LOW)

V

IH

V

IL

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

[13]

[13, 18]

I

I

OH

OL

= –0.1 mA, Nominal Impedance V

DDQ

= 0.1 mA, Nominal Impedance

I

I

I

I

X

OZ

V

REF

DD

SB1

Input Load Current

Output Leakage Current

Input Reference Voltage

V

DD

Operating Supply

Automatic

Power-Down

Current

[19]

GND

≤ V

I

≤ V

DDQ

GND

≤ V

I

≤ V

DDQ,

Output Disabled

Typical value = 0.75V

V

DD

= Max., I

OUT

= 0 mA, f = f

MAX

= 1/t

CYC

Max. V

V

IN

=1/t

DD

≥ V

IH

CYC,

, Both Ports Deselected,

or V

IN

≤ V

IL

Inputs Static

, f =f

MAX

AC Input Requirements Over the Operating Range

V

V

SS

REF

+ 0.1

–0.3

–5

–5

– 0.2

0.68

Typ.

2.5

1.5

0.75

Parameter Description Test Conditions Min.

Typ.

V

IH

V

IL

Input HIGH Voltage

Input LOW Voltage

V

REF

+ 0.2

–

Notes:

13. Overshoot: V

IH

(AC) < V

DDQ

+0.85V (Pulse width less than t

14. Power-up: Assumes a linear ramp from 0V to V

DD

15. All voltage referenced to Ground.

16. Output are impedance controlled. I

OH

17. Output are impedance controlled. I

OL

= –(V

= (V

DDQ

DDQ

CYC

/2), Undershoot: V

18. This spec is for all inputs except C and C Clock. For C and C Clock, V

IL

IL(

AC) > –1.5V (Pulse width less than t

(min.) within 200 ms. During this time V

IH

< V

/2)/(RQ/5) for values of 175

Ω <= RQ <= 350Ω.

/2)/(RQ/5) for values of 175

Ω <= RQ <= 350Ω.

(Max.) = V

REF

– 0.2V.

DD and V

DDQ

< V

19. V

REF

(Min.) = 0.68V or 0.46V

DDQ

, whichever is larger, V

REF

(Max.) = 0.95V or 0.54V

DDQ

, whichever is smaller.

DD

.

CYC

/2).

Max.

2.6

Unit

V

1.9

V

V

DDQ

/2 + 0.12

V

V

DDQ

/2 + 0.12

V

V

DDQ

0.2

V

V

V V

DDQ

+ 0.3

V

REF

– 0.1

5

5

0.95

V

µA

µA

V

500 mA

V

240

Max.

REF

–

– 0.2

mA

Unit

V

V


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CY7C1302DV25

Thermal Resistance

[20]

Parameter

Θ

JA

Θ

JC

Description Test Conditions

Thermal Resistance (Junction to Ambient) Test conditions follow standard test

Thermal Resistance (Junction to Case) methods and procedures for measuring thermal impedance, per EIA/JESD51.

165 FBGA Package Unit

16.7

2.5

°C/W

°C/W

Capacitance

[20]

Parameter

C

IN

C

CLK

C

O

Description

Clock Input Capacitance

Output Capacitance

AC Test Loads and Waveforms

Test Conditions

T

A

= 25°C, f = 1 MHz,

V

DD

= 2.5V.

V

DDQ

= 1.5V

Max.

5

6

7

Unit pF pF pF

V

REF

= 0.75V

0.75V

V

REF

OUTPUT

V

REF

0.75V

R = 50

Ω

Device

Under

Test

ZQ

Z

0

= 50

Ω

RQ =

250

Ω

R

L

= 50

Ω

V

REF

= 0.75V

OUTPUT

Device

Under

Test

ZQ

RQ =

250

Ω

5 pF 0.25V

ALL INPUT PULSES

[21]

1.25V

0.75V

Slew Rate = 2 V/ns

(a)

(b)

Switching Characteristics


[21] t t

Cypress

Parameter t

Power

[22]

Cycle Time t

CYC t

KH

KL

KHKH t

Consortium

Parameter t

KHKH t

KHKL t

KLKH

KHKH

V

CC

Description

(typical) to the First Access Read or Write

K Clock and C Clock Cycle Time

Input Clock (K/K and C/C) HIGH

Input Clock (K/K and C/C) LOW

K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge to rising edge)

K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)

167 MHz

Min.

10

6.0

2.4

2.4

2.7

Max.

3.3

Unit

µs ns ns ns ns t

KHCH

Set-up Times t

KHCH t

SA t

SC t

SD

Hold Times t

SA t

SC t

SD

Address Set-up to Clock (K and K) Rise

Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS

0

, BWS

1

)

D

[17:0]

Set-up to Clock (K and K) Rise

0.0

0.7

0.7

0.7

2.0

ns ns ns ns t

HA t

HA

Address Hold after Clock (K and K) Rise 0.7

ns t

HC t

HC

Control Signals Hold after Clock (K and K) Rise

(RPS, WPS, BWS

0

, BWS

1

)

0.7

ns t

HD t

HD

D

[17:0]

Hold after Clock (K and K) Rise 0.7

ns

Notes:

20. Tested initially and after any design or process change that may affect these parameters.

21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250W, V

DDQ

= 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified I

OL or write operation can be initiated.

/I

OH

and load capacitance shown in (a) of AC test loads.

22. This part has a voltage regulator that steps down the voltage internally; t

Power

is the time power needs to be supplied above V

DD

minimum initially before a read


[+] Feedback

CY7C1302DV25

Switching Characteristics

Over the Operating Range (continued)

[21]

Cypress

Parameter

Output Times

Consortium

Parameter Description

167 MHz

Min.

Max.

t

CO t

CHQV

C/C Clock Rise (or K/K in single clock mode) to Data Valid 2.5

t

DOH t

CHZ t

CLZ t t t

CHQX

CHZ

CLZ

Data Output Hold after Output C/C Clock Rise (Active to Active)

Clock (C and C) Rise to High-Z (Active to High-Z)

Clock (C and C) Rise to Low-Z

[23, 24]

[23, 24]

1.2

1.2

2.5

Notes:

23. t

CHZ

, t

CLZ

, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

24. At any given voltage and temperature t

CHZ

is less than t

CLZ and, t

CHZ

less than t

CO

.

Unit ns ns ns ns


[+] Feedback

CY7C1302DV25

Switching Waveforms

[25, 26, 27]

READ

1

WRITE

2

READ

3

K tKH tKL tCYC

WRITE

4

K

READ

5 tKHKH

WRITE

6

NOP

7

WRITE

8

NOP

9 10

RPS tSC tHC

WPS

A

A0 A1

D D10 t

SA t

HA

D11

Q tKHCH

A2 A3 A4 A5 A6 tKHCH t

SA t

HA

D30 t

SD

D31 t

HD

D50

Q00 Q01

D51 t

SD

Q20

D60 t

Q21

HD

D61

Q40 tCLZ tCO tCO tDOH tDOH

C tKH tKL tKHKH tCYC

C

Q41 tCHZ

DON’T CARE UNDEFINED

Notes:

25. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.

26. Outputs are disabled (High-Z) one clock cycle after a NOP.

27. In this example, if address A2=A1 then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.


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CY7C1302DV25

Ordering Information

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com

for actual products offered”.

Speed

(MHz) Ordering Code

Package

Diagram Package Type

167 CY7C1302DV25-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Operating

Range

Commercial

CY7C1302DV25-167BZXC

CY7C1302DV25-167BZI

CY7C1302DV25-167BZXI

165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free

165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead free

Industrial

Package Diagram

A

A

B

TOP VIEW

TOP VIEW

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)

BOTTOM VIEW

Ø0.05 M C

N

P

R

K

L

M

H

J

A

B

C

D

E

F

G

PIN 1 CORNER

PIN 1 CORNER

1 2 3 4 5

1 2 3

A

4

6

5

7

6

8

7

9 10

8 9

11

10 11

B

C

D

E

F

G

H

J

K

L

M

N

P

R

PIN 1 CORNER

11 10

11

9

10

8

9

7

8

6

7

5

Ø0.25 M C A B

+0.14

Ø0.50 (165X)

4 3

-

0.06

1

6 5 4 3 2

N

P

R

K

L

H

J

M

F

G

D

E

1 A

B

C

A

B

13.00±0.10

13.00±0.10

A

B

B

0.15(4X)

0.15(4X)

NOTES :

5.00

5.00

10.00

10.00

13.00±0.10

13.00±0.10

1.00

1.00

G

J

H

E

F

A

B

C

D

N

P

R

K

L

M

C

SEATING PLANE

SEATING PLANE

C

PACKAGE CODE : BB0AC

51-85180-*A

51-85180-*A

Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and

Samsung. All product and company names mentioned in this document are trademarks of their respective holders.


© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1302DV25

Document History Page

Document Title:CY7C1302DV25 9-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture

Document Number: 38-05625

REV.

**

ECN NO.

253010

Issue Date

See ECN

Orig. of

Change

SYT New Data Sheet

Description of Change

*A 436864 See ECN NXR Converted from Preliminary to Final

Removed 133 MHz & 100 MHz from product offering

Included the Industrial Operating Range.

Changed C/C Description in the Features Section & Pin Description Table

Changed t

TCYC changed t table

TH

from 100 ns to 50 ns, changed t

TF

from 10 MHz to 20 MHz and and t

TL from 40 ns to 20 ns in TAP AC Switching Characteristics

Modified the ZQ pin definition as follows:

Alternately, this pin can be connected directly to V

DDQ minimum impedance mode

, which enables the

Included Maximum Ratings for Supply Voltage on V

DDQ

Relative to GND

Changed the Maximum Ratings for DC Input Voltage from V

DDQ

Modified the Description of I

X

Current on page # 13

from Input Load current to Input Leakage

Modified test condition in note# 14 from V

DDQ

< V

DD to

to V

V

DDQ

≤ V

DD

DD

Updated the Ordering Information table and replaced the Package Name

Column with Package Diagram


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