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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
72-Mbit QDR
®
II SRAM 2-Word
Burst Architecture
Features
■
Separate Independent Read and Write Data Ports
❐
Supports concurrent transactions
■ 350 MHz Clock for High Bandwidth
■ 2-word Burst on all Accesses
■ Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 700 MHz) at 350 MHz
■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only
■
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
■
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■
Single Multiplexed Address Input bus latches Address Inputs for both Read and Write Ports
■
Separate Port Selects for Depth Expansion
■
Synchronous internally Self-timed Writes
■
QDR
®
II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH
■
Operates similar to QDR I Device with 1 Cycle Read Latency when DOFF is asserted LOW
■
Available in x8, x9, x18, and x36 Configurations
■
Full Data Coherency, providing Most Current Data
■
Core V
DD
❐
= 1.8V (±0.1V); I/O V
DDQ
= 1.4V to V
Supports both 1.5V and 1.8V I/O supply
DD
■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ Variable Drive HSTL Output Buffers
■ JTAG 1149.1 Compatible Test Access Port
■ Phase Locked Loop (PLL) for Accurate Data Placement
Table 1. Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
Configurations
CY7C1510KV18 – 8M x 8
CY7C1525KV18 – 8M x 9
CY7C1512KV18 – 4M x 18
CY7C1514KV18 – 2M x 36
Functional Description
The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and
CY7C1514KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common
I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the
QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 8-bit words (CY7C1510KV18), 9-bit words
(CY7C1525KV18), 18-bit words (CY7C1512KV18), or 36-bit words (CY7C1514KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects, which enables each port to operate independently.
All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
x8 x9 x18 x36
350 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz
350 333 300 250 200 167
825
825
790
790
730
730
640
640
540
540
480
480
840
1030
810
990
750
910
650
790
550
660
490
580
Unit
MHz mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00436 Rev. *L
• San Jose
,
CA 95134-1709 • 408-943-2600
Revised April 07, 2010
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Logic Block Diagram (CY7C1510KV18)
8
D
[7:0]
Write
Reg
A
(21:0)
22 Address
Register
K
K
DOFF
V
REF
WPS
NWS
[1:0]
CLK
Gen.
Control
Logic
Write
Reg
Read Data Reg.
16
8
8
Address
Register
22
A
(21:0)
Control
Logic
Reg.
Reg.
Reg.
8
8
8
RPS
C
C
CQ
CQ
Q
[7:0]
Logic Block Diagram (CY7C1525KV18)
9
D
[8:0]
Write
Reg
A
(21:0)
22 Address
Register
K
K
DOFF
V
REF
WPS
BWS
[0]
CLK
Gen.
Control
Logic
Write
Reg
Read Data Reg.
18
9
9
Address
Register
22
A
(21:0)
Control
Logic
Reg.
Reg.
Reg.
9
9
9
RPS
C
C
CQ
CQ
Q
[8:0]
Document Number: 001-00436 Rev. *L Page 2 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Logic Block Diagram (CY7C1512KV18)
18
D
[17:0]
Write
Reg
A
(20:0)
21 Address
Register
K
K
DOFF
V
REF
WPS
BWS
[1:0]
CLK
Gen.
Control
Logic
Write
Reg
Read Data Reg.
36
18
18
Address
Register
21
A
(20:0)
Control
Logic
Reg.
Reg.
Reg.
18
18
18
RPS
C
C
CQ
CQ
Q
[17:0]
Logic Block Diagram (CY7C1514KV18)
D
[35:0]
36
Write
Reg
Write
Reg
A
(19:0)
20 Address
Register
K
K
DOFF
V
REF
WPS
BWS
[3:0]
CLK
Gen.
Control
Logic
Read Data Reg.
72
36
36
Address
Register
20
A
(19:0)
Control
Logic
Reg.
Reg.
Reg.
36
36
36
RPS
C
C
CQ
CQ
Q
[35:0]
Document Number: 001-00436 Rev. *L Page 3 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Contents
Features ..............................................................................1
Configurations ....................................................................1
Functional Description .......................................................1
Contents ..............................................................................2
Logic Block Diagram (CY7C1510KV18) ............................3
Logic Block Diagram (CY7C1525KV18) ............................3
Logic Block Diagram (CY7C1512KV18) ............................4
Logic Block Diagram (CY7C1514KV18) ............................4
Pin Configuration ...............................................................5
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout ....................5
Pin Definitions ....................................................................7
Functional Overview ..........................................................9
Read Operations ...........................................................9
Write Operations ...........................................................9
Byte Write Operations ...................................................9
Single Clock Mode ........................................................9
Concurrent Transactions ...............................................9
Depth Expansion ...........................................................9
Programmable Impedance ............................................9
Echo Clocks ................................................................10
PLL ..............................................................................10
Application Example ........................................................10
Truth Table ........................................................................11
Write Cycle Descriptions .................................................11
Write Cycle Descriptions .................................................12
Write Cycle Descriptions .................................................12
IEEE 1149.1 Serial Boundary Scan (JTAG) ....................13
Disabling the JTAG Feature ........................................13
Test Access Port—Test Clock .....................................13
Test Mode Select (TMS) .............................................13
Test Data-In (TDI) .......................................................13
Test Data-Out (TDO) ...................................................13
Performing a TAP Reset .............................................13
TAP Registers .............................................................13
Instruction Register ..............................................13
Bypass Register ...................................................13
Boundary Scan Register ......................................13
Identification (ID) Register ....................................13
TAP Instruction Set ..................................................... 13
IDCODE ............................................................... 14
SAMPLE Z ........................................................... 14
SAMPLE/PRELOAD ............................................ 14
BYPASS ............................................................... 14
EXTEST ............................................................... 14
EXTEST OUTPUT BUS TRISTATE .................... 14
Reserved .............................................................. 14
TAP Controller State Diagram ......................................... 15
TAP Controller Block Diagram ........................................ 16
TAP Electrical Characteristics ........................................ 16
TAP AC Switching Characteristics ................................. 17
TAP Timing and Test Conditions .................................... 17
Identification Register Definitions .................................. 18
Scan Register Sizes ......................................................... 18
Instruction Codes ............................................................. 18
Boundary Scan Order ...................................................... 19
Power Up Sequence in QDR II SRAM ............................. 20
Power Up Sequence ................................................... 20
PLL Constraints ........................................................... 20
Maximum Ratings ............................................................. 21
Operating Range .............................................................. 21
Neutron Soft Error Immunity ........................................... 21
Electrical Characteristics ................................................ 21
DC Electrical Characteristics ....................................... 21
AC Electrical Characteristics ....................................... 23
Capacitance ...................................................................... 24
Thermal Resistance ......................................................... 24
Switching Characteristics ............................................... 25
Switching Waveforms ...................................................... 27
Ordering Information ....................................................... 28
Package Diagram ............................................................. 29
Document History Page ................................................... 30
Sales, Solutions, and Legal Information ........................ 31
Worldwide Sales and Design Support ......................... 31
Products ...................................................................... 31
Document Number: 001-00436 Rev. *L Page 4 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
P
R
M
N
K
L
H
J
F
G
D
E
A
B
C
Pin Configuration
The pin configurations for CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 follow.
P
R
M
N
K
L
H
J
F
G
D
E
A
B
C
DOFF
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
1
CQ
NC
NC
NC
Q6
NC
D7
NC
TCK
2
A
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
D6
NC
NC
Q7
A
3
A
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1510KV18 (8M x 8)
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
A
A
A
K
A
6
K
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
NWS
0
A
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
A
7 8
NC/144M RPS
A
A
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
NC
NC
NC
NC
NC
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
TMS
10
A
NC
NC
NC
D2
NC
NC
V
REF
Q1
DOFF
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
1
CQ
NC
NC
NC
D7
NC
NC
Q8
A
3
A
NC
NC
NC
Q5
NC
Q6
V
DDQ
NC
NC
Q7
NC
D8
NC
TCK
2
A
NC
NC
D5
NC
NC
D6
V
REF
NC
4
WPS
CY7C1525KV18 (8M x 9)
5
NC
6
K
7 8
NC/144M RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
BWS
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
0
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
NC
NC
NC
NC
NC
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
D0
TMS
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
D0
NC
NC
TDI
ZQ
D1
NC
Q0
NC
Q2
NC
NC
11
CQ
Q3
D3
D1
NC
Q0
TDI
ZQ
D2
NC
Q1
NC
Q3
NC
NC
11
CQ
Q4
D4
Note
1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-00436 Rev. *L Page 5 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
P
R
M
N
K
L
H
J
F
G
D
E
A
B
C
Pin Configuration
(continued)
The pin configurations for CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 follow.
[1]
P
R
M
N
K
L
H
J
F
G
D
E
A
B
C
DOFF
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
1
CQ
NC
NC
2
NC/144M
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
Q14
D15
D16
Q16
Q17
A
3
A
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1512KV18 (4M x 18)
5
BWS
1
NC
A
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
A
A
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
K
A
6
K
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
BWS
0
A
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
A
7 8
NC/288M RPS
A
A
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
NC
NC
NC
NC
NC
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
D3
NC
Q1
NC
D0
TMS
10
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
1
CQ
Q27
D27
D28
Q29
Q30
D30
2
NC/288M
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
Q23
D24
D25
Q25
Q26
A
3
A
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
CY7C1514KV18 (2M x 36)
5
BWS
2
BWS
3
A
6
K
K
A
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
A
A
A
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
A
C
C
7
BWS
1
BWS
0
A
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
Q12
D11
D10
Q10
Q9
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
10
NC/144M
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
D2
D1
Q0
TDI
ZQ
D4
Q3
Q2
D7
Q6
Q5
D5
11
CQ
Q8
D8
D2
D1
Q0
TDI
ZQ
D4
Q3
Q2
D7
Q6
Q5
D5
11
CQ
Q8
D8
Document Number: 001-00436 Rev. *L Page 6 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Pin Definitions
Pin Name
D
[x:0]
WPS
NWS
NWS
BWS
BWS
BWS
A
Q
RPS
C
C
K
K
[x:0]
0
1
0
1
2
BWS
3
,
,
,
,
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Output-
Synchronous
Input-
Synchronous
Pin Description
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1510KV18 D
CY7C1525KV18 D
[7:0]
CY7C1512KV18 D
[8:0]
CY7C1514KV18 D
[17:0]
[35:0]
Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
Nibble Write Select 0, 1 Active LOW (CY7C1510KV18 Only). Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered.
NWS
0
controls D
[3:0] and NWS
1
controls D
[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device.
Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered.
CY7C1525KV18 BWS
CY7C1512KV18 BWS
CY7C1514KV18 BWS
0
0
controls D
0
controls D
[8:0].
[8:0]
and BWS
controls D
[8:0]
, BWS
1
1
controls D
controls D
[17:9]
[17:9].
, BWS
2
controls D
[26:18]
and BWS
3
controls
D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device.
Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during active read and write operations. These address inputs are multiplexed for both read and write operations.
Internally, the device is organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1510KV18, 8M x 9
(2 arrays each of 4M x 9) for CY7C1525KV18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1512KV18, and 2M x 36 (2 arrays each of 1M x 36) for CY7C1514KV18. Therefore, only 22 address inputs are needed to access the entire memory array of CY7C1510KV18 and CY7C1525KV18, 21 address inputs for
CY7C1512KV18, and 20 address inputs for CY7C1514KV18. These inputs are ignored when the appropriate port is deselected.
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in single clock mode. When the read port is deselected, Q
CY7C1510KV18 Q
CY7C1525KV18 Q
[7:0]
CY7C1512KV18 Q
[8:0]
[x:0]
are automatically tristated.
CY7C1514KV18 Q
[17:0]
[35:0]
Read Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active, a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tristated following the next rising edge of the
C clock. Each read access consists of a burst of two sequential transfers.
Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See Application Example on page 10 for further details.
Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See Application Example on page 10 for further details.
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q edge of K.
[x:0] when in single clock mode. All accesses are initiated on the rising
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q
[x:0]
when in single clock mode.
Document Number: 001-00436 Rev. *L Page 7 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Pin Definitions
(continued)
Pin Name
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/144M
NC/288M
V
V
V
V
REF
DD
SS
DDQ
I/O Pin Description
Echo Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in
Switching Characteristics on page 25.
Echo Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in the Switching Characteristics on page 25.
Input
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q
[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, connect this pin directly to V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation, connect this pin to a pull up through a 10 K or less pull up resistor. The device behaves in QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR I timing.
Output
Input
Input
Input
N/A
Input
Input
Input-
Reference
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points.
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-00436 Rev. *L Page 8 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Functional Overview
The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and
CY7C1514KV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations.
Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR II completely eliminates the need to turn around the data bus and avoids any possible data contention, thereby simplifying system design.
Each access consists of two 8-bit data transfers in the case of
CY7C1510KV18, two 9-bit data transfers in the case of
CY7C1525KV18, two 18-bit data transfers in the case of
CY7C1512KV18, and two 36-bit data transfers in the case of
CY7C1514KV18 in one clock cycle.
This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to V
SS
then the device behaves in QDR I mode with a read latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C, or K and K when in single clock mode).
All synchronous data inputs (D
[x:0]
) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q
[x:0]
) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS clocks (K and K).
[x:0]
) inputs pass through input registers controlled by the rising edge of the input
CY7C1512KV18 is described in the following sections. The same basic descriptions apply to CY7C1510KV18,
CY7C1525KV18, and CY7C1514KV18.
Read Operations
The CY7C1512KV18 is organized internally as two arrays of 2M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address is latched on the rising edge of the K clock. The address presented to the address inputs is stored in the read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q
[17:0]
using
C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q
[17:0]
. The requested data is valid 0.45 ns from the rising edge of the output clock (C and C or K and K when in single clock mode).
Synchronous internal circuitry automatically tristates the outputs following the next rising edge of the output clocks (C/C). This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the same K clock rise the data presented to D
[17:0]
is latched and stored into the lower 18-bit write data register, provided BWS
[1:0]
are both asserted active. On the subsequent rising edge of the negative input clock (K), the address is latched and the information presented to D
[17:0] provided BWS
[1:0]
is also stored into the write data register,
are both asserted active. The 36 bits of data are then written into the memory array at the specified location.
When deselected, the write port ignores all inputs after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1512KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS
BWS
1
0
and
, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature is used to simplify read, modify, or write operations to a byte write operation.
Single Clock Mode
The CY7C1512KV18 is used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and
C/C clocks. All timing parameters remain the same in this mode.
To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation.
Concurrent Transactions
The read and write ports on the CY7C1512KV18 operate completely independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. The user can start reads and writes in the same clock cycle.
If the ports access the same location at the same time, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise.
Depth Expansion
The CY7C1512KV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port
Document Number: 001-00436 Rev. *L Page 9 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 and 350 , with V
DDQ
= 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture on high speed systems. Two echo clocks are generated by the
QDR II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the QDR II. In the single clock mode,
CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device
Application Example
Figure 1 shows two QDR II used in an application.
Figure 1. Application Example
Vt
R
D
A
S
#
R
P
W
P
S
#
SRAM #1
B
W
S
#
CQ/CQ#
Q
C C# K
ZQ
K#
R = 250 ohms
DATA IN
DATA OUT
Address
BUS
MASTER
(CPU or
RPS#
WPS#
BWS#
CLKIN/CLKIN#
Source K
ASIC)
Source K#
Delayed K
Delayed K#
R
R = 50 ohms
Vt = Vddq/2
D
A
R
Vt
Vt
S
#
R
P
W
P
S
#
B
W
S
#
SRAM #2
C C# K
ZQ
CQ/CQ#
Q
K#
R = 250 ohms
Document Number: 001-00436 Rev. *L Page 10 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Truth Table
The truth table for CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 follow.
Operation
Write Cycle:
Load address on the rising edge of K; input write data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges.
NOP: No Operation
K
L-H
L-H
L-H
RPS WPS
X
DQ
L D(A + 0) at K(t)
L
H
DQ
D(A + 1) at K(t)
X Q(A + 0) at C(t + 1) Q(A + 1) at C(t + 2)
Standby: Clock Stopped Stopped X
H D = X
Q = High-Z
X Previous State
D = X
Q = High-Z
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1510KV18 and CY7C1512KV18 follow.
BWS
0
/
NWS
0
L
BWS
1
/
NWS
1
L
L
L
L
H
H
H
H
L
H
H
L
L
H
H
K K Comments
L–H – During the data portion of a write sequence
CY7C1510KV18 both nibbles (D
[7:0]
) are written into the device.
CY7C1512KV18 both bytes (D
[17:0]
) are written into the device.
– L-H During the data portion of a write sequence
CY7C1510KV18 both nibbles (D
[7:0]
) are written into the device.
CY7C1512KV18 both bytes (D
[17:0]
) are written into the device.
L–H – During the data portion of a write sequence
CY7C1510KV18 only the lower nibble (D
[3:0]
) is written into the device, D
[7:4]
remains unaltered.
CY7C1512KV18 only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
– L–H During the data portion of a write sequence
CY7C1510KV18 only the lower nibble (D
[3:0]
) is written into the device, D
[7:4]
remains unaltered.
CY7C1512KV18 only the lower byte (D
[8:0]
) is written into the device, D
[17:9]
remains unaltered.
L–H – During the data portion of a write sequence
CY7C1510KV18 only the upper nibble (D
[7:4]
) is written into the device, D
CY7C1512KV18 only the upper byte (D
[17:9]
) is written into the device, D
[3:0]
remains unaltered.
[8:0]
remains unaltered.
– L–H During the data portion of a write sequence
CY7C1510KV18 only the upper nibble (D
[7:4]
) is written into the device, D
CY7C1512KV18 only the upper byte (D
[17:9]
) is written into the device, D
[3:0]
remains unaltered.
[8:0]
remains unaltered.
L–H – No data is written into the devices during this portion of a write operation.
– L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions
different portions of a write cycle, as long as the setup and hold requirements are achieved.
table. NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
, and BWS
3 can be altered on
Document Number: 001-00436 Rev. *L Page 11 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Write Cycle Descriptions
The write cycle description table for CY7C1525KV18 follow.
BWS
0
L
L
H
H
K
L–H
–
L–H
–
K
– During the data portion of a write sequence, the single byte (D
[8:0]
) is written into the device.
L–H During the data portion of a write sequence, the single byte (D
[8:0]
) is written into the device.
– No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1514KV18 follow.
BWS
0
L
L
L
L
H
H
H
H
H
H
H
H
BWS
1
L
L
H
H
L
L
H
H
H
H
H
H
BWS
2
L
L
H
H
H
H
L
L
H
H
H
H
BWS
3
L
L
H
H
H
H
H
H
L
L
H
H
K K Comments
L–H – During the data portion of a write sequence, all four bytes (D
[35:0] the device.
) are written into
– L–H During the data portion of a write sequence, all four bytes (D
[35:0] the device.
) are written into
L–H – During the data portion of a write sequence, only the lower byte (D into the device. D
[35:9]
remains unaltered.
[8:0]
) is written
– L–H During the data portion of a write sequence, only the lower byte (D
[8:0] into the device. D
[35:9]
remains unaltered.
) is written
L–H – During the data portion of a write sequence, only the byte (D
[17:9] the device. D
[8:0]
and D
[35:18] remains unaltered.
) is written into
– L–H During the data portion of a write sequence, only the byte (D
[17:9] the device. D
[8:0]
and D
[35:18] remains unaltered.
) is written into
L–H – During the data portion of a write sequence, only the byte (D the device. D
[17:0]
and D
[35:27] remains unaltered.
[26:18]
) is written into
– L–H During the data portion of a write sequence, only the byte (D
[26:18] the device. D
[17:0]
and D
[35:27] remains unaltered.
) is written into
L–H – During the data portion of a write sequence, only the byte (D the device. D
[26:0]
remains unaltered.
[35:27]
) is written into
– L–H During the data portion of a write sequence, only the byte (D
[35:27] the device. D
[26:0]
remains unaltered.
) is written into
L–H – No data is written into the device during this portion of a write operation.
– L–H No data is written into the device during this portion of a write operation.
Document Number: 001-00436 Rev. *L Page 12 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW
(V
SS
) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to V
DD
through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (V
DD
) for five rising edges of TCK. This Reset does not affect the operation of the
SRAM and is performed when the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI
the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (V the BYPASS instruction is executed.
SS
) when
Boundary Scan Register
The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are used to capture the contents of the input and output ring.
The Boundary Scan Order on page 19 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on page 18.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state.
Document Number: 001-00436 Rev. *L Page 13 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (t
CS
and t
CH
). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a
High-Z condition.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is pre-set LOW to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for future use. Do not use these instructions.
Document Number: 001-00436 Rev. *L Page 14 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows.
1
0
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
0
SELECT
DR-SCAN
0
CAPTURE-DR
0
SHIFT-DR
1
EXIT1-DR
0
PAUSE-DR
1
EXIT2-DR
1
UPDATE-DR
1
0
1
0
1
0
1
0
SELECT
IR-SCAN
0
CAPTURE-IR
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
EXIT2-IR
1
1
UPDATE-IR
0
1
0
1
0
Note
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-00436 Rev. *L Page 15 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
TAP Controller Block Diagram
TDI
Selection
Circuitry
2 1
0
Bypass Register
0
31
Instruction Register
30 29 .
.
2
Identification Register
1 0
108 .
.
.
.
2
Boundary Scan Register
1 0
Selection
Circuitry
TCK
TMS
TAP Electrical Characteristics
Over the Operating Range
Parameter
V
IH
V
IL
I
X
V
OH1
V
OH2
V
OL1
V
OL2
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and Output Load Current
TAP Controller
TDO
Test Conditions
I
OH
= 2.0 mA
I
OH
= 100 A
I
OL
= 2.0 mA
I
OL
= 100 A
GND V
I
V
DD
Min
1.4
1.6
Max
0.65V
DD
-0.3
-5
0.4
0.2
V
DD
+ 0.3
0.35V
DD
5
Unit
V
V
V
V
V
V
A
Notes
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI, and TDO). Parallel load levels are specified in the
table.
11. Overshoot: V
IH
(AC) < V
DDQ
+ 0.85V (Pulse width less than t
CYC
/2), Undershoot: V
IL
(AC) > -1.5V (Pulse width less than t
CYC
/2).
12. All voltage referenced to Ground.
Document Number: 001-00436 Rev. *L Page 16 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter t
TCYC t
TF t
TH t
TL
Setup Times t
TMSS t
TDIS t
CS
Hold Times t
TMSH t
TDIH t
CH
Output Times t
TDOV t
TDOX
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Description
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions.
Figure 2. TAP Timing and Test Conditions
0.9V
TDO
50
0V
1.8V
ALL INPUT PULSES
0.9V
Z
0
= 50
C
L
= 20 pF
Min
50
20
20
0
5
5
5
5
5
5
(a) GND t
TH t
TL
Test Clock
TCK t
TCYC t
TMSH t
TMSS
Test Mode Select
TMS t
TDIS t
TDIH
Test Data In
TDI
Test Data Out
TDO t
TDOV t
TDOX
Notes
13. t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC Test Conditions. t
R
/t
F
= 1 ns.
Document Number: 001-00436 Rev. *L
Max
20
10 ns ns ns ns ns
Unit ns
MHz ns ns ns ns ns
Page 17 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Identification Register Definitions
Instruction Field
CY7C1525KV18
Value
CY7C1512KV18
000 000
CY7C1514KV18
000
Description
Revision Number
(31:29)
Cypress Device ID
(28:12)
Cypress JEDEC ID
(11:1)
ID Register
Presence (0)
CY7C1510KV18
000 Version number.
11010011010000100 11010011010001100 11010011010010100 11010011010100100 Defines the type of
SRAM.
00000110100 00000110100 00000110100 00000110100 Allows unique identification of
SRAM vendor.
1 1 1 1 Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Instruction Codes
Instruction
EXTEST
IDCODE
Code
000
001
SAMPLE Z
RESERVED
SAMPLE/PRELOA
D
RESERVED
RESERVED
BYPASS
010
011
100
101
110
111
Bit Size
3
1
32
109
Description
Captures the input and output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the input and output contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Document Number: 001-00436 Rev. *L Page 18 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Boundary Scan Order
19
20
21
22
15
16
17
18
23
24
25
26
27
11
12
13
14
7
8
9
10
5
6
3
4
Bit #
0
1
2
9M
9N
11L
11M
9L
10L
11K
10K
9J
9K
10J
11J
11H
8P
9R
11P
10P
10N
9P
10M
11N
Bump ID
6R
6P
6N
7P
7N
7R
8R
47
48
49
50
43
44
45
46
51
52
53
54
55
39
40
41
42
35
36
37
38
31
32
33
34
Bit #
28
29
30
11C
9B
10B
11A
10A
9A
8B
7C
6C
8A
7A
7B
6B
10E
10D
9E
10C
11D
9C
9D
11B
Bump ID Bit #
10G 56
9G
11F
57
58
11G
9F
10F
11E
59
60
61
62
67
68
69
70
63
64
65
66
75
76
77
78
71
72
73
74
79
80
81
82
83
2E
1E
2F
3F
1D
2C
3E
2D
1G
1F
3G
2G
1H
1C
1B
3D
3C
2A
1A
2B
3B
Bump ID
6A
5B
5A
4A
5C
4B
3A
3M
1N
2M
3P
3L
1M
1L
3N
Bump ID
1J
2J
3K
3J
2K
1K
2L
4R
4P
5P
5N
2N
2P
1P
3R
5R
Internal
95
96
97
98
91
92
93
94
87
88
89
90
Bit #
84
85
86
103
104
105
106
99
100
101
102
107
108
Document Number: 001-00436 Rev. *L Page 19 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Power Up Sequence in QDR II SRAM
QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
Power Up Sequence
■
Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW).
❐
❐
❐
Apply V
DD
before V
DDQ
.
Apply V
DDQ before V
Drive DOFF HIGH.
REF
or at the same time as V
REF
.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s to lock the PLL.
PLL Constraints
■ PLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as t
KC Var
.
■ The PLL functions at frequencies down to 120 MHz.
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to relock to the desired clock frequency.
Figure 3. Power Up Waveforms
~ ~
K
K
Unstable Clock > 20Ps Stable clock Start Normal
Operation
V
DD
/ V
DDQ
DOFF
V DD / V DDQ
Stable (< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to VDDQ)
Document Number: 001-00436 Rev. *L Page 20 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature .................................. -65°C to +150°C
Ambient Temperature with Power Applied... -55°C to +125°C
Supply Voltage on V
DD
Relative to GND ........ -0.5V to +2.9V
Supply Voltage on V
DDQ
Relative to GND....... -0.5V to +V
DD
DC Applied to Outputs in High-Z .........-0.5V to V
DDQ
+ 0.5V
DC Input Voltage
................................ -0.5V to V
DD
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature (T
A
)
0°C to +70°C
-40°C to +85°C
V
DD
V
DDQ
1.8 ± 0.1V
1.4V to
V
DD
Neutron Soft Error Immunity
Parameter Description
LSBU
LMBU
SEL
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range
Parameter
V
DD
V
DDQ
V
OH
V
OL
V
OH(LOW)
V
OL(LOW)
V
IH
V
IL
I
X
I
OZ
V
REF
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Input Reference Voltage
Test Conditions
I
OH
= 0.1 mA, Nominal Impedance
I
OL
= 0.1 mA, Nominal Impedance
GND V
I
V
DDQ
GND V
I
V
DDQ,
Output Disabled
Typical Value = 0.75V
Logical
Single-Bit
Upsets
Logical
Multi-Bit
Upsets
Single Event
Latch up
Test
Conditions Typ Max* Unit
25°C 197 216 FIT/
Mb
25°C
85°C
0 0.01
FIT/
Mb
0 0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a statistical 2 , 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Min
1.7
1.4
V
DDQ
/2 – 0.12
V
DDQ
/2 – 0.12
V
DDQ
– 0.2
V
SS
V
REF
+ 0.1
-0.3
5
5
0.68
Typ
1.8
1.5
0.75
Max
1.9
Unit
V
V
DD
V
V
DDQ
/2 + 0.12
V
V
DDQ
/2 + 0.12
V
V
DDQ
0.2
V
V
V
DDQ
+ 0.3
V
REF
– 0.1
5
V
5
0.95
V
A
A
V
Notes
15. Power up: Assumes a linear ramp from 0V to V
16. Output are impedance controlled. I
17. Output are impedance controlled. I
18. V
REF
(min) = 0.68V or 0.46V
DDQ
OH
OL
=
= (V
(V
DD
(min) within 200 ms. During this time V
DDQ
/2)/(RQ/5) for values of 175
DDQ
/2)/(RQ/5) for values of 175
, whichever is larger, V
RQ 350
RQ 350
IH
.
< V
.
DD and V
DDQ
< V
REF
(max) = 0.95V or 0.54V
DDQ
, whichever is smaller.
DD
.
Document Number: 001-00436 Rev. *L Page 21 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Electrical Characteristics
(continued)
DC Electrical Characteristics
Over the Operating Range
[12]
Parameter
I
DD
Description
V
DD
Operating Supply
Test Conditions
I
V
DD
OUT
= Max,
= 0 mA, f = f
MAX
= 1/t
CYC
350 MHz (x8)
(x9)
(x18)
(x36)
333 MHz (x8)
(x9)
(x18)
(x36)
300 MHz (x8)
(x9)
(x18)
(x36)
250 MHz (x8)
(x9)
(x18)
(x36)
200 MHz (x8)
(x9)
(x18)
(x36)
167 MHz (x8)
(x9)
(x18)
(x36)
Min Typ
750
910
640
640
810
990
730
730
Max
825
825
840
1030
790
790
550
660
480
480
650
790
540
540
490
580
Unit mA mA mA mA mA mA
Note
19. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-00436 Rev. *L Page 22 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Electrical Characteristics
(continued)
DC Electrical Characteristics
Over the Operating Range
[12]
Parameter
I
SB1
Description
Automatic Power Down
Current
Test Conditions
Max V
DD
,
Both Ports Deselected,
V
IN
V
IH f = f
MAX
or V
= 1/t
Inputs Static
IN
V
CYC
,
IL
350 MHz (x8)
(x9)
(x18)
(x36)
333 MHz (x8)
(x9)
(x18)
(x36)
300 MHz (x8)
(x9)
(x18)
(x36)
250 MHz (x8)
(x9)
(x18)
(x36)
200 MHz (x8)
(x9)
(x18)
(x36)
167 MHz (x8)
(x9)
(x18)
(x36)
AC Electrical Characteristics
Over the Operating Range
Parameter
V
IH
V
IL
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
Min
V
REF
+ 0.2
–
Typ Unit mA mA mA mA mA mA
Typ
–
–
Max
–
V
REF
– 0.2
Unit
V
V
280
280
270
270
290
290
280
280
Max
295
295
295
295
290
290
250
250
250
250
270
270
250
250
250
250
Document Number: 001-00436 Rev. *L Page 23 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
C
IN
C
O
Description
Output Capacitance
Test Conditions
T
A
= 25 C, f = 1 MHz, V
DD
= 1.8V, V
DDQ
= 1.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
JA
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.
Figure 4. AC Test Loads and Waveforms
Max
4
4
165 FBGA
Package
13.7
3.73
Unit pF pF
Unit
°C/W
°C/W
V
REF
OUTPUT
DEVICE
UNDER
TEST
ZQ
0.75V
Z
0
= 50
R
L
= 50
V
REF
= 0.75V
RQ =
250
(a)
V
REF
OUTPUT
DEVICE
UNDER
TEST
ZQ
V
REF
= 0.75V
0.75V
R = 50
INCLUDING
JIG AND
SCOPE
RQ =
250
(b)
5 pF
0.25V
ALL INPUT PULSES
1.25V
0.75V
SLEW RATE= 2 V/ns
Note
20. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250 , V pulse levels of 0.25V to 1.25V, and output loading of the specified I
OL
/I
OH
and load capacitance shown in (a) of AC Test Loads and Waveforms
.
DDQ
= 1.5V, input
Document Number: 001-00436 Rev. *L Page 24 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Switching Characteristics
Over the Operating Range
t t t t t
Cypress
Parameter
Consortium
Parameter
POWER
CYC t
KH t t
KHKH
KHKL
Description
350 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz
Min Max Min Max Min Max Min Max Min Max Min Max
Unit
V
DD
(Typical) to the First Access
1 1 1 1 1 1 ms
K Clock and C Clock Cycle Time 2.85 8.4 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns
Input Clock (K/K; C/C) HIGH 1.14
– 1.20
– 1.32
– 1.6
– 2.0
– 2.4
– ns t
KL t
KHKH t
KLKH t
KHKH
Input Clock (K/K; C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge)
1.14
– 1.20
– 1.32
– 1.6
– 2.0
– 2.4
– ns
1.28
– 1.35
– 1.49
– 1.8
– 2.2
– 2.7
– ns t
KHCH t
KHCH
K/K Clock Rise to C/C Clock Rise
(rising edge to rising edge)
0 1.22
0 1.30
0 1.45
0 1.8
0 2.2
0 2.7 ns
Setup Times t
SA t
SC t
AVKH t
IVKH
SCDDR t
IVKH
Address Setup to K Clock Rise
Control Setup to K Clock Rise
(RPS, WPS)
DDR Control Setup to Clock (K/K)
Rise (BWS
0
, BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Setup to Clock (K/K) Rise
0.3
0.3
0.3
0.3
–
–
–
–
0.3
0.3
0.3
0.3
–
–
–
–
0.3
0.3
0.3
0.3
–
–
–
–
0.35
0.35
0.35
0.35
–
–
–
–
0.4
0.4
0.4
0.4
–
–
–
–
0.5
0.5
0.5
0.5
–
–
–
– ns ns ns ns t
SD
Hold Times t
DVKH t
HA t
HC t t
KHAX
KHIX
Address Hold after K Clock Rise 0.3
– 0.3
– 0.3
– 0.35
– 0.4
– 0.5
– ns
HCDDR
HD t t
KHIX
KHDX
Control Hold after K Clock Rise
(RPS, WPS)
DDR Control Hold after Clock (K/K)
Rise (BWS
0
, BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Hold after Clock (K/K) Rise
0.3
– 0.3
– 0.3
– 0.35
– 0.4
– 0.5
– ns
0.3
– 0.3
– 0.3
– 0.35
– 0.4
– 0.5
– ns
0.3
– 0.3
– 0.3
– 0.35
– 0.4
– 0.5
– ns
Notes
21. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range.
22. This part has a voltage regulator internally; t
POWER
is the time that the power must be supplied above V
DD minimum initially before initiating a read or write operation.
Document Number: 001-00436 Rev. *L Page 25 of 31
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CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Switching Characteristics
(continued)
Over the Operating Range
[20, 21] t t t t t t t t
Cypress
Parameter
Consortium
Parameter
Output Times t
CO t
CHQV
DOH
CCQO
CQOH
CQD
CQDOH
CQH
CQHCQH
CHZ t t t t t t t t
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
CHQZ
Description
350 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz
Min Max Min Max Min Max Min Max Min Max Min Max
Unit
C/C Clock Rise (or K/K in single clock mode) to Data Valid
– 0.45
– 0.45
– 0.45
– 0.45
– 0.45
– 0.50 ns
Data Output Hold after Output C/C
Clock Rise (Active to Active)
-0.45 – -0.45 – -0.45 – -0.45 – -0.45 – -0.50 – ns
C/C Clock Rise to Echo Clock Valid – 0.45
– 0.45
– 0.45
– 0.45
– 0.45
– 0.50 ns
Echo Clock Hold after C/C Clock
Rise
-0.45 – -0.45 – -0.45 – -0.45 – -0.45 – -0.50 – ns
Echo Clock High to Data Valid 0.25
0.25
0.27
– 0.30
– 0.35
– 0.40 ns
-0.25 – -0.25 – -0.27 – -0.30 – -0.35 – -0.40 – ns Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
Clock (C/C) Rise to High-Z
(Active to High-Z)
Clock (C/C) Rise to Low-Z
1.18
1.18
–
–
–
0.45
1.25
1.25
–
–
–
0.45
1.40
1.40
–
–
–
0.45
1.75
1.75
–
–
–
0.45
2.25
2.25
–
–
–
0.45
2.75
2.75
–
–
– ns ns
0.50 ns
-0.45 – -0.45 – -0.45 – -0.45 – -0.45 – -0.50 – ns t
CLZ
PLL Timing t
CHQX1 t
KC Var t
KC lock t
KC Reset t
KC Var t
KC lock t
KC Reset
Clock Phase Jitter
PLL Lock Time (K, C)
K Static to PLL Reset
–
20
30
0.20
–
–
20
30
0.20
–
–
20
30
0.20
–
–
20
30
0.20
–
–
20
30
0.20
–
–
20
30
0.20 ns
– s ns
Notes
23. These parameters are extrapolated from the input timing parameters (t
CYC
/2
24. t design and are not tested in production.
, t
CLZ
less than t
CO
.
- 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
CHZ
, are specified with a load capacitance of 5 pF as in part (b) of
AC Test Loads and Waveforms . Transition is measured
100 mV from steady state voltage.
25. At any voltage and temperature t
CHZ
is less than t
CLZ and t
CHZ
Document Number: 001-00436 Rev. *L Page 26 of 31
[+] Feedback
CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Switching Waveforms
CQ
Figure 5. Read/Write/Deselect Sequence
1
READ WRITE
2
READ
3
WRITE
4
READ
5
WRITE
6
NOP
7
K tKH tKL tCYC tKHKH
K
RPS t
SC t tHC
WPS
A A0
Q
D D10
A1 A2 tSA tHA
D11 tSA tHA
D30
A3
D31 tSD tHD tKHCH tKL tCLZ tCO
A4 A5
D50 D51 D60
Q00 tSD tHD
Q01 tDOH
Q20 tCQDOH
C tKH tKHCH tKHKH tCYC
C tCCQO tCQOH
CQ tCCQO tCQOH
WRITE
8
NOP
9
A6
D61
Q21 tCQD tCQH
10
Q40 t
CHZ
Q41 tCQHCQH
DON’T CARE UNDEFINED
Notes
26. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
27. Outputs are disabled (High-Z) one clock cycle after a NOP.
28. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-00436 Rev. *L Page 27 of 31
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Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com
and refer to the product summary page at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz) Ordering Code
350 CY7C1512KV18-350BZC
333 CY7C1525KV18-333BZC
CY7C1512KV18-333BZC
CY7C1514KV18-333BZC
CY7C1525KV18-333BZXC
CY7C1512KV18-333BZXC
CY7C1514KV18-333BZXC
CY7C1512KV18-333BZI
CY7C1514KV18-333BZI
CY7C1512KV18-333BZXI
CY7C1514KV18-333BZXI
300 CY7C1525KV18-300BZC
CY7C1512KV18-300BZC
CY7C1514KV18-300BZC
CY7C1525KV18-300BZXC
CY7C1512KV18-300BZXC
CY7C1514KV18-300BZXC
CY7C1512KV18-300BZI
CY7C1514KV18-300BZI
CY7C1512KV18-300BZXI
CY7C1514KV18-300BZXI
250 CY7C1525KV18-250BZC
CY7C1512KV18-250BZC
CY7C1514KV18-250BZC
CY7C1525KV18-250BZXC
CY7C1512KV18-250BZXC
CY7C1514KV18-250BZXC
CY7C1512KV18-250BZI
CY7C1514KV18-250BZI
CY7C1525KV18-250BZXI
CY7C1512KV18-250BZXI
CY7C1514KV18-250BZXI
Package
Diagram Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Industrial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Industrial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Operating
Range
Commercial
Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Industrial
Document Number: 001-00436 Rev. *L Page 28 of 31
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Package Diagram
Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
51-85180 *C
Document Number: 001-00436 Rev. *L Page 29 of 31
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Document History Page
Document Title: CY7C1510KV18/CY7C1525KV18/CY7C1512KV18/CY7C1514KV18, 72-Mbit QDR
®
II SRAM 2-Word Burst
Architecture
Document Number: 001-00436
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
*A
374703
1103823
SYT
VKN
See ECN New Data Sheet
See ECN Updated I
DD
Spec
Updated ordering information table
*B
*C
*D
*E
*F
*G
*H
*I
*J
*K
*L
1699083 VKN/AESA See ECN Converted from Advance Information to Preliminary
2148307 VKN/AESA See ECN Changed PLL lock time from 1024 cycles to 20 s
Added footnote #19 related to I
DD
Corrected typo in the footnote #23
2606839 VKN/PYRS 11/13/08 Changed JTAG ID [31:29] from 001 to 000,
Updated power up sequence waveform and its description,
Changed Ambient Temperature with Power Applied from “-10°C to +85°C” to
“-55°C to +125°C” in the “Maximum Ratings” on page 20,
Included Thermal Resistance values,
Changed the package size from 15 x 17 x 1.4 mm to 13 x 15 x 1.4 mm.
2681899 VKN/PYRS 04/01/2009 Converted from preliminary to final
Added note on top of the Ordering Information table
Moved to external web
2747635 VKN/AESA 08/03/2009 Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information
2767155 VKN 09/23/2009 Changed Input Capacitance (C
IN
Changed Output Capacitance (C
) from 2 pF to 4 pF
O
) from 3 pF to 4 pF
Modified Ordering code disclaimer
2794726 VKN
2868256 VKN
10/29/09 Included CY7C1525KV18-250BZXI in the Ordering Information table
Updated 165-ball package diagram
Added the
page
01/28/2010 Included 350 MHz speed information
Included CY7C1512KV18-350BZC in the Ordering Information table
2870201 NJY 02/01/2010 No technical updates. Post to external web.
2899924 VKN/NJY 03/26/2010 Updated Ordering Information
2905951 VKN/NJY 04/07/2010 Removed inactive parts from Ordering Information table.
Document Number: 001-00436 Rev. *L Page 30 of 31
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations .
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
© Cypress Semiconductor Corporation, 2005-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-00436 Rev. *L Revised April 07, 2010 Page 31 of 31
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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