Cypress CY7C68320C User's Manual

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge

Features

• Fixed-function mass storage device—requires no firmware

• Two power modes: Self-powered and USB bus-powered to enable bus powered CF readers and truly portable USB hard drives

• Certified compliant for USB 2.0 (TID# 40490119), the USB

Mass Storage Class, and the USB Mass Storage Class

Bulk-Only Transport (BOT) Specification

• Operates at high-speed (480 Mbps) or full-speed (12 Mbps)

USB

• Complies with ATA/ATAPI-6 specification

• Supports 48 bit addressing for large hard drives

• Supports ATA security features

• Supports any ATA command with the ATACB function

• Supports mode page 5 for BIOS boot support

• Supports ATAPI serial number VPD page retrieval for Digital

Rights Management (DRM) compatibility

• Supports PIO modes 0, 3, and 4, multiword DMA mode 2, and UDMA modes 2, 3, and 4

• Uses one small external serial EEPROM for storage of USB descriptors and device configuration data

• ATA interface IRQ signal support

• Supports one or two ATA/ATAPI devices

• Supports CompactFlash and one ATA/ATAPI device

• Supports board-level manufacturing test using the USB I/F

• Can place the ATA interface in high impedance (Hi-Z) to allow sharing of the ATA bus with another controller (i.e., an

IEEE-1394 to ATA bridge chip or MP3 Decoder)

• Low-power 3.3V operation

• Fully compatible with native USB mass storage class drivers

• Cypress mass storage class drivers available for Windows

(98SE, ME, 2000, XP) and Mac OS X operating systems

Features (CY7C68320C/CY7C68321C only)

• Supports HID interface or custom GPIOs to enable features such as single button backup, power-off, LED-based notification, etc.

• 56-pin QFN and 100-pin TQFP lead-free packages

• CY7C68321C is ideal for battery-powered designs

• CY7C68320C is ideal for self- and bus-powered designs

Features (CY7C68300C/CY7C68301C only)

• Pin-compatible with CY7C68300A (using Backward

Compatibility mode)

• 56-pin SSOP and 56-pin QFN lead-free packages

• CY7C68301C is ideal for battery-powered designs

• CY7C68300C is ideal for self- and bus-powered designs

Block Diagram

SCL

SDA

I

2

C Bus Master

24

MHz

XTAL

PLL

USB

VBUS

D+

D-

USB 2.0

Tranceiver

Misc control signals and GPIO

ATA 3-state Control

Internal Control Logic

CY Smart USB

FS/HS Engine

Control

ATA

Interface

Logic

ATA Interface

Control Signals

4 kByte FIFO Data 16 Bit ATA Data

Cypress Semiconductor Corporation

Document 001-05809 Rev. *A

• 198 Champion Court • San Jose

,

CA 95134-1709 • 408-943-2600

Revised November 30, 2006

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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Applications

The CY7C68300C/301C and CY7C68320C/321A implement a USB 2.0 bridge for all ATA/ATAPI-6 compliant mass storage devices, such as the following:

• Hard drives

• CD-ROM, CD-R/W

• DVD-ROM, DVD-RAM, DVD±R/W

• MP3 players

• Personal media players

• CompactFlash

• Microdrives

• Tape drives

• Personal video recorders

The CY7C68300C/301C and CY7C68320C/321A support one or two devices in the following configurations:

• ATA/ATAPI master only

• ATA/ATAPI slave only

• ATA/ATAPI master and ATA/ATAPI slave

• CompactFlash only

• ATA/ATAPI slave and CompactFlash or other removable

IDE master

Additional Resources

• CY4615C EZ-USB AT2LP Reference Design Kit

• USB Specification version 2.0

• ATA Specification T13/1410D Rev 3B

• USB Mass Storage Class Bulk Only Transport Specification, www.usb.org

Introduction

The EZ-USB AT2LP

™ (CY7C68300C/CY7C68301C and

CY7C68320C/CY7C68321C) implements a fixed-function bridge between one USB port and one or two ATA- or

ATAPI-based mass storage device ports. This bridge adheres to the Mass Storage Class Bulk-Only Transport Specification

(BOT) and is intended for bus- and self-powered devices.

The AT2LP is the latest addition to the Cypress USB mass storage portfolio, and is an ideal cost- and power-reduction path for designs that previously used Cypress’s ISD-300A1,

ISD-300LP, or EZ-USB AT2.

Specifically, the CY7C68300C/CY7C68301C includes a mode that makes it pin-for-pin compatible with the

EZ-USB AT2 (CY7C68300A).

The USB port of the CY7C68300C/301C and

CY7C68320C/321A (AT2LP) are connected to a host computer directly or with the downstream port of a USB hub.

Software on the USB host system issues commands and sends data to the AT2LP and receives status and data from the AT2LP using standard USB protocol.

The ATA/ATAPI port of the AT2LP is connected to one or two mass storage devices. A 4 KB buffer maximizes ATA/ATAPI data transfer rates by minimizing losses due to device seek times. The ATA interface supports ATA PIO modes 0, 3, and 4, multiword DMA mode 2, and Ultra DMA modes 2, 3, and 4.

The device initialization process is configurable, enabling the

AT2LP to initialize ATA/ATAPI devices without software intervention.

CY7C68300A Compatibility

As mentioned above, the CY7C68300C/301C contains a backward compatibility mode that allows it to be used in existing EZ-USB AT2 (CY7C68300A) designs. The backward compatibility mode is enabled by programming the EEPROM with the CY7C68300A signature.

During startup, the AT2LP checks the I

2

C™ bus for an

EEPROM with a valid signature in the first two bytes. If the signature is 0x4D4D, the AT2LP configures itself for pin-to-pin compatibility with the AT2 and begins normal mass storage operation. If the signature is 0x534B, the AT2LP configures itself with the AT2LP pinout and begins normal mass storage operation.

Refer to the logic flow in

Figure 1 for more information on the

pinout selection process.

Most designs that use the AT2 can migrate to the AT2LP with no changes to either the board layout or EEPROM data.

Cypress has published an application note focused on migrating from the AT2 to the AT2LP to help expedite the process. It can be downloaded from the Cypress website

( http://www.cypress.com

) or obtained through a Cypress representative.

Figure 1. Simplified Pinout Selection Flowchart

Read EEPROM

EEPROM

Signature

0x4D4D?

Yes

Set

EZ-USB AT2

(CY7C68300A)

Pinout

Normal Operation

No

Set

EZ-USB AT2LP

(CY7C68300B)

Pinout

Document 001-05809 Rev. *A Page 2 of 42

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Pin Diagrams

The AT2LP is available in different package types to meet a variety of design needs. The CY7C68320C/321C is available in 56-pin

QFN and 100-pin TQFP packages to provide the greatest flexibility for new designs. The CY7C68300C/301C is available in 56-pin

SSOP and QFN package types to ensure backward compatibility with CY7C68300A designs.

Figure 2. 56-pin SSOP Pinout (CY7C68300C/CY7C68301C only)

17

18

19

20

13

14

15

16

21

22

23

24

9

10

11

12

7

8

5

6

3

4

1

2

25

26

27

28

DD13

DD14

DD15

GND

ATAPUEN (GND)

VCC

GND

IORDY

DMARQ

AVCC

XTALOUT

XTALIN

DD12

DD11

DD10

DD9

DD8

(ATA_EN) VBUS_ATA_ENABLE

VCC

RESET#

GND

ARESET#

(VBUS_PWR_VALID) DA2

CS1#

AGND

VCC

DPLUS

DMINUS

GND

VCC

GND

EZ-USB AT2LP

CY7C68300C

CY7C68301C

PWR500# (PU 10K)

CS0#

(DA2) DRVPWRVLD

DA1

DA0

56-pin SSOP

INTRQ

VCC

DMACK#

DIOR#

GND (Reserved)

SCL

SDA

VCC

NOTE: Labels in italics denote pin functionality during CY7C68300A compatibility mode.

DD0

DD1

DD2

DD3

DIOW#

GND

VCC

GND

DD7

DD6

DD5

DD4

40

39

38

37

44

43

42

41

36

35

34

33

48

47

46

45

52

51

50

49

56

55

54

53

32

31

30

29


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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Figure 3. 56-pin QFN Pinout (CY7C68300C/CY7C68301C)

IORDY

DMARQ

AVCC

XTALOUT

XTALIN

AGND

VCC

DPLUS

DMINUS

GND

VCC

GND

(PU10K) PWR500#

GND

10

11

12

8

9

6

7

13

14

1

4

5

2

3

EZ-USB AT2LP

CY7C68300C

CY7C68301C

56-pin QFN

NOTE: Italic labels denote pin functionality during CY7C68300A compatibility mode.

33

32

31

37

36

35

34

30

29

42

41

40

39

38

RESET#

GND

ARESET#

DA2 (VBUS_PWR_VALID)

CS1#

CS0#

DRVPWRVLD (DA2)

DA1

DA0

INTRQ

VCC

DMACK#

DIOR#

DIOW#


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CY7C68320C/CY7C68321C

Figure 4. 56-pin SSOP Pinout (CY7C68320C/CY7C68321C)

15

16

17

18

19

10

11

12

13

14

5

6

7

8

9

3

4

1

2

25

26

27

28

20

21

22

23

24

SCL

SDA

VCC

DD0

DD1

DD2

DD3

DD13

DD14

DD15

GND

GPIO2

VCC

GND

IORDY

DMARQ

AVCC

XTALOUT

XTALIN

AGND

VCC

DPLUS

DMINUS

GND

VCC

GND

GPIO1

GND

EZ-USB AT2LP

CY7C68320C

CY7C68321C

56-pin SSOP

DD12

DD11

DD10

DD9

DD8

VBUS_ATA_ENABLE

VCC

RESET#

GND

ARESET#

DA2

CS1#

CS0#

GPIO0

DA1

DA0

INTRQ

VCC

DMACK#

DIOR#

DIOW#

GND

VCC

GND

DD7

DD6

DD5

DD4

42

41

40

39

38

47

46

45

44

43

52

51

50

49

48

56

55

54

53

32

31

30

29

37

36

35

34

33

Page 5 of 42

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CY7C68320C/CY7C68321C

Figure 5. 56-pin QFN Pinout (CY7C68320C/CY7C68321C)

9

10

11

12

13

14

7

8

5

6

3

4

1

2

IORDY

DMARQ

AVCC

XTALOUT

XTALIN

AGND

VCC

DPLUS

DMINUS

GND

VCC

GND

GPIO1

GND

EZ-USB AT2LP

CY7C68320C

CY7C68321C

56-pin QFN

34

33

32

31

30

29

38

37

36

35

42

41

40

39

RESET#

GND

ARESET#

DA2

CS1#

CS0#

GPIO0

DA1

DA0

INTRQ

VCC

DMACK#

DIOR#

DIOW#


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CY7C68320C/CY7C68321C

Figure 6. 100-pin TQFP Pinout (CY7C68320C/CY7C68321C only)

27

28

29

30

23

24

25

26

19

20

21

22

15

16

17

18

11

12

13

14

7

8

9

10

4

5

6

1

2

3

VCC

DPLUS

DMINUS

GND

VCC

GND

SYSIRQ

GND

GND

GND

PWR500#

GND

NC

SCL

SDA

VCC

GND

IORDY

DMARQ

GND

GND

GND

GND

AVCC

XTALOUT

XTALIN

AGND

NC

NC

NC

EZ-USB AT2LP

100-pin TQFP

DD8

VBUS_ATA_ENABLE

VCC

RESET#

NC

GND

ARESET#

DA2

CS1#

CS0#

DRVPWRVLD

DA1

DA0

INTRQ

VCC

GND

NC

NC

VBUSPWRD

NC

NC

NC

LOWPWR#

NC

DMACK#

DIOR#

DIOW#

VCC

NC

NC

54

53

52

51

58

57

56

55

62

61

60

59

66

65

64

63

70

69

68

67

74

73

72

71

77

76

75

80

79

78


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CY7C68320C/CY7C68321C

Pin Descriptions

The following table lists the pinouts for the 56-pin SSOP, 56-pin

QFN and 100-pin TQFP package options for the AT2LP. Refer

to the “Pin Diagrams” on page 3

for differences between the

68300C/01C and 68320C/321C pinouts for the 56-pin packages. For information on the CY7C68300A pinout, refer to the CY7C68300A data sheet that is found in the ’EZ-USB

AT2’ folder of the CY4615C reference design kit CD.

18

19

20

21

22

13

14

15

16

17

100

TQFP

1

2

7

8

5

6

9

3

4

Table 1. AT2LP Pin Descriptions

Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode)

56

QFN

55

56

1

2

N/A

56

SSOP

6

7

8

9

N/A

Pin Name

V

CC

GND

IORDY

DMARQ

GND

Pin

Type

PWR

GND

I

[1]

I

[1]

Default State at Startup

Input

Input

V

CC

. Connect to 3.3V power source.

Ground.

ATA control. Apply a 1k pull up to 3.3V.

ATA control.

Ground.

Pin Description

3 10 AV

CC

PWR

10

11

12

4

5

6

N/A

11

12

13

N/A

XTALOUT

XTALIN

AGND

NC

Xtal

Xtal

GND

Xtal

Xtal

Analog V

CC

. Connect to V

CC

through the shortest path possible.

24 MHz crystal output. (See “XTALIN, XTALOUT” on page 11 ).

24 MHz crystal input. (See

“XTALIN, XTALOUT” on page 11 ).

Analog ground. Connect to ground with as short a path as possible.

No connect.

23

24

25

26

[3]

7

8

9

10

11

12

N/A

N/A

13

[3]

14

15

16

17

18

19

N/A

N/A

20

V

CC

DPLUS

DMINUS

GND

V

CC

GND

SYSIRQ

GND

PWR500#

(PU 10K)

[2]

PWR

IO

IO

GND

PWR

GND

I

GND

O

Hi-Z

Hi-Z

Input

V

CC


USB D+ signal (See

USB D–signal (See

Ground.

V

CC

Ground.

“DPLUS, DMINUS” on page 11

“DPLUS, DMINUS” on page 11


).

).

USB interrupt request. (See

“SYSIRQ” on page 12

).

Active HIGH. Connect to GND if functionality is not used.

Ground.

27

28

29

14

N/A

15

21

N/A

22

GND (RESERVED)

NC

SCL O

bMaxPower request granted indicator. (See

“PWR500#” on page 14 ). Active LOW.

N/A for CY7C68320C/CY7C68321C 56-pin packages.

Reserved. Tie to GND.

Active for several ms at startup.

No connect.

Clock signal for I

2

C interface. (See “SCL, SDA” on page 11 ). Apply a 2.2k pull up resistor.

Notes

1. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See

“VBUS_ATA_ENABLE” on page 14 .

2. A ‘#’ sign after the pin name indicates that it is active LOW.


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CY7C68320C/CY7C68321C

43

44

45

46

39

40

41

42

35

36

37

38

31

32

33

34

47

48

49

50

51

52

53

54


Note: (Italic pin names denote pin functionality during CY7C68300A compatibility mode) (continued)

100

TQFP

30

56

QFN

16

N/A

56

SSOP

23

N/A

Pin Name

SDA

NC

Pin

Type

IO


Pin Description

Data signal for I

2

C interface. (See “SCL, SDA” on page 11 ).

Apply a 2.2k pull up resistor.

No connect.

55

56

57

58

59

60

61

62

23

24

25

26

N/A

N/A

N/A

22

21

N/A

N/A

N/A

17

18

19

20

27

28

N/A

N/A

29

30

31

N/A

N/A

N/A

N/A

24

25

26

27

28

N/A

N/A

N/A

N/A

N/A

N/A

29

30

31

32

33

34

35

N/A

N/A

36

37

38

N/A

N/A

N/A

N/A

NC

GND

NC

GND

DD4

DD5

DD6

DD7

GND

V

CC

GND

NC

V

CC

DD0

DD1

DD2

DD3

V

CC

GND

V

CC

DIOW#

DIOR#

NC

NC

[2]

DMACK#

LOWPWR#

VBUSPWRD

PWR

IO

[1]

IO

[1]

IO

[1]

IO

[1]

PWR

GND

NC

NC

IO

[1]

IO

[1]

IO

[1]

IO

[1]

GND

PWR

GND

NC

PWR

O/Z

O/Z

O/Z

NC

O

NC

I

[1]

[1]

[1]

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Input

V

CC


ATA data bit 0.

ATA data bit 1.

ATA data bit 2.

ATA data bit 3.

V

CC


Ground.

No connect.

Ground.

No connect.

Ground.

ATA data bit 4.

ATA data bit 5.

ATA data bit 6.

ATA data bit 7. Apply a 1k pull down to GND.

Ground.

V

CC


Ground.

No connect.

Driven HIGH

(CMOS)

V

CC


ATA control.

Driven HIGH

(CMOS)

ATA control.

Driven HIGH

(CMOS)

ATA control.

No connect.

USB suspend indicator. (See

“LOWPWR#” on page 13 ).

No connect.

N/A N/A NC NC

Bus-powered mode selector. (See “VBUSPWRD” on page 14 ).

No connect.

63

64

65

66

67

N/A

32

33

N/A

39

40

GND

V

CC

INTRQ

GND

PWR

I

[1]

Input

Ground.

V

CC


ATA interrupt request.


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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

84

85

86

87

88

89

90

91

92

93

80

81

82

83

94

95

96

97

98

99



100

TQFP

68

69

70

[3]

71

72

73

74

75

76

77

78

79

56

QFN

34

35

36

[3]

37

38

39

40

41

N/A

42

43

44

45

46

47

48

N/A

N/A

N/A

56

SSOP

41

42

43

44

45

46

47

48

N/A

49

Pin Name

DA0

DA1

DRVPWRVLD

(DA2)

CS0#

CS1#

DA2

(VBUS_PWR_VALID)

50 V

CC

51 VBUS_ATA_ENABLE

(ATA_EN)

52

53

54

55

N/A

N/A

N/A

ARESET#

GND

NC

RESET#

DD8

DD9

DD10

DD11

GND

V

CC

NC

Pin

Type

O/Z

[1]

O/Z

[1]

I

O/Z

[1]

O/Z

[1]

O/Z

[1]

O/Z

[1]

GND

NC

I

PWR

I

IO

IO

IO

IO

[1]

[1]

[1]

[1]

PWR

NC


Driven HIGH after 2 ms delay

ATA address.

Pin Description


ATA address.

Input Device presence detect. (See

“DRVPWRVLD” on page 13 ). Configurable logical polarity is controlled by

EEPROM address 0x08. This pin must be pulled HIGH if functionality is not utilized.

Alternate function. Input when the EEPROM configuration byte 8 has bit 7 set to one. The input value is reported through EP1IN (byte 0, bit 0).


ATA chip select.


ATA chip select.


ATA address.

ATA reset.

Ground.

Input

Input

Hi-Z

Hi-Z

Hi-Z

Hi-Z

No connect.

Chip reset (See “RESET#” on page 14 ).

V

CC


VBUS detection (See “VBUS_ATA_ENABLE” on page 14 ).

ATA data bit 8.

ATA data bit 9.

ATA data bit 10.


Ground.

V

CC


No connect.

36

13

54

[3]

[3]

[3]

N/A

49

50

51

52

53

N/A

N/A

56

1

2

3

4

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GND

DD12

DD13

DD14

DD15

GND

IO

GND

IO

[1]

IO

[1]

IO

[1]

IO

[3]

[1]

GND

Hi-Z

Hi-Z

Hi-Z

Hi-Z

General purpose IO pins (See

page 13

Ground.





Ground.

“GPIO Pins” on

). The GPIO pins must be tied to GND if

functionality is not used.


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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C



100

TQFP

100

[3]

56

QFN

54

[3]

56

SSOP

5

Pin Name

ATAPUEN

(NC)

Pin

Type

IO


Pin Description

Bus-powered ATA pull up voltage source (see

“ATAPUEN” on page 14 ).

Alternate function: General purpose input when the

EEPROM configuration byte 8 has bit 7 set to ‘1’. The input value is reported through EP1IN (byte 0, bit 2).

Additional Pin Descriptions

The following sections provide additional pin information.

DPLUS, DMINUS

DPLUS and DMINUS are the USB signaling pins; they must be tied to the D+ and D– pins of the USB connector. Because they operate at high frequencies, the USB signals require special consideration when designing the layout of the PCB.

See “General PCB Layout Recommendations For USB Mass

Storage Designs” on page 39

for PCB layout recommendations.

When RESET# is released, the assertion of the internal pull up on D+ is gated by a combination of the state of the

VBUS_ATA_ENABLE pin, the value of configuration address

0x08 bit 0 (DRVPWRVLD Enable), and the detection of a

non-removable ATA/ATAPI drive on the IDE bus. See Table 2

for a description of this relationship.

Table 2. D+ Pull Up Assertion Dependencies

VBUS_ATA_EN 1 1 1 1 0 0

DRVPWRVLD Enable Bit 1 1 0 0 1 1

ATA/ATAPI Drive Detected Yes No Yes No Yes No

State of D+ pull up 1 1 1 0 0 0 pins must still be connected to pull up resistors. The SCL and

SDA pins are active for several milliseconds at startup.

XTALIN, XTALOUT

The AT2LP requires a 24 MHz (

±

100 ppm) signal to derive internal timing. Typically, a 24 MHz (12 pF, 500

μW, parallel-resonant, fundamental mode) crystal is used, but a 24

MHz square wave (3.3V, 50/50 duty cycle) from another source can also be used. If a crystal is used, connect its pins to XTALIN and XTALOUT, and also through 12 pF capacitors to GND as shown in

Figure 7

. If an alternate clock source is used, apply it to XTALIN and leave XTALOUT unconnected.

Figure 7. XTALIN/XTALOUT Diagram

12pF

24MHz Xtal

12pF

SCL, SDA

The clock and data pins for the I

2

C port must be connected to the configuration EEPROM and to 2.2K pull up resistors tied to V

CC

. If no EEPROM is used in the design, the SCL and SDA

XTALIN XTALOUT


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SYSIRQ

The SYSIRQ pin provides a way for systems to request service from host software by using the USB Interrupt pipe on endpoint

1 (EP1). If the AT2LP has no pending interrupt data to return,

USB interrupt pipe data requests are NAKed. If pending data is available, the AT2LP returns 16 bits of data. This data indicates whether AT2LP is operating in high-speed or full-speed, whether the AT2LP is reporting self-powered or bus-powered operation, and the states of any GPIO pins that are configured as inputs. GPIO pins can be individually set as

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C inputs or outputs, with byte 0x09 of the configuration data. The state of any GPIO pin that is not set as an input is reported as

‘0’ in the EP1 data.

Table 3

gives the bitmap for the data returned on the interrupt

pipe and Figure 8 depicts the latching algorithm incorporated

by the AT2LP.

The SYSIRQ pin must be pulled LOW if HID functionality is used. Refer to

“HID Functions for Button Controls” on page 15

for more details on HID functionality.

Table 3. Interrupt Data Bitmap

7 6 5

EP1 Data Byte 1

4 3 2 1 0 7 6 5

EP1 Data Byte 0

4 3 2 1 0


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Figure 8. SYSIRQ Latching Algorithm

USB Interrupt

Pipe Polled?

Yes

Int_Data = 1?

No

NAK Request

Yes

Return Interrupt Data

Set Int_Data = 0

No No

Yes

SYSIRQ=1?

Yes

Latch State of IO Pins

Set Int_Data = 1

No

Int_Data = 0 and

SYSIRQ=0?

DRVPWRVLD

When this pin is enabled with bit 0 of configuration address

0x08 (DRVPWRVLD Enable), the AT2LP informs the host that a removable device, such as a CF card, is present. The AT2LP uses DRVPWRVLD to detect that the removable device is present. Pin polarity is controlled by bit 1 of configuration address 0x08. When DRVPWRVLD is deasserted, the AT2LP reports a “no media present” status (ASC = 0x3A, ASQ = 0x00) when queried by the host. When the media has been detected again, the AT2LP reports a “media changed” status to the host

(ASC = 0x28, ASQ = 0x00) when queried.

When a removable device is used, it is always considered by the AT2LP to be the IDE master device. Only one removable device may be attached to the AT2LP. If the system only contains a removable device, bit 6 of configuration address

0x08 (Search ATA Bus) must be set to ‘0’ to disable ATA device detection at startup. If a non-removable device is connected in addition to a removable media device, the non-removable device must be configured as IDE slave (device address 1).

GPIO Pins

The GPIO pins allow for a general purpose input and output interface. There are several different interfaces to the GPIO pins:

• Configuration bytes 0x09 and 0x0A contain the default settings for the GPIO pins upon initial AT2LP configuration.


• The host can modify the settings of the GPIO pins during operation. This is done with vendor-specific commands

described in “Programming the EEPROM” on page 33 .

• The status of the GPIO pins is returned on the interrupt

endpoint (EP1) in response to a SYSIRQ. See “SYSIRQ” on page 12

for SYSIRQ details.

LOWPWR#

LOWPWR# is an output pin that is driven to ‘0’ when the

AT2LP is not in suspend. LOWPWR# is placed in Hi-Z when the AT2LP is in a suspend state. This pin only indicates the state of the AT2LP and must not be used to determine the status of the USB host because of variations in the behavior of different hosts.

ATA Interface Pins

The ATA Interface pins must be connected to the corresponding pins on an IDE connector or mass storage device.

To allow sharing of the IDE bus with other master devices, the

AT2LP can place all ATA Interface Pins in a Hi-Z state whenever VBUS_ATA_ENABLE is not asserted. Enabling this feature is done by setting bit 4 of configuration address 0x08 to ‘1’. Otherwise, the ATA bus is driven by the AT2LP to a default inactive state whenever VBUS_ATA_ENABLE is not asserted.

Design practices for signal integrity as outlined in the

ATA/ATAPI-6 specification must be followed with systems that utilize a ribbon cable interconnect between the AT2LP’s ATA

Page 13 of 42

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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C interface and the attached mass storage device, especially if

Ultra DMA Mode is used.

VBUS_ATA_ENABLE

VBUS_ATA_ENABLE is typically used to indicate to the

AT2LP that power is present on VBUS. This pin is polled by the AT2LP at startup and then every 20 ms thereafter. If this pin is ‘0’, the AT2LP releases the pull up on D+ as required by the USB specification.

Also, if bit 4 of configuration address 0x08 is ‘1’, the ATA interface pins are placed in a Hi-Z state when

VBUS_ATA_ENABLE is ‘0’. If bit 4 of configuration address

0x08 is ‘0’, the ATA interface pins are still driven when

VBUS_ATA_ENABLE is ‘0’.

ATAPUEN

This output can be used to control the required host pull up resistors on the ATA interface in a bus-powered design to minimize unnecessary power consumption when the AT2LP is in suspend. ATAPUEN is driven to ‘0’ when the ATA bus is inactive. ATAPUEN is driven to ‘1’ when the ATA bus is active.

ATAPUEN is set to a Hi-Z state along with all other ATA interface pins if VBUS_ATA_ENABLE is deasserted and the

ATA_EN functionality (bit 4 of configuration address 0x08) is enabled (0).

ATAPUEN can also be configured as a GPIO input. See “HID

Functions for Button Controls” on page 15 for more infor-

mation on HID functionality.

PWR500#

The AT2LP asserts PWR500# to indicate that VBUS current may be drawn up to the limit specified by the bMaxPower field of the USB configuration descriptors. If the AT2LP enters a low-power state, PWR500# is deasserted. When normal operation is resumed, PWR500# is restored. The PWR500# pin must never be used to control power sources for the

AT2LP. In the 56-pin package, PWR500# only functions during bus-powered operation.

PWR500# can also be configured as a GPIO input. See

“HID

Functions for Button Controls” on page 15

for more information on HID functionality.

VBUSPWRD

VBUSPWRD is used to indicate self- or bus-powered operation. Some designs require the ability to operate in either self- or bus-powered modes. The VBUSPWRD input pin enables these devices to switch between self-powered and bus-powered modes by changing the contents of the bMaxPower field and the self-powered bit in the reported

configuration descriptors (see Table 4 ).

Note that current USB host drivers do not poll the device for this information, so the effect of this pin is only seen on a USB or power on reset.

Table 4. Behavior of Descriptor Data that is Dependent Upon VBUSPWRD State

Pin bMaxPower

Reported Value bmAttributes bit 6

Reported Value

VBUSPWRD = ‘1’

0xFA

(500 mA)

‘0’

(bus-powered)

VBUSPWRD = ‘0’

0x01

(2 mA)

‘1’

(self-powered)

VBUSPWRD N/A (56-pin)

The value from configuration address 0x34 is used.

‘0’ if bMaxPower

> 0x01

‘1’ if bMaxPower

≤ 0x01

RESET#

Asserting RESET# for 10 ms resets the entire AT2LP. In self-powered designs, this pin is normally tied to V

CC

through a 100k resistor, and to GND through a 0.1

μF capacitor, as

shown in Figure 9 .

Cypress does not recommend an RC reset circuit for bus-powered devices because of the potential for VBUS voltage drop, which may result in a startup time that exceeds the USB limit. Refer to the application note titled EZ-USB

FX2

™/AT2™/SX2™ Reset and Power Considerations, at www.cypress.com

, for more information.

While the AT2LP is in reset, all pins are held at their default startup state.

Figure 9. R/C Reset Circuit for Self-powered Designs

100K

Ω

0.1

μF

RESET#


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HID Functions for Button Controls

Cypress’s CY7C68320C/CY7C68321C has the capability of supporting Human Interface Device (HID) signaling to the host.

If there is a HID descriptor in the configuration data, the GPIO pins that are set as inputs are polled by the AT2LP logic approximately every 17 ms (depending on other internal interrupt routines). If a change is detected in the state of any

HID-enabled GPIO, an HID report is sent through EP1 to the host. The report format for byte 0 and byte 1 are shown in

Table 5 .

The ability to add buttons to a mass storage solution opens new applications for data backup and other device-side notification to the host. The AT2LP Blaster software, found in the

Table 5. HID Data Bitmap

7 6

USB Interrupt Data Byte 1

5 4 3 2 1 0

CY4615C files, provides an easy way to enable and modify the

HID features of the AT2LP.

GPIO pins can be individually set as inputs or outputs, with byte 0x09 of the configuration data, allowing for a mix of HID and general purpose outputs. GPIOs that are not configured as inputs are reported with a value of ‘0’ in the HID data. The

RESERVED bits’ values must be ignored, and Cypress recommends using a bitmask in software to filter out unused HID data.

Note that if using the 56-pin package, the reported GPIO[5:3] values must be ignored because the pins are not actually present.

7 6

USB Interrupt Data Byte 0

5 4 3 2 1 0

Functional Overview

Chip functionally is described in the subsequent sections.

USB Signaling Speed

AT2LP operates at the following two rates defined in the USB

Specification Revision 2.0 dated April 27, 2000:

• Full-speed, with a signaling bit rate of 12 Mbits/sec.

• High-speed, with a signaling bit rate of 480 Mbits/sec.

AT2LP does not operate at the low-speed signaling rate of 1.5

Mbits/sec.

ATA Interface

The ATA/ATAPI port on the AT2LP is compatible with the Infor- mation Technology–AT Attachment with Packet Interface–6

(ATA/ATAPI-6) Specification, T13/1410D Rev 2a. The AT2LP supports both ATAPI packet commands as well as ATA commands (by use of ATA Command Blocks), as outlined in

“ATA Command Block (ATACB)” on page 15 . Refer to the USB

Mass Storage Class (MSC) Bulk Only Transport (BOT) Specification for information on Command Block formatting.

Additionally, the AT2LP translates ATAPI SFF-8070i commands to ATA commands for seamless integration of ATA devices with generic Mass Storage Class BOT drivers.

ATA Command Block (ATACB)

The ATA Command Block (ATACB) functionality provides a means of passing ATA commands and ATA register accesses to the attached device for execution. ATACB commands are transferred in the Command Block Wrapper Command Block

(CBWCB) portion of the Command Block Wrapper (CBW).

The ATACB is distinguished from other command blocks by having the first two bytes of the command block match the bVSCBSignature and bVSCBSubCommand values that are defined in

Table 6

. Only command blocks that have a valid bVSCBSignature and bVSCBSubCommand are interpreted as ATA Command Blocks. All other fields of the CBW and restrictions on the CBWCB remain as defined in the USB Mass

Storage Class Bulk-Only Transport Specification. The ATACB must be 16 bytes in length. The following table and text defines the fields of the ATACB.


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Table 6. ATACB Field Descriptions

Byte

0

Field Name bVSCBSignature

1

2 bVSCBSubCommand bmATACBActionSelect

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Field Description

This field indicates to the CY7C68300C/CY7C68301C that the ATACB contains a vendor-specific command block. This value of this field must match the value in EEPROM address 0x04 for the command to be recognized as a vendor-specific ATACB command.

This field must be set to 0x24 for ATACB commands.

This field controls the execution of the ATACB according to the bitfield values:

Bit 7 IdentifyPacketDevice – This bit indicates that the data phase of the command contains ATAPI (0xA1) or ATA (0xEC) IDENTIFY device data.

Setting IdentifyPacketDevice when the data phase does not contain IDENTIFY device data results in unspecified device behavior.

0 = Data phase does not contain IDENTIFY device data

1 = Data phase contains ATAPI or ATA IDENTIFY device data

Bit 6 UDMACommand – This bit enables supported UDMA device transfers.

Setting this bit when a non-UDMA capable device is attached results in undetermined behavior.

0 = Do not use UDMA device transfers (only use PIO mode)

1 = Use UDMA device transfers

Bit 5 DEVOverride – This bit determines whether the DEV bit value is taken from the value assigned to the LUN during startup or from the ATACB.

0 = The DEV bit is taken from the value assigned to the LUN during startup

1 = The DEV bit is taken from the ATACB field 0x0B, bit 4

Bit 4 DErrorOverride – This bit controls the device error override feature. This bit must not be set during a bmATACBActionSelect TaskFileRead.

0 = Data accesses are halted if a device error is detected

1 = Data accesses are not halted if a device error is detected

Bit 3 PErrorOverride – This bit controls the phase error override feature. This bit must not be set during a bmATACBActionSelect TaskFileRead.

0 = Data accesses are halted if a phase error is detected

1 = Data accesses are not halted if a phase error is detected

Bit 2 PollAltStatOverride – This bit determines whether or not the Alternate

Status register is polled and the BSY bit is used to qualify the ATACB operation.

0 = The AltStat register is polled until BSY=0 before proceeding with the ATACB operation

1 = The ATACB operation is executed without polling the AltStat register.

Bit 1 DeviceSelectionOverride – This bit determines when the device selection is performed in relation to the command register write accesses.

0 = Device selection is performed before command register write accesses

1 = Device selection is performed following command register write accesses

Bit 0 TaskFileRead – This bit determines whether or not the taskfile register data selected in bmATACBRegisterSelect is returned. If this bit is set, the dCBWDataTransferLength field must be set to 8.

0 = Execute ATACB command and data transfer (if any)

1 = Only read taskfile registers selected in bmATACBRegisterSelect and return

0x00h for all others. The format of the 8 bytes of returned data is as follows:

• Address offset 0x00 (0x3F6) – Alternate Status

• Address offset 0x01 (0x1F1) – Features/Error

• Address offset 0x02 (0x1F2) – Sector Count

• Address offset 0x03 (0x1F3) – Sector Number

• Address offset 0x04 (0x1F4) – Cylinder Low

• Address offset 0x05 (0x1F5) – Cylinder High

• Address offset 0x06 (0x1F6) – Device/Head

• Address offset 0x07 (0x1F7) – Command/Status


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Table 6. ATACB Field Descriptions (continued)

Byte

3

Field Name bmATACBRegisterSelect

4

5–12

13–15 bATACBTransferBlockCount bATACBTaskFileWriteData

Reserved

Field Description

This field controls which of the taskfile register read or write accesses occur.

Taskfile read data is always 8 bytes in length, and unselected register data are returned as 0x00. Register accesses occur in sequential order as outlined below (0 to 7):

Bit 0 (0x3F6) Device Control/Alternate Status

Bit 1 (0x1F1) Features/Error

Bit 2 (0x1F2) Sector Count

Bit 3 (0x1F3) Sector Number

Bit 4 (0x1F4) Cylinder Low

Bit 5 (0x1F5) Cylinder High

Bit 6 (0x1F6) Device/Head

Bit 7 (0x1F7) Command/Status

This value indicates the maximum requested block size be in 512-byte increments. This value must be set to the last value used for the ’Sectors per block’ in the SET_MULTIPLE_MODE command. Legal values are 0, 1, 2, 4, 8, 16,

32, 64, and 128 where 0 indicates 256 sectors per block. A command failed status is returned if an illegal value is used in the ATACB.

These bytes contain ATA register data used with ATA command or PIO write operations. Only registers selected in bmATACBRegisterSelect are required to hold valid data when accessed. The registers are as follows.

ATACB Address Offset 0x05 (0x3F6) – Device Control

ATACB Address Offset 0x06 (0x1F1) – Features

ATACB Address Offset 0x07 (0x1F2) – Sector Count

ATACB Address Offset 0x08 (0x1F3) – Sector Number

ATACB Address Offset 0x09 (0x1F4) – Cylinder Low

ATACB Address Offset 0x0A (0x1F5) – Cylinder High

ATACB Address Offset 0x0B (0x1F6) – Device

ATACB Address Offset 0x0C (0x1F7) – Command

These bytes must be set to 0x00 for ATACB commands.


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Operating Modes

The different modes of operation and EEPROM information are presented in the following sections.

Operational Mode Selection Flow

During the power-up sequence, the AT2LP queries the I

2

C bus for an EEPROM. The AT2LP then selects a pinout configuration as shown below, and checks to see if ARESET# is configured for Board Manufacturing Test Mode.

• If no EEPROM is detected, the AT2LP uses the values in the factory-programmable (fused) memory space. See

“Fused Memory Data” on page 19

for more information. This is not a valid mode of operation if no factory programming has been done.

• If an EEPROM signature of 0x4D4D is found, the

CY7C68300C/CY7C68301C uses the same pinout and

EEPROM format as the CY7C68300A (EZ-USB AT2+).

• If an EEPROM signature of 0x534B is found, the AT2LP uses the values stored in the EEPROM to configure the USB descriptors for normal operation.

• If an EEPROM is detected, but an invalid signature is read, the AT2LP defaults into Board Manufacturing Test Mode.

Figure 10. Operational Mode Selection Flow

Check I

2

C Bus

EEPROM

Found?

Yes

Signature

0x534B?

Yes

Set

EZ-USB AT2LP

Pinout

No

Signature

0x4D4D?

Yes

Set

EZ-USB AT2+

(CY7C68300A)

Pinout

No

Load Fused

Memory Data

(AT2LP Pinout)

No

VBUS_ATA_ENABLE

Pin HIGH?

Yes

ARESET#

Pin LOW?

Yes

DD7 Pin Set

HIGH

No

ARESET#

Pin HIGH?

Yes

Board Manufacturing

Test Mode

No

Normal Mass

Storage Mode


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Fused Memory Data

When no EEPROM is detected at startup, the AT2LP enumerates with the VID/PID/DID values that are stored in the fused memory space. These values can be programmed into the AT2LP during chip manufacturing for high volume applications to avoid the need for an external EEPROM in some designs. Contact your local Cypress Semiconductor sales office for more information on this feature.

If no factory programming has been done, the values returned from the fused memory space would all be 0x00, which is not a valid mode of operation. In this case the chip uses the manufacturing mode and return the default descriptors

(VID/PID of 0x4B4/0x6830). An EEPROM must be used with designs that do not use factory-programmed chips in order to identify the device as your company’s product.

Normal Mass Storage Mode

In Normal Mass Storage Mode, the chip behaves as a USB 2.0

to ATA/ATAPI bridge. This includes all typical USB device states (powered, configured, etc.). The USB descriptors are returned according to the values stored in the external

EEPROM or fused memory space. A unique serial number is required for Mass Storage Class Bulk-Only Transport compliance, which is one reason why an EEPROM or factory-programmed part is needed.

Board Manufacturing Test Mode

In Board Manufacturing Test Mode the AT2LP behaves as a

USB 2.0 device but the ATA/ATAPI interface is not fully active.

This mode must not be used for mass storage operation in a finished design. In this mode, the AT2LP allows for reading from and writing to the EEPROM, and for board level testing, through vendor specific ATAPI commands utilizing the CBW

Command Block as described in the USB Mass Storage Class

Bulk-Only Transport Specification. There is a vendor-specific

Table 7. Command Block Wrapper

0–3

4–7

Offset

8–11 (08h–0Bh)

12 (0Ch)

13 (0Dh)

14 (0Eh)

15–30 (0Fh1Eh)

7

Dir

6

Obsolete

Reserved (0)

Reserved (0)

5

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

ATAPI command for EEPROM accesses (CfgCB) and one for board level testing (MfgCB), as described in the following sections.

There is a convenient method available for starting the AT2LP in Board Manufacturing Test Mode to allow reprogramming of

EEPROMs without a mass storage device attached. If the ATA

Reset (ARESET#) line is LOW on power up, the AT2LP enters

Board Manufacturing Test Mode. It is recommended that a 10k resistor be used to pull ARESET# to LOW. An easy way to pull the ARESET# line LOW is to short pins 1 and 3 on the 40-pin

ATA connector with a 10k resistor, that ties the ARESET# line to the required pull down on DD7.

CfgCB

The cfg_load and cfg_read vendor-specific commands are passed down through the bulk pipe in the CBWCB portion of the CBW. The format of this CfgCB is shown below. Byte 0 is a vendor-specific command designator whose value is configurable and set in the configuration data (address 0x04). Byte 1 must be set to 0x26 to identify it as a CfgCB command. Byte2 is reserved and must be set to zero. Byte 3 is used to determine the memory source to write/read. For the AT2LP, this byte must be set to 0x02, indicating the EEPROM is present. Bytes 4 and 5 are used to determine the start address, which must always be 0x0000. Bytes 6 through 15 are reserved and must be set to zero.

The data transferred to the EEPROM must be in the format

specified in Table 11

of this data sheet. Maximum data transfer size is 255 bytes.

The data transfer length is determined by the CBW Data

Transfer Length specified in bytes 8 through 11

(dCBWDataTransferLength) of the CBW (refer to

Table 7

).

The type/direction of the command is determined by the direction bit specified in byte 12, bit 7 (bmCBWFlags) of the

CBW (refer to Table 7 ).

Bits

4 3

DCBWSignature dCBWTag dCBWDataTransferLength bwCBWFLAGS

Reserved (0)

2 bCBWLUN bCBWCBLength

CBWCB (CfgCB or MfgCB)

1 0


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Table 8. Example CfgCB

Offset CfgCB Byte Descriptions

2

3

0

1 bVSCBSignature (set in configuration bytes) bVSCBSubCommand (must be 0x26)

Reserved (must be set to zero)

Data Source (must be set to 0x02)

4

5

Start Address (LSB) (must be set to zero)

Start Address (MSB) (must be set to zero)

6–15 Reserved (must be set to zero)

MfgCB

The mfg_load and mfg_read vendor-specific commands are passed down through the bulk pipe in the CBWCB portion of the CBW. The format of this MfgCB is shown as follows. Byte0 is a vendor-specific command designator whose value is configurable and set in the AT2LP configuration data. Byte 1 must be 0x27 to identify a MfgCB. Bytes 2 through 15 are reserved and must be set to zero.

The data transfer length is determined by the CBW Data

Transfer Length specified in bytes 8 through 11

(dCBWDataTransferLength) of the CBW. The type and direction of the command is determined by the direction bit specified in byte 12, bit 7 (bmCBWFlags) of the CBW.

Table 9. Example MfgCB

Offset MfgCB Byte Description Bits

7 6 5 4 3 2 1 0

0 0 bVSCBSignature

(set in configuration bytes)

1 1 bVSCBSubCommand

(hardcoded 0x27)

0 0 1 0 0 1 0 0

0 0 1 0 0 1 1 1

2–15 2–15 Reserved (must be zero) 0 0 0 0 0 0 0 0

Mfg_load

During a Mfg_load, the AT2LP enters into Manufacturing Test

Mode. Manufacturing Test Mode is provided as a means to implement board or system level interconnect tests. During

Manufacturing Test Mode operation, all outputs not directly associated with USB operation are controllable. Normal control of the output pins are disabled. Control of the select

AT2LP IO pins and their tri-state controls are mapped to the

ATAPI data packet associated with this request. (See

Table 10

for an explanation of the required Mfg_load data format.) Any data length can be specified, but only bytes 0 through 3 are mapped to pins, so a length of 4 bytes is recommended. To exit Manufacturing Test Mode, a hard reset (toggle RESET#) is required.

0

0

0

0

0

0

7

0

6

0

0

0

0

0

0

0

5

1

1

0

0

0

0

0

0

0

0

0

0

0

4

0

Bits

3

0

0

0

0

0

0

0

2

1

1

0

0

0

0

0

1

0

1

0

1

0

0

0

Mfg_read

This USB request returns a ’snapshot’ of select AT2LP input pins. AT2LP input pins not directly associated with USB operation can be sampled at any time during Manufacturing

Test Mode operation. See

Table 10 for an explanation of the

Mfg_read data format. Any data length can be specified, but only bytes 0 through 3 contain usable information, so a length of 4 bytes is recommended.

0

0

0

0

0

0

0

0

Table 10.Mfg_read and Mfg_load Data Format

Byte

0

1

2

3

1

0

7:0

7:0

3

2

5

4

3

2:1

0

7

Bits Read/Load

7 R/L ARESET#

Function

6

5:4

R

R/L

DA2

CS#[1:0]

R/L

R/L

R

L

DRVPWRVLD

DA[1:0]

INTRQ

DD[15:0] High-Z Status

0 = Hi-Z all DD pins

1 = Drive DD pins

6 R

R

R

R

R/L

R/L

R/L

R/L

R/L

MFG_SEL

0 = Mass Storage Mode

1 = Manufacturing Mode

VBUS_ATA_ENABLE

DMARQ

IORDY

DMACK#

DIOR#

DIOW#

DD[7:0]

DD[15:8]


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EEPROM Organization

The contents of the recommended 256-byte (2048-bit) I

2

C

EEPROM are arranged as follows. In Table 11

, the column labeled ‘Required Contents’ contains the values that must be used for proper operation of the AT2LP. The column labeled

‘Variable Contents’ contains suggested entries and values that may vary (like string lengths) according to the EEPROM data.

Some values, such as the Vendor ID, Product ID and device serial number, must be customized to meet USB compliance.

The ‘AT2LP Blaster’ tool in the CY4615C kit can be used to edit and program these values into an AT2LP-based product

(refer to

Figure 11

). The ‘AT2LP Primer’ tool can be used to program AT2LP-based products in a manufacturing environment and provides for serial number randomization.

See

“Board Manufacturing Test Mode” on page 19

The address pins on the serial EEPROM must be set such that the EEPROM is at physical address 2 (A0 = 0, A1 = 1, A2 = 0) or address 4 (A0 = 0, A1 = 0, A2 = 1) for EEPROM devices that are internally byte-addressed memories. It is recommended that the address pins be set this way even on

EEPROMs that may indicate that the address pins are internal no-connects.

for details on how to use vendor-specific ATAPI commands to read and program the EEPROM.

Figure 11. Snapshot of ‘AT2LP Blaster’ Utility


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CY7C68320C/CY7C68321C

Table 11.Configuration Data Organization

Byte

Address

Configuration

Item Name

Configuration

Item Description

Required

Contents

Variable

Contents

Note Devices running in Backward Compatibility (CY7C68300A) Mode must use the CY7C68300A EEPROM organization, and not the format shown in this document. Refer to the CY7C68300A data sheet for the CY7C68300A EEPROM format.

AT2LP Configuration

0x00 EEPROM signature byte 0 0x53

0x01

0x02

EEPROM signature byte 1

APM Value

I

2

C EEPROM signature byte 0. This byte must be 0x53 for proper AT2LP pin configuration.

I

2

C EEPROM signature byte 1. This byte must be 0x4B for proper AT2LP pin configuration.

ATA Device Automatic Power Management Value. If an attached ATA device supports APM and this field contains other than 0x00, the AT2LP issues a SET_FEATURES command to Enable APM with this value during the drive initialization process. Setting APM Value to 0x00 disables this functionality. This value is ignored with ATAPI devices.

0x4B

0x00

0x03

0x04

Reserved bVSCBSignature Value

Must be set to 0x00.

Value in the first byte of the CBW CB field that designates that the CB is to be decoded as vendor specific ATA commands instead of the ATAPI command block. See

“Functional Overview” on page 15 for more detail on how

this byte is used.

0x00

0x24

0x05 Reserved

Enable mode page 8

0x07

Disable wait for INTRQ

BUSY Bit Delay

Short Packet Before Stall

Bit 5

Enable the write caching mode page (page 8). If this page is enabled, Windows disables write caching by default, which limits write performance.

0= Disable mode page 8.

1= Enable mode page 8.

Bit 4

Poll status register rather than waiting for INTRQ. Setting this bit to 1 improves USB BOT test results but may introduce compatibility problems with some devices.

0 = Wait for INTRQ.

1 = Poll status register instead of using INTRQ.

Bit 3

Enable a delay of up to 120 ms at each read of the DRQ bit where the device data length does not match the host data length. This allows the CY7C68300C/CY7C68301C to work with most devices that incorrectly clear the BUSY bit before a valid status is present.

0 = No BUSY bit delay.

1 = Use BUSY bit delay.

Bit 2

Determines if a short packet is sent before the STALL of an

IN endpoint. The USB Mass Storage Class Bulk-Only Speci-

fication allows a device to send a short or zero-length IN packet before returning a STALL handshake for certain cases. Certain host controller drivers may require a short packet before STALL.

0 = Do not force a short packet before STALL.

1 = Force a short packet before STALL.


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Table 11.Configuration Data Organization (continued)

Byte

Address

0x06

0x07

Configuration

Item Name

SRST Enable

Skip Pin Reset

ATA UDMA Enable

ATAPI UDMA Enable

UDMA Modes

Reserved

Multi-word DMA mode

PIO Modes

Configuration


Bit 1

Determines if the AT2LP is to do an SRST reset during drive initialization. At least one reset must be enabled. Do not set

SRST to 0 and Skip Pin Reset to 1 at the same time.

0 = Do not perform SRST during initialization.

1 = Perform SRST during initialization.

Required

Contents

Bit 0

Skip ARESET# assertion. When this bit is set, the AT2LP bypasses ARESET# during any initialization other than power up. Do not set SRST Enable to 0 and Skip Pin Reset to 1 at the same time.

0 = Allow ARESET# assertion for all device resets.

1 = Disable ARESET# assertion except for chip reset cycles.

Bit 7

Enable Ultra DMA data transfer support for ATA devices. If enabled, and if the ATA device reports UDMA support for the indicated modes, the AT2LP uses UDMA data transfers at the highest negotiated rate possible.

0 = Disable ATA device UDMA support.

1 = Enable ATA device UDMA support.

Bit 6

Enable Ultra DMA data transfer support for ATAPI devices.

If enabled, and if the ATAPI device reports UDMA support for the indicated modes, the AT2LP uses UDMA data transfers at the highest negotiated rate possible.

0 = Disable ATAPI device UDMA support.

1 = Enable ATAPI device UDMA support.

Bits 5:0

These bits select which UDMA modes are enabled. The

AT2LP operates in the highest enabled UDMA mode supported by the device. The AT2LP supports UDMA modes

2, 3, and 4 only.

Bit 5 = Reserved. Must be set to 0.

Bit 4 = Enable UDMA mode 4.





Bits 7:3

Must be set to 0.

Bit 2

This bit enables multi-word DMA support. If this bit is set and the drive supports it, multi-word DMA is used.

Bits 1:0

These bits select which PIO modes are enabled. Setting to

‘1’ enables use of that mode with the attached drive, if the drive supports it. Multiple bits may be set. The AT2LP operates in the highest enabled PIO mode supported by the device. The AT2LP supports PIO modes 0, 3, and 4 only.

PIO mode 0 is always enabled and has no corresponding configuration bit.

Bit 1 = Enable PIO mode 4.

Bit 0 = Enable PIO mode 3.

Variable

Contents

0xD4

0x07


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Byte

Address

0x08

0x09

Configuration

Item Name

BUTTON_MODE

SEARCH_ATA_BUS

BIG_PACKAGE

ATA_EN

Reserved

Reserved

Drive Power Valid Polarity

Drive Power Valid Enable

Reserved

General Purpose IO Pin

Output Enable

Configuration


Bit 7

Button mode (100-pin package only). Sets ATAPUEN,

PWR500# and DRVPWRVLD to become button inputs returned on bits 2, 1, and 0 of EP1IN. This bit must be set to

‘0’ if the 56-pin packages are used.

0 = Disable button mode.

1 = Enable button mode.

Required

Contents

Bit 6

Search ATA bus after RESET to detect non-removable ATA and ATAPI devices. Systems with only a removable device

(like CF readers) must set this bit to ‘0’. Systems with at least one non-removable device must set this bit to ‘1’.

0 = Do not search for ATA devices.

1 = Search for ATA devices.

Bit 5

Selects the 100- or 56-pin package pinout configuration.

Using the wrong pinout may result in unpredictable behavior.

0 = Use 56-pin package pinout.

1 = Use 100-pin package pinout.

Bit 4

Drive ATA bus when AT2LP is in suspend. For designs in which the ATA bus is shared between the AT2LP and another ATA master (such as an MP3 player), the AT2LP can place the ATA interface pins in a Hi-Z state when it enters suspend. For designs that do not share the ATA bus, the ATA signals must be driven while the AT2LP is in suspend to avoid floating signals.

0 = Drive ATA signals when AT2LP is in suspend.

1 = Set ATA signals to Hi-Z when AT2LP is in suspend.

Bit 3

Reserved. This bit must be set to ‘0’.

Bit 2

Reserved. This bit must be set to ‘0’

Bit 1

Configure the logical polarity of the DRVPWRVLD input pin.

0 = Active LOW (‘connector ground’ indication)

1 = Active HIGH (power indication from device)

Bit 0

Enable the DRVPWRVLD pin. When this pin is enabled, the

AT2LP enumerates a removable ATA device, like Compact-

Flash or MicroDrive, as the IDE master device. Enabling this pin also affects other pins related to removable device operation.

0 = Disable removable ATA device support.

1 = Enable removable ATA device support.

Bits 7:6

Reserved. Must be set to zero.

Bits 5:0

GPIO[5:0] Input and output control. GPIOs can be individually set as inputs or outputs using these bits.

0 = Hi-Z (pin is an input). The state of the signal connected to GPIO input pins is reported in the SYSIRQ or HID data.

1 = Output enabled (pin is an output). The state of GPIO output pins is controlled by the value in address 0x0A.

Variable

Contents

0x78

0x00


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Byte

Address

0x0A

0x0B

0x0C

0x0D

Configuration

Reserved

Item Name

GPIO Output Pin State

LUN0 Identify String

LUN1 Identify String

Delay After Reset

Configuration


Bits 7:6

Reserved. Must be set to zero.

Bits 5:0

These bits select the value driven on the GPIO pins that are configured as outputs in configuration address 0x09.

0 = Drive the GPIO pin LOW

1 = Drive the GPIO pin HIGH

Required

Contents

This byte is a pointer to the start of a 24 byte ASCII

(non-Unicode) string in the EEPROM that is used as the

LUN0 device identifier. This string is used by many operating systems as the user-visible name for the drive. If this byte is

0x00, the Identify Device data from the drive is used instead.

This byte is a pointer to the start of a 24 byte ASCII

(non-Unicode) string in the EEPROM that is used as the

LUN1 device identifier. This string is used by many operating systems as the user-visible name for the drive. If this byte is

0x00, the Identify Device data from the drive is used instead.

Number of 20-ms ticks to wait between AT2LP startup or reset, and the first attempt to access any drives.

0x0E Reserved

Bus-Powered Flag

CF UDMA Enable

Fixed Number of Logical

Search ATA on VBUS

Must be set to zero.

Bit 4

Enable bus-powered HDD support. This bit enables the use of DRVPWRVLD features without reporting the LUN0 device as removable media.

0 = LUN0 is removable media or DRVPWRVLD is disabled

1 = LUN0 device is bus-powered and non-removable

Bit 3

Enable UDMA transfers for removable devices. Some CF devices interfere with UDMA transfers when more than one drive is connected to the ATA bus.

0 = Do not use UDMA transfers with removable devices

(UDMA signals are not connected to the CF pins).

1 = Allow UDMA transfers to be used with removable devices (UDMA signals are connected to the CF pins).

Bits 2:1

Assume the presence of devices and do not perform a search of the ATA bus to discover the number of LUNs.

00 = Search ATA bus and determine number of LUNs

01 = Assume only LUN0 present; no ATA bus search

10 = Assume LUN0 and LUN1 present; no ATA bus search

11 = Assume LUN0 and LUN1 present; no ATA bus search

Bit 0

Search for ATA devices when VBUS returns. If this bit is set, the ATA bus is searched for ATA devices every time

VBUS_ATA_ENABLE is asserted. This feature allows the

AT2LP to be used in designs where the drive may be physically removed (like docking stations or port replicators).

0 = Search ATA bus on VBUS_ATA_ENABLE assertion

1 = No ATA bus search on VBUS_ATA_ENABLE assertion

Must be set to 0x00 0x00 0x0F Reserved

Device Descriptor

0x10

0x11 bLength bDescriptor Type

Length of device descriptor in bytes

Descriptor type.

0x12

0x01

Variable

Contents

0x00

0x00

0x00

0x00

0x00


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Byte

Address

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

Configuration

Item Name bcdUSB (LSB) bcdUSB (MSB) bDeviceClass bDeviceProtocol bMaxPacketSize0 idVendor (LSB) idVendor (MSB) idProduct (LSB) idProduct (MSB) bcdDevice (LSB)

Configuration


USB Specification release number in BCD

Device class

Device protocol

USB packet size supported for default pipe

Vendor ID. Cypress’ Vendor ID may only be used for evaluation purposes, and not in released products.

Required

Contents

0x00

0x02

0x00

0x00

0x00

0x40

Product ID

0x1D

0x1E

0x1F

0x20

0x21 bcdDevice (MSB) iManufacturer iProduct iSerialNumber bNumConfigurations

Device release number in BCD LSB (product release number)

Device release number in BCD MSB (silicon release number)

Index to manufacturer string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist.

Index to product string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist.

Index to serial number string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist. The USB Mass Storage Class Bulk-Only

Transport Specification requires a unique serial number (in upper case, hexadecimal characters) for each device.

Number of configurations supported

1 for mass storage: 2 for HID: 3 for CSM

Device Qualifier

0x22 bLength

0x23

0x24

0x25

0x26 bcdUSB (LSB) bcdUSB (MSB)

0x27

0x28

0x29

0x2A bDeviceSubClass bMaxPacketSize0 bNumConfigurations

0x2B bReserved

Configuration Descriptor

0x2C

0x2D

0x2E

0x2F bDescriptorType bTotalLength (LSB) bTotalLength (MSB)

0x30

0x31 bNumInterfaces bConfiguration Value

Length of device descriptor in bytes



Device subclass

USB packet size supported for default pipe

Number of configurations supported

Reserved for future use. Must be set to zero

Descriptor type

Number of bytes returned in this configuration. This includes the configuration descriptor plus all the interface and endpoint descriptors.

Number of interfaces supported

The value to use as an argument to Set Configuration to select the configuration. This value must be set to 0x01.

0x09

0x02

0x01

0x0A

0x06

0x00

0x02

0x00

0x00

0x00

0x40

0x01

0x00

Variable

Contents

Your

Vendor ID

Your

Product ID

Your release number

0x53

0x69

0x75

0x03

0x20

0x00

0x01


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Byte

Address

0x32

0x33

0x34

Configuration

Item Name iConfiguration bmAttributes

bMaxPower

Configuration


Index to the configuration string. This entry must equal half of the address value where the string starts, or 0x00 if the string does not exist.

Required

Contents

Device attributes for this configuration

Bit 7 Reserved. Must be set to 1

Bit 6 Self-powered. See

Table 4

for reported value

Bit 5 Remote wakeup. Must be set to 0

Bits 4–0 Reserved. Must be set to 0

Maximum power consumption for this configuration. Units used are mA*2 (i.e., 0x31 = 98 mA, 0xF9 = 498 mA). The value entered here is only used by the 56-pin packages and affect the reported value of bit 6 of address 0x33 in that case.

See Table 4 on page 14 for a description of what value is

reported to the host by the AT2LP.

Interface and Endpoint Descriptors

Interface Descriptor

0x35

0x36 bLength bDescriptorType

0x37

0x38

0x39

0x3A bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass

0x3B

0x3C

0x3D bInterfaceSubClass bInterfaceProtocol iInterface

Length of interface descriptor in bytes

Descriptor type

Interface number

Alternate setting

Number of endpoints

Interface class

Interface subclass

Interface protocol

Index to first interface string. This entry must equal half of the address value where the string starts or 0x00 if the string does not exist.

0x09

0x04

0x00

0x00

0x08

0x50

USB Bulk Out Endpoint

0x3E bLength

0x3F

0x40 bDescriptorType bEndpointAddress

0x41

0x42

0x43

0x44 bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval

USB Bulk In Endpoint

0x45 bLength

0x46


0x48

0x49

0x4A

0x4B bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval

(Optional) HID Interface Descriptor

0x4C bLength

0x4D

0x4E bDescriptorTypes bInterfaceNumber

Length of this descriptor in bytes

Endpoint descriptor type

This is an Out endpoint, endpoint number 2.

This is a bulk endpoint.

Max data transfer size. To be set by speed (Full-speed

0x0040; High-speed 0x0200)

High-speed interval for polling (maximum NAK rate)



This is an In endpoint, endpoint number 6

This is a bulk endpoint

Max data transfer size. Automatically set by AT2 (Full-speed

0x0040; High-speed 0x0200)

High-speed interval for polling (maximum NAK rate)

Length of HID interface descriptor

Interface descriptor type

Number of interfaces (2)

0x07

0x05

0x02

0x02

0x00

0x07

0x05

0x86

0x02

0x00

Variable

Contents

0x00

0xC0

0x01

0x02

0x06

0x00

0x00

0x02

0x00

0x02

0x09

0x04

0x02


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Byte

Address

0x4F

0x50

0x51

0x52

0x53

0x54

Configuration

Item Name bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceSubSubClass iInterface

USB Interrupt In Endpoint

0x5E bLength

0x5F


0x61

0x62

0x63

0x64 bmAttributes wMaxPacketSize (LSB) wMaxPacketSize (MSB) bInterval

Alternate setting

Configuration


Number of endpoints used by this interface

Class code

Sub class

Sub Sub class

Index of string descriptor



This is an In endpoint, endpoint number 1

This is an interrupt endpoint

Max data transfer size

Interval for polling (max. NAK rate)

(Optional) HID Descriptor

0x55 bLength

0x56

0x57 bDescriptorType bcdHID (LSB)

0x58

0x59

0x5A

0x5B bcdHID (MSB) bCountryCode bNumDescriptors bDescriptorType

Length of HID descriptor

Descriptor Type HID

HID Class Specification release number (1.10)

Country Code

Number of class descriptors (1 report descriptor)

Descriptor Type

Length of HID report descriptor 0x5C

0x5D wDescriptorLength (LSB) wDescriptorLength (MSB)

Terminator Descriptors

0x65 Terminator

(Optional) HID Report Descriptor

0x66 Usage_Page

0x67

0x68

Usage 0x69

0x6A

0x6B

0x6C

Vendor defined

Vendor defined

Collection Application

Vendor defined 0x6D

0x6E

Usage

Input Report

0x6F Usage

0x70

0x71

0x72

0x73

0x74

Logical_Minimum

Logical_Maximum

Vendor defined

–128

127

Required

Contents

Variable

Contents

0x00

0x01

0x03

0x00

0x00

0x00

0x07

0x05

0x81

0x03

0x02

0x00

0x00

0x10

0x09

0x21

0x10

0x01

0x00

0x01

0x22

0x22

0x00

0x06

0xA0

0xFF

0x09

0xA5

0xA1

0x01

0x09

0xA6

0x09

0xA7

0x15

0x80

0x25

0x7F


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Byte

Address

0x75

0x76

0x77

0x78

0x79

0x7A

Configuration

Item Name

Report_Size

Report_Count

Input

Output Report

0x7B Usage

0x7C

0x7D Logical_Minimum

0x7E

0x7F

0x80

0x81

Logical_Maximum

Report_Size Report Size 8 bits

0x82

0x83

0x84

0x85

Report_Count Report Count 2 fields

0x86

0x87 End Collection

(optional) Standard Content Security Interface Descriptor

0x88

0x89

Output bLength

Output (Data, Variable, Absolute)

Byte length of this descriptor

Interface Descriptor type

0x8A

0x8B bDescriptorType bInterfaceNumber bAlternateSetting

Number of interface

Value used to select an alternate setting for the interface identified in prior field

Number of endpoints used by this interface (excluding endpoint 0) that are CSM dependent

0x8C

0x8D

0x8E

0x8F bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol

0x90 iInterface

Channel Descriptor

0x91

0x92

0x93 bLength bDescriptorType bChannelID

0x94 bmAttributes

8 bits

2 fields

Configuration


Input (Data, Variable, Absolute)

Usage - vendor defined

Logical Minimum (–128)

Logical Maximum (127)

Must be set to zero

Must be set to zero

Index of a string descriptor that describes this Interface


Channel descriptor type

Number of the channel, must be a zero based value that is unique across the device

Bits7:5

Reserved. Must be set to zero

Bits 4:0

Required

Contents

Variable

Contents

0x75

0x08

0x95

0x02

0x81

0x02

0x09

0x0D

0x02

0x00

0x02

0x0D

0x00

0x00

0x00

0x09

0x22

0x00

0x01

0x09

0xA9

0x15

0x80

0x25

0x7F

0x75

0x08

0x95

0x02

0x91

0x02

0xC0


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0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

Byte

Address

0x95

Configuration

Item Name bRecipient

Configuration


Identifier of the target recipient

If Recipient type field of bmAttributes = 1 then bRecipient field is the bInterfaceNumber

If Recipient type field of bmAttributes = 2 then bRecipient field is an endpoint address, where:

D7: Direction (0 = Out, 1 = IN)

D6...D4: Reserved and set to zero

D3...D0: Endpoint number

0x96 bRecipientAlt alternate setting for the interface to which this channel applies

Recipient Logical Unit 0x97

0x98 bRecipientLogicalUnit bMethod Index of a class-specific CSM descriptor That describes one of the Content Security Methods (CSM) offered by the device

CSM Variant descriptor 0x99 bMethodVariant

CSM Descriptor

0x9A

0x9B

0x9C bLength bDescriptorType bMethodID

Byte length of this descriptor

CSM Descriptor type

0x9D iCSMDescriptor

0x9E

0x9F bcdVersion (LSB) bcsVersion (MSB)

0xA0 Terminator

USB String Descriptor–Index 0 (LANGID)

Index of a class-specific CSM descriptor that describes on of the Content Security Methods offered by the device

Index of string descriptor that describes the Content Security

Method

CSM Descriptor Version number

Required

Contents

0x00

0xA1

0xA2

0xA3

0xA4

USB String Descriptor–Manufacturer

0xA5 bLength

0xA6

0xA7 bDescriptorType bString

0xB0

0xB1

0xB2

0xB3

0xB4 bLength bDescriptorType

LANGID (LSB)

LANGID (MSB) bString bString bString bString bString bString bString bString bString bString bString bString bString

LANGID string descriptor length in bytes

Descriptor type

Language supported. The CY7C68300B supports one

LANGID value.

String descriptor length in bytes (including bLength)

Descriptor type

Unicode character LSB

Unicode character MSB













0x04

0x03

0x03

Variable

Contents

0x00

0x00

0x00

0x01

0x00

0x06

0x23

0x01

0x00

0x10

0x02

0x09

0x04

0x2C

’C’ 0x43

0x00

’y’ 0x79

0x00

’p’ 0x70

0x00

’r’ 0x72

0x00

’e’ 0x65

0x00

’s’ 0x73

0x00

’s’ 0x73

0x00


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0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

Byte

Address

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0 bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString bString

Configuration

Item Name

USB String Descriptor–Product

0xD1 bLength

0xD2

0xD3

0xD4

0xD5 bDescriptorType bString bString bString bString bString bString bString bString bString bString bString bString

Configuration






























String descriptor length in bytes (including bLength)

Descriptor type.













0x03

0x2C

Required

Contents

’n’ 0x6E

0x00

’d’ 0x64

0x00

’u’ 0x75

0x00

’c’ 0x63

0x00

’t’ 0x74

0x00

’o’ 0x6F

0x00

’r’ 0x72

0x00

Variable

Contents

’ ’ 0x20

0x00

’S’ 0x53

0x00

’e’ 0x65

0x00

’m’ 0x6D

0x00

’i’ 0x69

0x00

’c’ 0x63

0x00

’o’ 0x6F

0x00

’U’ 0x55

0x00

’S’ 0x53

0x00

’B’ 0x42

0x00

’2’ 0x32

0x00

’.’ 0x2E

0x00

’0’ 0x30

0x00


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0XEB

0XEC

0XED

0XEE

0XEF

0XF0

0xF1

0xF2

Byte

Address

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8 bString bString bString bString bString bString bString bString bString bString

Configuration

Item Name

Configuration












Required

Contents

Variable

Contents

’ ’ 0x20

0x00

’D’ 0x53

0x00

’i’ 0x74

0x00

’s’ 0x6F

0x00

’k’ 0x72

0x00

USB String Descriptor–Serial Number (Note: The USB Mass Storage Class specification requires a unique serial number in each device. If you do not provide a unique serial number, the operating system may crash. The serial number must be at least

12 characters, but some USB hosts only use the least significant 12 characters of the serial number as a unique identifier.

0xE9

0xEA bLength bDescriptor Type

String descriptor length in bytes (including bLength).

Descriptor type.

0x03

0x22 bString bString bString bString bString bString bString bString









’1’ 0x31

0x00

’2’ 0x32

0x00

’3’ 0x33

0x00

’4’ 0x34

0x00

0xF3

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

0xFA bString bString bString bString bString bString bString bString









’5’ 0x35

0x00

’6’ 0x36

0x00

’7’ 0x37

0x00

’8’ 0x38

0x00

0xFB

0xFC

0xFD

0xFE bString bString bString bString





’9’ 0x39

0x00

’0’ 0x30

0x00

0xFF

0Xxx

0Xxx

0Xxx bString bString bString bString





’A’ 0x41

0x00

’B’ 0x42

0x00

Identify Device String (Note: This is not a Unicode string. It is the ASCII string returned by the device in the Identify Device information. It is a fixed length (24 bytes). Changing this string may cause CD authoring software to incorrectly identify the device.)

0Xxx

0Xxx

0Xxx

Device name byte 1

Device name byte 2

Device name byte 3

ASCII Character

ASCII Character

ASCII Character

’C’ 0x43

’y’ 0x79

’p’ 0x70


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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C


0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

Byte

Address

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

0Xxx

Configuration

Item Name

Device name byte 4

Device name byte 5

Device name byte 6

Device name byte 7

Device name byte 8

Device name byte 9

Device name byte 10

Device name byte 11

Device name byte 12

Device name byte 13

Device name byte 14

Device name byte 15

Device name byte 16

Device name byte 17

Device name byte 18

Device name byte 19

Device name byte 20

Device name byte 21

Device name byte 22

Device name byte 23

Device name byte 24

Unused ROM Space

Configuration


ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

ASCII Character

Amount of unused ROM space varies depending on strings.

Required

Contents

Variable

Contents

’r’ 0x72

’e’ 0x65

’s’ 0x73

’s’ 0x73

’ ’ 0x20

’C’ 0x43

’u’ 0x75

’s’ 0x73

’t’ 0x74

’o’ 0x6f

’m’ 0x6d

’ ’ 0x20

’N’ 0x4e

’a’ 0x61

’m’ 0x6d

’e’ 0x65

’ ’ 0x20

’L’ 0x4c

’U’ 0x55

’N’ 0x4e

’0’ 0x30

0xFF

Note: More than 0X100 bytes of configuration are shown for example only. The AT2LP only supports addresses up to 0xFF.

Programming the EEPROM

There are three methods of programming the EEPROM:

• Stand-alone EEPROM programmer

• Vendor-specific USB commands, listed in

Table 12

• In-system programming (for example, bed-of-nails tester)

Any vendor-specific USB write request to the Serial ROM device configuration space simultaneously update internal configuration register values as well. If the I

2

C device is programmed without vendor specific USB commands, the AT2LP must be synchronously reset (toggle RESET#) before configuration data is reloaded.

The AT2LP supports a subset of the ’slow mode’ specification (100 KHz) required for 24LCXXB EEPROM family device support.

Features such as ’Multi-Master,’ ’Clock Synchronization’ (the SCL pin is output only), ’10-bit addressing,’ and ’CBUS device support’ are not supported. Vendor-specific USB commands allow the AT2LP to address up to 256 bytes of EEPROM data.

LOAD_CONFIG_DATA

This request enables writes to the AT2LP’s configuration data space. The wIndex field specifies the starting address and the wLength field denotes the data length in bytes.


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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

Legal values for wValue are as follows:

• 0x0000 Internal Config bytes, address range 0x2 – 0xF

• 0x0002 External I

2

C memory device

Internal Config byte writes must be constrained to addresses 0x2 through 0xF, as shown in Table 12

. Attempts to write outside this address space result in undefined operation. Internal Config byte writes only overwrite AT2LP Configuration Byte registers, the original data source (I

2

C memory device) remains unchanged.

Table 12.EEPROM-related Vendor-specific Commands

Label

LOAD_CONFIG_DATA bmRequestType bRequest

0x40 0x01

READ_CONFIG_DATA 0xC0 0x02 wValue

0x0000 wIndex wLength Data

30x02 – 0x0F Data Length Configuration

Data

Data Source Starting Address Data Length Configuration

Data

READ_CONFIG_DATA

This USB request allows data retrieval from the data source specified by the wValue field. Data is retrieved beginning at the

address specified by the wIndex field (see Table 12 ). The wLength field denotes the length in bytes of data requested from the

data source.

Legal values for wValue are as follows:

• 0x0000 Configuration bytes, addresses 0x0 – 0xF only

• 0x0002 External I

2

C memory device

Illegal values for wValue result in an undefined operation. Attempted reads from an I

2

C memory device when none is connected result in an undefined operation. Attempts to read configuration bytes with starting addresses greater than 0xF also, result in an undefined operation.


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CY7C68320C/CY7C68321C

Absolute Maximum Ratings

Storage Temperature ............................................................................................................................................–65

°C to +150°C

Ambient Temperature with Power Supplied ................................................................................................................0

°C to +70°C

Supply Voltage to Ground Potential .......................................................................................................................–0.5 V to +4.0 V

DC Input Voltage to Any Input Pin ........................................................................................................................................ 5.25 V

DC Voltage Applied to Outputs in Hi-Z State................................................................................................. –0.5 V to V

CC

+ 0.5 V

Power Dissipation .............................................................................................................................................................. 300 mW

Static Discharge Voltage ................................................................................................................................................... > 2000 V

Max Output Current Per IO Port (D0-D7, D8-15, ATA control).............................................................................................. 10 mA

Operating Conditions

T

A

(Ambient Temperature Under Bias)........................................................................................................................0°C to +70°C

Supply Voltage .....................................................................................................................................................+3.00V to +3.60V

Ground Voltage ........................................................................................................................................................................... 0V

F osc

(Oscillator or Crystal Frequency)................................................................................ 24 MHz ± 100 ppm, Parallel Resonant

DC Characteristics

Parameter Description

V

OH

V

OL

I

OH

I

OL

C

IN

V

CC

V

CC

Ramp Supply Ramp Up 0V to 3.3V

V

IH

V

IL

Supply Voltage

Input High Voltage

Input Low Voltage

Input Leakage Current I

I

V

IH_X

V

IL_X

Crystal Input HIGH Voltage

Crystal Input LOW Voltage

Output Voltage High

Output Voltage Low

Output Current High

Output Current Low

Input Pin Capacitance

I

SUSP

I

CC

Suspend Current

CY7C68300C/CY7C68320C

Suspend Current

CY7C68301C/CY7C68321C

Supply Current

I

UNCONFIG

T

RESET

Unconfigured Current

Reset Time After Valid Power

Pin Reset After Power Up

Conditions

0 < V

IH

< V

CC

I

OUT

= 4 mA

I

OUT

= –4 mA

All but DPLUS/DMINUS

DPLUS/DMINUS

Connected

Disconnected

Connected

Disconnected

USB High-Speed

USB Full-Speed

Current before device is granted full amount requested in bMaxPower

V

CC

> 3.0V

5.0

200

Min.

3.00

200

2

–0.5

2

–0.5

2.4

Typ.

3.3

0.5

0.3

300

100

50

35

43

Max.

3.60

15

1.2

1.0

380

0.4

4

4

10

150

85

65

5.25

0.8

±10

5.25

0.8

pF mA mA

μA

μA mA

V mA mA pF mA mA

V

μA

V

V

V

Unit

V

μs

V ms

μs


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CY7C68320C/CY7C68321C

AC Electrical Characteristics

ATA Timing Characteristics

The ATA interface supports ATA PIO modes 0, 3, and 4, Ultra

DMA modes 2, 3, and 4, and multi-word DMA mode 2, per the

ATA/ATAPI 6 Specification. The highest enabled transfer rate common to both the AT2LP and the attached mass storage device is used. The AT2LP automatically determines the transfer rates during drive initialization based upon the values

Ordering Information

Part Number

CY7C68300C-56PVXC

CY7C68301C-56PVXC

CY7C68300C-56LFXC

CY7C68301C-56LFXC

CY7C68320C-56LFXC

CY7C68320C-56PVXC

CY7C68321C-56LFXC

CY7C68320C-100AXC

CY7C68321C-100AXC

CY4615B in the AT2LP configuration space and the data reported by the drives in response to an IDENTIFY DEVICE command.

USB Transceiver Characteristics

Complies with the USB 2.0 specification for full- and high-speed modes of operation.

Package Type

56 SSOP Lead-free for self- and bus-powered designs

56 SSOP Lead-free for battery-powered designs

56 QFN Lead-free for self- and bus-powered designs

56 QFN Lead-free for battery-powered designs

56 QFN Lead-free for self- and bus-powered designs

56 SSOP Lead-free for self- and bus-powered designs

56 QFN Lead-free for battery-powered designs

100 TQFP Lead-free for self- and bus-powered designs

100 TQFP Lead-free for battery-powered designs

EZ-USB AT2LP Reference Design Kit

GPIO Pins

–

–

–

–

3

[4]

3

[4]

3

[4]

6

6 n/a

Note

4. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD with EEPROM byte 8, bit 7 on CY7C68320C/CY7C68321C.


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Package Diagrams

Figure 12. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

1

100

16.00±0.20

14.00±0.10

81

80

0.30±0.08

CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

1.40±0.05

R 0.08 MIN.

0.20 MAX.

GAUGE PLANE

0.25

0°-7°

0.60±0.15

1.00 REF.

30

31

0° MIN.

R 0.08 MIN.

0.20 MAX.

0.20 MIN.

DETAIL

A

50

51

0.65

TYP.

12°±1°

(8X)

SEE DETAIL

A

0.20 MAX.

1.60 MAX.

STAND-OFF

0.05 MIN.

0.15 MAX.

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

51-85050-*B


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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C


(continued)

Figure 13. 56-lead Shrunk Small Outline Package 056

28

29

0.088

0.092

0.025

BSC

1

.020

0.292

0.299

0.395

0.420

DIMENSIONS IN INCHES MIN.

MAX.

0.720

0.730

56

0.008

0.0135

0.008

0.016

0.095

0.110

SEATING PLANE

GAUGE PLANE

.010

0.110

0°-8°

0.024

0.040

0.005

0.010

51-85062-*C


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CY7C68320C/CY7C68321C


(continued)

Figure 14. 56-Lead QFN 8 x 8 mm LF56A

A

DIMENSIONS IN MM[INCHES] MIN.

REFERENCE JEDEC MO-220

MAX.

TOP VIEW

7.90[0.311]

8.10[0.319]

7.70[0.303]

7.80[0.307]

N

0.80[0.031]

DIA.

1

2

SIDE VIEW

1.00[0.039] MAX.

0.80[0.031] MAX.

0.08[0.003]

0.05[0.002] MAX.

C

0.20[0.008] REF.

BOTTOM VIEW

0.18[0.007]

0.28[0.011]

N

PIN1 ID

0.20[0.008] R.

1

2

0.45[0.018]

E-PAD

(PAD SIZE VARY

BY DEVICE TYPE)

0.30[0.012]

0.50[0.020]

0°-12°

C

OPTION FOR CML - BOTTOM VIEW

.240TYP

N

1

2

1.925

R.100

R.600

R.500

R.400

R.300

R.200

PIN #1 ID

R.250

(3X)

E-PAD

(PAD SIZE VARY

BY DEVICE TYPE)

.000

.680

R.400

R.300

2.175

2.275

NOTE:

DIMENSIONS ARE SAME WITH STD DWG ON UPPER RIGHT EXCEPT

FOR THE U-GROOVE ON THE PADDLE

U-GROOVE DIMENSION

R.100

R.200

SEATING PLANE

2.375

1.975

2.075

6.45[0.254]

6.55[0.258]

0.50[0.020]

0.24[0.009]

0.60[0.024]

(4X)

51-85144 *F

General PCB Layout Recommendations For USB Mass Storage Designs

The following recommendations must be followed to ensure reliable high-performance operation:

• Use at least a four-layer, impedance controlled board to maintain signal quality.

• Specify specific impedance targets (ask your board vendor what they can achieve).

• Maintain uniform trace widths and trace spacing to control impedance.

• Minimize reflected signals by avoiding using stubs and vias.

• Connect the USB connector shell and signal ground as near to the USB connector as possible.

• Use bypass/flyback capacitors on VBUS near the connector.

• Keep DPLUS and DMINUS trace lengths to within 2 mm of each other in length, with a preferred length of 20–30 mm.

• Maintain a solid ground plane under the DPLUS and

DMINUS traces. Do not allow the plane to be split under these traces.

• Do not place vias on the DPLUS or DMINUS trace routing for a more stable design.

• Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.

• Source for recommendations:

• EZ-USB FX2LP PCB Design Recommendations http://www.cypress.com

• High-speed USB Platform Design Guidelines http://www.usb.org


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CY7C68320C/CY7C68321C

Quad Flat Package No Leads (QFN) Package Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper (Cu) fill must be designed into the PCB as a thermal pad under the package.

Heat is transferred from the AT2LP through the device’s metal paddle on the bottom side of the package. Heat from here is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x

5 array of vias. A via is a plated through-hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process.

For further information on this package design, refer to the application note Surface Mount Assembly of AMKOR’s

MicroLeadFrame (MLF) Technology. The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc.

Figure 15 displays a cross-sectional area underneath the

package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template must be

5 mil. It is recommended that ’No Clean,’ type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow.

Figure 15. Cross-Section of the Area Under the QFN Package

0.017” dia

Solder Mask

Cu Fill Cu Fill

0.013” dia

PCB Material PCB Material

Via hole for thermally connecting the

QFN to the circuit board ground plane.

This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane

Figure 16 is a plot of solder mask pattern and Figure 17

displays an X-Ray image of assembly (darker areas indicate solder).

Figure 16. Plot of the Solder Mask (White Area) Figure 17. X-Ray Image of the Assembly

Other Design Considerations

Certain design considerations must be followed to ensure proper operation of the CY7C68300C/CY7C68301C. The following items must be taken into account when designing a

USB device with the CY7C68300C/CY7C68301C.

Proper Power Up Sequence

Power must be applied to the CY7C68300C/CY7C68301C before, or at the same time as the ATA/ATAPI device. If power is supplied to the drive first, the CY7C68300C/CY7C68301C startup in an undefined state. Designs that utilize separate power supplies for the CY7C68300C/CY7C68301C and the

ATA/ATAPI device are not recommended.


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CY7C68300C/CY7C68301C

CY7C68320C/CY7C68321C

IDE Removable Media Devices

The AT2LP does not fully support IDE removable media devices. Changes in media state are not reported to the operating system so users are unable to eject/reinsert media properly. This may result in lost or corrupted data. Note that standard ATAPI optical drives and ATA CompactFlash-type devices are not part of this group.

Devices With Small Buffers

The size of the drive’s buffer can greatly affect the overall data transfer performance. Care must be taken to ensure that drives have large enough buffers to handle the flow of data to and from it. The exact buffer size needed depends on a number of variables, but a good rule of thumb is:

(aprox min buffer) = (data rate) * (seek time + rotation time + other) where ’other’ may include things like the time required to switch heads, power up a laser, etc. Drives with buffers that are too small to handle the extra data may perform considerably slower than expected.

Disclaimers, Trademarks, and Copyrights

Purchase of I

I

2

2

C™ components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips

C Patent Rights to use these components in an I

2

C system provided that the system conforms to the I

2

C Standard Specification as defined by Philips. Microsoft and Windows are registered trademarks of Microsoft Corporation. Apple and Mac OS are registered trademarks of Apple Computer, Inc. EZ-USB AT2LP, EZ-USB AT2, EZ-USB FX2 and EZ-USB TX2 are trademarks, and EZ-USB is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.


© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C68320C/CY7C68321C

Document History Paged

Description Title: CY7C68300C/CY7C68301C/CY7C68320C/CY7C68321C EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI

Bridge

Document Number: 001-05809

REV.

**

*A

ECN NO.

409321

611658

Issue Date

Orig. of

Change

GIR

Description of Change

See ECN New data sheet.

See ECN ARI/KKU Implemented new template. Added part number CY7C68320C-56PVXC to the Ordering Information. Corrected part numbers on figure 5 and 6. Moved figure titles to the top of each figure per new template requirements. Made grammatical corrections. Changed the Fused Memory Data section. Added new figure: 56-pin SSOP (CY7C68320C/CY7C68321C).

Changed figure 10 to reflect actual Flow for Operational Mode. Changes made between “VBUS_ATA_ENABLE PIN HIGH?” and “Board Manufacturing Test Mode”. Formatted “0=”, “1=” lines in Configuration Data Organization to always show up in the same order. Re-worded 3rd bullet point in the Operation Selection Flow section.

GPIO2_nHS function removed and corrected the sense of ATA_EN to allow drive on ‘0’ and Hi-Z on ‘1’.


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Cypress CY7C68320C User's Manual

EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge

Features

Block Diagram

Applications

Introduction

CY7C68300A Compatibility

±

HID Functions for Button Controls

Functional Overview

Operating Modes

Absolute Maximum Ratings

Operating Conditions

DC Characteristics

AC Electrical Characteristics

Ordering Information

Package Diagrams

Package Diagrams

Package Diagrams

General PCB Layout Recommendations For USB Mass Storage Designs

Quad Flat Package No Leads (QFN) Package Design Notes

PCB Material PCB Material

Other Design Considerations

Disclaimers, Trademarks, and Copyrights

Document History Paged

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