USER MANUAL SED 1520 GRAPHIC CONTROLLER SED 1520

195 USER MANUAL SED 1520
GRAPHIC CONTROLLER SED 1520
| |
e = о || || Display start line reg | ©
383% | > 3
8 9 > 7 > | oo —V1,V2,Va,Va,V5
ооо 8 : L dd decod
AS © 9 & 9 9 COMo to COM1s
RD,WR c 3 3 ; si $ :
ca : e |) 3 D 3 ie Г) : N 3 SEGo to SEGeo_
RES : & : | > 3
A Bus [Toners Г” 1/0 er _| мое
| Lies
FEATURES
* FAST 8-BIT MPU INTERFACE COMPATIBLE WITH 80- AND 68-FAMILY
MICROCOMPUTERS
* MANY COMMAND SET |
* LOW POWER - 30uW AT 2KHZ EXTERNAL CLOCK
* WIDE RANGE OF SUPPLY VOLTAGES
* VDD - VSS: -2.4 TO -7.0 V
* VDD - VEE: -3.5 TO -13.0 V
* LOW-POWER CMOS
INTELLIGENT ADD-ON CONTROLLER BOARD AVAILABLE (COMPLETE TEXTMODE
WITH 2 CHARACTER SETS, CLEAR AREA, SET LINE ETC.): EA 9720
* COMPLETE GRAPHIC MODULES AVAILABLE: E.G. EA P122-5NLED (122x32 DOTS)
ELECTRONIC
6 LOCHHAMER SCHLAG 17 - D-82166 GRÁFELFING
ASSEMBLY: TELEFON 089/854 1991 . TELEFAX 089/854 17 21
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
PIN DESCRIPTION
(1) Power Pins
Name Description
VDD Connected to the +5Vdc power. Common to the Vcc MPU power pin.
Vss 0 Vdc pin connected to the system ground.
V1, V2, V3, V4, Vs
Multi-level power supplies for LCD driving. The voltage determined for each liquid
crystal cell is divided by resistance or it is converted in impedance by the op amp,
and supplied. These voltages must satisfy the following:
Von > Vi > Vo > Va > Va > Vs
(2) System Bus Connection Pins
D7 to DO Three-state 1/0.
The 8-bit bidirectional data buses to be connected to the 8- or 16-bit standard MPU
data buses.
AO Input.
Usually connected to the low-order bit of the MPU address bus and used to identify
the data or a command.
A0=0: DO to D7 are display control data.
A0=1: DO to D7 are display data.
RES Input.
When the RES signal goes 1 5 the 68-series MPU is initialized, and when it
goes —+ 1 , the 80-series MPU is initialized. The system is reset during edge
sense of the RES signal. The interface type to the 68-series or 80-series MPU is
selected by the level input as follows:
High level: 68-series MPU interface
Low level: 80-series MPU interface
CS Input. Active low. Effective for an external clock operation model only.
An address bus signal is usually decoded by use of chip select signal, and it is
entered. If the system has a built-in oscillator, this is used as an input pin to the
oscillator amp and an Rf oscillator resistor is connected to it. In such case, the RD,
WR and E signals must be ORed with the CS signals and entered. |
E (RD) * th -series MPU is conn
Input. Active high.
Used as an enable clock input of the 68-series MPU.
* lf the 80-series MPU is connected:
Input. Active low.
The RD signal of the 80-series MPU is entered in this pin. When this signal is
kept low, the SED1520 data bus is in the output status.
R/W (WR) * lf the 68-series MPU is connected:
Input.
Used as an input pin of read control signals (if R/W is high) or write control
signals (if low).
* И {6 -series MPU | nn
Input. Active low.
The WR signal of the 80-series MPU is entered in this pin. A signal on the data
bus is fetched at the rising edge of WR signal.
(3) LCD Drive Circuit Signals
Name
Description
CL
Input. Effective for an external clock operation model only.
This is a display data latch signal to count up the line counter and common counter
at each signal falling and rising edges. If the system has a built-in oscillator, this is
used as an output pin of the oscillator amp and an Rf oscillator resistor is con-
nected to it.
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
BLOCK DESCRIPTION
System Bus
MPU interface
1. Selecting an interface type
The SED1520 series transfers data via 8-bit bidirec-
tional data buses (DO to D7). As its Reset pin has the
MPU interface select function, the 80-series MPU or
the 68-series MPU can directly be connected to the
MPU bus by the selection of high or low RES signal
level after reset (see Table 1).
When the CS signal is high, the SED1520 series is
disconnected from the MPU bus and set to stand by.
However, the reset signal is entered regardless of the
internal setup status.
Table 1
RES signal input level MPU type AO E R/W CS DO to D7
Active low 68-series T T T T T
Active high 80-series T RD WR T T
Data transfer
The SED1520 and SED1521 drivers use the AO, E (or
RD) and R/W (or WR) signals to transfer data between
the system MPU and internal registers. The combina-
tions used are given in the table blow.
In order to match the timing requirements of the MPU
with those of the display data RAM and control registers
all data is latched into and out of the driver. This
introduces a one cycle delay between a read request for
data and the data arriving. For example when the MPU
68 80
AO
1
7
0
0
Reset Circuit
Detects a rising or falling edge of an RES input and
initializes the MPU during power-on.
+ Initialization status
Display is off.
Display start line register is set to line 1.
Static drive is turned off.
Column address counter is set to address 0.
Page address register is set to page 3.
1/32 duty (SED1520) or 1/16 duty (SED1522) is
selected.
7. Forward ADC is selected (ADC command DO is
| and ADC status flag is 1).
8. Read-modify-write is tumed off.
пин
executes a read cycle to access display RAM the current
contents of the latch are placed on the system data bus
while the desired contents of the display RAM are moved
into the latch.
This means that a dummy read cycle has to be executed
at the start of every series of reads. See Figure 1.
No dummy cycle is required at the start of a series of
writes as data is transferred automatically from the input
latch to its destination.
Function
Read data
Write data
Read status
Write to internal
The input signal level at RES pin is sensed, and an
MPU interface mode is selected as shown on Table 1.
For the 80-series MPU, the RES input is passed through
the inverter and the active high reset signal must be
entered. For the 68-series MPU, the active low reset
signal must be entered.
As shown for the MPU interface (reference example),
the RES pin must be connected to the Reset pin and
reset at the same time as the MPU initialization.
Ifthe MPU is not initialized by the use of RES pinduring
power-on, an unrecoverable MPU failure may occur.
When the Reset command is issued, initialization
items 2 and 5 above are executed.
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
Internal
timing hold
READ
MPU
at N
-
-
u
Address set Dummy read
Data read
atN +1
4
Data read
at N
4
~\ /
|
internal
timing Column
address XX N
DC NA О №2 X
Bus
( hold XZ N
Figure 1
Busy flag
When the Busy flag is logical 1, the SED1520 series is
executing its internal operations. Any command other
than Status Read is rejected during this time. The Busy
flag is output at pin D7 by the Status Read command. If
an appropriate cycle time (tcyc) is given, this flag needs
not be checked at the beginning of each command and,
therefore, the MPU processing capacity can greatly be
enhanced.
Display Start Line and Line Count
Registers
The contents of this register form a pointer to a line of
data in display data RAM corresponding to the first line
of the display (COMO), and are set by the Display Start
Line command. See section 3.
The contents of the display start line register are copied
into the line count register at the start of every frame, that
is on each edge of FR. The line count register is
incremented by the CL clock once for every display line,
thus generating a pointer to the current line of data, in
display data RAM, being transferred to the segment
driver circuits.
XxX n+1 X n+2
Bus Buffer Delay
Column Address Counter
The column address counter is a 7-bit presettable counter
that supplies the column address for MPU access to the
display data RAM. See Figure 2. The counter is
incremented by one every time the driver receives a Read
or Write Display Data command. Addresses above SOH
are invalid, and the counter will not increment past this
value. The contents of the column address counter are set
with the Set Column Address command.
Page Register
The page resiter is a 2-bit register that supplies the page
address for MPU access to the display data RAM. See
Figure 2. The contents of the page register are set by the
Set Page Register command.
Display Data RAM
The display data RAM stores the LCD display data, on a
[-bit per pixel basis. The relation-ship between display
data, display address and the display is shown in Figure
2.
USER MANUAL SED 1520
:
Start line
(Example)
Page address | DATA Ling
TTT =
Do + - | _ 00H <
5 ++ | -
— 11, + + = - 91
D2 Ш ) ° [02
Da — + + + - - - о ==
D1,D2=0,0 Da +++-—-— 03
Ds el '— ++ - - Page 0 04
De +++ — 05
+++ 06
44H or =
Do 08 |= Start —-
Di IRE 09 =
= OA
3
0,1 I 08
Da a Page 1 oC
Ds | 1 1 1 1 0D ©
Ds OE D
D7 ++ t++- OF >
Do 10 =
Di EEE 1 1á
D2 12
D3
1,0 13
Da Il | Page 2 14
Ds 15
De | + 1 1 1 16
D7 + 17 Ha---+-14 - 1/16
Do 18
D1 19
| 1 1 | 1
= 1A
1,1 3 1B
Da ho E Page 3 1С
Ds LI 111 1D
De 1E <
D7 1F 7 -
©
= т
E 5858888815) mm o - JE
c o =
E ilelulalo|o|<
eS - 0 0 0 — и оо — 81518
© | си со | «10| | г-
io e SEE
alo
Response
Common
|__ output
COM 0
COM
COM
COM
COM
COM
COM
COM
69| > | ©) Сл $» | © | О! —
СОМ
COM
o
COM 10
COM 11
COM 12
COM 13
COM 14
COM 15
COM 16
COM 17
COM 18
COM 19
COM 20
COM 21
COM 22
COM 23
COM 24
COM 25
COM 26
COM 27
COM 28
COM 29
COM 30
COM 31
Figure 2 Display Data RAM Addressing
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
COMMANDS
Summary
Command Code Functi
AO D7 Ds Ds Da | Ds | D2 | Di Do unction
Display ONOFF | 0 1 | 0 | т | 0 [4/4 1 | on | Turms display on or off,
1: ON, 0: OFF
Display start line 0 1 1 0 Display start address (0 to 31) Specifies RAM line corresponding to top line
of display.
Set page address | 0 1 0 1 1 1 | 0 | Раде (0% 3) Sets display RAM page in page address
register.
Set column ; |
u 0 0 Column address (0 to 79) Sets display RAM column address in
(segment) address column address register.
Reads the following status:
BUSY 1: Busy
0: Ready
ADC 1: CW output
Read status 0 Busy | ADC |ON/OFF| Reset! 0 | O 0 0 0: CCW output
ON/OFF 1: Display off
0: Display on
RESET 1: Being reset
0: Normal
Write display data | 1 Write data Writes data from data bus into display RAM.
Reads data from display RAM onto data
Read display data | 1 Read data pe $ data from display RAM onto
Select ADC 0 1 0 1 0 0 |0 0 0/1 | 0: CW output, 1: CCW output
tatis drive О
Statis driv 0 0 o lofilo |on | Selects static driving operation.
ON/OFF 1: Static drive, 0: Normal driving
Selets LCD duty cycle
lect d 0 1 0 1 0 1 0 /1
Select duty 0 1 | 4: 482,0: 1/16
Read-Modify-Write | 0 1 1 1 0 0 | 0 0 0 Read-modify-write ON
End 0 1 1 1 1 | 1 1 0 Read-modify-write OFF
Reset 0 1 1 1 0 0 | 0 1 0 Software reset
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
Command Description
Table 3 is the command table. The SED 1520 series identifies a data bus using a combination of A0 and R/W (RD or WR)
signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed
is very high. The busy check is usually not required.
Display ON/OFF
R/W
Ao | RD | WR | D7 De Ds Da | Ds D2 D1 Do
0 1 0 1 0 1 0 1 1 1 D
AEH, AFH
This command turns the display on and off.
* D=1: Display ON
* D=0: Display OFF
Display Start Line
This command specifies the line address shown in Figure 3 and indicates the display line that corresponds to COMO. The
display area begins at the specified line address and continues in the line address increment direction. This area having
the number of lines of the specified display duty is displayed. If the line address is changed dynamically by this command,
the vertical smooth scrolling and paging can be used.
RW
Ao RD | WR | D7 Ds Ds Da D3 D2 D1 Do
0 1 0 1 1 0 A4 A3 A2 A1 A0 COH to DFH
This command loads the display start line register.
A4 A3 A2 A1 Ao |Line Address
0 O 0 0 QO 0
O 0 0 0 1 1
11 1 1 1 31
See Figure 2.
Set Page Address
This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed
by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified.
The display status is not changed even when the page address is changed.
_ | RW
Ao | RD | WR | D7 | De | Ds | Da | Da D2 | Di Do
0 1 0 1 0 1 1 1 0 A1 Ao | B8H to BBH
This command loads the page address register.
At Ao | Page
о O 0
Oo 1 1
1 0 2
1.1 3
See Figure 2.
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
Set Column Address
This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU
continuously, the column address is incremented by 1 each time it is accessed from the set address. Therefore, the MPU
can access to data continuously. The column address stops to be incremented at address 80, and the page address is not
changed continuously.
R/W
Ao | RD | WR | Dr? D6 Ds Da D3 D2 D1 Do
0 1 0 0 A6 As A4 A3 A2 A1 Ao | OOH to 4FH
This command loads the column address register.
A6 A5 A4 A3 A2 A1 Ao |Column Address
60 0 0 0 0 0 O 0
0 O 0 O O 0 1 1
1 0 0 1 1 1 1 79
Read Status
R/W
Ao RD | WR D7 De Ds Da D3 D2 Di Do
0 0 1 ¡BUSY| ADC [ON/OFFIRESET| O 0 0 0
Reading the command МО register (A0=0) yields system status information.
* The busy bit indicates whether the driver will accept a command or not.
Busy=1: The driver is currently executing a command or is resetting. No new command will be accepted.
Busy=0: The driver will accept a new command.
The ADC bit indicates the way column addresses are assigned to segment drivers.
ADC=1: Normal. Column address n — segment driver n.
ADC=0: Inverted. Column address 79-u — segment driver u.
* The ON/OFF bit indicates the current status of the display.
It is the inverse of the polarity of the display ON/OFF command.
ON/OFF=1: Display OFF |
ON/OFF=0: Display ON
» The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode.
RESET=1: Currently executing reset command.
RESET=0: Normal operation
Write Display Data
R/W
Ao RD | WR | D7 De Ds Da D3 D2 D1 | Do
1 1 0 Write data
Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page
address registers and then increments the column address register by one.
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
Read Display Data
R/W
Ao RD | WR | D7 Ds Ds D4 D3 D2 D1 Do
1 0 1 Read data
Reads 8-bits of data from the data I/O latch, updates the contents of the VO latch with display data from the display data
RAM location specified by the contents of the column address and page address registers and then increments the column
address register.
After loading a new address into the column address register one dummy read is required before valid data is obtained.
Select ADC
R/W
Ao RD | WR | D7 De Ds Da Da D2 D1 Do
0 1 0 1 0 1 0 0 0 0 D
AOH, A1H
This command selects the relationship between display data RAM column addresses and segment drivers.
D=1: SEGO €- column address 4FH, ... (inverted)
D=0: SEGO « column address 00H, ... (normal)
This command is provided to reduce restrictions on the placement of driver ICs and routin g of traces during printed circuit
board design. See Figure 2 for a table of segments and column addresses for the two values of D.
Static Drive ON/OFF
RAW
Ao {RD | WR | D7 | De | Ds | Da | D3 D2 | Di Do
0 1 0 1 0 1 0 0 1 0 D A4H, ASH
Forces display on and all common outputs to be selected.
D=1: Static drive on
D=0: Static drive off
Select Duty
RW
Ao | RD {WR | D7 | De | Ds | Da | D3 | D2 | Di Do
0 1 0 1 0 | 1 0 1 O | O D | A8H, ASH
This command sets the duty cycle of the LCD drive and is only valid for the SED1520F and SED1522F. It is invalid for
the SED1521F which performs passive operation. The duty cycle of the SEDI1521F is determined by the externally
generated FR signal.
SED1520 SED1522
D=1: 1/32 duty cycle — 1/16 duty cycle
D=0: 1/16 duty cycle = 1/8 duty cycle
When using the SED1520F0A, SED1522F0A (having a built-in oscillator) and the SED1521FOA continuously, set the
duty as follows:
SED1521Foa
SED1520Fo0A 1/32 1/32
1/16 1/16
SED1522F0A 1/16 1/32
1/8 1/16
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
Read-Modify-Write
RW
Ao | RD | WR | D7 D6 Ds Da D3 D2 D1 Do
0 1 0 1 1 1 0 0 0 0 0 EOH
This command defeats column address register auto-increment after data reads: The current conetents of the column
address register are saved. This mode remains active until an End command is received.
* Operation sequence during cursor display
When the End command is entered, the column address is returned to the one used during input of Read-Modify-Write
command. This function can reduce the load of MPU when data change is repeatedat a specific display area (suchas cursor
blinking).
* Any command other than Data Read or Write can be used in the Read-Modify-Write mode. However, the Column
Address Set command cannot be used.
Set Page Address
Y
Set Column Address
Вы,
Read-Modify-Write
Dummy Read
Y
Read Data
Y
Write Data
End
RW
Ao RD | WR D7 D6 Ds Da D3 D2 D1 Do
0 1 0 1 1 1 0 1 1 1 0 EEH
This command cancels read-modify-write mode and restores the contents of the column address register to their value prior
to the receipt of the Read-Modify-Write command.
La »|
i |
y Return
| |
Column address XN X N+1 xX N+2 Y N+3 Y---- N+m N xX
Read-Modify-Write mode is selected. E End
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
Reset
R/W
Ao RD | WR | D7 Ds Ds Da D3 D2 D1 Do
0 1 0 1 1 1 0 0 О 1 0 E2H
This command clears
* the display start line register.
* and set page address register to 3 page.
It does not affect the contents of the display data RAM.
When the power supply is turned on, a Reset signal is entered in the RES pin. The Reset command cannot be used instead
of this Reset signal.
Power Save (Combination command)
The Power Save mode is selected if the static drive is turned ON when the display is OFF. The current consumption can
be reduced to almost the static current level. In the Power Save mode:
(a) The LCD drive is stopped, and the segment and common driver outputs are set to the VDD level.
(b) The external oscillation clock input is inhibited, and the OSC2 is set to the floating mode.
(c) The display and operation modes are kept.
The Power Save mode is released when the display is turned ON or when the static drive is turned OFF. If the LCD drive
voltage is supplied from an external resistance divider circuit, the current passing through this resistor must be cut by the
Power Save signal.
Voo O—
+ Voo
Ñ— 5 V1
> EN V2
SED1520
Vs SED1522
*— —_ Va
Е
Power Save signal
VssH
Ifthe LCD drive power is generated by resistance division, the resistance and capacitance are determined by the LCD panel
size. After the panel size has been determined, reduce the resistance to the level where the display quality is not affected
and reduce the power consumption using the divider resistor.
11
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
SPECIFICATIONS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply voltage (1) Vss —8.0 to +0.3 Vv
Supply voltage (2) V5 —16.5 to +0.3 V
Supply voltage (3) V1, V4, V2, V3 V5 to +0.3 V
Input voltage VIN Vss—0.3 to +0.3 Vv
Output voltage Vo Vss—0.3 to +0.3 V
Power dissipation PD 250 mW
Operating temperature Topr —30 to +85 deg. C
Storage temperature Tstg —65 to +150 deg. C
Soldering temperature time at lead Tsol 260, 10 deg. C, sec
Notes: 1. All voltages are specified relative to VDD = О У.
2. The following relation must be always hold
VDD 2 VI 2 V2 > V3 > V4> VS
3. Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional
operation under these conditions is not implied.
4. Moisture resistance of flat packages can be reduced by the soldering process, so care should be taken to
avoid thermally stressing the package during board assembly.
Electrical Specifications
DC Characteristics
Ta = -20 to 75 deg. C, VDD = 0 V unless stated otherwise
os Rating . . .
Parameter Symbol Condition Min. Typ. Max. Unit | Applicable Pin
Operating | Recommended -5.5 -5.0 —4.5
voltage (1) Vss V |Vss
See note 1.| Allowable —7.0 — -2.4
Recommended V5 -13.0 — -3.5 y V5
Operating | Allowable -13.0 — — See note 10.
voltage (2) | Allowable V1, V2 0.6xV5 — VDD V |V1,V2
Allowable V3, V4 V5 — 0.4xV5 V {V3 V4
VIHT Vss+2.0 — VoD See note 2 & 3.
High-level input voltage | | =5° Jods] — | Von
9 pu 9 VIHT |VSS=-3V 0.2xVss — VDD See note 2 & 3
VIHC |Vss=-3V 0.2xVss — VDD у
VILT Vss Vss+0.8 See note 2 & 3.
Low-level input voltage Ve uz 0.85
P 9 VILT |Vss=-3V Vss 0.85xVss See note 2 8 3
Vite |Vss=-3V Vss 0.8xVss
VOHT |lOH=-3.0 mA Vss+2.4 — — 0SC2
VOHC1 |loH = -2.0 mA VSS+2.4 — — V
See note 4 & 5.
High-level t voltage Voxc2 |loH = -120 pA 0.2xVss — —
igh-level output voltag VOHT |Vss=-3V l[loH=-2maA|0.2xVss
See note 4 & 5.
Voxc1 |Vss=-3V loH = —2 MA | 0.2xVss V OSC?
VOHC2 |Vss=-3V IOH = -50 uAl 0.2xVss
(continued)
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
DC Characteristics (Cont'd)
Ta = —20 to 75 deg. C, VDD = 0 V unless stated otherwise
a Ш Rating Co
Applicable Pin
Parameter Symbol Condition Min. Typ. Max Unit pplicable
Voir _|loL = 3.0 mA — — | Vss+0.4 0SC2
VoLc1 |loL = 2.0 mA — — |Vss+04| V
See note 4 & 5.
Low-level output voltage VoLc2 {lol = 120 pA — — |0.8xVss
ow tp 9 Vor | М$$ = -3 \/ loL =2 mA 0.8xVss
See note 4 & 5.
VoLc: | М$$ = -3 \ loL =2 mA 0.8xVes | V 0SC2
VoLc2 | Vss=-3V loL = 50 pA 0.8xVss
Input leakage current IL —1.0 — 1.0 pA | See note 6.
Output leakage current ILO -3.0 — 3.0 pA | See note 7.
V5=-5.0V | — 5.0 75 SEGO to 79,
LCD driver ON resistance Ron |Ta=25deg.C ко [COMO to 15,
V6=-35V| — 10.0 50.0 See note 11
Static current dissipation 1900 |CS=CL=Voo — 0.05 1.0 LA |Voo
Durina disola fcL = 2 kHz — 2.0 5.0 Voo
ve а y YTRi=1MQ | — 95 | 150 | pA |See note 12,
a fcL= 18 kHz| — 5.0 10.0 13 & 14.
loo (1) 4
During display | fc. = 2 kHz 1.5 4.5 VDD
Dynamic current dissipation \/5 = -5 \/ НА
Vss=-3V |Rf=1MOQ 60 | .120 See note 12 & 13.
During access tcyc = 200 kHz| — 300 500
loo (2) | Vss = —3V, pA |See note 8.
During access teyc = 200 kHz 150 300
Input pin capacitance CIN |Ta=25 deg. C, f=1 MHz — 5.0 8.0 pF | All input pins
= 0
Rf = 1.0 MQ +2%, 15 18 я
Oscillation frequenc fosc vss =-5.0V kHz | See note 9
Equeney Rr = 1.0 MQ 2%, | le " |
Vss = -3.0 V
, RES
Reset time {А 1.0 — TN See note 15.
Notes: 1. Operation over the specified voltage range is guaranteed, except where the supply voltage changes
suddenly during CPU access.
AO, DO to D7, E (or RD), R/W (or WR) and CS
CL, FR, M/S and RES
DO to D7
FR
AO, E (or RD), R/W (or WR), CS, CL, M/S and RES
When DO to D7 and FR are high impedance.
During continual write acess at a frequency of tcyc. Current consumption during access is effectively
proportional to the access frequency.
9. See figure below for details
10. See figure below for details
11. Fora voltage differential of 0.1 V between input (V1, ..., V4) and output (COM, SEG) pins. All
voltages within specified operating voltage range.
12. SED1520*A+ and SED1521*A* and SED1522*A* only. Does not include transient currents due to stray
and panel capacitances.
13. SED1520*0* and SED1522*0* only. Does not include transient currents due to stray and panel
capacitances.
14. SED1521+0* only. Does not include transient currents due to stray and panel capacitances.
15. tR (Reset time) represents the time from the RES signal edge to the completion of reset of the internal
circuit. Therefore, the SED1520 series enters the normal operation status after this tR.
юн ом вы
13
USER MANUAL SED 1520
AC Characteristics
« MPU Bus Read/Write I (80-family MPU)
DO to 07
(WRITE)
DO to 07
(READ)
Ta = -20 to 75 deg. C, Vss =-5.0 V +10% unless stated otherwise
ELECTRONIC ASSEMBLY
e: Rating
Parameter Symbol Condition Min. Max Unit Signal
Address hold time tAH8 10 — ns AO. CS
Address setup time taws 20 — ns
System cycle time tcycs 1000 — ns WR. RD
Control pulsewidth tec 200 — ns
Data setup time toss 80 — ns
Data hold time toHs 10 — ns DO to D7
RD access time taccs CL = 100 oF — 90 ns
Output disable time {сна a Р 10 60 ns
Rise and fall time tr, tf — — 15 ns —
(VSS = -2.7 to -4.5 V, Ta = -20 to +75°C)
was Ratin ‚ ‚
Parameter Symbol Condition Min, Max. Unit Signal
Address hold time {АН8 _ 20 — ns AO. CS
Address setup time taws 40 — ns ’
System cycle time teYcs 2000 — ns
Control pulse width tec a 400 — ns WR, RD
Data setup time tDss 160 — ns
Data hold time tDH8 20 — ns DO to D7
RD access time taccs CL = 100 bE — 180 ns
Output disable time ICH8 a Р 20 120 ns
_Rise and fall time tr, tí — — 15 ns —
* MPU Bus Read/Write II (68-family MPU)
teves
E И N
Lew
t, Lo
но > t pse
7 X
t AH6
AO, CS”
! bre
DO to D7 A
(WRITE) °K
t
t acce _| OH6
DO to D?
(READ) 7
Ta = —20 to 75 deg. C, Vss = —5 V +10 unless stated otherwise
e: Rating . ;
Parameter Symbol Condition Min. Max. Unit Signal
System cycle time tCYC6 1000 — ns
Address setup time tAW6 20 — ns AO, CS, R/W
Address hold time tAH6 10 — ns
Data setup time tDS6 80 — ns
Data hold time | tDH6 10 — ns DO to D7
Output disable time tOH6 CL = 100 oF 10 60 ns
Access time tACC6 Ш p — 90 ns
Enable Read EW 100 — ns E
pulsewidth Write 80 — ns
Rise and fall time tr, tf — — 15 ns —
(VSs = -2.7 to — 4.5 \, Та = -20 10 +75°С)
Ratin
ce . ; |
Parameter Symbol Condition Min. Max. Unit Signa
System cycle time” tCYce — 2000 — ns
Address setup time tAW6 __ 40 — ns AO, CS, RW
Address hold time tAH6 20 — ns
Data setup time tDS6 __ 160 — ns
Data hold time | tDHE6 20 — ns DO to D7
Output disable time tOH6 CL = 100 oF 20 120 ns
Access time tacce Р — 180 ns
Enable Read tew _— 200 — ns E
pulse width | Write 160 — ns
Rise and fall time tr, tr — — 15 ns —
Notes: |.
ICYC6 is the cycle time of CS. E = H, not the cycle time of E.
USER MANUAL SED 1520
ELECTRONIC ASSEMBLY
LE
USER MANUAL SED 1520
APPLICATION NOTES
MPU Interface Configuration
80 Family MPU
Vee до sac VOD
Alto A7 "> —
DRÔ Decoder > CS ;
MPU 7 SED1520FAA T—
DO to D7 «<; > DO to D7 —
RD » RD
WR » WA T
GND NES 1 Ps RES Ves V5
RESET
e JUN 9
we E HIGH-LEVEL Grafikkontroller
fur Displays mit SED 1520 ..
TECHNISCHE DATEN
* FUR LC GRAFIKDISPLAYS 122x32 (120x32) MIT SED 1520 La Ls - A
* KEINE TIMINGPROBLEME MEHR BEI SCHNELLEM BUSSYSTEM VO a er
* PROGRAMMIERUNG UBER HOCHSPRACHENAHNLICHE BEFEHLE: ec" A
* GERADE, PUNKT, BEREICH, UND/ODER/EXOR, BARGRAPH... 5895 88588 ‘
* 3 VERSCHIEDENE FONTS INTEGRIERT солнц
* ZOOM FUNKTION (2-, 3- UND 4-FACH) ALLER FONTS NE we 22} vos
* 4-16 FREI DEFINIERBARE ZEICHEN (JE NACH GROBE) eer de EA Bp ver
* TEXT UND GRAFIK MISCHEN no 113 |C1520-P3sh Ne
* ANSTEUERUNG ÚBER RS-232 / CMOS-PEGEL a i Eo
* DIREKTER ANSCHLUB VON ICL232 O.Ä. MÖGLICH el 1 eRENAARANAZ? >
* BAUDRATE PROGRAMMIERBAR VON 150 BIS 115.200 BAUD 0EI39985888
* BELASTET NICHT DAS PROZESSORSYSTEM wg <<" PLCC44]
* NUR 4 EXTERNE BAUTEILE ERFORDERLICH
* 8 DIGITALE /O'S ZUR FREIEN VERWENDUNG
HARDWARE CODIERUNG VON BIS ZU 4 ADRESSEN
BESTELLBEZEICHNUNG
HIGH-LEVEL GRAFIKKONTROLLER 122x32 FUR SED1520 EA IC1520-PGH
KERAMIKRESONATOR SMD 7,37MHz, 3 PINS INKL. C's EA KERS7M37-C
PASSENDES GRAFIKDISPLAY MIT SED1520, 122x32 EA P122-NLED
ELECTRONIC
LOCHHAMER SCHLAG 17 - D-82166 GRÁFELFING
TELEFON 089/8541991 - TELEFAX 089/854 17 21 ASSEMBLY: