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240pin DDR3L SDRAM Unbuffered DIMM
DDR3L SDRAM
Unbuffered DIMMs
Based on 4Gb C-Die
HMT425U6CFR6A
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.0 / Nov. 2014 1
Revision History
Revision No.
0.1
1.0
History
Initial Release
IDD Specification update
Draft Date
Aug. 2014
Nov. 2014
Remark
Rev. 1.0 / Nov. 2014 2
Description
SK hynix Unbuffered DDR3L SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-
Line Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations.
Feature
• Power Supply: VDD=1.35V
(1.283V to 1.45V)
• VDDQ=1.35V
(1.283 to 1.45V)
• VDDSPD=3.0V to 3.6V
• Backward Compatible with 1.5V DDR3 Memory module
• 8 internal banks
• Data transfer rates: PC3-14900. PC3-12800, PC3-10600, PC3-8500
• Bi-directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4
• Supports ECC error correction and detection
• On Die Termination (ODT) supported
• Temperature sensor with integrated SPD (Serial Presence Detect) EEPROM
• This product is in Compliance with the RoHS directive
Ordering Information
Part Number
HMT425U6CFR6A-G7/H9/PB
Density Organization
2GB 256Mx64
Component Composition
256Mx16(H5TC4G63CFR)*4
# of ranks
FDHS
1 X
Rev. 1.0 / Nov. 2014 3
Key Parameters
MT/s
DDR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
Grade
-G7
-H9
-PB
-Rd
tCK
(ns)
1.875
1.5
1.25
1.07
CAS
Latency
(tCK)
7
9
11
13
tRCD
(ns) tRP
(ns)
13.125
13.125
13.5
(13.125)*
13.5
(13.125)*
13.75
(13.125)*
13.75
(13.125)*
13.91
(13.125)*
13.91
(13.125)*
tRAS
(ns)
37.5
36
35
34
tRC
(ns)
50.625
49.5
(49.125)*
48.75
(48.125)*
47.91
(48.125)*
CL-tRCD-tRP
7-7-7
9-9-9
11-11-11
13-13-13
*
SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [Mbps]
CL9 CL10 CL11 CL12 CL13
Remark Grade
-G7
-H9
-PB
-RD
CL6
800
800
800
800
Address Table
CL7
1066
1066
1066
1066
CL8
1066
1066
1066
1066
1333
1333
1333
1333
1333
1333
1600
1600 1866
Refresh Method
Row Address
Column Address
Bank Address
Page Size
2GB(1Rx16)
8K/64ms
A0-A14
A0-A9
BA0-BA2
2KB
Rev. 1.0 / Nov. 2014 4
Pin Descriptions
Pin Name Description Pin Name Description
A0–A15
BA0–BA2
RAS
CAS
WE
S0–S1
CKE0–CKE1
SDRAM address bus
SDRAM bank select
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
DIMM Rank Select Lines
SDRAM clock enable lines
ODT0–ODT1 On-die termination control lines
DQ0–DQ63 DIMM memory data bus
CB0–CB7
DQS0–DQS8
DIMM ECC check bits
SDRAM data strobes
(positive line of differential pair)
DQS0–DQS8
DM0–DM8
CK0–CK1
CK0–CK1
SDRAM data strobes
(negative line of differential pair)
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
SDRAM clocks
(positive line of differential pair)
SDRAM clocks
(negative line of differential pair)
SCL
SDA
SA0–SA2
V
DD*
V
DD
Q
*
V
REF
DQ
V
V
REF
V
V
-
CA
SS
DDSPD
NC
TEST
RESET
TT
RSVD
I
2
C serial bus clock for EEPROM
I
2
C serial bus data line for EEPROM
I
2
C slave address select for EEPROM
SDRAM core power supply
SDRAM I/O Driver power supply
SDRAM I/O reference supply
SDRAM command/address reference supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare pins (no connect)
Memory bus analysis tools
(unused on memory DIMMS)
Set DRAMs to Known State
SDRAM I/O termination supply
Reserved for future use
-
*The V
DD
and V
DD
Q pins are tied common to a single power-plane on these designs
Rev. 1.0 / Nov. 2014 5
Input/Output Functional Descriptions
Symbol Type
CK0–CK1
CK0–CK1
CKE0–CKE1
S0–S1
RAS, CAS, WE SSTL
ODT0–ODT1 SSTL
V
REF
DQ
V
REF
CA
Supply
Supply
V
DD
Q
BA0–BA2
A0–A15
DQ0–DQ63,
CB0–CB7
DM0–DM8
V
DD
, V
SS
SSTL
SSTL
SSTL
Supply
SSTL
SSTL
SSTL
SSTL
Supply
Polarity
Differential crossing
Active High
Active Low
Function
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK
(Both directions of crossing).
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks.
Active Low RAS, CAS, and WE (
ALONG WITH
S) define the command being entered.
Active High
When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming this function is enabled in the Mode Register 1 (MR1).
Reference voltage for SSTL15 I/O inputs.
Reference voltage for SSTL 15 command/address inputs.
—
—
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, V
DD
Q shares the same power plane as V
DD
pins.
Selects which SDRAM bank of eight is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0–RA15).
During a Read or Write command cycle, Address input defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which bank to precharge. A12(BC) is sampled during READ and
WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop; LOW, burst chopped).
— Data and Check Bit Input/Output pins.
Active High
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Power and ground for the DDR3 SDRAM input buffers, and core logic. V
DD and V
DD
Q pins are tied to V
DD
/V
DD
Q planes on these modules.
Rev. 1.0 / Nov. 2014 6
Symbol
DQS0–DQS8
DQS0–DQS8
SA0–SA2
V
SDA
SCL
DDSPD
Type
SSTL
Supply
Polarity
Differential crossing
Function
Data strobe for input and output data.
—
—
—
These signals are tied at the system planar to either V
SS
or V
DDSPD
to configure the serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD
EEPROM. An external resistor may be connected from the SDA bus line to
V
DDSPD
to act as a pullup on the system board.
This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to V
DDSPD
to act as a pullup on the system board.
Power supply for SPD EEPROM. This supply is separate from the V
DD
/V
DD
Q power plane. EEPROM supply is operable from 3.0V to 3.6V.
Rev. 1.0 / Nov. 2014 7
Pin Assignments
24
25
26
27
20
21
22
23
28
29
30
16
17
18
19
12
13
14
15
V
SS
DQ16
DQ17
V
SS
DQS2
DQS2
V
SS
DQ18
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
DQ10
DQ11
DQ19
V
SS
DQ24
5
6
7
8
9
2
3
4
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)
Pin
# x64
Non-ECC x72
ECC
Pin
#
1 V
REF
DQ V
REF
DQ 121
x64
Non-ECC
V
SS
x72
ECC
V
SS
Pin
#
61
x64
Non-ECC
A2
x72
ECC
A2
Pin
#
181
x64
Non-ECC
A1
x72
ECC
A1
10
V
DQ0
DQ1
V
SS
DQS0
DQS0
V
SS
SS
DQ2
DQ3
V
DQ0
DQ1
V
SS
DQS0 126
DQS0
V
SS
SS
DQ2
DQ3
122
123
124
125
127
128
129
130
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ4
DQ5
V
DM0
NC
V
DQ6
DQ7
V
SS
SS
SS
62
63
64
65
66
67
68
69
70
V
V
DD
CK1
CK1
V
DD
V
DD
REF
NC
V
CA
DD
A10
V
DD
CK1
CK1
V
DD
V
DD
182
183
184
185
186
V
REF
CA 187
NC
V
DD
A10
188
189
190
V
V
V
DD
DD
CK0
CK0
V
DD
NC
A0
DD
BA1
2
V
V
DD
DD
CK0
CK0
V
DD
EVENT
V
A0
DD
BA1
2
11 V
SS
V
SS
131
DQ8 132
DQ9 133
V
SS
134
DQS1 135
DQS1 136
V
SS
137
DQ10 138
DQ11 139
V
SS
140 DQ20
DQ16 141 DQ21
DQ17 142
V
SS
143
DQS2 144
DQS2 145
V
SS
146
DQ18 147
DQ19 148
V
SS
149
DQ24 150
DQ12
DQ13
V
SS
DM1
NC
V
SS
DQ14
DQ15
V
SS
V
V
SS
DM2
NC
SS
DQ22
DQ23
V
SS
DQ28
DQ29
DQ12
DQ13
V
SS
DM1
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
V
SS
DQ34
DQ35
V
SS
DQ40
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
BA0
2
V
DD
WE
CAS
V
DD
S1
ODT1
BA0
2
V
DD
WE
191
CAS
V
DD
S1 196
ODT1 197
192
193
194
195
V
DD
NC
198
199
V
SS
200
DQ32 201
DQ33 202
V
SS
203
DQS4 204
DQS4 205
V
SS
206
DQ34 207
DQ35 208
V
SS
209
DQ40 210
V
DD
V
DD
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
RAS
S0
V
DD
ODT0
A13
V
DD
NC
V
SS
V
SS
DQ44
DQ45
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
RAS
S0
V
DD
ODT0
A13
V
DD
NC
V
SS
V
SS
DQ44
DQ45
NC = No Connect; RFU = Reserved Future Use
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.
Rev. 1.0 / Nov. 2014 8
53
54
55
49
50
51
52
43
44
45
46
47
48
CKE0
V
DD
BA2
NC
V
DD
All
NC
V
SS
NC
NC
V
SS
NC
KEY
NC
39
40
41
42
35
36
37
38
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)
Pin
# x64
Non-ECC x72
ECC
Pin
# x64
Non-ECC x72
ECC
Pin
# x64
Non-ECC x72
ECC
Pin
# x64
Non-ECC x72
ECC
31
32
33
34
DQ25
V
SS
DQS3
DQS3
DQ25
V
SS
151
152
DQS3 153
DQS3 154
V
SS
DM3
NC
V
SS
V
DM3
NC
V
SS
SS
91
92
93
94
DQ41
V
SS
DQS5
DQS5
DQ41
V
SS
211
212
DQS5 213
DQS5 214
V
V
SS
DM5
NC
SS
V
SS
DM5
NC
V
SS
V
DQ26
DQ27
V
NC
NC
V
SS
SS
SS
NC
V
V
SS
DQ26
DQ27
SS
CB0
CB1
V
SS
155
156
157
158
159
160
161
DQS8 162
DQ30
DQ31
V
NC
NC
V
SS
SS
DM8
NC
DQ30
DQ31
V
V
SS
CB4
CB5
SS
DM8
NC
95
96
97
98
99
100
101
102
V
DQ42
DQ43
V
DQ48
DQ49
V
SS
SS
SS
DQS6
V
DQ42
DQ43
V
SS
SS
V
SS
215
216
217
218
DQ48 219
DQ49 220
221
DQS6 222
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
NC
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
NC
DQS8 163
V
SS
CB2
CB3
V
SS
NC
164
165
166
167
168
V
SS
NC
NC
V
SS
NC
Reset
V
SS
CB6
CB7
V
SS
NC
Reset
103
104
105
106
107
108
NC 169 CKE1/NC
CKE0 170 V
DD
KEY
CKE1/NC
V
DD
109
110
111
V
DD
171
BA2 172
NC 173
V
DD
174
All 175
NC
A14
V
DD
A12
A9
NC
A14
V
DD
A12
A9
112
113
114
115
116
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
DQS6 223
V
SS
224
DQ50 225
DQ51 226
V
SS
227
DQ56 228
DQ57 229
V
SS
230
DQS7 231
DQS7 232
V
SS
233
DQ58 234
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
DQ59 235
V
SS
236 V
V
SS
DDSPD
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
56
A7
2
A7
2
176 V
DD
V
DD
117 SA0 SA0 237 SA1 SA1
57
58
59
V
DD
A5
2
A4
2
V
DD
A5
A4
2
2
177
178
179
A8
2
A6
2
V
DD
A8
2
A6
2
V
DD
118
119
120
SCL
SA2
V
TT
SCL
SA2
V
TT
238
239
240
SDA
V
V
SS
TT
SDA
V
V
SS
TT
60 V
DD
V
DD
180
A3
2
A3
2
NC = No Connect; RFU = Reserved Future Use
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.
Rev. 1.0 / Nov. 2014 9
On DIMM Thermal Sensor
The DDRL3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.
Connection of Thermal Sensor
EVENT
SCL
SDA
SA0
SA1
SA2
EVENT
SCL
SPD with
Integrated
SDA
TS
SA0
SA1
SA2
Temperature-to-Digital Conversion Performance
Parameter
Temperature Sensor Accuracy (Grade B)
Condition
Active Range,
75°C < T
A
< 95°C
Monitor Range,
40°C < T
A
< 125°C
-20°C < T
A
< 125°C
Resolution
-
-
Min
-
Typ Max
± 0.5
± 1.0
Unit
°C
± 1.0
0.25
± 2.0
± 2.0
± 3.0
°C
°C
°C
Rev. 1.0 / Nov. 2014 10
Functional Block Diagram
2GB, 256Mx64 Module(1Rank of x16)
S0
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D0
ZQ
DQS4
DQS4
DM4
DQS5
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D2
ZQ
DQS2
DQS2
DM2
DQS3
DQS3
DM3
BA0–BA2
A0–A14
RAS
CAS
CKE0
WE
ODT0
CK0
CK0
RESET
Rev. 1.0 / Nov. 2014
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
ZQ
Serial PD
SCL
BA0–BA2: SDRAMs D0–D3
WP
A0 A1
A0–A14: SDRAMs D0–D3
RAS: SDRAMs D0–D3
CAS: SDRAMs D0–D3
CKE: SDRAMs D0–D3
V
DDSPD
V
DD
/V
DD
Q
WE: SDRAMs D0–D3
ODT: SDRAMs D0–D3
CK: SDRAMs D0–D3
CK: SDRAMs D0–D3
RESET:SDRAMs D0-D3
V
V
REF
REF
DQ
V
SS
CA
SA0 SA1
A2
SA2
DQS6
DQS6
DM6
DQS7
DQS7
DM7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CS
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
ZQ
SDA
SPD
D0–D3
D0–D3
D0–D3
D0–D3
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. DQ,DM,DQS,DQS resistors;Refer to associated topology diagram.
4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document.
5. The pair CK1 and CK1# is terminated in
75ohm but is not used on the module.
6. A15 is not routed on the module.
7. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is
240ohm+-1%
8. One SPD exists per module.
11
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
VDD
Parameter
Voltage on VDD pin relative to Vss
VDDQ Voltage on VDDQ pin relative to Vss
V
IN
, V
OUT
Voltage on any pin relative to Vss
T
STG
Notes:
Storage Temperature
Rating
- 0.4 V ~ 1.8 V
- 0.4 V ~ 1.8 V
- 0.4 V ~ 1.8 V
-55 to +100
Units
V
V
V o C
Notes
1
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
T
OPER
Parameter
Normal Operating Temperature Range
Extended Temperature Range
Rating
0 to 85
85 to 95
Units
o o
Notes
C 1,2
C 1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85 o
C under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 o
C and 95 o
C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).
DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the
DIMM SPD for tFEFI requirements in the Extended Temperature Range.
Rev. 1.0 / Nov. 2014 12
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Rating
Symbol Parameter
Typ.
1.35
Max.
1.45
Units Notes
VDD
Supply Voltage
Min.
1.283
V 1,2,3,4
VDDQ
Notes:
Supply Voltage for Output
1.283
1.35
1.45
V 1,2,3,4
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - - DDR3 (1.5V) operation
.
Rating
Symbol Parameter
Typ.
1.5
Max.
1.575
Units Notes
VDD
Supply Voltage
Min.
1.425
V 1,2,3
VDDQ
Notes:
Supply Voltage for Output
1.425
1.5
1.575
V 1,2,3
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 1.0 / Nov. 2014 13
Ta Tb Tc
CK,CK#
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
Tmin = 10ns
Tmin = 10ns
Tmin = 200us tCKSRX
T = 500us
RESET#
Td
CKE
Tmin = 10ns
COMMAND
BA
READ
READ
ODT
RTT
READ
Te Tf Tg Th Ti Tj Tk
VALID tDLLK tIS
1) tXPR
MRS tMRD
MRS tMRD
MRS tMRD
MRS tMOD
ZQCL tZQinit
1) VALID tIS
MR2 MR3 MR1 MR0
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID tIS
VALID
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.
TIME BREAK
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
DON’T CARE
Rev. 1.0 / Nov. 2014 14
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and Address
DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866
Symbol Parameter Unit Notes
Min Max Min Max Min Max
VIH.CA(DC90) DC input logic high Vref + 0.09
VDD Vref + 0.09
VDD
VIL.CA(DC90) DC input logic low VSS Vref - 0.09
VSS Vref - 0.09
VIH.CA(AC160) AC input logic high Vref + 0.160
Note2 Vref + 0.160
Note2
Vref - 0.09
V
VIL.CA(AC160) AC input logic low Note2 Vref - 0.160
Note2 Vref - 0.160
-
VIH.CA(AC135) AC Input logic high Vref + 0.135
Note2 Vref + 0.135
Note2 Vref + 0.135
Note2
VIL.CA(AC135) AC input logic low Note2 Vref - 0.135
Note2 Vref - 0.135
Vref + 0.09
VSS
-
Note2
VDD
-
Vref - 0.135
V
V
V
V
V
1
1
1,2,5
VIH.CA(AC125) AC Input logic high Vref + 0.125
Note2 V
VIL.CA(AC125) AC input logic low
V
RefCA(DC
)
Note2 Vref - 0.125
V
Reference Voltage for
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V
ADD, CMD inputs
3,4
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 28.
3. The ac peak noise on V
Ref
may not allow V
Ref
to deviate from V
RefCA(DC)
by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table "Single
Ended AC and DC Input Levels for DQ and DM" on page 16), the respective levels in JESD79-3 (VIH/L.CA(DC100),
VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) apply. The 1.5V levels (VIH/
L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) do not apply when the device is operated in the 1.35 voltage range.
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
Rev. 1.0 / Nov. 2014 15
AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below.
DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 50 in “DDR3L Device Operation”) as well as derating tables Table 46 in “DDR3L Device Operation” depending on Vih/Vil AC levels.
Single Ended AC and DC Input Levels for DQ and DM
DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866
Symbol Parameter Unit Notes
Min Max Min Max Min Max
VIH.DQ(DC90) DC input logic high Vref + 0.09
VIL.DQ(DC90) DC input logic low VSS
VDD
Vref - 0.09
Vref + 0.09
VSS
VDD
Vref - 0.09
VIH.DQ(AC160) AC input logic high Vref + 0.160
Note2
VIL.DQ(AC160) AC input logic low Note2 Vref - 0.160
-
-
-
-
VIH.DQ(AC135) AC Input logic high Vref + 0.135
Note2 Vref + 0.135
Note2
Vref + 0.09
VSS
-
-
-
VDD V
Vref - 0.09
V
-
-
-
1
1
V 1, 2, 5
V 1, 2, 5
V 1, 2, 5
VIL.DQ(AC135) AC input logic low
VIH.DQ(AC130) AC Input logic high
VIL.DQ(AC130) AC input logic low
Note2 Vref - 0.135
Note2 Vref - 0.135
-
-
-
Vref + 0.130
Note2
V
V
1, 2, 5
1, 2, 5
Note2 Vref - 0.130
V 1, 2, 5
V
RefDQ(DC
)
Reference Voltage for DQ, DM inputs
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V
Notes:
1. Vref = VrefDQ (DC).
3, 4
2. Refer to "Overshoot and Undershoot Specifications" on page 28.
3. The ac peak noise on V
Ref
may not allow V
Ref
to deviate from V
RefDQ(DC)
by more than +/-1% VDD (for reference: approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on page 15) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) apply. The 1.5V levels (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) do not apply when the device is operated in the 1.35 voltage range.
Rev. 1.0 / Nov. 2014 16
Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages
VRefCA
and V
RefDQ
are illustrated in figure below. It shows a valid reference voltage V
V
RefDQ
likewise).
Ref
(t) as a function of time. (V
Ref
stands for V
RefCA
and
V
Ref
(DC) is the linear average of V
Ref
(t) over a very long period of time (e.g. 1 sec). This average has to
more V
Ref
(t) may temporarily deviate from V
Ref (DC)
by no more than +/- 1% VDD.
voltage
VDD
V
Ref(DC)
V
Ref
ac-noise
V
Ref
(t)
V
Ref(DC)max
VDD/2
V
Ref(DC)min
VSS time
Illustration of V
Ref(DC)
tolerance and V
Ref
ac-noise limits
The voltage levels for setup and hold time measurements V
IH(AC) dent on V
Ref
.
, V
IH(DC)
, V
IL(AC)
, and V
IL(DC) are depen-
“V
Ref
” shall be understood as V
Ref(DC)
, as defined in figure above.
This clarifies that dc-variations of V
Ref
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for V
Ref(DC)
deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
Ref ac-noise. Timing and voltage effects due to ac-noise on V
Ref fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
up to the speci-
Rev. 1.0 / Nov. 2014 17
AC and DC Logic Input Levels for Differential Signals
Differential signal definition
t
DVAC
V
IL.DIFF.AC.MIN
V
IL.DIFF.MIN
0 half cycle
V
IL.DIFF.MAX
V
IL.DIFF.AC.MAX
t
DVAC time
Definition of differential ac-swing and “time above ac-level” t
DVAC
Rev. 1.0 / Nov. 2014 18
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
DDR3L-800, 1066, 1333, 1600
Symbol Parameter Unit Notes
Min Max
VIHdiff
VILdiff
VIHdiff (ac)
VILdiff (ac)
Differential input high
Differential input logic low
Differential input high ac
Differential input low ac
+ 0.180
Note 3
2 x (VIH (ac) - Vref)
Note 3
Note 3
- 0.180
Note 3
2 x (VIL (ac) - Vref)
V
V
V
V
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 28.
1
1
2
2
Allowed time before ringback
(tDVAC) for CK - CK and DQS - DQS
Slew Rate
[V/ns]
> 4.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
DDR3L-800/1066/1333/1600 tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 320mV tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 270mV
109
91
69
40
min
189
189
162 note note note
max
-
-
-
-
-
-
-
-
-
-
min
201
201
179
134
119
100
76
44 note note
max
-
-
-
-
-
-
-
-
-
62
37
5 note note
163
140
95
80
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 270mV min
163
max
-
-
-
-
-
-
-
-
-
DDR3L-1866 tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 250mV min
168
168
147
105
91
74
52
22 note note
max
-
-
-
-
-
-
-
-
-
78
56
24 note note
176
154
111
97
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 260mV min
176
max
-
-
-
-
-
-
-
-
note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
Rev. 1.0 / Nov. 2014 19
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) also has to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK.
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSELmax
VSEL
VSS or VSSQ time
Single-ended requirements for differential signals.
Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
Rev. 1.0 / Nov. 2014 20
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3L-800, 1066, 1333, 1600, 1866
Symbol Parameter Unit Notes
Min Max
VSEH
VSEL
Single-ended high level for strobes
Single-ended high level for Ck, CK
Single-ended low level for strobes
Single-ended low level for CK, CK
(VDD / 2) + 0.175
(VDD /2) + 0.175
Note 3
Note 3
Note 3
Note 3
(VDD / 2) - 0.175
(VDD / 2) - 0.175
V
V
V
V
Notes:
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 28.
1,2
1,2
1,2
1,2
Rev. 1.0 / Nov. 2014 21
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in table below. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS
Vix Definition
Cross point voltage for differential input signals (CK, DQS)
DDR3L-800, 1066, 1333, 1600, 1866
Symbol Parameter Unit Notes
Min Max
V
IX
(CK)
Differential Input Cross Point Voltage relative to VDD/2 for CK, CK
-150
-175
150
175 mV mV
V
IX
(DQS)
Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS
-150 150 mV 2
Notes:
1. Extended range for V
IX
is only allowed for clock and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -
CK is larger than 3 V/ns.
2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL 25mV
VSEH - ((VDD/2) + Vix (Max)) 25mV
2
1
Rev. 1.0 / Nov. 2014 22
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” in “DDR3L Device Operation” for single-ended slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” in “DDR3L Device Operation” for single-ended slew rate definition for data signals.
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table and figure below.
Differential Input Slew Rate Definition
Measured
Description
Defined by
Min
Max
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
V
V
ILdiffmax
IHdiffmin
V
V
IHdiffmin
ILdiffmax
[V
[V
IHdiffmin
-V
IHdiffmin
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
-V
ILdiffmax
] / DeltaTRdiff
ILdiffmax
] / DeltaTFdiff
Delta
TRdiff
V
IHdiffmin
0
V
ILdiffmax
Delta
TFdiff
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Rev. 1.0 / Nov. 2014 23
AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Single-ended AC and DC Output Levels
Symbol
V
OH(DC)
V
OM(DC)
V
OL(DC)
V
OH(AC)
V
OL(AC)
Notes:
Parameter
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output SR)
AC output low measurement level (for output SR)
DDR3L-800, 1066,
1333, 1600, 1866
0.8 x V
DDQ
0.5 x V
DDQ
0.2 x V
DDQ
V
TT
+ 0.1 x V
DDQ
V
TT
- 0.1 x V
DDQ
Unit
V
V
V
V
V
Notes
1
1
1. The swing of ±0.1 x V
DDQ
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 Ω and an effective test load of 25 Ω to V
TT
= V
DDQ
/ 2.
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Differential AC and DC Output Levels
DDR3L-800, 1066,
Symbol
V
OHdiff (AC)
V
OLdiff (AC)
Notes:
Parameter
AC differential output high measurement level (for output SR)
AC differential output low measurement level (for output SR)
1333, 1600, 1866
+ 0.2 x V
DDQ
- 0.2 x V
DDQ
Unit
V
V
Notes
1
1
1. The swing of ±0.2 x V
DDQ
is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 Ω and an effective test load of 25 Ω to V
TT
= V
DDQ
/2 at each of the differential outputs.
Rev. 1.0 / Nov. 2014 24
Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
OL(AC)
and V
OH(AC)
for single ended signals are shown in table and Figure below.
Single-ended Output slew Rate Definition
Measured
Description Defined by
From To
Single-ended output slew rate for rising edge
Single-ended output slew rate for falling edge
V
OL(AC)
V
OH(AC)
V
OH(AC)
V
OL(AC)
[V
OH(AC)
-V
OL(AC)
] / DeltaTRse
[V
OH(AC)
-V
OL(AC)
] / DeltaTFse
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse
V
OH(AC)
V
∏
V
Ol(AC)
Delta TFse
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
Parameter
DDR3L-800 DDR3L-1066DDR3L-1333DDR3L-1600DDR3L-1866
Units
Symbol Min Max Min Max Min Max Min Max Min Max
Single-ended Output Slew Rate SRQse 1.75
5
1)
1.75
5
1)
1.75
5
1)
1.75
5
1)
1.75
5
1)
V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals
For Ron = RZQ/7 setting
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular maximum limite of 5 V/ns applies.
Rev. 1.0 / Nov. 2014 25
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure below.
Differential Output Slew Rate Definition
Measured
Description Defined by
From To
Differential output slew rate for rising edge
Differential output slew rate for falling edge
Notes:
V
OLdiff (AC)
V
OHdiff (AC)
V
V
OHdiff (AC)
OLdiff (AC)
[V
[V
OHdiff (AC)
OHdiff (AC)
-V
-V
OLdiff (AC)
OLdiff (AC)
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
] / DeltaTRdiff
] / DeltaTFdiff
Delta
TRdiff
V
OHdiff(AC)
O
V
OLdiff(AC)
Delta
TFdiff
Differential Output slew Rate Definition
Differential Output Slew Rate
Parameter
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Units
Symbol Min Max Min Max Min Max Min Max Min Max
Differential Output Slew Rate SRQdiff 3.5
12 3.5
12
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals
For Ron = RZQ/7 setting
3.5
12 3.5
12 3.5
12 V/ns
Rev. 1.0 / Nov. 2014 26
Reference Load for AC Timing and Output Slew Rate
Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
CK, CK
DUT
DQ
DQS
DQS
25 Ohm
VTT = VDDQ/2
Reference Load for AC Timing and Output Slew Rate
Rev. 1.0 / Nov. 2014 27
Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter
DDR3
L-800
DDR3 DDR3 DDR3 DDR3
L-1066 L-1333 L-1600 L-1866
Units
Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4
0.4
0.4
0.4
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4
0.4
Maximum overshoot area above VDD (See Figure below) 0.67
0.5
0.4
0.4
0.4
0.4
V
V
0.4
0.33
0.28 V-ns
0.4
0.33
0.28 V-ns Maximum undershoot area below VSS (See Figure below) 0.67
0.5
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
Volts
(V)
VDD
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
Address and Control Overshoot and Undershoot Definition
Rev. 1.0 / Nov. 2014 28
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Parameter
DDR3
L-800
DDR3 DDR3 DDR3 DDR3
L-1066 L-1333 L-1600 L-1866
Units
Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4
0.4
0.4
0.4
0.4
V
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4
0.4
0.4
0.4
0.4
V
Maximum overshoot area above VDD (See Figure below) 0.25
0.19
0.15
0.13
0.11 V-ns
Maximum undershoot area below VSS (See Figure below)
(CK,
CK
, DQ, DQS,
DQS
, DM)
0.25
0.19
0.15
0.13
0.11 V-ns
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
Volts
(V)
VDDQ
VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
Rev. 1.0 / Nov. 2014 29
Refresh parameters by device density
Refresh parameters by device density
Parameter
REF command ACT or
REF command time
RTT_Nom Setting
tRFC
512Mb
90
1Gb
110
2Gb
160
4Gb
260
8Gb Units Notes
350 ns
Average periodic refresh interval tREFI
0
C
T
CASE
85
C 7.8
85
C
T
CASE
95
C 3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
us us
Notes:
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this materia.
Rev. 1.0 / Nov. 2014 30
Standard Speed Bins
DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3L-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin
CL - nRCD - nRP
Parameter
Internal read command to first data
Symbol
t
AA
min
DDR3L-800E
6-6-6 max
15 20
ACT to internal read or write delay time t
RCD
15 —
PRE command period t
RP
15 —
ACT to ACT or REF command period t
RC
52.5
—
ACT to PRE command period
CL = 6 CWL = 5
Supported CL Settings
Supported CWL Settings t
RAS t
CK(AVG)
37.5
2.5
6
5
9 * tREFI
3.3
Unit
ns ns ns ns ns ns n
CK n
CK
Notes
1,2,3
Rev. 1.0 / Nov. 2014 31
DDR3L-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin
CL - nRCD - nRP
Parameter Symbol
Internal read command to first data t
AA
ACT to internal read or write delay time t
RCD
min
13.125
13.125
DDR3L-1066F
7-7-7 max
20
—
PRE command period t
RP
ACT to ACT or REF command period t
RC
ACT to PRE command period t
RAS
CL = 6
CL = 7
CL = 8
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6 t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
Supported CL Settings
Supported CWL Settings
13.125
50.625
37.5
2.5
1.875
1.875
Reserved
Reserved
Reserved
6, 7, 8
5, 6
—
—
9 * tREFI
3.3
< 2.5
< 2.5
Unit
ns ns ns ns ns ns ns ns ns ns ns n
CK n
CK
Note
1,2,3,6
1,2,3,4
4
1,2,3,4
4
1,2,3
Rev. 1.0 / Nov. 2014 32
DDR3L-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin
CL - nRCD - nRP
Parameter Symbol
Internal read command to first data t
AA
ACT to internal read or write delay time t
RCD
PRE command period t
RP
min
13.5
(13.125)
5,10
13.5
(13.125)
5,10
13.5
(13.125)
5,10
49.5
(49.125)
5,10
DDR3L-1333H
9-9-9 max
20
—
—
—
ACT to ACT or REF command period t
RC
ACT to PRE command period
CL = 6
CWL = 5
CWL = 6
CWL = 7
CWL = 5 t
RAS t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
36
2.5
9 * tREFI
CL = 7 CWL = 6 t
CK(AVG)
CL = 8
CL = 9
CL = 10
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5, 6
CWL = 7
CWL = 5, 6
CWL = 7 t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
Supported CL Settings
Supported CWL Settings
1.875
1.875
1.5
1.5
3.3
Reserved
Reserved
Reserved
< 2.5
(Optional)
5,10
Reserved
Reserved
< 2.5
Reserved
Reserved
<1.875
Reserved
(Optional)
6, 7, 8, 9, 10
<1.875
5, 6, 7
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns n
CK n
CK
Note
1,2,3,7
1,2,3,4,7
4
4
1,2,3,4,7
1,2,3,4
4
1,2,3,7
1,2,3,4
4
1,2,3,4
4
1,2,3
5
Rev. 1.0 / Nov. 2014 33
DDR3L-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin
CL - nRCD - nRP
Parameter Symbol
Internal read command to first data t
AA
ACT to internal read or write delay time t
RCD
PRE command period t
RP
min
13.75
(13.125)
5,10
13.75
(13.125)
5,10
13.75
(13.125)
5,10
48.75
(48.125)
5,10
DDR3L-1600K
11-11-11 max
20
—
—
—
ACT to ACT or REF command period t
RC
ACT to PRE command period
CL = 6
CWL = 5
CWL = 6
CWL = 7
CWL = 5 t
RAS t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
CL = 7
CL = 8
CL = 9
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
CWL = 7
CL = 10
CL = 11
CWL = 8
CWL = 5, 6
CWL = 7
CWL = 8
CWL = 5, 6,7
CWL = 8 t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
Supported CL Settings
Supported CWL Settings t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
35
2.5
1.875
1.875
1.5
1.5
1.25
9 * tREFI
3.3
Reserved
Reserved
Reserved
< 2.5
(Optional)
5,10
Reserved
Reserved
Reserved
< 2.5
Reserved
Reserved
Reserved
(Optional)
5,10
Reserved
Reserved
<1.875
<1.875
Reserved
Reserved
<1.5
5, 6, 7, 8, 9, 10, 11
5, 6, 7, 8
Rev. 1.0 / Nov. 2014
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns n
CK n
CK ns ns ns
Note
1,2,3,8
1,2,3,4,8
4
4
1,2,3,4,8
1,2,3,4,8
4
4
1,2,3,8
1,2,3,4,8
1,2,3,4
4
1,2,3,4,8
1,2,3,4
4
1,2,3,8
1,2,3,4
4
1,2,3
34
DDR3L-1866 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 36.
Speed Bin
CL - nRCD - nRP
Parameter Symbol
Internal read command to first data t
AA
ACT to internal read or write delay time t
RCD
PRE command period t
RP
ACT to PRE command period t
RAS
ACT to ACT or PRE command period t
RC
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
CL = 12
CL = 13
CWL = 5
CWL = 6
CWL = 7,8,9
CWL = 5
CWL = 6
CWL = 7,8,9
CWL = 5
CWL = 6
CWL = 7
CWL = 8,9
CWL = 5, 6
CWL = 7
CWL = 8
CWL = 9
CWL = 5, 6
CWL = 7
CWL = 8
CWL = 5,6,7
CWL = 8
CWL = 9
CWL = 5,6,7,8
CWL = 9
CWL = 5,6,7,8
CWL = 9 t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
Supported CL Settings
Supported CWL Settings
min
13.91
(13.125)
13.91
5,11
(13.125)
13.91
5,11
(13.125)
5,11
DDR3L-1866M
13-13-13 max
20
—
—
34 9 * tREFI
47.91
(47.125)
5,11
2.5
1.875
1.875
1.5
1.5
1.25
1.07
-
3.3
Reserved
Reserved
Reserved
< 2.5
Reserved
Reserved
< 2.5
Reserved
Reserved
Reserved
<1.875
Reserved
Reserved
Reserved
<1.875
Reserved
Reserved
<1.5
Reserved
Reserved
Reserved
Reserved
<1.25
6, 7, 8, 9, 10, 11, 13
5, 6, 7, 8, 9
Rev. 1.0 / Nov. 2014
Unit
ns ns ns ns ns ns n
CK n
CK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
1,2,3,4,9
1,2,3,4,9
4
4
4
4
1,2,3,9
1,2,3,4,9
4
1,2,3,4,9
1,2,3,4
4
1,2,3,9
1,2,3,4,9
4
4
1,2,3,4,9
4
4
1,2,3,9
1,2,3,4,9
1,2,3,4
4
1, 2, 3
35
Speed Bin Table Notes
Absolute Specification (T
OPER
; V
DDQ
= V
DD
= 1.35V +0.100/- 0.067 V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
10. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
11. DDR3 SDRAM devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example, DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte 16), tRCDmin(byte 18) and tRPmin(byte 20) is programmed to 13.125ns, tRCmin(byte
21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin = 34ns +
13.125ns)
Rev. 1.0 / Nov. 2014 36
Environmental Parameters
Symbol
T
OPR
H
OPR
T
STG
H
STG
P
BAR
Parameter
Operating temperature (ambient)
Operating humidity (relative)
Storage temperature
Storage humidity (without condensation)
Barometric Pressure (operating & storage)
Rating
0 to +55
10 to 90
-50 to +100
5 to 95
105 to 69
Units Notes
o
C 3
% o
C
%
K Pascal
1
1
1, 2
Note
:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
Rev. 1.0 / Nov. 2014 37
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure below (Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements) shows the setup and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3L SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3L SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in the Figure below (Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ
Measurement). In DRAM module application, IDDQ cannot be measured separately since VDD and
VDDQ are using on merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
• ”0” and “LOW” is defined as VIN <= V
ILAC(max).
• ”1” and “HIGH” is defined as VIN >= V
IHAC(max).
• “MID_LEVEL” is defined as inputs are VREF = VDD/2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializing the DDR3L SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0
B
(Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
• Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 1.0 / Nov. 2014 38
I
DD
I
DDQ
(optional)
V
DD
RESET
CK/CK
CKE
CS
RAS, CAS, WE
A, BA
ODT
ZQ
V
SS
DDR3L
SDRAM
V
DDQ
DQS, DQS
DQ, DM,
TDQS, TDQS
R
TT
=
25 Ohm
V
DDQ
/2
V
SSQ
Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Application specific memory channel environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement
Rev. 1.0 / Nov. 2014 39
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol
t
CK
CL n
RCD n
RC n
RAS n
RP n
FAW
1KB page size
2KB page size n
RRD
1KB page size
2KB page size n
RFC
-512Mb n
RFC
-1 Gb n
RFC
- 2 Gb n
RFC
- 4 Gb n
RFC
- 8 Gb
DDR3L-1066
7-7-7
1.875
7
7
27
20
7
48
59
86
139
187
20
27
4
6
DDR3L-1333
9-9-9
1.5
9
9
33
24
9
60
74
107
174
234
20
30
4
5
DDR3L-1600
11-11-11
1.25
11
11
39
28
11
72
88
128
208
280
5
6
24
32
DDR3L-1866
13-13-13
1.07
13
13
45
32
13
85
103
150
243
328
5
6
26
33
Unit
nCK nCK nCK nCK ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
I
DD0
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8 a)
; AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
I
DD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8 a)
; AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 1.0 / Nov. 2014 40
Symbol
I
DD2N
Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Pattern Details: see Table 5.
Precharge Standby ODT Current
I
DD2NT
I
I
I
I
I
DD2P0
DD2P1
DD2Q
DD3N
DD3P
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit c)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit c)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Pattern Details: see
Table 5.
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0
Rev. 1.0 / Nov. 2014 41
Symbol
I
DD4R
Description
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registers b)
; ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
I
I
DD4W
DD5B
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registers b)
; ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8 a)
; AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registers b)
;
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
I
I
DD6
DD6ET
T
CASE
: 0 - 85 o
C; Auto Self-Refresh (ASR): Disabled d)
;Self-Refresh Temperature Range (SRT): Normal e)
; CKE:
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8 a)
; AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: MID_LEVEL
Self-Refresh Current: Extended Temperature Range
T
CASE
: 0 - 95 o
C; Auto Self-Refresh (ASR): Disabled d)
;Self-Refresh Temperature Range (SRT): Extended e)
;
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8 a)
; AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: MID_LEVEL
Rev. 1.0 / Nov. 2014 42
Symbol
I
DD7
Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8 a),f)
; AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Pattern
Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 1.0 / Nov. 2014 43
Table 3 - IDD0 Measurement-Loop Pattern a)
0
0
1,2
3,4
...
nRAS
...
1*nRC+0
1*nRC+1, 2
1*nRC+3, 4
...
1*nRC+nRAS
...
1 2*nRC
2 4*nRC
3 6*nRC
4 8*nRC
5 10*nRC
6 12*nRC
7 14*nRC
ACT 0 0 1 1 0 0 00 0 0 0
D, D 1 0 0 0 0 0 00 0 0
D, D 1 1 1 1 0 0 00 0 0 repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE 0 0 1 0 0 0 00 0 0
0
0
PRE 0 0 1 0 0 0 00 0 0 repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
0 repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT
D, D
0
D, D 1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
F repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
0
0
0
0
0
0
0
0 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Data b)
-
-
-
-
-
-
-
-
Rev. 1.0 / Nov. 2014 44
Table 4 - IDD1 Measurement-Loop Pattern a)
Data b)
0
0
1,2
3,4
...
nRCD
...
nRAS
...
1*nRC+0
1*nRC+1,2
1*nRC+3,4
...
1*nRC+nRCD
...
1*nRC+nRAS
...
1 2*nRC
2 4*nRC
3 6*nRC
4 8*nRC
5 10*nRC
6 12*nRC
7 14*nRC
ACT 0 0 1 1 0 0 00 0 0 0 0 -
D, D 1 0 0 0 0 0 00 0 0
D, D 1 1 1 1 0 0 00 0 repeat pattern 1...4 until nRCD - 1, truncate if necessary
0
RD 0 1 0 1 0 0 00 0 0 repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE 0 0 1 0 0 0 00 0 0
0
0
0
0
0
0
0 0 repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT 0
D, D 1
0
0
1
0
1
0
0
0
0
0
00 0
00 0
0
0
F
F
0
0
D, D 1 1 1 1 0 0 00 0 0 F 0 repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
-
-
00000000
-
-
-
-
RD 0 1 0 1 0 0 00 0 0 F 0 00110011 repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
0 PRE 0 0 1 0 0 0 00 0 0 F repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
Rev. 1.0 / Nov. 2014 45
Table 5 - IDD2N and IDD3N Measurement-Loop Pattern a)
0
0
1
2
3
1 4-7
2 8-11
3 12-15
4 16-19
5 20-23
6 24-17
7 28-31
D 1 0 0 0 0 0 0
D
D
D
1
1
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0 repeat Sub-Loop 0, use BA[2:0] = 1 instead
0
0
0 repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
0
0
0
0
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern a)
0
0
0
0
0
0
F
F
0
0
0
0
Data b)
-
-
-
-
0
0
1
2
3
1 4-7
2 8-11
3 12-15
4 16-19
5 20-23
6 24-17
7 28-31
D 1 0 0 0 0 0 0 0
D
D
D
1
1
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
0
0
0 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
0
0
0
0
0
0
F
F
0
0
0
0
Data b)
-
-
-
-
Rev. 1.0 / Nov. 2014 46
Table 7 - IDD4R and IDDQ4R Measurement-Loop Pattern a)
Data b)
0
0
1
2,3
4
5
6,7
1 8-15
2 16-23
3 24-31
4 32-39
5 40-47
6 48-55
7 56-63
RD 0 1 0 1 0
D
D,D
RD
D
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
0
D,D 1 1 1 1 0 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0 00000000
0
0
0 -
0 -
0 00110011
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Pattern a)
Data b)
0
0
1
2,3
4
5
6,7
1 8-15
2 16-23
3 24-31
4 32-39
5 40-47
6 48-55
7 56-63
WR 0 1 0 0 1
D
D,D
WR
1
1
0
0
1
1
0
1
0
0
1
0
1
1
1
D
D,D
1
1
0
1
0
1
0
1
1
1 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
00000000
0 -
0 -
0 00110011
-
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2014 47
Table 9 - IDD5B Measurement-Loop Pattern a)
0
0
1 1.2
3,4
5...8
9...12
13...16
17...20
21...24
25...28
29...32
2 33...nRFC-1
REF 0 0 0 1 0 0 0 0 0
D, D 1 0 0 0 0
D, D 1 1 1 1 0 repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6
0
0
00
00
0
0 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
0
0 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
0
0
F
0
0
0
Data b)
-
-
-
Rev. 1.0 / Nov. 2014 48
Table 10 - IDD7 Measurement-Loop Pattern a)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
Data b)
0 0
1
2
...
nRRD nRRD+1
1 nRRD+2
...
2 2*nRRD
3 3*nRRD
4
4*nRRD
5 nFAW
6 nFAW+nRRD
7 nFAW+2*nRRD
8 nFAW+3*nRRD
9 nFAW+4*nRRD
10
11
2*nFAW+0
2*nFAW+1
2&nFAW+2
2*nFAW+nRRD
2*nFAW+nRRD+1
2&nFAW+nRRD+2
12 2*nFAW+2*nRRD
13 2*nFAW+3*nRRD
14 2*nFAW+4*nRRD
15 3*nFAW
16 3*nFAW+nRRD
17 3*nFAW+2*nRRD
18 3*nFAW+3*nRRD
19 3*nFAW+4*nRRD
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0 repeat above D Command until nRRD - 1
ACT 0 0 1 1 0
RDA 0 1 0 1 0
0
0
0
1
1
00
00
00
00
00
00
0
1
0
0
1
0
0
0
0
0
0
0 D 1 0 0 0 0 1 repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3
D 1 0 0 0 0 3 00 0 0
Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6
F repeat Sub-Loop 1, but BA[2:0] = 7
D 1 0 0 0 0 7 00 0 0 F
Assert and repeat above D Command until 2* nFAW - 1, if necessary
F
F
F
0
0
0
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
Repeat above D Command until 2* nFAW + nRRD - 1
0
1
0
ACT
RDA
0
0
0
1
1
0
1
1
0
0
1
1
00
00
0
1
D 1 0 0 0 0 1 00 0
Repeat above D Command until 2* nFAW + 2* nRRD - 1
0
0
0
0
0
0
F
F
F
0
0
0 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3
D 1 0 0 0 0 3 00 0 0 0
Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7
D 1 0 0 0 0 7 00 0 0 0
Assert and repeat above D Command until 4* nFAW - 1, if necessary
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
00000000
-
-
00110011
-
-
00110011
-
-
00000000
-
-
-
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Nov. 2014 49
IDD Specifications (Tcase: 0 to 95
o
C)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec.
The actual measurements may vary according to DQ loading cap.
2GB, 256M x 64 U-DIMM: HMT425U6CFR6A
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
DDR3L 1066
132
168
52
64
40
40
52
112
84
368
380
520
40
52
620
DDR3L 1333
136
172
56
68
40
40
52
120
88
428
440
520
40
52
700
DDR3L 1600
140
176
60
76
40
40
56
124
88
500
488
520
40
52
720
DDR3L 1866
152
188
68
92
44
44
64
136
92
568
568
540
48
80
740 mA mA mA mA mA mA mA
Unit
mA mA mA mA mA mA mA mA
note
Rev. 1.0 / Nov. 2014 50
Module Dimensions
256Mx64 - HMT425U6CFR6A
4 x 3.00 0.10
Min 1.45
2 x
2.30 0.10
5.175
47.00
DETAIL-A
Front
SPD
DETAIL-B
128.95
133.35
Back
71.00
2 x
Max R0.70
2.50 0.10
17.30
9.50
30.00
Side
2.51mm Max
Detail - A
Note
:
Rev. 1.0 / Nov. 2014
1.27±0.10
1.00
Detail - B
2.50
FULL R
5.00
0.3~1.0
Units: millimeters
51
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