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Key Parameters
MT/s
DDR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
Grade
-G7
-H9
-PB
-Rd
tCK
(ns)
1.875
1.5
1.25
1.07
CAS
Latency
(tCK)
7
9
11
13
tRCD
(ns) tRP
(ns)
13.125
13.125
13.5
(13.125)*
13.5
(13.125)*
13.75
(13.125)*
13.75
(13.125)*
13.91
(13.125)*
13.91
(13.125)*
tRAS
(ns)
37.5
36
35
34
tRC
(ns)
50.625
49.5
(49.125)*
48.75
(48.125)*
47.91
(48.125)*
CL-tRCD-tRP
7-7-7
9-9-9
11-11-11
13-13-13
*
SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [Mbps]
CL9 CL10 CL11 CL12 CL13
Remark Grade
-G7
-H9
-PB
-RD
CL6
800
800
800
800
Address Table
CL7
1066
1066
1066
1066
CL8
1066
1066
1066
1066
1333
1333
1333
1333
1333
1333
1600
1600 1866
Refresh Method
Row Address
Column Address
Bank Address
Page Size
2GB(1Rx16)
8K/64ms
A0-A14
A0-A9
BA0-BA2
2KB
Rev. 1.0 / Nov. 2014 4
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Table of contents
- 3 Description
- 3 Feature
- 3 Ordering Information
- 4 Key Parameters
- 4 Speed Grade
- 4 Address Table
- 5 Pin Descriptions
- 6 Input/Output Functional Descriptions
- 8 Pin Assignments
- 10 On DIMM Thermal Sensor
- 10 Connection of Thermal Sensor
- 10 Temperature-to-Digital Conversion Performance
- 11 Functional Block Diagram
- 11 2GB, 256Mx64 Module(1Rank of x16)
- 12 Absolute Maximum Ratings
- 12 Absolute Maximum DC Ratings
- 12 DRAM Component Operating Temperature Range
- 13 AC & DC Operating Conditions
- 13 Recommended DC Operating Conditions
- 15 AC & DC Input Measurement Levels
- 15 AC and DC Input Levels for Single-Ended Command and Address Signals
- 16 AC and DC Input Levels for Single-Ended Signals
- 17 Vref Tolerances
- 18 AC and DC Logic Input Levels for Differential Signals
- 18 Differential signal definition
- 19 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- 20 Single-ended requirements for differential signals
- 22 Differential Input Cross Point Voltage
- 23 Slew Rate Definitions for Single-Ended Input Signals
- 23 Slew Rate Definitions for Differential Input Signals
- 24 AC & DC Output Measurement Levels
- 24 Single Ended AC and DC Output Levels
- 24 Differential AC and DC Output Levels
- 25 Single Ended Output Slew Rate
- 25 Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from l...
- 26 Differential Output Slew Rate
- 27 Reference Load for AC Timing and Output Slew Rate
- 28 Overshoot and Undershoot Specifications
- 28 Address and Control Overshoot and Undershoot Specifications
- 29 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
- 30 Refresh parameters by device density
- 31 Standard Speed Bins
- 31 DDR3L-800 Speed Bins
- 32 DDR3L-1066 Speed Bins
- 33 DDR3L-1333 Speed Bins
- 34 DDR3L-1600 Speed Bins
- 35 DDR3L-1866 Speed Bins
- 36 Speed Bin Table Notes
- 37 Environmental Parameters
- 38 IDD and IDDQ Specification Parameters and Test Conditions
- 50 IDD Specifications (Tcase: 0 to 95oC)
- 50 2GB, 256M x 64 U-DIMM: HMT425U6CFR6A
- 51 Module Dimensions
- 51 256Mx64 - HMT425U6CFR6A