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88SM9705
SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Marvell.
Moving Forward Faster
Doc No. MV-S109142-00 Rev. A
June 12, 2015
Document Classification: Proprietary
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
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June 12, 2015 Document Classification: Proprietary
Doc No. MV-S109142-00 Rev. A
Ordering Information
ORDERING INFORMATION
Ordering Part Numbers and Package Markings
The following figure shows the ordering part numbering scheme for the 88SM9705 part. For complete ordering information, contact your Marvell FAE or sales representative.
Figure 0-1 Sample Ordering Part Number
88XXXXX - XX - XXX - C000 - XXXX
Part Number
Extended Part Number
Product Revision
Custom Code
Package Code
3-character alphabetic code such as BCC, TEH
Custom Code
(optional )
Custom Code
Temperature Code
C = Commercial
I = Industrial
Environmental Code
+ = RoHS 0/6
– = RoHS 5/6
1 = RoHS 6/6
2 = Green)
The standard ordering part numbers for the respective solutions are indicated in the following table.
Ordering Part Numbers
Part Number
88SM9705A0-NNR2C000
88SM9705A0-NNR2I000
88SM9705A0-NNR2A000
Description
84-Pin 10 x 10 QFN Package, SATA 6.0 Gbps, One-to-Five Port Multiplier
84-Pin 10 x 10 Industrial Grade QFN Package, SATA 6.0 Gbps, One-to-Five Port
Multiplier
84-Pin 10 x 10 Automotive Grade QFN Package, SATA 6.0 Gbps, One-to-Five
Port Multiplier
The next figure shows a typical Marvell package marking.
Figure 0-2 88SM9705 Package Marking and Pin 1 Location
Country of origin
(contained in the mold ID or marked as the last line on the package)
Pin 1 location
88XXXXX-AAAe
Lot Number
YYWW xx@
Country of Origin
Marvell Logo
Part number, package code, environmental code e
XXXXX = Part number
AAA = Package code e = Environmental code
(+ = RoHS 0/6, no code = RoHS 5/6,
1 = RoHS 6/6, 2 = Green)
Date code, custom code, assembly plant code
YYWW = Date code (YY = year, WW = Work Week) xx = Custom code or die revision
@ = Assembly plant code
Note: The above drawing is not drawn to scale. The location of markings is approximate. Add-on marks are not represented. Flip chips vary widely in their markings and flip chip examples are not shown here. For flip chips, the markings may be omitted per customer requirement.
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
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Doc No. MV-S109142-00 Rev. A
Change History
CHANGE HISTORY
The following table identifies the document change history for Rev. A.
Document Changes *
Location Type Description Date
Global
Global
Global
Update
Update
Update
Update
Update
Update
Update
Added automotive grade part number 88SM9705A0-NNR2A000 to the
Ordering Part Numbers table.
Updated section 4.1, Board Schematic Example
as follows:
• Replaced schematic diagrams with updated versions.
Added an introduction sentence to all tables in the document.
May 6, 2015
April 7, 2015
Added GPIO registers.
Removed the following bullet item in section 2.1, General
:
“Full scan for high-production test coverage and PHY self-test.”
Added the following bullet item for 2.2, Functional
: “Supports SATA Port
Multiplier Rev. 1.2.”
Added section 9.5, Thermal Data
.
September
26, 2013
October 21,
2014
October 21,
2014
February
28,2013
September
14 2014
Parameter
Update
Corrected the default value of
[3:0]) from 5h to Vh. February 26,
2013
(
March 27,
2015
Page 8-42 Update
GPIO[18]_OUTPUT_SRC_SEL ( R3E4h [4:0]).
March 27,
2015
* The type of change is categorized as: Parameter, Revision, or Update. A Parameter change is a change to a spec value, a Revision change is one that originates from the chip Revision Notice, and an Update change includes all other document updates.
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
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Doc No. MV-S109142-00 Rev. A
Contents
CONTENTS
Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power Routes .................. 4-2
Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes ................... 4-3
UART INTERFACE ............................................................................................................................................ 6-1
UART ........................................................................................ 6-4
PORTS ............................................................................................................................................................... 7-1
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
ELECTRICAL SPECIFICATIONS ...................................................................................................................... 9-1
.................................................................................... 9-3
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Overview
1
OVERVIEW
The 88SM9705 is a SATA port multiplier that allows an active host connection to communicate with up to five device ports and one SEMB port. The 88SM9705 is used to consolidate the capacity of storage devices by allowing a single host SATA port to be connected to more than one SATA 6 gbps device.
Figure 1-1 illustrates a typical port multiplier configuration.
Figure 1-1 Overview (Five Port)
HDD
Host Bus Adapter
HDD
HDD
HDD
HDD
The 88SM9705 port multiplier employs Marvell SATA 6 Gbps Physical Layer (PHY) technology and recognizes the SATA-defined OOB sequence and speed-negotiation sequence on all of its SATA ports.
The 88SM9705 has programmable amplitude and pre-emphasis settings for a range of drive capabilities to support various backplane and cabling environments.The arbiter receives all the requests from the host port, the device ports, and the control port if these ports must transmit a FIS to the host port. The control port has the highest arbitration priority. The priority of the other ports is determined by a fair priority algorithm.
All device ports and the host port can be set up through the host port or UART interface to perform SATA self-tests at the same time.
The PHY Test module is specifically used to test the SATA PHY. All the test patterns are referenced from SATA Test Patterns and the High-Speed Serialized Attachment specification. For more information, see Serial ATA Revision 3.1 Specification
(http://www.sata-io.org).
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Figure 1-2 shows the 88SM9705 blocks.
Figure 1-2 88SM9705 Blocks
HT PORT
HT_PHY
SATA LINK
PORT5
SEMB
Port Multiplier Control
PORT0
SATA
LINK
PORT1
SATA
LINK
PORT2
SATA
LINK
PORT3
SATA
LINK
PORT4
SATA
LINK
P0_PHY P1_PHY P2_PHY P3_PHY P4_PHY
1-2
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Doc No. MV-S109142-00 Rev. A
2
FEATURES
This chapter contains the following sections:
Features
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
2.1
General
55 nm CMOS technology.
Supports Serial ATA Revision 3.1 Specification, with communication speeds of 1.5 Gbps, 3
Gbps, and 6 Gbps on host and device ports.
1.0V, 1.8V, and 3.3V power.
84-pin QFN ePad package.
PHY test mode.
One host port.
Five device
Supports 25 MHz reference clock.
2-2
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General
Doc No. MV-S109142-00 Rev. A
Features
2.2
Functional
115200 bps UART access.
Spread-spectrum clocking transmission.
SATA BIST over host and device links.
Asynchronous notification.
NOP command to select PM port field (Marvell Specific Mode, optional).SPI interface for internal register programming.
Supports SATA Port Multiplier Rev. 1.2.
Functional
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Preliminary Specifications
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2-4
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Functional
Doc No. MV-S109142-00 Rev. A
3
PACKAGE
This chapter contains the following sections:
Package
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
3.1
Package Pin-Out
Figure 3-1 88SM9705 Package Pin-Out (84-Pin QFN)
GPIO19
GPIO18
GPIO17
GPIO16
GPIO4
GPIO3
VDD
GPIO2
GPIO1
VDDIO
GPIO0
SPI_DO
SPI_CS
VDD
SPI_DI
SPI_CLK
TESTMODE
PWR_ON_RST_N
GPIO15
GPIO14
GPIO13
82
83
84
79
80
81
64
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
65
66
41
40
67
68
39
38
69
70
37
36
71
72
35
34
73
74
33
32
75
76
88SM9705
31
30
77
78
29
28
27
26
25
24
9 10 11 12 13
23
14 15 16 17 18 19 20 21
22
1 2 3 4 5 6 7 8
VSS1
VAA1
TP
N/C
N/C
N/C
N/C
N/C
VDD
VDDIO
TST0
TST1
SDA
SCL
VDD
HT_LED/GPIO5
P0_LEDGPIO6
P1_LED/GPIO7
P2_LED/GPIO8
P3_LED/GPIO9
P4_LED/GPIO10
3-2
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Package Pin-Out
Doc No. MV-S109142-00 Rev. A
3.2
Package Dimensions
Figure 3-2 Mechanical Drawings
Package
Package Dimensions
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Figure 3-3 Mechanical Dimensions
3-4
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Package Dimensions
Doc No. MV-S109142-00 Rev. A
Package
3.3
Pin Descriptions
3.3.1
Pin Type Definitions
This section outlines the 88SM9705 pin descriptions. All signals ending with the letter N indicate an active-low signal. Pin type definitions are shown in the following table.
Table 3-1 Pin Type Definitions
Pin Type
I
I/O
O
PD
PU mA
5
Definition
Input and output
Input only
Output only
Internal pull-down resistor (50 k
Ω)
Internal pull-up resistor (50 k
Ω)
DC sink capability
5V tolerance
3.3.2
Pin List
P0_TXP
P0_TXN
P1_TXP
P1_TXN
P2_TXP
P2_TXN
P3_TXP
P3_TXN
P4_TXP
P4_TXN
HT_TXP
HT_TXN
Table 3-2 Serial ATA Interface Signals
Signal Name
Signal
Number
5
4
11
10
51
50
17
16
63
62
53
54
Type
O
O
O
O
O
O
O
O
O
O
O
O
Description
Serial ATA Transmitter Differential Outputs.
Pin Descriptions
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
P0_RXN
P0_RXP
P1_RXN
P1_RXP
P2_RXN
P2_RXP
P3_RXN
P3_RXP
P4_RXN
P4_RXP
HT_RXN
HT_RXP
Table 3-2 Serial ATA Interface Signals (continued)
Signal Name
Signal
Number
2
1
8
7
48
47
14
13
60
59
56
57
Type
I
I
I
I
I
I
I
I
I
I
I
I
Description
Serial ATA Receiver Differential Inputs.
Table 3-3 Chip Power-On Reset Signal
Signal Name
PWR_ON_RST_N
Signal
Number
81 I
Type Description
Chip Power on Reset.
Active Low.
Table 3-4 UART Two-Wire Serial Interface
Signal Name
UAO
UAI
SCL
SDA
Signal
Number
18
19
29
30
Type
I
O
I/O
I/O
Description
UART Data Output.
UART Data Input.
Serial Clock
Serial Data.
Table 3-5 Configuration and Test Pins
Signal Name
GPIO19
GPIO18
GPIO17
GPIO16
Signal
Number
64
65
66
67
Type
I/O
I/O
I/O
I/O
Description
General Purpose I/O 19.
General Purpose I/O 18.
General Purpose I/O 17.
General Purpose I/O 16.
3-6
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Pin Descriptions
Doc No. MV-S109142-00 Rev. A
Package
Table 3-5 Configuration and Test Pins (continued)
Signal Name
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
P4_LED/GPIO10
Signal
Number
82
83
84
20
21
22
Type
I/O
I/O
I/O
I/O
I/O
I/O
P3_LED/GPIO9
P2_LED/GPIO8
P1_LED/GPIO7
P0_LED/GPIO6
HT_LED/GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
TST0
TST1
23
24
25
26
27
68
69
71
72
74
32
31
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
General Purpose I/O 15.
General Purpose I/O 14.
General Purpose I/O 13.
General Purpose I/O 12.
General Purpose I/O 11.
Device Port 4 Link-up and Activity LED or
General Purpose I/O 10.
Device Port 3 Link-up and Activity LED or
General Purpose I/O 9.
Device Port 2 Link-up and Activity LED or
General Purpose I/O 8.
Device Port 1 Link-up and Activity LED or
General Purpose I/O 7.
Device Port 0 Link-up and Activity LED or
General Purpose I/O 6.
Host Port Link-up and Activity LED or General
Purpose I/O 5.
General Purpose I/O 4.
General Purpose I/O 3
General Purpose I/O 2.
General Purpose I/O 1.
General Purpose I/O 0.
Test Pin.
Test Pin.
Table 3-6 Reference Signals
Signal Name
ISET
Signal
Number
45
XTLOUT
XTLIN_OSC
43
44 I
I
Type
O
Description
Reference Current for Crystal Oscillator and PLL.
This pin must be connected to an external
6.04 k
Ω 1% resistor to the Ground.
Crystal Output.
Reference Clock Input.
It can be from crystal or oscillator.
Pin Descriptions
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Table 3-7 Power Pins
Signal
Name
HT_VAA
P0_VAA
P1_VAA
P2_VAA
P3_VAA
P4_VAA
VAA1
VSS1
P0_VSS
P1_VSS
P2_VSS
HT_VSS
VDDIO
VDD
Signal Number Type
55
49
15
9
3
61
41
42, 46
52
12
6
58
33, 73
28, 34, 70, 77
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Table 3-8 SPI Flash Interface Signals
Signal Name
SPI_DO
SPI_CLK
SPI_CS
SPI_DI
Signal
Number
75
79
76
78
Type
O
O
I
O
Description
1.8V Power Source for Host Port SATA PHY.
1.8V Power Source for Device Port 0 SATA PHY.
1.8V Power Source for Device Port 1 SATA PHY.
1.8V Power Source for Device Port 2 SATA PHY.
1.8V Power Source for Device Port 3 SATA PHY.
1.8V Power Source for Device Port 4 SATA PHY.
1.8V Power Source for Analog logic.
Ground for Analog Logic.
Ground for SATA PHY.
Ground for SATA PHY.
Ground for SATA PHY.
Ground for SATA PHY.
3.3 V Power Source for Digital IO.
1.0 V Power Source for Digital.
Description
Data Output of SPI Flash Interface.
Clock Output of SPI Flash Interface.
Mode Select of SPI Flash Interface.
Data Input of SPI Flash Interface.
Table 3-9 Test Mode Interface Signals
Signal Name
TESTMODE
TP
Signal
Number
80
40
Table 3-10 Pins Not Connected
Signal Name
N/C
Type
I
O
Signal
Number
Type
35, 36, 37, 38,
39
N/A
3-8
Copyright © 2015 Marvell
June 12, 2015
Description
Chip Test Mode.
Analog Test Point.
Description
Not Connected.
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Pin Descriptions
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Layout Guidelines
4
LAYOUT GUIDELINES
This chapter describes the system recommendations from the Marvell Semiconductor design and application engineers who work with the 88SM9705. It is written for those who are designing schematics and printed circuit boards for an 88SM9705-based system.
Whenever possible, the PCB designer must try to follow the suggestions provided in this chapter.
The information in this chapter is preliminary. Consult with Marvell Semiconductor design and application engineers before starting your PCB design.
The chapter contains the following sections:
, for package information.
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
4.1
Board Schematic Example
The board schematic consists of the major interfaces of the 88SM9705. Figure 4-1 shows an
example board schematic.
Figure 4-1 88M9705 Example Board Schematic
5 4 3 2 1
1V8
D
C1
22uF
C0805
FB1
Ferrite
FB2
Ferrite
C2
100nF
C0402
10V
C3
10nF
C0402
16V
VAA1
C6
100nF
C0402
10V
C7
10nF
C0402
16V
3V3
C8
100nF
C0402
10V
1V8_VAA2_1
C9
10nF
C0402
16V
C10
100nF
C0402
10V
C11
10nF
C0402
16V
3V3
U1
R1
R0402
6.04K-1%
XTLIN
0-5%
XTLOUT
R5
1M-5%
R3
C16 16pF
S_RXP_HT
S_RXN_HT
S_TXN_HT
S_TXP_HT
C0402
C0402
C0402
C0402
SATA host port
Interface signals
C12
C13
C14
C15
10nF
10nF
10nF
10nF
C_RXP_HT
C_RXN_HT
C_TXN_HT
C_TXP_HT
SATA_HT1
KEY
6
7
4
5
1
2
3
S-ATA
Y2 TXC - 7M25070024
25MHz
C23 16pF
S_TX0_P
S_TX0_N
S_RX0_N
S_RX0_P
C0402
C0402
C0402
C0402
C24
C25
C26
C27
10nF
10nF
10nF
10nF
C_TX0_P
C_TX0_N
C_RX0_N
C_RX0_P
KEY
5
6
7
3
4
1
2
S-ATA
SATA1
C
B
1V8
3V3
C288
100nF
C0402
10V
1
4
5
U3
SVIN
2
SGND
3
FB2
MODE2
PGND2
L9 1.0uH
SW2
3V3
C295
10uF
C0603
6.3V
C293
4.7uF
C0402
6.3V
88PG8211
SDI
EN1
15
14
SS_DONE
FB1
13
12
EN2
11
C294
4.7uF
C0402
6.3V
SW1
L10 1.0uH
R109
100K-5%
R0402
3V3
PWR_ON_RST_N
3V3
1V0
1V0
1V0
R108
10K-5%
R0402
C296
C292
100nF
C0402
10V
10uF
C0603
6.3V
R107
10K-5%
R0402
C291
100nF
C0402
10V
C116
10nF
C0402
16V
3V3
SPI_DO
SPI_CS_N
SPI_DI_J
SPI_CLK
R7
75
76
77
78
79
80
81
82
83
84
69
70
71
72
73
74
64
65
66
67
68
GPIO19
GPIO18
GPIO17
GPIO16
GPIO4
GPIO3
VDD
GPIO2
GPIO1
VDDIO
GPIO0
SPI_DO
SPI_CS
VDD
SPI_DI
SPI_CLK
TESTMODE
PWR_ON_RST_N
GPIO15
GPIO14
GPIO13
85
EPAD
A
3V3
C33
10nF
C0402
16V
1V8
C28
100nF
C0402
10V
FB3
Ferrite
5
C29
22uF
C0805
1V0
C17
100nF
C0402
10V
C30
10nF
C0402
16V
C18
10nF
C0402
16V
C31
10nF
C0402
16V
88SM9705
VSS1
VAA1
TP
N/C
N/C
N/C
N/C
N/C
VDD
VDDIO
TST0
TST1
SDA
SCL
VDD
HT_LED/GPIO5
P0_LED/GPIO6
P1_LED/GPIO7
P2_LED/GPIO8
P3_LED/GPIO9
P4_LED/GPIO10
37
36
35
34
33
32
42
41
40
39
38
31
30
29
28
27
26
25
24
23
22
VAA1
TP1
SDA
SCL
HT_LED
P0_LED
P1_LED
P2_LED
P3_LED
P4_LED
1V0
3V3
S_TX1_P
S_TX1_N
S_RX1_N
S_RX1_P
C0402 C36
C0402 C37
C0402
C0402
C38
C39
S_TX2_P
S_TX2_N
S_RX2_N
S_RX2_P
C0402
C0402
C40
C41
C0402
C0402
C42
C43
C19
100nF
C0402
10V
C20
10nF
C0402
16V
C21
100nF
C0402
10V
1V8_VAA2_2
C22
10nF
C0402
16V
TP3 TP2
3V3
R0402
3.01K-1%
R51
SDA
SCL
C34
100nF
C0402
10V
C32
100nF
C0402
10V
C35
22uF
C0805
3V3
C297
100nF
C0402
10V
8
7
3
4
U6
VCC
HOLD#
WP#
SO
SI
2
5
6
SCLK
Gnd CS#
MX25L4006E
1
R58
0-5%
R0402
SPI_DO
SPI_CLK
SPI_CS_N
Contact Marvell for SPI support list
4
SPI_DI_J
3
R80
10K-5%
R0402
HT_LED
P0_LED
P1_LED
P2_LED
P3_LED
P4_LED
GREEN
GREEN
GREEN
GREEN
GREEN
GREEN
+
+
+
+
+
+
LED_HT1
LED_SATA0
LED_SATA1
LED_SATA2
LED_SATA3
LED_SATA4
R169
R170
R171
R174
R183
R105
3V3
R0402
3.01K-1%
R50
I2C0
I2C2
1
1
2
2
3
3
22-05-5035
1K-5% R0402
1K-5%
1K-5%
1K-5%
1K-5%
1K-5%
R0402
R0402
R0402
R0402
R0402
2
3V3
S_TX3_P
S_TX3_N
S_RX3_N
S_RX3_P
C0402
C0402
C45
C46
C0402
C0402
C47
C48
S_TX4_P
S_TX4_N
S_RX4_N
S_RX4_P
C0402
C0402
C50
C51
C0402 C52
C0402 C53
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
10nF
C_TX1_P
C_TX1_N
C_RX1_N
C_RX1_P
C_TX2_P
C_TX2_N
C_RX2_N
C_RX2_P
C_TX3_P
C_TX3_N
C_RX3_N
C_RX3_P
C_TX4_P
C_TX4_N
C_RX4_N
C_RX4_P
1
KEY
3
4
1
2
5
6
7
S-ATA
SATA2
KEY
3
4
1
2
5
6
7
S-ATA
SATA3
KEY
5
6
7
3
4
1
2
S-ATA
SATA4
KEY
5
6
3
4
7
1
2
S-ATA
SATA5
D
C
B
A
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest schematics.
4.2
Layer Stack-Up
The recommended minimum requirements are 5-mil traces and 5-mil spacing.The following layer stack up is recommended:
Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power Routes
Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes
4.2.1
Layer 1–Topside, Parts, Slow and High Speed Signal Routes, and Power
Routes
All active parts are to be placed on the topside. Some of the differential pairs for SATA are routed on the top layer, differential 100
Ω impedance must be maintained for those high speed signals.
4-2
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Board Schematic Example
Doc No. MV-S109142-00 Rev. A
Layout Guidelines
4.2.2
Layer 2–Solid Ground Plane
A solid ground plane must be located directly below the top layer of the PCB. This layer must be a minimum distance below the top layer to reduce the amount of crosstalk and EMI. No cutouts must exist in the ground plane. It is recommended to use 1 ounce copper.
4.2.3
Layer 3–Power Plane
Use solid planes on layer 3 to supply power to the ICs on the PCB. Avoid narrow traces and necks on this plane.
4.2.4
Layer 4–Bottom Layer, Slow and High-Speed Signal Routes, and Power Routes
Some of the differential pairs for SATA are routed on the top layer, differential 100
Ω impedance must be maintained for those high speed signals. The high speed signals have the return current on the third layer, which is the power plane. No cut-out must exist under the signal path.
4.3
Power Supply
The 88SM9705 operates using the following power supplies:
Power-on-Reset Timing Requirement
4.3.1
VDD Power (1.0V)
All digital power pins (VDD pins) must be connected directly to a VDD plane in the power layer with short and wide traces to minimize digital power-trace inductances.
Use vias close to the VDD pins to connect to this plane and avoid using the traces on the top layer. Marvell recommends placing capacitors around the three sides of the PCB near VDD pins with the following dimensions:
1 nF (1 capacitor)
0.1 µF (2 capacitors)
2.2 µF (1 ceramic capacitor)
The 2.2 µF ceramic decoupling capacitor is needed to filter the lower frequency power-supply noise.
To reduce system noise, the use of high-frequency surface-mount monolithic ceramic bypass capacitors must be placed as close as possible to the channel VDD pins. At least one decoupling capacitor must be placed on each side of the IC package.
Power Supply
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Short and wide copper traces must be used to minimize parasitic inductances. Low-value capacitors (1,000–10,000 pF) are preferable over higher values because they are more effective at higher frequencies.
4.3.2
Analog Power Supply (1.8V)
The 1.8V power is for analog design of the chip.
4.3.3
VDDIO Power (3.3V)
The digital power (3.3V) is the power supply for the digital pad.
4.3.4
Power-on-Reset Timing Requirement
The minimum timing requirement for power on reset is 50 µs after all power supplies are stable and before the power-on-reset signal is released.
4.3.5
Bias Current Resistor (RSET)
This resistor must connect a 6.04 K
Ω (1%) resistor to the
ISET
pin and the adjacent top ground plane. It must lie as close as possible to the
ISET
pin.
4.4
PCB Trace Routing
The stack-up parameters for the reference board are shown in Table 4-1.
Table 4-1 PCB Board Stack-up Parameters
3
4
1
2
Layer
Layer
Description
Signal
GND
Power
Signal
Copper Weight
(oz)
Target Impedance
(±10%)
0.5
1
1
0.5
50
N/A
N/A
50
4.5
Recommended Layout
Solid ground planes are recommended. However, special care must be taken when routing
VAA and VSS pins.
The following general tips describe what must be considered when determining your stack-up and board routing. These tips are not meant to substitute for consulting with a signal-integrity expert or doing your own simulations.
Note: Specific numbers or rules-of-thumb are not used here because they might not be applicable in every situation.
4-4
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PCB Trace Routing
Doc No. MV-S109142-00 Rev. A
Layout Guidelines
Do not split ground planes.
Keep good spacing between possible sensitive analog circuitry on your board and the digital signals to sufficiently isolate noise. A solid ground plane is necessary to provide a good return path for routing layers. Try to provide at least one ground plane adjacent to all routing layers
Keep trace layers as close as possible to the adjacent ground or power planes.
This helps minimize crosstalk and improve noise control on the planes.
Figure 4-2 Trace Has at Least One Solid Plane for Return Path
GND
V2
V1
When routing adjacent to only a power plane, do not cross splits.
Route traces only over the power plane that supplies both the driver and the load. Otherwise, provide a decoupling capacitor near the trace at the end that is not supplied by the adjacent power plane.
Critical signals must avoid running parallel and close to or directly over a gap.
This would change the impedance of the trace.
Separate analog powers onto opposing planes.
This helps minimize the coupling area that an analog plane has with an adjacent digital plane.
For dual strip-line routing, traces must only cross at 90 degrees.
Avoid more than two routing layers in a row to minimize tandem crosstalk and to better control impedance.
Planes must be evenly distributed in order to minimize warping.
Calculating or modeling impedance must be made prior to routing.
This helps ensure that a reasonable trace thickness is used and that the desired board thickness is available. Consult with your board fabricator for accurate impedance.
Allow good separation between fast signals to avoid crosstalk.
Crosstalk increases as the parallel traces get longer.
Recommended Layout
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
When packages become smaller, route traces over a split power plane
Smaller packages force vias to become smaller, thereby reducing board thickness and layer counts, which might create the need to route traces over a split power plane. Some alternatives to provide return path for these signals are listed below.
Caution must be used when applying these techniques. Digital traces must not cross over analog planes, and vice-versa. All of these rules must be followed closely to prevent noise contamination problems that might arise due to routing over the wrong plane.
By tightly controlling the return path, control noise on the power and ground planes can be controlled.
Place a ground layer close enough to the split power plane in order to couple enough to provide buried capacitance, such as
SIG-PWR-GND
(see Figure 4-3). Return signals that
encounter splits in this situation simply jumps to the ground plane, over the split, and back to the other power plane. Buried capacitance provides the benefit of adding low inductance decoupling to your board. Your fabricator may charge for a special license fee and special materials. To determine the amount of capacitance your planes provide, use the following equation:
C = 1.249
•
10
– 13
•
E r
•
L
•
Where E
R
is the dielectric coefficient, L
• W represents the area of copper, and H is the separation between planes.
Provide return-path capacitors that connect to both power planes and jumps the split.
Place them close to the traces so that there is one capacitor for every four or five traces.
The capacitors would then provide the return path (see Figure 4-4).
Allow only static or slow signals on layers where they are adjacent to split planes.
Figure 4-3 shows the ground layer close to the split power plane.
Figure 4-3 Close Power and Ground Planes Provide Coupling for Good Return Path
V2 PLANE
H
V1 PLANE
GND PLANE
4-6
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Recommended Layout
Doc No. MV-S109142-00 Rev. A
Layout Guidelines
Figure 4-4 shows the thermal ground plane in relation to the return-path capacitor.
Figure 4-4 Suggested Thermal Ground Plane on Opposite Side of Chip
V2
V1
Recommended Layout
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Preliminary Specifications
THIS PAGE LEFT INTENTIONALLY BLANK
4-8
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Recommended Layout
Doc No. MV-S109142-00 Rev. A
General Purpose I/O Port Interface
5
GENERAL PURPOSE I/O PORT INTERFACE
This chapter contains the following sections:
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5-1
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
5.1
Overview
The 88SM9705 contains a 20-bit General Purpose Port Input/Output (GPIO) interface. The
GPIO interface provides the following features:
Each of the GPIO pins can be assigned to act as a general purpose input or output pin.
A dedicated register provides the GPIO input value.
A dedicated register provides the GPIO output value.
Each of the GPIO outputs can be programmed for the LED to blink approximately every
100 ms.
5-2
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Overview
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General Purpose I/O Port Interface
5.2
GPIO Normal Mode
Table 5-1 describes the function of the GPIO pins.
Table 5-1 GPIO Pin Default Functions
Pin Name
Default
Setting
GPIO0 PU
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
Default Function
Capable
Function
Source
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
Three-device-port mode: This function is Device 2 port link-up and activity LED
0: LED blink for RAID
Otherwise: General Purpose I/O
1: Notification
SDB sending pulse output, pulse (1 µs)
2: System alert level output
Selectable
Selectable Host port link-up and activity LED * LED blink for
RAID
Device 0 port link-up and activity
LED *
Device 1 port link-up and activity
LED *
LED blink for
RAID
LED blink for
RAID
Selectable
Selectable
Device 2 port link-up and activity
LED *
Device 3 port link-up and activity
LED *
General Purpose I/O
LED blink for
RAID
LED blink for
RAID
LED blink for
RAID
LED blink for
RAID
Selectable
Selectable
Selectable
Selectable
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
LED blink for
RAID
LED blink for
RAID
LED blink for
RAID
LED blink for
RAID
LED blink for
RAID
LED blink for
RAID
LED blink for
RAID
General
Purpose I/O
Selectable
Selectable
Selectable
Selectable
Selectable
Selectable
Selectable
N/A
Description
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
Multiple blink frequency
GPIO Normal Mode
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5-3
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Table 5-1 GPIO Pin Default Functions (continued)
Pin Name
Default
Setting
GPIO16 PU
Default Function
System alert level output
Capable
Function
General
Purpose I/O
Source
N/A
GPIO17
GPIO18
PU
PU
General Purpose I/O
General Purpose I/O
General
Purpose I/O
N/A
Power management:
POW_OIT
N/A
GPIO19 PU General Purpose I/O Power management:
POW_IN
* The link up and activity can be separated and selectable for the blink source.
N/A
Description
Send level when system alert condition is met
N/A
N/A
N/A
5-4
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GPIO Normal Mode
Doc No. MV-S109142-00 Rev. A
General Purpose I/O Port Interface
5.3
GPIO Sample-at-Reset Pins
During chip reset, the method of using the GPIO pins to set the chip operation to the normal functional mode is called sample at reset. This method is activated when the
RST_N
input rises from low to high and is deactivated four reference cycles later. For example, if the reference cycle is 40 ns, the total time for deactivation is 4 x 40 ns = 160 ns.
Figure 5-1 shows the sample-at-reset timing.
Figure 5-1 Sample-at-Reset Timing
XTLIN_OSC
RST_N
GPIO0~5
Sample-At-Reset
During sample at reset, the signal levels of the GPIO pins must be kept stable so the chip can reliably sample the values. After the sample at reset is deactivated, the GPIO pins can switch to other functions and the chip stops sampling GPIO pins. The sampled values are
stored in the internal signals as shown in Table 5-2.
Table 5-2 Sample-at-Reset Signal Descriptions
Pin Name Function
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
Legacy Host Enable.
0h:
Legacy Host mode is disabled
1h:
Legacy Host mode is enabled
SEMB Disable.
0h:
SEMB is enabled
1h:
SEMB is disabled.
12C Speed-Up Disable.
0h:
I2C speed-up enabled.
1h:
I2C speed-up disabled.
PHY SSC Disable.
0h:
SATA host and device port SSC enabled.
1h:
SATA PHY SSC disabled
PLL SSC Disable.
0h:
System PLL SSC enabled.
1h:
System PLL SSC disabled.
PM Lock Disable.
0h:
PM Lock enabled.
1h:
PM Lock disabled
NOP Select Disable.
0h:
NOP command selection enabled
1h:
NOP command selection disabled
GPIO Sample-at-Reset Pins
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5-5
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Table 5-2 Sample-at-Reset Signal Descriptions (continued)
Pin Name Function
GPIO7
GPIO8
All Ports Disable.
0h:
All ports enabled
1h:
All ports disabled
8K FIFO Disable.
0h:
Device port 8K FIFO enabled
1h:
Device port 8K FIFO disabled
5-6
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GPIO Sample-at-Reset Pins
Doc No. MV-S109142-00 Rev. A
6
UART INTERFACE
This chapter contains the following sections:
Register Access Sequence Through UART
UART Interface
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6-1
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
6.1
UART Interface Overview
The 88SM9705 has one 115200 bps UART interface.
The UART interface is used to access internal registers, including those for the SATA status and SATA debug registers of each port. The UART interface is not required for normal operation. At the fixed baud rate of 115200 bps, the UART interface block is used mostly for debugging purposes. If the UART pins are not used, then all UAI pins must be left high for normal operation.
6-2
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UART Interface Overview
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6.2
UART Interface Timing
Figure 6-1 illustrates an example of UART signal timing.
Figure 6-1 UART Signal Timing Example
1 Character
D0 D1 D2 D3 D4 D5 D6 D7
UART Interface
UART Interface Timing
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
6.3
Register Access Sequence Through UART
This section describes the register access sequence through the UART. Figure 6.2 shows
the write command format.
Figure 6-2 Write Command Format
CMD BYTE 3 BYTE 2 BYTE 1 BYTE 0 BYTE 3 BYTE 2 BYTE 1 BYTE 0
CMD = W (register write)
Four-byte address
Four-byte data
Following are the parameters of the write command format:
A carriage return (CR) character and a line feed (LF) character are required after a
WRITE command for command execution.
A zero, a carriage return, and a line feed are returned if the command executes correctly.
A question mark (“?”), a carriage return, and a line feed are returned if an error is encountered.
All alphabetic characters must be in upper case. The backspace character is not recognized.
For example: W12AD34DF23 + CR + LF means write the value of AS34DF23h to the location R12h. If the UART returns 0 + CR + LF, then the command executed properly. If the
UART returns ? + CR + LF, then the command did not execute properly. Figure 6.3 shows
the read command format.
Figure 6-3 Read Command Format
CMD ADDR
CMD = R (register read)
One-byte address
Following are the parameters of the
READ
command format:
The carriage return and line feed characters are required after a
READ
command.
The register value, carriage return, and line feed characters are returned if the command executes correctly.
A question mark (“?”), carriage return, and line feed characters are returned if an error is encountered.
All alphabetic characters must be in upper case. The backspace character is not recognized.
For example, R12h + CR + LF means read from R12h. If the register value + CR + LF is returned, then the read command executed properly. If ? + CR + LF is returned from the
UART, then the command did not execute properly.
6-4
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Register Access Sequence Through UART
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UART Interface
6.3.1
UART Read/Write Command Sequences
Each UART sequence includes the parity bit in the last bit. Table 6-1 through Table 6-4, Write
Command, Error detail the register Read/Write sequences for Read and Write commands,
with and without errors.
Table 6-1 describes the registers read command sequence when no errors are returned.
Table 6-1 Read Command, No Error
Byte Master
6
7
4
5
1
2
3
CMD(R)
ADDR[31:24]
ADDR[23:16]
ADDR[15:8]
12
13
14
15
8
9
ADDR[7:0]
10 CR
11 LF
-
-
16
17
18
19
20 -
21 -
-
-
-
-
-
-
-
Slave
-
-
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
CR
LF
Value
52h
ASCII (ADDR[31:28])
ASCII (ADDR[27:24])
ASCII (ADDR[23:20])
ASCII (ADDR[19:16])
ASCII (ADDR[15:12])
ASCII (ADDR[11:8])
ASCII (ADDR[7:4])
ASCII (ADDR[3:0])
0Dh
0Ah
ASCII (DATA[31:28])
ASCII (DATA[27:24])
ASCII (DATA[23:20])
ASCII (DATA[19:16])
ASCII (DATA[15:12])
ASCII (DATA[11:8])
ASCII (DATA[7:4])
ASCII (DATA[3:0])
0Dh
0Ah
Table 6-2 describes the registers read command sequence when errors are returned.
Table 6-2 Read Command, Error
Byte Master
6
7
4
5
2
3
1 CMD(R)
ADDR[31:24]
ADDR[23:16]
ADDR[15:8] -
-
-
-
Slave Value
52h
ASCII (ADDR[31:28])
ASCII (ADDR[27:24])
ASCII (ADDR[23:20])
ASCII (ADDR[19:16])
ASCII (ADDR[15:12])
ASCII (ADDR[11:8])
Register Access Sequence Through UART
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Table 6-2 Read Command, Error (continued)
Byte Master Slave Value
8
9
ADDR[7:0]
10 CR
11 LF
12
13 -
14 -
-
-
-
?
CR
LF
ASCII (ADDR[7:4])
ASCII (ADDR[3:0])
0Dh
0Ah
3Fh
0Dh
0Ah
Table 6-3 describes the registers write command sequence when no errors are returned.
Table 6-3 Write Command, No Error
6
7
4
5
1
2
3
Byte Master
CMD(W)
ADDR[31:24]
16
17
18
19
20
21
22
12
13
14
15
8
9
10
11
-
-
-
ADDR[23:16]
ADDR[15:8]
ADDR[7:0]
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
CR
LF
-
-
-
-
-
-
-
-
-
Slave
-
-
0
CR
LF
Value
57h
ASCII (ADDR[31:28])
ASCII (ADDR[27:24])
ASCII (ADDR[23:20])
ASCII (ADDR[19:16])
ASCII (ADDR[15:12])
ASCII (ADDR[11:8])
ASCII (ADDR[7:4])
ASCII (ADDR[3:0])
ASCII (DATA[31:28])
ASCII (DATA[27:24])
ASCII (DATA[23:20])
ASCII (DATA[19:16])
ASCII (DATA[15:12])
ASCII (DATA[11:8])
ASCII (DATA[7:4])
ASCII (DATA[3:0])
0Dh
0Ah
30h
0Dh
0Ah
6-6
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Register Access Sequence Through UART
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UART Interface
Table 6-4 describes the registers write command sequence when errors are returned.
Table 6-4 Write Command, Error
6
7
4
5
1
2
3
Byte Master
CMD(W)
ADDR[31:24]
20
21
22
16
17
18
19
12
13
14
15
8
9
10
11
-
-
-
ADDR[23:16]
ADDR[15:8]
ADDR[7:0]
DATA3
DATA2
DATA1
DATA0
CR
LF
-
-
-
-
-
-
-
-
-
Slave
-
-
?
CR
LF
Value
57h
ASCII (ADDR[31:28])
ASCII (ADDR[27:24])
ASCII (ADDR[23:20])
ASCII (ADDR[19:16])
ASCII (ADDR[15:12])
ASCII (ADDR[11:8])
ASCII (ADDR[7:4])
ASCII (ADDR[3:0])
ASCII (BYTE3 [7:4])
ASCII (BYTE3[3:0])
ASCII (BYTE2 [7:4])
ASCII (BYTE2[3:0])
ASCII (BYTE1 [7:4])
ASCII (BYTE1[3:0])
ASCII (BYTE0 [7:4])
ASCII (BYTE0[3:0])
0Dh
0Ah
3Fh
0Dh
0Ah
Register Access Sequence Through UART
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Preliminary Specifications
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Register Access Sequence Through UART
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7
PORTS
This chapter contains the following sections:
Ports
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
7.1
PM_PORT Field
For the 88SM9705 to function, the host must be able to select each SATA device that is connected to the 88SM9705. To accomplish this, the
PM_PORT field has been added to all
SATA FISes (see Table 7-1). Before the introduction of the port multiplier, these bits had been
defined as reserved bits. If the host is port multiplier–enabled, then after the port multiplier’s detection and initialization process, the host is able to access each device by changing the value of the
PM_PORT
field.
Table 7-1 First Dword of All FIS Types
Byte Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
Dword 0 (As defined in Serial ATA 3.1 Specification) PM_PORT
Value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
6 5
0 1
4 3
FIS Type
2
0 1 1
1
1
0
0
Figure 7-1 shows an example of communication between a port multiplier–enabled host and
the port multiplier (PM).
Figure 7-1 Traffic Between a Port Multiplier-Aware Host and the Port Multiplier
Host PM
Device on
PM Port 3
FIS 27 (H2D Reg)
Write DMA,
PM_PORT = 3
FIS 27 (H2D Reg)
Write DMA,
PM_PORT =0
FIS 39 (DMA Active)
PM_PORT = 0
FIS 39 (DMA Active)
PM_PORT = 3
7.2
Control Ports
Each port multiplier has a control port that provides some device information—such as the connection status (S-Status), SATA Error (S-Error), and the supported port numbers—to the host. The control port also provides the host with some form of control over the devices. For example, the host can tell the port multiplier to disconnect a port or to engage in SATA BIST activity.
To the host, the control port functions exactly the same as a series of registers.
Port multiplier registers are categorized into the following types:
7-2
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PM_PORT Field
Doc No. MV-S109142-00 Rev. A
Ports
General Status and Control Registers (GSCR)
Port Status and Control Registers (PSCR).
Each port multiplier has only one set of GSCR and one set of PSCR for each port.
For more information on the GSCR and PSCR registers, see Chapter 8, Registers
.
The host can access the port multiplier’s control port as port Fh by using the
READ BUFFER
(E4h) and
WRITE BUFFER
(E8h) ATA commands. See section 8.1.1, Register Access from
for more detail on how these ATA commands can be used with the port
multiplier.
7.3
Cascading
The port multiplier should not be cascaded. Do not connect a port multiplier to another port multiplier.
Cascading
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Preliminary Specifications
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Cascading
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8
REGISTERS
This chapter contains the following sections:
Registers
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
8.1
Register Summary
This section contains the following subsections:
Register Access from Host and UART
General Status and Control Registers
Vendor-Specific Port Multiplier Control Registers
Host Port PHY Event Counter Registers
General Purpose Input/Output (GPIO) Registers
Device Port PHY Event Counter Registers
8.1.1
Register Access from Host and UART
Registers can be accessed from either the host (SATA) or the UART.
8.1.1.1
Accessing from the Host
All registers are accessed from the host (SATA) with an address that uses a combination of
the port number and an offset, as described in Table 8-1
Table 8-1 Access Registers from Host (SATA)
4
5
3
4
2
3
1
2
0
1
F
0
F
F
F
F
Port
Number
Address Range
00h–7Fh
80h–FFh
100h–1FFh
200h–2FFh
300h–3FFh
00h–FFh
100h–1FFh
00h–FFh
100h–1FFh
00h–FFh
100h–1FFh
00h–FFh
100h–1FFh
00h–FFh
100–1FFh
00–FFh
Register Description
General Purpose Status and Control
Vendor Specific
Host Port PHY Event
Host Port
GPIO
Device 0 Port
Device 0 Port PHY Event
Device 1 Port
Device 1 Port PHY Event
Device 2 Port
Device 2 Port PHY Event
Device 3 Port
Device 3 Port PHY Event
Device 4 Port
Device 4 Port PHY Event
SEMB
8-2
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Register Summary
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Registers
Example: Port Multiplier Register Read
To read PM port 2 register 01h, a port multiplier
READ
command (E4h) is issued to the port
multiplier, as shown in Table 8-2:
Table 8-2 PM Read Register
DWORD
DW0
DW1
DW2
DW3
DW4
[31:24] [23:16] [15:8]
Feature[7:0]
Reg address[7:0]
= 01h
Device
Command
E4h
LBA[23:16]
Port Num =
2
Reserved
Feature[15:8]
Reg address[15:8] =
00h
LBA[47:40]
Reserved
Control
Reserved
Auxiliary[31:24]
Reserved
C R R R
8
LBA[15:8]
Reserved
LBA[39:32]
Reserved
PM Port
F
ICC
Reserved
Count[15:8]
Reserved
Auxiliary[23:16] Auxiliary[15:8]
Reserved Reserved
[7:0]
FIS Type
27h
LBA[7:0]
Reserved
LBA[31:24]
Reserved
Count[7:0]
Reserved
Auxiliary[7:0]
Reserved
Note: FIS is the read Port Multiplier command.
Table 8-3 indicates that the port multiplier returns the read value of the specific register
(04050000h).
Table 8-3 PM Read Register Return
DWORD
DW0
DW1
DW2
DW3
[31:24]
Error
00h
Device
Reserved
Reserved
Reserved
Reserved
Reserved
[23:16]
Status
50h
LBA[23:16]
Value[31:24]
= 04h
LBA[47:40]
Reserved
Reserved
Reserved
DW4 Reserved
Reserved
Reserved
Reserved
Note: Register D2H FIS from Port Multiplier.
[15:8]
R I R R PM Port
4 F
LBA[15:8]
Value[23:16]
= 05h
LBA[39:32]
Reserved
Count[15:8]
Reserved
Reserved
Reserved
[7:0]
FIS Type
34h
LBA[7:0]
Value[15:8]
= 00h
LBA[31:24]
Reserved
Count[7:0]
Value[7:0]
= 00h
Reserved
Reserved
Register Summary
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Example: Port Multiplier Register Write
To write to PM port F register 90h with a value of CAFE1F1Fh, a PM
WRITE
command (E8h)
is issued to the PM as shown in Table 8-4.
Table 8-4 PM Write Register
DWORD
DW0
[31:24]
Feature[7:0]
Reg address[7:0]
= 90h
Device
Port = F
[23:16]
Command
E8h
DW1
DW2
DW3
DW4
Feature[15:8]
Reg address[15:8] =
00h
Control
Reserved
Auxiliary[31:24]
Reserved
LBA[23:16]
Value[31:24]
= CAh
LBA[47:40]
Reserved
ICC
Reserved
Auxiliary[23:16]
Reserved
Note: FIS is the write Port Multiplier command.
[15:8]
C R R R PM Port
8 F
LBA[15:8]
Value[23:16]
= FEh
LBA[39:32]
Reserved
Count[15:8]
Reserved
Auxiliary[15:8]
Reserved
[7:0]
FIS Type
27h
LBA[7:0]
Value[15:8]
= 1Fh
LBA[31:24]
Reserved
Count[7:0]
Value[7:0] = 1Fh
Auxiliary[7:0]
Reserved
8.1.1.2
Accessing from UART
All registers are accessed from UART with a base address of R00020xxxh.
The following items show read and write examples of accessing a General Purpose register with offset 58h:
Read—R00020058h
Write—W00020058A5A5A5A5 (write A5A5A5A5 to register 58h).
Table 8-5 shows the address offset ranges and descriptions for register access from UART.
Table 8-5 Register Access from UART
Offset Range Register Description
R000h–R07Fh General Status and Control
R080h–R0FFh Vendor-Specific
R1A0h–R1FFh GPIO
R300h–R3FFh
R400h–R4FFh
R500h–R5FFh
R600h–R6FFh
R700h–R7FFh
Host Port PHY Event
Device 0 Port
Device 0 Port PHY Event
Device 1 Port
Device 1 Port PHY Event
8-4
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Register Summary
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Table 8-5 Register Access from UART (continued)
Offset Range Register Description
R800h–R8FFh
R900h–R9FFh
RA00h–RAFFh
RB00h–RBFFh
Device 2 Port
Device 2 Port PHY Event
Device 3 Port
Device 3 Port PHY Event
RC00h–RCFFh
RD00h–RDFFh
Device 4 Port
Device 4 Port PHY Event
RE00h–REFFh SEMB
Registers
Register Summary
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
8.1.2
General Status and Control Registers
Table 8-6 General Purpose Status and Control Register Summary
Register Default Value Register Description
R021h
R022h
R060h
0400FFFFh
00000000h
Error Information Bit Enable
PHY Event Counter Control
00000001h Port Multiplier 1 X Feature Enable
8.1.3
Vendor-Specific Port Multiplier Control Registers
Table 8-7 Vendor-Specific PM Control Register Summary
Register Default Value Register Description
R083h
R084h
R086h
R091h
R093h
R0A0h
R0A1h
0000003Eh
00000000h
00002C2Bh
PM Lock Control
PM Lock Status
SEMB I2C Control
F81E003Ah
PLL 1
PLL 2
FIFO Size Control
00888888h
00000000h
00000000h
SATA Port PHY Control
Side Bank Address Register
Side Bank Data Register
8.1.4
Host Port PHY Event Counter Registers
Table 8-8 Host Port PHY Event Counter Register Summary
Register
R100h
Default Value Register Description
00000000h Host Port PHY Event Counter 1
8-6
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Location
Location
Register Summary
Doc No. MV-S109142-00 Rev. A
Location
Registers
8.1.5
General Purpose Input/Output (GPIO) Registers
Table 8-9 GPIO Register Summary
Register Default Value Register Description
R3A0h 00000000h
R3A4h 000107C0h
R3A8h 00000000h
R3ACh 00000000h
GPIO Data Out
GPIO Data Out Enable
GPIO Blink Enable
GPIO Data In Polarity
R3B0h 00000000h
R3C4h 2AF624C3h
GPIO Data In
GPIO [6] through GPIO [11] Port Source Select
R3C8h 047868C0h Power-Control
R3D8h 255AD6B5h GPIO [0] through GPIO [5] Port Source Select
R3E4h
R3E8h
R3ECh
000002B5h
00000041h
01041041h
R3F0h 01041041h
R3F4h 01041041h
R3F8h 01041041h
R3FCh 01041041h
GPIO[18] through GPIO[19] Port Source Select
Blink Rate Counter Register for SATA4 and Overall Link
Blink Rate Counter Register for SATA0/1/2/3/H
Blink Rate Counter Register for GPIO_OUT[4] through
GPIO_OUT[0]
Blink Rate Counter Register for GPIO_OUT[9] through
GPIO_OUT[5]
Blink Rate Counter Register for GPIO_OUT[14] through
GPIO_OUT[10]
Blink Rate Counter Register for GPIO_OUT[19] through
GPIO_OUT[15]
8.1.6
SATA PHY and Link Registers
This section includes the following sections:
SATA PHY—Low-Power SERDES PHY Registers
Location
Register Summary
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
8.1.6.1
Link Registers
Table 8-10 Link Register Summary
Register
Address
R00Eh
Default
Value
Register Description
00002001h PHY Reserved Input Control
8.1.6.2
SATA PHY—Low-Power SERDES PHY Registers
Table 8-11 SATA PHY—Low-Power SERDES PHY Register Summary
Register
Address
Default Value Register Description
R8Dh
R8Fh
C958h
AA62h
Generation 1 Setting 0
Generation 2 Setting 0
R91h 0BEBh Generation 3 Setting 0
8.1.7
Device Port PHY Event Counter Registers
Table 8-12 Device Port PHY Event Counter Register Summary
Register Default Value Register Description
R100h 00000000h
R101h 00000000h
Device Port PHY Event Counter 0
Device Port PHY Event Counter 2
Location
Location
Location
8.2
Register Map Summary
Table 8-13 General Status and Control Register Map Summary
Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7
6
5 4 3 2 1 0
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Register Map Summary
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Registers
Table 8-13 General Status and Control Register Map Summary (continued)
Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Table 8-14 Vendor-Specific Port Multiplier Control Register Map Summary
Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7 6 5 4 3
2
1
0
FIFO_SIZE_THRESH RSVD PM_CTL_FIFO_FLOW_CTL_THRSH
Table 8-15 Host Port PHY Event Counter Register Map Summary
Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Register Map Summary
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Table 8-17 GPIO Registers
Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7
6 5 4 3 2 1 0
RSVD GPIO[19:11]_BLINKING_EN GPIO[10:5]_BLINKING_DIS
GPIO_DATA_INPUT_POLARITY_BIT_MAP
Table 8-18 Link Register Map Summary
Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
8-10
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Register Map Summary
Doc No. MV-S109142-00 Rev. A
Registers
Table 8-19 SATA PHY—Low-Power SERDES PHY Register Map Summary
Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7 6
5 4 3 2
1 0
Table 8-20 Device Port PHY Event Counter Register Map Summary
Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
R100h DEV_PORT_PHY_EVENT_CNTR_0
R101h DEV_PORT_PHY_EVENT_CNTR_2
7 6 5 4 3 2 1 0
Register Map Summary
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
8.3
Register Description
This section contains the following subsections:
General Status and Control Registers
Vendor-Specific Port Multiplier Control Registers
Host Port PHY Event Counter Registers
Device Port PHY Event Counter Registers
8.3.1
General Status and Control Registers
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value V V V V V V V V V V V V V V V V 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 1
Bits Field Name
Read/
Write
Default
Value
Description
31:16 DEV_ID R VVVVh Product Identifier.
9705h: 1-to-5 Port Multiplier
15:0 VENDOR_ID R 1B4Bh Vendor Identifier.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0
Bits Field Name
Read/
Write
Default
Value
Description
31:16 RSVD
1
0
3
2
15:8
7:4
PM_REV
RSVD
SPT_PM_12
SPT_PM_S1
SPPRT_PM_10
RSVD
R
R
R
R
R
R
R
0000h Reserved.
Do not change the default value.
A0h
0h
Port Multiplier Revision.
Reserved.
1h
1h
1h
0h
Support for Port Multiplier Specification 1.2.
Support for Port Multiplier Specification 1.1.
Support for Port Multiplier Specification 1.0.
Reserved.
Do not change the default value.
8-12
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Register Description
Doc No. MV-S109142-00 Rev. A
Registers
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V V V V
Bits Field Name
Read/
Write
Default
Value
Description
31:4
3:0
RSVD
PORT_NUM
R
R
0000000h Reserved.
Vh Number of Exposed Device Fan Out Ports.
The default value is 6h if SEMB enabled and 5h if not enabled.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:5
4
3
2
1
0
RSVD
P4_SEL_BIT_PSCR_O
R
P3_SEL_BIT_PSCR_O
R
P2_SEL_BIT_PSCR_O
R
P1_SEL_BIT_PSCR_O
R
P0_SEL_BIT_PSCR_O
R
R
R
R
R
R
R
0000000h Reserved.
0h OR of Selectable Bits in Port 4 PSCR[1] (SError).
0h
0h
0h
0h
OR of Selectable Bits in Port 3 PSCR[1] (SError).
OR of Selectable Bits in Port 2 PSCR[1] (SError).
OR of Selectable Bits in Port 1 PSCR[1] (SError).
OR of Selectable Bits in Port 0 PSCR[1] (SError).
• Error Information Bit Enable
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits Field Name
Read/
Write
Default
Value
Description
31:0 ERR_INFO_BIT_EN R/W 0400FFFFh Error Information Bit Enable.
When this bit is enabled use Error Information
(
).
Register Description
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31 H_PORTH_GLBL_CNT
_RST
30:21 RSVD
20 P4_CNT_RST
19
18
17
16
15:1
0
P3_CNT_RST
P2_CNT_RST
P1_CNT_RST
P0_CNT_RST
RSVD
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
PHY_EVENT_CNT_EN R/W
0h
000h
0h
0h
Host Port Global Counter Reset.
0h:
No action is taken
1h:
Immediately resets all PHY event counters associated with the device port. After the reset is complete, this bit is cleared to 0h.
Reserved.
Port 4 Global Counter Reset.
0h:
No action is taken.
1h:
Immediately resets all PHY event counters associated with the device port. After the reset is complete, this bit is cleared to 0h.
Port 3 Global Counter Reset.
0h:
No action is taken.
1h:
Immediately resets all PHY event counters associated with the device port. After the reset is complete, this bit is cleared to 0h.
0h
0h
Port 2 Global Counter Reset.
0h:
No action is taken.
1h:
Immediately resets all PHY event counters associated with the device port. After the reset is complete, this bit is cleared to 0h.
Port 1 Global Counter Reset.
0h:
No action is taken.
1h:
Immediately resets all PHY event counters associated with the device port. After the reset is complete, this bit is cleared to 0h.
0h Port 0 Global Counter Reset.
0h:
No action is taken.
1h:
Immediately resets all PHY event counters associated with the device port. After the reset is complete, this bit is cleared to 0h.
0000h Reserved.
Do not change the default value.
0h PHY Event Counter Enabled.
0h:
All event counters stop counting and retain their current value.
1h:
Enable all PHY event counters.
8-14
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Register Description
Doc No. MV-S109142-00 Rev. A
Registers
• Port Multiplier Revision 1 X Features Support
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Bits Field Name
Read/
Write
Default
Value
Description
31:5
4
3
2
1
0
RSVD
SPT_PHY_CNT
SPT_NOTIFY
SPT_SSC
SPT_PMREQ
SPT_BIST
R
R
R
R
R
R
0000000h Reserved.
Do not change the default value.
1h Support PHY Event Counter.
0h:
Does not support PHY event counters.
1h:
Supports PHY event counters.
1h
1h
Support Asynchronous Notification.
This bit toggles asynchronous set bit device (SDB) notification.
0h:
Does not support SDB notification.
1h:
Supports SDB notification.
Support Dynamic SSC Transmit Enable.
This bit toggles support for dynamic spread spectrum clock
(SSC) transmission.
0h:
Does not support SSC transmit.
1h:
Supports SSC transmit.
1h
1h
Support PMREQp.
0h:
Does not support issuing a PMREQp to the host.
1h:
Supports issuing a PMREQp to the host.
Support BIST.
0h:
Does not support BIST.
1h:
Supports BIST.
• Port Multiplier 1 X Feature Enable
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:4 RSVD R 0000000h Reserved.
Do not change the default value.
Register Description
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Doc No. MV-S109142-00 Rev. A
Bits
3
2
1 PMREQP_EN
0
Field Name
NOTIFY_EN
SSC_EN
BIST_EN
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Read/
Write
R/W
R/W
R/W
R/W
Default
Value
0h
Description
0h
0h
1h
Asynchronous Notification Enable.
This bit enables asynchronous set bit device (SDB) notification.
0h:
Disable
1h:
Enable
SSC Enable.
This bit enables dynamic SSC transmitting.
0h:
Disable
1h:
Enable
PMREQ Enable.
This bit enables the issuing of PMREQp to the host.
0h:
Disable
1h:
Enable
BIST Support Enable.
0h:
Disable
1h:
Enable
8-16
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Registers
8.3.2
Vendor-Specific Port Multiplier Control Registers
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:30 RSVD
29 SEMB_MEMBIST_TES
T_FAIL
28
27
SEMB_MEMBIST_TES
T_FIN
PORT_4_MEMBIST_T
EST_FAIL
26
25
24
23
PORT_4_MEMBIST_T
EST_FIN
PORT_3_MEMBIST_T
EST_FAIL
PORT_3_MEMBIST_T
EST_FIN
PORT_2_MEMBIST_T
EST_FAIL
22
21
20
19
PORT_2_MEMBIST_T
EST_FIN
PORT_1_MEMBIST_T
EST_FAIL
PORT_1_MEMBIST_T
EST_FIN
PORT_0_MEMBIST_T
EST_FAIL
18
17
16
15:4
3
PORT_0_MEMBIST_T
EST_FIN
PM_CTL_MEMBIST_T
EST_FAIL
PM_CTL_MEMBIST_T
EST_FIN
RSVD
NOP_COM_EN
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
000h
0h
Reserved.
SEMB Memory BIST Test Fail.
SEMB Memory BIST Test Finish.
Port 4 Memory BIST Test Fail.
Port 4 Memory BIST Test Finish.
Port 3 Memory BIST Test Fail.
Port 3 Memory BIST Test Finish.
Port 2 Memory BIST Test Fail.
Port 2 Memory BIST Test Finish.
Port 1 Memory BIST Test Fail.
Port 1 Memory BIST Test Finish.
Port 0 Memory BIST Test Fail.
Port 0 Memory BIST Test Finish.
PM CTL Memory BIST Test Fail.
PM CTL Memory BIST Test Finish.
Reserved.
NOP Command Enable.
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-17
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits
2
1
0
Field Name
ALL_DEV_EN
HOST_DEV_INV
I2C_SPEED_SEL
Read/
Write
R
R
R
Default
Value
Description
0h
0h
0h
All Devices Enable.
Host Device Inversion.
I2C Speed Select.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:12 RSVD
11:8 PROBE_MON_SEL
7:4
3:0
PROBE_MOD_SEL
PROBE_SIG_SEL
R
R/W
R/W
R/W
00000h Reserved.
0h Probe Monitor Select.
0h
0h
Probe Module Select.
Probe Signal Select.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:16 RSVD
15:0 PROBE_SIG
R
R
0000h Reserved.
0000h Probe Signal.
8-18
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Registers
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0
Bits Field Name
Read/
Write
Default
Value
Description
31
30:6
5
LOCK_NOTIFY_EN R/W
R
R/W
0h Lock Notify Enable.
When this bit is set to 0, PM lock enable (PM lock control [0]) is set to 1, and some ports are in a locked state, the control port postpones sending SDB until no port is in the lock state.
0000000h Reserved.
1h Set Device BIT FIS Release Lock Enable.
4
3
2
1
0
RSVD
SET_DEV_BIT_FISRE
L_LOCK_EN
D2H_FIS_REL_LOCK_
EN
SET_DEV_BIT_FIS_L
OCK_EN
DMA_SETUP_FISLOC
K_EN
H2D_FIS_LOCK_EN
PM_LOCK_EN
R/W
R/W
R/W
R/W
R/W
1h
1h
1h
1h
0h
D2H FIS Release Lock Enable.
Set Device BIT FIS Lock Enable.
DMA Setup FIS Lock Enable.
H2D FIS Lock Enable.
PM Lock Enable.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:5
4
3:0
RSVD
PM_LOCK_VALID
PM_LOCK_PORT_ID
R
R
R
0000000h Reserved.
0h PM Lock Valid.
When this bit is set to 1, a port is in a locked state.
0h PM Lock Port ID.
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-19
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 1 1
Bits Field Name
Read/
Write
Default
Value
Description
31:29 RSVD
28 SEMB_INTR
27
15
14:8
7
6:0
SEMB_WR
26:24 SEMB_ADDR
RSVD
SEP_TWOWIRE_SERI
AL_ADD
RSVD
SEMB_TWOWIRE_SE
RIAL_ADD
R
R
R/W
R/W
23:16 SEMB_RD_WR_DATA R/W
R
R/W
R
R/W
0h
0h
0h
0h
00h
0h
2Ch
0h
2Bh
Reserved.
SEMB Interrupt.
Refer to the Two-Wire Serial IP specification for more detail.
SEMB Register Write.
SEMB_WR, SEMB_ADDR, and SEMB_RD_WR_DATA signals provide an interface for the software to program the
Two-Wire Serial register so that the software can control the interface of Two-Wire Serial.
Refer to the Two-Wire Serial IP Specification for more detail.
SEMB Register Address.
Refer to the Two-Wire Serial IP Specification for more detail.
SEMB Read Write Data.
Refer to the Two-Wire Serial IP Specification for more detail.
Reserved.
SEP Two-Wire Serial Address.
Reserved.
SEMB Two-Wire Serial Address.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:24 RSVD
23:0 SEMB_TO_VAL
R
R/W
00h Reserved.
900000h SEMB Time-Out Value.
SEMB time-out occurs when wait time larger than time-out value times cycle time.
8-20
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Registers
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31 RSVD
30:28 ANA_GROUP_TESTS
EL
R/W
R/W
27
26
ANA_GROUP_GAINX2 R/W
ANA_GROUP_BYPAS
S
R/W
25:24 ANA_GROUP_BG_SE
L
R/W
2
1
0
23:20 PLL_TEST_MON
19 PLL_SCC_RESET_EX
T
18:4
3
PLL_SCC_FREQ_DIV
PLL_SSC_GAINX2
R/W
R/W
R/W
R/W
PLL_SSC_MODE
PLL_PU_SSC
PLL_SSC_EN
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
Reserved.
Analog Group Test Select.
Analog Group Gain x2.
Analog Group Bypass.
Analog Group BG_SEL.
PLL Test Monitor.
PLL SCC Reset Extend.
0000h PLL SCC Frequency Divider.
0h PLL SSC Gain x2.
0h
0h
0h
PLL SSC Mode.
PLL Power Up SSC.
PLL SSC Enable.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Bits Field Name
Read/
Write
Default
Value
Description
7
6
31
30
PU_PLL
RSVD
29:16 PLL_SSC_RNG
15:8 RSVD
RSVD
RSVD
R/W
R/W
R/W
R
R
R
1h
0h
Power-Up PLL (Asynchronous Reset).
Reserved.
0000h PLL SSC Range.
00h Reserved.
0h
0h
Reserved.
Reserved.
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-21
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits
5
4
3
2
1
0
Field Name
SYSCLK_EN
SATA_DEV_4_CLK_E
N
SATA_DEV_3_CLK_E
N
SATA_DEV_2_CLK_E
N
SATA_DEV_1_CLK_E
N
SATA_DEV_0_CLK_E
N
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
Default
Value
Description
1h
1h
System Clock Enable.
SATA Device 4 Clock Enable.
1h
1h
1h
1h
SATA Device 3 Clock Enable.
SATA Device 2 Clock Enable.
SATA Device 1 Clock Enable.
SATA Device 0 Clock Enable.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0
Bits Field Name
Read/
Write
Default
Value
Description
31:27 FIFO_SIZE_THRESH_
SEL
26:16 FIFO_SIZE_THRESH
R/W
R/W
1Fh
01Eh
FIFO Size Threshold Select.
Selects the port FIFO size threshold that is to be read or written.
FIFO Size Threshold.
For received DATA FIS from all device ports, the PM stores the data in FIFO, then sends the data to the host if the amount of free space in the FIFO is less than the FIFO size threshold.
0h:
0x32
1h:
1x32
15:8
7:0
RSVD R
PM_CTL_FIFO_FLOW
_CTL_THRSH
R/W
00h
3Ah
1FFh: 511x32
Reserved.
Do not change the default value.
PM Control FIFO Flow Control Threshold.
For received DATA FIS from all device port, the PM stores the data into FIFO. when FIFO residue is less then this value, notify link layer to send HOLD
000h: 0 double word
001h: 1 double word
3Ah: 58 double word (default)
Fh: 255 double word
8-22
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Registers
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0
Bits Field Name
Read/
Write
Default
Value
Description
31:12 RSVD R
11:10 SEMB_1P_MEM_WTC R/W
9:8
7:6
SEMB_1P_MEM_RTC
PORT_2P_MEM_WTC
R/W
R/W
5:4
3:2
1:0
PORT_2P_MEM_RTC
PM_CTL_2P_MEM_W
TC
PM_CTL_2P_MEM_RT
C
R/W
R/W
R/W
00000h Reserved.
1h SEMB 1P Memory WTC.
2h
1h
SEMB 1P Memory RTC.
Device Port 2P Memory WTC.
2h
1h
Device Port 2P Memory RTC.
PM Control Port 2P Memory WTC.
2h PM Control Port 2P Memory RTC.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
10:8
7
6:4
3
2:0
31:24 RSVD
23 PORT4_PU
22:20 PORT4_SPD_SEL
19 PORT3_PU
18:16 PORT3_SPEED_SEL
15 PORT2_PU
14:12 PORT2_SPEED_SEL
11 PORT1_PU
PORT1_SPEED_SEL
PORT0_PU
PORT0_SPEED_SEL
HOST_PORT_PU
HOST_PORT_SPEED
_SEL
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
1h
0h
1h
00h
1h
0h
1h
0h
1h
0h
1h
0h
Reserved.
Port 4 Power Up.
Port 4 Speed Select.
Port3 Power Up.
Port3 Speed Select.
Port2 Power Up.
Port2 Speed Select.
Port 1 Power Up.
Port 1 Speed Select.
Port 0 Power Up.
Port 0 Speed Select.
Host Port Power Up.
Host Port Speed Select.
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-23
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31 SPI_MEM_ACCESS
30:28 RSVD
27:24 UNIT_SEL
23:0 MEM_ADD
R/W
R/W
R/W
R/W
0h
0h
Memory Access for SPI.
0h:
Other register access.
1h:
Read SPI memory.
Reserved.
Do not change the default value.
0h Unit Select.
0h:
SPI controller register
1h:
UART controller register
000000h Address for the Memory or Register.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:0 SIDE_BANK_ACCESS R/W 00000000h Data Register of Side Bank Access.
8-24
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Registers
8.3.3
Host Port PHY Event Counter Registers
• Host Port PHY Event Counter 1
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:0 PHY_EVENT_CNT_1 R/W 00000000h PHY Event Counter 1.
This register contains both the counter identifier and the counter value:
• Counter identifier: Read-only value 00002C01h.
• Counter: 32-bit counter, contains number of signature D2H register FISes that were transmitted to the host from the control port.
8.3.4
General Purpose Input/Output (GPIO) Registers
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:20 RSVD
19:0 GPIO[19:0]_DATA_OU
TPUT
R
R/W
000h Reserved.
00000h GPIO[19:0] Data Output.
When GPIO is in output mode, modify this register to control the output value.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31 OUTPUT_EN_POLARI
TY
30:20 RSVD
R
R
0h
000h
Output Enable Polarity.
0h:
Positive
1h:
Negative
Reserved.
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-25
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits
19:0
Field Name
GPIO_OUTPUT_EN
Read/
Write
R/W
Default
Value
Description
107C0h GPIO Output Enable.
GPIO 6, 7, 8, 9, 10, and 16 are enabled by default.
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:20 RSVD
19:11 GPIO[19:11]_BLINKIN
G_EN
10:5
4:0
GPIO[10:5]_BLINKING
_DIS
GPIO[4:0]_BLINKING_
EN
R
R/W
R/W
R/W
000h
000h
00h
00h
Reserved.
GPIO[19:11] Blinking Enable.
0h:
Disable
1h:
Enable
GPIO[10:5] Blinking Disable.
0h:
Enable
1h:
Disable
GPIO[4:0] Blinking Enable.
0h:
Disable
1h:
Enable
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
RSVD GPIO_DATA_INPUT_POLARITY_BIT_MAP
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:20 RSVD
19:0 GPIO_DATA_INPUT_P
OLARITY_BIT_MAP
R
R/W
000h Reserved.
00000h GPIO Data Input Polarity Bit Map.
0h:
Positive polarity
1h:
Negative polarity
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:20 RSVD
19:0 GPIO_INPUT_DATA_B
IT_MAP
R
R/W
000h Reserved.
00000h GPIO Input Data Bit Map.
8-26
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Registers
• GPIO [6] through GPIO [11] Port Source Select
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 1 0 1 0 1 0 1 1 1 1 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1
Bits Field Name
Read/
Write
Default
Value
Description
31:30 RSVD
29:25 GPIO[11]_OUTPUT_S
RC_SEL
R
R/W
0h
15h
Reserved.
GPIO [11] Output Source Select.
0h:
SATA 0_LINK and SATA 0_ACT or
SATA 1_LINK and SATA 1_ACT or
SATA 2_LINK and SATA 2_ACT or
SATA 3_LINK and SATA 3_ACT or
SATA 4_LINK and SATA 4_ACT
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[11]
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-27
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits Field Name
24:20 GPIO[10]_OUTPUT_S
RC_SEL
Read/
Write
R/W
Default
Value
0Fh
Description
GPIO [10] Output Source Select.
0h:
SATA 0_LINK and SATA 0_ACT or
SATA 1_LINK and SATA 1_ACT or
SATA 2_LINK and SATA 2_ACT or
SATA 3_LINK and SATA 3_ACT or
SATA 4_LINK and SATA 4_ACT
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[10]
8-28
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Bits Field Name
19:15 GPIO[9]_OUTPUT_SR
C_SEL
Read/
Write
R/W
Default
Value
0Ch
Description
GPIO [9] Output Source Select.
0h:
SATA 0_LINK and SATA 0_ACT or
SATA 1_LINK and SATA 1_ACT or
SATA 2_LINK and SATA 2_ACT or
SATA 3_LINK and SATA 3_ACT or
SATA 4_LINK and SATA 4_ACT
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[9]
Registers
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-29
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits Field Name
14:10 GPIO[8]_OUTPUT_SR
C_SEL
Read/
Write
R/W
Default
Value
09h
Description
GPIO [8] Output Source Select.
0h:
SATA 0_LINK and SATA 0_ACT or
SATA 1_LINK and SATA 1_ACT or
SATA 2_LINK and SATA 2_ACT or
SATA 3_LINK and SATA 3_ACT or
SATA 4_LINK and SATA 4_ACT
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[8]
8-30
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Bits
9:5
Field Name
GPIO[7]_OUTPUT_SR
C_SEL
Read/
Write
R/W
Default
Value
06h
Description
GPIO [7] Output Source Select.
0h:
SATA 0_LINK and SATA 0_ACT or
SATA 1_LINK and SATA 1_ACT or
SATA 2_LINK and SATA 2_ACT or
SATA 3_LINK and SATA 3_ACT or
SATA 4_LINK and SATA 4_ACT
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[7]
Registers
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-31
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits
4:0
Field Name
GPIO[6]_OUTPUT_SR
C_SEL
Read/
Write
R/W
Default
Value
03h
Description
GPIO [6] Output Source Select.
0h:
SATA 0_LINK and SATA 0_ACT or
SATA 1_LINK and SATA 1_ACT or
SATA 2_LINK and SATA 2_ACT or
SATA 3_LINK and SATA 3_ACT or
SATA 4_LINK and SATA 4_ACT
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[6]
• Power-Control Logic Time-Out Control Register
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:29 RSVD
28:0 TIMEOUT_CNTR_VAL
R
R/W
0h Reserved.
047868C0h Time-out Counter Value.
The time-out counter value based on 25 MHz clock.
8-32
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Registers
• GPIO [0] through GPIO [5] Port Source Select
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:30 RSVD
29:25 GPIO[5]_OUTPUT_SR
C_SEL
R
R/W
0h
12h
Reserved.
GPIO [5] Output Source Select.
0h:
SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT.
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT.
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK.
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[5]
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-33
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits Field Name
24:20 GPIO[4]_OUTPUT_SR
C_SEL
Read/
Write
R/W
Default
Value
15h
Description
GPIO [4] Output Source Select.
0h:
SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT.
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT.
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK.
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[4]
16h: Send SDB 1µs pulse output
17h: EM error
8-34
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Bits Field Name
19:15 GPIO[3]_OUTPUT_SR
C_SEL
Read/
Write
R/W
Default
Value
15h
Description
GPIO [3] Output Source Select.
0h:
SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT.
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT.
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK.
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[3]
Registers
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-35
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits Field Name
14:10 GPIO[2]_OUTPUT_SR
C_SEL
Read/
Write
R/W
Default
Value
15h
Description
GPIO [2] Output Source Select.
0h:
SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT.
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT.
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK.
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[2]
8-36
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Bits
9:5
Field Name
GPIO[1]_OUTPUT_SR
C_SEL
Read/
Write
R/W
Default
Value
15h
Description
GPIO [1] Output Source Select.
0h:
SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT.
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT.
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK.
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[1]
Registers
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-37
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits
4:0
Field Name
GPIO[0]_OUTPUT_SR
C_SEL
Read/
Write
R/W
Default
Value
15h
Description
GPIO [0] Output Source Select.
0h:
SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT.
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT.
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK.
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[0]
8-38
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Registers
• GPIO[12] through GPIO[17] Port Source Select
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:30 RSVD R
29:25 GPIO[17]_DATA_OUT R/W
24:20 GPIO16_OUTPUT_SR
C_SEL
R/W
19:15 GPIO[15]_DATA_OUT R/W
14:10 GPIO[14]_OUTPUT_S
RC_SEL
R/W
0h
15h
02h
15h
15h
Reserved.
GPIO [17] Data Out.
GPIO [16] Output Source Select.
2h:
System alert level output, em error output
15h: GPIO_DATA_OUT[16]
GPIO [15] Data Out.
GPIO [14] Output Source Select.
0h:
SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT.
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT.
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK.
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[14]
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-39
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits
9:5
Field Name
GPIO[13]_OUTPUT_S
RC_SEL
Read/
Write
R/W
Default
Value
15h
Description
GPIO [13] Output Source Select.
0h:
SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT.
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT.
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK.
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[13]
8-40
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Bits
4:0
Field Name
GPIO[12]_OUTPUT_S
RC_SEL
Read/
Write
R/W
Default
Value
15h
Description
GPIO [12] Output Source Select.
0h:
SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT.
1h:
SATA 0_ACT or
SATA 1_ACT or
SATA 2_ACT or
SATA 3_ACT or
SATA 4_ACT.
2h:
SATA 0_LINK or
SATA 1_LINK or
SATA 2_LINK or
SATA 3_LINK or
SATA 4_LINK.
3h:
SATA 0_LINK and SATA 0_ACT
4h:
SATA 0_ACT
5h:
SATA 0_LINK
6h:
SATA 1_LINK and SATA 1_ACT
7h:
SATA 1_ACT
8h:
SATA 1_LINK
9h:
SATA 2_LINK and SATA 2_ACT
Ah:
SATA 2_ACT
Bh:
SATA 2_LINK
Ch:
SATA 3_LINK and SATA3_ACT
Dh:
SATA 3_ACT
Eh:
SATA 3_LINK
Fh:
SATA 4_LINK and SATA4_ACT
10h: SATA 4_ACT
11h: SATA 4_LINK
12h: SATA H_LINK and SATA H_ACT
13h: SATA H_ACT
14h: SATA H_LINK
15h: GPIO_DATA_OUT[12]
Registers
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
8-41
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
• GPIO[18] through GPIO[19] Port Source Select
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:10 RSVD
9:5 GPIO[19]_SRC_SEL
R
R/W
000000h Reserved.
15h GPIO [19] Source Select.
1h:
POW_CTRL_IN
2h:
Reserved.
4:0 GPIO[18]_OUTPUT_S
RC_SEL
R/W 15h
14h: Reserved.
15h: GPIO_DATA_OUT[19]
GPIO [18] Output Source Select.
1h:
POW_CTRL_OUT
2h:
Reserved.
14h: Reserved.
15h: GPIO_DATA_OUT[18]
• Blink Rate Counter Register for SATA4 and Overall Link
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:12 RSVD
11:6 CNTR_VAL_BLINK_R
ATE_SATA4
R
R/W
00000h Reserved.
01h Blink Rate Counter Value for SATA4.
The counter value for blink rate based on 10 Hz clock for the following:
• SATA4_ACT
• SATA4_LINK
• SATA4_ACT_LINK
By default the blink period is 100 ms. (10 Hz blink rate)
8-42
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Register Description
Doc No. MV-S109142-00 Rev. A
Registers
Bits
5:0
Field Name
CNTR_VAL_BLINK_R
ATE
Read/
Write
R/W
Default
Value
01h
Description
Blink Rate Counter Value.
The counter value for blink rate based on 10 Hz clock for the following:
• SATA0_ACT or
SATA1_ACT or
SATA2_ACT or
SATA3_ACT or
SATA4_ACT,
• SATA0_LINK or
SATA1_LINK or
SATA2_LINK or
SATA3_LINK or
SATA4_LINK,
• SATA0_LINK and SATA0_ACT or
SATA1_LINK and SATA1_ACT or
SATA2_LINK and SATA2_ACT or
SATA3_LINK and SATA3_ACT or
SATA4_LINK and SATA4_ACT
By default the blink period is 100 ms. (10 Hz blink rate).
• Blink Rate Counter Register for SATA0/1/2/3/H
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:30 RSVD
29:24 SATAH_CNTR_VAL_B
LINK_RATE
23:18 SATA3_CNTR_VAL_B
LINK_RATE
R
R/W
R/W
0h
01h
01h
Reserved.
SATAH Blink Rate Counter Value.
The counter value for blink rate based on 10 Hz clock for the following:
• SATAH_ACT
• SATAH_LINK
• SATAH_ACT_LINK
By default the blink period is 100 ms (10 Hz blink rate).
SATA3 Blink Rate Counter Value.
The counter value for blink rate based on 10 Hz clock for the following:
• SATA3_ACT
• SATA3_LINK
• SATA3_ACT_LINK
By default the blink period is 100 ms (10 Hz blink rate).
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits Field Name
17:12 SATA2_CNTR_VAL_B
LINK_RATE
Read/
Write
R/W
11:6
5:0
SATA1_CNTR_VAL_B
LINK_RATE
R/W
SATA0_CNTR_VAL_B
LINK_RATE
R/W
Default
Value
01h
Description
01h
01h
SATA2 Blink Rate Counter Value.
The counter value for blink rate based on 10 Hz clock for the following:
• SATA2_ACT
• SATA2_LINK
• SATA2_ACT_LINK
By default the blink period is 100 ms. (10 Hz blink rate)
SATA1 Blink Rate Counter Value.
The counter value for blink rate based on 10 Hz clock for the following:
• SATA1_ACT
• SATA1_LINK
• SATA1_ACT_LINK
By default the blink period is 100 ms. (10 Hz blink rate)
SATA0 Blink Rate Counter Value.
The counter value for blink rate based on 10Hz clock for the following:
• SATA0_ACT
• SATA0_LINK
• SATA0_ACT_LINK
By default the blink period is 100 ms. (10 Hz blink rate)
• Blink Rate Counter Register for GPIO_OUT[4] through GPIO_OUT[0]
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:30 RSVD
29:24 GPIO[4]_CNTR_VAL_
BLINK_RATE
23:18 GPIO[3]_CNTR_VAL_
BLINK_RATE
17:12 GPIO[2]_CNTR_VAL_
BLINK_RATE
R
R/W
R/W
R/W
0h
01h
01h
01h
Reserved.
GPIO_OUT[4] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[4] blink rate based on 10Hz clock. By default the blink period is 100 ms. (10 Hz blink rate).
GPIO_OUT[3] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[3] blink rate based on 10Hz clock. By default the blink period is 100 ms. (10 Hz blink rate).
GPIO_OUT[2] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[2] blink rate based on 10 Hz clock. By default the blink period is
100 ms. (10 Hz blink rate).
8-44
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Register Description
Doc No. MV-S109142-00 Rev. A
Registers
Bits
11:6
5:0
Field Name
GPIO[1]_CNTR_VAL_
BLINK_RATE
Read/
Write
R/W
GPIO[0]_CNTR_VAL_
BLINK_RATE
R/W
Default
Value
01h
Description
01h
GPIO_OUT[1] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[1] blink rate based on 10Hz clock. By default the blink period is
100ms. (10Hz blink rate).
GPIO_OUT[0] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[0] blink rate based on 10Hz clock. By default the blink period is 100 ms. (10 Hz blink rate)
• Blink Rate Counter Register for GPIO_OUT[9] through GPIO_OUT[5]
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:30 RSVD
29:24 GPIO[9]_CNTR_VAL_
BLINK_RATE
23:18 GPIO[8]_CNTR_VAL_
BLINK_RATE
17:12 GPIO[7]_CNTR_VAL_
BLINK_RATE
11:6
5:0
GPIO[6]_CNTR_VAL_
BLINK_RATE
GPIO[5]_CNTR_VAL_
BLINK_RATE
R
R/W
R/W
R/W
R/W
R/W
0h
01h
01h
01h
01h
01h
Reserved.
GPIO_OUT[9] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[9] blink rate based on 10 Hz clock. By default the blink period is
100 ms. (10 Hz blink rate).
GPIO_OUT[8] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[8] blink rate based on 10Hz clock. By default the blink period is 100 ms. (10 Hz blink rate).
GPIO_OUT[7] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[7] blink rate based on 10 Hz clock. By default the blink period is
100 ms. (10 Hz blink rate).
GPIO_OUT[6] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[6] blink rate based on 10Hz clock. By default the blink period is
100ms. (10Hz blink rate).
GPIO_OUT[5] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[5] blink rate based on 10Hz clock. By default the blink period is 100 ms. (10 Hz blink rate)
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
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Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
\
• Blink Rate Counter Register for GPIO_OUT[14] through GPIO_OUT[10]
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:30 RSVD
29:24 GPIO[14]_CNTR_VAL_
BLINK_RATE
23:18 GPIO[13]_CNTR_VAL_
BLINK_RATE
17:12 GPIO[12]_CNTR_VAL_
BLINK_RATE
11:6
5:0
GPIO[11]_CNTR_VAL_
BLINK_RATE
GPIO[10]_CNTR_VAL_
BLINK_RATE
R
R/W
R/W
R/W
R/W
R/W
0h
01h
01h
01h
01h
01h
Reserved.
GPIO_OUT[14] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[14] blink rate based on 10 Hz clock. By default the blink period is
100 ms. (10 Hz blink rate).
GPIO_OUT[13] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[13] blink rate based on 10Hz clock. By default the blink period is 100 ms. (10 Hz blink rate).
GPIO_OUT[12] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[12] blink rate based on 10 Hz clock. By default the blink period is
100 ms. (10 Hz blink rate).
GPIO_OUT[11] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[11] blink rate based on 10Hz clock. By default the blink period is
100ms. (10Hz blink rate).
GPIO_OUT[10] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[10] blink rate based on 10Hz clock. By default the blink period is 100 ms. (10 Hz blink rate)
• Blink Rate Counter Register for GPIO_OUT[19] through GPIO_OUT[15]
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1
Bits Field Name
Read/
Write
Default
Value
Description
31:30 RSVD
29:24 GPIO[19]_CNTR_VAL_
BLINK_RATE
23:18 GPIO[18]_CNTR_VAL_
BLINK_RATE
R
R/W
R/W
0h
01h
01h
Reserved.
GPIO_OUT[19] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[19] blink rate based on 10 Hz clock. By default the blink period is
100 ms. (10 Hz blink rate).
GPIO_OUT[18] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[18] blink rate based on 10Hz clock. By default the blink period is 100 ms. (10 Hz blink rate).
8-46
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Register Description
Doc No. MV-S109142-00 Rev. A
Registers
Bits Field Name
17:12 GPIO[17]_CNTR_VAL_
BLINK_RATE
Read/
Write
R/W
11:6
5:0
GPIO[16]_CNTR_VAL_
BLINK_RATE
GPIO[15]_CNTR_VAL_
BLINK_RATE
R/W
R/W
Default
Value
01h
Description
01h
01h
GPIO_OUT[17] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[17] blink rate based on 10 Hz clock. By default the blink period is
100 ms. (10 Hz blink rate).
GPIO_OUT[16] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[16] blink rate based on 10Hz clock. By default the blink period is
100ms. (10Hz blink rate).
GPIO_OUT[15] Counter Value Blink Rate.
This field indicates the counter value for GPIO_OUT[15] blink rate based on 10Hz clock. By default the blink period is 100 ms. (10 Hz blink rate)
8.3.5
SATA PHY and Link Registers
This section contains the following subsections:
SATA PHY—Low-Power SERDES PHY Registers
8.3.5.1
Link Registers
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
Bits
Default Value 0 0 0 0 0 0 0 0 0 0
0 0 0 0
0 0 0 0 1 0 0 0 0 0 0
Bits Name
Read/
Write
Default
Value
Description
31:10 RSVD
9
8
7:0
SSC_EN
TX_AMP_ADJ
RSVD
R/W
R/W
R/W
R/W
6 5 4
0 0
3 2
0 0 0
1 0
0 1
000008h Reserved.
Do not change the default value.
0h Tx Spread Spectrum Enable.
0h:
Disable.
1h:
Enable.
0h
01h
Transmitter Amplitude Adjust.
For each reduction in range, additional power savings can be realized.
Reserved.
Do not change the default value.
Register Description
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June 12, 2015 Document Classification: Proprietary
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Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
8.3.5.2
SATA PHY—Low-Power SERDES PHY Registers
Bit Position 15 14 13 12 11
Bits
Default Value 1
1 0 0
1
Bits
15
Field Name
G1_TX_SLEW_CTRL_
EN
14:12 G1_TX_SLEW_RATE_
SEL
Read/
Write
R/W
R/W
10 9 8
7 6
5 4 3
0 0 1
Default
Value
Description
1h
4h
0 1 0 1 1
Transmitter Slew Control Enable.
This setting is used for 1.5 Gbps in SATA.
Transmitter Slew Rate Select.
0h:
Fastest edge
2
0
11
6
5:1
0
G1_TX_EMPH_EN
10:7 G1_TX_EMPH_AMP
RSVD
G1_TX_AMP
RSVD
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1h
2h
7h:
Slowest edge
The difference between the slowest and the fastest setting is about 100 ps.
This setting is used for 1.5 Gbps in SATA.
Transmitter Emphasis Enable.
This setting is used for 1.5 Gbps in SATA.
Transmitter Emphasis Amplitude.
Approximately 4% per step at the package pin.
0h:
4%
1h:
8%
1h Reserved.
Do not change the default value.
0Ch Transmitter Amplitude.
This setting is used for 1.5 Gbps in SATA.
0h
Ch:
48%
Settings Dh - Fh are not supported.
Reserved.
Do not change the default value.
Bit Position 15 14 13 12 11
Bits
Default Value 1
0 1 0
1
Bits
15
Field Name
G2_TX_SLEW_CTRL_
EN
Read/
Write
R/W
10 9 8
7 6
5 4 3
1h
0 1 0
Default
Value
Description
0 1 1 0
Transmitter Slew Control Enable.
This setting is used for 3 Gbps in SATA.
0
2
0
1
1
0
0
8-48
Copyright © 2015 Marvell
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Register Description
Doc No. MV-S109142-00 Rev. A
Registers
Bits Field Name
14:12 G2_TX_SLEW_RATE_
SEL
Read/
Write
R/W
Default
Value
Description
2h Transmitter Slew Rate Select.
0h:
Fastest edge
11
10:7
6
5:1
0
G2_TX_EMPH_EN
G2_TX_EMPH_AMP
RSVD
G2_TX_AMP
RSVD
R/W
R/W
R/W
R/W
R/W
1h
4h
7h:
Slowest edge
The difference between the slowest and the fastest setting is about 100 ps.
This setting is used for 3 Gbps in SATA.
Transmitter Emphasis Enable.
This setting is used for 3 Gbps in SATA.
Transmitter Emphasis Amplitude.
Approximately 4% per step at the package pin.
0h:
4%
1h:
8%
1h
11h
0h
Ch:
48%
Others: Not supported.
Reserved.
Do not change the default value.
Transmitter Amplitude.
This setting is used for 3 Gbps in SATA.
Reserved.
Do not change the default value.
Bit Position 15 14 13 12 11
Bits
Default Value 0
0 0 0 1
Bits Field Name
Read/
Write
10 9 8
0 1 1
Default
Value
Description
7
1
15 G3_TX_SLEW_CTRL_
EN
14:12 G3_TX_SLEW_RATE_
SEL
R/W
R/W
0h
0h
6
1
5
1
4
0
3
Transmitter Slew Control Enable.
This setting is used for 6 Gbps in SATA.
Transmitter Slew Rate Select.
0h:
Fastest edge
1
2
0
1
1
0
1
7h:
Slowest edge
The difference between the slowest and the fastest setting is about 100 ps
This setting is used for 6 Gbps in SATA.
Register Description
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
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Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
Bits
11
Field Name
G3_TX_EMPH_EN
10:7 G3_TX_EMPH_AMP
Read/
Write
R/W
R/W
Default
Value
Description
1h
7h
Transmitter Emphasis Enable.
This setting is used for 6 Gbps in SATA.
Transmitter Emphasis Amplitude.
Approximately 4% per step at the package pin.
0h:
4%
1h:
8%
6
5:1
0
RSVD
G3_TX_AMP
RSVD
R/W
R/W
R/W
1h
15h
1h
Ch:
48%
Settings Dh - Fh are not supported.
Reserved.
Do not change the default value.
Transmitter Amplitude.
This setting is used for 6 Gbps in SATA.
Reserved.
Do not change the default value.
8-50
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Register Description
Doc No. MV-S109142-00 Rev. A
Registers
8.3.6
Device Port PHY Event Counter Registers
• Device Port PHY Event Counter 0
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Field Name
Read/
Write
Default
Value
Description
31:0 DEV_PORT_PHY_EVE
NT_CNTR_0
R/W 00000000h Device Port PHY Event Counter 0.
This register contains both the identifier and the counter value.
Counter identifier: 00002C00h.
Counter: 32-bit counter, contains number of transmitted H2D non-data FISes to which the port multiplier responded with
R_ERR due to collision.
• Device Port PHY Event Counter 2
Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
31:0
Field Name
DEV_PORT_PHY_EVE
NT_CNTR_2
Read/
Write
Default
Value
Description
R/W 00000000h Device Port PHY Event Counter 2.
This register contains both the identifier and the counter value.
Counter identifier: 00002C02h.
Counter: 32-bit counter, contains number of corrupted CRC values that were transmitted to the host.
Register Description
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June 12, 2015 Document Classification: Proprietary
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88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
THIS PAGE LEFT INTENTIONALLY BLANK
8-52
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Register Description
Doc No. MV-S109142-00 Rev. A
9
ELECTRICAL SPECIFICATIONS
This chapter contains the following sections:
Recommended/Typical Operating Conditions
Electrical Specifications
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
9-1
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
9.1
Absolute Maximum Ratings
The following table describes the 88SM9705 absolute Maximum Ratings:
Table 9-1 Absolute Maximum Ratings
Parameter Symbol
Absolute Digital Power
Supply Voltage
Absolute Digital I/O pad
Supply Voltage
VDD
ABS
VDDIO
ABS
Absolute Analog Power
Supply Voltage for
Timebase Generators (TBG)
VAA1
ABS
VAA2
ABS
Absolute Analog Power
Supply Voltage for PHY
Absolute Input Voltage Vin
ABS
Tstor
ABS
Absolute Storage
Temperature
Absolute Junction
Temperature
Tjunc
ABS
Condition Min Typ
-0.5
1.0
-0.5
3.3
-0.5
1.8
-0.5
1.8
-0.4
-55
Max
1.1
3.63
1.98
1.98
vddio + 0.4
85
125
Unit
V
V
V
V
V
°C
°C
9.2
Power Requirements
The following table describes the 88SM9705 power requirements.
Table 9-2 Total Power Dissipation
Parameter
Absolute digital I/O pad power supply
Absolute digital power supply
Absolute analog power supply for TBG
Absolute analog power supply for PHY
Symbol
I
VDDIO
I
VDD
I
VAA1
I
VAA2
Condition Min Typ
20
300
10
400
Max Unit
mA mA mA mA
9-2
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
Absolute Maximum Ratings
Doc No. MV-S109142-00 Rev. A
Electrical Specifications
9.3
Recommended/Typical Operating Conditions
Table 9-3 Recommended/Typical Operating Conditions
Parameter
Ambient Operating
Temperature
Junction Operating
Temperature
Operating Digital Power
Supply Voltage
Operating Digital I/O Pad
Supply Voltage
Operating Analog Power
Supply Voltage for TBG
Operating Analog Power
Supply Voltage for PHY
Symbol
VDD
OP
VDDIO
OP
VAA1
OP
VAA2
OP
Condition Min
0
0
1.0 -
5%
3.3 -
5%
1.8 -
5%
1.8 -
5%
Typ
3.3
1.8
1.8
Max
70
125
5%
3.3 +
5%
1.8 +
5%
1.8 +
5%
Unit
°C
°C
V
V
V
V
Recommended/Typical Operating Conditions
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
9-3
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
9.4
DC Characteristics
Table 9-4 DC Characteristics
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Symbol Condition
V
IL
V
IH
V
OL
V
OH
I
I
OL
OL
=4 mA, VDDP=3.3V
=-2 mA, VDDP=3.3V
Min Typ
-0.4
2.0
-0.4
0.13
2.4
3.3
Max Unit
0.8
V
VDDIO
+ 0.4
V
0.4
V
V
9-4
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
DC Characteristics
Doc No. MV-S109142-00 Rev. A
Electrical Specifications
9.5
Thermal Data
It is recommended to read application note AN-63 Thermal Management for Selected
Marvell® Products and the ThetaJC, ThetaJA, and Temperature Calculations White Paper, available from Marvell, before designing a system. These documents describe the basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products.
Table 9-5 provides the thermal data for the 88SM9705. It shows the values for the package
thermal parameters for the 84-lead Quad Flat Non-Lead package (QFN 84) mounted on a
4-layer PCB. The simulation was performed according to JEDEC standards.‘
Table 9-5 Package Thermal Data, 4-Layer PCB*
Airflow Value
Parameter Definition
0 m/s
θ
JA
Thermal Resistance: Junction to
Ambient
28.2 C/W
θ
JB
Thermal Resistance: Junction to
Board
16.70 C/W
θ
JC
Thermal Resistance: Junction to
Case
14.90 C/W
Ψ
JT
Thermal Characterization:
Junction to Top
0.48
Ψ
JB
Thermal Characterization:
Junction to Board
16.5
* All data is based on parts mounted on a 3” x 4.5”, JEDEC 4L PCB.
1 m/s
27.6C/W
–
–
0.78
16.4
2 m/s
26.5 C/W
–
–
0.94
16.3
3 m/s
25.8 C/W
–
–
1.05
16.2
Thermal Data
Copyright © 2015 Marvell
June 12, 2015 Document Classification: Proprietary
9-5
Doc No. MV-S109142-00 Rev. A
88SM9705 SATA 6.0 Gbps: 1-to-5 Port Multiplier
Preliminary Specifications
THIS PAGE LEFT INTENTIONALLY BLANK
9-6
Copyright © 2015 Marvell
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Thermal Data
Doc No. MV-S109142-00 Rev. A
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