NXP MCF5227X V2 Microprocessor Reference Manual

MCF52277 Reference Manual
Devices Supported:
MCF52274
MCF52277
Document Number: MCF52277RM
Rev. 2
3/2009
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reserved.
MCF52277RM
Rev. 2
3/2009
About This Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
ColdFire Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxiv
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxiv
Register Figure Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv
Chapter 1
Overview
1.1
1.2
1.3
1.4
1.5
1.6
MCF5227x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chip Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Module-by-Module Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6.1 Version 2 ColdFire Variable-Length RISC Processor . . . . . . . . . . . . . . . . . . . . 1-5
1.6.2 On-chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.3 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.5 Chip Configuration Module (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.6 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.7 System Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.8 Crossbar Switch Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.9 Liquid Crystal Display Controller (LCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.10 Touchscreen Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.11 Universal Serial Bus (USB) 2.0 On-The-Go (OTG) Controller . . . . . . . . . . . . . 1-7
1.6.12 SDR/DDR SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.13 FlexBus (External Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.14 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.15 FlexCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.16 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.17 Programmable Interrupt Timers (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.18 DMA Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.19 DMA Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.20 Pulse Width Modulation (PWM) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.21 Universal Asynchronous Receiver Transmitters (UARTs) . . . . . . . . . . . . . . . . 1-9
1.6.22 I2C Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.23 Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.24 Edge Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
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1.7
1.8
1.6.25 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.26 General Purpose I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.27 System Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.28 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.1 Internal Peripheral Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-10
1-10
1-10
1-10
1-10
1-11
1-12
Chapter 2
Signal Descriptions
2.1
2.2
2.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Signal Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.1 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.2 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.3 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.4 FlexBus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.5 SDRAM Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3.6 Serial Boot Facility Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.7 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.8 DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.9 LCD Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.10 FlexCAN Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.11 Pulse Width Modulation (PWM) Module Signals . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.12 Universal Serial Bus (USB) On-the-Go Signals . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.13 Touschreen Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.14 I2C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.15 DMA Serial Peripheral Interface (DSPI) Signals . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.16 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3.17 Synchronous Serial Interface (SSI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3.18 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.19 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.20 Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.21 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Chapter 3
ColdFire Core
3.1
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . .
3.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-1
3-2
3-4
3-4
3-5
3-6
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3.3
3.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.6 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.7 Access Control Registers (ACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.8 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.9 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.10 Memory Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.3.1 Version 2 ColdFire Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.3.2 Instruction Set Architecture (ISA_A+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.3.3 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.3.4 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.3.5 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
4.1
4.2
4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1 MAC Status Register (MACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.2 Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.3 Accumulator Registers (ACC0–3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.2.4 Accumulator Extension Registers (ACCext01, ACCext23) . . . . . . . . . . . . . . . . 4-7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.3.1 Fractional Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.3.2 EMAC Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.3.3 EMAC Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
4.3.4 Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.3.5 MAC Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Chapter 5
Cache
5.1
5.2
5.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Cache Control Register (CACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Access Control Registers (ACR0, ACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Interaction with Other Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 Memory Reference Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 Cache Coherency and Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5 Cache Miss Fetch Algorithm/Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-1
5-1
5-2
5-3
5-6
5-7
5-7
5-8
5-8
5-8
5-9
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Chapter 6
Static RAM (SRAM)
6.1
6.2
6.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1 SRAM Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1 SRAM Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1
6-1
6-1
6-2
6-2
6-4
6-4
6-5
Chapter 7
Clock Module
7.1
7.2
7.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.1 PLL Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.2.2 PLL Status Register (PSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.3.1 PLL Frequency Multiplication Factor Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.3.2 Lock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.3 Loss-of-Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.4 System Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.5 Clock Operation During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Chapter 8
Power Management
8.1
8.2
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.1 Wake-up Control Register (WCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.2 Peripheral Power Management Set Register (PPMSR) . . . . . . . . . . . . . . . . . .
8.2.3 Peripheral Power Management Clear Register (PPMCR) . . . . . . . . . . . . . . . .
8.2.4 Peripheral Power Management Registers (PPMHR & PPMLR) . . . . . . . . . . . .
8.2.5 Low-Power Control Register (LPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1 Peripheral Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.2 Limp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.4 Peripheral Behavior in Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1
8-1
8-1
8-2
8-3
8-4
8-4
8-7
8-7
8-7
8-8
8-8
8-9
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Chapter 9
Chip Configuration Module (CCM)
9.1
9.2
9.3
9.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.1 BOOTMOD[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2.2 FB_A[21:16] (Reset Configuration Override) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.3.1 Chip Configuration Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3.2 Reset Configuration Register (RCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
9.3.3 Chip Identification Register (CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.4 Miscellaneous Control Register (MISCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.5 Clock-Divider Register (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
9.3.6 USB On-the-Go Controller Status Register (UOCSR) . . . . . . . . . . . . . . . . . . . 9-8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.4.1 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
9.4.2 Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.4.3 Output Pad Strength Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.4.4 Chip Select Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
9.4.5 Low Power Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
Chapter 10
Serial Boot Facility (SBF)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.1 Serial Boot Facility Status Register (SBFSR) . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.2 Serial Boot Facility Control Register (SBFCR) . . . . . . . . . . . . . . . . . . . . . . . .
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.1 Serial Initialization and Shift Clock Frequency Adjustment . . . . . . . . . . . . . . .
10.4.2 Reset Configuration and Optional Boot Load . . . . . . . . . . . . . . . . . . . . . . . . .
10.4.3 Execution Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.1 SPI Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.2 FAST_READ Feature Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-1
10-1
10-2
10-2
10-2
10-3
10-3
10-4
10-4
10-5
10-5
10-6
10-6
10-7
Chapter 11
Reset Controller Module
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
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11.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2.2 RSTOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.1 Reset Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.2 Reset Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4.3 Concurrent Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-1
11-1
11-2
11-2
11-2
11-2
11-3
11-3
11-4
11-4
11-5
11-7
Chapter 12
System Control Module (SCM)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.1 Master Privilege Register (MPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
12.2.2 Peripheral Access Control Registers (PACRx) . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.2.3 Core Watchdog Control Register (CWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.2.4 Core Watchdog Service Register (CWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.2.5 SCM Interrupt Status Register (SCMISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.2.6 Burst Configuration Register (BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.2.7 Core Fault Address Register (CFADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.2.8 Core Fault Interrupt Enable Register (CFIER) . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.2.9 Core Fault Location Register (CFLOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.2.10 Core Fault Attributes Register (CFATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.2.11 Core Fault Data Register (CFDTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.3.1 Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.3.2 Core Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.3.3 Core Data Fault Recovery Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
Chapter 13
Crossbar Switch (XBS)
13.1
13.2
13.3
13.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map / Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.1 XBS Priority Registers (XBS_PRSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4.2 XBS Control Registers (XBS_CRSn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-1
13-2
13-3
13-3
13-3
13-5
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13.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.5.1 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
13.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Chapter 14
General Purpose I/O Module
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.3.1 Port Output Data Registers (PODR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
14.3.2 Port Data Direction Registers (PDDR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.3.3 Port Pin Data/Set Data Registers (PPDSDR_x) . . . . . . . . . . . . . . . . . . . . . . 14-13
14.3.4 Port Clear Output Data Registers (PCLRR_x) . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.3.5 Pin Assignment Registers (PAR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.3.6 FlexBus Mode Select Control Register (MSCR_FLEXBUS) . . . . . . . . . . . . 14-23
14.3.7 SDRAM Mode Select Control Register (MSCR_SDRAM) . . . . . . . . . . . . . . 14-24
14.3.8 Drive Strength Control Registers (DSCR_x) . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
14.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
14.4.2 Port Digital I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
14.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
Chapter 15
Interrupt Controller Modules
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.1 68 K/ColdFire Interrupt Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.2.1 Interrupt Pending Registers (IPRHn, IPRLn) . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.2.2 Interrupt Mask Register (IMRHn, IMRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.2.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) . . . . . . . . . . . . . . . . . . . . 15-6
15.2.4 Interrupt Configuration Register (ICONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.2.5 Set Interrupt Mask Register (SIMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.2.6 Clear Interrupt Mask Register (CIMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.2.7 Current Level Mask Register (CLMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.2.8 Saved Level Mask Register (SLMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.2.9 Interrupt Control Register (ICR0n, ICR1n, (n = 00, 01, 02, ..., 63)) . . . . . . . 15-11
15.2.10 Software and Level 1 – 7 IACK Registers
(SWIACKn, L1IACKn – L7IACKn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.3.1 Interrupt Controller Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
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15.3.2 Prioritization Between Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . .
15.3.3 Low-Power Wake-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.4.1 Interrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-17
15-18
15-18
15-18
Chapter 16
Edge Port Module (EPORT)
16.1
16.2
16.3
16.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.1 EPORT Pin Assignment Register (EPPAR) . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.2 EPORT Data Direction Register (EPDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.3 Edge Port Interrupt Enable Register (EPIER) . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.4 Edge Port Data Register (EPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.5 Edge Port Pin Data Register (EPPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.4.6 Edge Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-1
16-2
16-2
16-2
16-3
16-4
16-5
16-5
16-5
16-6
Chapter 17
Enhanced Direct Memory Access (eDMA)
17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.2.2 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.3.1 External Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.4.1 eDMA Control Register (EDMA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.4.2 eDMA Error Status Register (EDMA_ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.4.3 eDMA Enable Request Register (EDMA_ERQ) . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.4.4 eDMA Enable Error Interrupt Registers (EDMA_EEI) . . . . . . . . . . . . . . . . . . 17-9
17.4.5 eDMA Set Enable Request Register (EDMA_SERQ) . . . . . . . . . . . . . . . . . 17-10
17.4.6 eDMA Clear Enable Request Register (EDMA_CERQ) . . . . . . . . . . . . . . . . 17-10
17.4.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEI) . . . . . . . . . . . . . . 17-11
17.4.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEI) . . . . . . . . . . . . 17-11
17.4.9 eDMA Clear Interrupt Request Register (EDMA_CINT) . . . . . . . . . . . . . . . . 17-12
17.4.10 eDMA Clear Error Register (EDMA_CERR) . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.4.11 eDMA Set START Bit Register (EDMA_SSRT) . . . . . . . . . . . . . . . . . . . . . . 17-13
17.4.12 eDMA Clear DONE Status Bit Register (EDMA_CDNE) . . . . . . . . . . . . . . . 17-14
17.4.13 eDMA Interrupt Request Register (EDMA_INT) . . . . . . . . . . . . . . . . . . . . . . 17-15
17.4.14 eDMA Error Register (EDMA_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
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17.4.15 eDMA Channel n Priority Registers (DCHPRIn) . . . . . . . . . . . . . . . . . . . . . .
17.4.16 Transfer Control Descriptors (TCDn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.1 eDMA Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5.2 eDMA Basic Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.1 eDMA Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.2 DMA Programming Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.3 DMA Arbitration Mode Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.4 DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.5 eDMA TCDn Status Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.6 Channel Linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6.7 Dynamic Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17-16
17-17
17-24
17-24
17-25
17-28
17-28
17-31
17-31
17-32
17-35
17-36
17-37
Chapter 18
FlexBus
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.2.1 Address and Data Buses (FB_A[23:0], FB_D[31:0]) . . . . . . . . . . . . . . . . . . . 18-2
18.2.2 Chip Selects (FB_CS[5:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.3 Byte Enables/Byte Write Enables (FB_BE/BWE[3:0]) . . . . . . . . . . . . . . . . . . 18-3
18.2.4 Output Enable (FB_OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.5 Read/Write (FB_R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.6 Transfer Start (FB_TS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.2.7 Transfer Acknowledge (FB_TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
18.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
18.3.1 Chip-Select Address Registers (CSAR0 – CSAR5) . . . . . . . . . . . . . . . . . . . . 18-5
18.3.2 Chip-Select Mask Registers (CSMR0 – CSMR5) . . . . . . . . . . . . . . . . . . . . . . 18-5
18.3.3 Chip-Select Control Registers (CSCR0 – CSCR5) . . . . . . . . . . . . . . . . . . . . . 18-6
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.4.1 Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
18.4.2 Data Transfer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
18.4.3 Data Byte Alignment and Physical Connections . . . . . . . . . . . . . . . . . . . . . . 18-11
18.4.4 Bus Cycle Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12
18.4.5 FlexBus Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13
18.4.6 Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24
18.4.7 Misaligned Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30
18.4.8 Bus Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30
Chapter 19
SDRAM Controller (SDRAMC)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
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19.2
19.3
19.4
19.5
19.6
19.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
19.1.3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
Interface Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3.1 Supported Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
19.3.2 SDRAM SDR Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10
19.3.3 SDRAM DDR Component Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12
19.3.4 DDR SDRAM Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12
Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
19.4.1 SDRAM Mode/Extended Mode Register (SDMR) . . . . . . . . . . . . . . . . . . . . 19-14
19.4.2 SDRAM Control Register (SDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.4.3 SDRAM Configuration Register 1 (SDCFG1) . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.4.4 SDRAM Configuration Register 2 (SDCFG2) . . . . . . . . . . . . . . . . . . . . . . . . 19-19
19.4.5 SDRAM Chip Select Configuration Registers (SDCSn) . . . . . . . . . . . . . . . . 19-20
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21
19.5.1 SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21
19.5.2 Read Clock Recovery (RCR) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.6.1 SDR SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.6.2 DDR SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
19.6.3 Low-power/Mobile SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . 19-29
19.6.4 Page Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
19.6.5 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
Chapter 20
Universal Serial Bus Interface – On-The-Go Module
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
20.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.2.1 USB OTG Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
20.3.1 Module Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.3.2 Device/Host Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
20.3.3 Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
20.3.4 Operational Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45
20.4.1 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45
20.4.2 DMA Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45
20.4.3 FIFO RAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45
20.4.4 Physical Layer (PHY) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-45
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20.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.5.1 Host Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.5.2 Device Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.5.3 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.5.4 Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.5.5 Deviations from the EHCI Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-46
20-46
20-47
20-54
20-72
20-73
Chapter 21
Liquid Crystal Display Controller (LCDC)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
21.3.1 LCDC Screen Start Address Register (LCD_SSAR) . . . . . . . . . . . . . . . . . . . 21-5
21.3.2 LCDC Size Register (LCD_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.3.3 LCDC Virtual Page Width Register (LCD_VPW) . . . . . . . . . . . . . . . . . . . . . . 21-5
21.3.4 LCDC Cursor Position Register (LCD_CPR) . . . . . . . . . . . . . . . . . . . . . . . . . 21-6
21.3.5 LCDC Cursor Width Height and Blink Register (LCD_CWHB) . . . . . . . . . . . . 21-7
21.3.6 LCDC Color Cursor Mapping Register (LCD_CCMR) . . . . . . . . . . . . . . . . . . 21-8
21.3.7 LCDC Panel Configuration Register (LCD_PCR) . . . . . . . . . . . . . . . . . . . . . . 21-9
21.3.8 LCDC Horizontal Configuration Register (LCD_HCR) . . . . . . . . . . . . . . . . . 21-12
21.3.9 LCDC Vertical Configuration Register (LCD_VCR) . . . . . . . . . . . . . . . . . . . 21-12
21.3.10 LCDC Panning Offset Register (LCD_POR) . . . . . . . . . . . . . . . . . . . . . . . . 21-13
21.3.11 LCDC Sharp Configuration Register (LCD_SCR) . . . . . . . . . . . . . . . . . . . . 21-14
21.3.12 LCDC PWM Contrast Control Register (LCD_PCCR) . . . . . . . . . . . . . . . . . 21-16
21.3.13 LCDC DMA Control Register (LCD_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16
21.3.14 LCDC Refresh Mode Control Register (LCD_RMCR) . . . . . . . . . . . . . . . . . 21-17
21.3.15 LCDC Interrupt Configuration Register (LCD_ICR) . . . . . . . . . . . . . . . . . . . 21-18
21.3.16 LCDC Interrupt Enable Register (LCD_IER) . . . . . . . . . . . . . . . . . . . . . . . . 21-19
21.3.17 LCDC Interrupt Status Register (LCD_ISR) . . . . . . . . . . . . . . . . . . . . . . . . . 21-20
21.3.18 LCDC Graphic Window Start Address Register (LCD_GWSAR) . . . . . . . . . 21-22
21.3.19 LCDC Graphic Window Size Register (LCD_GWSR) . . . . . . . . . . . . . . . . . 21-22
21.3.20 LCDC Graphic Window Virtual Page Width Register (LCD_GWVPW) . . . . 21-23
21.3.21 LCDC Graphic Window Panning Offset Register (LCD_GWPOR) . . . . . . . . 21-23
21.3.22 LCDC Graphic Window Position Register (LCD_GWPR) . . . . . . . . . . . . . . . 21-24
21.3.23 LCDC Graphic Window Control Register (LCD_GWCR) . . . . . . . . . . . . . . . 21-24
21.3.24 LCDC Graphic Window DMA Control Register (LCD_GWDCR) . . . . . . . . . 21-26
21.3.25 Mapping RAM Registers (BGLUT and GWLUT) . . . . . . . . . . . . . . . . . . . . . 21-26
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29
21.4.1 LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29
21.4.2 Graphic Window on Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30
21.4.3 Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31
21.4.4 Display Data Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31
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21.4.5 Black-and-White Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.4.6 Gray-Scale Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.4.7 Color Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.4.8 Frame Rate Modulation Control (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.4.9 Panel Interface Signals and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21.4.10 8 bpp Mode Color STN Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21-33
21-33
21-34
21-36
21-37
21-40
Chapter 22
Touchscreen Controller
22.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
22.3.1 ASP Control Register (ASP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
22.3.2 ASP Sample Setting Register (ASP_SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.3.3 ASP Sample Timing Register (ASP_TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
22.3.4 ASP Interrupt/DMA Control Register (ASP_ICR) . . . . . . . . . . . . . . . . . . . . . . 22-9
22.3.5 ASP Status Register (ASP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10
22.3.6 ASP Sample FIFO (ASP_SFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11
22.3.7 ASP FIFO Pointer Register (ASP_FIFOP) . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12
22.3.8 ASP Clock Divider Register (ASP_CLKD) . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.4 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.4.1 Touchscreen Controller Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14
22.4.2 General ADC Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16
22.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17
22.5.1 Touchscreen Mode 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17
22.5.2 Touchscreen Mode 01—Single Round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19
22.5.3 Touchscreen Mode 01—Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20
22.5.4 Touchscreen Mode 10—Single Round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21
22.5.5 Touchscreen Mode 10—Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22
22.5.6 Touchscreen Mode 11—Single Round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23
22.5.7 Touchscreen Mode 11—Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24
22.5.8 General Purpose ADC—Single Round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.5.9 General Purpose ADC—Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26
22.5.10 Touchscreen Calibration—Single Round . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27
22.5.11 Touchscreen Calibration – Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28
Chapter 23
FlexCAN
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23-1
23-1
23-3
23-4
23-5
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23.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.3.1 FlexCAN Configuration Register (CANMCR) . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.3.2 FlexCAN Control Register (CANCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9
23.3.3 FlexCAN Free Running Timer Register (TIMER) . . . . . . . . . . . . . . . . . . . . . 23-11
23.3.4 Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK) . . . . . . . . . . . . 23-12
23.3.5 FlexCAN Error Counter Register (ERRCNT) . . . . . . . . . . . . . . . . . . . . . . . . 23-13
23.3.6 FlexCAN Error and Status Register (ERRSTAT) . . . . . . . . . . . . . . . . . . . . . 23-14
23.3.7 Interrupt Mask Register (IMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16
23.3.8 Interrupt Flag Register (IFLAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17
23.3.9 Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17
23.3.10 Rx Individual Masking Registers (RXIMR0–15) . . . . . . . . . . . . . . . . . . . . . . 23-21
23.3.11 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22
23.3.12 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22
23.3.13 Arbitration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23
23.3.14 Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23
23.3.15 Matching Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24
23.3.16 Message Buffer Managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25
23.3.17 CAN Protocol Related Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-27
23.3.18 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-28
23.3.19 Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-28
23.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-30
23.4.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-31
Chapter 24
Pulse-Width Modulation (PWM) Module
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.2.1 PWM Enable Register (PWME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.2.2 PWM Polarity Register (PWMPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
24.2.3 PWM Clock Select Register (PWMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
24.2.4 PWM Prescale Clock Select Register (PWMPRCLK) . . . . . . . . . . . . . . . . . . 24-5
24.2.5 PWM Center Align Enable Register (PWMCAE) . . . . . . . . . . . . . . . . . . . . . . 24-6
24.2.6 PWM Control Register (PWMCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
24.2.7 PWM Scale A Register (PWMSCLA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
24.2.8 PWM Scale B Register (PWMSCLB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
24.2.9 PWM Channel Counter Registers (PWMCNTn) . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.2.10 PWM Channel Period Registers (PWMPERn) . . . . . . . . . . . . . . . . . . . . . . . 24-10
24.2.11 PWM Channel Duty Registers (PWMDTYn) . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
24.2.12 PWM Shutdown Register (PWMSDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
24.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.3.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.3.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
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Chapter 25
Synchronous Serial Interface (SSI)
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.2.1 SSI_CLKIN — SSI Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.2.2 SSI_BCLK — Serial Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.2.3 SSI_MCLK — Serial Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.2.4 SSI_FS — Serial Frame Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.2.5 SSI_RXD — Serial Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
25.2.6 SSI_TXD — Serial Transmit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
25.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
25.3.1 SSI Transmit Data Registers 0 and 1 (SSI_TX0/1) . . . . . . . . . . . . . . . . . . . . 25-8
25.3.2 SSI Transmit FIFO 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.3.3 SSI Transmit Shift Register (TXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9
25.3.4 SSI Receive Data Registers 0 and 1 (SSI_RX0/1) . . . . . . . . . . . . . . . . . . . 25-10
25.3.5 SSI Receive FIFO 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
25.3.6 SSI Receive Shift Register (RXSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11
25.3.7 SSI Control Register (SSI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
25.3.8 SSI Interrupt Status Register (SSI_ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
25.3.9 SSI Interrupt Enable Register (SSI_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
25.3.10 SSI Transmit Configuration Register (SSI_TCR) . . . . . . . . . . . . . . . . . . . . . 25-21
25.3.11 SSI Receive Configuration Register (SSI_RCR) . . . . . . . . . . . . . . . . . . . . . 25-23
25.3.12 SSI Clock Control Register (SSI_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24
25.3.13 SSI FIFO Control/Status Register (SSI_FCSR) . . . . . . . . . . . . . . . . . . . . . . 25-25
25.3.14 SSI AC97 Control Register (SSI_ACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27
25.3.15 SSI AC97 Command Address Register (SSI_ACADD) . . . . . . . . . . . . . . . . 25-28
25.3.16 SSI AC97 Command Data Register (SSI_ACDAT) . . . . . . . . . . . . . . . . . . . 25-29
25.3.17 SSI AC97 Tag Register (SSI_ATAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-29
25.3.18 SSI Transmit Time Slot Mask Register (SSI_TMASK) . . . . . . . . . . . . . . . . . 25-30
25.3.19 SSI Receive Time Slot Mask Register (SSI_RMASK) . . . . . . . . . . . . . . . . . 25-30
25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30
25.4.1 Detailed Operating Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30
25.4.2 SSI Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43
25.4.3 External Frame and Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46
25.4.4 Supported Data Alignment Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46
25.4.5 Receive Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-48
25.4.6 Transmit Interrupt Enable Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-48
25.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49
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Chapter 26
Real-Time Clock
26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
26.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1
26.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
26.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
26.3.1 RTC Hours and Minutes Counter Register (RTC_HOURMIN) . . . . . . . . . . . . 26-3
26.3.2 RTC Seconds Counter Register (RTC_SECONDS) . . . . . . . . . . . . . . . . . . . . 26-4
26.3.3 RTC Hours and Minutes Alarm Register (RTC_ALRM_HM) . . . . . . . . . . . . . 26-4
26.3.4 RTC Seconds Alarm Register (RTC_ALRM_SEC) . . . . . . . . . . . . . . . . . . . . 26-5
26.3.5 RTC Control Register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
26.3.6 RTC Interrupt Status Register (RTC_ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
26.3.7 RTC Interrupt Enable Register (RTC_IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7
26.3.8 RTC Stopwatch Minutes Register (RTC_STPWCH) . . . . . . . . . . . . . . . . . . . 26-9
26.3.9 RTC Days Counter Register (RTC_DAYS) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9
26.3.10 RTC Day Alarm Register (RTC_ALRM_DAY) . . . . . . . . . . . . . . . . . . . . . . . . 26-9
26.3.11 RTC General Oscillator Clock Upper Register (RTC_GOCU) . . . . . . . . . . . 26-10
26.3.12 RTC General Oscillator Clock Lower Register (RTC_GOCL) . . . . . . . . . . . 26-10
26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11
26.4.1 Clock Generation and Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11
26.4.2 Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12
26.4.3 Sampling Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12
26.4.4 Minute Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13
26.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13
26.5.1 Flow Chart of RTC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13
26.5.2 Programming the Alarm or Time-of-Day Registers . . . . . . . . . . . . . . . . . . . . 26-13
Chapter 27
Programmable Interrupt Timers (PIT0–PIT1)
27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.1.3 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.2.1 PIT Control and Status Register (PCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.2.2 PIT Modulus Register (PMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.2.3 PIT Count Register (PCNTRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3.1 Set-and-Forget Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3.2 Free-Running Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3.3 Timeout Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3.4 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27-1
27-1
27-1
27-1
27-2
27-3
27-4
27-5
27-5
27-5
27-6
27-6
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Chapter 28
DMA Timers (DTIM0–DTIM3)
28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1
28.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2
28.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
28.2.1 DMA Timer Mode Registers (DTMRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3
28.2.2 DMA Timer Extended Mode Registers (DTXMRn) . . . . . . . . . . . . . . . . . . . . . 28-5
28.2.3 DMA Timer Event Registers (DTERn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5
28.2.4 DMA Timer Reference Registers (DTRRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7
28.2.5 DMA Timer Capture Registers (DTCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7
28.2.6 DMA Timer Counters (DTCNn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.2 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.3 Reference Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8
28.3.4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.4.1 Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-9
28.4.2 Calculating Time-Out Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10
Chapter 29
DMA Serial Peripheral Interface (DSPI)
29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
29.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
29.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
29.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2
29.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
29.2.1 Signal Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
29.2.2 Peripheral Chip Select/Slave Select (DSPI_PCS0/SS) . . . . . . . . . . . . . . . . . 29-4
29.2.3 Peripheral Chip Selects 2,4 (DSPI_PCS[2,4]) . . . . . . . . . . . . . . . . . . . . . . . . 29-4
29.2.4 Serial Input (DSPI_SIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
29.2.5 Serial Output (DSPI_SOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4
29.2.6 Serial Clock (DSPI_SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
29.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5
29.3.1 DSPI Module Configuration Register (DSPI_MCR) . . . . . . . . . . . . . . . . . . . . 29-5
29.3.2 DSPI Transfer Count Register (DSPI_TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8
29.3.3 DSPI Clock and Transfer Attributes Registers 0–7 (DSPI_CTARn) . . . . . . . . 29-8
29.3.4 DSPI Status Register (DSPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-13
29.3.5 DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER) . . 29-15
29.3.6 DSPI Push Transmit FIFO Register (DSPI_PUSHR) . . . . . . . . . . . . . . . . . . 29-16
29.3.7 DSPI Pop Receive FIFO Register (DSPI_POPR) . . . . . . . . . . . . . . . . . . . . 29-18
29.3.8 DSPI Transmit FIFO Registers 0–15 (DSPI_TXFRn) . . . . . . . . . . . . . . . . . . 29-18
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29.3.9 DSPI Receive FIFO Registers 0–15 (DSPI_RXFRn) . . . . . . . . . . . . . . . . . .
29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.1 Start and Stop of DSPI Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.2 Serial Peripheral Interface (SPI) Configuration . . . . . . . . . . . . . . . . . . . . . . .
29.4.3 DSPI Baud Rate and Clock Delay Generation . . . . . . . . . . . . . . . . . . . . . . .
29.4.4 Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.5 Continuous Serial Communications Clock . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.6 Interrupts/DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.4.7 Power Saving Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5.1 How to Change Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5.2 Switching Master and Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5.3 Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5.4 Delay Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.5.5 Calculation of FIFO Pointer Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29-19
29-20
29-20
29-21
29-24
29-26
29-32
29-33
29-35
29-36
29-36
29-36
29-36
29-37
29-38
Chapter 30
UART Modules
30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1
30.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1
30.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2
30.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
30.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3
30.3.1 UART Mode Registers 1 (UMR1n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5
30.3.2 UART Mode Register 2 (UMR2n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6
30.3.3 UART Status Registers (USRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8
30.3.4 UART Clock Select Registers (UCSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9
30.3.5 UART Command Registers (UCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9
30.3.6 UART Receive Buffers (URBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11
30.3.7 UART Transmit Buffers (UTBn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-12
30.3.8 UART Input Port Change Registers (UIPCRn) . . . . . . . . . . . . . . . . . . . . . . . 30-12
30.3.9 UART Auxiliary Control Register (UACRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13
30.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn) . . . . . . . . . . . . . . . 30-13
30.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n) . . . . . . . . . . . . . . . 30-15
30.3.12 UART Input Port Register (UIPn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15
30.3.13 UART Output Port Command Registers (UOP1n/UOP0n) . . . . . . . . . . . . . . 30-16
30.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16
30.4.1 Transmitter/Receiver Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16
30.4.2 Transmitter and Receiver Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . 30-18
30.4.3 Looping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22
30.4.4 Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-24
30.4.5 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26
30.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26
30.5.1 Interrupt and DMA Request Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26
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30.5.2 UART Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-28
Chapter 31
I Interface
2C
31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1
31.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1
31.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
31.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2
31.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
31.2.1 I2C Address Register (I2ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
31.2.2 I2C Frequency Divider Register (I2FDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3
31.2.3 I2C Control Register (I2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4
31.2.4 I2C Status Register (I2SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5
31.2.5 I2C Data I/O Register (I2DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6
31.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7
31.3.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7
31.3.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8
31.3.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8
31.3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9
31.3.5 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9
31.3.6 Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9
31.3.7 Clock Synchronization and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-11
31.3.8 Handshaking and Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12
31.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12
31.4.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12
31.4.2 Generation of START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-12
31.4.3 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13
31.4.4 Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-13
31.4.5 Generation of Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14
31.4.6 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14
31.4.7 Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14
Chapter 32
Debug Module
32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1
32.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1
32.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1
32.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2
32.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3
32.3.1 Shared Debug Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4
32.3.2 Configuration/Status Register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5
32.3.3 BDM Address Attribute Register (BAAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8
32.3.4 Address Attribute Trigger Register (AATR) . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9
32.3.5 Trigger Definition Register (TDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-10
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32.3.6 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) . . . . . . . . .
32.3.7 Address Breakpoint Registers (ABLR, ABHR) . . . . . . . . . . . . . . . . . . . . . . .
32.3.8 Data Breakpoint and Mask Registers (DBR, DBMR) . . . . . . . . . . . . . . . . . .
32.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.4.1 Background Debug Mode (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.4.2 Real-Time Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.4.3 Concurrent BDM and Processor Operation . . . . . . . . . . . . . . . . . . . . . . . . .
32.4.4 Real-Time Trace Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.4.5 Processor Status, Debug Data Definition . . . . . . . . . . . . . . . . . . . . . . . . . . .
32.4.6 Freescale-Recommended BDM Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-13
32-15
32-16
32-17
32-17
32-38
32-40
32-40
32-43
32-49
Chapter 33
IEEE 1149.1 Test Access Port (JTAG)
33.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1
33.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1
33.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2
33.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2
33.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2
33.2.1 JTAG Enable (JTAG_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2
33.2.2 Test Clock Input (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3
33.2.3 Test Mode Select/Breakpoint (TMS/BKPT) . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3
33.2.4 Test Data Input/Development Serial Input (TDI/DSI) . . . . . . . . . . . . . . . . . . . 33-3
33.2.5 Test Reset/Development Serial Clock (TRST/DSCLK) . . . . . . . . . . . . . . . . . 33-4
33.2.6 Test Data Output/Development Serial Output (TDO/DSO) . . . . . . . . . . . . . . 33-4
33.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4
33.3.1 Instruction Shift Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4
33.3.2 IDCODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
33.3.3 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
33.3.4 TEST_CTRL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5
33.3.5 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
33.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
33.4.1 JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
33.4.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6
33.4.3 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7
33.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10
33.5.1 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10
33.5.2 Nonscan Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10
A.1 Changes Between Rev. 1 and Rev. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
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About This Book
The primary objective of this reference manual is to define the processor for software and hardware
developers. The information in this book is subject to change without notice, as described in the
disclaimers on the title page. As with any technical documentation, the reader must use the most recent
version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com/coldfire.
Portions of Chapter 20, “Universal Serial Bus Interface – On-The-Go Module,” relating to the EHCI
specification are Copyright © Intel Corporation 1999-2001. The EHCI specification is provided “As Is”
with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for
any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample.
Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of
information in the EHCI specification. Intel may make changes to the EHCI specifications at any time,
without notice.
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products with this ColdFire processor. It is assumed that the reader understands operating
systems, microprocessor system design, basic principles of software and hardware, and basic details of the
ColdFire® architecture.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about ColdFire architecture.
General Information
Useful information about the ColdFire architecture and computer architecture in general:
• ColdFire Programmers Reference Manual (MCF5200PRM/AD)
• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross
Bannatyne, Joseph D. Greenfield
• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David
A. Patterson.
• Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A.
Patterson and John L. Hennessy.
MCF52277 Reference Manual, Rev 2
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xxiii
ColdFire Documentation
ColdFire documentation is available from the sources listed on the back cover of this manual, as well as
our web site, http://www.freescale.com/coldfire.
• Reference manuals — These books provide details about individual ColdFire implementations and
are intended to be used in conjunction with the ColdFire Programmers Reference Manual.
• Data sheets — Data sheets provide specific data regarding pin-out diagrams, bus timing, signal
behavior, and AC, DC, and thermal characteristics, as well as other design considerations.
• Product briefs — Each device has a product brief that provides an overview of its features. This
document is roughly equivalent to the overview (Chapter 1) of an device’s reference manual.
• Application notes — These short documents address specific design issues useful to programmers
and engineers working with Freescale Semiconductor processors.
Additional literature is published as new processors become available. For a current list of ColdFire
documentation, refer to http://www.freescale.com/coldfire.
Conventions
This document uses the following notational conventions:
cleared/set
When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
MNEMONICS
In text, instruction mnemonics are shown in uppercase.
mnemonics
In code and tables, instruction mnemonics are shown in lowercase.
italics
Italics indicate variable command parameters.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
REG[FIELD]
Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, RAMBAR[BA] identifies the base address field
in the RAM base address register.
nibble
A 4-bit data unit
byte
An 8-bit data unit
word
A 16-bit data unit1
longword
A 32-bit data unit
x
In some contexts, such as signal encodings, x indicates a don’t care.
n
Used to express an undefined numerical value
~
NOT logical operator
&
AND logical operator
|
OR logical operator
1The
only exceptions to this appear in the discussion of serial communication modules that support variable-length data
transmission units. To simplify the discussion these units are referred to as words regardless of length.
MCF52277 Reference Manual, Rev 2
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||
OVERBAR
Field concatenation operator
An overbar indicates that a signal is active-low.
Register Figure Conventions
This document uses the following conventions for the register reset values:
—
Undefined at reset.
u
Unaffected by reset.
[signal_name]
Reset value is determined by the polarity of the indicated signal.
The following register fields are used:
R
0
Indicates a reserved bit field in a memory-mapped register. These bits are always read as zeros.
1
Indicates a reserved bit field in a memory-mapped register. These bits are always read as ones.
W
R
W
R FIELDNAME
Indicates a read/write bit.
W
R FIELDNAME
Indicates a read-only bit field in a memory-mapped register.
W
R
Indicates a write-only bit field in a memory-mapped register.
W FIELDNAME
R FIELDNAME
W
w1c
R
0
Write 1 to clear: indicates that writing a 1 to this bit field clears it.
Indicates a self-clearing bit.
W FIELDNAME
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Chapter 1
Overview
The MCF5227x devices are a family of highly-integrated 32-bit microprocessors based on the Version 2
ColdFire microarchitecture. All MCF5227x devices contain a 128-Kbyte internal SRAM, an LCD
controller, a touchscreen controller, a USB On-the-Go controller, a two-bank SDR/DDR SDRAM
controller, a 16-channel DMA controller, a serial boot facility, CAN module, a SSI interface, up to three
UARTs, a DMA SPI, as well as other peripherals that enable the MCF5227x family for use in .
This document provides details of the MCF5227x microprocessor family, focusing on its highly diverse
feature set. It was written from the perspective of the MCF52277 device. However, it also pertains to the
MCF52274. See the following section for a summary of differences between the various devices of the
MCF5227x family.
1.1
MCF5227x Family Comparison
The following table compares the various device derivatives available within the MCF5227x family.
Table 1-1. MCF5227x Family Configurations
Module
MCF52274
MCF52277
•
•
Core (System) Clock
up to 120 MHz
up to 166.67 MHz
Peripheral and External Bus Clock
(Core clock ÷ 2)
up to 60 MHz
up to 83.33 MHz
Performance (Dhrystone/2.1 MIPS)
up to 114
up to 159
ColdFire Version 2 Core with EMAC
(Enhanced Multiply-Accumulate Unit)
Static RAM (SRAM)
128 Kbytes
Configurable Cache
8 Kbytes
ASP Touchscreen Controller
•
•
12-bit color
18-bit color
USB 2.0 On-the-Go
•
•
FlexBus External Interface
•
•
SDR/DDR SDRAM Controller
•
•
FlexCAN 2.0B communication module
•
•
Real Time Clock
•
•
Watchdog Timer
•
•
LCD Controller
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
1-1
Overview
Table 1-1. MCF5227x Family Configurations (continued)
Module
MCF52274
MCF52277
16-channel Direct Memory Access
(DMA)
•
•
Interrupt Controllers (INTC)
1
1
Synchronous Serial Interface (SSI)
•
•
I2C
•
•
DSPI
•
•
UARTs
3
3
32-bit DMA Timers
4
4
Periodic Interrupt Timers (PIT)
2
2
PWM Module
•
•
Edge Port Module (EPORT)
•
•
General Purpose I/O Module (GPIO)
•
•
JTAG - IEEE® 1149.1 Test Access Port
•
•
176 LQFP
196 MAPBGA
Package
MCF52277 Reference Manual, Rev 2
1-2
Freescale Semiconductor
Overview
1.2
Block Diagram
Figure 1-1 shows a top-level block diagram of the MCF52277 superset device.
MCF52277
JTAG
Oscillator
Version 2 ColdFire Core
8K
Configurable
Cache
PLL
Serial Boot
Facility
BDM
Hardware
Divide
128K
SRAM
EMAC
USB OTG
LCD
Controller
eDMA
Crossbar Switch (XBS)
Peripheral Bridge
FlexBus
Touch
Screen
DSPI
RTC
SSI
FlexCAN
GPIO
EPORT
I2C
INTC
2 PITs
3 UARTs
4 DMA
Timers
SDRAM
Controller
PWM
LEGEND
BDM
DSPI
eDMA
EMAC
EPORT
GPIO
I2 C
INTC
JTAG
– Background debug module
– DMA serial peripheral interface
– Enhanced direct memory access
– Enchanced multiply-accumulate unit
– Edge port module
– General purpose input/output module
– Inter-intergrated circuit
– Interrupt controller
– Joint Test Action Group interface
LCD
PIT
PLL
PWM
RTC
SSI
UART
USB OTG
– Liquid-crystal display
– Programmable interrupt timer
– Phase-locked loop module
– Pulse-width modulator
– Real time clock
– Synchronous serial interface
– Universal asynchronous receiver/transmitter
– Universal Serial Bus On-the-Go controller
Figure 1-1. MCF52277 Block Diagram
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
1-3
Overview
1.3
•
•
1.4
Operating Parameters
-40ºC to 85ºC junction temperature devices are available
1.5V Core, 3.3V I/O, 1.8V/2.5V/3.3V external memory bus
Packages
Depending on device, the MCF5227x family is available in the following packages:
• 176-pin low-profile quad flat pack (LQFP)
• 196-pin molded array process ball grid array (MAPBGA)
1.5
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.6
Chip Level Features
Version 2 ColdFire® Core with EMAC
Up to 159 Dhrystone 2.1 MIPS @ 166.67 MHz
8 Kbytes configurable cache (instruction only, data only, or split instruction/data)
128 Kbytes internal SRAM
Support for booting from SPI-compatible flash, EEPROM, and FRAM devices
Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus
masters
16 channel DMA controller
16- or 32-bit SDR/DDR controller
USB 2.0 On-the-Go controller
Liquid crystal display controller
Touchscreen controller
FlexCAN module
4 32-bit timers with DMA support
DMA supported serial peripheral interface (DSPI)
3 UARTs
I2C bus interface
Synchronous serial interface (SSI)
Plus-width modulator (PWM)
Real-time clock (RTC)
Two programmable interrupt controllers (PIT)
Module-by-Module Feature List
The following is a brief summary of the functional blocks in the MCF52277 superset device. For more
details refer to the MCF52277 ColdFire Microprocessor Reference Manual (MCF52277RM).
MCF52277 Reference Manual, Rev 2
1-4
Freescale Semiconductor
Overview
1.6.1
•
•
•
•
•
•
•
1.6.2
•
•
1.6.3
•
•
1.6.4
•
•
•
•
1.6.5
•
•
•
•
•
1.6.6
•
Version 2 ColdFire Variable-Length RISC Processor
Static operation
32-bit address and data path on-chip
Maximum 166.67 MHz processor core and 83.33 MHz bus frequency
Sixteen total general-purpose 32-bit registers data and address
Enhanced multiply-accumulate unit (EMAC) for DSP and fast multiply operations
Hardware divide execution unit supporting various 32-bit operations
Implements the ColdFire Instruction Set Architecture, ISA_A+
On-chip Memories
128 Kbyte dual-ported SRAM on CPU internal bus
— Accessible to non-core bus masters (e.g. DMA, USB OTG, and LCD controller) via the
crossbar switch
8 Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
Phase Locked Loop (PLL)
16–40 MHz reference crystal
Loss-of-lock detection
Power Management
Fully static operation with processor sleep and whole chip stop modes
Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
Peripheral power management register to enable/disable clocks to most modules
Software controlled disable of external clock input for low power consumption
Chip Configuration Module (CCM)
System configuration during reset
Bus monitor
Configurable output pad drive strength control
Unique part identification and part revision numbers
Serial boot capability
— Supports SPI-compatible EEPROM, flash, and FRAM
— Configurable boot clock frequency
Reset Controller
Separate reset in and reset out signals
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
1-5
Overview
•
•
Six sources of reset: power-on reset (POR), external, software, watchdog timer, loss of lock, JTAG
instruction
Status flag indication of source of last reset
1.6.7
•
•
•
System Control Module
Access control registers
Core watchdog timer with a 2n (where n = 8–31) clock cycle selectable timeout period
Core fault reporting
1.6.8
•
•
•
Crossbar Switch Module
Concurrent access from different masters to different slaves
Slave arbitration attributes configured on a slave by slave basis
Fixed or round-robin arbitration
1.6.9
•
•
•
•
•
Liquid Crystal Display Controller (LCDC)
Support for single (non-split) screen monochrome/color LCD panels and self-refresh type LCD
panels
16 simultaneous gray-scale levels from a palette of 16 for monochrome display
Maximum supported panel size of 600 × 800 pixels
4(mapped to RGB444)/8(RGB444)/12 bits per pixel (bpp) for passive color panel
4(mapped to RGB666)/8(mapped to RGB666)/12(RGB444)/16(RGB565)/18 bpp for TFT
1.6.10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Touchscreen Controller
12-bit 125 kS/s ADC for touchscreen
Ratiometric measurements
Touch/pressure measurements
Supports 4/5/7 and 8-wire touchscreen configurations
Supports automatic sampling, single-round sampling, and manual sampling modes
Provides data-ready and FIFO-full interrupts
Pen-down detection circuitry to generate pen interrupt request
True differential input
Built-in selectable reference generator
Support for temperature compensation by software
Power-down capability
1.5/3.3 V dual power supply
Internal or external reference
Conversion executed synchronously to bus clock
MCF52277 Reference Manual, Rev 2
1-6
Freescale Semiconductor
Overview
•
Triggerable through software and/or external hardware
1.6.11
•
•
Support for full speed (FS) and low speed (LS) via an on-chip FS/LS transceiver
Uses 60 MHz reference clock based off of the system clock or from an external pin
1.6.12
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FlexBus (External Interface)
Glueless connections to 8-, 16-, and 32-bit external memory devices (SRAM, flash, ROM, etc.)
Support for independent primary and secondary wait states per chip select
Programmable address setup and hold time with respect to chip-select assertion, per transfer
direction
Glueless interface to SRAM devices with or without byte strobe inputs
Programmable wait state generator
32-bit external bidirectional data bus and 24-bit address bus
Up to six chip selects available
Byte/write enables (byte strobes)
Ability to boot from external memories that are 8, 16, or 32 bits wide
Shares address and data bus with the SDRAM controller
1.6.14
•
•
•
•
SDR/DDR SDRAM Controller
Supports a glueless interface to SDR and DDR SDRAM devices
Support for 16- or 32-bit fixed memory port width for SDR SDRAM devices; 16-bit fixed memory
port width for DDR SDRAM devices.
16-byte critical word first burst transfer
Up to 13 lines of row address, up to 12 (32-bit bus) or 13 (16-bit bus) column address lines, 2 bits
of bank address, and two pinned-out chip selects. The maximum row bits plus column bits equals
24 in 32-bit bus mode or 25 in 16-bit bus mode.
Supports up to 512 MByte of memory; minimum memory configuration of 8 MByte
Supports page mode to maximize the data rate
Supports sleep mode and self-refresh mode
Shares address and data bus with the FlexBus interface
1.6.13
•
•
•
Universal Serial Bus (USB) 2.0 On-The-Go (OTG) Controller
Synchronous Serial Interface (SSI)
Supports shared (synchronous) transmit and receive sections
Normal mode operation using frame sync
Network mode operation allowing multiple devices to share the port with as many as 32 time slots
Gated clock mode operation requiring no frame sync
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
1-7
Overview
•
•
•
Programmable data interface modes such as I2S, LSB aligned, and MSB aligned
Programmable word length up to 24 bits
AC97 support
1.6.15
•
•
•
•
•
•
•
•
•
Full implementation of the CAN protocol specification version 2.0B
— Standard data and remote frames (up to 109 bits long)
— Extended data and remote frames (up to 127 bits long)
— 0–8 bytes data length
— Programmable bit rate up to 1 Mbit/sec
Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 bytes data length each,
configurable as Rx or Tx, all supporting standard and extended messages
Unused MB space can be used as general purpose RAM space
Listen-only mode capability
Content-related addressing
Three programmable mask registers: global (for MBs 0-13), special for MB14 and special for
MB15
Programmable transmit-first scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
1.6.16
•
•
•
•
•
•
•
Programmable Interrupt Timers (PIT)
Two programmable interrupt timers each with a 16-bit counter
Configurable as a down counter or free-running counter
1.6.18
•
Real-Time Clock
Full clock: days, hours, minutes, seconds
Minute countdown timer with interrupt
Programmable daily alarm with interrupt
Sampling timer with interrupt
Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts
Operation determined by reference input oscillator clock frequency and value programmed into
user-accessible registers
Ability to wake the processor from low-power modes (wait, doze, and stop) via the RTC interrupts
1.6.17
•
•
FlexCAN Module
DMA Timers
Four 32-bit timers with DMA and interrupt request trigger capability
MCF52277 Reference Manual, Rev 2
1-8
Freescale Semiconductor
Overview
•
Input capture and reference compare modes
1.6.19
•
•
•
•
Full-duplex, three-wire synchronous transfer
Up to three chip selects available
Master and slave modes with programmable master bit-rates
Up to 16 pre-programmed transfers
1.6.20
•
•
•
•
•
•
•
•
I2C Module
Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
Fully compatible with industry-standard I2C bus
Master or slave modes support multiple masters
Automatic interrupt generation with programmable level
1.6.23
•
Universal Asynchronous Receiver Transmitters (UARTs)
16-bit divider for clock generation
Interrupt control logic
DMA support with separate transmit and receive requests
Programmable clock-rate generator
Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
Up to 2 stop bits in 1/16 increments
Error-detection capabilities
1.6.22
•
•
•
•
Pulse Width Modulation (PWM) Module
Four independent PWM channels with programmable period and duty cycle
Dedicated counter for each PWM channel
Programmable PWM enable/disable for each channel
Software selection of PWM duty pulse polarity for each channel
1.6.21
•
•
•
•
•
•
•
DMA Serial Peripheral Interface (DSPI)
Interrupt Controllers
Two interrupt controllers, supporting up to 64 interrupt sources each, organized as seven
programmable levels
Unique vector number for each interrupt source
Ability to mask any individual interrupt source plus a global mask-all capability
Support for service routine software interrupt acknowledge (IACK) cycles
Combinational path to provide wake-up from low power modes
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
1-9
Overview
1.6.24
•
•
Each pin can be individually configured as low level sensistive interrupt pin or edge-detecting
interrupt pin (rising, falling, or both)
Exit stop mode via level-detect function
1.6.25
•
•
•
•
•
•
1.7
System Debug Support
Background debug mode (BDM) Revision B+
Real time debug support, with four PC breakpoint registers and a pair of address breakpoint
registers with optional data
1.6.28
•
General Purpose I/O interface
Up to 47 bits of GPIO for the MCF52274 (176 LQFP)
Up to 55 bits of GPIO for the MCF52277 (196 MAPBGA)
Bit manipulation supported via set/clear functions
Various unused peripheral pins may be used as GPIO
1.6.27
•
•
DMA Controller
16 fully programmable channels with 32-byte transfer control
Data movement via dual-address transfers for 8-, 16-, 32- and 128-bit data values
Programmable source, destination addresses, transfer size, support for enhanced address modes
Support for major and minor nested counters with one request and one interrupt per channel
Support for channel-to-channel linking and scatter/gather for continuous transfers with fixed
priority and round-robin channel arbitration
External request pins for one channel
1.6.26
•
•
•
•
Edge Port Module
JTAG Support
JTAG part identification and part revision numbers
Memory Map Overview
Table 1-2 illustrates the overall memory map of the device.
Table 1-2. System Memory Map
Internal
Address[31:28]
Address Range
Destination Slave
Slave Memory Size
00xx
0x0000_0000–0x3FFF_FFFF
FlexBus
1024 MB
01xx
0x4000_0000–0x7FFF_FFFF
SDRAM Controller
1024 MB
1000
0x8000_0000–0x8FFF_FFFF
Internal SRAM
256 MB1
MCF52277 Reference Manual, Rev 2
1-10
Freescale Semiconductor
Overview
Table 1-2. System Memory Map (continued)
Internal
Address[31:28]
Address Range
Destination Slave
Slave Memory Size
1001, 101x
0x9000_0000–0xBFFF_FFFF
Reserved
256 MB
110x
0xC000_0000–0xDFFF_FFFF
FlexBus
512 MB
1110
0xE000_0000–0xEFFF_FFFF
Reserved
256 MB
1111
0xF000_0000–0xFFFF_FFFF
Internal Peripheral Space
256 MB
1
The actual size of the SRAM is 128 KByte. However, it may be placed anywhere within the 256 MB space
using the RAMBAR register.
NOTE
This memory map provides two disjointed regions mapped to the FlexBus
controller. The first region gives support for glueless connections to
external memories (flash and SRAM). The second space (starting at
0xC000_0000) gives support for one (or more) unique chip-selects that can
be used for non-cacheable, non-memory devices. Additionally, this
mapping is selected because it easily maps into the ColdFire access control
registers, which provide a coarse association between memory addresses
and their attributes (cacheable, non-cacheable). For this device, one possible
configuration defines the default memory attribute as non-chacheable, and
one ACR is then used to identify cacheable addresses, e.g., ADDR[31] set
to zero identifies the cacheable space.
1.7.1
Internal Peripheral Space
The internal peripheral space contains locations for all internal registers used to program and control the
device’s functional blocks and external interfaces. Table 1-3 summarizes the various register spaces and
their base addresses. Each slot is 16 kB in size, which is not necessarily taken up entirely by the functional
blocks. Any slot not illustrated is reserved. See corresponding chapter for details on their individual
memory maps.
Table 1-3. Internal Peripheral Space Memory Map
Base Address
Slot Number
Peripheral
0xFC00_0000
0
SCM (MPR & PACRs)
0xFC00_4000
1
Crossbar switch
0xFC00_8000
2
FlexBus
0xFC02_0000
8
FlexCAN
0xFC03_C000
15
Real-Time Clock
0xFC04_0000
16
SCM (CWT & Core Fault Registers)
0xFC04_4000
17
eDMA Controller
0xFC04_8000
18
Interrupt Controller 0
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
1-11
Overview
Table 1-3. Internal Peripheral Space Memory Map (continued)
1.8
Base Address
Slot Number
Peripheral
0xFC04_C000
19
Interrupt Controller 1
0xFC05_4000
21
Interrupt Controller IACK
0xFC05_8000
22
I2C
0xFC05_C000
23
DSPI
0xFC06_0000
24
UART0
0xFC06_4000
25
UART1
0xFC06_8000
26
UART2
0xFC07_0000
28
DMA Timer 0
0xFC07_4000
29
DMA Timer 1
0xFC07_8000
30
DMA Timer 2
0xFC07_C000
31
DMA Timer 3
0xFC08_0000
32
PIT 0
0xFC08_4000
33
PIT 1
0xFC09_0000
36
PWM
0xFC09_4000
37
Edge Port
0xFC0A_0000
40
CCM, Reset Controller, Power Management
0xFC0A_4000
41
GPIO Module
0xFC0A_8000
42
Touchscreen Controller
0xFC0A_C000
43
LCD Controller
0xFC0B_0000
44
USB On-the-Go
0xFC0B_8000
46
SDRAM Controller
0xFC0B_C000
47
SSI
0xFC0C_0000
48
PLL
Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale
Literature Distribution Center, or through the Freescale world-wide web address at
http://www.freescale.com/coldfire.
MCF52277 Reference Manual, Rev 2
1-12
Freescale Semiconductor
Chapter 2
Signal Descriptions
2.1
Introduction
This chapter describes the external signals on the device. It includes an alphabetical signal listing of signals
that characterizes each signal as an input or output, defines its state at reset, and identifies whether a
pull-up resistor should be used.
NOTE
The terms assertion and negation are used to avoid confusion when dealing
with a mixture of active-low and active-high signals. The term asserted
indicates that a signal is active, independent of the voltage level. The term
negated indicates that a signal is inactive.
Active-low signals, such as SD_SRAS and TA, are indicated with an
overbar.
2.2
Signal Properties Summary
The below table lists the signals grouped by functionality.
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., FB_A23), while designations for
multiple signals within a group use brackets (i.e., FB_A[23:21]) and is
meant to include all signals within the two bracketed numbers when these
numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Most pins that are muxed with GPIO will default to their GPIO
functionality. See Table 2-1 for a list of the exceptions.
Table 2-1. Special-Case Default Signal Functionality
Pin
Default Signal
FB_BE/BWE[3:0]
FB_BE/BWE[3:0]
FB_CS[3:0]
FB_CS[3:0]
FB_OE
FB_OE
FB_TA
FB_TA
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
2-1
Signal Descriptions
Table 2-1. Special-Case Default Signal Functionality (continued)
Pin
Default Signal
FB_R/W
FB_R/W
FB_TS
FB_TS
Pull-up (U)1
Pull-down (D)
Direction2
Voltage
Domain
Table 2-2. MCF5227x Signal Information and Muxing
MCF52274
176 LQFP
RESET
—
—
—
U
I
EVDD
103
J11
RSTOUT
—
—
—
—
O
EVDD
102
K11
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52277
196 MAPBGA
Reset
Clock
EXTAL
—
—
—
—
I
EVDD
106
F14
XTAL
—
—
—
U3
O
EVDD
105
G14
—
I
EVDD
110, 109
G10, H10
Mode Selection
BOOTMOD[1:0]
—
—
—
FlexBus
FB_A[23:22]
—
FB_CS[5:4]
—
—
O
SDVDD
143, 142
C11, D11
FB_A[21:16]
—
—
—
—
O
SDVDD
141–139,
137–135
A12, B12, C12,
B13, A13, A14
FB_A[15:14]
—
SD_BA[1:0]
—
—
O
SDVDD
131, 130
B14, C13
FB_A[13:11]
—
SD_A[13:11]
—
—
O
SDVDD
129–127
C14, D12, D13
FB_A10
—
—
—
O
SDVDD
126
D14
FB_A[9:0]
—
SD_A[9:0]
—
O
SDVDD
125–116
E11–E14,
F11–F13, G11,
G12, H11
FB_D[31:16]
—
SD_D[31:16]
—
I/O
SDVDD
30–37, 49–56
J4, K1–K4, L1–L3,
M3, N3, P3,M4,
N4, P4, L5, M5
FB_D[15:0]
—
FB_D[31:16]
—
I/O
SDVDD
19–26, 60–67
G1–G4, H1–H4,
M6, N6, P6, L7,
M7, N7, P7, L8
FB_CLK
—
—
—
O
SDVDD
42
P1
FB_BE/BWE[3:0]
PBE[3:0]
SD_DQM[3:0]
—
—
O
SDVDD
29, 57, 27, 59
J3, N5, J1, L6
FB_CS[3:2]
PCS[3:2]
—
—
—
O
SDVDD
—
B11, A11
FB_CS1
PCS1
SD_CS1
—
—
O
SDVDD
144
D10
MCF52277 Reference Manual, Rev 2
2-2
Freescale Semiconductor
Signal Descriptions
Alternate 1
Alternate 2
FB_CS0
PCS0
—
—
—
FB_OE
PFBCTL3
—
—
—
FB_TA
PFBCTL2
—
—
FB_R/W
PFBCTL1
—
FB_TS
PFBCTL0
DACK0
Voltage
Domain
GPIO
Direction2
Signal Name
Pull-up (U)1
Pull-down (D)
Table 2-2. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
O
SDVDD
145
C10
O
SDVDD
69
N8
U
I
SDVDD
115
H12
—
—
O
SDVDD
68
M8
—
—
O
SDVDD
15
F4
SDRAM Controller
SD_A10
—
—
—
—
O
SDVDD
46
L4
SD_CAS
—
—
—
—
O
SDVDD
47
N2
SD_CKE
—
—
—
—
O
SDVDD
17
F2
SD_CLK
—
—
—
—
O
SDVDD
40
M1
SD_CLK
—
—
—
—
O
SDVDD
41
N1
SD_CS0
—
—
—
—
O
SDVDD
18
F1
SD_DQS[3:2]
—
—
—
—
I/O
SDVDD
28, 58
J2, P5
SD_RAS
—
—
—
—
O
SDVDD
48
P2
SD_SDR_DQS
—
—
—
—
O
SDVDD
38
M2
SD_WE
—
—
—
—
O
SDVDD
16
F3
External Interrupts Port4
IRQ7
PIRQ7
—
—
—
I
EVDD
162
D7
IRQ4
PIRQ4
DREQ0
DSPI_PCS4
5
I
EVDD
161
C7
IRQ1
PIRQ1
USB_CLKIN
SSI_CLKIN
—
I
EVDD
160
B7
LCD Controller6
LCD_D[17:16]6
PLCDDH[1:0]
LCD_D[11:10]
—
—
O
EVDD
9, 8
E3, E4
LCD_D[15:14]6
PLCDDM[7:6]
LCD_D[9:8]
—
—
O
EVDD
7, 6
D1, D2
LCD_D13
PLCDDM5
CANTX
—
—
O
EVDD
—
C1
LCD_D12
PLCDDM4
CANRX
—
—
O
EVDD
—
C2
LCD_D[11:8]6
PLCDDM[3:0]
LCD_D[7:4]
—
—
O
EVDD
5–2
D3, C3, D4, B1
LCD_D7
PLCDDL7
PWM7
—
—
O
EVDD
—
B2
LCD_D6
PLCDDL6
PWM5
—
—
O
EVDD
—
A1
LCD_D[5:2]6
PLCDDL[5:2]
LCD_D[3:0]
—
—
O
EVDD
175–172
A2, A3, B3, A4
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
2-3
Signal Descriptions
Alternate 1
Alternate 2
LCD_D1
PLCDDL1
PWM3
—
—
LCD_D0
PLCDDL0
PWM1
—
—
LCD_ACD/
LCD_OE
PLCDCTL3
LCD_SPL_SPR
—
LCD_FLM/
LCD_VSYNC
PLCDCTL2
—
LCD_LP/
LCD_HSYNC
PLCDCTL1
LCD_LSCLK
PLCDCTL0
Voltage
Domain
GPIO
Direction2
Signal Name
Pull-up (U)1
Pull-down (D)
Table 2-2. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
O
EVDD
—
B4
O
EVDD
—
C4
—
O
EVDD
169
B5
—
—
O
EVDD
10
E2
—
—
—
O
EVDD
11
E1
—
—
—
O
EVDD
170
A5
USB On-the-Go
USB_DM
—
—
—
—
O
USB
VDD
149
A9
USB_DP
—
—
—
—
O
USB
VDD
150
A10
Real Time Clock
RTC_EXTAL
—
—
—
—
I
EVDD
100
J14
RTC_XTAL
—
—
—
—
O
EVDD
99
K14
Touchscreen Controller
ADC_IN[7:0]
—
—
—
—
I
VDD_
ADC
82–85, 87–90
P12, N12, P13,
N13, P14, N14,
M13, M14
ADC_REF
—
—
—
—
I
VDD_
ADC
86
M12
I2C
I2C_SCL
PI2C1
CANTX
U2TXD
U
I/O
EVDD
168
C5
I2C_SDA
PI2C0
CANRX
U2RXD
U
I/O
EVDD
167
D5
DSPI7
DSPI_PCS0/SS
PDSPI3
U2RTS
—
U
I/O
EVDD
152
B9
DSPI_SIN
PDSPI2
U2RXD
SBF_DI
8
I
EVDD
155
D8
DSPI_SOUT
PDSPI1
U2TXD
SBF_D0
—
O
EVDD
154
D9
DSPI_SCK
PDSPI0
U2CTS
SBF_CK
—
I/O
EVDD
153
C9
—
I
EVDD
156
C8
UARTs
U1CTS
PUART7
SSI_BCLK
LCD_CLS
MCF52277 Reference Manual, Rev 2
2-4
Freescale Semiconductor
Signal Descriptions
Alternate 1
Alternate 2
U1RTS
PUART6
SSI_FS
LCD_PS
—
U1TXD
PUART5
SSI_TXD
—
—
U1RXD
PUART4
SSI_RXD
—
U0CTS
PUART3
DT1OUT
U0RTS
PUART2
U0TXD
U0RXD
Voltage
Domain
GPIO
Direction2
Signal Name
Pull-up (U)1
Pull-down (D)
Table 2-2. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
O
EVDD
157
B8
O
EVDD
159
A7
—
I
EVDD
158
A8
USB_VBUS_EN
—
I
EVDD
97
K12
DT1IN
USB_VBUS_OC
—
O
EVDD
98
J12
PUART1
CANTX
—
—
O
EVDD
95
L12
PUART0
CANRX
—
—
I
EVDD
96
K13
DMA Timers
DT3IN
PTIMER3
DT3OUT
SSI_MCLK
—
I
EVDD
163
D6
DT2IN/SBF_CS7
PTIMER2
DT2OUT
DSPI_PCS2
—
I
EVDD
164
C6
DT1IN
PTIMER1
DT1OUT
LCD_CONTRAST
—
I
EVDD
165
B6
DT0IN
PTIMER0
DT0OUT
LCD_REV
—
I
EVDD
166
A6
BDM/JTAG9
PST[3:0]
—
—
—
—
O
EVDD
—
L9, M9, N9, P9
DDATA[3:0]
—
—
—
—
O
EVDD
—
L10, M10, N10,
P10
ALLPST
—
—
—
—
O
EVDD
76
—
JTAG_EN
—
—
—
D
I
EVDD
79
K10
PSTCLK
—
TCLK
—
U
O
EVDD
74
P8
DSI
—
TDI
—
U
I
EVDD
78
M11
DSO
—
TDO
—
—
O
EVDD
81
L11
BKPT
—
TMS
—
U
I
EVDD
80
N11
DSCLK
—
TRST
—
U
I
EVDD
77
P11
—
D
I
EVDD
134
E10
Test
TEST
—
—
Power Supplies
IVDD
—
—
—
—
—
—
39, 75, 114, 138,
171
K5, F10, E5, J10
EVDD
—
—
—
—
—
—
12, 72, 73, 94,
111, 148, 176
E6, E7, F5, F6,
G5, H9, J9, K8, K9
SD_VDD
—
—
—
—
—
—
14, 43, 44, 70,
113, 132, 146
E8, E9, F9, G9,
H5, J5, J6, K6, K7
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
2-5
Signal Descriptions
1
2
3
4
5
6
7
8
9
Alternate 1
Alternate 2
VDD_OSC
—
—
—
—
VDD_PLL
—
—
—
—
VDD_USB
—
—
—
VDD_RTC
—
—
VDD_ADC
—
VSS
Voltage
Domain
GPIO
Direction2
Signal Name
Pull-up (U)1
Pull-down (D)
Table 2-2. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
—
—
108
G13
—
—
104
H14
—
—
—
151
B10
—
—
—
—
101
J13
—
—
—
—
—
91
L13
—
—
—
—
—
—
1, 13, 45, 71, 93,
112, 133, 147
F7, F8, G6–G8,
H6–H8, J7, J8
VSS_OSC
—
—
—
—
—
—
107
H13
VSS_ADC
—
—
—
—
—
—
92
L14
Pull-ups are generally only enabled on pins with their primary function, except as noted.
Refers to pin’s primary function.
Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.
Pull-up when DREQ controls the pin.
The 176 LQFP device only supports a 12-bit LCD data bus.
DSPI or SBF signal functionality is controlled by RESET. When asserted, these pins are configured for serial boot; when negated, the
pins are configured for DSPI.
Pull-up when the serial boot facility (SBF) controls the pin.
If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these
pins.
2.3
Signal Primary Functions
2.3.1
Reset Signals
Table 2-3 describes signals used to reset the chip or to indicate a reset.
Table 2-3. Reset Signals
Signal Name
Abbreviation
Function
I/O
Reset In
RESET
Primary reset input to the device. Asserting RESET resets the core and
peripherals after four FB_CLK cycles. Asserting RESET also causes
RSTOUT to be asserted.
I
Reset Out
RSTOUT
Reset output is an indicator that the chip is in reset. RSTOUT is
asserted at least 512 internal system bus clock cycles in response to
any internal or external reset. (The exact time depends on how long it
takes for the PLL to lock and/or the serial boot sequence to complete.)
O
MCF52277 Reference Manual, Rev 2
2-6
Freescale Semiconductor
Signal Descriptions
2.3.2
PLL and Clock Signals
Table 2-4 describes signals that are used to support the on-chip clock generation circuitry.
Table 2-4. PLL and Clock Signals
Signal Name
Abbreviation
Function
I/O
External Clock In
EXTAL
Always driven by an external clock input except when used as a
connection to the external crystal if the internal oscillator circuit is
used. Clock source may be configured during reset. See Chapter 9,
“Chip Configuration Module (CCM),” for more details.
I
Crystal
XTAL
Used as a connection to the external crystal when the internal
oscillator circuit is used to drive the crystal.
O
RTC External Clock In
RTC_EXTAL
Crystal input clock for the real-time clock module.
I
RTC Crystal
RTC_XTAL
Oscillator output to RTC crystal.
O
FlexBus Clock Out
FB_CLK
Reflects the internal bus clock (or one-half the core/system clock).
(fsys/2)
O
USB Clock In
USB_CLKIN
This pin allows the user to drive the reference clock to the USB module
as an alternate method of generating the USB reference clock during
FS/LS operation. This pin should be driven only with a 60 MHz clock.
I
SSI Clock In
SSI_CLKIN
This pin allows the user to drive a specific clock frequency to the SSI
module.
I
2.3.3
Mode Selection
Table 2-5. Mode Selection Signals
Signal Name
Boot Mode
2.3.4
Abbreviation
Function
BOOTMOD[1:0] Indicates the device’s boot mode and chip configuration at reset. See
Chapter 9, “Chip Configuration Module (CCM),” for the signal
encodings.
I/O
I
FlexBus Signals
Table 2-6 describes signals that are used for performing transactions on the external bus.
Table 2-6. FlexBus Signals
Signal Name
Abbreviation
Function
I/O
Address Bus
FB_A[23:0]
Defines address of external byte, word, and longword accesses.
These three-state outputs are the 24 lsbs of the internal 32-bit
address bus.
O
Data Bus
FB_D[31:0]
These three-state bidirectional signals provide the general purpose
data path between the processor and all other devices.
I/O
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
2-7
Signal Descriptions
Table 2-6. FlexBus Signals (continued)
Signal Name
Byte Enables
Abbreviation
Function
I/O
FB_BE/BWE[3:0] Defines flow of data on data bus. During peripheral accesses, these
output signals indicate that data is to be latched or driven onto a byte
of the data bus when driven low. The BE/BWE[3:0] signals are
asserted only to the memory bytes used during a read or write access.
BE/BWE0 controls access to the most significant byte lane of data,
and BE/BWE3 controls access to the least significant byte lane of
data.
O
For SRAM or Flash devices, the BE/BWEn outputs should be
connected to individual byte strobe signals.
Chip Selects
FB_CS[5:0]
Select external devices for external bus transactions.
O
Output Enable
FB_OE
Indicates when an external device can drive data during external read
cycles.
O
Transfer Acknowledge
FB_TA
Indicates external data transfer is complete. During a read cycle, when
the processor recognizes FB_TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes FB_TA, the bus cycle is terminated.
I
Read/Write
FB_R/W
Indicates direction of the data transfer on the bus for SRAM accesses.
A logic 1 indicates a read from a slave device and a logic 0 indicates
a write to a slave device.
O
Transfer Start
FB_TS
Bus control output signal indicating the start of a transfer.
O
2.3.5
SDRAM Controller Signals
Table 2-7 describes signals used for SDRAM accesses.
Table 2-7. SDRAM Controller Signals
Signal Name
Abbreviation
Function
I/O
Address Bus
SD_A[13:0]
Address bus used for multiplexed row and column addresses during
SDRAM bus cycles.
O
Data Bus
SD_D[31:16]
Bidirectional, non-multiplexed data bus for SDRAM accesses.
I/O
Bank Address
SD_BA[1:0]
Selects one of the four SDRAM row banks.
O
Clock Enable
SD_CKE
SDRAM clock enable.
O
DDR Clock
SD_CLK
Output clock for DDR SDRAM.
O
DDR Clock
SD_CLK
Inverted output clock for DDR SDRAM.
O
Chip Selects
SD_CS[1:0]
SDRAM chip select signals.
O
DDR Data Strobes
SD_DQS[3:2]
Indicates when valid data is on data bus.
I/O
Write Data Byte Mask
SD_DQM[3:0]
Used to determine which byte lanes of data bus should be latched
during a write cycle.
The SD_DQMn should be connected to individual SDRAM DQM
signals. Most SDRAMs associate DQM3 with the MSB, in which case
SD_DQM3 should be connected to the SDRAM's DQM3 input.
O
MCF52277 Reference Manual, Rev 2
2-8
Freescale Semiconductor
Signal Descriptions
Table 2-7. SDRAM Controller Signals (continued)
Signal Name
Abbreviation
Function
I/O
Column Address Strobe
SD_CAS
SDRAM column address strobe.
O
Row Address Strobe
SD_RAS
SDRAM row address strobe.
O
SDR Data Strobe
SD_SDRDQS
Generated by the memory controller in SDR mode, to mimic the DQS
signal generated by DDR memories during reads. It is routed out and
connected back to SD_DQS inputs.
O
Write Enable
SD_WE
Indicates direction of data transfer on bus for SDRAM accesses. A
logic 1 indicates a read from a slave device and a logic 0 indicates a
write to a slave device.
O
2.3.6
Serial Boot Facility Signals
Table 2-8. SBF Signals
Signal Name
Abbreviation
Function
I/O
Chip Select
SBF_CS
Chip select used to access external SPI memory.
O
Clock
SBF_CK
25 MHz clock source for external SPI memory.
O
Data In
SBF_DI
Data being driven by SPI memory.
I
Data Out
SBF_DO
Data out to SPI memory. SBF uses this output solely for the purpose
of issuing the SPI memory READ command. SBF does not write data
to SPI memory.
O
2.3.7
External Interrupt Signals
Table 2-9. External Interrupt Signals
Signal Name
External Interrupts
2.3.8
Abbreviation
IRQ[7,4,1]
Function
External interrupt sources.
I/O
I
DMA Signals
Table 2-10. DMA Signals
Signal Name
Abbreviation
Function
I/O
DMA Request
DREQ0
Asserted by an external device to request a DMA transfer.
I
DMA Acknowledge
DACK0
Asserted by processor to indicate DMA request has been recognized.
O
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
2-9
Signal Descriptions
2.3.9
LCD Controller Signals
Table 2-10 describes the LCD controller signals.
Table 2-11. LCD Signals
Signal Name
Abbreviation
Function
I/O
Line Data
LCD_D[17:0]
LCD data bus.
O
First Line Marker/
Vertical Sync
LCD_FLM/
LCD_VSYNC
Passive matrix: First line marker
Active matrix: Vertical sync pulse. Indicates start of next frame.
O
Line Pulse/
Horizontal Sync
LCD_LP/
LCD_HSYNC
Passive matrix: Line pulse
Active matrix: Horizontal sync pulse. Indicates start of next line.
O
Shift Clock
LCD_LSCLK
Clock for latching data into the display driver’s internal shift register.
O
Alt. Crystal Direction/
Output Enable
LCD_ACD/
LCD_OE
Passive matrix: Alternate crystal direction
Active matrix: Output enable to enable data to be shifted onto the
display.
O
Contrast
LCD_CONTRAST Controls the LCD bias voltage for contrast control.
O
Power Save
LCD_PS
Controls signal output for source driver (Sharp HR-TFT 240x320
panels only).
O
Gate Driver Clock
Signal
LCD_CLS
Start signal output for gate driver, inverted version of LCD_PS (Sharp
HR-TFT 240x320 panels only).
O
Reverse Control
LCD_REV
Signal for common electrode driving signal preparation (Sharp
HR-TFT 240x320 panels only).
O
Sampling Start Signal
LCD_SPL_SPR
Sets the horizontal scan direction (Sharp HR-TFT 240x320 panels
only).
O
2.3.10
FlexCAN Signals
Table 2-12 describes the FlexCAN module signals.
Table 2-12. FlexCAN Signals
Signal Name
Abbreviation
Function
I/O
FlexCAN Transmit
CANTX
Controller area network transmit data output.
O
FlexCAN Receive
CANRX
Controller area network receive data input.
I
2.3.11
Pulse Width Modulation (PWM) Module Signals
The following table describes the signals for the PWM module.
Table 2-13. PWM Module Signals
Signal Name
Abbreviation
Function
I/O
PWM7 Output
PWM7
Waveform output for channel 7 of the PWM module. Also functions as
an input for the emergency shutdown feature of the PWM.
I/O
PWM[5,3,1,0] Outputs
PWM[5,3,1,0]
Waveform output for channels 5, 3, 1, and 0 respectively.
O
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Signal Descriptions
2.3.12
Universal Serial Bus (USB) On-the-Go Signals
Table 2-14. USB Module Signals
Signal Name
Abbreviation
Function
I/O
USB D-
USB_DM
D- output of the dual-speed transceiver for the On-the-Go module.
O
USB D+
USB_DP
D+ output of the dual-speed transceiver for the On-the-Go module.
O
USB VBUS Enable
USB_VBUS_EN
Enables the off-chip VBUS charge pump when USB OTG module is
configured as a host.
O
Indicates to the processor that a short has occurred on USB data
bus.
I
USB VBUS over-current USB_VBUS_OC
2.3.13
Touschreen Controller Signals
Table 2-15. Touchscreen Signals
Signal Name
Abbreviation
Function
I/O
Reference
ADC_REF
External ADC reference voltage
I
Touchscreen Inputs
ADC_IN[7:0]
Touchscreen inputs. ADC_IN[7:0] serves as a touchscreen interface.
I
2.3.14
I2C I/O Signals
Table 2-16. I2C I/O Signals
Signal Name
Abbreviation
Function
I/O
Serial Clock
I2C_SCL
Open-drain clock signal. It is driven by the I2C module when the bus
is in master mode, or it becomes the clock input when the I2C is in
slave mode.
I/O
Serial Data
I2C_SDA
Open-drain signal serving as the I2C data input/output.
I/O
2.3.15
DMA Serial Peripheral Interface (DSPI) Signals
Table 2-17. DMA Serial Peripheral Interface (DSPI) Signals
Signal Name
Synchronous Serial
Output
Abbreviation
DSPI_SOUT
Function
Provides the serial data from the DSPI, which may be driven on the
rising or falling edge of DSPI_SCK. Each byte is sent msb first.
I/O
O
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Freescale Semiconductor
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Signal Descriptions
Table 2-17. DMA Serial Peripheral Interface (DSPI) Signals (continued)
Signal Name
Abbreviation
Function
I/O
Synchronous Serial Data DSPI_SIN
Input
Provides the serial data to the DSPI, which may be sampled on the
rising or falling edge of DSPI_SCK. Each byte is written to RAM lsb
first.
Serial Clock
DSPI_SCK
Provides the serial clock from the DSPI. In master mode, the
processor generates DSPI_SCK; in slave mode, DSPI_SCK is an
input from an external bus master.
Peripheral Chip Selects
DSPI_PCS[4,2] Provide DSPI peripheral chip selects, which may be active high or low.
O
In master mode, DSPI_PCS0 is a peripheral chip select output that
selects which slave device the current transmission is intended.
In slave mode, the SS signal is a slave select input that an SPI master
uses to select the processor as the target for transmission.
I/O
Peripheral Chip Select 0/ DSPI_PCS0/
Slave Select
DSPI_SS
2.3.16
I
I/O
UART Module Signals
Table 2-18 describes the signals of the three UART modules, where n equals 0–2. Baud-rate clock inputs
are not supported.
Table 2-18. UART Module Signals
Signal Name
Abbreviation
Function
I/O
Transmit Serial Data
Output
UnTXD
Data is shifted out lsb first at the falling edge of the serial clock source.
Output is held high when transmitter is disabled, idle, or in local
loopback mode.
O
Receive Serial Data
Input
UnRXD
Data is sampled Isb first at the serial clock source’s rising edge. When
the UART clock is stopped for power-down mode, any transition on this
pin restarts it.
I
Request-to-Send
UnRTS
Automatic request-to-send outputs from UART modules. They may
also be asserted and negated as a function of the received FIFO level.
O
Clear-to-Send
UnCTS
Indicates UART modules can begin data transmission
I
2.3.17
Synchronous Serial Interface (SSI) Signals
Table 2-19. SSI Module Signals
Signal Name
Abbreviation
Function
I/O
Serial Bit Clock
SSI_BCLK
Used by the receive and transmit blocks. In gated clock mode,
SSI_BCLK is only valid during transmission of data; otherwise it is
pulled to an inactive state.
I/O
Serial Master Clock
SSI_MCLK
This clock signal is output from the device when it is the master. When
in I2S master mode, this signal is referred to as the oversampling
clock. The frequency of SSI_MCLK is a multiple of the frame clock.
O
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Signal Descriptions
Table 2-19. SSI Module Signals (continued)
Signal Name
Abbreviation
Function
I/O
I/O
Serial Frame Sync
SSI_FS
Used by transmitter/receiver to synchronize the transfer of data. In
gated clock mode, this signal is not used. When configured as an
input, the external device should drive SSI_FS during the rising edge
of SSI_BCLK.
Serial Receive Data
SSI_RXD
Receives data into the receive data shift register
I
Serial Transmit Data
SSI_TXD
Transmits data from the serial transmit shift register.
O
2.3.18
DMA Timer Signals
Table 2-20 describes the signals of the four DMA timer modules, where n equals 0–3.
Table 2-20. DMA Timer Signals
Signal Name
Abbreviation
Function
I/O
DMA Timer n Input
DTnIN
Can be programmed to cause events in the respective timer. It can
clock the event counter or provide a trigger to the timer value capture
logic.
I
DMA Timer n Output
DTnOUT
Output from respective timer.
O
2.3.19
Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and the BDM logic. Pin functionality
between JTAG and BDM is dependent upon the JTAG_EN pin.
Table 2-21. Debug Support Signals
Signal Name
JTAG Enable
Abbreviation
JTAG_EN
Function
Enables JTAG (asserted) or BDM (negated) operation.
I/O
I
JTAG Signals
Test Reset
TRST
Active-low signal used to initialize the JTAG logic asynchronously.
I
Test Clock
TCLK
Used to synchronize the JTAG logic.
I
Test Mode Select
TMS
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
I
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is three-stateable and
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
BDM Signals
Development Serial
Clock
DSCLK
Clocks the serial communication port to the BDM module during
packet transfers.
I
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Freescale Semiconductor
2-13
Signal Descriptions
Table 2-21. Debug Support Signals (continued)
Signal Name
Abbreviation
Function
I/O
Breakpoint
BKPT
Used to request a manual breakpoint.
I
Development Serial
Input
DSI
Internally-synchronized signal provides data input for the serial
communication port to the BDM module.
I
Development Serial
Output
DSO
Internally-registered signal provides serial output communication for
BDM module responses.
O
Processor Status Clock PSTCLK
Used by the development system to know when to sample DDATA and
PST signals.
O
Debug Data
DDATA[3:0]
Display captured processor data and breakpoint status. The PSTCLK
signal can be used by the development system to know when to
sample DDATA[3:0].
Only present on the BGA device (MCF52277).
O
Processor Status
Outputs
PST[3:0]
Indicate core status, as shown in Table 2-22. Debug mode timing is
synchronous with the processor clock; status is unrelated to the
current bus transfer. The PSTCLK signal can be used by the
development system to know when to sample PST[3:0].
Only present on the BGA device (MCF52277).
O
All Processor Status
Outputs
ALLPST
ALLPST is a logical AND of the four PST signals and is present in
place of PST[3:0] and DDATA[3:0] on the LQFP device (MCF52274).
When asserted, reflects that the core is halted.
O
Table 2-22. Processor Status
PST[3:0]
(MCF52274)
ALLPST
(MCF52277)
0000
0
Continue execution
0001
0
Begin execution of one instruction
0010
0
Reserved
0011
0
Entry into user mode
0100
0
Begin execution of PULSE and WDDATA instructions
0101
0
Begin execution of taken branch
0110
0
Reserved
0111
0
Begin execution of RTE instruction
1000
0
Begin one-byte transfer on DDATA
1001
0
Begin two-byte transfer on DDATA
1010
0
Begin three-byte transfer on DDATA
1011
0
Begin four-byte transfer on DDATA
1100
0
Exception processing
1101
0
Reserved
Processor Status
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Signal Descriptions
Table 2-22. Processor Status (continued)
2.3.20
PST[3:0]
(MCF52274)
ALLPST
(MCF52277)
1110
0
Processor is stopped
1111
1
Processor is halted
Processor Status
Test Signals
Table 2-23 describes test signals reserved for factory testing.
Table 2-23. Test Signals
Signal Name
Test
Abbreviation
TEST
2.3.21
Function
I/O
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of test
functions.
I
Power and Ground Pins
The pins described in Table 2-24 provide system power and ground to the device. Multiple pins are
provided for adequate current capability. All power supply pins must have adequate bypass capacitance
for high-frequency noise suppression.
Table 2-24. Power and Ground Pins
Signal Name
Abbreviation
Function
I/O
PLL Analog Supply
VDD_A_PLL
Dedicated power supply signal to isolate the sensitive PLL analog
(VCO) circuitry from the normal levels of noise present on the digital
power supply.
—
Oscillator
VDD_OSC
VSS_OSC
Dedicated power supply signals to isolate the sensitive oscillator
circuitry from the normal levels of noise present on the digital power
supply.
—
Positive I/O Supply
EVDD
These pins supply positive power to the I/O pads.
—
Positive Core Supply
IVDD
These pins supply positive power to the core logic.
—
SDRAMC Supply
SD_VDD
These pins supply positive power to the SDRAM controller.
—
USB Supply
VDD_USB
These pins supply positive power to the USB controller.
—
Real-time clock Supply VDD_RTC
These pins supply positive power to the RTC module.
—
Touchscreen supply
VDD_ADC
VSS_ADC
Dedicated power supply for the touchscreen controller.
—
Ground
VSS
These pins are the negative supply (ground) for the device.
—
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Signal Descriptions
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Chapter 3
ColdFire Core
3.1
Introduction
This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview
of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the
ColdFire Family Programmer’s Reference Manual.
3.1.1
Overview
As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an
instruction buffer.
IAG
Instruction
Address
Generation
IC
Instruction
Fetch Cycle
IB
FIFO
Instruction Buffer
Instruction
Fetch
Pipeline
Address [ 31 :0]
Read Data[31:0]
Operand
Execution
Pipeline
& Select,
DSOC Decode
Operand Fetch
Write Data[31:0]
AGEX
Address
Generation,
Execute
Figure 3-1. V2 ColdFire Core Pipelines
The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the
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3-1
ColdFire Core
instruction, fetches the required operands and then executes the required function. Because the IFP and
OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch
instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.
The V2 ColdFire core pipeline stages include the following:
• Two-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage)
— Instruction address generation (IAG) — Calculates the next prefetch address
— Instruction fetch cycle (IC)—Initiates prefetch on the processor’s local bus
— Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO
queue
• Two-stage operand execution pipeline (OEP)
— Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the
required components for effective address calculation, or the operand fetch cycle
— Address generation/execute cycle (AGEX)—Calculates operand address or executes the
instruction
When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the operand
execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction in the
IB until it is required by the OEP.
For register-to-register and register-to-memory store operations, the instruction passes through both OEP
stages once. For memory-to-register and read-modify-write memory operations, an instruction is
effectively staged through the OEP twice: the first time to calculate the effective address and initiate the
operand fetch on the processor’s local bus, and the second time to complete the operand reference and
perform the required function defined by the instruction.
The resulting pipeline and local bus structure allow the V2 ColdFire core to deliver sustained high
performance across a variety of demanding embedded applications.
3.2
Memory Map/Register Description
The following sections describe the processor registers in the user and supervisor programming models.
The programming model is selected based on the processor privilege level (user mode or supervisor mode)
as defined by the S bit of the status register (SR). Table 3-1 lists the processor registers.
The user-programming model consists of the following registers:
• 16 general-purpose 32-bit registers (D0–D7, A0–A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
• EMAC registers (described fully in Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC:
— Four 48-bit accumulator registers partitioned as follows:
– Four 32-bit accumulators (ACC0–ACC3)
– Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two
32-bit values for load and store operations (ACCEXT01 and ACCEXT23).
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ColdFire Core
Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC
arithmetic operations generally affect the entire 48-bit destination.
— One 16-bit mask register (MASK)
— One 32-bit Status register (MACSR) including four indicator bits signaling product or
accumulation overflow (one for each accumulator: PAV0–PAV3)
The supervisor programming model is to be used only by system control software to implement restricted
operating system functions, I/O control, and memory management. All accesses that affect the control
features of ColdFire processors are in the supervisor programming model, which consists of registers
available in user mode as well as the following control registers:
• 16-bit status register (SR)
• 32-bit supervisor stack pointer (SSP)
• 32-bit vector base register (VBR)
• 32-bit cache control register (CACR)
• 32-bit access control registers (ACR0, ACR1)
•
One 32-bit memory base address register (RAMBAR)
Table 3-1. ColdFire Core Programming Model
BDM1
Width
Access
(bits)
Register
Reset Value
Written with
Section/Page
MOVEC
Supervisor/User Access Registers
Load: 0x080
Store: 0x180
Data Register 0 (D0)
32
R/W
0xCF20_60
No
3.2.1/3-4
Load: 0x081
Store: 0x181
Data Register 1 (D1)
32
R/W
0x1500_1090
No
3.2.1/3-4
Data Register 2–7 (D2–D7)
32
R/W
Undefined
No
3.2.1/3-4
32
R/W
Undefined
No
3.2.2/3-4
Supervisor/User A7 Stack Pointer (A7)
32
R/W
Undefined
No
3.2.3/3-5
0x804
MAC Status Register (MACSR)
32
R/W
0x0000_0000
No
4.2.1/4-3
0x805
MAC Address Mask Register (MASK)
32
R/W
0xFFFF_FFFF
No
4.2.2/4-5
MAC Accumulators 0–3 (ACC0–3)
32
R/W
Undefined
No
4.2.3/4-6
0x807
MAC Accumulator 0,1 Extension Bytes
(ACCext01)
32
R/W
Undefined
No
4.2.4/4-7
0x808
MAC Accumulator 2,3 Extension Bytes
(ACCext23)
32
R/W
Undefined
No
4.2.4/4-7
0x80E
Condition Code Register (CCR)
8
R/W
Undefined
No
3.2.4/3-6
Load: 0x082–7
Store: 0x182–7
Load: 0x088–8E Address Register 0–6 (A0–A6)
Store: 0x188–8E
Load: 0x08F
Store: 0x18F
0x806, 0x809,
0x80A, 0x80B
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ColdFire Core
Table 3-1. ColdFire Core Programming Model (continued)
BDM1
Width
Access
(bits)
Register
0x80F
Program Counter (PC)
32
R/W
Written with
Section/Page
MOVEC
Reset Value
Contents of
location
0x0000_0004
No
3.2.5/3-7
Supervisor Access Only Registers
0x002
Cache Control Register (CACR)
32
R/W
0x0000_0000
Yes
3.2.6/3-7
Access Control Register 0–1 (ACR0–1)
32
R/W
See Section
Yes
3.2.7/3-7
0x800
User/Supervisor A7 Stack Pointer
(OTHER_A7)
32
R/W
Contents of
location
0x0000_0000
No
3.2.3/3-5
0x801
Vector Base Register (VBR)
32
R/W
0x0000_0000
Yes
3.2.8/3-7
0x80E
Status Register (SR)
16
R/W
0x27--
No
3.2.9/3-8
0xC05
RAM Base Address Register (RAMBAR)
32
R/W
See Section
Yes
3.2.10/3-8
0x004–5
1
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see Chapter 32, “Debug Module”.
3.2.1
Data Registers (D0–D7)
D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they
can also be used as index registers.
NOTE
Registers D0 and D1 contain hardware configuration details after reset. See
Section 3.3.4.15, “Reset Exception” for more details.
BDM: Load: 0x080 + n; n = 0-7 (Dn)
Store: 0x180 + n; n = 0-7 (Dn)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
Data
W
Reset
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
(D2-D7)
Reset
(D0, D1)
See Section 3.3.4.15, “Reset Exception”
Figure 3-2. Data Registers (D0–D7)
3.2.2
Address Registers (A0–A6)
These registers can be used as software stack pointers, index registers, or base address registers. They can
also be used for word and longword operations.
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ColdFire Core
BDM: Load: 0x088 + n; n = 0–6 (An)
Store: 0x188 + n; n = 0–6 (An)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
Address
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 3-3. Address Registers (A0–A6)
3.2.3
Supervisor/User Stack Pointers (A7 and OTHER_A7)
This ColdFire architecture supports two independent stack pointer (A7) registers—the supervisor stack
pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two
program-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead, the
hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents
are a function of the processor operation mode, as shown in the following:
if SR[S] = 1
then
else
A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer
A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the
responsibility of the external development system to determine, based on the setting of SR[S], the mapping
of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP). This functionality is
enabled by setting the enable user stack pointer bit, CACR[EUSP]. If this bit is cleared, only a single stack
pointer (A7), defined for ColdFire ISA_A, is available. EUSP is cleared at reset.
To support dual stack pointers, the following two supervisor instructions are included in the ColdFire
instruction set architecture to load/store the USP:
move.l Ay,USP;move to USP
move.l USP,Ax;move from USP
These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other
instruction references to the stack pointer, explicit or implicit, access the active A7 register.
NOTE
The SSP is loaded during reset exception processing with the contents of
location 0x0000_0000.
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3-5
ColdFire Core
BDM: Load: 0x08F (A7)
Store: 0x18F (A7)
0x800 (OTHER_A7)
Access: A7: User or BDM read/write
OTHER_A7: Supervisor or BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
Address
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 3-4. Stack Pointer Registers (A7 and OTHER_A7)
3.2.4
Condition Code Register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. The extend bit (X) is also an input operand during multiprecision
arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare
(CMP), Bcc, or Scc instructions are executed.
BDM: LSB of Status Register (SR)
R
Access: User read/write
BDM read/write
7
6
5
0
0
0
4
3
2
1
0
X
N
Z
V
C
—
—
—
—
—
W
Reset:
0
0
0
Figure 3-5. Condition Code Register (CCR)
Table 3-2. CCR Field Descriptions
Field
7–5
Description
Reserved, must be cleared.
4
X
Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified
result.
3
N
Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.
2
Z
Zero condition code bit. Set if result equals zero; otherwise cleared.
1
V
Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand
size; otherwise cleared.
0
C
Carry condition code bit. Set if a carry out of the operand msb occurs for an addition or if a borrow occurs in a
subtraction; otherwise cleared.
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ColdFire Core
3.2.5
Program Counter (PC)
The PC contains the currently executing instruction address. During instruction execution and exception
processing, the processor automatically increments contents of the PC or places a new value in the PC, as
appropriate. The PC is a base address for PC-relative operand addressing.
The PC is initially loaded during reset exception processing with the contents of location 0x0000_0004.
BDM: 0x80F (PC)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
Address
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 3-6. Program Counter Register (PC)
3.2.6
Cache Control Register (CACR)
The CACR controls operation of the instruction/data cache memories. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode and
write-protect fields. The CACR is described in Section 5.2.1, “Cache Control Register (CACR).”
3.2.7
Access Control Registers (ACRn)
The access control registers define attributes for user-defined memory regions. These attributes include the
definition of cache mode, write protect, and buffer write enables. The ACRs are described in Section 5.2.2,
“Access Control Registers (ACR0, ACR1).”
3.2.8
Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in memory. To access the vector table,
the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are
not implemented by ColdFire processors. They are assumed to be zero, forcing the table to be aligned on
a 1 MB boundary.
BDM: 0x801 (VBR)
Access: Supervisor read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Base Address
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 3-7. Vector Base Register (VBR)
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Freescale Semiconductor
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ColdFire Core
3.2.9
Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are
accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor
or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access
when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and
before any compare (CMP), Bcc, or Scc instructions execute.
BDM: 0x80E (SR)
Access: Supervisor read/write
BDM read/write
System Byte
15
R
W
Reset
T
0
14
0
0
13
12
S
M
1
0
11
Condition Code Register (CCR)
10
0
0
9
8
I
1
1
1
7
6
5
0
0
0
0
0
0
4
3
2
1
0
X
N
Z
V
C
—
—
—
—
—
Figure 3-8. Status Register (SR)
Table 3-3. SR Field Descriptions
Field
Description
15
T
Trace enable. When set, the processor performs a trace exception after every instruction.
14
Reserved, must be cleared.
13
S
Supervisor/user state.
0 User mode
1 Supervisor mode
12
M
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
11
Reserved, must be cleared.
10–8
I
Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
7–0
CCR
Refer to Section 3.2.4, “Condition Code Register (CCR)”.
3.2.10
Memory Base Address Register (RAMBAR)
The memory base address register is used to specify the base address of the internal SRAM module and
indicates the types of references mapped to it. The base address register includes a base address,
write-protect bit, address space mask bits, and an enable bit. RAMBAR determines the base address of
the on-chip RAM. For more information, refer to Section 6.2.1, “SRAM Base Address Register
(RAMBAR)”.
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3.3
3.3.1
Functional Description
Version 2 ColdFire Microarchitecture
From the block diagram in Figure 3-1, the non-Harvard architecture of the processor is readily apparent.
The processor interfaces to the local memory subsystem via a single 32-bit address and two unidirectional
32-bit data buses. This structure minimizes the core size without compromising performance to a large
degree.
A more detailed view of the hardware structure within the two pipelines is presented in Figure 3-9 and
Figure 3-10 below. In these diagrams, the internal structure of the instruction fetch and operand execution
pipelines is shown:
IAG
+4
IC
IB
Opword
Core Bus
Address
Extension 1
Core Bus
Read Data
FIFO
IB
Extension 2
Figure 3-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram
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DSOC
AGEX
RGF
Core Bus
Address
Opword
Extension 1
Core Bus
Write Data
Extension 2
Core Bus
Read Data
Figure 3-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram
The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For
sequential prefetches, the next instruction address is generated by adding four to the last prefetch address.
This function is performed during the IAG stage and the resulting prefetch address gated onto the core bus
(if there are no pending operand memory accesses assigned a higher priority). After the prefetch address
is driven onto the core bus, the instruction fetch cycle accesses the appropriate local memory and returns
the instruction read data back to the IFP during the cycle. If the accessed data is not present in a local
memory (e.g., an instruction cache miss, or an external access cycle is required), the IFP is stalled in the
IC stage until the referenced data is available. As the prefetch data arrives in the IFP, it can be loaded into
the FIFO instruction buffer or gated directly into the OEP.
The V2 design uses a simple static conditional branch prediction algorithm (forward-assumed as
not-taken, backward-assumed as taken), and all change-of-flow operations are calculated by the OEP and
the target instruction address fed back to the IFP.
The IFP and OEP are decoupled by the FIFO instruction buffer, allowing instruction prefetching to occur
with the available core bus bandwidth not used for operand memory accesses. For the V2 design, the
instruction buffer contains three 32-bit locations.
Consider the operation of the OEP for three basic classes of non-branch instructions:
• Register-to-register:
op
•
Embedded load:
op
•
Ry,Rx
<mem>y,Rx
Register-to-memory (store)
move
Ry,<mem>x
For simple register-to-register instructions, the first stage of the OEP performs the instruction decode and
fetching of the required register operands (OC) from the dual-ported register file, while the actual
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instruction execution is performed in the second stage (EX) in one of the execute engines (e.g., ALU,
barrel shifter, divider, EMAC). There are no operand memory accesses associated with this class of
instructions, and the execution time is typically a single machine cycle. See Figure 3-11.
Operand Execution Pipeline
DSOC
RGF
AGEX
Rx
new Rx
Ry
Core Bus
Address
Opword
Extension 1
Core Bus
Write
Data
Extension 2
Core Bus
Read Data
Figure 3-11. V2 OEP Register-to-Register
For memory-to-register (embedded-load) instructions, the instruction is effectively staged through the
OEP twice with a basic execution time of three cycles. First, the instruction is decoded and the components
of the operand address (base register from the RGF and displacement) are selected (DS). Second, the
operand effective address is generated using the ALU execute engine (AG). Third, the memory read
operand is fetched from the core bus, while any required register operand is simultaneously fetched (OC)
from the RGF. Finally, in the fourth cycle, the instruction is executed (EX). The heavily-used 32-bit load
instruction (move.l <mem>y,Rx) is optimized to support a two-cycle execution time. The following example
in Figure 3-12 shows an effective address of the form <ea>y = (d16,Ay), i.e., a 16-bit signed displacement
added to a base register Ay.
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Operand Execution Pipeline
DSOC
AGEX
RGF
<ea>y
Ay
Opword
Core Bus
Address
d16
Extension 1
Core Bus
Write
Data
Extension 2
Core Bus
Read Data
Figure 3-12. V2 OEP Embedded-Load Part 1
Operand Execution Pipeline
DSOC
AGEX
Rx
RGF
new Rx
Core Bus
Address
Opword
Extension 1
Core Bus
Write
Data
Extension 2
Core Bus
Read Data
<mem>y
Figure 3-13. V2 OEP Embedded-Load Part 2
For register-to-memory (store) operations, the stage functions (DS/OC, AG/EX) are effectively performed
simultaneously allowing single-cycle execution. See Figure 3-14 where the effective address is of the form
<ea>x = (d16,Ax), i.e., a 16-bit signed displacement added to a base register Ax.
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For read-modify-write instructions, the pipeline effectively combines an embedded-load with a store
operation for a three-cycle execution time.
Operand Execution Pipeline
DSOC
AGEX
Ax
RGF
<ea>x
Ry
Opword
Extension 1
Core Bus
Address
d16
Core Bus
Write
Data
Extension 2
Core Bus
Read Data
Figure 3-14. V2 OEP Register-to-Memory
The pipeline timing diagrams of Figure 3-15 depict the execution templates for these three classes of
instructions. In these diagrams, the x-axis represents time, and the various instruction operations are shown
progressing down the operand execution pipeline.
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Core clock
Register-to-Register
OEP.DSOC
OC
OEP.AGEX
next
EX
Core Bus
Embedded-Load
OEP.DSOC
DS
OEP.AGEX
OC
AG
Core Bus
next
EX
op read
Register-to-Memory
(Store)
OEP.DSOC
OEP.AGEX
DSOC
next
AGEX
op write
Core Bus
Figure 3-15. V2 OEP Pipeline Execution Templates
3.3.2
Instruction Set Architecture (ISA_A+)
The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes
based on extensive analysis of embedded application code. The ISA was optimized for code compiled
from high-level languages where the dominant operand size was the 32-bit integer declaration. This
approach minimized processor complexity and cost, while providing excellent performance for compiled
applications.
After the initial ColdFire compilers were created, developers noted there were certain ISA additions that
would enhance code density and overall performance. Additionally, as users implemented ColdFire-based
designs into a wide range of embedded systems, they found certain frequently-used instruction sequences
that could be improved by the creation of additional instructions.
The original ISA definition minimized support for instructions referencing byte- and word-sized operands.
Full support for the move byte and move word instructions was provided, but the only other opcodes
supporting these data types are CLR (clear) and TST (test). A set of instruction enhancements has been
implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three
areas:
1. Enhanced support for byte and word-sized operands
2. Enhanced support for position-independent code
3. Miscellaneous instruction additions to address new functionality
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Table 3-4 summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details
see the ColdFire Family Programmer’s Reference Manual.
Table 3-4. Instruction Enhancements over Revision ISA_A
Instruction
Description
BITREV
The contents of the destination data register are bit-reversed; new Dn[31] equals old Dn[0], new
Dn[30] equals old Dn[1],..., new Dn[0] equals old Dn[31].
BYTEREV
FF1
The contents of the destination data register are byte-reversed; new Dn[31:24] equals old
Dn[7:0],..., new Dn[7:0] equals old Dn[31:24].
The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending
with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.
Move from USP USP → Destination register
Move to USP
STLDSR
3.3.3
Source register → USP
Pushes the contents of the status register onto the stack and then reloads the status register
with the immediate data value.
Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
differ from the M68000 family because they include:
• A simplified exception vector table
• Reduced relocation capabilities using the vector-base register
• A single exception stack frame format
• Use of separate system stack pointers for user and supervisor modes.
All ColdFire processors use an instruction restart exception model. However, Version 2 ColdFire
processors require more software support to recover from certain access errors. See Section 3.3.4.1,
“Access Error Exception” for details.
Exception processing includes all actions from fault condition detection to the initiation of fetch for first
handler instruction. Exception processing is comprised of four major steps:
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
bit and disabling trace mode by clearing the T bit. The interrupt exception also forces the M bit to
be cleared and the interrupt priority mask to set to current interrupt request level.
2. The processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller. The IACK cycle is mapped to special locations within the interrupt
controller’s address space with the interrupt level encoded in the address.
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3. The processor saves the current context by creating an exception stack frame on the system stack.
The exception stack frame is created at a 0-modulo-4 address on top of the system stack pointed to
by the supervisor stack pointer (SSP). As shown in Figure 3-16, the processor uses a simplified
fixed-length stack frame for all exceptions. The exception type determines whether the program
counter placed in the exception stack frame defines the location of the faulting instruction (fault)
or the address of the next instruction to be executed (next).
4. The processor calculates the address of the first instruction of the exception handler. By definition,
the exception vector table is aligned on a 1 MB boundary. This instruction address is generated by
fetching an exception vector from the table located at the address defined in the vector base register.
The index into the exception table is calculated as (4 × vector number). After the exception vector
has been fetched, the vector contents determine the address of the first instruction of the desired
handler. After the instruction fetch for the first opcode of the handler has initiated, exception
processing terminates and normal instruction processing continues in the handler.
All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see
Table 3-5).
The table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are
device-specific peripheral interrupt vectors. See Chapter 15, “Interrupt Controller Modules” for details on
the device-specific interrupt sources.
Table 3-5. Exception Vector Assignments
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
0
0x000
—
Initial supervisor stack pointer
1
0x004
—
Initial program counter
2
0x008
Fault
Access error
3
0x00C
Fault
Address error
4
0x010
Fault
Illegal instruction
5
0x014
Fault
Divide by zero
6–7
0x018–0x01C
—
Reserved
8
0x020
Fault
Privilege violation
9
0x024
Next
Trace
10
0x028
Fault
Unimplemented line-A opcode
11
0x02C
Fault
Unimplemented line-F opcode
12
0x030
Next
Debug interrupt
13
0x034
—
Reserved
14
0x038
Fault
Format error
15–23
0x03C–0x05C
—
Reserved
24
0x060
Next
Spurious interrupt
25–31
0x064–0x07C
—
Reserved
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Table 3-5. Exception Vector Assignments (continued)
1
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
32–47
0x080–0x0BC
Next
Trap # 0-15 instructions
48–63
0x0C0–0x0FC
—
Reserved
64–255
0x100–0x3FC
Next
Device-specific interrupts
Fault refers to the PC of the instruction that caused the exception. Next refers to the PC
of the instruction that follows the instruction that caused the fault.
All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
This allows any handler to disable interrupts effectively, if necessary, by raising the interrupt mask level
contained in the status register. In addition, the ISA_A+ architecture includes an instruction (STLDSR)
that stores the current interrupt mask level and loads a value into the SR. This instruction is specifically
intended for use as the first instruction of an interrupt service routine that services multiple interrupt
requests with different interrupt levels. For more details, see ColdFire Family Programmer’s Reference
Manual.
3.3.3.1
Exception Stack Frame Definition
Figure 3-16 shows exception stack frame. The first longword contains the 16-bit format/vector word (F/V)
and the 16-bit status register, and the second longword contains the 32-bit program counter address.
SSP →
31 30 29 28 27
Format
26 25 24 23 22 21 20 19 18 17
FS[3:2]
Vector
+ 0x4
16 15 14 13 12 11 10 9
FS[1:0]
8
7
6
5
4
3
2
1
0
Status Register
Program Counter
Figure 3-16. Exception Stack Frame Form
The 16-bit format/vector word contains three unique fields:
• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by
the processor, indicating a two-longword frame format. See Table 3-6.
Table 3-6. Format Field Encodings
•
Original SSP @ Time
of Exception, Bits 1:0
SSP @ 1st
Instruction of
Handler
Format Field
00
Original SSP - 8
0100
01
Original SSP - 9
0101
10
Original SSP - 10
0110
11
Original SSP - 11
0111
There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for
access and address errors only and written as zeros for all other exceptions. See Table 3-7.
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Table 3-7. Fault Status Encodings
•
FS[3:0]
Definition
00xx
Reserved
0100
Error on instruction fetch
0101
Reserved
011x
Reserved
1000
Error on operand write
1001
Attempted write to write-protected space
101x
Reserved
1100
Error on operand read
1101
Reserved
111x
Reserved
The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor
for all internal faults and represents the value supplied by the interrupt controller in case of an
interrupt. See Table 3-5.
3.3.4
3.3.4.1
Processor Exceptions
Access Error Exception
The exact processor response to an access error depends on the memory reference being performed. For
an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an
instruction for execution. Therefore, faults during instruction prefetches followed by a change of
instruction flow do not generate an exception. When the processor attempts to execute an instruction with
a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For this
type of exception, the programming model has not been altered by the instruction generating the access
error.
If the access error occurs on an operand read, the processor immediately aborts the current instruction’s
execution and initiates exception processing. In this situation, any address register updates attributable to
the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming
model contains the updated An value. In addition, if an access error occurs during a MOVEM instruction
loading from memory, any registers already updated before the fault occurs contain the operands from
memory.
The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes.
Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the
signaling of an access error appears to be decoupled from the instruction that generated the write.
Accordingly, the PC contained in the exception stack frame merely represents the location in the program
when the access error was signaled. All programming model updates associated with the write instruction
are completed. The NOP instruction can collect access errors for writes. This instruction delays its
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execution until all previous operations, including all pending write operations, are complete. If any
previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.
3.3.4.2
Address Error Exception
Any attempted execution transferring control to an odd instruction address (if bit 0 of the target address is
set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of eight on an indexed effective
addressing mode generates an address error, as does an attempted execution of a full-format indexed
addressing mode, which is defined by bit 8 of extension word 1 being set.
If an address error occurs on a JSR instruction, the Version 2 ColdFire processor calculates the target
address then the return address is pushed onto the stack. If an address error occurs on an RTS instruction,
the Version 2 ColdFire processor overwrites the faulting return PC with the address error stack frame.
3.3.4.3
Illegal Instruction Exception
The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits.
The first instruction word is known as the operation word (or opword), while the optional words are known
as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper
four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode
(opmode), and the low-order 6 bits define the effective address. See Figure 3-17. The opword line
definition is shown in Table 3-8.
15
14
13
12
11
Line
10
9
8
7
6
5
4
OpMode
3
2
1
0
Effective Address
Mode
Register
Figure 3-17. ColdFire Instruction Operation Word (Opword) Format
Table 3-8. ColdFire Opword Line Definition
Opword[Line]
Instruction Class
0x0
Bit manipulation, Arithmetic and Logical Immediate
0x1
Move Byte
0x2
Move Long
0x3
Move Word
0x4
Miscellaneous
0x5
Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc)
0x6
PC-relative change-of-flow instructions
Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR)
0x7
Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ)
0x8
Logical OR (OR)
0x9
Subtract (SUB), Subtract Extended (SUBX)
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Table 3-8. ColdFire Opword Line Definition (continued)
Opword[Line]
Instruction Class
0xA
EMAC, Move 3-bit Quick (MOV3Q)
0xB
Compare (CMP), Exclusive-OR (EOR)
0xC
Logical AND (AND), Multiply Word (MUL)
0xD
Add (ADD), Add Extended (ADDX)
0xE
Arithmetic and logical shifts (ASL, ASR, LSL, LSR)
0xF
Cache Push (CPUSHL), Write DDATA (WDDATA), Write Debug (WDEBUG)
In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations
(line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors
associated with illegal opwords in these two lines.
Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an
illegal instruction exception (vector 4). Additionally, any attempted execution of any non-MAC line-A and
most line-F opcodes generate their unique exception types, vector numbers 10 and 11, respectively.
ColdFire cores do not provide illegal instruction detection on the extension words on any instruction,
including MOVEC.
3.3.4.4
Divide-By-Zero
Attempting to divide by zero causes an exception (vector 5, offset equal 0x014).
3.3.4.5
Privilege Violation
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. See ColdFire Programmer’s Reference Manual for a list of supervisor-mode
instructions.
There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode
instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in
user mode for debugging purposes.
3.3.4.6
Trace Exception
To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing
capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction
execution (for all but the stop instruction) signals a trace exception. This functionality allows a debugger
to monitor program execution.
The stop instruction has the following effects:
1. The instruction before the stop executes and then generates a trace exception. In the exception stack
frame, the PC points to the stop opcode.
2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate
operand from the instruction.
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3. The processor then generates a trace exception. The PC in the exception stack frame points to the
instruction after the stop, and the SR reflects the value loaded in the previous step.
If the processor is not in trace mode and executes a stop instruction where the immediate operand sets
SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points
to the instruction after the stop, and the SR reflects the value loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types. As
an example, consider a TRAP instruction execution while in trace mode. The processor initiates the trap
exception and then passes control to the corresponding handler. If the system requires that a trace exception
be processed, it is the responsibility of the trap exception handler to check for this condition (SR[T] in the
exception stack frame set) and pass control to the trace handler before returning from the original
exception.
3.3.4.7
Unimplemented Line-A Opcode
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the
attempted execution of an undefined line-A opcode.
3.3.4.8
Unimplemented Line-F Opcode
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when
attempting to execute an undefined line-F opcode.
3.3.4.9
Debug Interrupt
See Chapter 32, “Debug Module,” for a detailed explanation of this exception, which is generated in
response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle, but
rather calculates the vector number internally (vector number 12). Additionally, SR[M,I] are unaffected by
the interrupt.
3.3.4.10
RTE and Format Error Exception
When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the
frame type. For a ColdFire core, any attempted RTE execution (where the format is not equal to {4,5,6,7})
generates a format error. The exception stack frame for the format error is created without disturbing the
original RTE frame and the stacked PC pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code from M68000
applications. On M68000 family processors, the SR was located at the top of the stack. On those
processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE
is attempted using this old format, it generates a format error on a ColdFire processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second
longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address
after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the
second longword operand within the stack frame.
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3.3.4.11
TRAP Instruction Exception
The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing
system calls. The TRAP instruction may be used to change from user to supervisor mode.
3.3.4.12
Unsupported Instruction Exception
If execution of a valid instruction is attempted but the required hardware is not present in the processor, an
unsupported instruction exception is generated. The instruction functionality can then be emulated in the
exception handler, if desired.
All ColdFire cores record the processor hardware configuration in the D0 register immediately after the
negation of RESET. See Section 3.3.4.15, “Reset Exception,” for details.
3.3.4.13
Interrupt Exception
Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from
the interrupt controller using an IACK cycle. See Chapter 15, “Interrupt Controller Modules,” for details
on the interrupt controller.
3.3.4.14
Fault-on-Fault Halt
If a ColdFire processor encounters any type of fault during the exception processing of another fault, the
processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to
to exit this state.
3.3.4.15
Reset Exception
Asserting the reset input signal (RESET) to the processor causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from catastrophic
failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot
be recovered.
The reset exception places the processor in the supervisor mode by setting the SR[S] bit and disables
tracing by clearing the SR[T] bit. This exception also clears the SR[M] bit and sets the processor’s SR[I]
field to the highest level (level 7, 0b111). Next, the VBR is initialized to zero (0x0000_0000). The control
registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly
to the processor are disabled.
NOTE
Other implementation-specific registers are also affected. Refer to each
module in this reference manual for details on these registers.
After the processor is granted the bus, it performs two longword read-bus cycles. The first longword at
address 0x0000_0000 is loaded into the supervisor stack pointer and the second longword at address
0x0000_0004 is loaded into the program counter. After the initial instruction is fetched from memory,
program execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault state.
MCF52277 Reference Manual, Rev 2
3-22
Freescale Semiconductor
ColdFire Core
ColdFire processors load hardware configuration information into the D0 and D1 general-purpose
registers after system reset. The hardware configuration information is loaded immediately after the
reset-in signal is negated. This allows an emulator to read out the contents of these registers via the BDM
to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in Figure 3-18.
BDM: Load: 0x080 (D0)
Store: 0x180 (D0)
31
30
29
Access: User read-only
BDM read-only
28
R
27
26
25
24
23
22
PF
21
20
19
18
VER
17
16
REV
W
Reset
1
15
R MAC
1
14
DIV
0
0
1
1
13
12
11
10
0
0
0
0
0
0
EMAC FPU
1
1
0
0
9
8
7
6
0
0
1
0
0
0
0
0
5
4
3
2
1
0
ISA
DEBUG
W
Reset
0
1
1
0
1
0
0
0
1
0
0
1
Figure 3-18. D0 Hardware Configuration Info
Table 3-9. D0 Hardware Configuration Info Field Description
Field
Description
31–24
PF
Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.
23–20
VER
ColdFire core version number. Defines the hardware microarchitecture version of ColdFire core.
0001 V1 ColdFire core
0010 V2 ColdFire core (This is the value used for this device.)
0011 V3 ColdFire core
0100 V4 ColdFire core
0101 V5 ColdFire core
Else Reserved for future use
19–16
REV
Processor revision number. The default is 0b0000.
15
MAC
MAC present. This bit signals if the optional multiply-accumulate (MAC) execution engine is present in processor core.
0 MAC execute engine not present in core. (This is the value used for this device.)
1 MAC execute engine is present in core.
14
DIV
Divide present. This bit signals if the hardware divider (DIV) is present in the processor core.
0 Divide execute engine not present in core.
1 Divide execute engine is present in core. (This is the value used for this device.)
13
EMAC
12
FPU
EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution engine is present in
processor core.
0 EMAC execute engine not present in core.
1 EMAC execute engine is present in core. (This is the value used for this device.)
FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in processor core.
0 FPU execute engine not present in core. (This is the value used for this device.)
1 FPU execute engine is present in core.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
3-23
ColdFire Core
Table 3-9. D0 Hardware Configuration Info Field Description (continued)
Field
Description
11–8
Reserved.
7–4
ISA
ISA revision. Defines the instruction-set architecture (ISA) revision level implemented in ColdFire processor core.
0000 ISA_A
0001 ISA_B
0010 ISA_C
1000 ISA_A+ (This is the value used for this device.)
Else Reserved
3–0
Debug module revision number. Defines revision level of the debug module used in the ColdFire processor core.
DEBUG 0000 DEBUG_A
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
1001 DEBUG_B+ (This is the value used for this device.)
1011 DEBUG_D+
1111 DEBUG_D+PST Buffer
Else Reserved
Information loaded into D1 defines the local memory hardware configuration as shown in the figure below.
BDM: Load: 0x081 (D1)
Store: 0x181 (D1)
31
R
30
CLSZ
Access: User read-only
BDM read-only
29
28
27
CCAS
26
25
24
CCSZ
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
W
Reset
R
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
MBSZ
SRAMSZ
W
Reset
0
0
1
0
0
1
0
Figure 3-19. D1 Hardware Configuration Info
Table 3-10. D1 Hardware Configuration Information Field Description
Field
Description
31–30
CLSZ
Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.
29–28
CCAS
Configurable cache associativity.
00
Four-way
01
Direct mapped (This is the value used for this device)
Else Reserved for future use
MCF52277 Reference Manual, Rev 2
3-24
Freescale Semiconductor
ColdFire Core
Table 3-10. D1 Hardware Configuration Information Field Description (continued)
Field
Description
27–24
CCSZ
Configurable cache size. Indicates the amount of instruction/data cache. The cache configuration options
available are 50% instruction/50% data, 100% instruction, or 100% data, and are specified in the CACR register.
0000 No configurable cache
0001 512B configurable cache
0010 1KB configurable cache
0011 2KB configurable cache
0100 4KB configurable cache
0101 8KB configurable cache (This is the value used for this device)
0110 16KB configurable cache
0111 32KB configurable cache
Else Reserved
23–16
Reserved.
15–14
MBSZ
Bus size. Defines the width of the ColdFire master bus datapath.
00
32-bit system bus datapath (This is the value used for this device)
01
64-bit system bus datapath
Else Reserved
13–8
Reserved, resets to 0b010000
7–3
SRAMSZ
2–0
3.3.5
SRAM bank size.
00000 No SRAM
00010 512 bytes
00100 1 KB
00110 2 KB
01000 4 KB
01010 8 KB
01100 16 KB
01110 32 KB
10000 64 KB
10010 128 KB (This is the value used for this device)
Else Reserved for future use
Reserved.
Instruction Execution Timing
This section presents processor instruction execution times in terms of processor-core clock cycles. The
number of operand references for each instruction is enclosed in parentheses following the number of
processor clock cycles. Each timing entry is presented as C(R/W) where:
• C is the number of processor clock cycles, including all applicable operand fetches and writes, and
all internal core cycles required to complete the instruction execution.
• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation
performing a read-modify-write function is denoted as (1/1).
This section includes the assumptions concerning the timing values and the execution time details.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
3-25
ColdFire Core
3.3.5.1
Timing Assumptions
For the timing data presented in this section, these assumptions apply:
1. The OEP is loaded with the opword and all required extension words at the beginning of each
instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or
extension words.
2. The OEP does not experience any sequence-related pipeline stalls. The most common example of
stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE
operations (except MOVEM), certain hardware resources within the processor are marked as busy
for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store
instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is
stalled until the resource again becomes available. Thus, the maximum pipeline stall involving
consecutive STORE operations is two cycles. The MOVEM instruction uses a different set of
resources and this stall does not apply.
3. The OEP completes all memory accesses without any stall conditions caused by the memory itself.
Thus, the timing details provided in this section assume that an infinite zero-wait state memory is
attached to the processor core.
4. All operand data accesses are aligned on the same byte boundary as the operand size; for example,
16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4
addresses.
The processor core decomposes misaligned operand references into a series of aligned accesses as
shown in Table 3-11.
Table 3-11. Misaligned Operand References
3.3.5.2
address[1:0]
Size
Bus
Operations
Additional
C(R/W)
01 or 11
Word
Byte, Byte
2(1/0) if read
1(0/1) if write
01 or 11
Long
Byte, Word,
Byte
3(2/0) if read
2(0/2) if write
10
Long
Word, Word
2(1/0) if read
1(0/1) if write
MOVE Instruction Execution Times
Table 3-12 lists execution times for MOVE.{B,W} instructions; Table 3-13 lists timings for MOVE.L.
NOTE
For all tables in this section, the execution time of any instruction using the
PC-relative effective addressing modes is the same for the comparable
An-relative mode.
ET with {<ea> = (d16,PC)}
equals ET with {<ea> = (d16,An)}
ET with {<ea> = (d8,PC,Xi*SF)}
equals ET with {<ea> = (d8,An,Xi*SF)}
MCF52277 Reference Manual, Rev 2
3-26
Freescale Semiconductor
ColdFire Core
The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w
and xxx.l.
Table 3-12. MOVE Byte and Word Execution Times
Destination
Source
Rx
(Ax)
(Ax)+
-(Ax)
(d16,Ax)
(d8,Ax,Xi*SF)
xxx.wl
Dy
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
Ay
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
(Ay)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1))
3(1/1)
(Ay)+
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1))
3(1/1)
-(Ay)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1))
3(1/1)
(d16,Ay)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
—
—
(d8,Ay,Xi*SF)
4(1/0)
4(1/1)
4(1/1)
4(1/1)
—
—
—
xxx.w
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
xxx.l
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
(d16,PC)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
—
—
(d8,PC,Xi*SF)
4(1/0)
4(1/1)
4(1/1)
4(1/1))
—
—
—
#xxx
1(0/0)
3(0/1)
3(0/1)
3(0/1)
—
—
—
Table 3-13. MOVE Long Execution Times
Destination
Source
Rx
(Ax)
(Ax)+
-(Ax)
(d16,Ax)
(d8,Ax,Xi*SF)
xxx.wl
Dy
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
Ay
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
(Ay)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
(Ay)+
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
-(Ay)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
(d16,Ay)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,Ay,Xi*SF)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
xxx.w
2(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
xxx.l
2(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
(d16,PC)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,PC,Xi*SF)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
#xxx
1(0/0)
2(0/1)
2(0/1)
2(0/1)
—
—
—
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
3-27
ColdFire Core
3.3.5.3
Standard One Operand Instruction Execution Times
Table 3-14. One Operand Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn*SF)
xxx.wl
#xxx
BITREV
Dx
1(0/0)
—
—
—
—
—
—
—
BYTEREV
Dx
1(0/0)
—
—
—
—
—
—
—
CLR.B
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
CLR.W
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
CLR.L
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
EXT.W
Dx
1(0/0)
—
—
—
—
—
—
—
EXT.L
Dx
1(0/0)
—
—
—
—
—
—
—
EXTB.L
Dx
1(0/0)
—
—
—
—
—
—
—
FF1
Dx
1(0/0)
—
—
—
—
—
—
—
NEG.L
Dx
1(0/0)
—
—
—
—
—
—
—
NEGX.L
Dx
1(0/0)
—
—
—
—
—
—
—
NOT.L
Dx
1(0/0)
—
—
—
—
—
—
—
SCC
Dx
1(0/0)
—
—
—
—
—
—
—
SWAP
Dx
1(0/0)
—
—
—
—
—
—
—
TST.B
<ea>
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
TST.W
<ea>
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
TST.L
<ea>
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
1(0/0)
3.3.5.4
Standard Two Operand Instruction Execution Times
Table 3-15. Two Operand Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An) (d8,An,Xn*SF)
(d16,PC) (d8,PC,Xn*SF)
xxx.wl
#xxx
ADD.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
ADD.L
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
ADDI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
ADDQ.L
#imm,<ea>
1(0/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
ADDX.L
Dy,Dx
1(0/0)
—
—
—
—
—
—
—
AND.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
AND.L
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
ANDI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
MCF52277 Reference Manual, Rev 2
3-28
Freescale Semiconductor
ColdFire Core
Table 3-15. Two Operand Instruction Execution Times (continued)
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An) (d8,An,Xn*SF)
(d16,PC) (d8,PC,Xn*SF)
xxx.wl
#xxx
ASL.L
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
ASR.L
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
BCHG
Dy,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
5(1/1)
4(1/1)
—
BCHG
#imm,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
—
—
—
BCLR
Dy,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
5(1/1)
4(1/1)
—
BCLR
#imm,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
—
—
—
BSET
Dy,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
5(1/1)
4(1/1)
—
BSET
#imm,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
—
—
—
BTST
Dy,<ea>
2(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
—
BTST
#imm,<ea>
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
—
—
—
CMP.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
CMPI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
DIVS.W
<ea>,Dx
20(0/0)
23(1/0)
23(1/0)
23(1/0)
23(1/0)
24(1/0)
23(1/0)
20(0/0)
DIVU.W
<ea>,Dx
20(0/0)
23(1/0)
23(1/0)
23(1/0)
23(1/0)
24(1/0)
23(1/0)
20(0/0)
DIVS.L
<ea>,Dx
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
—
—
—
DIVU.L
<ea>,Dx
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
—
—
—
EOR.L
Dy,<ea>
1(0/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
EORI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
LEA
<ea>,Ax
—
1(0/0)
—
—
1(0/0)
2(0/0)
1(0/0)
—
LSL.L
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
LSR.L
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
MOVEQ.L
#imm,Dx
—
—
—
—
—
—
—
1(0/0)
OR.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
OR.L
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
ORI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
REMS.L
<ea>,Dx
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
—
—
—
REMU.L
<ea>,Dx
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
—
—
—
SUB.L
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
SUB.L
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
SUBI.L
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
SUBQ.L
#imm,<ea>
1(0/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
SUBX.L
Dy,Dx
1(0/0)
—
—
—
—
—
—
—
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
3-29
ColdFire Core
3.3.5.5
Miscellaneous Instruction Execution Times
Table 3-16. Miscellaneous Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn*SF)
xxx.wl
#xxx
CPUSHL
(Ax)
—
11(0/1)
—
—
—
—
—
—
LINK.W
Ay,#imm
2(0/1)
—
—
—
—
—
—
—
MOVE.L
Ay,USP
3(0/0)
—
—
—
—
—
—
—
MOVE.L
USP,Ax
3(0/0)
—
—
—
—
—
—
—
MOVE.W
CCR,Dx
1(0/0)
—
—
—
—
—
—
—
MOVE.W
<ea>,CCR
1(0/0)
—
—
—
—
—
—
1(0/0)
MOVE.W
SR,Dx
1(0/0)
—
—
—
—
—
—
—
MOVE.W
<ea>,SR
7(0/0)
—
—
—
—
—
—
7(0/0) 2
MOVEC
Ry,Rc
9(0/1)
—
—
—
—
—
—
—
MOVEM.L
<ea>,and
list
—
1+n(n/0)
—
—
1+n(n/0)
—
—
—
MOVEM.L
and
list,<ea>
—
1+n(0/n)
—
—
1+n(0/n)
—
—
—
3(0/0)
—
—
—
—
—
—
—
2(0/1)
—
NOP
PEA
<ea>
PULSE
2(0/1)
4
5
—
2(0/1)
—
—
1(0/0)
—
—
—
—
—
—
—
3(0/1)
STLDSR
#imm
—
—
—
—
—
—
—
5(0/1)
STOP
#imm
—
—
—
—
—
—
—
3(0/0) 3
TRAP
#imm
—
—
—
—
—
—
—
15(1/2)
TPF
1(0/0)
—
—
—
—
—
—
—
TPF.W
1(0/0)
—
—
—
—
—
—
—
TPF.L
1(0/0)
—
—
—
—
—
—
—
UNLK
Ax
2(1/0)
—
—
—
—
—
—
—
WDDATA
<ea>
—
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
—
WDEBUG
<ea>
—
5(2/0)
—
—
5(2/0)
—
—
—
1The
n is the number of registers moved by the MOVEM opcode.
a MOVE.W #imm,SR instruction is executed and imm[13] equals 1, the execution time is 1(0/0).
3The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
4PEA execution times are the same for (d16,PC).
5
PEA execution times are the same for (d8,PC,Xn*SF).
2If
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
ColdFire Core
3.3.5.6
EMAC Instruction Execution Times
Table 3-17. EMAC Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,
xxx.wl
Xn*SF)
#xxx
MAC.L
Ry, Rx, Raccx
1(0/0)
—
—
—
—
—
—
—
MAC.L
Ry, Rx, <ea>, Rw, Raccx
—
(1/0)
(1/0)
(1/0)
(1/0)1
—
—
—
MAC.W
Ry, Rx, Raccx
1(0/0)
—
—
—
—
—
—
—
MAC.W
Ry, Rx, <ea>, Rw, Raccx
—
(1/0)
(1/0)
(1/0)
(1/0)1
—
—
—
MOVE.L
<ea>y, Raccx
1(0/0)
—
—
—
—
—
—
1(0/0)
MOVE.L
Raccy,Raccx
1(0/0)
—
—
—
—
—
—
—
MOVE.L
<ea>y, MACSR
5(0/0)
—
—
—
—
—
—
5(0/0)
MOVE.L
<ea>y, Rmask
4(0/0)
—
—
—
—
—
—
4(0/0)
MOVE.L
<ea>y,Raccext01
1(0/0)
—
—
—
—
—
—
1(0/0)
MOVE.L
<ea>y,Raccext23
1(0/0)
—
—
—
—
—
—
1(0/0)
MOVE.L
Raccx,<ea>x
1(0/0)2
—
—
—
—
—
—
—
MOVE.L
MACSR,<ea>x
1(0/0)
—
—
—
—
—
—
—
MOVE.L
Rmask, <ea>x
1(0/0)
—
—
—
—
—
—
—
MOVE.L
Raccext01,<ea.x
1(0/0)
—
—
—
—
—
—
—
MOVE.L
Raccext23,<ea>x
1(0/0)
—
—
—
—
—
—
—
MSAC.L
Ry, Rx, Raccx
1(0/0)
—
—
—
—
—
—
—
MSAC.W
Ry, Rx, Raccx
1(0/0)
—
—
—
—
—
—
—
MSAC.L Ry, Rx, <ea>, Rw, Raccx
—
(1/0)
(1/0)
(1/0)
(1/0)1
—
—
—
MSAC.W Ry, Rx, <ea>, Rw, Raccx
—
(1/0)
(1/0)
(1/0)
(1/0)1
—
—
—
MULS.L
<ea>y, Dx
4(0/0)
(1/0)
(1/0)
(1/0)
(1/0)
—
—
—
MULS.W
<ea>y, Dx
4(0/0)
(1/0)
(1/0)
(1/0)
(1/0)
(1/0)
(1/0)
4(0/0)
MULU.L
<ea>y, Dx
4(0/0)
(1/0)
(1/0)
(1/0)
(1/0)
—
—
—
MULU.W
<ea>y, Dx
4(0/0)
(1/0)
(1/0)
(1/0)
(1/0)
(1/0)
(1/0)
4(0/0)
1
2
Effective address of (d16,PC) not supported
Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional
rounding is performed (MACSR[7:4] equals 1---, -11-, --11)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
3-31
ColdFire Core
NOTE
The execution times for moving the contents of the Racc, Raccext[01,23],
MACSR, or Rmask into a destination location <ea>x shown in this table
represent the best-case scenario when the store instruction is executed and
there are no load or M{S}AC instructions in the EMAC execution pipeline.
In general, these store operations require only a single cycle for execution,
but if preceded immediately by a load, MAC, or MSAC instruction, the
depth of the EMAC pipeline is exposed and the execution time is four
cycles.
3.3.5.7
Branch Instruction Execution Times
Table 3-18. General Branch Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d16,PC)
(d8,An,Xi*SF)
(d8,PC,Xi*SF)
xxx.wl
#xxx
BRA
—
—
—
—
2(0/1)
—
—
—
BSR
—
—
—
—
3(0/1)
—
—
—
JMP
<ea>
—
3(0/0)
—
—
3(0/0)
4(0/0)
3(0/0)
—
JSR
<ea>
—
3(0/1)
—
—
3(0/1)
4(0/1)
3(0/1)
—
RTE
—
—
10(2/0)
—
—
—
—
—
RTS
—
—
5(1/0)
—
—
—
—
—
Table 3-19. Bcc Instruction Execution Times
Opcode
Forward
Taken
Forward
Not Taken
Backward
Taken
Backward
Not Taken
Bcc
3(0/0)
1(0/0)
2(0/0)
3(0/0)
MCF52277 Reference Manual, Rev 2
3-32
Freescale Semiconductor
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
4.1
Introduction
This chapter describes the functionality, microarchitecture, and performance of the enhanced
multiply-accumulate (EMAC) unit in the ColdFire family of processors.
4.1.1
Overview
The EMAC design provides a set of DSP operations that can improve the performance of embedded code
while supporting the integer multiply instructions of the baseline ColdFire architecture.
The MAC provides functionality in three related areas:
1. Signed and unsigned integer multiplication
2. Multiply-accumulate operations supporting signed and unsigned integer operands as well as
signed, fixed-point, and fractional operands
3. Miscellaneous register operations
The ColdFire family supports two MAC implementations with different performance levels and
capabilities. The original MAC features a three-stage execution pipeline optimized for 16-bit operands,
with a 16x16 multiply array and a single 32-bit accumulator. The EMAC features a four-stage pipeline
optimized for 32-bit operands, with a fully pipelined 32 × 32 multiply array and four 48-bit accumulators.
The first ColdFire MAC supported signed and unsigned integer operands and was optimized for 16x16
operations, such as those found in applications including servo control and image compression. As
ColdFire-based systems proliferated, the desire for more precision on input operands increased. The result
was an improved ColdFire MAC with user-programmable control to optionally enable use of fractional
input operands.
EMAC improvements target three primary areas:
• Improved performance of 32 × 32 multiply operation.
• Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges
between the accumulator and the pipeline’s general-purpose registers
• A 48-bit accumulation data path to allow a 40-bit product, plus 8 extension bits increase the
dynamic number range when implementing signal processing algorithms
The three areas of functionality are addressed in detail in following sections. The logic required to support
this functionality is contained in a MAC module (Figure 4-1).
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
4-1
Enhanced Multiply-Accumulate Unit (EMAC)
Operand Y
Operand X
X
Shift 0,1,-1
+/-
Accumulator(s)
Figure 4-1. Multiply-Accumulate Functionality Diagram
4.1.1.1
Introduction to the MAC
The MAC is an extension of the basic multiplier in most microprocessors. It is typically implemented in
hardware within an architecture and supports rapid execution of signal processing algorithms in fewer
cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some
variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal
transforms may have more demanding speed requirements beyond scope of any processor architecture and
may require full DSP implementation.
To balance speed, size, and functionality, the ColdFire MAC is optimized for a small set of operations that
involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for
single-cycle pipelined operations with a possible accumulation after product generation. This functionality
is common in many signal processing applications. The ColdFire core architecture is also modified to
allow an operand to be fetched in parallel with a multiply, increasing overall performance for certain DSP
operations.
Consider a typical filtering operation where the filter is defined as in Equation 4-1.
N–1
y(i) =
N–1
∑ a ( k )y ( i – k ) + ∑ b ( k )x ( i – k )
k=1
Eqn. 4-1
k=0
Here, the output y(i) is determined by past output values and past input values. This is the general form of
an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting
coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies
and product summing. To show this point, reduce Equation 4-1 to a simple, four-tap FIR filter, shown in
Equation 4-2, in which the accumulated sum is a past data values and coefficients sum.
3
y(i) =
∑ b ( k )x ( i – k ) = b ( 0 )x ( i ) + b ( 1 )x ( i – 1 ) + b ( 2 )x ( i – 2 ) + b ( 3 )x ( i – 3 )
Eqn. 4-2
k=0
MCF52277 Reference Manual, Rev 2
4-2
Freescale Semiconductor
Enhanced Multiply-Accumulate Unit (EMAC)
4.2
Memory Map/Register Definition
The following table and sections explain the MAC registers:
Table 4-1. EMAC Memory Map
BDM1
1
Register
Width
(bits)
Access
Reset Value
Section/Page
0x804
MAC Status Register (MACSR)
32
R/W
0x0000_0000
4.2.1/4-3
0x805
MAC Address Mask Register (MASK)
32
R/W
0xFFFF_FFFF
4.2.2/4-5
0x806
MAC Accumulator 0 (ACC0)
32
R/W
Undefined
4.2.3/4-6
0x807
MAC Accumulator 0,1 Extension Bytes (ACCext01)
32
R/W
Undefined
4.2.4/4-7
0x808
MAC Accumulator 2,3 Extension Bytes (ACCext23)
32
R/W
Undefined
4.2.4/4-7
0x809
MAC Accumulator 1 (ACC1)
32
R/W
Undefined
4.2.3/4-6
0x80A
MAC Accumulator 2 (ACC2)
32
R/W
Undefined
4.2.3/4-6
0x80B
MAC Accumulator 3 (ACC3)
32
R/W
Undefined
4.2.3/4-6
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see Chapter 32, “Debug Module.”
4.2.1
MAC Status Register (MACSR)
The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and multiple overflow condition flags are also provided.
BDM: 0x804 (MACSR)
Access: Supervisor read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
8
PAVn
7
6
OMC S/U
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
5
4
3
2
1
0
F/I
R/T
N
Z
V EV
0
0
0
0
0
0
Figure 4-2. MAC Status Register (MACSR)
Table 4-2. MACSR Field Descriptions
Field
Description
31–12
Reserved, must be cleared.
11–8
PAVn
Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or
MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a
MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator forms the
general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a move.l, MACSR
instruction or the accumulator is loaded directly.
Bit 11: Accumulator 3
...
Bit 8: Accumulator 0
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
4-3
Enhanced Multiply-Accumulate Unit (EMAC)
Table 4-2. MACSR Field Descriptions (continued)
Field
Description
7
OMC
Overflow saturation mode. Enables or disables saturation mode on overflow. If set, the accumulator is set
to the appropriate constant (see S/U field description) on any operation that overflows the accumulator.
After saturation, the accumulator remains unaffected by any other MAC or MSAC instructions until the
overflow bit is cleared or the accumulator is directly loaded.
6
S/U
Signed/unsigned operations.
In integer mode:
S/U determines whether operations performed are signed or unsigned. It also determines the accumulator
value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, an accumulator saturates to the most positive
(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on the instruction and the
product value that overflowed.
1 Unsigned numbers. On overflow, if OMC is enabled, an accumulator saturates to the smallest value
(0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.
In fractional mode:
S/U controls rounding while storing an accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose
register as a 32-bit value.
1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when moved to
a general-purpose register. See Section 4.3.1.1, “Rounding”. The resulting 16-bit value is stored in the
lower word of the destination register. The upper word is zero-filled. This rounding procedure does not
affect the accumulator value.
5
F/I
Fractional/integer mode. Determines whether input operands are treated as fractions or integers.
0 Integers can be represented in signed or unsigned notation, depending on the value of S/U.
1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to
1 - 2-15 for 16-bit fractions and -1 to 1 - 2-31 for 32-bit fractions. See Section 4.3.4, “Data
Representation."
4
R/T
Round/truncate mode. Controls rounding procedure for move.l ACCx,Rx, or MSAC.L instructions when
in fractional mode.
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator. Additionally, when
a store accumulator instruction is executed (move.l ACCx,Rx), the 8 lsbs of the 48-bit accumulator
logic are truncated.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest
40-bit value. If the low-order 24 bits equal 0x80_0000, the upper 40 bits are rounded to the nearest even
(lsb = 0) value. See Section 4.3.1.1, “Rounding”. Additionally, when a store accumulator instruction is
executed (move.l ACCx,Rx), the lsbs of the 48-bit accumulator logic round the resulting 16- or 32-bit
value. If MACSR[S/U] is cleared and MACSR[R/T] is set, the low-order 8 bits are used to round the
resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit
fraction.
3
N
Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
2
Z
Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load
operations; it is not affected by MULS and MULU instructions.
MCF52277 Reference Manual, Rev 2
4-4
Freescale Semiconductor
Enhanced Multiply-Accumulate Unit (EMAC)
Table 4-2. MACSR Field Descriptions (continued)
Field
Description
1
V
Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction, indicating that the result
cannot be represented in the limited width of the EMAC. V is set only if a product overflow occurs or the
accumulation overflows the 48-bit structure. V is evaluated on each MAC or MSAC operation and uses the
appropriate PAVn flag in the next-state V evaluation.
0
EV
Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in integer mode
or the 40 lsbs in fractional mode of the destination accumulator. However, the result remains accurately
represented in the combined 48-bit accumulator structure. Although an overflow has occurred, the correct
result, sign, and magnitude are contained in the 48-bit accumulator. Subsequent MAC or MSAC operations
may return the accumulator to a valid 32/40-bit result.
Table 4-3 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.
Table 4-3. Summary of S/U, F/I, and R/T Control Bits
4.2.2
S/U
F/I
R/T
Operational Modes
0
0
x
Signed, integer
0
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores
0
1
1
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-32-bits on accumulator stores
1
0
x
Unsigned, integer
1
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
1
1
1
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Mask Register (MASK)
The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved
with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source
operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones.
This register performs a simple AND with the operand address for MAC instructions. The processor
calculates the normal operand address and, if enabled, that address is then ANDed with {0xFFFF,
MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address
can be constrained to a certain memory region. This is used primarily to implement circular queues with
the (An)+ addressing mode.
This minimizes the addressing support required for filtering, convolution, or any routine that implements
a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be
included in all memory effective address calculations. The syntax is as follows:
mac.sz
Ry,RxSF,<ea>yand ,Rw
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
4-5
Enhanced Multiply-Accumulate Unit (EMAC)
The and operator enables the MASK use and causes bit 5 of the extension word to be set. The exact
algorithm for the use of MASK is:
if extension word, bit [5] = 1, the MASK bit, then
if <ea> = (An)
oa = An and {0xFFFF, MASK}
if <ea> = (An)+
oa = An
An = (An + 4) and
{0xFFFF, MASK}
if <ea> =-(An)
oa = (An - 4) and
An = (An - 4) and
{0xFFFF, MASK}
{0xFFFF, MASK}
if <ea> = (d16,An)
oa = (An + se_d16) and
{0xFFFF0x, MASK}
Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For
auto-addressing modes of post-increment and pre-decrement, the updated An value calculation is also
shown.
Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue
implementations.
BDM: 0x805 (MASK)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
W
8
7
6
5
4
3
2
1
0
MASK
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 4-3. Mask Register (MASK)
Table 4-4. MASK Field Descriptions
Field
Description
31–16
Reserved, must be set.
15–0
MASK
Performs a simple AND with the operand address for MAC instructions.
4.2.3
Accumulator Registers (ACC0–3)
The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers
form the entire 48-bit result.
MCF52277 Reference Manual, Rev 2
4-6
Freescale Semiconductor
Enhanced Multiply-Accumulate Unit (EMAC)
BDM: 0x806 (ACC0)
0x809 (ACC1)
0x80A (ACC2)
0x80B (ACC3)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
Accumulator
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 4-4. Accumulator Registers (ACC0–3)
Table 4-5. ACC0–3 Field Descriptions
Field
Description
31–0
Accumulator
4.2.4
Store 32-bits of the result of the MAC operation.
Accumulator Extension Registers (ACCext01, ACCext23)
Each pair of 8-bit accumulator extension fields are concatenated with the corresponding 32-bit
accumulator register to form the 48-bit accumulator. For more information, see Section 4.3, “Functional
Description.”
BDM: 0x807 (ACCext01)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
ACC0U
W
ACC0L
8
7
ACC1U
6
5
4
3
2
1
0
ACC1L
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 4-5. Accumulator Extension Register (ACCext01)
Table 4-6. ACCext01 Field Descriptions
Field
Description
31–24
ACC0U
Accumulator 0 upper extension byte
23–16
ACC0L
Accumulator 0 lower extension byte
15–8
ACC1U
Accumulator 1 upper extension byte
7–0
ACC1L
Accumulator 1 lower extension byte
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BDM: 0x808 (ACCext23)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
ACC2U
ACC2L
8
7
ACC3U
6
5
4
3
2
1
0
ACC3L
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 4-6. Accumulator Extension Register (ACCext23)
Table 4-7. ACCext23 Field Descriptions
Field
4.3
Description
31–24
ACC2U
Accumulator 2 upper extension byte
23–16
ACC2L
Accumulator 2 lower extension byte
15–8
ACC3U
Accumulator 3 upper extension byte
7–0
ACC3L
Accumulator 3 lower extension byte
Functional Description
The MAC speeds execution of ColdFire integer-multiply instructions (MULS and MULU) and provides
additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC,
execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early
termination that the OEP normally uses if no MAC hardware is present.
The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed
by the addition or subtraction of the product to or from the value in an accumulator. Optionally, the product
may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation
arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions.
Multiply-accumulate operations support 16- or 32-bit input operands in these formats:
• Signed integers
• Unsigned integers
• Signed, fixed-point, fractional numbers
The EMAC is optimized for single-cycle, pipelined 32 × 32 multiplications. For word- and
longword-sized integer input operands, the low-order 40 bits of the product are formed and used with the
destination accumulator. For fractional operands, the entire 64-bit product is calculated and truncated or
rounded to the most-significant 40-bit result using the round-to-nearest (even) method before it is
combined with the destination accumulator.
For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for
signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined
with the 48-bit destination accumulator.
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Figure 4-7 and Figure 4-8 show relative alignment of input operands, the full 64-bit product, the resulting
40-bit product used for accumulation, and 48-bit accumulator formats.
OperandY
X
Product
32
OperandX
32
0
23
40
Extended Product
8
40
8
40
+
Accumulator
8
Extension Byte Upper [7:0]
Accumulator [31:0]
Extension Byte Lower [7:0]
Figure 4-7. Fractional Alignment
X
Product
OperandY
32
OperandX
32
24
8
32
Extended Product
+
8
8
32
Accumulator
8
8
32
Extension Byte Upper [7:0]
Accumulator [31:0]
Extension Byte Lower [7:0]
Figure 4-8. Signed and Unsigned Integer Alignment
Therefore, the 48-bit accumulator definition is a function of the EMAC operating mode. Given that each
48-bit accumulator is the concatenation of 16-bit accumulator extension register (ACCextn) contents and
32-bit ACCn contents, the specific definitions are:
if MACSR[6:5] == 00
/* signed integer mode */
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
if MACSR[6:5] == 01 or 11 /* signed fractional mode */
Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]}
if MACSR[6:5] == 10
/* unsigned integer mode */
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
The four accumulators are represented as an array, ACCn, where n selects the register.
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Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC instructions
have an effective issue rate of 1 cycle, regardless of input operand size or type.
All arithmetic operations use register-based input operands, and summed values are stored in an
accumulator. Therefore, an additional MOVE instruction is needed to store data in a general-purpose
register. One new feature in EMAC instructions is the ability to choose the upper or lower word of a
register as a 16-bit input operand. This is useful in filtering operations if one data register is loaded with
the input data and another is loaded with the coefficient. Two 16-bit multiply accumulates can be
performed without fetching additional operands between instructions by alternating word choice during
calculations.
The EMAC has four accumulator registers versus the MAC’s single accumulator. The additional registers
improve the performance of some algorithms by minimizing pipeline stalls needed to store an accumulator
value back to general-purpose registers. Many algorithms require multiple calculations on a given data set.
By applying different accumulators to these calculations, it is often possible to store one accumulator
without any stalls while performing operations involving a different destination accumulator.
The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP
engines. Existing ColdFire instructions can accommodate these requirements. A MOVEM instruction can
efficiently move large data blocks by generating line-sized burst references. The ability to load an operand
simultaneously from memory into a register and execute a MAC instruction makes some DSP operations
such as filtering and convolution more manageable.
The programming model includes a mask register (MASK), which can optionally be used to generate an
operand address during MAC + MOVE instructions. The register application with auto-increment
addressing mode supports efficient implementation of circular data queues for memory operands.
4.3.1
Fractional Operation Mode
This section describes behavior when the fractional mode is used (MACSR[F/I] is set).
4.3.1.1
Rounding
When the processor is in fractional mode, there are two operations during which rounding can occur:
1. Execution of a store accumulator instruction (move.l ACCx,Rx). The lsbs of the 48-bit accumulator
logic are used to round the resulting 16- or 32-bit value. If MACSR[S/U] is cleared, the low-order
8 bits round the resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to
round the resulting 16-bit fraction.
2. Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero,
multiplying two 32-bit numbers creates a 64-bit product truncated to the upper 40 bits; otherwise,
it is rounded using round-to-nearest (even) method.
To understand the round-to-nearest-even method, consider the following example involving the rounding
of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest
16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L.
• If R0.L is less than 0x8000, the result is truncated to the value of R0.U.
• If R0.L is greater than 0x8000, the upper word is incremented (rounded up).
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•
If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is based on
the lsb of R0.U, so the result is always even (lsb = 0).
— If the lsb of R0.U equals 1 and R0.L equals 0x8000, the number is rounded up.
— If the lsb of R0.U equals 0 and R0.L equals 0x8000, the number is rounded down.
This method minimizes rounding bias and creates as statistically correct an answer as possible.
The rounding algorithm is summarized in the following pseudocode:
if R0.L < 0x8000
then Result = R0.U
else if R0.L > 0x8000
then Result = R0.U + 1
else if lsb of R0.U = 0
then Result = R0.U
else Result = R0.U + 1
/* R0.L = 0x8000 */
The round-to-nearest-even technique is also known as convergent rounding.
4.3.1.2
Saving and Restoring the EMAC Programming Model
The presence of rounding logic in the EMAC output datapath requires special care during the EMAC’s
save/restore process. In particular, any result rounding modes must be disabled during the save/restore
process so the exact bit-wise contents of the EMAC registers are accessed. Consider the memory structure
containing the EMAC programming model:
struct
macState {
int acc0;
int acc1;
int acc2;
int acc3;
int accext01;
int accext02;
int mask;
int macsr;
} macState;
The following assembly language routine shows the proper sequence for a correct EMAC state save. This
code assumes all Dn and An registers are available for use, and the memory location of the state save is
defined by A7.
EMAC_state_save:
move.l
clr.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
movem.l
macsr,d7
d0
d0,macsr
acc0,d0
acc1,d1
acc2,d2
acc3,d3
accext01,d4
accext23,d5
mask,d6
#0x00ff,(a7)
;
;
;
;
save the macsr
zero the register to ...
disable rounding in the macsr
save the accumulators
; save the accumulator extensions
; save the address mask
; move the state to memory
This code performs the EMAC state restore:
EMAC_state_restore:
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movem.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
(a7),#0x00ff
#0,macsr
d0,acc0
d1,acc1
d2,acc2
d3,acc3
d4,accext01
d5,accext23
d6,mask
d7,macsr
; restore the state from memory
; disable rounding in the macsr
; restore the accumulators
; restore the accumulator extensions
; restore the address mask
; restore the macsr
Executing this sequence type can correctly save and restore the exact state of the EMAC programming
model.
4.3.1.3
MULS/MULU
MULS and MULU are unaffected by fractional-mode operation; operands remain assumed to be integers.
4.3.1.4
Scale Factor in MAC or MSAC Instructions
The scale factor is ignored while the MAC is in fractional mode.
4.3.2
EMAC Instruction Set Summary
Table 4-8 summarizes EMAC unit instructions.
Table 4-8. EMAC Instruction Summary
Command
Mnemonic
Description
Multiply Signed
muls <ea>y,Dx
Multiplies two signed operands yielding a signed result
Multiply Unsigned
mulu <ea>y,Dx
Multiplies two unsigned operands yielding an unsigned result
Multiply Accumulate
mac Ry,RxSF,ACCx
msac Ry,RxSF,ACCx
Multiplies two operands and adds/subtracts the product
to/from an accumulator
Multiply Accumulate
with Load
mac Ry,Rx,<ea>y,Rw,ACCx
msac Ry,Rx,<ea>y,Rw,ACCx
Multiplies two operands and combines the product to an
accumulator while loading a register with the memory operand
Load Accumulator
move.l {Ry,#imm},ACCx
Loads an accumulator with a 32-bit operand
Store Accumulator
move.l ACCx,Rx
Writes the contents of an accumulator to a CPU register
Copy Accumulator
move.l ACCy,ACCx
Copies a 48-bit accumulator
Load MACSR
move.l {Ry,#imm},MACSR
Writes a value to MACSR
Store MACSR
move.l MACSR,Rx
Write the contents of MACSR to a CPU register
Store MACSR to CCR
move.l MACSR,CCR
Write the contents of MACSR to the CCR
Load MAC Mask Reg
move.l {Ry,#imm},MASK
Writes a value to the MASK register
Store MAC Mask Reg
move.l MASK,Rx
Writes the contents of the MASK to a CPU register
Load Accumulator
Extensions 01
move.l {Ry,#imm},ACCext01 Loads the accumulator 0,1 extension bytes with a 32-bit
operand
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Table 4-8. EMAC Instruction Summary (continued)
Command
Mnemonic
Description
Load Accumulator
Extensions 23
move.l {Ry,#imm},ACCext23 Loads the accumulator 2,3 extension bytes with a 32-bit
operand
Store Accumulator
Extensions 01
move.l ACCext01,Rx
Writes the contents of accumulator 0,1 extension bytes into a
CPU register
Store Accumulator
Extensions 23
move.l ACCext23,Rx
Writes the contents of accumulator 2,3 extension bytes into a
CPU register
4.3.3
EMAC Instruction Execution Times
The instruction execution times for the EMAC can be found in Section 3.3.5.6, “EMAC Instruction
Execution Times”.
The EMAC execution pipeline overlaps the AGEX stage of the OEP (the first stage of the EMAC pipeline
is the last stage of the basic OEP). EMAC units are designed for sustained, fully-pipelined operation on
accumulator load, copy, and multiply-accumulate instructions. However, instructions that store contents
of the multiply-accumulate programming model can generate OEP stalls that expose the EMAC execution
pipeline depth:
mac.w
Ry, Rx, Acc0
move.l
Acc0, Rz
The MOVE.L instruction that stores the accumulator to an integer register (Rz) stalls until the
program-visible copy of the accumulator is available. Figure 4-9 shows EMAC timing.
Three-cycle
regBusy stall
move
mac
DSOC
move
AGEX
mac
move
EMAC EX1
mac
move
mac
EMAC EX2
mac
EMAC EX3
mac
EMAC EX4
Accumulator 0
old
new
Figure 4-9. EMAC-Specific OEP Sequence Stall
In Figure 4-9, the OEP stalls the store-accumulator instruction for three cycles: the EMAC pipleline depth
minus 1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the
AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is
performed, the recently updated accumulator 0 value is available.
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As with change or use stalls between accumulators and general-purpose registers, introducing intervening
instructions that do not reference the busy register can reduce or eliminate sequence-related store-MAC
instruction stalls. A major benefit of the EMAC is the addition of three accumulators to minimize stalls
caused by exchanges between accumulator(s) and general-purpose registers.
4.3.4
Data Representation
MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand
type:
1. Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2(N-1)
< operand < 2(N-1) - 1. The binary point is right of the lsb.
2. Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2N - 1. The
binary point is right of the lsb.
3. Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining
bits signify the first N-1 bits after the binary point. Given an N-bit number, aN-1aN-2aN-3... a2a1a0,
its value is given by the equation in Equation 4-3.
N–2
value = – ( 1 ⋅ a N – 1 ) +
∑2
–( i + 1 – N )
⋅ ai
Eqn. 4-3
i=0
This format can represent numbers in the range -1 < operand < 1 - 2(N-1).
For words and longwords, the largest negative number that can be represented is -1, whose internal
representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 - 2-15);
the most positive longword is 0x7FFF_FFFF or (1 - 2-31).
4.3.5
MAC Opcodes
MAC opcodes are described in the ColdFire Programmer’s Reference Manual.
Remember the following:
• Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that
involves the product and the accumulator.
• The overflow (V) flag is managed differently. It is set if the complete product cannot be represented
as a 40-bit value (this applies to 32 × 32 integer operations only) or if the combination of the
product with an accumulator cannot be represented in the given number of bits. The EMAC design
includes an additional product/accumulation overflow bit for each accumulator that are treated as
sticky indicators and are used to calculate the V bit on each MAC or MSAC instruction. See
Section 4.2.1, “MAC Status Register (MACSR)”.
• For the MAC design, the assembler syntax of the MAC (multiply and add to accumulator) and
MSAC (multiply and subtract from accumulator) instructions does not include a reference to the
single accumulator. For the EMAC, assemblers support this syntax and no explicit reference to an
accumulator is interpreted as a reference to ACC0. Assemblers also support syntaxes where the
destination accumulator is explicitly defined.
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•
The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1
indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is
added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the
EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because
a product can overflow, the following guidelines are implemented:
— For unsigned word and longword operations, a zero is shifted into the product on right shifts.
— For signed, word operations, the sign bit is shifted into the product on right shifts unless the
product is zero. For signed, longword operations, the sign bit is shifted into the product unless
an overflow occurs or the product is zero, in which case a zero is shifted in.
— For all left shifts, a zero is inserted into the lsb position.
The following pseudocode explains basic MAC or MSAC instruction functionality. This example is
presented as a case statement covering the three basic operating modes with signed integers, unsigned
integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {},
indicates a concatenation operation.
switch (MACSR[6:5])
/* MACSR[S/U, F/I] */
{
case 0:
/* signed integers */
if (MACSR.OMC == 0 || MACSR.PAVn == 0)
then {
MACSR.PAVn = 0
/* select the input operands */
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]}
else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]}
if (U/Lx == 1)
then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}
else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]}
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
if ((product[63:39] != 0x0000_00_0) and and (product[63:39] != 0xffff_ff_1))
then {
/* product overflow */
MACSR.PAVn = 1
MACSR.V = 1
if (inst == MSAC and and MACSR.OMC == 1)
then if (product[63] == 1)
then result[47:0] = 0x0000_7fff_ffff
else result[47:0] = 0xffff_8000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
if (product[63] == 1)
then result[47:0] = 0xffff_8000_0000
else result[47:0] = 0x0000_7fff_ffff
}
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/* sign-extend to 48 bits before performing any scaling */
product[47:40] = {8{product[39]}}
/* sign-extend */
/* scale product before combining with accumulator */
switch (SF)
/* 2-bit scale factor */
{
case 0:
/* no scaling specified */
break;
case 1:
/* SF = “<< 1” */
product[40:0] = {product[39:0], 0}
break;
case 2:
/* reserved encoding */
break;
case 3:
/* SF = “>> 1” */
product[39:0] = {product[39], product[39:1]}
break;
}
if (MACSR.PAVn == 0)
then {if (inst == MSAC)
then result[47:0] = ACCx[47:0] - product[47:0]
else result[47:0] = ACCx[47:0] + product[47:0]
}
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.PAVn = 1
MACSR.V = 1
if (MACSR.OMC == 1)
then /* accumulation overflow,
saturationMode enabled */
if (result[47] == 1)
then result[47:0] = 0x0000_7fff_ffff
else result[47:0] = 0xffff_8000_0000
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVn
MACSR.N = ACCx[47]
if (ACCx[47:0] == 0x0000_0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
if ((ACCx[47:31] == 0x0000_0) || (ACCx[47:31] == 0xffff_1))
then MACSR.EV = 0
else MACSR.EV = 1
break;
case 1,3:
/* signed fractionals */
if (MACSR.OMC == 0 || MACSR.PAVn == 0)
then {
MACSR.PAVn = 0
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {Ry[31:16], 0x0000}
else operandY[31:0] = {Ry[15:0], 0x0000}
if (U/Lx == 1)
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then operandX[31:0] = {Rx[31:16], 0x0000}
else operandX[31:0] = {Rx[15:0], 0x0000}
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
/* perform the multiply */
product[63:0] = (operandY[31:0] * operandX[31:0]) << 1
/* check for product rounding */
if (MACSR.R/T == 1)
then { /* perform convergent rounding */
if (product[23:0] > 0x80_0000)
then product[63:24] = product[63:24] + 1
else if ((product[23:0] == 0x80_0000) and and (product[24] == 1))
then product[63:24] = product[63:24] + 1
}
/* sign-extend to 48 bits and combine with accumulator */
/* check for the -1 * -1 overflow case */
if ((operandY[31:0] == 0x8000_0000) and and (operandX[31:0] == 0x8000_0000))
then product[71:64] = 0x00
/* zero-fill */
else product[71:64] = {8{product[63]}}
/* sign-extend */
if (inst == MSAC)
then result[47:0] = ACCx[47:0] - product[71:24]
else result[47:0] = ACCx[47:0] + product[71:24]
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.PAVn = 1
MACSR.V = 1
if (MACSR.OMC == 1)
then /* accumulation overflow,
saturationMode enabled */
if (result[47] == 1)
then result[47:0] = 0x007f_ffff_ff00
else result[47:0] = 0xff80_0000_0000
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVn
MACSR.N = ACCx[47]
if (ACCx[47:0] == 0x0000_0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
if ((ACCx[47:39] == 0x00_0) || (ACCx[47:39] == 0xff_1))
then MACSR.EV = 0
else MACSR.EV = 1
break;
case 2:
/* unsigned integers */
if (MACSR.OMC == 0 || MACSR.PAVn == 0)
then {
MACSR.PAVn = 0
/* select the input operands */
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {0x0000, Ry[31:16]}
else operandY[31:0] = {0x0000, Ry[15:0]}
if (U/Lx == 1)
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then operandX[31:0] = {0x0000, Rx[31:16]}
else operandX[31:0] = {0x0000, Rx[15:0]}
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
if (product[63:40] != 0x0000_00)
then {
/* product overflow */
MACSR.PAVn = 1
MACSR.V = 1
if (inst == MSAC and and MACSR.OMC == 1)
then result[47:0] = 0x0000_0000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
result[47:0] = 0xffff_ffff_ffff
}
/* zero-fill to 48 bits before performing any scaling */
product[47:40] = 0
/* zero-fill upper byte */
/* scale product before combining with accumulator */
switch (SF)
/* 2-bit scale factor */
{
case 0:
/* no scaling specified */
break;
case 1:
/* SF = “<< 1” */
product[40:0] = {product[39:0], 0}
break;
case 2:
/* reserved encoding */
break;
case 3:
/* SF = “>> 1” */
product[39:0] = {0, product[39:1]}
break;
}
/* combine with accumulator */
if (MACSR.PAVn == 0)
then {if (inst == MSAC)
then result[47:0] = ACCx[47:0] - product[47:0]
else result[47:0] = ACCx[47:0] + product[47:0]
}
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.PAVn = 1
MACSR.V = 1
if (inst == MSAC and and MACSR.OMC == 1)
then result[47:0] = 0x0000_0000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
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result[47:0] = 0xffff_ffff_ffff
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVn
MACSR.N = ACCx[47]
if (ACCx[47:0] == 0x0000_0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
if (ACCx[47:32] == 0x0000)
then MACSR.EV = 0
else MACSR.EV = 1
break;
}
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Enhanced Multiply-Accumulate Unit (EMAC)
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Chapter 5
Cache
5.1
Introduction
This chapter describes cache operation on the ColdFire processor.
5.1.1
Features
Features include the following:
• Configurable as instruction, data, or split instruction/data cache
• 8-Kbyte direct-mapped cache
• Single-cycle access on cache hits
• Physically located on the ColdFire core's high-speed local bus
• Nonblocking design to maximize performance
• Separate instruction and data 16-Byte line-fill buffers
• Configurable instruction cache miss-fetch algorithm
5.1.2
Introduction
The cache is a direct-mapped, single-cycle memory. It may be configured as an instruction cache, a
write-through data cache, or a split instruction/data cache. The cache storage is organized as 512 lines,
each containing 16 bytes. The memory storage consists of a 512-entry tag array (containing addresses and
a valid bit), and a data array containing 8 Kbytes, organized as 2048 × 32 bits.
Cache configuration is controlled by bits in the cache control register (CACR), detailed later in this
chapter. For the instruction or data-only configurations, only the associated instruction or data line-fill
buffer is used. For the split cache configuration, one-half of the tag and storage arrays is used for an
instruction cache and one-half is used for a data cache. The split cache configuration uses the instruction
and the data line-fill buffers. The core’s local bus is a unified bus used for instruction and data fetches.
Therefore, the cache can have only one fetch, instruction or data, active at one time.
For the instruction- or data-only configurations, the cache tag and storage arrays are accessed in parallel:
fetch address bits [12:4] addressing the tag array, and fetch address bits [12:2] addressing the storage array.
For the split cache configuration, the cache tag and storage arrays are accessed in parallel. The msb of the
tag array address is set for instruction fetches and cleared for operand fetches; fetch address bits [11:4]
provide the rest of the tag array address. The tag array outputs the address mapped to the given cache
location along with the valid bit for the line. This address field is compared to bits [31:13] for instructionor data-only configurations and to bits [31:12] for a split configuration of the fetch address from the local
bus to determine if a cache hit has occurred. If the desired address is mapped into the cache memory, the
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Cache
output of the storage array is driven onto the ColdFire core's local data bus, thereby completing the access
in a single cycle.
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded
into the cache.
The cache also contains separate 16-byte instruction and data line-fill buffers that provide temporary
storage for the last line fetched in response to a cache miss. With each fetch, the contents of the associated
line fill buffer are examined. Thus, each fetch address examines the tag memory array and the associated
line fill buffer to see if the desired address is mapped into either hardware resource. A cache hit in the
memory array or the associated line-fill buffer is serviced in a single cycle. Because the line fill buffer
maintains valid bits on a longword basis, hits in the buffer can be serviced immediately without waiting
for the entire line to be fetched.
If the referenced address is not contained in the memory array or the associated line-fill buffer, the cache
initiates the required external fetch operation. In most situations, this is a 16-byte line-sized burst
reference.
The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is released
after the initial access of a miss. Thus, the cache or the SRAM module can service subsequent requests
while the remainder of the line is being fetched and loaded into the fill buffer.
External Data[31:0]
Local Address Bus
31
12
43 2 1 0
31
4
I or D Line Buffer Storage
Data Index
Tag Index
I or D Line
Buffer
Address
=
MUX
Fill Hit
31
13
TAG
VALID
0
31
0
0
DATA
2047
511
=
MUX
Tag Hit
Local Data Bus
Figure 5-1. 8-Kbyte Cache Block Diagram
5.2
Memory Map/Register Definition
Three supervisor registers define the operation of the cache and local bus controller: the cache control
register (CACR) and two access control registers (ACR0, ACR1). Table 5-1 below shows the memory map
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Cache
of these registers. The CACR and ACRs can only be accessed in supervisor mode using the MOVEC
instruction with an Rc value of 0x002, 0x004 and 0x005, respectively.
Table 5-1. Cache Memory Map
BDM1
Register
Width
(bits)
Access2
Reset Value
Section/Page
0x002
Cache Control Register (CACR)
32
W
0x0000_0000
5.2.1/5-3
0x004
Access Control Register 0 (ACR0)
32
W
See Section
5.2.2/5-6
0x005
Access Control Register 1 (ACR1)
32
W
See Section
5.2.2/5-6
1
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For
more information see Chapter 32, “Debug Module.”
2
Readable through debug.
5.2.1
Cache Control Register (CACR)
The CACR controls the operation of the cache. The CACR provides a set of default memory access
attributes used when a reference address does not map into the spaces defined by the ACRs.
The CACR is a 32-bit, write-only supervisor control register. It is accessed in the CPU address space via
the MOVEC instruction with an Rc encoding of 0x002. The CACR can be read when in background debug
mode (BDM). Therefore, the register diagram, Figure 5-2, is shown as read/write. At system reset, the
entire register is cleared.
BDM: 0x002 (CACR)
31
R
W
Reset
R
Access: Supervisor write-only
Debug read/write
30
29
0
0
0
0
0
0
15
14
13
0
0
0
0
0
0
CENB
28
27
26
25
0
0
0
0
12
11
10
0
0
0
0
CPD CFRZ
W
Reset
24
22
21
20
CINV
DISI
DISD
INVI
INVD
0
0
0
0
0
0
9
8
5
4
CEIB DCM DBWE
0
23
0
0
7
6
0
0
0
0
DWP EUSP
0
0
19
18
17
16
0
0
0
0
0
0
0
0
1
0
3
2
0
0
0
0
CLNF
0
0
Figure 5-2. Cache Control Register (CACR)
Table 5-2. CACR Field Descriptions
Field
Description
31
CENB
Cache enable. The memory array of the cache is enabled only if CENB is asserted. This bit, along with the DISI
(disable instruction caching) and DISD (disable data caching) bits, control the cache configuration.
0 Cache disabled
1 Cache enabled
Table 5-3 describes cache configuration.
30–29
Reserved, must be cleared.
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Cache
Table 5-2. CACR Field Descriptions (continued)
Field
Description
28
CPDI
Disable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the cache entry defined by bits
[12:4] of the address is invalidated if CPDI is cleared. If CPDI is set, no operation is performed.
0 Enable invalidation
1 Disable invalidation
27
CFRZ
Cache freeze. This field allows the user to freeze the contents of the cache. When CFRZ is asserted line fetches can
be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritten. If a given cache location
is invalid, the contents of the line-fill buffer can be written into the memory array while CFRZ is asserted.
0 Normal Operation
1 Freeze valid cache lines
26–25
Reserved, must be cleared.
24
CINV
Cache invalidate. The cache invalidate operation is not a function of the CENB state (this operation is independent
of the cache being enabled or disabled). Setting this bit forces the cache to invalidate all, half, or none of the tag array
entries depending on the state of the DISI, DISD, INVI, and INVD bits. The invalidation process requires several
cycles of overhead plus 512 machine cycles to clear all tag array entries and 256 cycles to clear half of the tag array
entries, with a single cache entry cleared per machine cycle. The state of this bit is always read as a zero. After a
hardware reset, the cache must be invalidated before it is enabled.
0 No operation
1 Invalidate all cache locations
Table 5-4 describes how to set the cache invalidate all bit.
23
DISI
Disable instruction caching. When set, this bit disables instruction caching. This bit, along with the CENB (cache
enable) and DISD (disable data caching) bits, control the cache configuration. See the CENB definition for a detailed
description.
0 Enable instruction caching
1 Disable instruction caching
Table 5-3 describes cache configuration and Table 5-4 describes how to set the cache invalidate all bit.
22
DISD
Disable data caching. When set, this bit disables data caching. This bit, along with the CENB (cache enable) and
DISI (disable instruction caching) bits, control the cache configuration. See the CENB definition for a detailed
description.
0 Enable data caching
1 Disable data caching
Table 5-3 describes cache configuration and Table 5-4 describes how to set the cache invalidate all bit.
21
INVI
CINV instruction cache only. This bit can not be set unless the cache configuration is split (DISI and DISD cleared).
For instruction or data cache configurations this bit is a don’t-care. For the split cache configuration, this bit is part of
the control for the invalidate all operation. See the CINV definition for a detailed description
Table 5-4 describes how to set the cache invalidate all bit.
20
INVD
CINV data cache only. This bit can not be set unless the cache configuration is split (DISI and DISD cleared). For
instruction or data cache configurations this bit is a don’t-care. For the split cache configuration, this bit is part of the
control for the invalidate all operation. See the CINV definition for a detailed description
Table 5-4 describes how to set the cache invalidate all bit.
19–11
Reserved, must be cleared.
10
CEIB
Cache enable non-cacheable instruction bursting. Setting this bit enables the line-fill buffer to be loaded with burst
transfers under control of CLNF[1:0] for non-cacheable accesses. Non-cacheable accesses are never written into
the memory array. See Table 5-7.
0 Disable burst fetches on non-cacheable accesses
1 Enable burst fetches on non-cacheable accesses
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Cache
Table 5-2. CACR Field Descriptions (continued)
Field
Description
9
DCM
Default cache mode. This bit defines the default cache mode. For more information on the selection of the effective
memory attributes, see Section 5.3.2, “Memory Reference Attributes.
0 Caching enabled
1 Caching disabled
8
DBWE
Default buffered write enable. This bit defines the default value for enabling buffered writes. If DBWE = 0, the
termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is
completed. If DBWE = 1, the write cycle on the local bus is terminated immediately and the operation buffered in the
bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus and
the external bus. Generally, enabled buffered writes provide higher system performance but recovery from access
errors can be more difficult. For the ColdFire core, reporting access errors on operand writes is always imprecise
and enabling buffered writes further decouples the write instruction and the signaling of the fault
0 Disable buffered writes
1 Enable buffered writes
7–6
Reserved, must be cleared.
5
DWP
Default write protection
0 Read and write accesses permitted
1 Only read accesses permitted
4
EUSP
Enable user stack pointer. See Section 3.2.3, “Supervisor/User Stack Pointers (A7 and OTHER_A7)”for more
information on the dual stack pointer implementation.
0 Disable the processor’s use of the User Stack Pointer
1 Enable the processor’s use of the User Stack Pointer
3–2
1–0
CLNF
Reserved, must be cleared.
Cache line fill. These bits control the size of the memory request the cache issues to the bus controller for different
initial instruction line access offsets. See Table 5-6 for external fetch size based on miss address and CLNF.
Table 5-3 shows the relationship between CACR[CENB, DISI, & DISD] bits and the cache configuration.
Table 5-3. Cache Configuration as Defined by CACR
CACR
[CENB]
CACR
[DISI]
CACR
[DISD]
Configuration
0
x
x
N/A
1
0
0
Split Instruction/
Data Cache
4 KByte direct-mapped instruction cache (uses upper
half of tag and storage arrays) and 4 KByte
direct-mapped write-through data cache (uses lower
half of tag and storage arrays)
1
0
1
Instruction Cache
8 KByte direct-mapped instruction cache (uses all of
tag and storage arrays)
1
1
0
Data Cache
Description
Cache is completely disabled
8 KByte direct-mapped write-through data cache
(uses all of tag and storage arrays)
Table 5-4 shows the relationship between CACR[DISI, DISD, INVI, & INVD] and setting the cache
invalidate all bit (CACR[CINV]).
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Cache
Table 5-4. Cache Invalidate All as Defined by CACR
5.2.2
CACR
[DISI]
CACR
[DISD]
CACR
[INVI]
CACR
[INVD]
0
0
0
0
Split Instruction/
Data Cache
Invalidate all entries in 4-KByte instruction
cache and 4-KByte data cache
0
0
0
1
Split Instruction/
Data Cache
Invalidate only 4 KByte data cache
0
0
1
0
Split Instruction
Data Cache
Invalidate only 4 KByte instruction cache
0
0
1
1
Split Instruction/
Data Cache
No invalidate
1
0
x
x
Instruction Cache
Invalidate 8 KByte instruction cache
0
1
x
x
Data Cache
Invalidate 8 KByte data cache
Configuration
Operation
Access Control Registers (ACR0, ACR1)
The ACRs provide a definition of memory reference attributes for two memory regions (one per ACR).
This set of effective attributes is defined for every memory reference using the ACRs or the set of default
attributes contained in the CACR. The ACRs are examined for every processor memory reference not
mapped to the SRAM memories.
The ACRs are 32-bit, write-only supervisor control register. They are accessed in the CPU address space
via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The ACRs can be read when in
background debug mode (BDM). Therefore, the register diagram, Figure 5-3, is shown as read/write. At
system reset, both registers are disabled with ACRn[EN] cleared.
NOTE
Peripheral space (0xE000_0000-0xFFFF_FFFF) should not be cached. The
combination of the CACR defaults and the two ACRn registers must define
the non-cacheable attribute for this address space.
BDM: 0x004 (ACR0)
0x005 (ACR1)
Access: Supervisor write-only
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
R
W
AB
AM
Reset – – – – – – – – – – – – – – – –
EN
0
14
13
SM
–
–
12
11
10
9
8
7
0
0
0
0
0
0
0
0
0
0
0
0
6
5
CM BWE
–
–
4
3
0
0
0
0
2
WP
–
1
0
0
0
0
0
Figure 5-3. Access Control Registers (ACRn)
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Cache
Table 5-5. ACRn Field Descriptions
Field
Description
31–24
AB
Address base. This 8-bit field is compared to address bits [31:24] from the processor's local bus under control of the
ACR address mask. If the address matches, the attributes for the memory reference are sourced from the given ACR.
23–16
AM
Address mask. Masks any AB bit. If a bit in the AM field is set, the corresponding bit of the address field comparison
is ignored.
15
EN
ACR Enable. Hardware reset clears this bit, disabling the ACR.
0 ACR disabled
1 ACR enabled
14–13
SM
Supervisor mode. Allows the given ACR to be applied to references based on operating privilege mode of the
ColdFire processor. The field uses the ACR for user references only, supervisor references only, or all accesses.
00 Match if user mode
01 Match if supervisor mode
1x Match always—ignore user/supervisor mode
12–7
Reserved, must be cleared.
6
CM
5
BWE
Cache mode.
0 Caching enabled
1 Caching disabled
Buffered write enable. Defines the value for enabling buffered writes. If BWE is cleared, the termination of an operand
write cycle on the processor's local bus is delayed until the system bus cycle is completed. Setting BWE terminates
the write cycle on the local bus immediately and the operation is then buffered in the bus controller. In this mode,
operand write cycles are effectively decoupled between the processor's local bus and the system bus.
Generally, the enabling of buffered writes provides higher system performance but recovery from access errors may
be more difficult.
For the V2 ColdFire core, the reporting of access errors on operand writes is always imprecise, and enabling buffered
writes simply decouples the write instruction from the signaling of the fault even more.
0 Writes are not buffered.
1 Writes are buffered.
4–3
Reserved, must be cleared.
2
WP
Write protect. Defines the write-protection attribute. If the effective memory attributes for a given access select the
WP bit, an access error terminates any attempted write with this bit set.
0 Read and write accesses permitted
1 Only read accesses permitted
1–0
Reserved, must be cleared.
5.3
Functional Description
The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches from
the ColdFire core and certain memory fetches initiated by the debug module. Typically, the debug module's
memory references appear as supervisor data accesses but the unit can be programmed to generate
user-mode accesses and/or instruction fetches. The cache processes any fetch access in the normal manner.
5.3.1
Interaction with Other Modules
Because the cache and high-speed SRAM module are connected to the ColdFire core's local data bus,
certain user-defined configurations can result in simultaneous fetch processing.
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Cache
If the referenced address is mapped into the SRAM module, that module services the request in a single
cycle. In this case, data accessed from the cache is simply discarded and no external memory references
are generated. If the address is not mapped into the SRAM space, the cache handles the request in the
normal fashion.
5.3.2
Memory Reference Attributes
For every memory reference the ColdFire core or the debug module generates, a set of effective attributes
is determined based on the address and the access control registers (ACRs). This set of attributes includes
the cacheable/non-cacheable definition, the precise/imprecise handling of operand write, and the
write-protect capability.
In particular, each address is compared to the values programmed in the ACRs. If the address matches one
of the ACR values, the access attributes from that ACR are applied to the reference. If the address does
not match either ACR, then the default value defined in the cache control register (CACR) is used. The
specific algorithm is as follows:
if (address == ACR0_address including mask)
Effective Attributes = ACR0 attributes
else if (address == ACR1_address including mask)
Effective Attributes = ACR1 attributes
else Effective Attributes = CACR default attributes
5.3.3
Cache Coherency and Invalidation
The cache does not monitor data references for accesses to cached instructions. Therefore, software must
maintain instruction cache coherency by invalidating the appropriate cache entries after modifying code
segments if instructions are cached.
The cache invalidation can be performed in several ways. For the instruction- or data-only configurations,
setting CACR[CINV] forces the entire cache to be marked as invalid. The invalidation operation requires
512 cycles because the cache sequences through the entire tag array, clearing a single location each cycle.
For the split configuration, CACR[INVI] and CACR[INVD] can be used in addition to CACR[CINV] to
clear the entire cache, only the instruction half, or only the data half. Any subsequent fetch accesses are
postponed until the invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is executed,
the cache entry defined by bits [12:4] of the source address register is invalidated, provided CACR[CPDI]
is cleared. For the split data/instruction cache configuration, software directly controls bit 12 that selects
whether an instruction cache or data cache line is being accessed.
These invalidation operations can be initiated from the ColdFire core or the debug module.
5.3.4
Reset
A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected
by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting
CACR[CINV] before the cache can be enabled.
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Cache
5.3.5
Cache Miss Fetch Algorithm/Line Fills
As discussed in Section 5.1.2, “Introduction,” the cache hardware includes a 16-byte, line-fill buffer for
providing temporary storage for the last fetched line.
With the cache enabled as defined by CACR[CENB], a cacheable fetch that misses in the tag memory and
the line-fill buffer generates an external fetch. For data misses, the size of the external fetch is always 16
bytes. For instruction misses, the size of the external fetch is determined by the value contained in the 2-bit
CLNF field of the CACR and the miss address. Table 5-6 shows the relationship between the CLNF bits,
the miss address, and the size of the external fetch.
Table 5-6. Initial Fetch Offset vs. CLNF Bits
Longword Address Bits[3:2]
CLNF[1:0]
00
01
10
11
00
Line
Line
Line
Longword
01
Line
Line
Longword
Longword
1X
Line
Line
Line
Line
Depending on the runtime characteristics of the application and the memory response speed, overall
performance may be increased by programming the CLNF bits to values 00 or 01.
For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss address is accessed
first followed by the remaining three longwords that are accessed by incrementing the longword address
in a modulo-16 fashion as shown below:
if miss address[3:2] = 00
fetch sequence = 0x0, 0x4, 0x8, 0xC
if miss address[3:2] = 01
fetch sequence = 0x4, 0x8, 0xC, 0x0
if miss address[3:2] = 10
fetch sequence = 0x8, 0xC, 0x0, 0x4
if miss address[3:2] = 11
fetch sequence = 0xC, 0x0, 0x4, 0x8
After an external fetch has been initiated and the data is loaded into the line-fill buffer, the cache maintains
a special most-recently-used indicator that tracks the contents of the associated line-fill buffer versus its
corresponding cache location. At the time of the miss, the hardware indicator is set, marking the line-fill
buffer as most recently used. If a subsequent access occurs to the cache location defined by bits [12:4] (or
bits [11:4] for split configurations of the fill buffer address), the data in the cache memory array is now
most recently used, so the hardware indicator is cleared. In all cases, the indicator defines whether the
contents of the line-fill buffer or the memory data array are most recently used. At the time of the next
cache miss, the contents of the line-fill buffer are written into the memory array if the entire line is present,
and the line-fill buffer data is most recently used compared to the memory array.
Generally, longword references are used for sequential instruction fetches. If the processor branches to an
odd word address, a word-sized instruction fetch is generated.
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Cache
For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts of
non-cacheable references under control of CACR[CEIB]. With this bit set, a non-cacheable instruction
fetch is processed, as defined by Table 5-7. For this condition, the line-fill buffer is loaded and subsequent
references can hit in the buffer, but the data is never loaded into the memory array.
Table 5-7 shows the relationship between CACR bits CENB and CEIB and the type of instruction fetch.
Table 5-7. Instruction Cache Operation as Defined by CACR
CACR
[CENB]
CACR
[CEIB]
Type of
Instruction Fetch
0
0
N/A
Cache is completely disabled; all instruction fetches
are word or longword in size.
0
1
N/A
All instruction fetches are word or longword in size
1
X
Cacheable
1
0
Non-cacheable
All instruction fetches are word or longword in size,
and not loaded into the line-fill buffer
1
1
Non-cacheable
Instruction fetch size is defined by Table 5-6 and
loaded into the line-fill buffer, but are never written into
the memory array.
Description
Fetch size is defined by Table 5-6 and contents of the
line-fill buffer can be written into the memory array
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Chapter 6
Static RAM (SRAM)
6.1
Introduction
This chapter describes the on-chip static RAM (SRAM) implementation, including general operations,
configuration, and initialization. It also provides information and examples showing how to minimize
power consumption when using the SRAM.
6.1.1
Overview
The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a
single cycle. The location of the memory block can be specified to any 0-modulo-128K address within the
256-Mbyte address space (0x8000_0000 – 0x8FFF_FFFF). The memory is ideal for storing critical code
or data structures or for use as the system stack. Because the SRAM module is physically connected to the
processor's high-speed local bus, it can service processor-initiated accesses or memory-referencing
commands from the debug module.
Depending on configuration information, processor references may be sent to the cache and the SRAM
block simultaneously. If the reference maps into the region defined by the SRAM, the SRAM provides the
data back to the processor, and the cache data is discarded. Accesses from the SRAM module are not
cached.
The SRAM is dual-ported to provideaccess for any of the bus masters via the SRAM backdoor on the
crossbar switch. The SRAM is partitioned into two physical memory arrays to allow simultaneous access
to arrays by the processor core and another bus master. For more information on arbitration between
multiple masters accessing the SRAM, see .”
6.1.2
Features
The major features includes:
• One 128 Kbyte SRAM
• Single-cycle access
• Physically located on the processor's high-speed local bus
• Memory location programmable on any 0-modulo-128 Kbyte address
• Byte, word, and longword address capabilities
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Static RAM (SRAM)
6.2
Memory Map/Register Description
The SRAM programming model shown in Table 6-1 includes a description of the SRAM base address
register (RAMBAR), SRAM initialization, and power management.
Table 6-1. SRAM Programming Model
Rc[11:0]1
Width
Access
(bits)
Register
Reset Value
Written
Section/Page
w/ MOVEC
Supervisor Access Only Registers
0xC05
1
RAM Base Address Register (RAMBAR)
32
R/W
See Section
Yes
6.2.1/6-2
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see Chapter 32, “Debug Module.”
6.2.1
SRAM Base Address Register (RAMBAR)
The configuration information in the SRAM base-address register (RAMBAR) controls the operation of
the SRAM module.
• The RAMBAR holds the SRAM base address. The MOVEC instruction provides write-only access
to this register.
• The RAMBAR can be read or written from the debug module.
• All undefined bits in the register are reserved. These bits are ignored during writes to the
RAMBAR and return zeroes when read from the debug module.
• A reset clears the RAMBAR’s priority, backdoor write-protect, and valid bits, and sets the
backdoor enable bit. This enables the backdoor port and invalidates the processor port to the
SRAM (The RAMBAR must be initialized before the core can access the SRAM.) All other bits
are unaffected.
NOTE
The only applicable address ranges for the SRAM module’s base address are
0x8000_0000 – 0x8FFE_0000. The adress must be 0-modulo-128 K. Set
the RAMBAR register appropriately.
By default, the RAMBAR is invalid, but the backdoor is enabled. In this
state, any core accesses to the SRAM are routed through the backdoor.
Therefore, the SRAM is accessible by the core, but it does not have a
single-cycle access time. To ensure that the core has single-cycle access to
the SRAM, set the RAMBAR[V] bit.
Any access within the memory range allocated for the on-chip SRAM
(0x8000_0000-0x8FFF_FFFF) hits in the SRAM even if the address is
beyond the defined size for the SRAM. This creates address aliasing for the
on-chip SRAM memory. For example, writes to addresses 0x8000_0000
and 0x8002_0000 modify the same memory location. System software
should ensure SRAM address pointers do not exceed the SRAM size to
prevent unwanted overwriting of SRAM.
MCF52277 Reference Manual, Rev 2
6-2
Freescale Semiconductor
Static RAM (SRAM)
The RAMBAR contains several control fields. These fields are shown in Figure 6-1.
Rc[11:0]: 0x0C05 (RAMBAR)
Access: User write-only
Debug read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
R
0 0 0 0 0
BA
W
11
10
9
8
PRIU PRIL BDE WP
Reset U U U U U U U U U U U U U U U 0 0 0 0 0
0
0
1
U
7
0
6
5
4
3
2
1
BWP C/I SC SD UC UD V
0
0
U
U
U
U
U
Figure 6-1. SRAM Base Address Register (RAMBAR)
Table 6-2. RAMBAR Field Descriptions
Field
Description
31–17
BA
Base Address. Defines the 0-modulo-128K base address of the SRAM module. By programming this field,
the SRAM may be located on any 128-Kbyte boundary within the processor’s 256-Mbyte address space.
For proper operation, the base address must be set to between 0x8000_0000 and 0x8FFE_0000.
16–12
Reserved, must be cleared.
11–10
PRIU
PRIL
Priority Bit. PRIU determines if the SRAM backdoor or CPU has priority in the upper 128K bank of memory.
PRIL determines if the SRAM backdoor or CPU has priority in the lower 128K bank of memory. If a bit is
set, the CPU has priority. If a bit is cleared, the SRAM backdoor has priority. Priority is determined according
to the following table:
PRIU,PRIL
Upper Bank Priority
Lower Bank Priority
00
01
10
11
SRAM Backdoor
SRAM Backdoor
CPU
CPU
SRAM Backdoor
CPU
SRAM Backdoor
CPU
Note: The recommended setting (maximum performance) for the priority bits is 00.
9
BDE
Backdoor Enable. Allows access by non-core bus masters via the SRAM backdoor on the crossbar switch
0 Non-core crossbar switch master access to memory is disabled.
1 Non-core crossbar switch master access to memory is enabled.
8
WP
Write Protect. Allows only read accesses to the SRAM. When this bit is set, any attempted write access
from the core generates an access error exception to the ColdFire processor core.
0 Allows core reaought d and write accesses to the SRAM module
1 Allows only core read accesses to the SRAM module
Note: This bit does not affect non-core write accesses.
7
6
BWP
Reserved, must be cleared.
Backdoor Write Protect. Allows only read accesses from the non-core bus masters. When this bit is set, any
attempted write access from the non-core bus masters on the backdoor terminates the bus transfer with an
access error.
0 Allows read and write accesses to the SRAM module from non-core masters.
1 Allows only read accesses to the SRAM module from non-core masters.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
0
6-3
0
Static RAM (SRAM)
Table 6-2. RAMBAR Field Descriptions (continued)
Field
Description
Address Space Masks (ASn). These five bit fields allow types of accesses to be masked or inhibited from
5–1
C/I, SC, SD, UC, accessing the SRAM module. The address space mask bits are:
UD
C/I = CPU space/interrupt acknowledge cycle mask
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each address space bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address space is made, it
is inhibited from accessing the SRAM module and is processed like any other non-SRAM reference.
These bits do not affect accesses by non-core bus masters using the SRAM backdoor port in any manner.
These bits are useful for power management as detailed in Section 6.3.2, “Power Management.” In most
applications, the C/I bit is set
0
V
6.3
Valid. When set, this bit enables the SRAM module; otherwise, the module is disabled. A hardware reset
clears this bit.
0 Processor accesses of the SRAM are masked
1 Processor accesses of the SRAM are enabled
Initialization/Application Information
After a hardware reset, the SRAM module contents are undefined. The valid bit of the RAMBAR is
cleared, disabling the processor port into the memory. RAMBAR[BDE] is set, enabling the system
backdoor port into the memory. If the SRAM requires initialization with instructions or data, perform the
following steps:
1. Load the RAMBAR, mapping the SRAM module to the desired location within the address space.
2. Read the source data and write it to the SRAM. Various instructions support this function,
including memory-to-memory move instructions, or the MOVEM opcode. The MOVEM
instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this
opcode generally provides maximum performance.
3. After the data loads into the SRAM, it may be appropriate to load a revised value into the
RAMBAR with a new set of attributes. These attributes consist of the write-protect and address
space mask fields.
The ColdFire processor or an external debugger using the debug module can perform these initialization
functions.
6.3.1
SRAM Initialization Code
The following code segment describes how to initialize the SRAM. The code sets the base address of the
SRAM at 0x8000_0000 and initializes the SRAM to zeros.
RAMBASE
EQU 0x80000000
RAMVALID
EQU 0x00000001
;set this variable to 0x80000000
MCF52277 Reference Manual, Rev 2
6-4
Freescale Semiconductor
Static RAM (SRAM)
move.l
#RAMBASE+RAMVALID,D0
;load RAMBASE + valid bit into D0.
movec.l
D0, RAMBAR
;load RAMBAR and enable SRAM
The following loop initializes the entire SRAM to zero:
lea.l
RAMBASE,A0
;load pointer to SRAM
move.l
#32768,D0
;load loop counter into D0 (SRAM size/4)
clr.l
(A0)+
;clear 4 bytes of SRAM
clr.l
(A0)+
;clear 4 bytes of SRAM
clr.l
(A0)+
;clear 4 bytes of SRAM
clr.l
(A0)+
;clear 4 bytes of SRAM
subq.l
#4,D0
;decrement loop counter
bne.b
SRAM_INIT_LOOP
;if done, then exit; else continue looping
SRAM_INIT_LOOP:
6.3.2
Power Management
As noted previously, depending on the RAMBAR-defined configuration, instruction fetch and operand
read accesses may be sent to the SRAM and cache simultaneously. If the access maps to the SRAM
module, it sources the read data and the cache access is discarded. If the SRAM is used only for data
operands, setting the ASn bits associated with instruction fetches can decrease power dissipation.
Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power
dissipation. Table 6-3 shows examples of typical RAMBAR settings.
Table 6-3. Typical RAMBAR Setting Examples
Data Contained in SRAM
RAMBAR[7:0]
Instruction Only
0x2B
Data Only
0x35
Instructions and Data
0x21
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Freescale Semiconductor
6-5
Static RAM (SRAM)
MCF52277 Reference Manual, Rev 2
6-6
Freescale Semiconductor
Chapter 7
Clock Module
7.1
Introduction
The clock module allows the device to be configured for one of several clocking methods. Clocking modes
include internal phase-locked loop (PLL) clocking with an external clock reference or an external crystal
reference supported by an internal crystal amplifier. The PLL can also be disabled, and an external
oscillator can directly clock the device. The clock module contains:
• Crystal amplifier and oscillator (OSC)
• Phase-locked loop (PLL)
• Status and control registers
• Control logic
NOTE
Throughout this manual, fsys refers to the core frequency and fsys/2 refers to
the internal bus frequency.
Figure 7-1 is a high-level representation of clock connections. The exact functionality of the blocks is not
illustrated (SBF controls many configuration options, clocks to the SDRAMC controller are disabled when
the device is in limp mode, and the clocks to individual modules may be disabled via the peripheral power
management registers as described in Chapter 8, “Power Management”).
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
7-1
Clock Module
FB_A19 (when
BOOTMODE = 10) or
MISCCR[LIMP]
V2 ColdFire Core
Clock Module
SRAM/Cache
PCR
EXTAL
fvco
PCR
[PFDR]
fref
FB_A16 (when
BOOTMOD = 10)
OUTDIV1
0
1
fsys
OUTDIV2
fsys/2
OUTDIV3
fsys
OUTDIV5
Limp Mode
Clock
÷2
FlexBus
FB_CLK
SDRAMC
SD_CLK
SD_CLK
RTC_EXTAL
LCD
Touchscreen
PWM
PIT
DMA Timers
DSPI
CDR[SSIDIV]
Serial Boot
Facility
Must be 60MHz if used
as USB clock source
CDR[LPDIV]
RTC_XTAL
Oscillator
BDM
eDMA
Peripheral Bus Clock
Oscillator
XTAL
DSPI_SCK
UART
I2C
GPIO
FlexCAN
CANCTRL[CLKSRC]
Real Time Clock
MISCCR[RTCSRC]
SSI
SSICLKIN
MISCCR
[SSISRC]
USB OTG
USBCLKIN
MISCCR[USBSRC]
Notes:
1 The output frequency of OUTDIV2 must equal the output frequency of OUTDIV1 ÷ 2.
2
3
4
5
6
7
The output frequency of OUTDIV3 must equal the output frequency of OUTDIV1.
The output frequency of OUTDIV5 must be 60MHz if it is used as the USB clock source.
The SDRAMC module is disabled in limp mode. The USB controller is essentially disabled, as well.
However, it is able to capture a wake-up event to bring the device out of limp mode.
The SDRAMC, real time clock, SSI, and USB contain some logic that uses the fsys/2 clock, in addition
to the module-specific clock.
When loading boot code via the SBF, the device is clocked by the main oscillator (fref).
The LCD controller is also given a 32 Hz clock for the cursor blink counter.
Figure 7-1. Device Clock Connections
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
Clock Module
7.1.1
Block Diagram
Figure 7-2 shows the clock module block diagram.
RTC_XTAL
OSC
To Real-Time
Clock
RTC_EXTAL
XTAL
EXTAL
Crystal
Ref. Mode
Phase/Frequency
Detector (PFD)
OSC
Loop Filter
External
Ref. Mode
Feedback Divider
(P)
Voltage-Controlled
Oscillator (VCO)
VCO Clock
Frequency
Lock
Detect
Output Dividers
Bus
Interface
Reset Config
Signals
(÷2 to ÷16)
PLL
Registers
Output Clocks
Figure 7-2. Clock Module Diagram
7.1.2
Features
Features of the clock module include:
• 16–66.66 MHz input clock frequency
• Programmable frequency multiplication factor settings generating voltage-controlled oscillator
(VCO) frequencies from 300 – 540 MHz, resulting in a core frequency of 37.5 MHz (fvco ÷ 8) to
166.67 MHz (maximum rated frequency).
• Four user-programmable output dividers
— Each post-VCO divider can be programmed to divide-by-2 through divide-by-16. (There are
some dependencies of the divider settings. See Section 7.2.1, “PLL Control Register (PCR)”,
for details.) The post-VCO dividers can be enabled asynchronously or disabled via register.
— Allows glitch-free, dynamic switching of the output divider
• Provides signals indicating when the PLL has acquired lock and lost lock
• 16 – 40 MHz reference crystal oscillator
• Support for low-power modes
• Direct clocking of system by input clock, bypassing the PLL
• Loss-of-lock reset
• Reference crystal oscillator for the real time clock (RTC) module. Input clock used is
programmable within the RTC.
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Freescale Semiconductor
7-3
Clock Module
7.1.3
Modes of Operation
The PLL operational mode must be configured during reset. The reset configuration pins must be driven
to the appropriate state for the desired mode from the time RSTOUT asserts until it negates. Refer to
Chapter 9, “Chip Configuration Module (CCM).”
The clock module can operate in normal PLL mode with crystal reference, normal PLL mode with external
reference, and input-clock limp mode.
7.1.3.1
Normal PLL Mode with Crystal Reference
In normal mode with a crystal reference, the PLL receives an input clock frequency from the crystal
oscillator circuit and multiplies the frequency to create the PLL output clock. It can synthesize frequencies
ranging from 4 – 34x the input frequency. The user must supply a crystal oscillator within the appropriate
input frequency range, the crystal manufacturer’s recommended external support circuitry, and short signal
route from the device to the crystal.
7.1.3.2
Normal PLL Mode with External Reference
This second mode is the same as Section 7.1.3.1, “Normal PLL Mode with Crystal Reference,” except
EXTAL is driven by an external clock generator rather than a crystal oscillator. However, the input
frequency range is the same as the crystal reference. To enter normal mode with external clock generator
reference, the PLL configuration must be set at reset by overriding the default reset configuration. See
Chapter 9, “Chip Configuration Module (CCM),” for details on setting the device for external reference
(oscillator bypass mode).
7.1.3.3
Input Clock (Limp) Mode
Through parallel RCON, serial boot, or the MISCCR[LIMP] bit, the device may be placed into a
low-frequency limp mode, in which the PLL is bypassed and the device runs from a factor of the input
clock (EXTAL). In this mode, EXTAL feeds a 5-bit programmable counter that divides the input clock by
2n, where n is the value of the programmable counter field, MISCCR[LPDIV]. For more information on
programming the divider, see Chapter 8, “Power Management.” The programmed value of the divider may
be changed without glitches or otherwise negative affects to the system.
While in this mode, the PLL is placed in bypass mode to reduce overall system power consumption. A 2:1
ratio is maintained between the core and the primary bus clock, while a 1:1 ratio is maintained between
FB_CLK and the internal bus clock. Because they do not function at speeds as low as the minimum
input-clock frequency, the SDRAM controller are not functional in limp mode. The USB controller is
effectively disabled as well. However, it is able to capture a wake-up event to release the processor from
limp mode.
When switching from limp mode to normal functional mode, you must ensure that any peripheral
transactions in progress are allowed to complete to avoid data loss or corruption.
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
Clock Module
Entering limp mode via the MISCCR[LIMP] bit requires a special procedure for the SDRAM module. As
noted above, the SDRAM controller is disabled in limp mode, so follow these two critical steps before
setting the MISCCR[LIMP] bit:
1. Code execution must be transferred to another memory resource. Primary options are whatever
memory device is attached to the FlexBus boot chip-select or on-chip SRAM (but not the CPU
cache, as it may have to be flushed upon limp mode entrance or exit).
2. The SDRAM controller must be placed in self-refresh mode to avoid data loss while the SDRAMC
shuts down.
7.1.3.4
Low-power Mode Operation
This subsection describes the clock module operation in low-power and halted modes of operation.
Low-power modes are described in Chapter 8, “Power Management.” Table 7-1 shows the clock module
operation in low-power modes.
Table 7-1. Clock Module Operation in Low-power Modes
Low-power Mode
Clock Operation
Mode Exit
Wait
Clocks sent to peripheral modules only
Clock module does not cause exit, but normal
clocking resumes upon mode exit
Doze
Clocks sent to peripheral modules only
Clock module does not cause exit, but normal
clocking resumes upon mode exit
Stop
All system clocks disabled
Clock module does not cause exit, but clock
sources are re-enabled and normal clocking
resumes upon mode exit
Halted
Normal
Clock module does not cause exit
In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the core, and
SRAM are stopped. Each module can disable its clock locally at the module level.
In stop mode, all system clocks are disabled (except the real-time clock that continues to run via its external
clock). There are several options for enabling or disabling the PLL or crystal oscillator in stop mode,
compromising between stop mode current and wake-up recovery time. The PLL can be disabled in stop
mode, but requires a wake-up period before it relocks. The oscillator can also be disabled during stop
mode, but it requires a wake-up period to restart.
When the PLL is enabled in stop mode (LPCR[STPMD] = 00), the external FB_CLK signal can support
systems using FB_CLK as the clock source. For more information about operating the PLL in stop mode,
see Section 8.2.5, “Low-Power Control Register (LPCR).”
There is also a fast wake-up option for quickly enabling the system clocks during stop recovery
(LPCR[FWKUP]). This eliminates the wake-up recovery time but at the risk of sending a potentially
unstable clock to the system.
7.2
Memory Map/Register Definition
The PLL programming model consists of the following:
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
7-5
Clock Module
Table 7-2. PLL Memory Map
Address
Width
(bits)
Register
Access Reset Value
Section/Page
0xFC0C_0000 PLL Control Register (PCR)
32
R/W
See Section
7.2.1/7-6
0xFC0C_0004 PLL Status Register (PSR)
32
R/W
0x0000_0000
7.2.2/7-8
7.2.1
PLL Control Register (PCR)
The PCR register controls the feedback and output dividers for generating the core and bus clocks. For
details on altering these values after reset, see Section 7.3.1, “PLL Frequency Multiplication Factor
Select.”
NOTE
A single longword (32-bit) write to the PCR register is required. If
back-to-back word or longword writes are attempted, some of the clocks in
the system change frequency before others, which can cause the device to
hang.
Address: 0xFC0C_0000 (PCR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset
PFDR
See Note
0 1 1 1
0 1 1 1
OUTDIV5
See Note
0 0 0 0
8
OUTDIV3
7
6
5
4
OUTDIV2
3
2
1
0
OUTDIV1
0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0
Note: The reset values of PFDR and OUTDIV5 depend on the boot configuration mode. When
BOOTMOD[1:0] = 00, 01, or 10, PFDR resets to 0x1E and OUTDIV resets to 0x7. If
BOOTMOD[1:0] = 11, PFDR and OUTDIV5 reset to the value of SBF_RCON[7:0] and
SBF_RCON[9:8], respectively, specified by serial boot.
Figure 7-3. PLL Control Register (PCR)
Table 7-3. PCR Field Descriptions
Field
31–24
PFDR
Description
Feedback divider for setting the VCO frequency. Valid values range from 4 (0x4) to 34 (0x22). Other settings are
invalid and stable operation is not guaranteed. The reset value depends on the selected chip configuration. See
Chapter 9, “Chip Configuration Module (CCM),” for more information.
f VCO = f REF × PFDR
Eqn. 7-1
where fREF is the PLL input frequency from the internal oscillator or EXTAL clock source (defined by the selected
chip configuration).
23–20
Reserved, must be cleared.
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
Clock Module
Table 7-3. PCR Field Descriptions (continued)
Field
Description
19–16 Output divider for generating the USB clock frequency. The divider is the value of this bit field plus 1. The reset value
OUTDIV5 depends on the selected chip configuration. See Chapter 9, “Chip Configuration Module (CCM),” for more
information. A value of zero disables this clock.
Note: The OUTDIV5 resulting frequency must be 60 MHz if used as the USB clock source.
f VCO
f USB = -----------------------------------OUTDIV5 + 1
15–12
Eqn. 7-2
Reserved, must be cleared.
11–8
Output divider for generating the SDRAM clock frequency. The divider is the value of this bit field plus 1. The reset
OUTDIV3 value depends on the selected chip configuration. See Chapter 9, “Chip Configuration Module (CCM),” for more
information. A value of zero disables this clock.
Note: The OUTDIV3 divider value must equal the OUTDIV1 divider.
f VCO
f SDRAMC = f SYS = -----------------------------------OUTDIV3 + 1
Eqn. 7-3
7–4
Output divider for generating the internal bus clock frequency, including FlexBus clock (FB_CLK). The divider is the
OUTDIV2 value of this bit field plus one. The reset value depends on the chip configuration selected. See Chapter 9, “Chip
Configuration Module (CCM),” for more information. A value of zero disables this clock.
Note: The OUTDIV2 divider value must be twice the OUTDIV1 divider. For example, if OUTDIV1 equals 0001, then
OUTDIV2 equals 0011.
f VCO
f SYS
- = -----------------------------------f SYS/2 = --------2
OUTDIV2 + 1
Eqn. 7-4
3–0
Output divider for generating the CPU clock frequency. The divider is the value of this bit field plus 1. The reset value
OUTDIV1 depends on the selected chip configuration. See Chapter 9, “Chip Configuration Module (CCM),” for more
information. A value of zero disables this clock.
f VCO
f SYS = -----------------------------------OUTDIV1 + 1
Eqn. 7-5
Note: The maximum value restrictions on this field depend on the setting of OUTDIV2 and OUTDIV3, as shown
below:
OUTDIV3
(FB_CLK)
OUTDIV2
(Internal
Peripheral Clock)
OUTDIV1
Maximum
8 × OUTDIV1 + 7
(CPU freq ÷ 8)
—
0001
4 × OUTDIV1 + 3
(CPU freq ÷ 4)
—
0011
0
(Disabled)
≠0
(Enabled)
0111
0
(Disabled)
0
(Disabled)
1111
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Freescale Semiconductor
7-7
Clock Module
7.2.2
PLL Status Register (PSR)
The PSR register enables loss-of-lock reset and interrupt, and also indicates the PLL lock status.
Address: 0xFC0C_0004 (PSR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3
2
LOL
RE
LOL
IRQ
0
0
1
0
LOCK LOCKS
0
0
Figure 7-4. PLL Status Register (PSR)
Table 7-4. PSR Field Descriptions
Field
31–4
Description
Reserved, must be cleared.
3
LOLRE
PLL loss of lock reset enable. Because reset clears the PSR register, if this bit is set and a loss-of-lock occurs, the
user must read the reset status register (RSR) to determine a loss-of-lock condition occurred. See Chapter 11,
“Reset Controller Module,” for more details on RSR.
0 Loss of lock does not generate a reset.
1 Loss of lock generates a reset to the device.
2
LOLIRQ
PLL loss-of-lock interrupt enable. Enables an interrupt request to generate when the PLL loses lock.
0 Loss-of-lock does not generate an interrupt request.
1 Loss-of-lock generates an interrupt request.
1
LOCK
0
LOCKS
7.3
PLL lock status. Indicates a locked PLL. See Section 7.3.2, “Lock Conditions,” for more details.
0 PLL is not locked.
1 PLL is locked.
PLL lost lock. Indicates that the PLL has lost lock. If the PFDR field changes or if an unexpected loss-of-lock condition
occurs, this bit is set. This bit is sticky and the user must clear it before the PLL can write the register again.
0 PLL has not lost lock.
1 PLL has lost lock.
Functional Description
This subsection provides a functional description of the clock module.
7.3.1
PLL Frequency Multiplication Factor Select
The frequency multiplication factor of the PLL is defined by the feedback divider and output dividers. An
example equation for the core frequency is given below:
PCR [ PFDR ]
f SYS = f REF × ⎛ ------------------------------------------------------⎞
⎝ PCR [ OUTDIV1 ] + 1⎠
Eqn. 7-6
where fsys is the clock frequency of the ColdFire core and fREF is the PLL clock source as shown in
Figure 7-1. The allowable range of values for the PFDR is 4 to 34 and OUTDIVn is 1 to 15. However,
PFDR must also be selected such that the VCO frequency (fREF × PCR[PFDR]) is of the
range 300 – 540 MHz. The other clocks on the processor are configurable in a similar fashion. However,
there are various dependencies. See Section 7.2.1, “PLL Control Register (PCR),” for details.
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
Clock Module
The PCR[OUTDIVn] fields can be changed during normal operation or when the device is in limp mode.
However, PCR[PFDR] can only be altered during limp mode. After a new value is written to the PCR, the
PLL synchronizes the new value of the PCR with the VCO clock domain. Then, the transition from the old
divider value to the new divider value takes place, such that the PLL output clocks remain glitch free.
During the adjustment to the new divider value, a PLL output clock may experience an intermediate
transition while the divider values are being synchronized. Following the transition period, all output
clocks begin toggling at the new divider values simultaneously. The transition from the old divider value
to the new divider value takes no more than 100 ns. Because the output divider transition takes a period of
time to change, the PCR may not be written back-to-back without waiting 100 ns between writes.
7.3.2
Lock Conditions
The lock-detect logic monitors the reference frequency and the PLL feedback frequency to determine
when frequency lock has been achieved. Phase lock is inferred by the frequency relationship, but is not
guaranteed. The PLL lock status reflects in the PSR[LOCK] status bit. The lock-detect function uses two
counters clocked by the reference and PLL feedback, respectively. When the reference counter has counted
N cycles, the feedback counter is compared. If the feedback counter has also counted N cycles, the process
is repeated for N + K counts. Then, if the two counters counts continue to match, the lock criteria relaxes
by one count, and the system is notified that the PLL has achieved frequency lock by setting the
PSR[LOCK] bit.
After detection of lock, the lock circuitry continues monitoring the reference and feedback frequencies
using the alternate count and compare process. If the counters do not match at any comparison time, then
the PSR[LOCK] and PSR[LOCKS] status bits are cleared to indicate the PLL has lost lock. At this point,
the lock criteria tightens and the lock detect process repeats. The alternate count sequences prevent false
lock detects due to frequency aliasing while the PLL tries to lock. Alternating between a tight and relaxed
lock criteria prevents the lock detect function from randomly toggling between locked and not locked
status due to phase sensitivities.
In PLL bypass mode, the PSR[LOCK] bit is set 16 clock cycles after reset as described above. In this case,
the signal does not indicate the PLL has locked to the input reference, but the bypass clock is present on
the output. In bypass mode, no PLL lock exists.
7.3.3
Loss-of-Lock
When the PLL loses lock the PSR[LOCKS] status bit is set. If the PFDR is changed, or if an unexpected
loss of lock condition occurs, the LOCKS status bit is set. While the PLL is in an unlocked condition, the
system clocks continue to be sourced from the PLL as the PLL attempts to relock. Therefore, during the
re-locking process, the system-clock frequency is not well defined and may exceed the maximum system
frequency, violating the system clock timing specifications. Due to this condition, using the loss-of-lock
reset functionality as described in Section 7.3.3.1, “Loss of Lock Reset Request,” is recommended. After
the PLL has re-locked, the PLL does not update the PSR[LOCKS] status bit. The LOCKS status bit is
sticky, and the user must clear it before the PLL can write the register again.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
7-9
Clock Module
7.3.3.1
Loss of Lock Reset Request
The PLL provides the ability to assert reset when a loss-of-lock condition occurs by programming the
PSR[LOLRE] bit. Because the PSR[LOCK, LOCKS] bits are cleared after reset, the reset status register
(RSR) must be read to determine a loss of lock condition occurred. See Chapter 11, “Reset Controller
Module,” for more information on the RSR register. To exit reset in PLL mode, the reference must be
present and the PLL must acquire lock. In PLL bypass mode, the PLL cannot lock; therefore, a loss of lock
condition cannot occur, and LOLRE has no affect.
7.3.3.2
Loss of Lock Interrupt Request
By programming the PSR[LOLIRQ] bit, the PLL provides the ability to request an interrupt when a
loss-of-lock condition occurs. This bit is sticky, and remains asserted until the user clears the
PSR[LOCKS] status bit. LOLIRQ provides information to the lock detect logic to let it know if an interrupt
should be generated upon loss-of-lock. In PLL bypass mode, the PLL cannot lock; therefore, a loss-of-lock
condition cannot occur, and the LOLIRQ has no affect.
7.3.4
System Clock Modes
The system clock source is determined during reset. By default the PLL is placed in crystal-reference mode
and generates a core frequency of 10 times the input clock (internal bus 5x and USB clock 3.75x). The
BOOTMOD pins can override the default mode. See Chapter 9, “Chip Configuration Module (CCM),” for
more information on default configuration, as well as overwriting these defaults during reset.
Table 7-5 shows some of the various clocking scenarios offered on the processor. USB_CLKIN in the USB
OTG column indicates that the USB On-the-Go module receives its clock from the USB_CLKIN signal
rather than the PLL output.
Table 7-5. MCF52277 Clocking Scenarios (MHz)
Input Reference/
Crystal Frequency
PCR[PFDR]
OUTDIV1
+1
VCO
ColdFire
Core
Internal Bus
OUTDIV5
(Core ÷ 2)1
USB OTG
Default
(BOOTMOD = 00, 01)
fEXTAL
(User-Defined)
30
fEXTAL × 30
3
fEXTAL × 10
fEXTAL × 5
8
fEXTAL × 3.75
166.67
83.33
—
USB_CLKIN
160
80
8
60
Parallel Boot with PLL Enabled
(BOOTMOD = 10 and FB_A19 = 0)
16.67
30
500
3
16
30
480
MCF52277 Reference Manual, Rev 2
7-10
Freescale Semiconductor
Clock Module
Table 7-5. MCF52277 Clocking Scenarios (MHz) (continued)
Input Reference/
Crystal Frequency
PCR[PFDR]
VCO
OUTDIV1
+1
ColdFire
Core
Internal Bus
OUTDIV5
(Core ÷ 2)1
USB OTG
Parallel Boot into Limp Mode
(BOOTMOD = 10 and FB_A19 = 1)
User-Defined
User-Defined
500
166.67
83.33
—
USB_CLKIN
480
160
80
8
60
140
70
7
60
360
120
60
6
60
300
100
50
5
60
420
3
Serial Boot
(BOOTMOD = 11)
User-Defined
1
SBF_RCON
[9:8]
500
166.67
83.33
—
USB_CLKIN
480
160
80
8
60
140
70
7
60
360
120
60
6
60
300
100
50
5
60
420
3
(OUTDIV2 + 1) must equal 2 × (OUTDIV1 + 1).
7.3.5
Clock Operation During Reset
This section describes the PLL reset operation. Power-on reset and normal reset are described.
7.3.5.1
Power-On Reset (POR)
After VDD_PLL and the input clock are within specification, the PLL is held in reset for at least ten input
clock cycles to initialize the PLL. The reset configuration signals are used to select the multiply factor of
the PLL and the reset state of the PLL registers. While in reset, the PLL input clock is output to the device.
After RESET de-asserts, PLL output clocks generate; however, until the PSR[LOCK] bit is set, the PLL
output clock frequencies are not stable and within specification. When this bit is set, the PLL is in
frequency lock.
7.3.5.2
External Reset
When RESET asserts, the PLL input clock outputs to the device, and the PLL does not begin acquiring
lock until RESET is negated. The PSR[LOCK] bit is cleared and remains cleared while the PLL is
acquiring lock.
CAUTION
When running in an unlocked state, the clocks the PLL generate are not
guaranteed to be stable and may exceed the maximum specified frequency.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
7-11
Clock Module
MCF52277 Reference Manual, Rev 2
7-12
Freescale Semiconductor
Chapter 8
Power Management
8.1
Introduction
This chapter explains the low-power operation of the device.
8.1.1
Features
These features support low-power operation:
• Four operation modes: run, wait, doze, and stop
• Ability to shut down most peripherals independently
• Ability to shut down clocks to most peripherals independently
• Ability to run the device in low-frequency limp mode
• Ability to shut down the external FB_CLK pin
8.2
Memory Map/Register Definition
The power management programming model consists of registers from the SCM and CCM memory space:
Table 8-1. Power Management Memory Map
Address
Register
Width
(bits)
Access Reset Value
Section/Page
Supervisor Access Only Registers1
0xFC04_0013 Wakeup Control Register (WCR)
8
R/W
0x00
8.2.1/8-2
0xFC04_002C Peripheral Power Management Set Register (PPMSR)
8
W
0x00
8.2.2/8-3
0xFC04_002D Peripheral Power Management Clear Register (PPMCR)
8
W
0x00
8.2.3/8-4
0xFC04_0030 Peripheral Power Management High Register (PPMHR)
32
R/W
0x0000_0000
8.2.4/8-4
0xFC04_0034 Peripheral Power Management Low Register (PPMLR)
32
R/W
0x0000_0000
8.2.4/8-4
0xFC0A_0007 Low-Power Control Register (LPCR)
8
R/W
0x00
8.2.5/8-7
16
R/W
See Section
10.3.4/10-8
16
R/W
0x0001
10.3.5/10-10
0xFC0A_0010 Miscellaneous Control Register
0xFC0A_0012 Clock Divider Register (CDR)2
1
2
(MISCCR)2
User access to supervisor only address locations have no effect and result in a bus error
The MISCCR and CDR registers are described in Chapter 9, “Chip Configuration Module (CCM).”
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
8-1
Power Management
8.2.1
Wake-up Control Register (WCR)
Implementation of low-power stop mode and exit from a low-power mode via an interrupt requires
communication between the core and logic associated with the interrupt controller. The WCR enables
entry into low-power modes and includes the interrupt level setting needed to exit a low-power mode.
NOTE
The setting of the low-power mode select field, WCR[LPMD], determines
which low-power mode the device enters when a STOP instruction is issued.
Sequence of operations generally needed to enable this functionality:
1. The WCR register is programmed, setting the ENBWCR bit and the desired interrupt priority level.
2. At the appropriate time, the processor executes the privileged STOP instruction. After the
processor stops execution, it asserts a specific processor status (PST) encoding. Issuing the STOP
instruction when the WCR[ENBWCR] is set causes the SCM to enter the mode specified in
WCR[LPMD].
3. The low power mode control logic processes the entry into a low power mode, and the appropriate
clocks (usually those related to the high-speed processor core) are disabled.
4. After entering the low-power mode, the interrupt controller enables a combinational logic path that
evaluates any unmasked interrupt requests. The device waits for an event to generate an interrupt
request with a priority level greater than the value programmed in WCR[PRILVL].
5. After an appropriately high interrupt request level arrives, the interrupt controller signals its
presence, and the SCM responds by asserting the request to exit low-power mode.
6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.
7. With the processor clocks enabled, the core processes the pending interrupt request.
Address: 0xFC04_0013 (WCR)
7
R
Access: Supervisor read/write
6
5
4
0
3
2
1
0
0
ENBWCR
LPMD
PRILVL
W
Reset:
0
0
0
0
0
0
0
0
Figure 8-1. Wake-up Control Register (WCR)
Table 8-2. WCR Field Descriptions
Field
Description
7
Enable low-power mode entry. The mode entered is specified in WCR[LPMD].
ENBWCR 0 Low-power mode entry is disabled
1 Low-power mode entry is enabled.
6
Reserved, must be cleared.
MCF52277 Reference Manual, Rev 2
8-2
Freescale Semiconductor
Power Management
Table 8-2. WCR Field Descriptions (continued)
Field
5–4
LPMD
3
Description
Low-power mode select. Used to select the low-power mode the chip enters after the ColdFire core executes the
STOP instruction. To take effect, write these bits prior to instruction execution. The LPMD bits are readable and
writable in all modes.
00 Run
01 Doze
10 Wait
11 Stop
Note: If WCR[LPMD] is cleared, the device stops executing code upon a STOP instruction. However, no clocks
disable.
Reserved, must be cleared.
2–0
PRILVL
Exit low-power mode interrupt priority level. This field defines the interrupt priority level to exit the low-power mode:
8.2.2
PRILVL
Interrupt Level Needed to Exit Low-Power Mode
000
Any interrupt request exits low-power mode
001
Interrupt request levels [2-7] exit low-power mode
010
Interrupt request levels [3-7] exit low-power mode
011
Interrupt request levels [4-7] exit low-power mode
100
Interrupt request levels [5-7] exit low-power mode
101
Interrupt request levels [6-7] exit low-power mode
11x
Interrupt request level [7] exits low-power mode
Peripheral Power Management Set Register (PPMSR)
The PPMSR register provides a simple mechanism to set a given bit in the PPM{H,L}R registers to disable
the clock for a given peripheral module without needing to perform a read-modify-write on the PPMR.
The data value on a register write causes the corresponding bit in the PPM{H,L}R to be set. The SAMCD
bit provides a global set function forcing the entire contents of the PPMR to set, disabling all peripheral
module clocks. Reads of these registers return all zeroes.
Address: 0xFC04_002C (PPMSR)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset:
Access: Supervisor Write-only
SAMCD
0
0
SMCD
0
0
0
Figure 8-2. Peripheral Power Management Set Register (PPMSR)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
8-3
Power Management
Table 8-3. PPMSR Field Descriptions
Field
7
Description
Reserved, must be cleared.
6
SAMCD
5–0
SMCD
Set all module clock disables.
0 Set only those bits specified in the SMCD field
1 Set all bits in PPMRH and PPMRL, disabling all peripheral clocks
Set module clock disable. Set the corresponding bit in PPM{H,L}R, disabling the peripheral clock.
8.2.3
Peripheral Power Management Clear Register (PPMCR)
The PPMCR register provides a simple mechanism to clear a given bit in the PPMHR & PPMLR registers,
enabling the clock for a given peripheral module without needing to perform a read-modify write on the
PPMR. The data value on a register write causes the corresponding bit in the PPM{H,L}R to be clear. A
value of 64 to 127 (setting the CAMCD bit) provides a global clear function, forcing the entire PPMR
contents to clear, enabling all peripheral module clocks. Reads of these registers return all zeroes.
Address: 0xFC04_002D (PPMCR)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset:
Access: Supervisor Write-only
CAMCD
0
0
CMCD
0
0
0
Figure 8-3. Peripheral Power Management Clear Register (PPMCR)
Table 8-4. PPMCR Field Descriptions
Field
7
6
CAMCD
5–0
CMCD
8.2.4
Description
Reserved, must be cleared.
Clear all module clock disables.
0 Clear only those bits specified in the CMCD field
1 Clear all bits in PPMRH and PPMRL, enabling all peripheral clocks
Clear module clock disable. Clear the corresponding bit in PPMR{H,L}, enabling the peripheral clock.
Peripheral Power Management Registers (PPMHR & PPMLR)
The PPMR registers provide a bit map for controlling the generation of the peripheral clocks for each
decoded address space. Recall each peripheral module is mapped into 16 kByte slots within the memory
map, and a global region is provided in the upper 63 Mbytes of address space (0xFC10_FFFF to
0xFFFF_FFFF). The PPMR registers provide a unique control bit for each address space that defines
whether the module clock for the given space is enabled or disabled.
Because the operation of the crossbar switch and the system control module (SCM) are fundamental to the
operation of the device, the clocks for these modules cannot be disabled.
MCF52277 Reference Manual, Rev 2
8-4
Freescale Semiconductor
Power Management
Using a read-modify-write to this register directly or indirectly through writes to the PPMSR and PPMCR
registers to set/clear individual bits can modify the PPMR individual bits.
Address: 0xFC04_0030 (PPMHR)
R
Access: Supervisor read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
5
4
1
0
W
Reset
R
W
Reset
0
CD47 CD46
0
0
CD44 CD43 CD42 CD41 CD40
0
0
0
0
0
0
7
6
0
0
0
0
CD37 CD36
0
0
3
2
0
0
0
0
16
CD48
CD33 CD32
0
0
Figure 8-4. Peripheral Power Management High Register (PPMHR)
Table 8-5. PPMHR[CDn] Assignments
Slot Number
CDn
Peripheral
32
CD32
PIT 0
33
CD33
PIT 1
36
CD36
PWM
37
CD37
Edge Port
40
CD40
CCM, Reset Controller, Power Management
41
CD41
GPIO Module
42
CD42
Touchscreen Controller
43
CD43
LCD Controller
44
CD44
USB On-the-Go
46
CD46
SDRAM Controller
47
CD47
SSI
48
CD48
PLL
Address: 0xFC04_0034 (PPMLR)
31
R
W
Reset
R
W
Reset
30
29
Access: Supervisor read/write
28
CD31 CD30 CD29 CD28
27
0
26
0
0
0
0
0
15
14
13
12
11
0
0
0
0
0
0
0
0
0
24
23
22
21
CD26 CD25 CD24 CD23 CD22 CD21
0
CD15
25
0
0
10
9
8
0
0
0
0
CD8
0
0
0
0
20
0
0
19
18
17
CD19 CD18 CD17
0
0
0
2
1
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
CD2
CDG
0
0
16
0
0
0
0
0
Figure 8-5. Peripheral Power Management Low Registers (PPMLR)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
8-5
Power Management
Table 8-6. PPMLR[CDn] Assignments
Slot Number
CDn
Peripheral
—
CDG
Global Space
2
CD2
FlexBus
8
CD8
FlexCAN
15
CD15
Real-Time Clock
17
CD17
eDMA Controller
18
CD18
Interrupt Controller 0
19
CD19
Interrupt Controller 1
21
CD21
IACK
22
CD22
I2C
23
CD23
DSPI
24
CD24
UART0
25
CD25
UART1
26
CD26
UART2
28
CD28
DMA Timer 0
29
CD29
DMA Timer 1
30
CD30
DMA Timer 2
31
CD31
DMA Timer 3
Table 8-7. PPMHR & PPMLR Field Descriptions
Field
Description
CDn
Module slot n clock disable.
0 The clock for this module is enabled.
1 The clock for this module is disabled.
CDG
Global space clock disable
0 The clock for global space is enabled.
1 The clock for global space is disabled.
CAUTION
Take extreme caution when setting PPMR[CD40] to disable clocking of the
CCM, reset controller, and power management modules. This may disable
logic to reset the chip and disable the external bus monitor or other logic
contained within these blocks.
MCF52277 Reference Manual, Rev 2
8-6
Freescale Semiconductor
Power Management
8.2.5
Low-Power Control Register (LPCR)
The LPCR register controls chip operation and module operation during low-power modes.
Address: 0xFC0A_0007 (LPCR)
R
7
6
0
0
Access: Supervisor read/write
5
4
FWKUP
3
2
1
0
0
0
0
0
0
0
STPMD
W
Reset:
0
0
0
0
0
Figure 8-6. Low-Power Control Register (LPCR)
Table 8-8. LPCR Field Descriptions
Field
7–6
Description
Reserved, must be cleared.
5
Fast wake-up. Determines whether the system clocks are enabled upon wake-up from stop mode. This bit must be
FWKUP written before execution of the STOP instruction for it to take effect.
0 System clocks enabled only when PLL is locked or operating normally.
1 System clocks enabled upon wake-up from stop mode, regardless of PLL lock status.
Note: Setting this bit is potentially dangerous and unreliable. The system may behave unpredictably when using an
unlocked clock because the clock frequency could overshoot the maximum frequency of the device.
Note: If FWKUP is set before entering stop mode, it should not be cleared upon wake-up from stop mode until after
the PLL has actually acquired lock. Lock status may be obtained by reading PLL status register. Because the
PLL never locks in limp mode, the FWKUP is ineffective. The system clocks are always enabled upon wake-up
from stop mode, regardless of the value of FWKUP.
4–3
FB_CLK stop mode bits. Controls the operation of the clocks, PLL, and oscillator in stop mode:
STPMD
STPMD System Clocks
FB_CLK
PLL
Oscillator
2–0
8.3
00
Disabled
Enabled
Enabled
Enabled
01
Disabled
Disabled
Enabled
Enabled
10
Disabled
Disabled
Disabled
Enabled
11
Disabled
Disabled
Disabled
Disabled
Reserved, must be cleared.
Functional Description
This section discusses the functions and characteristics of the low-power modes, and how each module is
affected by, or affects these modes.
8.3.1
Peripheral Shut Down
All peripherals, except for the SCM and crossbar switch, may have the software remove their input clocks
individually to reduce power consumption. See Section 8.2.4, “Peripheral Power Management Registers
(PPMHR & PPMLR),” for more information. A peripheral may be disabled at any time and remains
disabled during any low-power mode of operation.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
8-7
Power Management
8.3.2
Limp mode
The device may also boot into a low-frequency limp mode, in which the PLL is bypassed and the device
runs from a factor of the input clock (EXTAL). In this mode, EXTAL feeds a counter that divides the input
clock by 2n, where n is the value of the programmable counter field, CDR[LPDIV]. The programmed
value of the divider may be changed without glitches or otherwise negative affects to the system. While in
this mode, the PLL is placed in bypass mode to reduce overall system-power consumption.
Limp mode may be entered and exited by writing to MISCCR[LIMP].
While in this mode, a 2:1 ratio maintains between the core and the primary bus clock. Because they do not
function at speeds as low as the minimum input clock frequency, the SDRAM and USB On-to-Go
controllers are not functional in limp mode.
8.3.3
Low-Power Modes
The system enters a low-power mode by executing a STOP instruction. The low-power mode the device
actually enters (stop, wait, or doze) depends on the setting of the WCR[LPMD] bits. Entry into any of these
modes idles the CPU with no cycles active, powers down the system, and stops all internal clocks
appropriately. During stop mode, the system clock is stopped low.
A wake-up event is required to exit a low-power mode and return to run mode. Wake-up events consist of
any of these conditions:
• Any type of reset
• Any valid, enabled interrupt request
Exiting from low-power mode via an interrupt request requires:
• An interrupt request whose priority is higher than the value programmed in the WCR[PRILVL].
• An interrupt request whose priority is higher than the value programmed in the interrupt priority
mask (I) field of the core’s status register.
• An interrupt request from a source not masked in the interrupt controller’s interrupt mask register.
• An interrupt request enabled at the module of the interrupt’s origin.
8.3.3.1
Run Mode
Run mode is the normal system operating mode. Current consumption in this mode is related directly to
the system clock frequency.
8.3.3.2
Wait Mode
Wait mode is intended to stop only the CPU and memory clocks until a wake-up event is detected. In this
mode, peripherals may be programmed to continue operating and can generate interrupts, causing the CPU
to exit from wait mode.
MCF52277 Reference Manual, Rev 2
8-8
Freescale Semiconductor
Power Management
8.3.3.3
Doze Mode
Doze mode affects the processor in the same manner as wait mode, except that some peripherals define
individual operational characteristics in doze mode. Peripherals continuing to run and having the
capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode.
Stopped peripherals restart operation on exit from doze mode, as defined for each peripheral.
8.3.3.4
Stop Mode
Stop mode affects the processor the same as the wait and doze modes, except that all clocks to the system
are stopped and the peripherals cease operation.
Stop mode must be entered in a controlled manner to ensure that any current operation is properly
terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation.
NOTE
Entering stop mode disables the SDRAMC, including the refresh counter. If
SDRAM is used, code is required to insure proper entry and exit from stop
mode. See Chapter 19, “SDRAM Controller (SDRAMC),” for more
information.
8.3.4
Peripheral Behavior in Low-Power Modes
The functionality of each of the peripherals and CPU during the various low-power modes is summarized
in Table 8-9 and detailed in the following sections. In Table 8-9 the status of each peripheral during a given
mode refers to the condition the peripheral automatically assumes when the STOP instruction is executed
and the WCR[LPMD] field is set for the particular low-power mode. Individual peripherals may be
disabled by programming its dedicated control bits. The wake-up procedure field refers to the ability of an
interrupt or reset by that peripheral to force the CPU into run mode.
Table 8-9. CPU and Peripherals in Low-Power Modes
Peripheral Status1 / Wake-up Procedure
Module
Wait Mode
Doze Mode
Stop Mode
ColdFire Core
Stopped
N/A
Stopped
N/A
Stopped
N/A
SRAM
Stopped
N/A
Stopped
N/A
Stopped
N/A
Clock Module
Enabled
Interrupt
Enabled
Interrupt
Program
Interrupt
Power Management
Enabled
N/A
Enabled
N/A
Stopped
N/A
Chip Configuration Module
Enabled
N/A
Enabled
N/A
Stopped
N/A
Reset Controller
Enabled
Reset
Enabled
Reset
Stopped
Reset
System Control Module
Enabled
Reset
Enabled
Reset
Enabled
N/A
GPIO Module
Enabled
N/A
Enabled
N/A
Stopped
N/A
Interrupt controller
Enabled
Interrupt
Enabled
Interrupt
Stopped
Interrupt
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
8-9
Power Management
Table 8-9. CPU and Peripherals in Low-Power Modes (continued)
Peripheral Status1 / Wake-up Procedure
Module
Wait Mode
Doze Mode
Stop Mode
Edge port
Enabled
Interrupt
Enabled
Interrupt
Stopped
Interrupt
eDMA Controller
Enabled
Yes
Enabled
Yes
Stopped
N/A
FlexBus Module
Enabled
N/A
Enabled
N/A
Stopped
N/A
SDRAM Controller
Enabled
N/A
Enabled
N/A
Stopped
N/A
USB OTG
Enabled
Interrupt
Stopped
Interrupt
Stopped
N/A
Touchscreen Controller
Enabled
Interrupt
Enabled
Interrupt
Stopped
Interrupt
LCD Controller
Enabled
Interrupt
Enabled
Interrupt
Stopped
N/A
FlexCAN
Enabled
Reset
Enabled
Reset
Stopped
N/A
PWM
Program
N/A
Program
N/A
Stopped
N/A
SSI
Enabled
Interrupt
Enabled
Interrupt
Stopped
N/A
Real Time Clock
Enabled
Interrupt
Enabled
Interrupt
Enabled
Interrupt
Programmable Interrupt Timers
Enabled
Interrupt
Program
Interrupt
Stopped
N/A
DMA Timers
Enabled
Interrupt
Enabled
Interrupt
Stopped
N/A
DSPI
Enabled
Interrupt
Enabled
Interrupt
Stopped
N/A
UARTs
Enabled
Interrupt
Enabled
Interrupt
Stopped
N/A
I2C
Enabled
Interrupt
Enabled
Interrupt
Stopped
N/A
JTAG2
Enabled
N/A
Enabled
N/A
Enabled
N/A
BDM3
Enabled
Yes
Enabled
Yes
Enabled
Yes
Module
1
Program indicates that the peripheral function during the low-power mode is dependent on programmable bits in the
peripheral register map.
2 The JTAG logic is clocked by a separate TCLK clock.
3 Entering halt mode via the BDM port exits any lower-power mode. Upon exit from halt mode, the previous low-power mode
is re-entered and changes made in halt mode remain in effect.
8.3.4.1
ColdFire Core
The ColdFire core disables during any low-power mode. No recovery time is required when exiting any
low-power mode.
8.3.4.2
Internal SRAM
The SRAM is disabled during any low-power mode. No recovery time is required when exiting any
low-power mode.
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Power Management
8.3.4.3
Clock Module
In wait and doze modes, the clocks to the CPU and SRAM stop and the system clocks to the peripherals
enable. Each module may disable the module clocks locally at the module level, or the module clocks may
be individually disabled by the PPMR registers (refer to Section 8.2.4, “Peripheral Power Management
Registers (PPMHR & PPMLR)”). In stop mode, all clocks to the system stop.
There are several options for enabling or disabling the PLL or crystal oscillator in stop mode,
compromising between stop mode current and wake-up recovery time. The PLL can be disabled in stop
mode, but requires a wake-up period before it can relock. The oscillator can also be disabled during stop
mode, but requires a wake-up period to restart.
When the PLL is enabled in stop mode (LPCR[STPMD] equals 00), the external FB_CLK signal can
support systems using FB_CLK as the clock source. See Section 8.2.5, “Low-Power Control Register
(LPCR),” for more information about operating the PLL in stop mode.
There is also a fast wake-up option for quickly enabling the system clocks during stop recovery
(LPCR[FWKUP]). This eliminates the wake-up recovery time but at the risk of sending a potentially
unstable clock to the system. This is also explained in Section 8.2.5, “Low-Power Control Register
(LPCR).”
8.3.4.4
Chip Configuration Module
The chip configuration module is unaffected by entry into a low-power mode. If a reset exits low-power
mode, chip configuration may execute if configured to do so.
8.3.4.5
Reset Controller
A power-on reset (POR) always causes a chip to reset and exit from any low-power mode.
In wait and doze modes, asserting the external RESET pin for at least four clocks causes an external reset
that resets the chip and exits any low-power modes.
In stop mode, the RESET pin synchronization disables and asserting the external RESET pin
asynchronously generates an internal reset and exit any low-power modes. Registers lose current values
and must be reconfigured from reset state if needed.
If the core watchdog timer remains enabled during wait or doze modes, a watchdog timer timeout may
generate a reset to exit these low-power modes.
When the CPU is inactive, a software reset cannot generate to exit any low-power mode.
8.3.4.6
System Control Module (SCM)
The SCM’s core watchdog timer can bring the device out of all low-power modes except stop mode. In
stop mode, all clocks stop, and the core watchdog timer does not operate.
When enabled, the core watchdog can bring the device out of low-power mode in one of two ways.
Depending on the setting of the CWCR[CWRI] field, a core watchdog timeout may reset the device. Other
settings of the CWRI field may enable a core watchdog interrupt and upon a watchdog timeout, this
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Power Management
interrupt can bring the device out of low-power mode. This system setup must meet the conditions
specified in Section 8.3.3, “Low-Power Modes,” for the core watchdog interrupt to bring the part out of
low-power mode.
8.3.4.7
Crossbar Switch
The crossbar switch is enabled during any low-power mode.
8.3.4.8
GPIO Ports
The GPIO ports are unaffected by entry into a low-power mode. These pins may impact low-power current
draw if they are configured as outputs and are sourcing current to an external load. If low-power mode is
exited by a reset, the state of the I/O pins reverts to their default direction settings.
8.3.4.9
Interrupt Controllers (INTC0, INTC1)
The interrupt controller is not affected by any of the low-power modes. All logic between the input sources
and generating the interrupt to the processor is combinational to allow the ability to wake up the core
during low-power stop mode when all system clocks stop.
An interrupt request causes the processor to exit a low-power mode only if that interrupt’s priority level is
at or above the level programmed in the interrupt priority mask field of the CPU’s status register (SR) and
above the level programmed in the WCR[PRILVL]. The interrupt must also be enabled in the interrupt
controller’s interrupt mask register as well as at the module from which the interrupt request would
originate.
8.3.4.10
Edge Port
In wait and doze modes, the edge port continues to operate normally and may be configured to generate
interrupts (an edge transition or low level on an external pin) to exit the low-power modes.
In stop mode, no system clock is available to perform the edge detect function. Therefore, only the level
detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an
interrupt (if enabled) to exit stop mode.
8.3.4.11
eDMA Controller
In wait and doze modes, the eDMA controller can bring the device out of a low-power mode by generating
an interrupt upon completion of a transfer or upon an error condition. The completion of transfer interrupt
generates when DMA interrupts are enabled by the setting of a EDMA_INTR[INTn], and an interrupt is
generated when TCDn[DONE] is set. The interrupt upon error condition is generated when
EDMA_EEIR[EEIn] is set, and an interrupt generates when any of the EDMA_ESR bits become set.
The eDMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode.
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Power Management
8.3.4.12
FlexBus Module
In wait and doze modes, the FlexBus module continues operation but does not generate interrupts;
therefore, it cannot bring a device out of a low-power mode. This module is stopped in STOP mode.
8.3.4.13
SDRAM Controller (SDRAMC)
SDRAM controller operation is unaffected by wait or doze modes; however, the SDRAMC is disabled by
stop mode. Because the STOP mode disables all clocks to the SDRAMC, the SDRAMC does not generate
refresh cycles.
To prevent data loss, SDRAMC should be placed in self-refresh mode by clearing SDCR[CKE] and setting
SDCR[REF_EN]. The SDRAM self-refresh mode allows the SDRAM to enter a low-power state where
internal refresh operations maintain the integrity of the SDRAM data.
When stop mode is exited, setting the SDCR[CKE] bit causes the SDRAM controller to exit the
self-refresh mode and allow bus cycles to the SDRAM to resume.
NOTE
The SDRAM is inaccessible in the self-refresh mode. Therefore, if stop
mode is used, the vector table and any interrupt handlers that could wake the
processor should not be stored in or attempt to access SDRAM.
8.3.4.14
USB On-the-Go Module
If the USB On-the-Go module is clocked externally, it operates normally in wait mode. It is capable of
generating an interrupt to wake-up the core from wait mode. In stop and doze mode, the USB module is
disabled.
The USB block contains an automatic low-power mode in which the module enters suspend mode after a
6.0 ms minimum period of inactivity. When the module receives a wake-up from the USB host, the
transceiver is re-enabled for normal USB operations.
8.3.4.15
Touchscreen Controller
The touchscreen controller operates normally in wait mode, and if the ASP_CR[DOZE] bit is cleared, it
also operates normally in doze mode. If in doze mode and ASP_CR[DOZE] is set, the clock is disabled
after the current conversion is complete.
In stop mode, the touschreen controller is disabled and the current conversion is stopped immediately no
matter if the current conversion is complete. It is recommended to clear ASP_CR[ASPE] before entering
stop mode.
The touchscreen controller is capable of generating an interrupt to wake-up the core from wait and doze
modes. In stop mode, there is a pen-down event that can generate an interrupt to wake-up the device. Upon
exiting stop mode, the touschreen controller resumes operation from the state prior to stop mode entry.
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Power Management
8.3.4.16
LCD Controller
In wait and doze modes, the LCD controller continues operation and is capable of generating an interrupt
to wake-up the core from these modes. In stop mode, the LCD controller is disabled and cannot generate
an interrupt to wake-up the device.
8.3.4.17
FlexCAN
When enabled, the FlexCAN module is capable of generating interrupts and bringing the device out of a
low-power mode.
When setting stop mode in the FlexCAN (by setting the CANMCR[MDIS] bit), the FlexCAN checks for
the CAN bus to be idle or waits for the third bit of intermission and checks to see if it is recessive. When
this condition exists, the FlexCAN waits for all internal activity other than in the CAN bus interface to
complete and then the following occurs:
• The FlexCAN shuts down its clocks, stopping most of the internal circuits, to achieve maximum
possible power saving.
• The internal bus interface logic continues operation, enabling CPU to access the CANMCR
register.
• The FlexCAN ignores its Rx input pin, and drives its Tx pins as recessive.
• FlexCAN loses synchronization with the CAN bus, and the CANMCR[STOP_ACK, NOT_RDY]
bits are set.
Exiting stop mode is done in one of the following ways:
• Reset the FlexCAN (by hard reset or by asserting the CANMCR[SOFT_RST] bit).
• Clearing the CANMCR[MDIS] bit.
Recommendations for, and features of, FlexCAN’s stop mode operation are as follows:
• Upon stop mode entry, the FlexCAN tries to receive the frame that caused it to wake; it assumes
that the dominant bit detected is a start-of-frame bit. It does not arbitrate for the CAN bus then.
• Before asserting stop mode, the CPU should disable all interrupts in the FlexCAN, otherwise it
may be interrupted while in stop mode upon a non-wake-up condition.
• If stop mode is asserted while the FlexCAN is BUSOFF (see error and status register), then the
FlexCAN enters stop mode and stops counting the synchronization sequence; it continues this
count after stop mode is exited.
• If halt mode is active at the time the MDIS bit is set, then the FlexCAN assumes that halt mode
should be exited; hence it tries to synchronize to the CAN bus (11 consecutive recessive bits), and
only then does it search for the correct conditions to stop.
• Trying to stop the FlexCAN immediately after reset is allowed only after basic initialization has
been performed.
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Power Management
8.3.4.18
PWM Module
The PWM module is user-programmable as to how it behaves when the device enters wait mode
(PWMCTL[PSWAI]) and debug mode (PWMCTL[PFRZ]). If either of these bits are set, the PWM input
clock to the prescalar is disabled during the respective low power mode.
In stop mode the input clock is disabled and PWM generation is halted.
8.3.4.19
Real Time Clock
In stop mode, the external clock driving EXTAL32K/XTAL32K continues to clock the RTC module.
Therefore, the device can update the RTC counters, alarms, etc. while in stop mode. An RTC
interrupt/wake-up can be generated while in stop mode to wakeup the device if the RTC alarms are
triggered.
8.3.4.20
Programmable Interrupt Timers (PIT0–3)
In stop mode (or doze mode, if so programmed in the PCSRn register), the programmable interrupt timer
(PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes
operation from the stopped value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the PIT may generate an interrupt to exit the low-power modes.
8.3.4.21
DMA Timers (DTIM0–3)
In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power mode. This
interrupt can generate when the DMA timer is in input capture mode or reference compare mode.
In input capture mode, where the capture enable (CE) field of the timer mode register (DTMR) has a
non-zero value and the DTXMR[DMAEN] is cleared, an interrupt issues upon a captured input. In
reference compare mode, where the output reference requests interrupt enable (ORRI) bit of DTMR is set
and DTXMR[DMAEN] is cleared, an interrupt issues when the timer counter reaches the reference value.
DMA timer operation disables in stop mode. Upon exiting stop mode, the timer resumes operation unless
stop mode was exited by reset.
8.3.4.22
DMA Serial Peripheral Interface (DSPI)
In wait and doze modes, the DSPI module is unaffected and may generate an interrupt to exit these
low-power modes.
In stop mode, the DSPI stops immediately and freezes operation, register values, state machines, and
external pins. During this mode, the DSPI clocks shut down. Coming out of stop mode returns the DSPI
to operation from the state prior to stop mode entry.
8.3.4.23
UART Modules (UART0–2)
In wait and doze modes, the UARTs are unaffected and may generate an interrupt to exit these low-power
modes.
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Freescale Semiconductor
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Power Management
In stop mode, the UARTs stop immediately and freeze their operation, register values, state machines, and
external pins. During this mode, the UART clocks shut down. Exiting stop mode returns the UARTs to the
operation of the state prior to stop-mode entry.
8.3.4.24
I2C Module
When the I2C Module is enabled by the setting of the I2CR[IEN] bit and the device is not in stop mode,
the I2C module is operable and may generate an interrupt to bring the device out of a low-power mode.
For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and the setting of the I2SR[IIF]
generates the interrupt signal to the CPU and interrupt controller. The setting of I2SR[IIF] signifies the
completion of one byte transfer or the reception of a calling address matching its own specified address
when in slave-receive mode.
In stop mode, the I2C module stops immediately and freezes operation, register values, and external pins.
Upon exiting stop mode, the I2C resumes operation unless stop mode was exited by reset.
8.3.4.25
BDM
Entering halt (debug) mode via the BDM port (by asserting the external BKPT pin) causes the processor
to exit any low-power mode.
8.3.4.26
JTAG
The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and not affected by
the system clock. The JTAG cannot generate an event to cause the processor to exit any low-power mode.
Toggling TCLK during any low-power mode increases the system current consumption.
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Chapter 9
Chip Configuration Module (CCM)
9.1
Introduction
The chip-configuration module (CCM) controls the chip configuration for the device.
9.1.1
Block Diagram
Reset
Configuration
Low-Power
Configuration
Serial Boot
Facility
Bus Monitor
Configuration
Chip Configuration Module
Registers
Figure 9-1. Chip-Configuration Module Block Diagram
9.1.2
Features
The CCM performs these operations:
• Configures device based on chosen reset configuration options
• Selects bus-monitor configuration
• Selects low-power configuration
• Facilitates serial boot (See Chapter 10, “Serial Boot Facility (SBF),” for details.)
9.1.3
Modes of Operation
The only chip operating mode available on this device is master mode. In master mode, the ColdFire core
can access external memories and peripherals.The external bus consists of a 32-bit data bus and 24 address
lines. The available bus control signals include FB_R/W, FB_TS, FB_TA, FB_OE, and
FB_BE/BWE[3:0]. Up to six chip selects can be programmed to select and control external devices and to
provide bus cycle termination.
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9-1
Chip Configuration Module (CCM)
9.2
External Signal Descriptions
Table 9-1 provides an overview of the CCM signals.
Table 9-1. Signal Properties
Name
Direction
BOOTMOD[1:0]
I
FB_A[21:16]
9.2.1
I/O
Description
Reset State
Reset configuration select
—
Reset configuration override pins
—
BOOTMOD[1:0]
If the BOOTMOD[1:0] signals determine the boot performed at reset. See the table below for
BOOTMOD[1:0] usage.
Table 9-2. BOOTMOD[1:0] Values
BOOTMOD[1:0]
9.2.2
Meaning
00
Boot from FlexBus with defaults, unified SDR bus/FlexBus.
01
Boot from FlexBus with defaults, split DDR bus/FlexBus.
10
Boot from FlexBus and override defaults via data bus (FB_A[21:16]).
11
Boot from SPI EEPROM, flash, or FRAM and override defaults. See
Chapter 10, “Serial Boot Facility (SBF).”
FB_A[21:16] (Reset Configuration Override)
If the external BOOTMOD[1:0] pins are driven to 10 during reset, the states of the FB_A[21:16] pins
during reset determine FlexBus, PCI, and PLL configurations after reset.
NOTE
The logic levels for reset configuration on FB_A[21:16] must be actively
driven when BOOTMOD = 10. FB_A[23:22,15:0] should be allowed to
float or be pulled high.
9.3
Memory Map/Register Definition
The CCM programming model consists of the registers listed in the below table.
Table 9-3. CCM Memory Map
Address
Register
Width
(bits)
Access Reset Value
Section/Page
Supervisor Access Only Registers1
0xFC0A_0004 Chip Configuration Register (CCR)
16
R
See Section
9.3.1/9-3
0xFC0A_0008 Reset Configuration Register (RCON)
16
R
0x000D
9.3.2/9-4
0xFC0A_000A Chip Identification Register (CIR)
16
R
See Section
9.3.3/9-5
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9-2
Freescale Semiconductor
Chip Configuration Module (CCM)
Table 9-3. CCM Memory Map (continued)
Address
Width
(bits)
Register
Access Reset Value
Section/Page
0xFC0A_0010 Miscellaneous Control Register (MISCCR)
16
R/W
See Section
9.3.4/9-5
0xFC0A_0012 Clock Divider Register (CDR)
16
R/W
0x0001
9.3.5/9-8
0xFC0A_0014 USB On-the-Go Controller Status Register (UOCSR)
16
R/W
0x3010
9.3.6/9-8
0xFC0A_0018 Serial Boot Facility Status Register (SBFSR)2
16
R
See Section
10.3.1/10-3
16
R/W
See Section
10.3.2/10-3
2
0xFC0A_001A Serial Boot Facility Control Register (SBFCR)
1
2
User access to supervisor-only address locations have no effect and result in a bus error.
See Chapter 10, “Serial Boot Facility (SBF),” for details.
9.3.1
Chip Configuration Register (CCR)
The CCR is a read-only register; writing to the CCR has no effect. At reset, the CCR reflects the chosen
operation of certain chip functions. These functions may be set to the defaults defined by the RCON
register or overridden during reset configuration using the external BOOTMOD[1:0] and the FB_A[21:16]
pins or the serial boot data obtained from external SPI memory.
Address: 0xFC0A_0004 (CCR)
15
R:
14
13
Access: Supervisor read-only
12
11
10
9
8
0
0
0
0
0
0
0
DRAM
SEL
0
0
0
0
0
0
0
See
Note
7
6
CSC
5
4
LIMP LOAD
3
2
BOOTPS
1
0
OSC
MODE
1
W
Reset
See Note
Note: See DRAMSEL bit description for reset value.
Note: CCR[7:0] reset value depends upon chosen reset configuration. Default reset value (BOOTMOD = 00 or 01) is the
value of RCON[7:0].
Figure 9-2. Chip Configuration Register (CCR)
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Freescale Semiconductor
9-3
Chip Configuration Module (CCM)
Table 9-4. CCR Field Descriptions
Field
15–9
8
DRAMSEL
Description
Reserved, must be cleared.
FlexBus/SDRAM data pin configuration. Reflects the chosen data bus configuration as determined by
BOOTMOD[1:0], FB_A21, or SBF_RCON29 as shown below:
BOOTMOD[1:0]
DRAMSEL
00
1
Unified SDR bus/FlexBus
01
0
Split DDR bus/FlexBus
10
FB_A21
11
SBF_RCON29
Override defaults via data bus (FB_A[21:16]).
Override defaults via serial boot.
Note: If DRAMSEL is cleared, only 8-bit and 16-bit port sizes are allowed.
0 D[31:16] = SDRAM DDR data[31:16]
D[15:0] = FlexBus data[31:16]
1 D[31:0] = SDRAM SDR data[31:0] or FlexBus data[31:0]
7–6
CSC
Chip select configuration. Reflects the chosen chip select configuration.
00 FB_A[23:22] = FB_A[23:22]
01 FB_A[23:22] = FB_CS5, A22
10 FB_A[23:22] = FB_CS[5:4]
11 Reserved
5
LIMP
Limp mode bit.
0 Normal operation; PLL drives internal clocks.
1 Limp mode; low-power clock divider drives internal clocks.
4
LOAD
Pad driver load bit. Reflects the chosen pad driver strength for those pins with drive strength control and the
chosen pad slew rate for those pins with slew rate control.
0 Low drive strength, low slew rate
1 High drive strength, high slew rate
3–2
BOOTPS
1
OSCMODE
0
9.3.2
Boot port size field. Indicates the selection for the boot port size.
00 32 bits
01 8 bits
10 16 bits
11 16 bits
Note: 32-bit port size cannot be selected when the DRAMSEL is 0.
Oscillator clock mode bit.
0 Crystal oscillator mode
1 Oscillator bypass mode
Reserved, must be set.
Reset Configuration Register (RCON)
At reset, the RCON register determines the default operation of certain chip functions. All default
functions defined by the RCON values can be overridden only during reset configuration (see
Section 9.4.1, “Reset Configuration”) if the external BOOTMOD[1:0] pins are driven to 10 or 11. RCON
is a read-only register and contains the same fields as the CCR register, except for DRAMSEL.
MCF52277 Reference Manual, Rev 2
9-4
Freescale Semiconductor
Chip Configuration Module (CCM)
Address: 0xFC0A_0008 (RCON)
15
R
14
13
Access: Supervisor
read-only
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
CSC
4
3
LIMP LOAD
2
BOOTPS
1
0
OSC
MODE
1
0
1
W
Reset
0
0
0
0
1
1
Figure 9-3. Reset Configuration Register (RCON)
9.3.3
Chip Identification Register (CIR)
Address: 0xFC0A_000A (CIR)
15
14
13
Access: Supervisor read-only
12
11
R
10
9
8
7
6
5
4
3
2
1
PIN
PRN
Device Dependent
Mask Set Dependent
0
W
Reset
Figure 9-4. Chip Identification Register (CIR)
Table 9-5. CIR Field Descriptions
Field
Description
15–6
PIN
Part identification number. Contains a unique identification number for the device.
0x06C MCF52277
0x06E MCF52274
5–0
PRN
Part revision number. This number increases by one for each new full-layer mask set of this part. The revision
numbers are assigned in chronological order.
9.3.4
Miscellaneous Control Register (MISCCR)
The MISCCR register provides clock source selection and configuration for internal clocks, as well as
SSI/timer DMA mux control and other miscellaneous control functionality.
Address: 0xFC0A_0010 (MISCCR)
R
15
14
13
0
RTC
SRC
USB
PUE
W
Reset
0
12
LIMP
Access: Supervisor read/write
11
BME
10
9
8
BMT
7
6
5
4
3
2
1
0
SSI
PUE
SSI
PUS
TIM
DMA
SSI
SRC
0
LCDC
HEN
USB
OC
USB
SRC
See Note
0
See Note
Note: Reset value depends on RCON type. See Table 9-6.
Figure 9-5. Miscellaneous Control Register (MISCCR)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
9-5
Chip Configuration Module (CCM)
Table 9-6. MISCCR Field Reset Values
BOOTMOD[1:0]
Field
00 or 01
10
11
RTCSRC
0
0
SBF_RCON[15]
USBPUE
1
1
1
LIMP
1
FB_A[19]
SBF_RCON[20]
BME
1
1
SBF_RCON[19]
BMT
000
000
SBF_RCON[18:16]
SSIPUE
1
1
SBF_RCON[14]
SSIPUS
1
1
SBF_RCON[13]
TIMDMA
1
1
SBF_RCON[23]
SSISRC
1
1
SBF_RCON[12]
LCDCHEN
0
0
SBF_RCON[22]
USBOC
1
1
SBF_RCON[11]
USBSRC
1
1
SBF_RCON[10]
Table 9-7. MISCCR Field Descriptions
Field
15
Description
Reserved, must be cleared.
14
RTCSRC
RTC clock source. Selects the RTC_XTAL input or an output from the main crystal oscillator.
0 RTC_EXTAL/RTC_XTAL are used
1 Output of system crystal oscillator is used.
13
USBPUE
USB transceiver pull-up enable. Enables the on-chip USB OTG controller to drive the internal transceiver pull-up.
0 Internal transceiver pull-up is disabled.
1 USB OTG drives the internal transceiver pull-up.
12
LIMP
Limp mode enable. Selects between the PLL and the low-power clock divider as the source of all system clocks.
0 Normal operation; PLL drives system clocks.
1 Limp mode; low-power clock divider drives system clocks.
Note: The transient behavior of the system when writing this bit cannot be predicted. When any USB wake-up
event is detected, this bit is cleared, limp mode is exited, and the PLL begins the process of relocking and
driving the system clocks.
11
BME
Bus monitor external enable bit. Enables the bus monitor to operate during external FlexBus cycles
0 Bus monitor disabled on external FlexBus cycles
1 Bus monitor enabled on external FlexBus cycles
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Chip Configuration Module (CCM)
Table 9-7. MISCCR Field Descriptions (continued)
Field
10–8
BMT
Description
Bus monitor timing field. Selects the timeout period in FlexBus clock cycles for the bus monitor:
Timeout period for external bus cycles equals 2(16-BMT) FB_CLK cycles
000 65536
001 32768
010 16384
011 8192
100 4096
101 2048
110 1024
111 512
7
SSIPUE
SSI RXD/TXD pull enable. Enables the internal weak pull cells on any external pin where the SSI receive data
(RXD) function or SSI transmit data (TXD) function is available. The affected pins include U1RXD and U1TXD.
0 SSI data pin weak pull cells disabled.
1 SSI data pin weak pull cells enabled.
Note: The SSIPUE bit enables only the pull cells when the SSI RXD and TXD functions are currently selected
for the affected pins. See the Chapter 14, “General Purpose I/O Module,” for information on how to enable
the SSI functions on those pins.
6
SSIPUS
SSI RXD/TXD pull select. Selects whether the internal weak pull cells enabled by the SSIPUE bit are pull-up or
pull-down.
0 SSI data pins are pulled down.
1 SSI data pins are pulled up.
Note: The SSIPUS bit has no effect when the SSIPUE bit is cleared.
5
TIMDMA
Timer DMA mux selection. Selects between the timer DMA signals and SSI DMA signals as those signals are
mapped to DMA channels 9-12. Refer to the Chapter 17, “Enhanced Direct Memory Access (eDMA),” for more
details on the DMA controller.
0 SSI RX0, SSI RX1, SSI TX0, and SSI TX1 DMA signals mapped to DMA channels 9–12, respectively.
1 Timer 0–3 DMA signals mapped to DMA channels 9–12, respectively.
4
SSISRC
SSI clock source. Selects between the PLL and the external SSI_CLKIN pin as the source of the SSI
oversampling clock.
0 SSI_CLKIN pin directly drives SSI oversampling clock.
1 PLL drives SSI oversampling clock with fractionally divided CPU clock.
3
2
LCDCHEN
Reserved, must be cleared.
LCD internal clock enable. Selects whether the internal clock input to the LCD controller is enabled.
0 LCD internal clock disabled
1 LCD internal clock enabled
1
USBOC
USB VBUS over-current sense polarity. Selects the polarity of the USB VBUS over-current sense signal driven
off-chip.
0 USB_VBUS_OC is active high.
1 USB_VBUS_OC is active low.
0
USBSRC
USB clock source. Selects between the PLL and the external USB_CLKIN external pin as the clock source for
the serial and ULPI interfaces of the USB module.
0 USB_CLKIN pin drives USB serial interface clocks.
1 PLL drives USB serial interface clocks.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
9-7
Chip Configuration Module (CCM)
9.3.5
Clock-Divider Register (CDR)
The CDR register provides clock division factors for the USB module, limp mode, and the SSI master
clock when the PLL is used to drive the SSI clock.
Address: 0xFC0A_0012 (CDR)
R
Access: Supervisor read/write
15
14
13
12
0
0
0
0
0
0
0
0
11
9
8
7
6
5
4
LPDIV
W
Reset
10
0
0
3
2
1
0
0
0
1
SSIDIV
0
0
0
0
0
0
0
Figure 9-6. Clock-Divider Register (CDR)
Table 9-8. CDR Field Descriptions
Field
Description
15–12
Reserved, must be cleared.
11–8
LPDIV
Low power clock divider. Specifies the divide value used to produce the system clocks during limp mode. A 2:1
ratio is maintained between the core and the internal bus. This field is used only when MISCCR[LIMP] bit is set.
f EXTAL
System Clocks = ---------------LPDIV
2
7–0
SSIDIV
Eqn. 9-1
SSI oversampling clock divider. Specifies the divide value used to produce the oversampling clock for the SSI.
This field is used only when MISCCR[SSISRC] is set (PLL is the source).
f sys
SSI Baud Clock = --------------------------SSIDIV ⁄ 2
Eqn. 9-2
Note: A value of 0 or 1 for SSIDIV represents a divide-by-65. SSIDIV should not be set to any value that sets the
SSI oversampling clock frequency over the bus clock frequency (fsys/2) because incorrect SSI operation
could result.
9.3.6
USB On-the-Go Controller Status Register (UOCSR)
The UOCSR register controls and reflects various features of the USB OTG module. When any bit of this
register generates an interrupt, that interrupt can be cleared by reading the UOCSR register. The read-only
bits of this register are set by the USB OTG module.
Address: 0xFC0A_0014 (UOCSR)
15
R
14
0
0
0
0
13
12
DPPD DMPD
Access: Supervisor read/write
11
0
10
9
8
7
6
5
4
CRG_ DCR_
DPPU
VBUS VBUS
AVLD BVLD VVLD SEND
3
0
2
1
0
WKUP UOMIE XPDE
W
Reset
1
1
0
0
0
0
0
0
0
1
0
0
0
0
Figure 9-7. USB On-the-Go Controller Status Register (UOCSR)
MCF52277 Reference Manual, Rev 2
9-8
Freescale Semiconductor
Chip Configuration Module (CCM)
Table 9-9. UOCSR Field Descriptions
Field
Description
15–14
Reserved, must be cleared.
13
DPPD
D+ 15 kΩ pull-down. Indicates the 15-kΩ pull-down on the OTG D+ line is active. When set, it asserts an interrupt
if the UOMIE bit is set.
12
DMPD
D- 15 kΩ pull-down. Indicates the 15-kΩ pull-down on the OTG D- line is active. When set, it asserts an interrupt
if the UOMIE bit is set.
11
Reserved, must be cleared.
10
Charge VBUS. Indicates a charge resistor to pull-up VBUS is enabled. When set, it asserts an interrupt if the
CRG_VBUS UOMIE bit is set.
9
Discharge VBUS. Indicates a discharge resistor to pull-down VBUS is enabled. When set, it asserts an interrupt
DCR_VBUS if the UOMIE bit is set.
8
DPPU
D+ pull-up. Indicates pull-up on D+ for FS-only applications is enabled. When set, it asserts an interrupt if the
UOMIE bit is set.
7
AVLD
A-peripheral is valid. Indicates if the session for an A-peripheral is valid.
0 Session is not valid for an A-peripheral.
1 Session is valid for an A-peripheral.
6
BVLD
B-peripheral is valid. Indicates if the session for a B-peripheral is valid.
0 Session is not valid for a B-peripheral.
1 Session is valid for a B-peripheral.
5
VVLD
VBUS valid. Indicates if voltage on VBUS is at a valid level for operation.
0 Voltage level on VBUS is not valid for operation.
1 Voltage level on VBUS is valid for operation.
4
SEND
Session end. Indicates if voltage on VBUS has dropped below the session end threshold.
0 Voltage on VBUS has not dropped below the session end threshold
1 Voltage on VBUS has dropped below the session end threshold
3
Reserved, must be cleared.
2
WKUP
USB OTG controller wake-up event. Reflects if a wake-up event has occurred on the USB OTG controller bus.
0 No outstanding wake-up event.
1 Wake-up event has occurred.
1
UOMIE
USB OTG miscellaneous interrupt enable. Enables an interrupt to generate from any of the following UOCSR
bits: DPPD, DMPD, CRG_VBUS, DCR_VBUS, DPPU, and WKUP
0 Interrupt sources are disabled.
1 Interrupt sources are enabled.
0
XPDE
On-chip transceiver pull-down enable.
0 50 kΩ pull-downs disabled on OTG D+ and D- pins of on-chip transceiver.
1 On-chip 50 kΩ pull-downs enabled on OTG D+ and D- transceiver pins of on-chip transceiver.
9.4
9.4.1
Functional Description
Reset Configuration
During reset, the pins for the reset override functions are immediately configured to known states.
Table 9-10 shows the states of the external pins while in reset.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
9-9
Chip Configuration Module (CCM)
Table 9-10. Reset Configuration Pin States During Reset
Pin
Direction
Pin Function
Input State
BOOTMOD[1:0]
I
BOOTMOD function for all modes
Must be driven by external logic
I
FlexBus address functions
(BOOTMO ≠ 10)
N/A
I
Reset configuration data functions
(BOOTMOD = 10)
Must be driven by external logic
FB_A[21:16]
9.4.1.1
Reset Configuration (BOOTMOD[1:0] = 00 or 01)
If the BOOTMOD pins are 00 or 01 during reset, the RCON register determines the chip configuration
after reset, regardless of the states of the external data pins. The internal configuration signals are driven
to levels specified by the RCON register’s reset state for default module configuration.
9.4.1.2
Reset Configuration (BOOTMOD[1:0] = 10)
If the BOOTMOD pins are 10 during reset, the chip configuration after reset is determined according to
the levels driven onto the FB_A[21:16] pins. (See Table 9-11.) The internal configuration signals are
driven to reflect the levels on the external configuration pins to allow for module configuration.
NOTE
The logic levels for reset configuration on FB_A[21:16] must be actively
driven when BOOTMOD equals 10. The FB_A[23:22,15:0] pins must be
allowed to float or be pulled high.
Table 9-11. Parallel Configuration During Reset1
Pin(s) Affected
(none)
Affected CCM
Register Bit(s)
RCON[1]
Override Pins
in Reset2,3
Function
FB_A16
Oscillator Mode
0
Crystal oscillator mode
1
Oscillator bypass mode
FB_A17
FB_D[31:0]
RCON[3:2]
Boot Device
0
8-bit (split bus) or 32-bit (unified bus)
1
16-bit split bus
FB_A18
All output pins
RCON[4]
Output Pad Drive Strength
0
Low Drive Strength
1
High Drive Strength
FB_A19
(none)
RCON[5]
PLL Mode
0
PLL mode
1
Limp mode
MCF52277 Reference Manual, Rev 2
9-10
Freescale Semiconductor
Chip Configuration Module (CCM)
Table 9-11. Parallel Configuration During Reset1 (continued)
Affected CCM
Register Bit(s)
Pin(s) Affected
FB_A[23:22]/FB_CS[5:4]
RCON[7:6]
Override Pins
in Reset2,3
Function
FB_A20
Chip Select Configuration
0
FB_A[23:22] = FB_A[23:22]
1
FB_A[23:22] = FB_CS[5:4]
FB_A21
(none)
RCON[8]
SDR/DDR Config
0
DDR
1
SDR
1
Modifying the default configurations through the FB_A[21:16] pins is possible only if the external BOOTMOD[1:0] pins
are 10 while RSTOUT is asserted.
2 The FB_A[23:22,15:0] pins do not affect reset configuration.
3
The external reset override circuitry drives the data bus pins with the override values while RSTOUT is asserted. It must
stop driving the data bus pins within one FB_CLK cycle after RSTOUT is negated. To prevent contention with the external
reset override circuitry, the reset override pins are forced to inputs during reset and do not become outputs until at least
one FB_CLK cycle after RSTOUT is negated.
9.4.1.3
Reset Configuration (BOOTMOD[1:0] = 11)
If the BOOTMOD pins are 11 during reset, then the chip configuration after reset is determined by data
obtained from external SPI memory through serial boot using the SBF_DI, SBF_DO, SBF_CS, and
SBF_CK signals. (See Table 9-12.) The internal configuration signals are driven to reflect the data being
received from the external SPI memory to allow for module configuration. See Chapter 10, “Serial Boot
Facility (SBF),” for more details on serial boot.
Table 9-12. Serial Configuration During Reset
Pin(s) Affected
Affected CCM
Register Bit(s)
Override
SBF_RCON Bits
Function
Mnemonic Bit Num
BOOTPS
FB_D[31:0]
CCR[3:2]
CCR[8]
Boot Port Size
00
32-bit port1
01
8-bit port
10
16-bit port
11
16-bit port
DRAMSEL
(none)
31:30
29
SDR/DDR Config
0
DDR
1
SDR
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
9-11
Chip Configuration Module (CCM)
Table 9-12. Serial Configuration During Reset (continued)
Pin(s) Affected
Affected CCM
Register Bit(s)
Override
SBF_RCON Bits
Function
Mnemonic Bit Num
CSC
FB_A[23:22]/
FB_CS[5:4]
CCR[7:6]
28:27
00
FB_A[23:22] = FB_A[23:22]
01
Reserved
10
FB_A[23:22] = FB_CS5, FB_A22
11
FB_A[23:22] = FB_CS[5:4]
LOAD
All output pins
CCR[4]
26
High drive strength
1
Low drive strength
23
MISCCR[2]
Timer 0-3 DMA signals mapped to DMA channels
9-12, respectively
1
SSI RX0, SSI RX1, SSI TX0, SSI TX1 DMA signals
mapped to DMA channels 9-12, respectively
CCR[1]
CCR[5]
1
LCD internal clock enabled
CCR[11]
21
Oscillator Mode
0
Crystal oscillator mode
1
Oscillator bypass mode
20
Limp Mode
0
PLL mode
1
Limp mode
BME
(none)
LCD Internal Clock Enable
LCD internal clock disabled
LIMP
(none)
22
0
OSCMODE
(none)
Timer/SSI DMA Channel Mux Select
0
MISCCR[5]
LCDCHEN
(none)
Output Pad Drive Strength
0
TIMDMA
(none)
Chip Select Configuration
19
External Bus Monitor Enable
0
Bus monitor disabled
1
Bus monitor enabled
MCF52277 Reference Manual, Rev 2
9-12
Freescale Semiconductor
Chip Configuration Module (CCM)
Table 9-12. Serial Configuration During Reset (continued)
Pin(s) Affected
Affected CCM
Register Bit(s)
Override
SBF_RCON Bits
Function
Mnemonic Bit Num
BMT
(none)
MISCCR[10:8]
18:16
000
65536
001
32768
010
16384
011
8192
100
4096
101
2048
110
1024
111
512
RTCSRC
RTC_EXTAL,
RTC_XTAL
MISCCR[14]
MISCCR[7]
MISCCR[6]
1
RTC clock from system oscillator
14
MISCCR[4]
SSI_RXD, SSI_TXD pull cells disabled
1
SSI_RXD, SSI_TXD pull cells enabled
13
MISCCR[1]
SSI_RXD, SSI_TXD pulled low
1
SSI_RXD, SSI_TXD pulled high
12
MISCCR[0]
SSI Clock Source
0
SSI_CLKIN pin drives SSI clock
1
PLL drives SSI clock
11
USB VBUS Overcurrent Sense Polarity
0
USB_VBUS_OC is active-low
1
USB_VBUS_OC is active-high
USBSRC
USB_CLKIN
SSI RXD/TXD Pull Select
0
USBOC
USB_VBUS_OC
SSI RXD/TXD Pull Enable
0
SSISRC
SSI_CLKIN
RTC Clock Source
RTC clock from RTC oscillator
SSIPUS
U1TXD (SSI_TXD),
U1RXD (SSI_RXD)
15
0
SSIPUE
U1TXD (SSI_TXD),
U1RXD (SSI_RXD)
Bus Monitor Timeout (FB_CLK Cycles)
10
USB Clock Source
0
USB_CLKIN pin drives USB serial interface clock
1
PLL drives USB serial interface clocks
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
9-13
Chip Configuration Module (CCM)
Table 9-12. Serial Configuration During Reset (continued)
Pin(s) Affected
Override
SBF_RCON Bits
Affected CCM
Register Bit(s)
Function
Mnemonic Bit Num
USBDIV
(none)
(none)
1
PLL’s
PCR[OUTDIV5]
PLL’s PCR[PFDR]
9:8
USB Clock Divider
00
VCO divided by 5
01
VCO divided by 6
10
VCO divided by 7
11
VCO divided by 8
PFDR
7:0
PLL Multiplier
32-bit port size is not available when DRAMSEL = 0.
9.4.2
Boot Configuration
The FB_CS0 chip select pin selects an external boot device during reset configuration if:
• It is not in serial boot mode
• It is in serial boot mode and the boot code is not in SPI memory
• You choose not to program FB_CS0 to be a GPIO after serial boot is complete
The valid (V) bit in the CSMR0 register is ignored and FB_CS0 is enabled after reset. FB_CS0 is asserted
for the initial boot fetch accessed from address 0x0000_0000 for the stack pointer and address
0x0000_0004 for the program counter (PC). It is assumed the reset vector loaded from address
0x0000_0004 causes the processor to start executing from external memory space decoded by FB_CS0.
9.4.3
Output Pad Strength Configuration
Output pad strength is determined during reset configuration as shown in Table 9-13. After reset is exited,
the output pad strength configuration can only be changed using the GPIO module. For more information,
see Chapter 14, “General Purpose I/O Module.”
Table 9-13. Output Pad Driver Strength Selection1
Optional Pin Function Selection
Output pads configured for high drive strength
Driven high
Output pads configured for low drive strength
Driven low
1
9.4.4
FB_A[18]
Modifying the default configurations is possible only if the external
RCON pin is asserted.
Chip Select Configuration
The chip select (FB_CS[5:4]) configuration is selected during reset and reflected in the CCR[CSC] field.
After reset is exited, the chip select configuration cannot be changed.
MCF52277 Reference Manual, Rev 2
9-14
Freescale Semiconductor
Chip Configuration Module (CCM)
9.4.5
Low Power Configuration
After reset, the device can be configured for operation during the low power modes using the low power
control register (LPCR). For more information on this register, see Section 8.2.5, “Low-Power Control
Register (LPCR).”
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
9-15
Chip Configuration Module (CCM)
MCF52277 Reference Manual, Rev 2
9-16
Freescale Semiconductor
Chapter 10
Serial Boot Facility (SBF)
10.1
Introduction
It is nearly impossible to dedicate and very impractical to share pins for the numerous available power-up
options on today’s complex, highly-integrated processors. The serial boot facility (SBF), shown in
Figure 10-1, solves this problem by providing the user with the capability to store and load all device reset
configuration data and user code from an external SPI memory. This method requires only a minimal
number of I/O pins.
On-chip
Modules
SBF
Clock
Control
SBF_CK
Reset
Controller
SBF_CS
Control
Chip
Configuration
Module
Read
Command
SBF_DO
Registers
Processor
Memory
Deserializer/
Debounce
SBF_DI
RAM
Interface
Figure 10-1. SBF Block Diagram
10.1.1
Overview
The SBF interfaces to an external SPI memory to read configuration data and boot code during the
processor reset sequence if BOOTMOD[1:0] equals 11. By reading data stored in the SPI memory, the SBF
adjusts the SPI memory clock frequency, configures an extended set of power-up options for the processor,
and optionally loads code into the on-chip SRAM. Through interaction with the reset controller, the SBF
performs these actions so that the chip is properly configured after exiting the reset state.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
10-1
Serial Boot Facility (SBF)
10.1.2
Features
The SBF includes these distinctive features:
• Support for many different SPI memory devices
— EEPROM
— Flash
— FRAM
— Embedded FPGA memory
• External interface maps directly to (and can be multiplexed with) the DMA serial peripheral
interface (DSPI) pins
• Self-adjusting shift clock frequency for maximum throughput supported by SPI memory
• Optionally load boot code into processor’s memory space
10.2
External Signal Description
Listed below are the SBF module external signals.
Table 10-1. Signal Properties
1
Signal
I/O
Description
Reset
Pull Up
SBF_CK
O
Shift clock. Alternate edges of this signal cause the SPI memory to accept
data from and drive data to the processor
—
—
SBF_CS
O
Chip select. This signal enables the SPI memory and places it into an
active state, ready to accept commands.
—
—
SBF_DI
I
Data in. The SPI memory drives and the processor accepts read data on
this signal.
—
Active1
SBF_DO
O
Data out. The SBF drives the read command and address on this signal.
—
—
Disabled by the SBF when the SPI memory begins shifting out data.
10.3
Memory Map/Register Definition
The SBF programming model consists of the registers listed below.
Table 10-2. SBF Memory Map
Address
Register
Width
(bits)
Access Reset Value
Section/Page
0xFC0A_0018 Serial boot facility status register (SBFSR)
16
R
See Section
10.3.1/10-3
0xFC0A_0020 Serial boot facility control register (SBFCR)
16
R/W
See Section
10.3.2/10-3
MCF52277 Reference Manual, Rev 2
10-2
Freescale Semiconductor
Serial Boot Facility (SBF)
10.3.1
Serial Boot Facility Status Register (SBFSR)
The read-only SBFSR register reflects the amount of boot code loaded through the external SPI memory.
Address: 0xFC0A_0018 (SBFSR)
15
14
13
Access: User read-only
12
11
10
9
8
R
7
6
5
4
3
2
1
0
BLL
W
Reset
See Note
Note: Reset value is user-defined (loaded from SPI memory during serial boot following any reset type)
Figure 10-2. Serial Boot Facility Status Register (SBFSR)
Table 10-3. SBFSR Field Descriptions
Field
Description
15–0
BLL
Boot load length. Reflects the number of longwords of boot code loaded from external SPI memory during serial
boot. No boot code was loaded if BLL equals 0x0000. Otherwise, BLL plus 1 longwords were loaded.
10.3.2
Serial Boot Facility Control Register (SBFCR)
The read-always/write-once SBFCR register controls SBF operation following subsequent warm resets.
Address: 0xFC0A_0020 (SBFCR)
R
Access: User read/write-once
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
4
3
2
1
FR
BLDIV
01
See Note
0
1
Reset value is 0 and is reset only by power-on reset (remains unchanged for other reset types)
Note: The reset value is loaded from SPI memory during serial boot following power-on reset. It remains unchanged
for other reset types. Prior to this register being loaded from SPI memory, a divisor of 67 is used to begin the
serial boot sequence.
Figure 10-3. Serial Boot Facility Control Register (SBFCR)
Table 10-4. SBFCR Field Descriptions
Field
15–5
4
FR
Description
Reserved, must be cleared.
Fast read. Determines whether the SBF uses the standard READ command or flash FAST_READ command on
reboot following any reset other than power-on reset. Because this register is write-once, the application must write
the value for this bit in the same write that the BLDIV field is written. Any subsequent writes to this field prior to a
power-on reset event terminate without effect.
0 SBF uses the standard READ command
1 SBF uses the FAST_READ command
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
10-3
Serial Boot Facility (SBF)
Table 10-4. SBFCR Field Descriptions (continued)
Field
Description
3–0
BLDIV
Boot loader clock divider. Determines the SBF clock (PLL input reference clock) divisor that generates the serial shift
clock output on SBF_CK. Prior to the serial boot sequence, a divisor of 67 is used.
During the serial boot sequence, this field is loaded with the value read from the SPI memory. The application may
write to this register to change the divisor for any subsequent serial boot that follows a soft-reset condition.
Because this register is write-once, the application must write the value for this field in the same write that the FR bit
is written (regardless of the value written to the FR bit). Any subsequent writes to this field prior to a power-on reset
event terminate without effect.
Shift Clock
Shift Clock
10.4
BLDIV
Ideal
Divisor
Bypass
1000
1
1
3
2
0011
4
0100
BLDIV
Ideal
Divisor
0000
High Time
(fref Ticks)
Low Time
(fref Ticks)
1
Bypass
0001
2
0010
High Time
(fref Ticks)
Low Time
(fref Ticks)
14
7
7
1001
17
9
8
1
1010
25
13
12
2
2
1011
33
17
16
5
3
2
1100
34
17
17
0101
7
4
3
1101
50
25
25
0110
10
5
5
1110
67
34
33
0111
13
7
6
1111
Reserved
Functional Description
When enabled, the SBF inserts three additional steps into the normal system boot process:
• Serial initialization and shift clock frequency adjustment
• Reset configuration and optional boot load
• Execution transfer
10.4.1
Serial Initialization and Shift Clock Frequency Adjustment
The following sequence is followed during a serial boot sequence:
1. The SBF is engaged when BOOTMOD[1:0] = 11 concurrent with the release of a pending source
of reset (power-on, software watchdog, RESET pin, etc).
2. Boot-up is paused.
3. The weak internal pull-up on SBF_DI is enabled. This allows a 1-to-0 transition to register when
the SPI memory output switches from high-impedance to logic 0.
4. The SBF shifts the standard SPI memory read command (0x03) followed by repeated 0x00 address
bytes to the SPI memory at fREF ÷ 67.
MCF52277 Reference Manual, Rev 2
10-4
Freescale Semiconductor
Serial Boot Facility (SBF)
5. After the SPI memory accepts however many shift clock edges are necessary to respond to the
READ command, it turns on its previously tri-stated output and begins driving the msb of the byte
at address 0.
Bits [7:4] of this byte must be 0000, so that the required 1-to-0 transition can be detected on
SBF_DI to synchronize the SBF state machine. If bits [7:4] of this byte are not 0000, bits[3:0] are
ignored, another byte is clocked out of the SPI memory (SBF_DO remains at logic 0), and the SBF
state machine again tests for a 1-to-0 transition followed by four consecutive zero bits.
6. After the necessary 1-to-0 transition and reception of a byte with bits [7:4] equal to 0000, the SBF
pauses and bits [3:0] of the received byte select a new shift clock divider according to Table 10-4.
7. The weak internal pull-up on SBF_DI is disabled.
8. The shift clock begins toggling at the new frequency, resuming the READ command already in
progress.
NOTE
Shift clock frequency adjustment follows a power-on/hard reset only. After
the new divisor is known, it is stored in the sticky SBFCR[BLDIV] field and
used for subsequent soft resets. This speeds reboot for systems that do not
benefit from the optional FAST_READ on soft reset feature (e.g., the SPI
memory does not support FAST_READ, or the input reference clock does
not exceed the maximum allowable frequency for the READ command).
10.4.2
Reset Configuration and Optional Boot Load
After the steps in Section 10.4.1, “Serial Initialization and Shift Clock Frequency Adjustment”, are
executed, the following is performed to load configuration data and optional boot code.
1. Next, the SBF shifts two bytes (16 bits) out of the SPI memory that indicate how many longwords,
if any, are to be read during the optional boot load sequence. These bytes are software-visible in
the SBFSR[BLL] field.
2. The read operation continues with one longwords (32 bits) of reset configuration data, formatted
in the order presented in Section 9.4.1.3, “Reset Configuration (BOOTMOD[1:0] = 11)”.
3. At this point, the SBF determines whether or not to read boot code. If SBFSR[BLL] is set, BLL
plus one longwords (4 × (BLL + 1) bytes) are consecutively loaded into the SRAM.
NOTE
Although the SBF permits up to 65,536 longwords (262,144 bytes) to be
loaded, the maximum practical number that can be read is limited by the size
of the device’s internal SRAM (32,768 longwords (131,072 bytes) for this
device).
10.4.3
Execution Transfer
After boot load is complete or if no boot load is requested (SBFSR[BLL] = 0), the following steps
complete the serial boot process:
1. The acquired configuration data is driven to the appropriate modules.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
10-5
Serial Boot Facility (SBF)
2. The system is released from reset.
3. The ColdFire processor initiates its normal reset vector fetch at address 0.
4. The actual memory that responds to the reset vector fetch depends on whether serial boot load is
requested:
— If SBFSR[BLL] is cleared, the reset vector fetch is handled by the FlexBus module, and
whatever external memory is mapped at address 0, governed by the user-provided setting of
RCON/CCR[DRAMSEL].
— If SBFSR[BLL] is set, the reset vector and boot code are read from the on-chip SRAM. (The
SBF enables the SRAM and maps it to address 0 via the RAMBAR before control of the
processor is restored to the ColdFire core.) The reset vector (initial stack pointer and program
counter) should point to locations in the on-chip SRAM, so that boot code can initialize the
device and load the application software from the SPI memory or via some other mechanism
(e.g. a network server responding to a TFTP client).
10.5
10.5.1
Initialization Information
SPI Memory Initialization
The SBF requires that, prior to device power-up, the SPI memory is loaded with data organized according
to Table 10-5. See Chapter 9, “Chip Configuration Module (CCM),” for the reset configuration (RCON)
data definition.
Table 10-5. SPI Memory Organization
Byte Address
Data Contents
0x0
{0000,BLDIV[3:0]}
0x1
BLL[7:0]
0x2
BLL[15:8]
0x3
RCON[7:0]
0x4
RCON[15:8]
0x5
RCON[23:16]
0x6
RCON[31:24]
0x71
CODE_BYTE_02
0x81
CODE_BYTE_1
...
...
0x6 + 4 × (BLL + 1)
1
CODE_BYTE_[4 × (BLL + 1) - 1]
1
This assumes SBFSR[BLL] is set. If BLL is cleared, the SBF does
not access data at these addresses.
2 Start of the user code copied into the on-chip SRAM.
MCF52277 Reference Manual, Rev 2
10-6
Freescale Semiconductor
Serial Boot Facility (SBF)
10.5.2
FAST_READ Feature Initialization
Many SPI flash memories implement a FAST_READ command that allows for a substantially higher
shift-clock frequency. The SBF always uses the normal read command when coming out of a
power-on/hard reset. However, when coming out of a soft reset, it is possible to use FAST_READ because
the SBF machine state is not lost.
For this reason, the SBFCR[FR] sticky bit may be set, causing the FAST_READ command to be issued
instead of the read command in the event of a soft reset. To enable the FAST_READ feature, set
SBFCR[FR] in the same write that sets the SBFCR[BLDIV] field. The value written to SBFCR[BLDIV]
should correspond to the frequency the SPI memory supports in FAST_READ mode. After a soft reset,
SBFCR[BLDIV] is not overwritten with the BLDIV[3:0] value read from the SPI memory. Instead, the
SBF uses the SBFCR[BLDIV] value to determin the SPI memory clock.
NOTE
The ability to use the FAST_READ command is limited by the SBF
electrical specifications. Specifically, delays present throughout the system
(including those between the SBF, the pin multiplexing logic, and the actual
I/O pads) effectively limit the maximum frequency at which the SBF
operates and can preclude use of the FAST_READ feature altogether. Even
when the delays within the processor itself are minimized, the actual SPI
memories may have similarly untenable electrical specifications (data input
setup and output valid times).
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
10-7
Serial Boot Facility (SBF)
MCF52277 Reference Manual, Rev 2
10-8
Freescale Semiconductor
Chapter 11
Reset Controller Module
11.1
Introduction
The reset controller determines the cause of reset, asserts the appropriate reset signals to the system, and
keeps a history of what caused the reset.
11.1.1
Block Diagram
Figure 11-1 illustrates the reset controller and is explained in these:
RESET
Pin
Power-On
Reset
Core Watchdog
Timer Timeout
RSTOUT
Pin
Reset
Controller
PLL
Loss of Lock
To Internal Resets
Software
Reset
Figure 11-1. Reset Controller Block Diagram
11.1.2
Features
Module features include the following:
• Five sources of reset:
— External
— Power-on reset (POR)
— Core watchdog timer
— Phase locked-loop (PLL) loss of lock
— Software
• Software-assertable RSTOUT pin independent of chip-reset state
• Software-readable status flags indicating the cause of the last reset
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
11-1
Reset Controller Module
11.2
External Signal Description
Table 11-1 provides a summary of the reset-controller signal properties. The signals are described in the
following paragraphs.
Table 11-1. Reset Controller Signal Properties
I/O
Pull-up1
Input
Hysteresis
Input
Synchronization
RESET
I
Active
Y
Y2
RSTOUT
O
—
—
—
Name
1
2
All pull-ups are disconnected when the signal is programmed as an output.
RESET is always synchronized except when in low-power stop mode.
11.2.1
RESET
Asserting the external RESET for at least four rising FB_CLK edges causes the external reset request to
be recognized and latched.
11.2.2
RSTOUT
This active-low output signal is driven low when the internal reset controller module resets the device. It
may take up to six FB_CLK edges after RESET assertion for RSTOUT to assert, due to an internal
synchronizer on RESET. When RSTOUT is active, the user can drive override options on the data bus. See
Chapter 9, “Chip Configuration Module (CCM),” for more details on these override options.
11.3
Memory Map/Register Definition
See Table 11-2 for the reset controller memory map and the following sections for register descriptions.
Table 11-2. Reset Controller Memory Map
Address
Register
Width
(bits)
Access Reset Value
Section/Page
0xFC0A_0000 Reset Control Register (RCR)
8
R/W
0x00
11.3.1/11-3
0xFC0A_0001 Reset Status Register (RSR)
8
R
See Section
11.3.2/11-3
MCF52277 Reference Manual, Rev 2
11-2
Freescale Semiconductor
Reset Controller Module
11.3.1
Reset Control Register (RCR)
The RCR allows software control for requesting a reset and for independently asserting the external
RSTOUT pin.
Address: 0xFC0A_0000 (RCR)
Access: User read/write
7
6
SOFTRST
FRCRSTOUT
0
0
R
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset:
Figure 11-2. Reset Control Register (RCR)
Table 11-3. RCR Field Descriptions
Field
Description
7
SOFTRST
Allows software to request a reset. The reset caused by setting this bit clears this bit.
1 Software reset request
0 No software reset request
6
Allows software to assert or negate the external RSTOUT pin.
FRCRSTOUT 1 Assert RSTOUT pin
0 Negate RSTOUT pin
Note: External logic driving reset configuration data during reset needs to be considered when asserting the
RSTOUT pin when setting FRCRSTOUT.
5–0
Reserved, must be cleared.
11.3.2
Reset Status Register (RSR)
The RSR contains a status bit for every reset source. When reset is entered, the cause of the reset condition
is latched, along with a value of 0 for the other reset sources that were not pending at the time of the reset
condition. These values are then reflected in RSR. One or more status bits may be set at the same time.
The cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset
condition.
RSR can be read at any time. Writing to RSR has no effect.
Address: 0xFC0A_0001 (RSR)
R
Access: User read-only
7
6
5
4
3
2
1
0
0
0
SOFT
0
POR
EXT
WDR
CORE
LOL
0
0
Reset
Dependent
0
Reset
Dependent
W
Reset:
Reset
Reset
Reset
Dependent Dependent Dependent
Figure 11-3. Reset Status Register (RSR)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
11-3
Reset Controller Module
Table 11-4. RSR Field Descriptions
Field
7–6
5
SOFT
4
Description
Reserved, must be cleared.
Software reset flag. Indicates the software caused last reset.
0 Last reset not caused by software
1 Last reset caused by software
Reserved, must be cleared.
3
POR
Power-on reset flag. Indicates power-on reset caused the last reset.
0 Last reset not caused by power-on reset
1 Last reset caused by power-on reset
2
EXT
External reset flag. Indicates that the last reset was caused by an external device or circuitry asserting the
external RESET pin.
0 Last reset not caused by external reset
1 Last reset caused by external reset
1
Core watchdog timer reset flag. Indicates the core watchdog timer timeout caused the last reset.
WDRCORE 0 Last reset not caused by watchdog timer timeout
1 Last reset caused by watchdog timer timeout
0
LOL
11.4
11.4.1
Loss-of-lock reset flag. Indicates the last reset state was caused by a PLL loss of lock.
0 Last reset not caused by loss of lock
1 Last reset caused by a loss of lock
Functional Description
Reset Sources
Table 11-5 defines the reset sources and the signals driven by the reset controller.
Table 11-5. Reset Source Summary
Source
Type
Power on
Asynchronous
External RESET pin (not stop mode)
Synchronous
External RESET pin (during stop mode)
Asynchronous
Core Watchdog timer
Synchronous
Loss of lock
Synchronous
Software
Synchronous
To protect data integrity, a synchronous reset source is not acted upon by the reset control logic until the
end of the current bus cycle. Reset is then asserted on the next rising edge of the system clock after the
cycle is terminated. Internal byte, word, or longword writes are guaranteed to complete without data
corruption when a synchronous reset occurs. External writes, including longword writes to 16-bit ports,
are also guaranteed to complete.
MCF52277 Reference Manual, Rev 2
11-4
Freescale Semiconductor
Reset Controller Module
Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does
not wait for the current bus cycle to complete. Reset is immediately asserted to the system.
11.4.1.1
Power-On Reset
At power up, the reset controller asserts RSTOUT. RSTOUT continues to be asserted until VDD has
reached a minimum acceptable level and, if PLL clock mode is selected, until the PLL achieves phase lock.
After approximately another 512 cycles (non-serial boot) or at the end of the serial boot sequence,
RSTOUT is negated and the device begins operation.
11.4.1.2
External Reset
Asserting the external RESET for at least four rising FB_CLK edges causes the external reset request to
be recognized and latched. After the RESET pin is negated and the PLL has acquired lock, the reset
controller asserts RSTOUT for approximately 512 bus clock cycles (non-serial boot) or for the duration of
the serial boot sequence. The device then exits reset and begins operation.
In low-power stop mode, the system clocks stop. Asserting the external RESET in stop mode causes an
external reset to be recognized asynchronously.
11.4.1.3
Core Watchdog Timer Reset
A core watchdog timer timeout causes the timer reset request to be recognized and latched. If the RESET
pin is negated and the PLL has acquired lock, the reset controller asserts RSTOUT for approximately 512
bus clock cycles (non-serial boot) or for the duration of the serial boot sequence. Then the device exits
reset and begins operation.
11.4.1.4
Loss-of-Lock Reset
This reset condition occurs when the PLL loses lock. After the PLL has acquired lock, the reset controller
asserts RSTOUT for approximately 512 bus clock cycles (non-serial boot) or for the duration of the serial
boot sequence. The device then exits reset and resumes operation.
11.4.1.5
Software Reset
A software reset occurs when the RCR[SOFTRST] bit is set. If the RESET is negated and the PLL has
acquired lock, the reset controller asserts RSTOUT for approximately 512 bus clock cycles (non-serial
boot) or for the duration of the serial boot sequence. Then the device exits reset and resumes operation.
11.4.2
Reset Control Flow
The reset logic control flow is shown in Figure 11-4. In this figure, the control state boxes have been
numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All
cycle counts given are approximate.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
11-5
Reset Controller Module
1
2
Power-on-Reset
Y
Loss Of Lock?
N
3
RESET
Pin or WD Timeout
or SW Reset?
Y
4
5
Assert RSTOUT and
Latch Reset Status
N
6
Assert RSTOUT and
Latch Reset Status
N
RESET Negated?
Y
7
N
PLL Locked?
Y
9
8
BOOTMOD[1:0] == 11?
(Serial Boot)
10
12
Negate RSTOUT
Y
Serial Boot Sequence
N
Wait 512 FB_CLK Cycles
11
BOOTMOD[1:0] == 10?
(Parallel RCON)
11A
Y
Latch Configuration
from FB_A[21:16] pins
N
Figure 11-4. Reset Control Flow
11.4.2.1
Synchronous Reset Requests
In this discussion, the reference in parentheses refer to the state numbers in Figure 11-4. All cycle counts
given are approximate.
MCF52277 Reference Manual, Rev 2
11-6
Freescale Semiconductor
Reset Controller Module
If the external device asserts the external RESET signal for at least four rising FB_CLK edges (3), if the
watchdog timer times out, or if software requests a reset, the reset control logic latches the reset request
internally. At this point the RSTOUT pin is asserted (5). (Even though the external RESET pin needs to
be asserted for only four FB_CLK edges, it may take up to six clocks beyond RESET assertion for
RSTOUT to assert.) The reset control logic waits until the RESET signal is negated (6) and for the PLL to
attain lock (7) before waiting 512 FB_CLK cycles (10) or for the duration of serial boot (9). For non-serial
boot, the reset control logic may latch the chip configuration options from the FB_A[21:16] pins (11, 11A).
RSTOUT is then negated (12).
If the external RESET signal is asserted by an external device for at least four rising FB_CLK edges during
the 512 count (10) or during the wait for PLL lock (7) or during serial boot (9), the reset flow switches to
(6) and waits for the RESET signal to be negated before continuing.
11.4.2.2
Asynchronous Reset Request
If reset is asserted by an asynchronous internal reset source, such as loss of lock (2) or power-on reset (1),
the reset control logic asserts RSTOUT (4). The reset control logic waits for the PLL to attain lock (7)
before waiting 512 bus clock cycles (10) or for the duration of serial boot (9). For non-serial boot, the reset
control logic may then latch the chip configuration options from the FB_A[21:16] pins (11, 11A).
RSTOUT is then negated (12).
If a loss of lock occurs during the 512 bus clock count (10) or during serial boot (9), the reset flow switches
to (7) and waits for the PLL to lock before continuing.
11.4.3
Concurrent Resets
This section describes the concurrent resets. As in the previous discussion references in parentheses refer
to the state numbers in Figure 11-4.
11.4.3.1
Reset Flow
If a power-on reset is detected during any reset sequence, the reset sequence starts immediately (1).
If the external RESET pin is asserted for at least four rising FB_CLK edges while waiting for PLL lock or
the 512 cycles or serial boot, the external reset is recognized. Reset processing switches to wait for the
external RESET pin to negate (6).
If a loss-of-lock condition is detected during the 512 cycle wait or during serial boot, the reset sequence
continues after a PLL lock (7).
11.4.3.2
Reset Status Flags
For a POR reset, the RSR[POR] bit is set, and all other RSR flags are cleared even if another type of reset
condition is pending or concurrently asserted.
If other reset sources are asserted after the RSR status bits have been latched (4 or 5), the device is held in
reset (9 or 10) until all sources have negated and the subsequent sources are not reflected in the RSR
contents.
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Freescale Semiconductor
11-7
Reset Controller Module
MCF52277 Reference Manual, Rev 2
11-8
Freescale Semiconductor
Chapter 12
System Control Module (SCM)
12.1
Introduction
This system control module (SCM) provides several control functions, including peripheral access control,
a software core watchdog timer, and generic access error information for the processor core.
12.1.1
Overview
The SCM provides programmable access protections for masters and peripherals. It allows the privilege
level of a master to be overridden, forcing it to user-mode privilege, and allows masters to be designated
as trusted or untrusted. Peripherals may be programmed to require supervisor privilege level for access,
may restrict access to a trusted master only, and may be write-protected.
The SCM’s core watchdog timer (CWT) provides a means of preventing system lockup due to
uncontrolled software loops via a special software service sequence. If periodic software servicing action
does not occur, the CWT times out with a programmed response (system reset or interrupt) to allow
recovery or corrective action to be taken.
Fault access reporting is also available within the SCM. The user can use these registers during the
resulting interrupt service routine and perform an appropriate recovery.
12.1.2
Features
The SCM includes these distinctive features:
• Access control registers
— Master privilege register (MPR)
— Peripheral access control registers (PACRs)
• System control registers
— Core watchdog control register (CWCR) for watchdog timer control
— Core watchdog service register (CWSR) to service watchdog timer
— SCM interrupt status register (SCMISR) to service a bus fault or watchdog interrupt
• Core fault reporting registers
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
12-1
System Control Module (SCM)
12.2
Memory Map/Register Definition
The memory map for the SCM registers is shown in Table 12-1.
Attempted accesses to reserved addresses result in a bus error, while attempted writes to read-only registers
are ignored and do not terminate with an error. Unless noted otherwise, writes to the programming model
must match the size of the register, e.g., an 8-bit register supports only 8-bit writes, etc. Attempted writes
of a different size than the register width produce a bus error and no change to the targeted register.
Table 12-1. SCM Memory Map
Address
Register
Access Reset Value
Section/Page
0xFC00_0000 Master Privilege Register (MPR)
32
R/W
0x7000_0007
12.2.1/12-2
0xFC00_0020 Peripheral Access Control Register A (PACRA)
32
R/W
0x5444_4444
12.2.2/12-3
0xFC00_0024 Peripheral Access Control Register B (PACRB)
32
R/W
0x4444_4444
12.2.2/12-3
0xFC00_0028 Peripheral Access Control Register C (PACRC)
32
R/W
0x4444_4444
12.2.2/12-3
0xFC00_002C Peripheral Access Control Register D (PACRD)
32
R/W
0x4444_4444
12.2.2/12-3
0xFC00_0040 Peripheral Access Control Register E (PACRE)
32
R/W
0x4444_4444
12.2.2/12-3
0xFC00_0044 Peripheral Access Control Register F (PACRF)
32
R/W
0x4444_4444
12.2.2/12-3
0xFC00_0048 Peripheral Access Control Register G (PACRG)
32
R/W
0x4444_4444
12.2.2/12-3
0xFC00_0050 Peripheral Access Control Register I (PACRI)
32
R/W
0x4400_0000
12.2.2/12-3
8
R/W
0x00
8.2.1/8-2
0xFC04_0016 Core Watchdog Control Register (CWCR)
16
R/W
0x0000
12.2.3/12-7
0xFC04_001B Core Watchdog Service Register (CWSR)
8
R/W
Undefined
12.2.4/12-8
0xFC04_001F SCM Interrupt Status Register (SCMISR)
8
R/W
0x00
12.2.5/12-8
0xFC04_0024 Burst Configuration Register (BCR)
32
R/W
0x0000_0000
12.2.6/12-9
0xFC04_0070 Core Fault Address Register (CFADR)
32
R
0x0000_0000
12.2.7/12-10
0xFC04_0075 Core Fault Interrupt Enable Register (CFIER)
8
R/W
0x00
12.2.8/12-10
0xFC04_0076 Core Fault Location Register (CFLOC)
8
R
Undefined
12.2.9/12-11
0xFC04_0077 Core Fault Attributes Register (CFATR)
8
R
Undefined
12.2.10/12-12
0xFC04_007C Core Fault Data Register (CFDTR)
32
R
Undefined
12.2.11/12-12
0xFC04_0013 Wakeup Control Register
1
Width
(bits)
(WCR)1
The WCR register is described in Chapter 8, “Power Management.”
12.2.1
Master Privilege Register (MPR)
The MPR specifies five 4-bit fields defining the access-privilege level associated with a bus master in the
device to the various peripherals listed in Table 12-4. The register provides one field per bus master.
MCF52277 Reference Manual, Rev 2
12-2
Freescale Semiconductor
System Control Module (SCM)
Address: 0xFC00_0000 (MPR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
MPROT0
0 0 0 0 0 0 0 0
MPROT1
MPROT4
8
7
0 0 0 0
6
5
4
MPROT6
3
2
1
0
MPROT7
Reset 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Figure 12-1. Master Privilege Register (MPR)
Each master is assigned depending on its connection to the various crossbar switch master ports.
Table 12-2. MPROTn Assignments
Crossbar Switch
Port Number
MPROTn
Master
M0
MPROT0
ColdFire Core
M1
MPROT1
eDMA Controller
M4
MPROT4
LCD Controller
M6
MPROT6
USB On-the-Go
M7
MPROT7
Serial Boot
The MPROTn field is defined as shown below.
3
R
2
1
0
MTR
MTW
MPL
0
W
Figure 12-2. MPROTn Fields
Table 12-3. MPROTn Field Descriptions
Field
3
Description
Reserved, must be cleared.
2
MTR
Master trusted for read. Determines whether the master is trusted for read accesses.
0 This master is not trusted for read accesses.
1 This master is trusted for read accesses.
1
MTW
Master trusted for writes. Determines whether the master is trusted for write accesses.
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
0
MPL
Master privilege level. Determines how the privilege level of the master is determined.
0 Accesses from this master are forced to user-mode.
1 Accesses from this master are not forced to user-mode.
12.2.2
Peripheral Access Control Registers (PACRx)
Each of the peripherals has a four-bit PACRn field that defines the access levels supported by the given
module. Eight PACRs are grouped together to form a 32-bit PACRx register (PACRA-PACRI). At reset
the SCM (PACR0) does not allow access from untrusted masters, while the other peripherals do.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
12-3
System Control Module (SCM)
Two global module enables are also available for the upper 63 Mbytes of address space
(0xFC00_0000–0xFFFF_FFFF) to allow for customization and expansion of addressed peripheral
devices. The access control register for these global enables is located in PACRI.
Address: 0xFC00_0020 (PACRA)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
PACR0
PACR1
PACR2
8
7
6
5
4
3
2
1
0
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Reset 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Figure 12-3. Peripheral Access Control Register A (PACRA)
Address: 0xFC00_0024 (PACRB)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
PACR8
8
7
6
5
4
3
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
2
1
0
PACR15
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Figure 12-4. Peripheral Access Control Register B (PACRB)
Address: 0xFC00_0028 (PACRC)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
PACR16
PACR17
PACR18
PACR19
0 1 0 0
8
7
PACR21
6
5
4
3
2
1
0
PACR23
PACR22
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Figure 12-5. Peripheral Access Control Register C (PACRC)
Address: 0xFC00_002C (PACRD)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
PACR24
PACR25
PACR26
0 1 0 0
PACR28
8
7
PACR29
6
5
4
3
PACR30
2
1
0
PACR31
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Figure 12-6. Peripheral Access Control Register D (PACRD)
Address: 0xFC00_0040 (PACRE)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
PACR32
PACR33
0 1 0 0 0 1 0 0
PACR36
PACR37
8
7
6
5
4
3
2
1
0
0 1 0 0 0 1 0 0
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Figure 12-7. Peripheral Access Control Register E (PACRE)
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
System Control Module (SCM)
Address: 0xFC00_0044 (PACRF)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
PACR40
PACR41
PACR42
PACR43
8
7
0 1 0 0
PACR44
6
5
4
3
2
1
0
PACR47
PACR46
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Figure 12-8. Peripheral Access Control Register F (PACRF)
Address: 0xFC00_0048 (PACRG)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
PACR48
8
7
6
5
4
3
2
1
0
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Figure 12-9. Peripheral Access Control Register G (PACRG)
Address: 0xFC00_0050 (PACRI)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
PACR64
PACR65
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-10. Peripheral Access Control Register I (PACRI)
Each peripheral is assigned to its PACRn field:
Table 12-4. PACRn Assignments
Slot Number
PACRn
Peripheral
0
PACR0
SCM (MPR & PACRs)
1
PACR1
Crossbar switch
2
PACR2
FlexBus
8
PACR8
FlexCAN
15
PACR15
Real-Time Clock
16
PACR16
SCM (CWT & Core Fault Registers)
17
PACR17
eDMA Controller
18
PACR18
Interrupt Controller 0
19
PACR19
Interrupt Controller 1
21
PACR21
Interrupt Controller IACK
22
PACR22
I2C
23
PACR23
DSPI
24
PACR24
UART0
25
PACR25
UART1
26
PACR26
UART2
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System Control Module (SCM)
Table 12-4. PACRn Assignments (continued)
Slot Number
PACRn
Peripheral
28
PACR28
DMA Timer 0
29
PACR29
DMA Timer 1
30
PACR30
DMA Timer 2
31
PACR31
DMA Timer 3
32
PACR32
PIT 0
33
PACR33
PIT 1
36
PACR36
PWM
37
PACR37
Edge Port
40
PACR40
CCM, Reset Controller, Power Management
41
PACR41
GPIO Module
42
PACR42
Touchscreen Controller
43
PACR43
LCD Controller
44
PACR44
USB On-the-Go
46
PACR46
SDRAM Controller
47
PACR47
SSI
48
PACR48
PLL
—
PACR64
Global Space 1
—
PACR65
Global Space 2
The PACRn field is defined as:
3
R
2
1
0
SP
WP
TP
0
W
Figure 12-11. PACRn Fields
Table 12-5. PACRn Field Descriptions
Field
3
2
SP
Description
Reserved, must be cleared.
Supervisor protect. Determines whether the peripheral requires supervisor privilege level for access.
0 This peripheral does not require supervisor privilege level for accesses.
1 This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate
supervisor access attribute, and the MPROTn[MPL] control bit for the master must be set. If not, access
terminates with an error response and no peripheral access initiates.
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System Control Module (SCM)
Table 12-5. PACRn Field Descriptions (continued)
Field
Description
1
WP
Write protect. Determines whether the peripheral allows write accesses
0 This peripheral allows write accesses.
1 This peripheral is write protected. If a write access is attempted, access terminates with an error response and
no peripheral access initiates.
0
TP
Trusted protect. Determines whether the peripheral allows accesses from an untrusted master.
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access
terminates with an error response and no peripheral access initiates.
12.2.3
Core Watchdog Control Register (CWCR)
The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer
interrupt. The register can be read or written at any time. At system reset, the software watchdog timer is
disabled.
Address: 0xFC04_0016 (CWCR)
15
R
W
Reset
RO
0
Access: User read/write
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
9
8
7
6
CW
CW
CWE
CIN16 RWH
0
0
0
5
4
3
CWRI
0
2
1
0
0
0
CWT
0
0
0
0
Figure 12-12. Core Watchdog Control Register (CWCR)
Table 12-6. CWCR Field Descriptions
Field
Description
15
RO
Read-only control bit.
0 CWCR can be read or written.
1 CWCR is read-only. A system reset is required to clear this register. The setting of this bit is intended to prevent
accidental writes of the CWCR from changing the defined core watchdog configuration.
14–10
Reserved, must be cleared.
9
Force CWT carry in 16. This control bit is intended for use only when testing the operation of the CWT. When set, it
CWCIN16 forces the actual timer to increment by 65537 (216 + 1) each cycle rather than by 1. It allows testing of large SWT
time-out values without actually incrementing through the entire range.
8
Core watchdog run while halted.
CWRWH 0 Core watchdog timer stops counting if the core is halted.
1 Core watchdog timer continues to count even while the core is halted.
7
CWE
Core watchdog timer enable.
0 CWT is disabled.
1 CWT is enabled.
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System Control Module (SCM)
Table 12-6. CWCR Field Descriptions (continued)
Field
Description
6–5
CWRI
Core watchdog reset/interrupt.
00 If a time-out occurs, the CWT generates an interrupt to the core. Refer to Chapter 15, “Interrupt Controller
Modules,” for details on setting its priority level.
01 The first time-out generates an interrupt to the processor, and if not serviced, a second time-out generates a
system reset and sets the RSR[WDRCORE] flag in the reset controller.
10 If a time-out occurs, the CWT generates a system reset and RSR[WDRCORE] in the reset controller is set.
11 The CWT functions in a “window” mode of operation. For this mode, the servicing of the CWSR must occur during
the last 25% of the time-out period. Any writes to the CWSR during the first 75% of the time-out period generate
an immediate system reset. Likewise, if the CWSR is not serviced during the last 25% of the time-out period, a
system reset is generated. For any type of reset response, the RSR[WDRCORE] flag is set.
4–0
CWT
Core watchdog time-out period. Selects the time-out period for the CWT. At reset, this field is cleared selecting the
minimum time-out period, but the CWT is disabled because CWCR[CWE] equals 0 at reset.
For CWCR[CWT] equal to n, the time-out period is 2n system clock cycles, where n equals 8–31. If n is less than 8,
then the time-out period is forced to 28.
12.2.4
Core Watchdog Service Register (CWSR)
The software watchdog service sequence must be performed using the CWSR as a data register to prevent
a CWT time-out. The service sequence requires two writes to this data register: a write of 0x55 followed
by a write of 0xAA. Both writes must be performed in this order prior to the CWT time-out, but any
number of instructions can be executed between the two writes. If the CWT has already timed out, writing
to this register has no effect in negating the CWT interrupt or reset. Figure 12-13 illustrates the CWSR. At
system reset, the contents of CWSR are uninitialized.
NOTE
If the CWT is enabled and has not timed out, then any write of a data value
other than 0x55 or 0xAA causes an immediate system reset, regardless of
the value in the CWCR[CWRI] field.
Address: 0xFC04_001B (CWSR)
7
6
Access: User read/write
5
4
3
2
1
0
—
—
—
—
R
CWSR
W
Reset:
—
—
—
—
Figure 12-13. Core Watchdog Service Register (CWSR)
12.2.5
SCM Interrupt Status Register (SCMISR)
For certain values in the CWCR[CWRI] field, the CWT generates an interrupt response to a time-out. For
these configurations, the SCMISR provides a program visible interrupt request from the watchdog timer.
During the interrupt service routine that manages this interrupt, the source must be explicitly cleared by
writing a 0x01 to the SCMISR.
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System Control Module (SCM)
The SCMISR also indicates system bus fault errors. An interrupt is sent only to the interrupt controller
when the CFIER[ECFEI] bit is set. The SCMISR[CFEI] bit flags fault errors independent of the
CFIER[ECFEI] setting. Therefore, if CFEI is set prior to setting ECFEI, an interrupt is requested
immediately after ECFEI is set.
Address: 0xFC04_001F (SCMISR)
R
Access: User read/write
7
6
5
4
3
2
1
0
0
0
0
0
0
0
CFEI
CWIC
w1c
w1c
0
0
W
Reset:
0
0
0
0
0
0
Figure 12-14. SCM Interrupt Status Register (SCMISR)
Table 12-7. SCMISR Field Descriptions
Field
Description
7–2
Reserved, must be cleared.
1
CFEI
Core fault error interrupt flag. Indicates if a bus fault has occurred. Writing a 1 clears this bit and negates the interrupt
request. Writing a 0 has no effect.
0 No bus error
1 A bus error has occurred. The faulting address, attributes (and possibly write data) are captured in the CFADR,
CFATR, and CFDTR registers. The error interrupt is enabled only if CFIER[ECFEI] is set.
Note: This bit reports core faults regardless of the setting of CFIER[ECFEI]. Therefore, if the error interrupt is
disabled and a core fault occurs, this bit is set. Then, if the error interrupt is subsequently enabled, an interrupt
is immediately requested. To prevent an undesired interrupt, clear the captured error by writing one to CFEI
before enabling the interrupt.
0
CWIC
Core watchdog interrupt flag. Indicates whether an CWT interrupt has occurred. Writing a 1 clears this bit and
negates the interrupt request. Writing a 0 has no effect.
0 No CWT interrupt has occurred.
1 CWT interrupt has occurred.
12.2.6
Burst Configuration Register (BCR)
The BCR register enables or disables the USB On-the-Go module for bursting to/from the crossbar switch
slave modules. There is an enable bit for each slave, and either direction (read and write) is supported via
the GBR and GBW bits.
Address: 0xFC04_0024 (BCR)
Access: User read-write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9
8
7
6
5
GBR GBW
0
0
4
3
2
1
0
0
0
0
SBE
0
0
0
0
0
Figure 12-15. Burst Configuration Register (BCR)
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System Control Module (SCM)
Table 12-8. BCR Field Descriptions
Field
31–10
Description
Reserved, must be cleared.
9
GBR
Global burst enable for reads. Allows bursts to happen on read transactions from the crossbar switch slaves to the
USB On-the-Go module.
0 Read bursts are disabled.
1 Read bursts are enabled.
Note: If GBR and GBW are cleared, then SBE is ignored.
8
GBW
Global burst enable for writes. Allows bursts to happen on write transactions to the crossbar switch slaves from the
USB On-the-Go module.
0 Write bursts are disabled.
1 Write bursts are enabled.
Note: If GBR and GBW are cleared, then SBE is ignored.
7–0
SBE
Slave burst enable. Allows bursts to happen to/from the crossbar switch slaves. The only valid settings for this field
are 0x00 or 0xFF.
0x00 Bursts disabled.
0xFF Bursts enabled. The GBR and GBW bits determine the burst direction. If neither is set, then this bit has no
effect.
Else Reserved.
12.2.7
Core Fault Address Register (CFADR)
The CFADR captures the address of the last core data access terminated with an error response. If the
faulting data transfer is a burst write, the captured fault address is valid only to the burst transfer size. For
example, if the data transfer was a 16-byte burst, the captured fault address is only valid to the modulo-16
address. The low-order four bits are undefined. This behavior is the result of the data pipelining typically
required to support burst writes in slave devices. This register can only be read; any attempted write is
ignored.
Address: 0xFC04_0070 (CFADR)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-16. Core Fault Address Register (CFADR)
Table 12-9. CFADR Field Descriptions
Field
31–0
ADDR
12.2.8
Description
Indicates the faulting address of the last core access terminated with an error response.
Core Fault Interrupt Enable Register (CFIER)
The CFIER register enables the system bus-error interrupt. See Chapter 15, “Interrupt Controller
Modules,” for more information on the interrupt controller.
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System Control Module (SCM)
Address: 0xFC04_0075 (CFIER)
R
Access: User read/write
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
ECFEI
W
Reset:
0
0
0
0
0
0
0
0
Figure 12-17. Core Fault Interrupt Enable Register (CFIER)
Table 12-10. CFIER Field Descriptions
Field
7–1
Description
Reserved, must be cleared.
0
ECFEI
12.2.9
Enable core fault error interrupt.
0 Do not generate an error interrupt on a faulted system bus cycle
1 Generate an error interrupt to the interrupt controller on a faulted system bus cycle
Core Fault Location Register (CFLOC)
The read-only CFLOC register indicates the exact location within the device of the captured fault
information.
Address: 0xFC04_0076 (CFLOC)
R
Access: User read-only
7
6
5
4
3
2
1
0
LOC
0
0
0
0
0
0
0
–
0
0
0
0
0
0
0
W
Reset:
Figure 12-18. Core Fault Location Register (CFLOC)
Table 12-11. CFLOC Field Descriptions
Field
Description
7
LOC
The location of the last captured fault.
0 Error occurred on the internal bus
1 Error occurred within the core
6–0
Reserved, must be cleared.
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System Control Module (SCM)
12.2.10 Core Fault Attributes Register (CFATR)
The read-only CFATR register captures the processor’s attributes of the last faulted core access to the
system bus.
Address: 0xFC04_0077 (CFATR)
7
R
6
WRITE
Access: User read-only
5
4
SIZE
3
2
1
0
0
0
MODE
TYPE
–
–
–
–
W
Reset:
–
–
–
–
Figure 12-19. Core Fault Attributes Register (CFATR)
Table 12-12. CFATR Field Descriptions
Field
7
WRITE
Description
Indicates the direction of the last faulted core access.
0 Core read access
1 Core write access
6–4
SIZE
Indicates the size of the last faulted core access.
000 8-bit core access
001 16-bit core access
010 32-bit core access
Else Reserved
3–2
Reserved, must be cleared.
1
MODE
Indicates the mode the device was in during the last faulted core access.
0 User mode
1 Supervisor mode
0
TYPE
Defines the type of last faulted core access.
0 Instruction
1 Data
12.2.11 Core Fault Data Register (CFDTR)
The read-only CFDTR captures the data associated with the last faulted processor write data access from
the device’s internal bus. The CFDTR is valid only for faulted internal write accesses. The contents of this
register are not valid if the last fault occurred on the core's local bus (CFLOC[LOC] = 1) or if the faulting
data transfer is a burst write because the captured data value is not guaranteed to be exactly associated with
the faulting transfer. This behavior is the result of the data pipelining needed to support burst writes in slave
devices.
This register is not updated on internal read access faults. This register can only be read; any attempted
write is ignored.
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System Control Module (SCM)
Address: 0xFC04_007C (CFDTR)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
CFDTR
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 12-20. Core Fault Data Register (CFDTR)
Table 12-13. CFDTR Field Descriptions
Field
Description
31–0
CFDTR
Contains data associated with the faulting access of the last internal bus write access. Contains the data value taken
directly from the write data bus.
12.3
12.3.1
Functional Description
Access Control
The SCM supports the traditional model of two privilege levels: supervisor and user. Typically, memory
references with the supervisor attribute have total accessibility to all the resources in the system, while user
mode references cannot access system control and configuration registers. In many systems, the operating
system executes in supervisor mode, while application software executes in user mode.
The SCM further partitions the access-control functions into two parts: one control register defines the
privilege level associated with each bus master (MPR), and another set of control registers define the
access levels associated with the peripheral modules (PACRx).
Each bus transaction targeted for the peripheral space is first checked to see if its privilege rights allow
access to the given memory space. If the privilege rights are correct, the access proceeds on the internal
bus. If the privilege rights are insufficient for the targeted memory space, the transfer is immediately
aborted and terminated with an exception, and the targeted module not accessed.
12.3.2
Core Watchdog Timer
The core watchdog timer (CWT) prevents system lockup if the software becomes trapped in a loop with
no controlled exit or if a bus transaction becomes hung. The core watchdog timer can be enabled through
CWCR[CWE]; it is disabled at reset. If enabled, the CWT requires the periodic execution of a core
watchdog servicing sequence. If this periodic servicing action does not occur, the timer expires and,
depending on the setting of CWCR[CWRI], different events may occur:
• An interrupt may be generated to the core.
• An immediate system reset.
• Upon the first time-out, a watchdog timer interrupt is asserted. If this time-out condition is not
serviced before a second time-out occurs, the CWT asserts a system reset. This configuration
supports a more graceful response to watchdog time-outs.
• In addition to these three basic modes of operation, the CWT also supports a windowed mode of
operation. In this mode, the time-out period is divided into four equal segments and the entire
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System Control Module (SCM)
service sequence of the CWT must occur during the last segment (last 25% of the time-out period).
If the timer is serviced anytime (any write to the CWSR register) in the first 75% of the time-out
period, an immediate system reset occurs.
To prevent the core watchdog timer from interrupting or resetting, the CWSR register must be serviced by
performing the following sequence:
1. Write 0x55 to CWSR.
2. Write 0xAA to CWSR.
Both writes must occur in order before the time-out, but any number of instructions can execute between
the two writes. This allows interrupts and exceptions to occur, if necessary, between the two writes.
NOTE
If the CWT is enabled and has not timed out, any write of a data value other
than 0x55 or 0xAA causes an immediate system reset, regardless of the
value in the CWCR[CWRI] field.
The timer value is constantly compared with the time-out period specified by CWCR[CWT], and any write
to the CWCR register resets the watchdog timer. In addition, a write-once control bit in the CWCR sets
the CWCR to read-only to prevent accidental updates to this control register from changing the desired
system configuration. After this bit, CWCR[RO], is set, a system reset is required to clear it.
For certain values in the CWCR[CWRI] field, the CWT generates an interrupt response to a time-out. For
these configurations, the SCMISR register provides a program visible interrupt request from the watchdog
timer. During the interrupt service routine that manages this interrupt, the source must be explicitly cleared
by writing a 0x01 to the SCMISR.
12.3.3
Core Data Fault Recovery Registers
To aid in recovery from certain types of access errors, the SCM module supports a number of registers that
capture access address, attribute, and data information on bus cycles terminated with an error response.
These registers can then be read during the resulting exception service routine and the appropriate recovery
performed.
The details on the core fault recovery registers are provided in the above sections. These registers are used
to capture fault recovery information on any processor-initiated system bus cycle terminated with an error.
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Chapter 13
Crossbar Switch (XBS)
13.1
Overview
This section provides information on the layout, configuration, and programming of the crossbar switch.
The crossbar switch connects the bus masters and bus slaves using a crossbar switch structure. This
structure allows bus masters to access different bus slaves simultaneously with no interference while
providing arbitration among the bus masters when they access the same slave. A variety of bus arbitration
methods and attributes may be programmed on a slave by slave basis.
The MCF5227x devices have up to five masters and three slaves (5Mx3S) connected to the crossbar
switch. The five masters are the ColdFire core, eDMA controller, LCD controller, USB OTG module, and
serial boot. The slaves are FlexBus/SDRAM controller, SRAM controller backdoor,and the peripheral bus
controller.
Figure 13-1 is a block diagram of the MCF5227x family bus architecture showing the crossbar switch
configuration.
ColdFire
Core
eDMA
Controller
LCD
Controller
USB
On-the-Go
M0
M1
M4
M6
Serial Boot
M7
Master Modules
Crossbar Switch
S1
S4
S7
FlexBus/SDRAM
Controller
SRAM
Backdoor
On-chip Slave
Peripherals
Slave Modules
Figure 13-1. Bus Architecture Block Diagram
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13-1
Crossbar Switch (XBS)
The modules are assigned to the numbered ports on the crossbar switch in the below table.
Table 13-1. Crossbar Switch Master/Slave Assignments
Master Modules
Crossbar Port
Module
Master 0 (M0)
ColdFire core
Master 1 (M1)
eDMA controller
Master 4 (M4)
LCD controller
Master 6 (M6)
USB On-the-Go
Master 7 (M7)
Serial boot
Slave Modules
Crossbar Port
Module
Address Range1
Slave 1 (S1)
Flexbus
SDRAM Controller
0x0000_0000–0x3FFF_FFFF &
0xC000_0000–0xDFFF_FFFF
0x4000_0000–0x7FFF_FFFF
Internal SRAM Backdoor
0x8000_0000–0x8FFF_FFFF
Slave 4 (S4)
Slave 7 (S7)
1
2
Other on-chip slave peripherals 0xF000_0000–0xFFFF_FFFF2
Unused address spaces are reserved.
See the various peripheral chapters for their memory maps. Any unused space by these
peripherals within this memory range is reserved and must not be accessed.
NOTE
This memory map provides two disjoint regions mapped to the FlexBus
controller to support glueless connections to external memories (e.g., flash
and SRAM) and a second space with one (or more) unique chip-selects that
can be used for non-cacheable, non-memory devices (addresses
0xC000_0000–0xDFFF_FFFF). Additionally, this mapping is easily maps
into the ColdFire access control registers, which provide a coarse
association between memory addresses and their attributes (e.g., cacheable,
non-cacheable). For this device, one possible configuration defines the
default memory attribute as non-cacheable, and one ACR then identifies
cacheable addresses, e.g., ADDR[31] equals 0 identifies the cacheable
space.
13.2
Features
The crossbar switch includes these distinctive features:
• Symmetric crossbar bus switch implementation
— Allows concurrent accesses from different masters to different slaves
— Slave arbitration attributes configured on a slave by slave basis
• 32 bits wide and supports byte, word (2 byte), longword (4 byte), and 16 byte burst transfers
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Crossbar Switch (XBS)
•
Operates at a 1-to-1 clock frequency with the bus masters
13.3
Modes of Operation
The crossbar switch supports two arbitration modes (fixed or round-robin), which may be set on a slave
by slave basis. Slaves configured for fixed arbitration mode have a unique arbitration level assigned to
each bus master.
In fixed priority mode, the highest priority active master accessing a particular slave is granted the master
bus path to that slave. A higher priority master blocks access to a given slave from a lower priority master
if the higher priority master continuously requests that slave. See Section 13.5.1.1, “Fixed-Priority
Operation.”
In round-robin arbitration, active masters accessing a particular slave are initially granted the slave based
on their master port number. Master priority is then modified in a wrap-around manner to give all masters
fair access to the slave. See Section 13.5.1.2, “Round-Robin Priority Operation.”
13.4
Memory Map / Register Definition
Two registers reside in each slave port of the crossbar switch. Read- and write-transfers require two bus
clock cycles. The registers can only be read from and written to in supervisor mode. Additionally, these
registers can only be read from or written to by 32-bit accesses.
A bus error response is returned if an unimplemented location is accessed within the crossbar switch. See
Section 12.2.5, “SCM Interrupt Status Register (SCMISR).”
The slave registers also feature a bit that, when set, prevents the registers from being written. The registers
remain readable, but future write attempts have no effect on the registers and are terminated with a bus
error response to the master initiating the write. The core, for example, takes a bus error interrupt.
Table 13-2 shows the memory map for the crossbar switch program-visible registers.
Table 13-2. XBS Memory Map
Address
Register
Width
Access
(bits)
Reset Value
Section/Page
0xFC00_4100 Priority Register Slave 1 (XBS_PRS1)
32
R/W
0x4302_0010
13.4.1/13-3
0xFC00_4110 Control Register Slave 1 (XBS_CRS1)
32
R/W
0x0000_0000
13.4.2/13-5
0xFC00_4400 Priority Register Slave 4 (XBS_PRS4)
32
R/W
0x4302_0010
13.4.1/13-3
0xFC00_4410 Control Register Slave 4 (XBS_CRS4)
32
R/W
0x0000_0000
13.4.2/13-5
0xFC00_4700 Priority Register Slave 7 (XBS_PRS7)
32
R/W
0x4302_0010
13.4.1/13-3
0xFC00_4710 Control Register Slave 7 (XBS_CRS7)
32
R/W
0x0000_0000
13.4.2/13-5
13.4.1
XBS Priority Registers (XBS_PRSn)
The priority registers (XBS_PRSn) set the priority of each master port on a per slave port basis and reside
in each slave port. The priority register can be accessed only with 32-bit accesses. After the
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
13-3
Crossbar Switch (XBS)
XBS_CRSn[RO] bit is set, the XBS_PRSn register can only be read; attempts to write to it have no effect
on XBS_PRSn and result in a bus-error response to the master initiating the write.
Additionally, no two available master ports may be programmed with the same priority level, including
reserved masters. Attempts to program two or more masters with the same priority level result in a
bus-error response (see Section 12.2.5, “SCM Interrupt Status Register (SCMISR)”) and the XBS_PRSn
is not updated.
Address: 0xFC00_4100 (XBS_PRS1)
0xFC00_4400 (XBS_PRS4)
0xFC00_4700 (XBS_PRS7)
Access: Supervisor read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0
W
M7
0
M6
0 0 0 0 0
M4
8
7
0 0 0 0 0 0 0 0 0
6
5
M1
4
3
0
2
1
0
M0
Reset 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 13-2. XBS Priority Registers Slave n (XBS_PRSn)
Table 13-3. XBS_PRSn Field Descriptions
Field
31
30–28
M7
27
Description
Reserved, must be cleared.
Master 7 (Serial Boot) priority. Sets the arbitration priority for this port on the associated slave port.
000 This master has level 1 (highest) priority when accessing the slave port.
001 This master has level 2 priority when accessing the slave port.
010 This master has level 3 priority when accessing the slave port.
011 This master has level 4 priority when accessing the slave port.
100 This master has level 5 priority when accessing the slave port.
101 This master has level 6 priority when accessing the slave port.
110 This master has level 7 (lowest) priority when accessing the slave port.ElseReserved
Reserved, must be cleared.
26–24
M6
Master 6 (USB OTG) priority. See M7 description.
23–19
Reserved, must be cleared.
18–16
M4
Master 4 (LCD Controller) priority. See M7 description.
15–7
Reserved, must be cleared.
6–4
M1
Master 1 (eDMA) priority. See M7 description.
3
2–0
M0
Reserved, must be cleared.
Master 0 (ColdFire core) priority. See M7 description.
MCF52277 Reference Manual, Rev 2
13-4
Freescale Semiconductor
Crossbar Switch (XBS)
NOTE
The possible values for the XBS_PRSn fields depend on the number of
masters available on the device. Because the device contains five masters,
valid values are 000 to 100. Unpredictable results occur when using the
reserved settings 101 to 111.
13.4.2
XBS Control Registers (XBS_CRSn)
The XBS control registers (XBS_CRSn) control several features of each slave port and must be accessed
using 32-bit accesses. After XBS_CRSn[RO] is set, the XBS_CRSn can only be read; attempts to write to
it have no effect and result in an error response.
Address: 0xFC00_4110 (XBS_PRS1)
0xFC00_4410 (XBS_PRS4)
0xFC00_4710 (XBS_PRS7)
31
R
W
RO1
Reset
0
1
Access: Supervisor read/write
30
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8
ARB
0
7
6
0 0
5
4
PCTL
3
0
2
1
0
PARK
0 0 0 0 0 0 0 0
After this bit is set, only a hardware reset clears it.
Figure 13-3. XBS Control Registers Slave n (XBS_CRSn)
Table 13-4. XBS_CRSn Field Descriptions
Field
Description
31
RO
Read only. Forces both of the slave port’s registers (XBS_CRSn and XBS_PRSn) to be read-only. After set, only a
hardware reset clears it.
0 Both of the slave port’s registers are writeable.
1 Both of the slave port’s registers are read-only and cannot be written (attempted writes have no effect on the
registers and result in a bus error response).
30–9
Reserved, must be cleared.
8
ARB
Arbitration Mode. Selects the arbitration policy for the slave port.
0 Fixed priority
1 Round robin (rotating) priority
7–6
Reserved, must be cleared.
5–4
PCTL
Parking control. Determines the slave port’s parking control. The low-power park feature results in an overall power
savings if the slave port is not saturated; however, this forces an extra latency clock when any master tries to access
the slave port while not in use because it is not parked on any master.
00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit
field.
01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave
port.
10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to
a constant safe state.
11 Reserved.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
13-5
Crossbar Switch (XBS)
Table 13-4. XBS_CRSn Field Descriptions (continued)
Field
3
2–0
PARK
13.5
Description
Reserved, must be cleared.
Park. Determines which master port the current slave port parks on when no masters are actively making requests
and the PCTL bits are cleared.
000 Park on master port M0 (ColdFire Core)
001 Park on master port M1 (eDMA Controller)
010 Reserved
011 Reserved
100 Park on master port M4 (LCD Controller)
101 Reserved
110 Park on master port M6 (USB OTG)
111 Park on master port M7 (Serial Boot)
Functional Description
13.5.1
Arbitration
The crossbar switch supports two arbitration schemes: a simple fixed-priority comparison algorithm and
a simple round-robin fairness algorithm. The arbitration scheme is independently programmable for each
slave port.
13.5.1.1
Fixed-Priority Operation
When operating in fixed-priority mode, each master is assigned a unique priority level in the XBS_PRSn
(priority registers). If two masters request access to a slave port, the master with the highest priority in the
selected priority register gains control over the slave port.
When a master makes a request to a slave port, the slave port checks if the new requesting master’s priority
level is higher than that of the master that currently has control over the slave port (unless the slave port is
in a parked state). The slave port does an arbitration check at every bus transfer boundary makes certain
that the proper master (if any) has control of the slave port.
If the new requesting master’s priority level is higher than that of the master that currently has control of
the slave port, the new requesting master is granted control over the slave port at the next clock edge. The
exception to this rule is if the master that currently has control over the slave port is running a fixed length
burst transfer or a locked transfer. In this case, the new requesting master must wait until the end of the
burst transfer or locked transfer before it is granted control of the slave port.
If the new requesting master’s priority level is lower than the master that currently has control of the slave
port, the new requesting master is forced to wait until the current master runs one of the following cycles:
• An IDLE cycle
• A non-IDLE cycle to a location other than the current slave port.
MCF52277 Reference Manual, Rev 2
13-6
Freescale Semiconductor
Crossbar Switch (XBS)
13.5.1.2
Round-Robin Priority Operation
When operating in round-robin mode, each master is assigned a relative priority based on the master port
number. This priority is based on how far ahead the master port number of the requesting master is to the
master port number of the current bus master for this slave. Master port numbers are compared modulo the
total number of bus masters, i.e. take the requesting master port number minus the current bus master’s
port number modulo the total number of bus masters. The master port with the highest priority based on
this comparison is granted control over the slave port at the next bus transfer boundary.
After granted access to a slave port, a master may perform as many transfers as desired to that port until
another master makes a request to the same slave port. The next master in line is granted access to the slave
port at the next transfer boundary.
Parking may continue to be used in a round-robin mode, but does not affect the round-robin pointer unless
the parked master actually performs a transfer. Handoff occurs to the next master in line after one cycle of
arbitration. If the slave port is put into low-power park mode, the round-robin pointer is reset to point at
master port 0, giving it the highest priority.
13.5.1.3
Priority Assignment
Each master port needs to be assigned a unique 3-bit priority level. If an attempt is made to program
multiple master ports with the same priority level within the priority registers (XBS_PRSn) the crossbar
switch responds with a bus error (refer to Section 12.2.5, “SCM Interrupt Status Register (SCMISR)”) and
the registers are not updated.
13.6
Initialization/Application Information
No initialization is required by or for the crossbar switch. Hardware reset ensures all the register bits used
by the crossbar switch are properly initialized to a valid state. Settings and priorities should be
programmed to achieve maximum system performance.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
13-7
Crossbar Switch (XBS)
MCF52277 Reference Manual, Rev 2
13-8
Freescale Semiconductor
Chapter 14
General Purpose I/O Module
14.1
Introduction
Many of the pins associated with the device may be used for several different functions. Their primary
functions are to provide external interfaces to access off-chip resources. When not used for their primary
function, many of the pins may be used as general-purpose digital I/O (GPIO) pins. In some cases, the pin
function is set by the operating mode, and the alternate pin functions are not supported.
14.1.1
Block Diagram
Each GPIO port has registers that configure, monitor, and control the port pins. Figure 14-1 is a block
diagram of the device ports.
NOTE
The GPIO functionality of the port IRQ pins is selected by the edge port
module. They are shown in the below figure only for completeness.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-1
General Purpose I/O Module
Port
FBCTL
FB_OE / PFBCTL3
FB_TA / PFBCTL2
FB_R/W / PFBCTL1
FB_TS / DACK0 / PFBCTL0
Port
BE
FB_BE/BWE[3:0] / PBE[3:0]
Port
CS
FB_CS[3:2] / PCS[3:2]
FB_CS1 / SD_CS1 / PCS1
FB_CS0 / PCS0
Port
DSPI
DSPI_PCS0/SS / U2RTS / PDSPI3
DSPI_SIN / U2RXD / PDSPI2
DSPI_SOUT / U2TXD / PDSPI1
DSPI_SCK / U2CTS / PDSPI0
Port
UART
U1CTS / LCD_CLS / SSI_BCLK / PUART7
U1RTS / LCD_PS / SSI_FS / PUART6
U1TXD / SSI_TXD / PUART5
U1RXD / SSI_RXD / PUART4
U0CTS / USB_VBUS_EN / T1OUT / PUART3
U0RTS / USB_VBUS_OC / T1IN / PUART2
U0TXD / CANTX / PUART1
U0RXD / CANRX / PUART0
Port
I2C
I2C_SCL / U2TXD / CANTX / PI2C1
I2C_SDA / U2RXD / CANRX / PI2C0
Port
LCD
DATAH
LCD_D[17:16] / LCD_D[11:10] / PLCDDH[1:0]
Port
LCD
DATAM
LCD_D[15:14] / LCD_D[9:8] / PLCDDM[7:6]
LCD_D13 / CANTX / PLCDDM5
LCD_D12 / CANRX / PLCDDM4
LCD_D[11:8] / LCD_D[7:4] / PLCDDM[3:0]
Port
LCD
DATAL
LCD_D7 / PWM7 / PLCDDL7
LCD_D6 / PWM5 / PLCDDL6
LCD_D[5:2] / LCD_D[3:0] / PLCDDL[5:2]
LCD_D1 / PWM3 / PLCDDL1
LCD_D0 / PWM1 / PLCDDL0
Port
LCDCTL
Port
TIMER
Port
IRQ
LCD_ACD/OE / LCD_SPL_SPR / PLCDCTL3
LCD_FLM/VSYNC / PLCDCTL2
LCD_LP/HYSNC / PLCDCTL1
LCD_LSCLK / PLCDCTL0
T3IN / T3OUT / SSI_MCLK / PTIMER3
T2IN / T2OUT / DSPI_PCS2 / PTIMER2
T1IN / T1OUT / LCD_CONTRAST / PTIMER1
T0IN / T0OUT / LCD_REV / PTIMER0
IRQ4 / DREQ0 / PIRQ4
IRQ1 / SSI_CLKIN / USB_CLKIN / PIRQ1
Pin Assignment and
Drive Strength Control
Internal Bus
Figure 14-1. Ports Module Block Diagram
14.1.2
Overview
The GPIO module controls the configuration for various external pins, including those used for:
• External bus accesses
• External device selection
• LCD
• I2C serial control
• DSPI
• SSI
• USB
• UART
• 32-bit DMA timers
14.1.3
Features
The ports module includes these distinctive features:
• Control of primary function use
— On all supported GPIO ports, except those for FB_AD[31:0] pins
MCF52277 Reference Manual, Rev 2
14-2
Freescale Semiconductor
General Purpose I/O Module
•
•
14.2
— On pins whose GPIO is not supported by ports module: IRQ[7,4,1]
General purpose I/O support for all ports
— Registers for storing output pin data
— Registers for controlling pin data direction
— Registers for reading current pin state
— Registers for setting and clearing output pin data registers
Control of functional pad drive strengths and slew rate modes
External Signal Description
The GPIO module controls the functionality of several external pins. These pins are listed in Table 14-2
under the GPIO column.
Refer to the Chapter 2, “Signal Descriptions,” for more detailed descriptions of these pins and other pins
not controlled by the ports module. The function of most of the pins (primary function, GPIO, etc.) is
determined by the ports module pin assignment registers (PAR_x).
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., FB_A23), while designations for
multiple signals within a group use brackets (i.e., FB_A[23:21]) and is
meant to include all signals within the two bracketed numbers when these
numbers are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Most pins that are muxed with GPIO will default to their GPIO
functionality. See Table 14-1 for a list of the exceptions.
Table 14-1. Special-Case Default Signal Functionality
Pin
Default Signal
FB_BE/BWE[3:0]
FB_BE/BWE[3:0]
FB_CS[3:0]
FB_CS[3:0]
FB_OE
FB_OE
FB_TA
FB_TA
FB_R/W
FB_R/W
FB_TS
FB_TS
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-3
General Purpose I/O Module
Pull-up (U)1
Pull-down (D)
Direction2
Voltage
Domain
Table 14-2. MCF5227x Signal Information and Muxing
MCF52274
176 LQFP
RESET
—
—
—
U
I
EVDD
103
J11
RSTOUT
—
—
—
—
O
EVDD
102
K11
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52277
196 MAPBGA
Reset
Clock
EXTAL
—
—
—
—
I
EVDD
106
F14
XTAL
—
—
—
U3
O
EVDD
105
G14
—
I
EVDD
110, 109
G10, H10
Mode Selection
BOOTMOD[1:0]
—
—
—
FlexBus
FB_A[23:22]
—
FB_CS[5:4]
—
—
O
SDVDD
143, 142
C11, D11
FB_A[21:16]
—
—
—
—
O
SDVDD
141–139,
137–135
A12, B12, C12,
B13, A13, A14
FB_A[15:14]
—
SD_BA[1:0]
—
—
O
SDVDD
131, 130
B14, C13
FB_A[13:11]
—
SD_A[13:11]
—
—
O
SDVDD
129–127
C14, D12, D13
FB_A10
—
—
—
O
SDVDD
126
D14
FB_A[9:0]
—
SD_A[9:0]
—
O
SDVDD
125–116
E11–E14,
F11–F13, G11,
G12, H11
FB_D[31:16]
—
SD_D[31:16]
—
I/O
SDVDD
30–37, 49–56
J4, K1–K4, L1–L3,
M3, N3, P3,M4,
N4, P4, L5, M5
FB_D[15:0]
—
FB_D[31:16]
—
I/O
SDVDD
19–26, 60–67
G1–G4, H1–H4,
M6, N6, P6, L7,
M7, N7, P7, L8
FB_CLK
—
—
—
O
SDVDD
42
P1
FB_BE/BWE[3:0]
PBE[3:0]
SD_DQM[3:0]
—
—
O
SDVDD
29, 57, 27, 59
J3, N5, J1, L6
FB_CS[3:2]
PCS[3:2]
—
—
—
O
SDVDD
—
B11, A11
FB_CS1
PCS1
SD_CS1
—
—
O
SDVDD
144
D10
FB_CS0
PCS0
—
—
—
O
SDVDD
145
C10
FB_OE
PFBCTL3
—
—
—
O
SDVDD
69
N8
FB_TA
PFBCTL2
—
—
U
I
SDVDD
115
H12
FB_R/W
PFBCTL1
—
—
—
O
SDVDD
68
M8
FB_TS
PFBCTL0
DACK0
—
—
O
SDVDD
15
F4
MCF52277 Reference Manual, Rev 2
14-4
Freescale Semiconductor
General Purpose I/O Module
Pull-up (U)1
Pull-down (D)
Direction2
Voltage
Domain
Table 14-2. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
SD_A10
—
—
—
—
O
SDVDD
46
L4
SD_CAS
—
—
—
—
O
SDVDD
47
N2
SD_CKE
—
—
—
—
O
SDVDD
17
F2
SD_CLK
—
—
—
—
O
SDVDD
40
M1
SD_CLK
—
—
—
—
O
SDVDD
41
N1
SD_CS0
—
—
—
—
O
SDVDD
18
F1
SD_DQS[3:2]
—
—
—
—
I/O
SDVDD
28, 58
J2, P5
SD_RAS
—
—
—
—
O
SDVDD
48
P2
SD_SDR_DQS
—
—
—
—
O
SDVDD
38
M2
SD_WE
—
—
—
—
O
SDVDD
16
F3
—
—
I
EVDD
162
D7
I
EVDD
161
C7
Signal Name
GPIO
Alternate 1
Alternate 2
MCF52277
196 MAPBGA
SDRAM Controller
External Interrupts Port4
IRQ7
PIRQ7
—
IRQ4
PIRQ4
DREQ0
DSPI_PCS4
5
IRQ1
PIRQ1
USB_CLKIN
SSI_CLKIN
—
I
EVDD
160
B7
LCD Controller6
LCD_D[17:16]6
PLCDDH[1:0]
LCD_D[11:10]
—
—
O
EVDD
9, 8
E3, E4
LCD_D[15:14]6
PLCDDM[7:6]
LCD_D[9:8]
—
—
O
EVDD
7, 6
D1, D2
LCD_D13
PLCDDM5
CANTX
—
—
O
EVDD
—
C1
LCD_D12
PLCDDM4
CANRX
—
—
O
EVDD
—
C2
LCD_D[11:8]6
PLCDDM[3:0]
LCD_D[7:4]
—
—
O
EVDD
5–2
D3, C3, D4, B1
LCD_D7
PLCDDL7
PWM7
—
—
O
EVDD
—
B2
LCD_D6
PLCDDL6
PWM5
—
—
O
EVDD
—
A1
LCD_D[5:2]6
PLCDDL[5:2]
LCD_D[3:0]
—
—
O
EVDD
175–172
A2, A3, B3, A4
LCD_D1
PLCDDL1
PWM3
—
—
O
EVDD
—
B4
LCD_D0
PLCDDL0
PWM1
—
—
O
EVDD
—
C4
LCD_ACD/
LCD_OE
PLCDCTL3
LCD_SPL_SPR
—
—
O
EVDD
169
B5
LCD_FLM/
LCD_VSYNC
PLCDCTL2
—
—
—
O
EVDD
10
E2
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-5
General Purpose I/O Module
Alternate 1
Alternate 2
LCD_LP/
LCD_HSYNC
PLCDCTL1
—
—
—
LCD_LSCLK
PLCDCTL0
—
—
—
Voltage
Domain
GPIO
Direction2
Signal Name
Pull-up (U)1
Pull-down (D)
Table 14-2. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
O
EVDD
11
E1
O
EVDD
170
A5
USB On-the-Go
USB_DM
—
—
—
—
O
USB
VDD
149
A9
USB_DP
—
—
—
—
O
USB
VDD
150
A10
Real Time Clock
RTC_EXTAL
—
—
—
—
I
EVDD
100
J14
RTC_XTAL
—
—
—
—
O
EVDD
99
K14
Touchscreen Controller
ADC_IN[7:0]
—
—
—
—
I
VDD_
ADC
82–85, 87–90
P12, N12, P13,
N13, P14, N14,
M13, M14
ADC_REF
—
—
—
—
I
VDD_
ADC
86
M12
I2C
I2C_SCL
PI2C1
CANTX
U2TXD
U
I/O
EVDD
168
C5
I2C_SDA
PI2C0
CANRX
U2RXD
U
I/O
EVDD
167
D5
DSPI7
DSPI_PCS0/SS
PDSPI3
U2RTS
—
U
I/O
EVDD
152
B9
DSPI_SIN
PDSPI2
U2RXD
SBF_DI
8
I
EVDD
155
D8
DSPI_SOUT
PDSPI1
U2TXD
SBF_D0
—
O
EVDD
154
D9
DSPI_SCK
PDSPI0
U2CTS
SBF_CK
—
I/O
EVDD
153
C9
UARTs
U1CTS
PUART7
SSI_BCLK
LCD_CLS
—
I
EVDD
156
C8
U1RTS
PUART6
SSI_FS
LCD_PS
—
O
EVDD
157
B8
U1TXD
PUART5
SSI_TXD
—
—
O
EVDD
159
A7
U1RXD
PUART4
SSI_RXD
—
—
I
EVDD
158
A8
U0CTS
PUART3
DT1OUT
USB_VBUS_EN
—
I
EVDD
97
K12
U0RTS
PUART2
DT1IN
USB_VBUS_OC
—
O
EVDD
98
J12
MCF52277 Reference Manual, Rev 2
14-6
Freescale Semiconductor
General Purpose I/O Module
Alternate 1
Alternate 2
U0TXD
PUART1
CANTX
—
—
U0RXD
PUART0
CANRX
—
—
Voltage
Domain
GPIO
Direction2
Signal Name
Pull-up (U)1
Pull-down (D)
Table 14-2. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
O
EVDD
95
L12
I
EVDD
96
K13
DMA Timers
DT3IN
PTIMER3
DT3OUT
SSI_MCLK
—
I
EVDD
163
D6
DT2IN/SBF_CS7
PTIMER2
DT2OUT
DSPI_PCS2
—
I
EVDD
164
C6
DT1IN
PTIMER1
DT1OUT
LCD_CONTRAST
—
I
EVDD
165
B6
DT0IN
PTIMER0
DT0OUT
LCD_REV
—
I
EVDD
166
A6
BDM/JTAG9
PST[3:0]
—
—
—
—
O
EVDD
—
L9, M9, N9, P9
DDATA[3:0]
—
—
—
—
O
EVDD
—
L10, M10, N10,
P10
ALLPST
—
—
—
—
O
EVDD
76
—
JTAG_EN
—
—
—
D
I
EVDD
79
K10
PSTCLK
—
TCLK
—
U
O
EVDD
74
P8
DSI
—
TDI
—
U
I
EVDD
78
M11
DSO
—
TDO
—
—
O
EVDD
81
L11
BKPT
—
TMS
—
U
I
EVDD
80
N11
DSCLK
—
TRST
—
U
I
EVDD
77
P11
—
D
I
EVDD
134
E10
Test
TEST
—
—
Power Supplies
IVDD
—
—
—
—
—
—
39, 75, 114, 138,
171
K5, F10, E5, J10
EVDD
—
—
—
—
—
—
12, 72, 73, 94,
111, 148, 176
E6, E7, F5, F6,
G5, H9, J9, K8, K9
SD_VDD
—
—
—
—
—
—
14, 43, 44, 70,
113, 132, 146
E8, E9, F9, G9,
H5, J5, J6, K6, K7
VDD_OSC
—
—
—
—
—
—
108
G13
VDD_PLL
—
—
—
—
—
—
104
H14
VDD_USB
—
—
—
—
—
—
151
B10
VDD_RTC
—
—
—
—
—
—
101
J13
VDD_ADC
—
—
—
—
—
—
91
L13
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-7
General Purpose I/O Module
1
2
3
4
5
6
7
8
9
Alternate 1
Alternate 2
VSS
—
—
—
—
VSS_OSC
—
—
—
—
VSS_ADC
—
—
—
—
Voltage
Domain
GPIO
Direction2
Signal Name
Pull-up (U)1
Pull-down (D)
Table 14-2. MCF5227x Signal Information and Muxing (continued)
MCF52274
176 LQFP
MCF52277
196 MAPBGA
—
—
1, 13, 45, 71, 93,
112, 133, 147
F7, F8, G6–G8,
H6–H8, J7, J8
—
—
107
H13
—
—
92
L14
Pull-ups are generally only enabled on pins with their primary function, except as noted.
Refers to pin’s primary function.
Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.
Pull-up when DREQ controls the pin.
The 176 LQFP device only supports a 12-bit LCD data bus.
DSPI or SBF signal functionality is controlled by RESET. When asserted, these pins are configured for serial boot; when negated, the
pins are configured for DSPI.
Pull-up when the serial boot facility (SBF) controls the pin.
If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these
pins.
It should be noted from Table 14-2 that there are several cases where a function is available on more than
one pin. While it is possible to enable the function on more than one pin simultaneously, this type of
programming should be avoided for input functions to prevent unexpected behavior. All multiple-pin
functions are listed in Table 14-3.
Table 14-3. Multiple-Pin Functions
Function
Direction
Associated Pins
U2RXD
I
I2C_SDA, DT3IN
U2TXD
O
I2C_SCL, DT2IN
CANRX
I
U0RXD, I2C_SDA, LCD_D12
CANTX
O
UOTXD, I2C_SCL, LCD_D13
DT1IN
I
DT1IN, U0RTS
MCF52277 Reference Manual, Rev 2
14-8
Freescale Semiconductor
General Purpose I/O Module
14.3
Memory Map/Register Definition
Table 14-4 summarizes all the registers in the ports address space.
Table 14-4. GPIO Module Memory Map
Address
Register
Width
Access Reset Value
(bits)
Section/Page
Port Output Data Registers
0xFC0A_4000 PODR_BE
8
R/W
0x0F
14.3.1/14-11
0xFC0A_4001 PODR_CS
8
R/W
0x0F
14.3.1/14-11
0xFC0A_4002 PODR_FBCTL
8
R/W
0x0F
14.3.1/14-11
0xFC0A_4003 PODR_I2C
8
R/W
0x03
14.3.1/14-11
0xFC0A_4005 PODR_UART
8
R/W
0xFF
14.3.1/14-11
0xFC0A_4006 PODR_DSPI
8
R/W
0x0F
14.3.1/14-11
0xFC0A_4007 PODR_TIMER
8
R/W
0x0F
14.3.1/14-11
0xFC0A_4008 PODR_LCDCTL
8
R/W
0x0F
14.3.1/14-11
0xFC0A_4009 PODR_LCDDATAH
8
R/W
0x03
14.3.1/14-11
0xFC0A_400A PODR_LCDDATAM
8
R/W
0xFF
14.3.1/14-11
0xFC0A_400B PODR_LCDDATAL
8
R/W
0xFF
14.3.1/14-11
Port Data Direction Registers
0xFC0A_400C PDDR_BE
8
R/W
0x00
14.3.2/14-12
0xFC0A_400D PDDR_CS
8
R/W
0x00
14.3.2/14-12
0xFC0A_400E PDDR_FBCTL
8
R/W
0x00
14.3.2/14-12
0xFC0A_400F PDDR_I2C
8
R/W
0x00
14.3.2/14-12
0xFC0A_4011 PDDR_UART
8
R/W
0x00
14.3.2/14-12
0xFC0A_4012 PDDR_DSPI
8
R/W
0x00
14.3.2/14-12
0xFC0A_4013 PDDR_TIMER
8
R/W
0x00
14.3.2/14-12
0xFC0A_4014 PDDR_LCDCTL
8
R/W
0x00
14.3.2/14-12
0xFC0A_4015 PDDR_LCDDATAH
8
R/W
0x00
14.3.2/14-12
0xFC0A_4016 PDDR_LCDDATAM
8
R/W
0x00
14.3.2/14-12
0xFC0A_4017 PDDR_LCDDATAL
8
R/W
0x00
14.3.2/14-12
Port Pin Data/Set Data Registers
0xFC0A_4018 PPDSDR_BE
8
R/W
See Section
14.3.3/14-13
0xFC0A_4019 PPDSDR_CS
8
R/W
See Section
14.3.3/14-13
0xFC0A_401A PPDSDR_FBCTL
8
R/W
See Section
14.3.3/14-13
0xFC0A_401B PPDSDR_I2C
8
R/W
See Section
14.3.3/14-13
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-9
General Purpose I/O Module
Table 14-4. GPIO Module Memory Map (continued)
Address
Register
Width
Access Reset Value
(bits)
Section/Page
0xFC0A_401D PPDSDR_UART
8
R/W
See Section
14.3.3/14-13
0xFC0A_401E PPDSDR_DSPI
8
R/W
See Section
14.3.3/14-13
0xFC0A_401F PPDSDR_TIMER
8
R/W
See Section
14.3.3/14-13
0xFC0A_4020 PPDSDR_LCDCTL
8
R/W
See Section
14.3.3/14-13
0xFC0A_4021 PPDSDR_LCDDATAH
8
R/W
See Section
14.3.3/14-13
0xFC0A_4022 PPDSDR_LCDDATAM
8
R/W
See Section
14.3.3/14-13
0xFC0A_4023 PPDSDR_LCDDATAL
8
R/W
See Section
14.3.3/14-13
Port Clear Output Data Registers
0xFC0A_4024 PCLRR_BE
8
W
0x00
14.3.4/14-15
0xFC0A_4025 PCLRR_CS
8
W
0x00
14.3.4/14-15
0xFC0A_4026 PCLRR_FBCTL
8
W
0x00
14.3.4/14-15
0xFC0A_4027 PCLRR_I2C
8
W
0x00
14.3.4/14-15
0xFC0A_4029 PCLRR_UART
8
W
0x00
14.3.4/14-15
0xFC0A_402A PCLRR_DSPI
8
W
0x00
14.3.4/14-15
0xFC0A_402B PCLRR_TIMER
8
W
0x00
14.3.4/14-15
0xFC0A_402C PCLRR_LCDCTL
8
W
0x00
14.3.4/14-15
0xFC0A_402D PCLRR_LCDDATAH
8
W
0x00
14.3.4/14-15
0xFC0A_402E PCLRR_LCDDATAM
8
W
0x00
14.3.4/14-15
0xFC0A_402F PCLRR_LCDDATAL
8
W
0x00
14.3.4/14-15
Pin Assignment Registers
0xFC0A_4030 PAR_BE
8
R/W
0x0F
14.3.5.1/14-16
0xFC0A_4031 PAR_CS
8
R/W
0x1F
14.3.5.2/14-16
0xFC0A_4032 PAR_FBCTL
8
R/W
0xF8
14.3.5.3/14-17
0xFC0A_4033 PAR_I2C
8
R/W
0x00
14.3.5.4/14-18
0xFC0A_4034 PAR_UART
16
R/W
0x0000
14.3.5.5/14-18
0xFC0A_4036 PAR_DSPI
8
R/W
0x00
14.3.5.6/14-19
0xFC0A_4037 PAR_TIMER
8
R/W
0x00
14.3.5.7/14-20
0xFC0A_4038 PAR_LCDCTL
8
R/W
0x00
14.3.5.8/14-20
0xFC0A_4039 PAR_IRQ
8
R/W
0x00
14.3.5.9/14-21
0xFC0A_403C PAR_LCDH
32
R/W
0x0000_0000 14.3.5.10/14-22
0xFC0A_4040 PAR_LCDL
32
R/W
0x0000_0000 14.3.5.11/14-22
MCF52277 Reference Manual, Rev 2
14-10
Freescale Semiconductor
General Purpose I/O Module
Table 14-4. GPIO Module Memory Map (continued)
Address
Width
Access Reset Value
(bits)
Register
Section/Page
Mode Select Control Registers
0xFC0A_4044 MSCR_FLEXBUS
8
R/W
0x3F
14.3.6/14-23
0xFC0A_4045 MSCR_SDRAM
8
R/W
0x3F
14.3.7/14-24
Drive Strength Control Registers
0xFC0A_4048 DSCR_DSPI
8
R/W
See Section
14.3.8/14-25
0xFC0A_4049 DSCR_TIMER
8
R/W
See Section
14.3.8/14-25
0xFC0A_404A DSCR_I2C
8
R/W
See Section
14.3.8/14-25
0xFC0A_404B DSCR_LCD
8
R/W
See Section
14.3.8/14-25
0xFC0A_404C DSCR_DEBUG
8
R/W
See Section
14.3.8/14-25
0xFC0A_404D DSCR_CLKRST
8
R/W
See Section
14.3.8/14-25
0xFC0A_404E DSCR_IRQ
8
R/W
See Section
14.3.8/14-25
0xFC0A_404F DSCR_UART
8
R/W
See Section
14.3.8/14-25
14.3.1
Port Output Data Registers (PODR_x)
The PODR_x registers store the data to be driven on the corresponding port pins when the pins are
configured for general purpose output. The PODR_x registers are each eight bits wide, but not all ports use
all eight bits. The register definitions for all ports are shown in the below figures. The PODR_x registers
are read/write. At reset, all implemented bits in the PODR_x registers are set. Reserved bits always remain
cleared.
Reading a PODR_x register returns the current values in the register, not the port pin values. To set bits in
a PODR_x register, set the PODR_x bits, or set the corresponding bits in the PPDSDR_x register. To clear
bits in a PODR_x register, clear the PODR_x bits, or clear the corresponding bits in the PCLRR_x register.
Address: 0xFC0A_4005 (PODR_UART)
0xFC0A_400A (PODR_LCDDATAM)
0xFC0A_400B (PODR_LCDDATAL)
7
6
5
Access: User read/write
4
3
2
1
0
1
1
1
1
R
PODR_x
W
Reset:
1
1
1
1
Figure 14-2. Port x Output Data Registers (PODR_x)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-11
General Purpose I/O Module
Address: 0xFC0A_4000 (PODR_BE)
0xFC0A_4001 (PODR_CS)
0xFC0A_4002 (PODR_FBCTL)
0xFC0A_4006 (PODR_DSPI)
0xFC0A_4007 (PODR_TIMER)
0xFC0A_4008 (PODR_LCDCTL)
R
Access: User read/write
7
6
5
4
0
0
0
0
3
2
1
0
1
1
PODR_x
W
Reset:
0
0
0
0
1
1
Figure 14-3. Port x Output Data Registers (PODR_x)
Address: 0xFC0A_4003 (PODR_I2C)
0xFC0A_4009 (PODR_LCDDATAH)
R
Access: User read/write
7
6
5
4
3
2
0
0
0
0
0
0
1
0
PODR_x
W
Reset:
0
0
0
0
0
0
1
1
Figure 14-4. Port x Output Data Registers (PODR_x)
Table 14-5. PODR_x Field Descriptions
Field
Description
PODR_x Port x output data bits.
0 Drives 0 when the port x pin is general purpose output
1 Drives 1 when the port x pin is general purpose output
Note: See above figures for bit field positions.
14.3.2
Port Data Direction Registers (PDDR_x)
The PDDRs control the direction of the port pin drivers when the pins are configured for GPIO. The
PDDR_x registers are each eight bits wide, but not all ports use all eight bits. The register definitions for
all ports are shown in the figures below.
The PDDRs are read/write. At reset, all bits in the PDDRs are cleared. Setting any bit in a PDDR_x register
configures the corresponding port pin as an output. Clearing any bit in a PDDR_x register configures the
corresponding pin as an input.
MCF52277 Reference Manual, Rev 2
14-12
Freescale Semiconductor
General Purpose I/O Module
Address: 0xFC0A_4011 (PDDR_UART)
0xFC0A_4016 (PDDR_LCDDATAM)
0xFC0A_4017 (PDDR_LCDDATAL)
7
6
5
Access: User read/write
4
3
2
1
0
0
0
0
0
R
PDDR_x
W
Reset:
0
0
0
0
Figure 14-5. Port Data Direction Registers (PDDR_x)
Address: 0xFC0A_400C (PDDR_BE)
0xFC0A_400D (PDDR_CS)
0xFC0A_400E (PDDR_FBCTL)
0xFC0A_4012 (PDDR_DSPI)
0xFC0A_4013 (PDDR_TIMER)
0xFC0A_4014 (PDDR_LCDCTL)
R
Access: User read/write
7
6
5
4
0
0
0
0
3
2
1
0
0
0
PDDR_x
W
Reset:
0
0
0
0
0
0
Figure 14-6. Port Data Direction Registers (PDDR_x)
Address: 0xFC0A_400F (PDDR_I2C)
0xFC0A_4015 (PDDR_LCDDATAH)
R
Access: User read/write
7
6
5
4
3
2
0
0
0
0
0
0
1
0
PDDR_x
W
Reset:
0
0
0
0
0
0
0
0
Figure 14-7. Port Data Direction Registers (PDDR_x)
Table 14-6. PDDR_x Field Descriptions
Field
Description
PDDR_x Port x output data direction bits.
1 Port x pin configured as output
0 Port x pin configured as input
Note: See above figures for bit field positions.
14.3.3
Port Pin Data/Set Data Registers (PPDSDR_x)
The PPDSDR registers reflect the current pin states and control the setting of output pins when the pin is
configured for GPIO. The PPDSDR_x registers are each eight bits wide, but not all ports use all eight bits.
The register definitions for all ports are shown in the below figures.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-13
General Purpose I/O Module
The PPDSDR_x registers are read/write. At reset, the bits in the PPDSDR_x registers are set to the current
pin states. Reading a PPDSDR_x register returns the current state of the port x pins. Setting a PPDSDR_x
register sets the corresponding bits in the PODR_x register. Writing 0s has no effect.
Address: 0xFC0A_401D (PPDSDR_UART)
0xFC0A_4022 (PPDSDR_LCDDATAM)
0xFC0A_4023 (PPDSDR_LCDDATAL)
7
6
5
Access: User read/write
4
3
2
1
0
[Px3]
[Px2]
[Px1]
[Px0]
R
PPDR_x
W
PSDR_x
Reset:
[Px7]
[Px6]
[Px5]
[Px4]
Figure 14-8. Port x Pin Data/Set Data Registers (PPDSDR_x)
Address: 0xFC0A_4018 (PPDSDR_BE)
0xFC0A_4019 (PPDSDR_CS)
0xFC0A_401A (PPDSDR_FBCTL)
0xFC0A_401E (PPDSDR_DSPI)
0xFC0A_401F (PPDSDR_TIMER)
0xFC0A_4020 (PPDSDR_LCDCTL)
R
Access: User read/write
7
6
5
4
0
0
0
0
3
2
0
[Px1]
[Px0]
PPDR_x
W
Reset:
1
PSDR_x
0
0
0
0
[Px3]
[Px2]
Figure 14-9. Port x Pin Data/Set Data Registers (PPDSDR_x)
Address: 0xFC0A_401B (PPDSDR_I2C)
0xFC0A_4021 (PPDSDR_LCDDATAH)
R
Access: User read/write
7
6
5
4
3
2
0
0
0
0
0
0
1
PPDR_x
W
Reset:
0
PSDR_x
0
0
0
0
0
0
[Px1]
[Px0]
Figure 14-10. Port x Pin Data/Set Data Registers (PPDSDR_x)
Table 14-7. PPDSDR_x Field Descriptions
Field
Description
PPDR_x Port x pin data bits.
(read)
0 Port x pin state is 0
1 Port x pin state is 1
PSDR_x Port x set data bits.
(write) 0 No effect.
1 Set corresponding PODR_x bit.
Note: See above figures for bit field positions.
MCF52277 Reference Manual, Rev 2
14-14
Freescale Semiconductor
General Purpose I/O Module
14.3.4
Port Clear Output Data Registers (PCLRR_x)
Clearing a PCLRR_x register clears the corresponding bits in the PODR_x register. Setting it has no effect.
Reading the PCLRR_x register returns 0s. The PCLRR_x registers are each eight bits wide, but not all
ports use all eight bits. The register definitions for all ports are shown in the figures below.
Address: 0xFC0A_4029 (PCLRR_UART)
0xFC0A_402E (PCLRR_LCDDATAM)
0xFC0A_402F (PCLRR_LCDDATAL)
R
Access: User write-only
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset:
PCLRR_x
0
0
0
0
Figure 14-11. Port Clear Output Data Registers (PCLRR_x)
Address: 0xFC0A_4024 (PCLRR_BE)
0xFC0A_4025 (PCLRR_CS)
0xFC0A_4026 (PCLRR_FBCTL)
0xFC0A_402A (PCLRR_DSPI)
0xFC0A_402B (PCLRR_TIMER)
0xFC0A_402C (PCLRR_LCDCTL)
R
Access: User write-only
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset:
PCLRR_x
0
0
0
0
0
0
Figure 14-12. Port x Clear Output Data Registers (PCLRR_x)
Address: 0xFC0A_4027 (PCLRR_I2C)
0xFC0A_402D (PCLRR_LCDDATAH)
R
Access: User write-only
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
Reset:
PCLRR_x
0
0
0
0
0
0
0
0
Figure 14-13. Port x Clear Output Data Registers (PCLRR_x)
Table 14-8. PCLRR_x Field Descriptions
Field
Description
PCLRR_x Port x clear data bits.
0 Clears corresponding PODR_x bit
1 No effect
Note: See above figures for bit field positions.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-15
General Purpose I/O Module
14.3.5
Pin Assignment Registers (PAR_x)
The pin assignment registers control which functions are currently active on the external pins. All pin
assignment registers are read/write.
14.3.5.1
Byte Enable Pin Assignment Register (PAR_BE)
The PAR_BE register controls the functions of the byte enable pins. After reset the byte enable signals are
configured to their primary functions.
Address: 0xFC0A_4030 (PAR_BE)
R
Access: User read/write
7
6
5
4
0
0
0
0
3
2
1
0
PAR_BE3
PAR_BE2
PAR_BE1
PAR_BE0
1
1
1
1
W
Reset:
0
0
0
0
Figure 14-14. Byte Enable Pin Assignment Register (PAR_BE)
Table 14-9. PAR_BE Field Descriptions
Field
Description
7–4
Reserved, must be cleared.
3
FB_BE3 pin assignment.
PAR_BE3 0 FB_BE3 pin configured for GPIO
1 FB_BE3 pin configured for FlexBus byte enable 3 function
2
FB_BE2 pin assignment.
PAR_BE2 0 FB_BE2 pin configured for GPIO
1 FB_BE2 pin configured for FlexBus byte enable 2 function
1
FB_BE1 pin assignment.
PAR_BE1 0 FB_BE1 pin configured for GPIO
1 FB_BE1 pin configured for FlexBus byte enable 1 function
0
FB_BE0 pin assignment.
PAR_BE0 0 FB_BE0 pin configured for GPIO
1 FB_BE0 pin configured for FlexBus byte enable 0 function
14.3.5.2
Chip Select Pin Assignment Register (PAR_CS)
The PAR_CS register controls the functions of the FlexBus chip select pins. After reset the byte enable
signals are configured to their primary functions.
Address: 0xFC0A_4031 (PAR_CS)
R
Access: User read/write
7
6
5
0
0
0
4
3
PAR_CS3
PAR_CS2
1
1
2
1
PAR_CS1
0
PAR_CS0
W
Reset:
0
0
0
1
1
1
Figure 14-15. Chip Select Pin Assignment Register (PAR_CS)
MCF52277 Reference Manual, Rev 2
14-16
Freescale Semiconductor
General Purpose I/O Module
Table 14-10. PAR_CS Field Descriptions
Field
Description
7–5
Reserved, must be cleared.
4
FB_CS3 pin assignment.
PAR_CS3 0 FB_CS3 pin configured for GPIO
1 FB_CS3 pin configured for FlexBus chip select 3 function
3
FB_CS2 pin assignment.
PAR_CS2 0 FB_CS2 pin configured for GPIO
1 FB_CS2 pin configured for FlexBus chip select 2 function
2–1
FB_CS1 pin assignment.
PAR_CS1 00 FB_CS1 pin configured for GPIO
01 Reserved
10 FB_CS1 pin configured for SD_CS1
11 FB_CS1 pin configured for FlexBus chip select 1 function
3
FB_CS0 pin assignment.
PAR_CS0 0 FB_CS0 pin configured for GPIO
1 FB_CS0 pin configured for FlexBus chip select 0 function
14.3.5.3
FlexBus Control Pin Assignment Register (PAR_FBCTL)
The PAR_FBCTL register controls the functions of the external FlexBus control signal pins. After reset
the FlexBus control signals are configured to their primary functions.
Address: 0xFC0A_4032 (PAR_FBCTL)
Access: User read/write
7
6
5
PAR_OE
PAR_TA
PAR_RWB
1
1
1
4
3
R
2
1
0
0
0
0
0
0
0
PAR_TS
W
Reset:
1
1
Figure 14-16. FlexBus Control Pin Assignment Register (PAR_FBCTL)
Table 14-11. PAR_FBCTL Field Descriptions
Field
Description
7
PAR_OE
FB_OE pin assignment.
0 FB_OE pin configured for GPIO
1 FB_OE pin configured for FlexBus output enable function
6
PAR_TA
FB_TA pin assignment.
0 FB_TA pin configured for GPIO
1 FB_TA pin configured for FlexBus transfer acknowledge function
5
FB_R/W pin assignment.
PAR_RWB 0 FB_R/W pin configured for GPIO
1 FB_R/W pin configured for FlexBus read/write function
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-17
General Purpose I/O Module
Table 14-11. PAR_FBCTL Field Descriptions (continued)
Field
Description
4–3
PAR_TS
FB_TS pin assignment.
00 FB_TS pin configured for GPIO
01 Reserved
10 FB_TS pin configured for DMA acknowledge 0 function
11 FB_TS pin configured for FlexBus transfer start function
2–0
Reserved, must be cleared.
14.3.5.4
I2C Pin Assignment Register (PAR_I2C)
The PAR_I2C register controls the functions of the I2C pins.
Address: 0xFC0A_4033 (PAR_I2C)
R
Access: User read/write
7
6
5
4
0
0
0
0
3
2
1
PAR_SCL
0
PAR_SDA
W
Reset:
0
0
0
0
0
0
0
0
Figure 14-17. I2C Pin Assignment Register (PAR_I2C)
Table 14-12. PAR_I2C Field Descriptions
Field
Description
7–4
Reserved, must be cleared.
3–2
PAR_SCL
I2C_SCL pin assignment.
00 I2C_SCL pin configured for GPIO
01 I2C_SCL pin configured for UART2 transmit data function
10 I2C_SCL pin configured for FlexCAN transmit data function
11 I2C_SCL pin configured for I2C SCL function
1–0
PAR_SDA
I2C_SDA pin assignment.
00 I2C_SDA pin configured for GPIO
01 I2C_SDA pin configured for UART2 receive data function
10 I2C_SDA pin configured for FlexCAN receive data function
11 I2C_SDA pin configured for I2C SDA function
14.3.5.5
UART Pin Assignment Register (PAR_UART)
The PAR_UART register controls the functions of the UART pins.
Address: 0xFC0A_4034 (PAR_UART)
15
R
W
Reset
14
13
12
Access: User read/write
11
10
9
8
7
6
5
4
3
2
1
0
PAR_U1CTS PAR_U1RTS PAR_U1RXD PAR_U1TXD PAR_U0CTS PAR_U0RTS PAR_U0RXD PAR_U0TXD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-18. UART Pin Assignment (PAR_UART)
MCF52277 Reference Manual, Rev 2
14-18
Freescale Semiconductor
General Purpose I/O Module
Table 14-13. PAR_UART Field Descriptions
Field
Description
15–14
UART1 pin assignment. These bit fields configure the UART1 pins for one of their primary functions or GPIO.
PAR_U1CTS
13–12
PAR_U1CTS PAR_U1RTS PAR_U1RXD PAR_U1TXD
PAR_U1RTS
00
GPIO
GPIO
GPIO
GPIO
11–10
PAR_U1RXD
01
LCD_CLS
LCD_PS
Reserved
Reserved
9–8
PAR_U1TXD
10
SSI_BCLK
SSI_FS
SSI_RXD
SSI_TXD
11
U1RTS
U1CTS
U1RXD
U1TXD
7–6
UART0 pin assignment. These bit fields configure the UART0 pins for one of their primary functions or GPIO.
PAR_U0CTS
5–4
PAR_U0CTS
PAR_U0RTS
PAR_U0RXD
PAR_U0TXD
PAR_U0RTS
00
GPIO
GPIO
GPIO
GPIO
3–2
PAR_U0RXD
01
USB_VBUS_EN USB_VBUS_OC
Reserved
Reserved
1–0
PAR_U0TXD
10
T1OUT
T1IN
CANRX
CANTX
11
14.3.5.6
U0RTS
U0CTS
U0RXD
U0TXD
DSPI Pin Assignment Register (PAR_DSPI)
The PAR_DSPI register controls the functions of the DSPI pins.
Address: 0xFC0A_4036 (PAR_DSPI)
7
6
Access: User read/write
5
4
3
2
1
0
R
PAR_PCS0
PAR_SIN
PAR_SOUT
PAR_SCK
W
Reset:
0
0
0
0
0
0
0
0
Figure 14-19. DSPI Pin Assignment Register (PAR_DSPI)
Table 14-14. PAR_DSPI Field Descriptions
Field
Description
7–6
DSPI pin assignment. These bit fields configure the DSPI pins for one of their primary functions or GPIO.
PAR_PCS0
5–4
PAR_PCS0
PAR_SIN
PAR_SOUT PAR_SCK
PAR_SIN
00
GPIO
GPIO
GPIO
GPIO
3–2
PAR_SOUT
01
Reserved
Reserved
Reserved
Reserved
1–0
PAR_SCK
10
U2RTS
U2RXD
U2TXD
U2CTS
11
DSPI_PCS0
DSPI_SIN
DSPI_SOUT
DSPI_SCK
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Freescale Semiconductor
14-19
General Purpose I/O Module
14.3.5.7
Timer Pin Assignment Registers (PAR_TIMER)
The PAR_TIMER register controls the functions of the DMA timer pins.
Address: 0xFC0A_4037 (PAR_TIMER)
7
6
Access: User read/write
5
4
3
2
1
0
R
PAR_T3IN
PAR_T2IN
PAR_T1IN
PAR_T0IN
W
Reset:
0
0
0
0
0
0
0
0
Figure 14-20. Timer Pin Assignment (PAR_TIMER)
Table 14-15. PAR_TIMER Field Descriptions
Field
Description
7–6
PAR_T3IN
5–4
PAR_T2IN
3–2
PAR_T1IN
1–0
PAR_T0IN
DMA timer pin assignment. These bit fields configure the DMA timer pins for one of their primary functions or GPIO.
14.3.5.8
PAR_T3IN
PAR_T2IN
PAR_T1IN
PAR_T0IN
00
GPIO
GPIO
GPIO
GPIO
01
SSI_MCLK
DSPI_PCS2
LCD_CONTRAST
LCD_REV
10
T3OUT
T2OUT
T1OUT
T0OUT
11
T3IN
T2IN
T1IN
T0IN
LCD Controller Control Pin Assignment Register (PAR_LCDCTL)
The PAR_LCDCTL register controls the functions of the LCDC control pins.
Address: 0xFC0A_4038 (PAR_LCDCTL)
R
Access: User read/write
7
6
5
0
0
0
4
3
PAR_ACD_OE
W
Reset:
0
0
0
0
2
1
PAR_
PAR_
FLM_VSYNC LP_HSYNC
0
0
0
0
PAR_
LSCLK
0
Figure 14-21. LCD Control Pin Assignment (PAR_LCDCTL)
Table 14-16. PAR_LCDCTL Field Descriptions
Field
7–5
4–3
PAR_ACD_OE
Description
Reserved, must be cleared.
LCD_ACD/OE pin assignment.
00 LCD_ACD/OE pin configured as GPIO.
01 Reserved
10 LCD_ACD/OE pin configured for LCD_SPL_SPR function.
11 LCD_ACD/OE pin configured for LCD controller ACD/OE function.
MCF52277 Reference Manual, Rev 2
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General Purpose I/O Module
Table 14-16. PAR_LCDCTL Field Descriptions (continued)
Field
Description
2
PAR_
FLM_VSYNC
LCD_FLM/VSYNC pin assignment.
0 LCD_FLM/VSYNC pin configured as GPIO.
1 LCD_FLM/VSYNC pin configured for LCD controller FLM/VSYNC function.
1
LCD_LP/HSYNC pin assignment.
PAR_LP_HSYNC 0 LCD_LP/HSYNC pin configured as GPIO.
1 LCD_LP/HSYNC pin configured for LCD controller LP/HSYNC function.
0
PAR_LSCLK
14.3.5.9
LCD_LSCLK pin assignment.
0 LCD_LSCLK pin configured as GPIO.
1 LCD_LSCLK pin configured for LCD controller LSCLK function.
IRQ Pin Assignment Register (PAR_IRQ)
The PAR_IRQ register controls the functions of the IRQ pins.
Address: 0xFC0A_4039 (PAR_IRQ)
R
Access: User read/write
7
6
5
4
0
0
0
0
3
2
1
PAR_IRQ4
0
PAR_IRQ1
W
Reset:
0
0
0
0
0
0
0
0
Figure 14-22. IRQ Pin Assignment (PAR_IRQ)
Table 14-17. PAR_IRQ Field Descriptions
Field
7–4
Description
Reserved, must be cleared.
3–2
IRQ4 pin assignment.
PAR_IRQ4 00 IRQ4 pin configured as GPIO or external interrupt request 4 function as determined by the edge port module.
See Chapter 16, “Edge Port Module (EPORT),” for details.
01 IRQ4 pin configured for DSPI PCS4 function
10 IRQ4 pin configured for DMA request 0 function
11 Reserved
1–0
IRQ1 pin assignment.
PAR_IRQ1 00 IRQ1 pin configured as GPIO or external interrupt request 1 function as determined by the edge port module.
See Chapter 16, “Edge Port Module (EPORT),” for details.
01 IRQ1 pin configured for SSI_CLKIN function
10 IRQ1 pin configured for USB_CLKIN function
11 Reserved
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Freescale Semiconductor
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General Purpose I/O Module
14.3.5.10 LCD Controller Data High Pin Assignment Register (PAR_LCDH)
The PAR_LCDH register controls the functions of the LCDC data pins.
Address: 0xFC0A_403C (PAR_LCDH)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
Reset:
R
PAR_LD17 PAR_LD16 PAR_LD15 PAR_LD14 PAR_LD13 PAR_LD12
W
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-23. LCD Data High Pin Assignment (PAR_LCDH)
Table 14-18. PAR_LCDH Field Descriptions
Field
Description
31–12
11–10
PAR_LD17
9–8
PAR_LD16
7–6
PAR_LD17
5–4
PAR_LD14
3–2
PAR_LD13
1–0
PAR_LD12
Reserved, must be cleared.
LCD data pin assignment. These bit fields configure the LCD data pins for one of their primary functions or GPIO.
PAR_LD17 PAR_LD16 PAR_LD15 PAR_LD14 PAR_LD13 PAR_LD12
00
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
01
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10
LCD_D11
(active)
LCD_D10
(active)
LCD_D9
(active)
LCD_D8
(active)
CANTX
CANRX
11
LCD_D17
(passive)
LCD_D16
(passive)
LCD_D15
(passive)
LCD_D14
(passive)
LCD_D13
(passive)
LCD_D12
(passive)
14.3.5.11 LCD Controller Data Low Pin Assignment Register (PAR_LCDL)
The PAR_LCDL register controls the functions of the LCDC data pins.
Address: 0xFC0A_4040 (PAR_LCDL)
31
R
W
Reset:
R
W
Reset:
30
29
28
PAR_LD11 PAR_LD10
Access: User read/write
27
26
PAR_LD9
25
24
PAR_LD8
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
PAR_LD3
0
0
PAR_LD2
0
0
PAR_LD1
0
0
PAR_LD0
0
0
23
22
PAR_LD7
0
0
21
20
PAR_LD6
0
0
19
18
PAR_LD5
0
0
17
16
PAR_LD4
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 14-24. LCD Data Low Pin Assignment (PAR_LCDL)
MCF52277 Reference Manual, Rev 2
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General Purpose I/O Module
Table 14-19. PAR_LCD_LOW Field Descriptions
Field
Description
31–30
PAR_LD11
29–28
PAR_LD10
27–26
PAR_LD9
25–24
PAR_LD8
23–22
PAR_LD7
21–20
PAR_LD6
LCD data pin assignment. These bit fields configure the LCD data pins for one of their primary functions or GPIO.
19–18
PAR_LD5
17–16
PAR_LD4
15–14
PAR_LD3
13–12
PAR_LD2
11–10
PAR_LD1
9–8
PAR_LD0
LCD data pin assignment. These bit fields configure the LCD data pins for one of their primary functions or GPIO.
7–0
14.3.6
PAR_LD11 PAR_LD10
PAR_LD9
PAR_LD8
PAR_LD7
PAR_LD6
00
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
01
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10
LCD_D7
(active)
LCD_D6
(active)
LCD_D5
(active)
LCD_D4
(active)
PWM7
PWM5
11
LCD_D11
(passive)
LCD_D10
(passive)
LCD_D9
(passive)
LCD_D8
(passive)
LCD_D7
(passive)
LCD_D6
(passive)
PAR_LD5
PAR_LD4
PAR_LD3
PAR_LD2
PAR_LD1
PAR_LD0
00
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
01
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10
LCD_D3
(active)
LCD_D2
(active)
LCD_D1
(active)
LCD_D0
(active)
PWM3
PWM1
11
LCD_D5
(passive)
LCD_D4
(passive)
LCD_D3
(passive)
LCD_D2
(passive)
LCD_D1
(passive)
LCD_D0
(passive)
Reserved, must be cleared.
FlexBus Mode Select Control Register (MSCR_FLEXBUS)
The MSCR_FLEXBUS register controls the output mode selects of the following FlexBus pins:
FB_A[23:0], FB_D[31:0], FB_BE/BWE[3:0], FB_OE, FB_R/W, FB_CS[5:0], FB_TA and FB_TS.
Address: 0xFC0A_4044 (MSCR_FLEXBUS)
R
7
6
0
0
5
Access: User read/write
4
MSCR_DUPPER
3
2
MSCR_DLOWER
1
0
MSCR_ADDRCTL
W
Reset:
0
0
1
1
1
1
1
1
Figure 14-25. FlexBus Mode Select Control Register (MSCR_FLEXBUS)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-23
General Purpose I/O Module
Table 14-20. MSCR_FLEXBUS Field Descriptions
Field
Description
7–6
Reserved, must be cleared.
5–4
MSCR_
DUPPER
FB_D[31:16] and SD_DQS[3:2]mode select control. These bit fields control the strength of the FlexBus upper data
and SD_DQS pins.
00 Half strength 1.8V low power/mobile DDR
01 Open drain
10 Full strength 1.8V low power/mobile DDR
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays
3–2
FB_D[15:0] mode select control. These bit fields control the strength of the FlexBus lower data pins.
MSCR_ 00 Half strength 1.8V low power/mobile DDR
DLOWER 01 Open drain
10 Full strength 1.8V low power/mobile DDR
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays
1–0
FB_A[23:0], BE/BWE[3:0], OE, R/W, FB_CS[5:0], TA, and TS mode select control. These bit fields control the
MSCR_ strength of the FlexBus address and control pins.
ADDRCTL 00 Half strength 1.8V low power/mobile DDR
01 Open drain
10 Full strength 1.8V low power/mobile DDR
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays
14.3.7
SDRAM Mode Select Control Register (MSCR_SDRAM)
The MSCR_SDRAM register controls the slew rate mode of the following dedicated SDRAM pins:
SD_A10, SD_CAS, SD_CKE, SD_CLK, SD_CLK, SD_CS1, SD_RAS, SD_SDR_DQS, and SD_WE.
Address: 0xFC0A_4045 (MSCR_SDRAM)
R
7
6
0
0
5
Access: User read/write
4
3
MSCR_SDCLKB
2
1
0
MSCR_SDCLK
MSCR_SDCTL
1
1
W
Reset:
0
0
1
1
1
1
Figure 14-26. SDRAM Mode Select Control Register (MSCR_SDRAM)
Table 14-21. MSCR_SDRAM Field Descriptions
Field
7–6
5–4
MSCR_
SDCLKB
Description
Reserved, must be cleared.
SD_CLK slew rate mode. Controls the strength of the SD_CLK pins.
00 Half strength 1.8V low power/mobile DDR
01 Open drain
10 Full strength 1.8V low power/mobile DDR
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays
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General Purpose I/O Module
Table 14-21. MSCR_SDRAM Field Descriptions (continued)
Field
Description
3–2
MSCR_
SDCLK
SD_CLK slew rate mode. Controls the strength of the SD_CLK pin.
00 Half strength 1.8V low power/mobile DDR
01 Open drain
10 Full strength 1.8V low power/mobile DDR
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays
1–0
MSCR_
SDCTL
SD_A10, SD_CAS, SD_CKE, SD_CS1, SD_RAS, SD_SDR_DQS, SD_WE slew rate mode. Controls the strength
of the SDRAM control pins.
00 Half strength 1.8V low power/mobile DDR
01 Open drain
10 Full strength 1.8V low power/mobile DDR
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays
14.3.8
Drive Strength Control Registers (DSCR_x)
The drive strength control registers set the output pin drive strengths. All drive strength control registers
are read/write. These drive strength settings are effective in all non-JTAG modes, regardless of the current
functions of the pins.
Address: 0xFC0A_4048 (DSCR_DSPI)
0xFC0A_4049 (DSCR_TIMER)
0xFC0A_404A (DSCR_I2C)
0xFC0A_404B (DSCR_LCD)
0xFC0A_404C (DSCR_DEBUG)
0xFC0A_404E (DSCR_IRQ)
R
Access: User read/write
7
6
5
4
3
2
0
0
0
0
0
0
1
0
DSE_x
W
Reset:
0
0
0
0
0
0
See Note
Note: Reset state is dependent on the chosen reset configuration. See Chapter 9, “Chip Configuration
Module (CCM),” for details.
Figure 14-27. Drive Strength Control Registers (DSCR_x)
Address: 0xFC0A_404D (DSCR_CLKRST)
R
Access: User read/write
7
6
5
4
0
0
0
0
3
2
1
DSE_RSTOUT
0
DSE_FBCLK
W
Reset:
0
0
0
0
See Note
Note: Reset state is dependent on the chosen reset configuration. See Chapter 9, “Chip Configuration
Module (CCM),” for details.
Figure 14-28. Clock/Reset Drive Strength Control Register (DSCR_CLKRST)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
14-25
General Purpose I/O Module
Address: 0xFC0A_404F (DSCR_UART)
R
Access: User read/write
7
6
5
4
0
0
0
0
3
2
1
DSE_UART1
0
DSE_UART0
W
Reset:
0
0
0
0
See Note
Note: Reset state is dependent on the chosen reset configuration. See Chapter 9, “Chip Configuration
Module (CCM),” for details.
Figure 14-29. UART Drive Strength Control Register (DSCR_UART)
Table 14-22. DSCR_x Field Descriptions
Field
Description
DSCR_x Drive strength control. Controls the drive strength of the various pins. See Table 14-23 for a list of the pins affected
for each register bit field.
00 10pF
01 20pF
10 30pF
11 50pF
Note: See above figures for bit field positions.
Table 14-23. DSCR_x Pins Affected
Register (DSCR_x)
DSCR_I2C
DSCR_UART
See below for individual bit fields.
U1RXD, U1TXD, U1CTS, and U1RTS
DSE_UART0
U0RXD, U0TXD, U0CTS, and U0RTS
DSCR_TIMER
DSCR_LCD
DSPI_PCS0, DSPI_SCK, DSPI_SIN, and DSPI_SOUT
T3IN, T2IN, T1IN, and T0IN
LCD_D[17:0], LCD_ACD/OE, LCD_FLM/SYNC, LCD_LP/VSYNC, and LCD_LSCLK
DSCR_DEBUG
PST[3:0], DDATA[3:0], ALLPST, and TDO (when configured for the DSO function,
JTAG_EN is negated).
DSCR_RESET
RSTOUT, FB_CLK
DSCR_IRQ
14.4.1
I2C_SDA and I2C_SCL
DSE_UART1
DSCR_DSPI
14.4
Pins Affected
IRQ[7,4,1]
Functional Description
Overview
Initial pin function is determined during reset configuration. The pin assignment registers allow the user
to select among various primary functions and general purpose I/O after reset. Most pins are configured
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General Purpose I/O Module
as GPIO by default. The notable exceptions to this are external bus control pins, address/data pins, and
chip select pins. These pins are configured for their primary functions after reset.
Every GPIO pin is individually configurable as an input or an output via a data direction register
(PDDR_x). Every GPIO port has an output data register (PODR_x) and a pin data register (PPDSDR_x)
to monitor and control the state of its pins. Data written to a PODR_x register is stored and then driven to
the corresponding port x pins configured as outputs.
Reading a PODR_x register returns the current state of the register regardless of the state of the
corresponding pins. Reading a PPDSDR_x register returns the current state of the corresponding pins
when configured as general purpose I/O, regardless of whether the pins are inputs or outputs.
Every GPIO port has a PPDSDR_x register and a clear register (PCLRR_x) for setting or clearing
individual bits in the PODR_x register. Initial pin output drive strength is determined during reset
configuration. The DSCR_x registers allow the pin drive strengths to be configured on a per-function basis
after reset.
14.4.2
Port Digital I/O Timing
Input data on all pins configured as general purpose input is synchronized to the rising edge of FB_CLK,
as shown in Figure 14-30.
FB_CLK
Input
Pin
Register
Pin Data
Figure 14-30. General Purpose Input Timing
Data written to the PODR_x register of any pin configured as a general purpose output is immediately
driven to its respective pin, as shown in Figure 14-31.
FB_CLK
Output Data
Register
Output Pin
Figure 14-31. General Purpose Output Timing
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General Purpose I/O Module
14.5
Initialization/Application Information
The initialization for the ports module is done during reset configuration. All registers are reset to a
predetermined state. Refer to Section 14.3, “Memory Map/Register Definition,” for more details on reset
and initialization.
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Chapter 15
Interrupt Controller Modules
15.1
Introduction
This section details the functionality of the interrupt controllers (INTC0, INTC1). The general features of
the interrupt controller block include:
• 128 fully-programmable interrupt sources. Not all possible interrupt source locations are used on
this device
• Each of the sources has a unique interrupt control register (ICR0n, ICR1n) to define the
software-assigned levels
• Unique vector number for each interrupt source
• Ability to mask any individual interrupt source, plus global mask-all capability
• Supports hardware and software interrupt acknowledge cycles
• Wake-up signal from low-power stop modes
The 64, fully-programmable interrupt sources for the two interrupt controllers manage the complete set of
interrupt sources from all of the modules on the device. This section describes how the interrupt sources
are mapped to the interrupt controller logic and how interrupts are serviced.
15.1.1
68 K/ColdFire Interrupt Architecture Overview
Before continuing with the specifics of the interrupt controllers, a brief review of the interrupt architecture
of the 68K/ColdFire family is appropriate.
The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit
encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt
requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The
processor samples for active interrupt requests once-per-instruction by comparing the encoded priority
level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machine’s status register (SR). If
the priority level is greater than the SR[I] field at the sample point, the processor suspends normal
instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as
non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and
may be masked depending on the value of the SR[I] field. For correct operation, the ColdFire device
requires that, after asserted, the interrupt source remain asserted until explicitly disabled by the interrupt
service routine.
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then
fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt
acknowledge (IACK) cycle with the ColdFire implementation using a special memory-mapped address
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Interrupt Controller Modules
space within the interrupt controller. The fetched data provides an index into the exception vector table
that contains 256 addresses, each pointing to the beginning of a specific exception service routine. In
particular, vectors 64 - 255 of the exception vector table are reserved for user interrupt service routines.
The first 64 exception vectors are reserved for the processor to manage reset, error conditions (access,
address), arithmetic faults, system calls, etc. After the interrupt vector number has been retrieved, the
processor continues by creating a stack frame in memory. For ColdFire, all exception stack frames are 2
longwords in length, and contain 32 bits of vector and status register data, along with the 32-bit program
counter value of the instruction that was interrupted (see Section 3.3.3.1, “Exception Stack Frame
Definition,” for more information on the stack frame format). After the exception stack frame is stored in
memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number
as the offset, and then jumps to that address to begin execution of the service routine. After the status
register is stored in the exception stack frame, the SR[I] mask field is set to the level of the interrupt being
acknowledged, effectively masking that level and all lower values while in the service routine.
The processing of the interrupt acknowledge cycle is fundamentally different than previous 68K/ColdFire
cores. In this approach, all IACK cycles are directly managed by the interrupt controller, so the requesting
peripheral device is not accessed during the IACK. As a result, the interrupt request must be explicitly
cleared in the peripheral during the interrupt service routine. For more information, see Section 15.3.1.3,
“Interrupt Vector Determination.”
ColdFire processors guarantee that the first instruction of the service routine is executed before sampling
for interrupts is resumed. By making this initial instruction a load of the SR, interrupts can be safely
disabled, if required.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual at
http://www.freescale.com/coldfire.
15.2
Memory Map/Register Definition
The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In
the following discussion, there are a number of program-visible registers greater than 32 bits in size. For
these control fields, the physical register is partitioned into two 32-bit values: a register high (the upper
longword) and a register low (the lower longword). The nomenclature <reg_name>H and <reg_name>L
is used to reference these values.
The registers and their locations are defined in Table 15-2. The base addresses for the interrupt controllers
are listed below.
Table 15-1. Interrupt Controller Base Addresses
1
Interrupt Controller Number
Base Address
INTC0
0xFC04_8000
INTC1
0xFC04_C000
Global IACK Registers Space1
0xFC05_4000
This address space only contains the global SWIACK and global L1ACK-L7IACK registers. See
Section 15.2.10, “Software and Level 1 – 7 IACK Registers (SWIACKn, L1IACKn – L7IACKn)" for more
information
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Interrupt Controller Modules
Table 15-2. Interrupt Controller Memory Map
Address
Register
Width
Access
(bits)
Reset Value
Section/
Page
Interrupt Controller 0
0xFC04_8000
Interrupt Pending Register High (IPRH0)
32
R
0x0000_0000
15.2.1/15-4
0xFC04_8004
Interrupt Pending Register Low (IPRL0)
32
R
0x0000_0000
15.2.1/15-4
0xFC04_8008
Interrupt Mask Register High (IMRH0)
32
R/W
0xFFFF_FFFF
15.2.2/15-5
0xFC04_800C
Interrupt Mask Register Low (IMRL0)
32
R/W
0xFFFF_FFFF
15.2.2/15-5
0xFC04_8010
Interrupt Force Register High (INTFRCH0)
32
R/W
0x0000_0000
15.2.3/15-6
0xFC04_8014
Interrupt Force Register Low (INTFRCL0)
32
R/W
0x0000_0000
15.2.3/15-6
0xFC04_801A
Interrupt Configuration Register (ICONFIG)
16
R/W
0x0000
15.2.4/15-7
0xFC04_801C
Set Interrupt Mask (SIMR0)
8
W
0x00
15.2.5/15-8
0xFC04_801D
Clear Interrupt Mask (CIMR0)
8
W
0x00
15.2.6/15-9
0xFC04_801E
Current Level Mask (CLMASK)
8
R/W
0x0F
15.2.7/15-9
0xFC04_801F
Saved Level Mask (SLMASK)
8
R/W
0x0F
15.2.8/15-10
Interrupt Control Registers (ICR0n)
8
R/W
0x00
15.2.9/15-11
Software Interrupt Acknowledge (SWIACK0)
8
R
0x00
15.2.10/15-14
8
R
0x18
15.2.10/15-14
0xFC04_8040 + n
(n=0:63)
0xFC04_80E0
0xFC04_80E0 + 4n Level n Interrupt Acknowledge Registers (LnIACK0)
(n=1:7)
Interrupt Controller 1
0xFC04_C000
Interrupt Pending Register High (IPRH1)
32
R
0x0000_0000
15.2.1/15-4
0xFC04_C004
Interrupt Pending Register Low (IPRL1)
32
R
0x0000_0000
15.2.1/15-4
0xFC04_C008
Interrupt Mask Register High (IMRH1)
32
R/W
0xFFFF_FFFF
15.2.2/15-5
0xFC04_C00C
Interrupt Mask Register Low (IMRL1)
32
R/W
0xFFFF_FFFF
15.2.2/15-5
0xFC04_C010
Interrupt Force Register High (INTFRCH1)
32
R/W
0x0000_0000
15.2.3/15-6
0xFC04_C014
Interrupt Force Register Low (INTFRCL1)
32
R/W
0x0000_0000
15.2.3/15-6
0xFC04_C01C
Set Interrupt Mask (SIMR1)
8
W
0x00
15.2.5/15-8
0xFC04_C01D
Clear Interrupt Mask (CIMR1)
8
W
0x00
15.2.5/15-8
8
R/W
0x00
15.2.9/15-11
8
R
0x00
15.2.10/15-14
8
R
0x18
15.2.10/15-14
0xFC04_C040 + n Interrupt Control Registers (ICR1n)
(n=1:63)
0xFC04_C0E0
Software Interrupt Acknowledge (SWIACK1)
0xFC04_C0E0 + 4n Level n Interrupt Acknowledge Registers (LnIACK1)
(n=1:7)
Global IACK Registers
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Interrupt Controller Modules
Table 15-2. Interrupt Controller Memory Map (continued)
Address
Width
Access
(bits)
Register
0xFC05_40E0
Global Software Interrupt Acknowledge (GSWIACK)
0xFC05_40E0 + 4n Global Level n Interrupt Acknowledge Registers
(n=1:7)
(GLnIACK)
15.2.1
Reset Value
Section/
Page
8
R
0x00
15.2.10/15-14
8
R
0x18
15.2.10/15-14
Interrupt Pending Registers (IPRHn, IPRLn)
The IPRHn and IPRLn registers, Figure 15-1 and Figure 15-2, are each 32 bits in size, and provide a bit
map for each interrupt request to indicate if there is an active request (1 equals active request, 0 equals no
request) for the given source. The interrupt mask register state does not affect the IPRn. The IPRn is
cleared by reset and is a read-only register, so any attempted write to this register is ignored.
Address 0xFC04_8000 (IPRH0)
0xFC04_C000 (IPRH1)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-1. Interrupt Pending Register High (IPRHn)
Table 15-3. IPRHn Field Descriptions
Field
Description
31–0
INT
Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether
an interrupt condition can generate an interrupt. At every system clock, the IPRHn samples the signal generated by
the interrupting source. The corresponding IPRHn bit reflects the state of the interrupt signal even if the
corresponding IMRHn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
Address 0xFC04_8004 (IPRL0)
0xFC04_C004 (IPRL1)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-2. Interrupt Pending Register Low (IPRLn)
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Interrupt Controller Modules
Table 15-4. IPRLn Field Descriptions
Field
Description
31–0
INT
Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an
interrupt condition can generate an interrupt. At every system clock, the IPRLn samples the signal generated by the
interrupting source. The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding
IMRLn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
15.2.2
Interrupt Mask Register (IMRHn, IMRLn)
The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each interrupt to allow
the request to be disabled (1 equals disable the request, 0 equals enable the request). The IMRL register is
used for masking interrupt sources 0 to 31, while the IMRH register is used for masking interrupts 32 to
63. The IMRn is set to all ones by reset, disabling all interrupt requests. The IMRn can be read and written.
NOTE
A spurious interrupt may occur if an interrupt source is being masked in the
interrupt controller mask register (IMR) or a module’s interrupt mask
register while the interrupt mask in the status register (SR[I]) is set to a value
lower than the interrupt’s level. This is because by the time the status
register acknowledges this interrupt, the interrupt has been masked. A
spurious interrupt is generated because the CPU cannot determine the
interrupt source. To avoid this situation for interrupts sources with levels
1-6, first write a higher level interrupt mask to the status register, before
setting the mask in the IMR or the module’s interrupt mask register. After
the mask is set, return the interrupt mask in the status register to its previous
value. Because level 7 interrupts cannot be disabled in the status register
prior to masking, use of the IMR or module interrupt mask registers to
disable level 7 interrupts is not recommended.
Address 0xFC04_8008 (IMRH0)
0xFC04_C008 (IMRH1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
8
7
6
5
4
3
2
1
0
INT_MASK
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 15-3. Interrupt Mask Register High (IMRHn)
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15-5
Interrupt Controller Modules
Table 15-5. IMRHn Field Descriptions
Field
Description
31–0
Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an
INT_MASK interrupt condition can generate an interrupt. The corresponding IPRHn bit reflects the state of the interrupt signal
even if the corresponding IMRHn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
Address 0xFC04_800C (IMRL0)
0xFC04_C00C (IMRL1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
INT_MASK
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 15-4. Interrupt Mask Register Low (IMRLn)
Table 15-6. IMRLn Field Descriptions
Field
Description
31–0
Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an
INT_MASK interrupt condition can generate an interrupt. The corresponding IPRLn bit reflects the state of the interrupt signal
even if the corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
15.2.3
Interrupt Force Registers (INTFRCHn, INTFRCLn)
The INTFRCHn and INTFRCLn registers are each 32 bits in size and provide a mechanism to allow
software generation of interrupts for each possible source for functional or debug purposes. The system
design may reserve one or more sources to allow software to self-schedule interrupts by forcing one or
more of these bits (set to force request, clear to negate request) in the appropriate INTFRCn register. The
INTFRCLn register forces interrupts for sources 0 to 31, while the INTFRCHn register forces interrupts
for sources 32 to 63. The assertion of an interrupt request via the interrupt force register is not affected by
the interrupt mask register. The INTFRCn registers are cleared by reset.
Address 0xFC04_8010 (INTFRCH0)
0xFC04_C010 (INTFRCH1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
8
7
6
5
4
3
2
1
0
INTFRCH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-5. Interrupt Force Register High (INTFRCHn)
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Interrupt Controller Modules
Table 15-7. INTFRCHn Field Descriptions
Field
Description
31–0
Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.
INTFRCH 0 No interrupt forced on the corresponding interrupt source
1 Force an interrupt on the corresponding source
Address 0xFC04_8014 (INTFRCL0)
0xFC04_C014 (INTFRCL1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
INTFRCL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-6. Interrupt Force Register Low (INTFRCLn)
Table 15-8. INTFRCLn Field Descriptions
Field
Description
31–0
INTFRCL
Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
15.2.4
Interrupt Configuration Register (ICONFIG)
This 16-bit register defines the operating configuration for the interrupt controller module.
NOTE
Only one copy of this register exists among the 2 interrupt controller
modules. All reads and writes to this register must be made to the INTC0
memory space.
Address: 0xFC04_801A (ICONFIG)
15
14
13
R
11
10
9
ELVLPRI
W
Reset
12
Access: User read/write
0
0
0
0
0
0
0
8
7
6
0
0
0
0
0
0
5
EMASK
0
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
Figure 15-7. Interrupt Configuration Register (ICONFIG)
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15-7
Interrupt Controller Modules
Table 15-9. ICONFIG Field Descriptions
Field
15–9
ELVLPRI
8–6
Description
Enable core’s priority elevation on priority levels. Each ELVLPRI[7:1] bit corresponds to the available priority
levels 1 – 7. If set, the assertion of the corresponding level-n request to the core causes the processor’s bus
master priority to be temporarily elevated in the device’s crossbar switch arbitration logic. The processor’s bus
master arbitration priority remains elevated until the level-n request is negated. If round-robin arbitration is
enabled, this bit has no effect.
If cleared, the assertion of a level-n request does not affect the processor’s bus master priority.
Reserved, must be cleared.
5
EMASK
4–0
If set, the interrupt controller automatically loads the level of an interrupt request into the CLMASK (current level
mask) when the acknowledge is performed. At the exact same cycle, the value of the current interrupt level mask is
saved in the SLMASK (saved level mask) register.
This feature can be used to support software-managed nested interrupts, and is intended to complement the
interrupt masking functions supported in the ColdFire processor. The value of SLMASK register should be read from
the interrupt controller and saved in the interrupt stack frame in memory, and restored near the service routine’s exit.
If cleared, the INTC does not perform any automatic masking of interrupt levels. The state of this bit does not affect
the ColdFire processor’s interrupt masking logic in any manner.
Reserved, must be cleared.
15.2.5
Set Interrupt Mask Register (SIMRn)
The SIMRn register provides a simple mechanism to set a given bit in the IMRn registers to mask the
corresponding interrupt request. The value written to the SIMR field causes the corresponding bit in the
IMRn register to be set. The SIMRn[SALL] bit provides a global set function, forcing the entire contents
of IMRn to be set, thus masking all interrupts. Reads of this register return all zeroes. This register is
provided so interrupt service routines can easily mask the given interrupt request without the need to
perform a read-modify-write sequence on the IMRn register.
Address: 0xFC04_801C (SIMR0)
0xFC04_C01C (SIMR1)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset:
Access: User write-only
SALL
0
0
SIMR
0
0
0
Figure 15-8. Set Interrupt Mask Register (SIMRn)
Table 15-10. SIMRn Field Descriptions
Field
7
Description
Reserved, must be cleared.
6
SALL
Set all bits in the IMRn register, masking all interrupt requests.
0 Only set those bits specified in the SIMR field.
1 Set all bits in IMRn register. The SIMR field is ignored.
5–0
SIMR
Set the corresponding bit in the IMRn register, masking the interrupt request.
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Interrupt Controller Modules
15.2.6
Clear Interrupt Mask Register (CIMRn)
The CIMRn register provides a simple mechanism to clear a given bit in the IMRn registers to enable the
corresponding interrupt request. The value written to the CIMR field causes the corresponding bit in the
IMRn register to be cleared. The CIMRn[CALL] bit provides a global clear function, forcing the entire
contents of IMRn to be cleared, thus enabling all interrupts. Reads of this register return all zeroes. This
register is provided so interrupt service routines can easily enable the given interrupt request without the
need to perform a read-modify-write sequence on the IMRn register.
In the event of a simultaneous write to the CIMRn and SIMRn, the SIMRn has priority and the resulting
function would be a set of the interrupt mask register.
Address: 0xFC04_801D (CIMR0)
0xFC04_C01D (CIMR1)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset:
Access: User write-only
CALL
0
0
CIMR
0
0
0
Figure 15-9. Clear Interrupt Mask Register (CIMRn)
Table 15-11. CIMRn Field Descriptions
Field
7
Description
Reserved, must be cleared.
6
CALL
Clear all bits in the IMRn register, enabling all interrupt requests.
0 Only set those bits specified in the CIMR field.
1 Clear all bits in IMRn register. The CIMR field is ignored.
5–0
CIMR
Clear the corresponding bit in the IMRn register, enabling the interrupt request.
15.2.7
Current Level Mask Register (CLMASK)
The CLMASK register is provided so the interrupt controller can optionally automatically manage
masking of interrupt requests based on the programmed priority level. If enabled by ICONFIG[EMASK]
bit being set, an interrupt acknowledge read cycle returns a vector number identifying the physical request
source, and the CLMASK register is loaded with the level number associated with the request. After the
CLMASK register is updated, then all interrupt requests with level numbers equal to or less than this value
are masked by the controller and are not allowed to cause the assertion of the interrupt signal to the
processor core. As the CLMASK register is updated during the IACK cycle read, the former value is saved
in the SLMASK register.
Typically, after a level-n interrupt request is managed, the service routine restores the saved level mask
value into the current level mask register to re-enable the lower priority requests. In addition, an interrupt
service routine can explicitly load this register with a lower priority value to query for any pending
interrupts via software interrupt acknowledge cycles.
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Interrupt Controller Modules
NOTE
Only one copy of this register exists among the 2 interrupt controller
modules. All reads and writes to this register must be made to the INTC0
memory space.
Address: 0xFC04_801E (CLMASK)
R
Access: User read/write
7
6
5
4
3
0
0
0
0
2
1
0
1
1
CLMASK
W
Reset:
0
0
0
0
1
1
Figure 15-10. Current Level Mask Register (CLMASK)
Table 15-12. CLMASK Field Descriptions
Field
7–4
3–0
CLMASK
15.2.8
Description
Reserved, must be cleared.
Current level mask. Defines the level mask, where only interrupt levels greater than the current value are processed
by the controller
0000 Level 1 – 7 requests are processed.
0001 Level 2 – 7 requests are processed.
0010 Level 3 – 7 requests are processed.
0011 Level 4 – 7 requests are processed.
0100 Level 5 – 7 requests are processed.
0101 Level 6 – 7 requests are processed.
0110 Level 7 requests are processed.
0111 All requests are masked.
1000 – 1110 Reserved.
1111 Level 1 – 7 requests are processed.
Saved Level Mask Register (SLMASK)
The SLMASK register is provided so the interrupt controller can optionally automatically manage
masking of interrupt requests based on the programmed priority level. If enabled by ICONFIG[EMASK]
bit being set, an interrupt acknowledge read cycle returns a vector number identifying the physical request
source, and the CLMASK register is loaded with the level number associated with the request. After the
CLMASK register is updated, then all interrupt requests with level numbers equal to or less than this value
are masked by the controller and are not allowed to cause the assertion of the interrupt signal to the
processor core. As the CLMASK register is updated during the IACK cycle read, the former value is saved
in the SLMASK register.
Typically, after a level-n interrupt request is managed, the service routine restores the saved level mask
value into the current level mask register to re-enable the lower priority requests.
NOTE
Only one copy of this register exists among the two interrupt controller
modules. All reads and writes to this register must be made to the INTC0
memory space.
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Interrupt Controller Modules
Address: 0xFC04_801F (SLMASK)
R
Access: User read/write
7
6
5
4
3
0
0
0
0
2
1
0
1
1
SLMASK
W
Reset:
0
0
0
0
1
1
Figure 15-11. Saved Level Mask Register (SLMASK)
Table 15-13. SLMASK Field Descriptions
Field
7–4
Description
Reserved, must be cleared.
3–0
SLMASK
Saved level mask. Defines the saved level mask. See the CLMASK field definition for more information on the specific
values.
15.2.9
Interrupt Control Register (ICR0n, ICR1n, (n = 00, 01, 02, ..., 63))
Each ICR register specifies the interrupt level (1–7) for the corresponding interrupt source. These registers
are cleared by reset and should be programmed with the appropriate levels before interrupts are enabled.
When multiple interrupt requests are programmed to the same level number, they are processed in a
descending request number order. As an example, if requests 63, 62, 2, and 1 are programmed to a common
level, request 63 is processed first, then request 62, then request 2, and finally request 1.
This definition allows software maximum flexibility in grouping interrupt request sources within any
given priority level. The priority level in the ICRs directly corresponds to the interrupt level supported by
the ColdFire processor.
Address: 0xFC04_8040 – 7F (ICR000 – ICR063)
0xFC04_C040 – 7F (ICR100 – ICR163)
R
Access: User read/write
7
6
5
4
3
0
0
0
0
0
2
1
0
LEVEL
W
Reset:
0
0
0
0
0
0
0
0
Figure 15-12. Interrupt Control Registers (ICR0n, ICR1n)
Table 15-14. ICRn Field Descriptions
Field
7–3
2–0
LEVEL
Description
Reserved, must be cleared.
Interrupt level. Indicates the interrupt level assigned to each interrupt input. A level of 0 effectively disables the
interrupt request, while a level 7 interrupt is given the highest priority.
If interrupt masking is enabled (ICONFIG[EMASK] = 1), the acknowledgement of a level-n request forces the
controller to automatically mask all interrupt requests of level-n and lower.
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Interrupt Controller Modules
15.2.9.1
Interrupt Sources
Table 15-15 and Table 15-16 list the interrupt sources for each interrupt request line for INTC0 and
INTC1.
Table 15-15. Interrupt Source Assignment For INTC0
Source Module
Flag
Source Description
0
Not Used
1
EPFR[EPF1]
Edge port flag 1
Write EPF1 = 1
2
Not Used
3
Not Used
4
Flag Clearing Mechanism
EPORT
EPFR[EPF4]
Edge port flag 4
Write EPF4 = 1
5
Not Used
6
Not Used
7
EPFR[EPF7]
Edge port flag 7
Write EPF7 = 1
8
EDMA_INTR[INT00] DMA Channel 0 transfer complete
Write EDMA_CINTR[CINT] = 0
9
EDMA_INTR[INT01] DMA Channel 1 transfer complete
Write EDMA_CINTR[CINT] = 1
10
EDMA_INTR[INT02] DMA Channel 2 transfer complete
Write EDMA_CINTR[CINT] = 2
11
EDMA_INTR[INT03] DMA Channel 3 transfer complete
Write EDMA_CINTR[CINT] = 3
12
EDMA_INTR[INT04] DMA Channel 4transfer complete
Write EDMA_CINTR[CINT] = 4
13
EDMA_INTR[INT05] DMA Channel 5 transfer complete
Write EDMA_CINTR[CINT] = 5
14
EDMA_INTR[INT06] DMA Channel 6 transfer complete
Write EDMA_CINTR[CINT] = 6
15
EDMA_INTR[INT07] DMA Channel 7 transfer complete
Write EDMA_CINTR[CINT] = 7
EDMA_INTR[INT08] DMA Channel 8 transfer complete
Write EDMA_CINTR[CINT] = 8
17
EDMA_INTR[INT09] DMA Channel 9 transfer complete
Write EDMA_CINTR[CINT] = 9
18
EDMA_INTR[INT10] DMA Channel 10 transfer complete Write EDMA_CINTR[CINT] = 10
19
EDMA_INTR[INT11] DMA Channel 11 transfer complete Write EDMA_CINTR[CINT] = 11
20
EDMA_INTR[INT12] DMA Channel 12 transfer complete Write EDMA_CINTR[CINT] = 12
21
EDMA_INTR[INT13] DMA Channel 13 transfer complete Write EDMA_CINTR[CINT] = 13
22
EDMA_INTR[INT14] DMA Channel 14 transfer complete Write EDMA_CINTR[CINT] = 14
23
EDMA_INTR[INT15] DMA Channel 15 transfer complete Write EDMA_CINTR[CINT] = 15
24
EDMA_ERR[ERRn] DMA Error Interrupt
16
DMA
Write EDMA_CERR[CERR] = n
25
SCM
SCMIR[CWIC]
Core Watchdog Timeout
Write SCMISR[CWIC] = 1
26
UART0
UISR0 register
UART0 Interrupt Request
Automatically cleared
27
UART1
UISR1 register
UART1 Interrupt Request
Automatically cleared
28
UART2
UISR2 register
UART2 Interrupt Request
Automatically cleared
29
Not Used
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Interrupt Controller Modules
Table 15-15. Interrupt Source Assignment For INTC0 (continued)
Source Module
Flag
I2C
30
31
DSPI
Source Description
I2SR[IIF]
DSPI_SR register
Flag Clearing Mechanism
I2C Interrupt
Write I2SR[IIF] = 0
DSPI interrupt (Logical OR of
INTC1’s source #54–60)
Write 1 to appropriate DSPI_SR bit
32
DTIM0
DTER0 register
Timer 0 interrupt
Write 1 to appropriate DTER0 bit
33
DTIM1
DTER1 register
Timer 1 interrupt
Write 1 to appropriate DTER1 bit
34
DTIM2
DTER2 register
Timer 2 interrupt
Write 1 to appropriate DTER2 bit
35
DTIM3
DTER3 register
Timer 3 interrupt
Write 1 to appropriate DTER3 bit
36–61
Not Used
62
SCM
SCMIR[CFEI]
63
RTC
RTC_ISR
Core bus error interrupt
Write SCMIR[CFEI] = 1
Real Time Clock Interrupt
Write 1 to corresponding bit in RTC_ISR.
Table 15-16. Interrupt Source Assignment for INTC1
Source Module
Flag
0
1
BOFF_INT
Source Description
Flag Clearing Mechanism
Logical OR of CAN0’s MB requests
Write 1 to BUFnI after reading as 1
Bus-Off Interrupt
Write 0 to BOFF_INT
2
Not Used
3
ERR_INT
Error Interrupt
Read reported error bits in ESR or write 0 to ERR_INT
4
BUF0I
Message Buffer 0 Interrupt
Write 1 to BUF0I after reading as 1
5
BUF1I
Message Buffer 1 Interrupt
Write 1 to BUF1I after reading as 1
6
BUF2I
Message Buffer 2 Interrupt
Write 1 to BUF2I after reading as 1
7
BUF3I
Message Buffer 3 Interrupt
Write 1 to BUF3I after reading as 1
8
BUF4I
Message Buffer 4 Interrupt
Write 1 to BUF4I after reading as 1
BUF5I
Message Buffer 5 Interrupt
Write 1 to BUF5I after reading as 1
BUF6I
Message Buffer 6 Interrupt
Write 1 to BUF6I after reading as 1
11
BUF7I
Message Buffer 7 Interrupt
Write 1 to BUF7I after reading as 1
12
BUF8I
Message Buffer 8 Interrupt
Write 1 to BUF8I after reading as 1
13
BUF9I
Message Buffer 9 Interrupt
Write 1 to BUF9I after reading as 1
14
BUF10I
Message Buffer 10 Interrupt
Write 1 to BUF10I after reading as 1
15
BUF11I
Message Buffer 11 Interrupt
Write 1 to BUF11I after reading as 1
16
BUF12I
Message Buffer 12 Interrupt
Write 1 to BUF12I after reading as 1
17
BUF13I
Message Buffer 13 Interrupt
Write 1 to BUF13I after reading as 1
18
BUF14I
Message Buffer 14 Interrupt
Write 1 to BUF14I after reading as 1
19
BUF15I
Message Buffer 15 Interrupt
Write 1 to BUF15I after reading as 1
9
10
FLEX
CAN
20–42
Not Used
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Interrupt Controller Modules
Table 15-16. Interrupt Source Assignment for INTC1 (continued)
Source Module
Flag
Source Description
Flag Clearing Mechanism
43
PIT0
PCSR0[PIF]
PIT interrupt flag
Write PIF = 1 or write PMR
44
PIT1
PCSR1[PIF]
PIT interrupt flag
Write PIF = 1 or write PMR
45
Not Used
46
Not Used
47
USB
OTG
USB_STS
USB OTG interrupt
48
Not Used
49
SSI
SSI_ISR
50
PWM
PWMSDN[IF]
51
LCDC
LCD_ISR
SSI interrupt
Various, see chapter for details.
PWM interrupt
Write PWMSDN[IF] = 1
LCD controller interrupt
Read the LCD_ISR register.
52
53
Write 1 to corresponding bit in the USB_STS.
Not Used
CCM
UOCSR
USB status Interrupt
Read UOCSR.
54
DSPI_SR[EOQF]
End of queue interrupt
Write 1 to EOQF.
55
DSPI_SR[TFFF]
Transmit FIFO fill interrupt
Write 1 to TFFF.
56
DSPI_SR[TCF]
Transfer complete interrupt
Write 1 to TCF.
DSPI_SR[TFUF]
Transmit FIFO underflow interrupt
Write 1 to TFUF.
58
DSPI_SR[RFDF]
Receive FIFO not empty interrupt
Write 1 to RFDF after reading the DSPI_POPR register.
59
DSPI_SR[RFOF]
Receive FIFO overflow interrupt
Write 1 to RFOF.
57
DSPI
DSPI_SR[RFOF] or Receive FIFO overflow or
DSPI_SR[TFUF]
transmit FIFO underflow interrupt
60
61
Touch
screen
ASP_SR
62
PLL
PSR[LOCKS]
63
Write 1 to RFOF or TFUF.
Touchscreen controller interrupt
Depends on which ASP_SR bit is set
PLL loss-of-lock interrupt
Wrtie a 0 to PSR[LOCKS]
Not Used
15.2.10 Software and Level 1 – 7 IACK Registers (SWIACKn, L1IACKn –
L7IACKn)
The eight IACK registers (per interrupt controller) can be explicitly addressed via the CPU, or implicitly
addressed via a processor-generated interrupt acknowledge cycle during exception processing. In either
case, the interrupt controller’s actions are very similar.
First, consider an IACK cycle to a specific level: a level-n IACK. When this type of IACK arrives in the
interrupt controller, the controller examines all the currently-active level n interrupt requests, determines
the highest priority within the level, and then responds with the unique vector number corresponding to
that specific interrupt source. The vector number is supplied as the data for the byte-sized IACK read cycle.
In addition to providing the vector number, the interrupt controller also loads the level into the CLMASK
register, where it may be retrieved later.
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Interrupt Controller Modules
This interrupt controller design also supports the concept of a software IACK. A software IACK allows
an interrupt service routine to determine if there are other pending interrupts so that the overhead
associated with interrupt exception processing (including machine state save/restore functions) can be
minimized. In general, the software IACK is performed near the end of an interrupt service routine, and if
there are additional active interrupt sources, the current interrupt service routine (ISR) passes control to
the appropriate service routine, but without taking another interrupt exception.
When the interrupt controller receives a software IACK read, it returns the vector number associated with
the highest unmasked interrupt source for that interrupt controller. If there are no active sources, the
interrupt controller returns an all-zero vector as the operand for the SWIACK register. A read from the
LnIACK registers when there are no active requests returns a value of 24 (0x18), signaling a spurious
interrupt.
In addition to the software IACK registers in each interrupt controller, there are global software IACK
registers. A read from the global SWIACK (GSWIACK) returns the vector number for the highest level
and priority unmasked interrupt source from all interrupt controllers. A read from one of the global
LnIACK (GLnIACK) registers returns the vector for the highest priority unmasked interrupt within a level
for all interrupt controllers.
Address: 0xFC04_80E0 (SWIACK0)
0xFC04_80E0+4n (LnIACK0) n=1:7
0xFC04_C0E0 (SWIACK1)
0xFC04_C0E0+4n (LnIACK1) n=1:7
0xFC05_40E0 (GSWIACK)
0xFC05_40E0+4n (GLnIACK) n=1:7
7
6
5
Access: User read-only
4
R
3
2
1
0
VECTOR
W
Reset
(SWIACKn):
0
0
0
0
0
0
0
0
Reset
(LnIACKn):
0
0
0
1
1
0
0
0
Figure 15-13. Software and Level n IACK Registers (SWIACKn, L1IACKn – L7IACKn)
Table 15-17. SWIACKn and LxIACKn Field Descriptions
Field
7–0
VECTOR
Description
Vector number. A read from the SWIACK register returns the vector number associated with the highest priority
pending interrupt source. A read from one of the LnIACK registers returns the highest priority unmasked interrupt
source within the level.
A write to any IACK register causes an error termination.
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Interrupt Controller Modules
15.3
Functional Description
15.3.1
Interrupt Controller Theory of Operation
To support the interrupt architecture of the 68K/ColdFire programming model, the 64 interrupt sources are
organized as 7 levels, with an arbitrary number of requests programmed to each level. The priority
structure within a single interrupt level depends on the interrupt source number assignments (see
Section 15.2.9.1, “Interrupt Sources”). The higher numbered interrupt source has priority over the lower
numbered interrupt source. See the below table for an example.
Table 15-18. Example Interrupt Priority Within a Level
Interrupt Source
ICR[2:0]
Priority
40
011
Highest
22
011
8
011
2
011
Lowest
The level is fully programmable for all sources. The 3-bit level is defined in the interrupt control register
(ICR0n, ICR1n).
The operation of the interrupt controller can be broadly partitioned into three activities:
• Recognition
• Prioritization
• Vector determination during IACK
15.3.1.1
Interrupt Recognition
The interrupt controller continuously examines the request sources (IPRn) and the interrupt mask register
(IMRn) to determine if there are active requests. This is the recognition phase. The interrupt force register
(INTFRCn) also factors into the generation of an active request.
15.3.1.2
Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level. Next, the appropriate
level masking is performed if this feature is enabled. The level of the active request must be greater than
the current mask level before it is signaled in the processor. The resulting unmasked decoded priority level
is driven out of the interrupt controller. The decoded priority levels from the interrupt controllers are
logically summed together, and the highest enabled interrupt request is sent to the processor core during
this prioritization phase.
15.3.1.3
Interrupt Vector Determination
After the core has sampled for pending interrupts and begun interrupt exception processing, it generates
an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a memory-mapped byte read by
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Interrupt Controller Modules
the processor, and routed to the appropriate interrupt controller. Next, the interrupt controller extracts the
level being acknowledged from address bits[4:2], and then determines the highest unmasked level for the
type of interrupt being acknowledged, and returns the 8-bit interrupt vector for that request to complete the
cycle. The 8-bit interrupt vector is formed using the following algorithm:
For INTC0,
vector_number = 64 + interrupt source number
For INTC1,
vector_number = 128 + interrupt source number
Recall vector_numbers 0-63 are reserved for the ColdFire processor and its internal exceptions. Thus, the
following mapping of bit positions to vector numbers applies for INTC0:
if interrupt source 0 is active and acknowledged, then vector_number =
64
if interrupt source 1 is active and acknowledged, then vector_number =
65
if interrupt source 2 is active and acknowledged, then vector_number =
66
...
if interrupt source 63 is active and acknowledged, then vector_number = 127
The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector
number.
If there is no active interrupt source for the given level, a special spurious interrupt vector (vector_number
equals 24) is returned and it is the responsibility of the service routine to manage this error situation.
This protocol implies the interrupting peripheral is not accessed during the acknowledge cycle because the
interrupt controller completely services the acknowledge. This means the interrupt source must be
explicitly disabled in the interrupt service routine. This design provides unique vector capability for all
interrupt requests, regardless of the complexity of the peripheral device.
In some applications, it is expected that the hardware masking of interrupt levels by the interrupt controller
is enabled. This masking capability can be used with the processor’s masking logic to form a dual-mask
capability. In this operation mode, the IACK read cycle also causes the current interrupt level mask to be
saved in the SLMASK register, and the new level being acknowledged loaded into the CLMASK register.
This operation then automatically masks the new level (and all lower levels) while in the service routine.
Generally, as the service routine completes execution, and the initiating request source has been negated,
the saved mask level is restored into the current mask level to re-enable the lower priority levels.
Finally, the vector number returned during the IACK cycle provides the association with the request and
the physical interrupt signal. The CLMASK and SLMASK registers are all loaded (if properly enabled)
during the interrupt acknowledge read cycle.
15.3.2
Prioritization Between Interrupt Controllers
The interrupt controllers have a fixed priority, where INTC0 has the highest priority, and INTC1 has the
lowest priority. If both interrupt controllers have active interrupts at the same level, then the INTC0
interrupt is serviced first. If INTC1 has an active interrupt with a higher level than the highest INTC0
interrupt, then the INTC1 interrupt is serviced first.
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Interrupt Controller Modules
15.3.3
Low-Power Wake-up Operation
The system control module (SCM) contains an 8-bit low-power control register (LPCR) to control the
low-power stop mode. This register must be explicitly programmed by software to enter low-power mode.
It also contains a wake-up control register (WCR) sets the priority level of the interrupt necessary to bring
the device out of the specified low-power mode. Refer to Chapter 8, “Power Management,” for definitions
of the LPCR and WCR registers, as well as more information on low-power modes.
Each interrupt controller provides a special combinatorial logic path to provide a special wake-up signal
to exit from the low-power stop mode. This special mode of operation works as follows:
1. The WCR register is programmed, setting the ENBWCR bit and the desired interrupt priority level.
2. At the appropriate time, the processor executes the privileged STOP instruction. After the
processor has stopped execution, it asserts a specific processor status (PST) encoding. Issuing the
STOP instruction when the WCR[ENBWCR] bit is set causes the SCM to enter the mode specified
in LPCR[LPMD].
3. The entry into a low-power mode is processed by the low-power mode control logic, and the
appropriate clocks (usually those related to the high-speed processor core) are disabled.
4. After entering the low-power mode, the interrupt controller enables a combinational logic path
which evaluates any unmasked interrupt requests. The device waits for an event to generate a level
7 interrupt request or an interrupt request with a priority level greater than the value programmed
in WCR[PRILVL].
5. After an appropriately high interrupt request level arrives, the interrupt controller signals its
presence, and the SCM responds by asserting the request to exit low-power mode.
6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.
7. With the processor clocks enabled, the core processes the pending interrupt request.
For more information, see Section 8.2.1, “Wake-up Control Register (WCR)”.
15.4
Initialization/Application Information
The interrupt controller’s reset state has all requests masked via the IMR. Before any interrupt requests are
enabled, the following steps must be taken:
1. Set the ICONFIG register to the desired system configuration.
2. Program the ICRn registers with the appropriate interrupt levels.
3. The reset value for the level mask registers (CLMASK and SLMASK) is 0xF (no levels masked).
Typically, these registers do not need to be modified before interrupts are enabled.
4. Load the appropriate interrupt vector tables and interrupt service routines into memory.
5. Enable the interrupt requests, by clearing the appropriate bits in the IMR and lowering the interrupt
mask level in the core’s status register (SR[I]) to an appropriate level.
15.4.1
Interrupt Service Routines
This section focuses on the interaction of the interrupt masking functionality with the service routine.
Figure 15-14 presents a timing diagram showing various phases during the execution of an interrupt
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Interrupt Controller Modules
service routine with the controller level masking functionality enabled. The time scale in this diagram is
not meant to be accurate.
A
B
C
D
E
F
Interrupt
Request
Interrupt Service Routine
Core
Activity
iack
n
SR[I]
CLMASK
0xF
SLMASK
Interrupts
swiack
n
n
0xF
0xF
Enabled
≤ n Disabled
Note: Not to scale
Figure 15-14. Interrupt Service Routine and Masking
Consider the events depicted in each segment (A – F) of the above diagram.
In A, an interrupt request is asserted, which is then signalled to the core.
As B begins, the interrupt request is recognized, and the core begins interrupt exception processing. During
the core’s exception processing, the IACK cycle performs and the interrupt controller returns the
appropriate vector number. As the interrupt acknowledge read performs, the vector number returns to the
core. The contents of the CLMASK register load into the SLMASK register, and the CLMASK register
updates to the level of the acknowledge interrupt. Additionally, the processor raises the interrupt mask in
the status register (SR[I]) to match the level of the acknowledged request. At the end of the core’s
exception processing, control passes to the interrupt service routine (ISR), shown as the beginning of
segment C.
During C, the initial portion of the ISR executes. Near the end of this segment, the ISR accesses the
peripheral to negate the interrupt request source. At the conclusion of segment C, the SR[I] field can be
lowered to re-enable interrupts with a priority greater than the original request.
The bulk of the interrupt service routine executes in segment D, with interrupts enabled. Near the end of
the service routine, the SR[I] field is again raised to the original acknowledged level, preparing to perform
the context switch.
At the end of segment E, the original value in the saved level mask (SLMASK) is restored in the current
level mask (CLMASK). Optionally, the service routine can directly load the CLMASK register with any
value with pending interrupt requests of certain levels need to be examined.
In segment F, the interrupt service routine completes execution. During this period of time, it is possible
to access the interrupt controller with a software IACK to see if there are any pending properly-enabled
requests. Checking for any pending interrupt requests at this time provides ability to initiate processing of
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Interrupt Controller Modules
another interrupt without the need to return from the original and incur the overhead of another interrupt
exception.
At the conclusion of segment G, the processor core returns to the original interrupted task or a different
task ready to execute.
Obviously, there are many variations to the managing of the SR[I] and the CLMASK values to create a
flexible, responsive system for managing interrupt requests within the device.
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Chapter 16
Edge Port Module (EPORT)
16.1
Introduction
The edge port module (EPORT) has up to eight interrupt pins, IRQ7 – IRQ0. Each pin can be configured
individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or
both), or a general-purpose input/output (I/O) pin.
NOTE
Not all EPORT signals may be output from the device. See Chapter 2,
“Signal Descriptions,” to determine which signals are available.
Stop
Mode
EPPAR[2n, 2n + 1]
Edge Detect
Logic
EPFRn
D0
Internal Bus
Q
D0
D1
Q
D1
To Interrupt
Controller
EPPDRn
Synchronizer
Rising Edge
of System Clock
EPIERn
IRQn pin
Figure 16-1. EPORT Block Diagram
NOTE
The GPIO module must be configured to enable the peripheral function of
the appropriate pins (refer to Chapter 14, “General Purpose I/O Module”)
prior to configuring the edge-port module.
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16-1
Edge Port Module (EPORT)
16.2
Low-Power Mode Operation
This section describes the operation of the EPORT module in low-power modes. For more information on
low-power modes, see Chapter 8, “Power Management”. Table 16-1 shows EPORT-module operation in
low-power modes and describes how this module may exit each mode.
NOTE
The wakeup control register (WCR) in the system control module specifies
the interrupt level at or above what is needed to bring the device out of a
low-power mode.
Table 16-1. Edge Port Module Operation in Low-Power Modes
Low-power Mode
EPORT Operation
Mode Exit
Wait
Normal
Any IRQn interrupt at or above level in WCR
Doze
Normal
Any IRQn interrupt at or above level in WCR
Stop
Level-sensing only
Any IRQn interrupt set for level-sensing at or
above level in WCR. See note below.
In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may be
configured to exit the low-power modes by generating an interrupt request on a selected edge or a low level
on an external pin. In stop mode, no clocks are available to perform the edge-detect function. Only the
level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate
an interrupt (if enabled) to exit stop mode.
NOTE
In stop mode, the input pin synchronizer is bypassed for the level-detect
logic because no clocks are available.
16.3
Signal Descriptions
All EPORT pins default to general-purpose input pins at reset. The pin value is synchronized to the rising
edge of FB_CLK when read from the EPORT pin data register (EPPDR). The values used in the edge/level
detect logic are also synchronized to the rising edge of FB_CLK. These pins use Schmitt-triggered input
buffers with built-in hysteresis designed to decrease the probability of generating false, edge-triggered
interrupts for slow rising and falling input signals.
When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding
bit in the EPORT data register (EPDR). All bits in the EPDR are set at reset.
16.4
Memory Map/Register Definition
This subsection describes the memory map and register structure. Refer to Table 16-2 for a description of
the EPORT memory map.
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Edge Port Module (EPORT)
NOTE
Longword accesses to any of the edge-port registers result in a bus error.
Only byte and word accesses are allowed.
Table 16-2. Edge Port Module Memory Map
Address
Width
Access Reset Value
(bits)
Register
Section/Page
Supervisor Access Only Registers1
0xFC09_4000 EPORT Pin Assignment Register (EPPAR)
16
R/W
0x0000
16.4.1/16-3
0xFC09_4002 EPORT Data Direction Register (EPDDR)
8
R/W
0x00
16.4.2/16-4
0xFC09_4003 EPORT Interrupt Enable Register (EPIER)
8
R/W
0x00
16.4.3/16-5
Supervisor/User Access Registers
1
0xFC09_4004 EPORT Data Register (EPDR)
8
R/W
0xFF
16.4.4/16-5
0xFC09_4005 EPORT Pin Data Register (EPPDR)
8
R
See Section
16.4.5/16-5
0xFC09_4006 EPORT Flag Register (EPFR)
8
R/W
0x00
16.4.6/16-6
User access to supervisor-only address locations have no effect and result in a bus error.
16.4.1
EPORT Pin Assignment Register (EPPAR)
The EPORT pin assignment register (EPPAR) controls the function of each pin individually.
Address: 0xFC09_4000 (EPPAR)
EPDRn
15
R
W
Reset
14
EPPA7
0
0
13
Access: Supervisor read/write
12
EPPA6
EPDDRn
0
0
11
10
EPPA5
0
0
9
8
EPPA4
0
0
7
6
EPPA3
0
0
5
4
EPPA2
0
0
3
2
EPPA1
0
0
1
0
EPPA0
0
0
Figure 16-2. EPORT Pin Assignment Register (EPPAR)
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Freescale Semiconductor
16-3
Edge Port Module (EPORT)
Table 16-3. EPPAR Field Descriptions
Field
Description
15–0
EPPAn
EPORT pin assignment select fields. The read/write EPPAn fields configure EPORT pins for level detection and rising
and/or falling edge detection.
Pins configured as level-sensitive are active-low (logic 0 on the external pin represents a valid interrupt request).
Level-sensitive interrupt inputs are not latched. To guarantee that a level-sensitive interrupt request is acknowledged,
the interrupt source must keep the signal asserted until acknowledged by software. Level sensitivity must be selected
to bring the device out of stop mode with an IRQn interrupt.
Pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. A pin
configured for edge detection can trigger an interrupt regardless of its configuration as input or output.
Interrupt requests generated in the EPORT module can be masked by the interrupt controller module. EPPAR
functionality is independent of the selected pin direction.
Reset clears the EPPAn fields.
00 Pin IRQn level-sensitive
01 Pin IRQn rising edge triggered
10 Pin IRQn falling edge triggered
11 Pin IRQn falling edge and rising edge triggered
16.4.2
EPORT Data Direction Register (EPDDR)
The EPORT data direction register (EPDDR) controls the direction of each one of the pins individually.
Address: 0xFC09_4002 (EPDDR)
R
W
Reset
Access: Supervisor read/write
7
6
5
4
3
2
1
0
EPDD7
EPDD6
EPDD5
EPDD4
EPDD3
EPDD2
EPDD1
EPDD0
0
0
0
0
0
0
0
0
Figure 16-3. EPORT Data Direction Register (EPDDR)
Table 16-4. EPDDR Field Descriptions
Field
Description
7–0
EPDDn
Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in EPDDR configures
the corresponding pin as an input. Pin direction is independent of the level/edge detection configuration. Reset clears
EPDD7–EPDD0.
To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear.
Software can generate interrupt requests by programming the EPORT data register when the EPDDR selects output.
0 Corresponding EPORT pin configured as input
1 Corresponding EPORT pin configured as output
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Freescale Semiconductor
Edge Port Module (EPORT)
16.4.3
Edge Port Interrupt Enable Register (EPIER)
The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin individually.
Address: 0xFC09_4003 (EPIER)
Access: User read/write
7
6
5
4
3
2
1
0
EPIE7
EPIE6
EPIE5
EPIE4
EPIE3
EPIE2
EPIE1
EPIE0
0
0
0
0
0
0
0
0
R
W
Reset:
Figure 16-4. EPORT Port Interrupt Enable Register (EPIER)
Table 16-5. EPIER Field Descriptions
Field
7–0
EPIEn
Description
Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set, EPORT generates an
interrupt request when:
• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set
• The corresponding pin level is low and the pin is configured for level-sensitive operation
Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin. Reset clears
EPIE7–EPIE0.
0 Interrupt requests from corresponding EPORT pin disabled
1 Interrupt requests from corresponding EPORT pin enabled
16.4.4
Edge Port Data Register (EPDR)
The EPORT data register (EPDR) holds the data to be driven to the pins.
Address: 0xFC09_4004 (EPDR)
Access: User read/write
7
6
5
4
3
2
1
0
EPD7
EPD6
EPD5
EPD4
EPD3
EPD2
EPD1
EPD0
1
1
1
1
1
1
1
1
R
W
Reset:
Figure 16-5. EPORT Port Data Register (EPDR)
Table 16-6. EPDR Field Descriptions
Field
Description
7–0
EPDn
Edge port data bits. An internal register stores data written to EPDR; if any pin of the port is configured as an output,
the bit stored for that pin is driven onto the pin. Reading EDPR returns the data stored in the register. Reset sets
EPD7 – EPD0.
16.4.5
Edge Port Pin Data Register (EPPDR)
The EPORT pin data register (EPPDR) reflects the current state of the pins.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
16-5
Edge Port Module (EPORT)
Address: 0xFC09_4005 (EPPDR)
R
Access: User read-only
7
6
5
4
3
2
1
0
EPPD7
EPPD6
EPPD5
EPPD4
EPPD3
EPPD2
EPPD1
EPPD0
[IRQ7]
[IRQ6]
[IRQ5]
[IRQ4]
[IRQ3]
[IRQ2]
[IRQ1]
[IRQ0]
W
Reset:
Figure 16-6. EPORT Port Pin Data Register (EPPDR)
Table 16-7. EPPDR Field Descriptions
Field
Description
7–0
EPPDn
Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins IRQ7 – IRQ0. Writing to
EPPDR has no effect, and the write cycle terminates normally. Reset does not affect EPPDR.
16.4.6
Edge Port Flag Register (EPFR)
The EPORT flag register (EPFR) individually latches EPORT edge events.
Address: 0xFC09_4006 (EPFR)
Access: User read/write
7
6
5
4
3
2
1
0
R
EPF7
EPF6
EPF5
EPF4
EPF3
EPF2
EPF1
EPF0
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
Reset:
Figure 16-7. EPORT Port Flag Register (EPFR)
Table 16-8. EPFR Field Descriptions
Field
Description
7–0
EPFn
Edge port flag bits. When an EPORT pin is configured for edge triggering, its corresponding read/write bit in EPFR
indicates that the selected edge has been detected. Reset clears EPF7 – EPF0.
Bits in this register are set when the selected edge is detected on the corresponding pin. A bit remains set until
cleared by writing a 1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARn = 00), pin
transitions do not affect this register.
0 Selected edge for IRQn pin not detected
1 Selected edge for IRQn pin detected
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Chapter 17
Enhanced Direct Memory Access (eDMA)
17.1
Overview
The enhanced direct memory access (eDMA) controller is a second-generation module capable of
performing complex data transfers with minimal intervention from a host processor. The hardware
microarchitecture includes a DMA engine that performs source- and destination-address calculations, and
the actual data-movement operations, along with local memory containing transfer control descriptors for
each channel.
17.1.1
Block Diagram
Figure 17-1 is a block diagram of the eDMA module.
eDMA
Write Address
Write Data
0
Transfer Control
Descriptor (TCD)
15
64
eDMA Engine
Program Model/
Channel Arbitration
Read Data
Internal Peripheral Bus
To/From Crossbar Switch
1
2
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA Peripheral
Request
eDMA Done
Figure 17-1. eDMA Block Diagram
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
17-1
Enhanced Direct Memory Access (eDMA)
17.1.2
Features
The eDMA is a highly-programmable data-transfer engine optimized to minimize the required
intervention from the host processor. It is intended for use in applications where the data size to be
transferred is statically known and not defined within the data packet itself. The eDMA module features:
• All data movement via dual-address transfers: read from source, write to destination
— Programmable source and destination addresses and transfer size, plus support for enhanced
addressing modes
• 16-channel implementation that performs complex data transfers with minimal intervention from
a host processor
— Internal data buffer, used as temporary storage to support 16-byte burst transfers
— Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
— 32-byte TCD stored in local memory for each channel
— An inner data transfer loop defined by a minor byte transfer count
— An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continual transfers
— Peripheral-paced hardware requests (one per channel)
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are optionally enabled per channel and logically summed together to form
one error interrupt to the interrupt controller
• Optional support for scatter/gather DMA processing
Throughout this chapter, n is used to reference the channel number.
17.2
17.2.1
Modes of Operation
Normal Mode
In normal mode, the eDMA transfers data between a source and a destination. The source and destination
can be a memory block or an I/O block capable of operation with the eDMA.
A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the transfer
control descriptor (TCD). The minor loop is the sequence of read-write operations that transfers these
NBYTES per service request. A major loop is the number of minor loop iterations defining a task.
MCF52277 Reference Manual, Rev 2
17-2
Freescale Semiconductor
Enhanced Direct Memory Access (eDMA)
17.2.2
Debug Mode
In debug mode, the eDMA stops transferring data. If debug mode is entered during the transfer of a data
block described by a minor loop in the current active channel’s TCD, the eDMA continues operation until
completion of the minor loop.
17.3
External Signal Description
This section describes the external signals of the eDMA controller.
Table 17-1. External Signal List
17.3.1
Signal Name
I/O
Description
DREQ0
I
Provides external requests from peripherals needing DMA service. When
asserted, the device is requesting service. This request pin is tied to DMA
channel 0.
DACK0
O
Indicates when the external DMA request has been acknowledged.
External Signal Timing
Asserting the external DMA request signal, DREQn, initiates a service request for that channel. It must
remain asserted until the corresponding DACKn signal indicates the channel’s data transfer has started.
The DACKn output is asserted for one cycle during the address phase of the channel’s first internal read
access.
• When no further requests are needed, the DREQn signal must negate after the DACKn assertion
and on or before the second cycle following the data phase of the last internal bus write (see
Figure 17-2).
• If another service request is needed, DREQn may simply remain asserted.
• To request continuous service, DREQn may remain continuously asserted.
Internal
Bus Clock
Internal
Address Phase
Internal
Data Phase
rd1
wr1
rd2
wr2
rd1
wr1
rd2
wr2
DREQn
DACKn
Figure 17-2. DREQn and DACKn Timing
After a service request has been initiated, it cannot be canceled. Removing a service request after it has
been asserted may result in one of three actions depending on the DMA engine’s status:
• The request is never recognized because another channel is executing.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
17-3
Enhanced Direct Memory Access (eDMA)
•
•
The request is considered spurious and discarded, because the request is removed during arbitration
for next channel selection.
The channel is selected by arbitration and begins execution.
17.4
Memory Map/Register Definition
The eDMA’s programming model is partitioned into two regions: the first region defines a number of
registers providing control functions, while the second region corresponds to the local transfer control
descriptor memory.
Reading reserved bits in a register return the value of zero and writes to reserved bits in a register are
ignored. Reading or writing to a reserved memory location generates a bus error.
Table 17-2. eDMA Controller Memory Map
Address
Register
Width
Access
(bits)
Reset Value
Section/Page
0xFC04_4000 eDMA Control Register (EDMA_CR)
32
R/W
0x0000_0000
17.4.1/17-4
0xFC04_4004 eDMA Error Status Register (EDMA_ES)
32
R
0x0000_0000
17.4.2/17-5
0xFC04_400E eDMA Enable Request Register (EDMA_ERQ)
16
R/W
0x0000
17.4.3/17-8
0xFC04_4016 eDMA Enable Error Interrupt Register (EDMA_EEI)
16
R/W
0x0000
17.4.4/17-9
0xFC04_4018 eDMA Set Enable Request (EDMA_SERQ)
8
W
0x00
17.4.5/17-10
0xFC04_4019 eDMA Clear Enable Request (EDMA_CERQ)
8
W
0x00
17.4.6/17-10
0xFC04_401A eDMA Set Enable Error Interrupt Register (EDMA_SEEI)
8
W
0x00
17.4.7/17-11
0xFC04_401B eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)
8
W
0x00
17.4.8/17-11
0xFC04_401C eDMA Clear Interrupt Request Register (EDMA_CINT)
8
W
0x00
17.4.9/17-12
0xFC04_401D eDMA Clear Error Register (EDMA_CERR)
8
W
0x00
17.4.10/17-13
0xFC04_401E eDMA Set START Bit Register (EDMA_SSRT)
8
W
0x00
17.4.11/17-13
0xFC04_401F eDMA Clear DONE Status Bit Register (EDMA_CDNE)
8
W
0x00
17.4.12/17-14
0xFC04_4026 eDMA Interrupt Request Register (EDMA_INT)
32
R/W
0x0000
17.4.13/17-15
0xFC04_402E eDMA Error Register (EDMA_ERR)
32
R/W
0x0000
17.4.14/17-15
0xFC04_4100 eDMA Channel n Priority Register (DCHPRIn)
+ hex(n)
for n = 0 – 15
8
R/W
See Section
17.4.15/17-16
256
R/W
See Section
17.4.16/17-17
0xFC04_5000 Transfer Control Descriptor (TCDn)
+ hex(32×n) for n = 0 – 15
17.4.1
eDMA Control Register (EDMA_CR)
The EDMA_CR defines the basic operating configuration of the eDMA. Arbitration can be configured to
use a fixed-priority or a round-robin scheme. In fixed-priority arbitration, the highest priority channel
requesting service is selected to execute. The channel priority registers assign the priorities (see
Section 17.4.15, “eDMA Channel n Priority Registers (DCHPRIn)”). In round-robin arbitration mode, the
channel priorities are ignored, and channels are cycled through without regard to priority.
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
Enhanced Direct Memory Access (eDMA)
NOTE
For proper operation, writes to the EDMA_CR register must only be
performed when the DMA channels are inactive (TCRn_CSR[ACTIVE]
bits are cleared).
Address: 0xFC04_4000 (EDMA_CR)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
ERCA EDBG
0
0
0
0
0
Figure 17-3. eDMA Control Register (EDMA_CR)
Table 17-3. EDMA_CR Field Descriptions
Field
Description
31–8
Reserved, must be cleared.
7–3
Reserved, should be cleared.
2
ERCA
Enable round robin channel arbitration.
0 Fixed priority arbitration is used for channel selection.
1 Round robin arbitration is used for channel selection.
1
EDBG
Enable debug.
0 When in debug mode the DMA continues to operate.
1 When in debug mode, the eDMA stalls the start of a new channel. Executing channels are allowed to complete.
Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
0
17.4.2
Reserved, must be cleared.
eDMA Error Status Register (EDMA_ES)
The EDMA_ES provides information concerning the last recorded channel error. Channel errors can be
caused by a configuration error (an illegal setting in the transfer-control descriptor or an illegal priority
register setting in fixed-arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is reported when the starting source or destination address, source or destination
offsets, minor loop byte count, or the transfer size represent an inconsistent state. Each of these possible
causes are detailed in the below list:
• The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries
• The minor loop byte count must be a multiple of the source and destination transfer sizes.
• All source reads and destination writes must be configured to the natural boundary of the
programmed transfer size respectively.
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Freescale Semiconductor
17-5
Enhanced Direct Memory Access (eDMA)
•
•
•
In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal.
All channel priority levels must be unique when fixed arbitration mode is enabled.
If a scatter/gather operation is enabled upon channel completion, a configuration error is reported
if the scatter/gather address (DLAST_SGA) is not aligned on a 32-byte boundary.
If minor loop channel linking is enabled upon channel completion, a configuration error is reported
when the link is attempted if the TCDn_CITER[E_LINK] bit does not equal the
TCDn_BITER[E_LINK] bit.
If enabled, all configuration error conditions, except the scatter/gather and minor-loop link errors, report
as the channel activates and asserts an error interrupt request. A scatter/gather configuration error is
reported when the scatter/gather operation begins at major loop completion when properly enabled. A
minor loop channel link configuration error is reported when the link operation is serviced at minor loop
completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate
bus error flag set. In this case, the state of the channel's transfer control descriptor is updated by the eDMA
engine with the current source address, destination address and current iteration count at the point of the
fault. When a system-bus error occurs, the channel terminates after the read or write transaction (which is
already pipelined after errant access) has completed. If a bus error occurs on the last read prior to beginning
the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on
the last write prior to switching to the next read sequence, the read sequence executes before the channel
terminates due to the destination bus error.
The occurrence of any error causes the eDMA engine to stop the active channel immediately, and the
appropriate channel bit in the eDMA error register is asserted. At the same time, the details of the error
condition are loaded into the EDMA_ES. The major loop complete indicators, setting the transfer control
descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is
detected. After the error status has been updated, the eDMA engine continues operating by servicing the
next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a
channel is terminated by an error and then issues another service request before the error is fixed, that
channel executes and terminate with the same error condition.
Address: 0xFC04_4004 (EDMA_ES)
31
Access: User read-only
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
CPE
0
0
0
0
0
0
R VLD
W
Reset
R
0
ERRCHN
7
6
5
4
3
2
1
0
SAE
SOE
DAE
DOE
NCE
SGE
SBE
DBE
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
Figure 17-4. eDMA Error Status Register (EDMA_ES)
MCF52277 Reference Manual, Rev 2
17-6
Freescale Semiconductor
Enhanced Direct Memory Access (eDMA)
Table 17-4. EDMA_ES Field Descriptions
Field
31
VLD
30–15
14
CPE
13–12
11–8
ERRCHN
Description
Logical OR of all EDMA_ERR status bits
0 No EDMA_ERR bits are set
1 At least one EDMA_ERR bit is set indicating a valid error exists that has not been cleared
Reserved, must be cleared.
Channel priority error
0 No channel priority error
1 The last recorded error was a configuration error in the channel priorities. Channel priorities are not unique.
Reserved, must be cleared.
Error channel number. The channel number of the last recorded error (excluding CPE errors).
7
SAE
Source address error.
0 No source address configuration error.
1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is
inconsistent with TCDn_ATTR[SSIZE]
6
SOE
Source offset error.
0 No source offset configuration error.
1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is
inconsistent with TCDn_ATTR[SSIZE].
5
DAE
Destination address error.
0 No destination address configuration error.
1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is
inconsistent with TCDn_ATTR[DSIZE].
4
DOE
Destination offset error.
0 No destination offset configuration error.
1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is
inconsistent with TCDn_ATTR[DSIZE].
3
NCE
NBYTES/CITER configuration error.
0 No NBYTES/CITER configuration error.
1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
• TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or
• TCDn_CITER[CITER] is equal to zero, or
• TCDn_CITER[E_LINK] is not equal to TCDn_BITER[E_LINK].
2
SGE
Scatter/gather configuration error.
0 No scatter/gather configuration error.
1 The last recorded error was a configuration error detected in the TCDn_DLAST_SGA field. This field is
checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[E_SG] is
enabled. TCDn_DLAST_SGA is not on a 32 byte boundary.
1
SBE
Source bus error.
0 No source bus error.
1 The last recorded error was a bus error on a source read.
0
DBE
Destination bus error.
0 No destination bus error.
1 The last recorded error was a bus error on a destination write.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
17-7
Enhanced Direct Memory Access (eDMA)
17.4.3
eDMA Enable Request Register (EDMA_ERQ)
The EDMA_ERQ register provides a bit map for the 16 implemented channels to enable the request signal
for each channel. The state of any given channel enable is directly affected by writes to this register; it is
also affected by writes to the EDMA_SERQ and EDMA_CERQ. The EDMA_{S,C}ERQR are provided
so the request enable for a single channel can easily be modified without needing to perform a
read-modify-write sequence to the EDMA_ERQ.
DMA request input signals and this enable request flag must be asserted before a channel’s hardware
service request is accepted. The state of the eDMA enable request flag does not affect a channel service
request made explicitly through software or a linked channel request.
Address: 0xFC04_400E (EDMA_ERQ)
15
R ERQ
W 15
Reset
0
Access: User read/write
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERQ
14
ERQ
13
ERQ
12
ERQ
11
ERQ
10
ERQ
9
ERQ
8
ERQ
7
ERQ
6
ERQ
5
ERQ
4
ERQ
3
ERQ
2
ERQ
1
ERQ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-5. eDMA Enable Request Register (EDMA_ERQ)
Table 17-5. EDMA_ERQ Field Descriptions
Field
15–0
ERQn
Description
Enable DMA Request n.
0 The DMA request signal for channel n is disabled.
1 The DMA request signal for channel n is enabled.
The assignments between the DMA requests from the peripherals to the channels of the eDMA are shown
in Table 17-6.
Table 17-6. DMA Request Summary for eDMA
Channel
Source
Description
0
DREQ0
External DMA request 0
1
—
Reserved/Not used
2
ASP_ISR
Touchscreen
3
UISR0[FFULL/RXRDY]
UART0 Receive
4
UISR0[TXRDY]
UART0 Transmit
5
UISR1[FFULL/RXRDY]
UART1 Receive
6
UISR1[TXRDY]
UART1 Transmit
7
UISR2[FFULL/RXRDY]
UART2 Receive
8
UISR2[TXRDY]
UART2 Transmit
9
DTER0[CAP] or DTER0[REF] /
SSISR[RFF0]
Timer 0 / SSI0 Receive1
10
DTER1[CAP] or DTER1[REF] /
SSISR[RFF1]
Timer 1 / SSI1 Receive1
MCF52277 Reference Manual, Rev 2
17-8
Freescale Semiconductor
Enhanced Direct Memory Access (eDMA)
Table 17-6. DMA Request Summary for eDMA (continued)
Channel
Source
Description
11
DTER2[CAP] or DTER2[REF] /
SSISR[TFE0]
Timer 2 / SSI0 Transmit1
12
DTER3[CAP] or DTER3[REF] /
SSISR[TFE1]
Timer 3 / SSI1 Transmit1
13
DSPI_SR[RFDF]
DSPI Receive
14
DSPI_SR[TFFF]
DSPI Transmit
15
—
Reserved/Not used
1
For information on how to select between SSI and Timer sources, refer to
Chapter 9, “Chip Configuration Module (CCM).”
As a given channel completes the processing of its major iteration count, a flag in the transfer control
descriptor that affect the ending state of the EDMA_ERQ bit for that channel. If the TCDn_CSR[D_REQ]
bit is set, the corresponding EDMA_ERQ bit is cleared, disabling the DMA request. If the D_REQ bit
clears, the state of the EDMA_ERQ bit is unaffected.
17.4.4
eDMA Enable Error Interrupt Registers (EDMA_EEI)
The EDMA_EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each
channel. The state of any given channel’s error interrupt enable is directly affected by writes to this
register; it is also affected by writes to the EDMA_SEEI and EDMA_CEEI. The EDMA_{S,C}EEIR are
provided so the error interrupt enable for a single channel can easily be modified without the need to
perform a read-modify-write sequence to the EDMA_EEI register.
The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt
request for a given channel is asserted to the interrupt controller.
Address: 0xFC04_4016 (EDNA_EEI)
15
R
W
Reset
14
13
12
Access: User read/write
11
10
9
EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
EEI8
EEI7
EEI6
EEI5
EEI4
EEI3
EEI2
EEI1
EEI0
0
0
0
0
0
0
0
0
0
Figure 17-6. eDMA Enable Error Interrupt Register (EDMA_EEI)
Table 17-7. EDMA_EEI Field Descriptions
Field
15–0
EEIn
Description
Enable error interrupt n.
0 The error signal for channel n does not generate an error interrupt.
1 The assertion of the error signal for channel n generates an error interrupt request.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
17-9
Enhanced Direct Memory Access (eDMA)
17.4.5
eDMA Set Enable Request Register (EDMA_SERQ)
The EDMA_SERQ provides a simple memory-mapped mechanism to set a given bit in the EDMA_ERQ
to enable the DMA request for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire
contents of EDMA_ERQ to be set. Reads of this register return all zeroes.
Address: 0xFC04_4018 (EDMA_SERQ)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Access: User write-only
SAER
0
SERQ
0
0
0
0
0
Figure 17-7. eDMA Set Enable Request Register (EDMA_SERQ)
Table 17-8. EDMA_SERQ Field Descriptions
Field
7
Description
Reserved, must be cleared.
6
SAER
5–4
3–0
SERQ
17.4.6
Set all enable requests.
0 Set only those EDMA_ERQ bits specified in the SERQ field.
1 Set all bits in EDMA_ERQ.
Reserved, must be cleared.
Set enable request. Sets the corresponding bit in EDMA_ERQ
eDMA Clear Enable Request Register (EDMA_CERQ)
The EDMA_CERQ provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_ERQ to disable the DMA request for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_ERQ to be cleared. Setting the CAER bit provides a global clear
function, forcing the entire contents of the EDMA_ERQ to be cleared, disabling all DMA request inputs.
Reads of this register return all zeroes.
Address: 0xFC04_4019 (EDMA_CERQ)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Access: User write-only
CAER
0
0
CERQ
0
0
0
0
Figure 17-8. eDMA Clear Enable Request Register (EDMA_CERQ)
MCF52277 Reference Manual, Rev 2
17-10
Freescale Semiconductor
Enhanced Direct Memory Access (eDMA)
Table 17-9. EDMA_CERQ Field Descriptions
Field
7
Description
Reserved, must be cleared.
6
CAER
5–4
3–0
CERQ
17.4.7
Clear all enable requests.
0 Clear only those EDMA_ERQ bits specified in the CERQ field.
1 Clear all bits in EDMA_ERQ.
Reserved, must be cleared.
Clear enable request. Clears the corresponding bit in EDMA_ERQ.
eDMA Set Enable Error Interrupt Register (EDMA_SEEI)
The EDMA_SEEI provides a simple memory-mapped mechanism to set a given bit in the EDMA_EEI to
enable the error interrupt for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire
EDMA_EEI contents to be set. Reads of this register return all zeroes.
Address: 0xFC04_401A (EDMA_SEEI)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Access: User write-only
SAEE
0
SEEI
0
0
0
0
0
Figure 17-9. eDMA Set Enable Error Interrupt Register (EDMA_SEEI)
Table 17-10. EDMA_SEEI Field Descriptions
Field
7
6
SAEE
5–4
3–0
SEEI
17.4.8
Description
Reserved, must be cleared.
Sets all enable error interrupts.
0 Set only those EDMA_EEI bits specified in the SEEI field.
1 Sets all bits in EDMA_EEI.
Reserved, must be cleared.
Set enable error interrupt. Sets the corresponding bit in EDMA_EEI.
eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)
The EDMA_CEEI provides a simple memory-mapped mechanism to clear a given bit in the EDMA_EEI
to disable the error interrupt for a given channel. The data value on a register write causes the
corresponding bit in the EDMA_EEI to be cleared. Setting the CAEE bit provides a global clear function,
forcing the EDMA_EEI contents to be cleared, disabling all DMA request inputs. Reads of this register
return all zeroes.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
17-11
Enhanced Direct Memory Access (eDMA)
Address: 0xFC04_401B (EDNA_CEEI)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Access: User write-only
CAEE
0
CEEI
0
0
0
0
0
Figure 17-10. eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)
Table 17-11. EDMA_CEEI Field Descriptions
Field
7
Description
Reserved, must be cleared.
6
CAEE
5–4
3–0
CEEI
17.4.9
Clear all enable error interrupts.
0 Clear only those EDMA_EEI bits specified in the CEEI field.
1 Clear all bits in EDMA_EEI.
Reserved, must be cleared.
Clear enable error interrupt. Clears the corresponding bit in EDMA_EEI.
eDMA Clear Interrupt Request Register (EDMA_CINT)
The EDMA_CINT provides a simple, memory-mapped mechanism to clear a given bit in the EDMA_INT
to disable the interrupt request for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_INT to be cleared. Setting the CAIR bit provides a global clear function,
forcing the entire contents of the EDMA_INT to be cleared, disabling all DMA interrupt requests. Reads
of this register return all zeroes.
Address: 0xFC04_401C (EDMA_CINT)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Access: User write-only
CAIR
0
CINT
0
0
0
0
0
Figure 17-11. eDMA Clear Interrupt Request (EDMA_CINT)
Table 17-12. EDMA_CINT Field Descriptions
Field
7
6
CAIR
Description
Reserved, must be cleared.
Clear all interrupt requests.
0 Clear only those EDMA_INT bits specified in the CINT field.
1 Clear all bits in EDMA_INT.
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Freescale Semiconductor
Enhanced Direct Memory Access (eDMA)
Table 17-12. EDMA_CINT Field Descriptions (continued)
Field
5–4
3–0
CINT
Description
Reserved, must be cleared.
Clear interrupt request. Clears the corresponding bit in EDMA_INT.
17.4.10 eDMA Clear Error Register (EDMA_CERR)
The EDMA_CERR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERR
to disable the error condition flag for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_ERR to be cleared. Setting the CAEI bit provides a global clear function,
forcing the EDMA_ERR contents to be cleared, clearing all channel error indicators. Reads of this register
return all zeroes.
Address: 0xFC04_401D (EDMA_CERR)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Access: User write-only
CAEI
0
CERR
0
0
0
0
0
Figure 17-12. eDMA Clear Error Register (EDMA_CERR)
Table 17-13. EDMA_CERR Field Descriptions
Field
7
6
CAEI
5–4
3–0
CERR
Description
Reserved, must be cleared.
Clear all error indicators.
0 Clear only those EDMA_ERR bits specified in the CERR field.
1 Clear all bits in EDMA_ERR.
Reserved, must be cleared.
Clear error indicator. Clears the corresponding bit in EDMA_ERR.
17.4.11 eDMA Set START Bit Register (EDMA_SSRT)
The EDMA_SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the
given channel. The data value on a register write causes the START bit in the corresponding transfer
control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to
be set. Reads of this register return all zeroes.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
17-13
Enhanced Direct Memory Access (eDMA)
Address: 0xFC04_401E (EDMA_SSRT)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Access: User write-only
SAST
0
SSRT
0
0
0
0
0
Figure 17-13. eDMA Set START Bit Register (EDMA_SSRT)
Table 17-14. EDMA_SSRT Field Descriptions
Field
7
Description
Reserved, must be cleared.
6
SAST
5–4
3–0
SSRT
Set all START bits (activates all channels).
0 Set only those TCDn_CSR[START] bits specified in the SSRT field.
1 Set all bits in TCDn_CSR[START].
Reserved, must be cleared.
Set START bit. Sets the corresponding bit in TCDn_CSR[START].
17.4.12 eDMA Clear DONE Status Bit Register (EDMA_CDNE)
The EDMA_CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of
the given channel. The data value on a register write causes the DONE bit in the corresponding transfer
control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE
bits to be cleared. Reads of this register return all zeroes.
Address: 0xFC04_401F (EDMA_CDNE)
R
7
6
5
4
3
2
0
0
0
0
0
0
CADN
W
Reset
Access: User write-only
0
1
0
0
0
CDNE
0
0
0
0
0
Figure 17-14. eDMA Clear DONE Status Bit Register (EDMA_CDNE)
Table 17-15. EDMA_CDNE Field Descriptions
Field
7
6
CADN
5–4
3–0
CDNE
Description
Reserved, must be cleared.
Clears all DONE bits.
0 Clears only those TCDn_CSR[DONE] bits specified in the CDNE field.
1 Clears all bits in TCDn_CSR[DONE]
Reserved, must be cleared.
Clear DONE bit. Clears the corresponding bit in TCDn_CSR[DONE].
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
Enhanced Direct Memory Access (eDMA)
17.4.13 eDMA Interrupt Request Register (EDMA_INT)
The EDMA_INT provide a bit map for the 16 channels signaling the presence of an interrupt request for
each channel. Depending on the appropriate bit setting in the transfer-control descriptions, the eDMA
engine generates an interrupt a data transfer completion. The outputs of this register are directly routed to
the interrupt controller (INTC). During the interrupt-service routine associated with any given channel, it
is the software’s responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write
to the EDMA_CINT in the interrupt service routine is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the EDMA_CINT. On writes to the EDMA_INT, a 1 in any bit position clears the
corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding
channel’s current interrupt status. The EDMA_CINT is provided so the interrupt request for a single
channel can easily be cleared without the need to perform a read-modify-write sequence to the
EDMA_INT.
Address: 0xFC04_4026 (EDMA_INT)
15
8
7
6
5
4
3
2
1
0
R INT15 INT14 INT13 INT12 INT11 INT10 INT9
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
W w1c
Reset
0
14
13
12
Access: User read/write
11
10
9
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-15. eDMA Interrupt Request Register (EDMA_INT)
Table 17-16. EDMA_INT Field Descriptions
Field
15–0
INTn
Description
eDMA interrupt request n
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.
17.4.14 eDMA Error Register (EDMA_ERR)
The EDMA_ERR provide a bit map for the 16 channels, signaling the presence of an error for each
channel. The eDMA engine signals the occurrence of a error condition by setting the appropriate bit in this
register. The outputs of this register are enabled by the contents of the EDMA_EEI,and then routed to the
interrupt controller. During the execution of the interrupt-service routine associated with any DMA errors,
it is software’s responsibility to clear the appropriate bit, negating the error-interrupt request. Typically, a
write to the EDMA_CERR in the interrupt-service routine is used for this purpose. The normal DMA
channel completion indicators (setting the transfer control descriptor DONE flag and the possible assertion
of an interrupt request) are not affected when an error is detected.
The contents of this register can also be polled because a non-zero value indicates the presence of a channel
error regardless of the state of the EDMA_EEI. The state of any given channel’s error indicators is affected
by writes to this register; it is also affected by writes to the EDMA_CERR. On writes to the EDMA_ERR,
a one in any bit position clears the corresponding channel’s error status. A zero in any bit position has no
affect on the corresponding channel’s current error status. The EDMA_CERR is provided so the error
indicator for a single channel can easily be cleared.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
17-15
Enhanced Direct Memory Access (eDMA)
Address: 0xFC04_402E (EDMA_ERR)
15
Access: User read/write
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R ERR
15
ERR
14
ERR
13
ERR
12
ERR
11
ERR
10
ERR
9
ERR
8
ERR
7
ERR
6
ERR
5
ERR
4
ERR
3
ERR
2
ERR
1
ERR
0
W w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
Figure 17-16. eDMA Error Register (EDMA_ERR)
Table 17-17. EDMA_ERR Field Descriptions
Field
Description
15–0
ERRn
eDMA Error n.
0 An error in channel n has not occurred.
1 An error in channel n has occurred.
17.4.15 eDMA Channel n Priority Registers (DCHPRIn)
When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the contents of
these registers define the unique priorities associated with each channel. The channel priorities are
evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next higher priority, then 2, 3,
etc. Software must program the channel priorities with unique values. Otherwise, a configuration error is
reported. The range of the priority value is limited to the values of 0 through 15.
Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit. Channel
preemption allows the executing channel’s data transfers to temporarily suspend in favor of starting a
higher priority channel. After the preempting channel has completed all its minor loop data transfers, the
preempted channel is restored and resumes execution. After the restored channel completes one read/write
sequence, it is again eligible for preemption. If any higher priority channel is requesting service, the
restored channel is suspended and the higher priority channel is serviced. Nested preemption (attempting
to preempt a preempting channel) is not supported. After a preempting channel begins execution, it cannot
be preempted. Preemption is available only when fixed arbitration is selected.
Address: 0xFC04_4100 + n, where n = 0 – 15 (DCHPRIn)
7
R
Access: User read/write
6
5
4
0
0
0
3
2
ECP
1
0
–1
–1
CHPRI
W
Reset
0
1
0
0
0
–1
–1
Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number for each priority
register, i.e., DCHPRI15[CHPRI] equals 0b1111.
Figure 17-17. eDMA Channel n Priority Register (DCHPRIn)
MCF52277 Reference Manual, Rev 2
17-16
Freescale Semiconductor
Enhanced Direct Memory Access (eDMA)
Table 17-18. DCHPRIn Field Descriptions
Field
Description
7
ECP
Enable channel preemption.
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
6–4
Reserved, must be cleared.
3–0
CHPRI
Channel n arbitration priority. Channel priority when fixed-priority arbitration is enabled.
17.4.16 Transfer Control Descriptors (TCDn)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel
1,... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. Table 17-19 is a register
list of the basic TCD structure.
Table 17-19. TCDn Memory Structure
eDMA Offset
TCDn Register Name
Abbreviation
Width
(bits)
0xFC04_5000 + (0x20 × n)
Source Address
TCDn_SADDR
32
0xFC04_5004 + (0x20 × n)
Transfer Attributes
TCDn_ATTR
16
0xFC04_5006 + (0x20 × n)
Signed Source Address Offset
TCDn_SOFF
16
0xFC04_5008 + (0x20 × n)
Minor Byte Count
TCDn_NBYTES
32
0xFC04_500C + (0x20 × n)
Last Source Address Adjustment
TCDn_SLAST
32
0xFC04_5010 + (0x20 × n)
Destination Address
TCDn_DADDR
32
0xFC04_5014 + (0x20 × n)
Current Minor Loop Link, Major Loop Count
TCDn_CITER
16
0xFC04_5016 + (0x20 × n)
Signed Destination Address Offset
TCDn_DOFF
16
0xFC04_5018 + (0x20 × n)
Last Destination Address Adjustment/Scatter Gather Address TCDn_DLAST_SGA
32
0xFC04_501C + (0x20 × n)
Beginning Minor Loop Link, Major Loop Count
TCDn_BITER
16
0xFC04_501E + (0x20 × n)
Control and Status
TCDn_CSR
16
The following figures and tables define the fields of the TCDn structure:
Address: 0xFC04_5000 + (0x20 × n) (TCDn_SADDR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
8
7
6
5
4
3
2
1
0
SADDR
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 17-18. TCDn Source Address (TCDn_SADDR)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
17-17
Enhanced Direct Memory Access (eDMA)
Table 17-20. TCDn_SADDR Field Descriptions
Field
31–0
SADDR
Description
Source address. Memory address pointing to the source data.
Address: 0xFC04_5004 + (0x20 × n) (TCDn_ATTR)
15
14
R
12
11
10
SMOD
W
Reset
13
—
—
—
Access: User read/write
9
8
7
6
SSIZE
—
—
—
—
5
4
3
2
DMOD
—
—
—
—
1
0
DSIZE
—
—
—
—
—
Figure 17-19. TCDn Transfer Attributes (TCDn_ATTR)
Table 17-21. TCDn_ATTR Field Descriptions
Field
Description
15–11
SMOD
Source address modulo.
0 Source address modulo feature is disabled.
non-0 This value defines a specific address range specified to be the value after SADDR + SOFF
calculation is performed or the original register value. The setting of this field provides the ability to
implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue
should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for
the queue, freezing the desired number of upper address bits. The value programmed into this field
specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF
is typically set to the transfer size to implement post-increment addressing with the SMOD function
constraining the addresses to a 0-modulo-size range.
10–8
SSIZE
Source data transfer size.
000 8-bit
001 16-bit
010 32-bit
100 16-byte
Else Reserved
The attempted use of a Reserved encoding causes a configuration error.
7–3
DMOD
Destination address modulo. See the SMOD definition.
2–0
DSIZE
Destination data transfer size. See the SSIZE definition.
Address: 0xFC04_5006 + (0x20 × n) (TCDn_SOFF)
15
14
13
12
11
10
Access: User read/write
9
R
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
SOFF
W
Reset
8
—
—
—
—
—
—
—
—
—
Figure 17-20. TCDn Signed Source Address Offset (TCDn_SOFF)
MCF52277 Reference Manual, Rev 2
17-18
Freescale Semiconductor
Enhanced Direct Memory Access (eDMA)
Table 17-22. TCDn_SOFF Field Descriptions
Field
Description
15–0
SOFF
Source address signed offset. Sign-extended offset applied to the current source address to form the
next-state value as each source read is completed.
Address: 0xFC04_5008 + (0x20 × n) (TCDn_NBYTES)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
NBYTES
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 17-21. TCDn Minor Byte Count (TCDn_NBYTES)
Table 17-23. TCDn_NBYTES Field Descriptions
Field
Description
31–0
NBYTES
Minor byte transfer count. Number of bytes to be transferred in each service request of the channel. As a
channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and
writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot
be halted. (Although, it may be stalled by using the bandwidth control field, or via preemption.) After the
minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major
iteration count is decremented and restored to the TCD memory. If the major iteration count is completed,
additional processing is performed.
Note: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer.
Address: 0xFC04_500C + (0x20 × n) (TCDn_SLAST)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
SLAST
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 17-22. TCDn Source Last Address Adjustment (TCDn_SLAST)
Table 17-24. TCDn_SLAST Field Descriptions
Field
Description
31–0
SLAST
Last source address adjustment. Adjustment value added to the source address at the completion of the
major iteration count. This value can be applied to restore the source address to the initial value, or adjust
the address to reference the next data structure.
Address: 0xFC04_5010 + (0x20 × n) (TCDn_DADDR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
8
7
6
5
4
3
2
1
0
DADDR
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 17-23. TCDn Destination Address (TCDn_DADDR)
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Table 17-25. TCDn_DADDR Field Descriptions
Field
Description
31–0
DADDR
Destination address. Memory address pointing to the destination data.
Address: 0xFC04_5014 + (0x20 × n) (TCDn_CITER)
15
E_LINK = 1
E_LINK = 0
R
W
R
W
Reset
E_LINK
14
13
0
0
12
11
10
Access: User read/write
9
8
6
5
LINKCH
4
3
2
1
0
—
—
—
—
CITER
E_LINK
—
7
CITER
—
—
—
—
—
—
—
—
—
—
—
Figure 17-24. TCDn Current Major Iteration Count (TCDn_CITER)
Table 17-26. TCDn_CITER Field Descriptions
Field
Description
15
E_LINK
Enable channel-to-channel linking on minor-loop complete. As the channel completes the minor loop, this
flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a
channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified
channel.
If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If
the major loop is exhausted, this link mechanism is suppressed in favor of the MAJOR_E_LINK channel
linking.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
Note: This bit must be equal to the BITER.E_LINK bit. Otherwise, a configuration error is reported.
14–13
Reserved, must be cleared.
12–9
LINKCH
Link channel number. If channel-to-channel linking is enabled (E_LINK = 1), then after the minor loop is
exhausted, the eDMA engine initiates a channel service request to the channel defined by these four bits
by setting that channel’s TCDn_CSR[START] bit.
0–15 Link to DMA channel 0–15
14–0 or
8–0
CITER
Current major iteration count. This 9-bit (E_LINK = 1) or 15-bit (E_LINK = 0) count represents the current
major loop count for the channel. It is decremented each time the minor loop is completed and updated in
the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs
a number of operations (e.g., final source and destination address calculations), optionally generating an
interrupt to signal channel completion before reloading the CITER field from the beginning iteration count
(BITER) field.
Note: When the CITER field is initially loaded by software, it must be set to the same value as that
contained in the BITER field.
Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER
should be 0x0001.
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Address: 0xFC04_5016 + (0x20 × n) (TCDn_DOFF)
15
14
13
12
11
10
Access: User read/write
9
8
R
6
5
4
3
2
1
0
—
—
—
—
—
—
—
DOFF
W
Reset
7
—
—
—
—
—
—
—
—
—
Figure 17-25. TCDn Destination Address Signed Offset (TCDn_DOFF)
Table 17-27. TCDn_DOFF Field Descriptions
Field
Description
15–0
DOFF
Destination address signed offset. Sign-extended offset applied to the current destination address to form
the next-state value as each destination write is completed.
Address: 0xFC04_5018 + (0x20 × n) (TCDn_DLAST_SGA)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
1
0
DLAST_SGA
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 17-26. TCDn Destination Last Address Adjustment (TCDn_DLAST_SGA)
Table 17-28. TCDn_DLAST_SGA Field Descriptions
Field
Description
31–0
DLAST_SGA
Destination last address adjustment or the memory address for the next transfer control descriptor to be
loaded into this channel (scatter/gather).
If (TCDn_CSR[E_SG] = 0) then
• Adjustment value added to the destination address at the completion of the major iteration count. This
value can apply to restore the destination address to the initial value or adjust the address to reference
the next data structure.
else
• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control
descriptor to be loaded into this channel. This channel reload is performed as the major iteration count
completes. The scatter/gather address must be 0-modulo-32-byte, else a configuration error is
reported.
Address: 0xFC04_501C + (0x20 × n) (TCDn_BITER)
15
E_LINK = 1
E_LINK = 0
R
W
R
W
Reset
E_LINK
14
13
0
0
12
11
10
9
Access: User read/write
8
6
5
LINKCH
4
3
2
1
0
—
—
—
—
BITER
E_LINK
—
7
BITER
—
—
—
—
—
—
—
—
—
—
—
Figure 17-27. TCDn Beginning Major Iteration Count (TCDn_BITER)
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Table 17-29. TCDn_BITER Field Descriptions
Field
Description
15
E_LINK
Enables channel-to-channel linking on minor loop complete. As the channel completes the minor loop, this
flag enables the linking to another channel, defined by BITER.LINKCH. The link target channel initiates a
channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified
channel. If channel linking disables, the BITER value extends to 15 bits in place of a link channel number.
If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJOR_E_LINK channel
linking.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
Note: When the software loads the TCD, this field must be set equal to the corresponding CITER field.
Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents
of this field is reloaded into the CITER field.
14–13
Reserved, must be cleared.
12–9
LINKCH
Link channel number. If channel-to-channel linking is enabled (E_LINK = 1), then after the minor loop is
exhausted, the eDMA engine initiates a channel service request at the channel defined by these four bits
by setting that channel’s TCDn_CSR[START] bit.
0–15 Link to DMA channel 0–15
Note: When the software loads the TCD, this field must be set equal to the corresponding CITER field.
Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents
of this field is reloaded into the CITER field.
14–0 or
8–0
BITER
Starting major iteration count. As the transfer control descriptor is first loaded by software, this 9-bit
(E_LINK = 1) or 15-bit (E_LINK = 0) field must be equal to the value in the CITER field. As the major
iteration count is exhausted, the contents of this field are reloaded into the CITER field.
Note: When the software loads the TCD, this field must be set equal to the corresponding CITER field.
Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents
of this field is reloaded into the CITER field. If the channel is configured to execute a single service
request, the initial values of BITER and CITER should be 0x0001.
Address: 0xFC04_501E + (0x20 × n) (TCDn_CSR)
15
R
W
Reset
14
BWC
—
—
13
12
0
0
11
—
—
10
Access: User read/write
9
8
MAJOR_LINKCH
—
—
—
—
7
6
DONE ACTIVE
0
5
4
3
2
1
0
MAJOR_
INT_ INT_
E_SG D_REQ
START
E_LINK
HALF MAJOR
0
—
—
—
—
—
0
Figure 17-28. TCDn Control and Status (TCDn_CSR)
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Table 17-30. TCDn_CSR Field Descriptions
Field
Description
15–14
BWC
Bandwidth control. Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the
eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is
exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the
bus request bandwidth seen by the crossbar switch (XBS).
00 No eDMA engine stalls
01 Reserved
10 eDMA engine stalls for 4 cycles after each r/w
11 eDMA engine stalls for 8 cycles after each r/w
Note: If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing start-up
latency.
13–12
Reserved, must be cleared.
11–8
Link channel number.
MAJOR_LINKCH If (MAJOR_E_LINK = 0) then
• No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted.
else
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the
channel defined by these four bits by setting that channel’s TCDn_CSR[START] bit.
0–15 Link to DMA channel 0–15
7
DONE
Channel done. This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the
CITER count reaches zero; The software clears it, or the hardware when the channel is activated.
Note: This bit must be cleared to write the MAJOR_E_LINK or E_SG bits.
6
ACTIVE
Channel active. This flag signals the channel is currently in execution. It is set when channel service begins,
and the eDMA clears it as the minor loop completes or if any error condition is detected.
5
Enable channel-to-channel linking on major loop complete. As the channel completes the major loop, this
MAJOR_E_LINK flag enables the linking to another channel, defined by MAJOR_LINKCH. The link target channel initiates
a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified
channel.
Note: To support the dynamic linking coherency model, this field is forced to zero when written to while the
TCDn_CSR[DONE] bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
4
E_SG
Enable scatter/gather processing. As the channel completes the major loop, this flag enables scatter/gather
processing in the current channel. If enabled, the eDMA engine uses DLAST_SGA as a memory pointer to
a 0-modulo-32 address containing a 32-byte data structure loaded as the transfer control descriptor into the
local memory.
Note: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to
while the TCDn_CSR[DONE] bit is set.
0 The current channel’s TCD is normal format.
1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA field provides a memory
pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
3
D_REQ
Disable request. If this flag is set, the eDMA hardware automatically clears the corresponding EDMA_ERQ
bit when the current major iteration count reaches zero.
0 The channel’s EDMA_ERQ bit is not affected.
1 The channel’s EDMA_ERQ bit is cleared when the major loop is complete.
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Table 17-30. TCDn_CSR Field Descriptions (continued)
Field
Description
2
INT_HALF
Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an
interrupt request by setting the appropriate bit in the EDMA_INT when the current major iteration count
reaches the halfway point. Specifically, the comparison performed by the eDMA engine is (CITER ==
(BITER >> 1)). This halfway point interrupt request is provided to support double-buffered (aka ping-pong)
schemes or other types of data movement where the processor needs an early indication of the transfer’s
progress. The halfway complete interrupt disables when BITER values are less than two.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
1
INT_MAJOR
0
START
17.5
Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an
interrupt request by setting the appropriate bit in the EDMA_INT when the current major iteration count
reaches zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
Channel start. If this flag is set, the channel is requesting service. The eDMA hardware automatically clears
this flag after the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
Functional Description
This section provides an overview of the microarchitecture and functional operation of the eDMA module.
17.5.1
eDMA Microarchitecture
The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control
descriptor local memory. Additionally, the eDMA engine is further partitioned into four submodules:
• eDMA Engine
— Address Path:
This block implements registered versions of two channel transfer control descriptors,
channel x and channel y, and manages all master bus-address calculations. All the channels
provide the same functionality. This structure allows data transfers associated with one
channel to be preempted after the completion of a read/write sequence if a higher priority
channel activation is asserted while the first channel is active. After a channel is activated,
it runs until the minor loop is completed, unless preempted by a higher priority channel. This
provides a mechanism (enabled by DCHPRIn[ECP]) where a large data move operation can
be preempted to minimize the time another channel is blocked from execution.
When any channel is selected to execute, the contents of its TCD are read from local
memory and loaded into the address path channel x registers for a normal start and into
channel y registers for a preemption start. After the minor loop completes execution, the
address path hardware writes the new values for the TCDn_{SADDR, DADDR, CITER}
back to local memory. If the major iteration count is exhausted, additional processing are
performed, including the final address pointer updates, reloading the TCDn_CITER field,
and a possible fetch of the next TCDn from memory as part of a scatter/gather operation.
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•
— Data Path:
This block implements the bus master read/write datapath. It includes 16 bytes of register
storage and the necessary multiplex logic to support any required data alignment. The
internal read data bus is the primary input, and the internal write data bus is the primary
output.
The address and data path modules directly support the 2-stage pipelined internal bus. The
address path module represents the 1st stage of the bus pipeline (address phase), while the
data path module implements the 2nd stage of the pipeline (data phase).
— Program Model/Channel Arbitration:
This block implements the first section of the eDMA programming model as well as the
channel arbitration logic. The programming model registers are connected to the internal
peripheral bus (not shown). The eDMA peripheral request inputs and interrupt request
outputs are also connected to this block (via control logic).
— Control:
This block provides all the control functions for the eDMA engine. For data transfers where
the source and destination sizes are equal, the eDMA engine performs a series of source
read/destination write operations until the number of bytes specified in the minor loop byte
count has moved. For descriptors where the sizes are not equal, multiple accesses of the
smaller size data are required for each reference of the larger size. As an example, if the
source size references 16-bit data and the destination is 32-bit data, two reads are performed,
then one 32-bit write.
Transfer Control Descriptor Memory
— Memory Controller:
This logic implements the required dual-ported controller, managing accesses from the
eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the
event of simultaneous accesses, the eDMA engine is given priority and the peripheral
transaction is stalled.
— Memory Array: TCD storage is implemented using a single-port, synchronous RAM array.
17.5.2
eDMA Basic Data Flow
The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 17-29, the first
segment involves the channel activation. In the diagram, this example uses the assertion of the eDMA
peripheral request signal to request service for channel n. Channel activation via software and the
TCDn_CSR[START] bit follows the same basic flow as peripheral requests. The eDMA request input
signal is registered internally and then routed through the eDMA engine: first through the control module,
then into the program model and channel arbitration. In the next cycle, the channel arbitration performs,
using the fixed-priority or round-robin algorithm. After arbitration is complete, the activated channel
number is sent through the address path and converted into the required address to access the local memory
for TCDn. Next, the TCD memory is accessed and the required descriptor read from the local memory and
loaded into the eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to
minimize the time needed to fetch the activated channel descriptor and load it into the address path channel
x or y registers.
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eDMA
Write Address
Write Data
0
Transfer
Control
Descriptor (TCD)
n-1
64
Internal Peripheral Bus
To/From Crossbar Switch
1
2
eDMA Engine
Program Model/
Channel Arbitration
Read Data
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA Peripheral
Request
eDMA Done
Figure 17-29. eDMA Operation, Part 1
In the second part of the basic data flow (Figure 17-30), the modules associated with the data transfer
(address path, data path, and control) sequence through the required source reads and destination writes to
perform the actual data movement. The source reads are initiated and the fetched data is temporarily stored
in the data path block until it is gated onto the internal bus during the destination write. This source
read/destination write processing continues until the minor byte count has transferred.
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eDMA
Write Address
Write Data
0
Transfer
Control
Descriptor (TCD)
n-1
64
Internal Peripheral Bus
To/From Crossbar Switch
1
2
eDMA Engine
Program Model/
Channel Arbitration
Read Data
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA Peripheral
Request
eDMA Done
Figure 17-30. eDMA Operation, Part 2
After the minor byte count has moved, the final phase of the basic data flow performs. In this segment, the
address path logic performs the required updates to certain fields in the appropriate TCD, e.g., SADDR,
DADDR, CITER. If the major iteration count is exhausted, additional operations are performed. These
include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an
optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory
using the scatter/gather address pointer included in the descriptor. The updates to the TCD memory and
the assertion of an interrupt request are shown in Figure 17-31.
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eDMA
Write Address
Write Data
0
Transfer
Control
Descriptor (TCD)
n-1
64
Internal Peripheral Bus
To/From Crossbar Switch
1
2
eDMA Engine
Program Model/
Channel Arbitration
Read Data
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA Peripheral
Request
eDMA Done
Figure 17-31. eDMA Operation, Part 3
17.6
17.6.1
Initialization/Application Information
eDMA Initialization
A typical initialization of the eDMA has the following sequence:
1. Write the EDMA_CR if a configuration other than the default is desired.
2. Write the channel priority levels into the DCHPRIn registers if a configuration other than the
default is desired.
3. Enable error interrupts in the EDMA_EEI if so desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the EDMA_ERQ.
6. Request channel service by software (setting the TCDn_CSR[START] bit) or hardware (slave
device asserting its eDMA peripheral request signal).
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After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The eDMA engine read the entire TCD, including the TCD
control and status fields (Table 17-31) for the selected channel into its internal address path module. As
the TCD is read, the first transfer is initiated on the internal bus unless a configuration error is detected.
Transfers from the source (as defined by the source address, TCDn_SADDR) to the destination (as defined
by the destination address, TCDn_DADDR) continue until the specified number of bytes
(TCDn_NBYTES) are transferred. When transfer is complete, the eDMA engine's local TCDn_SADDR,
TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any minor loop
channel linking is performed, if enabled. If the major loop is exhausted, further post processing executes
(interrupts, major loop channel linking, and scatter/gather operations) if enabled.
Table 17-31. TCD Control and Status Fields
TCDn_CSR
Field Name
Description
START
Control bit to start channel explicitly when using a software
initiated DMA service (Automatically cleared by hardware)
ACTIVE
Status bit indicating the channel is currently in execution
DONE
Status bit indicating major loop completion (cleared by software
when using a software initiated DMA service)
D_REQ
Control bit to disable DMA request at end of major loop
completion when using a hardware initiated DMA service
BWC
Control bits for throttling bandwidth control of a channel
E_SG
Control bit to enable scatter-gather feature
INT_HALF
Control bit to enable interrupt when major loop is half complete
INT_MAJ
Control bit to enable interrupt when major loop completes
Table 17-32 shows how each DMA request initiates one minor-loop transfer (iteration) without CPU
intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA
preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration
count (BITER).
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Table 17-32. Example of Multiple Loop Iterations
Current Major
Loop Iteration
Count (CITER)
DMA Request
.
.
.
Minor Loop
.
.
.
Minor Loop
.
.
.
Minor Loop
3
DMA Request
Major Loop
2
DMA Request
1
Table 17-33 lists the memory array terms and how the TCD settings interrelate.
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Table 17-33. Memory Array Terms
xADDR: (Starting Address)
xSIZE
(size of one
data transfer)
.
.
.
.
.
.
.
.
.
.
.
Minor Loop
(NBYTES in
Minor Loop,
often the same
value as xSIZE)
.
.
.
.
.
.
.
.
Minor Loop
.
.
.
Last Minor Loop
Offset (xOFF): number of bytes added to
current address after each transfer
(often the same value as xSIZE)
Each DMA source (S) and
destination (D) has its own:
Address (xADDR)
Size (xSIZE)
Offset (xOFF)
Modulo (xMOD)
Last Address Adjustment (xLAST)
where x = S or D
Peripheral queues typically
have size and offset equal
to NBYTES.
xLAST: Number of bytes added to
current address after major loop
(typically used to loop back)
17.6.2
DMA Programming Errors
The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor
data. Most programming errors are reported on a per channel basis with the exception of channel priority
error (EDMA_ES[CPE]).
For all error types other than channel priority error, the channel number causing the error is recorded in
the EDMA_ES. If the error source is not removed before the next activation of the problem channel, the
error is detected and recorded again.
If priority levels are not unique, when any channel requests service, a channel priority error is reported.
The highest channel priority with an active request is selected, but the lowest numbered channel with that
priority is selected by arbitration and executed by the eDMA engine. The hardware service request
handshake signals, error interrupts, and error reporting is associated with the selected channel.
17.6.3
17.6.3.1
DMA Arbitration Mode Considerations
Fixed Channel Arbitration
In this mode, the channel service request from the highest priority channel is selected to execute.
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17.6.3.2
Round Robin Channel Arbitration
Channels are serviced starting with the highest channel number and rotating through to the lowest channel
number without regard to the channel priority levels
17.6.4
17.6.4.1
DMA Transfer
Single Request
To perform a simple transfer of n bytes of data with one activation, set the major loop to one
(TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is
acknowledged and the channel is selected to execute. After the transfer is complete, the
TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is
programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has
a byte wide memory port located at 0x1000. The destination memory has a longword-wide port located at
0x2000. The address offsets are programmed in increments to match the transfer size: one byte for the
source and four bytes for the destination. The final source and destination addresses are adjusted to return
to their beginning values.
Example 17-1. Single Request DMA Transfer
TCDn_CITER = TCDn_BITER = 1
TCDn_NBYTES = 16
TCDn_SADDR = 0x1000
TCDn_SOFF = 1
TCDn_ATTR[SSIZE] = 0
TCDn_SLAST = -16
TCDn_DADDR = 0x2000
TCDn_DOFF = 4
TCDn_ATTR[DSIZE] = 2
TCDn_DLAST_SGA= –16
TCDn_CSR[INT_MAJ] = 1
TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized)
All other TCDn fields = 0
This generates the following event sequence:
1. User write to the TCDn_CSR[START] bit requests channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
4. eDMA engine reads: channel TCD data from local memory to internal register file.
5. The source-to-destination transfers are executed as follows:
a) Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read
byte from 0x1003.
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b) Write longword to location 0x2000 → first iteration of the minor loop.
c) Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read
byte from 0x1007.
d) Write longword to location 0x2004 → second iteration of the minor loop.
e) Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read
byte from 0x100B.
f) Write longword to location 0x2008 → third iteration of the minor loop.
g) Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E,
read byte from 0x100F.
h) Write longword to location 0x200C → last iteration of the minor loop → major loop complete.
6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER
= 1 (TCDn_BITER).
7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, EDMA_INT[n]
= 1.
8. The channel retires and the eDMA goes idle or services the next channel.
17.6.4.2
Multiple Requests
Besides transferring 32 bytes via two hardware requests, the next example is the same as previous. The
only fields that change are the major loop iteration count and the final address offsets. The eDMA is
programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel’s
hardware requests are enabled in EDMA_ERQ, the slave device initiates channel service requests.
TCDn_CITER = TCDn_BITER = 2
TCDn_SLAST = –32
TCDn_DLAST_SGA = –32
This would generate the following sequence of events:
1. First hardware (eDMA peripheral) request for channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE]
= 1.
4. eDMA engine reads: channel TCDn data from local memory to internal register file.
5. The source to destination transfers are executed as follows:
a) Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read
byte from 0x1003.
b) Write longword to location 0x2000 → first iteration of the minor loop.
c) Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read
byte from 0x1007.
d) Write longword to location 0x2004 → second iteration of the minor loop.
e) Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read
byte from 0x100B.
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Enhanced Direct Memory Access (eDMA)
f) Write longword to location 0x2008 → third iteration of the minor loop.
g) Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E,
read byte from 0x100F.
h) Write longword to location 0x200C → last iteration of the minor loop.
6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1.
7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0.
8. The channel retires → one iteration of the major loop. The eDMA goes idle or services the next
channel.
9. Second hardware (eDMA peripheral) requests channel service.
10. The channel is selected by arbitration for servicing.
11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE]
= 1.
12. eDMA engine reads: channel TCD data from local memory to internal register file.
13. The source to destination transfers are executed as follows:
a) Read byte from location 0x1010, read byte from location 0x1011, read byte from 0x1012, read
byte from 0x1013.
b) Write longword to location 0x2010 → first iteration of the minor loop.
c) Read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read
byte from 0x1017.
d) Write longword to location 0x2014 → second iteration of the minor loop.
e) Read byte from location 0x1018, read byte from location 0x1019, read byte from 0x101A, read
byte from 0x101B.
f) Write longword to location 0x2018 → third iteration of the minor loop.
g) Read byte from location 0x101C, read byte from location 0x101D, read byte from 0x101E,
read byte from 0x101F.
h) Write longword to location 0x201C → last iteration of the minor loop → major loop complete.
14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2
(TCDn_BITER).
15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, EDMA_INT[n] = 1.
16. The channel retires → major loop complete. The eDMA goes idle or services the next channel.
17.6.4.3
Modulo Feature
The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size
of the queue is a power of 2. MOD is a 5-bit field for the source and destination in the TCD, and it specifies
which lower address bits increment from their original value after the address+offset calculation. All upper
address bits remain the same as in the original value. A setting of 0 for this field disables the modulo
feature.
Table 17-34 shows how the transfer addresses are specified based on the setting of the MOD field. Here a
circular buffer is created where the address wraps to the original value while the 28 upper address bits
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Enhanced Direct Memory Access (eDMA)
(0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the
offset is set to 4 bytes and the MOD field is set to 4, allowing for a 24 byte (16-byte) size queue.
Table 17-34. Modulo Feature Example
17.6.5
Transfer
Number
Address
1
0x12345670
2
0x12345674
3
0x12345678
4
0x1234567C
5
0x12345670
6
0x12345674
eDMA TCDn Status Monitoring
17.6.5.1
Minor Loop Complete
There are two methods to test for minor loop completion when using software initiated service requests.
The first is to read the TCDn_CITER field and test for a change. (Another method may be extracted from
the sequence shown below). The second method is to test the TCDn_CSR[START] bit and the
TCDn_CSR[ACTIVE] bit. The minor-loop-complete condition is indicated by both bits reading zero after
the TCDn_CSR[START] was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the
active status may be missed if the channel execution is short in duration.
The TCD status bits execute the following sequence for a software activated channel:
TCDn_CSR bits
State
START
ACTIVE
DONE
1
1
0
0
Channel service request via software
2
0
1
0
Channel is executing
3a
0
0
0
Channel has completed the minor loop and is idle
3b
0
0
1
Channel has completed the major loop and is idle
The best method to test for minor-loop completion when using hardware (peripheral) initiated service
requests is to read the TCDn_CITER field and test for a change. The hardware request and acknowledge
handshakes signals are not visible in the programmer’s model.
The TCD status bits execute the following sequence for a hardware-activated channel:
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Enhanced Direct Memory Access (eDMA)
TCDn_CSR bits
State
START
ACTIVE
DONE
1
0
0
0
Channel service request via hardware (peripheral
request asserted)
2
0
1
0
Channel is executing
3a
0
0
0
Channel has completed the minor loop and is idle
3b
0
0
1
Channel has completed the major loop and is idle
For both activation types, the major-loop-complete status is explicitly indicated via the
TCDn_CSR[DONE] bit.
The TCDn_CSR[START] bit is cleared automatically when the channel begins execution regardless of
how the channel activates.
17.6.5.2
Active Channel TCDn Reads
The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES values if read
while a channel executes. The true values of the SADDR, DADDR, and NBYTES are the values the
eDMA engine currently uses in its internal register file and not the values in the TCD local memory for
that channel. The addresses (SADDR and DADDR) and NBYTES (decrements to zero as the transfer
progresses) can give an indication of the progress of the transfer. All other values are read back from the
TCD local memory.
17.6.5.3
Preemption Status
Preemption is available only when fixed arbitration is selected as the channel arbitration mode. A
preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes
active. When the eDMA engine is not operating in fixed channel arbitration mode, the determination of
the actively running relative priority outstanding requests become undefined. Channel priorities are treated
as equal (constantly rotating) when round-robin arbitration mode is selected.
The TCDn_CSR[ACTIVE] bit for the preempted channel remains asserted throughout the preemption.
The preempted channel is temporarily suspended while the preempting channel executes one major loop
iteration. If two TCDn_CSR[ACTIVE] bits are set simultaneously in the global TCD map, a higher
priority channel is actively preempting a lower priority channel.
17.6.6
Channel Linking
Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of
another channel (or itself), therefore initiating a service request for that channel. When properly enabled,
the EDMA engine automatically performs this operation at the major or minor loop completion.
The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major
loop). The TCDn_CITER[E_LINK] field determines whether a minor loop link is requested. When
enabled, the channel link is made after each iteration of the major loop except for the last. When the major
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Enhanced Direct Memory Access (eDMA)
loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be
made. For example, the initial fields of:
TCDn_CITER[E_LINK] = 1
TCDn_CITER[LINKCH] = 0xC
TCDn_CITER[CITER] value = 0x4
TCDn_CSR[MAJOR_E_LINK] = 1
TCDn_CSR[MAJOR_LINKCH] = 0x7
executes as:
1. Minor loop done → set TCD12_CSR[START] bit
2. Minor loop done → set TCD12_CSR[START] bit
3. Minor loop done → set TCD12_CSR[START] bit
4. Minor loop done, major loop done → set TCD7_CSR[START] bit
When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the TCDn_CITER[CITER] field uses
a nine bit vector to form the current iteration count. When minor loop linking is disabled
(TCDn_CITER[E_LINK] = 0), the TCDn_CITER[CITER] field uses a 15-bit vector to form the current
iteration count. The bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the
CITER value to increase the range of the CITER.
NOTE
The TCDn_CITER[E_LINK] bit and the TCDn_BITER[E_LINK] bit must
equal or a configuration error is reported. The CITER and BITER vector
widths must be equal to calculate the major loop, half-way done interrupt
point.
Table 17-35 summarizes how a DMA channel can link to another DMA channel, i.e, use another channel’s
TCD, at the end of a loop.
Table 17-35. Channel Linking Parameters
Desired Link
Behavior
Link at end of
Minor Loop
Link at end of
Major Loop
17.6.7
TCD Control Field Name
Description
CITER[E_LINK]
Enable channel-to-channel linking on minor loop completion (current iteration)
CITER[LINKCH]
Link channel number when linking at end of minor loop (current iteration)
CSR[MAJOR_E_LINK]
Enable channel-to-channel linking on major loop completion
CSR[MAJOR_LINKCH]
Link channel number when linking at end of major loop
Dynamic Programming
This section provides recommended methods to change the programming model during channel execution.
17.6.7.1
Dynamic Channel Linking and Dynamic Scatter/Gather
Dynamic channel linking and dynamic scatter/gather is the process of changing the
TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits during channel execution. These bits are read
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Enhanced Direct Memory Access (eDMA)
from the TCD local memory at the end of channel execution, therefore allowing software to enable either
feature during channel execution.
Because software can change the configuration during execution, a coherency sequence must be followed.
Consider the scenario the user attempts to execute a dynamic channel link by enabling the
TCDn_CSR[MAJOR_E_LINK] bit as the eDMA engine retires the channel. The
TCDn_CSR[MAJOR_E_LINK] would be set in the programmer’s model, but it would be indeterminate
whether the actual link was made before the channel retired.
The following coherency sequence is recommended when executing a dynamic channel link or dynamic
scatter/gather request:
1. Set the TCDn_CSR[MAJOR_E_LINK] bit.
2. Read back the TCDn_CSR[MAJOR_E_LINK] bit.
3. Test the TCDn_CSR[MAJOR_E_LINK] request status.
a) If the bit is set, the dynamic link attempt was successful.
b) If the bit is cleared, the attempted dynamic link did not succeed, the channel was already
retiring.
This same coherency model is true for dynamic scatter/gather operations. For both dynamic requests, the
TCD local memory controller forces the TCDn_CSR[MAJOR_E_LINK] and TCDn_CSR[E_SG] bits to
zero on any writes to a TCDn after the TCDn_CSR[DONE] bit for that channel is set, indicating the major
loop is complete.
NOTE
Software must clear the TCDn_CSR[DONE] bit before writing the
TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits. The
TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after
a channel begins execution.
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Chapter 18
FlexBus
18.1
Introduction
This chapter describes external bus data transfer operations and error conditions. It describes transfers
initiated by the ColdFire processor (or any other bus master) and includes detailed timing diagrams
showing the interaction of signals in supported bus operations.
NOTE
In this chapter, unless otherwise noted, clock refers to the FB_CLK used for
the external bus (fsys/2).
•
18.1.1
The external data bus is shared between the FlexBus module and the
SDRAM controller. When the SDRAM controller is in SDR mode, the
data bus is switched dynamically between the SDRAM controller and
the FlexBus module. However, when the SDRAM controller is in DDR
mode, D[31:16] is dedicated to the SDRAM data bus and D[15:0] is
dedicated to the FlexBus data bus. In this case, external pins D[15:0], are
mapped internally to the upper two bytes of the FlexBus data bus,
FB_D[31:16]. This chapter only uses FB_D[31:0] or FB_D[31:X] to
designate the data bus, but the actual pins used depend on the setting.
Take this into consideration throughout this chapter.
Overview
A multi-function external bus interface called the FlexBus interface controller is provided on the device
with basic functionality of interfacing to slave-only devices with a maximum bus frequency up to
83.33 MHz. It can be directly connected to the following asynchronous or synchronous devices with little
or no additional circuitry:
• External boot ROMs
• Flash memories
• Programmable logic devices
• Other simple target (slave) devices
For asynchronous devices, a simple chip-select based interface can be used.
The FlexBus interface has up to six general purpose chip-selects, FB_CS[5:0]. The actual number of chip
selects available depends upon the device and its pin configuration. See Table 2-2 for more details.
Chip-select FB_CS0 can be dedicated to boot memory access and programmed to be byte (8 bits), word
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FlexBus
(16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM and flash
memories.
18.1.2
Features
Key FlexBus features include:
• Six independent, user-programmable chip-select signals (FB_CS[5:0]) that can interface with
external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals
• 8-, 16-, and 32-bit port sizes
• Byte-, word-, longword-, and 16-byte line-sized transfers
• Programmable burst- and burst-inhibited transfers selectable for each chip select and transfer
direction
• Programmable address-setup time with respect to the assertion of chip select
• Programmable address-hold time with respect to the negation of chip select and transfer direction
18.2
External Signals
This section describes the external signals involved in data-transfer operations.
Table 18-1. FlexBus Signal Summary
1
18.2.1
Signal Name
I/O1
Description
FB_A[23:0]
O
Address bus. During the first cycle, this bus drives the upper address byte,
addr[31:24].
FB_D[31:0]
I/O
Data bus
FB_CS[5:0]
O
General purpose chip-selects. The actual number of chip selects available
depends upon the device and its pin configuration. See Table 2-2 for more
details.
FB_BE/BWE[3:0]
O
Byte enable/byte write enable
FB_OE
O
Output enable
FB_R/W
O
Read/write. 1 = Read, 0 = Write
FB_TS
O
Transfer start
FB_TA
I
Transfer acknowledge
Because this device shares the FlexBus signals with the SDRAM controller, these signal directions are only
valid when the FlexBus controls them. The directions may change during SDRAM cycles.
Address and Data Buses (FB_A[23:0], FB_D[31:0])
The FB_A[23:0] and FB_D[31:0] buses carry the address and data, respectively. The number of byte lanes
carrying the data is determined by the port size associated with the matching chip select.
Because this device shares the FlexBus signals with the SDRAM controller, these signals tristate between
bus cycles.
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FlexBus
18.2.2
Chip Selects (FB_CS[5:0])
The chip-select signal indicates which device is selected. A particular chip-select asserts when the transfer
address is within the device’s address space, as defined in the base- and mask-address registers. The actual
number of chip selects available depends upon the pin configuration. See Table 2-2 for more details.
18.2.3
Byte Enables/Byte Write Enables (FB_BE/BWE[3:0])
When driven low, the byte enable (FB_BE/BWE[3:0]) outputs indicate data is to be latched or driven onto
a byte of the data bus. FB_BE/BWEn signals are asserted only to the memory bytes used during read or
write accesses. A configuration option is provided to assert these signals on reads and writes (byte enable)
or writes only (byte-write enable).
The FB_BE/BWEn signals are asserted during accesses to on-chip peripherals but not to on-chip SRAM
or cache. For external SRAM or flash devices, the FB_BE/BWEn outputs must be connected to individual
byte strobe signals.
18.2.4
Output Enable (FB_OE)
The output enable signal (FB_OE) is sent to the interfacing memory and/or peripheral to enable a read
transfer. FB_OE is only asserted during read accesses when a chip select matches the current address
decode.
Because this device shares the FlexBus signals with the SDRAM controller, this signal tristates between
bus cycles.
18.2.5
Read/Write (FB_R/W)
The processor drives the FB_R/W signal to indicate the current bus operation direction. It is driven high
during read bus cycles and low during write bus cycles.
Because this device shares the FlexBus signals with the SDRAM controller, this signal tristates between
bus cycles.
18.2.6
Transfer Start (FB_TS)
The assertion of FB_TS indicates that the device has begun a bus transaction and the address and attributes
are valid. FB_TS is asserted for one bus clock cycle.
Because this device shares the FlexBus signals with the SDRAM controller, this signal tristates between
bus cycles.
18.2.7
Transfer Acknowledge (FB_TA)
This signal indicates the external data transfer is complete. When the processor recognizes FB_TA during
a read cycle, it latches the data and then terminates the bus cycle. When the processor recognizes FB_TA
during a write cycle, the bus cycle is terminated.
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FlexBus
If auto-acknowledge is disabled (CSCRn[AA] = 0), the external device drives FB_TA to terminate the bus
transfer; if auto-acknowledge is enabled (CSCRn[AA] = 1), FB_TA is generated internally after a
specified number of wait states, or the external device may assert external FB_TA before the wait-state
countdown, terminating the cycle early. The device negates FB_CSn one cycle after the last FB_TA
asserts. During read cycles, the peripheral must continue to drive data until FB_TA is recognized. For write
cycles, the processor continues driving data one clock after FB_CSn is negated.
The number of wait states is determined by CSCRn or the external FB_TA input. If the external FB_TA is
used, the peripheral has total control on the number of wait states.
NOTE
External devices should only assert FB_TA while the FB_CSn signal to the
external device is asserted.
Because this device shares the FlexBus signals with the SDRAM controller,
this signal tristates between bus cycles.
18.3
Memory Map/Register Definition
The following tables describe the registers and bit meanings for configuring chip-select operation.
Table 18-2 shows the chip-select register memory map.
The actual number of chip select registers available depends upon the device and its pin configuration. See
Table 2-2 for more details. If the device does not support certain chip select signals or the pin is not
configured for a chip-select function, then that corresponding set of chip-select registers has no effect on
an external pin.
NOTE
You must set CSMR0[V] before the chip select registers take effect.
Table 18-2. FlexBus Chip Select Memory Map
Address
Register
Width
Access
(bits)
Reset Value
Section/
Page
0xFC00_8000 Chip-Select Address Register (CSARn)
+ (n × 0xC)
n=0–5
32
R/W
0x0000_0000
18.3.1/18-5
0xFC00_8004 Chip-Select Mask Register (CSMRn)
+ (n × 0xC)
n=0–5
32
R/W
0x0000_0000
18.3.2/18-5
0xFC00_8008 Chip-Select Control Register (CSCRn)
+ (n × 0xC)
n=0–5
32
R/W
See Section
18.3.3/18-6
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FlexBus
18.3.1
Chip-Select Address Registers (CSAR0 – CSAR5)
The CSARn registers specify the chip-select base addresses.
NOTE
Because the FlexBus module is one of the slaves connected to the crossbar
switch, it is only accessible within a certain memory range. The only
applicable address ranges for which the chip-selects can be active are
0x0000_0000 – 0x3FFF_FFFF and 0xC000_0000 – 0xDFFF_FFFF. Set the
CSARn registers appropriately.
Address: 0xFC00_8000 (CSAR0)
0xFC00_800C (CSAR1)
0xFC00_8018 (CSAR2)
0xFC00_8024 (CSAR3)
0xFC00_8030 (CSAR4)
0xFC00_803C (CSAR5)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
BA
W
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-1. Chip-Select Address Registers (CSARn)
Table 18-3. CSARn Field Descriptions
Field
Description
31–16
BA
Base address. Defines the base address for memory dedicated to chip-select FB_CSn. BA is compared to
bits 31–16 on the internal address bus to determine if chip-select memory is being accessed.
15–0
Reserved, must be cleared.
18.3.2
Chip-Select Mask Registers (CSMR0 – CSMR5)
CSMRn registers specify the address mask and allowable access types for the respective chip-selects.
Address: 0xFC00_8004 (CSMR0)
0xFC00_8010 (CSMR1)
0xFC00_801C (CSMR2)
0xFC00_8028 (CSMR3)
0xFC00_8034 (CSMR4)
0xFC00_8040 (CSMR5)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
BAM
0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8
WP
0
7
6
5
4
3
2
1
0 0 0 0 0 0 0
0
V
0 0 0 0 0 0 0 0
Figure 18-2. Chip-Select Mask Registers (CSMRn)
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FlexBus
Table 18-4. CSMRn Field Descriptions
Field
31–16
BAM
Description
Base address mask. Defines the chip-select block size by masking address bits. Setting a BAM bit causes the
corresponding CSAR bit to be a don’t care in the decode.
0 Corresponding address bit is used in chip-select decode.
1 Corresponding address bit is a don’t care in chip-select decode.
The block size for FB_CSn is 2n; n = (number of bits set in respective CSMR[BAM]) + 16.
For example, if CSAR0 equals 0x0000 and CSMR0[BAM] equals 0x0008, FB_CS0 addresses two discontinuous
64 KB memory blocks: one from 0x40_0000 – 0x40_FFFF and one from 0x48_0000 – 0x48_FFFF.
Likewise, for FB_CS0 to access 32 MB of address space starting at location 0x00_0000, FB_CS1 must begin at the
next byte after FB_CS0 for a 16 MB address space. Then, CSAR0 equals 0x0000, CSMR0[BAM] equals 0x01FF,
CSAR1 equals 0x0200, and CSMR1[BAM] equals 0x00FF.
15–9
Reserved, must be cleared.
8
WP
Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the
range of addresses for which CSARn[WP] is set results in a bus error termination of the internal cycle and no external
cycle.
0 Read and write accesses are allowed
1 Only read accesses are allowed
7–1
Reserved, must be cleared.
0
V
18.3.3
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed
chip-selects do not assert until V bit is set (except for FB_CS0, which acts as the global chip-select). Reset clears
each CSMRn[V].
Note: At reset, no chip-select other than FB_CS0 can be used until the CSMR0[V] is set. Afterward, FB_CS[5:0]
functions as programmed.
0 Chip-select invalid
1 Chip-select valid
Chip-Select Control Registers (CSCR0 – CSCR5)
Each CSCRn controls the auto-acknowledge, address setup and hold times, port size, burst capability, and
number of wait states. To support the global chip-select, FB_CS0, the CSCR0 reset values differ from the
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other CSCRs. FB_CS0 allows address decoding for an external device to serve as the boot memory before
system initialization and configuration are completed.
Address: 0xFC00_8008 (CSCR0)
0xFC00_8014 (CSCR1)
0xFC00_8020 (CSCR2)
0xFC00_802C (CSCR3)
0xFC00_8038 (CSCR4)
0xFC00_8044 (CSCR5)
31
30
29
R
28
Access: User
read/write
27
26
SWS
W
25
24
0
0
23
22
SWSEN
21
0
20
ASET
19
18
RDAH
17
16
WRAH
Reset: CSCR0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Reset: CSCR1–5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
R
WS
W
Reset: CSCR0
Reset: CSCR1–5
SBM
AA
PS
BEM BSTR BSTW
2
1
0
0
0
0
1
1
1
1
1
1
See
Note
1
See
Note
See
Note
1
0
0
0
0
0
0
0
0
0
0
0
See
Note
1
0
0
1
0
0
0
0
0
Note: The SBM reset value is determined by the chosen chip configuration. See SBM field description in Table 18-5 for more
information.
Note: The PS reset value depends upon the chosen chip configuration. If using the default or parallel configurations
(BOOTMOD ≠ 11), CSCR0[PS] resets to 11. If serial boot is chosen (BOOTMOD = 11), the CSCR0[PS] reset value is
determined by SBF_RCON[BOOTPS].
Figure 18-3. Chip-Select Control Registers (CSCRn)
Table 18-5. CSCRn Field Descriptions
Field
Description
31–26
SWS
Secondary wait states. The number of wait states inserted before an internal transfer acknowledge is generated for
a burst transfer except for the first termination, which is controlled by the wait state count. The secondary wait state
is used only if the SWSEN bit is set. Otherwise, the WS value is used for all burst transfers.
25–24
Reserved, must be cleared
23
Secondary wait state enable.
SWSEN 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers.
1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer
secondary terminations.
22
21–20
ASET
Reserved, must be cleared
Address setup. This field controls the assertion of the chip-select with respect to assertion of a valid address and
attributes. The address and attributes are considered valid at the same time FB_TS asserts.
00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)
01 Assert FB_CSn on second rising clock edge after address is asserted.
10 Assert FB_CSn on third rising clock edge after address is asserted.
11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-7
FlexBus
Table 18-5. CSCRn Field Descriptions (continued)
Field
Description
19–18
RDAH
Read address hold or deselect. This field controls the address and attribute hold time after the termination during a
read cycle that hits in the chip-select address space.
Note: The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer to a port size
smaller than the transfer size, the hold time is only added after the last bus cycle.
The number of cycles the address and attributes are held after FB_CSn negation depends on the value of
CSCRn[AA] as shown below.
RDAH
AA = 0
AA = 1
00
(FB_CSn Default)
1 cycle
0 cycles
01
2 cycles
1 cycles
10
3 cycles
2 cycles
11
(FB_CS0 Default)
4 cycles
3 cycles
17–16
WRAH
Write address hold or deselect. This field controls the address, data, and attribute hold time after the termination of
a write cycle that hits in the chip-select address space.
Note: The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer to a port size
smaller than the transfer size, the hold time is only added after the last bus cycle.
00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)
01 Hold address and attributes two cycles after FB_CSn negates on writes.
10 Hold address and attributes three cycles after FB_CSn negates on writes.
11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)
15–10
WS
Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge
is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states). If AA is reserved, FB_TA must be
asserted by the external system regardless of the number of generated wait states. In that case, the external transfer
acknowledge ends the cycle. An external FB_TA supersedes the generation of an internal FB_TA.
9
SBM
Split bus mode. For proper operation of the chip select signals, this bit must be set when the SDRAM controller is in
DDR mode.
0 Device is not in split bus mode (SDRAM controller is in SDR mode).
1 Device is in split bus mode (SDRAM controller is in DDR mode).
Note: Placing the device in split bus mode is only controlled by BOOTMOD or override signals (see Chapter 9, “Chip
Configuration Module (CCM),” for more details). This bit is only used to provide correct operation of the chip
select signals.
8
AA
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by
the chip-select address.
0 No internal FB_TA is asserted. Cycle is terminated externally
1 Internal transfer acknowledge is asserted as specified by WS
Note: If AA is set for a corresponding FB_CSn and the external system asserts an external FB_TA before the
wait-state countdown asserts the internal FB_TA, the cycle is terminated. Burst cycles increment the address
bus between each internal termination.
MCF52277 Reference Manual, Rev 2
18-8
Freescale Semiconductor
FlexBus
Table 18-5. CSCRn Field Descriptions (continued)
Field
Description
7–6
PS
Port size. Specifies the data port width associated with each chip-select. It determines where data is driven during
write cycles and where data is sampled during read cycles.
00 32-bit port size. Valid data sampled and driven on FB_D[31:0]
01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if SBM = 0 or FB_D[7:0] if SBM = 1
1x 16-bit port size. Valid data sampled and driven on FB_D[31:16] if SBM = 0 or FB_D[15:0] if SBM = 1
5
BEM
Byte-enable mode. Specifies the byte enable operation. Certain memories have byte enables that must be asserted
during reads and writes. BEM can be set in the relevant CSCR to provide the appropriate mode of byte enable
support for these SRAMs.
0 FB_BE/BWE is not asserted for reads. FB_BE/BWE is asserted for data write only.
1 FB_BE/BWE is asserted for read and write accesses.
4
BSTR
Burst-read enable. Specifies whether burst reads are used for memory associated with each FB_CSn.
0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a
longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports,
word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.
3
BSTW
Burst-write enable. Specifies whether burst writes are used for memory associated with each FB_CSn.
0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword
write to an 8-bit port takes four byte writes.
1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word
writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
2–0
18.4
18.4.1
Reserved, must be cleared.
Functional Description
Chip-Select Operation
Each chip-select has a dedicated set of registers for configuration and control:
• Chip-select address registers (CSARn) control the base address space of the chip-select. See
Section 18.3.1, “Chip-Select Address Registers (CSAR0 – CSAR5).”
• Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See
Section 18.3.2, “Chip-Select Mask Registers (CSMR0 – CSMR5).”
• Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state
generation, address setup and hold times, and automatic acknowledge generation features. See
Section 18.3.3, “Chip-Select Control Registers (CSCR0 – CSCR5).”
FB_CS0 is a global chip-select after reset and provides external boot memory capability.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-9
FlexBus
18.4.1.1
General Chip-Select Operation
When a bus cycle is routed to the FlexBus, the device first compares its address with the base address and
mask configurations programmed for chip-selects 0 to 5 (configured in CSCR0 – CSCR5). The results
depend on if the address matches or not as shown in Table 18-6.
Table 18-6. Results of Address Comparison
Address Matches
CSARn?
Result
Yes,
one CSAR
The appropriate chip-select is asserted, generating an external bus cycle as defined in the chip-select
control register.
No
The chip-select signals are not driven. However, the FlexBus runs an external bus cycle with external
termination.
Yes,
multiple CSARs
18.4.1.2
The chip-select signals are driven. However, they are driven using an external burst-inhibited bus cycle
with external termination on a 32-bit port.
8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. The processor always drives a
24 -bit address on the FB_A bus regardless of the external device’s address size. The external device must
connect its address lines to the appropriate FB_A bits from FB_A0 upward. Its data bus must be connected
to FB_D[7:0] from FB_AD31 downward. No bit ordering is required when connecting address and data
lines to the FB_A and FB_D buses. For example, a full 16-bit address/16-bit data device connects its
addr[15:0] to FB_A[16:1] and data[15:0] to FB_D[31:16]. See Figure 18-4 for a graphical connection.
18.4.1.3
Global Chip-Select Operation
FB_CS0, the global (boot) chip-select, supports external boot memory accesses before system
initialization. Its operation differs from other external chip-select outputs after system reset.
After system reset, FB_CS0 is asserted for every external access. No other chip-select can be used until
the valid bit, CSMR0[V], is set; at this point FB_CS0 functions as configured. After this, FB_CS[5:1] can
be used as well. At reset during parallel boot, the logic levels on the FB_A17 and FB_A21 signals
determine global chip-select port size. During serial boot, the value of SBF_RCON[31:30] determine the
port size.
See Chapter 9, “Chip Configuration Module (CCM),” for more information.
18.4.2
Data Transfer Operation
Data transfers between the chip and other devices involve these signals:
•
Address/data bus (FB_A[23:0], FB_D[31:0])
•
Control signals (FB_TS, FB_TA, FB_CSn, FB_OE, FB_BE/BWE[3:0])
•
Attribute signals (FB_R/W)
MCF52277 Reference Manual, Rev 2
18-10
Freescale Semiconductor
FlexBus
The address, write data, FB_TS, FB_CSn, and all attribute signals change on the rising edge of the FlexBus
clock (FB_CLK). Read data is latched into the device on the rising edge of the clock.
The FlexBus supports byte-, word-, longword-, and 16-byte (line) operand transfers and allows accesses
to 8-, 16-, and 32-bit data ports.Transfer parameters (address setup and hold, port size, the number of wait
states for the external device being accessed, automatic internal transfer termination enable or disable, and
burst enable or disable) are programmed in the chip-select control registers (CSCRs). See Section 18.3.3,
“Chip-Select Control Registers (CSCR0 – CSCR5).”
18.4.3
Data Byte Alignment and Physical Connections
The device aligns data transfers in FlexBus byte lanes with the number of lanes depending on the data port
width. The byte lane assignment is also dependent on the split bus mode setting in the CSCRn register.
Figure 18-4 shows the byte lanes that external memory connects to and the sequential transfers of a
longword transfer for the supported port sizes when not in split bus mode. For example, an 8-bit memory
connects to the single lane FB_D[31:24] (FB_BE/BWE0). A longword transfer through this 8-bit port
takes four transfers, starting with the MSB to the LSB. A longword transfer through a 32-bit port requires
one transfer on each four-byte lane of the FlexBus.
Byte Select
External
Data Bus
FB_BE/BWE0 FB_BE/BWE1 FB_BE/BWE2 FB_BE/BWE3
FB_D[31:24]
FB_D[23:16]
32-Bit Port
Memory
Byte 0
Byte 1
16-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 3
8-Bit Port
Memory
FB_D[15:8]
Byte 2
FB_D[7:0]
Byte 3
Driven with
address values
Byte 0
Byte 1
Byte 2
Driven with
address values
Byte 3
Figure 18-4. Connections for External Memory Port Sizes (CSCRn[SBM] = 0)
Figure 18-5 shows the byte lanes that external memory connects to and the sequential transfers of a
longword transfer for the supported port sizes when in split bus mode.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-11
FlexBus
Byte Select
FB_BE/BWE1 FB_BE/BWE0
External
Data Bus
FB_D[15:8]
16-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 3
8-Bit Port
Memory
FB_D[7:0]
Byte 0
Driven with
address
values
Byte 1
Byte 2
Byte 3
Figure 18-5. Connections for External Memory Port Sizes (CSCRn[SBM] = 1)
18.4.4
Bus Cycle Execution
As shown in Figure 18-8 and Figure 18-10, basic bus operations occur in four clocks:
1. S0: At the first clock edge, the address, attributes, and FB_TS are driven.
2. S1: FB_CSn is asserted at the second rising clock edge to indicate the device selected; by that time,
the address and attributes are valid and stable. FB_TS is negated at this edge.
For a write transfer, data is driven on the bus at this clock edge and continues to be driven until one
clock cycle after FB_CSn negates. For a read transfer, data is also driven into the device during this
cycle.
External slave asserts FB_TA at this clock edge.
3. S2: Read data and FB_TA are sampled on the third clock edge. FB_TA can be negated after this
edge and read data can then be tri-stated.
4. S3: FB_CSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what
would be an idle clock between cycles to provide hold time for address, attributes, and write data.
MCF52277 Reference Manual, Rev 2
18-12
Freescale Semiconductor
FlexBus
18.4.4.1
Data Transfer Cycle States
An on-chip state machine controls the data-transfer operation in the device. Figure 18-6 shows the
state-transition diagram for basic read and write cycles.
S0
Next Cycle
Wait States
S3
S1
S2
Figure 18-6. Data-Transfer-State-Transition Diagram
Table 18-7 describes the states as they appear in subsequent timing diagrams.
Table 18-7. Bus Cycle States
State
Cycle
Description
S0
All
The read or write cycle is initiated. On the rising clock edge, the device places a valid address on
FB_A[ 23 :0], asserts FB_TS, and drives FB_R/W high for a read and low for a write.
S1
All
FB_TS is negated on the rising edge of FB_CLK, and FB_CSn is asserted. Data is driven on
FB_D[31:X] for writes, and FB_D[31:X] is tristated for reads. Address continues to be driven on
the FB_A pins.
If FB_TA is recognized asserted, then the cycle moves on to S2. If FB_TA is not asserted
internally or externally, then the S1 state continues to repeat.
S2
S3
18.4.5
Read
Data is driven by the external device before the next rising edge of FB_CLK (the rising edge that
begins S2) with FB_TA asserted.
All
For internal termination, FB_CSn is negated and the internal system bus transfer is completed.
For external termination, the external device should negate FB_TA, and the FB_CSn chip select
negates after the rising edge of FB_CLK at the end of S2.
Read
The processor latches data on the rising clock edge entering S2. The external device can stop
driving data after this edge. However, data can be driven until the end of S3 or any additional
address hold cycles.
All
Address, data, and FB_R/W go invalid off the rising edge of FB_CLK at the beginning of S3,
terminating the read or write cycle.
FlexBus Timing Examples
NOTE
Because this device shares the FlexBus signals with the SDRAM controller,
all signals, except the chip selects, tristate between bus cycles.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-13
FlexBus
18.4.5.1
Basic Read Bus Cycle
During a read cycle, the ColdFire device receives data from memory or a peripheral device. Figure 18-7
is a read cycle flowchart.
NOTE
Throughout this chapter FB_D[31:X] indicates a 32-, 16-, or 8-bit wide data bus.
ColdFire device
System
1. Set FB_R/W to read.
2. Place address on FB_D[23:0].
3. Assert FB_TS.
1. Decode address.
1. Negate FB_TS.
2. Assert FB_CSn.
1. FlexBus asserts internal FB_TA
(auto-acknowledge/internal termination).
1. Select the appropriate slave device.
2. Sample FB_TA low and latch data.
3. Assert FB_TA (external termination).
1. Start next cycle.
1. Negate FB_TA (external termination).
2. Drive data on FB_D[31:X].
Figure 18-7. Read Cycle Flowchart
The read cycle timing diagram is shown in Figure 18-8.
NOTE
In the next set of timing diagrams, the dotted lines indicate FB_TA, FB_OE,
and FB_CSn timing when internal termination is used (CSCR[AA] = 1).
The external and internal FB_TA assert at the same time; however, FB_TA
is not driven externally for internally-terminated bus cycles.
NOTE
The processor drives the data lines during the first clock cycle of the transfer
with the full 32-bit address. This may be ignored by standard connected
devices using non-multiplexed address and data buses. However, some
applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the read bus cycles the address signals are
indeterminate.
MCF52277 Reference Manual, Rev 2
18-14
Freescale Semiconductor
FlexBus
S0
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-8. Basic Read-Bus Cycle
18.4.5.2
Basic Write Bus Cycle
During a write cycle, the device sends data to memory or to a peripheral device. Figure 18-9 shows the
write cycle flowchart.
ColdFire device
System
1. Set FB_R/W to write.
2. Place address on FB_D[23:0].
3. Assert FB_TS.
1. Decode address.
1. Negate FB_TS.
2. Assert FB_CSn.
3. Drive data.
1. Select the appropriate slave device.
1. FlexBus asserts internal FB_TA
(auto acknowledge/internal termination).
2. Latch data on FB_D[31:X].
2. Sample FB_TA low.
3. Assert FB_TA (external termination).
1. Start next cycle.
1. Negate FB_TA (external termination).
Figure 18-9. Write-Cycle Flowchart
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-15
FlexBus
Figure 18-10 shows the write cycle timing diagram.
NOTE
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the write bus cycles, the address signals are
indeterminate.
S0
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
ADDR[23:0]
FB_D[31:X]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 18-10. Basic Write-Bus Cycle
18.4.5.3
Bus Cycle Sizing
This section shows timing diagrams for various port size scenarios. Figure 18-11 illustrates the basic byte
read transfer to an 8-bit device with no wait states. The address is driven on the FB_A[ 23:8 ] bus
throughout the bus cycle. The external device returns the read data on FB_D[31:24] and may tristate the
data line or continue driving the data one clock after FB_TA is sampled asserted.
S0
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:24]
ADDR[23:0]
ADDR[31:24]
DATA[7:0]
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-11. Single Byte-Read Transfer
MCF52277 Reference Manual, Rev 2
18-16
Freescale Semiconductor
FlexBus
Figure 18-12 shows the similar configuration for a write transfer. The data is driven from the second clock
on FB_D[31:24].
S0
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:24]
ADDR[23:0]
ADDR[31:24]
DATA[7:0]
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 18-12. Single Byte-Write Transfer
Figure 18-13 illustrates the basic word read transfer to a 16-bit device with no wait states. The address is
driven on the FB_A[ 23:8 :0] bus throughout the bus cycle. The external device returns the read data on
FB_D[31:16], and may tristate the data line or continue driving the data one clock after FB_TA is sampled
asserted.
S0
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:16]
ADDR[23:0]
ADDR[31:16]
DATA[15:0]
FB_R/W
FB_TS
FB_CSn, FB_OE
FB_BE/BWEn
FB_TA
Figure 18-13. Single Word-Read Transfer
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-17
FlexBus
Figure 18-14 shows the similar configuration for a write transfer. The data is driven from the second clock
on FB_D[31:16].
S1
S0
S2
S3
S0
FB_CLK
FB_A[15:0]
FB_D[31:16]
ADDR[15:0]
ADDR[31:16]
DATA[15:0]
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 18-14. Single Word-Write Transfer
Figure 18-15 depicts a longword read from a 32-bit device.
S0
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:0]
ADDR[23:0]
ADDR[31:0]
DATA[31:0]
FB_R/W
FB_TS
FB_CSn, FB_OE
FB_BE/BWEn
FB_TA
Figure 18-15. Longword-Read Transfer
MCF52277 Reference Manual, Rev 2
18-18
Freescale Semiconductor
FlexBus
Figure 18-16 illustrates the longword write to a 32-bit device.
S0
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:0]
ADDR[23:0]
ADDR[31:0]
DATA[31:0]
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 18-16. Longword-Write Transfer
18.4.5.4
Timing Variations
The FlexBus module has several features that can change the timing characteristics of a basic read- or
write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch
data.
18.4.5.4.1
Wait States
Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states
can give the peripheral or memory more time to return read data or sample write data.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-19
FlexBus
Figure 18-17 and Figure 18-18 show the basic read and write bus cycles (also shown in Figure 18-8 and
Figure 18-13) with the default of no wait states.
S0
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-17. Basic Read-Bus Cycle (No Wait States)
S0
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 18-18. Basic Write-Bus Cycle (No Wait States)
MCF52277 Reference Manual, Rev 2
18-20
Freescale Semiconductor
FlexBus
If wait states are used, the S1 state repeats continuously until the the chip-select auto-acknowledge unit
asserts internal transfer acknowledge or the external FB_TA is recognized as asserted. Figure 18-19 and
Figure 18-20 show a read and write cycle with one wait state.
S0
S1
WS
S2
S3
S0
FB_CLK
FB_A[23:0]
ADDR[23:0]
FB_D[31:X]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-19. Read-Bus Cycle (One Wait State)
S0
S1
WS
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 18-20. Write-Bus Cycle (One Wait State)
18.4.5.4.2
Address Setup and Hold
The timing of the assertion and negation of the chip selects, byte selects, and output enable can be
programmed on a chip-select basis. Each chip-select can be programmed to assert one to four clocks after
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-21
FlexBus
transfer start (FB_TS) is asserted. Figure 18-21 and Figure 18-22 show read- and write-bus cycles with
two clocks of address setup.
S0
AS
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-21. Read-Bus Cycle with Two-Clock Address Setup (No Wait States)
S0
AS
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 18-22. Write-Bus Cycle with Two Clock Address Setup (No Wait States)
MCF52277 Reference Manual, Rev 2
18-22
Freescale Semiconductor
FlexBus
In addition to address setup, a programmable address hold option for each chip select exists. Address and
attributes can be held one to four clocks after chip-select, byte-selects, and output-enable negate.
Figure 18-23 and Figure 18-24 show read and write bus cycles with two clocks of address hold.
S0
S1
S2
AH
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-23. Read Cycle with Two-Clock Address Hold (No Wait States)
S0
S1
S2
AH
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 18-24. Write Cycle with Two-Clock Address Hold (No Wait States)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-23
FlexBus
Figure 18-25 shows a bus cycle using address setup, wait states, and address hold.
S0
AS
S1
WS
S2
AH
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
ADDR[31:X]
DATA
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
Figure 18-25. Write Cycle with Two-Clock Address Setup and
Two-Clock Hold (One Wait State)
18.4.6
Burst Cycles
The device can be programmed to initiate burst cycles if its transfer size exceeds the port size of the
selected destination. With bursting disabled, any transfer larger than the port size breaks into multiple
individual transfers. With bursting enabled, an access larger than port size results in a burst cycle of
multiple beats. Table 18-8 shows the result of such transfer translations.
Table 18-8. Transfer Size and Port Size Translation
Port Size PS[1:0]
Transfer Size
Burst-Inhibited: Number of Transfers
Burst Enabled: Number of Beats
01 (8-bit)
word
2
longword
4
line
16
longword
2
line
8
line
4
1x (16-bit)
00 (32-bit)
The FlexBus can support 2-1-1-1 burst cycles to maximize system performance. Delaying termination of
the cycle can add wait states. If internal termination is used, different wait state counters can be used for
the first access and the following beats.
The CSCRn registers enable bursting for reads, writes, or both. Memory spaces can be declared
burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW] bits.
MCF52277 Reference Manual, Rev 2
18-24
Freescale Semiconductor
FlexBus
Figure 18-26 shows a longword read to an 8-bit device programmed for burst enable. The transfer results
in a 4-beat burst and the data is driven on FB_D[31:24].
NOTE
Address lines increment only during internally-terminated burst cycles. The
first address is driven throughout the entire burst for externally-terminated
cycles.
S0
S1
S2
S2
S2
ADDR + 1
ADDR + 2
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:24]
ADDR[23:0]
ADDR[31:24]
DATA
DATA
DATA
ADDR + 3
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-26. Longword-Read Burst from 8-Bit Port 2-1-1-1 (No Wait States)
Figure 18-27 shows a longword write to an 8-bit device with burst enabled. The transfer results in a 4-beat
burst and the data is driven on FB_D[31:24].
NOTE
The first beat of any write burst cycle has at least one wait state. If the bus
cycle is programmed for zero wait states (CSCRn[WS] = 0), one wait state
is added. Otherwise, the programmed number of wait states are used.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-25
FlexBus
S0
S1
WS
S2
S2
S2
S2
S3
S0
FB_CLK
FB_A[23:0]
ADDR + 1
ADDR[23:0]
ADDR
[31:24]
FB_D[31:24]
DATA
ADDR + 2
DATA
ADDR + 3
DATA
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-27. Longword-Write Burst to 8-Bit Port 3-1-1-1 (No Wait States)
Figure 18-28 shows a longword read from an 8-bit device with burst inhibited. The transfer results in four
individual transfers.
NOTE
There is an extra clock of address setup (AS) for each burst-inhibited
transfer between states S0 and S1.
S0
AS
S1
S2
S0
AS
S1
S2
S0
AS
S1
S2
S0
AS
S1
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:24]
ADDR[23:0]
ADDR
[31:24]
DATA
ADDR + 1
ADDR + 2
DATA
DATA
ADDR + 3
DATA
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE
FB_BE/BWEn
FB_TA
Figure 18-28. Longword-Read Burst-Inhibited from 8-Bit Port (No Wait States)
MCF52277 Reference Manual, Rev 2
18-26
Freescale Semiconductor
FlexBus
Figure 18-29 shows a longword write to an 8-bit device with burst inhibited. The transfer results in four
individual transfers.
S0
AS
S1
S2
S0
AS
S1
S2
S0
AS
S1
S2
S0
S1
AS
S2
S3
S0
FB_CLK
FB_A[23:0]
ADDR[23:0]
ADDR
[31:24]
FB_D[31:24]
ADDR + 1
DATA
ADDR + 2
DATA
ADDR + 3
DATA
DATA
DATA
FB_R/W
FB_TS
FB_CSn
FB_BE/BWEn
FB_OE
FB_TA
Figure 18-29. Longword-Write Burst-Inhibited to 8-Bit Port (No Wait States)
Figure 18-30 illustrates another read burst transfer, but in this case a wait state is added between individual
beats.
NOTE
CSCRn[WS] determines the number of wait states in the first beat.
However, for subsequent beats, the CSCRn[WS] (or CSCRn[SWS] if
CSCRn[SWSEN] is set) determines the number of wait states.
S0
S1
WS
S2
WS/SWS
S2
WS/SWS
S2
WS/SWS
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:24]
ADDR + 1
ADDR[23:0]
ADDR[31:24]
DATA
DATA
ADDR + 2
DATA
ADDR + 3
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-30. Longword-Read Burst from 8-Bit Port 3-2-2-2 (One Wait State)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-27
FlexBus
Figure 18-30 illustrates a write burst transfer with one wait state.
S0
S1
WS
S2
WS/SWS
S2
WS/SWS
S2
WS/SWS
S2
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:24]
ADDR[23:0]
ADDR
[31:24]
ADDR + 1
ADDR + 2
ADDR + 3
DATA
DATA
DATA
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE,
FB_BE/BWEn
FB_TA
Figure 18-31. Longword-Write Burst to 8-Bit Port 3-2-2-2 (One Wait State)
If address setup and hold are used, only the first and last beat of the burst cycle are affected. Figure 18-32
shows a read cycle with one clock of address setup and address hold.
NOTE
When using internal termination in this scenario (CSCRn[AA] = 1), the
address increments after the clock-edge boundary. The attached device must
be able to account for this, or a wait state must be added.
S0
AS
S1
S2
S2
S2
S2
AH1
S3
FB_CLK
DATA
DATA
DATA
DATA
FB_R/W
FB_TS
FB_TA
Figure 18-32. Longword-Read Burst from 8-Bit Port 3-1-1-1 (Address Setup and Hold)
MCF52277 Reference Manual, Rev 2
18-28
Freescale Semiconductor
FlexBus
Figure 18-33 shows a write cycle with one clock of address setup and address hold.
S0
AS
S1
S2
S2
S2
S2
AH
S3
S0
FB_CLK
FB_A[23:0]
FB_D[31:24]
ADDR[23:0]
ADDR[31:24]
ADDR + 1 ADDR + 2
DATA
DATA
DATA
ADDR + 3
DATA
FB_R/W
FB_TS
FB_CSn, FB_OE
FB_BE/BWEn
FB_TA
Figure 18-33. Longword-Write Burst to 8-Bit Port 3-1-1-1 (Address Setup and Hold)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
18-29
FlexBus
18.4.7
Misaligned Operands
Because operands, unlike opcodes, can reside at any byte boundary, they are allowed to be misaligned.
• Byte operand is properly aligned at any address
• Word operand is misaligned at an odd address
• Longword is misaligned at any address not a multiple of four
Although the processor enforces no alignment restrictions for data operands (including program counter
(PC) relative data addressing), misaligned operands require additional bus cycles.
Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch
a misaligned instruction word causes an address-error exception.
The processor core converts misaligned, cache-inhibited operand accesses to multiple aligned accesses.
Example 18-1 shows the transfer of a longword operand from a byte address to a 32-bit port. First, a byte
transfers at an offset of 0x1. The slave device supplies the byte and acknowledges the data transfer. When
the processor starts the second cycle, a word transfers with a byte offset of 0x2. The next two bytes are
transferred in this cycle. In the third cycle, byte 3 transfers. The byte offset is now 0x0, the port supplies
the final byte, and the operation completes.
31
24 23
16 15
8 7
0
FB_A[2:0]
Transfer 1
––
Byte 0
––
––
001
Transfer 2
––
––
Byte 1
Byte 2
010
Transfer 3
Byte 3
––
––
––
100
Example 18-1. A Misaligned Longword Transfer (32-Bit Port)
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the
cache. The example in Example 18-2 differs from the one in Example 18-1 because the operand is
word-sized and the transfer takes only two bus cycles.
31
24 23
16 15
8 7
0
FB_A[2:0]
Transfer 1
––
––
––
Byte 0
001
Transfer 2
Byte 0
––
––
—
100
Example 18-2. A Misaligned Word Transfer (32-Bit Port)
18.4.8
Bus Errors
If the auto-acknowledge feature is not enabled for the address that generates the error, the bus cycle can
be terminated by asserting FB_TA. If the processor must manage a bus error differently, asserting an
interrupt to the core along with FB_TA when the bus error occurs can invoke an interrupt handler.
The device also includes a bus monitor that generates a bus error for unterminated cycles.
MCF52277 Reference Manual, Rev 2
18-30
Freescale Semiconductor
Chapter 19
SDRAM Controller (SDRAMC)
19.1
Introduction
This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It
begins with a general description and brief glossary and includes a description of signals involved in
DRAM operations. The remainder of the chapter describes the programming model and signal timing, as
well as the command set required for synchronous operations. It also includes examples to better
understand how to configure the DRAM controller for synchronous operations.
NOTE
Unless otherwise noted, in this chapter clock refers to the system clock
(fsys/2).
The external data bus is shared between the FlexBus module and the
SDRAM controller. When the SDRAM controller is in SDR mode, the data
bus is switched dynamically between the SDRAM controller and the
FlexBus module. However, when the SDRAM controller is in DDR mode,
D[31:16] is dedicated to the SDRAM data bus and D[15:0] is dedicated to
the FlexBus data bus.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
19-1
SDRAM Controller (SDRAMC)
19.1.1
Block Diagram
Block diagram of the SDRAM controller:
Column
Column
ADDR
Address
Input
MUX
Bank
Row
Address
Pipeline
Latches
Bank
Row
Address
Output
MUX
SD_A[13:0]
SD_BA[1:0]
Bus Gasket to SDRAM Controller
Internal System Bus
Command
Type
SD_CLK/CLK
IPS Interface
Register
File
SDRAM
Controller
State
Machine
SD_CKE
SD_CS[1:0]
SD_RAS
SD_CAS
SD_WE
Address
SD_SDRDQS
SD_DQS[3:2]
Controls
SD_DQM[3:0]
Data in [63:0]
Data out [63:0]
Write Data
Buffer
SD_D[31:0]
Read Data
Buffer
Figure 19-1. SDRAM Controller Block Diagram
19.1.2
Features
The SDRAM controller contains:
• Supports standard SDRAM (single data rate, or SDR) and dual data rate (DDR) SDRAM; one or
the other, not mixed
• Support for lower-power/mobile DDR SDRAM
• Dynamic 16- or 32-bit fixed memory data port width
• 16 bytes critical word first burst transfer. Supports sequential address order only
• Up to 14 lines of row address, up to 12 (in 32-bit bus mode) or 13 (in 16-bit bus mode) column
address lines, 2 bits of bank address, and two pinned-out chip selects. The maximum row bits plus
column bits equals 24 in 32-bit bus mode or 25 in 16-bit bus mode.
• Minimum memory configuration of 8 MByte
— 11 bit row address (RA), 8 bit column address (CA), 2 bit bank address (BA), 32-bit bus,
one chip select
MCF52277 Reference Manual, Rev 2
19-2
Freescale Semiconductor
SDRAM Controller (SDRAMC)
•
•
•
•
•
•
•
— 11 bit row address (RA), 9 bit column address (CA), 2 bit bank address (BA), 16-bit bus,
one chip select
Supports up to 512 MByte of memory.
— 24/25 bits RA+CA, 2 bits BA, 32/16-bit bus, two chip selects
Supports page mode for decreased latency and higher bandwidth; remembers one active row for
each bank; four independent active rows per each chip select
Programmable refresh interval timer
Supports sleep mode and self-refresh mode
Error detect and parity check are not supported
The SDRAM controller does not include a dedicated I2C interface to access memory module
(DIMM) serial presence detect EEPROM. If needed, this must be managed by one of the on-chip
I2C channels external to the SDRAM controller.
Read clock recovery block
19.1.3
Terminology
The following terminology is used in this chapter:
• SDRAM block: Any group of DRAM memories selected by one of the SD_CS signals. Therefore,
the SDRAMC can support up to two independent memory blocks. The base address of each block
is programmed in the SDRAM chip-select configuration registers.
• SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit SDRAM
component might be configured as four 512K x 32 banks. Banks are selected through the
SD_BA[1:0] signals.
• SDRAM: RAMs that operate like asynchronous DRAMs but with a synchronous clock, a
pipelined, multiple-bank architecture, and a faster speed.
19.2
External Signal Description
This section introduces the signal names used in this chapter.
Table 19-1. SDRAM Interface—Detailed Signal Descriptions
Signal
I/O
Description
SD_A[13:0]
O
Memory multiplexed row/column address. Provides the row address for ACTV commands, and the column
address and auto-precharge bit for READ/WRITE commands, to select one location out of the memory array
in the respective bank. A10 is sampled during a precharge command to determine whether the precharge
applies to one bank (A10 negated) or all banks (A10 asserted). If only one bank is to be precharged, the
bank is selected by SD_BA[1:0].
The address outputs also provide the opcode during a MODE REGISTER SET command. SD_BA[1:0]
signals define which mode register is loaded during the MODE REGISTER SET (MRS). A12 is used on
device densities of 256 Mb and above.
Timing
Assertion/Negation — Occurs synchronously with SD_CLK
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
19-3
SDRAM Controller (SDRAMC)
Table 19-1. SDRAM Interface—Detailed Signal Descriptions (continued)
Signal
I/O
SD_BA[1:0]
O
Description
Memory bank address. Define which bank an ACTV, READ, WRITE, or PRECHARGE command is being
applied. It is also used to select the SDRAM internal mode register during power-up initialization.
Timing
SD_CAS
O
Assertion/Negation — Occurs synchronously with SD_CLK
Column address strobe/command input. Along with SD_CS, SD_RAS, and SD_WE, defines the current
command.
State
See Table 19-12 for the SDRAM commands.
Meaning
Timing
SD_RAS
O
Assertion/Negation — Occurs synchronously with SD_CLK
Row address strobe/command input. Along with SD_CS, SD_CAS, and SD_WE, defines the current
command.
State
See Table 19-12 for SDRAM commands.
Meaning
Timing
SD_CKE
O
Assertion/Negation — Occurs synchronously with SD_CLK.
Clock enable. SD_CKE must be maintained high throughout READ and WRITE accesses. SD_CKE negates
to put the SDRAM into low-power, self-refresh mode. Input buffers, excluding SD_CLK, SD_CLK, and
SD_CKE, are disabled during self-refresh.
State
Asserted — Activates internal clock signals and device input buffers and output drivers.
Meaning Negated —Deactivates internal clock signals and device input buffers and output drivers.
Timing
SD_CLK
SD_CLK
O
SD_CLK and SD_CLK are differential clock outputs. All address and control output signals are sent on the
crossing of the positive edge of SD_CLK and the negative edge of SD_CLK. Output data is referenced to
the crossing of SD_CLK and SD_CLK (both directions of crossing).
Timing
SD_CS[1:0]
O
Assertion — Asynchronous for self-refresh exit and for output disable
Negation — Occurs synchronously with SD_CLK
Command signals occur synchronously with the rising edge of this clock. Data signals can
change on the rising and falling edge of the clock.
SD_CS provides external bank selection on systems with multiple banks. SD_CS is considered part of the
command code.
State
Asserted — Commands for the selected chip occur
Meaning Negated — All commands are masked.
Timing
SD_DATA[31:0]
Assertion/Negation — Occurs synchronously with SD_CLK
I/O Data bus. In 16-bit DDR configuration, the memory device data bus is connected to SD_D[31:16] bits.
Timing
Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK.
High Impedance - Depending on the OE_RULE bit in SDCFG1, the SD_DATA bus can be in high
impedance until a write occurs or only when a read occurs.
MCF52277 Reference Manual, Rev 2
19-4
Freescale Semiconductor
SDRAM Controller (SDRAMC)
Table 19-1. SDRAM Interface—Detailed Signal Descriptions (continued)
Signal
I/O
Description
SD_DQM[3:0]
O
Output mask signal for write data. During reads, SD_DQM may be driven high, low, or floating. The address
correspondence:
SD_DQM3 - SD_D[31:24]
SD_DQM2 - SD_D[23:16]
SD_DQM1 - SD_D[15:8]
SD_DQM0 - SD_D[7:0]
State
Asserted — Data is written to SDRAM
Meaning Negation — Data is masked
Timing
SD_DQS[3:2]
Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK.
I/O Data strobes that indicate valid read/write data. (Edge-aligned with read data, centered with write data.)
The DQS frequency equals the memory clock frequency. Data is normally 1/4 memory clock period after a
DQS transition. For DDR operation, there is data following each DQS edge (rising and falling); for SDR
operation, valid data follows the rising edges only. The address correspondence:
SD_DQS3 - SD_D[31:24]
SD_DQS2 - SD_D[23:16]
Note: If a read is attempted from a DDR SDRAM chip select when there is no memory to respond with the
appropriate SD_DQS pulses, the bus cycle hangs. Because there is no high level bus monitor on the
device, a reset is the only way to exit this error condition.
State
Asserted — Similar to a clock signal, the edges are more important than being asserted or
Meaning
negated.
High impedance — Depending on the SDCFG1[OE_RULE] bit, the SD_DQS can be in high
impedance until a write is occurring or only when a read is occurring.
Timing
SD_WE
O
Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK.
Command input. Along with SD_CS, SD_CAS, and SD_RAS defines the current command.
State
Please see Table 19-12 for SDRAM commands.
Meaning
Timing
19.3
19.3.1
Assertion/Negation— Occurs synchronously with SD_CLK.
Interface Recommendations
Supported Memory Configurations
The SDRAM controller supports up to 14 row addresses and up to (13 in 16-bit bus mode) column
addresses. However, the maximum row and column addresses are not simultaneously supported. The
number of row and column addresses must be less than or equal to 24 (25 in 16-bit bus mode). In addition
to row/column address lines, there are always two row bank address bits. Therefore, the greatest possible
address space accessed using a single chip select is 226 x 32 bit (227 x 16 bit) or 256 MBytes.
Table 19-5 and Table 19-6 show the address multiplexing used by the memory controller for different
configurations. When the SDRAM controller receives the internal module enable, it latches the internal
bus address lines IA[27:0] (IA equals internal address) and multiplexes them into row, column, and bank
addresses (RA, CA, and BA respectfully). In 32-bit bus mode, IA[9:2] are used for CA[7:0]. In 16-bit
mode, IA[9:1] are used for CA[8:0]. IA[11:10] are always used for BA[1:0], and IA[23:12] are always
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
19-5
SDRAM Controller (SDRAMC)
used for RA[11:0]. IA[27:24] can be used for additional row or column address bits, as needed. The
additional row- or column-address bits are programmed via the SDCR[ADDR_MUX] bits.
NOTE
When the SDRAMC is configured to support an external 32-bit data bus. It
is not possible to connect a smaller device(s) to only part of the SDRAM’s
data bus. For example, if 16-bit wide devices are used, then user must use
two 16-bit devices connected as a 32-bit port.
Table 19-2. Address Multiplexing for 32-bit Bus Mode
Internal Address Bits [27:24]
SDCR[ADDR_MUX]
IA[27]
IA[26]
IA[25]
IA[24]
00
CA12
CA11
CA9
CA8
01
CA11
CA9
CA8
RA12
10
CA9
CA8
RA13
RA12
11
Reserved, do not use.
Table 19-3. SDRAM Address Multiplexing in 32-bit Bus Mode
Device
64 Mbits
Configuration
Row bit x SDCR
Col bit x [ADDR_
Banks
MUX]
Internal Address
27
26
25
24
2M x 32 bit
11 x 8 x 4
00
—1,2
—
—
—
4M x 16 bit
12 x 8 x 4
00
—
—
—
—
12 x 9 x 4
00
—
—
—
CA8
13 x 8 x 4
01
—
—
—
RA12
12 x 10 x 4
00
—
—
CA9
CA8
13 x 9 x 4
01
—
—
CA8
RA12
12 x 8 x 4
00
—
—
—
—
12 x 9 x 4
00
—
—
—
CA8
13 x 8 x 4
01
—
—
—
RA12
12 x 10 x 4
00
—
—
CA9
CA8
13 x 9 x 4
01
—
—
CA8
RA12
14 x 8 x 4
10
—
—
RA13
RA12
12 x 11 x 4
00
—
CA11
CA9
CA8
13 x 10 x 4
01
—
CA9
CA8
RA12
14 x 9 x 4
10
—
CA8
RA13
RA12
8M x 8 bit
23–12
11–10
9–2
RA11-0 BA1-0
CA7-0
RA11-0 BA1-0
CA7-0
16M x 4 bit
4M x 32 bit
8M x 16 bit
128 Mbits
16M x 8 bit
32M x 4 bit
MCF52277 Reference Manual, Rev 2
19-6
Freescale Semiconductor
SDRAM Controller (SDRAMC)
Table 19-3. SDRAM Address Multiplexing in 32-bit Bus Mode (continued)
Device
Configuration
Row bit x SDCR
Col bit x [ADDR_
Banks
MUX]
Internal Address
27
26
25
24
12 x 9 x 4
00
—
—
—
CA8
13 x 8 x 4
01
—
—
—
RA12
12 x 10 x 4
00
—
—
CA9
CA8
13 x 9 x 4
01
—
—
CA8
RA12
14 x 8 x 4
10
—
—
RA13
RA12
12 x 11 x 4
00
—
CA11
CA9
CA8
13 x 10 x 4
01
—
CA9
CA8
RA12
14 x 9 x 4
10
—
CA8
RA13
RA12
12 x 12 x 4
00
CA12
CA11
CA9
CA8
13 x 11 x 4
01
CA11
CA9
CA8
RA12
14 x 10 x 4
10
CA9
CA8
RA13
RA12
12 x 10 x 4
00
—
—
CA9
CA8
13 x 9 x 4
01
—
—
CA8
RA12
14 x 8 x 4
10
—
—
RA13
RA12
12 x 11 x 4
00
—
CA11
CA9
CA8
13 x 10 x 4
01
—
CA9
CA8
RA12
14 x 9 x 4
10
—
CA8
RA13
RA12
12 x 12 x 4
00
CA12
CA11
CA9
CA8
13 x 11 x 4
01
CA11
CA9
CA8
RA12
14 x 10 x 4
10
CA9
CA8
RA13
RA12
12 x 11 x 4
00
—
CA11
CA9
CA8
13 x 10 x 4
01
—
CA9
CA8
RA12
14 x 9 x 4
10
—
CA8
RA13
RA12
12 x 12 x 4
00
CA12
CA11
CA9
CA8
13 x 11 x 4
01
CA11
CA9
CA8
RA12
14 x 10 x 4
10
CA9
CA8
RA13
RA12
12 x 12 x 4
00
CA12
CA11
CA9
CA8
13 x 11 x 4
01
CA11
CA9
CA8
RA12
14 x 10 x 4
10
CA9
CA8
RA13
RA12
23–12
11–10
9–2
8M x 32 bit
16M x 16 bit
256 Mbits
32M x 8 bit
64M x 4 bit
16M x 32 bit
512 Mbits
32 M x 16 bit
64M x 8 bit
32M x 32 bit
1 Gbits
64M x 16 bit
2 Gbits
1
2
64M x 32 bit
RA11-0 BA1-0
CA7-0
RA11-0 BA1-0
CA7-0
RA11-0 BA1-0
CA7-0
RA11-0 BA1-0
CA7-0
All SD_A[13:0] bits are generated on every access, but only the bits actually used by the memory are shown.
All column address (CA) bits in this table are physical column address lines. The SDRAM controller inserts an
extra bit CA10 to control the precharge option.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
19-7
SDRAM Controller (SDRAMC)
Table 19-4. Address Multiplexing for 16-bit Bus Mode
Internal Address Bits [27:24]
SDCR[ADDR_MUX]
IA[27]
IA[26]
IA[25]
IA[24]
00
CA13
CA12
CA11
CA9
01
CA12
CA11
CA9
RA12
10
CA11
CA9
RA13
RA12
11
Reserved. Do Not Use.
Table 19-5. SDRAM-Address Multiplexing in 16-bit Bus Mode
Device
Configuration
Row bit x SDCR
Col bit x [ADDR_
Banks
MUX]
Internal Address
27
26
25
24
4M x 16 bit
11 x 9 x 4
00
—1,2
—
—
—
8M x 8 bit
12 x 9 x 4
00
—
—
—
—
12 x 10 x 4
00
—
—
—
CA9
13 x 9 x 4
01
—
—
—
RA12
12 x 9 x 4
00
—
—
—
—
12 x 10 x 4
00
—
—
—
CA9
13 x 9 x 4
01
—
—
—
RA12
12 x 11 x 4
00
—
—
CA11
CA9
13 x 10 x 4
01
—
—
CA9
RA12
14 x 9 x 4
10
—
—
RA13
RA12
12 x 10 x 4
00
—
—
—
CA9
13 x 9 x 4
01
—
—
—
RA12
12 x 11 x 4
00
—
—
CA11
CA9
13 x 10 x 4
01
—
—
CA9
RA12
14 x 9 x 4
10
—
—
RA13
RA12
12 x 12 x 4
00
—
CA12
CA11
CA9
13 x 11 x 4
01
—
CA11
CA9
RA12
14 x 10 x 4
10
—
CA9
RA13
RA12
64 Mbits
23 – 12 11 – 10
9–1
RA11-0 BA1-0
CA8-0
RA11-0 BA1-0
CA8-0
RA11-0 BA1-0
CA8-0
16M x 4 bit
8M x 16 bit
16M x 8 bit
128 Mbits
32M x 4 bit
16M x 16 bit
32M x 8 bit
256 Mbits
64M x 4 bit
MCF52277 Reference Manual, Rev 2
19-8
Freescale Semiconductor
SDRAM Controller (SDRAMC)
Table 19-5. SDRAM-Address Multiplexing in 16-bit Bus Mode (continued)
Device
Configuration
32 M x 16 bit
Row bit x SDCR
Col bit x [ADDR_
Banks
MUX]
Internal Address
27
26
25
24
12 x 11 x 4
00
—
—
CA11
CA9
13 x 10 x 4
01
—
—
CA9
RA12
14 x 9 x 4
10
—
—
RA13
RA12
12 x 12 x 4
00
—
CA12
CA11
CA9
13 x 11 x 4
01
—
CA11
CA9
RA12
14 x 10 x 4
10
—
CA9
RA13
RA12
12 x 12 x 4
00
—
CA12
CA11
CA9
13 x 11 x 4
01
—
CA11
CA9
RA12
14 x 10 x 4
10
—
CA9
RA13
RA12
12 x 13 x 4
00
CA13
CA12
CA11
CA9
13 x 12 x 4
01
CA12
CA11
CA9
RA12
14 x 11 x 4
10
CA11
CA9
RA13
RA12
512 Mbits
64M x 8bit
1 Gbits
2 Gbits
1
2
64M x 16bit
128M x16bit
23 – 12 11 – 10
9–1
RA11-0 BA1-0
CA8-0
RA11-0 BA1-0
CA8-0
RA11-0 BA1-0
CA8-0
All SD_A[13:0] bits are generated on every access, but only the bits actually used by the memory are shown.
All column address (CA) bits in this table are physical column address lines. The SDRAM controller inserts an
extra bit CA10 to control the precharge option.
All memory devices of a single chip-select block must have the same configuration and row/column
address width; however, this is not necessary between different blocks. If mixing different memory
organizations in different blocks, the following guidelines ensure that every block is fully contiguous.
For 32-bit data bus configuration:
• If all devices’ row address width is 12 bits, the column address can be ≥ 8 bits.
• If all devices’ row address width is 13 bits, the column address can be ≥ 8 bits.
• If all devices’ column address width is 8 bits, the row address can be ≥ 11 bits.
• The maximum row bits plus column bits equals 24.
• x8 and x16 data width memory devices can be mixed (but not in the same space).
• x32 data width memory devices cannot be mixed with any other width.
For 16-bit data bus configuration:
• If all devices’ row address width is 12 bits, the column address can be ≥ 9 bits.
• If all devices’ row address width is 13 bits, the column address can be ≥ 9 bits.
• If all devices’ column address width is 9 bits, the row address can be ≥ 11 bits.
• The maximum row bits plus column bits equals 25.
• x16 data width memory devices cannot be mixed with any other width.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
19-9
SDRAM Controller (SDRAMC)
19.3.2
SDRAM SDR Connections
Figure 19-2 shows a block diagram using 32-bit wide SDR SDRAM (such as Micron MT48LC4M32B2)
and flash (such as Spansion AM29LV160D). SDR design requires special timing consideration for the
SD_DQS[3:2] signals. For reads from DDR SDRAMs, the memory drives the DQS pins so that the data
lines and DQS signals have concurrent edges. The SDRAMC is designed to latch data 1/4 clock after the
SD_DQS[3:2] edge. For DDR SDRAM, this ensures that the latch time is in the middle of the data valid
window.
The SDRAMC also uses the SD_DQS[3:2] signals to determine when read data can be latched for SDR
SDRAM; however, SDR memories do not provide DQS outputs. Instead the SDRAMC provides a
SD_SDRDQS output routed back into the controller as SD_DQS[3:2]. The SD_SDRDQS signal should
be routed such that the valid data from the SDRAM reaches the controller at the same time or before the
SD_SDRDQS reaches the SD_DQS[3:2] inputs.
When routing SD_SDRDQS the outbound trace length should be matched to the SD_CLK trace length.
This aligns SD_SDRDQS to the SD_CLK as if the memory had generated the DQS pulse. The inbound
trace should be routed along the data path, which should synchronize the SD_DQS so that the data is
latched in the middle of the data valid window.
MCF52277 Reference Manual, Rev 2
19-10
Freescale Semiconductor
SDRAM Controller (SDRAMC)
SDRAM Control Signals
SDRAM Controller
3.3V SDR SDRAM
SD_CLK
SD_CKE
CLK
CKE
CS
RAS
SD_CS0
SD_RAS
SD_CAS
SDWE
SD_A10
SD_SDR_DQS
CAS
WE
A10/AP
Delay
SD_DQS[3:2]
SD_DQM[3:0]
DQM[3:0]
A[15:14]
BA[1:0]
SD_A[23:0]
A[13:11,9:0]
SD_D[31:0]
A[13:11,9:0]
D[31:0]
FlexBus Control Signals
3.3V Flash
A[23:2]
R/W
OE
FB_CS0
A[21:0]
D[31:0]
WE
OE
CE
Figure 19-2. Example 3.3V, 32-bit SDR SDRAM System
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
19-11
SDRAM Controller (SDRAMC)
19.3.3
SDRAM DDR Component Connections
Figure 19-3 shows a block diagram using 16-bit wide DDR SDRAM (such as Micron MT46V8M16) and
flash (such as Spansion AM29DBB160G).
SDRAM Controller
2.5V DDR SDRAM
SDRAM Control Signals
SD_CLK
SD_CLK
SD_CKE
CLK
CLK
CKE
CS
RAS
SD_CS0
SD_RAS
SD_CAS
SDWE
SD_A10
CAS
WE
A10/AP
SD_DQS[3:2]
DQS[1:0]
BE/BWE/DQM[3:2]
DQM[3:2]
A[15:14]
BA[1:0]
SD_A[23:0]
A[13:11,9:0]
A[13:11,9:0]
SD_D[31:16]
D[15:0]
1.25V
VREF
FlexBus Control Signals
2.5V Flash
A[23:1]
FB_D[15:0]
FB_R/W
FB_OE
FB_CS0
A[22:0]
D[15:0]
WE
OE
CE
Figure 19-3. Example 2.5V, 16-bit DDR SDRAM System
19.3.4
DDR SDRAM Layout Considerations
Due to the critical timing for DDR SDRAM, a number of considerations should be taken into account
during PCB layout:
• Minimize overall trace lengths.
MCF52277 Reference Manual, Rev 2
19-12
Freescale Semiconductor
SDRAM Controller (SDRAMC)
•
•
•
•
•
•
•
•
•
•
•
•
•
Each DQS, DM, and DQ group must have identical loading and similar routing to maintain timing
integrity.
The loading and routing of SD_DQS must match those of SD_D.
Control and clock signals are routed point-to-point.
Trace length for clock, address, and command signals should match.
Route DDR signals on layers adjacent to the ground plane.
Use a VREF plane under the SDRAM.
VREF is decoupled from SDVDD and VSS.
To avoid crosstalk, address and command signals must remain separate from data and data strobes.
Use different resistor packs for command/address and data/data strobes.
Series termination should be used to help match output driver impedance to trace impedance.
(Driver impedance is affected by drive strength.) Typically, a 50 Ω system with a 22 Ω series
resistor is a good starting point, but this should be analyzed based on actual board design and
loading.
Series termination should be between the processor and memory, but closest to the processor.
The SD_CLK and SD_CLK signals can be terminated with a single termination resistor between
the two clock phases. A 100 – 120 Ω resistor produces effective termination for the differential
SD_CLK. Placement of the terminator should be physically close to the input receiver on the
SDRAM(s).
If using a SDRAM DIMM, such as a 144-pin DDR2 SO-DIMM, termination on the CLK lines is
not recommended, as clock line termination is already populated on the DIMM module. Additional
termination on the motherboard (main board) may cause undersired effects.
0.1 μF decoupling for every termination resistor pack.
NOTE
Only series termination is supported on this device, which is different than
typical DDR designs.
19.3.4.1
Termination Example
Figure 19-4 shows the recommended termination circuitry for DDR SDRAM signals.
Processor
Address, Data
and Control
22 Ω
DDR SDRAM
Note: Place series resistors as close
as possible to the processor
SD_CLK
Address, Data
and Control
CLK
100 Ω
Note: Place 100 Ω resistor as
close as possible to the
DDR’s clock receiver
SD_CLK
CLK
Figure 19-4. DDR SDRAM Termination Circuit
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
19-13
SDRAM Controller (SDRAMC)
19.4
Memory Map/Register Definition
The SDRAM controller and its associated logic contain two sets of programming registers:
• SDRAM controller’s control and configuration registers
• Chip-select configuration control registers
NOTE
The slew rate for the SDRAM pins is controlled by a register in the pin
multiplexing and control module. See Section 14.3.7, “SDRAM Mode
Select Control Register (MSCR_SDRAM),” for more details.
Table 19-6 shows the SDRAM controller control and configuration registers. Unspecified memory spaces
are reserved for future use. Access to reserved space is prohibited. It is recommended to write 0 to reserved
space. Reads from a write-only bit return 0.
Table 19-6. SDRAMC Memory Map
Width
(bits)
Access
Reset Value
Section/Page
0xFC0B_8000 SDRAM Mode/Extended Mode Register (SDMR)
32
R/W
0x0000_0000
19.4.1/19-14
0xFC0B_8004 SDRAM Control Register (SDCR)
32
R/W
0x0000_0000
19.4.2/19-15
0xFC0B_8008 SDRAM Configuration Register 1 (SDCFG1)
32
R/W
0x0000_0000
19.4.3/19-17
0xFC0B_800C SDRAM Configuration Register 2 (SDCFG2)
32
R/W
0x0000_0000
19.4.4/19-19
0xFC0B_8110 SDRAM Chip Select 0 Configuration (SDCS0)
32
R/W
0x0000_0000
19.4.5/19-20
0xFC0B_8114 SDRAM Chip Select 1 Configuration (SDCS1)
32
R/W
0x0000_0000
19.4.5/19-20
Address
Register
19.4.1
SDRAM Mode/Extended Mode Register (SDMR)
The SDMR (Figure 19-5) writes to the mode and extended mode registers physically residing within the
SDRAM chips. These registers must be programmed during SDRAM initialization. See Section 19.6,
“Initialization/Application Information” for more information on the initialization sequence.
Address: 0xFC0B_8000 (SDMR)
R
W
Access: SDCR[MODE_EN] = 0 User read-only
SDCR[MODE_EN] = 1 User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
16
15 14 13 12 11 10 9
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BK
AD
8
7
6
5
4
3
2
1
0
CMD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-5. SDRAM-Mode/Extended-Mode Register (SDMR)
MCF52277 Reference Manual, Rev 2
19-14
Freescale Semiconductor
SDRAM Controller (SDRAMC)
Table 19-7. SDMR Field Descriptions
Field
Description
31–30
BK
Bank address. Driven onto SD_BA[1:0] along with a LMR/LEMR command. All SDRAM chip selects are asserted
simultaneously. SDCR[CKE] must be set before attempting to generate an LMR/LEMR command. The SD_BA[1:0]
value is used to select between LMR and LEMR commands.
00 Load mode register command (LMR)
01 Load extended mode register command (LEMR) for non-mobile DDR devices
10 Load extended mode register command (LEMR) for mobile DDR devices
11 Reserved
29–18
AD
Address. Driven onto SD_A[11:0] along with an LMR/LEMR command. The AD value is stored as the mode (or
extended mode) register data.
17
Reserved, must be cleared.
16
CMD
Command. This bit is write-only and always returns a 0 when read.
1 Generate an LMR/LEMR command
0 Do not generate any command
15–0
Reserved, must be cleared.
19.4.2
SDRAM Control Register (SDCR)
The SDCR (Figure 19-6) controls SDRAMC operating modes, including refresh count and address line
muxing.
Address: 0xFC0B_8004 (SDCR)
31
30
29
Access: User read/write
28
R MODE
DDR_ REF_
CKE
MODE EN
W _EN
Reset
R
0
0
15
0
0
26
0
0
0
0
0
0
14
13
12
11
10
0
MEM_
PS
0
0
0
0
W
Reset
27
DQS_OE
0
0
25
24
ADDR_MUX
0
0
23
22
0
OE_
RULE
0
0
21
20
19
18
17
16
0
0
REF_CNT
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IREF IPALL
0
0
0
Figure 19-6. SDRAM Control Register (SDCR)
Table 19-8. SDCR Field Descriptions
Field
31
MODE_EN
30
CKE
Description
SDRAM mode register programming enable.
0 SDMR locked, cannot be written.
1 SDMR enabled, can be written.
Note: MODE_EN must be cleared during normal operation,
Clock enable. CKE must be set to perform normal read and write operations. Clear CKE to put the memory in
self-refresh or power-down mode.
0 SD_CKE is negated (low)
1 SD_CKE is asserted (high)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
19-15
SDRAM Controller (SDRAMC)
Table 19-8. SDCR Field Descriptions (continued)
Field
Description
29
DDR mode select.
DDR_MODE 0 SDR mode
1 DDR mode
28
REF_EN
27–26
25–24
ADDR_MUX
23
Refresh enable.
0 Automatic refresh disabled
1 Automatic refresh enabled
Reserved, must be cleared.
Controls the use of internal address bits A[27:24] as row or column bits on the SD_A bus. See Table 19-4, and
Table 19-5.
Reserved, must be cleared.
22
OE_RULE
Drive rule selection.
0 Tri-state except to write. SD_D and SD_DQS are only driven when necessary to perform a write command.
1 Drive except to read. SD_D and SD_DQS are only tristated when necessary to perform a read command.
When not being driven for a write cycle, SD_D hold the most recent value and SD_DQS are driven low. This
mode is intended for minimal applications only, to prevent floating signals and allow unterminated board
traces. However, terminated wiring is always recommended over unterminated.
21–16
REF_CNT
The average periodic interval at which the controller generates refresh commands to memory; measured in
increments of 64 × SD_CLK period.
REF_CNT = (tREFI/ (tCK × 64)) - 1, rounded down to the next integer value.
If the SDRAM data sheet does not define tREFI, it can be calculated by tREFI = tREF / #rows.
15–14
13
MEM_PS
12
11–10
DQS_OE
Reserved, must be cleared.
Memory data port size.
0 32-bit data bus
1 16-bit data bus
Reserved, must be cleared.
DQS output enable. Each bit of the DQS_OE field is a master enable for the corresponding SD_DQSn signal.
DQS_OE[1] (SDCR[11]) enables SD_DQS3 and DQS_OE[0] (SDCR[10]) enables SD_DQS2.
0 SD_DQSn can never drive. Use this value in SDR mode or in DDR mode with a single DQS memory. Some
32-bit DDR devices have only a single DQS pin. Enable one of the SD_DQSn signals and disable the other.
Then, short both pins external to the device.
1 SD_DQSn can drive as necessary, depending on commands and SDCR[OE_RULE] setting. DDR only.
9–3
Reserved, must be cleared.
MCF52277 Reference Manual, Rev 2
19-16
Freescale Semiconductor
SDRAM Controller (SDRAMC)
Table 19-8. SDCR Field Descriptions (continued)
Field
Description
2
IREF
Initiate refresh command. Used to force a software-initiated refresh command. This bit is write-only, reads return
zero.
0 Do not generate a refresh command.
1 Generate a refresh command. All SD_CSn signals are asserted simultaneously. SDCR[CKE] must be set
before attempting to generate a software refresh command.
Note: A software requested refresh is completely independent of the periodic refresh interval counter. Software
refresh is only possible when MODE_EN is set.
1
IPALL
Initiate precharge all command. Used to force a software-initiated precharge all command. This bit is write-only,
reads return zero.
0 Do not generate a precharge command.
1 Generate a precharge all command. All SD_CSn signals are asserted simultaneously. SDCR[CKE] must be
set before generating a software precharge command.
Note: Software precharge is only possible when MODE_EN is set.
Note: Do not set IREF and IPALL at the same time.
19.4.3
SDRAM Configuration Register 1 (SDCFG1)
The 32-bit read/write SDRAM configuration register 1 (SDCFG1) stores necessary delay values between
specific SDRAM commands. During initialization, software loads values to the register according to the
selected SD_CLK frequency and SDRAM information obtained from the data sheet. This register resets
only by a power-up reset signal.
The read and write latency fields govern the relative timing of commands and data and must be exact
values. All other fields govern the relative timing from one command to another; they have minimum
values, but any larger value is also legal (but with decreased performance).
The minimum values of certain fields can be different for SDR, DDR SDRAM, even if the data sheet
timing is the same, because:
• In SDR mode, the memory controller counts the delay in SD_CLK
• In DDR mode, the memory controller counts the delay in 2 x SD_CLK (also referred to as
SD_CLK2)
• SD_CLK—memory controller clock—is the speed of the SDRAM interface and is equal to the
internal bus clock.
• SD_CLK2—double frequency of SD_CLK—DDR uses both edges of the bus-frequency clock
(SD_CLK) to read/write data
NOTE
In all calculations for setting the fields of this register, convert time units to
clock units and round up to the nearest integer.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
19-17
SDRAM Controller (SDRAMC)
Address: 0xFC0B_8008 (SDCFG1)
31
R
R
28
27
26
0
25
24
0
0
0
0
0
0
15
14
13
12
11
10
9
8
PRE2ACT
0
0
0
0
0
0
21
20
0
0
0
0
7
6
5
4
0
WT_LAT
0
0
19
18
0
0
0
REF2ACT
0
22
RD_LAT
0
0
23
SWT2RWP
0
W
Reset
29
SRD2RWP
W
Reset
30
Access: User read/write
0
0
17
16
ACT2RW
0
0
0
3
2
1
0
0
0
0
0
0
0
0
0
Figure 19-7. SDRAM Configuration Register 1 (SDCFG1)
Table 19-9. SDCFG1 Field Descriptions
Field
Description
31–28
Single read to read/write/precharge delay. Limiting case is read to write.
SRD2RWP SDR: SRD2RWP = CL + tHZ + 2
DDR: SRD2RWP = CL + 1
tHZ is the time the data bus uses to return to hi-impedance after a read and is found in the SDRAM device
specifications.
Note: Count value is in SD_CLK periods for SDR and DDR mode.
27
Reserved, must be cleared.
26–24
Single write to read/write/precharge delay. Limiting case is write to precharge.
SWT2RWP SDR: SWT2RWP = tWR
DDR: SWT2RWP = tWR + 1
Note: Count value is in SD_CLK periods for SDR and DDR mode.
23–20
RD_LAT
Read CAS Latency. Read command to read data available delay counter.
For DDR:
If CL = 2, write 0x6
If CL = 2.5, write 0x7
For SDR:
If CL = 2, write 0x2
If CL = 3, write 0x3
Note: The recommended values are just a starting point and may need to be adjusted depending on the trace
length for the data and DQS lines.
CL = 2.5 is not supported for SDR.
SDR: Count value is in SD_CLK periods.
DDR: Count value is in SD_CLK2 periods.
19
18–16
ACT2RW
Reserved, must be cleared.
Active to read/write delay. Active command to any following read- or write-delay counter.
Suggested value = (tRCD × fSD_CLK) - 1 (Round up to nearest integer)
Example:
If tRCD = 20ns and fSD_CLK = 99 MHz
Suggested value = (20ns × 99 MHz) - 1= 0.98; round to 1.
Note: Count value is in SD_CLK periods for SDR and DDR modes.
MCF52277 Reference Manual, Rev 2
19-18
Freescale Semiconductor
SDRAM Controller (SDRAMC)
Table 19-9. SDCFG1 Field Descriptions (continued)
Field
Description
15
Reserved, must be cleared.
14–12
Precharge to active delay. Precharge command to following active command delay counter.
PRE2ACT
Suggested value = (tRP × fSD_CLK) - 1 (Round up to nearest integer)
Example:
If tRP = 20ns and fSD_CLK = 99 MHz
Suggested value = (20ns × 99 MHz) - 1 = 0.98; round to 1.
Note: Count value is in SD_CLK periods for SDR and DDR modes.
11–8
Refresh to active delay. Refresh command to following active or refresh command delay counter.
REF2ACT
SDR/DDR: REF2ACT = (tRFC × fSD_CLK) - 1 (Round up to nearest integer)
Example (for SDR/DDR):
If tRFC = 75ns and fSD_CLK = 99 MHz
Suggested value = (75ns × 99 MHz) - 1 = 6.425; round to 7.
Note: Count value is in SD_CLK periods for SDR and DDR modes.
7
Reserved, must be cleared.
6–4
WT_LAT
Write latency. Write command to write data delay counter.
SDR: write 0x0
DDR: write 0x3
Note: SDR mode: Count value is in SD_CLK periods.
DDR mode: Count value is in SD_CLK2 periods.
3–0
19.4.4
Reserved, must be cleared.
SDRAM Configuration Register 2 (SDCFG2)
The 32-bit read/write configuration register 2 stores delay values necessary between specific SDRAM
commands. During initialization, software loads values to the register according to the SDRAM
information obtained from the data sheet. This register is reset only by a power-up reset signal.
The burst length (BL) field must be exact. All other fields govern the relative timing from one command
to another, they have minimum values but any larger value is also legal (but with decreased performance).
All delays in this register are expressed in SD_CLK. In all calculations for setting the fields of this register,
convert time units to clock units and round up to the nearest integer.
Address: 0xFC0B_800C (SCFG2)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
BRD2RP
BWT2RWP
BRD2W
BL
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-8. SDRAM Configuration Register 2 (SDCFG2)
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Freescale Semiconductor
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SDRAM Controller (SDRAMC)
Table 19-10. SDCFG2 Field Descriptions
Field
31–28
BRD2RP
Description
Burst read to read/precharge delay. Limiting case is read to read.
SDR: BRD2RP = BurstLength + 1
DDR: BRD2RP = BurstLength/2 + 1
27–24
Burst write to read/write/precharge delay. Limiting case is write to precharge.
BWT2RWP SDR: BWT2RWP = BurstLength + tWR - 2
DDR: BWT2RWP = BurstLength/2 + tWR
23–20
BRD2W
19–16
BL
Burst read to write delay.
SDR: BRD2W = CL + BurstLength + tHZ
DDR: BRD2W = CL + BurstLength/2 - 1
Burst length.
BL = BurstLength - 1
Note: Burst length depends on port sizeIf 32-bit bus (SDCR[MEM_PS] = 0), burst length is 4. Write BL = 3.. If
16-bit bus (SDCR[MEM_PS] = 1), burst length is 8. Write BL = 7.
15–0
19.4.5
Reserved, must be cleared.
SDRAM Chip Select Configuration Registers (SDCSn)
These registers define base address and space size of each chip select.
NOTE
Because the SDRAM module is one of the slaves connected to the crossbar
switch, it is only accessible within a certain memory range. The only
applicable address ranges for which the chip-selects can be active are
0x4000_0000 – 0x7FFF_FFFF. Be sure to set the SDCSn registers
appropriately.
NOTE
The user should not probe memory on a DDR chip select to determine if
memory is connected. If a read is attempted from a DDR SDRAM chip
select when there is no memory to respond with the appropriate DQS pulses,
the bus cycle hangs. Because no high level bus monitor exists on the device,
a reset is the only way to exit the error condition.
Address: 0xFC0B_8110 (SDCS0)
0xFC0B_8114 (SDCS1)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
CSBA
9
8
7
6
5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4
3
2
1
0
CSSZ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-9. SRAM Chip Select Configuration Register (SDCSn)
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SDRAM Controller (SDRAMC)
Table 19-11. SDCSn Field Descriptions
Field
Description
31–20
CSBA
Chip-select base address. Because the SDRAM module is one of the slaves connected to the crossbar switch, it is
only accessible within a certain memory range. The only applicable address ranges for which the chip-selects can
be active are 0x4000_0000 – 0x7FFF_FFFF. Therefore, the possible range for this field is 0x400 – 0x7FF.
19–5
Reserved, must be cleared.
4–0
CSSZ
Chip select size.
CSSZ
Size
Address Lines
to Compare
CSSZ
Size
Address Lines
to Compare
00000
Disabled
—
11000
32 MByte
A[31:25]
00001–10001
Reserved
Reserved
11001
64 MByte
A[31:26]
10010
Reserved
Reserved
11010
128 MByte
A[31:27]
10011
1 MByte
A[31:20]
11011
256 MByte
A[31:28]
10100
2 MByte
A[31:21]
11100
512 MByte
A[31:29]
10101
4 MByte
A[31:22]
11101
1 GByte
A[31:30]
10110
8 MByte
A[31:23]
11110
2 GByte
A31
10111
16 MByte
A[31:24]
11111
4 GByte
Ignore A[31:20]
Any chip-select can be enabled or disabled, independent of others. Any chip-select can be allocated any
size of address space from 1M to 4G, independent of others. Any chip-select address space can begin at
any size-aligned base address, independent of others.
For contiguous memory with different sizes of memory blocks, place largest block at the lowest address
and place smaller blocks in descending size order at ascending base addresses.
For example, assume a system with 2 chip selects: CS0=16M, CS1=256M:
CS0CFG = 0x4F000017 = enable 16M @ 0x4F000000-0x4FFFFFFF
CS1CFG = 0x5000001B = enable 256M @ 0x50000000-0x5FFFFFFF
This gives 272 MB total memory, at 0x4F000000-0x5FFFFFFF.
19.5
19.5.1
Functional Description
SDRAM Commands
When an internal bus master accesses SDRAM address space, the memory controller generates the
corresponding SDRAM command. Table 19-12 lists SDRAM commands supported by the memory
controller.
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Freescale Semiconductor
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SDRAM Controller (SDRAMC)
Table 19-12. SDRAM Commands
Function
Symbol
CKE
CS
RAS
CAS
WE
BA[1:0]
A[10]
Other A
Command Inhibit
INH
H
H
X
X
X
X
X
X
No Operation
NOP
H
L
H
H
H
X
X
X
Row and Bank Active
ACTV
H
L
L
H
H
V
V
V
Read
READ
H
L
H
L
H
V
L
V
Write
WRITE
H
L
H
L
L
V
L
V
Burst Terminate (SDR/DDR only)
BST
H
L
H
H
L
X
X
X
Precharge All Banks
PALL
H
L
L
H
L
X
H
X
Precharge Selected Bank
PRE
H
L
L
H
L
V
L
X
Load Mode Register
LMR
H
L
L
L
L
LL
V
V
Load Extended Mode Register
LEMR
H
L
L
L
L
LH
V
V
Auto Refresh
REF
H
L
L
L
H
X
X
X
Self Refresh
SREF
H→L
L
L
L
H
X
X
X
Power Down
PDWN
H→L
H
X
X
X
X
X
X
H = High
L = Low
V = Valid
X = Don’t care
Many commands require a delay before the next command may be issued; sometimes the delay depends
on the type of the next command. These delay requirements are managed by the values programmed in the
memory controller configuration registers (SDCFG1, SDCFG2).
19.5.1.1
Row and Bank Active Command (ACTV)
The ACTV command is responsible for latching the row and bank address and activating the specified row
bank of a memory block. After the row is activated, it can be accessed using subsequent read and write
commands.
NOTE
The SDRAMC supports one active row for each chip select block. See
Section 19.6.4, “Page Management,” for more information.
19.5.1.2
Read Command (READ)
When the SDRAMC receives a read request via the internal bus, it first checks the row and bank of the
new access. If the address falls within the active row of an active bank, it is a page hit, and the read is issued
as soon as possible (pending any delays required by previous commands). If the address is within an
inactive bank, the memory controller issues an ACTV followed by the read command. If the address is not
within the active row of an active bank, the memory controller issues a pre command to close the active
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SDRAM Controller (SDRAMC)
row. Then, the SDRAMC issues ACTV to activate the necessary row and bank for the new access,
followed by the read to the SDRAM.
The PALL/PRE and ACTV commands (if necessary) can sometimes be issued in parallel with an on-going
data movement.
To truncate a burst read when only a single read is needed, the memory controller issues the
burst-terminate command. With SDR memory, the data masks are negated throughout the entire read size.
With DDR memory, the data masks are asserted high throughout the entire read size; but DDR memory
ignores the data masks during reads.
19.5.1.3
Write Command (WRITE)
When the memory controller receives a write request via the internal bus, it first checks the row and bank
of the new access. If the address falls within the active row of an active bank, it is a page hit, and the WRITE
is issued as soon as possible (pending any delays required by previous commands). If the address is within
the inactive bank, the memory controller issues an ACTV followed by the write command. If the address
is not within the active row of an active bank, the memory controller issues a PRE command to close the
active row. Then, the SDRAMC issues ACTV to activate the necessary row and bank for the new access,
followed by the WRITE command to the SDRAM.
The PALL/PRE and ACTV commands (if necessary) can sometimes be issued in parallel with an on-going
data movement.
In SDR mode, the memory controller issues the burst terminate command to truncate burst write for a
single write. This is not the case for DDR system. With SDR and DDR memory, a read command can be
issued overlapping the masked beats at the end of a previous single write of the case CS; the read command
aborts the remaining (unnecessary) write beats.
19.5.1.4
Burst-Terminate Command (BST)
SDRAMs are burst-only devices, but provide mechanisms to truncate a burst if all of the beats are not
needed. The burst-terminate command truncates read bursts (SDR and DDR) and write bursts (SDR). To
truncate a burst write for DDR, the read command can abort the remaining unnecessary write beats. This
method also works when in SDR mode. The most recently registered read or write command prior to the
burst terminate command is truncated. The active page remains open.
19.5.1.5
Precharge-All-Banks (PALL) and Selected-Bank (PRE) Commands
The precharge command puts SDRAM into an idle state. The SDRAM must be in this idle state before a
REF, LMR, LEMR, or ACTV command to open a new row within a particular bank can be issued.
The memory controller issues the precharge command only when necessary for one of these conditions:
• Access to a new row
• Refresh interval elapsed
• Software commanded precharge during device initialization
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SDRAM Controller (SDRAMC)
NOTE
A precharge is required after DRAMs also have a maximum bank-open
period. The memory controller does not time the bank-open period because
the refresh interval is always less.
19.5.1.6
Load Mode/Extended Mode Register Command (LMR, LEMR)
All SDRAM devices contain mode registers that configure the timing and burst mode for the SDRAM.
These commands access the mode registers that physically reside within the SDRAM devices. During the
LMR or LEMR command, SDRAM latches the address and bank buses to load the values into the selected
mode register.
NOTE
The LMR and LEMR commands are only used during SDRAM initialization.
Use the following steps to write the mode register and extended mode register:
1. Set the SDCR[MODE_EN] bit.
2. Write the SDMR[BA] bits to select the mode register.
3. Write the desired mode register value to the SDMR[ADDR]. Do not overwrite the SDMR[BA]
values. This step can be performed in the same register write in step 2.
4. Set the SDMR[CMD] bit.
5. For DDR, perform steps 2–4 more than once to write the extended-mode register and the mode
register.
6. Clear the SDCR[MODE_EN] bit.
19.5.1.6.1
Mode Register Definition
Figure 19-10 shows a typical mode register definition. This is the SDRAM’s mode register, not the
SDRAMC’s mode/extended mode register (SDMR) defined in Section 19.4.1, “SDRAM Mode/Extended
Mode Register (SDMR).” Refer to the SDRAM manufacturer’s device data sheet to confirm correct
settings.
Field
BA1
BA0
0
0
A11
A10
A9
A8
A7
A6
OP_MODE
A5
A4
CL
A3
BT
A2
A1
A0
BLEN
Figure 19-10. Typical Mode Register
Table 19-13. Mode Register Field Descriptions
Field
BA1–BA0
Description
Bank address. These must be zero to select the mode register.
A11–A7 Operating mode.
OP_MODE xx000 Standard Operation (SDR only)
00000 Normal Operation (DDR)
00010 Reset DLL (DDR)
Else Reserved
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SDRAM Controller (SDRAMC)
Table 19-13. Mode Register Field Descriptions (continued)
Field
Description
A6–A4
CL
CAS latency. Delay in clocks from issuing a READ to valid data out. Check the SDRAM manufacturer’s spec because
the CL settings supported can vary from memory to memory.
A3
BT
A2–A0
BLEN
Burst type.
0 Sequential
1 Interleaved. This setting should not be used because the SDRAMC does not support interleaved bursts.
Burst length. Determines the number of column locations that are accessed for a given READ or WRITE command.
000 One. This setting is not valid for DDR.
001 Two
010 Four
011 Eight
Else Reserved
19.5.1.6.2
DDR Extended Mode Register Definition
Figure 19-12 shows a typical extended-mode register used by DDR SDRAMs. This is the SDRAM’s
extended mode register, not the SDRAMC’s mode/extended-mode register (SDMR) defined in
Section 19.4.1, “SDRAM Mode/Extended Mode Register (SDMR).” Refer to the SDRAM manufacturer’s
device data sheet to confirm correct settings.
Field
BA1
BA0
0
1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
OPTION
A0
DLL
Figure 19-11. Typical DDR Extended Mode Register
Table 19-14. Typical DDR Extended-Mode Register Field Descriptions
Field
Description
BA1–BA0 Bank address. These must be set to 01 to select the extended mode register.
A11–A1 Option. These bits are not defined by the DDR specification. Each DDR SDRAM manufacturer can use these bits to
OPTION implement optional features. Check with the SDRAM manufacturer to determine if any optional features have been
implemented. For normal operation all bits must be cleared.
A0
DLL
Delay locked loop. Controls enabling of the delay locked loop circuitry used for DDR timing.
0 Enabled
1 Disabled
19.5.1.6.3
Low-Power/Mobile DDR Extended Mode Register Definition
Figure 19-12 shows a typical extended-mode register used by low-power/mobile DDR SDRAMs. This is
the SDRAM’s extended mode register, not the SDRAMC’s mode/extended-mode register (SDMR)
defined in Section 19.4.1, “SDRAM Mode/Extended Mode Register (SDMR).” Refer to the SDRAM
manufacturer’s device data sheet to confirm correct settings.
Field
BA1
BA0
1
0
A11
A10
A9
—
A8
A7
A6
A5
DS
A4
A3
TCSR
A2
A1
A0
PASR
Figure 19-12. Typical Mobile DDR Extended Mode Register
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Freescale Semiconductor
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SDRAM Controller (SDRAMC)
Table 19-15. Mobile DDR Extended-Mode Register Field Descriptions
Field
Description
BA1–BA0 Bank address. These must be set to 10 to select the extended mode register.
A11–A7
Reserved, must be cleared.
A6–A5
DS
Drive strength.
00 Full strength
01 Half strength
10 Quarter strength
11 One-eighth strength
A4–A3
TCSR
Temperature-compensated self-refresh. Check the SDRAM manufacturer’s spec because the use of the TCSR
settings can vary from memory to memory.
A2–A0
PASR
Partial array self refresh coverage.
000 Full array
001 Half array
010 Quarter array
101 One-eighth array
110 One-sixteenth array
All other settings are reserved.
19.5.1.7
Auto-Refresh Command (REF)
The memory controller issues auto-refresh commands according to the SDCR[REF_CNT] value. Each
time the programmed refresh interval elapses, the memory controller issues a PALL command followed by
a REF command.
If a memory access is in progress at the time the refresh interval elapses, the memory controller schedules
the refresh after the transfer finishes; the interval timer continues counting so the average refresh rate is
constant.
After REF command, the SDRAM is in an idle state and waits for an ACTV command.
19.5.1.8
Self-Refresh (SREF) and Power Down (PDWN) Commands
The memory controller issues a PDWN or a SREF command if the SDCR[CKE] bit is cleared. If the
SDCR[REF_EN] bit is set when CKE is negated, the controller issues a SREF command; if the REF_EN
bit is cleared, the controller issues a PDWN command. The REF_EN bit may be changed in the same
register write that changes the CKE bit; the controller acts upon the new value of the REF_EN bit.
Like an auto-refresh command, the controller automatically issues a PALL command before the self-refresh
command.
The memory reactivates from power-down or self-refresh mode by setting the CKE bit.
If a normal refresh interval elapses while the memory is in self-refresh mode, a PALL and REF performs
when the memory reactivates. If the memory is put into and brought out of self-refresh all within a
single-refresh interval, the next automatic refresh occurs on schedule.
In self-refresh mode, memory does not require an external clock. The SD_CLK can be stopped for
maximum power savings. If the memory controller clock is stopped, the refresh-interval timer must be
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SDRAM Controller (SDRAMC)
reset before the memory is reactivated (if periodic refresh is to be resumed). The refresh-interval timer
resets by clearing the REF_EN bit. This can be done at any time while the memory is in self-refresh mode,
before or after the memory controller clock is stopped/restarted, but not with the same control register
write that clears CKE; this would put the memory in power down mode. To restart periodic refresh when
the memory reactivates, the REF_EN bit must be reasserted; this can be done before the memory
reactivates or in the same control register write that sets CKE to exit self-refresh mode.
19.5.2
Read Clock Recovery (RCR) Block
The RCR block allows the external DDR memory devices to generate clock pulses (strobes) that define
the data valid window for each DDR data cycle. The RCR delay block compensates for each byte lane and
generates an internal read strobe targeted to the center of the data valid window provided by the external
DDR memories.
Figure 19-13 displays a simple timing diagram that illustrates the end result of the RCR delay.
tCLK
Memory
Clock
tCLK/2
tCLK/2
Don’t Care
tCLK
tCLK/2
tCLK/2
SD_DQSn
tCLK/4
tCLK/4
tCLK/2
tCLK/2
rd_clk
(internal signal)
Figure 19-13. Frequency Doubler Block Diagram
Dual data rate (DDR) memories provide data strobe (DQS) timing reference signals in parallel with read
data. However, these strobe signals cannot directly clock the data because the strobe edges are aligned with
the edges of the data valid window, not the center. The RCR delay module is responsible for delaying the
received DQS edges to achieve data-center alignment instead of data-edge alignment. There are two data
valid windows per memory clock period with DDR, so the nominal delay of read clocks from DQS is 1/4
memory clock period.
Single data rate (SDR) memories do not use or provide DQS signals. In SDR mode, the SDRAM controller
provides an SDRDQS signal that can be driven off-chip and routed back into the DQS inputs. The center
of the data valid window is guaranteed relative to the memory clock at the memory devices.
The round-trip SDRDQS-to-DQS delay must match the memory clock output + read data input +
round-trip time-of-flight delay so that the received DQS edges have a known phase relationship to the
received data. The SDRDQS signal is generated with a 1/4 memory clock period lead time, to compensate
for the 1/4 memory clock period delay of DQS through the RCR delay module.
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SDRAM Controller (SDRAMC)
The RCR delay module maintains the 1/4 memory clock period delay of the DQS signals across the full
range of silicon process, voltage, and temperature conditions.
The RD_CLK is an internal reconstructed clock derived from DQS. It is twice the frequency of DQS, with
the rising edge shifted 1/4 memory clock period after the DQS edge to align with the nominal center of the
data valid window.
19.6
Initialization/Application Information
SDRAMs have a prescribed initialization sequence. The following sections detail the memory
initialization steps for SDR, DDR SDRAM, and mobile DDR SDRAM. The sequence might change
slightly from device-to-device. Refer to the SDRAM manufacturer’s device datasheet as the most relevant
reference.
19.6.1
SDR SDRAM Initialization Sequence
1. After reset is deactivated, pause for the amount of time indicated in SDRAM specification. Usually
100μs.
2. Configure pin multiplex control for shared SD_CS pins in pin multiplexing and control module if
needed.
3. Configure the slew rate for the SDRAM external pins in the pin multiplexing and control module’s
MSCR_SDRAM register if needed.
4. Write the SDCSn register values for each chip select that is used.
5. Program SDRAM configuration registers (SDCFG1 and SDCFG2) with correct delay and timing
values.
6. Issue a PALL command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] and
SDCR[MODE_EN] set. The SDCR[REF and IREF] bits should remain cleared for this step.
7. Refresh the SDRAM. The SDRAM specification should indicate a number of refresh cycles to be
performed before issuing an LMR command (usually two). Write to the SDCR with the IREF and
MODE_EN bits set (SDCR[REF and IPALL] must be cleared). This forces a refresh of the
SDRAM each time the IREF bit is set. Repeat this step until the specified number of refresh cycles
have been completed.
8. Initialize the SDRAM’s mode register using the LMR command. See Section 19.5.1.6, “Load
Mode/Extended Mode Register Command (lmr, lemr),” for more instruction on issuing an LMR
command.
9. Set SDCR[REF] to enable automatic refreshing, and clear SDCR[MODE_EN] to lock the SDMR.
SDCR[IREF and IPALL] remain cleared.
19.6.2
DDR SDRAM Initialization Sequence
1. After reset is deactivated, pause for the amount of time indicated in SDRAM specification. Usually
200μs.
2. Configure pin multiplex control for shared SD_CS pins in pin multiplexing and control module if
needed.
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SDRAM Controller (SDRAMC)
3. Configure the slew rate for the SDRAM external pins in the pin multiplexing and control module’s
MSCR_SDRAM register if needed.
4. Write the SDCSn register values for each chip select that is used.
5. Program SDRAM configuration registers (SDCFG1 and SDCFG2) with correct delay and timing
values.
6. Issue a PALL command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] and
SDCR[MODE_EN] set. The SDCR[REF and IREF] bits should remain cleared for this step.
7. Initialize the SDRAM’s extended mode register to enable the DLL. See Section 19.5.1.6, “Load
Mode/Extended Mode Register Command (lmr, lemr),” for instructions on issuing a LEMR
command.
8. Initialize the SDRAM’s mode register and reset the DLL using the LMR command. See
Section 19.5.1.6, “Load Mode/Extended Mode Register Command (lmr, lemr),” for more
instruction on issuing a LMR command. During this step the OP_MODE field of the mode register
should be set to normal operation/reset DLL.
9. Pause for the DLL lock time specified by the memory.
10. Issue a second PALL command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL]
and SDCR[MODE_EN] set. The SDCR[REF and IREF] bits should remain cleared for this step.
11. Refresh the SDRAM. The SDRAM specification should indicate a number of refresh cycles to be
performed before issuing an LMR command (usually two). Write to the SDCR with the IREF and
MODE_EN bits set (SDCR[REF and IPALL] must be cleared). This forces a refresh of the
SDRAM each time the IREF bit is set. Repeat this step until the specified number of refresh cycles
have been completed.
12. Initialize the SDRAM’s mode register using the LMR command. See Section 19.5.1.6, “Load
Mode/Extended Mode Register Command (lmr, lemr),” for more instruction on issuing an LMR
command. During this step the OP_MODE field of the mode register should be set to normal
operation.
13. Set SDCR[REF] to enable automatic refreshing, and clear SDCR[MODE_EN] to lock the SDMR.
SDCR[IREF and IPALL] remain cleared.
19.6.3
Low-power/Mobile SDRAM Initialization Sequence
1. After reset is deactivated, pause for the amount of time indicated in SDRAM specification. Usually
100μs or 200μs.
2. Configure pin multiplex control for shared SD_CS pins in pin multiplexing and control module.
3. Configure the slew rate for the SDRAM external pins in the pin multiplexing and control module’s
MSCR_SDRAM register.
4. Write the base address and mask registers (SDBAR0, SDBAR1, SDMR0, and SDMR1) to setup
the address space for each chip-select.
5. Program SDRAM configuration registers (SDCFG1 and SDCFG2) with correct delay and timing
values.
6. Issue a PALL command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] and
SDCR[MODE_EN] set. The SDCR[REF and IREF] bits should remain cleared for this step.
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SDRAM Controller (SDRAMC)
7. Refresh the SDRAM. The SDRAM specification should indicate a number of refresh cycles to be
performed before issuing an LMR command (usually two). Write to the SDCR with the IREF and
MODE_EN bits set (SDCR[REF and IPALL] must be cleared). This forces a refresh of the
SDRAM each time the IREF bit is set. Repeat this step until the specified number of refresh cycles
have been completed.
8. Initialize the SDRAM’s mode register using the LMR command. See Section 19.5.1.6, “Load
Mode/Extended Mode Register Command (lmr, lemr),” for more instruction on issuing an LMR
command.
9. Initialize the SDRAM’s extended mode register using the LEMR command. See Section 19.5.1.6,
“Load Mode/Extended Mode Register Command (lmr, lemr),” for more instruction on issuing an
LEMR command.
10. Set SDCR[REF] to enable automatic refreshing, and clear SDCR[MODE_EN] to lock the SDMR.
SDCR[IREF and IPALL] remain cleared.
19.6.4
Page Management
SDRAM devices have four internal banks. A particular row and bank of memory must be activated to
allow read and write accesses. The SDRAM controller supports paging mode to maximize the memory
access throughout. During operation, the SDRAM controller maintains an open page for each SD_CS
block. An open page is composed of the active rows in the internal banks. Each internal bank has its own
active row.
The physical page size of a SD_CS block is equal to the space size divided by the number of rows; but the
page may not be contiguous in the internal address space because SDRAMs can have a different row
address open in each bank and the internal address bits (A[27:24] and A[9:2]) or (A[27:24] and A[9:1])
used for memory column addresses are not consecutive.
Because the column address may split across two portions of the internal address, the contiguous page size
is (number of contiguous columns per bank) × (number of bits). This gives a contiguous page size of
1 KBytes. However, the total (possibly fragmented) page size is (number of banks) × (number of
columns) × (number of bits).
If a new access does not fall in the open row of an open bank of a SD_CS block, the open row must be
closed (PRE) and the new row must be opened (ACTV), then the READ or WRITE command can proceed. An
ACTV command activates only one bank at one time. If another read or write falls in an inactive bank,
another ACTV is needed, but no precharge is needed. If a read or write falls in any open row of any active
banks of a page, no PRE or ACTV is needed; the read or write command can be issued immediately.
A page is kept open until one of the following conditions occurs:
• An access outside the open page.
• A refresh cycle is started.
All SD_CS blocks are refreshed at the same time. The refresh closes all banks of every SDRAM block.
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SDRAM Controller (SDRAMC)
19.6.5
Transfer Size
In the SDRAMC, the internal data bus is 32 bits wide, while the SDRAM external interface bus is
32 or 16 bits wide. Therefore, each internal data beat requires one or two memory data beats. The SDRAM
controller manages the size translation (packing/unpacking) between internal and external DRAM buses.
The burst size is the processor standard 16 bytes: Four beats of 4 bytes on the internal bus, four beats of 4
bytes (32-bit mode), or eight beats of 2 bytes (16-bit mode) on the memory bus. The SDRAM controller
follows the critical beat first, sequential transfer format required.
The burst size and transfer order must be programmed in the SDRAM mode registers during initialization;
the burst size also must be programmed in the memory controller (SDCFG2 register).
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Freescale Semiconductor
19-31
SDRAM Controller (SDRAMC)
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Chapter 20
Universal Serial Bus Interface – On-The-Go Module
20.1
Introduction
This chapter describes the universal serial bus (USB) interface, which implements many industry
standards. However, it is beyond the scope of this document to document the intricacies of these standards.
Instead, you should refer to the governing specifications. Readers of this chapter are assumed to be fluent
in the operation and requirements of a USB network.
Visit the USB Implementers Forum web page at http://www.usb.org/developers/docs for:
• Universal Serial Bus Specification, Revision 2.0
• On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a
Visit the Intel USB specifications web page at http://www.intel.com/technology/usb/spec.htm for:
• Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0
20.1.1
Overview
The USB On-The-Go (OTG) module is a USB 2.0-compliant serial interface engine for implementing a
USB interface. The registers and data structures are based on the Enhanced Host Controller Interface
Specification for Universal Serial Bus (EHCI) from Intel Corporation. The USB OTG module can act as
a host, a device, or an On-The-Go negotiable host/device on the USB bus.
The USB 2.0 OTG module interfaces to the processor’s ColdFire core. The USB controller is
programmable to support host, or device operations under firmware control. Full-speed (FS) and
low-speed (LS) applications are supported by the integrated on-chip transceiver. The processor’s on-chip
PLL provides all necessary clocks to the USB controller, including a system interface clock and a 60 MHz
clock. For special applications, pin access (via USBCLKIN) is provided for an external 60 MHz reference
clock. See Section 9.3.4, “Miscellaneous Control Register (MISCCR),” for more information.
The USB controller provides control and status signals to interface with external USB OTG and USB host
power devices. Use these control and status signals on the chip interface and the I2C bus to communicate
with external USB On-The-Go and USB host power devices.
USB-host modules must supply 500 mA with a 5 V supply on its downstream port (referred to as VBUS);
however, the USB OTG standard provides a minimum 8 mA VBUS supply requirement. Optionally, the
OTG module may supply up to 500 mA to the USB-connected devices. If the connected device attempts
to draw more than the allocated amount of current, the USB host must disable the port and remove power.
USB VBUS is not provided on-chip. This processor provides pins for control and status to an external IC
capable of managing the VBUS downstream supply.
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20-1
Universal Serial Bus Interface – On-The-Go Module
For OTG operations, external circuitry is required to manage the host negotiation protocol (HNP) and
session request protocol (SRP). External ICs that are capable of providing the OTG VBUS with support
for HNP and SRP, as well as support for programmable pullup and pulldown resistors on the USB DP and
DM lines are available from various manufacturers.
The on-chip FS/LS transceiver also includes a programmable pullup resistor on USB DP. This pullup is
configurable via the CCM. Also, configurable 50 kΩ pulldown resistors are available on the USB_DP and
USB_DM signals of the on-chip transceiver. See Section 9.3.4, “Miscellaneous Control Register
(MISCCR),” for more information. The primary function of the transceiver is the physical signal
conditioning of the external USB DP and DM cable signals for a USB 2.0 network. Several USB system
elements are not supported on the device as they are available via standard products from various
manufacturers.
20.1.2
Block Diagram
Figure 20-1 shows the USB On-The-Go interface using the on-chip full-speed/low-speed transceiver.
USB On-The-Go
USBD_DM
Controller
USB Host/Dev/OTG
Interrupt Subsystem
Internal Bus
USBD_DP
FS/LS
Transceiver
OTG
Control
Status
Chip
Configuration
Module
VBUS
Interrupt
I2C
SCL/SDA
Master
Figure 20-1. USB On-The-Go with on-chip FS/LS Transceiver Interface Block Diagram
20.1.3
Features
The USB On-The-Go module includes these features:
• Complies with USB specification rev 2.0
• USB host mode
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Universal Serial Bus Interface – On-The-Go Module
•
— Supports enhanced-host-controller interface (EHCI).
— Allows direct connection of FS/LS devices without an OHCI/UHCI companion controller.
— Supported by Linux and other commercially available operating systems.
USB device mode
— Supports full-speed operation via the on-chip transceiver.
— Supports one upstream facing port.
— Supports four programmable, bidirectional USB endpoints, including endpoint 0. See endpoint
configurations:
Table 20-1. Endpoint Configurations
•
•
Endpoint
Type
FIFO Size
Data Transfer
Comments
0
Bidirectional
Variable
Control
Mandatory
1-3
IN or OUT
Variable
Ctrl, Int, Bulk, or Iso
Optional
Suspend mode/low power
— As host, firmware can suspend individual devices or the entire USB and disable chip clocks for
low-power operation
— Device supports low-power suspend
— Remote wake-up supported for host and device
— Integrated with the processor’s doze and stop modes for low power operation
Includes an on-chip full-speed (12 Mbps) and low-speed (1.5 Mbps) transceiver
20.1.4
Modes of Operation
The USB OTG module has two basic operating modes: host and device. Selection of operating mode is
accomplished via the USBMODE[CM] bit field.
Speed selection is auto-detected at connect time via sensing of the DP or DM pull-up resistor on the
connected device using enumeration procedures in the USB network. The USB OTG module provides
these operation modes:
• USB disabled. In this mode, the USB OTG’s datapath does not accept transactions received on the
USB interface.
• USB enabled. In this mode, the USB host’s datapath is enabled to accept transactions received on
the USB interface.
• USB enabled, low-power modes. See Section 20.1.4.1, “Low-Power Modes,” for details.
20.1.4.1
Low-Power Modes
The USB OTG module is integrated with the processor’s low-power modes (stop, doze and wait). The
modes are implemented as follows:
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
20-3
Universal Serial Bus Interface – On-The-Go Module
•
Stop — The processor stops the clock to the USB OTG module. In this state, the USB OTG module
ignores traffic on the USB and does not generate any interrupts or wake-up events. The on-chip
transceiver is disabled to save power.
Wait — The clocks to the USB OTG module are running.
Doze — The processor stops the system clocks to the USB OTG module, but the 60 MHz
transceiver clock remains active. In doze mode, detection of resume signaling initiates a restart of
the module clocks.
•
•
20.2
External Signal Description
Table 20-2 describes the external signal functionality of the USB OTG module.
Table 20-2. USB OTG Signal Descriptions
Signal
I/O
Description
On-chip FS/LS transceiver
USB_CLKIN
USB_DM
I
Optional 60 MHz clock source.
I/O Data minus. Output of dual-speed transceiver for the USB OTG module.
State Asserted—Data 1
Meaning Negated—Data 0
Timing Asynchronous
USB_DP
I/O Data plus. Output of dual-speed transceiver for the USB OTG module.
State Asserted—Data 1
Meaning Negated—Data 0
Timing Asynchronous
USB_VBUS_EN
O Enables the off-chip VBUS charge pump when USB OTG module is configured as a host.
State Asserted—Enables the external VBUS supply.
Meaning Negated—Disables the external VBUS supply.
Timing Asynchronous
USB_VBUS_OC
I
Alerts the processor that a short (overcurrent) has occurred on USB data bus.
State Asserted—Power fault occurred.
Meaning Negated—No power fault.
Timing Asynchronous
20.2.1
USB OTG Control and Status Signals
The USB OTG module uses a number of control and status signals to implement the OTG protocols. The
USB OTG module must be able to individually enable and disable the pull-up and pull-down resistors on
DP and DM, and it must be able to control and sense the levels on the USB VBUS line.
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Universal Serial Bus Interface – On-The-Go Module
These control and status signals are implemented on chip as registers within the chip-configuration module
(CCM) to minimize the pin-count on the device. With firmware, the system designer uses an external
device to manage the OTG functions to implement communications across the I2C bus or GPIO pins.
The OTG controller status register (UOCSR) implements as follows:
• Writes to the UOCSR register from the firmware set the corresponding bits on the USB interface.
• When the USB OTG module outputs change, the corresponding bits on the UOCSR register are
updated, and a maskable interrupt is generated.
The UOCSR register is documented in the CCM chapter, see Section 9.3.6, “USB On-the-Go Controller
Status Register (UOCSR).”
Table 20-3. Internal Control and Status Bits for USB OTG Module
Signal
Mnemonic
Direction
Comments
Interrupt
Trigger?
DP Pull-down
Enable
DPPD
Enables 15 kΩ resistor pull-down
on DP
R
Y
DM Pull-down
Enable
DMPD
Enables 15 kΩ resistor pull-down
on DM
R
Y
VBUS Charge
CRG_VBUS
Enables 8 mA pull-up to charge
VBUS.
R
Y
VBUS Discharge
DCR_VBUS
Enables 8 mA pull-down to
discharge VBUS.
R
Y
DP Pull-up Enable
DPPU
Enables the 1.5KΩ resistor pull-up
on DP
R
Y
A Session Valid
AVLD
Indicates a valid session level for A
device detected on VBUS.
R/W
N
B Session Valid
BVLD
Indicates a valid session level for B
device detected on VBUS.
R/W
N
Session Valid
VVLD
Indicates valid operating level on
VBUS from USB device’s
perspective.
R/W
N
Session End
SEND
Indicates VBUS fell below the
session valid threshold.
R/W
N
Wake-up Event
WKUP
Reflects when a wake-up event
occurred on the USB bus.
R/W
Y
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20-5
Universal Serial Bus Interface – On-The-Go Module
Table 20-3. Internal Control and Status Bits for USB OTG Module (continued)
Mnemonic
Direction
Comments
Interrupt
Trigger?
Interrupt Mask
UOMIE
Interrupt enable. When this bit is 1,
changes on DPPD, DMPD, DPPU,
CHRG_VBUS, DCRG_VBUS, or
VBUS_PWR cause an interrupt to
be asserted.
When this bit is 0, the interrupt is
masked.
R/W
N/A
On-chip Transceiver
Pull-down Enable
XPDE
Enables the on-chip 50 kΩ
pull-downs on the OTG controller’s
DM and DP pins when the on-chip
transceiver is used.
R/W
N
Signal
20.3
Memory Map/Register Definition
This section provides the memory map and detailed descriptions of all USB-interface registers. See
Table 20-4 for the memory map of the USB OTG interface.
0xFC0B_0000 Identification Register (ID)
N
H/D
32
R
0x0042_FA05
20.3.1.1/20-8
0xFC0B_0004 General Hardware Parameters (HWGENERAL)
N
H/D
32
R
0x0000_07C5
20.3.1.2/20-8
0xFC0B_0008 Host Hardware Parameters (HWHOST)
N
H/D
32
R
0x1002_0001
20.3.1.3/20-9
0xFC0B_000C Device Hardware Parameters (HWDEVICE)
N
D
32
R
0x0000_0009
20.3.1.4/20-9
0xFC0B_0010 TX Buffer Hardware Parameters (HWTXBUF)
N
H/D
32
R
0x8004_0604
20.3.1.5/20-10
0xFC0B_0014 RX Buffer Hardware Parameters (HWRXBUF)
N
H/D
32
R
0x0000_0404
20.3.1.6/20-11
Register
H/D2
Reset
Address
EHCI1
Access
Table 20-4. USB On-The-Go Memory Map
Width
(bits)
Section/Page
Module Identification Registers
Device/Host Timer Registers
0xFC0B_0080 General Purpose Timer 0 Load (GPTIMER0LD)
N
H/D
32
R/W 0x0000_0000
20.3.2.1/20-11
0xFC0B_0084 General Purpose Timer 0 Control (GPTIMER0CTL)
N
H/D
32
R/W 0x0000_0000
20.3.2.2/20-12
0xFC0B_0088 General Purpose Timer 1 Load (GPTIMER1LD)
N
H/D
32
R/W 0x0000_0000
20.3.2.1/20-11
0xFC0B_008C General Purpose Timer 1 Control (GPTIMER1CTL)
N
H/D
32
R/W 0x0000_0000
20.3.2.2/20-12
0xFC0B_0100 Host Interface Version Number (HCIVERSION)
Y
H
16
R
0x0100
20.3.3.1/20-13
0xFC0B_0103 Capability Register Length (CAPLENGTH)
Y
H/D
8
R
0x40
20.3.3.2/20-13
0xFC0B_0104 Host Structural Parameters (HCSPARAMS)
Y
H
32
R
0x0001_0011
20.3.3.3/20-14
0xFC0B_0108 Host Capability Parameters (HCCPARAMS)
Y
H
32
R
0x0000_0006
20.3.3.4/20-15
Capability Registers
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
Universal Serial Bus Interface – On-The-Go Module
EHCI1
H/D2
Width
(bits)
Access
Table 20-4. USB On-The-Go Memory Map (continued)
Reset
0xFC0B_0122 Device Interface Version Number (DCIVERSION)
N
D
16
R
0x0001
20.3.3.5/20-15
0xFC0B_0124 Device Capability Parameters (DCCPARAMS)
N
D
32
R
0x0000_0184
20.3.3.6/20-16
Address
Register
Section/Page
Operational Registers
0xFC0B_0140 USB Command (USBCMD)
Y
H/D
32
R/W 0x0008_0000
20.3.4.1/20-17
0xFC0B_0144 USB Status (USBSTS)
Y
H/D
32
R/W 0x0000_0080
20.3.4.2/20-19
0xFC0B_0148 USB Interrupt Enable (USBINTR)
Y
H/D
32
R/W 0x0000_0000
20.3.4.3/20-22
0xFC0B_014C USB Frame Index (FRINDEX)
Y
H/D
32
R/W 0x0000_0000
20.3.4.4/20-24
0xFC0B_0154 Periodic Frame List Base Address (PERIODICLISTBASE)
Y
H
32
R/W 0x0000_0000
20.3.4.5/20-25
0xFC0B_0154 Device Address (DEVICEADDR)
N
D
32
R/W 0x0000_0000
20.3.4.6/20-26
0xFC0B_0158 Current Asynchronous List Address (ASYNCLISTADDR)
Y
H
32
R/W 0x0000_0000
20.3.4.7/20-26
0xFC0B_0158 Address at Endpoint List (EPLISTADDR)
N
D
32
R/W 0x0000_0000
20.3.4.8/20-27
0xFC0B_015C Host TT Asynchronous Buffer Control (TTCTRL)
N
H
32
R/W 0x0000_0000
20.3.4.9/20-27
0xFC0B_0160 Master Interface Data Burst Size (BURSTSIZE)
N
H/D
32
R/W 0x0000_0404 20.3.4.10/20-28
0xFC0B_0164 Host Transmit FIFO Tuning Control (TXFILLTUNING)
N
H
32
R/W 0x0000_0000 20.3.4.11/20-28
0xFC0B_0180 Configure Flag Register (CONFIGFLAG)
Y
H/D
32
0xFC0B_0184 Port Status/Control (PORTSC1)
Y
H/D
32
R/W 0xEC00_0004 20.3.4.13/20-30
0xFC0B_01A4 On-The-Go Status and Control (OTGSC)
N
H/D
32
R/W 0x0000_1020 20.3.4.14/20-35
0xFC0B_01A8 USB Mode Register (MODE)
N
H/D
32
R/W 0x0000_0000 20.3.4.15/20-37
0xFC0B_01AC Endpoint Setup Status Register (EPSETUPSR)
N
D
32
R/W 0x0000_0000 20.3.4.16/20-39
0xFC0B_01B0 Endpoint Initialization (EPPRIME)
N
D
32
R/W 0x0000_0000 20.3.4.17/20-39
0xFC0B_01B4 Endpoint De-initialize (EPFLUSH)
N
D
32
R/W 0x0000_0000 20.3.4.18/20-40
0xFC0B_01B8 Endpoint Status Register (EPSR)
N
D
32
0xFC0B_01BC Endpoint Complete (EPCOMPLETE)
N
D
32
R/W 0x0000_0000 20.3.4.20/20-41
0xFC0B_01C0 Endpoint Control Register 0 (EPCR0)
N
D
32
R/W 0x0080_0080 20.3.4.21/20-42
0xFC0B_01C4 Endpoint Control Register 1 (EPCR1)
N
D
32
R/W 0x0000_0000 20.3.4.22/20-43
0xFC0B_01C8 Endpoint Control Register 2 (EPCR2)
N
D
32
R/W 0x0000_0000 20.3.4.22/20-43
0xFC0B_01CC Endpoint Control Register 3 (EPCR3)
N
D
32
R/W 0x0000_0000 20.3.4.22/20-43
1
2
R
R
0x0000_0001 20.3.4.12/20-30
0x0000_0000 20.3.4.19/20-40
Indicates if the register is present in the EHCI specification.
Indicates if the register is available in host and/or device modes.
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Freescale Semiconductor
20-7
Universal Serial Bus Interface – On-The-Go Module
20.3.1
Module Identification Registers
Declare the slave interface presence and include a table of the hardware configuration parameters. These
registers are not defined by the EHCI specification.
20.3.1.1
Identification (ID) Register
Provides a simple way to determine if the module is provided in the system. The ID register identifies the
module and its revision.
Address: 0xFC0B_0000 (ID)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
REVISION
1
1
1
1
9
8
NID
7
6
0
0
0
0
5
4
3
2
1
0
1
0
1
ID
W
Reset 0
0
1
0
0
0
0
1
0
1
1
1
0
1
0
0
0
0
Figure 20-2. Identification Register (ID)
Table 20-5. ID Field Descriptions
Field
Description
31–24
Reserved, always cleared.
23–16
Revision number of the module.
REVISION
15–14
Reserved, always set.
13–8
NID
Ones-complement version of the ID bit field.
7–6
Reserved, always cleared.
5–0
ID
Configuration number. This number is set to 0x05.
20.3.1.2
General Hardware Parameters Register (HWGENERAL)
The HWGENERAL register contains parameters defining the particular implementation of the module.
Address: 0xFC0B_0004 (HWGENERAL)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
SM
8
7
6
PHYM
3
2
1
0
PHYW 0
5
4
0
0
0
1
0
1
W
Reset 0
1
1
1
1
1
0
0
0
Figure 20-3. General Hardware Parameters Register (HWGENERAL)
MCF52277 Reference Manual, Rev 2
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Universal Serial Bus Interface – On-The-Go Module
Table 20-6. HWGENERAL Field Descriptions
Field
Description
31–11
Reserved, always cleared.
10–9
SM
Serial mode. Indicates presence of serial interface. Always 11.
11 Serial engine is present and defaulted for all FS/LS operations
8–6
PHYM
PHY Mode. Indicates USB transceiver interface used. Always reads 111.
111 Software controlled reset to serial FS
5–4
PHYW
PHY width. Indicates data interface to UTMI transceiver. This field is relevant only for UTMI mode; therefore, it is
relevant only to the USB OTG module in UTMI mode. Always reads 00.
00 8-bit data bus (60 MHz)
3
Reserved, always cleared.
2–1
Reserved. For the USB OTG module, always 10.
0
Reserved, always set.
20.3.1.3
Host Hardware Parameters Register (HWHOST)
Provides host hardware parameters for this implementation of the module.
Address: 0xFC0B_0008 (HWHOST)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
TTPER
TTASY
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
NPORT HC
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
Figure 20-4. Host Hardware Parameters Register (HWHOST)
Table 20-7. HWHOST Field Descriptions
Field
Description
31–24
TTPER
Transaction translator periodic contexts. Number of supported transaction translator periodic contexts.
Always 0x10.
0x10 16
23–16
TTASY
Transaction translator contexts. Number of transaction translator contexts. Always 0x02.
0x02 2
15–4
3–1
NPORT
0
HC
20.3.1.4
Reserved, always cleared.
Indicates number of ports in host mode minus 1. Always 0 for the USB OTG module.
Indicates module is host capable. Always set.
Device Hardware Parameters Register (HWDEVICE)
Provides device hardware parameters for this implementation of the USB OTG module.
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Freescale Semiconductor
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Universal Serial Bus Interface – On-The-Go Module
Address: 0xFC0B_000C (HWDEVICE)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0
9
8
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
DEVEP
DC
W
Reset 0
0
0
1
0
0
1
Figure 20-5. Device Hardware Parameters Register (HWDEVICE)
Table 20-8. HWDEVICE Field Descriptions
Field
31–6
5–1
DEVEP
0
DC
Description
Reserved, always cleared.
Device endpoints. The number of supported endpoints. Always 0x04.
Indicates the OTG module is device capable. Always set.
20.3.1.5
Transmit Buffer Hardware Parameters Register (HWTXBUF)
Provides the transmit-buffer parameters for this implementation of the module.
Address: 0xFC0B_0010 (HWTXBUF)
31
Access: User read-only
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R TXLC 0
0
0
0
0
0
0
0
0
0
0
0
0
TXCHANADD
9
8
7
6
TXADD
5
4
3
2
1
0
0
0
TXBURST
W
Reset
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
Figure 20-6. Transmit Buffer Hardware Parameters Register (HWTXBUF)
Table 20-9. HWTXBUF Field Descriptions
Field
Description
31
TXLC
Transmit local context registers. Indicates how the device transmit context registers implement. Always set on
USB OTG module.
0 Store device transmit contexts in the TX FIFO
1 Store device transmit contexts in a register file
30–24
Reserved, always cleared.
23–16
Transmit channel address. Number of address bits required to address one channel’s worth of TX data. Always
TXCHANADD 0x04.
15–8
TXADD
7–0
TXBURST
Transmit address. Number of address bits for the entire TX buffer. Always 0x06.
Transmit burst. Indicates number of data beats in a burst for transmit DMA data transfers. Always 0x04.
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Universal Serial Bus Interface – On-The-Go Module
20.3.1.6
Receive Buffer Hardware Parameters Register (HWRXBUF)
Provides the receive buffer parameters for this implementation of the module.
Address: 0xFC0B_0014 (HWRXBUF)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
RXADD
4
3
2
1
0
0
0
RXBURST
W
Reset 0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
Figure 20-7. Receive Buffer Hardware Parameters Register (HWRXBUF)
Table 20-10. HWRXBUF Field Descriptions
Field
Description
31–16
Reserved.
15–8
RXADD
Receive address. The number of address bits for the entire RX buffer. Always 0x04.
7–0
RXBURST
20.3.2
Receive burst. Indicates the number of data beats in a burst for receive DMA data transfers. Always 0x04.
Device/Host Timer Registers
The host/device controller drivers can measure time-related activites using these timer registers, which are
not defined by the EHCI specification.
20.3.2.1
General Purpose Timer n Load Registers (GPTIMERnLD)
The GPTIMERnLD registers contain the timer duration or load value.
Address: 0xFC0B_0080 (GPTIMER0LD)
0xFC0B_0088 (GPTIMER1LD)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
GPTLD
W
Reset 0
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-8. General Purpose Timer n Load Registers (GPTIMERnLD)
Table 20-11. GPTIMERnLD Field Descriptions
Field
Description
31–24
Reserved, must be cleared.
23–0
GPTLD
Specifies the value to be loaded into the countdown timer on a reset. The value in this register represents the
time in microseconds minus 1 for the timer duration. For example, for a one millisecond timer,
load 1000 – 1 = 999 (0x00_03E7).
Note: Maximum value of 0xFF_FFFF or 16.777215 seconds.
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Freescale Semiconductor
20-11
Universal Serial Bus Interface – On-The-Go Module
20.3.2.2
General Purpose Timer n Control Registers (GPTIMERnCTL)
The GPTIMERnCTL registers control the various functions of the general purpose timers.
Address: 0xFC0B_0084 (GPTIMER0CTL)
0xFC0B_008C (GPTIMER1CTL)
31
R
W
RUN
Reset
0
30
29 28 27 26 25
0
0
0
0
0
0
0
0
0
0
0
RST
0
24
Access: User read/write
23 22 21 20 19 18 17 16 15 14 13 12 11 10
MODE
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
GPTCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-9. General Purpose Timer n Control Registers (GPTIMERnCTL)
Table 20-12. GPTIMERnCTL Field Descriptions
Field
Description
31
RUN
Timer run. Enables the general purpose timer. Setting or clearing this bit does not have an effect on the
GPTCNT field.
0 Timer stop
1 Timer run
30
RST
Timer reset. Setting this bit reloads GPTCNT with the value in GPTIMERnLD[GPTLD].
0 No action
1 Load counter value
29–25
Reserved, must be cleared.
24
MODE
Timer mode. Selects between a single timer countdown and a looped countdown. In one-shot mode, the timer
counts down to zero, generates an interrupt, and stops until the counter is reset by software. In repeat mode,
the timer counts down to zero, generates an interrupt, and automatically reloads the counter and begins
another countdown.
0 One shot
1 Repeat
23–0
GPTCNT
20.3.3
Timer count. Indicates the current value of the running timer.
Capability Registers
Specifies software limits, restrictions, and capabilities of the host/device controller implementation. Most
of these registers are defined by the EHCI specification. Registers not defined by the EHCI specification
are noted in their descriptions.
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Universal Serial Bus Interface – On-The-Go Module
20.3.3.1
Host Controller Interface Version Register (HCIVERSION)
This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this
OTG controller. The most-significant byte of the register represents a major revision; the least-significant
byte is the minor revision. Figure 20-10 shows the HCIVERSION register.
Address: 0xFC0B_0100 (HCIVERSION)
15
14
13
12
Access: User read-only
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
HCIVERSION
W
Reset
0
0
0
0
0
0
0
1
0
Figure 20-10. Host Controller Interface Version Register (HCIVERSION)
Table 20-13. HCIVERSION Field Descriptions
Field
Description
15–0
EHCI revision number. Value is 0x0100 indicating version 1.0.
HCIVERSION
20.3.3.2
Capability Registers Length Register (CAPLENGTH)
Register is used as an offset to add to the register base address to find the beginning of the operational
register space, the location of the USBCMD register.
Address: 0xFC0B_0103 (CAPLENGTH)
7
6
Access: User read-only
5
R
4
3
2
1
0
0
0
0
0
CAPLENGTH
W
Reset:
0
1
0
0
Figure 20-11. Capability Registers Length Register (CAPLENGTH)
Table 20-14. CAPLENGTH Field Descriptions
Field
Description
7–0
Capability registers length. Always 0x40.
CAPLENGTH
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Freescale Semiconductor
20-13
Universal Serial Bus Interface – On-The-Go Module
20.3.3.3
Host Controller Structural Parameters Register (HCSPARAMS)
This register contains structural parameters such as the number of downstream ports. Figure 20-12 shows
the HCSPARAMS register.
Address: 0xFC0B_0104 (HCSPARAMS)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
R 0
0
0
0
0
0
0
N_TT
N_PTT
16
0
0
0
PI
0
0
0
0
15 14 13 12 11 10
N_CC
9
8
N_PCC
7
6
5
0
0
0 PPC
4
3
N_PORTS
2
1
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
Figure 20-12. Host Controller Structural Parameters Register (HCSPARAMS)
Table 20-15. HCSPARAMS Field Descriptions
Field
Description
31–28
Reserved, always cleared.
27–24
N_TT
Number of transaction translators. Non-EHCI field. Indicates number of embedded transaction translators
associated with host controller. This field is always 0x0.
See Section 20.5.5.1, “Embedded Transaction Translator Function,” for more information on embedded
transaction translators.
23–20
N_PTT
Ports per transaction translator. Non-EHCI field. Indicates number of ports assigned to each transaction
translator within host controller.
19–17
Reserved, always cleared.
16
PI
15–12
N_CC
11–8
N_PCC
Port indicators. Indicates whether the ports support port indicator control. Always cleared.
0 No port indicator fields.
1 The port status and control registers include a R/W field for controlling the state of the port indicator. See
Table 20-3 for more information.
Number of companion controllers. Indicates number of companion controllers associated with USB OTG
controller. Always cleared.
Number ports per CC. Indicates number of ports supported per internal companion controller. This field is 0
because no companion controllers are present.
7–5
Reserved, always cleared.
4
PPC
Power port control. Indicates whether host controller supports port power control. Always set.
1 Ports have power port switches.
3–0
N_PORTS
Number of ports. Indicates number of physical downstream ports implemented for host applications. Field value
determines how many addressable port registers in the operational register. For the USB OTG module, this is
always 0x1.
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Universal Serial Bus Interface – On-The-Go Module
20.3.3.4
Host Controller Capability Parameters Register (HCCPARAMS)
Identifies multiple mode control (time-base bit functionality) addressing capability.
Address: 0xFC0B_0108 (HCCPARAMS)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
8
7
EECP
6
5
4
3
IST
2
1
0
0 ASP PFL ADC
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
Figure 20-13. Host Controller Capability Parameters Register (HCCPARAMS)
Table 20-16. HCCPARAMS Field Descriptions
Field
Description
31–16
Reserved, always cleared.
15–8
EECP
EHCI extended capabilities pointer. This optional field indicates the existence of a capabilities list.
0x00 No extended capabilities are implemented. This field is always 0.
7–4
IST
Isochronous scheduling threshold. Indicates where software can reliably update the isochronous schedule,
relative to the current position of the executing host controller. This field is always 0.
0 The value of the least significant 3 bits indicates the number of microframes a host controller can hold a set
of isochronous data structures (one or more) before flushing the state.
3
Reserved, always cleared.
2
ASP
Asynchronous schedule park capability. Indicates if the host controller supports the park feature for high-speed
queue heads in the asynchronous schedule. The feature can be disabled or enabled and set to a specific level
by using the asynchronous schedule park mode enable and asynchronous schedule park mode count fields in
the USBCMD register. This bit is always set.
0 Park not supported.
1 Park supported.
1
PFL
Programmable frame list flag. Indicates that system software can specify and use a frame list length less that
1024 elements. This bit is always set.
1 Frame list size is configured via the USBCMD register frame list size field. The frame list must always be
aligned on a 4K-page boundary. This requirement ensures that the frame list is always physically contiguous.
0
ADC
64-bit addressing capability. This field is always 0; 64-bit addressing is not supported.
0 Data structures use 32-bit address memory pointers
20.3.3.5
Device Controller Interface Version (DCIVERSION)
Not defined in the EHCI specification. DCIVERSION is a two-byte register containing a BCD encoding
of the device controller interface. The most-significant byte of the register represents a major revision and
the least-significant byte is the minor revision.
Address: 0xFC0B_0120 (DCIVERSION)
15
14
13
12
Access: User read-only
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
DCIVERSION
W
Reset
0
0
0
0
0
0
0
0
0
Figure 20-14. Device Controller Interface Version Register (DCIVERSION)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
20-15
Universal Serial Bus Interface – On-The-Go Module
Table 20-17. DCIVERSION Field Descriptions
Field
Description
15–0
Device interface revision number.
DCIVERSION
20.3.3.6
Device Controller Capability Parameters (DCCPARAMS)
Not defined in the EHCI specification. Register describes the overall host/device capability of the USB
OTG module.
Address: 0xFC0B_0124 (DCCPARAMS)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0
6
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 HC DC 0
9
8
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
0
0
DEN
W
Reset 0
1
1
0
0
0
1
Figure 20-15. Device Control Capability Parameters (DCCPARAMS)
Table 20-18. DCCPARAMS Field Descriptions
Field
31–9
Description
Reserved, always cleared.
8
HC
Host capable. Indicates the USB OTG controller can operate as an EHCI compatible USB 2.0 host. Always set.
7
DC
Device Capable. Indicates the USB OTG controller can operate as an USB 2.0 device. Always set.
6–5
Reserved, always cleared.
4–0
DEN
Device endpoint number. This field indicates the number of endpoints built into the device controller. Always
0x04.
20.3.4
Operational Registers
Comprised of dynamic control or status registers and are defined below.
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Universal Serial Bus Interface – On-The-Go Module
20.3.4.1
USB Command Register (USBCMD)
The module executes the command indicated in this register.
Address: 0xFC0B_0140 (USBCMD)
Access: User read/write
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
R
23
22
21
20
19
18
17
16
ITC
W
Reset
R
W
FS2 ATDTW SUTW
Reset
0
0
0
0
0
ASPE
0
0
0
0
0
0
1
0
0
0
7
6
5
4
3
2
1
0
IAA
ASE
PSE
FS1
FS0
RST
RS
0
0
0
0
0
0
0
0
ASP
0
0
0
0
Figure 20-16. USB Command Register (USBCMD)
Table 20-19. USBCMD Field Descriptions
Field
Description
31–24
Reserved, must be cleared.
23–16
ITC
Interrupt threshold control. System software uses this field to set the maximum rate at which the module issueS
interrupts. ITC contains maximum interrupt interval measured in microframes.
0x00 Immediate (no threshold)
0x01 1 microframe
0x02 2 microframes
0x04 4 microframes
0x08 8 microframes
0x10 16 microframes
0x20 32 microframes
0x40 64 microframes
Else Reserved
15
FS2
See the FS bit description below. This is a non-EHCI bit.
14
ATDTW
Add dTD TripWire. This is a non-EHCI bit. This bit is used as a semaphore when a dTD is added to an active
(primed) endpoint. This bit is set and cleared by software. This bit is also cleared by hardware when the state
machine is in a hazard region where adding a dTD to a primed endpoint may go unrecognized. More
information appears in Section 20.5.3.6.3, “Executing a Transfer Descriptor.”
13
SUTW
Setup TripWire. A non-EHCI bit. Used as a semaphore to ensure that the setup data payload of 8 bytes is
extracted from a QH by driver software without being corrupted. If the setup lockout mode is off
(USBMODE[SLOM] = 1) then a hazard exists when new setup data arrives, and the software copies setup from
the QH for a previous setup packet. This bit is set and cleared by software and is cleared by hardware when a
hazard exists. More information appears in Section 20.5.3.4.4, “Control Endpoint Operation.”
12
11
ASPE
10
Reserved, must be cleared.
Asynchronous schedule park mode enable. Software uses this bit to enable or disable park mode.
1 Park mode enabled
0 Park mode disabled
Reserved, must be cleared.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
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Universal Serial Bus Interface – On-The-Go Module
Table 20-19. USBCMD Field Descriptions (continued)
Field
Description
9–8
ASP
Asynchronous schedule park mode count. Contains a count of the successive transactions the host controller
can execute from a high-speed queue head on the asynchronous schedule before continuing traversal of the
asynchronous schedule. Valid values are 0x1 to 0x3. Software must not write a zero to this field when ASPE is
set as this results in undefined behavior.
7
Reserved, must be cleared.
6
IAA
Interrupt on async advance doorbell. Used as a doorbell by software to tell controller to issue an interrupt the
next time it advances the asynchronous schedule. Software must write a 1 to this bit to ring the doorbell.
When controller has evicted all appropriate cached schedule states, it sets USBSTS[AAI] register. If the
USBINTR[AAE] bit is set, the host controller asserts an interrupt at the next interrupt threshold.
The controller clears this bit after it has set the USBSTS[AAI] bit. Software must not write a 1 to this bit when
the asynchronous schedule is inactive. Doing so yields undefined results. This bit used only in host mode.
Writing a 1 to this bit when the USB OTG module is in device mode has undefined results.
5
ASE
Asynchronous schedule enable. Controls whether the controller skips processing the asynchronous schedule.
Only used in host mode.
1 Use the ASYNCLISTADDR register to access asynchronous schedule.
0 Do not process asynchronous schedule.
4
PSE
Periodic schedule enable. Controls whether the controller skips processing periodic schedule. Used only in host
mode.
1 Use the PERIODICLISTBASE register to access the periodic schedule.
0 Do not process periodic schedule.
3–2
FS
Frame list size. With bit 15, these bits make the FS[2:0] fields, which specifies the frame list size controling
which bits in the frame index register must be used for the frame list current index. Used only in host mode.
Note: Values below 256 elements are not defined in the EHCI specification.
000 1024 elements (4096 bytes)
001 512 elements (2048 bytes)
010 256 elements (1024 bytes)
011 128 elements (512 bytes)
100 64 elements (256 bytes)
101 32 elements (128 bytes)
110 16 elements (64 bytes)
111 8 elements (32 bytes)
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Universal Serial Bus Interface – On-The-Go Module
Table 20-19. USBCMD Field Descriptions (continued)
Field
Description
1
RST
Controller reset. Software uses this bit to reset controller. Controller clears this bit when reset process
completes. Clearing this register does not allow software to terminate the reset process early.
Host mode:
When software sets this bit, the controller resets its internal pipelines, timers, counters, state machines etc.
to their initial value. Any transaction in progress on the USB immediately terminates. A USB reset is not
driven on downstream ports. Software must not set this bit when the USBSTS[HCH] bit is cleared.
Attempting to reset an actively running host controller results in undefined behavior.
Device mode:
When software sets this bit, the controller resets its internal pipelines, timers, counters, state machines, etc.
to their initial value. Setting this bit with the device in the attached state is not recommended because it has
an undefined effect on an attached host. To ensure the device is not in an attached state before initiating a
device controller reset, all primed endpoints must be flushed and the USBCMD[RS] bit must be cleared.
0
RS
Run/Stop.
Host mode:
When set, the controller proceeds with the execution of the schedule. The controller continues execution as
long as this bit is set. When this bit is cleared, the controller completes the current transaction on the USB
and then halts. The USBSTS[HCH] bit indicates when the host controller finishes the transaction and enters
the stopped state. Software must not set this bit unless controller is in halted state (USBSTS[HCH] = 1).
Device mode:
Setting this bit causes the controller to enable a pull-up on DP and initiate an attach event. This control bit is
not directly connected to the pull-up enable, as the pull-up becomes disabled upon transitioning into
high-speed mode. Software must use this bit to prevent an attach event before the USB OTG controller has
properly initialized. Clearing this bit causes a detach event.
20.3.4.2
USB Status Register (USBSTS)
This register indicates various states of each module and any pending interrupts. This register does not
indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register by
writing a 1 to them.
Address: 0xFC0B_0144 (USBSTS)
R
Access: User read/write
31
30
29
28
27
26
0
0
0
0
0
0
W
Reset
R
0
0
0
0
0
0
25
23
22
21
20
0
0
0
0
0
0
0
0
TI1
TI0
w1c
w1c
0
0
19
18
UPI
UAI
0
0
17
16
0
NAKI
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AS
PS
RCL
HCH
0
0
0
SLI
SRI
URI
AAI
SEI
FRI
PCI
UEI
UI
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
W
Reset
24
Figure 20-17. USB Status Register (USBSTS)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
20-19
Universal Serial Bus Interface – On-The-Go Module
Table 20-20. USBSTS Field Descriptions
Field
31–26
Description
Reserved, must be cleared.
25
TI1
General purpose timer 1 interrupt. Set when the counter in the GPTIMER1CTRL register transitions to zero.
Writing a one to this bit clears it.
0 No interrupt
1 Interrupt occurred.
24
TI0
General purpose timer 0 interrupt. Set when the counter in the GPTIMER0CTRL register transitions to zero.
Writing a one to this bit clears it.
0 No interrupt
1 Interrupt occurred.
23–20
Reserved, must be cleared.
19
UPI
USB host periodic interrupt. Set by the host controller when the cause of an interrupt is a completion of a USB
transaction where the transfer descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from
the periodic schedule.
This bit is also set by the host controller when a short packet is detected and the packet is on the periodic
schedule. A short packet is when the actual number of bytes received was less than the expected number of
bytes.
Note: This bit is not used by the device controller and is always zero.
18
UAI
USB host asynchronous interrupt. Set by the host controller when the cause of an interrupt is a completion of
a USB transaction where the transfer descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was
from the asynchronous schedule.
This bit is also set by the host controller when a short packet is detected and the packet is on the asynchronous
schedule. A short packet is when the actual number of bytes received was less than the expected number of
bytes.
Note: This bit is not used by the device controller and is always zero.
17
Reserved, must be cleared.
16
NAKI
NAK interrupt. Set by hardware for a particular endpoint when the TX/RX endpoint’s NAK bit and the
corresponding TX/RX endpoint’s NAK enable bit are set. The hardware automatically clears this bit when all
the enabled TX/RX endpoint NAK bits are cleared.
15
AS
Asynchronous schedule status. Reports the current real status of asynchronous schedule. Controller is not
immediately required to disable or enable the asynchronous schedule when software transitions the
USBCMD[ASE] bit. When this bit and the USBCMD[ASE] bit have the same value, the asynchronous schedule
is enabled (1) or disabled (0). Used only in host mode.
0 Disabled.
1 Enabled.
14
PS
Periodic schedule status. Reports current real status of periodic schedule. Controller is not immediately
required to disable or enable the periodic schedule when software transitions the USBCMD[PSE] bit. When this
bit and the USBCMD[PSE] bit have the same value, the periodic schedule is enabled or disabled. Used only in
host mode.
0 Disabled.
1 Enabled.
13
RCL
Reclamation. DetectS an empty asynchronous schedule. Used only by the host mode.
0 Non-empty asynchronous schedule.
1 Empty asynchronous schedule.
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Universal Serial Bus Interface – On-The-Go Module
Table 20-20. USBSTS Field Descriptions (continued)
Field
Description
12
HCH
Host controller halted. This bit is cleared when the USBCMD[RS] bit is set. The controller sets this bit after it
stops executing because of the USBCMD[RS] bit being cleared, by software or the host controller hardware (for
example, internal error). Used only in host mode.
0 Running.
1 Halted.
11–9
Reserved, must be cleared.
8
SLI
Device-controller suspend. Non-EHCI bit. When a device controller enters a suspend state from an active state,
this bit is set. The device controller clears the bit upon exiting from a suspend state. Used only by the device
controller.
0 Active.
1 Suspended.
7
SRI
SOF received. This is a non-EHCI status bit. Software writes a 1 to this bit to clear it.
Host mode:
In host mode, this bit is set every 125 μs, provided PHY clock is present and running (for example, the port
is NOT suspended) and can be used by the host-controller driver as a time base.
Device mode:
When controller detects a start of (micro) frame, bit is set. When a SOF is extremely late, controller
automatically sets this bit to indicate an SOF was expected. Therefore, this bit is set roughly every 1 ms in
device FS mode and every 125 μsec in HS mode, and it is synchronized to the actual SOF received.
Because the controller is initialized to FS before connect, this bit is set at an interval of 1 ms during the
prelude to the connect and chirp.
6
URI
USB reset received. A non-EHCI bit. When the controller detects a USB reset and enters the default state, this
bit is set. Software can write a 1 to this bit to clear it. Used only by in device mode.
0 No reset received.
1 Reset received.
5
AAI
Interrupt on async advance. By setting the USBCMD[IAA] bit, system software can force the controller to issue
an interrupt the next time the controller advances the asynchronous schedule. This status bit indicates the
assertion of that interrupt source. Used only by the host mode.
0 No async advance interrupt.
1 Async advance interrupt.
4
SEI
System error. Set when an error is detected on the system bus. If the system error enable bit (USBINTR[SEE])
is set, interrupt generates. The interrupt and status bits remain set until cleared by writing a 1 to this bit.
Additionally, when in host mode, the USBCMD[RS] bit is cleared, effectively disabling controller. An interrupt
generates for the USB OTG controller in device mode, but no other action is taken.
0 Normal operation
1 Error
3
FRI
Frame-list rollover. Controller sets this bit when the frame list index (FRINDEX) rolls over from its maximum
value to 0. The exact value the rollover occurs depends on the frame list size. For example, if the frame list size
(as programmed in the USBCMD[FS] field) is 1024, the frame index register rolls over every time FRINDEX[13]
toggles. Similarly, if the size is 512, the controller sets this bit each time FRINDEX[12] toggles. Used only in the
host mode.
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Universal Serial Bus Interface – On-The-Go Module
Table 20-20. USBSTS Field Descriptions (continued)
Field
Description
2
PCI
Port change detect. This bit is not EHCI compatible.
Host mode:
Controller sets this bit when a connect status occurs on any port, a port enable/disable change occurs, an
over-current change occurs, or the force port resume (PORTSCn[FPR]) bit is set as the result of a J-K
transition on the suspended port.
Device mode:
The controller sets this bit when it enters the full- or high-speed operational state. When it exits the full- or
high-speed operation states due to reset or suspend events, the notification mechanisms are URI and SLI
bits respectively. The device controller detects resume signaling only.
1
UEI
USB error interrupt. When completion of USB transaction results in error condition, the controller sets this bit.
If the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set, this bit is set
along with the USBINT bit. See Section 4.15.1 in the EHCI specification for a complete list of host error interrupt
conditions. See Table 20-57 for more information on device error matrix.
0 No error.
1 Error detected.
0
UI
USB interrupt (USBINT). This bit is set by the controller when the cause of an interrupt is a completion of a USB
transaction where the TD has an interrupt on complete (IOC) bit set. This bit is also set by the controller when
a short packet is detected. A short packet is when the actual number of bytes received was less than the
expected number of bytes.
20.3.4.3
USB Interrupt Enable Register (USBINTR)
The interrupts to software are enabled with this register. An interrupt generates when a bit is set and the
corresponding interrupt is active. The USB status register (USBSTS) continues to show interrupt sources
(even if the USBINTR register disables them), allowing polling of interrupt events by the software.
Address: 0xFC0B_0148 (USBINTR)
R
Access: User read/write
31
30
29
28
27
26
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SLE
SRE
URE
AAE
SEE
FRE
PCE
UEE
UE
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
25
TIE1
TIE0
0
0
W
Reset
24
23
22
21
20
0
0
0
0
0
0
0
0
19
18
UPIE UAIE
0
0
17
0
0
16
NAKE
0
Figure 20-18. USB Interrupt Enable Register (USBINTR)
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Universal Serial Bus Interface – On-The-Go Module
Table 20-21. USBINTR Field Descriptions
Field
31–26
Description
Reserved, must be cleared.
25
TIE1
General purpose timer 1 interrupt enable. When this bit and USBSTS[GPTINT1] are set, the USB controller
issues an interrupt to the processor. The interrupt is acknowledged by clearing GPTINT1.
0 Disabled
1 Enabled
24
TIE0
General purpose timer 0 interrupt enable. When this bit and USBSTS[GPTINT0] are set, the USB controller
issues an interrupt to the processor. The interrupt is acknowledged by clearing GPTINT0.
0 Disabled
1 Enabled
23–20
Reserved, must be cleared.
19
UPIE
USB host periodic interrupt enable. When this bit and USBSTS[USBHSTPERINT] are set, the host controller
issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by clearing USBHSTPERINT.
18
UAIE
USB host asynchronous interrupt enable. When this bit and USBSTS[USBHSTASYNCINT] are set, the host
controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by clearing
USBHSTASYNCINT.
17
Reserved, must be cleared.
16
NAKE
NAK interrupt enable. When this bit and the USBSTS[NAKI] bit are set, an interrupt generates.
0 Disabled
1 Enabled
15–9
Reserved, must be cleared.
8
SLE
Sleep (DC suspend) enable. A non-EHCI bit. When this bit is set and the USBSTS[SLI] bit transitions, USB
OTG controller issues an interrupt. Software writing a 1 to the USBSTS[SLI] bit acknowledges the interrupt.
Used only in device mode.
0 Disabled
1 Enabled
7
SRE
SOF-received enable. This is a non-EHCI bit. When this bit and the USBSTS[SRI] bit are set, controller issues
an interrupt. Software clearing the USBSTS[SRI] bit acknowledges the interrupt.
0 Disabled
1 Enabled
6
URE
USB-reset enable. A non-EHCI bit. When this bit and the USBSTS[URI] bit are set, device controller issues an
interrupt. Software clearing the USBSTS[URI] bit acknowledges the interrupt. Used only in device mode.
0 Disabled
1 Enabled
5
AAE
Interrupt on async advance enable. When this bit and the USBSTS[AAI] bit are set, controller issues an
interrupt at the next interrupt threshold. Software clearing the USBSTS[AAI] bit acknowledges the interrupt.
Used only in host mode.
0 Disabled
1 Enabled
4
SEE
System error enable. When this bit and the USBSTS[SEI] bit are set, controller issues an interrupt. Software
clearing the USBSTS[SEI] bit acknowledges the interrupt.
0 Disabled
1 Enabled
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Universal Serial Bus Interface – On-The-Go Module
Table 20-21. USBINTR Field Descriptions (continued)
Field
Description
3
FRE
Frame list rollover enable. When this bit and the USBSTS[FRI] bit are set, controller issues an interrupt.
Software clearing the USBSTS[FRI] bit acknowledges the interrupt. Used only in host mode.
0 Disabled
1 Enabled
2
PCE
Port change detect enable. When this bit and the USBSTS[PCI] bit are set, controller issues an interrupt.
Software clearing the USBSTS[PCI] bit acknowledges the interrupt.
0 Disabled
1 Enabled
1
UEE
USB error interrupt enable. When this bit and the USBSTS[UEI] bit are set, controller issues an interrupt at the
next interrupt threshold. Software clearing the USBSTS[UEI] bit acknowledges the interrupt.
0 Disabled
1 Enabled
0
UE
USB interrupt enable. When this bit is 1 and the USBSTS[UI] bit is set, the USB OTG controller issues an
interrupt at the next interrupt threshold. Software clearing the USBSTS[UI] bit acknowledges the interrupt.
0 Disabled
1 Enabled
20.3.4.4
Frame Index Register (FRINDEX)
In host mode, the controller uses this register to index the periodic frame list. The register updates every
125 microseconds (once each microframe). Bits [N–3] select a particular entry in the periodic frame list
during periodic schedule execution. The number of bits used for the index depends on the size of the frame
list as set by system software in the USBCMD[FS] field.
This register must be a longword. Byte writes produce undefined results. This register cannot be written
unless the USB OTG controller is in halted state as the USBSTS[HCH] bit indicates. A write to this
register while the USBSTS[RS] bit is set produces undefined results. Writes to this register also affect the
SOF value.
In device mode, this register is read-only, and the USB OTG controller updates the FRINDEX[13–3] bits
from the frame number the SOF marker indicates. When the USB bus receives a SOF, FRINDEX[13–3]
checks against the SOF marker. If FRINDEX[13–3] is different from the SOF marker, FRINDEX[13–3]
is set to the SOF value and FRINDEX[2–0] is cleared (SOF for 1 ms frame). If FRINDEX[13–3] equals
the SOF value, FRINDEX[2–0] is incremented (SOF for 125 μsec microframe.)
Address: 0xFC0B_014C (FRINDEX)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
8
7
6
5
4
3
2
1
0
FRINDEX
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-19. Frame Index Register (FRINDEX)
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Table 20-22. FRINDEX Field Descriptions
Field
Description
31–14
13–0
FRINDEX
Reserved, must be cleared.
Frame index. The value in this register increments at the end of each time frame (microframe). Bits [N– 3] are
for the frame list current index. This means each location of the frame list is accessed 8 times per frame (once
each microframe) before moving to the next index.
In device mode, the value is the current frame number of the last frame transmitted and not used as an index.
In either mode, bits 2–0 indicate current microframe.
Table 20-23 illustrates values of N based on the value of the USBCMD[FS] field when used in host mode.
Table 20-23. FRINDEX N Values
20.3.4.5
USBCMD[FS]
Frame List Size
FRINDEX N value
000
1024 elements (4096 bytes)
12
001
512 elements (2048 bytes)
11
010
256 elements (1024 bytes)
10
011
128 elements (512 bytes)
9
100
64 elements (256 bytes)
8
101
32 elements (128 bytes)
7
110
16 elements (64 bytes)
6
111
8 elements (32 bytes)
5
Periodic Frame List Base Address Register (PERIODICLISTBASE)
This register contains the beginning address of the periodic frame list in the system memory. The host
controller driver loads this register prior to starting the schedule execution by the controller. The memory
structure referenced by this physical memory pointer assumes to be 4-Kbyte aligned. The contents
combine with the FRINDEX register to enable the controller to step through the periodic frame list in
sequence.
The host and device mode functions share this register. In host mode, it is the PERIODICLISTBASE
register; in device mode, it is the DEVICEADDR register. See Section 20.3.4.6, “Device Address Register
(DEVICEADDR),” for more information.
Address: 0xFC0B_0154 (PERIODICLISTBASE)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
PERBASE
W
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-20. Periodic Frame List Base Address Register (PERIODICLISTBASE)
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Universal Serial Bus Interface – On-The-Go Module
Table 20-24. PERIODICLISTBASE Field Descriptions
Field
Description
31–12
PERBASE
11–0
Base Address. These bits correspond to memory address signal [31:12]. Used only in the host mode
Reserved, must be cleared.
20.3.4.6
Device Address Register (DEVICEADDR)
This register is not defined in the EHCI specification. For device mode, the upper seven bits of this register
represent the device address. After any controller or USB reset, the device address is set to the default
address (0). The default address matches all incoming addresses. Software reprograms the address after
receiving a SET_ADDRESS descriptor.
The host and device mode functions share this register. In device mode, it is the DEVICEADDR register;
in host mode, it is the PERIODICLISTBASE register. See Section 20.3.4.5, “Periodic Frame List Base
Address Register (PERIODICLISTBASE),” for more information.
Address: 0xFC0B_0154 (DEVICEADDR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
USBADR
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-21. Device Address Register (DEVICEADDR)
Table 20-25. DEVICEADDR Field Descriptions
Field
Description
31–25
USBADR
24–0
Device Address. This field corresponds to the USB device address.
Reserved, must be cleared.
20.3.4.7
Current Asynchronous List Address Register (ASYNCLISTADDR)
The ASYNCLISTADDR register contains the address of the next asynchronous queue head to executed
by the host.
The host and device mode functions share this register. In host mode, it is the ASYNCLISTADDR register;
in device mode, it is the EPLISTADDR register. See Section 20.3.4.8, “Endpoint List Address Register
(EPLISTADDR),” for more information.
Address: 0xFC0B_0158 (ASYNCLISTADDR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
ASYBASE
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-22. Current Asynchronous List Address Register (ASYNCLISTADDR)
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Universal Serial Bus Interface – On-The-Go Module
Table 20-26. ASYNCLISTADDR Field Descriptions
Field
Description
31–5
ASYBASE
Link pointer low (LPL). These bits correspond to memory address signal [31:5]. This field may only reference
a queue head (QH). Used only in host mode.
4–0
Reserved, must be cleared.
20.3.4.8
Endpoint List Address Register (EPLISTADDR)
This register is not defined in the EHCI specification. For device mode, this register contains the address
of the endpoint list top in system memory. The memory structure referenced by this physical memory
pointer assumes to be 64-bytes. The queue head is actually a 48-byte structure, but must be aligned on
64-byte boundary. However, the EPBASE field has a granularity of 2 Kbytes; in practice, the queue head
should be 2-Kbyte aligned.
The host and device mode functions share this register. In device mode, it is the EPLISTADDR register;
in host mode, it is the ASYNCLISTADDR register. See Section 20.3.4.7, “Current Asynchronous List
Address Register (ASYNCLISTADDR),” for more information.
Address: 0xFC0B_0158 (EPLISTADDR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
EPBASE
W
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-23. Endpoint List Address Register (EPLISTADDR)
Table 20-27. EPLISTADDR Field Descriptions
Field
Description
31–11
EPBASE
Endpoint list address. Correspond to memory address signals [31:11] References a list of up to 32 queue heads
(i.e. one queue head per endpoint and direction). Address of the top of the endpoint list.
10–0
Reserved, must be cleared.
20.3.4.9
Host TT Asynchronous Buffer Control (TTCTRL)
Address: 0xFC0B_015C (TTCTRL)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
R 0
TTHA
9
8
7
6
5
4
3
W
Figure 20-24. Host TT Asynchronous Buffer Control (TTCTRL)
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Universal Serial Bus Interface – On-The-Go Module
Table 20-28. TTCTRL Field Descriptions
Field
Description
31
Reserved, must be cleared.
30–24
TTHA
TT Hub Address. This field is used to match against the Hub Address field in a QH or siTD to determine if the
packet is routed to the internal TT for directly attached FS/LS devices. If the hub address in the QH or siTD
does not match this address then the packet is broadcast on the high speed ports destined for a downstream
HS hub with the address in the QH or siTD.
23–0
Reserved, must be cleared.
20.3.4.10 Master Interface Data Burst Size Register (BURSTSIZE)
This register is not defined in the EHCI specification. BURSTSIZE dynamically controls the burst size
during data movement on the initiator (master) interface.
Address: 0xFC0B_0160 (BURSTSIZE)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
9
8
7
6
TXPBURST
5
4
3
2
1
0
RXPBURST
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0
Figure 20-25. Master Interface Data Burst Size (BURSTSIZE)
Table 20-29. BURSTSIZE Field Descriptions
Field
31–16
Description
Reserved, must be cleared.
15–8
TXPBURST
Programable TX burst length. Represents the maximum length of a burst in 32-bit words while moving data from
system memory to the USB bus. Must not be set to greater than 16.
7–0
RXPBURST
Programable RX burst length. This register represents the maximum length of a burst in 32-bit words while
moving data from the USB bus to system memory. Must not be set to greater than 16.
20.3.4.11 Transmit FIFO Tuning Control Register (TXFILLTUNING)
This register is not defined in the EHCI specification. The TXFILLTUNING register controls performance
tuning associated with how the module posts data to the TX latency FIFO before moving the data onto the
USB bus. The specific areas of performance include how much data to post into the FIFO and an estimate
for how long that operation takes in the target system.
Definitions:
T0 = Standard packet overhead
T1 = Time to send data payload
Ts = Total packet flight time (send-only) packet (Ts = T0 + T1)
Tff = Time to fetch packet into TX FIFO up to specified level
Tp = Total packet time (fetch and send) packet (Tp = Tff + Ts)
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Upon discovery of a transmit (OUT/SETUP) packet in the data structures, the host controller checks to
ensure Tp remains before the end of the (micro)frame. If so, it pre-fills the TX FIFO. If at anytime during
the pre-fill operation the time remaining the (micro)frame is less than Ts, packet attempt ceases and tries
at a later time. Although this is not an error condition and the module eventually recovers, a mark is made
in the scheduler health counter to mark the occurrence of a back-off event. When a back-off event is
detected, the partial packet fetched may need to be discarded from the latency buffer to make room for
periodic traffic beginning after the next SOF. Too many back-off events can waste bandwidth and power
on the system bus and should be minimized (not necessarily eliminated). The TSCHHEALTH (Tff)
parameter described below can minimize back-offs.
Address: 0xFC0B_0164 (TXFILLTUNING)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0
W
TXFIFOTHRES
0 0 0
9
8
7
TXSCHHEALTH
6
5
4
3
2
1
0
TXSCHOH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-26. Transmit FIFO Tuning Controls (TXFILLTUNING)
Table 20-30. TXFILLTUNING Field Descriptions
Field
31–22
Description
Reserved, must be cleared.
21–16
FIFO burst threshold. Controls the number of data bursts that are posted to the TX latency FIFO in host mode
TXFIFOTHRES before the packet begins on the bus. The minimum value is 2 and this value should be as low as possible to
maximize USB performance. Systems with unpredictable latency and/or insufficient bandwidth can use a
higher value where the FIFO may underrun because the data transferred from the latency FIFO to USB
occurs before it can replenish from system memory.
This value is ignored if the USBMODE[SDIS] bit is set. When the USBMODE[SDIS] bit is set, the host
controller behaves as if TXFIFOTHRES is set to its maximum value.
15–13
Reserved, must be cleared.
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Universal Serial Bus Interface – On-The-Go Module
Table 20-30. TXFILLTUNING Field Descriptions (continued)
Field
Description
12–8
Scheduler health counter. These bits increment when the host controller fails to fill the TX latency FIFO to the
TXSCHHEALTH level programmed by TXFIFOTHRES before running out of time to send the packet before the next SOF.
This health counter measures the number of times this occurs to provide feedback to selecting a proper
TXSCHOH. Writing to this register clears the counter and this counter stops counting after reaching the
maximum of 31.
7–0
TXSCHOH
Scheduler overhead. These bits add an additional fixed offset to the schedule time estimator described as Tff.
As an approximation, the value chosen for this register should limit the number of back-off events captured in
the TXSCHHEALTH field to less than 10 per second in a highly utilized bus. Choosing a value too high for this
register is not desired as it can needlessly reduce USB utilization.
The time unit represented in this register is 1.267 μs when a device connects in high-speed mode.
The time unit represented in this register is 6.333 μs when a device connects in low-/full-speed mode.
For most applications, TXSCHOH can be set to 4 or less. A good value to begin with is:
TXFIFOTHRES × ( BURSTSIZE × 4 )
-------------------------------------------------------------------------------------------40 × TimeUnit
Eqn. 20-1
Always rounded to the next higher integer. TimeUnit is 1.267 or 6.333 as noted earlier in this description. For
example, if TXFIFOTHRES is 5 and BURSTSIZE is 8, set TXSCHOH to 5×(8×4)/(40×1.267) equals 4 for a
high-speed link. If this value of TXSCHOH results in a TXSCHHEALTH count of 0 per second, low the value
by 1 if optimizing performance is desired. If TXSCHHEALTH exceeds 10 per second, raise the value by 1.
If streaming mode is disabled via the USBMODE register, treat TXFIFOTHRES as the maximum value for
purposes of the TXSCHOH calculation.
20.3.4.12 Configure Flag Register (CONFIGFLAG)
This EHCI register is not used in this implementation. A read from this register returns a constant of a
0x0000_0001 to indicate that all port routings default to this host controller.
Address: 0xFC0B_0180 (CONFIGFLAG)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11
10
9
8
7
0
0
0
0
0
0 0 0 0 0 0 0 1
6
5
4
3
2
1
0
0
0
0
0
0
0 0 0 0 0 0 0 1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-27. Configure Flag Register (CONFIGFLAG)
Table 20-31. CONFIGFLAG Field Descriptions
Field
31–0
Description
Reserved. (0x0000_0001, all port routings default to this host)
20.3.4.13 Port Status and Control Registers (PORTSCn)
The USB module contains a single PORTSC register. This register only resets when power is initially
applied or in response to a controller reset. Initial conditions of a port are:
• No device connected
• Port disabled
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If the port has port power control, this state remains until software applies power to the port by setting port
power to one.
For the USB OTG module in device mode, the USB OTG controller does not support power control. Port
control in device mode is used only for status port reset, suspend, and current connect status. It is also used
to initiate test mode or force signaling, and allows software to place the PHY into low-power suspend
mode and disable the PHY clock.
Address: 0xFC0B_0184 (PORTSC1)
31
R
PTS
W
Reset
1
1
15
14
R
0
29
28
1
0
1
0
1
13
12
11
PO
PIC
W
Reset
30
0
Access: User read/write
0
27
26
PSPD
1
10
LS
PP
0
0
25
0
23
22
0
0
0
9
8
7
6
0
21
20
19
18
PR
SUSP
FPR
0
0
0
0
0
0
0
2
5
4
3
OCC
OCA
PEC
w1c
0
w1c
0
17
16
0
0
PTC
PFSC PHCD WKOC WKDS WLCN
0
HSP
0
24
0
PE
1
1
0
CSC
CCS
w1c
0
0
Figure 20-28. Port Status and Control Register (PORTSC1)
Table 20-32. PORTSC1 Field Descriptions
Field
31–30
PTS
Description
Port transceiver select. Controls which parallel transceiver interface is selected.
00 Reserved
01 Reserved
10 Reserved
11 FS/LS on-chip transceiver
This bit is not defined in the EHCI specification.
29
Reserved, must be set.
28
Reserved, must be cleared.
27–26
PSPD
25
24
PFSC
Port speed. This read-only register field indicates the speed the port operates. This bit is not defined in the EHCI
specification.
00 Full speed
01 Low speed
10 High speed
11 Undefined
Reserved, must be cleared.
Port force full-speed connect. Disables the chirp sequence that allows the port to identify itself as a HS port. useful
for testing FS configurations with a HS host, hub, or device. Not defined in the EHCI specification.
0 Allow the port to identify itself as high speed.
1 Force the port to only connect at full speed.
This bit is for debugging purposes.
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Table 20-32. PORTSC1 Field Descriptions (continued)
Field
Description
23
PHCD
PHY low power suspend. This bit is not defined in the EHCI specification.
Host mode:
The PHY can be placed into low-power suspend when downstream device is put into suspend mode or when no
downstream device connects. Software completely controls low-power suspend.
Device mode:
For the USB OTG module in device mode, the PHY can be put into low power suspend when the device is not
running (USBCMD[RS] = 0) or suspend signaling is detected on the USB. The PHCD bit is cleared automatically
when the resume signaling is detected or when forcing port resumes.
0 Normal PHY operation.
1 Signal the PHY to enter low-power suspend mode
Reading this bit indicates the status of the PHY.
22
WKOC
Wake on over-current enable. Enables the port to be sensitive to over-current conditions as wake-up events. This
field is 0 if the PP bit is cleared. In host mode, this bit can work with an external power control circuit.
21
WKDS
Wake on disconnect enable. Enables the port to be sensitive to device disconnects as wake-up events.
This field is 0 if the PP bit is cleared or the module is in device mode. In host mode, this bit can work with an external
power control circuit.
20
WLCN
Wake on connect enable. Enables the port to be sensitive to device connects as wake-up events.
This field is 0 if the PP bit is cleared or the module is in device mode. In host mode, this can work with an external
power control circuit.
19–16
PTC
Port test control. Any value other than 0 indicates the port operates in test mode. Refer to Chapter 7 of the USB
Specification Revision 2.0 for details on each test mode.
0000 Not enabled.
0001 J_STATE
0010 K_STATE
0011 SEQ_NAK
0100 Packet
0101 FORCE_ENABLE_HS
0110 FORCE_ENABLE_FS
0111 FORCE_ENABLE_LS
Else Reserved.
Note: The FORCE_ENABLE_FS and FORCE ENABLE_LS settings are extensions to the test mode support in the
EHCI specification. Writing the PTC field to any of the FORCE_ENABLE values forces the port into the
connected and enabled state at the selected speed. Then clearing the PTC field allows the port state
machines to progress normally from that point.
15–14
PIC
Port indicator control.For this device, this feature is not implemented, therefore this field is read-only and is always
cleared.
13
PO
Port owner. Port owner handoff is not implemented in this design, therefore this bit is read-only and is always
cleared.
12
PP
Port power. Represents the current setting of the port power control switch (0 equals off, 1 equals on). When power
is not available on a port (PP = 0), it is non-functional and does not report attaches, detaches, etc.
When an over-current condition is detected on a powered port, the host controller driver from a 1to a 0 (removing
power from the port) transitions the PP bit in each affected port.
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Table 20-32. PORTSC1 Field Descriptions (continued)
Field
Description
11–10
LS
Line status. Reflects current logical levels of the USB DP (bit 11) and DM (bit 10) signal lines. In host mode, the line
status by the host controller driver is not necessary (unlike EHCI) because hardware manages the connection of FS
and LS. In device mode, LS by the device controller is not necessary.
00 SE0
01 J-state
10 K-state
11 Undefined
9
HSP
8
PR
7
SUSP
High speed port. Indicates if the host/device connected is in high speed mode.
0 FS or LS
1 HS
Note: This bit is redundant with the PSPD bit field.
Port reset. This field is cleared if the PP bit is cleared.
Host mode:
When software sets this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 starts. This
bit automatically clears after the reset sequence completes. This behavior is different from EHCI where the host
controller driver is required to clear this bit after the reset duration is timed in the driver.
Device mode:
This bit is a read-only status bit. Device reset from the USB bus is also indicated in the USBSTS register.
0 Port is not in reset.
1 Port is in reset.
Suspend
0 Port not in suspend state.
1 Port in suspend state.
Host mode:
The PE and SUSP bits define the port state as follows:
PE
SUSP
Port State
0
x
Disable
1
0
Enable
1
1
Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The
blocking occurs at the end of the current transaction if a transaction was in progress when this bit was set. In the
suspend state, the port is sensitive to resume detection. The bit status does not change until the port is
suspended and there may be a delay in suspending a port if there is a transaction currently in progress on the
USB.
The module unconditionally clears this bit when software clears the FPR bit. The host controller ignores clearing
this bit. If host software sets this bit when the port is not enabled (PE = 0), the results are undefined.
This field is cleared if the PP bit is cleared in host mode.
Device mode:
In device mode, this bit is a read-only status bit.
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Table 20-32. PORTSC1 Field Descriptions (continued)
Field
Description
6
FPR
Force Port Resume. This bit is not-EHCI compatible.
0 No resume (K-state) detected/driven on port.
1 Resume detected/driven on port.
Host mode:
Software sets this bit to drive resume signaling. The controller sets this bit if a J-to-K transition is detected while
the port is in suspend state (PE = SUSP = 1), which in turn sets the USBSTS[PCI] bit. This bit automatically
clears after the resume sequence is complete. This behavior is different from EHCI where the host controller
driver is required to clear this bit after the resume duration is timed in the driver.
When the controller owns the port, the resume sequence follows the defined sequence documented in the USB
Specification Revision 2.0. The resume signaling (full-speed K) is driven on the port as long as this bit remains
set. This bit remains set until the port switches to the high-speed idle. Clearing this bit has no affect because the
port controller times the resume operation to clear the bit the port control state switches to HS or FS idle.
This field is cleared if the PP bit is cleared in host mode.
Device mode:
After the device is in suspend state for 5 ms or more, software must set this bit to drive resume signaling before
clearing. The device controller sets this bit if a J-to-K transition is detected while port is in suspend state, which
in turn sets the USBSTS[PCI] bit. The bit is cleared when the device returns to normal operation.
5
OCC
Over-current change. Indicates a change to the OCA bit. Software clears this bit by writing a 1. For host mode, the
user can provide over-current detection to the USBn_PWRFAULT signal for this condition. For device-only
implementations, this bit must always be cleared.
0 No over-current.
1 Over-current detect.
4
OCA
Over-current active. This bit automatically transitions from 1 to 0 when the over-current condition is removed. For
host/OTG implementations, the user can provide over-current detection to the USBn_PWRFAULT signal for this
condition. For device-only implementations, this bit must always be cleared.
0 Port not in over-current condition.
1 Port currently in over-current condition.
3
PEC
Port enable/disable change. For the root hub, this bit gets set only when a port is disabled due to disconnect on the
port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification).
Software clears this by writing a 1 to it.
In device mode, the device port is always enabled. (This bit is zero).
0 No change.
1 Port disabled.
This field is cleared if the PP bit is cleared.
2
PE
Port enabled/disabled.
Host mode:
Ports can only be enabled by the controller as a part of the reset and enable sequence. Software cannot enable
a port by setting this bit. A fault condition (disconnect event or other fault condition) or host software can disable
ports. The bit status does not change until the port state actually changes. There may be a delay in disabling or
enabling a port due to other host and bus events.
When the port is disabled, downstream propagation of data is blocked except for reset. This field is cleared if the
PP bit is cleared in host mode.
Device mode:
The device port is always enabled. (This bit is set).
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Table 20-32. PORTSC1 Field Descriptions (continued)
Field
Description
1
CSC
Connect change status.
Host mode:
This bit indicates a change occurred in the port’s current connect status. The controller sets this bit for all changes
to the port device connect status, even if system software has not cleared an existing connect status change. For
example, the insertion status changes twice before system software has cleared the changed condition; hub
hardware is setting an already-set bit (i.e., the bit remains set). Software clears this bit by writing a 1 to it. This
field is cleared if the PP bit is cleared.
0 No change.
1 Connect status has changed.
In device mode, this bit is undefined.
0
CCS
Current connect status. Indicates that a device successfully attaches and operates in high speed or full speed as
indicated by the PSPD bit. If clear, the device did not attach successfully or forcibly disconnects by the software
clearing the USBCMD[RUN] bit. It does not state the device disconnected or suspended. This field is cleared if the
PP bit is cleared in host mode.
0 No device present (host mode) or attached (device mode)
1 Device is present (host mode) or attached (device mode)
20.3.4.14 On-the-Go Status and Control Register (OTGSC)
This register is not defined in the EHCI specification. The host controller implements one OTGSC register
corresponding to port 0 of the host controller.
The OTGSC register has four sections:
• OTG interrupt enables (read/write)
• OTG interrupt status (read/write to clear)
• OTG status inputs (read-only)
• OTG controls (read/write)
The status inputs de-bounce using a 1 ms time constant. Values on the status inputs that do not persist for
more than 1 ms do not cause an update of the status inputs or an OTG interrupt.
Address: 0xFC0B_01A4 (OTGSC)
31
R
0
W
Reset
0
15
R
0
30
29
28
Access: User read/write
27
26
25
24
DPIE 1MSE BSEIE BSVIE ASVIE AVVIE IDIE
0
0
14
13
DPS 1MST
0
0
0
0
0
23
0
0
22
0
0
0
20
19
18
17
16
DPIS 1MSS BSEIS BSVIS ASVIS AVVIS IDIS
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
1
0
0
0
0
0
5
4
3
2
1
0
VC
VD
0
0
12
11
10
9
8
7
6
BSE
BSV
ASV
AVV
ID
0
0
1
0
0
0
0
0
0
W
Reset
21
IDPU
DP
OT
1
0
0
0
0
Figure 20-29. On-the-Go Status and Control Register (OTGSC)
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Table 20-33. OTGSC Field Descriptions
Field
Description
31
Reserved, must be cleared.
30
DPIE
Data pulse interrupt enable.
0 Disable
1 Enable
29
1MSE
1 millisecond timer interrupt enable.
0 Disable
1 Enable
28
BSEIE
B session end interrupt enable.
0 Disable
1 Enable
27
BSVIE
B session valid interrupt enable.
0 Disable
1 Enable
26
ASVIE
A session valid interrupt enable.
0 Disable
1 Enable
25
AVVIE
A VBUS valid interrupt enable.
0 Disable
1 Enable
24
IDIE
23
USB ID interrupt enable.
0 Disable
1 Enable
Reserved, must be cleared.
22
DPIS
Data pulse interrupt status. Indicates when data bus pulsing occurs on DP or DM. Data bus pulsing only detected
when USBMODE[CM] equals 11 and PORTSC0[PP] is cleared. Software must write a 1 to clear this bit.
21
1MSS
1 millisecond timer interrupt status. This bit is set once every millisecond. Software must write a 1 to clear this bit.
20
BSEIS
B session end interrupt status. Indicates when VBUS falls below the B session end threshold. Software must write
a 1 to clear this bit.
19
BSVIS
B session valid interrupt status. Indicates when VBUS rises above or falls below the B session valid threshold (0.8
VDC). Software must write a 1 to clear this bit.
18
ASVIS
A session valid interrupt status. Indicates when VBUS rises above or falls below the A session valid threshold (0.8
VDC). Software must write a 1 to clear this bit.
17
AVVIS
A VBUS valid interrupt status. Indicates when VBUS rises above or falls below the VBUS valid threshold (4.4
VDC) on an A device. Software must write a 1 to clear this bit.
16
IDIS
USB ID interrupt status. Indicates when a change on the ID input is detected. Software must write a 1 to clear this
bit.
15
Reserved, must be cleared.
14
DPS
Data bus pulsing status.
0 No pulsing on port.
1 Pulsing detected on port.
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Table 20-33. OTGSC Field Descriptions (continued)
Field
13
1MST
Description
1 millisecond timer toggle. This bit toggles once per millisecond.
12
BSE
B session end.
0 VBus is above B session end threshold.
1 VBus is below B session end threshold.
11
BSV
B Session valid.
0 VBus is below B session valid threshold.
1 VBus is above B session valid threshold.
10
ASV
A Session valid.
0 VBus is below A session valid threshold.
1 VBus is above A session valid threshold.
9
AVV
A VBus valid.
0 VBus is below A VBus valid threshold.
1 VBus is above A VBus valid threshold.
8
ID
7–6
5
IDPU
USB ID.
0 A device.
1 B device.
Reserved, must be cleared.
ID Pull-up. Provides control over the ID pull-up resistor.
0 Disable pull-up. ID input not sampled.
1 Enable pull-up.
4
DP
Data pulsing.
0 The pull-up on DP is not asserted.
1 The pull-up on DP is asserted for data pulsing during SRP.
3
OT
OTG Termination. This bit must be set with the OTG module in device mode.
0 Disable pull-down on DM.
1 Enable pull-down on DM.
2
Reserved, must be cleared.
1
VC
VBUS charge. Setting this bit causes the VBUS line to charge. This is used for VBus pulsing during SRP.
0
VD
VBUS discharge. Setting this bit causes VBUS to discharge through a resistor.
20.3.4.15 USB Mode Register (USBMODE)
This register is not defined in the EHCI specification. It controls the operating mode of the module.
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Address: 0xFC0B_01A8 (USBMODE)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
SDIS SLOM
0
0
ES
0
CM
0
0
Figure 20-30. USB Mode Register (USBMODE)
Table 20-34. USBMODE Field Descriptions
Field
Description
31–5
Reserved, must be cleared.
4
SDIS
Stream disable.
0 Inactive.
1 Active.
Host mode:
Setting this bit ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems
where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the
effect of ensuring the TX latency fills to capacity before the packet launches onto the USB.
Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to
characterize the adjustments needed for the scheduler when using this feature.
Also, in systems with high system bus utilization, setting this bit ensures no overruns or underruns during
operation at the expense of link utilization. SDIS can be left clear and the rules under the description of the
TXFILLTUNING register can limit underruns/overruns for those who desire optimal link performance.
Device mode:
Setting this bit disables double priming on RX and TX for low bandwidth systems. This mode ensures that when
the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is
disabled to prevent overruns/underruns in bandwidth limited systems.
In high-speed mode, all packets received are responded to with a NYET handshake when stream disable is
active.
3
SLOM
Setup lockout mode. For the module in device mode, this bit controls behavior of the setup lock mechanism. See
Section 20.5.3.4.4, “Control Endpoint Operation.”
0 Setup lockouts on.
1 Setup lockouts off (software requires use of the USBCMD[SUTW] bit).
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Table 20-34. USBMODE Field Descriptions (continued)
Field
Description
2
ES
Endian select. Controls the byte ordering of the transfer buffers to match the host microprocessor bus architecture.
The bit fields in the register interface and the DMA data structures (including the setup buffer within the device QH)
are unaffected by the value of this bit, because they are based upon 32-bit words.
0 Little endian. First byte referenced in least significant byte of 32-bit word.
1 Big endian. First byte referenced in most significant byte of 32-bit word.
Note: For proper operation, this bit must be set for this ColdFire device.
1–0
CM
Controller mode. This register can be written only once after reset. If necessary to switch modes, software must
reset the controller by writing to the USBCMD[RST] bit before reprogramming this register.
00 Idle (default for the USB OTG module)
01 Reserved
10 Device controller
11 Host controller
Note: The USB OTG module must be initialized to the desired operating mode after reset.
20.3.4.16 Endpoint Setup Status Register (EPSETUPSR)
This register is not defined in the EHCI specification. This register contains the endpoint setup status and
is used only in device mode.
Address: 0xFC0B_01AC (EPSETUPSR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
3
1
0
EPSETUPSTAT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2
0
0
0
0
Figure 20-31. Endpoint Setup Status Register (EPSETUPSR)
Table 20-35. EPSETUPSR Field Descriptions
Field
31–4
3–0
EPSETUPSTAT
Description
Reserved, must be cleared.
Setup endpoint status. For every setup transaction received, a corresponding bit in this field is set.
Software must clear or acknowledge the setup transfer by writing a 1 to a respective bit after it has read
the setup data from the queue head. The response to a setup packet, as in the order of operations and
total response time, is crucial to limit bus time outs while the setup lockout mechanism engages.
20.3.4.17 Endpoint Initialization Register (EPPRIME)
This register is not defined in the EHCI specification. This register is used to initialize endpoints and is
used only in device mode.
Address: 0xFC0B_01B0 (EPPRIME)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
6
5
4
0 0 0 0 0 0 0 0 0 0
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
R 0 0 0 0 0 0 0 0 0 0 0 0
W
PETB
9
8
7
3
2
1
0
PERB
0
0
0
0
Figure 20-32. Endpoint Initialization Register (EPPRIME)
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Table 20-36. EPPRIME Field Descriptions
Field
Description
31–20
Reserved, must be cleared.
19–16
PETB
Prime endpoint transmit buffer. For each endpoint, a corresponding bit requests that a buffer be prepared for a
transmit operation to respond to a USB IN/INTERRUPT transaction. Software must write a 1 to the corresponding
bit when posting a new transfer descriptor to an endpoint. Hardware automatically uses this bit to begin parsing for
a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware clears this bit when
associated endpoint(s) is (are) successfully primed.
Note: These bits are momentarily set by hardware during hardware re-priming operations when a dTD retires, and
the dQH updates.
15–4
Reserved, must be cleared.
3–0
PERB
Prime endpoint receive buffer. For each endpoint, a corresponding bit requests that a buffer be prepared for a
receive operation to respond to a USB OUT transaction. Software must write a 1 to the corresponding bit when
posting a new transfer descriptor to an endpoint. Hardware automatically uses this bit to begin parsing for a new
transfer descriptor from the queue head and prepare a receive buffer. Hardware clears this bit when associated
endpoint(s) is (are) successfully primed.
Note: These bits are momentarily set by hardware during hardware re-priming operations when a dTD retires, and
the dQH updates.
20.3.4.18 Endpoint Flush Register (EPFLUSH)
This register is not defined in the EHCI specification. This register used only in device mode.
Address: 0xFC0B_01B4 (EPFLUSH)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
6
5
4
0 0 0 0 0 0 0 0 0 0
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
R 0 0 0 0 0 0 0 0 0 0 0 0
W
FETB
9
8
7
3
2
1
0
FERB
0
0
0
0
Figure 20-33. Endpoint Flush Register (EPFLUSH)
Table 20-37. EPFLUSH Field Descriptions
Field
Description
31–20
Reserved, must be cleared.
19–16
FETB
Flush endpoint transmit buffer. Writing a 1 to a bit in this field causes the associated endpoint to clear any primed
buffers. If a packet is in progress for an associated endpoint, that transfer continues until completion. Hardware
clears this register after the endpoint flush operation is successful.
15–4
Reserved, must be cleared.
3–0
FERB
Flush endpoint receive buffer. Writing a 1 to a bit in this field causes the associated endpoint to clear any primed
buffers. If a packet is in progress for an associated endpoint, that transfer continues until completion. Hardware
clears this register after the endpoint flush operation is successful. FERB[3] corresponds to endpoint 3.
20.3.4.19 Endpoint Status Register (EPSR)
This register is not defined in the EHCI specification. This register is only used in device mode.
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Address: 0xFC0B_01B8 (EPSR)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
6
5
4
0 0 0 0 0 0 0 0 0 0
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
R 0 0 0 0 0 0 0 0 0 0 0 0
ETBR
9
8
7
3
2
1
0
ERBR
W
0
0
0
0
Figure 20-34. Endpoint Status Register (EPSR)
Table 20-38. EPSR Field Descriptions
Field
Description
31–20
Reserved, must be cleared.
19–16
ETBR
Endpoint transmit buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. The
hardware sets this bit in response to receiving a command from a corresponding bit in the EPPRIME register. A
constant delay exists between setting a bit in the EPPRIME register and endpoint indicating ready. This delay time
varies based upon the current USB traffic and the number of bits set in the EPPRIME register. USB reset, USB DMA
system, or EPFLUSH register clears the buffer ready. ETBR[3] (bit 19) corresponds to endpoint 3.
Note: Hardware momentarily clears these bits during hardware endpoint re-priming operations when a dTD is
retired, and the dQH is updated.
15–4
Reserved, must be cleared.
3–0
ERBR
Endpoint receive buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. The
hardware sets this bit in response to receiving a command from a corresponding bit in the EPPRIME register. A
constant delay exists between setting a bit in the EPPRIME register and endpoint indicating ready. This delay time
varies based upon the current USB traffic and the number of bits set in the EPPRIME register. USB reset, USB DMA
system, or EPFLUSH register clears the buffer ready. ERBR[3] (bit 19) corresponds to endpoint 3.
Note: Hardware momentarily clears these bits during hardware endpoint re-priming operations when a dTD is
retired, and the dQH is updated.
20.3.4.20 Endpoint Complete Register (EPCOMPLETE)
This register is not defined in the EHCI specification. This register is used only in device mode.
Address: 0xFC0B_01BC (EPCOMPLETE)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0 0 0 0 0 0 0 0 0 0 0 0
W
ETCE
9
8
7
6
5
4
0 0 0 0 0 0 0 0 0 0 0 0
w1c
3
2
1
0
ERCE
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-35. Endpoint Complete Register (EPCOMPLETE)
Table 20-39. EPCOMPLETE Field Descriptions
Field
Description
31–20
Reserved, must be cleared.
19–16
ETCE
Endpoint transmit complete event. Each bit indicates a transmit event (IN/INTERRUPT) occurs and software must
read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the
transfer descriptor, this bit is set simultaneously with the USBINT. Writing a 1 clears the corresponding bit in this
register. ETCE[3] (bit 19) corresponds to endpoint 3.
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Table 20-39. EPCOMPLETE Field Descriptions (continued)
Field
Description
15–4
Reserved, must be cleared
3–0
ERCE
Endpoint receive complete event. Each bit indicates a received event (OUT/SETUP) occurs and software must
read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the
transfer descriptor, this bit is set simultaneously with the USBINT. Writing a 1 clears the corresponding bit in this
register. ERCE[3] corresponds to endpoint 3.
20.3.4.21 Endpoint Control Register 0 (EPCR0)
This register is not defined in the EHCI specification. Every device implements endpoint 0 as a control
endpoint.
Address: 0xFC0B_01C0 (EPCR0)
31 30 29 28 27 26 25 24
Access: User read/write
23
22 21 20 19 18 17
R 0 0 0 0 0 0 0 0 TXE 0 0 0
TXT
0
W
Reset 0 0 0 0 0 0 0 0
1
0 0 0 0 0 0
16
TXS
0
15 14 13 12 11 10
9
8
7
6
5
4
0 0 0 0 0 0 0 0 RXE 0 0 0
0 0 0 0 0 0 0 0
1
3
2
1
RXT
0
0 0 0 0 0 0
0
RXS
0
Figure 20-36. Endpoint Control 0 (EPCR0)
Table 20-40. EPCR0 Field Descriptions
Field
31–24
23
TXE
Description
Reserved, must be cleared.
TX endpoint enable. Endpoint zero is always enabled.
1 Enable
22–20
Reserved, must be cleared.
19–18
TXT
TX endpoint type. Endpoint zero is always a control endpoint.
00 Control
17
Reserved, must be cleared.
16
TXS
TX endpoint stall. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host.
It continues returning STALL until software clears the bit or it automatically clears upon receipt of a new SETUP
request.
0 Endpoint OK
1 Endpoint stalled
15–8
Reserved, must be cleared.
7
RXE
RX endpoint enable. Endpoint zero is always enabled.
1 Enabled.
6–4
Reserved, must be cleared.
3–2
RXT
RX endpoint type. Endpoint zero is always a control endpoint.
00 Control
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Table 20-40. EPCR0 Field Descriptions (continued)
Field
Description
1
Reserved, must be cleared.
0
RXS
RX endpoint stall. Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host.
It continues returning STALL until software clears the bit or it automatically clears upon receipt of a new SETUP
request.
0 Endpoint OK
1 Endpoint stalled
20.3.4.22 Endpoint Control Register n (EPCRn)
These registers are not defined in the EHCI specification. There is an EPCRn register for each endpoint in
a device.
Address: 0xFC0B_01C4 (EPCR1)
0xFC0B_01C8 (EPCR2)
0xFC0B_01CA (EPCR3)
R
Access: User read/write
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
W
Reset
R
0
0
0
0
0
0
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
0
TXE
0
0
9
8
7
0
0
W
Reset
23
0
0
RXE
0
22
0
TXR
21
TXI
0
0
6
5
0
RXR
0
RXI
0
20
19
0
18
TXT
17
16
TXD
TXS
0
0
0
0
0
4
3
2
1
0
RXD
RXS
0
0
0
0
RXT
0
0
Figure 20-37. Endpoint Control Registers (EPCRn)
Table 20-41. EPCRn Field Descriptions
Field
31–24
Description
Reserved, must be cleared.
23
TXE
TX endpoint enable.
0 Disabled
1 Enabled
22
TXR
TX data toggle reset. When a configuration event is received for this Endpoint, software must write a 1 to this bit
to synchronize the data PID’s between the host and device. This bit is self-clearing.
21
TXI
TX data toggle inhibit. This bit is used only for test and should always be written as 0. Writing a 1 to this bit causes
this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet.
0 PID sequencing enabled.
1 PID sequencing disabled.
20
Reserved, must be cleared.
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Table 20-41. EPCRn Field Descriptions (continued)
Field
Description
19–18
TXT
TX endpoint type.
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
17
TXD
TX endpoint data source. This bit should always be written as 0, which selects the dual port memory/DMA engine
as the source.
16
TXS
TX endpoint stall. This bit sets automatically upon receipt of a SETUP request if this endpoint is not configured as
a control endpoint. It clears automatically upon receipt of a SETUP request if this endpoint is configured as a
control endpoint.
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host. It continues
returning STALL until software clears this bit clears or automatically clears as above.
0 Endpoint OK
1 Endpoint stalled
15–8
Reserved, must be cleared.
7
RXE
RX endpoint enable.
0 Disabled
1 Enabled
6
RXR
RX data toggle reset. When a configuration event is received for this endpoint, software must write a 1 to this bit
to synchronize the data PIDs between the host and device. This bit is self-clearing.
5
RXI
RX data toggle inhibit. This bit is only for testing and should always be written as 0. Writing a 1 to this bit causes
this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.
0 PID sequencing enabled
1 PID sequencing disabled
4
Reserved, must be cleared.
3–2
RXT
RX endpoint type.
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
1
RXD
RX endpoint data sink. This bit should always be written as 0, which selects the dual port memory/DMA engine
as the sink.
0
RXS
RX endpoint stall. This bit sets automatically upon receipt of a SETUP request if this endpoint is not configured
as a control endpoint. It clears automatically upon receipt of a SETUP request if this endpoint is configured as a
control endpoint,
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host. It continues
returning STALL until software clears this bit or automatically clears as above,
0 Endpoint OK
1 Endpoint stalled
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20.4
Functional Description
This module can be broken down into functional sub-blocks as described below.
20.4.1
System Interface
The system interface block contains all the control and status registers to allow a core to interface to the
module. These registers allow the processor to control the configuration and ascertain the capabilities of
the module and, they control the module’s operation.
20.4.2
DMA Engine
The USB module contains a local DMA engine. It is responsible for moving all of the data transferred over
the USB between the module and system memory. Like the system interface block, the DMA engine block
uses a simple synchronous bus signaling protocol.
The DMA controllers must access control information and packet data from system memory. Control
information is contained in link list based queue structures. The DMA controllers have state machines able
to parse data structures defined in the EHCI specification. In host mode, the data structures are EHCI
compliant and represent queues of transfers performed by the host controller, including the
split-transaction requests that allow an EHCI controller to direct packets to FS and LS speed devices. In
device mode, data structures are similar to those in the EHCI specification and used to allow device
responses to be queued for each of the active pipes in the device.
20.4.3
FIFO RAM Controller
The FIFO RAM controller is used for context information and to control FIFOs between the protocol
engine and the DMA controller. These FIFOs decouple the system processor/memory bus requests from
the extremely tight timing required by USB.
The use of the FIFO buffers differs between host and device mode operation. In host mode, a single data
channel maintains in each direction through the buffer memory. In device mode, multiple FIFO channels
maintain for each of the active endpoints in the system.
In host mode, the USB OTG modules use 16-byte transmit buffers and 16-byte receive buffers. For the
USB OTG module, device operation uses a single 16-byte receive buffer and a 16-byte transmit buffer for
each endpoint.
20.4.4
Physical Layer (PHY) Interface
Readers should familiarize themselves with chapter 7 of the Universal Serial Bus Specification, Revision
2.0. The USB OTG modules contain an on-chip digital to analog transceiver (XCVR) for DP and DN USB
network communication. The USB module defaults to FS XCVR operation and can communicate in LS.
Due to pin-count limitations the USB module only supports certain combinations of PHY interfaces and
USB functionality. Refer to the Table 20-42 for more information.
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Table 20-42. USB Network Speed and Required Physical Interface
USB Mode and Speed
DP and DN
On-Chip Analog
XCVR Active
USB Host FS/LS
Yes
No
Yes See Section 20.4.4.1, “USB On-Chip Transceiver
Required External Components”
USB Device FS
Yes
No
Yes See Section 20.4.4.1, “USB On-Chip Transceiver
Required External Components”
20.4.4.1
I2C FEC
External Integrated Circuit Required
USB On-Chip Transceiver Required External Components
USB system operation does not require external components. However, the recommended method ensures
driver output impedance, eye diagram, and VBUS cable fault tolerance requirements are met. The
recommended method is for the DM and DP I/O pads to connect through series resistors (approximately
33 Ω each) to the USB connector on the application printed circuit board (PCB). Additionally, signal
quality optimizes when these 33 Ω resistors are mounted close to the processor rather than closer to the
USB board level connector.
NOTE
Internal pull-down resistors are included that keep the DP and DM ports in
a known quiescent state when the USB port is not used or when a USB cable
is not connected.
Also included is an internal 1.5k Ω pull-up resistor on DP controlled by the
CCM. (See Chapter 9, “Chip Configuration Module (CCM),” for more
details.) This allows the OTG module to operate in full-speed device
operation. Host operation requires this internal resistor to be disabled via the
CCM, and 15k Ω external resistors to connect from DP and DM signals to
ground.
20.5
Initialization/Application Information
20.5.1
Host Operation
Enhanced Host Controller Interface (EHCI) Specification defines the general operational model for the
USB module in host mode. The EHCI specification describes the register-level interface for a host
controller for USB Revision 2.0. It includes a description of the hardware/software interface between
system software and host controller hardware. The next section has information about the initialization of
the USB modules; however, full details of the EHCI specification are beyond the scope of this document.
20.5.1.1
Host Controller Initialization
After initial power-on or module reset (via the USBCMD[RST] bit), all of the operational registers are at
default values, as illustrated in the register memory map in Table 20-4.
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To initialize the host controller, software must:
1. Optionally set streaming disable in the USBMODE[SDIS] bit.
2. Optionally modify the BURSTSIZE register.
3. Optionally write the appropriate value to the USBINTR register to enable the desired interrupts.
4. Set the USBMODE[CM] field to enable host mode, and set the USBMODE[ES] bit for big endian
operation.
5. Write the USBCMD register to set the desired interrupt threshold, frame list size (if applicable),
and turn the controller on by setting the USBCMD[RS] bit.
6. Enable external VBUS supply. The exact steps required for initialization depend on the external
hardware used to supply the 5V VBUS power.
7. Set the PORTSC[PP] bit.
At this point, the host controller is up and running and the port registers begin reporting device connects.
System software can enumerate a port through the reset process (port is in the enabled state).
To communicate with devices via the asynchronous schedule, system software must write the
ASYNCLISTADDR register with the address of a control or bulk queue head. Software must then enable
the asynchronous schedule by setting the asynchronous schedule enable (ASE) bit in the USBCMD
register. To communicate with devices via the periodic schedule, system software must enable the periodic
schedule by setting the periodic schedule enable (PSE) bit in the USBCMD register. Schedules can be
turned on before the first port is reset and enabled.
Any time the USBCMD register is written, system software must ensure the appropriate bits are preserved,
depending on the intended operation.
20.5.2
Device Data Structures
This section defines the interface data structures used to communicate control, status, and data between
device controller driver (DCD) software and the device controller.The interface consists of device queue
heads and transfer descriptors.
NOTE
Software must ensure that data structures do not span a 4K-page boundary.
The USB OTG uses an array of device endpoint queue heads to organize device transfers. As shown in
Figure 20-38, there are two endpoint queue heads in the array for each device endpoint—one for IN and
one for OUT. The EPLISTADDR provides a pointer to the first entry in the array.
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ENDPOINTLISTADDR
Endpoint Queue Heads
(up to 8 elements)
Endpoint QH0 - Out
Transfer Buffer
Pointer
Transfer
Buffer
Endpoint QH0 - In
Transfer Buffer
Pointer
Transfer
Buffer
Transfer
Buffer
Endpoint QH1 - Out
Endpoint
Transfer
Descriptors
Transfer
Buffer
Figure 20-38. End Point Queue Head Organization
20.5.2.1
Endpoint Queue Head
All transfers are managed in the device endpoint queue head (dQH). The dQH is a 48-byte data structure,
but must align on 64-byte boundaries. During priming of an endpoint, the dTD (device transfer descriptor)
copies into the overlay area of the dQH, which starts at the nextTD pointer longword and continues
through the end of the buffer pointers longwords. After a transfer is complete, the dTD status longword
updates in the dTD pointed to by the currentTD pointer. While a packet is in progress, the overlay area of
the dQH acts as a staging area for the dTD so the device controller can access needed information with
minimal latency.
Figure 20-39 shows the endpoint queue head structure.
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31 30
29
28 27 26 25 24 23 22 21 20 19 18 17 16
Mult ZLT 0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
offset
0
0
0
0
0
0
0
0
0
0
0
0
0x00
Current dTD Pointer
0
0
0
0
0
0x04
Next dTD Pointer
0
0
0
0
T
0x081
Maximum Packet Length
14 13 12
IOS 0
Total Bytes
0
15
IOC 0
0
0
0
0 MultO 0
0
Status
0x0C1
Buffer Pointer (Page 0)
Current Offset
0x101
Buffer Pointer (Page 1)
Reserved
0x141
Buffer Pointer (Page 2)
Reserved
0x181
Buffer Pointer (Page 3)
Reserved
0x1C1
Buffer Pointer (Page 4)
Reserved
0x201
Reserved
0x24
Setup Buffer Bytes 3–0
0x28
Setup Buffer Bytes 7–4
0x2C
Device controller read/write; all others read-only.
Figure 20-39. Endpoint Queue Head Layout
1
Offsets 0x08 through 0x20 contain the transfer overlay.
20.5.2.1.1
Endpoint Capabilities/Characteristics (Offset = 0x0)
This longword specifies static information about the endpoint. In other words, this information does not
change over the lifetime of the endpoint. DCD software must not attempt to modify this information while
the corresponding endpoint is enabled.
Table 20-43. Endpoint Capabilities/Characteristics
Field
31–30
Mult
Description
Mult. This field indicates the number of packets executed per transaction description as given by:
00 Execute N Transactions as demonstrated by the USB variable length packet protocol where N computes
using the Maximum Packet Length (dQH) and the Total Bytes field (dTD)
01 Execute 1 Transaction.
10 Execute 2 Transactions.
11 Execute 3 Transactions.
Note: Non-ISO endpoints must set Mult equal to 00. ISO endpoints must set Mult equal to 01, 10, or 11 as
needed.
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Table 20-43. Endpoint Capabilities/Characteristics (continued)
Field
Description
29
ZLT
Zero length termination select. This bit is ignored in isochronous transfers.
Clearing this bit enables the hardware to automatically append a zero length packet when the following
conditions are true:
• The packet transmitted equals maximum packet length
• The dTD has exhausted the field Total Bytes
After this the dTD retires. When the device is receiving, if the last packet length received equals the maximum
packet length and the total bytes is zero, it waits for a zero length packet from the host to retire the current dTD.
Setting this bit disables the zero length packet. When the device is transmitting, the hardware does not append
any zero length packet. When receiving, it does not require a zero length packet to retire a dTD whose last packet
was equal to the maximum packet length packet. The dTD is retired as soon as Total Bytes field goes to zero,
or a short packet is received.
0 Enable zero length packet (default).
1 Disable the zero length packet.
Note: Each transfer is defined by one dTD, so the zero length termination is for each dTD. In some software
application cases, the logic transfer does not fit into only one dTD, so it does not make sense to add a zero
length termination packet each time a dTD is consumed. On those cases we recommend to disable the
ZLT feature, and use software to generate the zero length termination.
28–27
Reserved. Reserved for future use and must be cleared.
26–16
Maximum packet length. This directly corresponds to the maximum packet size of the associated endpoint
Maximum
(wMaxPacketSize). The maximum value this field may contain is 0x400 (1024).
Packet Length
15
IOS
Interrupt on setup (IOS). This bit used on control type endpoints indicates if USBSTS[UI] is set in response to a
setup being received.
14–0
Reserved. Reserved for future use and must be cleared.
20.5.2.1.2
Current dTD Pointer (Offset = 0x4)
The device controller uses the current dTD pointer to locate transfer in progress. This word is for USB
OTG (hardware) use only and should not be modified by DCD software.
Table 20-44. Current dTD Pointer
Field
Description
31–5
Current dtd. This field is a pointer to the dTD represented in the transfer overlay area. This field is modified by the
Current dtd device controller to next dTD pointer during endpoint priming or queue advance.
4–0
20.5.2.1.3
Reserved. Reserved for future use and must be cleared.
Transfer Overlay (Offset = 0x8–0x20)
The seven longwords in the overlay area represent a transaction working space for the device controller.
The general operational model is that the device controller can detect whether the overlay area contains a
description of an active transfer. If it does not contain an active transfer, it does not read the associated
endpoint.
After an endpoint is readied, the dTD is copied into this queue head overlay area by the device controller.
Until a transfer expires, software must not write the queue head overlay area or the associated transfer
descriptor. When the transfer is complete, the device controller writes the results back to the original
transfer descriptor and advance the queue.
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See Section 20.5.2.2, “Endpoint Transfer Descriptor (dTD),” for a description of the overlay fields.
20.5.2.1.4
Setup Buffer (Offset = 0x28–0x2C)
The set-up buffer is dedicated storage for the 8-byte data that follows a set-up PID. Refer to
Section 20.5.3.4.4, “Control Endpoint Operation” for information on the procedure for reading the setup
buffer
NOTE
Each endpoint has a TX and an RX dQH associated with it, and only the RX
queue head receives setup data packets.
Table 20-45. Multiple Mode Control
longword
Field
Description
1
31–0
Setup Buffer 0. This buffer contains bytes 3 to 0 of an incoming setup buffer packet and is written
Setup Buffer 0 by the device controller software reads.
2
31–0
Setup Buffer 1. This buffer contains bytes 7 to 4 of an incoming setup buffer packet and is written
Setup Buffer 1 by the device controller software reads.
20.5.2.2
Endpoint Transfer Descriptor (dTD)
The dTD describes to the device controller the location and quantity of data sent/received for a given
transfer. The DCD software should not attempt to modify any field in an active dTD except the next dTD
pointer, which must be modified only as described in Section 20.5.3.6, “Managing Transfers with Transfer
Descriptors.”
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15
14 13 12 11 10
9
8
7
6
5
Next dTD Pointer
0
Total Bytes
ioc 0
0
0 MultO 0
0
Buffer Pointer (Page 0)
4
3
2
1
0
offset
0
0
0
0
T
0x00
Status
0x04
Current Offset
0x08
Buffer Pointer (Page 1)
0
Frame Number
0x0C
Buffer Pointer (Page 2)
0
0
0
0
0
0
0
0
0
0
0
0
0x10
Buffer Pointer (Page 3)
0
0
0
0
0
0
0
0
0
0
0
0
0x14
Buffer Pointer (Page 4)
0
0
0
0
0
0
0
0
0
0
0
0
0x18
Device controller read/write; all others read-only.
Figure 20-40. Endpoint Transfer Descriptor (dTD)
20.5.2.2.1
Next dTD Pointer (Offset = 0x0)
The next dTD pointer is used to point the device controller to the next dTD in the linked list.
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Table 20-46. Next dTD Pointer
Field
Description
31–5
Next dTD
pointer
Next dTD pointer. This field contains the physical memory address of the next dTD to be processed. The field
corresponds to memory address signals [31:5], respectively.
4–1
0
T
20.5.2.2.2
Reserved. Reserved for future use and must be cleared.
Terminate. This bit indicates to the device controller no more valid entries exist in the queue.
0=Pointer is valid (points to a valid transfer element descriptor).
1=pointer is invalid.
dTD Token (Offset = 0x4)
The dTD token is used to specify attributes for the transfer including the number of bytes to read or write
and the status of the transaction.
Table 20-47. dTD Token
Field
31
Description
Reserved. Reserved for future use and must be cleared.
30–16
Total bytes. This field specifies the total number of bytes moved with this transfer descriptor. This field decrements
Total Bytes by the number of bytes actually moved during the transaction and only on the successful completion of the
transaction.
The maximum value software may store in the field is 5*4K(0x5000). This is the maximum number of bytes 5 page
pointers can access. Although possible to create a transfer up to 20K, this assumes the first offset into the first
page is 0. When the offset cannot be predetermined, crossing past the fifth page can be guaranteed by limiting
the total bytes to 16K**. Therefore, the maximum recommended transfer is 16K (0x4000).
Note: Larger transfer sizes can be supported, but require disabling ZLT and using multiple dTDs.
If the value of the field is 0 when the host controller fetches this transfer descriptor (and the active bit is set), the
device controller executes a zero-length transaction and retires the transfer descriptor.
For IN transfers it is not a requirement for total bytes to transfer be an even multiple of the maximum packet length.
If software builds such a transfer descriptor for an IN transfer, the last transaction is always less than maximum
packet length.
For OUT transfers the total bytes must be evenly divisible by the maximum packet length.
15
IOC
14–12
Interrupt on complete. Indicates if USBSTS[UI] is set in response to device controller finished with this dTD.
Reserved. Reserved for future use and must be cleared.
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Table 20-47. dTD Token (continued)
Field
Description
11–10
MultO
Multiplier Override. This field can possibly transmit-ISOs ( ISO-IN) to override the multiplier in the QH. This field
must be 0 for all packet types not transmit-ISO.
For example, if QH.MULT equals 3; Maximum packet size equals 8; Total Bytes equals 15; MultiO equals 0
[default], then three packets are sent: {Data2(8); Data1(7); Data0(0)}.
If QH.MULT equals 3; Maximum packet size equals 8; Total Bytes equals 15; MultO equals 2, then two packets
are sent: {Data1(8); Data0(7)}
For maximal efficiency, software must compute MultO equals greatest integer of (Total Bytes / Max. Packet Size)
except for the case when Total Bytes equals 0; then MultO must be 1.
Note: Non-ISO and Non-TX endpoints must set MultO equals 00.
9–8
7–0
Status
Reserved. Reserved for future use and must be cleared.
Status. Device controller communicates individual command execution states back to the DCD software. This field
contains the status of the last transaction performed on this dTD. The bit encodings are:
Bit
7
Active. Set by software to enable the execution of transactions by the device controller.
6
Halted. Set by the device controller during status updates to indicate a serious error has
occurred at the device/endpoint addressed by this dTD. Any time a transaction results in the
halted bit being set, the active bit is also cleared.
5
Data Buffer Error. Set by the device controller during status update to indicate the device
controller is unable to maintain the reception of incoming data (overrun) or is unable to supply
data fast enough during transmission (under run).
4
Reserved.
3
Transaction Error. Set by the device controller during status update in case the device did not
receive a valid response from the host (time-out, CRC, bad PID).
2–0
20.5.2.2.3
Status Field Description
Reserved.
dTD Buffer Page Pointer List (Offset = 0x8–0x18)
The last five longwords of a device element transfer descriptor are an array of physical memory address
pointers. These pointers reference the individual pages of a data buffer.
Table 20-48. Buffer Page Pointer List
Field
Description
31–12
Buffer Pointer
Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems typically
set the buffer pointers to a series of incrementing integers.
0;11–0
Current Offset
Current Offset. Offset into the 4kB buffer where the packet begins.
1;10–0
Frame Number. Written by the device controller to indicate the frame number a packet finishes in. Typically
Frame Number correlates relative completion times of packets on an ISO endpoint.
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20.5.3
Device Operation
The device controller performs data transfers using a set of linked list transfer descriptors pointed to by a
queue head. The next sections explain the use of the device controller from the device controller driver
(DCD) point-of-view and further describe how specific USB bus events relate to status changes in the
device controller programmer's interface.
20.5.3.1
Device Controller Initialization
After hardware reset, USB OTG is disabled until the run/stop bit in the USBCMD register is set. At
minimum, it is necessary to have the queue heads set up for endpoint 0 before the device attach occurs.
Shortly after the device is enabled, a USB reset occurs followed by setup packet arriving at endpoint 0. A
queue head must be prepared so the device controller can store the incoming setup packet.
To initialize a device, the software must:
1. Optionally set streaming disable in the USBMODE[SDIS] bit.
2. Optionally modify the BURSTSIZE register.
3. Write the appropriate value to the USBINTR to enable the desired interrupts. For device operation,
setting UE, UEE, PCE, URE, and SLE is recommended.
For a list of available interrupts, refer to Section 20.3.4.3, “USB Interrupt Enable Register
(USBINTR),” and Section 20.3.4.2, “USB Status Register (USBSTS).”
4. Set the USBMODE[CM] field to enable device mode, and set the USBMODE[ES] bit for big
endian operation.
5. Optionally write the USBCMD register to set the desired interrupt threshold.
6. Set USBMODE[SLOM] to disable setup lockouts.
7. Initialize the EPLISTADDR.
8. Create two dQHs for endpoint 0—one for IN transactions and one for OUT transactions.
For information on device queue heads, refer to Section 20.5.2.1, “Endpoint Queue Head.”
9. Set the CCM’s UOCSR[BVLD] bit to allow device to connect to a host.
10. Set the USBCMD[RS] bit.
After the run/stop bit is set, a device reset occurs. The DCD must monitor the reset event and set the
DEVICEADDR and EPCRn registers, and adjust the software state as described in Section 20.5.3.2.1,
“Bus Reset.”
NOTE
Endpoint 0 is a control endpoint only and does not need to configured using
the EPCR0 register.
It is not necessary to initially prime endpoint 0 because the first packet received is always a setup packet.
The contents of the first setup packet requires a response in accordance with USB device framework
command set.
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20.5.3.2
Port State and Control
From a chip or system reset, the USB OTG module enters the powered state. A transition from the powered
state to the attach state occurs when the USBCMD[RS] bit is set. After receiving a reset on the bus, the
port enters the defaultFS or defaultHS state in accordance with the protocol reset described in Appendix
C.2 of the Universal Serial Bus Specification, Revision 2.0. Figure 20-41 depicts the state of a USB 2.0
device.
Active State
Inactive State
Powered
Set Run/Stop bit
to run mode
Attach
Power
Interruption
Reset
Bus Inactive
When the host
resets, the device
returns to the
default state.
Default
FS/HS
Suspend
FS/HS
Bus Activity
Address
Assigned
Bus Inactive
Address
FS/HS
Suspend
FS/HS
Bus Activity
Device
Configured
Device
De-configured
Bus Inactive
Configured
FS/HS
Suspend
FS/HS
Bus Activity
Software-only state
Figure 20-41. USB 2.0 Device States
States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the USB OTG, and they are
communicated to the DCD using these status bits:
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Table 20-49. Device Controller State Information Bits
Bit
Register
DC Suspend (SLI)
USBSTS
USB Reset Received (URI)
USBSTS
Port Change Detect (PCI)
USBSTS
High-Speed Port (PSPD)
PORTSCn
DCD software must maintain a state variable to differentiate between the defaultFS/HS state and the
address/configured states. Change of state from default to the address and configured states is part of the
enumeration process described in the device framework section of the USB 2.0 specification.
As a result of entering the address state, the DCD must program the device address register
(DEVICEADDR).
Entry into the configured state indicates that all endpoints to be used in the operation of the device have
been properly initialized by programming the EPCRn registers and initializing the associated queue heads.
20.5.3.2.1
Bus Reset
The host uses a bus reset to initialize downstream devices. When a bus reset is detected, USB OTG
controller renegotiates its attachment speed, resets the device address to 0, and notifies the DCD by
interrupt (assuming the USB reset interrupt enable is set). After a reset is received, all endpoints (except
endpoint 0) are disabled and the device controller cancels any primed transactions. The concept of priming
is clarified below, but when a reset is received, the DCD must perform:
1. Clear all setup token semaphores by reading the EPSETUPSR register and writing the same value
back to the EPSETUPSR register.
2. Clear all the endpoint complete status bits by reading the EPCOMPLETE register and writing the
same value back to the EPCOMPLETE register.
3. Cancel all primed status by waiting until all bits in the EPPRIME are 0 and then writing
0xFFFF_FFFF to EPFLUSH.
4. Read the reset bit in the PORTSCn register and make sure it remains active. A USB reset occurs
for a minimum of 3 ms and the DCD must reach this point in the reset clean-up before end of the
reset occurs, otherwise a hardware reset of the device controller is recommended (rare).
a) Setting USBCMD[RST] bit can perform a hardware reset.
NOTE
A hardware reset causes the device to detach from the bus by clearing the
USBCMD[RS] bit. Therefore, the DCD must completely re-initialize the
USB OTG after a hardware reset.
5. Free all allocated dTDs because the device controller no longer executes them. If this is the first
time the DCD processes a USB reset event, it is likely w3a4no dTDs have been allocated.
6. At this time, the DCD may release control back to the OS because no further changes to the device
controller are permitted until a port change detect is indicated.
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7. After a port change detect, the device has reached the default state and the DCD can read the
PORTSCn register to determine if the device operates in FS or HS mode. At this time, the device
controller has reached normal operating mode and DCD can begin enumeration according to the
chapter 9 Device Framework of the USB specification.
In some applications, it may not be possible to enable one or more pipes while in FS mode. Beyond the
data rate issue, there is no difference in DCD operation between FS and HS modes.
20.5.3.2.2
Suspend/Resume
To conserve power, USB OTG module automatically enters the suspended state when no bus traffic is
observed for a specified period. When suspended, the module maintains any internal status, including its
address and configuration. Attached devices must be prepared to suspend any time they are powered,
regardless if they are assigned a non-default address, are configured, or neither. Bus activity may cease due
to the host entering a suspend mode of its own. In addition, a USB device shall also enter the suspended
state when the hub port it is attached to is disabled.
The USB OTG module exits suspend mode when there is bus activity. It may also request the host to exit
suspend mode or selective suspend by using electrical signaling to indicate remote wake-up. The ability
of a device to signal remote wake-up is optional. The USB OTG is capable of remote wake-up signaling.
When the USB OTG is reset, remote wake-up signaling must be disabled.
Suspend Operational Model
The USB OTG moves into the suspend state when suspend signaling is detected or activity is missing on
the upstream port for more than a specific period. After the device controller enters the suspend state, an
interrupt notifies the DCD (assuming device controller suspend interrupt is enabled,
USBINTR[SLE] is set). When the PORTSCn[SUSP] is set, the device controller is suspended.
DCD response when the device controller is suspended is application specific and may involve switching
to low power operation. Find information on the bus power limits in suspend state in USB 2.0
specification.
Resume
If the USB OTG is suspended, its operation resumes when any non-idle signaling is received on its
upstream facing port. In addition, the USB OTG can signal the system to resume operation by forcing
resume signaling to the upstream port. Setting the PORTSCn[FPR] bit while the device is in suspend state
sends resume signaling upstream. Sending resume signal to an upstream port should cause the host to issue
resume signaling and bring the suspended bus segment (one more devices) back to the active condition.
NOTE
Before use of resume signaling, the host must enable it by using the set
feature command defined in chapter 9 Device Framework of the USB 2.0
specification.
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20.5.3.3
Managing Endpoints
The USB 2.0 specification defines an endpoint (also called a device endpoint or an address endpoint) as a
uniquely addressable portion of a USB device that can source or sink data in a communications channel
between the host and the device. Combination of the endpoint number and the endpoint direction specifies
endpoint address.
The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint 0 for a
device is always a control type data channel used for device discovery and enumeration. Other types of
endpoints are supported by USB include bulk, interrupt, and isochronous. Each endpoint type has specific
behavior related to packet response and error managing. Find more detail on endpoint operation in the USB
2.0 specification.
The USB OTG supports up to four endpoint specified numbers. The DCD can enable, disable, and
configure each endpoint.
Each endpoint direction is essentially independent and can have differing behavior in each direction. For
example, the DCD can configure endpoint 1-IN to be a bulk endpoint and endpoint 1-OUT to be an
isochronous endpoint. This helps to conserve the total number of endpoints required for device operation.
The only exception is that control endpoints must use both directions on a single endpoint number to
function as a control endpoint. Endpoint 0, for example, is always a control endpoint and uses both
directions.
Each endpoint direction requires a queue head allocated in memory. If the maximum is four endpoint
numbers (one for each endpoint direction used by the device controller), eight queue heads are required.
The operation of an endpoint and use of queue heads are described later in this document.
20.5.3.3.1
Endpoint Initialization
After hardware reset, all endpoints except endpoint 0 are uninitialized and disabled. The DCD must
configure and enable each endpoint by writing to the appropriate EPCRn register. Each EPCRn is split into
an upper and lower half. The lower half of EPCRn configures the receive or OUT endpoint, and the upper
half configures the corresponding transmit or IN endpoint. Control endpoints must be configured the same
in the upper and lower half of the EPCRn register; otherwise, behavior is undefined. Table 20-50 shows
how to construct a configuration word for endpoint initialization.
Table 20-50. Device Controller Endpoint Initialization
Field
Data Toggle Reset (TXR, RXR)
Data Toggle Inhibit (TXI, RXI)
Value
1 Synchronize the data PIDs
0 PID sequencing disabled
Endpoint Type (TXT, RXT)
00
01
10
11
Control
Isochronous
Bulk
Interrupt
Endpoint Stall (TXS, RXS)
0 Not stalled
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20.5.3.3.2
Stalling
There USB OTG has two occasions it may need to return to the host a STALL:
• The first is the functional stall, a condition set by the DCD as described in the USB 2.0 Device
Framework chapter. A functional stall is used only on non-control endpoints and can be enabled in
the device controller by setting the endpoint stall bit in the EPCRn register associated with the
given endpoint and the given direction. In a functional stall condition, the device controller
continues to return STALL responses to all transactions occurring on the respective endpoint and
direction until the endpoint stall bit is cleared by the DCD.
• A protocol stall, unlike a function stall, is used on control endpoints and automatically cleared by
the device controller at the start of a new control transaction (setup phase). When enabling a
protocol stall, DCD must enable the stall bits as a pair (TXS and RXS bits). A single write to the
EPCRn register can ensure both stall bits are set at the same instant.
NOTE
Any write to the EPCRn register during operational mode must preserve the
endpoint type field (perform a read-modify-write).
Table 20-51. Device Controller Stall Response Matrix
Endpoint
Stall Bit
Effect on
Stall bit
USB Response
N/A
None
STALL
IN/OUT/PING packet received by a
non-control endpoint.
1
None
STALL
IN/OUT/PING packet received by a
non-control endpoint.
0
None
ACK/NAK/NYET
SETUP packet received by a control
endpoint.
N/A
Cleared
ACK
IN/OUT/PING packet received by a control
endpoint
1
None
STALL
IN/OUT/PING packet received by a control
endpoint.
0
None
ACK/NAK/NYET
USB Packet
SETUP packet received by a non-control
endpoint.
20.5.3.3.3
Data Toggle
Data toggle maintains data coherency between host and device for any given data pipe. For more
information on data toggle, refer to the USB 2.0 specification.
Data Toggle Reset
The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device
controller by setting the data toggle reset bit in the EPCRn register. This should only happen when
configuring/initializing an endpoint or returning from a STALL condition.
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Data Toggle Inhibit
This feature is for test purposes only and must never be used during normal device controller operation.
Setting the data toggle inhibit bit causes the USB OTG module to ignore the data toggle pattern normally
sent and accepts all incoming data packets regardless of the data toggle state.
In normal operation, the USB OTG checks the DATA0/DATA1 bit against the data toggle to determine if
the packet is valid. If the data PID does not match the data toggle state bit maintained by the device
controller for that endpoint, the data toggle is considered not valid. If the data toggle is not valid, the device
controller assumes the packet was already received and discards the packet (not reporting it to the DCD).
To prevent the USB OTG from re-sending the same packet, the device controller responds to the error
packet by acknowledging it with an ACK or NYET response.
20.5.3.4
Packet Transfers
The host initiates all transactions on the USB bus and in turn, the device must respond to any request from
the host within the turnaround time stated in the USB 2.0 specification.
A USB host sends requests to the USB OTG in an order that can not be precisely predicted as a single
pipeline, so it is not possible to prepare a single packet for the device controller to execute. However, the
order of packet requests is predictable when the endpoint number and direction is considered. For example,
if endpoint 3 (transmit direction) is configured as a bulk pipe, expect the host to send IN requests to that
endpoint. This USB OTG module prepares packets for each endpoint/direction in anticipation of the host
request. The process of preparing the device controller to send or receive data in response to host initiated
transaction on the bus is referred to as priming the endpoint. This term appears throughout the
documentation to describe the USB OTG operation so the DCD is built properly. Further, the term flushing
describes the action of clearing a packet queued for execution.
20.5.3.4.1
Priming Transmit Endpoints
Priming a transmit endpoint causes the device controller to fetch the device transfer descriptor (dTD) for
the transaction pointed to by the device queue head (dQH). After the dTD is fetched, it is stored in the dQH
until the device controller completes the transfer described by the dTD. Storing the dTD in the dQH allows
the device controller to fetch the operating context needed to manage a request from the host without the
need to follow the linked list, starting at the dQH when the host request is received.
After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device
controller. This FIFO splits into virtual channels so the leading data can be stored for any endpoint up to
the maximum number of endpoints configured at device synthesis time.
After a priming request is complete, an endpoint state of primed is indicated in the EPSR register. For a
primed transmit endpoint, the device controller can respond to an IN request from the host and meet the
stringent bus turnaround time of high-speed USB.
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20.5.3.4.2
Priming Receive Endpoints
Priming receives endpoints identical to priming of transmit endpoints from the point of view of the DCD.
The major difference in the operational model at the device controller is no data movement of the leading
packet data because the data is to be received from the host.
As part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels like
the transmit FIFO. Thus, the size of the RX FIFO does not scale with the number of endpoints.
20.5.3.4.3
Interrupt/Bulk Endpoint Operation
The behaviors of the device controller for interrupt and bulk endpoints are identical. All valid IN and OUT
transactions to bulk pipes handshake with a NAK unless the endpoint is primed. After the endpoint is
primed, data delivery commences.
A dTD is retired by the device controller when the packets described in the transfer descriptor are
completed. Each dTD describes N packets to transfer according to the USB variable length transfer
protocol. The formula below and Table 20-52 describe how the device controller computes the number and
length of the packets sent/received by the USB vary according to the total number of bytes and maximum
packet length. See Section 20.5.2.1.1, “Endpoint Capabilities/Characteristics (Offset = 0x0),” for details
on the ZLT bit.
With zero-length termination (ZLT) cleared:
N = INT(number of bytes/max. packet length) + 1
With zero-length termination (ZLT) set:
N = MAXINT(number of bytes/max. packet length)
Table 20-52. Variable Length Transfer Protocol Example (ZLT=0)
Bytes
(dTD)
Max. Packet
Length (dQH)
N
P1
P2
P3
511
256
2
256
255
—
512
256
3
256
256
0
512
512
2
512
0
—
Table 20-53. Variable Length Transfer Protocol Example (ZLT=1)
Bytes
(dTD)
Max. Packet
Length (dQH)
N
P1
P2
P3
511
256
2
256
255
—
512
256
2
256
256
—
512
512
1
512
—
—
NOTE
The MULT field in the dQH must be set to 00 for bulk, interrupt, and control
endpoints.
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TX-dTD is complete when:
• All packets described in the dTD successfully transmit. Total bytes in dTD equal 0 when this
occurs.
RX-dTD is complete when:
• All packets described in the dTD are successfully received. Total bytes in dTD equal 0 when this
occurs.
• A short packet (number of bytes < maximum packet length) was received.
This is a successful transfer completion; DCD must check the total bytes field in the dTD to
determine the number of bytes remaining. From the total bytes remaining in the dTD, the DCD can
compute the actual bytes received.
• A long packet was received (number of bytes > maximum packet size) or (total bytes received >
total bytes specified).
This is an error condition. The device controller discards the remaining packet and set the buffer
error bit in the dTD. In addition, the endpoint flushes and the USBERR interrupt becomes active.
NOTE
Disabling zero-length packet termination allows transfers larger than the
total bytes field spanning across two or more dTDs.
Upon successful completion of the packet(s) described by the dTD, the active bit in the dTD is cleared and
the next pointer is followed when the terminate bit is clear. When the terminate bit is set, USB OTG flushes
the endpoint/direction and ceases operations for that endpoint/direction.
Upon unsuccessful completion of a packet (see long packet above), the dQH is left pointing to the dTD in
error. To recover from this error condition, DCD must properly re-initialize the dQH by clearing the active
bit and update the nextTD pointer before attempting to re-prime the endpoint.
NOTE
All packet level errors, such as a missing handshake or CRC error, are
retried automatically by the device controller. There is no required
interaction with the DCD for managing such errors.
Table 20-54. Interrupt/Bulk Endpoint Bus Response Matrix
1
Token
Type
Stall
Not
Primed
Primed
Underflow
Overflow
Setup
Ignore
Ignore
Ignore
N/A
N/A
In
STALL
NAK
Transmit
BS Error1
N/A
Out
STALL
NAK
Receive + NYET/ACK2
N/A
NAK
Ping
STALL
NAK
ACK
N/A
N/A
Invalid
Ignore
Ignore
Ignore
Ignore
Ignore
Force bit stuff error
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2
20.5.3.4.4
NYET/ACK — NYET unless the transfer descriptor has packets remaining according
to the USB variable length protocol then ACK.
Control Endpoint Operation
Setup Phase
All requests to a control endpoint begin with a setup phase followed by an optional data phase and a
required status phase.
Setup packet managing:
• Disable setup lockout by setting the setup lockout mode bit (USBMODE[SLOM]), once at
initialization. Setup lockout is not necessary when using the tripwire as described below.
NOTE
Leaving the setup lockout mode cleared results in a potential compliance
issue.
•
1.
2.
3.
4.
5.
6.
7.
After receiving an interrupt and inspecting EPSETUPSR to determine a setup packet was received
on a particular pipe:
Write 1 to clear corresponding bit in EPSETUPSR.
Set the setup tripwire bit (USBCMD[SUTW]).
Duplicate contents of dQH.SetupBuffer into local software byte array.
Read the USBCMD[SUTW] bit. If set, continue; if cleared, goto 2)
Clear the USBCMD[SUTW] bit.
Poll until the EPSETUPSR bit clears.
Process setup packet using the local software byte array copy and execute status/handshake phases.
NOTE
After receiving a new setup packet, status and/or handshake phases may
remain pending from a previous control sequence. These should be flushed
and de-allocated before linking a new status and/or handshake dTD for the
most recent setup packet.
Data Phase
Following the setup phase, the DCD must create a device transfer descriptor for the data phase and prime
the transfer.
After priming the packet, the DCD must verify a new setup packet is not received by reading the
EPSETUPSR register immediately verifying that the prime had completed. A prime completes when the
associated bit in the EPPRIME register is cleared and the associated bit in the EPSR register is set. If the
EPPRIME bit goes to 0 and the EPSR bit is not set, the prime fails. This can only happen because of
improper setup of the dQH, dTD, or a setup arriving during the prime operation. If a new setup packet is
indicated after the EPPRIME bit is cleared, then the transfer descriptor can be freed and the DCD must
re-interpret the setup packet.
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Should a setup arrive after the data stage is primed, the device controller automatically clears the prime
status (EPSR) to enforce data coherency with the setup packet.
NOTE
Error managing of data phase packets is the same as bulk packets described
previously.
Status Phase
Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime
the endpoint for the status phase. The DCD must also perform the same checks of the EPSETUPSR as
described above in the data phase.
NOTE
Error managing of status phase packets is the same as bulk packets
described previously.
Control Endpoint Bus Response Matrix
Table 20-55 shows the device controller response to packets on a control endpoint according to the device
controller state.
Table 20-55. Control Endpoint Bus Response Matrix
Token
Type
Endpoint State
Setup
Lockout
Stall
Not Primed
Primed
Underflow
Overflow
Setup
ACK
ACK
ACK
N/A
SYSERR1
In
STALL
NAK
Transmit
BS Error2
N/A
N/A
STALL
NAK
Receive +
NYET/ACK3
N/A
NAK
N/A
Ping
STALL
NAK
ACK
N/A
N/A
N/A
Invalid
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
Out
1
SYSERR — System error must never occur when the latency FIFOs are correctly sized and
the DCD is responsive.
2
Force bit stuff error
3
NYET/ACK — NYET unless the transfer descriptor has packets remaining according to the
USB variable length protocol then ACK.
20.5.3.4.5
Isochronous Endpoint Operation
Isochronous endpoints used for real-time scheduled delivery of data, and their operational model is
significantly different than the host throttled bulk, interrupt, and control data pipes. Real time delivery by
the USB OTG is accomplished by:
• Exactly MULT packets per (micro)frame are transmitted/received.
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NOTE
MULT is a two-bit field in the device queue head. Isochronous endpoints do
not use the variable length packet protocol.
•
•
NAK responses are not used. Instead, zero length packets are sent in response to an IN request to
unprimed endpoints. For unprimed RX endpoints, the response to an OUT transaction is to ignore
the packet within the device controller.
Prime requests always schedule the transfer described in the dTD for the next (micro)frame. If
ISO-dTD remains active after that frame, ISO-dTD holds ready until executed or canceled by the
DCD.
The USB OTG in host mode uses the periodic frame list to schedule data exchanges to isochronous
endpoints. The operational model for device mode does not use such a data structure. Instead, the same
dTD used for control/bulk/interrupt endpoints is also used for isochronous endpoints. The difference is in
the managing of the dTD.
The first difference between bulk and ISO-endpoints is that priming an ISO-endpoint is a delayed
operation such that an endpoint becomes primed only after a SOF is received. After the DCD writes the
prime bit, the prime bit clears as usual to indicate to software that the device controller completed a
priming the dTD for transfer. Internal to the design, the device controller hardware masks that prime start
until the next frame boundary. This behavior is hidden from the DCD, but occurs so the device controller
can match the dTD to a specific (micro)frame.
Another difference with isochronous endpoints is that the transaction must wholly complete in a
(micro)frame. After an ISO transaction is started in a (micro)frame, it retires the corresponding dTD when
MULT transactions occur or the device controller finds a fulfillment condition.
The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment
error occurs, the frame after the transfer failed to complete wholly, and the device controller retires the
current ISO-dTD and move to the next ISO-dTD.
Fulfillment errors are only caused due to partially completed packets. If no activity occurs to a primed
ISO-dTD, the transaction stays primed indefinitely. This means it is up to software must discard transmit
ISO-dTDs that pile up from a failure of the host to move the data.
Finally, the last difference with ISO packets is in the data level error managing. When a CRC error occurs
on a received packet, the packet is not retried similar to bulk and control endpoints. Instead, the CRC is
noted by setting the transaction error bit and the data is stored as usual for the application software to sort
out.
• TX packet retired:
— MULT counter reaches zero.
— Fulfillment error (transaction error bit is set):
– # packets occurred > 0 AND # packets occurred < MULT
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NOTE
For TX-ISO, MULT counter can be loaded with a lesser value in the dTD
multiplier override field. If the multiplier override field is zero, the MULT
counter initializes to the multiplier in the QH.
•
RX packet retired:
— MULT counter reaches zero.
— Non-MDATA data PID is received
— Overflow error:
– Packet received is > maximum packet length. (Buffer Error bit is set)
– Packet received exceeds total bytes allocated in dTD. (Buffer Error bit is set)
— Fulfillment error (Transaction Error bit is set):
– # packets occurred > 0 AND # packets occurred < MULT
— CRC error (Transaction Error bit is set)
NOTE
For ISO, when a dTD is retired, the next dTD is primed for the next frame.
For continuous (micro)frame to (micro)frame operation, DCD must ensure
the dTD linked-list is out ahead of the device controller by at least two
(micro)frames.
Isochronous Pipe Synchronization
When it is necessary to synchronize an isochronous data pipe to the host, the (micro)frame number
(FRINDEX register) can act as a marker. To cause a packet transfer to occur at a specific (micro)frame
number (N), the DCD must interrupt on SOF during frame N-1. When the FRINDEX equals N-1, the DCD
must write the prime bit. The USB OTG primes the isochronous endpoint in (micro)frame N-1 so the
device controller executes delivery during (micro)frame N.
CAUTION
Priming an endpoint towards the end of (micro)frame N-1 does not
guarantee delivery in (micro)frame N. The delivery may actually occur in
(micro)frame N+1 if the device controller does not have enough time to
complete the prime before the SOF for packet N is received.
Isochronous Endpoint Bus Response Matrix
Table 20-56. Isochronous Endpoint Bus Response Matrix
Token
Type
Stall
Not
Primed
Primed
Underflow
Overflow
Setup
STALL
STALL
STALL
N/A
N/A
In
NULL1
Packet
NULL
Packet
Transmit
BS Error2
N/A
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Table 20-56. Isochronous Endpoint Bus Response Matrix (continued)
Token
Type
Stall
Not
Primed
Primed
Underflow
Overflow
Ignore
Ignore
Receive
N/A
Drop
Packet
Ping
Ignore
Ignore
Ignore
Ignore
Ignore
Invalid
Ignore
Ignore
Ignore
Ignore
Ignore
Out
1
2
20.5.3.5
Zero length packet
Force bit stuff error
Managing Queue Heads
The device queue head (dQH) points to the linked list of transfer tasks, each depicted by the device transfer
descriptor (dTD). An area of memory pointed to by EPLISTADDR contains a group of all dQH's in a
sequential list (Figure 20-42). The even elements in the list of dQH's receive endpoints (OUT/SETUP) and
the odd elements transmit endpoints (IN/INTERRUPT). Device transfer descriptors are linked head to tail
starting at the queue head and ending at a terminate bit. After the dTD retires, it is no longer part of the
linked list from the queue head. Therefore, software is required to track all transfer descriptors because
pointers no longer exist within the queue head after the dTD is retired (see Section 20.5.3.6.1, “Software
Link Pointers”).
Endpoint Queue Heads
ENDPOINTLISTADDR
(up to 32 elements)
Endpoint QH0 - Out
Transfer Buffer
Pointer
Transfer
Buffer
Endpoint QH0 - In
Transfer Buffer
Pointer
Transfer
Buffer
Transfer
Buffer
Endpoint QH1 - Out
Endpoint
Transfer
Descriptors
Transfer
Buffer
Figure 20-42. Endpoint Queue Head Diagram
In addition to current and next pointers and the dTD overlay examined in Section 20.5.3.4, “Packet
Transfers,” the dQH also contains the following parameters for the associated endpoint: multipler,
maximum packet length, and interrupt on setup. The next section includes demonstration of complete
initialization of the dQH including these fields.
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20.5.3.5.1
Queue Head Initialization
One pair of device queue heads must be initialized for each active endpoint. To initialize a device queue
head:
• Write the wMaxPacketSize field as required by the USB specification chapter 9 or application
specific protocol.
• Write the multiplier field to 0 for control, bulk, and interrupt endpoints. For ISO endpoints, set the
multiplier to 1,2, or 3 as required for bandwidth with the USB specification chapter 9 protocol. In
FS mode, the multiplier field can only be 1 for ISO endpoints.
• Set the next dTD terminate bit field.
• Clear the active bit in the status field.
• Clear the halt bit in the status field.
NOTE
The DCD must only modify dQH if the associated endpoint is not primed
and there are no outstanding dTDs.
20.5.3.5.2
Setup Transfers Operation
As discussed in Section 20.5.3.4.4, “Control Endpoint Operation,” setup transfers require special
treatment by the DCD. A setup transfer does not use a dTD, but instead stores the incoming data from a
setup packet in an 8-byte buffer within the dQH.
Upon receiving notification of the setup packet, the DCD should manage the setup transfer by:
1. Copying setup buffer contents from dQH-RX to software buffer.
2. Acknowledging setup backup by writing a 1 to the corresponding bit in the EPSETUPSR register.
NOTE
The acknowledge must occur before continuing to process the setup packet.
After acknowledge occurs, DCD must not attempt to access the setup buffer
in dQH-RX. Only local software copy should be examined.
3. Checking for pending data or status dTD's from previous control transfers and flushing if any exist
as discussed in Section 20.5.3.6.5, “Flushing/De-priming an Endpoint.”
NOTE
It is possible for the device controller to receive setup packets before
previous control transfers complete. Existing control packets in progress
must be flushed and the new control packet completed.
4. Decoding setup packet and prepare data phase (optional) and status phase transfer as required by
the USB specification chapter 9 or application specific protocol.
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20.5.3.6
20.5.3.6.1
Managing Transfers with Transfer Descriptors
Software Link Pointers
It is necessary for the DCD software to maintain head and tail pointers for the linked list of dTDs for each
respective queue head. This is necessary because the dQH only maintains pointers to the current working
dTD and the next dTD executed. The operations described in the next section for managing dTDs assumes
DCD can reference the head and tail of the dTD linked list.
NOTE
To conserve memory, the reserved fields at the end of the dQH can be used
to store the head and tail pointers, but DCD must continue maintaining the
pointers.
Head Pointer
Endpoint QH
current
next
Completed dTDs
Tail Pointer
Queued dTDs
Figure 20-43. Software Link Pointers
NOTE
Check the status of each dTD to determine completed status.
20.5.3.6.2
Building a Transfer Descriptor
Before a transfer can be executed from the linked list, a dTD must be built to describe the transfer. Use the
following procedure for building dTDs.
Allocate an 8-longword dTD block of memory aligned to 8-longword boundaries. The last 5 bits of the
address must equal 00000.
Write the following fields:
1. Initialize the first 7 longwords to 0.
2. Set the terminate bit.
3. Fill in total bytes with transfer size.
4. Set the interrupt on complete bit if desired.
5. Initialize the status field with the active bit set, and all remaining status bits cleared.
6. Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer.
7. Initialize buffer pointer page 1 through page 4 to be one greater than each of the previous buffer
pointers.
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20.5.3.6.3
Executing a Transfer Descriptor
To safely add a dTD, the DCD must follow this procedure that manages the event where the device
controller reaches the end of the dTD list. At the same time, a new dTD is added to the end of the list.
Determine whether the linked list is empty:
Check the DCD driver to see if the pipe is empty (internal representation of the linked list should
indicate if any packets are outstanding)
Case 1: Link list is empty
1. Write dQH next pointer AND dQH terminate bit to 0 as a single longword operation.
2. Clear active and halt bit in dQH (in case set from a previous error).
3. Prime endpoint by writing 1 to the correct bit position in the EPPRIME register.
Case 2: Link list is not empty
1.
2.
3.
4.
5.
Add dTD to end of the linked list.
Read correct prime bit in EPPRIME - if set, DONE.
Set the USBCMD[ATDTW] bit.
Read correct status bit in EPSR, and store in a temporary variable for later.
Read the USBCMD[ATDTW] bit:
If clear, go to 3.
If set, continue to 6.
6. Clear the USBCMD[ATDTW] bit.
7. If status bit read in step 4 is 1 DONE.
8. If status bit read in step 4 is 0 then go to case 1, step 1.
20.5.3.6.4
Transfer Completion
After a dTD is initialized and the associated endpoint is primed, the device controller executes the transfer
upon the host-initiated request. The DCD is notified with a USB interrupt if the interrupt-on-complete bit
was set, or alternatively, the DCD can poll the endpoint complete register to determine when the dTD had
been executed. After a dTD is executed, DCD can check the status bits to determine success or failure.
CAUTION
Multiple dTDs can be completed in a single endpoint complete notification.
After clearing the notification, the DCD must search the dTD linked list and
retire all finished (active bit cleared) dTDs.
By reading the status fields of the completed dTDs, the DCD can determine if the transfers completed
successfully. Success is determined with the following combination of status bits:
• Active = 0, Halted = 0, Transaction error = 0, Data buffer error = 0
Should any combination other than the one shown above exist, the DCD must take proper action. Transfer
failure mechanisms are indicated in Section 20.5.3.6.6, “Device Error Matrix.”
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In addition to checking the status bit, the DCD must read the transfer bytes field to determine the actual
bytes transferred. When a transfer is complete, the total bytes transferred decrements by the actual bytes
transferred. For transmit packets, a packet is only complete after the actual bytes reaches zero. However,
for receive packets, the host may send fewer bytes in the transfer according the USB variable length packet
protocol.
20.5.3.6.5
Flushing/De-priming an Endpoint
It is necessary for the DCD to flush or de-prime endpoints during a USB device reset or during a broken
control transfer. There may also be application specific requirements to stop transfers in progress. The
DCD can use this procedure to stop a transfer in progress:
1. Set the corresponding bit(s) in the EPFLUSH register.
2. Wait until all bits in the EPFLUSH register are cleared.
NOTE
This operation may take a large amount of time depending on the USB bus
activity. It is not desirable to have this wait loop within an interrupt service
routine.
3. Read the EPSR register to ensure that for all endpoints commanded to be flushed, that the
corresponding bits are now cleared. If the corresponding bits are set after step #2 has finished, flush
failed as described below:
In very rare cases, a packet is in progress to the particular endpoint when commanded to flush using
EPFLUSH. A safeguard is in place to refuse the flush to ensure that the packet in progress
completes successfully. The DCD may need to repeatedly flush any endpoints that fail to flush by
repeating steps 1-3 until each endpoint successfully flushes.
20.5.3.6.6
Device Error Matrix
The following table summarizes packet errors not automatically managed by the USB OTG module.
Table 20-57. Device Error Matrix
Direction
Packet
Type
Data Buffer Overflow
RX
Any
1
0
ISO Packet Error
RX
ISO
0
1
Both
ISO
0
1
Error
ISO Fulfillment Error
Data Buffer Transaction
Error Bit
Error Bit
The device controller manages all errors on bulk/control/interrupt endpoints except for a data buffer
overflow. However, for ISO endpoints, errors packets are not retried and errors are tagged as indicated.
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Table 20-58. Error Descriptions
Overflow
Number of bytes received exceeded max. packet size or total buffer length.
Note: This error also sets the halt bit in the dQH, and if there are dTDs remaining in the
linked list for the endpoint, those are not executed.
ISO Packet Error
CRC error on received ISO packet. Contents not guaranteed correct.
ISO Fulfillment Error
Host failed to complete the number of packets defined in the dQH mult field within the given
(micro)frame. For scheduled data delivery, DCD may need to readjust the data queue
because a fulfillment error causes the device controller to cease data transfers on the pipe
for one (micro)frame. During the dead (micro)frame, the device controller reports error on
the pipe and primes for the following frame.
20.5.4
Servicing Interrupts
The interrupt service routine must understand there are high frequency, low frequency, and error
operations to order accordingly.
20.5.4.1
High Frequency Interrupts
In particular, high frequency interrupts must be managed in the order below. The most important of these
is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible.
Table 20-59. Interrupt Managing Order
1
Execution
Order
Interrupt
Action
1a
USB Interrupt1
EPSETUPSR
Copy contents of setup buffer and acknowledge setup packet (as indicated
in Section 20.5.3.5, “Managing Queue Heads”). Process setup packet
according to USB specification chapter 9 or application specific protocol.
1b
USB Interrupt
EPCOMPLETE
Manage completion of dTD as indicated in Section 20.5.3.5, “Managing
Queue Heads.”
2
SOF Interrupt
Action as deemed necessary by application. This interrupt may not have a
use in all applications.
It is likely multiple interrupts stack up on any call to the interrupt service routine and during interrupt service routine.
20.5.4.1.1
Low Frequency Interrupts
The low frequency events include the following interrupts. These interrupts can be managed in any order
because they do not occur often in comparison to the high-frequency interrupts.
Table 20-60. Low Frequency Interrupt Events
Interrupt
Port Change
Action
Change software state information.
Sleep Enable (Suspend)
Change software state information. Low power managing as
necessary.
Reset Received
Change software state information. Abort pending transfers.
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20.5.4.1.2
Error Interrupts
Error interrupts are least frequent and should be placed last in the interrupt service routine.
Table 20-61. Error Interrupt Events
Interrupt
Action
USB Error Interrupt.
This error is redundant because it combines USB interrupt and an error status in the dTD.
The DCD more aptly manages packet-level errors by checking the dTD status field upon
receipt of USB interrupt (w/ EPCOMPLETE).
System Error
20.5.5
Unrecoverable error. Immediate reset of module; free transfers buffers in progress and
restart the DCD.
Deviations from the EHCI Specifications
The host mode operation of the USB OTG module is nearly EHCI-compatible with a few minor
differences. For the most part, the modules conform to the data structures and operations described in
Section 3, “Data Structures,” and Section 4, “Operational Model,” in the EHCI specification. The
particulars of the deviations occur in the following areas:
• Embedded transaction translator—Allows direct attachment of FS and LS devices in host mode
without the need for a companion controller.
• Device operation—In host mode, the device operational registers are generally disabled; therefore,
device mode is mostly transparent when in host mode. However, there are a couple exceptions
documented in the following sections.
• Embedded design interface—The module does not have a PCI Interface and therefore the PCI
configuration registers described in the EHCI specification are not applicable.
For the purposes of the USB OTG implementing a dual-role host/device controller with support for OTG
applications, it is necessary to deviate from the EHCI specification. Device and OTG operation are not
specified in the EHCI specification, and thus the implementation supported in the USB OTG module is
proprietary.
20.5.5.1
Embedded Transaction Translator Function
The USB host mode supports directly connected full- and low-speed devices without requiring a
companion controller by including the capabilities of a USB 2.0 high-speed hub transaction translator.
Although there is no separate transaction translator block in the system, the transaction translator function
normally associated with a high-speed hub is implemented within the DMA and protocol engine blocks.
The embedded transaction translator function is an extension to EHCI interface, but makes use of the
standard data structures and operational models existing in the EHCI specification to support full- and
low-speed devices.
20.5.5.1.1
Capability Registers
These additions to the capability registers support the embedded Transaction translator function:
• N_TT added to HSCPARAMS - Host Controller Structural Parameters
• N_PTT added to HSCPARAMS - Host Controller Structural Parameters
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See Section 20.3.3.3, “Host Controller Structural Parameters Register (HCSPARAMS)” for usage
information.
20.5.5.1.2
Operational Registers
These additions to the operational registers support the embedded TT:
• Addition of the TTCTRL register.
• Addition of a two-bit port speed (PSPD) field to the PORTSCn register.
20.5.5.1.3
Discovery
In a standard EHCI controller design, the EHCI host controller driver detects a full-speed (FS) or
low-speed (LS) device by noting if the port enable bit is set after the port reset operation. The port enable
is set only in a standard EHCI controller implementation after the port reset operation and when the host
and device negotiate a high-speed connection (chirp completes successfully).
The module always sets the port enable bit after the port reset operation regardless of the result of the host
device chirp result, and the resulting port speed is indicated by the PORTSCn[PSPD] field. Therefore, the
standard EHCI host controller driver requires an alteration to manage directly connected full- and
low-speed devices or hubs. The change is a fundamental one summarized in Table 20-62.
Table 20-62. Functional Differences Between EHCI and EHCI with Embedded TT
Standard EHCI
20.5.5.1.4
EHCI with embedded Transaction Translator
After port enable bit is set following a
connection and reset sequence, the
device/hub is assumed to be HS.
After port enable bit is set following a connection and
reset sequence, the device/hub speed is noted from
PORTSCn.
FS and LS devices are assumed to be
downstream from a HS hub.
Therefore, all port-level control
performs through the hub class to the
nearest hub.
FS and LS device can be downstream from a HS hub or
directly attached. When the FS/LS device is downstream
from a HS hub, port-level control acts using the hub class
through the nearest hub. When a FS/LS device is directly
attached, then port-level control is accomplished using
PORTSCn.
FS and LS devices are assumed to be
downstream from a HS hub with
HubAddr equal to X. [where HubAddr
> 0 and HubAddr is the address of the
hub where the bus transitions from HS
to FS/LS (split target hub)]
FS and LS device can be downstream from a HS hub
with HubAddr equal to X [HubAddr > 0] or directly
attached [where HubAddr equals 0 and HubAddr is the
address of the root hub where the bus transitions from
HS to FS/LS (split target hub is the root hub)]
Data Structures
The same data structures used for FS/LS transactions though a HS hub are also used for transactions
through the root hub. It is demonstrated here how hub address and endpoint speed fields should be set for
directly attached FS/LS devices and hubs:
1. QH (for direct attach FS/LS) – asynchronous (bulk/control endpoints) periodic (interrupt)
• Hub address equals 0
• Transactions to direct attached device/hub.
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•
— QH.EPS equals port speed
Transactions to a device downstream from direct attached FS hub.
— QH.EPS equals downstream device speed
NOTE
When QH.EPS equals 01 (LS) and PORTSCn[PSPD] equals 00 (FS), a
LS-pre-PID is sent before transmitting LS traffic.
Maximum packet size must equal 64 or less to prevent undefined behavior.
2. siTD (for direct attach FS) – Periodic (ISO endpoint)
• All FS ISO transactions:
— Hub address equals 0
— siTD.EPS equals 00 (full speed)
Maximum packet size must equal to 1023 or less to prevent undefined behavior.
20.5.5.1.5
Operational Model
The operational models are well defined for the behavior of the transaction translator (see USB 2.0
specification) and for the EHCI controller moving packets between system memory and a USB-HS hub.
Because the embedded transaction translator exists within the USB host controller, no physical bus
between EHCI host controller driver and the USB FS/LS bus. These sections briefly discuss the
operational model for how the EHCI and transaction translator operational models combine without the
physical bus between. The following sections assume the reader is familiar with the EHCI and USB 2.0
transaction translator operational models.
Microframe Pipeline
The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline between
the host (H) and the bus (B). The embedded transaction translator uses the same pipeline algorithms
specified in the USB 2.0 specification for a hub-based transaction translator.
All periodic transfers always begin at B-frame 0 (after SOF) and continue until the stored periodic transfers
are complete. As an example of the microframe pipeline implemented in the embedded transaction
translator, all periodic transfers that are tagged in EHCI to execute in H-frame 0 are ready to execute on
the bus in B-frame 0.
When programming the S-mask and C-masks in the EHCI data structures to schedule periodic transfers
for the embedded transaction translator, the EHCI host controller driver must follow the same rules
specified in EHCI for programming the S-mask and C-mask for downstream hub-based transaction
translators.
After periodic transfers are exhausted, any stored asynchronous transfer is moved. Asynchronous transfers
are opportunistic because they execute when possible and their operation is not tied to H-frame and
B-frame boundaries with the exception that an asynchronous transfer cannot babble through the SOF (start
of B-frame 0.)
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Split State Machines
The start and complete-split operational model differs from EHCI slightly because there is no bus medium
between the EHCI controller and the embedded transaction translator. Where a start or complete-split
operation would occur by requesting the split to the HS hub, the start/complete-split operation is simple
an internal operation to the embedded transaction translator. Table 20-63 summarizes the conditions where
handshakes are emulated from internal state instead of actual handshakes to HS split bus traffic.
Table 20-63. Emulated Handshakes
Condition
Emulate TT Response
Start-Split: All asynchronous buffers full
NAK
Start-Split: All periodic buffers full
ERR
Start-Split: Success for start of async. transaction
ACK
Start-Split: Start periodic transaction
No handshake (Ok)
Complete-Split: Failed to find transaction in queue
Bus time-out
Complete-Split: Transaction in queue is busy
Complete-Split: Transaction in queue is complete
NYET
Actual handshake from FS/LS device
Asynchronous Transaction Scheduling and Buffer Management
The following USB 2.0 specification items are implemented in the embedded Transaction Translator:
• USB 2.0 – 11.17.3
— Sequencing is provided and a packet length estimator ensures no full-/low-speed packet
babbles into SOF time.
• USB 2.0 – 11.17.4
— • Transaction tracking for 2 data pipes.
• USB 2.0 – 11.17.5
— • Clear_TT_Buffer capability provided though the use of the TTCTRL register.
Periodic Transaction Scheduling and Buffer Management
The following USB 2.0 specification items are implemented in the embedded transaction translator:
• USB 2.0 – 11.18.6.[1-2]
— Abort of pending start-splits
– EOF (and not started in microframes 6)
– Idle for more than 4 microframes
— Abort of pending complete-splits
– EOF
– Idle for more than 4 microframes
• USB 2.0 - 11.18.[7-8]
— Transaction tracking for up to 4 data pipes.
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– No more than 4 periodic transactions (interrupt/isochronous) can be scheduled through the
embedded TT per frame.
— Complete-split transaction searching.
NOTE
There is no data schedule mechanism for these transactions other than the
microframe pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 ms) or else
undefined behavior may result.
20.5.5.2
Device Operation
The co-existence of a device operational controller within the USB OTG module has little effect on EHCI
compatibility for host operation. However, given that the USB OTG controller initializes in neither host
nor device mode, the USBMODE register must be programmed for host operation before the EHCI host
controller driver can begin EHCI host operations.
20.5.5.3
Non-Zero Fields in the Register File
Some of the reserved fields and reserved addresses in the capability registers and operational registers have
use in device mode. Adhere to these steps:
• Write operations to all EHCI reserved fields (some of which are device fields in the USB OTG
module) in the operation registers should always be written to zero. This is an EHCI requirement
of the device controller driver that must be adhered to.
• Read operations by the module must properly mask EHCI reserved fields (some of which are
device fields in the USB OTG module registers).
20.5.5.4
SOF Interrupt
The SOF interrupt is a free running 125 µs interrupt for host mode. EHCI does not specify this interrupt,
but it has been added for convenience and as a potential software time base. The free running interrupt is
shared with the device mode start-of-frame interrupt. See Section 20.3.4.2, “USB Status Register
(USBSTS),” and Section 20.3.4.3, “USB Interrupt Enable Register (USBINTR),” for more information.
20.5.5.5
Embedded Design
This is an embedded USB host controller as defined by the EHCI specification; therefore, it does not
implement the PCI configuration registers.
20.5.5.5.1
Frame Adjust Register
Given that the optional PCI configuration registers are not included in this implementation, there is no
corresponding bit level timing adjustments like those provided by the frame adjust register in the PCI
configuration registers. Starts of microframes are timed precisely to 125 µs using the transceiver clock as
a reference clock or a 60 Mhz transceiver clock for 8-bit physical interfaces and full-speed serial
interfaces.
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20.5.5.6
20.5.5.6.1
Miscellaneous Variations from EHCI
Programmable Physical Interface Behavior
The modules support multiple physical interfaces that can operate in different modes when the module is
configured with the software programmable physical interface modes. The control bits for selecting the
PHY operating mode are added to the PORTSCn register providing a capability not defined by the EHCI
specification.
20.5.5.6.2
Discovery
Port Reset
The port connect methods specified by EHCI require setting the port reset bit in the PORTSCn register for
a duration of 10 ms. Due to the complexity required to support the attachment of devices not high speed,
a counter is present in the design that can count the 10 ms reset pulse to alleviate the requirement of the
software to measure this duration. Therefore, the basic connection is summarized as:
• Port change interrupt—Port connect change occurs to notify the host controller driver that a device
has attached.
• Software shall set the PORTSCn[PR] bit to reset the device.
• Software shall clear the PORTSCn[PR] bit after 10 ms.
— This step, necessary in a standard EHCI design, may be omitted with this implementation.
Should the EHCI host controller driver attempt to write a 0 to the reset bit while a reset is in
progress, the write is ignored and the reset continues until completion.
• Port change interrupt—Port enable change occurs to notify the host controller that the device is
now operational and at this point the port speed is determined.
Port Speed Detection
After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the port
speed. Unlike the EHCI implementation, which re-assigns the port owner for any device that does not
connect at high speed, this host controller supports direct attach of non-HS devices. Therefore, the
following differences are important regarding port speed detection:
• Port owner hand-off is not implemented. Therefore, PORTSCn[PO] bit is read-only and always
reads 0.
• A 2-bit port speed indicator field has been added to PORTSCn to provide the current operating
speed of the port to the host controller driver.
• A 1-bit high-speed indicator bit has been added to PORTSCn to signify that the port is in HS vs.
FS/LS.
— This information is redundant with the 2-bit port speed indicator field above.
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Chapter 21
Liquid Crystal Display Controller (LCDC)
21.1
Introduction
The liquid crystal display controller (LCDC) provides display data for external gray-scale or color LCD
panels. The LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color (passive
color or CSTN), and active-matrix color (active color or TFT) LCD panels.
21.1.1
Block Diagram
The LCD controller block diagram is shown below.
4/8bpp Color
Byte
Swap
DMA
FIFO
Panning
Data
Shifter
256x18
LUT
Background Plane
LCDC
Arbiter
4/8bpp Color
Byte
Swap
DMA
FIFO
Panning
Data
Shifter
256x18
LUT
Graphic Window
NonColor
Cursor
Interface
Buffer
4bpp
Gray
Interface
FRC
Gray
TFT
Interface
Logic
CSTN
Buffer
FRC
Color
4bpp
gray
Alpha
Blending
1/2bpp gray
Color
CSTN
Color
Cursor
To Panel
Figure 21-1. LCDC Block Diagram
21.1.2
Features
The LCDC provides the following features:
• Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD
panels
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•
•
16 simultaneous gray-scale levels from a palette of 16 for monochrome display
Support for:
— Maximum resolution of 800 × 600
— Passive color panel:
– 4 (mapped to RGB444) / 8 (mapped to RGB444) / 12 (RGB444) bits per pixel (bpp)
— TFT panel:
– 4 (mapped to RGB666) / 8 (mapped to RGB666) / 12 (RGB444) / 16 (RGB565) / 18
(RGB666) bpp
— 16 and 256 colors out of a palette of 4096 colors for 4 bpp and 8 bpp CSTN display respectively
— 16 and 256 colors out of a palette of 256K colors for 4 bpp and 8 bpp TFT display respectively
— True 4096 colors for a 12 bpp display
— True 64K colors for 16 bpp
— True 256K colors for 18 bpp
— Additional support details are shown in Table 21-1
Table 21-1. Supported Panel Characteristics
Panel Type
Bit/Pixel
Panel Interface (Bits)
Number of Gray Level/Color
Monochrome
1
1, 2, 4, 8
black-and-white
2
1, 2, 4, 8
4 out of palette of 16
4
1, 2, 4, 8
16
4, 8
12
16, 256 out of palette of 4096
12
12
4096
4, 8
18
16, 256 out of palette of 256K
12, 16, 18
12, 16, 18
4096, 64K, 256K
CSTN
TFT
•
•
•
•
•
•
•
•
•
•
•
Standard panel interface for common LCD drivers
Panel interface of 1-, 2-, 4-, 8-bit for monochrome panels
Panel interface of 12-, 16-, 18-bit for color panels
For 4 bpp and 8 bpp a palette table is used for re-mapping of data from memory, independent of
type of panel used. For the 1 bpp, 2 bpp, 12 bpp, 16 bpp, and 18 bpp the palette table is by-passed.
Interface to passive and active color panel (TFT)
Supports timing requirements for Sharp 240 × 320 HR-TFT panel
Hardware-generated cursor with blink, color, and size programmability
Logical operation between color hardware cursor and background
Hardware panning (soft horizontal scrolling)
8-bit pulse-width modulator for software contrast control
Graphic window support for viewfinder function in color display
MCF52277 Reference Manual, Rev 2
21-2
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
•
•
21.2
Graphic window color keying for graphical hardware cursor
256 transparency levels for alpha blending between graphic window and background plane
External Signal Description
Table 21-2 describes the LCD controller signals.
Table 21-2. LCD Signals
21.3
Signal
I/O
Function
LCD_D[17:0]
O
Line data. LCD data bus.
LCD_FLM/
LCD_VSYNC
O
Passive matrix: First line marker
Active matrix: Vertical sync pulse. Indicates start of next frame.
LCD_LP/
LCD_HSYNC
O
Passive matrix: Line pulse
Active matrix: Horizontal sync pulse. Indicates start of next line.
LCD_LSCLK
O
Shift clock. Clock for latching data into the display driver’s internal shift register.
LCD_ACD/
LCD_OE
O
Passive matrix: Alternate crystal direction
Active matrix: Output enable to enable data to be shifted onto the display.
LCD_CONTRAST
O
Contrast. Controls the LCD bias voltage for contrast control.
LCD_PS
O
Power save. Controls signal output for source driver (Sharp HR-TFT 240x320
panels only)
LCD_CLS
O
Gate driver clock signal. Start signal output for gate driver, inverted version of
LCD_PS (Sharp HR-TFT 240x320 panels only).
LCD_REV
O
Reverse control. Signal for common electrode driving signal preparation (Sharp
HR-TFT 240x320 panels only).
LCD_SPL_SPR
O
Sampling start signal. Sets the horizontal scan direction (Sharp HR-TFT
240x320 panels only).
Memory Map/Register Definition
The LCDC memory space contains 21 32-bit registers for display parameters, a read-only status register,
and two 256 × 18 color-mapping RAMs—one for graphic window and the other for background plane.
The color-mapping RAMs are physically located inside the palette lookup table module.
Table 21-3 summarizes these registers and their addresses. Only longword access is supported. Byte and
word access is undefined.
Table 21-3. LCD Controller Memory Map
Width
(bits)
Access
Reset Value
Section/Page
0xFC0A_C000 Screen Start Address Register (LCD_SSAR)
32
R/W
0x0000_0000
21.3.1/21-5
0xFC0A_C004 LCD Size Register (LCD_SR)
32
R/W
0x0000_0000
21.3.2/21-5
0xFC0A_C008 LCD Virtual Page Width Register (LCD_VPW)
32
R/W
0x0000_0000
21.3.3/21-5
0xFC0A_C00C LCD Cursor Position Register (LCD_CPR)
32
R/W
0x0000_0000
21.3.4/21-6
Address
Register
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-3
Liquid Crystal Display Controller (LCDC)
Table 21-3. LCD Controller Memory Map (continued)
Width
(bits)
Access
Reset Value
Section/Page
0xFC0A_C010 LCD Cursor Width Height and Blink Register
(LCD_CWHB)
32
R/W
0x0101_00FF
21.3.5/21-7
0xFC0A_C014 LCD Color Cursor Mapping Register (LCD_CCMR)
32
R/W
0x0000_0000
21.3.6/21-8
0xFC0A_C018 LCD Panel Configuration Register (LCD_PCR)
32
R/W
0x0000_0000
21.3.7/21-9
0xFC0A_C01C LCD Horizontal Configuration Register (LCD_HCR)
32
R/W
0x0400_0000
21.3.8/21-12
0xFC0A_C020 LCD Vertical Configuration Register (LCD_VCR)
32
R/W
0x0400_0000
21.3.9/21-12
0xFC0A_C024 LCD Panning Offset Register (LCD_POR)
32
R/W
0x0000_0000 21.3.10/21-13
0xFC0A_C028 LCD Sharp Configuration Register (LCD_SCR)
32
R/W
0x400C_0373 21.3.11/21-14
0xFC0A_C02C LCD PWM Contrast Control Register (LCD_PCCR)
32
R/W
0x0000_0000 21.3.12/21-16
0xFC0A_C030 LCD DMA Control Register (LCD_DCR)
32
R/W
0x8010_0004 21.3.13/21-16
0xFC0A_C034 LCD Refresh Mode Control Register (LCD_RMCR)
32
R/W
0x0000_0000 21.3.14/21-17
0xFC0A_C038 LCD Interrupt Configuration Register (LCD_ICR)
32
R/W
0x0000_0000 21.3.15/21-18
0xFC0A_C03C LCD Interrupt Enable Register (LCD_IER)
32
R/W
0x0000_0000 21.3.16/21-19
0xFC0A_C040 LCD Interrupt Status Register (LCD_ISR)
32
R/W
0x0000_0000 21.3.17/21-20
0xFC0A_C050 LCD Graphic Window Start Address Register
(LCD_GWSAR)
32
R/W
0x0000_0000 21.3.18/21-22
0xFC0A_C054 LCD Graphic Window Size Register (LCD_GWSR)
32
R/W
0x0000_0000 21.3.19/21-22
0xFC0A_C058 LCD Graphic Window Virtual Page Width Register
(LCD_GWVPW)
32
R/W
0x0000_0000 21.3.20/21-23
0xFC0A_C05C LCD Graphic Window Panning Offset Register
(LCD_GWPOR)
32
R/W
0x0000_0000 21.3.21/21-23
0xFC0A_C060 LCD Graphic Window Position Register (LCD_GWPR)
32
R/W
0x0000_0000 21.3.22/21-24
0xFC0A_C064 LCD Graphic Window Control Register (LCD_GWCR)
32
R/W
0x0000_0000 21.3.23/21-24
0xFC0A_C068 LCD Graphic Window DMA Control Register
(LCD_GWDCR)
32
R/W
0x8010_0004 21.3.24/21-26
0xFC0A_C800 Background Look-up Table (BGLUT)
...
0xFC0A_CBFC
32
R/W
—
21.3.25/21-26
0xFC0A_CC00 Graphic Window Look-up Table (GWLUT)
...
0xFC0A_CFFC
32
R/W
—
21.3.25/21-26
Address
Register
MCF52277 Reference Manual, Rev 2
21-4
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
21.3.1
LCDC Screen Start Address Register (LCD_SSAR)
The screen start address register specifies the start address of the LCD screen.
Address: 0xFC0A_C000 (LCD_SSAR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
0
0 0
SSA
W
1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-2. LCD Screen Start Address Register (LCD_SSAR)
Table 21-4. LCD_SSAR Field Descriptions
Field
Description
31–2
SSA
Screen start address of the LCD panel. Holds pixel data for a new frame from the SSA address. This field must start
at a location that enables a complete picture to be stored in a 4 Mbyte memory boundary (A [21:0]). A [31:22] has a
fixed value for a picture’s image.
1–0
Reserved, must be cleared.
21.3.2
LCDC Size Register (LCD_SR)
The size register defines the height and width of the LCD screen.
Address: 0xFC0A_C004 (LCD_SR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0
XMAX
W
0 0 0 0 0 0 0 0 0 0
8
7
6
5
4
3
2
1
0
YMAX
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-3. LCD Size Register (LCD_SR)
Table 21-5. LCD_SR Field Descriptions
Field
Description
31–26
Reserved, must be cleared.
25–20
XMAX
Screen width divided by 16. Holds screen x-axis size in pixels, divided by 16. For black-and-white panels (1 bpp),
XMAX[0] is ignored, forcing the x-axis of the screen size to be a multiple of 32 pixels/line. A value of zero in this bit
field is reserved.
Note: The maximum supported panel size is 800x600 pixels. Therefore the maximum value for this bit field is 0x32.
19–10
Reserved, must be cleared.
9–0
YMAX
Screen height. Specifies the height of the LCD panel in terms of pixels or lines. The lines are numbered from 1 to
YMAX for a total of YMAX lines. A value of zero in this bit field is reserved.
Note: The maximum supported panel size is 800x600 pixels. Therefore the maximum value for this bit field is 0x258.
21.3.3
LCDC Virtual Page Width Register (LCD_VPW)
The virtual page width register defines the width of the virtual page for the LCD panel.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-5
Liquid Crystal Display Controller (LCDC)
Address: 0xFC0A_C008 (LCD_VPW)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5
4
3
2
1
0
VPW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-4. LCD Virtual Page Width Register (LCD_VPW)
Table 21-6. LCD_VPW Field Descriptions
Field
Description
31–10
Reserved, must be cleared.
9–0
VPW
Virtual page width. Defines the virtual page width of the LCD panel. The VPW bits represent the number of 32-bit
longwords required to hold the data for one virtual line. VPW is used in calculating the starting address representing
the beginning of each displayed line.
21.3.4
LCDC Cursor Position Register (LCD_CPR)
The cursor position register is used to determine the starting position of the cursor on the LCD panel.
Address: 0xFC0A_C00C (LCD_CPR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
CC
0
Reset 0 0 0
OP
0
0 0
CXP
8
0 0 0 0 0 0
7
6
5
4
3
2
1
0
CYP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-5. LCD Cursor Position Register (LCD_CPR)
MCF52277 Reference Manual, Rev 2
21-6
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
Table 21-7. LCD_CPR Field Descriptions
Field
Description
31–30
CC
Cursor control. Controls the format of the cursor and the type of arithmetic operations, if enabled by the OP bit.
1
OP1
CC
X
00
Transparent, cursor is disabled
0
01
1 for non-color displays; color defined in the
LCD_CCMR register for color displays
0
10
Reversed, INV background for non-color displays;
INV color defined in the LCD_CCMR register
for color displays
0
11
0 for non-color displays; AND between background
and cursor for color displays
1
01
OR between background and cursor
1
10
XOR between background and cursor
1
11
AND between background and cursor
Cursor Format
OP = 1 for color modes only.
29
Reserved, must be cleared.
28
OP
Arithmetic operation control. Enables/disables arithmetic operations between the background and the cursor.
0 Arithmetic operation disabled.
1 Arithmetic operation enabled. (Should only be used for color modes.)
27–26
Reserved, must be cleared.
25–16
CXP
Cursor X-position. Indicates the cursor’s horizontal starting position in pixel count (from 0 to LCD_SR[XMAX]).
15–10
Reserved, must be cleared.
9–0
CYP
Cursor Y-position. Indicates the cursor’s vertical starting position in pixel count (from 0 to LCD_SR[YMAX]).
21.3.5
LCDC Cursor Width Height and Blink Register (LCD_CWHB)
The cursor width height and blink register is used to determine the width and height of the cursor, and how
it blinks.
Address: 0xFC0A_C010 (LCD_CWHB)
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R BK_ 0 0
W EN
Reset
0
Access: User read/write
CW
0 0 0
CH
8
7
6
5
0 0 0 0 0 0 0 0
4
3
2
1
0
BD
0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Figure 21-6. LCD Cursor Width Height and Blink Register (LCD_CWHB)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-7
Liquid Crystal Display Controller (LCDC)
Table 21-8. LCD_CWHB Field Descriptions
Field
Description
31
BK_EN
Blink enable. Determines whether the cursor blinks or remains steady.
0 Blink is disabled.
1 Blink is enabled.
30–29
Reserved, must be cleared.
28–24
CW
Cursor width. Specifies the width of the hardware cursor in pixels. This field can be any value between 1 and 31.
Setting this field to zero disables the cursor.
23–21
Reserved, must be cleared.
20–16
CH
Cursor height. Specifies the height of the hardware cursor in pixels. This field can be any value between 1 and 31.
Setting this field to zero disables the cursor.
15–8
Reserved, must be cleared.
7–0
BD
Blink divisor. Sets the cursor blink rate. A 32 Hz clock from the real-time clock (RTC) module is used to clock the 8-bit
up counter. When the counter value equals BD, the cursor toggles on/off. Hence the larger the BD, the slower the
cursor is blinking. The fastest cursor blinking rate is when BD is 0.
21.3.6
LCDC Color Cursor Mapping Register (LCD_CCMR)
The color cursor mapping register defines the color of the cursor in passive or TFT color modes. If the bpp
mode setting is smaller than 18bpp, the cursor color component bits should be put in the msbs. For
example, if the color cursor of RGB = (0x1A, 0x26, 0x05) is wanted, the CUR_COL_R, CUR_COL_G
and CUR_COL_B should be set to 0x34, 0x26 and 0x0A respectively.
Address: 0xFC0A_C014 (LCD_CCMR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
CUR_COL_R
8
7
6
CUR_COL_G
5
4
3
2
1
0
CUR_COL_B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-7. LCD Color Cursor Mapping Register (LCD_CCMR)
Table 21-9. LCD_CCMR Field Descriptions
Field
30–18
Description
Reserved, must be cleared.
17–12
Cursor red field. Defines the red component of the cursor color in color mode.
CUR_COL_R 0x00 No red.
...
0x3F Full red.
MCF52277 Reference Manual, Rev 2
21-8
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
Table 21-9. LCD_CCMR Field Descriptions (continued)
Field
Description
11–6
Cursor green field. Defines the green component of the cursor color in color mode.
CUR_COL_G 0x00 No green.
...
0x3F Full green.
5–0
Cursor blue field. Defines the blue component of the cursor color in color mode.
CUR_COL_B 0x00 No blue.
...
0x3F Full blue.
21.3.7
LCDC Panel Configuration Register (LCD_PCR)
The panel configuration register defines all of the properties of the LCD screen.
Address: 0xFC0A_C018 (LCD_PCR)
R
W
Reset
29
28
31
30
TFT
COL
OR
0
0
0
0
0
0
15
14
13
12
11
10
0
27
PBSIZ
R ACD
W SEL
Reset
Access: User read/write
26
25
24
23
22
21
PIX
POL
FLM
POL
LP
POL
CLK
POL
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
BPIX
0
0
0
19
SCLK
SHARP
SEL
ACD
0
20
0
0
0
0
0
18
17
16
OE SCLK END_ SWAP_ REV_
POL IDLE SEL
SEL
VS
PCD
0
0
0
0
Figure 21-8. LCD Panel Configuration Register (LCD_PCR)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-9
Liquid Crystal Display Controller (LCDC)
Table 21-10. LCD_PCR Field Descriptions
Field
Description
31
TFT
TFT display enable. Controls the format and timing of the output control signals. Active and passive displays use
different signal timing formats as described in Section 21.4.9, “Panel Interface Signals and Timing.” TFT also
controls the use of the frame rate control (FRC) in color mode. Refer to below table for TFT/COLOR setting
usage.
0 The LCD panel is a passive display.
1 The LCD panel is an active display: digital CRT signal format, FRC is bypassed.
TFT
COLOR
LCD Display
0
0
Monochrome
0
1
CSTN
1
0
Reserved
1
1
TFT
30
COLOR
Color display enable. Activates three channels of FRC in passive mode to allow use of the special 2 2/3 pixels
per output vector format. Refer to TFT bit field description for TFT/COLOR setting usage.
0 The LCD panel is a monochrome display.
1 The LCD panel is a color display.
29–28
PBSIZ
Panel bus width. Specifies the panel bus width. Applicable for monochrome or passive matrix color monitors. For
passive color panels, only a 12-bit panel bus width is supported.
00 1-bit
01 Reserved
10 4-bit
11 8-bit
27–25
BPIX
Indicates the number of bits per pixel in memory.
000 1 bpp, FRC bypassed
001 2 bpp
010 4 bpp
011 8 bpp
100 12 bpp (16 bits of memory used)
101 16 bpp
110 18 bpp (32 bits of memory used)
111 Reserved
Note: To set normal 18 bpp mode, use the following settings: BPIX = 110, END_SEL = 0, SWAP_SEL = X (don’t
care). To set Microsoft PAL_BGR 18 bpp mode, use the following: BPIX = 110, END_SEL = 1,
SWAP_SEL = 1.
24
PIXPOL
Pixel polarity.
0 Active high
1 Active low
23
FLMPOL
First line marker polarity.
0 Active high
1 Active low
22
LPPOL
Line pulse polarity.
0 Active high
1 Active low
MCF52277 Reference Manual, Rev 2
21-10
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
Table 21-10. LCD_PCR Field Descriptions (continued)
Field
Description
21
CLKPOL
LCD shift clock polarity. Sets the polarity of the active edge of the LCD shift clock.
0 Active negative edge of LCD_LSCLK (in TFT mode, active on positive edge of LCD_LSCLK)
1 Active positive edge of LCD_LSCLK (in TFT mode, active on negative edge of LCD_LSCLK)
20
OEPOL
LCD output enable polarity.
0 Disable LCD_LSCLK.
1 Enable LCD_LSCLK.
19
LCD SCLK idle enable. Enables/disables LCD_LSCLK when LCD_VSYNC is idle in TFT mode.
SCLKIDLE 0 Disable LCD_LSCLK.
1 Enable LCD_LSCLK.
18
END_SEL
Endian select. Selects the image download into memory as big or little endian format.
0 Little endian.
1 Big endian.
17
Swap Select. LCDC operates in big endian mode internally. Swap Select controls the swap of data before
SWAP_SEL operation in little endian mode.
0 16 bpp, 12 bpp mode.
1 8 bpp, 4 bpp, 2 bpp, 1 bpp mode.
Note: When SWAP_SEL = 0, byte 3 (bits 31–24), byte 2 (bits 23–16), byte 1 (bits 15–8), byte 0 (bits 7–0) data
swapped to byte 1, byte 0, byte 3 and byte 2 respectively.
Note: When SWAP_SEL = 1, byte 3, byte 2, byte 1, byte 0 data swapped to byte 0, byte 1, byte 2 and byte 3
respectively.
16
REV_VS
Reverse vertical scan. Selects the vertical scan direction as normal or reverse (the image flips along the x-axis).
The LCD_SSAR register must be changed accordingly.
0 Vertical scan in normal direction.
1 Vertical scan in reverse direction.
15
ACDSEL
LCD_ACD clock source select. Selects the clock source used by the alternative crystal direction counter.
0 Use LCD_FLM as clock source for ACD count.
1 Use LCD_LP/HSYNC as clock source for ACD count.
14–8
ACD
7
SCLKSEL
6
SHARP
5–0
PCD
Alternate crystal direction. Toggles the LCD_ACD signal once every 1–16 LCD_FLM cycles based on the value
specified in this field. The actual number of LCD_FLM cycles between toggles is the programmed value plus one.
Note: For active mode (TFT=1), this parameter is not used.
LCD_LSCLK select. Selects whether to enable or disable LCD_LSCLK in TFT mode when there is no data
output.
0 Disable LCD_OE and LCD_LSCLK in TFT mode when no data output.
1 Always enable LCD_LSCLK in TFT mode even if there is no data output.
Sharp panel enable. Enables/disables signals for Sharp HR-TFT 240 x 320 panels.
0 Disable Sharp signals.
1 Enable Sharp signals.
Pixel clock divider. Indicates the clock divider value. The LCDC clock (fsys/2) is divided by N (PCD plus one) to
yield the pixel clock rate. Values of 1 to 63 yield N=2 to 64. The pixel clock rate is faster than LCD_LSCLK by a
factor equal to the data bus width for monochrome display. For all other displays, the pixel clock rate is the same
as LCD_LSCLK.
Note: Set PCD so that the LCD_LSCLK frequency is less than one-third (TFT mode) or one-fourth (CSTN mode)
of the system bus clock (fsys/2) frequency. Otherwise, the line data (LCD_D) is incorrect.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-11
Liquid Crystal Display Controller (LCDC)
21.3.8
LCDC Horizontal Configuration Register (LCD_HCR)
The horizontal configuration register defines the horizontal sync pulse timing. For detailed settings, please
refer to the panel’s data sheet.
Address: 0xFC0A_C01C (LCD_HCR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
H_WIDTH
0 0 0 0 0 0 0 0 0 0
8
7
6
H_WAIT_1
5
4
3
2
1
0
H_WAIT_2
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-9. LCD Horizontal Configuration Register (LCD_HCR)
Table 21-11. LCD_HCR Field Descriptions
Field
Description
31–26
Horizontal sync pulse width. Specifies the number of LCD_LSCLK periods that LCD_HSYNC is activated. The
H_WIDTH active time is equal to (H_WIDTH + 1) of the LCD_LSCLK periods.
25–16
Reserved, must be cleared.
15–8
Wait between LCD_OE and LCD_HSYNC. In TFT mode, this field specifies the number of LCD_LSCLK periods
H_WAIT_1 between the end of LCD_OE signal and the beginning of the LCD_HSYNC. Total delay time equals
(H_WAIT_1 + 1) of LCD_LSCLK periods.
In CSTN mode, H_WAIT_1 specifies the number of LCD_LSCLK periods between the last display data and the
beginning of the LCD_HSYNC signal. Total delay time equals (H_WAIT_1 + 1) of LCD_LSCLK periods.
7–0
Wait between LCD_HSYNC and start of next line. In TFT mode, this field specifies the number of LCD_LSCLK
H_WAIT_2 periods between the end of LCD_HSYNC and the beginning of the LCD_OE signal. Total delay time equals
(H_WAIT_2 + 3).
In CSTN mode, H_WAIT_2 specifies the number of LCD_LSCLK periods between the end of LCD_HSYNC and
the first display data in each line. Total delay time equals (H_WAIT_2 + 2) of LCD_LSCLK periods.
21.3.9
LCDC Vertical Configuration Register (LCD_VCR)
The vertical configuration register defines the vertical sync pulse timing. For detailed settings, please refer
to the panel’s data sheet.
Address: 0xFC0A_C020 (LCD_VCR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
V_WIDTH
0 0 0 0 0 0 0 0 0 0
8
7
6
V_WAIT_1
5
4
3
2
1
0
V_WAIT_2
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-10. LCD Vertical Configuration Register (LCD_VCR)
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
Table 21-12. LCD_VCR Field Descriptions
Field
Description
31–26
Vertical sync pulse width. Specifies the width, in lines, of the LCD_VSYNC pulse for active mode (TFT=1). For a
V_WIDTH value of 0x01, the vertical sync pulse encompasses one LCD_HSYNC pulse. For a value of 0x02, the vertical sync
pulse encompasses two LCD_HSYNC pulses, and so on. For passive mode (TFT=0) and non-color mode, see
Figure 21-39.
25–16
Reserved, must be cleared.
15–8
Wait between frames 1. Defines the delay, in lines, between the end of the LCD_OE pulse and the beginning of
V_WAIT_1 the LCD_VSYNC pulse for active mode (TFT=1). This field has no meaning in passive non-color mode. The actual
delay is V_WAIT_1 lines. In passive color mode, this field is the delay, measured in virtual clock periods, between
the last line of the frame to the beginning of the next frame.
7–0
Wait between frames 2. Defines the delay, in lines, between the end of the LCD_VSYNC pulse and the beginning
V_WAIT_2 of the LCD_OE pulse of the first line in active mode (TFT=1). The actual delay is V_WAIT_2 lines. Set this field to
zero for passive non-color mode. The minimum value of this field is 0x01.
21.3.10 LCDC Panning Offset Register (LCD_POR)
The panning offset register sets up the panning for the image.
Address: 0xFC0A_C024 (LCD_POR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
4
3
2
1
0
POS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-11. LCD Panning Offset Register (LCD_POR)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-13
Liquid Crystal Display Controller (LCDC)
Table 21-13. LCD_POR Field Descriptions
Field
Description
31–5
Reserved, must be cleared.
4–0
POS
Panning offset. Defines the number of bits that the data from memory is panned to the left before processing. The
POS field is read by the LCDC once at the beginning of each frame.
For example, in 4 bpp mode, setting POS = 16 shifts the data 16bits, which equates to panning the image by 4 pixels
to the left.
Note: Use the LSSAR register to shift the data more than 32 bits or for 18 bpp panning.
To achieve panning of the final image by N bits:
Bits Per Pixel
POS
Effective # of pixels
Panned on Image
1
N
N
2
2N
N
4
4N
N
8
8N
N
12/16
16N
N
21.3.11 LCDC Sharp Configuration Register (LCD_SCR)
For 2 bpp modes, full black and full white are the two predefined display levels. The other two
intermediate gray-scale shading densities can be adjusted within the Sharp configuration register. The
LCD_SCR register also controls the relative delay timing of the LCD_CLS, LCD_REV, and LCD_PS
signals. For detailed Sharp panel settings, please refer to panel’s data sheet. The TFT timing diagram that
shows the relationship between these signals is shown in Figure 21-13.
Address: 0xFC0A_C028 (LCD_SCR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R
W
PS_RISE_DELAY
0 0
CLS_RISE_DELAY
0 0 0 0
9
8
REV_TOG
GLE_DELAY
Reset 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
7
6
5
GRAY2
4
3
2
1
0
GRAY1
1 1 0 1 1 1 0 0 1 1
Figure 21-12. LCD Sharp Configuration Register (LCD_SCR)
Table 21-14. LCD_SCR Field Descriptions
Field
Description
31–26
PS_RISE_
DELAY
LCD_PS rise delay. Controls the delay of the rising edge of LCD_PS relative to the falling edge of LCD_CLS.
Total delay time is equal to PS_RISE_DELAY LCD_LSCLK periods.
0x00 Zero LCD_LSCLK periods
...
0x3F 63 LCD_LSCLK periods
25–24
Reserved, must be cleared.
MCF52277 Reference Manual, Rev 2
21-14
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
Table 21-14. LCD_SCR Field Descriptions (continued)
Field
Description
23–16
CLS_RISE_
DELAY
LCD_CLS rise delay. Controls the delay of the rising edge of LCD_CLS relative to the last line data of the
line. Total delay time is equal to (CLS_RISE_DELAY + 1) LCD_LSCLK periods
0x00 1 LCD_LSCLK period
…
0xFF 256 LCD_LSCLK periods
15–12
Reserved, must be cleared.
11–8
LCD_REV toggle delay. Controls the transition delay of LCD_REV relative to the last line data of the line.
REV_TOGGLE_ Total delay time is equal to (REV_TOGGLE_DELAY + 1) LCD_LSCLK periods
DELAY
0x0 1 LCD_LSCLK period
…
0xF 16 LCD_LSCLK periods
7–4
GRAY2
Grayscale 2. Represents one of the two grayscale shading densities. This field is programmable to any value
between 0 and 16 (0 and 16 are already defined as two of the four colors).
3–0
GRAY1
Grayscale 1. Represents one of the two grayscale shading densities. This field is programmable to any value
between 0 and 16 (0 and 16 are already defined as two of the four colors).
XMAX
LCD_LSCLK
R0–R5
G0–G5
B0–B5
D320
D1
D320
D2
1 LCD_LSCLK
LCD_SPL_SPR
Hwait1+1
Hwait1 + 1
Hwait2+4
LCD_LP
cls_rise_delay + 1
cls_hi_width + 1
LCD_CLS
LCD_PS
ps_rise_delay
rev_tog_delay +1
rev_tog_delay +1
LCD_REV
Falling edge of LCD_PS aligns with rising edge of LCD_CLS
The rising edge delay of LCD_PS is programmed by PS_RISE_DELAY
CLS_HI_WIDTH is equal to PWM_SCR0 • 256 + PWM_WIDTH in units of
LCD_LSCLK.
LCD_SPL_SPR pulse width is fixed and aligned to the first data of the line.
Figure 21-13. Horizontal Timing
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-15
Liquid Crystal Display Controller (LCDC)
21.3.12 LCDC PWM Contrast Control Register (LCD_PCCR)
The PWM contrast control register is used to control the signal output at the contrast pin, which controls
the contrast of the LCD panel.
Address: 0xFC0A_C02C (LCD_PCCR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0
CLS_HI_WIDTH
W
15
14 13 12 11 10 9
8
7
CC_
LD 0 0 0 0
SCR
EN
MSK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0
0
6
5
4
3
2
1
0
PW
0 0 0 0 0 0 0 0
Figure 21-14. LCD PWM Contrast Control Register (LCD_PCCR)
Table 21-15. LCD_PCCR Field Descriptions
Field
31–25
Description
Reserved, must be cleared.
24–16 LCD_CLS high pulse width. Controls the pulse width of LCD_CLS in units of LCD_LSCLK. The actual pulse width
CLS_HI_ is CLS_HI_WDITH + 1.
WIDTH
15
LDMSK
LD mask. Enables/disables the line data (LCD_D[17:0]) output to zero for the Sharp TFT panel power-off sequence.
0 LCD_D[17:0] is normal.
1 LCD_D[17:0] always equals 0.
14–11
Reserved, must be cleared.
10–9
SCR
Source select. Selects the input clock source for the PWM counter. The PWM output frequency is equal to the
frequency of the input clock divided by 256.
00 Line pulse
01 Pixel clock
10 LCD clock (fsys/2)
11 Reserved
8
CC_EN
7–0
PW
Contrast control enable. Enables/disables the contrast control function.
0 Contrast control is off.
1 Contrast control is on.
Pulse width. Controls the pulse width of the built-in pulse width modulator, which controls the contrast of the LCD
screen.
21.3.13 LCDC DMA Control Register (LCD_DCR)
There is a 32 × 32 bit line buffer in the LCDC that stores DMA data from system memory. The DMA
control register controls the DMA burst length and when to trigger a DMA burst in terms of the number
of data bytes left in the pixel buffer.
MCF52277 Reference Manual, Rev 2
21-16
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
Address: 0xFC0A_C030 (LCD_DCR)
31
R
W
Reset
BURST
1
Access: User read/write
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0 0 0
HM
8
7
6
5
4
3
0 0 0 0 0 0 0 0 0 0 0
2
1
0
TM
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Figure 21-15. LCD DMA Control Register (LCD_DCR)
Table 21-16. LCD_DCR Field Descriptions
Field
Description
31
BURST
Burst length. Determines whether the burst length is fixed or dynamic.
0 Burst length is dynamic
1 Burst length is fixed
30–21
Reserved, must be cleared.
20–16
HM
DMA high mark. Establishes the high mark for DMA requests. For dynamic burst length, after the DMA request is
made, data is loaded and the pixel buffer continues to be filled until the number of empty longwords left in the DMA
FIFO is equal to the high mark minus 2. The minimum HM setting in dynamic burst is 3.
For fixed burst length, the burst length (in longwords) of each request is equal to the HM setting and its value must
be larger than TM.
15–5
Reserved, must be cleared.
4–0
TM
DMA trigger mark. Sets the low-level mark in the pixel buffer to trigger a DMA request. The low-level mark equals
the number of longwords left in the pixel buffer.
NOTE
For SDRAM access, a fixed burst length of 16 is recommended:
BURST = 1; HM = 16; TM = 4
For a heavily loaded bus that requires SDRAM access, a dynamic burst length is recommended:
BURST = 0; HM = 4; TM = 8
21.3.14 LCDC Refresh Mode Control Register (LCD_RMCR)
The refresh mode control register is used to enable/disable self-refresh mode.
Address: 0xFC0A_C034 (LCD_RMCR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELF_
REF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
Figure 21-16. LCD Refresh Mode Control Register (LCD_RMCR)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-17
Liquid Crystal Display Controller (LCDC)
Table 21-17. LCD_RMCR Field Descriptions
Field
31–1
Description
Reserved, must be cleared.
0
Self-refresh mode enable.
SELF_REF 0 Disable self-refresh.
1 Enable self-refresh.
NOTE
1. On entering self-refresh mode, the LCD_LSCLK and LCD_D[17:0] signals stay low. HYSN and
VSYN operate normally.
2. Except for the SSA, BGLUT, and GWLUT registers, all configurations must be performed before
enabling the LCDC to avoid a malfunction.
3. The SSA must always match the address range of the RAM selected. If the user wants to switch
between various types of RAM, the LCDC must be disabled before switching.
21.3.15 LCDC Interrupt Configuration Register (LCD_ICR)
The interrupt configuration register is used to configure the interrupt conditions.
Address: 0xFC0A_C038 (LCD_ICR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GW_ 0
0
INT_
INT
W
SYN
_CON
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
INT_
CON
0
Figure 21-17. LCD Interrupt Configuration Register (LCD_ICR)
Table 21-18. LCD_ICR Field Descriptions
Field
31–5
4
GW_INT_
CON
3
Description
Reserved, must be cleared.
Graphic window interrupt condition. Determines if an interrupt condition is set at the beginning or the end of graphic
window condition.
0 Interrupt flag is set when the end of a graphic window is reached
1 Interrupt flag is set when the beginning of a graphic window is reached
Reserved, must be cleared.
MCF52277 Reference Manual, Rev 2
21-18
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
Table 21-18. LCD_ICR Field Descriptions (continued)
Field
Description
2
INT_SYN
Interrupt source. Determines if an interrupt flag is set during last data/first data of frame loading or on last data/first
data of frame output to the LCD panel. Please refer to the below table for INTSYN/INTCON setting usage.
There is a latency between loading the last/first data of frame to output to LCD panel.
0 Interrupt flag is set on loading the last data/first data of frame from memory
1 Interrupt flag is set on output of the last data/first data of frame to LCD panel
INTSYN INTCON
1
Description
0
0
Interrupt flag is set on loading last data of
frame from memory.
0
1
Interrupt flag is set on loading first data of
frame from memory.
1
0
Interrupt flag is set on output of last data
of frame to LCD panel.
1
1
Interrupt flag is set on output of first data
of frame to LCD panel.
Reserved, must be cleared.
0
INT_CON
Interrupt condition. Determines if an interrupt condition is set at the beginning or the end of frame condition. Refer
to table in the INT_SYN field description for INTSYN/INTCON setting usage.
0 Interrupt flag is set when the End of Frame (EOF) is reached
1 Interrupt flag is set when the Beginning of Frame (BOF) is reached
21.3.16 LCDC Interrupt Enable Register (LCD_IER)
The LCDC interrupt enable Register is used to enable the LCDC interrupt signal generated to the interrupt
controller. When the interrupt is masked, the LCDC does not generate the interrupt request, but its status
can be observed in the interrupt status register.
Address: 0xFC0A_C03C (LCD_IER)
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
GW
UDR
GW
ERR
GW
EOF
GW
BOF
UDR
ERR
EOF
BOF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 21-18. LCD Interrupt Endable Register (LCD_IER)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-19
Liquid Crystal Display Controller (LCDC)
Table 21-19. LCD_IER Field Descriptions
Field
31–8
Description
Reserved, must be cleared.
7
GWUDR
Graphic window underrun error interrupt enable.
0 Mask interrupt.
1 Enable interrupt.
6
GWERR
Graphic window error response interrupt enable.
0 Mask interrupt.
1 Enable interrupt.
5
GWEOF
Graphic window end-of-frame interrupt enable.
0 Mask interrupt.
1 Enable interrupt.
4
GWBOF
Graphic window beginning-of-frame interrupt enable.
0 Mask interrupt.
1 Enable interrupt.
3
UDR
Underrun error interrupt enable.
0 Mask interrupt.
1 Enable interrupt.
2
ERR
Error response interrupt enable.
0 Mask interrupt.
1 Enable interrupt.
1
EOF
End-of-frame interrupt enable.
0 Mask interrupt.
1 Enable interrupt.
0
BOF
Beginning-of-frame interrupt enable.
0 Mask interrupt.
1 Enable interrupt.
21.3.17 LCDC Interrupt Status Register (LCD_ISR)
The read-only interrupt status register indicates whether an interrupt has occurred. The status bit is set
when the interrupt condition is met. If any bit in this register is set and the corresponding bit in the
LCD_IER register is set, an LCD interrupt is asserted to the interrupt controller. The status bit is cleared
by reading the register.
MCF52277 Reference Manual, Rev 2
21-20
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
Address: 0xFC0A_C040 (LCD_ISR)
R
Access: User read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GW
ERR
GW
EOF
GW
BOF
UDR
ERR
EOF
BOF
0
0
0
0
0
0
0
W
Reset
R
0
0
0
0
0
0
0
0
GW
UDR
0
0
0
0
0
0
0
0
0
W
Reset
Figure 21-19. LCD Interrupt Status Register (LCD_ISR)
Table 21-20. LCD_ISR Field Descriptions
Field
31–8
Description
Reserved, must be cleared.
7
GWUDR
Graphic window underrun error. Indicates whether the LCDC FIFO in the graphic window plane has hit an underrun
condition. This is when the data output rate is faster than the data input rate to the FIFO of the graphic window plane.
Underrun can cause erroneous data output to LCD_D. The LCD_D data output rate must be adjusted to prevent
this error.
0 Interrupt has not occurred.
1 Interrupt has occurred.
6
GWERR
Graphic window error response interrupt. Indicates whether the LCDC has issued a read data request in graphic
window and has received a bus error. It is cleared by reading the status register, at power on reset, or when the
LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
5
GWEOF
Graphic window end-of-frame interrupt. Indicates whether the end of graphic window has been reached. It is
cleared by reading the status register, at power on reset, or when the LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
4
GWBOF
Graphic window beginning-of-frame interrupt. Indicates whether the beginning of the graphic window has been
reached. It is cleared by reading the status register, at power on reset, or when the LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
3
UDR
Underrun error interrupt. Indicates whether the LCDC FIFO has hit an underrun condition. This is when the data
output rate is faster than the data input rate to the FIFO. Underrun can cause erroneous data output to LCD_D. The
LCD_D data output rate must be adjusted to prevent this error.
0 Interrupt has not occurred.
1 Interrupt has occurred.
2
ERR
Error response interrupt. Indicates whether the LCDC has issued a read data request and has received a bus error.
It is cleared by reading the status register, at power on reset, or when the LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-21
Liquid Crystal Display Controller (LCDC)
Table 21-20. LCD_ISR Field Descriptions (continued)
Field
Description
1
EOF
End-of-frame interrupt. Indicates whether the end of frame has been reached. It is cleared by reading the status
register, at power on reset, or when the LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
0
BOF
Beginning-of-frame interrupt. Indicates whether the beginning of frame has been reached. It is cleared by reading
the status register, at power on reset, or when the LCDC is disabled.
0 Interrupt has not occurred.
1 Interrupt has occurred.
21.3.18 LCDC Graphic Window Start Address Register (LCD_GWSAR)
The LCDC graphic window start address register defines the starting address of the graphic window
image.
Address: 0xFC0A_C050 (LCD_GWSAR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
5
4
3
2
0
0 0
GWSA
W
1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-20. LCD Graphic Window Start Address Register (LCD_GWSAR)
Table 21-21. LCD_GWSAR Field Descriptions
Field
Description
31–2
GWSA
Graphic window start address on LCD screen. Holds the starting address of the graphic window picture. This field
must start at a location that enables a complete graphic window picture to be stored in a 4 Mbyte memory boundary
(A[21:0]). A[31:22] has a fixed value for the graphic window picture’s image.
1–0
Reserved, must be cleared.
21.3.19 LCDC Graphic Window Size Register (LCD_GWSR)
The LCDC graphic window size register defines the height and width of the graphic window on the LCD
screen.
Address: 0xFC0A_C054 (LCD_GWSR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0
W
GW_XMAX
0 0 0 0 0 0 0 0 0 0
8
7
6
5
4
3
2
1
0
GW_YMAX
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-21. LCD Graphic Window Size Register (LCD_GWSR)
MCF52277 Reference Manual, Rev 2
21-22
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
Table 21-22. LCD_GWSR Field Descriptions
Field
Description
31–26
Reserved, must be cleared.
25–20
Graphic window width divided by 16. Holds graphic window x-axis size, divided by 16. For black-and-white panels (1
GW_XMAX bpp), GW_XMAX[0] is ignored, forcing the x-axis of the screen size to be a multiple of 32 pixels/line. The graphic
window size cannot be set to 0.
Note: The maximum supported panel size is 800x600 pixels. Therefore the maximum value for this bit field is 0x32.
19–10
Reserved, must be cleared.
9–0
Graphic window height. Specifies the height of the graphic window in terms of pixels or lines. The lines are numbered
GW_YMAX from 1 to GW_YMAX for a total of GW_YMAX lines. The graphic window size cannot be set to 0.
Note: The maximum supported panel size is 800x600 pixels. Therefore the maximum value for this bit field is 0x258.
21.3.20 LCDC Graphic Window Virtual Page Width Register (LCD_GWVPW)
The graphic window virtual page width register defines the width of the virtual page for the graphic
window picture on the LCD screen.
Address: 0xFC0A_C058 (LCD_GWVPW)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6
5
4
3
2
1
0
GWVPW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-22. LCD Graphic Window Virtual Page Width Register (LCD_GWVPW)
Table 21-23. LCD_GWVPW Field Descriptions
Field
Description
31–10
Reserved, must be cleared.
9–0
GWVPW
Graphic window virtual page width. Defines the virtual page width of the graphic window picture. The VPW bits
represent the number of 32-bit longwords required to hold the data for one virtual line. GWVPW is used in
calculating the starting address representing the beginning of each line of the graphic window picture.
21.3.21 LCDC Graphic Window Panning Offset Register (LCD_GWPOR)
The panning offset register sets up the panning for the image.
Address: 0xFC0A_C05C (LCD_GWPOR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Access: User read/write
8
7
6
5
4
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
3
2
1
0
GWPO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-23. LCD Graphic Window Panning Offset Register (LCD_GWPOR)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-23
Liquid Crystal Display Controller (LCDC)
Table 21-24. LCD_GWPOR Field Descriptions
Field
Description
31–5
Reserved, must be cleared.
4–0
GWPO
Graphic window panning offset. Defines the number of bits that the graphic window data from memory is panned
to the left before processing. GWPO is read by the LCDC once at the beginning of each frame. For example, in
4 bpp mode, setting GWPO = 16 shifts 16 bits, which means panning the image by 4 pixels left.
Note: Use the LGWSAR register to shift the data more than 32 bits or for 18 bpp panning.
To achieve panning of the final image by N bits:
Bits Per Pixel
GWPO
Effective # of pixels
Panned on Image
1
N
N
2
2N
N
4
4N
N
8
8N
N
12/16
16N
N
21.3.22 LCDC Graphic Window Position Register (LCD_GWPR)
The LCDC graphic window position register is used to determine the starting position of the graphic
window on the LCD panel.
Address: 0xFC0A_C060 (LCD_GWPR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0
GWXP
W
0 0 0 0 0 0
8
7
6
5
4
3
2
1
0
GWYP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-24. LCD Graphic Window Position Register (LCD_GWPR)
Table 21-25. LCD_GWPR Field Descriptions
Field
Description
31–26
Reserved, must be cleared.
25–16
GWXP
Graphic window X-position. Represents the graphic window’s horizontal starting position in pixel count (from 0 to
XMAX).
15–10
Reserved, must be cleared.
9–0
GWYP
Graphic window Y-position. Represents the graphic window’s vertical starting position in lines (from 0 to YMAX).
21.3.23 LCDC Graphic Window Control Register (LCD_GWCR)
The LCD graphic window control register defines various aspects of the graphic window.
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Liquid Crystal Display Controller (LCDC)
NOTE
The graphic window can only be enabled while the clock to the LCD
controller is disabled (MISCCR[LCDCHEN] is cleared). See Chapter 9,
“Chip Configuration Module (CCM),” for details on this bit. The graphics
window can be disabled at any time.
Address: 0xFC0A_C064 (LCD_GWCR)
31 30 29 28 27 26 25 24
R
GWAV
W
23
Access: User read/write
22
21
20 19 18 17 16 15 14 13 12 11 10 9
GW_
0 0 0
GW
GWE RVS
CKE
Reset 0 0 0 0 0 0 0 0
0
0
0
GWCKR
8
7
GWCKG
6
5
4
3
2
1
0
GWCKB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-25. LCD Graphic Window Control Register (LCD_GWCR)
Table 21-26. LCD_GWCR Field Descriptions
Field
Description
31–24
GWAV
Graphic window alpha value. Defines the alpha value of graphic window used for alpha blending between the graphic
window and the background plane
0 Graphic window totally transparent, not displayed on the LCD screen.
1 Graphic window totally opaque, completely visible on the LCD screen.
23
Graphic window color keying enable. Enable or disable graphic window color keying.
GWCKE 0 Disable color keying of graphic window.
1 Enable color keying of graphic window.
22
GWE
Graphic window enable. Enable or disable graphic window displayed on screen.
0 Disable graphic window on screen.
1 Enable graphic window on screen.
21
Graphic window reverse vertical scan. Selects the graphic window vertical scan direction as normal or reverse
GW_RVS (graphic window image flips along the x-axis). The LGWSAR must be changed accordingly.
0 Vertical scan in normal direction.
1 Vertical scan in reverse direction.
20–18
Reserved, must be cleared.
17–12 Graphic window color keying red component. Defines the red component of graphic window color keying.
GWCKR 0x00 No red
…
0x3F Full red
11–6
Graphic window color keying green component. Defines the green component of graphic window color keying.
GWCKG 0x00 No green
…
0x3F Full green
5–0
Graphic window color keying blue component. Defines the blue component of graphic window color keying.
GWCKB 0x00 No blue
…
0x3F Full blue
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Liquid Crystal Display Controller (LCDC)
21.3.24 LCDC Graphic Window DMA Control Register (LCD_GWDCR)
There is a 32 × 32 bit line buffer in the LCDC that stores graphic window data from system memory. The
graphic window DMA control register controls the DMA burst length and when to trigger a DMA burst in
terms of the number of data bytes left in the pixel buffer.
Address: 0xFC0A_C068 (LCD_GWDCR)
31
R
W
Reset
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
GWBT
1
Access: User read/write
0 0 0 0 0 0 0 0 0 0
GWHM
8
7
6
5
0 0 0 0 0 0 0 0 0 0 0
4
3
2
1
0
GWTM
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Figure 21-26. LCD Graphic Window DMA Control Register (LCD_GWDCR)
Table 21-27. LCD_GWDCR Field Descriptions
Field
Description
31
GWBT
Graphic window DMA burst type. Determines whether the burst length is fixed or dynamic in graphic window plane.
0 Burst length is dynamic
1 Burst length is fixed
30–21
Reserved, must be cleared.
20–16
GWHM
Graphic window DMA high mark. Establishes the high mark for DMA requests. For dynamic burst length, after the
DMA request is made, data is loaded and the graphic window FIFO continues to be filled until the number of empty
longwords left in the graphic window FIFO is equal to the high mark minus 2. The minimum GWHM setting in dynamic
burst is 3. For fixed burst length, the burst length (in longwords) of each request is equal to the GWHM setting and
its value must be larger than GWTM.
15–5
4–0
GWTM
Reserved, must be cleared.
Graphic window DMA trigger mark. Sets the low level mark in the graphic window FIFO to trigger a DMA request.
The low level mark equals the number of longwords left in the pixel buffer.
21.3.25 Mapping RAM Registers (BGLUT and GWLUT)
There are two separate mapping RAMs in the LCD controller, the background lookup table (BGLUT) and
the graphic window lookup table (GWLUT). The BGLUT is for the background plane and the mapping
table is addressable from 0xFC0A_C800–0xFC0A_CBFC. The GWLUT is for the graphic window and
its mapping table is addressable from 0xFC0A_CC00–0xFC0A_CFFC.
These mapping RAMs are used for mapping 4-bit codes for grayscale to 16 gray shades, and for mapping
4-bit color and 8-bit color to 16 colors and 256 colors, respectively, out of a palette of 4096 (passive panels)
or 256K (active panels).
The mapping RAM contains 256 entries and each entry is accessed with longword transactions only and
the address must be longword aligned. Unimplemented bits are read as 0. All read and write data use the
least significant 12 or 18 bits.
NOTE
Byte or word access to the RAM corrupts its contents.
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Liquid Crystal Display Controller (LCDC)
In 4 bpp mode, the first 16 RAM entries are used. In 8 bpp mode, all 256 RAM entries are used. The color
RAM is not initialized at reset. Only the following settings use the mapping RAMs:
• 4 bpp gray-scale mode
• 4 bpp passive matrix color mode
• 8 bpp passive matrix color mode
• 4 bpp active matrix color mode
• 8 bpp active matrix color mode
21.3.25.1 Four Bits Per Pixel Gray-Scale Mode
In four bits per pixel gray-scale mode, a 4-bit code represents a gray-scale level. The first 16 mapping
RAM entries must be written to define the codes for all 16 combinations.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
GPM
Table 21-28. Four Bits Per Pixel Gray-Scale Mode
Field
Description
31–4
Reserved, must be cleared.
3–0
GPM
Gray palette map. Represents the gray-scale level for a given pixel code.
21.3.25.2 Four Bits Per Pixel Passive Matrix Color Mode
In four bits per pixel passive matrix color mode, a 4-bit code represents a 12-bit color. Because only four
bits are used to encode the color, a maximum of 16 colors can be selected out of a palette of 4096. The first
16 mapping RAM entries must be written to define the codes for the 16 available combinations.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
R
7
6
5
G
4
3
2
1
0
B
Table 21-29. Four Bits Per Pixel Passive Matrix Color Mode
Field
Description
31–12
Reserved, must be cleared.
11–8
R
Red level (color display). Represents the red component level in the color.
7–4
G
Green level (color display). Represents the green component level in the color.
3–0
B
Blue level (color display). Represents the blue component level in the color.
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Liquid Crystal Display Controller (LCDC)
21.3.25.3 Eight Bits Per Pixel Passive Matrix Color Mode
In eight bits per pixel passive matrix color mode, an 8-bit code represents a 12-bit color. Because eight bits
are used to encode the color, a maximum of 256 colors can be selected out of a palette of 4096. All 256
mapping RAM entries must be written to define the codes for the 256 available combinations.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
R
5
4
3
2
G
1
0
B
Table 21-30. Eight Bits Per Pixel Passive Matrix Color Mode
Field
Description
31–12
Reserved, must be cleared.
11–8
R
Red level (color display). Represents the red component level in the color.
7–4
G
Green level (color display). Represents the green component level in the color.
3–0
B
Blue level (color display). Represents the blue component level in the color.
21.3.25.4 Four Bits Per Pixel Active Matrix Color Mode
In four bits per pixel active color mode, a 4-bit code represents a 18-bit color. Because only four bits are
used to encode the color, a maximum of 16 colors can be selected out of a palette of 256K. The first 16
mapping RAM entries must be written to define the codes for the 16 available combinations.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
G
5
4
3
2
1
0
B
Table 21-31. Four Bits Per Pixel Active Matrix Color Mode
Field
Description
31–18
Reserved, must be cleared.
17–12
R
Red level (color display). Represents the red component level in the color.
11–6
G
Green level (color display). Represents the green component level in the color.
5–0
B
Blue level (color display). Represents the blue component level in the color.
21.3.25.5 Eight Bits Per Pixel Active Matrix Color Mode
In eight bits per pixel active color mode, an 8-bit code represents an 18-bit color. Because eight bits are
used to encode the color, a maximum of 256 colors can be selected out of a palette of 256K. All 256
mapping RAM entries must be written to define the codes for the 256 available combinations.
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Liquid Crystal Display Controller (LCDC)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
8
7
6
G
5
4
3
2
1
0
B
Table 21-32. Eight Bits Per Pixel Active Matrix Color Mode
Field
Description
31–18
Reserved, must be cleared.
17–12
R
Red level (color display). Represents the red component level in the color.
11–6
G
Green level (color display). Represents the green component level in the color.
5–0
B
Blue level (color display). Represents the blue component level in the color.
21.4
Functional Description
The following sections describe the operation of the LCD controller with various industry standard LCD
displays.
21.4.1
LCD Screen Format
The number of pixels forming the screen width and screen height of the LCD panel are software
programmable. Figure 21-27 shows the relationship between the screen size and memory window.
Virtual Page Width (VPW)
Screen Starting Address (SSA)
Screen Height (YMAX)
Virtual Page Height (VPH)
Screen Width (XMAX)
Figure 21-27. LCD Screen Format
The screen width (XMAX) and screen height (YMAX) parameters specify the LCD panel size. The LCDC
begins scanning the display memory at the location pointed to by the screen starting address register
(LCD_SSAR), represented by the shaded area in Figure 21-27, for display on the LCD panel.
The maximum page width is specified by the virtual page width (VPW) parameter. Virtual page height
(VPH) does not affect the LCDC and is limited only by memory size. By changing the SSA register, a
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Freescale Semiconductor
21-29
Liquid Crystal Display Controller (LCDC)
screen-sized window can be vertically or horizontally scrolled (panned) anywhere inside the virtual page
boundaries. The software must control the starting address in the SSA properly so that the scanning logic’s
system memory pointer (SMP) stays within the VPW and VPH limits to prevent the display of strange
artifacts on the screen.
VPH is used by the programmer only for boundary checks. There is no VPH parameter internal to the
LCDC.
VPW is used in calculating the RAM starting address representing the beginning of each displayed line.
SSA sets the address of data for the first line of a frame. For each subsequent line, VPW is added to an
accumulation initialized by the SSA to yield the starting address of that line.
21.4.2
Graphic Window on Screen
Graphic window is supported in LCD color panel screens for viewfinder and graphic hardware cursor
functions. Similar to the screen, the virtual page width, graphic window start address and graphic window
width and height are software programmable. The position of the graphic window on screen is specified
by the graphic window position register. Figure 21-28 shows how the graphic window is configured and
placed on the screen.
Graphic Window Virtual Page Width
Background Image
Graphic Window Image
Graphic Window Width
Screen
Graphic
Window
Height
Graphic window
Graphic Window Start Address
Graphic Window Position
Figure 21-28. Graphic Window on Screen
The graphic window and background plane can be alpha blended. The alpha value is programmable on a
window basis, which means all the pixels in the graphic window have the same level of transparency.
There are a total of 256 levels of transparency to be configured. In addition, one of the pixel colors can be
chosen for color keying in which the selected pixel color in the graphics window is made totally
transparent. One of the applications can be a graphical hardware cursor.
NOTE
The graphic window and background images must have the same bpp
setting.
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Liquid Crystal Display Controller (LCDC)
21.4.3
Panning
Panning offset (POS) is expressed in bits, not pixels, so when operating in any mode other than 1 bpp, only
even pixel boundaries are valid. In 12 bpp mode, the pixels are aligned to 16-bit boundaries, and POS also
must align to these boundaries.
SSA and POS are located in isolated registers and are double buffered because they are dynamic
parameters likely to change while the LCDC is running. New values of SSA and POS do not take effect
until the beginning of the next frame. A typical panning algorithm includes an interrupt at the beginning
of the frame. In the interrupt service routine, POS and/or SSA are updated (the old values are internally
latched). The updates take effect on the next frame.
21.4.4
Display Data Mapping
The LCDC supports 1/2/4 bpp in monochrome mode and 4/8/12/16/18 bpp in color mode. System memory
data mapping in 2/4/8/12/16/18 bpp modes is shown in Figure 21-29.
NOTE
In 12 bpp mode, 16 bits of memory are used for each set of 12 bits, to leave
4 bits unused. In 18 bpp mode, 32 bits of memory are used for each pixel,
leaving 14 bits unused. Refer to Figure 21-30 and Figure 21-31.
P0
P1
P2
P3
LCD Screen
Figure 21-29. Pixel Location on Display Screen
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Freescale Semiconductor
21-31
Liquid Crystal Display Controller (LCDC)
1 bpp Mode
Byte
Address
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0
P1
P2
P3
P4
P5
P6
P7
Bit 9
Bit 8
P14
P15
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
P9
P10
P11
P12
P13
P17
P18
P19
P20
P21
P22
P25
P26
P27
P28
P29
Bit 7
1
Bit 5
P4
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 9
P6
Bit 8
P7
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
P31
P9
P12
P10
P13
P14
P11
P15
Bit 1
Bit 0
Sample Bit-to-Pixel Mapping
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
P1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
1
P1
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
2
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
3
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
P5
P2
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
P6
Bit 3
P0
P3
P4
3
Bit 0
P3
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
Byte
Address
Bit 2
P2
2
Bit 1
8 bpp Mode
P0
1
Bit 2
P2
2
P8
Sample Bit-to-Pixel Mapping
Bit 7
Bit 3
P5
4 bpp Mode
Byte
Address
Bit 4
P1
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
P23
P30
Bit 6
P0
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24
P24
Sample Bit-to-Pixel Mapping
0
Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
P16
3
Byte
Address
Bit 7
P8
2
2 bpp Mode
Sample Bit-to-Pixel Mapping
P7
P3
12 bpp Mode
Byte
Address
0
1
2
3
Sample Bit-to-Pixel Mapping
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Green0 [3]
Green0 [2]
Green0 [1]
Green0 [0]
Blue0 [3]
Blue0 [2]
Blue0 [1]
Blue0 [0]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Red0 [3]
Red0 [2]
Red0 [1]
Red0 [0]
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Green1 [3]
Green1 [2]
Green1 [1]
Green1[0]
Blue1 [3]
Blue1 [2]
Blue1 [1]
Blue1 [0]
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Red1 [3]
Red1 [2]
Red1 [1]
Red1 [0]
16 bpp Mode
Byte
Address
0
1
2
3
Sample Bit-to-Pixel Mapping
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Green0 [2]
Green0 [1]
Green0 [0]
Blue0 [4]
Blue0 [3]
Blue0 [2]
Blue0 [1]
Blue0 [0]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Red0 [4]
Red0 [3]
Red0 [2]
Red0 [1]
Red0 [0]
Green0 [5]
Green0 [4]
Green0 [3]
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Green1 [2]
Green1 [1]
Green1 [0]
Blue1 [4]
Blue1 [3]
Blue1 [2]
Blue1 [1]
Blue1 [0]
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
Red1 [4]
Red1 [3]
Red1 [2]
Red1 [1]
Red1 [0]
Green1 [5]
Green1 [4]
Green1 [3]
Figure 21-30. Display Data Mapping 1 bpp Through 16 bpp Modes
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Liquid Crystal Display Controller (LCDC)
18 bpp Mode
Byte
Address
0
1
2
3
Sample Bit-to-Pixel Mapping
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Blue [5]
Blue [4]
Blue [3]
Blue [2]
Blue [1]
Blue [0]
Bit 12
Bit 11
Bit 15
Bit 14
Bit 13
Green [5]
Green [4]
Green [3]
Green [2] Green [1]
Bit 10
Bit 1
Bit 0
Bit 9
Bit 8
Bit 17
Bit 16
Bit 25
Bit 24
Bit 1
Bit 0
Bit 9
Bit 8
Bit 17
Bit 16
Bit 25
Bit 24
Green [0]
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Red [5]
Red [4]
Red [3]
Red [2]
Red [1]
Red [0]
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Microsoft PAL_BGR 18bpp Mode
Byte
Address
0
1
2
3
Sample Bit-to-Pixel Mapping
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Red [5]
Red [4]
Red [3]
Red [2]
Red [1]
Red [0]
Bit 12
Bit 11
Bit 15
Bit 14
Bit 13
Green [5]
Green [4]
Green [3]
Green [2] Green [1]
Bit 10
Green [0]
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Blue [5]
Blue [4]
Blue [3]
Blue [2]
Blue [1]
Blue [0]
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Figure 21-31. Display Data Mapping for 18 bpp Modes
21.4.5
Black-and-White Operation
The 1 bpp mode is also known as black-and-white mode because each pixel is always fully on or fully off.
21.4.6
Gray-Scale Operation
The LCDC generates a maximum of 16 gray levels. These gray levels are defined by 2 or 4 bits of display
data for each pixel. Using 2 bpp, the LCDC displays 4 shades of gray, and using 4 bpp, the LCDC displays
all 16 shades. The shades of gray are obtained by controlling the number of frames in which the pixel is
on over a period of 16 frames. This method is known as frame rate control (FRC). For more information
on FRC, see Section 21.4.8, “Frame Rate Modulation Control (FRC)
The use of the mapping RAM is shown in Figure 21-32. When using 2 bpp, the 2-bit code is mapped to
one of four gray levels, and when using 4 bpp, the 4-bit code is mapped to one of 16 gray levels. Because
crystal formulations and driving voltages vary, the visual gray effect may or may not be linearly related to
the frame rate. A logarithmic scale such as 0, 1/4, 1/2 and 1 might be more pleasing than a linearly spaced
scale such as 0, 5/16, 11/16 and 1 for certain graphics.
Figure 21-32 illustrates gray-scale pixel generation. The flexible mapping scheme allows the user to
optimize the visual effect for a specific panel or application.
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Liquid Crystal Display Controller (LCDC)
7 6 5 4 3 2 1 0
1 0
2 bpp Data
1 1 0 0
4 bpp Data
- - - - - - - - 1 1 1 0
FRC
1
To Panel
Figure 21-32. Gray-Scale Pixel Generation
21.4.7
Color Generation
The value corresponding to each color pixel on the screen is represented by a 4-, 8-, 12-, 16- or 18-bit code
in the display memory.
For 4- and 8-bit modes the LCDC’s color mapping RAM is used to map the data to a 12-bit and 18-bit
RGB code for passive and active matrix color displays respectively. For 4-bit and 8-bit passive matrix
color displays, the 12-bit RGB code from the mapping RAM is output to the FRC blocks that
independently process the code corresponding to the red, green, and blue components of each pixel to
generate the required shade and intensity.
For 4-bit and 8-bit active matrix display, the 18-bit output from the mapping RAM is output to the panel.
For 12-bit mode for passive matrix color display, the mapping RAM is bypassed and output directly to the
FRC block.
For 12-, 16- and 18-bit active matrix color display, pixel data is simply moved from display memory to the
LCDC output bus.
Figure 21-33 and Figure 21-34 illustrate passive matrix and active matrix color pixel generation.
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Liquid Crystal Display Controller (LCDC)
7 6 5 4 3 2 1 0
1 0 1 1
4 bpp Data
1 1 0 0 1 1 0 1
8 bpp Data
0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1
12 bpp Data
R
G
B
Color
RAM
Inside
LCDC
256 rows
1 0 1 0 1 1 0 0 1 1 1 0
FRC
FRC
FRC
1
0
1
To panel
Figure 21-33. Passive Matrix Color Pixel Generation
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Freescale Semiconductor
21-35
Liquid Crystal Display Controller (LCDC)
.
7 6 5 4 3 2 1 0
1 0 1 1
4 bpp Data
1 1 0 0 1 1 0 1
8 bpp Data
0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1
R
G
12/16/18 bpp Data
B
Color
RAM
Inside
LCDC
256 Rows
0 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1
To Panel
Figure 21-34. Active Matrix Color Pixel Generation
21.4.8
Frame Rate Modulation Control (FRC)
Circuitry inside the LCDC generates intermediate gray-scale colors on the panel by adjusting the density
of zeroes and ones that appear over the frames. The LCDC can generate 16 simultaneous gray-scale levels.
Table 21-33. Gray Palette Density
Gray Code
(Hexadecimal)
Density
Density
(Decimal)
0
0
0
1
1/8
0.125
2
1/5
0.2
3
1/4
0.25
4
1/3
0.333
5
2/5
0.4
6
4/9
0.444
7
1/2
0.5
8
5/9
0.555
9
3/5
0.6
A
2/3
0.666
B
3/4
0.75
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Liquid Crystal Display Controller (LCDC)
Table 21-33. Gray Palette Density (continued)
Gray Code
(Hexadecimal)
Density
Density
(Decimal)
C
4/5
0.8
D
7/8
0.875
E
14/15
0.933
F
1
1
Note: Overbars indicate repeating decimal numbers.
21.4.9
Panel Interface Signals and Timing
The LCDC continuously provides pixel data to the LCD panel via the LCD panel interface. Panel interface
signals are illustrated in Figure 21-35.
LCD Controller
LCD_D[17:0]
LCD_FLM/LCD_VSYNC
LCD_LP/LCD_HSYNC
LCD_LSCLK
LCD_ACD/LCD_OE
LCD_PS
LCD_CONTRAST
LCD_CLS
LCD_REV
LCD_SPL_SPR
Figure 21-35. LCDC Interface Signals
The format, timing, and polarity of the panel interface signals are programmable. There are two basic
modes, passive and active, selected by the TFT register bit. The user must also select grayscale mode or
color mode.
The LCD_SPL_SPR, LCD_PS, LCD_CLS, and LCD_REV interface signals are dedicated for Sharp
HR-TFT 240 × 320 panels only.
21.4.9.1
Pin Configuration for LCDC
Figure 21-35 shows the signals used for the LCDC. These pins are multiplexed with other functions on the
device, and must be configured for LCDC operation before they can be used.
21.4.9.2
Passive Matrix Panel Interface Signals
Figure 21-36 shows the LCD interface timing for monochrome panels and Figure 21-37 shows the LCD
interface timing for passive matrix color panels. Signal polarities are shown positive, however it can be
reversed by clearing the bits in the panel configuration register (LCD_PCR). The data bus timing for
passive panels is determined by the shift clock (LCD_LSCLK), line pulse (LCD_LP), first line marker
(LCD_FLM), alternate crystal direction (LCD_ACD), and line data (LCD_D) signals.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-37
Liquid Crystal Display Controller (LCDC)
Operation of the panel interface is accomplished in the following steps:
1. LCD_LSCLK clocks the pixel data into the display driver’s internal shift register.
2. LCD_LP signifies the end of the current line of serial data and latches the shifted pixel data into a
wide latch.
3. LCD_FLM marks the first line of the displayed page. The LCD_D (and the associated LCD_LP),
enclosed by the LCD_FLM signal, marks the first line of the current frame.
4. LCD_ACD toggles after a pre-programmed number of LCD_FLM pulses. This signal refreshes the
LCD panel.
NOTE
The LCD_D bus width is programmable to 1, 2, 4, or 8 bits in monochrome
mode (the COLOR bit in the panel configuration register is set to 0). Data is
justified to the least significant bits of the LCD_D[17:0] bus. Passive color
displays use a fixed 2-2/3 pixels of data per 8-bit vector as shown in
Figure 21-37.
LCD_FLM
LCD_LP
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
LINE 1
LCD_LP
1
2
3
59
60
m/4-1
m/4
LCD_D0
[0,0]
[0,4]
[0,8]
[0,232] [0,236]
[0,m-8] [0,m-4]
LCD_D1
[0,1]
[0,5]
[0,9]
[0,233] [0,237]
[0,m-7] [0,m-3]
LCD_D2
[0,2]
[0,6]
[0,10]
[0,234] [0,238]
[0,m-6] [0,m-2]
LCD_D3
[0,3]
[0,7]
[0,11]
[0,235] [0,239]
[0,m-5] [0,m-1]
LCD_LSCLK
Figure 21-36. LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels
MCF52277 Reference Manual, Rev 2
21-38
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
LCD_FLM
LCD_LP
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
LINE 1
LCD_LP
1
2
3
89
90
3*m/8-1 3*m/8
LCD_D7
R[0,0]
B[0,2]
G[0,5]
B[0,234] G[0,237]
B[0,m-6] G[0,m-3]
LCD_D6
G[0,0]
R[0,3]
B[0,5]
R[0,235] B[0,237]
R[0,m-5] B[0,m-3]
LCD_D5
B[0,0]
G[0,3]
R[0,6]
G[0,235] R[0,238]
G[0,m-5] R[0,m-2]
LCD_D4
R[0,1]
B[0,3]
G[0,6]
B[0,235] G[0,238]
B[0,m-5] G[0,m-2]
LCD_D3
G[0,1]
R[0,4]
B[0,6]
R[0,236] B[0,238]
R[0,m-4] B[0,m-2]
LCD_D2
B[0,1]
G[0,4]
R[0,7]
G[0,236] R[0,239]
G[0,m-4] R[0,m-1]
LCD_D1
R[0,2]
B[0,4]
G[0,7]
B[0,236] G[0,239]
B[0,m-4] G[0,m-1]
LCD_D0
G[0,2]
R[0,5]
B[0,7]
R[0,237] B[0,239]
R[0,m-3] B[0,m-1]
LCD_LSCLK
Figure 21-37. LCDC Interface Timing for 8-bit Data Passive Matrix Color Panels
21.4.9.3
Passive Panel Interface Timing
Figure 21-38 shows the horizontal timing (timing of one line), including the line pulse (LCD_LP) and the
data. The width of LCD_LP and delays before and after LCD_LP are programmable.
The parameters used for panel interface timing are:
• XMAX (X size) defines the number of pixels per line. XMAX is the total number of pixels per line.
• H_WAIT_1 defines the delay from the end of data output to the beginning of LCD_LP.
• H_WIDTH (horizontal sync pulse width) defines the width of the LCD_FLM pulse, and
H_WIDTH must be at least 1.
• H_WAIT_2 defines the delay from the end of LCD_LP to the beginning of data output.
NOTE
All parameters are defined in unit of pixel clock period
unless stated otherwise.
+1
⎛ LCD_PCR[PCD]
---------------------------------------------------⎞
⎝
⎠
f sys/2
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-39
Liquid Crystal Display Controller (LCDC)
Hwait2+2
Hwait2+2
LCD_FLM
(last line)
Hwidth+1
T
Hwait1+1
XMAX
(first line)
Hwidth+1
LCD_LP
LCD_LSCLK
Ts
LCD_D[17:0]
When it is in CSTN mode or monochrome mode with bus width = 1, T = 1 LCD_LSCLK period.
When it is in monochrome mode with bus width = 2, 4 and 8, T = 1, 2 and 4 LCD_LSCLK period respectively.
Figure 21-38. Horizontal Sync Pulse Timing in Passive Mode
YMAX
(lines)
PASS_FRAME_WAIT
LCD_FLM
LCD_LP
LCD_LSCLK
End of last line
Start of frame
Figure 21-39. Vertical Sync Pulse Timing in Passive Mode
21.4.10 8 bpp Mode Color STN Panel
21.4.10.1 Active Matrix Panel Interface Signals
Figure 21-40 shows the LCD interface timing for an active matrix color TFT panel. In this figure, signals
are shown with negative polarity (FLMPOL=1, LPPOL=1, CLKPOL=0, OEPOL=1). In TFT mode, the
LCD_LSCLK is automatically inverted. The panel interface timing for active matrix panels is sometimes
referred to as a digital CRT and is controlled by the shift clock (LCD_LSCLK), horizontal sync pulse
(LCD_HSYNC, the LCD_LP pin in passive mode), vertical sync pulse (LCD_VSYNC, the LCD_FLM
pin in passive mode), output enable (LCD_OE, the LCD_ACD pin in passive mode), and line data
(LCD_D) signals. The sequence of events for active matrix interface timing is:
1. LCD_LSCLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, LCD_LSCLK runs continuously.
2. LCD_HSYNC causes the panel to start a new line.
MCF52277 Reference Manual, Rev 2
21-40
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
3. LCD_VSYNC causes the panel to start a new frame. It always encompasses at least one
LCD_HSYNC pulse.
4. LCD_OE functions as an output enable signal to the CRT. This output enable signal is similar to
the blanking output in a CRT and enables the data to be shifted onto the display. When disabled,
the data is invalid and the trace is off.
In 4- and 8-bit mode, the LCD_D[17:12] bits define red, the LCD_D[11:6] bits define green, and the
LCD_D[5:0] bits define blue. In 12-bit mode, the LCD_D[17:14] bits define red, the LCD_D[11:8] bits
define green, and the LCD_D[5:2] bits define blue. In 16-bit mode, the LCD_D[17:13] bits define red, the
LCD_D[11:6] bits define green, and the LCD_D[5:1] bits define blue.
The actual TFT color channel assignments are shown in Table 21-34. The unused bits are fixed at 0.
Table 21-34. TFT Color Channel Assignments
LCD_D[17:0]
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
4 bpp
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
8 bpp
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
12 bpp
R3
R2
R1
R0
–
–
G3
G2
G1
G0
–
–
B3
B2
B1
B0
–
–
16 bpp
R4
R3
R2
R1
R0
–
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
–
18 bpp
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-41
Liquid Crystal Display Controller (LCDC)
LCD_VSYNC
LCD_HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n
LINE 1
LCD_HSYNC
LCD_OE
1
2
3
239
240
m-1
m
LCD_D15
R4[0,0]
R4[0,1]
R4[0,2]
R4[0,238] R4[0,239]
R4[0,m-2] R4[0,m-1]
LCD_D14
R3[0,0]
R3[0,1]
R3[0,2]
R3[0,238] R3[0,239]
R3[0,m-2] R3[0,m-1]
LCD_D13
R2[0,0]
R2[0,1]
R2[0,2]
R2[0,238] R2[0,239]
R2[0,m-2] R2[0,m-1]
LCD_D12
R1[0,0]
R1[0,1]
R1[0,2]
R1[0,238] R1[0,239]
R1[0,m-2] R1[0,m-1]
LCD_D11
R0[0,0]
R0[0,1]
R0[0,2]
R0[0,238] R0[0,239]
R0[0,m-2] R0[0,m-1]
LCD_D10
G5[0,0]
G5[0,1]
G5[0,2]
G5[0,238] G5[0,239]
G5[0,m-2] G5[0,m-1]
LCD_D9
G4[0,0]
G4[0,1]
G4[0,2]
G4[0,238] G4[0,239]
G4[0,m-2] G4[0,m-1]
LCD_D8
G3[0,0]
G3[0,1]
G3[0,2]
G3[0,238] G3[0,239]
G3[0,m-2] G3[0,m-1]
LCD_D7
G2[0,0]
G2[0,1]
G2[0,2]
G2[0,238] G2[0,239]
G2[0,m-2] G2[0,m-1]
LCD_D6
G1[0,0]
G1[0,1]
G1[0,2]
G1[0,238] G1[0,239]
G1[0,m-2] G1[0,m-1]
LCD_D5
G0[0,0]
G0[0,1]
G0[0,2]
G0[0,238] G0[0,239]
G0[0,m-2] G0[0,m-1]
LCD_D4
B4[0,0]
B4[0,1]
B4[0,2]
B4[0,238] B4[0,239]
B4[0,m-2] B4[0,m-1]
LCD_D3
B3[0,0]
B3[0,1]
B3[0,2]
B3[0,238] B3[0,239]
B3[0,m-2] B3[0,m-1]
LCD_D2
B2[0,0]
B2[0,1]
B2[0,2]
B2[0,238] B2[0,239]
B2[0,m-2] B2[0,m-1]
LCD_D1
B1[0,0]
B1[0,1]
B1[0,2]
B1[0,238] B1[0,239]
B1[0,m-2] B1[0,m-1]
LCD_D0
B0[0,0]
B0[0,1]
B0[0,2]
B0[0,238] B0[0,239]
B0[0,m-2] B0[0,m-1]
LCD_LSCLK
Figure 21-40. LCDC Interface Timing for Active Matrix Color Panels
21.4.10.2 Active Panel Interface Timing
Figure 21-41 shows the horizontal timing (timing of one line), including the horizontal sync pulse and the
data. The width of LCD_HSYNC and delays before and after LCD_HSYNC are programmable.
The timing signal parameters are defined as follows:
• H_WIDTH defines the width of the LCD_HSYNC pulse and must be at least 1.
• H_WAIT_2 defines the delay from the end of LCD_HSYNC to the beginning of the LCD_OE
pulse.
• H_WAIT_1 defines the delay from end of LCD_OE to the beginning of the LCD_HSYNC pulse.
• XMAX defines the (total) number of pixels per line.
MCF52277 Reference Manual, Rev 2
21-42
Freescale Semiconductor
Liquid Crystal Display Controller (LCDC)
NOTE
All parameters are defined in pixel periods
LCD_LSCLK periods.
H_WIDTH+1
+1
⎛ LCD_PCR[PCD]
---------------------------------------------------⎞
⎝
⎠
f sys/2
H_WAIT_2+3
, not
XMAX
H_WAIT_1+1
LCD_LSCLK
LCD_HSYNC
LCD_OE
DATA
LCD_VSYNC
Figure 21-41. Horizontal Sync Pulse Timing in TFT Mode
Figure 21-42 shows the vertical timing (timing of one frame). The delay from the end of one frame until
the beginning of the next is programmable. The memory timing signal parameters are:
• V_WAIT_1 is a delay measured in lines. For V_WAIT_1= 1 there is a delay of one LCD_HSYNC
(time = one line period) before LCD_VSYNC. The LCD_HSYNC pulse is output during the
V_WAIT_1 delay.
• For V_WIDTH (vertical sync pulse width) = 0, LCD_VSYNC encloses one LCD_HSYNC pulse.
For V_WIDTH = 2, LCD_VSYNC encloses two LCD_HSYNC pulses.
• V_WAIT_2 is a delay measured in lines. For V_WAIT_2 = 1, there is a delay of one LCD_HSYNC
(time = one line period) after LCD_VSYNC. The LCD_HSYNC pulse is output during the
V_WAIT_2 delay.
End of frame
V_WIDTH
(lines)
Beginning of frame
YMAX
LCD_VSYNC
LCD_HSYNC
LCD_OE
V_WAIT_1
V_WAIT_2
Figure 21-42. Vertical Sync Pulse Timing TFT Mode
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
21-43
Liquid Crystal Display Controller (LCDC)
MCF52277 Reference Manual, Rev 2
21-44
Freescale Semiconductor
Chapter 22
Touchscreen Controller
The analog signal processor (ASP) supports resistive 4-, 5-, 7-, and 8-wire interface touch
panels.Figure 22-1 shows the block diagram of the touchscreen module.
Internal Bus
Bus Clock
(fsys/2)
Clock
Generator
ADC_CLK
Pen
Detect
Bus Interface
ADC +
Bias Network +
Pen State
ASP
Control
FIFO
ADC
Control
Figure 22-1. ASP System Block Diagram
22.1
Overview
The ASP module is composed of an ADC, clock generator, ASP and ADC control blocks, pen-detect logic,
FIFO memory, and bus interface.
• The ADC block includes the bias network and touchscreen pen-state detection.
• ADC control works together with the ADC to implement the ADC function.
• Clock generator generates the programmable ADC_CLK clock from the free-running peripheral
bus clock.
• ASP control is the core touchscreen control block. It is responsible for running the touchscreen in
the defined sequence according to the operating modes and timing settings.
• The pen detect block provides pen-down and pen-up interrupts by sampling the pen state signal
from the ADC block and removing the bouncing effect.
• The FIFO temporarily stores the measured data and allows the MCU to burst the measured data by
using the various FIFO usage flags.
• FIFO temporarily stores the measured data and provides a capability for the CPU to process the
measured data in a burst way with aid of the variant FIFO usage flags.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-1
Touchscreen Controller
22.1.1
Features
The ASP module includes the following features:
• Supports 4-, 5-, 7-, and 8-wire touchscreen configurations
• Embedded touchscreen control circuitry
• Touch/pressure measurements
• 12-bit 125 kS/s ADC for touchscreen measurements
• Ratiometric measurements drivers (support differential mode)
• Up to eight auxiliary input channels are available for general purpose ADC measurements (the
number of the auxiliary input channels are defined by the touch-screen topology)
• Power-down and quick wake-up capability
• Pen-up detection by polling the pen-down state
• Pen-down detection circuitry to generate pen-down signal
• Pen detection de-bouncing circuit
• Touchscreen mode supports auto-sampling, single-round sampling, and manual sampling modes
• Touchscreen calibration and auto-zero support
• Provides data-ready, FIFO full, and configurable water mark interrupts
• Hardware pen detection interrupt
MCF52277 Reference Manual, Rev 2
22-2
Freescale Semiconductor
Touchscreen Controller
22.2
External Signal Description
ASP external signal names are listed in the following table.
Table 22-1. ASP Signal Descriptions
Signal Name
I/O
Description
ADC_REF
I
External ADC reference voltage
ADC_IN[7:0]
I
Touchscreen and/or ADC inputs. ADC_IN[7:0] serves as a touchscreen interface or generic ADC
interface, determined by ASP_CR[TSE]. Also, the touchscreen signal functionality for these pins
depends on the setting of ASP_CR[TSTYPE]. The available configurations are shown in the table
below.
Touchscreen
8-wire
ADC
(TSTYPE = 11)
7-wire
(TSTYPE = 10)
5-wire
(TSTYPE = 01)
4-wire
ADC_IN[7:0]
(TSTYPE = 00)
(TSE = 1)
(TSE = 0)
ADC_IN7
—1
—1
—1
X−force
ADC_IN7
ADC_IN6
—1
—1
LRsense
X+force
ADC_IN6
ADC_IN5
—1
—1
ULsense
Y−sense
ADC_IN5
—1
Wiper/
Sense
Wiper
Y+sense
ADC_IN4
ADC_IN3
LR/Y–
LR
Y−
Y−force
ADC_IN3
ADC_IN2
LL/Y+
LL
Y+
Y+force
ADC_IN2
ADC_IN1
UR/X–
UR
X−
X−sense
ADC_IN1
ADC_IN0
UL/X+
UL
X+
X+sense
ADC_IN0
ADC_IN4
1
May be used as a general-purpose ADC signal by setting the
appropriate ASP_CR[APTN] bit.
Note: LR: lower-left, LL: lower-left, UR: upper-right, UL: upper-left
22.3
Memory Map/Register Definition
The ASP module registers are summarized in Table 22-2.
Table 22-2. ASP Memory Map
Address
Register
Width
Access
(bits)
Reset Value
Section/Page
0xFC0A_8000 ASP Control Register (ASP_CR)
32
R/W
0x0008_0000
22.3.1/22-4
0xFC0A_8004 ASP Sampling Setting Register (ASP_SET)
32
R/W
0x7787_0000
22.3.2/22-7
0xFC0A_8008 A/D Sampling Timing Register (ASP_TIM)
32
R/W
0x000F_0FFF
22.3.3/22-8
0xFC0A_800C ASP Interrupt/DMA Control Register (ASP_ICR)
32
R/W
0x0020_0000
22.3.4/22-9
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-3
Touchscreen Controller
Table 22-2. ASP Memory Map (continued)
Address
Width
Access
(bits)
Register
Reset Value
Section/Page
0xFC0A_8010 ASP Interrupt Status Register (ASP_ISR)
32
R/W
0x0000_0000
22.3.5/22-10
0xFC0A_8014 ASP Sample FIFO (ASP_SFIFO)
32
R
See Section
22.3.6/22-11
0xFC0A_8018 ASP FIFO Pointer (ASP_FIFOP)
32
R/W
0x0000_0000
22.3.7/22-12
0xFC0A_801C ASP Clock Divider Register (ASP_CLKDIV)
32
R/W
0x0000_0029
22.3.8/22-13
22.3.1
ASP Control Register (ASP_CR)
ASP_CR determines the configuration of touchscreen controller.
Address: 0xFC0A_8000 (ASP_CR)
31
R
W
R
W
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
ASPE
Reset
AZE CALA
Reset
Access: User read/write
0
0
AUTO
0
23
22
21
0
0
0
0
0
0
1
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
DOZE
20
PENE MDIS
MODE
0
0
19
18
TSE
17
16
TSTYPE
APTN
0
0
0
0
Figure 22-2. ASP Control Register (ASP_CR)
Table 22-3. ASP_CR Field Descriptions
Field
31
ASPE
Description
ASP conversion enable. Controls the ASP state machine to start/end the predefined operation sequence
according to other fields in ASP_CR. ASPE’s effect on ASP operation depends on the timing before an
ADC_CLK rising edge and the current state of the ASP state machine. The ASP state machine operates on
ADC_CLK and must run in a proper sequence. The state machine ignores any ASPE changes during some
specific operations. To avoid this delay uncertainty, change the ASPE according to the typical operation
sequence, where an interrupt driven mechanism is used.
Besides explicitly clearing this bit, ASPE automatically clears if ASP_CR[PENE] is set and a pen-up interrupt
occurs in touchscreen non-manual modes. If the touchscreen is in auto mode and this bit is cleared, the state
machine goes into the next conversion state, but the start conversion control signal is blocked because the ASPE
is cleared. Therefore, the ADC conversion does not occur and no extra data is written into the FIFO.
If you clear this bit and set it again within a single ADC_CLK cycle, this short pulse is expanded to a longer pulse
so it is captured by the ASP.
0 Stop the sequence operation.
1 Initiate the sequence operation.
30–24
Reserved, must be cleared.
MCF52277 Reference Manual, Rev 2
22-4
Freescale Semiconductor
Touchscreen Controller
Table 22-3. ASP_CR Field Descriptions (continued)
Field
Description
23
DOZE
Module Doze Enable. Controls operation of the ASP module when the processor is placed in doze mode. When
this bit is set, the ASP enters a low-power state by powering down the ADC and the bias network by disabling
the module clock. Any conversion in progress is completed before entering the low-power state. When exiting
doze mode, the ASP wakes up by re-enabling the module clock and powering up the hard macro. Some
stabilization delay is likely to be required before the ADC is ready for use. Allow this delay to elapse before using
the results from the ADC.
0 ASP ignores doze mode and continues operation
1 ASP enters low-power state in doze mode
22–21
Reserved, must be cleared.
20
PENE
Pen Detection Enable. Enables insertion of the pen detection phase between two rounds of measurement
sequences when TSE and AUTO are set. It also automatically clears the ASPE bit.
0 Pen detection phase disabled
1 Pen detection phase enabled
19
MDIS
Module Disable. Forces the ADC into a power-down mode by disabling the ADC clock.
0 Enable touchscreen module
1 Disable touchscreen module
Note: At reset, this bit is set; clear this bit to enable operation of the ASP.
18
TSE
Touchscreen enable. Controls the ASP application type.
0 General purpose A/D application
1 Touchscreen application
17–16
TSTYPE
15
AZE
Touchscreen Type. Selects the touchscreen configuration.
00 4-wire touchscreen
01 5-wire touchscreen
10 7-wire touchscreen
11 8-wire touchscreen
Auto-Zero Enable. Auto-zero measurement inserts samples of what should be the X and Y ground points prior
to taking the actual X and Y coordinate sample.
0 No auto-zero measurement
1 Auto-zero measurement taken before every pin input measurement
Note: MIDLECNT has no affect on inserting idle phases between the auto-zero measurement and the
corresponding coordinate measurement.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-5
Touchscreen Controller
Table 22-3. ASP_CR Field Descriptions (continued)
Field
Description
14
CALA
Calibration assist. Controls the calibration assistance feature, a defined sequence of conversions that generates
data frames to calibrate the ADC. The samples converted depend on the type of touchscreen selected by the
TSTYPE field as follows:
TSE
TSTYPE Touchscreen
Number of
Data Values
Conversion Sequence
0
—
None
No calibration assist available
—
1
00
4-wire
REFP, REFN
4
1
01
5-wire
REFP, REFN
6
1
10
7-wire
REFP, REFN, ULsense, LRsense
6
1
11
8-wire
REFP, REFN, X+sense, X−sense, Y+sense, Y−sense
8
When CALA and ASPE are set, calibration assist conversion sequences are run according to the type of
touchscreen selected by TSTYPE. If AUTO is set, calibration assistance conversion sequences continue
running until ASPE is cleared. If AUTO is cleared, only one round of calibration sequence is run. CALA overtakes
the other touchscreen related settings of the ASP (MODE, AZE, PENE, etc.). However, the measurement idle
phase and round idle phase are valid during the calibration.
0 Calibration assistance feature disabled
1 Calibration assistance conversion sequences enabled
13–11
Reserved, must be cleared.
10
AUTO
Auto-round control. Determines whether the ASP performs automatic, continuous sampling, or a single scan of
ADC inputs.
0 Single-scan sampling
1 Auto-continuous sampling
9–8
MODE
Auto-sampling mode. Along with the AUTO bit, determines ASP operation sequence so that the ADC samples
only the touchscreen inputs, the general-purpose inputs, or both sets of inputs in a single, single round, or
auto-continuous way.
MODE
00
AUTO = 0
Software initiated conversion with manual control
of bias switches and input muxes
01
Automatic continuous sampling
of touchscreen inputs
Single scan sampling
of touchscreen inputs
10
Automatic continuous sampling
of general-purpose inputs
Single scan sampling
of general-purpose inputs
11
7–0
APTN
AUTO = 1
Automatic sampling of touchscreen and Single scan sampling of touchscreen and
general-purpose inputs
general-purpose inputs
ASP sampling pattern. If the corresponding ADC channel is not used by the touchscreen interface, these bits
set the ADC channel to be used as general purpose ADC inputs. If TSE is cleared, all ADC input channels are
controlled by APTN. If TSE is set, only channels not used for touchscreen operation are affected by APTN. Any
APTN bits set for channels that have touchscreen functions are ignored.
0 Channel is not selected for general purpose ADC channels conversion
1 Channel is selected for general purpose ADC channels conversion
MCF52277 Reference Manual, Rev 2
22-6
Freescale Semiconductor
Touchscreen Controller
22.3.2
ASP Sample Setting Register (ASP_SET)
This register configures the touchscreen interface bias switches and reference/input select muxes when the
ASP is configured for full manual operation (ASP_CR[AUTO,MODE] = 0x0).
Address: 0xFC0A_8004 (ASP_SET)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0
W
REFP
0
REFN
TRIMC
0
INP
8
0 0 0
7
6
5
4
3
2
1
0
SW
Reset 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-3. ASP Sample Setting Register (ASP_SET)
Table 22-4. ASP_SET Field Descriptions
Field
31
30–28
REFP
27
Description
Reserved, must be cleared.
Positive reference. Selects the positive reference input to the ADC when full manual operation is selected
(ASP_CR[MODE] = 00).
000 ADC_IN0
001 ADC_IN2
010 ADC_IN4
011 ADC_IN5
100 ADC_REF
101 VDD_ADC
110 VDD_ADC
111 VDD_ADC
Reserved, must be cleared.
26–24
REFN
Negative reference. Selects the negative reference input to the ADC when full manual operation is selected
(ASP_CR[MODE] = 00).
000 ADC_IN1
001 ADC_IN3
010 ADC_IN5
011 ADC_IN6
100 Reserved
101 VSS_ADC
110 VSS_ADC
111 VSS_ADC
23–16
TRIMC
Trim value for ADC. After reset, the default value for TRIMMING is 0x87. It is strongly recommended to use the
default reset value.
15
Reserved, must be cleared.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-7
Touchscreen Controller
Table 22-4. ASP_SET Field Descriptions (continued)
Field
Description
14–12
INP
Positive input. Selects the positive input to the ADC as one of the ADC_IN[7:0] signals when the ASP is
configured for full manual operation (ASP_CR[AUTO,MODE] = 0x0).
000 ADC_IN0
001 ADC_IN1
010 ADC_IN2
011 ADC_IN3
100 ADC_IN4
101 ADC_IN5
110 ADC_IN6
111 ADC_IN7
11–9
Reserved, must be cleared.
8–0
SW
Bias switch control. Enables the touchscreen bias transistor switches when the ASP is configured for full manual
operation (ASP_CR[MODE] = 00).
0 Bias transistor off
1 Bias transistor on
22.3.3
ASP Sample Timing Register (ASP_TIM)
The sample timing register provides programmable delays for different portions of the conversion
sequence.
Address: 0xFC0A_8008 (ASP_TIM)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
RIDLECNT
8
MIDLECNT
7
6
5
BIACNT
4
3
2
1
0
SPCNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Figure 22-4. ASP Sample Timing Register (ASP_TIM)
Table 22-5. ASP_TIM Field Descriptions
Field
Description
31–16
Idle time setting between two rounds of measurements when ASP_CR[AUTO] is set. When this field is cleared,
RIDLECNT there is no idle phase between two rounds of measurements.
15–8
Idle time setting between two successive measurements. When this field is cleared, there is no idle phase
MIDLECNT between two successive measurements. There is no idle phase between AZX/AZY and X/Y measurements.
MCF52277 Reference Manual, Rev 2
22-8
Freescale Semiconductor
Touchscreen Controller
Table 22-5. ASP_TIM Field Descriptions (continued)
Field
Description
7–4
BIACNT
Bias phase count. Controls the timing from changing the bias switch bus to the beginning of the conversion. The
formula to calculate the time is:
Bias setting time = BIACNT[0] + 4 × ( BIACNT[3:1] + 1 )
Eqn. 22-1
The number is given in ADC_CLK cycles. BIACNT is used as the effective timing setting of the bias phase. The
input and reference selections share the same timing configuration.
3–0
SPCNT
Sample pulse count. Controls the width of the sample pulse, which can be calculated as:
Sample pulse count = SPCNT[0] + 4 × ( SPCNT[3:1] + 1 )
Eqn. 22-2
The number is given in ADC_CLK cycles.
22.3.4
ASP Interrupt/DMA Control Register (ASP_ICR)
The ASP_ICR enables and controls each interrupt and DMA request function.
Address: 0xFC0A_800C (ASP_ICR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0
W
FIFO_WM
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 POV 0 PU PD PFL PFL PFF PDR
IE
IE IE DE IE IE
IE
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
Figure 22-5. ASP Interrupt Control Register (ASP_ICR)
Table 22-6. ASP_ICR Field Descriptions
Field
31–22
21–16
FIFO_WM
15–8
7
POVIE
6
Description
Reserved, must be cleared.
FIFO watermark. Controls the FIFO watermark level. When the FIFO is changed (reading/writing data from/into
the FIFO), the FIFO level is compared with this value. If the current FIFO level is greater than or equal to
FIFO_WM, an interrupt request is generated if PFLIE is set and a DMA request is generated if PFLDE is set.
Reserved, must be cleared.
Pen FIFO overflow interrupt enable. Enables a request for interrupt service if an overflow of the pen FIFO occurs.
0 Disable the pen FIFO overflow interrupt
1 Enable the pen FIFO overflow interrupt
Reserved, must be cleared.
5
PUIE
Pen-up interrupt enable.
0 Disable
1 Enable
4
PDIE
Pen-down interrupt enable.
0 Disable
1 Enable
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-9
Touchscreen Controller
Table 22-6. ASP_ICR Field Descriptions (continued)
Field
Description
3
PFLDE
Pen FIFO level DMA request enable. Enables a DMA service request when the sample FIFO level matches the
value in FIFO_WM.
0 Disables the FIFO level DMA request
1 Enables the FIFO level DMA request
2
PFLIE
Pen FIFO level interrupt request enable. Enables an interrupt request when the sample FIFO level matches the
value in FIFO_WM.
0 Disables the FIFO interrupt request
1 Enables the FIFO interrupt request
1
PFFIE
Pen FIFO full interrupt request enable. Enables an interrupt request when the sample FIFO is full.
0 Disables the FIFO full interrupt request
1 Enables the FIFO full interrupt request
0
PDRIE
Pen data ready interrupt enable. Enables and disables the pen data ready interrupt request.
1 Enable the pen sample data ready interrupt
0 Disable the pen sample data ready interrupt
22.3.5
ASP Status Register (ASP_SR)
The ASP_SR reflects pen and FIFO states and interrupt and DMA requests enabled by bits in ASP_ICR.
Each bit is cleared by writing a 1 to it or by reading or writing the associated data register, depending on
the nature of the interrupt.
Address: 0xFC0A_8010 (ASP_ISR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POVF 0 PUF PDF 0 PFLF PFFF PDRF
w1c
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
w1c w1c
0
0
0
0
0
0
0
Figure 22-6. ASP Interrupt Status Register (ASP_ISR)
Table 22-7. ASP_ISR Field Descriptions
Field
Description
31–8
Reserved, must be cleared.
7
POVF
Pen sample FIFO overflow flag. Indicates that a pen sample FIFO overflow has occurred. This flag is sticky, and
is only cleared by explicitly writing a 1 to it, clearing the FIFO by writing to ASP_FIFOP, or asynchronous reset
of the touchscreen module. Clearing this bit is processed asynchronously.
0 No pen FIFO overflow
1 The pen FIFO has overflowed
6
5
PUF
Reserved, must be cleared.
Pen up flag. Indicates a pen-down event has occurred. This flag is sticky and is cleared by writing a 1 to it.
Clearing this bit is processed asynchronously.
0 Pen up not detected
1 Pen up detected
MCF52277 Reference Manual, Rev 2
22-10
Freescale Semiconductor
Touchscreen Controller
Table 22-7. ASP_ISR Field Descriptions (continued)
Field
4
PDF
Description
Pen down flag. Indicates a pen-down event has occurred. This flag is sticky and is cleared by writing a 1 to it.
Clearing this bit is processed asynchronously.
0 Pen down not detected
1 Pen down detected
3
Reserved, must be cleared.
2
PFLF
Pen FIFO programmable level flag. Indicates the sample FIFO level has matched the value in
ASP_ICR[FIFO_WM]. Reading data out of the FIFO so the FIFO level is less than the value in FIFO_WM clears
PFLF automatically.
0 Pen FIFO has not reached the level programmed in FIFO_WM
1 Pen FIFO has reached the level programmed in FIFO_WM
1
PFFF
Pen FIFO full flag. Indicates the sample FIFO is full. Reading data out of the FIFO so the FIFO is not full clears
PFFF automatically.
0 Pen FIFO is not full
1 Pen FIFO full
Note: Although setting PFFF is immediate, there is a maximum of a two ADC_CLK cycle delay from FIFO
changes to this bit clearing. Therefore, it is suggested not to use this bit during normal operation, but as
a mechanism for error handling.
0
PDRF
Pen data ready flag. Indicates at least one valid sample is available in the pen sample FIFO. Emptying the FIFO
by reading all samples in it clears this bit automatically.
0 The pen sample FIFO is empty
1 One or more samples available in the pen sample FIFO
Note: Although clearing PDRF is immediate after reading out the last sample in the FIFO, there is a maximum
of a two internal bus clocks (fsys/2) delay from FIFO changes to this bit setting.
22.3.6
ASP Sample FIFO (ASP_SFIFO)
The ASP sample FIFO holds the sample data after A/D sampling. The data sequence is controlled by the
setting of ASP_CR. This register supports only the lower 16-bit and 32-bit read accesses. Write accesses,
upper 16-bit, and byte read accesses result in a transfer error.
NOTE
The ASP sample FIFO is read-only. After reset, the FIFO is empty and
reading the FIFO results in an undefined value.
Address: 0xFC0A_8014 (ASP_SFIFO)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8
CHANID
7
6
5
4
3
2
1
0
SAMPLE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U U U U U U U U U U U U U U U U
Figure 22-7. ASP Sample FIFO Register (ASP_SFIFO)
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-11
Touchscreen Controller
Table 22-8. ASP_SFIFO Field Descriptions
Field
31–16
15–12
CHANID
11–0
SAMPLE
22.3.7
Description
Reserved, must be cleared.
Channel ID for corresponding sample data.
CHANID
Channel
CHANID
Channel
0000
ADC_IN0
1000
X-coordinate
0001
ADC_IN1
1001
Y-coordinate
0010
ADC_IN2
1010
Auto-zero X
0011
ADC_IN3
1011
Auto-zero Y
0100
ADC_IN4
1100
Reserved
0101
ADC_IN5
1101
Reserved
0110
ADC_IN6
1110
Calibration assist 0
0111
ADC_IN7
1111
Calibration assist 1
Sample. Holds the sample data after pen A/D sampling. The data structure is controlled by ASP_CR[MODE].
The pen sample data is in a 12-bit unsigned word format.
ASP FIFO Pointer Register (ASP_FIFOP)
The FIFO pointer register indicates the current write and read pointer used for the pen sample. Any write
to ASP_FIFOP clears the FIFO, including the read/write pointer, and all the FIFO flags.
Address: 0xFC0A_8018 (ASP_FIFOP)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0
FFRP
8
7
6
0 0 0 0 0 0 0 0 0 0
5
4
3
2
1
0
FFWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-8. ASP FIFO Pointer Register (ASP_FIFOP)
Table 22-9. ASP_FIFOP Field Descriptions
Field
Description
31–22
Reserved, must be cleared.
21–16
FFRP
FIFO read pointer. Indicates the 6-bit FIFO read pointer.
15–6
Reserved, must be cleared.
5–0
FFWP
FIFO write pointer. Indicates the 6-bit FIFO write pointer. If a writing event is in process, the write pointer may
not be accurate.
MCF52277 Reference Manual, Rev 2
22-12
Freescale Semiconductor
Touchscreen Controller
22.3.8
ASP Clock Divider Register (ASP_CLKD)
ASP_CLKD controls the divider for the ADC clock (nominally 2 MHz). The delays controlled by the bit
fields in the ASP_TIM register are counted in ticks of the clock generated by this divisor (nominally 0.5 μs
when the ADC clock is 2 MHz).
Address: 0xFC0A_801C (ASP_CLKD)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
6
5
4
3
2
1
0
CLKD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
Figure 22-9. ASP Clock Divide Register (ASP_CLKD)
Table 22-10. ASP_CLKD Field Descriptions
Field
Description
31–7
Reserved, must be cleared.
6–0
CLKD
ASP clock divider. The ASP clock is derived using the following formulas.
If 15 ≤ CLKD ≤ 127:
f sys/2
f ASP = -----------------------CLKD + 1
Eqn. 22-3
f sys/2
f ASP = --------------CLKD
Eqn. 22-4
f sys/2
f ASP = -----------------------CLKD + 1
Eqn. 22-5
If 1 ≤ CLKD ≤ 14 and CLKD is even:
If 1 ≤ CLKD ≤ 14 and CLKD is odd:
The clock divider supports odd and even numbers of divisors for the clock. When an odd number is specified,
the high-time count is one count larger than the low count. This produces an asymmetric clock for all odd counts.
Take care when using an odd divider to ensure the duty cycle of the ASP clock does not exceed 60%. This is
generally a problem when the internal bus clock frequency (fsys/2) is less than ~8 MHz.
To avoid duty cycle issues, the divider automatically adjusts small odd divider settings. When the divide ratio of
(CLKD + 1) is odd and less than 16, the nearest smaller even setting is used. For example, when the CLKD
setting is six, before the automatic adjusting, the ADC_CLK frequency is 1/7 of the bus clock and the duty cycle
is 57.14%. After the automatic adjusting, the ADC_CLK frequency is 1/6 of the bus clock and the duty cycle is
50%.
Note: When ASP_CLKD is set to zero, the ADC_CLK signal is disabled.
22.4
Function Description
The analog signal processor may be configured as a touchscreen or generic ADC depending on
ASP_CR[TSE]. If set, the module is configured as a touchscreen controller; if cleared, the module is
configured as general purpose ADC.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-13
Touchscreen Controller
22.4.1
Touchscreen Controller Function
When the ASP is configured as touchscreen, the operation of the block is defined in Table 22-11. If
ASP_CR[ASPE] is set, the sequence defined in the table is written into the pen sample FIFO. The
configuration bits used in the below table are:
• MODE — Two bit mode select field
• AUTO — Automatic sampling features enabled
• AZE — Automatic zero value measurement to assist in dynamic calibration
• ASPE — ASP conversion enable
When AUTO and ASPE are set, the sampling continues until ASPE is cleared. There are two ways to clear
the ASPE bit: write 0 to ASP_CR[ASPE], or when the PENUP condition is detected and PENE is set, the
ASP automatically clears ASPE.
While ASPE is set, do not to change any of the ASP_CR, ASP_SET, ASP_TIM registers.
Because the ASP mostly works in the ADC_CLK domain, which is a much lower frequency than the
internal bus clock domain, commands to ASP normally need some time delay to be accepted by the ASP.
Normally, this delay is within one ADC_CLK cycle depending on the time the command is sent.
Table 22-11. Touchscreen Controller Operating Modes (TSE = 1)
ASPE
AZE
AUTO
MODE
ASP_CR Field
Pen Sample FIFO
Data Format
Notes
MCU Direct Sample Mode
00
00
X
X
X
X
0
The ASP_SET register determines the configuration of the bias switches and
No data is written
reference/input muxes. However, there is no conversion by the ADC. The pen
to the FIFO
detection circuit is active if ASP_SET[SW] is set.
1
After ASPE is set, the ADC starts one conversion. The ASP_SET register determines
the configuration of the bias switches and reference/input muxes. After the
Manual Sampling conversion is completed, the pen detection circuit is active, depending on the setting
of ASP_SET[SW]. To start another conversion, software must clear ASPE and set it
again.
Touchscreen Sample Mode
01
1
0
0
01
1
0
1
01
1
1
0
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
X,Y,
X,Y,
…
After ASPE is set, the ADC starts the conversion of the X, Y coordinate pairs. The
result is written to the pen sample FIFO. Between the X and Y conversion, optional
measurement idle time may be inserted using ASP_TIM[MIDLECNT]. After one
round (a pair of X, Y conversions) of measurement is complete, optional round idle
time may be inserted using ASP_TIM[RIDLECNT]. After that, the ASP automatically
starts another round of measurement. Between each round of conversion, there is an
option to insert one pen-down detection phase after the round idle phase using
ASP_CR[PENE]. Pen-up detection ise active at this time as well.
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
MCF52277 Reference Manual, Rev 2
22-14
Freescale Semiconductor
Touchscreen Controller
Table 22-11. Touchscreen Controller Operating Modes (TSE = 1) (continued)
ASPE
AZE
AUTO
MODE
ASP_CR Field
01
1
1
1
01
0
0
0
01
0
0
1
01
0
1
0
01
0
1
1
Pen Sample FIFO
Data Format
Notes
AZX, X, AZY, Y,
…
After ASPE is set, the ADC starts the conversion of the AZX, X, AZY, and Y
coordinates sets. The result is written to pen sample FIFO. The measurement idle
time, as configured in ASP_TIM[MIDLECNT], is only inserted after the X
measurement. Between AZX and X and between AZY and Y, no measurement idle
time is inserted. After one round of measurement is complete, optional round idle
time may be inserted using ASP_TIM[RIDLECNT]. After that, the ASP automatically
starts another round of measurement. Between each round of conversion, there is an
option to insert one pen-down detection phase after the round idle phase using
ASP_CR[PENE]. Pen-up detection is active at this time as well.
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
X,Y
After ASPE is set, the ADC starts the conversion of the X, Y coordinates pairs. The
result is written to the pen sample FIFO. Between the X and Y conversion, optional
measurement idle time may be inserted using ASP_TIM[MIDLECNT]. After the X and
Y conversions, no more conversions occur in the current round and pen-up detection
is active. To start another round of conversion, ASPE must be first cleared and set
again.
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
AZX, X, AZY, Y
After ASPE is set, the ADC starts the conversion of the AZX, X, AZY, and Y
coordinates sets. The result is written to pen sample FIFO. Between the conversion
of AZX to X and AZY to Y, no measurement idle time is inserted. The measurement
idle is only inserted after X measurement. After the X and Y conversions, no more
conversions occur in the current round and pen-up detection is active. To start
another round of conversion, ASPE must be first cleared and set again.
Auxiliary Input Sample Mode
10
1
X
0
10
1
X
1
10
0
X
0
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
Un,…,U1,
Un,…,U1,
…
After ASPE is set, the continuous conversion of the active auxiliary channel begins.
Ui indicates the active auxiliary channel numbering from high to low. For example, if
the touchscreen controller is configured as a 4-wire interface, then ADC_IN[7:4] are
available for ADC conversion, by setting the corresponding bit in ASP_CR[APTN].
Between each conversion except the round that wraps to the highest numbered
auxiliary channel, optional measurement idle time can be inserted using
ASP_TIM[MIDLECNT]. At the end of each round of conversion, there is an option to
insert round idle time using ASP_TIM[RIDLECNT]. Between each round of
conversion, you may insert one pen-down detection phase after the round idle phase.
The pen detection circuit is active if ASP_SET[SW] is set. AZE has no effect when
only general-purpose channels are converted.
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-15
Touchscreen Controller
Table 22-11. Touchscreen Controller Operating Modes (TSE = 1) (continued)
10
0
x
ASPE
AZE
AUTO
MODE
ASP_CR Field
1
Pen Sample FIFO
Data Format
Notes
Un,…,U1
Ui indicates the active auxiliary channel numbering from high to low. For example, if
the touchscreen controller is configured as a 4-wire interface, ADC_IN[7:4] is
available for ADC conversion by setting the corresponding bit in ASP_CR[APTN].
Between each conversion, optional measurement idle time may be inserted using
ASP_TIM[MIDLECNT]. After the X and Y conversions, no more conversions occur in
the current round and pen-up detection is active. AZE has no effect when only
general-purpose channels are converted. To start another round of conversion, the
ASPE must be first cleared and set again.
Touchscreen & Auxiliary Input Sample Mode
11
1
0
0
11
1
0
1
11
1
1
0
11
1
1
1
11
0
0
0
11
0
0
1
11
0
1
0
11
0
22.4.2
1
1
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
X,Y,Un,…,U1,
X,Y,Un,…,U1,
…
After ASPE is set, the continuous conversion on touchscreen coordinates and active
auxiliary channels begins. Between each conversion except the round that wraps to
X coordinate conversion, optional measurement idle time can be inserted using
ASP_TIM[MIDLECNT]. At the end of each round of conversion, there is an option to
insert round idle time using ASP_TIM[RIDLECNT]. Between each round of
conversion, you may insert one pen-down detection phase after the round idle phase.
The pen detection circuit is active if ASP_SET[SW] is set.
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
AZX, X, AZY, Y,
Un,…,U1
AZX, X, AZY, Y,
Un,…,U1,
…
Similar to the operation when AZE is cleared. However, the auto-calibration of the 0
value measurements are made for the touchscreen before X/Y measurement. No
measurement idle phase is inserted between the auto-zero and the X/Y
measurement.
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
X,Y,Un,…,U1
After ASPE is set, one round of conversion of touchscreen coordinates and active
auxiliary channels begins. Between each conversion, optional measurement idle time
may be inserted using ASP_TIM[MIDLECNT]. After the X and Y conversions, no
more conversions occur in the current round and pen-up detection is active.
No data is written The touchscreen is parked in the pen-detection state.
to the FIFO
AZX, X, AZY, Y,
Un,…,U1
Similar to the operation when AZE is cleared. However, the auto-calibration of the 0
value measurements are made for the touchscreen before X/Y measurement. No
measurement idle phase is inserted between the auto-zero and the X/Y
measurement.
General ADC Function
To configure the block as a general ADC, clear ASP_CR[TSE]. Table 22-12 describes the block’s
operation.
MCF52277 Reference Manual, Rev 2
22-16
Freescale Semiconductor
Touchscreen Controller
Table 22-12. General ADC Operating Modes (TSE=0)
AUTO
ASPE
ASP_CR Field
0
0
0
1
1
0
1
22.5
1
Pen Sample FIFO
Data Format
Notes
No data is written When ASPE is cleared, there is no operation.
to the FIFO
Un,…,U1
When ASPE is set, the ASP starts one round of conversion. For each active auxiliary
channel an ADC conversion is initiated. The process repeats until the last active auxiliary
channel is complete. Between each conversion, optional measurement idle time can be
inserted using ASP_TIM[MIDLECNT].
If no auxiliary channel is active (ASP_CR[APTN] = 0x00), there is no operation.
No data is written When ASPE is cleared, there is no operation.
to the FIFO
Un,…,U1,
Un,…,U1,
…
When ASPE is set, the ASP starts continuous conversion on active auxiliary channels.
The measurement sequence is started from highest numbered active channel to lowest
numbered active channel. The same sequence repeats until ASPE is cleared. For each
active auxiliary channel an ADC conversion is initiated. Between each conversion, except
the round that wraps to the highest numbered auxiliary channel, optional measurement
idle time can be inserted using ASP_TIM[MIDLECNT]. At the end of each round of
conversion, there is an option to insert round idle time using ASP_TIM[RIDLECNT].
If no auxiliary channel is active (ASP_CR[APTN] = 0x00), there is no operation.
Initialization/Application Information
After reset, the ASP module is in power-down mode. Configure the module according to the application
requirements. Then, enable the module by clearing ASP_CR[MDIS]. The suggested configuration for
various typical applications is defined in this section.
22.5.1
Touchscreen Mode 00
Touchscreen mode 00 provides the most flexibility. All control of the bias switches and reference/input
muxes is dependent on ASP_SET. Starting the conversion is also fully decided by asserting ASPE. With
this flexibility, you can freely define your own operation sequence. Although TSE is set in this mode, you
can also use this mode to implement complex general-purpose ADC conversion sequences. Because of this
flexibility, it is the only mode not suitable for basic operation and requires the heaviest load on the
processor. Therefore, it is highly recommended not to use this mode, unless other modes cannot achieve
the required operation.
Figure 22-10 and Figure 22-11 illustrate a typical operation sequence when TSE = 1, CALA = 0,
MODE = 00 (AUTO, AZE, PENE, MIDLECNT, and RIDLECNT are not relevant to the operation).
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-17
Touchscreen Controller
Touchscreen
logic
Pen detect
X-measurement setting
Y-measurement setting
c
Pen down
interrupt
a
h
b
ASP_CR[ASPE]
d
f
Data ready
interrupt
i
e
k
g
j
l
Figure 22-10. Manual Mode For Touchscreen Application
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
k)
l)
Pen-down is detected by the touchscreen controller and pen-down interrupt is initiated
MCU clears/masks pen-down interrupt
MCU configures ASP_SET for X measurement
MCU sets ASPE to initiate X-coordinate conversion
Conversion completes, result is written into the FIFO, and the data ready interrupt occurs
MCU clears ASPE to prepare for the next operation
MCU reads out the X measurement result, and data ready interrupt is cleared automatically
MCU changes the configuration to Y measurement
MCU sets ASPE again to initiate Y-coordinate conversion
Conversion complete, the result is written into FIFO, and the data ready interrupt occurs
MCU clears ASPE to prepare for the next operation
MCU reads out the Y measurement result, and data ready interrupt is cleared automatically
Touchscreen
logic
Configuration 1
Configuration 2
a
f
ASP_CR[ASPE]
b
Data ready
interrupt
d
c
g
e
i
h
j
Figure 22-11. Manual Mode For General-Purpose ADC Application
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
MCU sets ASP_SET to configuration 1
MCU sets ASPE to initiate the conversion
Conversion completes, result is written into FIFO, and data ready interrupt occurs
MCU clears ASPE to prepare for the next operation
MCU reads out the conversion result and the data ready interrupt is cleared automatically
MCU changes ASP_SET to configuration 2
MCU sets ASPE to initiate the conversion
Conversion completes, result is written into FIFO, and data ready interrupt occurs
MCU clears ASPE to prepare for the next operation
MCU reads out the conversion result and the data ready interrupt is cleared automatically
MCF52277 Reference Manual, Rev 2
22-18
Freescale Semiconductor
Touchscreen Controller
22.5.2
Touchscreen Mode 01—Single Round
Touchscreen mode 01 single round is recommended for discrete input touchscreen applications such as a
push-button application. Using this mode can greatly reduce MCU power and processing because one
touch results in one pair of X/Y coordinate conversions. Two extra conversions (AZX and AZY) are
introduced if auto-zero capability is enabled. After the parameter configuration is complete in this mode,
the MCU can be driven via interrupts and leave the control of the bias switches and reference/input muxes
to the ASP. The drawback of this mode is the touch measurement cannot be cancelled, and using one
measurement may reduce the resolution caused by noise.
Figure 22-12 illustrates a typical operation sequence when TSE = 1, CALA = 0, MODE = 01, and
AUTO = 0. The following example assumes AZE = 1 and MIDLECNT ≠ 0.
Touchscreen
logic
Pen
detection
Pen
detection
AZX
measure
a
X
measure
Measurement idle
AZY
measure
Y
measure
e
Pen
detection
Pen
detection
f
Pen down
interrupt
b
c
ASP_CR[ASPE]
d
Pen up
interrupt
h
g
i
Figure 22-12. Mode 01 Single Round
a)
b)
c)
d)
e)
f)
g)
h)
i)
When ASP configuration is complete, the ASP parks on the pen-detect state
Pen-down event is detected and the pen-down interrupt occurs
MCU responds to the interrupt and clears/masks the interrupt
MCU sets ASPE to initiate the measurement operation
ASP begins with the AZX measurement, followed by X measurement, measurement IDLE,
AZY measurement, Y measurement. All results are written into the FIFO.
After a round of measurements completes, the ASP parks on the pen-detect state again. If the
watermark interrupt is enabled and set to 4, the MCU should detect the FIFO watermark
interrupt and upload the conversion results at this time.
Pen-up event is detected and pen-up interrupt occurs. If the FIFO interrupts mechanism is not
used, the conversion results can be uploaded at this time.
The ASP automatically clears ASPE if PENE is set, or software must clear ASPE
MCU clears the pen-up interrupt
NOTE
If MIDLECNT is equal to zero, remove the IDLE measurement phase.
If AZE is cleared, remove the AZX and AZY measure phases.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-19
Touchscreen Controller
22.5.3
Touchscreen Mode 01—Auto
Touchscreen mode 01 auto is recommended for applications that require continuous input (such as a
drawing), higher coordinate resolution (by averaging the measurement), or touch with cancel capability
(by detecting that the pen-up point is different than the pen-down point).
The operation in this mode is also highly automatic. After the MCU completes configuration, the handling
can be interrupt driven to save processing load on the MCU. The processor needs to set ASPE when the
pen-down interrupt is detected and then upload the measurement results during the FIFO watermark
interrupt service routine.
Figure 22-13 and Figure 22-14 illustrate a typical operation sequence when TSE = 1, CALA = 0,
MODE = 01 and AUTO = 1. The following example assumes MIDLECNT ≠ 0, RIDLECNT ≠ 0,
PENE = 1, AZE = 1.
Touchscreen
logic
Pen
detection
Pen
detection
X
measure
AZX
a
Measurement idle
AZY
Y
measure
Round
idle
Pen
detection
AZX
X
measure
e
Pen down
interrupt
b
c
ASP_CR[ASPE]
d
FIFO watermark
interrupt
f
g
Figure 22-13. Mode 01 Auto, Part 1
Touchscreen
logic
AZX
X
measure
AZY
Y
measure
Round
idle
Pen
detection
Pen
detection
AZX
Pen
detection
Pen
detection
n
FIFO watermark
interrupt
i
j
Pen up
interrupt
k
m
ASP_CR[ASPE]
l
Figure 22-14. Mode 01 Auto, Part 2
a) When ASP configuration is complete, the ASP parks on pen detection state
b) Pen-down event is detected and the pen-down interrupt occurs
c) MCU responds to the interrupt and disables the pen-down interrupt. It is recommended to clear
the FIFO in this step.
d) MCU sets ASPE to initiate the measurement operation
e) ASP is begins the continuous measurement
f) FIFO watermark interrupt occurs when one round of conversions is complete. For this
example, the watermark level is 4
g) MCU uploads the results of one round of conversions, which clears the FIFO watermark
interrupt
MCF52277 Reference Manual, Rev 2
22-20
Freescale Semiconductor
Touchscreen Controller
h) Step f and g occur repeatedly
i) FIFO watermark interrupt occurs for the last round of conversions
j) MCU uploads the results of this round of conversions, which clears the FIFO watermark
interrupt
k) Pen-up event is detected and the pen-up interrupt occurs
l) ASPE is cleared automatically by the ASP
m) MCU responds by clearing the pen-up interrupt. The pen-down interrupt can also be cleared
here and enabled again.
n) One extra conversion state is run by the state machine, but ASPE being cleared blocks the real
conversion operation by the ADC and no extra data is written into the FIFO
NOTE
If MIDLECNT is equal to zero, remove the IDLE measurement phase.
If AZE is cleared, remove the AZX and AZY measure phases.
If RIDLECNT is equal to zero, remove the round IDLE phase.
If PENE is cleared, there is no pen detection phase after the end of round.
Software must stop the conversion according to the measurement results.
22.5.4
Touchscreen Mode 10—Single Round
Touchscreen mode 10 single round is used for touchscreen-controlled auxiliary channel measurement. In
this mode, the touchscreen can be used as purely a push button. Pressing the push button (the coordinates
are not relevant) triggers one single round of conversions.
NOTE
Figure 22-15 illustrates a typical operation sequence when TSE = 1, CALA = 0, MODE = 10, and
AUTO = 0. The following example assumes MIDLECNT ≠ 0.
Touchscreen
logic
Pen
detection
Pen
detection
Un
measure
a
Measurement idle
Ui
measure
Measurement idle
e
U1
measure
Pen
Pen
detection detection
f
Pen down
interrupt
b
c
ASP_CR[ASPE]
d
Pen up
interrupt
h
g
i
Figure 22-15. Mode 10 Single Round
a) When ASP configuration is complete, the ASP parks on the pen detection state
b) Pen-down event is detected and the pen-down interrupt occurs
c) MCU responds to the interrupt and disables the pen-down interrupt. It is recommended to clear
the FIFO in this step.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-21
Touchscreen Controller
d) MCU sets ASPE to initiate the measurement operation
e) ASP begins one round of auxiliary channel measurements, starting with the highest numbered
active channel
f) ASP completes one round of auxiliary channel measurement and enters the pen-detect state
again. If the FIFO watermark is set to the number of active auxiliary channels, the FIFO
watermark interrupt can be used to upload the conversion results.
g) A pen-up event is detected and the pen-up interrupt occurs. If the FIFO watermark interrupt is
not used, the conversion results may be uploaded here.
h) ASPE is cleared automatically or by MCU depending on the PENE setting. The ASP is ready
to detect the next pen-down event.
i) MCU clears the pen-up interrupt
NOTE
If MIDLECNT is equal to zero, remove the IDLE measurement phase.
22.5.5
Touchscreen Mode 10—Auto
Touchscreen mode 10 auto is also used for touchscreen-controlled auxiliary channel measurement. The
difference with the mode 10 single round is that the touchscreen press duration may control the number of
conversions.
NOTE
Figure 22-16 and Figure 22-17 illustrate a typical operation sequence when TSE = 1, CALA = 0,
MODE = 10, and AUTO = 1. The following example assumes MIDLECNT ≠ 0, RIDLECNT ≠ 0,
PENE = 1.
Touchscreen
logic
Pen
detection
Pen
detection
Un
measure
a
Measurement idle
Ui
measure
Measurement idle
U1
measure
e
Round
idle
Pen
detection
Un
measure
Measurement idle
f
Pen down
interrupt
b
c
ASP_CR[ASPE]
d
FIFO watermark
interrupt
g
h
Figure 22-16. Mode 10 Auto, Part 1
MCF52277 Reference Manual, Rev 2
22-22
Freescale Semiconductor
Touchscreen Controller
Touchscreen
logic
Un
measure
Measurement idle
Ui
measure
Measurement idle
U1
measure
Round
idle
Pen
detection
Pen
detection
Un
measure
j
Pen
detection
Pen
detection
p
FIFO watermark
interrupt
k
l
Pen up
interrupt
m
o
ASP_CR[ASPE]
n
Figure 22-17. Mode 10 Auto, Part 2
a) When ASP configuration is complete, the ASP parks on the pen detection state
b) Pen-down event is detected and the pen-down interrupt occurs
c) MCU responds to the interrupt and masks the pen-down interrupt. It is recommended to clear
the FIFO in this step
d) MCU sets ASPE to initiate the measurement operation
e) ASP begins the continuous auxiliary channel measurements
f) ASP completes one round of measurements
g) If the FIFO watermark level is set to the same number of active auxiliary channels, the FIFO
watermark interrupt occurs
h) MCU uploads the conversion results, which clears the FIFO watermark interrupt
i) Steps f–h repeat
j) ASP completes the last round of auxiliary channel measurements
k) FIFO watermark interrupt occurs
l) MCU uploads the conversion results, which clears the FIFO watermark interrupt
m) Pen-up event is detected and the pen-up interrupt occurs
n) ASPE is cleared automatically after detection of pen-up interrupt
o) MCU clears the pen-up and pen-down interrupt
p) One extra conversion state is run by the state machine, but ASPE being cleared blocks the real
conversion operation by the ADC and no extra data is written into the FIFO
NOTE
If MIDLECNT is equal to zero, remove the IDLE measurement phase.
If RIDLECNT is cleared, remove the IDLE round phase.
If PENE is cleared, no pen-detection phase is after the end of the round.
Software must stop the conversion.
22.5.6
Touchscreen Mode 11—Single Round
Touchscreen mode 11 single round is used for touchscreen-controlled X/Y coordinate and auxiliary
channel measurement. One touch only results in one round of measurement.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-23
Touchscreen Controller
Figure 22-18 illustrates a typical operation sequence when TSE = 1, CALA = 0, MODE = 11, and
AUTO = 0. The following example assumes MIDLECNT ≠ 0, RIDLECNT ≠ 0, AZE = 1.
Touchscreen
logic
Pen
detection
Pen
detection
AZX
a
X
Measuremeasure ment idle
Y
AZY measure
Measurement idle
Ui
measure
MeasureU1
ment idle measure
e
Pen
detection
Pen
detection
f
Pen down
interrupt
b
c
ASP_CR[ASPE]
d
h
Pen up
interrupt
g
i
Figure 22-18. Mode 11 Single Round
a) When ASP configuration is complete, the ASP parks on the pen detection state
b) Pen-down event is detected and the pen-down interrupt occurs
c) MCU responds to the interrupt and masks the pen-down interrupt. It is recommended to clear
the FIFO in this step.
d) MCU sets ASPE to initiate the measurement operation
e) ASP begins one round of X/Y coordinate and active auxiliary channels measurements
f) ASP completes one round of measurement and enters the pen-detect state again. If the FIFO
watermark level is set properly, the FIFO watermark interrupt may be used to upload the
conversion results here.
g) Pen-up event is detected and the pen-up interrupt occurs. If FIFO watermark interrupt is not
used, the conversion results may be uploaded here.
h) ASPE is cleared automatically or by software depending on the setting of PENE. The ASP is
ready to detect the next pen-down event.
i) MCU clears the pen-up interrupt
NOTE
If MIDLECNT is cleared, only need to remove IDLE measurement phase.
22.5.7
Touchscreen Mode 11—Auto
Touchscreen mode 11 auto is also used for touchscreen-controlled X/Y coordinate and auxiliary channel
measurement. The difference with the mode 11 single round is that the touchscreen press duration may be
used to control the number of conversions.
Figure 22-19 and Figure 22-20 illustrate a typical operation sequence when TSE = 1, CALA = 0,
MODE = 11, and AUTO = 1. The following example with MIDLECNT ≠ 0, RIDLECNT ≠ 0, AZE = 1,
PENE = 1.
MCF52277 Reference Manual, Rev 2
22-24
Freescale Semiconductor
Touchscreen Controller
Touchscreen
logic
Pen
detection
Pen
detection
AZX
a
X
Measuremeasure ment idle
Y
AZY measure
Measurement idle
Ui
measure
MeasureU1
ment idle measure
e
Pen
detection
Round
idle
f
Pen down
interrupt
b
c
ASP_CR[ASPE]
d
FIFO watermark
interrupt
g
h
Figure 22-19. Mode 11 Auto, Part 1
Touchscreen
logic
AZX
X
Measuremeasure ment idle
Y
AZY measure
Measurement idle
Ui
measure
MeasureU1
ment idle measure
Round
idle
Pen
detection
Pen
detection
AZX
j
p
FIFO watermark
interrupt
k
l
Pen up
interrupt
m
o
ASP_CR[ASPE]
n
Figure 22-20. Mode 11 Auto, Part 2
a) When ASP configuration is complete, the ASP parks on the pen detection state
b) Pen-down event is detected and the pen-down interrupt occurs
c) MCU responds to the interrupt and masks the pen-down interrupt. It is recommended to clear
the FIFO in this step.
d) MCU sets ASPE to initiate the measurement operation
e) ASP begins the measurements
f) ASP completes one round of auxiliary channel measurements
g) If the FIFO watermark level is set to the same number of active auxiliary channels plus four,
the FIFO watermark interrupt occurs
h) MCU uploads the conversion results, which clears the FIFO watermark interrupt
i) Steps f–h repeat
j) ASP completes the last round of measurement
k) FIFO watermark interrupt occurs
l) MCU uploads the conversion results, which clears the FIFO watermark interrupt
m) Pen-up event is detected and the pen-up interrupt occurs
n) ASPE is cleared automatically after detection of the pen-up interrupt
o) MCU clears the pen-up and pen-down interrupt
p) One extra conversion state is run by the state machine, but ASPE being cleared blocks the real
conversion operation by the ADC and no extra data is written into the FIFO
NOTE
If MIDLECNT is equal to zero, remove the IDLE measurement phase.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-25
Touchscreen Controller
If AZE is cleared, remove the AZX and AZY measure phases.
If RIDLECNT is equal to zero, remove the IDLE round phase.
If PENE is cleared, no pen-detection phase is after the end of round.
Software must stop the conversion.
22.5.8
General Purpose ADC—Single Round
General purpose ADC single round can be used to take a round of measurement on a pre-defined auxiliary
channel pattern. All eight input channels may be configured in any combination. However, the
measurement is always started with the highest active channel down to lowest active channel.
Figure 22-21 illustrates a typical operation sequence when TSE = 0 and AUTO = 0. (CALA, MODE,
AZE, TSTYP, PENE, and RIDLECNT have no effect.) The following example assumes MIDLECNT ≠ 0.
Touchscreen
logic
Un
measure
Idle
a
MeasureUi
ment idle measure
Measurement idle
U1
measure
c
Idle
d
ASP_CR[ASPE]
b
FIFO watermark
interrupt
g
e
f
Figure 22-21. General Purpose ADC Single Round
a)
b)
c)
d)
e)
ASP configuration is complete, and waits for ASPE to be set
MCU sets ASPE to initiate the conversions
ASP begins a round of conversions
ASP completes the round of conversions and enters idle state again
If the FIFO watermark level is set to the number of active auxiliary channels, the FIFO
watermark interrupt occurs
f) MCU uploads the conversion results, which clears the FIFO watermark interrupt
g) MCU clears the ASPE bit and ASP is ready for the next round of conversions
NOTE
If MIDLECNT is equal to zero, remove the IDLE measurement phase.
22.5.9
General Purpose ADC—Auto
General purpose ADC auto can be used to take continuous measurements on a pre-defined auxiliary
channel pattern repeatedly. All eight input channels may be configured in any combination. However, the
measurement is always started with the highest active channel, down to lowest active channel, and
repeated.
Figure 22-22 and Figure 22-23 illustrate a typical operation sequence when TSE = 0 and AUTO = 1.
(CALA, MODE, AZE, TSTYP, and PENE have no effect.) The following example assumes
MIDLECNT ≠ 0, RIDLECNT ≠ 0.
MCF52277 Reference Manual, Rev 2
22-26
Freescale Semiconductor
Touchscreen Controller
Touchscreen
logic
Un
measure
Idle
a
MeasureUi
ment idle measure
Measurement idle
U1
measure
Round
idle
c
Un
Measuremeasure ment idle
d
ASP_CR[ASPE]
b
FIFO watermark
interrupt
e
f
Figure 22-22. General Purpose ADC Auto, Part 1
Touchscreen
logic
Un
measure
MeasureUi
ment idle measure
Measurement idle
U1
measure
Round
idle
Idle
h
ASP_CR[ASPE]
j
FIFO watermark
interrupt
i
k
Figure 22-23. General Purpose ADC Auto, Part 2
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
k)
ASP configuration is complete, and waits for ASPE to be set.
MCU sets ASPE to initiate the conversions.
ASP begins a round of conversions.
ASP completes one round of conversions.
If the FIFO watermark level is set to the number of active auxiliary channels, the FIFO
watermark interrupt occurs.
MCU uploads the conversion results, which clears the FIFO watermark interrupt.
Steps d–e repeat.
The last round of conversions is completed. (For this example, the required number of rounds
of conversions is done.)
FIFO watermark interrupt occurs.
MCU clears ASPE to stop the conversion.
MCU uploads the last round of conversion results, which clears the FIFO watermark interrupt.
NOTE
If MIDLECNT is equal to zero, remove the IDLE measurement phase.
If RIDLECNT is equal to zero, remove the IDLE round phase.
22.5.10 Touchscreen Calibration—Single Round
Touchscreen calibration single round is used to capture one set of calibration data for correction for the
device and environment. The calibration process starts when ASPE is set. The size of the data set received
is dependent on the touchscreen interface type (e.g., 4 data for 4-wire).
Figure 22-24 illustrates a typical operation sequence when TSE = 1, CALA = 1, AUTO = 0. (MODE,
AZE, PENE, and RIDLECNT have no effect.) The following example assumes MIDLECNT ≠ 0.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-27
Touchscreen Controller
Touchscreen
logic
CALA1
measure
Idle
Measure- CALAi
ment idle measure
Measurement idle
CALAn
measure
Idle
a
ASP_CR[ASPE]
b
d
FIFO watermark
interrupt
c
e
Figure 22-24. Touchscreen Calibration Single Round
a) ASP configuration is complete, and waits for ASPE to be set.
b) MCU sets ASPE to initiate the calibration process.
c) FIFO watermark interrupt occurs when the watermark level is equal to the amount of data
captured.
d) ASP responds to the interrupt by clearing the ASPE bit.
e) ASP clears the FIFO watermark interrupt by uploading the data from the FIFO.
NOTE
If MIDLECNT is equal to zero, remove the IDLE measurement phase.
22.5.11 Touchscreen Calibration – Auto
Touchscreen calibration auto is similar to the single round in capturing the calibration data set. However,
it improves the calibration precision by repeating the process.
NOTE
Figure 22-25 and Figure 22-26 illustrate a typical operation sequence when TSE = 1, CALA = 1, and
AUTO = 1. (MODE, AZE, and PENE have no effect.) The following example assumes MIDLECNT ≠ 0
and RIDLECNT ≠ 0.
Touchscreen
logic
CALA1
measure
Idle
Measure- CALAi
ment idle measure
Measurement idle
CALAn
measure
Round
idle
CALA1 Measuremeasure ment idle
a
ASP_CR[ASPE]
b
FIFO watermark
interrupt
c
d
Figure 22-25. Touchscreen Calibration Auto, Part 1
Touchscreen
logic
Round
idle
CALA1
measure
Measure- CALAi
ment idle measure
Measurement idle
CALAn
measure
Round
idle
Idle
ASP_CR[ASPE]
g
FIFO watermark
interrupt
f
h
Figure 22-26. Touchscreen Calibration Auto, Part 2
a) ASP configuration is complete, and waits for ASPE to be set
MCF52277 Reference Manual, Rev 2
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Freescale Semiconductor
Touchscreen Controller
b) MCU sets ASPE to initiate the calibration process
c) FIFO watermark interrupt occurs when the water mark level is equal to the amount of data for
one round of calibration
d) ASP clears the FIFO watermark interrupt by uploading the data from the FIFO
e) Steps c and d repeat
f) The FIFO watermark interrupt for the last round of calibration occurs
g) ASP clears ASPE to stop the calibration
h) ASP uploads the last round of calibration data from the FIFO, which clears the FIFO watermark
interrupt
NOTE
If MIDLECNT is equal to zero, remove the IDLE measurement phase.
If RIDLECNT is equal to zero, remove the IDLE round phase.
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
22-29
Touchscreen Controller
MCF52277 Reference Manual, Rev 2
22-30
Freescale Semiconductor
Chapter 23
FlexCAN
23.1
Introduction
The FlexCAN is a communication controller implementing the controller area network (CAN) protocol,
an asynchronous communications protocol used in automotive and industrial control systems. It is a high
speed (1 Mbps), short distance, priority-based protocol that can communicate using a variety of mediums
(such as fiber optic cable or an unshielded twisted pair of wires). The FlexCAN supports the standard and
extended identifier (ID) message formats specified in the CAN protocol specification, revision 2.0, part B.
The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting
the specific requirements of this field: real-time processing, reliable operation in the EMI environment of
a vehicle, cost-effectiveness, and required bandwidth. A general working knowledge of the CAN protocol
revision 2.0 is assumed in this document. For details, refer to the CAN protocol revision 2.0 specification.
23.1.1
Block Diagram
A block diagram describing the various submodules of the FlexCAN module is shown in Figure 23-1.
Each submodule is described in detail in subsequent sections.
FlexCAN
RXIMR15
MB15
RXIMR14
MB14
••
•
•••
••
••
•
•••
••
RXIMR3
MB3
RXIMR2
RXIMR1
RXIMR0
MB2
MB1
MB0
Message
Buffer
Management
••
•
•••
•
•••
••
Max MB #
[0:15]
CAN
Protocol
Interface
CANTX
CANRX
Bus Interface Unit
Internal Bus Interface
Clocks, Address and Data Buses,
Interrupt and Test Signals
Figure 23-1. FlexCAN Block Diagram
MCF52277 Reference Manual, Rev 2
Freescale Semiconductor
23-1
FlexCAN
The message buffer architecture is shown in Figure 23-2 and Figure 23-3. Figure 23-3 shows the MB
architecture when individual masks are used, while Figure 23-2 shows the legacy configuration">