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describes cache configuration.

30–29 Reserved, must be cleared.

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Table 5-2. CACR Field Descriptions (continued)

Field Description

CPDI

CFRZ

Disable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the cache entry defined by bits

[12:4] of the address is invalidated if CPDI is cleared. If CPDI is set, no operation is performed.

0 Enable invalidation

1 Disable invalidation

Cache freeze. This field allows the user to freeze the contents of the cache. When CFRZ is asserted line fetches can be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritten. If a given cache location is invalid, the contents of the line-fill buffer can be written into the memory array while CFRZ is asserted.

0 Normal Operation

1 Freeze valid cache lines

26–25 Reserved, must be cleared.

CINV

Cache invalidate. The cache invalidate operation is not a function of the CENB state (this operation is independent of the cache being enabled or disabled). Setting this bit forces the cache to invalidate all, half, or none of the tag array entries depending on the state of the DISI, DISD, INVI, and INVD bits. The invalidation process requires several cycles of overhead plus 512 machine cycles to clear all tag array entries and 256 cycles to clear half of the tag array entries, with a single cache entry cleared per machine cycle. The state of this bit is always read as a zero. After a hardware reset, the cache must be invalidated before it is enabled.

0 No operation

1 Invalidate all cache locations

describes how to set the cache invalidate all bit.

DISI

DISD

Disable instruction caching. When set, this bit disables instruction caching. This bit, along with the CENB (cache enable) and DISD (disable data caching) bits, control the cache configuration. See the CENB definition for a detailed description.

0 Enable instruction caching

1 Disable instruction caching

describes cache configuration and Table 5-4

describes how to set the cache invalidate all bit.

Disable data caching. When set, this bit disables data caching. This bit, along with the CENB (cache enable) and

DISI (disable instruction caching) bits, control the cache configuration. See the CENB definition for a detailed description.

0 Enable data caching

1 Disable data caching

describes cache configuration and Table 5-4

describes how to set the cache invalidate all bit.

INVI

INVD

CINV instruction cache only. This bit can not be set unless the cache configuration is split (DISI and DISD cleared).

For instruction or data cache configurations this bit is a don’t-care. For the split cache configuration, this bit is part of the control for the invalidate all operation. See the CINV definition for a detailed description

describes how to set the cache invalidate all bit.

CINV data cache only. This bit can not be set unless the cache configuration is split (DISI and DISD cleared). For instruction or data cache configurations this bit is a don’t-care. For the split cache configuration, this bit is part of the control for the invalidate all operation. See the CINV definition for a detailed description

memory attributes, see Section 5.3.2, “Memory Reference Attributes .

describes how to set the cache invalidate all bit.

19–11 Reserved, must be cleared.

CEIB

Cache enable non-cacheable instruction bursting. Setting this bit enables the line-fill buffer to be loaded with burst transfers under control of CLNF[1:0] for non-cacheable accesses. Non-cacheable accesses are never written into the memory array. See

Table 5-7

0 Disable burst fetches on non-cacheable accesses

1 Enable burst fetches on non-cacheable accesses

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Table 5-2. CACR Field Descriptions (continued)

Field

DCM

DBWE

7–6

DWP

EUSP

3–2

1–0

CLNF

Description

Default cache mode. This bit defines the default cache mode. For more information on the selection of the effective

0 Caching enabled

1 Caching disabled

Default buffered write enable. This bit defines the default value for enabling buffered writes. If DBWE = 0, the termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is completed. If DBWE = 1, the write cycle on the local bus is terminated immediately and the operation buffered in the bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus and the external bus. Generally, enabled buffered writes provide higher system performance but recovery from access errors can be more difficult. For the ColdFire core, reporting access errors on operand writes is always imprecise and enabling buffered writes further decouples the write instruction and the signaling of the fault

0 Disable buffered writes

1 Enable buffered writes

Reserved, must be cleared.

Default write protection

0 Read and write accesses permitted

1 Only read accesses permitted

Enable user stack pointer. See Section 3.2.3, “Supervisor/User Stack Pointers (A7 and OTHER_A7)”

for more information on the dual stack pointer implementation.

0 Disable the processor’s use of the User Stack Pointer

1 Enable the processor’s use of the User Stack Pointer

Reserved, must be cleared.

Cache line fill. These bits control the size of the memory request the cache issues to the bus controller for different

initial instruction line access offsets. See Table 5-6

for external fetch size based on miss address and CLNF.

shows the relationship between CACR[CENB, DISI, & DISD] bits and the cache configuration.

Table 5-3. Cache Configuration as Defined by CACR

CACR

[CENB]

CACR

[DISI]

1 x

CACR

[DISD]

Configuration Description

N/A

Split Instruction/

Data Cache

Cache is completely disabled

4 KByte direct-mapped instruction cache (uses upper half of tag and storage arrays) and 4 KByte direct-mapped write-through data cache (uses lower half of tag and storage arrays)

Instruction Cache 8 KByte direct-mapped instruction cache (uses all of tag and storage arrays)

Data Cache 8 KByte direct-mapped write-through data cache

(uses all of tag and storage arrays)

background debug mode (BDM). Therefore, the register diagram, Figure 5-3 , is shown as read/write. At

shows the relationship between CACR[DISI, DISD, INVI, & INVD] and setting the cache invalidate all bit (CACR[CINV]).

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Table 5-4. Cache Invalidate All as Defined by CACR

CACR

[DISI]

CACR

[DISD]

CACR

[INVI]

1 x x

CACR

[INVD]

1 x x

Configuration Operation

Split Instruction/

Data Cache

Split Instruction/

Data Cache

Split Instruction

Data Cache

Split Instruction/

Data Cache

Invalidate all entries in 4-KByte instruction cache and 4-KByte data cache

Invalidate only 4 KByte data cache

Invalidate only 4 KByte instruction cache

No invalidate

Instruction Cache Invalidate 8 KByte instruction cache

Data Cache Invalidate 8 KByte data cache

5.2.2 Access Control Registers (ACR0, ACR1)

The ACRs provide a definition of memory reference attributes for two memory regions (one per ACR).

This set of effective attributes is defined for every memory reference using the ACRs or the set of default attributes contained in the CACR. The ACRs are examined for every processor memory reference not mapped to the SRAM memories.

The ACRs are 32-bit, write-only supervisor control register. They are accessed in the CPU address space via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The ACRs can be read when in

system reset, both registers are disabled with ACRn[EN] cleared.

NOTE

Peripheral space (0xE000_0000-0xFFFF_FFFF) should not be cached. The combination of the CACR defaults and the two ACRn registers must define the non-cacheable attribute for this address space.

BDM: 0x004 (ACR0)

0x005 (ACR1)

Access: Supervisor write-only

BDM read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7

0 0 0 0 0 0

AB AM EN SM

6 5

CM BWE

4 3

0 0

1 0

0 0

Reset – – – – – – – – – – – – – – – – 0 – – 0 0 0 0 0 0 – – 0 0 – 0 0

Figure 5-3. Access Control Registers (ACRn)

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Table 5-5. ACRn Field Descriptions

Field

31–24

23–16

14–13

12–7

BWE

4–3

1–0

Description

Address base. This 8-bit field is compared to address bits [31:24] from the processor's local bus under control of the

ACR address mask. If the address matches, the attributes for the memory reference are sourced from the given ACR.

Address mask. Masks any AB bit. If a bit in the AM field is set, the corresponding bit of the address field comparison is ignored.

ACR Enable. Hardware reset clears this bit, disabling the ACR.

0 ACR disabled

1 ACR enabled

Supervisor mode. Allows the given ACR to be applied to references based on operating privilege mode of the

ColdFire processor. The field uses the ACR for user references only, supervisor references only, or all accesses.

00 Match if user mode

01 Match if supervisor mode

1x Match always—ignore user/supervisor mode

Reserved, must be cleared.

Cache mode.

0 Caching enabled

1 Caching disabled

Buffered write enable. Defines the value for enabling buffered writes. If BWE is cleared, the termination of an operand write cycle on the processor's local bus is delayed until the system bus cycle is completed. Setting BWE terminates the write cycle on the local bus immediately and the operation is then buffered in the bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus and the system bus.

Generally, the enabling of buffered writes provides higher system performance but recovery from access errors may be more difficult.

For the V2 ColdFire core, the reporting of access errors on operand writes is always imprecise, and enabling buffered writes simply decouples the write instruction from the signaling of the fault even more.

0 Writes are not buffered.

1 Writes are buffered.

Reserved, must be cleared.

Write protect. Defines the write-protection attribute. If the effective memory attributes for a given access select the

WP bit, an access error terminates any attempted write with this bit set.

0 Read and write accesses permitted

1 Only read accesses permitted

Reserved, must be cleared.

5.3 Functional Description

The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches from the ColdFire core and certain memory fetches initiated by the debug module. Typically, the debug module's memory references appear as supervisor data accesses but the unit can be programmed to generate user-mode accesses and/or instruction fetches. The cache processes any fetch access in the normal manner.

5.3.1 Interaction with Other Modules

Because the cache and high-speed SRAM module are connected to the ColdFire core's local data bus, certain user-defined configurations can result in simultaneous fetch processing.

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If the referenced address is mapped into the SRAM module, that module services the request in a single cycle. In this case, data accessed from the cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the cache handles the request in the normal fashion.

5.3.2 Memory Reference Attributes

For every memory reference the ColdFire core or the debug module generates, a set of effective attributes is determined based on the address and the access control registers (ACRs). This set of attributes includes the cacheable/non-cacheable definition, the precise/imprecise handling of operand write, and the write-protect capability.

In particular, each address is compared to the values programmed in the ACRs. If the address matches one of the ACR values, the access attributes from that ACR are applied to the reference. If the address does not match either ACR, then the default value defined in the cache control register (CACR) is used. The specific algorithm is as follows: if (address == ACR0_address including mask)

Effective Attributes = ACR0 attributes

else if (address == ACR1_address including mask)

Effective Attributes = ACR1 attributes

else Effective Attributes = CACR default attributes

5.3.3 Cache Coherency and Invalidation

The cache does not monitor data references for accesses to cached instructions. Therefore, software must maintain instruction cache coherency by invalidating the appropriate cache entries after modifying code segments if instructions are cached.

The cache invalidation can be performed in several ways. For the instruction- or data-only configurations, setting CACR[CINV] forces the entire cache to be marked as invalid. The invalidation operation requires

512 cycles because the cache sequences through the entire tag array, clearing a single location each cycle.

For the split configuration, CACR[INVI] and CACR[INVD] can be used in addition to CACR[CINV] to clear the entire cache, only the instruction half, or only the data half. Any subsequent fetch accesses are postponed until the invalidation sequence is complete.

The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is executed, the cache entry defined by bits [12:4] of the source address register is invalidated, provided CACR[CPDI] is cleared. For the split data/instruction cache configuration, software directly controls bit 12 that selects whether an instruction cache or data cache line is being accessed.

These invalidation operations can be initiated from the ColdFire core or the debug module.

5.3.4 Reset

A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting

CACR[CINV] before the cache can be enabled.

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5.3.5 Cache Miss Fetch Algorithm/Line Fills

As discussed in Section 5.1.2, “Introduction ,” the cache hardware includes a 16-byte, line-fill buffer for providing temporary storage for the last fetched line.

With the cache enabled as defined by CACR[CENB], a cacheable fetch that misses in the tag memory and the line-fill buffer generates an external fetch. For data misses, the size of the external fetch is always 16 bytes. For instruction misses, the size of the external fetch is determined by the value contained in the 2-bit

CLNF field of the CACR and the miss address. Table 5-6

shows the relationship between the CLNF bits, the miss address, and the size of the external fetch.

Table 5-6. Initial Fetch Offset vs. CLNF Bits

CLNF[1:0]

Line

Longword Address Bits[3:2]

Line

Longword

Line

Longword

Line

Depending on the runtime characteristics of the application and the memory response speed, overall performance may be increased by programming the CLNF bits to values 00 or 01.

For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss address is accessed first followed by the remaining three longwords that are accessed by incrementing the longword address in a modulo-16 fashion as shown below:

if miss address[3:2] = 00

fetch sequence = 0x0, 0x4, 0x8, 0xC

if miss address[3:2] = 01

fetch sequence = 0x4, 0x8, 0xC, 0x0

if miss address[3:2] = 10

fetch sequence = 0x8, 0xC, 0x0, 0x4

if miss address[3:2] = 11

fetch sequence = 0xC, 0x0, 0x4, 0x8

After an external fetch has been initiated and the data is loaded into the line-fill buffer, the cache maintains a special most-recently-used indicator that tracks the contents of the associated line-fill buffer versus its corresponding cache location. At the time of the miss, the hardware indicator is set, marking the line-fill buffer as most recently used. If a subsequent access occurs to the cache location defined by bits [12:4] (or bits [11:4] for split configurations of the fill buffer address), the data in the cache memory array is now most recently used, so the hardware indicator is cleared. In all cases, the indicator defines whether the contents of the line-fill buffer or the memory data array are most recently used. At the time of the next cache miss, the contents of the line-fill buffer are written into the memory array if the entire line is present, and the line-fill buffer data is most recently used compared to the memory array.

Generally, longword references are used for sequential instruction fetches. If the processor branches to an odd word address, a word-sized instruction fetch is generated.

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For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts of non-cacheable references under control of CACR[CEIB]. With this bit set, a non-cacheable instruction fetch is processed, as defined by

Table 5-7

. For this condition, the line-fill buffer is loaded and subsequent references can hit in the buffer, but the data is never loaded into the memory array.

Table 5-7

shows the relationship between CACR bits CENB and CEIB and the type of instruction fetch.

Table 5-7. Instruction Cache Operation as Defined by CACR

CACR

[CENB]

CACR

[CEIB]

0 0

Type of

Instruction Fetch

Description

N/A Cache is completely disabled; all instruction fetches are word or longword in size.

All instruction fetches are word or longword in size N/A

Cacheable Fetch size is defined by

Table 5-6

and contents of the line-fill buffer can be written into the memory array

Non-cacheable All instruction fetches are word or longword in size, and not loaded into the line-fill buffer

Non-cacheable Instruction fetch size is defined by

Table 5-6 and

loaded into the line-fill buffer, but are never written into the memory array.

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Chapter 6 Static RAM (SRAM)

6.1 Introduction

This chapter describes the on-chip static RAM (SRAM) implementation, including general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM.

6.1.1 Overview

The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. The location of the memory block can be specified to any 0-modulo-16K address within the

256-Mbyte address space (0x8000_0000 – 0x8FFF_FFFF). The memory is ideal for storing critical code or data structures or for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can service processor-initiated accesses or memory-referencing commands from the debug module.

Depending on configuration information, processor references may be sent to the cache and the SRAM block simultaneously. If the reference maps into the region defined by the SRAM, the SRAM provides the data back to the processor, and the cache data is discarded. Accesses from the SRAM module are not cached.

The SRAM is dual-ported to provide access for any of the bus masters via the SRAM backdoor on the crossbar switch. The SRAM is partitioned into two physical memory arrays to allow simultaneous access to arrays by the processor core and another bus master. For more information on arbitration between

multiple masters accessing the SRAM, see Chapter 11, “System Control Module (SCM) .

”

6.1.2 Features

The major features includes:

• One 16 Kbyte SRAM

• Single-cycle access

• Physically located on the processor's high-speed local bus

• Memory location programmable on any 0-modulo-16 Kbyte address

• Byte, word, and longword address capabilities

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6.2 Memory Map/Register Description

The SRAM programming model shown in

Table 6-1

includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management.

Table 6-1. SRAM Programming Model

Rc[11:0]

Register

Width

(bits)

Access Reset Value

Written w/ MOVEC

Section/Page

Supervisor Access Only Registers

0xC05 RAM Base Address Register (RAMBAR) 32 R/W See Section Yes

6.2.1/6-2

The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more

information see Chapter 26, “Debug Module.”

6.2.1 SRAM Base Address Register (RAMBAR)

The configuration information in the SRAM base-address register (RAMBAR) controls the operation of the SRAM module.

• The RAMBAR holds the SRAM base address. The MOVEC instruction provides write-only access to this register.

• The RAMBAR can be read or written from the debug module.

• All undefined bits in the register are reserved. These bits are ignored during writes to the

RAMBAR and return zeroes when read from the debug module.

• A reset clears the RAMBAR’s priority, backdoor write-protect, and valid bits, and sets the backdoor enable bit. This enables the backdoor port and invalidates the processor port to the

SRAM (The RAMBAR must be initialized before the core can access the SRAM.) All other bits are unaffected.

NOTE

The only applicable address ranges for the SRAM module’s base address are

0x8000_0000 – 0x8FFF_C000. The adress must be 0-modulo-16 K. Set the

RAMBAR register appropriately.

By default, the RAMBAR is invalid, but the backdoor is enabled. In this state, any core accesses to the SRAM are routed through the backdoor.

Therefore, the SRAM is accessible by the core, but it does not have a single-cycle access time. To ensure that the core has single-cycle access to the SRAM, set the RAMBAR[V] bit.

Any access within the memory range allocated for the on-chip SRAM

(0x8000_0000-0x8FFF_FFFF) hits in the SRAM even if the address is beyond the defined size for the SRAM. This creates address aliasing for the on-chip SRAM memory. For example, writes to addresses 0x8000_0000 and 0x8000_4000 modify the same memory location. System software should ensure SRAM address pointers do not exceed the SRAM size to prevent unwanted overwriting of SRAM.

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The RAMBAR contains several control fields. These fields are shown in

Figure 6-1

Rc[11:0]: 0x0C05 (RAMBAR) Access: User write-only

Debug read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12

0 0

11 10 9 8

PRIU PRIL BDE WP

Reset U U U U U U U U U U U U U U U U U U 0 0 0 0

6 5 4 3 2 1 0

BWP C/I SC SD UC UD V

1 U 0 0 U U U U U 0

Figure 6-1. SRAM Base Address Register (RAMBAR)

Field

31–14

13–12

11–10

PRIU

PRIL

BDE

BWP

Table 6-2. RAMBAR Field Descriptions

Description

Base Address. Defines the 0-modulo-16K base address of the SRAM module. By programming this field, the SRAM may be located on any 16-Kbyte boundary within the processor’s 256-Mbyte address space. For proper operation, the base address must be set to between 0x8000_0000 and 0x8FFF_C000.

Reserved, must be cleared.

Priority Bit. PRIU determines if the SRAM backdoor or CPU has priority in the upper 8K bank of memory.

PRIL determines if the SRAM backdoor or CPU has priority in the lower 8K bank of memory. If a bit is set, the CPU has priority. If a bit is cleared, the SRAM backdoor has priority. Priority is determined according to the following table:

PRIU,PRIL

Upper Bank Priority

SRAM Backdoor

CPU

Lower Bank Priority

SRAM Backdoor

CPU

SRAM Backdoor

CPU

Note: The recommended setting (maximum performance) for the priority bits is 00.

Backdoor Enable. Allows access by non-core bus masters via the SRAM backdoor on the crossbar switch

0 Non-core crossbar switch master access to memory is disabled.

1 Non-core crossbar switch master access to memory is enabled.

Write Protect. Allows only read accesses to the SRAM. When this bit is set, any attempted write access from the core generates an access error exception to the ColdFire processor core.

0 Allows core reaought d and write accesses to the SRAM module

1 Allows only core read accesses to the SRAM module

Note: This bit does not affect non-core write accesses.

Reserved, must be cleared.

Backdoor Write Protect. Allows only read accesses from the non-core bus masters. When this bit is set, any attempted write access from the non-core bus masters on the backdoor terminates the bus transfer with an access error.

0 Allows read and write accesses to the SRAM module from non-core masters.

1 Allows only read accesses to the SRAM module from non-core masters.

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Table 6-2. RAMBAR Field Descriptions (continued)

Field Description

5–1

C/I, SC, SD, UC,

Address Space Masks (ASn). These five bit fields allow types of accesses to be masked or inhibited from accessing the SRAM module. The address space mask bits are:

C/I = CPU space/interrupt acknowledge cycle mask

SC = Supervisor code address space mask

SD = Supervisor data address space mask

UC = User code address space mask

UD = User data address space mask

For each address space bit:

0 An access to the SRAM module can occur for this address space

1 Disable this address space from the SRAM module. If a reference using this address space is made, it is inhibited from accessing the SRAM module and is processed like any other non-SRAM reference.

These bits do not affect accesses by non-core bus masters using the SRAM backdoor port in any manner.

These bits are useful for power management as detailed in Section 6.3.2, “Power Management.”

In most applications, the C/I bit is set

Valid. When set, this bit enables the SRAM module; otherwise, the module is disabled. A hardware reset clears this bit.

0 Processor accesses of the SRAM are masked

1 Processor accesses of the SRAM are enabled

6.3 Initialization/Application Information

After a hardware reset, the SRAM module contents are undefined. The valid bit of the RAMBAR is cleared, disabling the processor port into the memory. RAMBAR[BDE] is set, enabling the system backdoor port into the memory. If the SRAM requires initialization with instructions or data, perform the following steps:

1. Load the RAMBAR, mapping the SRAM module to the desired location within the address space.

2. Read the source data and write it to the SRAM. Various instructions support this function, including memory-to-memory move instructions, or the MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this opcode generally provides maximum performance.

3. After the data loads into the SRAM, it may be appropriate to load a revised value into the

RAMBAR with a new set of attributes. These attributes consist of the write-protect and address space mask fields.

The ColdFire processor or an external debugger using the debug module can perform these initialization functions.

6.3.1 SRAM Initialization Code

The following code segment describes how to initialize the SRAM. The code sets the base address of the

SRAM at 0x8000_0000 and initializes the SRAM to zeros.

RAMBASE EQU 0x0000000 ;set this variable to 0x0000000

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move.l #RAMBASE+RAMVALID,D0 movec.l

D0, RAMBAR

;load RAMBASE + valid bit into D0.

;load RAMBAR and enable SRAM

The following loop initializes the entire SRAM to zero: lea.l RAMBASE,A0 move.l

#4096,D0

;load pointer to SRAM

;load loop counter into D0 (SRAM size/4)

SRAM_INIT_LOOP: clr.l (A0)+ clr.l (A0)+ clr.l (A0)+ clr.l (A0)+ subq.l #4,D0 bne.b SRAM_INIT_LOOP

;clear 4 bytes of SRAM

;decrement loop counter

;if done, then exit; else continue looping

6.3.2 Power Management

As noted previously, depending on the RAMBAR-defined configuration, instruction fetch and operand read accesses may be sent to the SRAM and cache simultaneously. If the access maps to the SRAM module, it sources the read data and the cache access is discarded. If the SRAM is used only for data operands, setting the ASn bits associated with instruction fetches can decrease power dissipation.

Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power dissipation.

Table 6-3

shows examples of typical RAMBAR settings.

Table 6-3. Typical RAMBAR Setting Examples

Data Contained in SRAM

Instruction Only

Data Only

Instructions and Data

RAMBAR[7:0]

0x2B

0x35

0x21

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Chapter 7 Clock Module

7.1 Introduction

The clock module allows the device to be configured for one of several clocking methods. Clocking modes include internal phase-locked loop (PLL) clocking with an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device directly. The clock module contains:

• Crystal amplifier and oscillator (OSC)

• Dithering phase-locked loop (PLL)

• Status and control registers

• Control logic

NOTE

Throughout this manual, f sys the internal bus frequency.

refers to the core frequency and f sys/2

refers to

Figure 7-1

is a high level representation of the clock connections. The exact functionality of the blocks is not illustrated (e.g. clocks to the SDRAMC are disabled when the device is in limp mode, and the clocks to individual modules may be disabled via the peripheral power management registers).

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Clock Module

PLL

D2 (when RCON

is asserted)

1 0

XTAL

EXTAL

Oscillator

Clock Module

MISCCR[LPDIV]

D6 (when RCON

is asserted) and

MISCCR[LIMP]

1 f sys

÷ 2

Figure 7-1. Device Clock Connections

7.1.1 Block Diagram

Figure 7-2

shows a block diagram of the clock module.

Divide-by-4 Phase/Frequency

Detector (PFD)

Loop Filter

ColdFire V2 Core

SRAM

BDM eDMA

SDRAMC

FlexBus

FEC

Watchdog Timer

PIT

DMA Timers

QSPI

UART

GPIO

Voltage-Controlled

Oscillator (VCO)

VCO Clock

Frequency

Feedback Divider

(MFD)

Modulator

Divider/Counter

Output Dividers

EXTAL

XTAL

OSC

Bus

Interface

Reset Config

Signals

PLL

Registers

Figure 7-2. Clock Module Diagram

Output Clocks

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7.1.2 Features

Features of the clock module include the following:

• 16-MHz reference crystal oscillator

• Voltage controlled oscillator range from 350 MHz to 540 MHz, resulting in a core frequency

(f vco

÷ 3 (or f vco

÷ 4)) of 87.5 MHz to 166.67 MHz (maximum rated for device)

• Programmable dithering

• Support for low-power modes

• Direct clocking of system by input clock, bypassing the PLL

• Loss-of-lock reset

7.1.3 Modes of Operation

The PLL operational mode must be configured during reset. The reset configuration pins must be driven to the appropriate state for the desired mode from the time RSTOUT asserts until it negates. Refer to

Chapter 9, “Chip Configuration Module (CCM).”

The clock module can operate in normal PLL mode with crystal reference, normal PLL mode with external reference, and input clock limp mode.

7.1.3.1

Normal PLL Mode with Crystal Reference

In normal mode with a crystal reference, the PLL receives an input clock frequency from the crystal oscillator circuit and multiplies the frequency to create the PLL output clock. It can synthesize frequencies ranging from 22x to 33.75x the input frequency. The user must supply a crystal oscillator that is within the appropriate input frequency range, the crystal manufacturer’s recommended external support circuitry, and short signal route from the device to the crystal. In normal mode, the PLL can generate a dithered clock or a non-dithered clock (locked on a single frequency). The dithering deviation, dither modulation frequency, and whether the PLL is modulating or not can be programmed by writing to the PLL registers through the bus interface.

7.1.3.2

Normal PLL Mode with External Reference

Same as

Section 7.1.3.1, “Normal PLL Mode with Crystal Reference”

except EXTAL is driven by an external clock generator rather than a crystal oscillator. However, the input frequency range is the same as the crystal reference. To enter normal mode with external clock generator reference, the PLL configuration

must be set at reset by overriding the default reset configuration. See Chapter 9, “Chip Configuration

Module (CCM),”

for details on setting the device for external reference.

7.1.3.3

Input Clock (Limp) Mode

Through the use of RCON, the device may be booted into a low-frequency limp mode, in which the PLL is bypassed and the device runs from a factor of the input clock (EXTAL). In this mode, EXTAL feeds a

5-bit programmable counter that divides the input clock by 2

, where n is the value of the programmable counter field, MISCCR[LPDIV]. For more information on programming the divider, see

Chapter 8,

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“Power Management.”

The programmed value of the divider may be changed without glitches or otherwise negative affects to the system.

While in this mode, the PLL is placed in bypass mode to reduce overall system power consumption. A 2:1 ratio is maintained between the core and the primary bus clock. Because they do not function at speeds as low as the minimum input clock frequency, the SDRAM controller and FEC are not functional in limp mode.

When switching from LIMP mode to normal functional mode, you must ensure that any peripheral transactions in progress (e.g. Ethernet frame reception/transmission) are allowed to complete to avoid data loss or corruption.

Limp mode may also be entered and exited from by writing to the MISCCR[LIMP] bit. This is useful because it places the PLL in a state where the multiplication factor (PFMDR) can be altered. Entering limp mode also requires a special procedure with the SDRAM module. As noted above the SDRAM controller is disabled in limp mode, so two critical steps must be followed before setting the MISCCR[LIMP] bit.

1. Code execution must be transferred to another memory resource. Primary options are whatever memory device is attached to the FlexBus boot chip select or on-chip SRAM (but not the CPU cache, as it may have to be flushed upon limp mode entrance or exit).

2. The SDRAM controller must be placed in self-refresh mode to avoid data loss while the SDRAMC is shut down.

7.1.3.4

Low-power Mode Operation

This subsection describes the operation of the clock module in low-power and halted modes of operation.

Low-power modes are described in

Chapter 8, “Power Management.”

Table 7-1

shows the clock module operation in low-power modes.

Table 7-1. Clock Module Operation in Low-power Modes

Low-power Mode

Wait

Clock Operation

Clocks sent to peripheral modules only

Doze

Stop

Halted

Clocks sent to peripheral modules only

All system clocks disabled

Normal

Mode Exit

Exit not caused by clock module, but normal clocking resumes upon mode exit

Exit not caused by clock module, but clock sources are re-enabled and normal clocking resumes upon mode exit

Exit not caused by clock module

In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the core, and

SRAM are stopped. Each module can disable its clock locally at the module level.

In stop mode, all system clocks are disabled. There are several options for enabling or disabling the PLL or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time.

The PLL can be disabled in stop mode, but requires a wakeup period before it can relock. The oscillator can also be disabled during stop mode, but requires a wakeup period to restart.

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When the PLL is enabled in stop mode (LPCR[STPMD] = 00), the external FB_CLK signal can support

systems using FB_CLK as the clock source. See Section 8.2.5, “Low-Power Control Register (LPCR),”

for more information about operating the PLL in stop mode.

There is also a fast wakeup option for quickly enabling the system clocks during stop recovery

(LPCR[FWKUP]). This eliminates the wakeup recovery time but at the risk of sending a potentially unstable clock to the system.

7.2 Memory Map/Register Definition

The PLL module programming model consists of the following registers:

Table 7-2. PLL Memory Map

Address Register

0xFC09_0000 PLL Output Divider Register (PODR)

0xFC09_0002 PLL Control Register (PCR)

0xFC09_0004 PLL Modulation Divider Register (PMDR)

0xFC09_0006 PLL Feedback Divider Register (PFDR)

With default reset configuration (RCON is negated).

Width

(bits)

Access Reset Value Section/Page

8 R/W 0x36

7.2.1/7-5

R/W

0x00

0x42

7.2.2/7-6

7.2.3/7-7

7.2.4/7-8

7.2.1 PLL Output Divider Register (PODR)

The PODR register controls the output divider for generating the core and bus clocks. The value of this register may be 0x48 or 0x36 and writing any other value to this register results in unpredictable behaivor.

Address: 0xFC09_0000 (PODR) Access:User read/write

7 6 5 4 3 2 1 0

CPUDIV BUSDIV

Reset: See Note See Note

Note: Default value determined by reset configuration. See Chapter 9, “Chip Configuration Module (CCM),”

for more information. For the default reset configuration (RCON negated), the reset value is 0x48. If

RCON and D1 is asserted at reset, the reset value of PODR is 0x36.

Figure 7-3. PLL Output Divider Register (PODR)

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Clock Module

Table 7-3. PODR Field Descriptions

Field Description

7–4

CPUDIV

Divider for generating the core frequency. See BUSDIV for a table of possible values.

3–0

BUSDIV

Divider for generating the internal bus frequency.

Value Core Clock Bus Clock

0011

0100

0110

1000

Else

VCO/3

VCO/4

Reserved

VCO/6

VCO/8

Reserved

7.2.2 PLL Control Register (PCR)

Address: 0xFC09_0002 (PCR)

7 6

0 R

Reset:

DITHEN

0 0 0 0

Figure 7-4. PLL Control Register (PCR)

Table 7-4. PCR Field Descriptions

Description Field

DITHEN

Dithering enable bit.

0 Dithering disabled.

1 Dithering enabled.

Access:User read/write

1 0

DITHDEV

0 0

7-6

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Clock Module

Table 7-4. PCR Field Descriptions (continued)

Field Description

6–3 Reserved, should be cleared.

2–0

DITHDEV

Dither Deviation. The dither deviation settings are target percentages based on simulation. The actual percentages observed are slightly larger than these targets. See

Section 7.3.2, “Dithering Waveform Definition”

for more information.

Deviation = -0.75% - (DITHDEV

0.75%)

DITHDEV Deviation

000

001

010

011

100

101

110

111

- 0.75%

- 1.00%

- 1.25%

- 1.50%

- 1.75%

- 2.00%

- 2.25%

- 2.50%

Note: This field should only be written when dithering mode is disabled (PCR[DITHEN] = 0). Else, unpredictable PLL operation results.

7.2.3 PLL Modulation Divider Register (PMDR)

Address: 0xFC09_0004 (PMDR)

7 6

Reset: 0

5 4

MODDIV

3 2

0 0 0 0 0

Figure 7-5. PLL Modulation Divider Register (PMDR)

Table 7-5. PMDR Field Descriptions

Access: User read/write

1 0

0 0

Field Description

7–0

MODDIV

Dither modulation divider.

Dither Modulation Frequency = Input Frequency / (MODDIV

32)

A dither modulation frequency greater than 105 kHz or less than 9.95 kHz is invalid. For example, for a 16 MHz input frequency, MODDIV may be programmed between 5 (100 kHz) and 50 (10 kHz). Programming MODDIV outside the specified range results in unpredictable PLL operation.

Note: This field should only be written when dithering mode is disabled (PCR[DITHEN] = 0). Else, unpredictable PLL operation results.

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7.2.4 PLL Feedback Divider Register (PFDR)

Field

7–0

MFD

Address: 0xFC09_0006 (PFDR) Access: User read/write

7 6 5 4 3 2 1 0

MFD

Reset: See Note See Note See Note See Note See Note See Note See Note See Note

Note: Reset value determined by reset configuration. See

Chapter 9, “Chip Configuration Module (CCM),”

for more information. For the default reset configuration (RCON negated), the reset value is 0x58. If RCON and D1 is asserted at reset, the reset value of PFDR is 0x7D.

Figure 7-6. PLL Feedback Divider Register (PFDR)

Table 7-6. PFDR Field Descriptions

Description

The MFD bits control the value of the divider in the PLL feedback loop. The value specified by the MFD bits establish

the multiplication factor applied to the reference frequency. See Section 7.3.3, “PLL Frequency Multiplication Factor

Select”

for more details.

0x58 88

0x59 89

0x5A 90

...

0x86 134

0x87 135

Else Reserved

Note: The MFD bits may only be written when the device is in limp mode (MISCCR[LIMP] = 1).

7.3 Functional Description

This subsection provides a functional description of the clock module.

7.3.1 PLL Dithered and Non-Dithered Operation

The PLL is capable of generating output clocks with a frequency that modulates in a triangular waveform with a specified percentage frequency deviation and a specified dither modulation frequency. This modulation of the output clock is called dithered operation. When the PLL operates at a fixed frequency, this operation is known as non-dithered operation. The selection of dithered or non-dithered operation is controlled by the PCR[DITHEN] bit. The percent frequency deviation and dither modulation frequency

are also controlled by the PCR and PMDR registers, whose operation is described in Section 7.3.2,

“Dithering Waveform Definition.”

After reset, dithering is disabled. After the PLL has locked (indicated by the MISCCR[PLLLOCK] bit described in

Section 8.2.6, “Miscellaneous Control Register (MISCCR)”

), the PLL may be changed from non-dithered operation to dithered operation by writing to the PCR. After the PCR[DITHEN] bit has been set, the PLL synchronizes the new value with the VCO clock domain. Then the transition from non-dithered operation to dithered operation takes place such that the PLL output clocks remain glitch-free. However, the dithering waveform and deviation percentages are not guaranteed to meet

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specifications until two modulation periods have passed after the time of the write to the PCR register.

During the transition the frequency of the PLL output clocks does not exceed 10% of the respective non-dithered frequency.

The PLL may also be changed from dithered operation to non-dithered operation by clearing the

PCR[DITHEN] bit. After this occurs, the PLL synchronizes the new value with the VCO clock domain.

Then, the transition from dithered operation to non-dithered operation takes place such that PLL output clocks remain glitch-free. However, the frequency of the PLL output clocks are not guaranteed to be completely stable until one modulation period has passed after the time of the write to the PCR. During the transition the frequency of the PLL output clocks does not exceed 10% of the respective non-dithered frequency.

Because the transition between dithered and non-dithered operation (and vice-versa) takes a period of time to change, the PCR may not be written back-to-back without waiting two modulation periods between writes.

NOTE

Failure to wait two modulation periods between writes to the PCR results in unpredictable PLL operation.

7.3.2 Dithering Waveform Definition

The dithering waveform created by the changes in the frequency of the PLL output clocks is defined by the percent frequency deviation and dither modulation frequency. The definitions of the percent frequency deviation (or dithering deviation) and the modulation period (which is the inverse of the dither modulation frequency) are shown in

Figure 7-7

. The dithering deviation is controlled by PCR[DITHDEV] field, while the dither modulation frequency is controlled by the PMDR[MODDIV] field.

Modulation period

Frequency of a PLL output clock

Percent Frequency

Deviation

Time

Figure 7-7. Ideal Triangular Dithering Waveform

After reset, the PCR and PMDR registers are cleared, disabling dithering. After reset has been de-asserted and the PLL has locked (indicated by the MISCCR[PLLLOCK] bit), the dithering waveform definition may be changed by writing to the PCR[DITHDEV] field and the PMDR register. However, the

PCR[DITHDEV] field and PMDR register may only be written to when the PLL is in non-dithered operation (i.e. the PCR[DITHEN] bit must be cleared).

NOTE

Writing to the PCR[DITHDEV] field or the PMDR during dithering operation results in unpredictable PLL operation.

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The dither deviation can be programmed to be between -0.75% of the non-dithered frequency up to -2.50% of the non-dithered frequency in steps of 0.25%.

NOTE

The dither deviation settings in the PCR[DITHDEV] field are target percentages based on simulation. The actual percentages achieved may be numerically different than the percentages listed in the specification; however, the actual percentages achieved are in proportion to each other and are stable within ±10% across process, voltage, and temperature conditions.

The dither modulation frequency can be programmed to be between approximately 10kHz and 100kHz.

Because the dither modulation frequency is determined as a division of the input frequency, the dither modulation frequency is given by the following equation:

Dither Modulation Frequency =

Input Frequency

PMDR MODDIV

NOTE

PMDR[MODDIV] field values that result in a dither modulation frequency greater than 105kHz or less than 9.95kHz are invalid and result in unpredictable PLL operation.

Eqn. 7-1

7.3.3 PLL Frequency Multiplication Factor Select

The frequency multiplication factor of the PLL is defined by the feedback divider in the following equation: f sys

= f ref

⎛

⎝

---------------------------------------------------

4 PODR[CPUDIV]

⎞

⎠

Eqn. 7-2

where f sys

is the core frequency. The allowable range of values for the PFDR is 88 to 135, resulting in a frequency multiplication factor range of 7.33 to 11.25 times the input reference frequency (typically

16 MHz).

The PFDR can only be modified while the device is in limp mode, which is entered by setting the

MISCCR[LIMP] bit. After the PFDR register has been changed, re-enter normal mode by clearing the

MISCCR[LIMP] bit. The PLL then begins to acquire lock accordingly on the new frequency.

7.3.4 System Clock Modes

The system clock source is determined during reset. By default the PLL is placed in crystal reference mode and generates a core/bus frequency of 88/44 MHz. This default mode can be overridden by asserting the

RCON pin. See Chapter 9, “Chip Configuration Module (CCM),”

for more information on overriding the default configuration during reset.

Table 7-7

shows the clock-out frequency to clock-in frequency relationships for the possible system clock modes. Refer to

Section 7.1.3, “Modes of Operation”

for details on each mode.

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System Clock Mode

Table 7-7. Clock Out and Clock In Relationships

PLL Options

Cross-Reference

Normal PLL clock mode RCON negated (default): f sys

= f ref

⎛

⎝

----------------

⎠

⎞

RCON and D1 asserted:

Section 7.1.3.1, “Normal PLL Mode with

Crystal Reference”

and

Section 7.1.3.2,

“Normal PLL Mode with External Reference”

f sys

= f ref

⎛

⎝

----------------

⎠

⎞

Limp mode f sys

= f

-----------------------------------------

MISCCR LPDIV

]

1 f ref

= input reference frequency = 16 MHz

PFDR ranges from 88 to 135

MISCCR[LPDIV] ranges from 0 to 15

Section 7.1.3.3, “Input Clock (Limp) Mode”

7.3.5 Clock Operation During Reset

This section describes the reset operation of the PLL. Power-on reset and normal reset are described.

7.3.5.1

Power-On Reset (POR)

After V

DDPLL

and the input clock are within specification, the PLL is held in reset for at least 10 input clock cycles to initialize the PLL. The reset configuration signals are used to select the multiply factor of the PLL and the reset state of the PLL registers. While in reset, the PLL input clock is output to the device.

After RESET is de-asserted, PLL output clocks are generated; however, until the MISCCR[PLLLOCK] bit is set the PLL output clock frequencies are not stable and not within specification. The

MISCCR[PLLLOCK] bit is set after RESET has negated for a minimum of 1 ms. When this bit is set, the

PLL is in frequency lock.

7.3.5.2

External Reset

When RESET is asserted, the PLL input clock is output to the device and the PLL does not begin acquiring lock until RESET is negated. The MISCCR[PLLLOCK] bit is cleared and remains cleared while the PLL is acquiring lock. This bit is set after the PLL lock period of 1 ms has passed.

CAUTION

When running in an unlocked state, the clocks generated by the PLL are not guaranteed to be stable and may exceed the maximum specified frequency of the device.

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Chapter 8 Power Management

8.1 Introduction

This chapter explains the low-power operation of the device.

8.1.1 Features

The following features support low-power operation:

• Four modes of operation: run, wait, doze, and stop

• Ability to shut down most peripherals independently

• Ability to shut down clocks to most peripherals independently

• Ability to run the device in low-frequency limp mode

• Ability to shut down the external FB_CLK pin

8.2 Memory Map/Register Definition

The power management programming model consists of registers from the SCM and CCM memory space, as shown below:

Table 8-1. Power Management Memory Map

Address Register

Width

(bits)

Access Reset Value Section/Page

Supervisor Access Only Registers

0xFC04_0013 Wakeup Control Register (WCR)

0xFC04_002C Peripheral Power Management Set Register 0 (PPMSR0)

0xFC04_002D Peripheral Power Management Clear Register 0 (PPMCR0)

0xFC04_0030 Peripheral Power Management High Register 0 (PPMHR0)

R/W

0x00

W 0x00

R/W 0x0000_0000

0xFC04_0034 Peripheral Power Management Low Register 0 (PPMLR0)

0xFC0A_0007 Low-Power Control Register (LPCR)

R/W

0xFC0A_0010 Miscellaneous Control Register (MISCCR) 16 R/W

User access to supervisor only address locations have no effect and result in a bus error

0x0000_0000

0x00

See Section

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8.2.1 Wake-up Control Register

Implementation of low-power stop mode and exit from a low-power mode via an interrupt require communication between the core and logic associated with the interrupt controller. The WCR enables entry into low-power modes, and includes the setting of the interrupt level needed to exit a low-power mode.

NOTE

The setting of the low-power mode select field, LPCR[LPMD], determines which low-power mode the device enters when a STOP instruction is issued.

The following sequence of operations is generally needed to enable this functionality:

1. The WCR register is programmed, setting the ENBWCR bit and the desired interrupt priority level.

2. At the appropriate time, the processor executes the privileged STOP instruction. After the processor has stopped execution, it asserts a specific processor status (PST) encoding. Issuing the

STOP instruction when the WCR[ENBWCR] bit is set causes the SCM to enter the mode specified in LPCR[LPMD].

3. The entry into a low-power mode is processed by the low-power mode control logic, and the appropriate clocks (usually those related to the high-speed processor core) are disabled.

4. After entering the low-power mode, the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests. The device waits for an event to generate an interrupt request with a priority level greater than the value programmed in WCR[PRILVL].

5. After an appropriately high interrupt request level arrives, the interrupt controller signals its presence, and the SCM responds by asserting the request to exit low-power mode.

6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.

7. With the processor clocks enabled, the core processes the pending interrupt request.

Address: 0xFC04_0013 (WCR)

Reset:

ENBWCR

0 0 0 0

Figure 8-1. Wake-up Control Register (WCR)

Access: Supervisor read/write

1 0

PRILVL

0 0

Table 8-2. WCR Field Descriptions

Field Description

ENBWCR

Enable low-power mode entry. The mode entered is specified in LPCR[LPMD].

0 Low-power mode entry is disabled

1 Low-power mode entry is enabled.

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Table 8-2. WCR Field Descriptions (continued)

Field

6–3

2–0

PRILVL

Description

Reserved, should be cleared.

Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the low-power mode.

PRILVL

000

001

010

011

100

101

11x

Interrupt Level Needed to Exit Low-Power Mode

Any interrupt request exits low-power mode

Interrupt request levels [2-7] exit low-power mode

Interrupt request levels [3-7] exit low-power mode

Interrupt request levels [4-7] exit low-power mode

Interrupt request levels [5-7] exit low-power mode

Interrupt request levels [6-7] exit low-power mode

Interrupt request level [7] exits low-power mode

8.2.2 Peripheral Power Management Set Register (PPMSR0)

The PPMSR register provides a simple mechanism to set a given bit in the PPM{H,L}R registers to disable the clock for a given peripheral module without the need to perform a read-modify write on the PPMR.

The data value on a register write causes the corresponding bit in the PPM{H,L}R to be set. The SAMCD bit provides a global set function forcing the entire contents of the PPMR to be set, disabling all peripheral module clocks. Reads of these registers return all zeroes.

Address: 0xFC04_002C (PPMSR0)

Reset:

SAMCD

SMCD

Access: Supervisor Write-only

0 0 0 0

Figure 8-2. Peripheral Power Management Set Register (PPMSR0)

Table 8-3. PPMSR0 Field Descriptions

Field Description

5–0

SMCD

Reserved, should be cleared.

SAMCD

Set all module clock disables.

0 Set only those bits specified in the SMCD field

1 Set all bits in PPMRH and PPMRL, disabling all peripheral clocks

Set module clock disable. Set the corresponding bit in PPM{H,L}R, disabling the peripheral clock.

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8.2.3 Peripheral Power Management Clear Register (PPMCR)

The PPMCR register provides a simple mechanism to clear a given bit in the PPMHR & PPMLR registers, enabling the clock for a given peripheral module without the need to perform a read-modify write on the

PPMR. The data value on a register write causes the corresponding bit in the PPM{H,L}R to be clear. A value of 64 to 127 (setting the CAMCD bit) provides a global clear function forcing the entire contents of the PPMR to be clear, enabling all peripheral module clocks. Reads of these registers return all zeroes.

Address: 0xFC04_002D (PPMCR0)

Reset:

CAMCD

CMCD

Access: Supervisor Write-only

0 0 0 0 0

Figure 8-3. Peripheral Power Management Clear Register (PPMCR0)

Table 8-4. PPMCR0 Field Descriptions

Field Description

5–0

CMCD

Reserved, should be cleared.

CAMCD

Clear all module clock disables.

0 Clear only those bits specified in the CMCD field

1 Clear all bits in PPMRH and PPMRL, enabling all peripheral clocks

Clear module clock disable. Clear the corresponding bit in PPMR{H,L}, enabling the peripheral clock.

8.2.4 Peripheral Power Management Registers (PPMHR0 & PPMLR0)

The PPMR registers provide a bit map for controlling the generation of the peripheral clocks for each decoded address space. Recall each peripheral module is mapped into 16 kByte slots within the memory map. The PPMR registers provide a unique control bit for each of these address spaces that defines whether the module clock for the given space is enabled or disabled.

Because the operation of the crossbar switch and the system control module (SCM) are fundamental to the operation of the device, the clocks for these modules cannot be disabled.

The individual bits of the PPMR can be modified using a read-modify-write to this register directly or indirectly through writes to the PPMSR and PPMCR registers to set/clear individual bits.

8-4

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Power Management

Address: 0xFC04_0030 (PPMHR0)

R 0

Reset 0

R 0

Reset 0

10 9 8

CD42 CD41 CD40

Access: Supervisor read/write

0 0 0 0 0

4 3 2 1 0

CD36 CD35 CD34 CD33 CD32

0 0

Figure 8-4. Peripheral Power Management High Register (PPMHR0)

Slot Number

Table 8-5. PPMHR0[CDn] Assignments

CDn

CD32

CD33

CD34

CD35

CD36

CD40

CD41

CD42

Peripheral

PIT 0

PIT 1

Edge Port

On-chip Watchdog Timer

PLL

CCM, Reset Controller, Power Management

GPIO Module

SDRAM Controller

0 0 0

Address: 0xFC04_0034 (PPMLR0)

31 30 29 28

CD31 CD30 CD29 CD28

Reset 0 0 0 0

26 25 24 23 22 21

CD26 CD25 CD24 CD23 CD22 CD21

0 0 0 0 0 0

Access: Supervisor read/write

18 17

CD18 CD17

0 0 0 0 0

R 0

Reset 0

CD12

Slot Number

Table 8-6. PPMLR0[CDn] Assignments

CDn

CD2

CD12

CD17

Peripheral

FlexBus

FEC eDMA Controller

0 0 0 0 0 0 0 0 0 0 0 0

Figure 8-5. Peripheral Power Management Low Registers (PPMLR0)

CD2

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Table 8-6. PPMLR0[CDn] Assignments (continued)

Slot Number

CDn

CD18

CD21

CD22

CD23

CD24

CD25

CD26

CD28

CD29

CD30

CD31

Peripheral

Interrupt Controller

IACK

QSPI

UART0

UART1

UART2

DMA Timer 0

DMA Timer 1

DMA Timer 2

DMA Timer 3

Table 8-7. PPMHR & PPMLR Field Descriptions

Description Field

CDn Module slot n clock disable.

0 The clock for this module is enabled.

1 The clock for this module is disabled.

CAUTION

Extreme caution should be taken by the customer when setting

PPMR[CD40] to disable clocking of the CCM, reset controller, and power management modules. This may disable logic to reset the chip, disable the external bus monitor, and other logic contained within these blocks.

8.2.5 Low-Power Control Register (LPCR)

The LPCR register controls chip operation and module operation during low-power modes.

Address: 0xFC0A_0007 (LPCR)

7 6

Reset: 0

LPMD

FWKUP

STPMD

0 0 0 0 0

Figure 8-6. Low-Power Control Register (LPCR)

Access: Supervisor read/write

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Table 8-8. LPCR Field Descriptions

Field Description

7–6

LPMD

Low-power mode select. Used to select the low-power mode the chip enters after the ColdFire core executes the

STOP instruction. These bits must be written prior to instruction execution for them to take effect. The LPMD bits are readable and writable in all modes.

00 Run

01 Doze

10 Wait

11 Stop

Note: If LPCR[LPMD] is cleared, the device stops executing code upon issue of a STOP instruction. However, no clocks are disabled.

FWKUP

Fast wake-up. Determines whether the system clocks are enabled upon wake-up from stop mode. This bit must be written before execution of the STOP instruction for it to take effect.

0 System clocks enabled only when PLL is locked or operating normally.

1 System clocks enabled upon wake-up from stop mode, regardless of PLL lock status.

Note: Setting this bit is potentially dangerous and unreliable. The system may behave unpredictably when using an unlocked clock because the clock frequency could overshoot the maximum frequency of the device.

Note: If FWKUP is set before entering stop mode, it should not be cleared upon wake-up from stop mode until after the PLL has actually acquired lock. Lock status may be obtained by reading the MISCCR[PLLLOCK] bit.

FWKUP is not effective in limp mode because the PLL never locks in this mode. The system clocks are always enabled upon wake-up from stop mode, regardless of the value of FWKUP.

4–3

STPMD

FB_CLK stop mode bits. Controls the operation of the clocks, PLL, and oscillator in stop mode as shown below.

STPMD System Clocks

Disabled

FB_CLK

Enabled

Disabled

PLL

Enabled

Disabled

Oscillator

Enabled

Disabled

2–0 Reserved, should be cleared.

8.2.6 Miscellaneous Control Register (MISCCR)

The MISCCR provides clock source selection and configuration for internal clocks.

Address: 0xFC0A_0010 (MISCCR)

13 12

PLL

LOCK LIMP

Reset

0 0 1

See

Note

0 0 0 0 0 0 0

Note: Reset value depends upon chosen reset configuration (RCON[RLIMP]).

Figure 8-7. Miscellaneous Control Register (MISCCR)

Access: Supervisor read/write

3 2 1 0

0 0

LPDIV

0 0

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Table 8-9. MISCCR Field Descriptions

Field Description

15–14 Reserved, should be cleared.

PLLLOCK

PLL lock status.

0 PLL is not locked.

1 PLL is locked.

LIMP

Limp mode enable. Selects between the PLL and the low-power clock divider as the source of all system clocks.

0 Normal operation; PLL drives all internal clocks.

1 Limp mode; low-power clock divider drivers internal clocks.

Reserved, should be cleared.

11–4

3–0

LPDIV

Low power divider. Specifies the limp mode divide value used to produce the clock for the ColdFire core, bus, and other system clocks. A 2:1 ratio is maintained between the core and the internal bus. This field is used only when

LIMP is set, and ignored otherwise.

Limp mode clock = Oscillator clock / 2

LPDIV

Note: When LPDIV is 0 (divide-by-1), the internal bus clock and FB_CLK will not have a 50/50 duty cycle.

8.3 Functional Description

The functions and characteristics of the low-power modes, and how each module is affected by, or affects these modes are discussed in this section.

8.3.1 Peripheral Shut Down

All peripherals, except for the SCM and crossbar switch, may have their input clocks individually removed by software to reduce power consumption. See

Section 8.2.4, “Peripheral Power Management Registers

(PPMHR0 & PPMLR0)”

for more information. A peripheral may be disabled at any time and remains disabled during any low-power mode of operation.

8.3.2 Limp mode

The device may also be booted into a low-frequency limp mode, in which the PLL is bypassed and the device runs from a factor of the input clock (EXTAL). In this mode, EXTAL feeds a 5-bit programmable counter that divides the input clock by 2

, where n is the value of the programmable counter field,

MISCCR[LPDIV]. The programmed value of the divider may be changed without glitches or otherwise negative affects to the system. While in this mode, the PLL is placed in bypass mode to reduce overall system power consumption.

Limp mode may also be entered and exited from by writing to the MISCCR[LIMP] bit.

While in this mode a 2:1 ratio is maintained between the core and the primary bus clock. Because they do not function at speeds as low as the minimum input clock frequency, the SDRAM controller, and FEC are not functional in limp mode.

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8.3.3 Low-Power Modes

The system enters a low-power mode by executing a STOP instruction. The low-power mode the device actually enters (stop, wait, or doze) depends on the setting of LPCR[LPMD]. Entry into any of these modes idles the CPU with no cycles active, powers down the system, and stops all internal clocks appropriately.

During stop mode, the system clock is stopped low.

A wake-up event is required to exit a low-power mode and return to run mode. Wake-up events consist of any of these conditions:

• Any type of reset

• Any valid, enabled interrupt request

Exiting from low power mode via an interrupt request requires:

• An interrupt request whose priority is higher than the value programmed in the WCR[PRILVL].

• An interrupt request whose priority is higher than the value programmed in the interrupt priority mask (I) field of the core’s status register.

• An interrupt request from a source which is not masked in the interrupt controller’s interrupt mask register.

• An interrupt request which has been enabled at the module of the interrupt’s origin.

8.3.3.1

Run Mode

Run mode is the normal system operating mode. Current consumption in this mode is related directly to the system clock frequency.

8.3.3.2

Wait Mode

Wait mode is intended to be used to stop only the CPU and memory clocks until a wake-up event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU to exit from wait mode.

8.3.3.3

Doze Mode

Doze mode affects the CPU in the same manner as wait mode, except that some peripherals define individual operational characteristics in doze mode. Peripherals which continue to run and have the capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode.

Peripherals that are stopped restart operation on exit from doze mode as defined for each peripheral.

8.3.3.4

Stop Mode

Stop mode affects the CPU in the same manner as the wait and doze modes, except that all clocks to the system are stopped and the peripherals cease operation.

Stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation.

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The following subsections specify the operation of each module while in and when exiting low-power modes.

NOTE

Entering stop mode disables the SDRAMC including the refresh counter. If

SDRAM is used, then code is required to ensure proper entry and exit from stop mode. See

Chapter 18, “SDRAM Controller (SDRAMC),”

for more information.

8.3.4 Peripheral Behavior in Low-Power Modes

8.3.4.1

ColdFire Core

The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any low-power mode.

8.3.4.2

Internal SRAM

The SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power mode.

8.3.4.3

Clock Module

In wait and doze modes, the clocks to the CPU and SRAM is stopped and the system clocks to the peripherals are enabled. Each module may disable the module clocks locally at the module level or the module clocks may be individually disabled by the PPMR registers (refer to

Section 8.2.4, “Peripheral

Power Management Registers (PPMHR0 & PPMLR0)”

). In stop mode, all clocks to the system are stopped.

There are several options for enabling or disabling the PLL or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time. The PLL can be disabled in stop mode, but requires a wakeup period before it can relock. The oscillator can also be disabled during stop mode, but requires a wakeup period to restart.

When the PLL is enabled in stop mode (LPCR[STPMD] = 00), the external FB_CLK signal can support

systems using FB_CLK as the clock source. See Section 8.2.5, “Low-Power Control Register (LPCR),”

for more information about operating the PLL in stop mode.

There is also a fast wakeup option for quickly enabling the system clocks during stop recovery

(LPCR[FWKUP]). This eliminates the wakeup recovery time but at the risk of sending a potentially

unstable clock to the system. This is also explained in Section 8.2.5, “Low-Power Control Register

(LPCR).”

8.3.4.4

Chip Configuration Module

The chip configuration module is unaffected by entry into a low-power mode. If low-power mode is exited by a reset, chip configuration may be executed if configured to do so.

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8.3.4.5

Reset Controller

A power-on reset (POR) always causes a chip reset and exit from any low-power mode.

In wait and doze modes, asserting the external RESET pin for at least four clocks causes an external reset that resets the chip and exit any low-power modes.

In stop mode, the RESET pin synchronization is disabled and asserting the external RESET pin asynchronously generates an internal reset and exit any low-power modes. Registers lose current values and must be reconfigured from reset state if needed.

If the core or on-chip watchdog timer remains enabled during wait or doze modes, then a watchdog timer timeout may generate a reset to exit these low-power modes.

When the CPU is inactive, a software reset cannot be generated to exit any low-power mode.

8.3.4.6

System Control Module (SCM)

The SCM’s core watchdog timer can bring the device out of all low-power modes except stop mode. In stop mode, all clocks stop, and the core watchdog timer does not operate.

When enabled, the core watchdog can bring the device out of low-power mode in one of two ways.

Depending on the setting of the CWCR[CWRI] field, a core watchdog timeout may cause a reset of the device. Other settings of the CWRI field may enable a core watchdog interrupt and upon a watchdog timeout, this interrupt can bring the device out of low-power mode. This system setup must meet the

conditions specified in Section 8.3.3, “Low-Power Modes

” for the core watchdog interrupt to bring the part out of low-power mode.

8.3.4.7

Cross-Bar Switch

8.3.4.8

GPIO Ports

The GPIO ports are unaffected by entry into a low-power mode. These pins may impact low-power current draw if they are configured as outputs and are sourcing current to an external load. If low-power mode is exited by a reset, the state of the I/O pins reverts to their default direction settings.

8.3.4.9

Interrupt Controllers (INTC0)

The interrupt controller is not affected by any of the low-power modes. All logic between the input sources and generating the interrupt to the processor is combinational to allow the ability to wake up the core during low-power stop mode when all system clocks are stopped.

An interrupt request causes the CPU to exit a low-power mode only if that interrupt’s priority level is at or above the level programmed in the interrupt priority mask field of the CPU’s status register (SR) and above the level programmed in the WCR[PRILVL]. The interrupt must also be enabled in the interrupt controller’s interrupt mask register as well as at the module from which the interrupt request would originate.

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8.3.4.10

Edge Port

In wait and doze modes, the edge port continues to operate normally and may be configured to generate interrupts (an edge transition or low level on an external pin) to exit the low-power modes.

In stop mode, there is no system clock available to perform the edge detect function. Thus, only the level detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode.

8.3.4.11

eDMA Controller

In wait and doze modes, the eDMA controller is capable of bringing the device out of a low-power mode by generating an interrupt upon completion of a transfer or an error condition. The completion of transfer interrupt is generated when DMA interrupts are enabled by the setting of a EDMA_INTR[INTn] bit, and an interrupt is generated when the TCDn[DONE] bit is set. The interrupt upon error condition is generated when the EDMA_EEIR[EEIn] bit is set, and an interrupt is generated when any of the EDMA_ESR bits becomes set.

The eDMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode.

8.3.4.12

FlexBus Module

In wait and doze modes, the FlexBus module continues operation but does not generate interrupts; therefore it cannot bring a device out of a low-power mode. This module is stopped in stop mode.

8.3.4.13

SDRAM Controller (SDRAMC)

SDRAM controller operation is unaffected by the wait or doze modes; however, the SDRAMC is disabled by stop mode. Because all clocks to the SDRAMC are disabled by stop mode, the SDRAMC does not generate refresh cycles.

To prevent loss of data the SDRAMC should be placed in self-refresh mode by clearing SDCR[CKE] and setting SDCR[REF_EN]. The SDRAM self-refresh mode allows the SDRAM to enter a low-power state where internal refresh operations are used to maintain the integrity of the data stored in the SDRAM.

When stop mode is exited, setting the SDCR[CKE] bit causes the SDRAM controller to exit the self-refresh mode and allow bus cycles to the SDRAM to resume.

NOTE

The SDRAM is inaccessible while in the self-refresh mode. Therefore, if stop mode is used the vector table and any interrupt handlers that could wake the processor should not be stored in or attempt to access SDRAM.

8.3.4.14

Fast Ethernet Controller (FEC)

In wait and doze modes, the FEC is unaffected and may generate an interrupt to exit these low-power modes. In stop mode, the FEC stops immediately and freezes operation, register values, state machines, and external pins. During this mode, the FEC clocks are shut down. Coming out of stop mode returns the

FEC to operation from the state prior to stop mode entry.

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8.3.4.15

On-chip Watchdog Timer

In stop mode (or in wait/doze mode, if so programmed in the WCR register), the watchdog ceases operation and freezes at the current value. When exiting these modes, the watchdog resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation.

When not stopped, the watchdog may generate a reset to exit the low-power modes.

8.3.4.16

Programmable Interrupt Timers (PIT0–3)

In stop mode (or in doze mode, if so programmed in the PCSRn register), the programmable interrupt timer

(PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation.

When not stopped, the PIT may generate an interrupt to exit the low-power modes.

8.3.4.17

DMA Timers (DTIM0–3)

In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power mode. This interrupt can be generated when the DMA timer is in input capture mode or reference compare mode.

In input capture mode, where the capture enable (CE) field of the timer mode register (DTMR) has a non-zero value and the DTXMR[DMAEN] is cleared, an interrupt is issued upon a captured input. In reference compare mode, where the output reference request interrupt enable (ORRI) bit of DTMR is set and the DTXMR[DMAEN] bit is cleared, an interrupt is issued when the timer counter reaches the reference value.

DMA timer operation is disabled in stop mode. Upon exiting stop mode, the timer resumes operation unless stop mode was exited by reset.

8.3.4.18

Queued Serial Peripheral Interface (QSPI)

In wait and doze modes, the QSPI module is unaffected and may generate an interrupt to exit these low-power modes.

In stop mode, the QSPI stops immediately and freezes operation, register values, state machines, and external pins. During this mode, the QSPI clocks are shut down. Coming out of stop mode returns the QSPI to operation from the state prior to stop mode entry.

8.3.4.19

UART Modules (UART0–2)

In wait and doze modes, the UARTs are unaffected and may generate an interrupt to exit these low-power modes.

In stop mode, the UARTs stop immediately and freeze their operation, register values, state machines, and external pins. During this mode, the UART clocks are shut down. Coming out of stop mode returns the

UARTs to operation from the state prior to stop mode entry.

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8.3.4.20

C Module

When the I mode, the I

C Module is enabled by the setting of the I2CR[IEN] bit and when the device is not in stop

C module is operable and may generate an interrupt to bring the device out of a low-power mode. For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and the setting of the

I2SR[IIF] generates the interrupt signal to the CPU and interrupt controller. The setting of I2SR[IIF] signifies the completion of one byte transfer or the reception of a calling address matching its own specified address when in slave receive mode.

In stop mode, the I

C module stops immediately and freezes operation, register values, and external pins.

Upon exiting stop mode, the I

C resumes operation unless stop mode was exited by reset.

8.3.4.21

BDM

Entering halt (debug) mode via the BDM port (by asserting the external BKPT pin) causes the CPU to exit any low-power mode.

8.3.4.22

JTAG

The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not affected by the system clock. The JTAG cannot generate an event to cause the CPU to exit any low-power mode.

Toggling TCLK during any low-power mode increases the system current consumption.

8.3.5 Summary of Peripheral State During Low-power Modes

The functionality of each of the peripherals and CPU during the various low-power modes is summarized

in Table 8-10 . The status of each peripheral during a given mode refers to the condition the peripheral

automatically assumes when the STOP instruction is executed and the LPCR[LPMD] field is set for the particular low-power mode. Individual peripherals may be disabled by programming its dedicated control bits. The wake-up capability field refers to the ability of an interrupt or reset by that peripheral to force the

CPU into run mode.

Module

Table 8-10. CPU and Peripherals in Low-Power Modes

Peripheral Status

/ Wake-up Procedure

Wait Mode Doze Mode Stop Mode

ColdFire Core

SRAM

Clock Module

Power Management

Chip Configuration Module

Reset Controller

System Control Module

GPIO Module

Stopped

Enabled

N/A

Interrupt

N/A

Reset

N/A

Stopped

Enabled

N/A

Interrupt

N/A

Reset

N/A

Stopped

Program

Stopped

Enabled

Stopped

Enabled

N/A

Interrupt

N/A

Reset

N/A

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Table 8-10. CPU and Peripherals in Low-Power Modes (continued)

Peripheral Status

/ Wake-up Procedure

Module

Wait Mode Doze Mode Stop Mode

Interrupt controller

Edge port eDMA Controller

FlexBus Module

SDRAM Controller

Fast Ethernet Controller

On-chip Watchdog Timer

Programmable Interrupt Timers

Enabled

Program

Enabled

Interrupt

Yes

N/A

Interrupt

Reset

Interrupt

Enabled

Program

Interrupt

Yes

N/A

Interrupt

Reset

Interrupt

Enabled

Stopped

DMA Timers

QSPI

Enabled

Interrupt

Enabled

Interrupt

Stopped

N/A

UARTs

C Module

Enabled

Interrupt

Enabled

Interrupt

Stopped

N/A

JTAG

BDM

Enabled

N/A

Yes

Enabled

N/A

Yes

Enabled

N/A

Yes

Program indicates that the peripheral function during the low-power mode is dependent on programmable bits in the peripheral register map.

The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any lower-power mode.

Upon exit from halt mode, the previous low-power mode is re-entered and changes made in halt mode remain in effect.

Interrupt

N/A

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8-16

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Chapter 9 Chip Configuration Module (CCM)

9.1 Introduction

The chip configuration module (CCM) controls the chip configuration for the device.

9.1.1 Block Diagram

Reset

Configuration

Boot Device / Port

Size Selection

Output Pad

Strength Selection

Chip Select

Configuration

Chip Configuration Register

Reset Configuration Register

Chip Identification Register

Figure 9-1. Chip Configuration Module Block Diagram

9.1.2 Features

The CCM performs the following operations:

• Selects the chip operating mode

• Selects external clock or phase-lock loop (PLL) mode with internal or external reference

• Selects output pad drive strength

• Selects boot device and data port size

• Selects bus monitor configuration

• Selects low-power configuration

9.1.3 Modes of Operation

The only chip operating mode available on this device is master mode. In master mode, the ColdFire core can access external memories and peripherals.The external bus consists of a 32-bit data bus and 24 address

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lines. The available bus control signals include R/W, TS, TA, OE, and BE/BWE[3:0]. Up to six chip selects can be programmed to select and control external devices and to provide bus cycle termination.

9.2 External Signal Descriptions

Table 9-1

provides an overview of the CCM signals.

Table 9-1. Signal Properties

RCON

D[9,7:1]

Name Function

Reset configuration select

Reset configuration override pins

Reset State

Internal weak pull-up device

—

9.2.1 RCON

If the external RCON pin is asserted during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins (see

Section 9.4, “Functional Description”

). The internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration.

9.2.2 D[9,7:1] (Reset Configuration Override)

If the external RCON pin is asserted during reset, then the states of these data pins during reset determine the chip mode of operation, boot device, clock mode, and certain module configurations after reset.

NOTE

It is recommended that the logic levels for reset configuration on D[9,7:1] be actively driven when RCON is used. The rest of the data bus should be allowed to float or be pulled high.

9.3 Memory Map/Register Definition

The CCM programming model consists of the registers listed in the below table.

Table 9-2. CCM Memory Map

Address Register

Width

(bits)

Access Reset Value Section/Page

Supervisor Access Only Registers

0xFC0A_0004 Chip Configuration Register (CCR)

0xFC0A_0008 Reset Configuration Register (RCON)

0xFC0A_000A Chip Identification Register (CIR) 16 R

User access to supervisor only address locations have no effect and result in a bus error.

See Section

0x0201

See Section

9.3.1/9-3

9.3.2/9-4

9.3.3/9-4

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9.3.1 Chip Configuration Register (CCR)

The CCR is a read-only register; writing to the CCR has no effect. At reset, the CCR reflects the chosen operation of certain chip functions. These functions may be set to the defaults defined by the RCON register values or may be overridden during reset configuration using the external RCON and D[15:0] pins.

(See Figure 9-3 for the RCON register definition.)

Address: 0xFC0A_0004 (CCR) Access: Supervisor read-only

CSC

OSC

FREQ

6 5 4 3

LIMP LOAD BOOTPS

OSC

MODE

PLL

MODE

Reset 0 0 0 0 0 0 See Note 1

Note: Reset value depends upon chosen reset configuration. Default reset value (RCON is not asserted) is 0x012B.

Figure 9-2. Chip Configuration Register (CCR)

Table 9-3. CCR Field Descriptions

Field Description

15–10

CSC

LOAD

Reserved, should be cleared.

Chip select configuration field. Reflects the chosen chip select configuration.

0 A[23:22] = A[23:22]

1 A[23] = FB_CS5 and A[22] = FB_CS4

Reserved, should be set.

OSCFREQ

Oscillator frequency select bit. Reflects the chosen PLL multiplier for the device. However, this bit is valid only if

PLLMODE is set (D1 is asserted during RCON).

0 PLL’s PFDR[MFD] is set to 125, if PLLMODE is set.

1 PLL’s PFDR[MFD] is set to 120, if PLLMODE is set.

LIMP

Limp mode bit.

0 Normal operation; PLL drives internal clocks.

1 Limp mode; low-power clock divider drives internal clocks.

Pad driver load bit. Reflects the chosen pad driver strength for those pins with drive strength control and the chosen pad slew rate for those pins with slew rate control.

0 Low drive strength, low slew rate

1 High drive strength, high slew rate

4–3

BOOTPS

Boot port size field. Indicates the selection for the boot port size.

00 32 bits

01 16 bits

10 8 bits

11 32 bits

OSCMODE

Oscillator clock mode bit.

0 Crystal oscillator mode

1 Oscillator bypass mode

PLLMODE

PLL clock mode

0 88/44 MHz operation

1 166.67/83.33 MHz operation

0 Reserved, should be set.

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9.3.2 Reset Configuration Register (RCON)

At reset, RCON determines the default operation of certain chip functions. All default functions defined by the RCON values can only be overridden during reset configuration (see

Section 9.4.1, “Reset

Configuration ”) if the external RCON pin is asserted. RCON is a read-only register and contains the same

fields as the CCR register. See Table 9-3 for field descriptions.

Address: 0xFC0A_0008 (RCON)

15 14 13 12

0 0 0 0

Reset 0 0 0

CSC

Access: Supervisor read-only

0 7

OSC

FREQ

6 5 4 3

LIMP LOAD BOOTPS

OSC

MODE

PLL

MODE

0 0 0 0 1 0 0 1

Figure 9-3. Reset Configuration Register (RCON)

0 1 0 1 1

9.3.3 Chip Identification Register (CIR)

Address: 0xFC0A_000A (CIR)

15 14 13

Reset

12 11

10 9 8 7 6 5

Device Dependent

Figure 9-4. Chip Identification Register (CIR)

Access: Supervisor read-only

PRN

2 1 0

Mask Set Dependent

Field

15–6

Table 9-4. CIR Field Description

Description

Part identification number. Contains a unique identification number for the device.

0x044 MCF5208

0x045 MCF5207

5–0

PRN

Part revision number. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order.

9.4 Functional Description

Six functions are defined within the chip configuration module:

1. Reset configuration

2. PLL mode

3. Oscillator mode

4. Boot device selection

5. Output pad strength configuration

6. Chip select configuration

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These functions are described below.

9.4.1 Reset Configuration

During reset, the pins for the reset override functions are immediately configured to known states.

Table 9-5

shows the states of the external pins while in reset.

Table 9-5. Reset Configuration Pin States During Reset

Pin

Function

I/O

Output

State

Input

State

D[15:0] Primary function Input — Must be driven by external logic

RCON RCON function for all modes

Input — Internal weak pull-up device

If the external RCON pin is not asserted during reset, pin functions are determined by the default operation mode defined in the RCON register. If the external RCON pin is asserted, pin functions are determined by the override values driven on the external data bus pins.

During reset, the external RCON pin assumes its RCON pin function, but this pin changes to the function defined by the chip operation mode immediately after reset. See

Table 9-6 .

If the RCON pin is not asserted during reset, the chip configuration and the reset configuration pin functions after reset are determined by the RCON register or fixed defaults, regardless of the states of the external data pins. The internal configuration signals are driven to levels specified by the RCON register’s reset state for default module configuration.

If the RCON pin is asserted during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins. (See

Table 9-6

.) The internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration.

NOTE

It is recommended that the logic levels for reset configuration on D[9,7:1] be actively driven when RCON is used. The rest of the data bus should be allowed to float or be pulled high.

Table 9-6. Configuration During Reset

Pin(s) Affected

None

Default

Configuration

RCON[1] = 1

Override Pins in Reset

Function

PLL Mode

88/44 MHz operation

166.67/83.33 MHz operation

(default)

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Table 9-6. Configuration During Reset

(continued)

Pin(s) Affected

None

All output pins

None

Default

Configuration

RCON[2] = 0

RCON[4:3] = 01

RCON[5] = 1

RCON[6] = 0

RCON[7] = 0

Override Pins in Reset

D[4:3]

Function

Oscillator Mode

Crystal oscillator mode (default)

Oscillator bypass mode

Boot Device

External with 32-bit port

External with 16-bit port (default)

External with 8-bit port

External with 32-bit port

Output pad drive strength

Low Drive Strength

High Drive Strength (default)

Limp Mode

PLL mode (default)

Limp mode

PLL Multiplier Select

A[23:22]/FB_CS[5:4] RCON[9] = 0

120 (default)

125

Chip Select Configuration

0 A[23:22] = A[23:22]

1 A[23:22] = FB_CS[5:4] (default)

Modifying the default configurations is possible only if the external RCON pin is asserted.

The external reset override circuitry drives the data bus pins with the override values while RSTOUT is asserted. It must stop driving the data bus pins within one FB_CLK cycle after RSTOUT is negated. To prevent contention with the external reset override circuitry, the reset override pins are forced to inputs during reset and do not become outputs until at least one FB_CLK cycle after RSTOUT is negated.

32-bit port size is not available when DRAMSEL = 0. Defaults to 16-bit mode instead.

Valid only if D1 is set.

9.4.2 PLL Mode Selection

The initial device operating frequency is determined during reset configuration by the D1 pin. The default configuration with a 16 MHz input clock is 88 MHz for the core and 44 MHz for the internal bus. The user may choose to almost double these frequencies (166.67 MHz and 83.33 MHz) by placing the device in limp mode and reconfiguring the appropriate PLL registers, or asserting D1 during reset configuration.

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9.4.3 Oscillator Mode Selection

Use of the internal oscillator can be selected during reset configuration via the D2 pin. By default, the oscillator is enabled and the PLL is placed in normal mode with a crystal reference. If default configuration is over-ridden and D2 is asserted, the PLL is placed in normal mode with a external reference and the

internal oscillator is bypassed. After reset is exited, the oscillator mode cannot be changed. See Chapter 7,

“Clock Module”

for more details on the available modes.

9.4.4 Boot Device Selection

During reset configuration, the FB_CS0 chip select pin is configured to select an external boot device. In this case, the V (valid) bit in the CSMR0 register is ignored, and FB_CS0 is enabled after reset. FB_CS0 is asserted for the initial boot fetch accessed from address 0x0000_0000 for the stack pointer and address

0x0000_0004 for the program counter (PC). It is assumed that the reset vector loaded from address

0x0000_0004 causes the core to start executing from external memory space decoded by FB_CS0.

9.4.5 Output Pad Strength Configuration

Output pad strength is determined during reset configuration as shown in

Table 9-7

. After reset is exited, the output pad strength configuration can only be changed using the GPIO module. For more information

see Chapter 13, “General Purpose I/O Module.”

Table 9-7. Output Pad Driver Strength Selection

Optional Pin Function Selection D5

Output pads configured for low drive strength D5 driven low

Output pads configured for full drive strength D5 driven high

Modifying the default configurations is possible only if the external RCON pin is asserted low.

9.4.6 Chip Select Configuration

The chip select configuration (FB_CS[5:4]) is selected during reset and reflected in the CCR[CSC] field.

After reset is exited, the chip select configuration cannot be changed. Table 9-6

shows the different chip select configurations that can be implemented during reset configuration.

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Chapter 10 Reset Controller Module

10.1 Introduction

The reset controller determines the cause of reset, asserts the appropriate reset signals to the system, and keeps a history of what caused the reset.

10.1.1 Block Diagram

Figure 10-1

illustrates the reset controller and is explained in the following sections.

RESET

Power-On

Reset

Core Watchdog

Timer Timeout

RSTOUT

Reset

Controller

On-chip Watchdog

Timer Timeout

PLL

Loss of Lock

To Internal Resets

Software

Reset

Figure 10-1. Reset Controller Block Diagram

10.1.2 Features

Module features include the following:

• Six sources of reset:

— External

— Power-on reset (POR)

— Core watchdog timer

— On-chip watchdog timer

— Phase locked-loop (PLL) loss of lock

— Software

• Software-assertable RSTOUT pin independent of chip reset state

• Software-readable status flags indicating the cause of the last reset

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10.2 External Signal Description

Table 10-1

provides a summary of the reset controller signal properties. The signals are described in the following paragraphs.

Table 10-1. Reset Controller Signal Properties

Name Direction

Input

Hysteresis

RESET I Y

RSTOUT O —

RESET is always synchronized except when in low-power stop mode.

Input

Synchronization

—

10.2.1 RESET

Asserting the external RESET for at least four rising FB_CLK edges causes the external reset request to be recognized and latched.

10.2.2 RSTOUT

This active-low output signal is driven low when the internal reset controller module resets the chip. It may take up to six FB_CLK edges after RESET assertion for RSTOUT to assert, due to an internal synchronizer on RESET. When RSTOUT is active, the user can drive override options on the data bus. See

Chapter 9,

“Chip Configuration Module (CCM),”

for more details on these override options.

10.3 Memory Map/Register Definition

The reset controller programming model consists of these registers:

• Reset control register (RCR), which selects reset controller functions

• Reset status register (RSR), which reflects the state of the last reset source

See Table 10-2 for the memory map and the following paragraphs for a description of the registers.

Table 10-2. Reset Controller Memory Map

Address Register

0xFC0A_0000 Reset Control Register (RCR)

0xFC0A_0001 Reset Status Register (RSR)

Width

(bits)

Access Reset Value Section/Page

R/W

0x00

10.3.1/10-2

See Section

10.3.2/10-3

10.3.1 Reset Control Register (RCR)

The RCR allows software control for requesting a reset, and for independently asserting the external

RSTOUT pin.

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Reset Controller Module

Address: 0xFC0A_0000 (RCR)

7 6

Reset:

SOFTRST FRCRSTOUT

0 0 0 0

Figure 10-2. Reset Control Register (RCR)

Access: User read/write

0 0

Table 10-3. RCR Field Descriptions

Field Description

SOFTRST

Allows software to request a reset. The reset caused by setting this bit clears this bit.

1 Software reset request

0 No software reset request

FRCRSTOUT

Allows software to assert or negate the external RSTOUT pin.

1 Assert RSTOUT pin

0 Negate RSTOUT pin

CAUTION: External logic driving reset configuration data during reset needs to be considered when asserting the RSTOUT pin when setting FRCRSTOUT.

10.3.2 Reset Status Register (RSR)

The RSR contains a status bit for every reset source. When reset is entered, the cause of the reset condition is latched, along with a value of 0 for the other reset sources that were not pending at the time of the reset condition. These values are then reflected in RSR. One or more status bits may be set at the same time.

The cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset condition.

RSR can be read at any time. Writing to RSR has no effect.

Address: 0xFC0A_0001 (RSR)

SOFT

WDR

CHIP

POR

EXT

Access: User read-only

WDR

CORE

LOL

Field

7–6

SOFT

Reset: 0 0 Reset

Dependent

Reset

Dependent

Reset

Dependent

Reset

Dependent

Reset

Dependent

Reset

Dependent

Figure 10-3. Reset Status Register (RSR)

Table 10-4. RSR Field Descriptions

Description

Reserved, should be cleared.

Software reset flag. Indicates that the last reset was caused by software.

0 Last reset not caused by software

1 Last reset caused by software

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Table 10-4. RSR Field Descriptions (continued)

Field Description

WDRCHIP

On-chip watchdog timer reset flag. Indicates that the last reset was caused by the on-chip watchdog timer timeout.

0 Last reset not caused by watchdog timer timeout

1 Last reset caused by watchdog timer timeout

POR

EXT

Power-on reset flag. Indicates that the last reset was caused by a power-on reset.

0 Last reset not caused by power-on reset

1 Last reset caused by power-on reset

External reset flag. Indicates that the last reset was caused by an external device or circuitry asserting the external RESET pin.

0 Last reset not caused by external reset

1 Last reset caused by external reset

WDRCORE

Core watchdog timer reset flag. Indicates that the last reset was caused by the core watchdog timer timeout.

0 Last reset not caused by watchdog timer timeout

1 Last reset caused by watchdog timer timeout

LOL

Loss-of-lock reset flag. Indicates that the last reset state was caused by a PLL loss of lock.

0 Last reset not caused by loss of lock

1 Last reset caused by a loss of lock

10.4 Functional Description

10.4.1 Reset Sources

Table 10-5

defines the sources of reset and the signals driven by the reset controller.

Table 10-5. Reset Source Summary

Source

Power on

External RESET pin (not stop mode)

External RESET pin (during stop mode)

Core Watchdog timer

On-chip watchdog timer

Loss of lock

Software

Type

Asynchronous

Synchronous

Asynchronous

Synchronous

Asynchronous

Synchronous

To protect data integrity, a synchronous reset source is not acted upon by the reset control logic until the end of the current bus cycle. Reset is then asserted on the next rising edge of the system clock after the cycle is terminated. Internal byte, word, or longword writes are guaranteed to complete without data corruption when a synchronous reset occurs. External writes, including longword writes to 16-bit ports, are also guaranteed to complete.

Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the system.

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10.4.1.1

Power-On Reset

At power up, the reset controller asserts RSTOUT. RSTOUT continues to be asserted until V

has reached a minimum acceptable level and, if PLL clock mode is selected, until the PLL achieves phase lock.

Then after approximately another 512 cycles, RSTOUT is negated and the device begins operation.

10.4.1.2

External Reset

Asserting the external RESET for at least four rising FB_CLK edges causes the external reset request to be recognized and latched. The reset controller asserts RSTOUT for approximately 512 cycles after

RESET is negated and the PLL has acquired lock. The device then exits reset and begins operation.

In low-power stop mode, the system clocks are stopped. Asserting the external RESET in stop mode causes an external reset to be recognized asynchronously.

10.4.1.3

On-chip Watchdog Timer Reset

An on-chip watchdog timer timeout causes timer reset request to be recognized and latched. If the RESET pin is negated and the PLL has acquired lock, the reset controller asserts RSTOUT for approximately 512 cycles. Then the device exits reset and begins operation.

10.4.1.4

Core Watchdog Timer Reset

A core watchdog timer timeout causes timer reset request to be recognized and latched. If the RESET pin is negated and the PLL has acquired lock, the reset controller asserts RSTOUT for approximately 512 cycles. Then the device exits reset and begins operation.

10.4.1.5

Loss-of-Lock Reset

This reset condition occurs when the device is operating in PLL mode and the PLL loses lock. The reset controller asserts RSTOUT for approximately 512 cycles after the PLL has acquired lock. The device then exits reset and resumes operation.

When operating in limp mode and the PLL loses lock (e.g. when changing PLL frequencies) this reset does not occur.

10.4.1.6

Software Reset

A software reset occurs when the RCR[SOFTRST] bit is set. If the RESET is negated and the PLL has acquired lock, the reset controller asserts RSTOUT for approximately 512 cycles. Then the device exits reset and resumes operation.

10.4.2 Reset Control Flow

The reset logic control flow is shown in

Figure 10-4

. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate.

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Freescale Semiconductor 10-5

Reset Controller Module

1 POR

LOSS OF LOCK?

RESET

PIN OR WD TIMEOUT

OR SW RESET?

ASSERT RSTOUT AND

LATCH RESET STATUS

ASSERT RSTOUT AND

LATCH RESET STATUS

RESET NEGATED?

PLL LOCKED?

WAIT 512 FB_CLK CYCLES

NEGATE RSTOUT

RCON ASSERTED?

LATCH CONFIGURATION

Figure 10-4. Reset Control Flow

10.4.2.1

Synchronous Reset Requests

In this discussion, the reference in parentheses refer to the state numbers in

Figure 10-4

. All cycle counts given are approximate.

If the external RESET signal is asserted by an external device for at least four rising FB_CLK edges (3), if the watchdog timer times out, or if software requests a reset, the reset control logic latches the reset request internally. At this point the RSTOUT pin is asserted (5). The reset control logic waits until the

RESET signal is negated (6) and for the PLL to attain lock (7) before waiting 512 FB_CLK cycles (8). The

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reset control logic may latch the configuration according to the RCON signal level (9, 9A) before negating

RSTOUT (10).

If the external RESET signal is asserted by an external device for at least four rising FB_CLK edges during the 512 count (8) or during the wait for PLL lock (7), the reset flow switches to (6) and waits for the

RESET signal to be negated before continuing.

10.4.2.2

Internal Reset Request

If reset is asserted by an asynchronous internal reset source, such as loss of clock (1), the reset control logic asserts RSTOUT (4). The reset control logic waits for the PLL to attain lock (7) before waiting 512

FB_CLK cycles (8). Then the reset control logic may latch the configuration according to the RCON pin level (9, 9A) before negating RSTOUT (10).

If loss of lock occurs during the 512 count (8), the reset flow switches to (7) and waits for the PLL to lock before continuing.

10.4.2.3

Power-On Reset

When the reset sequence is initiated by power-on reset (1), the same reset sequence is followed as for the other asynchronous reset sources.

10.4.3 Concurrent Resets

This section describes the concurrent resets. As in the previous discussion references in parentheses refer

to the state numbers in Figure 10-4 .

10.4.3.1

Reset Flow

If a power-on reset is detected during any reset sequence, the reset sequence starts immediately (1).

If the external RESET pin is asserted for at least four rising FB_CLK edges while waiting for PLL lock or the 512 cycles, the external reset is recognized. Reset processing switches to wait for the external RESET pin to negate (6).

If a loss-of-lock condition is detected during the 512 cycle wait, the reset sequence continues after a PLL lock (7).

10.4.3.2

Reset Status Flags

For a POR reset, the RSR[POR] bit is set, and all other RSR flags are cleared even if another type of reset condition is pending or concurrently asserted.

If other sources of reset are asserted after the RSR status bits have been latched (4 or 5), the device is held in reset (8) until all sources have negated and the subsequent sources are not reflected in the RSR contents.

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Chapter 11 System Control Module (SCM)

11.1 Introduction

This system control module (SCM) provides several control functions, including peripheral access control, a software core watchdog timer, and generic access error information for the processor core.

11.1.1 Overview

The SCM provides programmable access protections for both masters and peripherals. It allows the privilege level of a master to be overridden, forcing it to user-mode privilege, and allows masters to be designated as trusted or untrusted. Peripherals may be programmed to require supervisor privilege level for access, may restrict access to a trusted master only, and may be write-protected.

The SCM’s core watchdog timer (CWT) provides a means of preventing system lockup due to uncontrolled software loops via a special software service sequence. If periodic software servicing action does not occur, the CWT times out with a programmed response (system reset or interrupt) to allow recovery or corrective action to be taken.

NOTE

The core watchdog timer is available to provide compatibility with the watchdog timer implemented on previous ColdFire devices. However, there

is a second watchdog timer available that has new features. See Chapter 20,

“Watchdog Timer Module,”

for more information.

Fault access reporting is also available within the SCM. The user can use these registers during the resulting interrupt service routine and perform an appropriate recovery.

11.1.2 Features

The SCM includes these distinctive features:

• Access control registers

— Master privilege register (MPR)

— Peripheral access control registers (PACRs)

• System control registers

— Core watchdog control register (CWCR) for watchdog timer control

— Core watchdog service register (CWSR) to service watchdog timer

— SCM interrupt status register (SCMISR) to service a bus fault or watchdog interrupt

— Bus monitor timeout register (BMT)

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System Control Module (SCM)

• Core fault reporting registers

11.2 Memory Map/Register Definition

The memory map for the SCM registers is shown in

Table 11-1

Attempted accesses to reserved addresses result in a bus error, while attempted writes to read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the programming model must match the size of the register, e.g., an 8-bit register only supports 8-bit writes, etc. Attempted writes of a different size than the register width produce a bus error and no change to the targeted register.

Table 11-1. SCM Memory Map

Address Register

0xFC00_0000 Master Privilege Register (MPR)

0xFC00_0020 Peripheral Access Control Register A (PACRA)

0xFC00_0024 Peripheral Access Control Register B (PACRB)

0xFC00_0028 Peripheral Access Control Register C (PACRC)

0xFC00_002C Peripheral Access Control Register D (PACRD)

0xFC00_0040 Peripheral Access Control Register E (PACRE)

0xFC00_0044 Peripheral Access Control Register F (PACRF)

0xFC00_0054 Bus Monitor Timeout (BMT)

0xFC04_0013 Wakeup Control Register (WCR)

0xFC04_0016 Core Watchdog Control Register (CWCR)

0xFC04_001B Core Watchdog Service Register (CWSR)

0xFC04_001F SCM Interrupt Status Register (SCMISR)

0xFC04_0070 Core Fault Address Register (CFADR)

0xFC04_0075 Core Fault Interrupt Enable Register (CFIER)

0xFC04_0076 Core Fault Location Register (CFLOC)

0xFC04_0077 Core Fault Attributes Register (CFATR)

0xFC04_007C Core Fault Data Register (CFDTR)

The WCR register is described in Chapter 8, “Power Management.”

Width

(bits)

Access Reset Value Section/Page

R/W

R/W 0x7777_7777

R/W 0x5444_4444

R/W 0x4444_4444

R/W 0x4444_4444

R/W 0x4444_4444

R/W 0x4444_4444

R/W 0x4444_4444

R/W 0x0000_0008

0x00

0x0000

Undefined

0x00

0x0000_0000

0x00

Undefined

Undefined

Undefined

11.2.1 Master Privilege Register (MPR)

The MPR specifies three 4-bit fields defining the access privilege level associated with a bus master in the

device to the various peripherals listed in Table 11-4 . The register provides one field per bus master.

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System Control Module (SCM)

Address: 0xFC00_0000 (MPR) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

MPROT0 MPROT1 MPROT2

Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1

Figure 11-1. Master Privilege Register (MPR)

Each master is assigned depending on its connection to the various cross-bar switch master ports.

Table 11-2. MPROTn Assignments

Cross-bar Switch

Port Number

MPROTn

MPROT0

MPROT1

MPROT2

Master

ColdFire Core eDMA Controller

FEC

The MPROTn field is defined as shown below.

MTR

MTW

MPL

Field

MTR

MTW

MPL

Figure 11-2. MPROTn Fields

Table 11-3. MPROTn Field Descriptions

Description

Reserved, should be cleared.

Master trusted for read. Determines whether the master is trusted for read accesses.

0 This master is not trusted for read accesses.

1 This master is trusted for read accesses.

Master trusted for writes. Determines whether the master is trusted for write accesses.

0 This master is not trusted for write accesses.

1 This master is trusted for write accesses.

Master privilege level. Determines how the privilege level of the master is determined.

0 Accesses from this master are forced to user-mode.

1 Accesses from this master are not forced to user-mode.

11.2.2 Peripheral Access Control Registers (PACRx)

Each of the peripherals has a four-bit PACRn field which defines the access levels supported by the given module. Eight PACRs are grouped together to form a 32-bit PACRx register (PACRA-PACRF). At reset the SCM (PACR0) does not allow access from untrusted masters, while the other peripherals do.

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System Control Module (SCM)

Address: 0xFC00_0020 (PACRA) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

PACR0 PACR1 PACR2

Reset 0 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Figure 11-3. Peripheral Access Control Register A (PACRA)

Address: 0xFC00_0024 (PACRB) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

PACR12

0 1 0 0 0 1 0 0 0 1 0 0

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Figure 11-4. Peripheral Access Control Register B (PACRB)

Address: 0xFC00_0028 (PACRC) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 0 1 0 0

PACR16 PACR17 PACR18 PACR21 PACR22 PACR23

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Figure 11-5. Peripheral Access Control Register C (PACRC)

Address: 0xFC00_002C (PACRD) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0

PACR24 PACR25 PACR26 PACR28 PACR29 PACR30 PACR31

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Figure 11-6. Peripheral Access Control Register D (PACRD)

Address: 0xFC00_0040 (PACRE) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 0 1 0 0 0 1 0 0

PACR32 PACR33 PACR34 PACR35 PACR36

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Figure 11-7. Peripheral Access Control Register E (PACRE)

Address: 0xFC00_0044 (PACRF) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

PACR40 PACR41 PACR42

Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

Figure 11-8. Peripheral Access Control Register F (PACRF)

Each peripheral is assigned to its PACRn field as shown below:

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Slot Number

The PACRn field is defined as shown below.

Table 11-4. PACRn Assignments

PACRn

PACR22

PACR23

PACR24

PACR25

PACR26

PACR28

PACR29

PACR30

PACR0

PACR1

PACR2

PACR12

PACR16

PACR17

PACR18

PACR21

PACR31

PACR32

PACR33

PACR34

PACR35

PACR36

PACR40

PACR41

PACR42

Peripheral

SCM (MPR & PACRs)

Cross-bar switch

FlexBus

FEC

SCM (CWT & Core Fault Registers) eDMA Controller

Interrupt Controller 0

Interrupt Controller IACK

QSPI

UART0

UART1

UART2

DMA Timer 0

DMA Timer 1

DMA Timer 2

DMA Timer 3

PIT 0

PIT 1

Edge Port

On-chip Watchdog Timer

PLL

CCM, Reset Controller, Power Management

GPIO Module

SDRAM Controller

Figure 11-9. PACRn Fields

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Table 11-5. PACRn Field Descriptions

Field

Description

Reserved, should be cleared.

Supervisor protect. Determines whether the peripheral requires supervisor privilege level for access.

0 This peripheral does not require supervisor privilege level for accesses.

1 This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor access attribute, and the MPROTn[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated.

Write protect. Determines whether the peripheral allows write accesses

0 This peripheral allows write accesses.

1 This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated.

Trusted Protect. Determines whether the peripheral allows accesses from an untrusted master.

0 Accesses from an untrusted master are allowed.

1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated.

11.2.3 Bus Monitor Timeout Register (BMT)

Each AIPS controller implements a bus timeout monitor to insure that every bus cycle is properly terminated within a programmed period of time. The monitor continually checks for termination of each bus cycle and completes the cycle if there is no response when the programmed monitor cycle count is reached.

The monitor can be programmed from 8–1024 internal bus cycles under control of the BMT register. If the programmed timeout value is reached before a termination, the bus monitor completes the cycle with an error termination. Thus, the SCMISR[CFEI] bit is set, and an interrupt to the interrupt controller is generated if the CFIER[ECFEI] bit is set. At reset, the BMT is enabled with a maximum timeout value.

Address: 0xFC00_0054 (BMT) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

3 2 1 0

BME BMT

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

Figure 11-10. Bus Monitor Timeout Register (BMT)

Field

31–4

Table 11-6. BMT Field Descriptions

Description

Reserved, should be cleared.

11-6

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Field

BME

2–0

BMT

System Control Module (SCM)

Table 11-6. BMT Field Descriptions (continued)

Description

Bus monitor timeout enable.

0 BMT disabled

1 BMT enabled

Bus monitor timeout period. Indicates the timeout period in internal bus cycles for the bus monitor.

000 1024 cycles

001 512 cycles

010 256 cycles

011 128 cycles

100 64 cycles

101 32 cycles

110 16 cycles

111 8 cycles

11.2.4 Core Watchdog Control Register (CWCR)

The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer interrupt. The register can be read or written at any time. At system reset, the software watchdog timer is disabled.

Address: 0xFC04_0016 (CWCR)

Reset 0

RWH

CWE

CWRI

Figure 11-11. Core Watchdog Control Register (CWCR)

Access: User read/write

2 1 0

CWT

0 0 0 0

Table 11-7. CWCR Field Descriptions

Field Description

Read-only control bit.

0 CWCR can be read or written.

1 CWCR is read-only. A system reset is required to clear this register. The setting of this bit is intended to prevent accidental writes of the CWCR from changing the defined core watchdog configuration.

14–9 Reserved, should be cleared.

CWRWH

Core watchdog run while halted.

0 Core watchdog timer stops counting if the core is halted.

1 Core watchdog timer continues to count even while the core is halted.

CWE

Core watchdog timer enable.

0 CWT is disabled.

1 CWT is enabled.

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Table 11-7. CWCR Field Descriptions (continued)

Field

6–5

CWRI

4–0

CWT

Description

Core watchdog reset/interrupt.

00 If a time-out occurs, the CWT generates an interrupt to the core. Refer to

Chapter 14, “Interrupt Controller

Module,”

for details on setting its priority level.

The first time-out generates an interrupt to the processor, and if not serviced, a second time-out generates a system reset and sets theRSR[WDRCORE] flag in the reset controller.

10 If a time-out occurs, the CWT generates a system reset and

RSR[WDRCORE]

in the reset controller is set.

11 The CWT functions in a “window” mode of operation. For this mode, the servicing of the CWSR must occur during the last 25% of the time-out period. Any writes to the CWSR during the first 75% of the time-out period generate an immediate system reset. Likewise, if the CWSR is not serviced during the last 25% of the time-out period, a system reset is generated. For any type of reset response, the

RSR[WDRCORE]

flag is set.

Core watchdog time-out period. Selects the time-out period for the CWT. At reset, this field is cleared selecting the minimum time-out period, but the CWT is disabled since CWCR[CWE] = 0 at reset.

For CWCR[CWT] = n, time-out period = 2

system clock cycles, where n = 8–31. If n < 8, then time-out period is forced to 2

11.2.5 Core Watchdog Service Register (CWSR)

The software watchdog service sequence must be performed using the CWSR as a data register to prevent a CWT time-out. The service sequence requires two writes to this data register: first a write of 0x55 followed by a write of 0xAA. Both writes must be performed in this order prior to the CWT time-out, but any number of instructions can be executed between the two writes. If the CWT has already timed out, writing to this register has no effect in negating the CWT interrupt or reset.

Figure 11-12 illustrates the

CWSR. At system reset, the contents of CWSR are uninitialized.

NOTE

If the CWT is enabled and has not timed out, then any write of a data value other than 0x55 or 0xAA causes an immediate system reset, regardless of the value in the CWCR[CWRI] field.

Address: 0xFC04_001B (CWSR)

7 6

Reset: —

5 4

CWSR

3 2

— — — — —

Figure 11-12. Core Watchdog Service Register (CWSR)

Access: User read/write

—

11.2.6 SCM Interrupt Status Register (SCMISR)

For certain values in the CWCR[CWRI] field, the CWT generates an interrupt response to a time-out. For these configurations, the SCMISR provides a program visible interrupt request from the watchdog timer.

During the interrupt service routine which handles this interrupt, the source must be explicitly cleared by writing a 0x01 to the SCMISR.

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The SCMISR also indicates system bus fault errors. An interrupt will only be sent to the interrupt controller when the CFIER[ECFEI] bit is set. The SCMISR[CFEI] bit flags fault errors independent of the

CFIER[ECFEI] setting. Therefore, if CFEI is set prior to setting ECFEI, an interrupt is requested immediately after ECFEI is set.

Address: 0xFC04_001F (SCMISR)

0 R

Reset: 0

0 0 0 0 0

Figure 11-13. SCM Interrupt Status Register (SCMISR)

Access: User read/write

CFEI w1c

CWIC w1c

Table 11-8. SCMISR Field Descriptions

Field

7–2

CFEI

CWIC

Description

Reserved, should be cleared.

Core fault error interrupt flag. Indicates if a bus fault has occurred.

0 No bus error.

1 A bus error has occurred. The faulting address, attributes (and possibly write data) are captured in the CFADR,

CFATR, and CFDTR registers. The error interrupt is only enabled if CFLOC[ECFEI] is set. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no effect.

Note: This bit reports core faults regardless of the setting of CFIER[ECFEI]. Therefore, if the error interrupt is disabled and a core fault occurs, this bit is set. Then, if the error interrupt is subsequently enabled, an interrupt is immediately requested. To prevent an undesired interrupt, clear the captured error by writing one to CFEI before enabling the interrupt.

Core watchdog interrupt flag. Indicates whether an CWT interrupt has occurred.

0 No CWT interrupt has occurred.

1 CWT interrupt has occurred. Writing a 1 clears this bit and negates the interrupt request. Writing a 0 has no effect.

11.2.7 Core Fault Address Register (CFADR)

The CFADR is a read-only register for indicating the address of the last core access which was terminated with an error response.

Address: 0xFC04_0070 (CFADR) Access: User read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 11-14. Core Fault Address Register (CFADR)

Table 11-9. CFADR Field Descriptions

Field

31–0

ADDR

Description

Indicates the faulting address of the last core access terminated with an error response.

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System Control Module (SCM)

11.2.8 Core Fault Interrupt Enable Register (CFIER)

The CFIER register is used to enable the system bus error interrupt. See Chapter 14, “Interrupt Controller

Module,”

for more information of the interrupt controller.

Address: 0xFC04_0075 (CFIER)

0 R

Reset: 0

Access: User read/write

0 1

ECFEI

0 0 0 0 0

Figure 11-15. Core Fault Interrupt Enable Register (CFIER)

0 0

Table 11-10. CFIER Field Descriptions

Field Description

7–1

ECFEI

Reserved, should be cleared.

Enable core fault error interrupt.

0 Do not generate an error interrupt on a faulted system bus cycle.

1 Generate an error interrupt to the interrupt controller on a faulted system bus cycle.

11.2.9 Core Fault Location Register (CFLOC)

The read-only CFLOC register indicates the exact location within the device of the captured fault information.

Address: 0xFC04_0076 (CFLOC)

LOC

0 R

Reset: –

0 0 0 0 0

Figure 11-16. Core Fault Location Register (CFLOC)

Access: User read-only

Field

LOC

6–0

Table 11-11. CFLOC Field Descriptions

Description

The location of the last captured fault.

0 Error occurred on the internal bus.

1 Error occurred within the core.

Reserved, should be cleared.

11.2.10 Core Fault Attributes Register (CFATR)

The read-only CFATR register captures the processor’s attributes of the last faulted core access to the system bus.

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System Control Module (SCM)

Address: 0xFC04_0077 (CFATR)

6 7

R WRITE

Reset: –

SIZE

4 3

CACHE

– – – – –

Figure 11-17. Core Fault Attributes Register (CFATR)

Access: User read-only

MODE

–

TYPE

–

Table 11-12. CFATR Field Descriptions

Field Description

WRITE

Indicates the direction of the last faulted core access.

0 Core read access.

1 Core write access.

6–4

SIZE

Indicates the size of the last faulted core access.

000 8-bit core access.

001 16-bit core access.

010 32-bit core access.

Else Reserved.

CACHE

Indicates if last faulted core access was cacheable.

0 Non-cacheable

1 Cacheable

MODE

TYPE

Reserved, should be cleared.

Indicates the mode the device was in during the last faulted core access.

0 User mode

1 Supervisor mode

Defines the type of last faulted core access.

0 Instruction

1 Data

11.2.11 Core Fault Data Register (CFDTR)

The CFDTR is a read-only register for capturing the data associated with the last faulted processor write data access from the device’s internal bus. The CFDTR is only valid for faulted internal bus write accesses,

CFLOC[LOC] = 0.

Address: 0xFC04_007C (CFDTR) Access: User read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CFDTR

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 11-18. Core Fault Data Register (CFDTR)

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System Control Module (SCM)

Table 11-13. CFDTR Field Descriptions

Field Description

31–0

CFDTR

Contains the data associated with the faulting access of the last internal bus write access. The register contains the data value taken directly from the write data bus.

11.3 Functional Description

11.3.1 Access Control

The SCM supports the traditional model of two privilege levels: supervisor and user. Typically, memory references with the supervisor attribute have total accessibility to all the resources in the system, while user mode references cannot access system control and configuration registers. In many systems, the operating system executes in supervisor mode, while application software executes in user mode.

The SCM further partitions the access control functions into two parts: one control register defines the privilege level associated with each bus master (MPR), and another set of control registers define the access levels associated with the peripheral modules (PACRx).

Each bus transaction targeted for the peripheral space is first checked to see if its privilege rights allow access to the given memory space. If the privilege rights are correct, the access proceeds on the internal bus. If the privilege rights are insufficient for the targeted memory space, the transfer is immediately aborted and terminated with an exception, and the targeted module not accessed.

11.3.2 Core Watchdog Timer

The core watchdog timer (CWT) prevents system lockup if the software becomes trapped in a loop with no controlled exit or if a bus transaction becomes hung. The core watchdog timer can be enabled through

CWCR[CWE]; it is disabled at reset. If enabled, the CWT requires the periodic execution of a core watchdog servicing sequence. If this periodic servicing action does not occur, the timer expires and, depending on the setting of CWCR[CWRI], different events may occur:

1. An interrupt may be generated to the core.

2. An immediate system reset.

3. Upon the first time-out, a watchdog timer interrupt is asserted. If this time-out condition is not serviced before a second time-out occurs, the CWT asserts a system reset. This configuration supports a more graceful response to watchdog time-outs.

4. In addition to these three basic modes of operation, the CWT also supports a windowed mode of operation. In this mode, the time-out period is divided into four equal segments and the entire service sequence of the CWT must occur during the last segment (last 25% of the time-out period).

If the timer is serviced anytime (any write to the CWSR register) in the first 75% of the time-out period, an immediate system reset occurs.

To prevent the core watchdog timer from interrupting or resetting, the CWSR register must be serviced by performing the following sequence:

1. Write 0x55 to CWSR.

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System Control Module (SCM)

2. Write 0xAA to CWSR.

Both writes must occur in order before the time-out, but any number of instructions can be executed between the two writes. This allows interrupts and exceptions to occur, if necessary, between the two writes.

NOTE

If the CWT is enabled and has not timed out, then any write of a data value other than 0x55 or 0xAA will cause an immediate system reset, regardless of the value in the CWCR[CWRI] field.

The timer value is constantly compared with the time-out period specified by CWCR[CWT], and any write to the CWCR register resets the watchdog timer. In addition, there is a write-once control bit in the CWCR that sets the CWCR to read-only to prevent accidental updates to this control register from changing the desired system configuration. Once this bit, CWCR[RO], is set, a system reset is required to clear it.

For certain values in the CWCR[CWRI] field, the CWT generates an interrupt response to a time-out. For these configurations, the SCMISR register provides a program visible interrupt request from the watchdog timer. During the interrupt service routine which handles this interrupt, the source must be explicitly cleared by writing a 0x01 to the SCMISR.

11.3.3 Core Data Fault Recovery Registers

To aid in recovery from certain types of access errors, the SCM module supports a number of registers that capture access address, attribute, and data information on bus cycles terminated with an error response.

These registers can then be read during the resulting exception service routine and the appropriate recovery performed.

The details on the core fault recovery registers are provided in the above sections. It is important to note these registers are used to capture fault recovery information on any processor-initiated system bus cycle that is terminated with an error.

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Chapter 12 Crossbar Switch (XBS)

12.1 Overview

This section provides information on the layout, configuration, and programming of the crossbar switch.

The crossbar switch connects the bus masters and bus slaves using a crossbar switch structure. This structure allows bus masters to access different bus slaves simultaneously with no interference while providing arbitration among the bus masters when they access the same slave. A variety of bus arbitration methods and attributes may be programmed on a slave by slave basis.

The MCF5208 devices have up to four masters and three slaves (4Mx3S) connected to the crossbar switch.

The four masters are the ColdFire core, eDMA controller, FEC, and a reserved master for factory test. The slaves are FlexBus/SDRAM controller, SRAM controller,and the peripheral bus controller.

Figure 12-1

is a block diagram of the MCF5208 family bus architecture showing the crossbar switch configuration.

ColdFire

Core eDMA

Controller

Fast Ethernet

Controller

Reserved for

Factory Test

M1 M2

Crossbar Switch

S4 S7

Master Modules

Slave Modules

FlexBus/SDRAM

Controller

SRAM

Backdoor

On-chip Slave

Peripherals

Figure 12-1. Bus Architecture Block Diagram

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Crossbar Switch (XBS)

The modules are assigned to the numbered ports on the crossbar switch in the below table.

Table 12-1. Crossbar Switch Master/Slave Assignments

Master Modules

Crossbar Port

Master 0 (M0)

Master 1 (M1)

Master 2 (M2)

Master 7 (M7)

Module

ColdFire core eDMA controller

Fast Ethernet controller

Reserved for factory test

Slave Modules

Crossbar Port Module

Address Range

Slave 1 (S1) Flexbus

SDRAM Controller

0x0000_0000–0x3FFF_FFFF &

0xC000_0000–0xDFFF_FFFF

0x4000_0000–0x7FFF_FFFF

Slave 4 (S4)

Slave 7 (S7)

Internal SRAM Backdoor 0x8000_0000–0x8FFF_FFFF

Other on-chip slave peripherals 0xF000_0000–0xFFFF_FFFF

Unused address spaces are reserved.

See the various peripheral chapters for their memory maps. Any unused space by these peripherals within this memory range is reserved and must not be accessed.

NOTE

This memory map provides two disjoint regions mapped to the FlexBus controller to support glueless connections to external memories (e.g., flash and SRAM) and a second space with one (or more) unique chip-selects that can be used for non-cacheable, non-memory devices (addresses

0xC000_0000–0xDFFF_FFFF). Additionally, this mapping is easily maps into the ColdFire access control registers, which provide a coarse association between memory addresses and their attributes (e.g., cacheable, non-cacheable). For this device, one possible configuration defines the default memory attribute as non-cacheable, and one ACR then identifies cacheable addresses, e.g., ADDR[31] equals 0 identifies the cacheable space.

12.2 Features

The crossbar switch includes these distinctive features:

• Symmetric crossbar bus switch implementation

— Allows concurrent accesses from different masters to different slaves

— Slave arbitration attributes configured on a slave by slave basis

• 32 bits wide and supports byte, word (2 byte), longword (4 byte), and 16 byte burst transfers

• Operates at a 1-to-1 clock frequency with the bus masters

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Crossbar Switch (XBS)

12.3 Modes of Operation

The crossbar switch supports two arbitration modes (fixed or round-robin), which may be set on a slave by slave basis. Slaves configured for fixed arbitration mode have a unique arbitration level assigned to each bus master.

In fixed priority mode, the highest priority active master accessing a particular slave is granted the master

bus path to that slave. A higher priority master blocks access to a given slave from a lower priority master

if the higher priority master continuously requests that slave. See Section 12.5.1.1, “Fixed-Priority

Operation.”

In round-robin arbitration, active masters accessing a particular slave are initially granted the slave based on their master port number. Master priority is then modified in a wrap-around manner to give all masters

fair access to the slave. See Section 12.5.1.2, “Round-Robin Priority Operation.”

12.4 Memory Map / Register Definition

Two registers reside in each slave port of the crossbar switch. Read- and write-transfers require two bus clock cycles. The registers can only be read from and written to in supervisor mode. Additionally, these registers can only be read from or written to by 32-bit accesses.

A bus error response is returned if an unimplemented location is accessed within the crossbar switch. See

Section 11.2.6, “SCM Interrupt Status Register (SCMISR).”

The slave registers also feature a bit that, when set, prevents the registers from being written. The registers remain readable, but future write attempts have no effect on the registers and are terminated with a bus error response to the master initiating the write. The core, for example, takes a bus error interrupt.

Table 12-2

shows the memory map for the crossbar switch program-visible registers.

Table 12-2. XBS Memory Map

Address Register

0xFC00_4100 Priority Register Slave 1 (XBS_PRS1)

0xFC00_4110 Control Register Slave 1 (XBS_CRS1)

0xFC00_4400 Priority Register Slave 4 (XBS_PRS4)

0xFC00_4410 Control Register Slave 4 (XBS_CRS4)

0xFC00_4700 Priority Register Slave 7 (XBS_PRS7)

0xFC00_4710 Control Register Slave 7 (XBS_CRS7)

Width

(bits)

Access Reset Value Section/Page

R/W

0x3000_0210

0x0000_0000

0x3000_0210

0x0000_0000

0x3000_0210

0x0000_0000

12.4.1 XBS Priority Registers (XBS_PRS

)

The priority registers (XBS_PRSn) set the priority of each master port on a per slave port basis and reside

in each slave port. The priority register can be accessed only with 32-bit accesses. After the

XBS_CRSn[RO] bit is set, the XBS_PRSn register can only be read; attempts to write to it have no effect on XBS_PRSn and result in a bus-error response to the master initiating the write.

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Crossbar Switch (XBS)

Additionally, no two available master ports may be programmed with the same priority level, including reserved masters. Attempts to program two or more masters with the same priority level result in a

bus-error response (see Section 11.2.6, “SCM Interrupt Status Register (SCMISR)”

) and the XBS_PRSn is not updated.

Address: 0xFC00_4100 (XBS_PRS1)

0xFC00_4400 (XBS_PRS4)

0xFC00_4700 (XBS_PRS7)

Access: Supervisor read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0

Figure 12-2. XBS Priority Registers Slave n (XBS_PRSn)

Table 12-3. XBS_PRSn Field Descriptions

Field Description

30–28

Reserved, must be cleared.

Master 7 (Factory Test) priority. Sets the arbitration priority for this port on the associated slave port.

000 This master has level 1 (highest) priority when accessing the slave port.

001 This master has level 2 priority when accessing the slave port.

010 This master has level 3 priority when accessing the slave port.

011 This master has level 4 (lowest) priority when accessing the slave port.

Else Reserved

27–11 Reserved, must be cleared.

10–8

Master 2 (FEC) priority. See M7 description.

6–4

Reserved, must be cleared.

Master 1 (eDMA) priority. See M7 description.

2–0

Reserved, must be cleared.

Master 0 (ColdFire core) priority. See M7 description.

NOTE

The possible values for the XBS_PRSn fields depend on the number of masters available on the device. Because the device contains four masters

(including reserved masters), valid values are 000 to 011. Unpredictable results occur when using the reserved settings 100 to 111.

12.4.2 XBS Control Registers (XBS_CRSn)

The XBS control registers (XBS_CRSn) control several features of each slave port and must be accessed using 32-bit accesses. After XBS_CRSn[RO] is set, the XBS_CRSn can only be read; attempts to write to it have no effect and result in an error response.

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Crossbar Switch (XBS)

Address: 0xFC00_4110 (XBS_PRS1)

0xFC00_4410 (XBS_PRS4)

0xFC00_4710 (XBS_PRS7)

Access: Supervisor read/write

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ARB

7 6 5 4 3 2 1 0

0 0

PCTL

PARK

Reset 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

After this bit is set, only a hardware reset clears it.

0 0 0 0 0 0 0 0 0

Figure 12-3. XBS Control Registers Slave n (XBS_CRSn)

Table 12-4. XBS_CRSn Field Descriptions

Field Description

Read only. Forces both of the slave port’s registers (XBS_CRSn and XBS_PRSn) to be read-only. After set, onlya hardware reset clears it.

0 Both of the slave port’s registers are writteable.

1 Both of the slave port’s registers are read-only and cannot be written (attempted writes have no effect on the registers and result in a bus error response).

30–9 Reserved, must be cleared.

ARB

Arbitration Mode. Selects the arbitration policy for the slave port.

0 Fixed priority

1 Round robin (rotating) priority

7–6

5–4

PCTL

2–0

PARK

Reserved, must be cleared.

Parking control. Determines the slave port’s parking control. The low-power park feature results in an overall power savings if the slave port is not saturated; however, this forces an extra latency clock when any master tries to access the slave port while not in use because it is not parked on any master.

00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK bit field.

01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port.

10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state.

11 Reserved.

Reserved, must be cleared.

Park. Determines which master port the current slave port parks on when no masters are actively making requests and the PCTL bits are cleared.

000 Park on master port M0 (ColdFire Core)

001 Park on master port M1 (eDMA Controller)

010 Park on master port M2 (FEC)

Else Reserved

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12.5 Functional Description

12.5.1 Arbitration

The crossbar switch supports two arbitration schemes: a simple fixed-priority comparison algorithm and a simple round-robin fairness algorithm. The arbitration scheme is independently programmable for each slave port.

12.5.1.1

Fixed-Priority Operation

When operating in fixed-priority mode, each master is assigned a unique priority level in the XBS_PRSn

(priority registers). If two masters request access to a slave port, the master with the highest priority in the selected priority register gains control over the slave port.

When a master makes a request to a slave port, the slave port checks if the new requesting master’s priority level is higher than that of the master that currently has control over the slave port (unless the slave port is in a parked state). The slave port does an arbitration check at every bus transfer boundary makes certain that the proper master (if any) has control of the slave port.

If the new requesting master’s priority level is higher than that of the master that currently has control of the slave port, the new requesting master is granted control over the slave port at the next clock edge. The exception to this rule is if the master that currently has control over the slave port is running a fixed length burst transfer or a locked transfer. In this case, the new requesting master must wait until the end of the burst transfer or locked transfer before it is granted control of the slave port.

If the new requesting master’s priority level is lower than the master that currently has control of the slave port, the new requesting master is forced to wait until the current master runs one of the following cycles:

• An IDLE cycle

• A non-IDLE cycle to a location other than the current slave port.

12.5.1.2

Round-Robin Priority Operation

When operating in round-robin mode, each master is assigned a relative priority based on the master port number. This priority is based on how far ahead the master port number of the requesting master is to the master port number of the current bus master for this slave. Master port numbers are compared modulo the total number of bus masters, i.e. take the requesting master port number minus the current bus master’s port number modulo the total number of bus masters. The master port with the highest priority based on this comparison is granted control over the slave port at the next bus transfer boundary.

After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port at the next transfer boundary.

Parking may continue to be used in a round-robin mode, but does not affect the round-robin pointer unless the parked master actually performs a transfer. Handoff occurs to the next master in line after one cycle of arbitration. If the slave port is put into low-power park mode, the round-robin pointer is reset to point at master port 0, giving it the highest priority.

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12.5.1.3

Priority Assignment

Each master port needs to be assigned a unique 3-bit priority level. If an attempt is made to program multiple master ports with the same priority level within the priority registers (XBS_PRSn) the crossbar

switch responds with a bus error (refer to Section 11.2.6, “SCM Interrupt Status Register (SCMISR)”

) and the registers are not updated.

12.6 Initialization/Application Information

No initialization is required by or for the crossbar switch. Hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state. Settings and priorities should be programmed to achieve maximum system performance.

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Chapter 13 General Purpose I/O Module

13.1 Introduction

Many of the pins associated with the device may be used for several different functions. Their primary functions are to provide external interfaces to access off-chip resources. When not used for their primary function, many of the pins may be used as general-purpose digital I/O (GPIO) pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.

Each GPIO port has registers that configure, monitor, and control the port pins.

Figure 13-1

is a block diagram of the device ports. The GPIO functionality of the port IRQ pins is selected by the edge port module. They are shown in the below figure only for completeness.

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General Purpose I/O Module

Port

FECH

Port

FECL

Port

BUSCTL

Port

FEC_TXCLK / PFECH7

FEC_TXEN / U1RTS / PFECH6

FEC_TXD0 / PFECH5

FEC_COL / PFECH4

FEC_RXCLK / PFECH3

FEC_RXDV / PFECH2

FEC_RXD0 / PFECH1

FEC_CRS / PFECH0

FEC_TXD[3:1] / PFECL[7:5]

FEC_TXER / U0RTS / PFECL4

FEC_RXD[3:2] / PFECL[3:2]

FEC_RXD1 / U1CTS / PFECL1

FEC_RXER / U0CTS / PFECL0

OE / PBUSCTL3

TA / PBUSCTL2

R/W / PBUSCTL1

TS / DACK0 / PBUSCTL0

BE/BWE[3:0] / SD_DQM[3:0] / PBE[3:0]

Port

FECI2C

Port

UART

Port

QSPI

Port

TIMER

FB_CS[3:2] / PCS[3:2]

FB_CS1 / SD_CS1 / PCS1

Port

IRQ

Pin Assignment Control

FEC_MDC / I2C_SCL / U2TXD / PFECI2C3

FEC_MDIO / I2C_SDA / U2RXD / PFECI2C2

I2C_SCL / U2TXD / PFECI2C1

I2C_SDA / U2RXD / PFECI2C0

U1CTS / DT1IN / QSPI_CS1 / PUART7

U1RTS / DT1OUT / QSPI_CS1 / PUART6

U1TXD / PUART5

U1RXD / PUART4

U0CTS / DT0IN / QSPI_CS0 / PUART3

U0RTS / DT0OUT / QSPI_CS0 / PUART2

U0TXD / PUART1

U0RXD / PUART0

QSPI_CS2 / DACK0 / U2RTS / PQSPI3

QSPI_DIN / DREQ0 / U2CTS / PQSPI2

QSPI_DOUT / I2C_SDA / PQSPI1

QSPI_CLK / I2C_SCL / PQSPI0

DT3IN / DT3OUT / U2CTS / PTIMER3

DT2IN / DT2OUT / U2RTS / PTIMER2

DT1IN / DT1OUT / U2RXD / PTIMER1

DT0IN / DT0OUT / U2TXD / PTIMER0

IRQ[7,1] / PIRQ[7,1]

IRQ4 / DREQ0 / PIRQ4

Drive Strength Control

Internal Bus

Figure 13-1. Ports Module Block Diagram

13.1.1 Overview

The GPIO module controls the configuration for various external pins, including those used for:

• External bus accesses

• External chip selection

• Ethernet data and control

• I

C serial control

• QSPI

• 32-bit DMA timers

• FEC

• UART

MCF5208 Reference Manual, Rev 2

13-2 Freescale Semiconductor

General Purpose I/O Module

13.1.2 Features

The ports module includes these distinctive features:

• Control of primary function use

— On all supported GPIO ports

— On pins whose GPIO is not supported by ports module: IRQ4

• General purpose I/O support for all ports

— Registers for storing output pin data

— Registers for controlling pin data direction

— Registers for reading current pin state

— Registers for setting and clearing output pin data registers

13.2 External Signal Description

The GPIO module controls the functionality of several external pins. These pins are listed in

Table 13-2

under the GPIO column.

After reset ports BUSCTL, BE and CS are configured for external memory. They are available for the user as GPIO if the corresponding registers are set appropriately. All other ports default to GPIO after reset.

NOTE

The primary functionality of a pin is not necessarily its default functionality.

Pins that are muxed with GPIO default to their GPIO functionality.

Table 13-1. MCF5207/8 Signal Information and Muxing

Signal Name GPIO Alternate 1 Alternate 2

MCF5207

144

LQFP

MCF5207

144

MAPBGA

MCF5208

160

QFP

MCF5208

196

MAPBGA

RESET

RSTOUT

EXTAL

XTAL

FB_CLK

—

Reset

I EVDD

O EVDD

Clock

I EVDD

O EVDD

O SDVDD

J10

M12

K12

J12

J14

N14

L14

K14

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 13-3

General Purpose I/O Module

Signal Name

RCON

DRAMSEL

A[23:22]

A[21:16]

A[15:14]

A[13:11]

A10

A[9:0]

D[31:16]

D[15:0]

BE/BWE[3:0]

R/W

FB_CS[3:2]

FB_CS1

Table 13-1. MCF5207/8 Signal Information and Muxing (continued)

GPIO

—

PBE[3:0]

PBUSCTL3

PBUSCTL2

PBUSCTL1

PBUSCTL0

PCS[3:2]

PCS1

Alternate 1

—

FB_CS[5:4]

—

SD_BA[1:0]

SD_A[13:11]

—

SD_A[9:0]

—

DACK0

—

SD_CS1

SD_D[31:16]

FB_D[31:16]

SD_DQM[3:0]

Alternate 2

MCF5207

144

LQFP

MCF5207

144

MAPBGA

MCF5208

160

QFP

MCF5208

196

MAPBGA

—

Mode Selection

FlexBus

EVDD

—

144

H10

160

K11

O SDVDD 118, 117

O SDVDD 116–114,

112, 108,

107

I/O

SDVDD

O SDVDD

SDVDD

106, 105

104–102

101

100–91

21–28,

40–47

B9, A10

C9, A11,

B10, A12,

C11, B11

B12, C12

D11, E10,

D12

C10

E11, D9,

E12, F10,

F11, E9,

F12, G10,

G12, F9

F1, F2, G1,

G2, G4, G3,

H1, H2, K3,

L2, L3, K2,

M3, J4, M4,

126, 125

124, 123,

122, 120,

116, 115

114, 113

112, 111,

110

109

108–99

27–34,

46–53

B11, A11

B12, A12,

A13, B13,

B14, C13

C14, D12

D13, D14,

E11

E12

E13, E14,

F11–F14,

G11–G14

J4–J1,

K4–K1, M3,

N3, M4, N4,

P4, L5, M5,

I/O SDVDD 8–15, 51–58 B2, B1, C2,

C1, D2, D1,

E2, E1, L5,

K5, L6, J6,

M6, J7, L7,

O SDVDD 20, 48, 18,

F4, L4, E3,

16–23,

57–64

F3–F1,

G4–G1, H1,

N6, P6, L7,

M7, N7, P7,

N8, P8

26, 54, 24,

H2, P5, H4,

O SDVDD

I SDVDD

O SDVDD

G11

H14

—

Chip Selects

O SDVDD 119, 120

O SDVDD 121

D7, A9

—

127

C11, A10

B10

MCF5208 Reference Manual, Rev 2

13-4 Freescale Semiconductor

General Purpose I/O Module

Signal Name

FB_CS0

SD_A10

SD_CKE

SD_CLK

SD_CS0

SD_DQS[3:2]

SD_SCAS

SD_SRAS

SD_SDR_DQS

SD_WE

IRQ7

IRQ4

IRQ1

FEC_MDC

FEC_MDIO

FEC_TXCLK

—

FEC_TXEN

FEC_TXD0

FEC_COL

FEC_RXCLK

PFECI2C3

PFECI2C2

PFECH7

PFECH6

PFECH5

PFECH4

PFECH3

FEC_RXDV

FEC_RXD0

PFECH2

PFECH1

FEC_CRS PFECH0

FEC_TXD[3:1] PFECL[7:5]

—

FEC_TXER

PFECL4

—

GPIO

—

Table 13-1. MCF5207/8 Signal Information and Muxing (continued)

PIRQ7

PIRQ4

PIRQ1

—

I2C_SCL

I2C_SDA

—

Alternate 1

—

Alternate 2

— O SDVDD

SDRAM Controller

MCF5207

144

LQFP

122

—

DREQ0

—

U2TXD

U2RXD

—

U1RTS

—

U0RTS

—

SDVDD

— O SDVDD

External Interrupts Port

19, 49

—

FEC

EVDD

134

133

132

O EVDD

I/O EVDD

I EVDD

O EVDD

EVDD

I EVDD

EVDD

I EVDD

O EVDD

—

141

—

142

MCF5207

144

MAPBGA

F3, M5

—

MCF5208

160

QFP

128

142

141

140

25, 55

153

152

6–4

—

156

158

154

148

147

157

—

MCF5208

196

MAPBGA

C10

H3, L6

C1, C2, B2

—

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 13-5

General Purpose I/O Module

Table 13-1. MCF5207/8 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

MCF5207

144

LQFP

MCF5207

144

MAPBGA

MCF5208

160

QFP

MCF5208

196

MAPBGA

FEC_RXD[3:2] PFECL[3:2]

— PFECL1

FEC_RXD1

—

PFECL1

PFECL0

—

U1CTS

U0CTS I

I EVDD

EVDD

—

139

—

140

—

149–150

—

151

—

A5, B5

—

FEC_RXER PFECL0 — U0CTS I EVDD — — 155 C4

Note: The MCF5207 does not contain an FEC module. However, the UART0 and UART1 control signals (as well as their GPIO signals) are available by setting the appropriate FEC GPIO port registers.

I2C_SDA

I2C_SCL

PFECI2C0

PFECI2C1

U2RXD

U2TXD

—

I/O

EVDD

—

DMA

DACK0 and DREQ0 do not have a dedicated bond pads. Please refer to the following pins for muxing:

TS and QSPI_CS2 for DACK0, IRQ4 and QSPI_DIN for DREQ0.

QSPI

QSPI_CS2

QSPI_CLK

QSPI_DOUT

QSPI_DIN

PQSPI3

PQSPI0

PQSPI1

PQSPI2

DACK0

I2C_SCL

I2C_SDA

DREQ0

U2RTS

—

U2CTS

EVDD

126

127

128

129

132

133

134

135

D10

Note: The QSPI_CS1 and QSPI_CS0 signals are available on the U1CTS, U1RTS, U0CTS, or U0RTS pins for the 196 and 160-pin packages.

UARTs

U1CTS

U1RTS

U1TXD

U1RXD

PUARTL7

PUARTL6

PUARTL5

PUARTL4

DT1IN

DT1OUT

—

QSPI_CS1 I EVDD

QSPI_CS1 O EVDD

—

EVDD

—

131

130

—

136

137

139

138

U0CTS

U0RTS

U0TXD

U0RXD

PUARTL3

PUARTL2

PUARTL1

PUARTL0

DT0IN

DT0OUT

—

QSPI_CS0 I EVDD

QSPI_CS0 O EVDD

—

EVDD

—

L10

M10

N12

P12

P13

N13

Note: The UART2 signals are multiplexed on the DMA Timers, QSPI, FEC, and I2C pins. For the MCF5207 devices, the UART0 and

UART1 control signals are multiplexed internally on the FEC signals.

MCF5208 Reference Manual, Rev 2

13-6 Freescale Semiconductor

Signal Name

DT3IN

DT2IN

DT1IN

DT0IN

JTAG_EN

DSCLK

PSTCLK

BKPT

DSI

DSO

DDATA[3:0]

PST[3:0]

ALLPST

TEST

PLL_TEST

EVDD

IVDD

PLL_VDD

General Purpose I/O Module

—

GPIO

PTIMER3

PTIMER2

PTIMER1

PTIMER0

—

Table 13-1. MCF5207/8 Signal Information and Muxing (continued)

Alternate 1

DT3OUT

DT2OUT

DT1OUT

DT0OUT

—

TRST

—

TCLK

TMS

TDI

TDO

—

Alternate 2

MCF5207

144

LQFP

MCF5207

144

MAPBGA

MCF5208

160

QFP

MCF5208

196

MAPBGA

—

DMA Timers

U2CTS

U2RTS I

I EVDD

EVDD

U2RXD I EVDD

U2TXD I EVDD

BDM/JTAG

—

EVDD

O EVDD

I EVDD

O EVDD

EVDD

135

136

137

138

—

J11

K11

L12

K9, L9, M11,

L11, L8,

K10, K8

—

143

144

145

146

—

O EVDD

Test

I EVDD

EVDD

—

Power Supplies

— —

—

109

—

C12

M13

1, 33, 63,

66, 72, 81,

87, 125

30, 68, 84,

113, 143

E5–E6, F5,

G8–G9,

H7–H8

2, 9, 69, 72,

80, 89, 95,

131

E5–E7, F5,

F6, G5,

H10, J9,

J10,

K8–K10,

K13, M9

D4, D8, H4,

H11, J9

36, 74, 92,

121, 159

J12, D4,

D11, H11,

L4, L11,

86 H12 94 H13

J13

L12

M14

K12

M12

P11, N11,

M11, P10

N10, M10,

L10, L9

—

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 13-7

General Purpose I/O Module

Table 13-1. MCF5207/8 Signal Information and Muxing (continued)

Signal Name GPIO Alternate 1 Alternate 2

MCF5207

144

LQFP

MCF5207

144

MAPBGA

MCF5208

160

QFP

MCF5208

196

MAPBGA

SD_VDD

VSS

—

3, 17, 35,

61, 89, 110,

123

E7–E8, F8,

G5, H5–H6,

11, 39, 41,

67, 97, 118,

129

E8–E10, F9,

F10, G10,

H5, J5, J6,

K5–K7, L2

2, 16, 36,

62, 65, 73,

88, 111, 124

D10, F6–F7,

G6–G7

1, 10, 42,

68, 71, 81,

96, 117,

119, 130

A1, A14,

F7–F8,

G6–G9,

H6–H9,

J7–J8, L13,

M2, N9, P1,

P14

PLL_VSS — — — — — 85 — 93 H12

Refers to pin’s primary function.

Pull-up enabled internally on this signal for this mode.

The SDRAM functions of these signals are not programmable by the user. They are dynamically switched by the processor when accessing SDRAM memory space and are included here for completeness.

Primary functionality selected by asserting the DRAMSEL signal (SDR mode). Alternate functionality selected by negating the

DRAMSEL signal (DDR mode). The GPIO module is not responsible for assigning these pins.

GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.

If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.

Pull-down enabled internally on this signal for this mode.

Refer to the Chapter 2, “Signal Descriptions,”

for more detailed descriptions of these pins and other pins not controlled by the ports module. The function of most of the pins (primary function, GPIO, etc.) is determined by the ports module pin assignment registers.

It should be noted from

Table 13-2 that there are several cases where a function is available on more than

one pin. While it is possible to enable the function on more than one pin simultaneously, this type of programming should be avoided for input functions to prevent unexpected behavior. All multiple-pin functions are listed in

Table 13-2

Table 13-2. Multiple-Pin Functions

Function

DACK0

DREQ0

I2C_SCL

I2C_SDA

U2CTS

U2RTS

Direction

I/O

Associated Pins

QSPI_CS2, TS

IRQ4, QSPI_DIN

I2C_SCL, QSPI_CLK, FEC_MDC

I2C_SDA, QSPI_DOUT, FEC_MDIO

DT3IN, QSPI_DIN

DT2IN, QSPI_CS2

MCF5208 Reference Manual, Rev 2

13-8 Freescale Semiconductor

General Purpose I/O Module

Function

U2TXD

U2RXD

DT0IN

DT0OUT

DT1IN

DT1OUT

QSPI_CS0

QSPI_CS1

Table 13-2. Multiple-Pin Functions (continued)

Direction

Associated Pins

DT0IN, FEC_MDC, I2C_SCL

DT1IN, FEC_MDIO, I2C_SDA

DT0IN, U0CTS

DT0IN, U0RTS

DT1IN, U1CTS

DT1IN, U1RTS

U0CTS, U0RTS

U1CTS, U1RTS

13.3 Memory Map/Register Definition

Table 13-3

summarizes all the registers in the ports address space.

Table 13-3. GPIO Module Memory Map

Address

0xFC0A_4000 PODR_BUSCTL

0xFC0A_4001 PODR_BE

0xFC0A_4002 PODR_CS

0xFC0A_4003 PODR_FECI2C

0xFC0A_4004 PODR_QSPI

0xFC0A_4005 PODR_TIMER

0xFC0A_4006 PODR_UART

0xFC0A_4007 PODR_FECH

0xFC0A_4008 PODR_FECL

0xFC0A_400C PDDR_BUSCTL

0xFC0A_400D PDDR_BE

0xFC0A_400E PDDR_CS

0xFC0A_400F PDDR_FECI2C

0xFC0A_4010 PDDR_QSPI

0xFC0A_4011 PDDR_TIMER

0xFC0A_4012 PDDR_UART

Register

Port Output Data Registers

Width

(bits)

Access Reset Value Section/Page

R/W

0x0F

0x0E

0x0F

0xFF

13.3.1/13-11

Port Data Direction Registers

R/W

0x00

13.3.2/13-12

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 13-9

General Purpose I/O Module

Address

0xFC0A_4013 PDDR_FECH

0xFC0A_4014 PDDR_FECL

0xFC0A_401A PPDSDR_CS

0xFC0A_401B PPDSDR_FECI2C

0xFC0A_401C PPDSDR_QSPI

0xFC0A_401D PPDSDR_TIMER

0xFC0A_401E PPDSDR_UART

0xFC0A_401F PPDSDR_FECH

0xFC0A_4020 PPDSDR_FECL

0xFC0A_4024 PCLRR_BUSCTL

0xFC0A_4025 PCLRR_BE

0xFC0A_4026 PCLRR_CS

0xFC0A_4027 PCLRR_FECI2C

0xFC0A_4028 PCLRR_QSPI

0xFC0A_4029 PCLRR_TIMER

0xFC0A_402A PCLRR_UART

0xFC0A_402B PCLRR_FECH

0xFC0A_402C PCLRR_FECL

0xFC0A_4030 PAR_BUSCTL

0xFC0A_4031 PAR_BE

0xFC0A_4032 PAR_CS

0xFC0A_4033 PAR_FECI2C

0xFC0A_4034 PAR_QSPI

0xFC0A_4035 PAR_TIMER

0xFC0A_4036 PAR_UART

0xFC0A_4038 PAR_FEC

0xFC0A_4039 PAR_IRQ

Table 13-3. GPIO Module Memory Map (continued)

Register

Width

(bits)

Access Reset Value Section/Page

Port Pin Data/Set Data Registers

R/W

0x00

13.3.2/13-12

Port Clear Output Data Registers

R/W

See Section

See Section

See Section

See Section

See Section

See Section

See Section

0x00

Pin Assignment Registers

R/W

0x1F

0x0F

0x00

0x0000

0x00

Mode Select Control Registers

MCF5208 Reference Manual, Rev 2

13-10 Freescale Semiconductor

General Purpose I/O Module

Address

0xFC0A_403A MSCR_FLEXBUS

0xFC0A_403B MSCR_SDRAM

0xFC0A_403C DSCR_I2C

0xFC0A_403D DSCR_MISC

0xFC0A_403E DSCR_FEC

0xFC0A_403F DSCR_UART

0xFC0A_4040 DSCR_QSPI

Table 13-3. GPIO Module Memory Map (continued)

Register

Width

(bits)

Access Reset Value Section/Page

Drive Strength Control Registers

R/W

0xFF

0x3F

13.3.6/13-23

13.3.7/13-24

R/W

See Section

See Section

See Section

See Section

See Section

13.3.1 Port Output Data Registers (PODR_x)

The PODR_x registers store the data to be driven on the corresponding port pins when the pins are configured for general purpose output. The PODR_x registers are each eight bits wide, but not all ports use all eight bits. The register definitions for all ports are shown in the below figures. The PODR_x registers are read/write. At reset, all implemented bits in the PODR_x registers are set. Reserved bits always remain cleared.

Reading a PODR_x register returns the current values in the register, not the port pin values. To set bits in a PODR_x register, set the PODR_x bits, or set the corresponding bits in the PPDSDR_x register. To clear bits in a PODR_x register, clear the PODR_x bits, or clear the corresponding bits in the PCLRR_x register.

Address: 0xFC0A_4000 (PODR_BUSCTL)

0xFC0A_4001 (PODR_BE)

0xFC0A_4003 (PODR_FECI2C)

0xFC0A_4004 (PODR_QSPI)

0xFC0A_4005 (PODR_TIMER)

0 R

Reset: 0

3 2

0 0 0 1 1

Figure 13-2. Port x Output Data Registers (PODR_x)

Access: User read/write

PODR_x

Address: 0xFC0A_4002 (PODR_CS)

0 R

Reset: 0

3 2

PODR_CS

0 0 0 1 1

Figure 13-3. Port CS Output Data Register (PODR_CS)

Access: User read/write

1 0

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 13-11

General Purpose I/O Module

Address: 0xFC0A_4006 (PODR_UART)

0xFC0A_4007 (PODR_FECH)

0xFC0A_4008 (PODR_FECL)

7 6

Reset: 1

5 4

PODR_x

3 2

1 1 1 1 1

Figure 13-4. Port x Output Data Registers (PODR_x)

Table 13-4. PODR_x Field Descriptions

Field Description

PODR_x Port x output data bits.

0 Drives 0 when the port x pin is general purpose output

1 Drives 1 when the port x pin is general purpose output

Note: See above figures for bit field positions.

Access: User read/write

13.3.2 Port Data Direction Registers (PDDR_x)

The PDDRs control the direction of the port pin drivers when the pins are configured for GPIO. The

PDDR_x registers are each eight bits wide, but not all ports use all eight bits. The register definitions for all ports are shown in the figures below.

The PDDRs are read/write. At reset, all bits in the PDDRs are cleared. Setting any bit in a PDDR_x register configures the corresponding port pin as an output. Clearing any bit in a PDDR_x register configures the corresponding pin as an input.

Address: 0xFC0A_400C (PDDR_BUSCTL)

0xFC0A_400D (PDDR_BE)

0xFC0A_400F (PDDR_FECI2C)

0xFC0A_4010 (PDDR_QSPI)

0xFC0A_4011 (PDDR_TIMER)

0 R

Reset: 0

3 2

0 0 0 0 0

Figure 13-5. Port Data Direction Registers (PDDR_x)

Access: User read/write

PDDR_x

13-12

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

General Purpose I/O Module

Address: 0xFC0A_400E (PDDR_CS)

0 R

Reset: 0

3 2

PDDR_CS

0 0 0 0 0

Figure 13-6. Port CS Data Direction Register (PDDR_CS)

Access: User read/write

1 0

0 0

Address: 0xFC0A_4012 (PDDR_UART)

0xFC0A_4013 (PDDR_FECH)

0xFC0A_4014 (PDDR_FECL)

7 6

Reset: 0

5 4

PDDR_x

3 2

0 0 0 0 0

Figure 13-7. Port Data Direction Registers (PDDR_x)

Table 13-5. PDDR_x Field Descriptions

Description Field

PDDR_x Port x output data direction bits.

1 Port x pin configured as output

0 Port x pin configured as input

Note: See above figures for bit field positions.

Access: User read/write

13.3.3 Port Pin Data/Set Data Registers (PPDSDR_x)

The PPDSDR registers reflect the current pin states and control the setting of output pins when the pin is configured for GPIO. The PPDSDR_x registers are each eight bits wide, but not all ports use all eight bits.

The register definitions for all ports are shown in the below figures.

The PPDSDR_x registers are read/write. At reset, the bits in the PPDSDR_x registers are set to the current pin states. Reading a PPDSDR_x register returns the current state of the port x pins. Setting a PPDSDR_x register sets the corresponding bits in the PODR_x register. Writing 0s has no effect.

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

13-13

General Purpose I/O Module

Address: 0xFC0A_4018 (PPDSDR_BUSCTL)

0xFC0A_4019 (PPDSDR_BE)

0xFC0A_401B (PPDSDR_FECI2C)

0xFC0A_401C (PPDSDR_QSPI)

0xFC0A_401D (PPDSDR_TIMER)

Reset:

3 2

PPDR_x

PSDR_x

[Px2] [Px1] 0 0 0 [Px3]

Figure 13-8. Port Pin Data/Set Data Registers (PPDSDR_x)

Access: User read/write

[Px0]

Address: 0xFC0A_401A (PPDSDR_CS)

Reset:

3 2

PPDR_CS

PSDR_CS

[PCS2]

Access: User read/write

0 0 0 [PCS3]

Figure 13-9. Port CS Pin Data/Set Data Register (PPDSDR_CS)

[PCS1]

Address: 0xFC0A_401E (PPDSDR_UART)

0xFC0A_401F (PPDSDR_FECH)

0xFC0A_4020 (PPDSDR_FECL)

Reset:

Access: User read/write

[Px7]

6 5 4 3

PPDR_x

PSDR_x

[Px4] [Px3]

[Px6] [Px5] [Px2]

Figure 13-10. Port Pin Data/Set Data Registers (PPDSDR_x)

[Px1]

[Px0]

Table 13-6. PPDSDR_x Field Descriptions

Description Field

PPDR_x

(read)

Port x pin data bits.

0 Port x pin state is 0

1 Port x pin state is 1

PSDR_x

(write)

Port x set data bits.

0 No effect.

1 Set corresponding PODR_x bit.

Note: See above figures for bit field positions.

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13.3.4 Port Clear Output Data Registers (PCLRR_x)

Clearing a PCLRR_x register clears the corresponding bits in the PODR_x register. Setting it has no effect.

Reading the PCLRR_x register returns 0s. The PCLRR_x registers are each eight bits wide, but not all ports use all eight bits. The register definitions for all ports are shown in the figures below.

Address: 0xFC0A_4024 (PCLRR_BUSCTL)

0xFC0A_4025 (PCLRR_BE)

0xFC0A_4027 (PCLRR_FECI2C)

0xFC0A_4028 (PCLRR_QSPI)

0xFC0A_4029 (PCLRR_TIMER)

Reset:

PCLRR_x

0 0 0 0

Figure 13-11. Port Clear Output Data Registers (PCLRR_x)

Access: User write-only

Address: 0xFC0A_4026 (PCLRR_CS)

Reset:

Access: User write-only

PCLRR_CS

0 0 0 0 0

Figure 13-12. Port CS Clear Output Data Register (PCLRR_CS)

Address: 0xFC0A_402A (PCLRR_UART)

0xFC0A_402B (PCLRR_FECH)

0xFC0A_402C (PCLRR_FECL)

Reset:

PCLRR_x

0 0 0 0 0

Figure 13-13. Port Clear Output Data Registers (PCLRR_x)

Access: User write-only

Table 13-7. PCLRR_x Field Descriptions

Description Field

PCLRR_x Port x clear data bits.

0 Clears corresponding PODR_x bit

1 No effect

Note: See above figures for bit field positions.

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General Purpose I/O Module

13.3.5 Pin Assignment Registers (PAR_x)

The pin assignment registers control which functions are currently active on the external pins. All pin assignment registers are read/write.

13.3.5.1

External Bus Control Pin Assignment Register (PAR_BUSCTL)

The PAR_BUSCTL register controls the functions of the external bus control signal pins.

Address: 0xFC0A_4030 (PAR_BUSCTL) Access: User read/write

Reset:

PAR_OE

3 2

PAR_TA PAR_RWB

PAR_TS

0 0 0 1 1 1 1

Figure 13-14. External Bus Control Pin Assignment Register (PAR_BUSCTL)

Table 13-8. PAR_BUSCTL Field Descriptions

Field Description

7–5

PAR_OE

Reserved, should be cleared.

0 OE pin configured for GPIO

1 OE pin configured for external bus OE function

PAR_TA

0 TA pin configured for GPIO

1 TA pin configured for external bus TA function

PAR_RWB

0 R/W pin configured for GPIO

1 R/W pin configured for external bus read/write function

1–0

PAR_TS

0x TS pin configured for GPIO

10 TS pin configured for DMA acknowledge 0 function

11 TS pin configured for external bus TS function

13.3.5.2

Byte Enable Pin Assignment Register (PAR_BE)

The PAR_BE register controls the functions of the byte enable pins.

Address: 0xFC0A_4031 (PAR_BE)

0 R

Reset:

3 2

Access: User read/write

1 0

PAR_BE

0 0 0 0 1 1

Figure 13-15. Byte Enable Pin Assignment Register (PAR_BE)

1 1

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General Purpose I/O Module

Table 13-9. PAR_BE Field Descriptions

Field Description

7–4

3–0

PAR_BE

Reserved, should be cleared.

BE/BWE[3:0] pin assignment. The PAR_BE[3:0] bits configure the BE/BWE[3:0] pins for their primary function or

GPIO.

0 BE/BWE[3:0] pin configured for GPIO

1 BE/BWE[3:0] pin configured for BE/BWE[3:0] function

Refer to

Chapter 9, “Chip Configuration Module (CCM)”

for more information on reset configuration.

13.3.5.3

Chip Select Pin Assignment Register (PAR_CS)

The PAR_CS register controls the functions of the FlexBus chip select pins.

Address: 0xFC0A_4032 (PAR_CS)

0 R

Reset:

3 2

PAR_CS3 PAR_CS2

Access: User read/write

1 0

0 0 0 0 1 1

Figure 13-16. Chip Select Pin Assignment Register (PAR_CS)

PAR_CS1

Table 13-10. PAR_CS Field Descriptions

Field Description

7–4 Reserved, should be cleared.

PAR_CS3

FB_CS3 pin assignment.

0 FB_CS3 pin configured for GPIO

1 FB_CS3 pin configured for FlexBus FB_CS3 function

PAR_CS2

FB_CS2 pin assignment.

0 FB_CS2 pin configured for GPIO

1 FB_CS2 pin configured for FlexBus FB_CS2 function

1–0

PAR_CS1

FB_CS1 pin assignment.

0x FB_CS1 pin configured for GPIO

10 FB_CS1 pin configured for SD_CS1 function

11 FB_CS1 pin configured for FlexBus FB_CS1 function

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General Purpose I/O Module

13.3.5.4

FEC/I2C Pin Assignment Register (PAR_FECI2C)

The PAR_FECI2C register controls the functions of the I

C and some of the FEC pins.

Address: 0xFC0A_4033 (PAR_FECI2C)

7 6 5

Reset: 0

PAR_MDC PAR_MDIO

4 3

PAR_SCL

0 0 0 0 0

Figure 13-17. FEC/I2C Pin Assignment (PAR_FECI2C)

Access: User read/write

PAR_SDA

Table 13-11. PAR_FECI2C Field Descriptions

Field Description

7–6

PAR_MDC

5–4

PAR_MDIO

3–2

PAR_SCL

1–0

PAR_SDA

FEC & I

C pin assignment. These bit fields configure the FEC_MDC, FEC_MDIO, I2C_SCL, and I2C_SDA pins for one of their primary functions or GPIO.

PAR_MDC

GPIO

U2TXD

PAR_MDIO

GPIO

U2RXD

PAR_SCL

GPIO

U2TXD

PAR_SDA

GPIO

U2RXD

10 I2C_SCL I2C_SDA GPIO GPIO

11 FEC_MDC FEC_MDIO I2C_SCL I2C_SDA

13.3.5.5

QSPI Pin Assignment Register (PAR_QSPI)

The PAR_QSPI register controls the functions of the QSPI pins.

Address: 0xFC0A_4034 (PAR_QSPI)

7 6

Reset: 0

PAR_PCS2

PAR_DIN

4 3

PAR_DOUT

0 0 0 0 0

Figure 13-18. QSPI Pin Assignment (PAR_QSPI)

Access: User read/write

1 0

PAR_SCK

0 0

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Table 13-12. PAR_QSPI Field Descriptions

Field Description

7–6

PAR_PCS2

5–4

PAR_DIN

3–2

PAR_DOUT

1–0

PAR_SCK

QSPI pin assignment. These bit fields configure the QSPI pins for one of their primary functions or GPIO.

PAR_PCS2

GPIO

U2RTS

DACK0

PAR_DIN

GPIO

U2CTS

DREQ0

PAR_DOUT

GPIO

I2C_SDA

PAR_SCK

GPIO

I2C_SCL

11 QSPI_PCS2 QSPI_DIN QSPI_DOUT QSPI_SCK

13.3.5.6

Timer Pin Assignment Registers (PAR_TIMER)

The PAR_TIMER register controls the functions of the DMA timer pins.

Address: 0xFC0A_4035 (PAR_TIMER)

7 6

Reset: 0

PAR_T3IN

PAR_T2IN

4 3

PAR_T1IN

0 0 0 0 0

Figure 13-19. Timer Pin Assignment (PAR_TIMER)

Table 13-13. PAR_TIMER Field Descriptions

Access: User read/write

1 0

PAR_T0IN

Field Description

7–6

PAR_T3IN

5–4

PAR_T2IN

3–2

PAR_T1IN

1–0

PAR_T0IN

DMA Timer pin assignment. These bit fields configure the DMA Timer pins for one of their primary functions or GPIO.

PAR_T3IN

GPIO

U2CTS

T3OUT

PAR_T2IN

GPIO

U2RTS

T2OUT

PAR_T1IN

GPIO

U2RXD

T1OUT

PAR_T0IN

GPIO

U2TXD

T0OUT

11 T3IN T2IN T1IN T0IN

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General Purpose I/O Module

13.3.5.7

UART Pin Assignment Register (PAR_UART)

The PAR_UART register controls the functions of the UART pins.

Address: 0xFC0A_4036 (PAR_UART)

R 0

Reset 0

Access: User read/write

11 10 9 8 7 6 5 4 3 2

PAR_U1CTS PAR_U1RTS

PAR_

U1TXD

PAR_

U1RXD

PAR_U0CTS PAR_U0RTS

0 0 0 0 0 0 0 0 0 0

Figure 13-20. UART Pin Assignment (PAR_UART)

1 0

PAR_

U0TXD

PAR_

U0RXD

0 0

Table 13-14. PAR_UART Field Descriptions

Field Description

15–12 Reserved, should be cleared.

11–10

PAR_U1CTS

9–8

PAR_U1RTS

7–6

PAR_U1RXD

5–4

PAR_U1TXD

UART1 control pin assignment. These bit fields configure the UART1 control pins for one of their primary functions or GPIO.

PAR_U1CTS

GPIO

QSPI_PCS1

PAR_U1RTS

GPIO

QSPI_PCS1

10 T1IN T1OUT

11 U1CTS U1RTS

PAR_U1TXD

U1TXD pin assignment.

0 U1TXD pin configured for GPIO

1 U1TXD pin configured for UART1 TXD function

PAR_U1RXD

U1RXD pin assignment.

0 U1RXD pin configured for GPIO

1 U1RXD pin configured for UART1 RXD function

5–4

PAR_U0CTS

3–2

PAR_U0RTS

UART0 control pin assignment. These bit fields configure the UART0 control pins for one of their primary functions or GPIO.

PAR_U0CTS PAR_U0RTS

00 GPIO GPIO

01 QSPI_PCS0 QSPI_PCS0

T0IN

U0CTS

T0OUT

U0RTS

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Table 13-14. PAR_UART Field Descriptions (continued)

Field

PAR_U0TXD

U0TXD pin assignment.

0 U0TXD pin configured for GPIO

1 U0TXD pin configured for UART0 TXD function

PAR_U0RXD

U0RXD pin assignment.

0 U0RXD pin configured for GPIO

1 U0RXD pin configured for UART0 RXD function

Description

13.3.5.8

FEC Pin Assignment Register (PAR_FEC)

The PAR_FEC register controls the functions of the FEC pins.

Field

7–4

Address: 0xFC0A_4038 (PAR_FEC)

0 R

Reset: 0

3 2

PAR_FEC_7W

0 0 0 0 0

Figure 13-21. FEC Pin Assignment (PAR_FEC)

Table 13-15. PAR_FEC Field Descriptions

Description

Reserved, should be cleared.

Access: User read/write

1 0

PAR_FEC_MII

0 0

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Table 13-15. PAR_FEC Field Descriptions (continued)

Field Description

3–2

PAR_FEC_7W

FEC 7-wire pin assignment. These bit fields configure the FEC_COL, FEC_RXCLK, FEC_RXDV, FEC_RXD0,

FEC_TXCLK, FEC_TXD0, and FEC_TXEN pins for one of their primary functions or GPIO.

FEC_COL FEC_RXCLK FEC_RXDV FEC_RXD0 FEC_TXCLK FEC_TXD0 FEC_TXEN

GPIO

FEC_COL

GPIO

FEC_RXCLK FEC_RXDV

GPIO

FEC_RXD0 FEC_TXCLK

GPIO

FEC_TXD0

GPIO

U1RTS

GPIO

FEC_TXEN

Note: The MCF5207 devices do not contain an FEC module. However, the U1RTS signal can be selected by the

appropriate setting in PAR_FEC_7W. See Table 13-1 for the location of this pin on the device.

1–0

PAR_FEC_MII

FEC MII pin assignment. These bit fields configure the FEC_CRS, FEC_RXD3, FEC_RXD2, FEC_RXD1,

FEC_RXER, FEC_TXD3, FEC_TXD2, FEC_TXD1 and FEC_TXER pins for one of their primary functions or GPIO.

FEC_RXD3 FEC_RXD2 FEC_RXD1 FEC_RXER

GPIO

U1CTS

GPIO

U0CTS

GPIO GPIO GPIO GPIO

FEC_RXD3 FEC_RXD2 FEC_RXD1 FEC_RXER

FEC_CRS

GPIO

FEC_CRS

FEC_TXD3 FEC_TXD2 FEC_TXD1 FEC_TXER

GPIO

FEC_TXD3

GPIO

FEC_TXD2

GPIO

FEC_TXD1

GPIO

U0RTS

GPIO

FEC_TXER

Note: The MCF5207 devices do not contain an FEC module. However, the U0RTS, U0CTS, and U1CTS signals

can be selected by the appropriate setting in PAR_FEC_MII. See Table 13-1 for the location of these pins

on the device.

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13.3.5.9

IRQ Pin Assignment Register (PAR_IRQ)

The PAR_IRQ register controls the functions of the IRQ4 pin.

Address: 0xFC0A_4039 (PAR_IRQ)

0 R

Reset: 0

0 0 0 0 0

Figure 13-22. IRQ Pin Assignment (PAR_IRQ)

Access: User read/write

0 1

PAR_IRQ4

0 0

Table 13-16. PAR_IRQ Field Descriptions

Field Description

7–1 Reserved, should be cleared.

PAR_IRQ4

IRQ4 pin assignment.

0 IRQ4 pin configured for IRQ4 function (if IRQ4 is enabled in the Edge Port module) or GPIO (if IRQ4 is disabled in the Edge Port module).

1 IRQ4 pin configured for DREQ0 function.

13.3.6 FlexBus Mode Select Control Register (MSCR_FLEXBUS)

The MSCR_FLEXBUS register controls the output mode selects of the following FlexBus pins:

FB_A[23:0], D[31:0], BE/BWE[3:0], OE, R/W, FB_CS[5:0], TA and TS.

Address: 0xFC0A_403A (MSCR_FLEXBUS)

7 6 5

Reset:

MSCR_FBCLK

MSCR_DUPPER

3 2

MSCR_DLOWER

Access: User read/write

1 0

MSCR_ADDRCTL

1 1 1 1 1 1 1

Figure 13-23. FlexBus Mode Select Control Register (MSCR_FLEXBUS)

Table 13-17. MSCR_FLEXBUS Field Descriptions

Field Description

7–6

MSCR_

FBCLK

FB_CLK mode select control. These bit fields control the strength of the FlexBus clock pin.

00 Half strength 1.8V low power/mobile DDR.

01 Open drain.

10 Full strength 1.8V low power/mobile DDR.

11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

5–4

MSCR_

DUPPER

FB_D[31:16] mode select control. These bit fields control the strength of the FlexBus upper data pins.

00 Half strength 1.8V low power/mobile DDR.

01 Open drain.

10 Full strength 1.8V low power/mobile DDR.

11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

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Table 13-17. MSCR_FLEXBUS Field Descriptions (continued)

Field Description

3–2

MSCR_

DLOWER

FB_D[15:0] mode select control. These bit fields control the strength of the FlexBus lower data pins.

00 Half strength 1.8V low power/mobile DDR.

01 Open drain.

10 Full strength 1.8V low power/mobile DDR.

11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

1–0

MSCR_

ADDRCTL

FB_A[23:0], BE/BWE[3:0], OE, R/W, FB_CS[5:0], TA, and TS mode select control. These bit fields control the strength of the FlexBus address and control pins.

00 Half strength 1.8V low power/mobile DDR.

01 Open drain.

10 Full strength 1.8V low power/mobile DDR.

11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

13.3.7 SDRAM Mode Select Control Register (MSCR_SDRAM)

The MSCR_SDRAM register controls the output mode selects of the following dedicated SDRAM pins:

SD_A10, SD_CAS, SD_CKE, SD_CLK, SD_CLK, SD_CS0, SD_DQS[3:2], SD_RAS, SD_SDRDQS, and SD_WE.

Address: 0xFC0A_403B (MSCR_SDRAM)

Reset:

MSCR_SDCLKB

3 2

MSCR_SDCLK

Access: User read/write

1 0

MSCR_SDRAM

0 0 1 1 1 1 1

Figure 13-24. SDRAM Mode Select Control Register (MSCR_SDRAM)

Table 13-18. MSCR_SDRAM Field Descriptions

Field Description

7–6

5–4

MSCR_

SDCLKB

Reserved, should be cleared

SD_CLK mode select control. These bit fields control the strength of the FlexBus upper data pins.

00 Half strength 1.8V Mobile DDR.

01 Open drain.

10 Full strength 1.8V Mobile DDR.

11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

3–2

MSCR_

SDCLK

1–0

MSCR_

SDRAM

SD_CLK mode select control. These bit fields control the strength of the FlexBus lower data pins.

00 Half strength 1.8V Mobile DDR.

01 Open drain.

10 Full strength 1.8V Mobile DDR.

11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

SD_A10, SD_CAS, SD_CKE, SD_CS0, SD_DQS[3:2], SD_RAS, SD_SDRDQS, SD_WE mode select control.

These bit fields control the strength of the FlexBus address and control pins.

00 Half strength 1.8V Mobile DDR.

01 Open drain.

10 Full strength 1.8V Mobile DDR.

11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays.

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General Purpose I/O Module

13.3.8 Drive Strength Control Registers (DSCR_x)

The drive strength control registers set the output pin drive strengths. All drive strength control registers are read/write.

13.3.8.1

C Drive Strength Control Register (DSCR_I2C)

The DSCR_I2C register controls the output drive strengths of the I2C_SDA and I2C_SCL pins.

Address: 0xFC0A_403C (DSCR_I2C) Access: User read/write

Reset:

I2C_DSE

0 0 0 0 0 0 See Note

Note: Reset state is 0 when RCON = 1, and is value of D[5] when RCON = 0.

Figure 13-25. I

C Drive Strength Control Register (DSCR_I2C)

Table 13-19. DSCR_I2C Field Descriptions

Field Description

7–2

1–0

I2C_DSE

Reserved, should be cleared

C drive strength control. This bit field controls the drive strength of the I2C_SDA and I2C_SCL pins.

00 10pF

01 20pF

10 30pF

11 50pF

13.3.8.2

Miscellaneous Drive Strength Control Register (DSCR_MISC)

The DSCR_MISC register controls the output drive strengths of the following pins: PSTCLK, PST[3:0],

DDATA[3:0], ALLPST, DSO, DT3IN, DT2IN, DT1IN, DT0IN, and RSTOUT.

Address: 0xFC0A_403D (DSCR_MISC) Access: User read/write

5 4

DEBUG_DSE

3 2

RSTOUT_DSE

TIMER_DSE

Reset: 0 0 1 1 See Note 1

Note: Reset state is 0 when RCON = 1, and is value of D[5] when RCON = 0.

See Note

Figure 13-26. Miscellaneous Drive Strength Control Register (DSCR_MISC)

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General Purpose I/O Module

Table 13-20. DSCR_MISC Field Descriptions

Field Description

7–6

5–4

DEBUG_

DSE

Reserved, should be cleared

Debug drive strength control. This bit field controls the drive strength of the PST[3:0], DDATA[3:0], ALLPST, and

DSO pins.

00 10pF

01 20pF

10 30pF

11 50pF

3–2

RSTOUT_

DSE

RSTOUT drive strength control. This bit field controls the drive strength of the RSTOUT pin.

00 10pF

01 20pF

10 30pF

11 50pF

1–0

TIMER_

DSE

Timer drive strength control. This bit field controls the drive strength of the DT3IN, DT2IN, DT1IN, and DT0IN pins.

00 10pF

01 20pF

10 30pF

11 50pF

13.3.8.3

FEC Drive Strength Control Register (DSCR_FEC)

The DSCR_FEC register controls the output drive strengths of the FEC_MDC and FEC_MDIO pins.

Address: 0xFC0A_403E (DSCR_FEC) Access: User read/write

FEC_DSE

Reset: 0 0 0 0 0 0

Note: Reset state is 0 when RCON = 1, and is value of D[5] when RCON = 0.

See Note

Figure 13-27. FEC Drive Strength Control Register (DSCR_FEC)

Table 13-21. DSCR_FEC Field Descriptions

Field

7–2

1–0

FEC_

DSE

Description

Reserved, should be cleared

FEC drive strength control. This bit field controls the drive strength of the FEC_MDC and FEC_MDIO pins.

00 10pF

01 20pF

10 30pF

11 50pF

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13.3.8.4

UART/IRQ Drive Strength Control Register (DSCR_UART)

The DSCR_UART register controls the output drive strengths of the UART1, UART0, and IRQ pins.

Address: 0xFC0A_403F (DSCR_UART) Access: User read/write

UART1_DSE

4 3

UART0_DSE

2 1

IRQ_DSE

Reset: 0 0 See Note 1 See Note 1

Note: Reset state is 0 when RCON = 1, and is value of D[5] when RCON = 0.

See Note

Figure 13-28. UART/IRQ Drive Strength Control Register (DSCR_UART)

Table 13-22. DSCR_UART Field Descriptions

Field Description

7–6 Reserved, should be cleared

5–4

UART1_DSE

UART1 drive strength control. This bit field controls the drive strength of the U1RXD, U1TXD, U1CTS, and

U1RTS pins.

00 10pF

01 20pF

10 30pF

11 50pF

3–2

UART0_DSE

UART0 drive strength control. This bit field controls the drive strength of the U0RXD, U0TXD, U0CTS, and

U0RTS pins.

00 10pF

01 20pF

10 30pF

11 50pF

1–0

IRQ_DSE

IRQ drive strength control. This bit field controls the drive strength of the IRQ[7:1] pins.

00 10pF

01 20pF

10 30pF

11 50pF

13.3.8.5

QSPI Drive Strength Control Register (DSCR_QSPI)

The DSCR_QSPI register controls the output drive strengths of the QSPI_PCS2, QSPI_SCK, QSPI_DIN, and QSPI_DOUT pins.

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Address: 0xFC0A_4040 (DSCR_QSPI) Access: User read/write

QSPI_DSE

Reset: 0 0 0 0 0 0

Note: Reset state is 0 when RCON = 1, and is value of D[5] when RCON = 0.

See Note

Figure 13-29. QSPI Drive Strength Control Register (DSCR_QSPI)

Table 13-23. DSCR_QSPI Field Descriptions

Field Description

7–2 Reserved, should be cleared

1–0

QSPI_DSE

QSPI drive strength control. This bit field controls the drive strength of the QSPI_PCS2, QSPI_SCK, QSPI_DIN,

QSPI_DOUT pins.

00 10pF

01 20pF

10 30pF

11 50pF

13.4 Functional Description

13.4.1 Overview

Initial pin function is determined during reset configuration. The pin assignment registers allow the user to select among various primary functions and general purpose I/O after reset. Most pins are configured as GPIO by default. The notable exceptions to this are external bus control pins, address/data pins, and chip select pins. These pins are configured for their primary functions after reset.

Every GPIO pin is individually configurable as an input or an output via a data direction register

(PDDR_x). Every GPIO port has an output data register (PODR_x) and a pin data register (PPDSDR_x) to monitor and control the state of its pins. Data written to a PODR_x register is stored and then driven to the corresponding port x pins configured as outputs.

Reading a PODR_x register returns the current state of the register regardless of the state of the corresponding pins. Reading a PPDSDR_x register returns the current state of the corresponding pins when configured as general purpose I/O, regardless of whether the pins are inputs or outputs.

Every GPIO port has a PPDSDR_x register and a clear register (PCLRR_x) for setting or clearing individual bits in the PODR_x register. Initial pin output drive strength is determined during reset configuration. The DSCR_x registers allow the pin drive strengths to be configured on a per-function basis after reset.

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General Purpose I/O Module

13.4.2 Port Digital I/O Timing

Input data on all pins configured as general purpose input is synchronized to the rising edge of the bus

clock, FB_CLK, as shown in Figure 13-30 .

FB_CLK

Input

Pin Data

Figure 13-30. General Purpose Input Timing

Data written to the PODR_x register of any pin configured as a general purpose output is immediately

driven to its respective pin, as shown in Figure 13-31 .

FB_CLK

Output Data

Output Pin

Figure 13-31. General Purpose Output Timing

13.5 Initialization/Application Information

The initialization for the ports module is done during reset configuration. All registers are reset to a

predetermined state. Refer to Section 13.3, “Memory Map/Register Definition

,” for more details on reset and initialization.

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Chapter 14 Interrupt Controller Module

14.1 Introduction

This section details the functionality of the interrupt controller (INTC). The general features of the interrupt controller block include:

• 64 fully-programmable interrupt sources. Not all possible interrupt source locations are used on this device.

• Each of the sources has a unique interrupt control register (ICRn) to define the software-assigned levels.

• Unique vector number for each interrupt source.

• Ability to mask any individual interrupt source, plus global mask-all capability.

• Supports hardware and software interrupt acknowledge cycles.

• Wake-up signal from low-power stop modes.

The 64, fully-programmable interrupt sources for the interrupt controller manage the complete set of interrupt sources from all of the modules on the device. This section describes how the interrupt sources are mapped to the interrupt controller logic and how interrupts are serviced.

14.1.1 68 K/ColdFire Interrupt Architecture Overview

Before continuing with the specifics of the interrupt controller, a brief review of the interrupt architecture of the 68K/ColdFire family is appropriate.

The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The processor samples for active interrupt requests once-per-instruction by comparing the encoded priority level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machine’s status register (SR). If the priority level is greater than the SR[I] field at the sample point, the processor suspends normal instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For correct operation, the ColdFire device requires that, after asserted, the interrupt source remain asserted until explicitly disabled by the interrupt service routine.

During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt acknowledge (IACK) cycle with the ColdFire implementation using a special memory-mapped address

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space within the interrupt controller. The fetched data provides an index into the exception vector table that contains 256 addresses, each pointing to the beginning of a specific exception service routine. In particular, vectors 64 - 255 of the exception vector table are reserved for user interrupt service routines.

The first 64 exception vectors are reserved for the processor to manage reset, error conditions (access, address), arithmetic faults, system calls, etc. After the interrupt vector number has been retrieved, the processor continues by creating a stack frame in memory. For ColdFire, all exception stack frames are 2 longwords in length, and contain 32 bits of vector and status register data, along with the 32-bit program

counter value of the instruction that was interrupted (see Section 3.3.3.1, “Exception Stack Frame

Definition,”

for more information on the stack frame format). After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number as the offset, and then jumps to that address to begin execution of the service routine. After the status register is stored in the exception stack frame, the SR[I] mask field is set to the level of the interrupt being acknowledged, effectively masking that level and all lower values while in the service routine.

The processing of the interrupt acknowledge cycle is fundamentally different than previous 68K/ColdFire cores. In this approach, all IACK cycles are directly managed by the interrupt controller, so the requesting peripheral device is not accessed during the IACK. As a result, the interrupt request must be explicitly cleared in the peripheral during the interrupt service routine. For more information, see

Section 14.3.1.3,

“Interrupt Vector Determination .”

ColdFire processors guarantee that the first instruction of the service routine is executed before sampling for interrupts is resumed. By making this initial instruction a load of the SR, interrupts can be safely disabled, if required.

For more information on exception processing, see the ColdFire Programmer’s Reference Manual at http://www.freescale.com/coldfire .

14.2 Memory Map/Register Definition

The register programming model for the interrupt controller is memory-mapped to a 256-byte space. In the following discussion, there are a number of program-visible registers greater than 32 bits in size. For these control fields, the physical register is partitioned into two 32-bit values: a register high (the upper longword) and a register low (the lower longword). The nomenclature <reg_name>H and <reg_name>L is used to reference these values.

The registers and their locations are defined in

Table 14-2 . The base addresses for the interrupt controller

is listed below.

Table 14-1. Interrupt Controller Base Addresses

Interrupt Controller Number

INTC

Base Address

0xFC04_8000

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Address

Table 14-2. Interrupt Controller Memory Map

Register

Width

(bits)

Access Reset Value

Interrupt Controller 0

0xFC04_8000

0xFC04_8004

Interrupt Pending Register High (IPRH)

Interrupt Pending Register Low (IPRL)

0xFC04_8008 Interrupt Mask Register High (IMRH)

0xFC04_800C Interrupt Mask Register Low (IMRL)

0xFC04_8010

0xFC04_8014

Interrupt Force Register High (INTFRCH)

Interrupt Force Register Low (INTFRCL)

0xFC04_801A Interrupt Configuration Register (ICONFIG)

0xFC04_801C Set Interrupt Mask (SIMR)

0xFC04_801D Clear Interrupt Mask (CIMR)

0xFC04_801E Current Level Mask (CLMASK)

0xFC04_801F Saved Level Mask (SLMASK)

0xFC04_8040 + n

(n=0:63)

Interrupt Control Registers (ICRn)

0xFC04_80E0 Software Interrupt Acknowledge (SWIACK)

0xFC04_80E0 + 4n

(n=1:7)

Level n Interrupt Acknowledge Registers (LnIACK)

0x00

0x18

Section/

Page

R/W

0x0000_0000

0x0000_0000

R/W 0xFFFF_FFFF

R/W 0xFFFF_FFFF

0x0000_0000

0x0000_0000

0x0000

0x00

14.2.4/14-6

14.2.5/14-7

0x00

0x0F

0x00

14.2.1 Interrupt Pending Registers (IPRH, IPRL)

The IPRH and IPRL registers,

Figure 14-1

and

Figure 14-2

, are each 32 bits in size, and provide a bit map

for each interrupt request to indicate if there is an active request (1 equals active request, 0 equals no request) for the given source. The interrupt mask register state does not affect the IPR. The IPR is cleared by reset and is a read-only register, so any attempted write to this register is ignored.

Address 0xFC04_8000 (IPRH)

Access: User read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

1 0

INT

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 14-1. Interrupt Pending Register High (IPRH)

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Table 14-3. IPRH Field Descriptions

Field

31–0

INT

Description

Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRH samples the signal generated by the interrupting source. The corresponding IPRH bit reflects the state of the interrupt signal even if the corresponding

IMRHn bit is set.

0 The corresponding interrupt source does not have an interrupt pending

1 The corresponding interrupt source has an interrupt pending

Address 0xFC04_8004 (IPRL) Access: User read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 14-2. Interrupt Pending Register Low (IPRL)

Table 14-4. IPRL Field Descriptions

Field

31–0

INT

Description

Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRL samples the signal generated by the interrupting source. The corresponding IPRL bit reflects the state of the interrupt signal even if the corresponding

IMRL bit is set.

0 The corresponding interrupt source does not have an interrupt pending

1 The corresponding interrupt source has an interrupt pending

14.2.2 Interrupt Mask Register (IMRH, IMRL)

The IMRH and IMRL registers are each 32 bits in size and provide a bit map for each interrupt to allow the request to be disabled (1 equals disable the request, 0 equals enable the request). The IMRL register is used for masking interrupt sources 0 to 31, while the IMRH register is used for masking interrupts 32 to

63. The IMR is set to all ones by reset, disabling all interrupt requests. The IMR can be read and written.

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NOTE

A spurious interrupt may occur if an interrupt source is being masked in the interrupt controller mask register (IMR) or a module’s interrupt mask register while the interrupt mask in the status register (SR[I]) is set to a value lower than the interrupt’s level. This is because by the time the status register acknowledges this interrupt, the interrupt has been masked. A spurious interrupt is generated because the CPU cannot determine the interrupt source. To avoid this situation for interrupts sources with levels

1-6, first write a higher level interrupt mask to the status register, before setting the mask in the IMR or the module’s interrupt mask register. After the mask is set, return the interrupt mask in the status register to its previous value. Because level 7 interrupts cannot be disabled in the status register prior to masking, use of the IMR or module interrupt mask registers to disable level 7 interrupts is not recommended.

Address 0xFC04_8008 (IMRH) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT_MASK

Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 14-3. Interrupt Mask Register High (IMRH)

Table 14-5. IMRH Field Descriptions

Field Description

31–0

INT_MASK

Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRH bit determines whether an interrupt condition can generate an interrupt. The corresponding IPRH bit reflects the state of the interrupt signal even if the corresponding IMRH bit is set.

0 The corresponding interrupt source is not masked

1 The corresponding interrupt source is masked

Address 0xFC04_800C (IMRL) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INT_MASK

Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 14-4. Interrupt Mask Register Low (IMRL)

Table 14-6. IMRL Field Descriptions

Field Description

31–0

INT_MASK

Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRL bit determines whether an interrupt condition can generate an interrupt. The corresponding IPRL bit reflects the state of the interrupt signal even if the corresponding IMRL bit is set.

0 The corresponding interrupt source is not masked

1 The corresponding interrupt source is masked

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14.2.3 Interrupt Force Registers (INTFRCH, INTFRCL)

The INTFRCH and INTFRCL registers are each 32 bits in size and provide a mechanism to allow software generation of interrupts for each possible source for functional or debug purposes. The system design may reserve one or more sources to allow software to self-schedule interrupts by forcing one or more of these bits (set to force request, clear to negate request) in the appropriate INTFRC register. The INTFRCL register forces interrupts for sources 0 to 31, while the INTFRCH register forces interrupts for sources 32 to 63. The assertion of an interrupt request via the interrupt force register is not affected by the interrupt mask register. The INTFRC registers are cleared by reset.

Address 0xFC04_8010 (INTFRCH) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTFRCH

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 14-5. Interrupt Force Register High (INTFRCH)

Table 14-7. INTFRCH Field Descriptions

Field Description

31–0

INTFRCH

Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.

0 No interrupt forced on the corresponding interrupt source

1 Force an interrupt on the corresponding source

Address 0xFC04_8014 (INTFRCL) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTFRCL

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 14-6. Interrupt Force Register Low (INTFRCL)

Table 14-8. INTFRCL Field Descriptions

Field Description

31–0

INTFRCL

Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.

0 No interrupt forced on corresponding interrupt source

1 Force an interrupt on the corresponding source

14.2.4 Interrupt Configuration Register (ICONFIG)

This 16-bit register defines the operating configuration for the interrupt controller module.

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Address: 0xFC04_801A (ICONFIG)

14 13 12 15

Reset 0 0

ELVLPRI

11 10 9 8

EMASK

0 0 0 0 0 0 0 0 0 0

Figure 14-7. Interrupt Configuration Register (ICONFIG)

Table 14-9. ICONFIG Field Descriptions

Access: User read/write

0 0 0 0

Field Description

15–9

ELVLPRI

8–6

EMASK

4–0

Enable core’s priority elevation on priority levels. Each ELVLPRI[7:1] bit corresponds to the available priority levels 1 – 7. If set, the assertion of the corresponding level-n request to the core causes the processor’s bus master priority to be temporarily elevated in the device’s crossbar switch arbitration logic. The processor’s bus master arbitration priority remains elevated until the level-n request is negated. If round-robin arbitration is enabled, this bit has no effect.

If cleared, the assertion of a level-n request does not affect the processor’s bus master priority.

Reserved, must be cleared.

If set, the interrupt controller automatically loads the level of an interrupt request into the CLMASK (current level mask) when the acknowledge is performed. At the exact same cycle, the value of the current interrupt level mask is saved in the SLMASK (saved level mask) register.

This feature can be used to support software-managed nested interrupts, and is intended to complement the interrupt masking functions supported in the ColdFire processor. The value of SLMASK register should be read from the interrupt controller and saved in the interrupt stack frame in memory, and restored near the service routine’s exit.

If cleared, the INTC does not perform any automatic masking of interrupt levels. The state of this bit does not affect the ColdFire processor’s interrupt masking logic in any manner.

Reserved, must be cleared.

14.2.5 Set Interrupt Mask Register (SIMR)

The SIMR register provides a simple mechanism to set a given bit in the IMR registers to mask the corresponding interrupt request. The value written to the SIMR field causes the corresponding bit in the

IMR register to be set. The SIMR[SALL] bit provides a global set function, forcing the entire contents of

IMR to be set, thus masking all interrupts. Reads of this register return all zeroes. This register is provided so interrupt service routines can easily mask the given interrupt request without the need to perform a read-modify-write sequence on the IMR register.

Address: 0xFC04_801C (SIMR)

0 R

Reset: 0

SALL

SIMR

0 0 0 0

Figure 14-8. Set Interrupt Mask Register (SIMR)

Access: User write-only

0 0

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Field

SALL

5–0

SIMR

Table 14-10. SIMR Field Descriptions

Description

Reserved, must be cleared.

Set all bits in the IMR register, masking all interrupt requests.

0 Only set those bits specified in the SIMR field.

1 Set all bits in IMR register. The SIMR field is ignored.

Set the corresponding bit in the IMR register, masking the interrupt request.

14.2.6 Clear Interrupt Mask Register (CIMR)

The CIMR register provides a simple mechanism to clear a given bit in the IMR registers to enable the corresponding interrupt request. The value written to the CIMR field causes the corresponding bit in the

IMR register to be cleared. The CIMR[CALL] bit provides a global clear function, forcing the entire contents of IMR to be cleared, thus enabling all interrupts. Reads of this register return all zeroes. This register is provided so interrupt service routines can easily enable the given interrupt request without the need to perform a read-modify-write sequence on the IMR register.

In the event of a simultaneous write to the CIMR and SIMR, the SIMR has priority and the resulting function would be a set of the interrupt mask register.

Access: User write-only

Field

CALL

Address: 0xFC04_801D (CIMR)

0 R

Reset: 0

CALL

CIMR

0 0 0 0

Figure 14-9. Clear Interrupt Mask Register (CIMR)

5–0

CIMR

Table 14-11. CIMR Field Descriptions

Description

Reserved, must be cleared.

Clear all bits in the IMR register, enabling all interrupt requests.

0 Only set those bits specified in the CIMR field.

1 Clear all bits in IMR register. The CIMR field is ignored.

Clear the corresponding bit in the IMR register, enabling the interrupt request.

0 0

14.2.7 Current Level Mask Register (CLMASK)

The CLMASK register is provided so the interrupt controller can optionally automatically manage masking of interrupt requests based on the programmed priority level. If enabled by ICONFIG[EMASK] bit being set, an interrupt acknowledge read cycle returns a vector number identifying the physical request source, and the CLMASK register is loaded with the level number associated with the request. After the

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CLMASK register is updated, then all interrupt requests with level numbers equal to or less than this value are masked by the controller and are not allowed to cause the assertion of the interrupt signal to the processor core. As the CLMASK register is updated during the IACK cycle read, the former value is saved in the SLMASK register.

Typically, after a level-n interrupt request is managed, the service routine restores the saved level mask value into the current level mask register to re-enable the lower priority requests. In addition, an interrupt service routine can explicitly load this register with a lower priority value to query for any pending interrupts via software interrupt acknowledge cycles.

Address: 0xFC04_801E (CLMASK)

0 R

Reset: 0

3 2

CLMASK

0 0 0 1 1

Figure 14-10. Current Level Mask Register (CLMASK)

Access: User read/write

1 0

1 1

Table 14-12. CLMASK Field Descriptions

Field Description

7–4

3–0

CLMASK

Reserved, must be cleared.

Current level mask. Defines the level mask, where only interrupt levels greater than the current value are processed by the controller

0000 Level 1 – 7 requests are processed.

0001 Level 2 – 7 requests are processed.

0010 Level 3 – 7 requests are processed.

0011 Level 4 – 7 requests are processed.

0100 Level 5 – 7 requests are processed.

0101 Level 6 – 7 requests are processed.

0110 Level 7 requests are processed.

0111 All requests are masked.

1000 – 1110 Reserved.

1111 Level 1 – 7 requests are processed.

14.2.8 Saved Level Mask Register (SLMASK)

The SLMASK register is provided so the interrupt controller can optionally automatically manage masking of interrupt requests based on the programmed priority level. If enabled by ICONFIG[EMASK] bit being set, an interrupt acknowledge read cycle returns a vector number identifying the physical request source, and the CLMASK register is loaded with the level number associated with the request. After the

Typically, after a level-n interrupt request is managed, the service routine restores the saved level mask value into the current level mask register to re-enable the lower priority requests.

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Address: 0xFC04_801F (SLMASK)

0 R

Reset: 0

3 2

SLMASK

0 0 0 1 1

Figure 14-11. Saved Level Mask Register (SLMASK)

Access: User read/write

1 0

1 1

Table 14-13. SLMASK Field Descriptions

Field Description

7–4

3–0

SLMASK

Reserved, must be cleared.

Saved level mask. Defines the saved level mask. See the CLMASK field definition for more information on the specific values.

14.2.9 Interrupt Control Register (ICRn, (n = 00, 01, 02, ..., 63))

Each ICR register specifies the interrupt level (1–7) for the corresponding interrupt source. These registers are cleared by reset and should be programmed with the appropriate levels before interrupts are enabled.

When multiple interrupt requests are programmed to the same level number, they are processed in a descending request number order. As an example, if requests 63, 62, 2, and 1 are programmed to a common level, request 63 is processed first, then request 62, then request 2, and finally request 1.

This definition allows software maximum flexibility in grouping interrupt request sources within any given priority level. The priority level in the ICRs directly corresponds to the interrupt level supported by the ColdFire processor.

Field

7–3

2–0

LEVEL

Address: 0xFC04_8040 – 7F (ICR00 – ICR63)

0 R

Reset: 0

0 0 0 0 0

Figure 14-12. Interrupt Control Registers (ICRn)

Access: User read/write

1 0

LEVEL

0 0

Table 14-14. ICRn Field Descriptions

Description

Reserved, must be cleared.

Interrupt level. Indicates the interrupt level assigned to each interrupt input. A level of 0 effectively disables the interrupt request, while a level 7 interrupt is given the highest priority.

If interrupt masking is enabled (ICONFIG[EMASK] = 1), the acknowledgement of a level-n request forces the controller to automatically mask all interrupt requests of level-n and lower.

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14.2.9.1

Interrupt Sources

Table 14-15

list the interrupt sources for each interrupt request line for INTC.

Table 14-15. Interrupt Source Assignment For INTC

Source Module Flag Flag Clearing Mechanism

Not Used

EPORT

PIT0

PIT1

EPFR[EPF1]

EPFR[EPF4]

EPFR[EPF7]

PCSR0[PIF]

Edge port flag 1

Edge port flag 4

Edge port flag 7

PIT interrupt flag

Write 1 to EPF1

Write 1 to EPF4

Write 1 to EPF7

Write 1 to PIF or write PMR

Not Used

EDMA_INTR[INT00] DMA Channel 0 transfer complete Write EDMA_CINTR[CINT] = 0

EDMA_INTR[INT01] DMA Channel 1 transfer complete Write EDMA_CINTR[CINT] = 1

DMA

EDMA_INTR[INT02] DMA Channel 2 transfer complete Write EDMA_CINTR[CINT] = 2

EDMA_INTR[INT03] DMA Channel 3 transfer complete Write EDMA_CINTR[CINT] = 3

EDMA_INTR[INT04] DMA Channel 4transfer complete Write EDMA_CINTR[CINT] = 4

EDMA_INTR[INT05] DMA Channel 5 transfer complete Write EDMA_CINTR[CINT] = 5

EDMA_INTR[INT06] DMA Channel 6 transfer complete Write EDMA_CINTR[CINT] = 6

EDMA_INTR[INT07] DMA Channel 7 transfer complete Write EDMA_CINTR[CINT] = 7

EDMA_INTR[INT08] DMA Channel 8 transfer complete Write EDMA_CINTR[CINT] = 8

EDMA_INTR[INT09] DMA Channel 9 transfer complete Write EDMA_CINTR[CINT] = 9

EDMA_INTR[INT10] DMA Channel 10 transfer complete Write EDMA_CINTR[CINT] = 10

EDMA_INTR[INT11] DMA Channel 11 transfer complete Write EDMA_CINTR[CINT] = 11

EDMA_INTR[INT12] DMA Channel 12 transfer complete Write EDMA_CINTR[CINT] = 12

EDMA_INTR[INT13] DMA Channel 13 transfer complete Write EDMA_CINTR[CINT] = 13

SCM

UART0

UART1

UART2

EDMA_INTR[INT14] DMA Channel 14 transfer complete Write EDMA_CINTR[CINT] = 14

EDMA_INTR[INT15] DMA Channel 15 transfer complete Write EDMA_CINTR[CINT] = 15

EDMA_ERR[ERRn] DMA Error Interrupt

SCMIR[CWIC]

UISR0 register

UISR1 register

UISR2 register

Core Watchdog Timeout

UART0 Interrupt Request

UART1 Interrupt Request

UART2 Interrupt Request

Write EDMA_CERR[CERR] = n

Write 1 to SCMISR[CWIC]

Automatically cleared

Not Used

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Source Module

30 I

QSPI

DTIM0

DTIM1

DTIM2

DTIM3

FEC

SCM

Table 14-15. Interrupt Source Assignment For INTC (continued)

Flag

I2SR[IIF]

QIR register

C Interrupt

QSPI interrupt

DTER0 register DMA Timer 0 interrupt

DTER1 register DMA Timer 1 interrupt

DTER2 register DMA Timer 2 interrupt

DTER3 register DMA Timer 3 interrupt

EIR[TXF] Transmit frame interrupt

EIR[TXB]

EIR[UN]

Transmit buffer interrupt

Transmit FIFO underrun

EIR[RL]

EIR[RXF]

EIR[RXB]

EIR[MII]

EIR[LC]

EIR[HBERR]

EIR[GRA]

EIR[EBERR]

EIR[BABT]

EIR[BABR]

Collision retry limit

Receive frame interrupt

Receive buffer interrupt

MII interrupt

Late collision

Heartbeat error

Graceful stop complete

Ethernet bus error

Babbling transmit error

Babbling receive error

Not Used

SCMISR[CFEI] Bus error interrupt

Not Used

Write SCMISR[CFEI] = 1

Flag Clearing Mechanism

Write 0 to I2SR[IIF]

Write 1 to appropriate QIR bit

Write 1 to appropriate DTER0 bit

Write 1 to appropriate DTER1 bit

Write 1 to appropriate DTER2 bit

Write 1 to appropriate DTER3 bit

Write EIR[TXF] = 1

Write EIR[TXB] = 1

Write EIR[UN] = 1

Write EIR[RL] = 1

Write EIR[RXF] = 1

Write EIR[RXB] = 1

Write EIR[MII] = 1

Write EIR[LC] = 1

Write EIR[HBERR] = 1

Write EIR[GRA] = 1

Write EIR[EBERR] = 1

Write EIR[BABT] = 1

Write EIR[BABR] = 1

14.2.10 Software and Level 1 – 7 IACK Registers (SWIACK, L1IACK –

L7IACK)

The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a processor-generated interrupt acknowledge cycle during exception processing. In either case, the interrupt controller’s actions are very similar.

First, consider an IACK cycle to a specific level: a level-n IACK. When this type of IACK arrives in the interrupt controller, the controller examines all the currently-active level n interrupt requests, determines the highest priority within the level, and then responds with the unique vector number corresponding to that specific interrupt source. The vector number is supplied as the data for the byte-sized IACK read cycle.

In addition to providing the vector number, the interrupt controller also loads the level into the CLMASK register, where it may be retrieved later.

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This interrupt controller design also supports the concept of a software IACK. A software IACK allows an interrupt service routine to determine if there are other pending interrupts so that the overhead associated with interrupt exception processing (including machine state save/restore functions) can be minimized. In general, the software IACK is performed near the end of an interrupt service routine, and if there are additional active interrupt sources, the current interrupt service routine (ISR) passes control to the appropriate service routine, but without taking another interrupt exception.

When the interrupt controller receives a software IACK read, it returns the vector number associated with the highest unmasked interrupt source for that interrupt controller. If there are no active sources, the interrupt controller returns an all-zero vector as the operand for the SWIACK register. A read from the

LnIACK registers when there are no active requests returns a value of 24 (0x18), signaling a spurious interrupt.

Address: 0xFC04_80E0 (SWIACK)

0xFC04_80E0+4n (LnIACK) n=1:7

Access: User read-only

7 6 5 4 3 2 1

Reset

(SWIACK):

Reset

(LnIACK):

VECTOR

Figure 14-13. Software and Level n IACK Registers (SWIACKn, L1IACKn – L7IACKn)

Table 14-16. SWIACKn and LxIACKn Field Descriptions

Field Description

7–0

VECTOR

Vector number. A read from the SWIACK register returns the vector number associated with the highest priority pending interrupt source. A read from one of the LnIACK registers returns the highest priority unmasked interrupt source within the level.

A write to any IACK register causes an error termination.

14.3 Functional Description

14.3.1 Interrupt Controller Theory of Operation

To support the interrupt architecture of the 68K/ColdFire programming model, the 64 interrupt sources are organized as 7 levels, with an arbitrary number of requests programmed to each level. The priority structure within a single interrupt level depends on the interrupt source number assignments (see

Section 14.2.9.1, “Interrupt Sources”

). The higher numbered interrupt source has priority over the lower numbered interrupt source. See the below table for an example.

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Table 14-17. Example Interrupt Priority Within a Level

Interrupt Source

ICR[2:0]

011

Priority

Highest

Lowest

The level is fully programmable for all sources. The 3-bit level is defined in the interrupt control register

(ICRn).

The operation of the interrupt controller can be broadly partitioned into three activities:

• Recognition

• Prioritization

• Vector determination during IACK

14.3.1.1

Interrupt Recognition

The interrupt controller continuously examines the request sources (IPR) and the interrupt mask register

(IMR) to determine if there are active requests. This is the recognition phase. The interrupt force register

(INTFRC) also factors into the generation of an active request.

14.3.1.2

Interrupt Prioritization

As an active request is detected, it is translated into the programmed interrupt level. Next, the appropriate level masking is performed if this feature is enabled. The level of the active request must be greater than the current mask level before it is signaled in the processor. The resulting unmasked decoded priority level is driven out of the interrupt controller to the processor core during this prioritization phase.

14.3.1.3

Interrupt Vector Determination

After the core has sampled for pending interrupts and begun interrupt exception processing, it generates an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a memory-mapped byte read by the processor, and routed to the appropriate interrupt controller. Next, the interrupt controller extracts the level being acknowledged from address bits[4:2], and then determines the highest unmasked level for the type of interrupt being acknowledged, and returns the 8-bit interrupt vector for that request to complete the cycle. The 8-bit interrupt vector is formed using the following algorithm:

For INTC, vector_number = 64 + interrupt source number

Recall vector_numbers 0-63 are reserved for the ColdFire processor and its internal exceptions. Thus, the following mapping of bit positions to vector numbers applies for INTC: if interrupt source 0 is active and acknowledged, then vector_number = 64 if interrupt source 1 is active and acknowledged, then vector_number = 65 if interrupt source 2 is active and acknowledged, then vector_number = 66

...

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if interrupt source 63 is active and acknowledged, then vector_number = 127

The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector number.

If there is no active interrupt source for the given level, a special spurious interrupt vector (vector_number equals 24) is returned and it is the responsibility of the service routine to manage this error situation.

This protocol implies the interrupting peripheral is not accessed during the acknowledge cycle because the interrupt controller completely services the acknowledge. This means the interrupt source must be explicitly disabled in the interrupt service routine. This design provides unique vector capability for all interrupt requests, regardless of the complexity of the peripheral device.

In some applications, it is expected that the hardware masking of interrupt levels by the interrupt controller is enabled. This masking capability can be used with the processor’s masking logic to form a dual-mask capability. In this operation mode, the IACK read cycle also causes the current interrupt level mask to be saved in the SLMASK register, and the new level being acknowledged loaded into the CLMASK register.

This operation then automatically masks the new level (and all lower levels) while in the service routine.

Generally, as the service routine completes execution, and the initiating request source has been negated, the saved mask level is restored into the current mask level to re-enable the lower priority levels.

Finally, the vector number returned during the IACK cycle provides the association with the request and the physical interrupt signal. The CLMASK and SLMASK registers are all loaded (if properly enabled) during the interrupt acknowledge read cycle.

14.3.2 Low-Power Wake-up Operation

The system control module (SCM) contains an 8-bit low-power control register (LPCR) to control the low-power stop mode. This register must be explicitly programmed by software to enter low-power mode.

It also contains a wake-up control register (WCR) sets the priority level of the interrupt necessary to bring

the device out of the specified low-power mode. Refer to Chapter 8, “Power Management,”

for definitions of the LPCR and WCR registers, as well as more information on low-power modes.

Each interrupt controller provides a special combinatorial logic path to provide a special wake-up signal to exit from the low-power stop mode. This special mode of operation works as follows:

1. The WCR register is programmed, setting the ENBWCR bit and the desired interrupt priority level.

2. At the appropriate time, the processor executes the privileged STOP instruction. After the processor has stopped execution, it asserts a specific processor status (PST) encoding. Issuing the

STOP instruction when the WCR[ENBWCR] bit is set causes the SCM to enter the mode specified in LPCR[LPMD].

3. The entry into a low-power mode is processed by the low-power mode control logic, and the appropriate clocks (usually those related to the high-speed processor core) are disabled.

4. After entering the low-power mode, the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests. The device waits for an event to generate a level

7 interrupt request or an interrupt request with a priority level greater than the value programmed in WCR[PRILVL].

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Interrupt Controller Module

5. After an appropriately high interrupt request level arrives, the interrupt controller signals its presence, and the SCM responds by asserting the request to exit low-power mode.

6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.

7. With the processor clocks enabled, the core processes the pending interrupt request.

For more information, see ”.

14.4 Initialization/Application Information

The interrupt controller’s reset state has all requests masked via the IMR. Before any interrupt requests are enabled, the following steps must be taken:

1. Set the ICONFIG register to the desired system configuration.

2. Program the ICRn registers with the appropriate interrupt levels.

3. The reset value for the level mask registers (CLMASK and SLMASK) is 0xF (no levels masked).

Typically, these registers do not need to be modified before interrupts are enabled.

4. Load the appropriate interrupt vector tables and interrupt service routines into memory.

5. Enable the interrupt requests, by clearing the appropriate bits in the IMR and lowering the interrupt mask level in the core’s status register (SR[I]) to an appropriate level.

14.4.1 Interrupt Service Routines

This section focuses on the interaction of the interrupt masking functionality with the service routine.

Figure 14-14

presents a timing diagram showing various phases during the execution of an interrupt service routine with the controller level masking functionality enabled. The time scale in this diagram is not meant to be accurate.

A B C D E F

Interrupt

Request

Core

Activity

Interrupt Service Routine

SR[I] iack n n swiack

0xF

CLMASK

0xF n

SLMASK

0xF

Interrupts

Enabled

≤

n Disabled

Note: Not to scale

Figure 14-14. Interrupt Service Routine and Masking

Consider the events depicted in each segment (A – F) of the above diagram.

In A, an interrupt request is asserted, which is then signalled to the core.

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As B begins, the interrupt request is recognized, and the core begins interrupt exception processing. During the core’s exception processing, the IACK cycle performs and the interrupt controller returns the appropriate vector number. As the interrupt acknowledge read performs, the vector number returns to the core. The contents of the CLMASK register load into the SLMASK register, and the CLMASK register updates to the level of the acknowledge interrupt. Additionally, the processor raises the interrupt mask in the status register (SR[I]) to match the level of the acknowledged request. At the end of the core’s exception processing, control passes to the interrupt service routine (ISR), shown as the beginning of segment C.

During C, the initial portion of the ISR executes. Near the end of this segment, the ISR accesses the peripheral to negate the interrupt request source. At the conclusion of segment C, the SR[I] field can be lowered to re-enable interrupts with a priority greater than the original request.

The bulk of the interrupt service routine executes in segment D, with interrupts enabled. Near the end of the service routine, the SR[I] field is again raised to the original acknowledged level, preparing to perform the context switch.

At the end of segment E, the original value in the saved level mask (SLMASK) is restored in the current level mask (CLMASK). Optionally, the service routine can directly load the CLMASK register with any value with pending interrupt requests of certain levels need to be examined.

In segment F, the interrupt service routine completes execution. During this period of time, it is possible to access the interrupt controller with a software IACK to see if there are any pending properly-enabled requests. Checking for any pending interrupt requests at this time provides ability to initiate processing of another interrupt without the need to return from the original and incur the overhead of another interrupt exception.

At the conclusion of segment G, the processor core returns to the original interrupted task or a different task ready to execute.

Obviously, there are many variations to the managing of the SR[I] and the CLMASK values to create a flexible, responsive system for managing interrupt requests within the device.

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Chapter 15 Edge Port Module (EPORT)

15.1 Introduction

The edge port module (EPORT) has eight interrupt pins, IRQ7 – IRQ0.

Each pin can be configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (I/O) pin.

NOTE

Not all EPORT signals may be output from the device. See

Chapter 2,

“Signal Descriptions,”

to determine which signals are available.

Stop

Mode

EPPAR[2n, 2n + 1]

Edge Detect

Logic

EPFRn

Q D0

To Interrupt

Controller

EPPDRn

Synchronizer

EPIERn

Rising Edge of System Clock

EPDRn

IRQn pin

EPDDRn

Figure 15-1. EPORT Block Diagram

NOTE

The GPIO module must be configured to enable the peripheral function of

the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”

) prior to configuring the edge-port module.

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15.2 Low-Power Mode Operation

This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see

Chapter 8, “Power Management”.

Table 15-1 shows EPORT-module operation in

low-power modes and describes how this module may exit each mode.

NOTE

The wakeup control register (WCR) in the system control module specifies the interrupt level at or above what is needed to bring the device out of a low-power mode.

Table 15-1. Edge Port Module Operation in Low-Power Modes

Low-power Mode

Wait

Doze

Stop

EPORT Operation

Normal

Level-sensing only

Mode Exit

Any IRQn interrupt at or above level in WCR

Any IRQn interrupt set for level-sensing at or above level in WCR. See note below.

In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may be configured to exit the low-power modes by generating an interrupt request on a selected edge or a low level on an external pin. In stop mode, no clocks are available to perform the edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode.

NOTE

In stop mode, the input pin synchronizer is bypassed for the level-detect logic because no clocks are available.

15.3 Interrupt/GPIO Pin Descriptions

All EPORT pins default to general-purpose input pins at reset. The pin value is synchronized to the rising edge of FB_CLK when read from the EPORT pin data register (EPPDR). The values used in the edge/level detect logic are also synchronized to the rising edge of FB_CLK. These pins use Schmitt-triggered input buffers with built-in hysteresis designed to decrease the probability of generating false, edge-triggered interrupts for slow rising and falling input signals.

When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are set at reset.

15.4 Memory Map/Register Definition

This subsection describes the memory map and register structure. Refer to Table 15-2 for a description of

the EPORT memory map.

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NOTE

Longword accesses to any of the edge-port registers result in a bus error.

Only byte and word accesses are allowed.

Table 15-2. Edge Port Module Memory Map

Address Register

Width

(bits)

Access Reset Value Section/Page

Supervisor Access Only Registers

0xFC08_8000 EPORT Pin Assignment Register (EPPAR)

0xFC08_8002 EPORT Data Direction Register (EPDDR)

0xFC08_8003 EPORT Interrupt Enable Register (EPIER)

Supervisor/User Access Registers

R/W

0x0000

0x00

15.4.1/15-3

15.4.2/15-4

15.4.3/15-5

0xFC08_8004 EPORT Data Register (EPDR)

0xFC08_8005 EPORT Pin Data Register (EPPDR)

R/W

0xFC08_8006 EPORT Flag Register (EPFR) 8 R/W

User access to supervisor-only address locations have no effect and result in a bus error.

0xFF

15.4.4/15-5

See Section

15.4.5/15-5

0x00

15.4.6/15-6

15.4.1 EPORT Pin Assignment Register (EPPAR)

The EPORT pin assignment register (EPPAR) controls the function of each pin individually.

: 0xFC08_8000 (EPPAR)

13 15 14

Reset 0

EPPA7

0 0

EPPA6

11 10

EPPA5

EPPA4

8 7

EPPA3

6 5

EPPA2

0 0 0 0 0 0 0 0 0

Figure 15-2. EPORT Pin Assignment Register (EPPAR)

Access: Supervisor read/write

EPPA1

EPPA0

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Table 15-3. EPPAR Field Descriptions

Field Description

15–0

EPPAn

EPORT pin assignment select fields. The read/write EPPAn fields configure EPORT pins for level detection and rising and/or falling edge detection.

Pins configured as level-sensitive are active-low (logic 0 on the external pin represents a valid interrupt request).

Level-sensitive interrupt inputs are not latched. To guarantee that a level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. Level sensitivity must be selected to bring the device out of stop mode with an IRQn interrupt.

Pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. A pin configured for edge detection can trigger an interrupt regardless of its configuration as input or output.

Interrupt requests generated in the EPORT module can be masked by the interrupt controller module. EPPAR functionality is independent of the selected pin direction.

Reset clears the EPPAn fields.

00 Pin IRQn level-sensitive

01 Pin IRQn rising edge triggered

10 Pin IRQn falling edge triggered

11 Pin IRQn falling edge and rising edge triggered

15.4.2 EPORT Data Direction Register (EPDDR)

The EPORT data direction register (EPDDR) controls the direction of each one of the pins individually.

Address: 0xFC08_8002 (EPDDR)

7 6

Reset

EPDD7

EPDD6

EPDD5

EPDD4

EPDD3

EPDD2

0 0 0 0 0

Figure 15-3. EPORT Data Direction Register (EPDDR)

Access: Supervisor read/write

EPDD1

EPDD0

Table 15-4. EPDDR Field Descriptions

Field Description

7–0

EPDDn

Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in EPDDR configures the corresponding pin as an input. Pin direction is independent of the level/edge detection configuration. Reset clears

EPDD7–EPDD0.

To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear.

Software can generate interrupt requests by programming the EPORT data register when the EPDDR selects output.

0 Corresponding EPORT pin configured as input

1 Corresponding EPORT pin configured as output

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15.4.3 Edge Port Interrupt Enable Register (EPIER)

The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin individually.

Address: 0xFC08_8003 (EPIER)

7 6

Reset:

EPIE7

EPIE6

EPIE5

EPIE4

EPIE3

EPIE2

0 0 0 0 0

Figure 15-4. EPORT Port Interrupt Enable Register (EPIER)

Access: User read/write

EPIE1

EPIE0

Table 15-5. EPIER Field Descriptions

Field

7–0

EPIEn

Description

Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set, EPORT generates an interrupt request when:

• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set.

• The corresponding pin level is low and the pin is configured for level-sensitive operation.

Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin. Reset clears EPIE7 –

EPIE0.

0 Interrupt requests from corresponding EPORT pin disabled

1 Interrupt requests from corresponding EPORT pin enabled

15.4.4 Edge Port Data Register (EPDR)

The EPORT data register (EPDR) holds the data to be driven to the pins.

Address: 0xFC08_8004 (EPDR)

7 6

Reset:

EPD7

EPD6

EPD5

EPD4

EPD3

EPD2

1 1 1 1 1

Figure 15-5. EPORT Port Data Register (EPDR)

Table 15-6. EPDR Field Descriptions

Access: User read/write

1 0

EPD1

EPD0

Field

7–0

EPDn

Description

Edge port data bits. An internal register stores data written to EPDR; if any pin of the port is configured as an output, the bit stored for that pin is driven onto the pin. Reading EDPR returns the data stored in the register. Reset sets

EPD7 – EPD0.

15.4.5 Edge Port Pin Data Register (EPPDR)

The EPORT pin data register (EPPDR) reflects the current state of the pins.

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Address: 0xFC08_8005 (EPPDR)

R EPPD7

Reset: [IRQ7]

EPPD6

EPPD5

EPPD4

EPPD3

EPPD2

[IRQ6] [IRQ5] [IRQ4] [IRQ3] [IRQ2]

Figure 15-6. EPORT Port Pin Data Register (EPPDR)

Access: User read-only

EPPD1

EPPD0

[IRQ1] [IRQ0]

Table 15-7. EPPDR Field Descriptions

Field Description

7–0

EPPDn

Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins IRQ7 – IRQ0. Writing to

EPPDR has no effect, and the write cycle terminates normally. Reset does not affect EPPDR.

15.4.6 Edge Port Flag Register (EPFR)

The EPORT flag register (EPFR) individually latches EPORT edge events.

Address: 0xFC08_8006 (EPFR)

7 6

Reset:

EPF7

EPF6

EPF5

EPF4

EPF3

EPF2

0 0 0 0

Figure 15-7. EPORT Port Flag Register (EPFR)

Access: User read/write

1 0

EPF1

EPF0

Table 15-8. EPFR Field Descriptions

Field

7–0

EPFn

Description

Edge port flag bits. When an EPORT pin is configured for edge triggering, its corresponding read/write bit in EPFR indicates that the selected edge has been detected. Reset clears EPF7 – EPF0.

Bits in this register are set when the selected edge is detected on the corresponding pin. A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPARn = 00), pin transitions do not affect this register.

0 Selected edge for IRQn pin has not been detected.

1 Selected edge for IRQn pin has been detected.

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Chapter 16 Enhanced Direct Memory Access (eDMA)

16.1 Overview

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. The hardware microarchitecture includes a DMA engine that performs source- and destination-address calculations, and the actual data-movement operations, along with local memory containing transfer control descriptors for each channel.

16.2 Block Diagram

Figure 16-1

is a block diagram of the eDMA module.

eDMA

Write Address

Write Data

eDMA Engine

Read Data

Write Data

Address

Data Path

Transfer Control

Descriptor (TCD)

Program Model/

Channel Arbitration

Address Path

Control

Read Data eDMA Peripheral

Request

Figure 16-1. eDMA Block Diagram

eDMA Done

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16.3 Features

The eDMA is a highly-programmable data-transfer engine optimized to minimize the required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known and not defined within the data packet itself. The eDMA module features:

• All data movement via dual-address transfers: read from source, write to destination

— Programmable source and destination addresses and transfer size, plus support for enhanced addressing modes

• 16-channel implementation that performs complex data transfers with minimal intervention from a host processor

— Internal data buffer, used as temporary storage to support 16-byte burst transfers

— Connections to the crossbar switch for bus mastering the data movement

• Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations

— 32-byte TCD stored in local memory for each channel

— An inner data transfer loop defined by a minor byte transfer count

— An outer data transfer loop defined by a major iteration count

• Channel activation via one of three methods:

— Explicit software initiation

— Initiation via a channel-to-channel linking mechanism for continual transfers

— Peripheral-paced hardware requests (one per channel)

• Support for fixed-priority and round-robin channel arbitration

• Channel completion reported via optional interrupt requests

— One interrupt per channel, optionally asserted at completion of major iteration count

— Error terminations are optionally enabled per channel and logically summed together to form one error interrupt to the interrupt controller

• Optional support for scatter/gather DMA processing

Throughout this chapter, n is used to reference the channel number.

16.4 Modes of Operation

16.4.1 Normal Mode

In normal mode, the eDMA transfers data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA.

A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that transfers these

NBYTES per service request. A major loop is the number of minor loop iterations defining a task.

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16.4.2 Debug Mode

In debug mode, the eDMA stops transferring data. If debug mode is entered during the transfer of a data block described by a minor loop in the current active channel’s TCD, the eDMA continues operation until completion of the minor loop.

16.5 External Signal Description

This section describes the external signals of the eDMA controller.

Table 16-1. External Signal List

Signal Name

DREQ0

DACK0

I/O Description

Provides external requests from peripherals needing DMA service. When asserted, the device is requesting service. This request pin is tied to DMA channel 0.

O Indicates when the external DMA request has been acknowledged.

16.5.1 External Signal Timing

Asserting the external DMA request signal, DREQn, initiates a service request for that channel. It must remain asserted until the corresponding DACKn signal indicates the channel’s data transfer has started.

The DACKn output is asserted for one cycle during the address phase of the channel’s first internal read access.

• When no further requests are needed, the DREQn signal must negate after the DACKn assertion and on or before the second cycle following the data phase of the last internal bus write (see

Figure 16-2

• If another service request is needed, DREQn may simply remain asserted.

• To request continuous service, DREQn may remain continuously asserted.

Internal

Bus Clock

Internal

Address Phase

Internal

Data Phase rd1 wr1 rd1 rd2 wr1 wr2 rd2 wr2

DREQn

DACKn

Figure 16-2. DREQn and DACKn Timing

After a service request has been initiated, it cannot be canceled. Removing a service request after it has been asserted may result in one of three actions depending on the DMA engine’s status:

• The request is never recognized because another channel is executing.

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• The request is considered spurious and discarded, because the request is removed during arbitration for next channel selection.

• The channel is selected by arbitration and begins execution.

16.6 Memory Map/Register Definition

The eDMA’s programming model is partitioned into two regions: the first region defines a number of registers providing control functions, while the second region corresponds to the local transfer control descriptor memory.

Reading reserved bits in a register return the value of zero and writes to reserved bits in a register are ignored. Reading or writing to a reserved memory location generates a bus error.

Table 16-2. eDMA Controller Memory Map

Address Register

0xFC04_4000 eDMA Control Register (EDMA_CR)

0xFC04_4004 eDMA Error Status Register (EDMA_ES)

0xFC04_400E eDMA Enable Request Register (EDMA_ERQ)

0xFC04_4016 eDMA Enable Error Interrupt Register (EDMA_EEI)

0xFC04_4018 eDMA Set Enable Request (EDMA_SERQ)

0xFC04_4019 eDMA Clear Enable Request (EDMA_CERQ)

0xFC04_401A eDMA Set Enable Error Interrupt Register (EDMA_SEEI)

0xFC04_401B eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)

0xFC04_401C eDMA Clear Interrupt Request Register (EDMA_CINT)

0xFC04_401D eDMA Clear Error Register (EDMA_CERR)

0xFC04_401E eDMA Set START Bit Register (EDMA_SSRT)

0xFC04_401F eDMA Clear DONE Status Bit Register (EDMA_CDNE)

0xFC04_4026 eDMA Interrupt Request Register (EDMA_INT)

0xFC04_402E eDMA Error Register (EDMA_ERR)

0xFC04_4100

+ hex(n) eDMA Channel n Priority Register (DCHPRIn) for n = 0 – 15

0xFC04_5000

+ hex(32

Transfer Control Descriptor (TCDn) for n = 0 – 15

Width

(bits)

Access Reset Value Section/Page

R/W 0x0000_0000

16.6.1/16-4

R 0x0000_0000

16.6.2/16-5

R/W

0x0000

16.6.3/16-8

16.6.4/16-9

R/W

0x00

0x0000

See Section

256 R/W See Section

16.6.1 eDMA Control Register (EDMA_CR)

The EDMA_CR defines the basic operating configuration of the eDMA. Arbitration can be configured to use a fixed-priority or a round-robin scheme. In fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The channel priority registers assign the priorities (see

Section 16.6.15, “eDMA Channel n Priority Registers (DCHPRIn)”

). In round-robin arbitration mode, the

channel priorities are ignored, and channels are cycled through without regard to priority.

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NOTE

For proper operation, writes to the EDMA_CR register must only be performed when the DMA channels are inactive (TCRn_CSR[ACTIVE] bits are cleared).

Address: 0xFC04_4000 (EDMA_CR)

R 0

Reset 0

Access: User read/write

0 0 0 0 0 0 0 0 0 0 0

R 0

Reset 0

2 1

ERCA EDBG

0 0

Field

31–3

ERCA

EDBG

0 0 0 0 0 0 0 0 0 0

Figure 16-3. eDMA Control Register (EDMA_CR)

0 0

Table 16-3. eDMA_CR Field Descriptions

Description

Reserved, must be cleared.

Enable round robin channel arbitration.

0 Fixed priority arbitration is used for channel selection.

1 Round robin arbitration is used for channel selection.

Enable debug.

0 When in debug mode the DMA continues to operate.

1 When in debug mode, the eDMA stalls the start of a new channel. Executing channels are allowed to complete.

Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.

Reserved, must be cleared.

16.6.2 eDMA Error Status Register (EDMA_ES)

The EDMA_ES provides information concerning the last recorded channel error. Channel errors can be caused by a configuration error (an illegal setting in the transfer-control descriptor or an illegal priority register setting in fixed-arbitration mode) or an error termination to a bus master read or write cycle.

A configuration error is reported when the starting source or destination address, source or destination offsets, minor loop byte count, or the transfer size represent an inconsistent state. Each of these possible causes are detailed in the below list:

• The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries

• The minor loop byte count must be a multiple of the source and destination transfer sizes.

• All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively.

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• In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal.

All channel priority levels must be unique when fixed arbitration mode is enabled.

• If a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32-byte boundary.

• If minor loop channel linking is enabled upon channel completion, a configuration error is reported when the link is attempted if the TCDn_CITER[E_LINK] bit does not equal the

TCDn_BITER[E_LINK] bit.

If enabled, all configuration error conditions, except the scatter/gather and minor-loop link errors, report as the channel activates and asserts an error interrupt request. A scatter/gather configuration error is reported when the scatter/gather operation begins at major loop completion when properly enabled. A minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion.

If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate bus error flag set. In this case, the state of the channel's transfer control descriptor is updated by the eDMA engine with the current source address, destination address and current iteration count at the point of the fault. When a system-bus error occurs, the channel terminates after the read or write transaction (which is already pipelined after errant access) has completed. If a bus error occurs on the last read prior to beginning the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on the last write prior to switching to the next read sequence, the read sequence executes before the channel terminates due to the destination bus error.

The occurrence of any error causes the eDMA engine to stop the active channel immediately, and the appropriate channel bit in the eDMA error register is asserted. At the same time, the details of the error condition are loaded into the EDMA_ES. The major loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the eDMA engine continues operating by servicing the next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminate with the same error condition.

Address: 0xFC04_4004 (EDMA_ES)

R VLD

Reset 0

Access: User read-only

0 0 0 0

R 0

Reset 0

CPE

11 10 9

ERRCHN

8 7 6 5 4 3 2 1 0

SAE SOE DAE DOE NCE SGE SBE DBE

0 0 0 0 0 0 0 0 0 0

Figure 16-4. eDMA Error Status Register (EDMA_ES)

0 0 0 0

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Enhanced Direct Memory Access (eDMA)

Field

VLD

30–15

CPE

Table 16-4. EDMA_ES Field Descriptions

Description

Logical OR of all EDMA_ERR status bits.

0 No EDMA_ERR bits are set.

1 At least one EDMA_ERR bit is set indicating a valid error exists that has not been cleared.

Reserved, must be cleared.

Channel priority error

0 No channel priority error.

1 The last recorded error was a configuration error in the channel priorities. Channel priorities are not unique.

Reserved, must be cleared.

Error channel number. The channel number of the last recorded error. (excluding CPE errors)

13–12

11–8

ERRCHN

SAE

SOE

DAE

DOE

NCE

SGE

SBE

DBE

Source address error.

0 No source address configuration error.

1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]

Source offset error.

0 No source offset configuration error.

1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

Destination address error.

0 No destination address configuration error.

1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

Destination offset error.

0 No destination offset configuration error.

1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

NBYTES/CITER configuration error.

0 No NBYTES/CITER configuration error.

1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.

• TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or

• TCDn_CITER[CITER] is equal to zero, or

• TCDn_CITER[E_LINK] is not equal to TCDn_BITER[E_LINK].

Scatter/gather configuration error.

0 No scatter/gather configuration error.

1 The last recorded error was a configuration error detected in the TCDn_DLAST_SGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[E_SG] is enabled. TCDn_DLAST_SGA is not on a 32 byte boundary.

Source bus error.

0 No source bus error.

1 The last recorded error was a bus error on a source read.

Destination bus error.

0 No destination bus error.

1 The last recorded error was a bus error on a destination write.

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Freescale Semiconductor 16-7

Enhanced Direct Memory Access (eDMA)

16.6.3 eDMA Enable Request Register (EDMA_ERQ)

The EDMA_ERQ register provides a bit map for the16 implemented channels to enable the request signal for each channel. The state of any given channel enable is directly affected by writes to this register; it is also affected by writes to the EDMA_SERQ and EDMA_CERQ. The EDMA_{S,C}ERQR are provided so the request enable for a single channel can easily be modified without needing to perform a read-modify-write sequence to the EDMA_ERQ.

DMA request input signals and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the eDMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request.

Address: 0xFC04_400E (EDMA_ERQ)

R ERQ

Reset 0

ERQ

Figure 16-5. eDMA Enable Request Register (EDMA_ERQ)

ERQ

Access: User read/write

ERQ

Table 16-5. EDMA_ERQ Field Descriptions

Field

15–0

ERQn

Description

Enable DMA Request n.

0 The DMA request signal for channel n is disabled.

1 The DMA request signal for channel n is enabled.

The assignments between the DMA requests from the peripherals to the channels of the eDMA are shown

in Table 16-6 .

Table 16-6. DMA Request Summary for eDMA

Channel

Source

DREQ0

UISR0[FFULL/RXRDY]

UISR0[TXRDY]

UISR1[FFULL/RXRDY]

UISR1[TXRDY]

UISR2[FFULL/RXRDY]

UISR2[TXRDY]

DTER0[CAP] or DTER0[REF]

DTER1[CAP] or DTER1[REF]

DTER2[CAP] or DTER2[REF]

Description

External DMA request 0

UART0 Receive

UART0 Transmit

UART1 Receive

UART1 Transmit

UART2 Receive

UART2 Transmit

Timer 0

Timer 1

Timer 2

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Enhanced Direct Memory Access (eDMA)

Channel

11–15

Table 16-6. DMA Request Summary for eDMA (continued)

Source

DTER3[CAP] or DTER3[REF]

Software Activated

Description

Timer 3

Activated explicitly by setting the

TCDn_CSR[START] bit

As a given channel completes the processing of its major iteration count, a flag in the transfer control descriptor that affect the ending state of the EDMA_ERQ bit for that channel. If the TCDn_CSR[D_REQ] bit is set, the corresponding EDMA_ERQ bit is cleared, disabling the DMA request. If the D_REQ bit clears, the state of the EDMA_ERQ bit is unaffected.

16.6.4 eDMA Enable Error Interrupt Registers (EDMA_EEI)

The EDMA_EEI register provides a bit map for the16 channels to enable the error interrupt signal for each channel. The state of any given channel’s error interrupt enable is directly affected by writes to this register; it is also affected by writes to the EDMA_SEEI and EDMA_CEEI. The EDMA_{S,C}EEIR are provided so the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the EDMA_EEI register.

The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller.

Address: 0xFC04_4016 (EDNA_EEI) Access: User read/write

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI9 EEI8 EEI7 EEI6 EEI5 EEI4 EEI3 EEI2 EEI1 EEI0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 16-6. eDMA Enable Error Interrupt Register (EDMA_EEI)

Field

15–0

EEIn

Table 16-7. EDMA_EEI Field Descriptions

Description

Enable error interrupt n.

0 The error signal for channel n does not generate an error interrupt.

1 The assertion of the error signal for channel n generates an error interrupt request.

16.6.5 eDMA Set Enable Request Register (EDMA_SERQ)

The EDMA_SERQ provides a simple memory-mapped mechanism to set a given bit in the EDMA_ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the EDMA_ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire contents of EDMA_ERQ to be set. Reads of this register return all zeroes.

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Freescale Semiconductor 16-9

Enhanced Direct Memory Access (eDMA)

Address: 0xFC04_4018 (EDMA_SERQ)

Reset

SAER

Table 16-8. EDMA_SERQ Field Descriptions

SERQ

0 0 0 0

Figure 16-7. eDMA Set Enable Request Register (EDMA_SERQ)

Access: User write-only

Field

SAER

5–4

3–0

SERQ

Description

Reserved, must be cleared.

Set all enable requests.

0 Set only those EDMA_ERQ bits specified in the SERQ field.

1 Set all bits in EDMA_ERQ.

Reserved, must be cleared.

Set enable request. Sets the corresponding bit in EDMA_ERQ

16.6.6 eDMA Clear Enable Request Register (EDMA_CERQ)

The EDMA_CERQ provides a simple memory-mapped mechanism to clear a given bit in the

EDMA_ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the EDMA_ERQ to be cleared. Setting the CAER bit provides a global clear function, forcing the entire contents of the EDMA_ERQ to be cleared, disabling all DMA request inputs.

Reads of this register return all zeroes.

Address: 0xFC04_4019 (EDMA_CERQ)

Reset

CAER

Table 16-9. EDMA_CERQ Field Descriptions

CERQ

Figure 16-8. eDMA Clear Enable Request Register (EDMA_CERQ)

Access: User write-only

Field

CAER

Description

Reserved, must be cleared.

Clear all enable requests.

0 Clear only those EDMA_ERQ bits specified in the CERQ field.

1 Clear all bits in EDMA_ERQ.

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Enhanced Direct Memory Access (eDMA)

Field

5–4

3–0

CERQ

Table 16-9. EDMA_CERQ Field Descriptions (continued)

Description

Reserved, must be cleared.

Clear enable request. Clears the corresponding bit in EDMA_ERQ.

16.6.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEI)

The EDMA_SEEI provides a simple memory-mapped mechanism to set a given bit in the EDMA_EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EDMA_EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire

EDMA_EEI contents to be set. Reads of this register return all zeroes.

Address: 0xFC04_401A (EDMA_SEEI)

Reset

SAEE

Table 16-10. EDMA_SEEI Field Descriptions

SEEI

Figure 16-9. eDMA Set Enable Error Interrupt Register (EDMA_SEEI)

Access: User write-only

Field

SAEE

5–4

3–0

SEEI

Description

Reserved, must be cleared.

Sets all enable error interrupts.

0 Set only those EDMA_EEI bits specified in the SEEI field.

1 Sets all bits in EDMA_EEI.

Reserved, must be cleared.

Set enable error interrupt. Sets the corresponding bit in EDMA_EEI.

16.6.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)

The EDMA_CEEI provides a simple memory-mapped mechanism to clear a given bit in the EDMA_EEI to disable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EDMA_EEI to be cleared. Setting the CAEE bit provides a global clear function, forcing the EDMA_EEI contents to be cleared, disabling all DMA request inputs. Reads of this register return all zeroes.

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16-11

Enhanced Direct Memory Access (eDMA)

Address: 0xFC04_401B (EDNA_CEEI)

Reset

Access: User write-only

0 7

CAEE

CEEI

0 0 0 0 0

Figure 16-10. eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)

Table 16-11. EDMA_CEEI Field Descriptions

Field

CAEE

5–4

3–0

CEEI

Description

Reserved, must be cleared.

Clear all enable error interrupts.

0 Clear only those EDMA_EEI bits specified in the CEEI field.

1 Clear all bits in EDMA_EEI.

Reserved, must be cleared.

Clear enable error interrupt. Clears the corresponding bit in EDMA_EEI.

16.6.9 eDMA Clear Interrupt Request Register (EDMA_CINT)

The EDMA_CINT provides a simple, memory-mapped mechanism to clear a given bit in the EDMA_INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the EDMA_INT to be cleared. Setting the CAIR bit provides a global clear function, forcing the entire contents of the EDMA_INT to be cleared, disabling all DMA interrupt requests. Reads of this register return all zeroes.

Address: 0xFC04_401C (EDMA_CINT)

Reset

CAIR

CINT

0 0 0 0

Figure 16-11. eDMA Clear Interrupt Request (EDMA_CINT)

Table 16-12. EDMA_CINT Field Descriptions

Access: User write-only

1 0

0 0

Field

CAIR

Description

Reserved, must be cleared.

Clear all interrupt requests.

0 Clear only those EDMA_INT bits specified in the CINT field.

1 Clear all bits in EDMA_INT.

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16-12 Freescale Semiconductor

Field

5–4

3–0

CINT

Enhanced Direct Memory Access (eDMA)

Table 16-12. EDMA_CINT Field Descriptions (continued)

Description

Reserved, must be cleared.

Clear interrupt request. Clears the corresponding bit in EDMA_INT.

16.6.10 eDMA Clear Error Register (EDMA_CERR)

The EDMA_CERR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the EDMA_ERR to be cleared. Setting the CAEI bit provides a global clear function, forcing the EDMA_ERR contents to be cleared, clearing all channel error indicators. Reads of this register return all zeroes.

Address: 0xFC04_401D (EDMA_CERR)

Reset

CAEI

Table 16-13. EDMA_CERR Field Descriptions

CERR

0 0 0 0

Figure 16-12. eDMA Clear Error Register (EDMA_CERR)

Access: User write-only

Field

CAEI

5–4

3–0

CERR

Description

Reserved, must be cleared.

Clear all error indicators.

0 Clear only those EDMA_ERR bits specified in the CERR field.

1 Clear all bits in EDMA_ERR.

Reserved, must be cleared.

Clear error indicator. Clears the corresponding bit in EDMA_ERR.

16.6.11 eDMA Set START Bit Register (EDMA_SSRT)

The EDMA_SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. Reads of this register return all zeroes.

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

16-13

Enhanced Direct Memory Access (eDMA)

Address: 0xFC04_401E (EDMA_SSRT)

Reset

SAST

Table 16-14. EDMA_SSRT Field Descriptions

SSRT

0 0 0 0

Figure 16-13. eDMA Set START Bit Register (EDMA_SSRT)

Access: User write-only

Field

SAST

5–4

3–0

SSRT

Description

Reserved, must be cleared.

Set all START bits (activates all channels).

0 Set only those TCDn_CSR[START] bits specified in the SSRT field.

1 Set all bits in TCDn_CSR[START].

Reserved, must be cleared.

Set START bit. Sets the corresponding bit in TCDn_CSR[START].

16.6.12 eDMA Clear DONE Status Bit Register (EDMA_CDNE)

The EDMA_CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE bits to be cleared. Reads of this register return all zeroes.

Address: 0xFC04_401F (EDMA_CDNE)

Reset

Access: User write-only

0 6

CADN

CDNE

0 0 0 0

Figure 16-14. eDMA Clear DONE Status Bit Register (EDMA_CDNE)

Table 16-15. EDMA_CDNE Field Descriptions

Field

CADN

5–4

3–0

CDNE

Description

Reserved, must be cleared.

Clears all DONE bits.

0 Clears only those TCDn_CSR[DONE] bits specified in the CDNE field.

1 Clears all bits in TCDn_CSR[DONE]

Reserved, must be cleared.

Clear DONE bit. Clears the corresponding bit in TCDn_CSR[DONE].

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Enhanced Direct Memory Access (eDMA)

16.6.13 eDMA Interrupt Request Register (EDMA_INT)

The EDMA_INT provide a bit map for the16 channels signaling the presence of an interrupt request for each channel. Depending on the appropriate bit setting in the transfer-control descriptions, the eDMA engine generates an interrupt a data transfer completion. The outputs of this register are directly routed to the interrupt controller (INTC). During the interrupt-service routine associated with any given channel, it is the software’s responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the EDMA_CINT in the interrupt service routine is used for this purpose.

The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the EDMA_CINT. On writes to the EDMA_INT, a 1 in any bit position clears the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding channel’s current interrupt status. The EDMA_CINT is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the

EDMA_INT.

Address: 0xFC04_4026 (EDMA_INT) Access: User read/write

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0

W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 16-15. eDMA Interrupt Request Register (EDMA_INT)

Table 16-16. EDMA_INT Field Descriptions

Field

15–0

INTn eDMA interrupt request n

0 The interrupt request for channel n is cleared.

1 The interrupt request for channel n is active.

Description

16.6.14 eDMA Error Register (EDMA_ERR)

The EDMA_ERR provide a bit map for the16 channels, signaling the presence of an error for each channel.

The eDMA engine signals the occurrence of a error condition by setting the appropriate bit in this register.

The outputs of this register are enabled by the contents of the EDMA_EEI,and then routed to the interrupt controller. During the execution of the interrupt-service routine associated with any DMA errors, it is software’s responsibility to clear the appropriate bit, negating the error-interrupt request. Typically, a write to the EDMA_CERR in the interrupt-service routine is used for this purpose. The normal DMA channel completion indicators (setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request) are not affected when an error is detected.

The contents of this register can also be polled because a non-zero value indicates the presence of a channel error regardless of the state of the EDMA_EEI. The state of any given channel’s error indicators is affected by writes to this register; it is also affected by writes to the EDMA_CERR. On writes to the EDMA_ERR, a one in any bit position clears the corresponding channel’s error status. A zero in any bit position has no affect on the corresponding channel’s current error status. The EDMA_CERR is provided so the error indicator for a single channel can easily be cleared.

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Freescale Semiconductor 16-15

Enhanced Direct Memory Access (eDMA)

Address: 0xFC04_402E (EDMA_ERR) Access: User read/write

R ERR

ERR

W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 16-16. eDMA Error (EDMA_ERR) Register

Table 16-17. EDMA_ERR Field Descriptions

Description Field

15–0

ERRn eDMA Error n.

0 An error in channel n has not occurred.

1 An error in channel n has occurred.

16.6.15 eDMA Channel n Priority Registers (DCHPRIn)

When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel. The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. Software must program the channel priorities with unique values. Otherwise, a configuration error is reported. The range of the priority value is limited to the values of 0 through 15.

Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit. Channel preemption allows the executing channel’s data transfers to temporarily suspend in favor of starting a higher priority channel. After the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution. After the restored channel completes one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption (attempting to preempt a preempting channel) is not supported. After a preempting channel begins execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected.

Address: 0xFC04_4100 + n, where n = 0 – 15 (DCHPRIn) Access: User read/write

7 6

3 2 1 0

ECP CHPRI

Reset 0 0 0 0

–

Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.

Figure 16-17. eDMA Channel n Priority Register (DCHPRIn)

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16-16 Freescale Semiconductor

Field

ECP

6–4

3–0

CHPRI

Enhanced Direct Memory Access (eDMA)

Table 16-18. DCHPRIn Field Descriptions

Description

Enable channel preemption.

0 Channel n cannot be suspended by a higher priority channel’s service request.

1 Channel n can be temporarily suspended by the service request of a higher priority channel.

Reserved, must be cleared.

Channel n arbitration priority. Channel priority when fixed-priority arbitration is enabled.

16.6.16 Transfer Control Descriptors (TCDn)

Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel

1,... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. Table 16-19

is a register list of the basic TCD structure.

Table 16-19. TCDn Memory Structure eDMA Offset TCDn Register Name Abbreviation

Width

(bits)

0xFC04_5000 + (0x20

0xFC04_5004 + (0x20

0xFC04_5006 + (0x20

0xFC04_5008 + (0x20

0xFC04_500C + (0x20

0xFC04_5010 + (0x20

0xFC04_5014 + (0x20

0xFC04_5016 + (0x20

Source Address

Transfer Attributes

Signed Source Address Offset

Minor Byte Count

Last Source Address Adjustment

Destination Address

Current Minor Loop Link, Major Loop Count

Signed Destination Address Offset

TCDn_SADDR

TCDn_ATTR

TCDn_SOFF

TCDn_NBYTES

TCDn_SLAST

TCDn_DADDR

TCDn_CITER

TCDn_DOFF

0xFC04_5018 + (0x20

n) Last Destination Address Adjustment/Scatter Gather Address TCDn_DLAST_SGA 32

0xFC04_501C + (0x20

n) Beginning Minor Loop Link, Major Loop Count TCDn_BITER 16

0xFC04_501E + (0x20

n) Control and Status TCDn_CSR 16

The following figures and tables define the fields of the TCDn structure:

Address: 0xFC04_5000 + (0x20

n) (TCDn_SADDR) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SADDR

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 16-18. TCDn Source Address (TCDn_SADDR)

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Freescale Semiconductor 16-17

Enhanced Direct Memory Access (eDMA)

Field

31–0

SADDR

Table 16-20. TCDn_SADDR Field Descriptions

Description

Source address. Memory address pointing to the source data.

Address: 0xFC04_5004 + (0x20

n) (TCDn_ATTR)

14 13 12 11 10 15

Reset — —

SMOD

— — — —

SSIZE

—

8 7 6 5

DMOD

— — — — —

Figure 16-19. TCDn Transfer Attributes (TCDn_ATTR)

Table 16-21. TCDn_ATTR Field Descriptions

Field

15–11

SMOD

10–8

SSIZE

Description

Source address modulo.

0 Source address modulo feature is disabled.

non-0 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed or the original register value. The setting of this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range.

Source data transfer size.

000 8-bit

001 16-bit

010 32-bit

100 16-byte

Else Reserved

The attempted use of a Reserved encoding causes a configuration error.

Destination address modulo. See the SMOD definition.

7–3

DMOD

2–0

DSIZE

Destination data transfer size. See the SSIZE definition.

Access: User read/write

2 1 0

DSIZE

— — — —

Address: 0xFC04_5006 + (0x20

n) (TCDn_SOFF)

14 13 12 11 10 15

Reset — — — — — —

—

SOFF

—

Figure 16-20. TCDn Signed Source Address Offset (TCDn_SOFF)

Access: User read/write

—

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16-18 Freescale Semiconductor

Field

15–0

SOFF

Enhanced Direct Memory Access (eDMA)

Table 16-22. TCDn_SOFF Field Descriptions

Description

Source address signed offset. Sign-extended offset applied to the current source address to form the next-state value as each source read is completed.

Address: 0xFC04_5008 + (0x20

n) (TCDn_NBYTES) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NBYTES

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 16-21. TCDn Minor Byte Count (TCDn_NBYTES)

Table 16-23. TCDn_NBYTES Field Descriptions

Field

31–0

NBYTES

Description

Minor byte transfer count. Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. (Although, it may be stalled by using the bandwidth control field, or via preemption.) After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed.

Note: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer.

Address: 0xFC04_500C + (0x20

n) (TCDn_SLAST) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SLAST

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 16-22. TCDn Source Last Address Adjustment (TCDn_SLAST)

Field

31–0

SLAST

Table 16-24. TCDn_SLAST Field Descriptions

Description

Last source address adjustment. Adjustment value added to the source address at the completion of the major iteration count. This value can be applied to restore the source address to the initial value, or adjust the address to reference the next data structure.

Address: 0xFC04_5010 + (0x20

n) (TCDn_DADDR) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DADDR

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 16-23. TCDn Destination Address (TCDn_DADDR)

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Field

31–0

DADDR

Table 16-25. TCDn_DADDR Field Descriptions

Description

Destination address. Memory address pointing to the destination data.

Address: 0xFC04_5014 + (0x20

n) (TCDn_CITER) Access: User read/write

E_LINK = 1

E_LINK

E_LINK = 0

E_LINK

Reset —

12 11 10

LINKCH

9 8 7

CITER

6 5 4

CITER

3 2 1

— — — — — — — — — — — — — —

Figure 16-24. TCDn Current Major Iteration Count (TCDn_CITER)

—

Field

E_LINK

14–13

12–9

LINKCH

14–0 or

8–0

CITER

Table 16-26. TCDn_CITER Field Descriptions

Description

Enable channel-to-channel linking on minor-loop complete. As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.

If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJOR_E_LINK channel linking.

0 The channel-to-channel linking is disabled.

1 The channel-to-channel linking is enabled.

Note: This bit must be equal to the BITER.E_LINK bit. Otherwise, a configuration error is reported.

Reserved, must be cleared.

Link channel number. If channel-to-channel linking is enabled (E_LINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request to the channel defined by these four bits by setting that channel’s TCDn_CSR[START] bit.

0–15 Link to DMA channel 0–15

Current major iteration count. This 9-bit (E_LINK = 1) or 15-bit (E_LINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations (e.g., final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count

(BITER) field.

Note: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field.

Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001.

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Address: 0xFC04_5016 + (0x20

n) (TCDn_DOFF)

14 13 12 11 10 15

Reset — — — — — —

9 8

DOFF

7 6 5 4 3

Access: User read/write

— — — — — — —

Figure 16-25. TCDn Destination Address Signed Offset (TCDn_DOFF)

—

Table 16-27. TCDn_DOFF Field Descriptions

Field

15–0

DOFF

Description

Destination address signed offset. Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed.

Address: 0xFC04_5018 + (0x20

n) (TCDn_DLAST_SGA) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DLAST_SGA

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 16-26. TCDn Destination Last Address Adjustment (TCDn_DLAST_SGA)

Table 16-28. TCDn_DLAST_SGA Field Descriptions

Field

31–0

DLAST_SGA

Description

Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather).

If (TCDn_CSR[E_SG] = 0) then

• Adjustment value added to the destination address at the completion of the major iteration count. This value can apply to restore the destination address to the initial value or adjust the address to reference the next data structure.

else

• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, else a configuration error is reported.

Address: 0xFC04_501C + (0x20

n) (TCDn_BITER) Access: User read/write

E_LINK = 1

E_LINK

E_LINK = 0

E_LINK

Reset —

— —

12 11 10

LINKCH

— — —

9 8 7

BITER

— — —

6 5 4

BITER

— — —

3 2 1

— — —

Figure 16-27. TCDn Beginning Major Iteration Count (TCDn_BITER)

—

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Field

E_LINK

14–13

12–9

LINKCH

14–0 or

8–0

BITER

Table 16-29. TCDn_BITER Field Descriptions

Description

Enables channel-to-channel linking on minor loop complete. As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER.LINKCH. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking disables, the BITER value extends to 15 bits in place of a link channel number.

If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJOR_E_LINK channel linking.

0 The channel-to-channel linking is disabled.

1 The channel-to-channel linking is enabled.

Note: When the software loads the TCD, this field must be set equal to the corresponding CITER field.

Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field.

Reserved, must be cleared.

Link channel number. If channel-to-channel linking is enabled (E_LINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel defined by these four bits by setting that channel’s TCDn_CSR[START] bit.

0–15 Link to DMA channel 0–15

Note: When the software loads the TCD, this field must be set equal to the corresponding CITER field.

Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field.

Starting major iteration count. As the transfer control descriptor is first loaded by software, this 9-bit

(E_LINK = 1) or 15-bit (E_LINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field.

Note: When the software loads the TCD, this field must be set equal to the corresponding CITER field.

Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001.

Address: 0xFC04_501E + (0x20

n) (TCDn_CSR)

15 14

Reset —

BWC

—

MAJOR_LINKCH

—

Access: User read/write

7 6 5 4 3 2 1 0

DONE ACTIVE

MAJOR_

E_LINK

E_SG D_REQ

INT_

HALF

INT_

MAJOR

START

0 0 — — — — — 0

Figure 16-28. TCDn Control and Status (TCDn_CSR)

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Table 16-30. TCDn_CSR Field Descriptions

Field Description

15–14

BWC

Bandwidth control. Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch (XBS).

00 No eDMA engine stalls

01 Reserved

10 eDMA engine stalls for 4 cycles after each r/w

11 eDMA engine stalls for 8 cycles after each r/w

Note: If the source and destination sizes are equal, this field is ignored between the first and second transfers and after the last write of each minor loop. This behavior is a side effect of reducing start-up latency.

Reserved, must be cleared.

13–12

11–8

MAJOR_LINKCH

Link channel number.

If (MAJOR_E_LINK = 0) then

• No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted.

else

• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by these four bits by setting that channel’s TCDn_CSR[START] bit.

0–15 Link to DMA channel 0–15

DONE

ACTIVE

Channel done. This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the

CITER count reaches zero; The software clears it, or the hardware when the channel is activated.

Note: This bit must be cleared to write the MAJOR_E_LINK or E_SG bits.

Channel active. This flag signals the channel is currently in execution. It is set when channel service begins, and the eDMA clears it as the minor loop completes or if any error condition is detected.

MAJOR_E_LINK

Enable channel-to-channel linking on major loop complete. As the channel completes the major loop, this flag enables the linking to another channel, defined by MAJOR_LINKCH. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel.

Note: To support the dynamic linking coherency model, this field is forced to zero when written to while the

TCDn_CSR[DONE] bit is set.

0 The channel-to-channel linking is disabled.

1 The channel-to-channel linking is enabled.

E_SG

D_REQ

Enable scatter/gather processing. As the channel completes the major loop, this flag enables scatter/gather processing in the current channel. If enabled, the eDMA engine uses DLAST_SGA as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure loaded as the transfer control descriptor into the local memory.

Note: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.

0 The current channel’s TCD is normal format.

1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.

Disable request. If this flag is set, the eDMA hardware automatically clears the corresponding DMAERQ bit when the current major iteration count reaches zero.

0 The channel’s DMAERQ bit is not affected.

1 The channel’s DMAERQ bit is cleared when the major loop is complete.

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Field

INT_HALF

INT_MAJOR

START

Table 16-30. TCDn_CSR Field Descriptions (continued)

Description

Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the EDMA_INT when the current major iteration count reaches the halfway point. Specifically, the comparison performed by the eDMA engine is (CITER ==

(BITER >> 1)). This halfway point interrupt request is provided to support double-buffered (aka ping-pong) schemes or other types of data movement where the processor needs an early indication of the transfer’s progress. The halfway complete interrupt disables when BITER values are less than two.

0 The half-point interrupt is disabled.

1 The half-point interrupt is enabled.

Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the EDMA_INT when the current major iteration count reaches zero.

0 The end-of-major loop interrupt is disabled.

1 The end-of-major loop interrupt is enabled.

Channel start. If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution.

0 The channel is not explicitly started.

1 The channel is explicitly started via a software initiated service request.

16.7 Functional Description

This section provides an overview of the microarchitecture and functional operation of the eDMA module.

16.7.1 eDMA Microarchitecture

The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. Additionally, the eDMA engine is further partitioned into four submodules:

• eDMA Engine

— Address Path:

This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality. This structure allows data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel activation is asserted while the first channel is active. After a channel is activated, it runs until the minor loop is completed, unless preempted by a higher priority channel. This provides a mechanism (enabled by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time another channel is blocked from execution.

When any channel is selected to execute, the contents of its TCD are read from local memory and loaded into the address path channel x registers for a normal start and into channel y registers for a preemption start. After the minor loop completes execution, the address path hardware writes the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major iteration count is exhausted, additional processing are performed, including the final address pointer updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation.

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— Data Path:

This block implements the bus master read/write datapath. It includes 16 bytes of register storage and the necessary multiplex logic to support any required data alignment. The internal read data bus is the primary input, and the internal write data bus is the primary output.

The address and data path modules directly support the 2-stage pipelined internal bus. The address path module represents the 1st stage of the bus pipeline (address phase), while the data path module implements the 2nd stage of the pipeline (data phase).

— Program Model/Channel Arbitration:

This block implements the first section of the eDMA programming model as well as the channel arbitration logic. The programming model registers are connected to the internal peripheral bus (not shown). The eDMA peripheral request inputs and interrupt request outputs are also connected to this block (via control logic).

— Control:

This block provides all the control functions for the eDMA engine. For data transfers where the source and destination sizes are equal, the eDMA engine performs a series of source read/destination write operations until the number of bytes specified in the minor loop byte count has moved. For descriptors where the sizes are not equal, multiple accesses of the smaller size data are required for each reference of the larger size. As an example, if the source size references 16-bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write.

• Transfer Control Descriptor Memory

— Memory Controller:

This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled.

— Memory Array: TCD storage is implemented using a single-port, synchronous RAM array.

16.7.2 eDMA Basic Data Flow

The basic flow of a data transfer can be partitioned into three segments. As shown in

Figure 16-29

, the first segment involves the channel activation. In the diagram, this example uses the assertion of the eDMA peripheral request signal to request service for channel n. Channel activation via software and the

TCDn_CSR[START] bit follows the same basic flow as peripheral requests. The eDMA request input signal is registered internally and then routed through the eDMA engine: first through the control module, then into the program model and channel arbitration. In the next cycle, the channel arbitration performs, using the fixed-priority or round-robin algorithm. After arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the local memory for TCDn. Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers.

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Write Address

Write Data

Transfer

Control

Descriptor (TCD)

64 n-1 eDMA Engine

Read Data

Program Model/

Channel Arbitration

Address Path

Control

Read Data

Write Data

Address

Data Path eDMA Peripheral

Request

Figure 16-29. eDMA Operation, Part 1

eDMA Done

In the second part of the basic data flow ( Figure 16-30 ), the modules associated with the data transfer

(address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write. This source read/destination write processing continues until the minor byte count has transferred.

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Write Address

Write Data

2 eDMA Engine

Read Data

Transfer

Control

Descriptor (TCD)

Program Model/

Channel Arbitration

Address Path

Control n-1

Read Data

Write Data

Address

Data Path eDMA Peripheral

Request

Figure 16-30. eDMA Operation, Part 2

eDMA Done

After the minor byte count has moved, the final phase of the basic data flow performs. In this segment, the address path logic performs the required updates to certain fields in the appropriate TCD, e.g., SADDR,

DADDR, CITER. If the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor. The updates to the TCD memory and

the assertion of an interrupt request are shown in Figure 16-31 .

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Write Address

Write Data

2 eDMA Engine

Read Data

Transfer

Control

Descriptor (TCD)

Program Model/

Channel Arbitration

Address Path

Control n-1

Read Data

Write Data

Address

Data Path eDMA Peripheral

Request

Figure 16-31. eDMA Operation, Part 3

eDMA Done

16.8 Initialization/Application Information

16.8.1 eDMA Initialization

A typical initialization of the eDMA has the following sequence:

1. Write the EDMA_CR if a configuration other than the default is desired.

2. Write the channel priority levels into the DCHPRIn registers if a configuration other than the default is desired.

3. Enable error interrupts in the EDMA_EEI if so desired.

4. Write the 32-byte TCD for each channel that may request service.

5. Enable any hardware service requests via the EDMA_ERQ.

6. Request channel service by software (setting the TCDn_CSR[START] bit) or hardware (slave device asserting its eDMA peripheral request signal).

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After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The eDMA engine read the entire TCD, including the TCD control and status fields (

Table 16-31

) for the selected channel into its internal address path module. As the TCD is read, the first transfer is initiated on the internal bus unless a configuration error is detected.

Transfers from the source (as defined by the source address, TCDn_SADDR) to the destination (as defined by the destination address, TCDn_DADDR) continue until the specified number of bytes

(TCDn_NBYTES) are transferred. When transfer is complete, the eDMA engine's local TCDn_SADDR,

TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing executes

(interrupts, major loop channel linking, and scatter/gather operations) if enabled.

Table 16-31. TCD Control and Status Fields

TCDn_CSR

Field Name

START

ACTIVE

DONE

D_REQ

BWC

E_SG

INT_HALF

INT_MAJ

Description

Control bit to start channel explicitly when using a software initiated DMA service (Automatically cleared by hardware)

Status bit indicating the channel is currently in execution

Status bit indicating major loop completion (cleared by software when using a software initiated DMA service)

Control bit to disable DMA request at end of major loop completion when using a hardware initiated DMA service

Control bits for throttling bandwidth control of a channel

Control bit to enable scatter-gather feature

Control bit to enable interrupt when major loop is half complete

Control bit to enable interrupt when major loop completes

Table 16-32

shows how each DMA request initiates one minor-loop transfer (iteration) without CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER).

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Table 16-32. Example of Multiple Loop Iterations

DMA Request

Minor Loop

DMA Request

Minor Loop Major Loop

DMA Request

Minor Loop

Table 16-33

lists the memory array terms and how the TCD settings interrelate.

Current Major

Loop Iteration

Count (CITER)

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Table 16-33. Memory Array Terms

xADDR: (Starting Address)

xSIZE

(size of one

data transfer)

Minor Loop

(NBYTES in

Minor Loop, often the same value as xSIZE)

Minor Loop

Offset (xOFF): number of bytes added to current address after each transfer

(often the same value as xSIZE)

Each DMA source (S) and destination (D) has its own:

Address (xADDR)

Size (xSIZE)

Offset (xOFF)

Modulo (xMOD)

Last Address Adjustment (xLAST) where x = S or D

Peripheral queues typically have size and offset equal to NBYTES.

Last Minor Loop

xLAST: Number of bytes added to current address after major loop

(typically used to loop back)

16.8.2 DMA Programming Errors

The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (EDMA_ES[CPE]).

For all error types other than channel priority error, the channel number causing the error is recorded in the EDMA_ES. If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again.

If priority levels are not unique, when any channel requests service, a channel priority error is reported.

The highest channel priority with an active request is selected, but the lowest numbered channel with that priority is selected by arbitration and executed by the eDMA engine. The hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel.

16.8.3 DMA Arbitration Mode Considerations

16.8.3.1

Fixed Channel Arbitration

In this mode, the channel service request from the highest priority channel is selected to execute.

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16.8.3.2

Round Robin Channel Arbitration

Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels

16.8.4 DMA Transfer

16.8.4.1

Single Request

To perform a simple transfer of n bytes of data with one activation, set the major loop to one

(TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the

TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled.

For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a longword-wide port located at

0x2000. The address offsets are programmed in increments to match the transfer size: one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values.

Example 16-1. Single Request DMA Transfer

TCDn_CITER = TCDn_BITER = 1

TCDn_NBYTES = 16

TCDn_SADDR = 0x1000

TCDn_SOFF = 1

TCDn_ATTR[SSIZE] = 0

TCDn_SLAST = -16

TCDn_DADDR = 0x2000

TCDn_DOFF = 4

TCDn_ATTR[DSIZE] = 2

TCDn_DLAST_SGA= –16

TCDn_CSR[INT_MAJ] = 1

TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized)

All other TCDn fields = 0

This generates the following event sequence:

1. User write to the TCDn_CSR[START] bit requests channel service.

2. The channel is selected by arbitration for servicing.

3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,

TCDn_CSR[ACTIVE] = 1.

4. eDMA engine reads: channel TCD data from local memory to internal register file.

5. The source-to-destination transfers are executed as follows: a) Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003.

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b) Write longword to location 0x2000

→ first iteration of the minor loop.

c) Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007.

d) Write longword to location 0x2004

→ second iteration of the minor loop.

e) Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B.

f) Write longword to location 0x2008

→ third iteration of the minor loop.

g) Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F.

h) Write longword to location 0x200C

→ last iteration of the minor loop → major loop complete.

6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER

= 1 (TCDn_BITER).

7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, EDMA_INT[n]

= 1.

8. The channel retires and the eDMA goes idle or services the next channel.

16.8.4.2

Multiple Requests

Besides transferring 32 bytes via two hardware requests, the next example is the same as previous. The only fields that change are the major loop iteration count and the final address offsets. The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel’s hardware requests are enabled in EDMA_ERQ, the slave device initiates channel service requests.

TCDn_CITER = TCDn_BITER = 2

TCDn_SLAST = –32

TCDn_DLAST_SGA = –32

This would generate the following sequence of events:

1. First hardware (eDMA peripheral) request for channel service.

2. The channel is selected by arbitration for servicing.

3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE]

= 1.

4. eDMA engine reads: channel TCDn data from local memory to internal register file.

5. The source to destination transfers are executed as follows: a) Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003.

b) Write longword to location 0x2000

→ first iteration of the minor loop.

c) Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007.

d) Write longword to location 0x2004

→ second iteration of the minor loop.

e) Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B.

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f) Write longword to location 0x2008

→ third iteration of the minor loop.

g) Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F.

h) Write longword to location 0x200C

→ last iteration of the minor loop.

6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1.

7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0.

8. The channel retires

→ one iteration of the major loop. The eDMA goes idle or services the next channel.

9. Second hardware (eDMA peripheral) requests channel service.

10. The channel is selected by arbitration for servicing.

11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE]

= 1.

12. eDMA engine reads: channel TCD data from local memory to internal register file.

13. The source to destination transfers are executed as follows: a) Read byte from location 0x1010, read byte from location 0x1011, read byte from 0x1012, read byte from 0x1013.

b) Write longword to location 0x2010

→ first iteration of the minor loop.

c) Read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read byte from 0x1017.

d) Write longword to location 0x2014

→ second iteration of the minor loop.

e) Read byte from location 0x1018, read byte from location 0x1019, read byte from 0x101A, read byte from 0x101B.

f) Write longword to location 0x2018

→ third iteration of the minor loop.

g) Read byte from location 0x101C, read byte from location 0x101D, read byte from 0x101E, read byte from 0x101F.

h) Write longword to location 0x201C

→ last iteration of the minor loop → major loop complete.

14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2

(TCDn_BITER).

15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, EDMA_INT[n] = 1.

16. The channel retires

→ major loop complete. The eDMA goes idle or services the next channel.

16.8.4.3

Modulo Feature

The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and destination in the TCD, and it specifies which lower address bits increment from their original value after the address+offset calculation. All upper address bits remain the same as in the original value. A setting of 0 for this field disables the modulo feature.

Table 16-34

shows how the transfer addresses are specified based on the setting of the MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits

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(0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the offset is set to 4 bytes and the MOD field is set to 4, allowing for a 2

byte (16-byte) size queue.

Table 16-34. Modulo Feature Example

Transfer

Number

Address

0x12345670

0x12345674

0x12345678

0x1234567C

0x12345670

0x12345674

16.8.5 eDMA TCDn Status Monitoring

16.8.5.1

Minor Loop Complete

There are two methods to test for minor loop completion when using software initiated service requests.

The first is to read the TCDn_CITER field and test for a change. (Another method may be extracted from the sequence shown below). The second method is to test the TCDn_CSR[START] bit and the

TCDn_CSR[ACTIVE] bit. The minor-loop-complete condition is indicated by both bits reading zero after the TCDn_CSR[START] was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active status may be missed if the channel execution is short in duration.

The TCD status bits execute the following sequence for a software activated channel:

START

TCDn_CSR bits

ACTIVE

DONE

State

Channel service request via software

Channel is executing

Channel has completed the minor loop and is idle

Channel has completed the major loop and is idle

The best method to test for minor-loop completion when using hardware (peripheral) initiated service requests is to read the TCDn_CITER field and test for a change. The hardware request and acknowledge handshakes signals are not visible in the programmer’s model.

The TCD status bits execute the following sequence for a hardware-activated channel:

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START

TCDn_CSR bits

ACTIVE

DONE

State

Channel service request via hardware (peripheral request asserted)

Channel is executing

Channel has completed the minor loop and is idle

Channel has completed the major loop and is idle

For both activation types, the major-loop-complete status is explicitly indicated via the

TCDn_CSR[DONE] bit.

The TCDn_CSR[START] bit is cleared automatically when the channel begins execution regardless of how the channel activates.

16.8.5.2

Active Channel TCDn Reads

The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES values if read while a channel executes. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses (SADDR and DADDR) and NBYTES (decrements to zero as the transfer progresses) can give an indication of the progress of the transfer. All other values are read back from the

TCD local memory.

16.8.5.3

Preemption Status

Preemption is available only when fixed arbitration is selected as the channel arbitration mode. A preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes active. When the eDMA engine is not operating in fixed channel arbitration mode, the determination of the actively running relative priority outstanding requests become undefined. Channel priorities are treated as equal (constantly rotating) when round-robin arbitration mode is selected.

The TCDn_CSR[ACTIVE] bit for the preempted channel remains asserted throughout the preemption.

The preempted channel is temporarily suspended while the preempting channel executes one major loop iteration. If two TCDn_CSR[ACTIVE] bits are set simultaneously in the global TCD map, a higher priority channel is actively preempting a lower priority channel.

16.8.6 Channel Linking

Channel linking (or chaining) is a mechanism where one channel sets the TCDn_CSR[START] bit of another channel (or itself), therefore initiating a service request for that channel. When properly enabled, the EDMA engine automatically performs this operation at the major or minor loop completion.

The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). The TCDn_CITER[E_LINK] field determines whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the major loop except for the last. When the major

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loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. For example, the initial fields of:

TCDn_CITER[E_LINK] = 1

TCDn_CITER[LINKCH] = 0xC

TCDn_CITER[CITER] value = 0x4

TCDn_CSR[MAJOR_E_LINK] = 1

TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as:

1. Minor loop done

→ set TCD12_CSR[START] bit

2. Minor loop done

→ set TCD12_CSR[START] bit

3. Minor loop done

→ set TCD12_CSR[START] bit

4. Minor loop done, major loop done

→ set TCD7_CSR[START] bit

When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the TCDn_CITER[CITER] field uses a nine bit vector to form the current iteration count. When minor loop linking is disabled

(TCDn_CITER[E_LINK] = 0), the TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the

CITER value to increase the range of the CITER.

NOTE

The TCDn_CITER[E_LINK] bit and the TCDn_BITER[E_LINK] bit must equal or a configuration error is reported. The CITER and BITER vector widths must be equal to calculate the major loop, half-way done interrupt point.

Table 16-35

summarizes how a DMA channel can link to another DMA channel, i.e, use another channel’s

TCD, at the end of a loop.

Table 16-35. Channel Linking Parameters

Desired Link

Behavior

TCD Control Field Name

Link at end of

Minor Loop

Link at end of

Major Loop

Description

CITER[E_LINK]

CITER[LINKCH]

Enable channel-to-channel linking on minor loop completion (current iteration)

Link channel number when linking at end of minor loop (current iteration)

CSR[MAJOR_E_LINK] Enable channel-to-channel linking on major loop completion

CSR[MAJOR_LINKCH] Link channel number when linking at end of major loop

16.8.7 Dynamic Programming

This section provides recommended methods to change the programming model during channel execution.

16.8.7.1

Dynamic Channel Linking and Dynamic Scatter/Gather

Dynamic channel linking and dynamic scatter/gather is the process of changing the

TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits during channel execution. These bits are read

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from the TCD local memory at the end of channel execution, therefore allowing software to enable either feature during channel execution.

Because software can change the configuration during execution, a coherency sequence must be followed.

Consider the scenario the user attempts to execute a dynamic channel link by enabling the

TCDn_CSR[MAJOR_E_LINK] bit as the eDMA engine retires the channel. The

TCDn_CSR[MAJOR_E_LINK] would be set in the programmer’s model, but it would be indeterminate whether the actual link was made before the channel retired.

The following coherency sequence is recommended when executing a dynamic channel link or dynamic scatter/gather request:

1. Set the TCDn_CSR[MAJOR_E_LINK] bit.

2. Read back the TCDn_CSR[MAJOR_E_LINK] bit.

3. Test the TCDn_CSR[MAJOR_E_LINK] request status.

a) If the bit is set, the dynamic link attempt was successful.

b) If the bit is cleared, the attempted dynamic link did not succeed, the channel was already retiring.

This same coherency model is true for dynamic scatter/gather operations. For both dynamic requests, the

TCD local memory controller forces the TCDn_CSR[MAJOR_E_LINK] and TCDn_CSR[E_SG] bits to zero on any writes to a TCDn after the TCDn_CSR[DONE] bit for that channel is set, indicating the major loop is complete.

NOTE

Software must clear the TCDn_CSR[DONE] bit before writing the

TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits. The

TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after a channel begins execution.

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Chapter 17 FlexBus

17.1 Introduction

This chapter describes external bus data transfer operations and error conditions. It describes transfers initiated by the ColdFire processor (or any other bus master) and includes detailed timing diagrams showing the interaction of signals in supported bus operations.

NOTE

In this chapter, unless otherwise noted, clock refers to the FB_CLK used for the external bus (f sys/2

The external data bus is shared between the FlexBus module and the

SDRAM controller. When the SDRAM controller is in SDR mode

(DRAMSEL = 1), the data bus is switched dynamically between the

SDRAM controller and the FlexBus module. However, when the SDRAM controller is in DDR mode (DRAMSEL = 0), D[31:16] is dedicated to the

SDRAM data bus and D[15:0] is dedicated to the FlexBus data bus. In this case, external pins D[15:0], are mapped internally to the upper two bytes of the FlexBus data bus, FB_D[31:16]. This chapter only uses FB_D[31:0] or

FB_D[31:X] to designate the data bus, but the actual pins used depend on the DRAMSEL setting. Take this into consideration throughout this chapter.

17.1.1 Overview

A multi-function external bus interface called the FlexBus interface controller is provided on the device with basic functionality of interfacing to slave-only devices with a maximum bus frequency up to

83.33 MHz. It can be directly connected to the following asynchronous or synchronous devices with little or no additional circuitry:

• External boot ROMs

• Flash memories

• Gate-array logic

• Other simple target (slave) devices

For asynchronous devices, a simple chip-select based interface can be used.

The FlexBus interface has up to six general purpose chip-selects, FB_CS[5:0]. The actual number of chip selects available depends upon the device and its pin configuration. See

Table 13-1 for more details.

Chip-select FB_CS0 can be dedicated to boot memory access and programmed to be byte (8 bits), word

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(16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM and flash memories.

17.1.2 Features

Key FlexBus features include:

• Six independent, user-programmable chip-select signals (FB_CS[5:0]) that can interface with external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals

• 8-, 16-, and 32-bit port sizes

• Byte-, word-, longword-, and 16-byte line-sized transfers

• Programmable burst- and burst-inhibited transfers selectable for each chip select and transfer direction

• Programmable address-setup time with respect to the assertion of chip select

• Programmable address-hold time with respect to the negation of chip select and transfer direction

17.2 External Signals

This section describes the external signals involved in data-transfer operations.

Table 17-1. FlexBus Signal Summary

Signal Name I/O

Description

FB_A[23:0]

FB_D[31:0]

FB_CS[5:0]

O Address bus. During the first cycle, this bus drives the upper address byte, addr[31:24].

I/O Data bus

O General purpose chip-selects. The actual number of chip selects available depends upon the device and its pin configuration. See

Table 13-1

for more details.

FB_BE/BWE[3:0]

FB_OE

FB_R/W

FB_TS

Byte enable/byte write enable

Output enable

Read/write. 1 = Read, 0 = Write

Transfer start

FB_TA I Transfer acknowledge

Because this device shares the FlexBus signals with the SDRAM controller, these signal directions are only valid when the FlexBus controls them. The directions may change during SDRAM cycles.

17.2.1 Address and Data Buses (FB_A[23:0], FB_D[31:0])

The FB_A[23:0] and FB_D[31:0] buses carry the address and data, respectively. The number of byte lanes carrying the data is determined by the port size associated with the matching chip select.

Because this device shares the FlexBus signals with the SDRAM controller, these signals tristate between bus cycles.

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17.2.2 Chip Selects (FB_CS[5:0])

The chip-select signal indicates which device is selected. A particular chip-select asserts when the transfer address is within the device’s address space, as defined in the base- and mask-address registers. The actual number of chip selects available depends upon the pin configuration. See

Table 13-1 for more details.

17.2.3 Byte Enables/Byte Write Enables (FB_BE/BWE[3:0])

When driven low, the byte enable (FB_BE/BWE[3:0]) outputs indicate data is to be latched or driven onto a byte of the data bus. FB_BE/BWEn signals are asserted only to the memory bytes used during read or write accesses. A configuration option is provided to assert these signals on reads and writes (byte enable) or writes only (byte-write enable).

The FB_BE/BWEn signals are asserted during accesses to on-chip peripherals but not to on-chip SRAM or cache. For external SRAM or flash devices, the FB_BE/BWEn outputs must be connected to individual byte strobe signals.

17.2.4 Output Enable (FB_OE)

The output enable signal (FB_OE) is sent to the interfacing memory and/or peripheral to enable a read transfer. FB_OE is only asserted during read accesses when a chip select matches the current address decode.

Because this device shares the FlexBus signals with the SDRAM controller, this signal tristates between bus cycles.

17.2.5 Read/Write (FB_R/W)

The processor drives the FB_R/W signal to indicate the current bus operation direction. It is driven high during read bus cycles and low during write bus cycles.

Because this device shares the FlexBus signals with the SDRAM controller, this signal tristates between bus cycles.

17.2.6 Transfer Start (FB_TS)

The assertion of FB_TS indicates that the device has begun a bus transaction and the address and attributes are valid. FB_TS is asserted for one bus clock cycle.

Because this device shares the FlexBus signals with the SDRAM controller, this signal tristates between bus cycles.

17.2.7 Transfer Acknowledge (FB_TA)

This signal indicates the external data transfer is complete. When the processor recognizes FB_TA during a read cycle, it latches the data and then terminates the bus cycle. When the processor recognizes FB_TA during a write cycle, the bus cycle is terminated.

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If auto-acknowledge is disabled (CSCRn[AA] = 0), the external device drives FB_TA to terminate the bus transfer; if auto-acknowledge is enabled (CSCRn[AA] = 1), FB_TA is generated internally after a specified number of wait states, or the external device may assert external FB_TA before the wait-state countdown, terminating the cycle early. The device negates FB_CSn one cycle after the last FB_TA asserts. During read cycles, the peripheral must continue to drive data until FB_TA is recognized. For write cycles, the processor continues driving data one clock after FB_CSn is negated.

The number of wait states is determined by CSCRn or the external FB_TA input. If the external FB_TA is used, the peripheral has total control on the number of wait states.

NOTE

External devices should only assert FB_TA while the FB_CSn signal to the external device is asserted.

Because this device shares the FlexBus signals with the SDRAM controller, this signal tristates between bus cycles.

17.3 Memory Map/Register Definition

The following tables describe the registers and bit meanings for configuring chip-select operation.

Table 17-2

shows the chip-select register memory map.

The actual number of chip select registers available depends upon the device and its pin configuration. See

Table 13-1

for more details. If the device does not support certain chip select signals or the pin is not configured for a chip-select function, then that corresponding set of chip-select registers has no effect on an external pin.

Address

Table 17-2. FlexBus Chip Select Memory Map

Register

Width

(bits)

Access Reset Value

Section/

Page

R/W 0x0000_0000

17.3.1/17-4

0xFC00_8000

+ (n

0xC)

Chip-Select Address Register (CSARn)

n = 0 – 5

0xFC00_8004

+ (n

0xC)

Chip-Select Mask Register (CSMRn)

n = 0 – 5

0xFC00_8008

+ (n

0xC)

Chip-Select Control Register (CSCRn)

n = 0 – 5

R/W 0x0000_0000

17.3.2/17-5

R/W See Section

17.3.3/17-6

17.3.1 Chip-Select Address Registers (CSAR0 – CSAR5)

The CSARn registers specify the chip-select base addresses.

NOTE

Because the FlexBus module is one of the slaves connected to the crossbar switch, it is only accessible within a certain memory range. The only applicable address ranges for which the chip-selects can be active are

0x0000_0000 – 0x3FFF_FFFF and 0xC000_0000 – 0xDFFF_FFFF. Set the

CSARn registers appropriately.

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Address: 0xFC00_8000 (CSAR0)

0xFC00_800C (CSAR1)

0xFC00_8018 (CSAR2)

0xFC00_8024 (CSAR3)

0xFC00_8030 (CSAR4)

0xFC00_803C (CSAR5)

Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 17-1. Chip-Select Address Registers (CSARn)

Table 17-3. CSARn Field Descriptions

Field Description

31–16

Base address. Defines the base address for memory dedicated to chip-select FB_CSn. BA is compared to bits 31–16 on the internal address bus to determine if chip-select memory is being accessed.

15–0 Reserved, must be cleared.

17.3.2 Chip-Select Mask Registers (CSMR0 – CSMR5)

CSMRn registers specify the address mask and allowable access types for the respective chip-selects.

Address: 0xFC00_8004 (CSMR0)

0xFC00_8010 (CSMR1)

0xFC00_801C (CSMR2)

0xFC00_8028 (CSMR3)

0xFC00_8034 (CSMR4)

0xFC00_8040 (CSMR5)

Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

0 0 0 0 0 0 0

BAM WP

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 17-2. Chip-Select Mask Registers (CSMRn)

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Table 17-4. CSMRn Field Descriptions

Field

31–16

BAM

Description

Base address mask. Defines the chip-select block size by masking address bits. Setting a BAM bit causes the corresponding CSAR bit to be a don’t care in the decode.

0 Corresponding address bit is used in chip-select decode.

1 Corresponding address bit is a don’t care in chip-select decode.

The block size for FB_CSn is 2 n

; n = (number of bits set in respective CSMR[BAM]) + 16.

For example, if CSAR0 equals 0x0000 and CSMR0[BAM] equals 0x0008, FB_CS0 addresses two discontinuous

64-Kbyte memory blocks: one from 0x0_0000 – 0x0_FFFF and one from 0x8_0000 – 0x8_FFFF.

Likewise, for FB_CS0 to access 32 Mbytes of address space starting at location 0x00_0000, FB_CS1 must begin at the next byte after FB_CS0 for a 16-Mbyte address space. Then, CSAR0 equals 0x0000,

CSMR0[BAM] equals 0x01FF, CSAR1 equals 0x0200, and CSMR1[BAM] equals 0x00FF.

15–9 Reserved, must be cleared.

Write protect. Controls write accesses to the address range in the corresponding CSAR. Attempting to write to the range of addresses for which CSARn[WP] is set results in a bus error termination of the internal cycle and no external cycle.

0 Read and write accesses are allowed

1 Only read accesses are allowed

7–1

Reserved, must be cleared.

Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip-selects do not assert until V bit is set (except for FB_CS0, which acts as the global chip-select). Reset clears each CSMRn[V].

Note: At reset, no chip-select other than FB_CS0 can be used until the CSMR0[V] is set. Afterward, FB_CS[5:0] functions as programmed.

0 Chip-select invalid

1 Chip-select valid

17.3.3 Chip-Select Control Registers (CSCR0 – CSCR5)

Each CSCRn controls the auto-acknowledge, address setup and hold times, port size, burst capability, and number of wait states. To support the global chip-select, FB_CS0, the CSCR0 reset values differ from the

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other CSCRs. FB_CS0 allows address decoding for an external device to serve as the boot memory before system initialization and configuration are completed.

Address: 0xFC00_8008 (CSCR0)

0xFC00_8014 (CSCR1)

0xFC00_8020 (CSCR2)

0xFC00_802C (CSCR3)

0xFC00_8038 (CSCR4)

0xFC00_8044 (CSCR5)

30 29 28 31

Reset: CSCR0 0

Reset: CSCR1–5 0

SWS

SWSEN

ASET

Access: User read/write

RDAH

18 17 16

WRAH

1 1 1

0 0 0

Reset: CSCR0

Reset: CSCR1–5

12 11 10 9 8

SBM AA

6 5 4 3

BEM BSTR BSTW

2 1 0

0 0 0

[DRAM

SEL]

[DRAM

SEL]

Figure 17-3. Chip-Select Control Registers (CSCRn)

0 0 0

Table 17-5. CSCRn Field Descriptions

Field Description

31–26

SWS

Secondary wait states. The number of wait states inserted before an internal transfer acknowledge is generated for

a burst transfer except for the first termination, which is controlled by the wait state count. The secondary wait state is used only if the SWSEN bit is set. Otherwise, the WS value is used for all burst transfers.

25–24 Reserved, must be cleared

SWSEN

Secondary wait state enable.

0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers.

1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations.

21–20

ASET

Reserved, must be cleared

Address setup. This field controls the assertion of the chip-select with respect to assertion of a valid address and attributes. The address and attributes are considered valid at the same time FB_TS asserts.

00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn)

01 Assert FB_CSn on second rising clock edge after address is asserted.

10 Assert FB_CSn on third rising clock edge after address is asserted.

11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0)

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Table 17-5. CSCRn Field Descriptions (continued)

Field Description

19–18

RDAH

Read address hold or deselect. This field controls the address and attribute hold time after the termination during a read cycle that hits in the chip-select address space. The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer to a port size smaller than the transfer size, the hold time is only added after the last bus cycle.

The number of cycles the address and attributes are held after FB_CSn negation depends on the value of

CSCRn[AA] as shown below.

RDAH

(FB_CSn Default)

(FB_CS0 Default)

AA = 0

1 cycle

2 cycles

3 cycles

4 cycles

AA = 1

0 cycles

1 cycles

2 cycles

3 cycles

17–16

WRAH

15–10

SBM

7–6

Write address hold or deselect. This field controls the address, data, and attribute hold time after the termination of a write cycle that hits in the chip-select address space. The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer to a port size smaller than the transfer size, the hold time is only added after the last bus cycle.

00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn)

01 Hold address and attributes two cycles after FB_CSn negates on writes.

10 Hold address and attributes three cycles after FB_CSn negates on writes.

11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0)

Wait states. The number of wait states inserted after FB_CSn asserts and before an internal transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states). If AA is reserved, FB_TA must be asserted by the external system regardless of the number of generated wait states. In that case, the external transfer acknowledge ends the cycle. An external FB_TA supersedes the generation of an internal FB_TA.

Split bus mode. For proper operation of the chip select signals, this bit must be set when the SDRAM controller is in

DDR mode (DRAMSEL signal is negated). The reset value of SBM is the opposite of the DRAMSEL signal.

0 Device is not in split bus mode (SDRAM controller is in SDR mode, DRAMSEL = 1).

1 Device is in split bus mode (SDRAM controller is in DDR mode, DRAMSEL = 0).

Note: Placing the device in split bus mode is only controlled by the DRAMSEL signal. This bit is only used to provide correct operation of the chip select signals.

Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by the chip-select address.

0 No internal FB_TA is asserted. Cycle is terminated externally

1 Internal transfer acknowledge is asserted as specified by WS

Note: If AA is set for a corresponding FB_CSn and the external system asserts an external FB_TA before the wait-state countdown asserts the internal FB_TA, the cycle is terminated. Burst cycles increment the address bus between each internal termination.

Note:

Port size. Specifies the data port width associated with each chip-select. It determines where data is driven during write cycles and where data is sampled during read cycles.

00 32-bit port size. Valid data sampled and driven on FB_D[31:0]

01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if SBM = 0 or FB_D[7:0] if SBM = 1

1x 16-bit port size. Valid data sampled and driven on FB_D[31:16] if SBM = 0 or FB_D[15:0] if SBM = 1

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17-8 Freescale Semiconductor

FlexBus

Table 17-5. CSCRn Field Descriptions (continued)

Field

BEM

Description

Byte-enable mode. Specifies the byte enable operation. Certain memories have byte enables that must be asserted during reads and writes. BEM can be set in the relevant CSCR to provide the appropriate mode of byte enable support for these SRAMs.

0 FB_BE/BWE is not asserted for reads. FB_BE/BWE is asserted for data write only.

1 FB_BE/BWE is asserted for read and write accesses.

BSTR

BSTW

2–0

Burst-read enable. Specifies whether burst reads are used for memory associated with each FB_CSn.

0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.

1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.

Burst-write enable. Specifies whether burst writes are used for memory associated with each FB_CSn.

0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes.

1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.

Reserved, must be cleared.

17.4 Functional Description

17.4.1 Chip-Select Operation

Each chip-select has a dedicated set of registers for configuration and control:

• Chip-select address registers (CSARn) control the base address space of the chip-select. See

Section 17.3.1, “Chip-Select Address Registers (CSAR0 – CSAR5).”

• Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See

Section 17.3.2, “Chip-Select Mask Registers (CSMR0 – CSMR5).”

• Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, address setup and hold times, and automatic acknowledge generation features. See

Section 17.3.3, “Chip-Select Control Registers (CSCR0 – CSCR5).”

FB_CS0 is a global chip-select after reset and provides external boot memory capability.

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17-9

FlexBus

17.4.1.1

General Chip-Select Operation

When a bus cycle is routed to the FlexBus, the device first compares its address with the base address and mask configurations programmed for chip-selects 0 to 5 (configured in CSCR0 – CSCR5). The results

depend on if the address matches or not as shown in Table 17-6

Table 17-6. Results of Address Comparison

Address Matches

CSARn?

Yes, one CSAR

Yes, multiple CSARs

Result

The appropriate chip-select is asserted, generating an external bus cycle as defined in the chip-select control register.

The internal bus cycle terminates and no chip select is asserted.

The chip-select signals are driven. However, they are driven using an external burst-inhibited bus cycle with external termination on a 32-bit port.

17.4.1.2

8-, 16-, and 32-Bit Port Sizing

Static bus sizing is programmable through the port size bits, CSCR[PS]. The processor always drives a

-bit address on the FB_A bus regardless of the external device’s address size. The external device must connect its address lines to the appropriate FB_A bits from FB_A0 upward. It must also connect its data lines to the FB_D bus from FB_D31 downward. No bit ordering is required when connecting address and data lines to the FB_A and FB_D buses. For example, a full 16-bit address/16-bit data device connects its

addr[15:0] to FB_A[16:1] and data[15:0] to FB_D[31:16]. See Figure 17-4 for a graphical connection.

17.4.1.3

Global Chip-Select Operation

FB_CS0, the global (boot) chip-select, supports external boot memory accesses before system initialization. Its operation differs from other external chip-select outputs after system reset.

After system reset, FB_CS0 is asserted for every external access. No other chip-select can be used until the valid bit, CSMR0[V], is set; at this point FB_CS0 functions as configured. After this, FB_CS[5:1] can be used as well. At reset, the logic levels on the FB_D[4:3] signals determine global chip-select port size.

See

Chapter 9, “Chip Configuration Module (CCM),”

for more information.

17.4.2 Data Transfer Operation

Data transfers between the chip and other devices involve these signals:

• Address/data bus (FB_A[23:0], FB_D[31:0])

• Control signals (FB_TS, FB_TA, FB_CSn, FB_OE, FB_BE/BWE[3:0])

• Attribute signals (FB_R/W)

The address, write data, FB_TS, FB_CSn, and all attribute signals change on the rising edge of the FlexBus clock (FB_CLK). Read data is latched into the device on the rising edge of the clock.

MCF5208 Reference Manual, Rev 2

17-10 Freescale Semiconductor

FlexBus

The FlexBus supports byte-, word-, longword-, and 16-byte (line) operand transfers and allows accesses to 8-, 16-, and 32-bit data ports.Transfer parameters (address setup and hold, port size, the number of wait states for the external device being accessed, automatic internal transfer termination enable or disable, and

burst enable or disable) are programmed in the chip-select control registers (CSCRs). See Section 17.3.3,

“Chip-Select Control Registers (CSCR0 – CSCR5)

.”

17.4.3 Data Byte Alignment and Physical Connections

The device aligns data transfers in FlexBus byte lanes with the number of lanes depending on the data port width. The byte lane assignment is also dependent on the split bus mode setting in the CSCRn register.

Figure 17-4

shows the byte lanes that external memory connects to and the sequential transfers of a longword transfer for the supported port sizes when not in split bus mode. For example, an 8-bit memory connects to the single lane FB_D[31:24] (FB_BE/BWE0). A longword transfer through this 8-bit port takes four transfers, starting with the MSB to the LSB. A longword transfer through a 32-bit port requires one transfer on each four-byte lane of the FlexBus.

Byte Select

External

Data Bus

FB_BE/BWE0 FB_BE/BWE1 FB_BE/BWE2 FB_BE/BWE3

FB_D[31:24] FB_D[23:16] FB_D[15:8] FB_D[7:0]

32-Bit Port

Memory

16-Bit Port

Memory

Byte 0

Byte 2

Byte 1

Byte 3

Byte 2 Byte 3

Driven with address values

8-Bit Port

Memory

Byte 0

Byte 1

Byte 2

Byte 3

Driven with address values

Figure 17-4. Connections for External Memory Port Sizes (CSCRn[SBM] = 0)

Byte Select

External

Data Bus

FB_BE/BWE0 FB_BE/BWE1

FB_D[15:8] FB_D[7:0]

16-Bit Port

Memory

Byte 0

Byte 2

Byte 1

Byte 3

8-Bit Port

Memory

Driven with address values

Byte 0

Byte 1

Byte 2

Byte 3

Figure 17-5. Connections for External Memory Port Sizes (CSCRn[SBM] = 1)

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 17-11

FlexBus

17.4.4 Bus Cycle Execution

As shown in Figure 17-8 and

Figure 17-10

, basic bus operations occur in four clocks:

1. S0: At the first clock edge, the address, attributes, and FB_TS are driven.

2. S1: FB_CSn is asserted at the second rising clock edge to indicate the device selected; by that time, the address and attributes are valid and stable. FB_TS is negated at this edge.

For a write transfer, data is driven on the bus at this clock edge and continues to be driven until one clock cycle after FB_CSn negates. For a read transfer, data is also driven into the device during this cycle.

External slave asserts FB_TA at this clock edge.

3. S2: Read data and FB_TA are sampled on the third clock edge. FB_TA can be negated after this edge and read data can then be tri-stated.

4. S3: FB_CSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes, and write data.

17.4.4.1

Data Transfer Cycle States

An on-chip state machine controls the data-transfer operation in the device.

Figure 17-6 shows the

state-transition diagram for basic read and write cycles.

Next Cycle

Wait States

S3 S1

Figure 17-6. Data-Transfer-State-Transition Diagram

Table 17-7

describes the states as they appear in subsequent timing diagrams.

Table 17-7. Bus Cycle States

State

Cycle

All

Description

The read or write cycle is initiated. On the rising clock edge, the device places a valid address on

FB_A[ 23 :0], asserts FB_TS, and drives FB_R/W high for a read and low for a write.

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MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

State

Cycle

All

Read

All

Read

All

FlexBus

Table 17-7. Bus Cycle States (continued)

Description

FB_TS is negated on the rising edge of FB_CLK, and FB_CSn is asserted. Data is driven on

FB_D[31:X] for writes, and FB_D[31:X] is tristated for reads. Address continues to be driven on the FB_A pins.

If FB_TA is recognized asserted, then the cycle moves on to S2. If FB_TA is not asserted internally or externally, then the S1 state continues to repeat.

Data is driven by the external device before the next rising edge of FB_CLK (the rising edge that begins S2) with FB_TA asserted.

For internal termination, FB_CSn is negated and the internal system bus transfer is completed.

For external termination, the external device should negate FB_TA, and the FB_CSn chip select negates after the rising edge of FB_CLK at the end of S2.

The processor latches data on the rising clock edge entering S2. The external device can stop driving data after this edge. However, data can be driven until the end of S3 or any additional address hold cycles.

Address, data, and FB_R/W go invalid off the rising edge of FB_CLK at the beginning of S3, terminating the read or write cycle.

17.4.5 FlexBus Timing Examples

NOTE

Because this device shares the FlexBus signals with the SDRAM controller, all signals, except the chip selects, tristate between bus cycles.

17.4.5.1

Basic Read Bus Cycle

During a read cycle, the ColdFire device receives data from memory or a peripheral device. Figure 17-7

is a read cycle flowchart.

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MCF5208 Reference Manual, Rev 2

17-13

FlexBus

NOTE

Throughout this chapter FB_D[31:X] indicates a 32-, 16-, or 8-bit wide data bus.

ColdFire device System

1. Set FB_R/W to read.

2. Place address on FB_D[23:0].

3. Assert FB_TS.

1. Decode address.

1. Negate FB_TS.

Assert FB_CSn.

FlexBus asserts internal FB_TA

(auto-acknowledge/internal termination).

Sample FB_TA low and latch data.

1. Select the appropriate slave device.

2. Drive data on FB_D[31:X].

Assert FB_TA (external termination).

1. Start next cycle.

1. Negate FB_TA (external termination).

Figure 17-7. Read Cycle Flowchart

The read cycle timing diagram is shown in

Figure 17-8

NOTE

In the next set of timing diagrams, the dotted lines indicate FB_TA, FB_OE, and FB_CSn timing when internal termination is used (CSCR[AA] = 1).

The external and internal FB_TA assert at the same time; however, FB_TA is not driven externally for internally-terminated bus cycles.

NOTE

The processor drives the data lines during the first clock cycle of the transfer with the full 32-bit address. This may be ignored by standard connected devices using non-multiplexed address and data buses. However, some applications may find this feature beneficial.

The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the read bus cycles the address signals are indeterminate.

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MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

FlexBus

S0 S1

FB_CLK

FB_A[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

ADDR[31:X]

ADDR[23:0]

DATA

S2 S3 S0

Figure 17-8. Basic Read-Bus Cycle

17.4.5.2

Basic Write Bus Cycle

During a write cycle, the device sends data to memory or to a peripheral device. Figure 17-9

shows the write cycle flowchart.

System ColdFire device

1. Set FB_R/W to write.

2. Place address on FB_D[23:0].

3. Assert FB_TS.

1. Decode address.

1. Negate FB_TS.

Assert FB_CSn.

Drive data.

FlexBus asserts internal FB_TA

(auto acknowledge/internal termination).

Sample FB_TA low.

1. Select the appropriate slave device.

2. Latch data on FB_D[31:X].

Assert FB_TA (external termination).

1. Start next cycle.

1. Negate FB_TA (external termination).

Figure 17-9. Write-Cycle Flowchart

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MCF5208 Reference Manual, Rev 2

17-15

FlexBus

Figure 17-10

shows the write cycle timing diagram.

NOTE

The address and data busses are muxed between the FlexBus and SDRAM controller. At the end of the write bus cycles, the address signals are indeterminate.

S0 S1 S2 S3 S0

FB_CLK

FB_A[23:0]

ADDR[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_BE/BWEn

ADDR[31:X]

DATA

FB_OE

FB_TA

Figure 17-10. Basic Write-Bus Cycle

17.4.5.3

Bus Cycle Sizing

This section shows timing diagrams for various port size scenarios. Figure 17-11

illustrates the basic byte read transfer to an 8-bit device with no wait states. The address is driven on the FB_A[ 23:8 ] bus throughout the bus cycle. The external device returns the read data on FB_D[31:24] and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted.

S0 S1 S2 S3 S0

FB_CLK

FB_A[23:0]

FB_D[31:24]

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

ADDR[31:24]

ADDR[23:0]

DATA[7:0]

Figure 17-11. Single Byte-Read Transfer

MCF5208 Reference Manual, Rev 2

17-16 Freescale Semiconductor

FlexBus

Figure 17-12

shows the similar configuration for a write transfer. The data is driven from the second clock on FB_D[31:24].

S0 S1 S2 S3 S0

FB_CLK

FB_A[23:0]

FB_D[31:24]

ADDR[31:24]

ADDR[23:0]

DATA[7:0]

FB_R/W

FB_TS

FB_CSn, FB_BE/BWEn

FB_OE

FB_TA

Figure 17-12. Single Byte-Write Transfer

Figure 17-13

illustrates the basic word read transfer to a 16-bit device with no wait states. The address is driven on the FB_A[ 23:8 :0] bus throughout the bus cycle. The external device returns the read data on

FB_D[31:16], and may tristate the data line or continue driving the data one clock after FB_TA is sampled asserted.

S0 S1

FB_CLK

FB_A[23:0]

FB_D[31:16]

FB_R/W

FB_TS

FB_CSn, FB_OE

FB_BE/BWEn

FB_TA

ADDR[31:16]

ADDR[23:0]

DATA[15:0]

S2 S3 S0

Figure 17-13. Single Word-Read Transfer

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 17-17

FlexBus

Figure 17-14

shows the similar configuration for a write transfer. The data is driven from the second clock on FB_D[31:16].

FB_CLK

FB_A[15:0]

FB_D[31:16]

FB_R/W

FB_TS

FB_CSn, FB_BE/BWEn

FB_OE

FB_TA

ADDR[31:16]

ADDR[15:0]

DATA[15:0]

S3 S0

Figure 17-14. Single Word-Write Transfer

Figure 17-15

depicts a longword read from a 32-bit device.

S0 S1

FB_CLK

FB_A[23:0]

FB_D[31:0]

FB_R/W

FB_TS

FB_CSn, FB_OE

FB_BE/BWEn

FB_TA

ADDR[31:0]

ADDR[23:0]

DATA[31:0]

S2 S3 S0

Figure 17-15. Longword-Read Transfer

MCF5208 Reference Manual, Rev 2

17-18 Freescale Semiconductor

FlexBus

Figure 17-16

illustrates the longword write to a 32-bit device.

S0 S1

FB_CLK

FB_A[23:0]

FB_D[31:0]

FB_R/W

FB_TS

FB_CSn, FB_BE/BWEn

FB_OE

FB_TA

ADDR[31:0]

ADDR[23:0]

DATA[31:0]

S3 S0

Figure 17-16. Longword-Write Transfer

17.4.5.4

Timing Variations

The FlexBus module has several features that can change the timing characteristics of a basic read- or write-bus cycle to provide additional address setup, address hold, and time for a device to provide or latch data.

17.4.5.4.1

Wait States

Wait states can be inserted before each beat of a transfer by programming the CSCRn registers. Wait states can give the peripheral or memory more time to return read data or sample write data.

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MCF5208 Reference Manual, Rev 2

17-19

FlexBus

Figure 17-17 and Figure 17-18 show the basic read and write bus cycles (also shown in

Figure 17-8

and

Figure 17-13

) with the default of no wait states.

S0 S1 S2 S3 S0

FB_CLK

FB_A[23:0]

ADDR[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

ADDR[31:X]

DATA

Figure 17-17. Basic Read-Bus Cycle (No Wait States)

S0 S1 S2 S3 S0

FB_CLK

FB_A[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_BE/BWEn

FB_OE

FB_TA

ADDR[31:X]

ADDR[23:0]

DATA

Figure 17-18. Basic Write-Bus Cycle (No Wait States)

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Freescale Semiconductor

FlexBus

If wait states are used, the S1 state repeats continuously until the the chip-select auto-acknowledge unit asserts internal transfer acknowledge or the external FB_TA is recognized as asserted.

Figure 17-19

and

Figure 17-20

show a read and write cycle with one wait state.

S0 S1 WS S2 S3 S0

FB_CLK

FB_A[23:0]

ADDR[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

ADDR[31:X]

DATA

FB_CLK

FB_A[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_BE/BWEn

FB_OE

FB_TA

Figure 17-19. Read-Bus Cycle (One Wait State)

S0 S1 WS S2

ADDR[31:X]

ADDR[23:0]

DATA

S3 S0

Figure 17-20. Write-Bus Cycle (One Wait State)

17.4.5.4.2

Address Setup and Hold

The timing of the assertion and negation of the chip selects, byte selects, and output enable can be programmed on a chip-select basis. Each chip-select can be programmed to assert one to four clocks after

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

17-21

FlexBus

transfer start (FB_TS) is asserted.

Figure 17-21 and Figure 17-22 show read- and write-bus cycles with

two clocks of address setup.

S0 AS S1 S2 S3 S0

FB_CLK

FB_A[23:0]

ADDR[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

ADDR[31:X]

DATA

Figure 17-21. Read-Bus Cycle with Two-Clock Address Setup (No Wait States)

S0 AS S1 S2 S3 S0

FB_CLK

FB_A[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_BE/BWEn

FB_OE

FB_TA

ADDR[31:X]

ADDR[23:0]

DATA

Figure 17-22. Write-Bus Cycle with Two Clock Address Setup (No Wait States)

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Freescale Semiconductor

FlexBus

In addition to address setup, a programmable address hold option for each chip select exists. Address and attributes can be held one to four clocks after chip-select, byte-selects, and output-enable negate.

Figure 17-23 and Figure 17-24 show read and write bus cycles with two clocks of address hold.

S0 S1 S2 AH S3 S0

FB_CLK

FB_A[23:0]

ADDR[23:0]

FB_D[31:X]

ADDR[31:X]

DATA

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

Figure 17-23. Read Cycle with Two-Clock Address Hold (No Wait States)

S0 S1 S2 AH S3 S0

FB_CLK

FB_A[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_BE/BWEn

FB_OE

FB_TA

ADDR[31:X]

ADDR[23:0]

DATA

Figure 17-24. Write Cycle with Two-Clock Address Hold (No Wait States)

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MCF5208 Reference Manual, Rev 2

17-23

FlexBus

Figure 17-25

shows a bus cycle using address setup, wait states, and address hold.

S0 AS S1 WS S2 AH

FB_CLK

FB_A[23:0]

ADDR[23:0]

FB_D[31:X]

FB_R/W

FB_TS

FB_CSn, FB_BE/BWEn

FB_OE

FB_TA

ADDR[31:X]

DATA

Figure 17-25. Write Cycle with Two-Clock Address Setup and

Two-Clock Hold (One Wait State)

17.4.6 Burst Cycles

The device can be programmed to initiate burst cycles if its transfer size exceeds the port size of the selected destination. With bursting disabled, any transfer larger than the port size breaks into multiple individual transfers. With bursting enabled, an access larger than port size results in a burst cycle of

multiple beats. Table 17-8 shows the result of such transfer translations.

Table 17-8. Transfer Size and Port Size Translation

Port Size PS[1:0]

01 (8-bit)

1x (16-bit)

00 (32-bit)

Transfer Size

word longword line longword line line

Burst-Inhibited: Number of Transfers

Burst Enabled: Number of Beats

The FlexBus can support 2-1-1-1 burst cycles to maximize system performance. Delaying termination of the cycle can add wait states. If internal termination is used, different wait state counters can be used for the first access and the following beats.

The CSCRn registers enable bursting for reads, writes, or both. Memory spaces can be declared burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW] bits.

MCF5208 Reference Manual, Rev 2

17-24 Freescale Semiconductor

FlexBus

Figure 17-26

shows a longword read to an 8-bit device programmed for burst enable. The transfer results in a 4-beat burst and the data is driven on

FB_D[31:24].

NOTE

Address lines increment only during internally-terminated burst cycles. The first address is driven throughout the entire burst for externally-terminated cycles.

S3 S0 S0 S1 S2 S2 S2 S2

FB_CLK

FB_A[23:0]

FB_D[31:24]

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

ADDR[23:0]

ADDR[31:24]

ADDR + 1 ADDR + 2

DATA DATA DATA

ADDR + 3

DATA

Figure 17-26. Longword-Read Burst from 8-Bit Port 2-1-1-1 (No Wait States)

Figure 17-27

shows a longword write to an 8-bit device with burst enabled. The transfer results in a 4-beat burst and the data is driven on FB_D[31:24].

NOTE

The first beat of any write burst cycle has at least one wait state. If the bus cycle is programmed for zero wait states (CSCRn[WS] = 0), one wait state is added. Otherwise, the programmed number of wait states are used.

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MCF5208 Reference Manual, Rev 2

17-25

FlexBus

S0 S1 WS

FB_CLK

FB_A[23:0]

FB_D[31:24]

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

ADDR

[31:24]

ADDR[23:0]

DATA

S2 S2 S2 S2

ADDR + 1 ADDR + 2

DATA DATA

ADDR + 3

DATA

S3 S0

Figure 17-27. Longword-Write Burst to 8-Bit Port 3-1-1-1 (No Wait States)

Figure 17-28

shows a longword read from an 8-bit device with burst inhibited. The transfer results in four individual transfers.

NOTE

There is an extra clock of address setup (AS) for each burst-inhibited transfer between states S0 and S1.

FB_CLK

FB_A[23:0]

FB_D[31:24]

FB_R/W

FB_TS

FB_CSn, FB_OE

FB_BE/BWEn

FB_TA

S0 AS S1 S2 S0 AS S1 S2 S0 AS S1 S2 S0 AS S1 S2

ADDR[23:0]

ADDR

[31:24]

DATA

ADDR + 1

DATA

ADDR + 2

DATA

ADDR + 3

Figure 17-28. Longword-Read Burst-Inhibited from 8-Bit Port (No Wait States)

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Freescale Semiconductor

FlexBus

Figure 17-29

shows a longword write to an 8-bit device with burst inhibited. The transfer results in four individual transfers.

FB_CLK

FB_A[23:0]

FB_D[31:24]

FB_R/W

FB_TS

FB_CSn

FB_BE/BWEn

FB_OE

FB_TA

S0 AS S1 S2 S0 AS S1 S2 S0 AS S1 S2 S0 AS S1 S2

ADDR[23:0]

ADDR

[31:24]

DATA

ADDR + 1

DATA

ADDR + 2

DATA

ADDR + 3

Figure 17-29. Longword-Write Burst-Inhibited to 8-Bit Port (No Wait States)

Figure 17-30

illustrates another read burst transfer, but in this case a wait state is added between individual beats.

NOTE

CSCRn[WS] determines the number of wait states in the first beat.

However, for subsequent beats, the CSCRn[WS] (or CSCRn[SWS] if

CSCRn[SWSEN] is set) determines the number of wait states.

S0 S1 WS S2 WS/SWS S2 WS/SWS S2 WS/SWS S2 S3 S0

FB_CLK

FB_A[23:0]

FB_D[31:24]

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

ADDR[31:24]

ADDR[23:0]

DATA DATA

ADDR + 1

DATA

ADDR + 2 ADDR + 3

DATA

Figure 17-30. Longword-Read Burst from 8-Bit Port 3-2-2-2 (One Wait State)

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 17-27

FlexBus

Figure 17-30

illustrates a write burst transfer with one wait state.

FB_CLK

FB_A[23:0]

FB_D[31:24]

FB_R/W

FB_TS

FB_CSn, FB_OE,

FB_BE/BWEn

FB_TA

ADDR

[31:24]

S1 WS

ADDR[23:0]

DATA

S2 WS/SWS S2 WS/SWS S2 WS/SWS S2

ADDR + 1

DATA

ADDR + 2

DATA

ADDR + 3

DATA

S3 S0

Figure 17-31. Longword-Write Burst to 8-Bit Port 3-2-2-2 (One Wait State)

If address setup and hold are used, only the first and last beat of the burst cycle are affected. Figure 17-32

shows a read cycle with one clock of address setup and address hold.

NOTE

When using internal termination in this scenario (CSCRn[AA] = 1), the address increments after the clock-edge boundary. The attached device must be able to account for this, or a wait state must be added.

S0 AS S1 S2 S2 S2 S2 AH

S3 S0

FB_CLK

FB_A[23:0]

FB_D[31:24]

FB_R/W

FB_TS

FB_CSn, FB_OE

FB_BE/BWEn

FB_TA

ADDR[23:0]

ADDR[31:24]

DATA DATA

ADDR + 1 ADDR + 2

DATA DATA

ADDR + 3

The address hold time depends on the setting of CSCRn[AA]. See

Section 17.3.3, “Chip-Select

Control Registers (CSCR0 – CSCR5)”,

for more details.

Figure 17-32. Longword-Read Burst from 8-Bit Port 3-1-1-1 (Address Setup and Hold)

MCF5208 Reference Manual, Rev 2

17-28 Freescale Semiconductor

Figure 17-33

shows a write cycle with one clock of address setup and address hold.

S0 AS S1 S2 S2 S2 S2 AH

FB_CLK

FB_A[23:0]

FB_D[31:24]

FB_R/W

FB_TS

FB_CSn, FB_OE

FB_BE/BWEn

FB_TA

ADDR[23:0]

ADDR[31:24]

DATA

ADDR + 1 ADDR + 2

DATA DATA

ADDR + 3

DATA

S3 S0

FlexBus

Figure 17-33. Longword-Write Burst to 8-Bit Port 3-1-1-1 (Address Setup and Hold)

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

17-29

FlexBus

17.4.7 Misaligned Operands

Because operands, unlike opcodes, can reside at any byte boundary, they are allowed to be misaligned.

• Byte operand is properly aligned at any address

• Word operand is misaligned at an odd address

• Longword is misaligned at any address not a multiple of four

Although the processor enforces no alignment restrictions for data operands (including program counter

(PC) relative data addressing), misaligned operands require additional bus cycles.

Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch a misaligned instruction word causes an address-error exception.

The processor core converts misaligned, cache-inhibited operand accesses to multiple aligned accesses.

Example 17-1

shows the transfer of a longword operand from a byte address to a 32-bit port. First, a byte transfers at an offset of 0x1. The slave device supplies the byte and acknowledges the data transfer. When the processor starts the second cycle, a word transfers with a byte offset of 0x2. The next two bytes are transferred in this cycle. In the third cycle, byte 3 transfers. The byte offset is now 0x0, the port supplies the final byte, and the operation completes.

Transfer 1

Transfer 2

Transfer 3

––

Byte 3

24 23

Byte 0

––

16 15

––

Byte 1

––

8 7

––

Byte 2

––

0 FB_A[2:0]

001

010

100

Example 17-1. A Misaligned Longword Transfer (32-Bit Port)

If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the

cache. The example in Example 17-2 differs from the one in Example 17-1 because the operand is

word-sized and the transfer takes only two bus cycles.

31 24 23 16 15

Transfer 1

Transfer 2

––

Byte 0

––

8 7

Byte 0

—

0 FB_A[2:0]

001

100

Example 17-2. A Misaligned Word Transfer (32-Bit Port)

17.4.8 Bus Errors

The ColdFire device has no bus monitor. If the auto-acknowledge feature is not enabled for the address that generates the error, the bus cycle can be terminated by asserting FB_TA or by using the software watchdog timer. If the processor must manage a bus error differently, asserting an interrupt to the core along with FB_TA when the bus error occurs can invoke an interrupt handler.

MCF5208 Reference Manual, Rev 2

17-30 Freescale Semiconductor

Chapter 18 SDRAM Controller (SDRAMC)

18.1 Introduction

This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It begins with a general description and brief glossary and includes a description of signals involved in

DRAM operations. The remainder of the chapter describes the programming model and signal timing, as well as the command set required for synchronous operations. It also includes examples to better understand how to configure the DRAM controller for synchronous operations.

NOTE

Unless otherwise noted, in this chapter clock refers to the system clock

(f sys/2

The external data bus is shared between the FlexBus module and the

SDRAM controller. When the SDRAM controller is in SDR mode

(DRAMSEL = 1), the data bus is switched dynamically between the

SDRAM controller and the FlexBus module. However, when the SDRAM controller is in DDR mode (DRAMSEL = 0), D[31:16] is dedicated to the

SDRAM data bus and D[15:0] is dedicated to the FlexBus data bus.

In this chapter, the SDRAM data bus signals are named SD_D[31:0].

However, because these signals share external pins with the FlexBus, the pin names on the device are D[31:0].

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

18-1

SDRAM Controller (SDRAMC)

18.1.1 Block Diagram

Block diagram of the SDRAM controller:

ADDR

Address

Input

MUX

Column

Bank

Row

Address

Pipeline

Latches

Column

Bank

Row

IPS Interface Register

File

Address

Controls

Data in [63:0]

Data out [63:0]

Address

Output

MUX

SD_A[13:0]

SD_BA[1:0]

Command

Type

SDRAM

Controller

State

Machine

Write Data

Buffer

Read Data

Buffer

SD_CLK/CLK

SD_CKE

SD_CS[1:0]

SD_RAS

SD_CAS

SD_WE

SD_SDRDQS

SD_DQS[3:2]

SD_DQM[3:0]

SD_D[31:0]

Figure 18-1. SDRAM Controller Block Diagram

18.1.2 Features

The SDRAM controller contains:

• Supports standard SDRAM (single data rate, or SDR) and dual data rate (DDR) SDRAM; one or the other, not mixed.

• Support for lower-power/mobile DDR SDRAM.

• Dynamic 16- or 32-bit fixed memory data port width.

• 16 bytes critical word first burst transfer. Supports sequential address order only.

• Up to 14 lines of row address, up to 12 (in 32-bit bus mode) or 13 (in 16-bit bus mode) column address lines, 2 bits of bank address, and two pinned-out chip selects. The maximum row bits plus column bits equals 24 in 32-bit bus mode or 25 in 16-bit bus mode.

• Minimum memory configuration of 8 MByte

— 11 bit row address (RA), 8 bit column address (CA), 2 bit bank address (BA), 32-bit bus, one chip select

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18-2 Freescale Semiconductor

SDRAM Controller (SDRAMC)

— 11 bit row address (RA), 9 bit column address (CA), 2 bit bank address (BA), 16-bit bus, one chip select

• Supports up to 512 MByte of memory.

— 24/25 bits RA+CA, 2 bits BA, 32/16-bit bus, two chip selects

• Supports page mode for decreased latency and higher bandwidth; remembers one active row for each bank; four independent active rows per each chip select.

• Programmable refresh interval timer.

• Supports sleep mode and self-refresh mode.

• Error detect and parity check are not supported.

• The SDRAM controller does not include a dedicated I

C interface to access memory module

(DIMM) serial presence detect EEPROM. If needed, this must be managed by one of the on-chip

C channels external to the SDRAM controller.

• Read clock recovery block

18.1.3 Terminology

The following terminology is used in this chapter:

• SDRAM block: Any group of DRAM memories selected by one of the SD_CS signals. Therefore, the SDRAMC can support up to two independent memory blocks. The base address of each block is programmed in the SDRAM chip-select configuration registers.

• SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit SDRAM component might be configured as four 512K x 32 banks. Banks are selected through the

SD_BA[1:0] signals.

• SDRAM: RAMs that operate like asynchronous DRAMs but with a synchronous clock, a pipelined, multiple-bank architecture, and a faster speed.

18.2 External Signal Description

This section introduces the signal names used in this chapter.

Table 18-1. SDRAM Interface—Detailed Signal Descriptions

Signal

SD_A[13:0]

I/O Description

O Memory multiplexed row/column address. Provides the row address for

ACTV

commands, and the column address and auto-precharge bit for

READ

WRITE

commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 negated) or all banks (A10 asserted). If only one bank is to be precharged, the bank is selected by SD_BA[1:0].

The address outputs also provide the opcode during a MODE REGISTER SET command. SD_BA[1:0] signals define which mode register is loaded during the MODE REGISTER SET (MRS). A12 is used on device densities of 256 Mb and above.

Timing

Assertion/Negation — Occurs synchronously with SD_CLK

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 18-3

SDRAM Controller (SDRAMC)

Table 18-1. SDRAM Interface—Detailed Signal Descriptions (continued)

Signal I/O Description

SD_BA[1:0]

SD_CAS

SD_RAS

SD_CKE

O Memory bank address. Define which bank an

ACTV

READ

WRITE

, or PRECHARGE command is being applied. It is also used to select the SDRAM internal mode register during power-up initialization.

Timing

Assertion/Negation — Occurs synchronously with SD_CLK

O Column address strobe/command input. Along with SD_CS, SD_RAS, and SD_WE, defines the current command.

State

Meaning

See Table 18-12

for the SDRAM commands.

Timing

Assertion/Negation — Occurs synchronously with SD_CLK

O Row address strobe/command input. Along with SD_CS, SD_CAS, and SD_WE, defines the current command.

State

Meaning

See Table 18-12

for SDRAM commands.

Timing

Assertion/Negation — Occurs synchronously with SD_CLK.

O Clock enable. SD_CKE must be maintained high throughout

READ

and

WRITE

accesses. SD_CKE negates to put the SDRAM into low-power, self-refresh mode. Input buffers, excluding SD_CLK, SD_CLK, and

SD_CKE, are disabled during self-refresh.

State

Meaning

Asserted — Activates internal clock signals and device input buffers and output drivers.

Negated —Deactivates internal clock signals and device input buffers and output drivers.

SD_CLK

SD_CS[1:0]

Timing

Assertion — Asynchronous for self-refresh exit and for output disable

Negation — Occurs synchronously with SD_CLK

O SD_CLK and SD_CLK are differential clock outputs. All address and control output signals are sent on the crossing of the positive edge of SD_CLK and the negative edge of SD_CLK. Output data is referenced to the crossing of SD_CLK and SD_CLK (both directions of crossing).

Timing

Command signals occur synchronously with the rising edge of this clock. Data signals can change on the rising and falling edge of the clock.

O SD_CS provides external bank selection on systems with multiple banks. SD_CS is considered part of the command code.

State

Meaning

Asserted — Commands for the selected chip occur

Negated — All commands are masked.

Timing Assertion/Negation — Occurs synchronously with SD_CLK

SD_DATA[31:0] I/O Data bus. In 16-bit DDR configuration, the memory device data bus is connected to SD_D[31:16] bits.

Timing

Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK.

High Impedance - Depending on the OE_RULE bit in SDCFG1, the SD_DATA bus can be in high impedance until a write occurs or only when a read occurs.

18-4

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Freescale Semiconductor

SDRAM Controller (SDRAMC)

Table 18-1. SDRAM Interface—Detailed Signal Descriptions (continued)

Signal I/O Description

SD_DQM[3:0] O Output mask signal for write data. During reads, SD_DQM may be driven high, low, or floating. The address correspondence:

SD_DQM3 - SD_D[31:24]

SD_DQM2 - SD_D[23:16]

SD_DQM1 - SD_D[15:8]

SD_DQM0 - SD_D[7:0]

State

Meaning

Asserted — Data is written to SDRAM

Negation — Data is masked

Timing

Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK.

SD_DQS[3:2] I/O Data strobes that indicate valid read/write data. (Edge-aligned with read data, centered with write data.)

The DQS frequency equals the memory clock frequency. Data is normally 1/4 memory clock period after a

DQS transition. For DDR operation, there is data following each DQS edge (rising and falling); for SDR operation, valid data follows the rising edges only. The address correspondence:

SD_DQS3 - SD_D[31:24]

SD_DQS2 - SD_D[23:16]

Note: If a read is attempted from a DDR SDRAM chip select when there is no memory to respond with the appropriate SD_DQS pulses, the bus cycle hangs. Because there is no high level bus monitor on the device, a reset is the only way to exit this error condition.

State

Meaning

Asserted — Similar to a clock signal, the edges are more important than being asserted or negated.

High impedance — Depending on the SDCFG1[OE_RULE] bit, the SD_DQS can be in high impedance until a write is occurring or only when a read is occurring.

Timing

Assertion/Negation — Occurs on crossing of SD_CLK and SD_CLK.

SD_SDRDQS O SDR data strobe. Generated by the memory controller in SDR mode, to mimic the DQS generated by DDR memories during reads. It should be routed out and connected back to the SD_DQS inputs.

SD_WE

State

Meaning

Asserted— Similar to a clock signal, the edges are more important than being asserted or negated.

Timing

Assertion/Negation—Occurs on crossing of SD_CLK and SD_CLK.

O Command input. Along with SD_CS, SD_CAS, and SD_RAS defines the current command.

State

Meaning

Please see

Table 18-12 for SDRAM commands.

Timing

Assertion/Negation— Occurs synchronously with SD_CLK.

18.3 Interface Recommendations

18.3.1 Supported Memory Configurations

The SDRAM controller supports up to 14 row addresses and up to (13 in 16-bit bus mode) column addresses. However, the maximum row and column addresses are not simultaneously supported. The number of row and column addresses must be less than or equal to 24 (25 in 16-bit bus mode). In addition to row/column address lines, there are always two row bank address bits. Therefore, the greatest possible address space accessed using a single chip select is 2

x 32 bit (2

x 16 bit) or 256 MBytes.

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 18-5

SDRAM Controller (SDRAMC)

Table 18-5

and Table 18-6

show the address multiplexing used by the memory controller for different configurations. When the SDRAM controller receives the internal module enable, it latches the internal bus address lines IA[27:0] (IA equals internal address) and multiplexes them into row, column, and bank addresses (RA, CA, and BA respectfully). In 32-bit bus mode, IA[9:2] are used for CA[7:0]. In 16-bit mode, IA[9:1] are used for CA[8:0]. IA[11:10] are always used for BA[1:0], and IA[23:12] are always used for RA[11:0]. IA[27:24] can be used for additional row or column address bits, as needed. The additional row- or column-address bits are programmed via the SDCR[ADDR_MUX] bits.

NOTE

When the SDRAMC is configured to support an external 32-bit data bus. It is not possible to connect a smaller device(s) to only part of the SDRAM’s data bus. For example, if 16-bit wide devices are used, then user must use two 16-bit devices connected as a 32-bit port.

Table 18-2. Address Multiplexing for 32-bit Bus Mode

Internal Address Bits [27:24]

SDCR[ADDR_MUX]

IA[27]

CA12

CA11

CA9

IA[26] IA[25]

CA11

CA9

CA8

CA8 RA13

Reserved, do not use.

IA[24]

CA8

RA12

Table 18-3. SDRAM Address Multiplexing in 32-bit Bus Mode

Device Configuration

Row bit x

Col bit x

Banks

SDCR

[ADDR_

MUX]

64 Mbits

2M x 32 bit 11 x 8 x 4

4M x 16 bit 12 x 8 x 4

8M x 8 bit

16M x 4 bit

12 x 9 x 4

13 x 8 x 4

12 x 10 x 4

13 x 9 x 4

—

1,2

—

Internal Address

25 24 23–12 11–10 9–2

—

CA8

RA12

CA9 CA8

CA8 RA12

RA11-0 BA1-0 CA7-0

18-6

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

SDRAM Controller (SDRAMC)

Table 18-3. SDRAM Address Multiplexing in 32-bit Bus Mode (continued)

128 Mbits

256 Mbits

4M x 32 bit 12 x 8 x 4

12 x 9 x 4

8M x 16 bit

13 x 8 x 4

16M x 8 bit

12 x 10 x 4

13 x 9 x 4

32M x 4 bit

14 x 8 x 4

12 x 11 x 4

13 x 10 x 4

14 x 9 x 4

8M x 32 bit

16M x 16 bit

32M x 8 bit

12 x 9 x 4

13 x 8 x 4

12 x 10 x 4

13 x 9 x 4

14 x 8 x 4

12 x 11 x 4

13 x 10 x 4

14 x 9 x 4

64M x 4 bit

12 x 12 x 4

13 x 11 x 4

14 x 10 x 4

12 x 10 x 4

16M x 32 bit

512 Mbits 32 M x 16 bit

13 x 9 x 4

14 x 8 x 4

12 x 11 x 4

13 x 10 x 4

64M x 8 bit

14 x 9 x 4

12 x 12 x 4

13 x 11 x 4

14 x 10 x 4

Device Configuration

Row bit x

Col bit x

Banks

SDCR

[ADDR_

MUX]

Internal Address

27 26 25 24 23–12 11–10 9–2

—

CA9

—

CA8

RA12

CA8

—

CA8

CA11 CA9

RA12

RA13 RA12

CA8

RA11-0 BA1-0 CA7-0

CA9

CA8

—

CA11

CA9

CA8

CA8 RA12

RA13

—

CA9

CA8

CA9

RA13

CA12 CA11 CA9

RA12

CA8

RA12

CA8

RA12

RA13 RA12

CA8

CA8 RA12

RA12

CA8

RA11-0 BA1-0 CA7-0

CA11 CA9

CA9 CA8

CA8

RA13

RA12

—

CA9 CA8

CA8 RA12

— RA13 RA12

CA11 CA9 CA8

—

CA9 CA8 RA12

CA8 RA13 RA12

RA11-0 BA1-0 CA7-0

CA12 CA11 CA9

CA11 CA9 CA8

CA8

RA12

CA9 CA8 RA13 RA12

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 18-7

SDRAM Controller (SDRAMC)

Table 18-3. SDRAM Address Multiplexing in 32-bit Bus Mode (continued)

Device Configuration

Row bit x

Col bit x

Banks

SDCR

[ADDR_

MUX] 27 26

Internal Address

25 24 23–12 11–10 9–2

1 Gbits

32M x 32 bit

12 x 11 x 4

13 x 10 x 4

14 x 9 x 4

12 x 12 x 4

—

CA11 CA9

CA9 CA8

CA8

RA12

— CA8 RA13 RA12

CA12 CA11 CA9 CA8

RA11-0 BA1-0 CA7-0

64M x 16 bit 13 x 11 x 4

14 x 10 x 4

CA11 CA9

CA9 CA8

CA8

RA13

RA12

2 Gbits 64M x 32 bit

12 x 12 x 4

13 x 11 x 4

CA12

CA11

CA9

CA8

RA12 RA11-0 BA1-0 CA7-0

14 x 10 x 4 10 CA9 CA8 RA13 RA12

All SD_A[13:0] bits are generated on every access, but only the bits actually used by the memory are shown.

All column address (CA) bits in this table are physical column address lines. The SDRAM controller inserts an extra bit CA10 to control the precharge option.

Table 18-4. Address Multiplexing for 16-bit Bus Mode

Internal Address Bits [27:24]

SDCR[ADDR_MUX]

IA[27]

CA13

CA12

CA11

IA[26] IA[25]

CA12

CA11

CA9

CA9 RA13

Reserved. Do Not Use.

IA[24]

CA9

RA12

Table 18-5. SDRAM-Address Multiplexing in 16-bit Bus Mode

Device Configuration

Row bit x

Col bit x

Banks

SDCR

[ADDR_

MUX]

64 Mbits

4M x 16 bit 11 x 9 x 4

8M x 8 bit

16M x 4 bit

12 x 9 x 4

12 x 10 x 4

13 x 9 x 4

—

1,2

—

Internal Address

—

CA9

RA12

23 – 12 11 – 10 9 – 1

RA11-0 BA1-0 CA8-0

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Freescale Semiconductor

SDRAM Controller (SDRAMC)

Table 18-5. SDRAM-Address Multiplexing in 16-bit Bus Mode (continued)

Device Configuration

Row bit x

Col bit x

Banks

SDCR

[ADDR_

MUX] 27 26

Internal Address

25 24 23 – 12 11 – 10 9 – 1

128 Mbits

256 Mbits

8M x 16 bit

16M x 8 bit

32M x 4 bit

16M x 16 bit

12 x 9 x 4

12 x 10 x 4

13 x 9 x 4

12 x 11 x 4

13 x 10 x 4

14 x 9 x 4

12 x 10 x 4

13 x 9 x 4

32M x 8 bit

12 x 11 x 4

13 x 10 x 4

14 x 9 x 4

12 x 12 x 4

64M x 4 bit 13 x 11 x 4

14 x 10 x 4

32 M x 16 bit

12 x 11 x 4

13 x 10 x 4

—

CA9

— RA12

CA11 CA9

RA11-0 BA1-0 CA8-0

CA9 RA12

RA13 RA12

—

CA9

RA12

—

CA11 CA9

CA9 RA12

— RA13 RA12

CA12 CA11 CA9

RA11-0 BA1-0 CA8-0

CA11 CA9 RA12

CA9 RA13 RA12

—

CA11

CA9

RA12

512 Mbits

1 Gbits

64M x 8bit

64M x 16bit

14 x 9 x 4

12 x 12 x 4

13 x 11 x 4

14 x 10 x 4

12 x 12 x 4

13 x 11 x 4

14 x 10 x 4

12 x 13 x 4

—

CA12

RA13

CA11

RA12

CA9

RA11-0 BA1-0 CA8-0

—

CA11 CA9 RA12

CA9 RA13 RA12

CA12

CA11

CA9

RA12

— CA9 RA13 RA12

CA13 CA12 CA11 CA9

RA11-0 BA1-0 CA8-0

2 Gbits 128M x16bit 13 x 12 x 4 01 CA12 CA11 CA9 RA12 RA11-0 BA1-0 CA8-0

14 x 11 x 4 10 CA11 CA9 RA13 RA12

All SD_A[13:0] bits are generated on every access, but only the bits actually used by the memory are shown.

All column address (CA) bits in this table are physical column address lines. The SDRAM controller inserts an extra bit CA10 to control the precharge option.

All memory devices of a single chip-select block must have the same configuration and row/column address width; however, this is not necessary between different blocks. If mixing different memory organizations in different blocks, the following guidelines ensure that every block is fully contiguous.

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 18-9

SDRAM Controller (SDRAMC)

For 32-bit data bus configuration:

• If all devices’ row address width is 12 bits, the column address can be

≥ 8 bits.

• If all devices’ row address width is 13 bits, the column address can be

≥ 8 bits.

• If all devices’ column address width is 8 bits, the row address can be

≥ 11 bits.

• The maximum row bits plus column bits equals 24.

• x8 and x16 data width memory devices can be mixed (but not in the same space).

• x32 data width memory devices cannot be mixed with any other width.

For 16-bit data bus configuration:

• If all devices’ row address width is 12 bits, the column address can be

≥ 9 bits.

• If all devices’ row address width is 13 bits, the column address can be

≥ 9 bits.

• If all devices’ column address width is 9 bits, the row address can be

≥ 11 bits.

• The maximum row bits plus column bits equals 25.

• x16 data width memory devices cannot be mixed with any other width.

18.3.2 SDRAM SDR Connections

Figure 18-2

shows a block diagram using 32-bit wide SDR SDRAM (such as Micron MT48LC4M32B2) and flash (such as Spansion AM29LV160D). SDR design requires special timing consideration for the lines and DQS signals have concurrent edges. The SDRAMC is designed to latch data 1/4 clock after the window.

SDRAM; however, SDR memories do not provide DQS outputs. Instead the SDRAMC provides a be routed such that the valid data from the SDRAM reaches the controller at the same time or before the

When routing SD_SDRDQS the outbound trace length should be matched to the SD_CLK trace length.

This aligns SD_SDRDQS to the SD_CLK as if the memory had generated the DQS pulse. The inbound trace should be routed along the data path, which should synchronize the SD_DQS so that the data is latched in the middle of the data valid window.

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SDRAM Controller (SDRAMC)

SDRAM Controller

SD_CLK

SD_CKE

SD_CS0

SD_RAS

SD_CAS

SDWE

SD_A10

SD_SDR_DQS

SD_DQS[3:2]

SD_DQM[3:0]

SD_A[23:0]

SD_D[31:0]

Delay

3.3V SDR SDRAM

CLK

CKE

RAS

CAS

A10/AP

R/W

FB_CS0

DRAMSEL 3.3V

A[15:14]

DQM[3:0]

BA[1:0]

A[13:11,9:0]

D[31:0]

A[23:2]

3.3V Flash

A[21:0]

D[31:0]

Figure 18-2. Example 3.3V, 32-bit SDR SDRAM System

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

18-11

SDRAM Controller (SDRAMC)

18.3.3 SDRAM DDR Component Connections

Figure 18-3

shows a block diagram using 16-bit wide DDR SDRAM (such as Micron MT46V8M16) and flash (such as Spansion AM29DBB160G).

SDRAM Controller

SD_CLK

SD_CKE

SD_CS0

SD_RAS

SD_CAS

SDWE

SD_A10

2.5V DDR SDRAM

CLK

CKE

RAS

CAS

A10/AP

SD_DQS[3:2]

BE/BWE/DQM[3:2]

SD_A[23:0]

SD_D[31:16]

DQS[1:0]

A[15:14]

DQM[3:2]

BA[1:0]

A[13:11,9:0]

D[15:0]

1.25V

VREF

D[15:0]

R/W

FB_CS0

DRAMSEL GND

A[23:1]

2.5V Flash

A[22:0]

D[15:0]

Figure 18-3. Example 2.5V, 16-bit DDR SDRAM System

18.3.4 DDR SDRAM Layout Considerations

Due to the critical timing for DDR SDRAM, a number of considerations should be taken into account during PCB layout:

• Minimize overall trace lengths.

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18-12 Freescale Semiconductor

SDRAM Controller (SDRAMC)

• Each DQS, DM, and DQ group must have identical loading and similar routing to maintain timing integrity.

• The loading and routing of SD_DQS must match those of SD_D.

• Control and clock signals are routed point-to-point.

• Trace length for clock, address, and command signals should match.

• Route DDR signals on layers adjacent to the ground plane.

• Use a VREF plane under the SDRAM.

• VREF is decoupled from SDVDD and VSS.

• To avoid crosstalk, address and command signals must remain separate from data and data strobes.

• Use different resistor packs for command/address and data/data strobes.

• Series termination should be used to help match output driver impedance to trace impedance.

(Driver impedance is affected by drive strength.) Typically, a 50

Ω system with a 22 Ω series resistor is a good starting point, but this should be analyzed based on actual board design and loading.

• Series termination should be between the processor and memory, but closest to the processor.

• The SD_CLK and SD_CLK signals can be terminated with a single termination resistor between the two clock phases. A 100 – 120

Ω resistor produces effective termination for the differential

SD_CLK. Placement of the terminator should be physically close to the input receiver on the

SDRAM(s).

If using a SDRAM DIMM, such as a 144-pin DDR2 SO-DIMM, termination on the CLK lines is not recommended, as clock line termination is already populated on the DIMM module. Additional termination on the motherboard (main board) may cause undersired effects.

• 0.1

μF decoupling for every termination resistor pack.

NOTE

Only series termination is supported on this device, which is different than typical DDR designs.

18.3.4.1

Termination Example

Figure 18-4

shows the recommended termination circuitry for DDR SDRAM signals.

Processor

Address, Data and Control

Note: Place series resistors as close as possible to the processor

DDR SDRAM

Address, Data and Control

SD_CLK

CLK

Note: Place 100

resistor as close as possible to the

DDR’s clock receiver

100

CLK

Figure 18-4. DDR SDRAM Termination Circuit

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 18-13

SDRAM Controller (SDRAMC)

18.4 Memory Map/Register Definition

The SDRAM controller and its associated logic contain two sets of programming registers:

• SDRAM controller’s control and configuration registers

• Chip-select configuration control registers

NOTE

The slew rate for the SDRAM pins is controlled by a register in the GPIO

module. See Section 13.3.7, “SDRAM Mode Select Control Register

(MSCR_SDRAM) ,

” for more details.

Table 18-6

shows the SDRAM controller control and configuration registers. Unspecified memory spaces are reserved for future use. Access to reserved space is prohibited. It is recommended to write 0 to reserved space. Reads from a write-only bit return 0.

Table 18-6. SDRAMC Memory Map

Address Register

0xFC0A_8000 SDRAM Mode/Extended Mode Register (SDMR)

0xFC0A_8004 SDRAM Control Register (SDCR)

0xFC0A_8008 SDRAM Configuration Register 1 (SDCFG1)

0xFC0A_800C SDRAM Configuration Register 2 (SDCFG2)

0xFC0A_8110 SDRAM Chip Select 0 Configuration (SDCS0)

0xFC0A_8114 SDRAM Chip Select 1 Configuration (SDCS1)

Width

(bits)

Access Reset Value Section/Page

R/W

0x0000_0000

18.4.1 SDRAM Mode/Extended Mode Register (SDMR)

The SDMR (

Figure 18-5

) writes to the mode and extended mode registers physically residing within the

SDRAM chips. These registers must be programmed during SDRAM initialization. See

Section 18.6,

“Initialization/Application Information

” for more information on the initialization sequence.

Address: 0xFC0A_8000 (SDMR)

Access: SDCR[MODE_EN] = 0 User read-only

SDCR[MODE_EN] = 1 User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BK AD

CMD

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 18-5. SDRAM-Mode/Extended-Mode Register (SDMR)

18-14

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

SDRAM Controller (SDRAMC)

Field

31–30

29–18

CMD

15–0

Table 18-7. SDMR Field Descriptions

Description

Bank address. Driven onto SD_BA[1:0] along with a

LMR

LEMR

command. All SDRAM chip selects are asserted simultaneously. SDCR[CKE] must be set before attempting to generate an

LMR

LEMR

command. The SD_BA[1:0] value is used to select between

LMR

and

LEMR

commands.

00 Load mode register command (

LMR

)

01 Load extended mode register command (

LEMR

) for non-mobile DDR devices

10 Load extended mode register command (

LEMR

) for mobile DDR devices

11 Reserved

Address. Driven onto SD_A[11:0] along with an

LMR

LEMR

command. The AD value is stored as the mode (or extended mode) register data.

Reserved, must be cleared.

Command. This bit is write-only and always returns a 0 when read.

1 Generate an

LMR

LEMR

command

0 Do not generate any command

Reserved, must be cleared.

18.4.2 SDRAM Control Register (SDCR)

The SDCR (

Figure 18-6

) controls SDRAMC operating modes, including refresh count and address line muxing.

Address: 0xFC0A_8004 (SDCR)

R MODE

_EN

Reset 0

CKE

29 28

DDR_

MODE

REF_

0 0 0

25 24

ADDR_MUX

0 0

OE_

RULE

Access: User read/write

18 17 16

REF_CNT

0 0 0 0

R 0

Reset 0

14 13

MEM_

0 0

11 10

DQS_OE

0 0 0 0 0 0 0 0

Figure 18-6. SDRAM Control Register (SDCR)

Table 18-8. SDCR Field Descriptions

IREF IPALL

0 0

Field

MODE_EN

CKE

Description

SDRAM mode register programming enable.

0 SDMR locked, cannot be written.

1 SDMR enabled, can be written.

Note: MODE_EN must be cleared during normal operation,

Clock enable. CKE must be set to perform normal read and write operations. Clear CKE to put the memory in self-refresh or power-down mode.

0 SD_CKE is negated (low)

1 SD_CKE is asserted (high)

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Freescale Semiconductor 18-15

SDRAM Controller (SDRAMC)

Table 18-8. SDCR Field Descriptions (continued)

Field

15–14

MEM_PS

11–10

DQS_OE

Description

DDR_MODE

DDR mode select.

0 SDR mode

1 DDR mode

REF_EN

27–26

Refresh enable.

0 Automatic refresh disabled

1 Automatic refresh enabled

Reserved, must be cleared.

25–24

ADDR_MUX

Controls the use of internal address bits A[27:24] as row or column bits on the SD_A bus. See Table 18-4 , and

Table 18-5 .

OE_RULE

21–16

REF_CNT

Reserved, must be cleared.

Drive rule selection.

0 Tri-state except to write. SD_D and SD_DQS are only driven when necessary to perform a write command.

1 Drive except to read. SD_D and SD_DQS are only tristated when necessary to perform a read command.

When not being driven for a write cycle, SD_D hold the most recent value and SD_DQS are driven low. This mode is intended for minimal applications only, to prevent floating signals and allow unterminated board traces. However, terminated wiring is always recommended over unterminated.

The average periodic interval at which the controller generates refresh commands to memory; measured in increments of 64

SD_CLK period.

REF_CNT = (t

REFI

/ (t

64)) - 1, rounded down to the next integer value.

If the SDRAM data sheet does not define t

REFI

, it can be calculated by t

REFI

= t

REF

/ #rows.

Reserved, must be cleared.

Memory data port size.

0 32-bit data bus

1 16-bit data bus

Reserved, must be cleared.

DQS output enable. Each DQS_OE bit is a master enable for the corresponding SD_DQSn signal. DQS_OE[1]

(SDCR[11]) enables SD_DQS3 and DQS_OE[0] (SDCR[10]) enables SD_DQS2.

9–3

IREF

0 SD_DQSn can never drive. Use this value in SDR mode or in DDR mode with a single DQS memory. Some

32-bit DDR devices have only a single DQS pin. Enable one of the SD_DQSn signals and disable the other.

Then, short both pins external to the device.

1 SD_DQSn can drive as necessary, depending on commands and SDCR[OE_RULE] setting. DDR only.

Reserved, must be cleared.

Initiate refresh command. Used to force a software-initiated refresh command. This bit is write-only, reads return zero.

0 Do not generate a refresh command.

1 Generate a refresh command. All SD_CSn signals are asserted simultaneously. SDCR[CKE] must be set before attempting to generate a software refresh command.

Note: A software requested refresh is completely independent of the periodic refresh interval counter. Software refresh is only possible when MODE_EN is set.

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18-16 Freescale Semiconductor

Field

IPALL

SDRAM Controller (SDRAMC)

Table 18-8. SDCR Field Descriptions (continued)

Description

Initiate precharge all command. Used to force a software-initiated precharge all command. This bit is write-only, reads return zero.

0 Do not generate a precharge command.

1 Generate a precharge all command. All SD_CSn signals are asserted simultaneously. SDCR[CKE] must be set before generating a software precharge command.

Note: Software precharge is only possible when MODE_EN is set.

Note: Do not set IREF and IPALL at the same time.

Reserved, should be cleared.

18.4.3 SDRAM Configuration Register 1 (SDCFG1)

The 32-bit read/write SDRAM configuration register 1 (SDCFG1) stores necessary delay values between specific SDRAM commands. During initialization, software loads values to the register according to the selected SD_CLK frequency and SDRAM information obtained from the data sheet. This register resets only by a power-up reset signal.

The read and write latency fields govern the relative timing of commands and data and must be exact values. All other fields govern the relative timing from one command to another; they have minimum values, but any larger value is also legal (but with decreased performance).

The minimum values of certain fields can be different for SDR, DDR SDRAM, even if the data sheet timing is the same, because:

• In SDR mode, the memory controller counts the delay in SD_CLK

• In DDR mode, the memory controller counts the delay in 2 x SD_CLK (also referred to as

SD_CLK2)

• SD_CLK—memory controller clock—is the speed of the SDRAM interface and is equal to the internal bus clock.

• SD_CLK2—double frequency of SD_CLK—DDR uses both edges of the bus-frequency clock

(SD_CLK) to read/write data

NOTE

In all calculations for setting the fields of this register, convert time units to clock units and round up to the nearest integer.

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

18-17

SDRAM Controller (SDRAMC)

Address: 0xFC0A_8008 (SDCFG1)

30 29 28 31

Reset 0

SRD2RWP

0 0 0

26 25

SWT2RWP

0 0 0

22 21

RD_LAT

0 0

Access: User read/write

18 17 16

ACT2RW

0 0 0 0

R 0

Reset 0

14 13

PRE2ACT

0 0

11 10 9

REF2ACT

8 7

6 5

WT_LAT

0 0 0 0 0 0 0 0 0

Figure 18-7. SDRAM Configuration Register 1 (SDCFG1)

Table 18-9. SDCFG1 Field Descriptions

Field Description

31–28

SRD2RWP

Single read to read/write/precharge delay. Limiting case is read to write.

SDR: SRD2RWP = CL

+ t

DDR: SRD2RWP = CL + 1

+ 2

0 t

is the time the data bus uses to return to hi-impedance after a read and is found in the SDRAM device specifications.

Note: Count value is in SD_CLK periods for SDR and DDR mode.

Reserved, must be cleared.

26–24

SWT2RWP

Single write to read/write/precharge delay. Limiting case is write to precharge.

SDR: SWT2RWP = t

DDR: SWT2RWP = t

+ 1

23–20

RD_LAT

Note: Count value is in SD_CLK periods for SDR and DDR mode.

Read CAS Latency. Read command to read data available delay counter.

For DDR:

If CL = 2, write 0x6

If CL = 2.5, write 0x7

For SDR:

If CL = 2, write 0x2

If CL = 3, write 0x3

18–16

ACT2RW

Note: The recommended values are just a starting point and may need to be adjusted depending on the trace length for the data and DQS lines.

CL = 2.5 is not supported for SDR.

SDR: Count value is in SD_CLK periods.

DDR: Count value is in SD_CLK2 periods.

Reserved, must be cleared.

Active to read/write delay. Active command to any following read- or write-delay counter.

Suggested value = (t

RCD

Example:

× f

SD_CLK

) - 1 (Round up to nearest integer)

If t

RCD

= 20ns and f

SD_CLK

= 99 MHz

Suggested value = (20ns

99 MHz) - 1= 0.98; round to 1.

Note: Count value is in SD_CLK periods for SDR and DDR modes.

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18-18 Freescale Semiconductor

SDRAM Controller (SDRAMC)

Table 18-9. SDCFG1 Field Descriptions (continued)

Field Description

15 Reserved, must be cleared.

14–12

PRE2ACT

Precharge to active delay. Precharge command to following active command delay counter.

Suggested value = (t

Example:

× f

SD_CLK

) - 1 (Round up to nearest integer)

If t

= 20ns and f

SD_CLK

= 99 MHz

Suggested value = (20ns

99 MHz) - 1 = 0.98; round to 1.

Note: Count value is in SD_CLK periods for SDR and DDR modes.

11–8

REF2ACT

Refresh to active delay. Refresh command to following active or refresh command delay counter.

SDR/DDR: REF2ACT = (t

RFC

Example (for SDR/DDR):

× f

SD_CLK

) - 1 (Round up to nearest integer)

If t

RFC

= 75ns and f

SD_CLK

= 99 MHz

Suggested value = (75ns

99 MHz) - 1 = 6.425; round to 7.

6–4

WT_LAT

Note: Count value is in SD_CLK periods for SDR and DDR modes.

Reserved, must be cleared.

Write latency. Write command to write data delay counter.

SDR: write 0x0

DDR: write 0x3

3–0

Note: SDR mode: Count value is in SD_CLK periods.

DDR mode: Count value is in SD_CLK2 periods.

Reserved, must be cleared.

18.4.4 SDRAM Configuration Register 2 (SDCFG2)

The 32-bit read/write configuration register 2 stores delay values necessary between specific SDRAM commands. During initialization, software loads values to the register according to the SDRAM information obtained from the data sheet. This register is reset only by a power-up reset signal.

The burst length (BL) field must be exact. All other fields govern the relative timing from one command to another, they have minimum values but any larger value is also legal (but with decreased performance).

All delays in this register are expressed in SD_CLK. In all calculations for setting the fields of this register, convert time units to clock units and round up to the nearest integer.

Address: 0xFC0A_800C (SCFG2) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BRD2RP BWT2RWP BRD2W BL

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 18-8. SDRAM Configuration Register 2 (SDCFG2)

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 18-19

SDRAM Controller (SDRAMC)

15–0

Table 18-10. SDCFG2 Field Descriptions

Field Description

31–28

BRD2RP

Burst read to read/precharge delay. Limiting case is read to read.

SDR: BRD2RP = BurstLength + 1

DDR: BRD2RP = BurstLength/2 + 1

27–24

BWT2RWP

Burst write to read/write/precharge delay. Limiting case is write to precharge.

SDR: BWT2RWP = BurstLength + t

- 2

DDR: BWT2RWP = BurstLength/2 + t

23–20

BRD2W

Burst read to write delay.

SDR: BRD2W = CL + BurstLength

+ t

DDR: BRD2W = CL + BurstLength/2 - 1

19–16

Burst length.

BL = BurstLength - 1

Note: Burst length depends on port sizeIf 32-bit bus (SDCR[MEM_PS] = 0), burst length is 4. Write BL = 3.. If

16-bit bus (SDCR[MEM_PS] = 1), burst length is 8. Write BL = 7.

Reserved, must be cleared.

18.4.5 SDRAM Chip Select Configuration Registers (SDCSn)

These registers define base address and space size of each chip select.

NOTE

Because the SDRAM module is one of the slaves connected to the crossbar switch, it is only accessible within a certain memory range. The only applicable address ranges for which the chip-selects can be active are

0x4000_0000 – 0x7FFF_FFFF. Be sure to set the SDCSn registers appropriately.

NOTE

The user should not probe memory on a DDR chip select to determine if memory is connected. If a read is attempted from a DDR SDRAM chip select when there is no memory to respond with the appropriate DQS pulses, the bus cycle hangs. Because no high level bus monitor exists on the device, a reset is the only way to exit the error condition.

Address: 0xFC0A_8110 (SDCS0)

0xFC0A_8114 (SDCS1)

Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CSBA CSSZ

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 18-9. SRAM Chip Select Configuration Register (SDCSn)

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18-20 Freescale Semiconductor

SDRAM Controller (SDRAMC)

Table 18-11. SDCSn Field Descriptions

Field Description

31–20

CSBA

Chip-select base address. Because the SDRAM module is one of the slaves connected to the crossbar switch, it is only accessible within a certain memory range. The only applicable address ranges for which the chip-selects can be active are 0x4000_0000 – 0x7FFF_FFFF. Therefore, the possible range for this field is 0x400 – 0x7FF.

19–5 Reserved, must be cleared.

4–0

CSSZ

Chip select size.

CSSZ Size

Address Lines to Compare

CSSZ Size

Address Lines to Compare

00000 Disabled

00001–10001 Reserved

10010

10011

Reserved

1 MByte

10100

10101

10110

10111

2 MByte

4 MByte

8 MByte

16 MByte

—

Reserved

A[31:20]

A[31:21]

A[31:22]

A[31:23]

A[31:24]

11000

11001

11010

11011

11100

11101

11110

11111

32 MByte

64 MByte

128 MByte

256 MByte

512 MByte

1 GByte

2 GByte

4 GByte

A[31:25]

A[31:26]

A[31:27]

A[31:28]

A[31:29]

A[31:30]

A31

Ignore A[31:20]

Any chip-select can be enabled or disabled, independent of others. Any chip-select can be allocated any size of address space from 1M to 4G, independent of others. Any chip-select address space can begin at any size-aligned base address, independent of others.

For contiguous memory with different sizes of memory blocks, place largest block at the lowest address and place smaller blocks in descending size order at ascending base addresses.

For example, assume a system with 2 chip selects: CS0=16M, CS1=256M:

CS0CFG = 0x4F000017 = enable 16M @ 0x4F000000-0x4FFFFFFF

CS1CFG = 0x5000001B = enable 256M @ 0x50000000-0x5FFFFFFF

This gives 272 MB total memory, at 0x4F000000-0x5FFFFFFF.

18.5 Functional Description

18.5.1 SDRAM Commands

When an internal bus master accesses SDRAM address space, the memory controller generates the corresponding SDRAM command.

Table 18-12

lists SDRAM commands supported by the memory controller.

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Freescale Semiconductor 18-21

SDRAM Controller (SDRAMC)

Table 18-12. SDRAM Commands

Function

Command Inhibit

No Operation

Row and Bank Active

Read

Write

Burst Terminate (SDR/DDR only)

Precharge All Banks

Precharge Selected Bank

Load Mode Register

Load Extended Mode Register

Auto Refresh

Self Refresh

Power Down

INH

NOP

ACTV

READ

WRITE

BST

PALL

PRE

LMR

LEMR

REF

SREF

PDWN

Symbol CKE CS RAS CAS WE BA[1:0] A[10] Other A

→

H = High

L = Low

V = Valid

X = Don’t care

Many commands require a delay before the next command may be issued; sometimes the delay depends on the type of the next command. These delay requirements are managed by the values programmed in the memory controller configuration registers (SDCFG1, SDCFG2).

18.5.1.1

Row and Bank Active Command (

ACTV

)

The

ACTV

command is responsible for latching the row and bank address and activating the specified row bank of a memory block. After the row is activated, it can be accessed using subsequent read and write commands.

NOTE

The SDRAMC supports one active row for each chip select block. See

Section 18.6.1, “Page Management,”

for more information.

18.5.1.2

Read Command (

READ

)

When the SDRAMC receives a read request via the internal bus, it first checks the row and bank of the new access. If the address falls within the active row of an active bank, it is a page hit, and the read is issued as soon as possible (pending any delays required by previous commands). If the address is within an inactive bank, the memory controller issues an ACTV followed by the read command. If the address is not within the active row of an active bank, the memory controller issues a pre command to close the active

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18-22 Freescale Semiconductor

SDRAM Controller (SDRAMC)

row. Then, the SDRAMC issues ACTV to activate the necessary row and bank for the new access, followed by the read to the SDRAM.

The

PALL

PRE

and

ACTV

commands (if necessary) can sometimes be issued in parallel with an on-going data movement.

To truncate a burst read when only a single read is needed, the memory controller issues the burst-terminate command. With SDR memory, the data masks are negated throughout the entire read size.

With DDR memory, the data masks are asserted high throughout the entire read size; but DDR memory ignores the data masks during reads.

18.5.1.3

Write Command (

WRITE

)

When the memory controller receives a write request via the internal bus, it first checks the row and bank of the new access. If the address falls within the active row of an active bank, it is a page hit, and the

WRITE is issued as soon as possible (pending any delays required by previous commands). If the address is within the inactive bank, the memory controller issues an ACTV followed by the write command. If the address is not within the active row of an active bank, the memory controller issues a PRE command to close the active row. Then, the SDRAMC issues ACTV to activate the necessary row and bank for the new access, followed by the

WRITE

command to the SDRAM.

The PALL/PRE and ACTV commands (if necessary) can sometimes be issued in parallel with an on-going data movement.

In SDR mode, the memory controller issues the burst terminate command to truncate burst write for a single write. This is not the case for DDR system. With SDR and DDR memory, a read command can be issued overlapping the masked beats at the end of a previous single write of the case CS; the read command aborts the remaining (unnecessary) write beats.

18.5.1.4

Burst-Terminate Command (

BST

)

SDRAMs are burst-only devices, but provide mechanisms to truncate a burst if all of the beats are not needed. The burst-terminate command truncates read bursts (SDR and DDR) and write bursts (SDR). To truncate a burst write for DDR, the read command can abort the remaining unnecessary write beats. This method also works when in SDR mode. The most recently registered read or write command prior to the burst terminate command is truncated. The active page remains open.

18.5.1.5

Precharge-All-Banks (

PALL

) and Selected-Bank (

PRE

) Commands

The precharge command puts SDRAM into an idle state. The SDRAM must be in this idle state before a

REF,

LMR

LEMR

, or

ACTV

command to open a new row within a particular bank can be issued.

The memory controller issues the precharge command only when necessary for one of these conditions:

• Access to a new row

• Refresh interval elapsed

• Software commanded precharge during device initialization

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 18-23

SDRAM Controller (SDRAMC)

NOTE

A precharge is required after DRAMs also have a maximum bank-open period. The memory controller does not time the bank-open period because the refresh interval is always less.

18.5.1.6

Load Mode/Extended Mode Register Command (

LMR

LEMR

)

All SDRAM devices contain mode registers that configure the timing and burst mode for the SDRAM.

These commands access the mode registers that physically reside within the SDRAM devices. During the

LMR

LEMR

command, SDRAM latches the address and bank buses to load the values into the selected mode register.

NOTE

The

LMR

and

LEMR

commands are only used during SDRAM initialization.

Use the following steps to write the mode register and extended mode register:

1. Set the SDCR[MODE_EN] bit.

2. Write the SDMR[BA] bits to select the mode register.

3. Write the desired mode register value to the SDMR[ADDR]. Do not overwrite the SDMR[BA] values. This step can be performed in the same register write in step 2.

4. Set the SDMR[CMD] bit.

5. For DDR, step 2 to 4 should be performed twice. The first is for the extended-mode register, and the last is for the mode register.

6. Clear the SDCR[MODE_EN] bit.

18.5.1.6.1

Mode Register Definition

Figure 18-10

shows the mode register definition. This is the SDRAM’s mode register, not the SDRAMC’s mode/extended mode register (SDMR) defined in

Section 18.4.1, “SDRAM Mode/Extended Mode

.” Refer to device data sheet for detailed description.

BA1

Field 0

BA0

A11 A10 A9

OP_MODE

A8 A7 A6 A5

Figure 18-10. Mode Register

Table 18-13. Mode Register Field Descriptions

A2 A1

BLEN

Field Description

BA1–BA0 Bank address. These must be zero to select the mode register.

A11–A7

OP_MODE

Operating mode.

xx000 Standard Operation (SDR only)

00000 Normal Operation (DDR)

00010 Reset DLL (DDR)

Else Reserved

A6–A4

CAS latency. Delay in clocks from issuing a

READ

to valid data out. Check the SDRAM manufacturer’s spec because the CL settings supported can vary from memory to memory.

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18-24 Freescale Semiconductor

SDRAM Controller (SDRAMC)

Field

A2–A0

BLEN

Table 18-13. Mode Register Field Descriptions (continued)

Description

Burst type.

0 Sequential

1 Interleaved. This setting should not be used because the SDRAMC does not support interleaved bursts.

Burst length. Determines the number of column locations that are accessed for a given

READ

WRITE

command.

000 One. This setting is not valid for DDR.

001 Two

010 Four

011 Eight

Else Reserved

18.5.1.6.2

Extended Mode Register Definition

Figure 18-11 shows the extended-mode register used by DDR SDRAMs. This is the SDRAM’s extended

mode register, not the SDRAMC’s mode/extended-mode register (SDMR) defined in Section 18.4.1,

“SDRAM Mode/Extended Mode Register (SDMR) .” Refer to device data sheet for detailed description.

BA1

Field 0

BA0

A11 A10 A9 A8 A7 A6

OPTION

Figure 18-11. Extended Mode Register

A4 A3

Table 18-14. Extended-Mode Register Field Descriptions

A2 A1 A0

DLL

Field Description

BA1–BA0 Bank address. These must be set to 01 to select the extended mode register.

A11–A1

OPTION

Option. These bits are not defined by the DDR specification. Each DDR SDRAM manufacturer can use these bits to implement optional features. Check with the SDRAM manufacturer to determine if any optional features have been implemented. For normal operation all bits must be cleared.

DLL

Delay locked loop. Controls enabling of the delay locked loop circuitry used for DDR timing.

0 Enabled

1 Disabled

18.5.1.7

Auto-Refresh Command (REF)

The memory controller issues auto-refresh commands according to the SDCR[REF_CNT] value. Each time the programmed refresh interval elapses, the memory controller issues a

PALL

command followed by a REF command.

If a memory access is in progress at the time the refresh interval elapses, the memory controller schedules the refresh after the transfer finishes; the interval timer continues counting so the average refresh rate is constant.

After REF command, the SDRAM is in an idle state and waits for an

ACTV

command.

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SDRAM Controller (SDRAMC)

18.5.1.8

Self-Refresh (SREF) and Power Down (PDWN) Commands

The memory controller issues a PDWN or a SREF command if the SDCR[CKE] bit is cleared. If the

SDCR[REF_EN] bit is set when CKE is negated, the controller issues a SREF command; if the REF_EN bit is cleared, the controller issues a PDWN command. The REF_EN bit may be changed in the same register write that changes the CKE bit; the controller acts upon the new value of the REF_EN bit.

Like an auto-refresh command, the controller automatically issues a

PALL

command before the self-refresh command.

The memory reactivates from power-down or self-refresh mode by setting the CKE bit.

If a normal refresh interval elapses while the memory is in self-refresh mode, a PALL and REF performs when the memory reactivates. If the memory is put into and brought out of self-refresh all within a single-refresh interval, the next automatic refresh occurs on schedule.

In self-refresh mode, memory does not require an external clock. The SD_CLK can be stopped for maximum power savings. If the memory controller clock is stopped, the refresh-interval timer must be reset before the memory is reactivated (if periodic refresh is to be resumed). The refresh-interval timer resets by clearing the REF_EN bit. This can be done at any time while the memory is in self-refresh mode, before or after the memory controller clock is stopped/restarted, but not with the same control register write that clears CKE; this would put the memory in power down mode. To restart periodic refresh when the memory reactivates, the REF_EN bit must be reasserted; this can be done before the memory reactivates or in the same control register write that sets CKE to exit self-refresh mode.

18.5.2 Read Clock Recovery (RCR) Block

The RCR block allows the external DDR memory devices to generate clock pulses (strobes) that define the data valid window for each DDR data cycle. The RCR delay block compensates for each byte lane and generates an internal read strobe targeted to the center of the data valid window provided by the external

DDR memories.

Figure 18-12

displays a simple timing diagram that illustrates the end result of the RCR delay.

CLK

Memory

Clock t

CLK

/2 t

CLK

/2 Don’t Care t

CLK t

CLK

/2 t

CLK

SD_DQSn t

CLK

/4 t

CLK

/2 t

CLK

/4 t

CLK

rd_clk

(internal signal)

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SDRAM Controller (SDRAMC)

Figure 18-12. Frequency Doubler Block Diagram

Dual data rate (DDR) memories provide data strobe (DQS) timing reference signals in parallel with read data. However, these strobe signals cannot directly clock the data because the strobe edges are aligned with the edges of the data valid window, not the center. The RCR delay module is responsible for delaying the received DQS edges to achieve data-center alignment instead of data-edge alignment. There are two data valid windows per memory clock period with DDR, so the nominal delay of read clocks from DQS is 1/4 memory clock period.

Single data rate (SDR) memories do not use or provide DQS signals. In SDR mode, the SDRAM controller provides an SDRDQS signal that can be driven off-chip and routed back into the DQS inputs. The center of the data valid window is guaranteed relative to the memory clock at the memory devices.

The round-trip SDRDQS-to-DQS delay must match the memory clock output + read data input + round-trip time-of-flight delay so that the received DQS edges have a known phase relationship to the received data. The SDRDQS signal is generated with a 1/4 memory clock period lead time, to compensate for the 1/4 memory clock period delay of DQS through the RCR delay module.

The RCR delay module maintains the 1/4 memory clock period delay of the DQS signals across the full range of silicon process, voltage, and temperature conditions.

The RD_CLK is an internal reconstructed clock derived from DQS. It is twice the frequency of DQS, with the rising edge shifted 1/4 memory clock period after the DQS edge to align with the nominal center of the data valid window.

18.6 Initialization/Application Information

SDRAMs have a prescribed initialization sequence. The following section details the memory initialization steps for DDR SDRAM. The sequence might change slightly from device-to-device. Refer to the device datasheet as the most relevant reference.

1. After reset is deactivated, pause for the amount of time indicated in SDRAM specification. Usually

100

μs or 200μs.

2. Configure pin multiplex control for shared SD_CS pins in GPIO module.

3. Configure the slew rate for the SDRAM external pins in the pin multiplexing and control module’s

MSCR_SDRAM register.

4. Write the base address and mask registers (SDBAR0, SDBAR1, SDMR0, and SDMR1) to setup the address space for each chip-select.

5. Program SDRAM configuration registers (SDCFG1 and SDCFG2) with correct delay and timing values.

6. Issue a

PALL

command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] set.

The SDCR[REF and IREF] bits should remain cleared for this step.

7. Initialize the SDRAM’s extended mode register to enable the DLL. See

Section 18.5.1.6, “Load

Mode/Extended Mode Register Command (

LMR

LEMR

),”

for instructions on issuing a

LEMR command.

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SDRAM Controller (SDRAMC)

8. Initialize the SDRAM’s mode register and reset the DLL using the

LMR

command. See

Section 18.5.1.6, “Load Mode/Extended Mode Register Command (

LMR

LEMR

),”

for more instruction on issuing a

LMR

command. During this step the OP_MODE field of the mode register should be set to normal operation/reset DLL.

9. Pause for the DLL lock time specified by the memory.

10. Issue a second

PALL

command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL] set. The SDCR[REF and IREF] bits should remain cleared for this step.

11. Refresh the SDRAM. The SDRAM specification should indicate many refresh cycles performed before issuing an

LMR

command. Write to the SDCR with the IREF bit set (SDCR[REF and

IPALL] must be cleared). This forces a refresh of the SDRAM each time the IREF bit is set. Repeat this step until the specified number of refresh cycles have been completed.

12. Initialize the SDRAM’s mode register using the

LMR

command. See Section 18.5.1.6, “Load

Mode/Extended Mode Register Command (

LMR

LEMR

),”

for more instruction on issuing an

LMR command. During this step the OP_MODE field of the mode register should be set to normal operation.

13. Set SDCR[REF] to enable automatic refreshing, and clear SDCR[MODE_EN] to lock the SDMR.

SDCR[IREF and IPALL] remain cleared.

18.6.1 Page Management

SDRAM devices have four internal banks. A particular row and bank of memory must be activated to allow read and write accesses. The SDRAM controller supports paging mode to maximize the memory access throughout. During operation, the SDRAM controller maintains an open page for each SD_CS block. An open page is composed of the active rows in the internal banks. Each internal bank has its own active row.

The physical page size of a SD_CS block is equal to the space size divided by the number of rows; but the page may not be contiguous in the internal address space because SDRAMs can have a different row address open in each bank and the internal address bits (A[27:24] and A[9:2]) or (A[27:24] and A[9:1]) used for memory column addresses are not consecutive.

Because the column address may split across two portions of the internal address, the contiguous page size is (number of contiguous columns per bank)

× (number of bits). This gives a contiguous page size of

1 KBytes. However, the total (possibly fragmented) page size is (number of banks)

× (number of columns)

× (number of bits).

If a new access does not fall in the open row of an open bank of a SD_CS block, the open row must be closed (

PRE

) and the new row must be opened (

ACTV

), then the

READ

WRITE

command can proceed. An

ACTV

command activates only one bank at one time. If another read or write falls in an inactive bank, another

ACTV

is needed, but no precharge is needed. If a read or write falls in any open row of any active banks of a page, no

PRE

ACTV

is needed; the read or write command can be issued immediately.

A page is kept open until one of the following conditions occurs:

• An access outside the open page.

• A refresh cycle is started.

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SDRAM Controller (SDRAMC)

All SD_CS blocks are refreshed at the same time. The refresh closes all banks of every SDRAM block.

18.6.2 Transfer Size

In the SDRAMC, the internal data bus is 32 bits wide, while the SDRAM external interface bus is

32 or 16 bits wide. Therefore, each internal data beat requires one or two memory data beats. The SDRAM controller manages the size translation (packing/unpacking) between internal and external DRAM buses.

The burst size is the processor standard 16 bytes: Four beats of 4 bytes on the internal bus, four beats of 4 bytes (32-bit mode), or eight beats of 2 bytes (16-bit mode) on the memory bus. The SDRAM controller follows the critical beat first, sequential transfer format required.

The burst size and transfer order must be programmed in the SDRAM mode registers during initialization; the burst size also must be programmed in the memory controller (SDCFG2 register).

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Freescale Semiconductor

Chapter 19 Fast Ethernet Controller (FEC)

19.1 Introduction

This chapter provides a feature-set overview, a functional block diagram, and transceiver connection information for the 10 and 100 Mbps MII (media independent interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included.

19.1.1 Overview

The Ethernet media access controller (MAC) supports 10 and 100 Mbps Ethernet/IEEE 802.3 networks.

An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports three different standard MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and the 10 Mbps-only 7-wire interface.

NOTE

The module must be configured to enable the peripheral function of the

appropriate pins (refer to Chapter 13, “General Purpose I/O Module”

) prior to configuring the FEC.

19.1.2 Block Diagram

Figure 19-1

shows the block diagram of the FEC. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards.

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19-1

Fast Ethernet Controller (FEC)

Internal Bus

Interface

Bus

Controller

Control/Status

Registers

MIB

Counter RAM

FIFO

RAM

Interface

FIFO

Controller

Descriptor

Controller

(RISC + microcode)

Crossbar Switch

Master Bus

FEC DMA

MII Transmit Receive

MDO

MDEN

MDI

I/O

PAD

FEC_MDIO FEC_MDC

FEC_TXEN

FEC_TXD[3:0]

FEC_TXER

FEC_TXCLK

FEC_CRS

FEC_COL

FEC_RXCLK

FEC_RXDV

FEC_RXD[3:0]

FEC_RXER

MII/7-Wire data option

FEC Bus

Figure 19-1. FEC Block Diagram

The descriptor controller is a RISC-based controller providing these functions in the FEC:

• Initialization (those internal registers not initialized by you or hardware)

• High level control of the DMA channels (initiating DMA transfers)

• Interpreting buffer descriptors

• Address recognition for receive frames

• Random number generation for transmit collision backoff timer

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Fast Ethernet Controller (FEC)

NOTE

DMA references in this section refer to the FEC’s DMA engine. This DMA engine transfers FEC data only and is not related to the eDMA controller

described in Chapter 16, “Enhanced Direct Memory Access (eDMA)

, ” nor to the DMA timers described in

Chapter 22, “DMA Timers

(DTIM0–DTIM3).”

The RAM is the focal point of all data flow in the Fast Ethernet controller and divides into transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the transmit block, and receive data flows from the receive block into the receive FIFO.

You control the FEC by writing into control registers located in each block. The CSR (control and status registers) block provides global control (Ethernet reset and enable) and interrupt managing registers.

The MII block provides a serial channel for control/status communication with the external physical layer device (transceiver). This serial channel consists of the FEC_MDC (management data clock) and

FEC_MDIO (management data input/output) lines of the MII interface.

The FEC DMA block (not to be confused with the device’s eDMA controller) provides multiple channels allowing transmit data, transmit descriptor, receive data and receive descriptor accesses to run independently.

The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from microcode).

The message information block (MIB) maintains counters for a variety of network events and statistics. It is not necessary for operation of the FEC, but provides valuable counters for network management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3

counters. See Section 19.4.1, “MIB Block Counters Memory Map,”

for more information.

19.1.3 Features

The FEC incorporates the following features:

• Support for three different Ethernet physical interfaces:

— 100-Mbps IEEE 802.3 MII

— 10-Mbps IEEE 802.3 MII

— 10-Mbps 7-wire interface (industry standard)

• IEEE 802.3 full duplex flow control

• Programmable max frame length supports IEEE 802.1 VLAN tags and priority

• Support for full-duplex operation (200 Mbps throughput) with a minimum internal bus clock rate of 50 MHz

• Support for half-duplex operation (100 Mbps throughput) with a minimum internal bus clock rate of 50 MHz

• Retransmission from transmit FIFO following a collision (no processor bus utilization)

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Fast Ethernet Controller (FEC)

• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization)

• Address recognition

— Frames with broadcast address may be always accepted or always rejected

— Exact match for single 48-bit individual (unicast) address

— Hash (64-bit hash) check of individual (unicast) addresses

— Hash (64-bit hash) check of group (multicast) addresses

— Promiscuous mode

19.2 Modes of Operation

The primary operational modes are described in this section.

19.2.1 Full and Half Duplex Operation

Full duplex mode is for use on point-to-point links between switches or end node to switch. Half duplex mode works in connections between an end node and a repeater or between repeaters. TCR[FDEN] controls duplex mode selection.

When configured for full duplex mode, flow control may be enabled. Refer to the

TCR[RFC_PAUSE,TFC_PAUSE] bits, the RCR[FCE] bit, and Section 19.5.11, “Full Duplex Flow

Control ,” for more details.

19.2.2 Interface Options

The following interface options are supported. A detailed discussion of the interface configurations is provided in

Section 19.5.6, “Network Interface Options.”

19.2.2.1

10 Mbps and 100 Mbps MII Interface

The IEEE 802.3 standard defines the media independent interface (MII) for 10/100 Mbps operation. The

MAC-PHY interface may be configured to operate in MII mode by setting RCR[MII_MODE].

FEC_TXCLK and FEC_RXCLK pins driven by the external transceiver determine the operation speed.

The transceiver auto-negotiates the speed or software controls it via the serial management interface

(FEC_MDC/FEC_MDIO pins) to the transceiver. Refer to the MMFR and MSCR register descriptions, as well as the section on the MII, for a description of how to read and write registers in the transceiver via this interface.

19.2.2.2

10 Mpbs 7-Wire Interface Operation

The FEC supports 7-wire interface used by many 10 Mbps Ethernet transceivers. The RCR[MII_MODE] bit controls this functionality. If this bit is cleared, MII mode is disabled and the 10 Mbps 7-wire mode is enabled.

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Fast Ethernet Controller (FEC)

19.2.3 Address Recognition Options

The address options supported are promiscuous, broadcast reject, individual address (hash or exact match), and multicast hash match. Address recognition options are discussed in detail in

Section 19.5.9, “Ethernet

Address Recognition.”

19.2.4 Internal Loopback

Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in

Section 19.5.14, “MII Internal and External Loopback.”

19.3 External Signal Description

Table 19-1

describes the various FEC signals, as well as indicating which signals work in available modes.

Table 19-1. FEC Signal Descriptions

Signal Name Description

FEC_COL

FEC_CRS

FEC_MDC

X X Asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode.

X — When asserted, indicates that transmit or receive medium is not idle.

X — Output clock which provides a timing reference to the PHY for data transfers on the FEC_MDIO signal.

FEC_MDIO X — Transfers control information between the external PHY and the media-access controller. Data is synchronous to FEC_MDC. This signal is an input after reset. When the FEC is operated in

10Mbps 7-wire interface mode, this signal should be connected to VSS.

FEC_RXCLK X X Provides a timing reference for FEC_RXDV, FEC_RXD[3:0], and FEC_RXER.

FEC_RXDV X X Asserting the FEC_RXDV input indicates that the PHY has valid nibbles present on the MII.

FEC_RXDV should remain asserted from the first recovered nibble of the frame through to the last nibble. Assertion of FEC_RXDV must start no later than the SFD and exclude any EOF.

FEC_RXD0

FEC_RXD1

X X This pin contains the Ethernet input data transferred from the PHY to the media-access controller when FEC_RXDV is asserted.

X — This pin contains the Ethernet input data transferred from the PHY to the media access controller when FEC_RXDV is asserted.

FEC_RXD[3:2] X — These pins contain the Ethernet input data transferred from the PHY to the media access controller when FEC_RXDV is asserted.

FEC_RXER X — When asserted with FEC_RXDV, indicates that the PHY has detected an error in the current frame. When FEC_RXDV is not asserted FEC_RXER has no effect.

FEC_TXCLK X X Input clock which provides a timing reference for FEC_TXEN, FEC_TXD[3:0] and FEC_TXER.

FEC_TXD0 X X The serial output Ethernet data and is only valid during the assertion of FEC_TXEN.

FEC_TXD1 X — This pin contains the serial output Ethernet data and is valid only during assertion of

FEC_TXEN.

FEC_TXD[3:2] X — These pins contain the serial output Ethernet data and are valid only during assertion of

FEC_TXEN.

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Fast Ethernet Controller (FEC)

Table 19-1. FEC Signal Descriptions (continued)

Signal Name

FEC_TXEN

FEC_TXER

Description

X X Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first FEC_TXCLK following the final nibble of the frame.

X — When asserted for one or more clock cycles while FEC_TXEN is also asserted, the PHY sends one or more illegal symbols. FEC_TXER has no effect at 10 Mbps or when FEC_TXEN is negated.

19.4 Memory Map/Register Definition

The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The

CSRs control operation modes and extract global status information. The descriptors pass data buffers and related buffer information between the hardware and software.

Each FEC implementation requires a 1-Kbyte memory map space, which is divided into two sections of

512 bytes each for:

• Control/status registers

• Event/statistic counters held in the MIB block

Table 19-2

defines the top level memory map.

Table 19-2. Module Memory Map

Address

0xFC03_0000 – FC03_01FF

0xFC03_0200 – FC03_02FF

Function

Control/Status Registers

MIB Block Counters

Table 19-3

shows the FEC register memory map.

Table 19-3. FEC Register Memory Map

Address Register

0xFC03_0004 Interrupt Event Register (EIR)

0xFC03_0008 Interrupt Mask Register (EIMR)

0xFC03_0010 Receive Descriptor Active Register (RDAR)

0xFC03_0014 Transmit Descriptor Active Register (TDAR)

0xFC03_0024 Ethernet Control Register (ECR)

0xFC03_0040 MII Management Frame Register (MMFR)

0xFC03_0044 MII Speed Control Register (MSCR)

0xFC03_0064 MIB Control/Status Register (MIBC)

0xFC03_0084 Receive Control Register (RCR)

0xFC03_00C4 Transmit Control Register (TCR)

Width

(bits)

Access Reset Value

R/W

0x0000_0000

0xF000_0000

Undefined

0x0000_0000

Section/Page

0x05EE_0001

0x0000_0000

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Fast Ethernet Controller (FEC)

Table 19-3. FEC Register Memory Map (continued)

Address Register

Width

(bits)

Access Reset Value

0xFC03_00E4 Physical Address Low Register (PALR)

0xFC03_00E8 Physical Address High Register (PAUR)

0xFC03_00EC Opcode/Pause Duration (OPD) 32

0xFC03_0118 Descriptor Individual Upper Address Register (IAUR) 32

0xFC03_011C Descriptor Individual Lower Address Register (IALR) 32

0xFC03_0120 Descriptor Group Upper Address Register (GAUR) 32

0xFC03_0124 Descriptor Group Lower Address Register (GALR)

0xFC03_0144 Transmit FIFO Watermark (TFWR)

0xFC03_014C FIFO Receive Bound Register (FRBR)

0xFC03_0150 FIFO Receive FIFO Start Register (FRSR)

0xFC03_0180 Pointer to Receive Descriptor Ring (ERDSR)

0xFC03_0184 Pointer to Transmit Descriptor Ring (ETDSR)

0xFC03_0188 Maximum Receive Buffer Size (EMRBR)

R/W

Section/Page

Undefined

See Section

Undefined

Undefined

Undefined

0x0000_0000

0x0000_0600

0x0000_0500

Undefined

19.4.1 MIB Block Counters Memory Map

The MIB counters memory map ( Table 19-4 ) defines the locations in the MIB RAM space where

hardware-maintained counters reside. The counters are divided into two groups:

• RMON counters include the Ethernet statistics counters defined in RFC 1757

• A counter is included to count truncated frames since only frame lengths up to 2047 bytes are supported

The transmit and receive RMON counters are independent, which ensures accurate network statistics when operating in full duplex mode.

The included IEEE counters support the mandatory and recommended counter packages defined in

Section 5 of ANSI/IEEE Std. 802.3 (1998 edition). The FEC supports IEEE Basic Package objects, but these do not require counters in the MIB block. In addition, some of the recommended package objects supported do not require MIB counters. Counters for transmit and receive full duplex flow control frames are also included.

Table 19-4. MIB Counters Memory Map

Address

0xFC03_0200

0xFC03_0204

0xFC03_0208

0xFC03_020C

Register

Count of frames not counted correctly (RMON_T_DROP)

RMON Tx packet count (RMON_T_PACKETS)

RMON Tx broadcast packets (RMON_T_BC_PKT)

RMON Tx multicast packets (RMON_T_MC_PKT)

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Fast Ethernet Controller (FEC)

Address

0xFC03_0250

0xFC03_0254

0xFC03_0258

0xFC03_025C

0xFC03_0260

0xFC03_0264

0xFC03_0268

0xFC03_026C

0xFC03_0270

0xFC03_0274

0xFC03_0280

0xFC03_0284

0xFC03_0288

0xFC03_028C

0xFC03_0290

0xFC03_0294

0xFC03_0298

0xFC03_0210

0xFC03_0214

0xFC03_0218

0xFC03_021C

0xFC03_0220

0xFC03_0224

0xFC03_0228

0xFC03_022C

0xFC03_0230

0xFC03_0234

0xFC03_0238

0xFC03_023C

0xFC03_0240

0xFC03_0244

0xFC03_0248

0xFC03_024C

Table 19-4. MIB Counters Memory Map (continued)

Register

RMON Tx packets with CRC/align error (RMON_T_CRC_ALIGN)

RMON Tx packets < 64 bytes, good CRC (RMON_T_UNDERSIZE)

RMON Tx packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE)

RMON Tx packets < 64 bytes, bad CRC (RMON_T_FRAG)

RMON Tx packets > MAX_FL bytes, bad CRC (RMON_T_JAB)

RMON Tx collision count (RMON_T_COL)

RMON Tx 64 byte packets (RMON_T_P64)

RMON Tx 65 to 127 byte packets (RMON_T_P65TO127)

RMON Tx 128 to 255 byte packets (RMON_T_P128TO255)

RMON Tx 256 to 511 byte packets (RMON_T_P256TO511)

RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023)

RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047)

RMON Tx packets with > 2048 bytes (RMON_T_P_GTE2048)

RMON Tx Octets (RMON_T_OCTETS)

Count of transmitted frames not counted correctly (IEEE_T_DROP)

Frames transmitted OK (IEEE_T_FRAME_OK)

Frames transmitted with single collision (IEEE_T_1COL)

Frames transmitted with multiple collisions (IEEE_T_MCOL)

Frames transmitted after deferral delay (IEEE_T_DEF)

Frames transmitted with late collision (IEEE_T_LCOL)

Frames transmitted with excessive collisions (IEEE_T_EXCOL)

Frames transmitted with Tx FIFO underrun (IEEE_T_MACERR)

Frames transmitted with carrier sense error (IEEE_T_CSERR)

Frames transmitted with SQE error (IEEE_T_SQE)

Flow control pause frames transmitted (IEEE_T_FDXFC)

Octet count for frames transmitted without error (IEEE_T_OCTETS_OK)

Count of received frames not counted correctly (RMON_R_DROP)

RMON Rx packet count (RMON_R_PACKETS)

RMON Rx broadcast packets (RMON_R_BC_PKT)

RMON Rx multicast packets (RMON_R_MC_PKT)

RMON Rx packets with CRC/Align error (RMON_R_CRC_ALIGN)

RMON Rx packets < 64 bytes, good CRC (RMON_R_UNDERSIZE)

RMON Rx packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE)

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Fast Ethernet Controller (FEC)

Table 19-4. MIB Counters Memory Map (continued)

Address Register

0xFC03_029C

0xFC03_02A0

0xFC03_02A4

0xFC03_02A8

0xFC03_02AC

0xFC03_02B0

0xFC03_02B4

0xFC03_02B8

RMON Rx packets < 64 bytes, bad CRC (RMON_R_FRAG)

RMON Rx packets > MAX_FL bytes, bad CRC (RMON_R_JAB)

Reserved (RMON_R_RESVD_0)

RMON Rx 64 byte packets (RMON_R_P64)

RMON Rx 65 to 127 byte packets (RMON_R_P65TO127)

RMON Rx 128 to 255 byte packets (RMON_R_P128TO255)

RMON Rx 256 to 511 byte packets (RMON_R_P256TO511)

RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023)

0xFC03_02BC

0xFC03_02C0

0xFC03_02C4

0xFC03_02C8

RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047)

RMON Rx packets with > 2048 bytes (RMON_R_P_GTE2048)

RMON Rx octets (RMON_R_OCTETS)

Count of received frames not counted correctly (IEEE_R_DROP)

0xFC03_02CC Frames received OK (IEEE_R_FRAME_OK)

0xFC03_02D0 Frames received with CRC error (IEEE_R_CRC)

0xFC03_02D4

0xFC03_02D8

Frames received with alignment error (IEEE_R_ALIGN)

Receive FIFO overflow count (IEEE_R_MACERR)

0xFC03_02DC Flow control pause frames received (IEEE_R_FDXFC)

0xFC03_02E0 Octet count for frames received without error (IEEE_R_OCTETS_OK)

19.4.2 Ethernet Interrupt Event Register (EIR)

When an event occurs that sets a bit in EIR, an interrupt occurs if the corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to an EIR bit clears it; writing 0 has no effect. This register is cleared upon hardware reset.

These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB, and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR,

BABR, BABT, LC, and RL. Interrupts resulting from internal errors are HBERR and UN.

Some of the error interrupts are independently counted in the MIB block counters:

• HBERR - IEEE_T_SQE

• BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)

• BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)

• LATE_COL - IEEE_T_LCOL

• COL_RETRY_LIM - IEEE_T_EXCOL

• XFIFO_UN - IEEE_T_MACERR

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Fast Ethernet Controller (FEC)

Software may choose to mask off these interrupts because these errors are visible to network management via the MIB counters.

Address: 0xFC03_0004

R HB

ERR

30 29 28

BABR BABT GRA

TXF

TXB

RXF

RXB

MII

ERR

W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Access: User read/write

R 0

Reset 0

0 0 0 0 0 0 0 0 0 0

Figure 19-2. Ethernet Interrupt Event Register (EIR)

Table 19-5. EIR Field Descriptions

0 0 0 0

Field Description

TXF

TXB

RXF

RXB

MII

HBERR

Heartbeat error. Indicates TCR[HBC] is set and that the COL input was not asserted within the heartbeat window following a transmission.

Babbling receive error. Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.

BABR

BABT

GRA

Babbling transmit error. Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually this condition is caused by a frame that is too long is placed into the transmit data buffer(s). Truncation does not occur.

Graceful stop complete. Indicates the graceful stop is complete. During graceful stop the transmitter is placed into a pause state after completion of the frame currently being transmitted. This bit is set by one of three conditions:

1) A graceful stop initiated by the setting of the TCR[GTS] bit is now complete.

2) A graceful stop initiated by the setting of the TCR[TFC_PAUSE] bit is now complete.

3) A graceful stop initiated by the reception of a valid full duplex flow control pause frame is now complete. Refer

to Section 19.5.11, “Full Duplex Flow Control.”

Transmit frame interrupt. Indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated.

Transmit buffer interrupt. Indicates a transmit buffer descriptor has been updated.

Receive frame interrupt. Indicates a frame has been received and the last corresponding buffer descriptor has been updated.

Receive buffer interrupt. Indicates a receive buffer descriptor not the last in the frame has been updated.

MII interrupt. Indicates the MII has completed the data transfer requested.

EBERR

Ethernet bus error. Indicates a system bus error occurred when a DMA transaction is underway. When the EBERR bit is set, ECR[ETHER_EN] is cleared, halting frame processing by the FEC. When this occurs, software needs to ensure that the FIFO controller and DMA also soft reset.

Late collision. Indicates a collision occurred beyond the collision window (slot time) in half duplex mode. The frame truncates with a bad CRC and the remainder of the frame is discarded.

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Table 19-5. EIR Field Descriptions (continued)

Field Description

Collision retry limit. Indicates a collision occurred on each of 16 successive attempts to transmit the frame. The frame is discarded without being transmitted and transmission of the next frame commences. This error can only occur in half duplex mode.

Transmit FIFO underrun. Indicates the transmit FIFO became empty before the complete frame was transmitted. A bad CRC is appended to the frame fragment and the remainder of the frame is discarded.

18–0 Reserved, must be cleared.

19.4.3 Interrupt Mask Register (EIMR)

The EIMR register controls which interrupt events are allowed to generate actual interrupts. All implemented bits in this CSR are read/write. A hardware reset clears this register. If the corresponding bits in the EIR and EIMR registers are set, an interrupt is generated. The interrupt signal remains asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.

Address: 0xFC03_0008

ERR

Reset 0

BABR BABT GRA TXF TXB RXF RXB MII

ERR

Access: User read/write

0 0 0 0

R 0

Reset 0

0 0 0 0 0 0 0 0 0 0 0

Figure 19-3. Ethernet Interrupt Mask Register (EIMR)

0 0 0 0

Table 19-6. EIMR Field Descriptions

Field Description

31–19

See

Figure 19-3

and Table 19-5

Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The corresponding

EIMR bit determines whether an interrupt condition can generate an interrupt. At every processor clock, the

EIR samples the signal generated by the interrupting source. The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit is set.

0 The corresponding interrupt source is masked.

1 The corresponding interrupt source is not masked.

18–0 Reserved, must be cleared.

19.4.4 Receive Descriptor Active Register (RDAR)

RDAR is a command register, written by the user, indicating the receive descriptor ring is updated (the driver produced empty receive buffers with the empty bit set).

When the register is written, the RDAR bit is set. This is independent of the data actually written by the user. When set, the FEC polls the receive descriptor ring and processes receive frames (provided

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ECR[ETHER_EN] is also set). After the FEC polls a receive descriptor whose empty bit is not set, FEC clears the RDAR bit and ceases receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors are placed into the receive descriptor ring.

The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared.

Address: 0xFC03_0010 Access: User read/write

31 30 29 28 27 26 25

R 0 0 0 0 0 0 0

RDAR

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 19-4. Receive Descriptor Active Register (RDAR)

Table 19-7. RDAR Field Descriptions

Field Description

31–25 Reserved, must be cleared.

RDAR

Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional empty descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared.

23–0 Reserved, must be cleared.

19.4.5 Transmit Descriptor Active Register (TDAR)

The TDAR is a command register which the user writes to indicate the transmit descriptor ring is updated

(transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor).

When the register is written, the TDAR bit is set. This value is independent of the data actually written by the user. When set, the FEC polls the transmit descriptor ring and processes transmit frames (provided

ECR[ETHER_EN] is also set). After the FEC polls a transmit descriptor that is a ready bit not set, FEC clears the TDAR bit and ceases transmit descriptor ring polling until the user sets the bit again, signifying additional descriptors are placed into the transmit descriptor ring.

The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set.

Address: 0xFC03_0014 Access: User read/write

31 30 29 28 27 26 25

R 0 0 0 0 0 0 0

TDAR

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 19-5. Transmit Descriptor Active Register (TDAR)

Field

31–25 Reserved, must be cleared.

Table 19-8. TDAR Field Descriptions

Description

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Fast Ethernet Controller (FEC)

Table 19-8. TDAR Field Descriptions (continued)

Field Description

TDAR

Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional ready descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared.

23–0 Reserved, must be cleared.

19.4.6 Ethernet Control Register (ECR)

ECR is a read/write user register, though hardware may alter fields in this register as well. The ECR enables/disables the FEC.

Address: 0xFC03_0024 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

R 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETHER

_EN

RESET

Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 19-6. Ethernet Control Register (ECR)

Table 19-9. ECR Field Descriptions

Field Description

31–2 Reserved, must be cleared.

ETHER_EN

When this bit is set, FEC is enabled, and reception and transmission are possible. When this bit is cleared, reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When

ETHER_EN is cleared, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer descriptor and FIFO pointers. Hardware alters the ETHER_EN bit under the following conditions:

• ECR[RESET] is set by software, in which case ETHER_EN is cleared

• An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN is cleared

RESET

When this bit is set, the equivalent of a hardware reset is performed but it is local to the FEC. ECR[ETHER_EN] is cleared and all other FEC registers take their reset values. Also, any transmission/reception currently in progress is abruptly aborted. This bit is automatically cleared by hardware during the reset sequence. The reset sequence takes approximately eight internal bus clock cycles after this bit is set.

19.4.7 MII Management Frame Register (MMFR)

The MMFR is user-accessible and does not reset to a defined value. The MMFR register is used to communicate with the attached MII compatible PHY device(s), providing read/write access to their MII registers. Performing a write to the MMFR causes a management frame to be sourced unless the MSCR is programmed to 0. If MSCR is cleared while MMFR is written and then MSCR is written with a non-zero value, an MII frame is generated with the data previously written to the MMFR. This allows MMFR and

MSCR to be programmed in either order if MSCR is currently zero.

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Address: 0xFC03_0040 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ST OP PA RA TA DATA

Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

Figure 19-7. MII Management Frame Register (MMFR)

Table 19-10. MMFR Field Descriptions

Field

31–30

29–28

Description

Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame.

27–23

22–18

17–16

15–0

DATA

Operation code.

00 Write frame operation, but not MII compliant.

01 Write frame operation for a valid MII management frame.

10 Read frame operation for a valid MII management frame.

11 Read frame operation, but not MII compliant.

PHY address. This field specifies one of up to 32 attached PHY devices.

Turn around. This field must be programmed to 10 to generate a valid MII management frame.

Management frame data. This is the field for data to be written to or read from the PHY register.

To perform a read or write operation on the MII Management Interface, write the MMFR register. To generate a valid read or write management frame, ST field must be written with a 01 pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame is generated, but does not comply with the IEEE 802.3 MII definition.

To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern causes the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time, contents of the MMFR register are altered as the contents are serially shifted and are unpredictable if read by the user. After the write management frame operation completes, the MII interrupt is generated. At this time, contents of the MMFR register match the original value written.

To generate an MII management interface read frame (read a PHY register), the user must write {01 10

PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a don’t care). Writing this pattern causes the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time, contents of the MMFR register are altered as the contents are serially shifted and are unpredictable if read by the user. After the read management frame operation completes, the MII interrupt is generated. At this time, the contents of the MMFR register match

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the original value written except for the DATA field whose contents are replaced by the value read from the PHY register.

If the MMFR register is written while frame generation is in progress, the frame contents are altered.

Software must use the MII interrupt to avoid writing to the MMFR register while frame generation is in progress.

19.4.8 MII Speed Control Register (MSCR)

The MSCR provides control of the MII clock (FEC_MDC pin) frequency and allows a preamble drop on the MII management frame.

Address: 0xFC03_0044 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIS_

PRE

6 5 4 3 2 1 0

MII_SPEED

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 19-8. MII Speed Control Register (MSCR)

Table 19-11. MSCR Field Descriptions

Field Description

31–8

DIS_PRE

Reserved, must be cleared.

Setting this bit causes the preamble (32 ones) not to be prepended to the MII management frame. The MII standard allows the preamble to be dropped if the attached PHY device(s) does not require it.

6–1

MII_SPEED

Controls the frequency of the MII management interface clock (FEC_MDC) relative to the internal bus clock. A value of 0 in this field turns off the FEC_MDC and leaves it in low voltage state. Any non-zero value results in the

FEC_MDC frequency of 1/(MII_SPEED

2) of the internal bus frequency.

0 Reserved, must be cleared.

The MII_SPEED field must be programmed with a value to provide an FEC_MDC frequency of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to a non-zero value to source a read or write management frame. After the management frame is complete, the MSCR register may optionally be set to 0 to turn off the FEC_MDC. The FEC_MDC generated has a

50% duty cycle except when MII_SPEED changes during operation (change takes effect following a rising or falling edge of FEC_MDC).

If the internal bus clock is 25 MHz, programming this register to 0x0000_0005 results in an FEC_MDC as stated the equation below.

25 MHz

------------

= 2.5 MHz

Eqn. 19-1

A table showing optimum values for MII_SPEED as a function of internal bus clock frequency is provided below.

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Table 19-12. Programming Examples for MSCR

Internal FEC Clock

Frequency

25 MHz

33 MHz

40 MHz

50 MHz

66 MHz

MSCR[MII_SPEED]

0x5

0x7

0x8

0xA

0xE

FEC_MDC frequency

2.50 MHz

2.36 MHz

2.50 MHz

2.36 MHz

19.4.9 MIB Control Register (MIBC)

The MIBC is a read/write register controlling and observing the state of the MIB block. User software accesses this register if there is a need to disable the MIB block operation. For example, to clear all MIB counters in RAM:

1. Disable the MIB block

2. Clear all the MIB RAM locations

3. Enable the MIB block

The MIB_DIS bit is reset to 1. See Table 19-4 for the locations of the MIB counters.

Address: 0xFC03_0064 Access: User read/write

MIB_

DIS

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MIB_

IDLE

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 19-9. MIB Control Register (MIBC)

Table 19-13. MIBC Field Descriptions

Field Description

MIB_DIS

A read/write control bit. If set, the MIB logic halts and not update any MIB counters.

MIB_IDLE

A read-only status bit. If set the MIB block is not currently updating any MIB counters.

29–0 Reserved.

19.4.10 Receive Control Register (RCR)

RCR controls the operational mode of the receive block and must be written only when ECR[ETHER_EN] is cleared (initialization time).

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Address: 0xFC03_0084

R 0

Reset 0

22 21

MAX_FL

1 1 0

Access: User read/write

18 17 16

1 1 1 0

R 0

Reset 0

FCE

0 0 0 0 0 0 0 0

Figure 19-10. Receive Control Register (RCR)

BC_

REJ

3 2

PROM

MII_

MODE

1 0

DRT LOOP

0 0 0 0 1

Table 19-14. RCR Field Descriptions

Field Description

31–27

26–16

MAX_FL

15–6

FCE

Reserved, must be cleared.

Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Receive frames longer than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame receive buffer descriptor.

The recommended default value to be programmed is 1518 or 1522 if VLAN tags are supported.

Reserved, must be cleared.

Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame detection, the transmitter stops transmitting data frames for a given duration.

BC_REJ

LOOP

Broadcast frame reject. If asserted, frames with DA (destination address) equal to FFFF_FFFF_FFFF are rejected unless the PROM bit is set. If BC_REJ and PROM are set, frames with broadcast DA are accepted and the M

(MISS) is set in the receive buffer descriptor.

Promiscuous mode. All frames are accepted regardless of address matching.

PROM

MII_MODE

Media independent interface mode. Selects the external interface mode for transmit and receive blocks.

0 7-wire mode (used only for serial 10 Mbps)

1 MII mode

DRT

Disable receive on transmit.

0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode).

1 Disable reception of frames while transmitting (normally used for half duplex mode).

Internal loopback. If set, transmitted frames are looped back internal to the device and transmit output signals are not asserted. The internal bus clock substitutes for the FEC_TXCLK when LOOP is asserted. DRT must be set to

0 when setting LOOP.

19.4.11 Transmit Control Register (TCR)

TCR is read/write and configures the transmit block. This register is cleared at system reset. Bits 2 and 1 must be modified only when ECR[ETHER_EN] is cleared.

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Address: 0xFC03_00C4 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4 3

RFC_

PAUSE TFC_

PAUSE

2 1 0

FDEN HBC GTS

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 19-11. Transmit Control Register (TCR)

Table 19-15. TCR Field Descriptions

Field Description

31–5 Reserved, must be cleared.

RFC_PAUSE

Receive frame control pause. This read-only status bit is asserted when a full duplex flow control pause frame is received and the transmitter pauses for the duration defined in this pause frame. This bit automatically clears when the pause duration is complete.

TFC_PAUSE

Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC stops transmission of data frames after the current transmission is complete. At this time, GRA interrupt in the EIR register is asserted. With transmission of data frames stopped, MAC transmits a MAC Control PAUSE frame.

Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If the transmitter pauses due to user assertion of GTS or reception of a PAUSE frame, the MAC may continue transmitting a MAC Control

PAUSE frame.

FDEN

HBC

Full duplex enable. If set, frames transmit independent of carrier sense and collision inputs. This bit should only be modified when ECR[ETHER_EN] is cleared.

Heartbeat control. If set, the heartbeat check performs following end of transmission and the HB bit in the status register is set if the collision input does not assert within the heartbeat window. This bit should only be modified when ECR[ETHER_EN] is cleared.

GTS

Graceful transmit stop. When this bit is set, MAC stops transmission after any frame currently transmitted is complete and GRA interrupt in the EIR register is asserted. If frame transmission is not currently underway, the

GRA interrupt is asserted immediately. After transmission finishes, clear GTS to restart. The next frame in the transmit FIFO is then transmitted. If an early collision occurs during transmission when GTS is set, transmission stops after the collision. The frame is transmitted again after GTS is cleared. There may be old frames in the transmit FIFO that transmit when GTS is reasserted. To avoid this, clear ECR[ETHER_EN] following the GRA interrupt.

19.4.12 Physical Address Lower Register (PALR)

PALR contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address recognition process to compare with the DA (destination address) field of receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte source address field when transmitting

PAUSE frames. This register is not reset and you must initialize it.

Address: 0xFC03_00E4 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PADDR1

Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

Figure 19-12. Physical Address Lower Register (PALR)

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Table 19-16. PALR Field Descriptions

Field Description

31–0

PADDR1

Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact match and the source address field in PAUSE frames.

19.4.13 Physical Address Upper Register (PAUR)

PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address recognition process to compare with the DA (destination address) field of receive frames with an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte Source Address field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for transmission of PAUSE frames. The upper 16 bits of this register are not reset and you must initialize it.

Address: 0xFC03_00E8 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PADDR2

TYPE

Reset — — — — — — — — — — — — — — — — 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0

Figure 19-13. Physical Address Upper Register (PAUR)

Table 19-17. PAUR Field Descriptions

Field Description

31–16

PADDR2

Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames.

15–0

TYPE

Type field in PAUSE frames. These 16 read-only bits are a constant value of 0x8808.

19.4.14 Opcode/Pause Duration Register (OPD)

The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode field is a constant value, 0x0001. When another node detects a PAUSE frame, that node pauses transmission for the duration specified in the pause duration field. The lower 16 bits of this register are not reset and you must initialize them.

Address: 0xFC03_00EC Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R OPCODE

PAUSE_DUR

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 — — — — — — — — — — — — — — — —

Figure 19-14. Opcode/Pause Duration Register (OPD)

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Table 19-18. OPD Field Descriptions

Field Description

31–16

OPCODE

Opcode field used in PAUSE frames. These read-only bits are a constant, 0x0001.

15–0

PAUSE_DUR

Pause Duration field used in PAUSE frames.

19.4.15 Descriptor Individual Upper Address Register (IAUR)

IAUR contains the upper 32 bits of the 64-bit individual address hash table. The address recognition process uses this table to check for a possible match with the destination address (DA) field of receive frames with an individual DA. This register is not reset and you must initialize it.

Address: 0xFC03_0118 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IADDR1

Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

Figure 19-15. Descriptor Individual Upper Address Register (IAUR)

Table 19-19. IAUR Field Descriptions

Field Description

31–0

IADDR1

The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.

19.4.16 Descriptor Individual Lower Address Register (IALR)

IALR contains the lower 32 bits of the 64-bit individual address hash table. The address recognition process uses this table to check for a possible match with the DA field of receive frames with an individual

DA. This register is not reset and you must initialize it.

Address: 0xFC03_011C Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IADDR2

Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

Figure 19-16. Descriptor Individual Lower Address Register (IALR)

Table 19-20. IALR Field Descriptions

Field Description

31–0

IADDR2

The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.

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19.4.17 Descriptor Group Upper Address Register (GAUR)

GAUR contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. You must initialize this register.

Address: 0xFC03_0120 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GADDR1

Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

Figure 19-17. Descriptor Group Upper Address Register (GAUR)

Table 19-21. GAUR Field Descriptions

Field Description

31–0

GADDR1

The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.

19.4.18 Descriptor Group Lower Address Register (GALR)

GALR contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. You must initialize this register.

Address: 0xFC03_0124 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GADDR2

Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

Figure 19-18. Descriptor Group Lower Address Register (GALR)

Table 19-22. GALR Field Descriptions

Field Description

31–0

GADDR2

The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.

19.4.19 Transmit FIFO Watermark Register (TFWR)

The TFWR controls the amount of data required in the transmit FIFO before transmission of a frame can begin. This allows you to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access latency (TFWR = 11) due to contention for the system bus. Setting the watermark to a high value minimizes the risk of transmit FIFO underrun due to contention for the system bus. The byte counts associated with the TFWR field may need to be modified to match a given system requirement (worst case bus access latency by the transmit data DMA channel).

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Address: 0xFC03_0144 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TFWR

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 19-19. Transmit FIFO Watermark Register (TFWR)

Table 19-23. TFWR Field Descriptions

Field Description

31–2 Reserved, must be cleared.

1–0

TFWR

Number of bytes written to transmit FIFO before transmission of a frame begins

00 64 bytes written

01 64 bytes written

10 128 bytes written

11 192 bytes written

19.4.20 FIFO Receive Bound Register (FRBR)

FRBR indicates the upper address bound of the FIFO RAM. Drivers can use this value, along with the

FRSR, to appropriately divide the available FIFO RAM between the transmit and receive data paths.

Address: 0xFC03_014C Access: User read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R_BOUND 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

Figure 19-20. FIFO Receive Bound Register (FRBR)

Table 19-24. FRBR Field Descriptions

Field Description

31–10 Reserved, read as 0 (except bit 10, which is read as 1).

9–2

R_BOUND

Read-only. Highest valid FIFO RAM address.

1–0 Reserved, read as 0.

19.4.21 FIFO Receive Start Register (FRSR)

FRSR indicates the starting address of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed into the FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive.

Hardware initializes the FRSR register at reset. FRSR only needs to be written to change the default value.

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Address: 0xFC03_0150 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

R_FSTART

0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0

Figure 19-21. FIFO Receive Start Register (FRSR)

Table 19-25. FRSR Field Descriptions

Field Description

31–11 Reserved, must be cleared.

10 Reserved, must be set.

9–2

R_FSTART

Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs. For proper operation, ensure that R_FSTART is set to 0x48 or greater.

1–0 Reserved, must be cleared.

19.4.22 Receive Descriptor Ring Start Register (ERDSR)

ERDSR points to the start of the circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16).

This register is not reset and must be initialized prior to operation.

Address: 0xFC03_0180 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R_DES_START

0 0

Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

Figure 19-22. Ethernet Receive Descriptor Ring Start Register (ERDSR)

Table 19-26. ERDSR Field Descriptions

Field Description

31–2

R_DES_START

Pointer to start of receive buffer descriptor queue.

1–0 Reserved, must be cleared.

19.4.23 Transmit Buffer Descriptor Ring Start Registers (ETSDR)

ETSDR provides a pointer to the start of the circular transmit buffer descriptor queue in external memory.

This pointer must be 32-bit aligned; however, it is recommended it be made 128-bit aligned (evenly divisible by 16). You should write zeros to bits 1 and 0. Hardware ignores non-zero values in these two bit positions.

This register is undefined at reset and must be initialized prior to operation.

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Address: 0xFC03_0184 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

X_DES_START

0 0

Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

Figure 19-23. Transmit Buffer Descriptor Ring Start Register (ETDSR)

Table 19-27. ETDSR Field Descriptions

Field Description

31–2

X_DES_START

Pointer to start of transmit buffer descriptor queue.

1–0 Reserved, must be cleared.

19.4.24 Receive Buffer Size Register (EMRBR)

The EMRBR is a user-programmable register that dictates the maximum size of all receive buffers. This value should take into consideration that the receive CRC is always written into the last receive buffer. To allow one maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger. To properly align the buffer, EMRBR must be evenly divisible by 16. To ensure this, bits 3–0 are forced low.

To minimize bus utilization (descriptor fetches), it is recommended that EMRBR be greater than or equal to 256 bytes.

The EMRBR register is undefined at reset and must be initialized by the user.

Address: 0xFC03_0188 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R_BUF_SIZE

0 0 0 0

Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

Figure 19-24. Receive Buffer Size Register (EMRBR)

Table 19-28. EMRBR Field Descriptions

Field Description

31–11 Reserved, must be cleared.

10–4

R_BUF_SIZE

Maximum size of receive buffer size in bytes. To minimize bus utilization (descriptor fetches), set this field to 256 bytes (0x10) or larger.

0x10 256 + 15 bytes (minimum size recommended)

0x11 272 + 15 bytes

...

0x7F 2032 + 15 bytes. The FEC writes up to 2047 bytes in the receive buffer. If data larger than 2047 is received, the FEC truncates it and shows 0x7FF in the receive descriptor

3–0 Reserved, must be cleared.

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19.5 Functional Description

This section describes the operation of the FEC, beginning with the buffer descriptors, the hardware and software initialization sequence, then the software (Ethernet driver) interface for transmitting and receiving frames.

Following the software initialization and operation sections are sections providing a detailed description of the functions of the FEC.

19.5.1 Buffer Descriptors

This section provides a description of the operation of the driver/DMA via the buffer descriptors. It is followed by a detailed description of the receive and transmit descriptor fields.

19.5.1.1

Driver/DMA Operation with Buffer Descriptors

The data for the FEC frames resides in one or more memory buffers external to the FEC. Associated with each buffer is a buffer descriptor (BD), which contains a starting address (32-bit aligned pointer), data length, and status/control information (which contains the current state for the buffer). To permit maximum user flexibility, the BDs are also located in external memory and are read by the FEC DMA engine.

Software produces buffers by allocating/initializing memory and initializing buffer descriptors. Setting the

RxBD[E] or TxBD[R] bit produces the buffer. Software writing to TDAR or RDAR tells the FEC that a buffer is placed in external memory for the transmit or receive data traffic, respectively. The hardware reads the BDs and consumes the buffers after they have been produced. After the data DMA is complete and the DMA engine writes the buffer descriptor status bits, hardware clears RxBD[E] or TxBD[R] to signal the buffer has been consumed. Software may poll the BDs to detect when the buffers are consumed or may rely on the buffer/frame interrupts. The driver may process these buffers, and they can return to the free list.

The ECR[ETHER_EN] bit operates as a reset to the BD/DMA logic. When ECR[ETHER_EN] is cleared, the DMA engine BD pointers are reset to point to the starting transmit and receive BDs. The buffer descriptors are not initialized by hardware during reset. At least one transmit and receive buffer descriptor must be initialized by software before ECR[ETHER_EN] is set.

The buffer descriptors operate as two separate rings. ERDSR defines the starting address for receive BDs and ETDSR defines the starting address for transmit BDs. The wrap (W) bit defines the last buffer descriptor in each ring. When W is set, the next descriptor in the ring is at the location pointed to by

ERDSR and ETDSR for the receive and transmit rings, respectively. Buffer descriptor rings must start on a 32-bit boundary; however, it is recommended they are made 128-bit aligned.

19.5.1.1.1

Driver/DMA Operation with Transmit BDs

Typically, a transmit frame is divided between multiple buffers. An example is to have an application payload in one buffer, TCP header in a second buffer, IP header in a third buffer, and Ethernet/IEEE 802.3 header in a fouth buffer. The Ethernet MAC does not prepend the Ethernet header (destination address, source address, length/type field(s)), so the driver must provide this in one of the transmit buffers. The

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Ethernet MAC can append the Ethernet CRC to the frame. TxBD[TC], which must be set by the driver, determines whether the MAC or driver appends the CRC.

The driver (TxBD software producer) should set up Tx BDs so a complete transmit frame is given to the hardware at once. If a transmit frame consists of three buffers, the BDs should be initialized with pointer, length, and control (W, L, TC, ABC) and then the TxBD[R] bit should be set in reverse order (third, second, then first BD) to ensure that the complete frame is ready in memory before the DMA begins. If the TxBDs are set up in order, the DMA controller could DMA the first BD before the second was made available, potentially causing a transmit FIFO underrun.

In the FEC, the driver notifies the DMA that new transmit frame(s) are available by writing to TDAR.

When this register is written to (data value is not significant) the FEC, RISC tells the DMA to read the next transmit BD in the ring. After started, the RISC + DMA continues to read and interpret transmit BDs in order and DMA the associated buffers until a transmit BD is encountered with the R bit cleared. At this point, the FEC polls this BD one more time. If the R bit is cleared the second time, RISC stops the transmit descriptor read process until software sets up another transmit frame and writes to TDAR.

When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the R bit, indicating that the hardware consumer is finished with the buffer.

19.5.1.1.2

Driver/DMA Operation with Receive BDs

Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore, the driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to the EMRBR register.

The driver (RxBD software producer) should set up some number of empty buffers for the Ethernet by initializing the address field and the E and W bits of the associated receive BDs. The hardware (receive

DMA) consumes these buffers by filling them with data as frames are received and clearing the E bit and writing to the L bit (1 indicates last buffer in frame), the frame status bits (if L is set), and the length field.

If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the frame. For non-last buffers, the length field in the receive BD is written by the DMA (at the same time the E bit is cleared) with the default receive buffer length value. For end-of-frame buffers, the receive BD is written with L set and information written to the status bits (M, BC, MC, LG, NO, CR, OV, TR). Some of the status bits are error indicators which, if set, indicate the receive frame should be discarded and not given to higher layers. The frame status/length information is written into the receive FIFO following the end of the frame

(as a single 32-bit word) by the receive logic. The length field for the end of frame buffer is written with the length of the entire frame, not only the length of the last buffer.

For simplicity, the driver may assign a large enough default receive buffer length to contain an entire frame, keeping in mind that a malfunction on the network or out-of-spec implementation could result in giant frames. Frames of 2K (2048) bytes or larger are truncated by the FEC at 2047 bytes so software never sees a receive frame larger than 2047 bytes.

Similar to transmit, the FEC polls the receive descriptor ring after the driver sets up receive BDs and writes to the RDAR register. As frames are received, the FEC fills receive buffers and updates the associated BDs, then reads the next BD in the receive descriptor ring. If the FEC reads a receive BD and finds the E bit

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cleared, it polls this BD once more. If RxBD[E] is clear a second time, FEC stops reading receive BDs until the driver writes to RDAR.

19.5.1.2

Ethernet Receive Buffer Descriptor (RxBD)

In the RxBD, the user initializes the E and W bits in the first longword and the pointer in the second longword. When the buffer has been DMA’d, the Ethernet controller modifies the E, L, M, BC, MC, LG,

NO, CR, OV, and TR bits and writes the length of the used portion of the buffer in the first longword. The

M, BC, MC, LG, NO, CR, OV, and TR bits in the first longword of the buffer descriptor are only modified by the Ethernet controller when the L bit is set.

15 14 13 12 11

Offset + 0 E RO1 W RO2 L

Offset + 2

Offset + 4

Offset + 6

—

7 6 5 4 3 2 1 0

BC MC LG NO — CR OV TR

Data Length

Rx Data Buffer Pointer - A[31:16]

Rx Data Buffer Pointer - A[15:0]

Figure 19-25. Receive Buffer Descriptor (RxBD)

Word

Offset + 0

Field

RO1

RO2

10–9

Table 19-29. Receive Buffer Descriptor Field Definitions

Description

Empty. Written by the FEC (=0) and user (=1).

0 The data buffer associated with this BD is filled with received data, or data reception has aborted due to an error condition. The status and length fields have been updated as required.

1 The data buffer associated with this BD is empty, or reception is currently in progress.

Receive software ownership. This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its value affect hardware.

Wrap. Written by user.

0 The next buffer descriptor is found in the consecutive location

1 The next buffer descriptor is found at the location defined in ERDSR.

Receive software ownership. This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its value affect hardware.

Last in frame. Written by the FEC.

0 The buffer is not the last in a frame.

1 The buffer is the last in a frame.

Reserved, must be cleared.

Miss. Written by the FEC. This bit is set by the FEC for frames accepted in promiscuous mode, but flagged as a miss by the internal address recognition. Therefore, while in promiscuous mode, you can use the M-bit to quickly determine whether the frame was destined to this station. This bit is valid only if the L-bit is set and the PROM bit is set.

0 The frame was received because of an address recognition hit.

1 The frame was received because of promiscuous mode.

Set if the DA is broadcast (FFFF_FFFF_FFFF).

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Table 19-29. Receive Buffer Descriptor Field Definitions (continued)

Word Field Description

Offset + 0

Set if the DA is multicast and not BC.

Rx frame length violation. Written by the FEC. A frame length greater than RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The receive data is not altered in any way unless the length exceeds 2047 bytes.

Receive non-octet aligned frame. Written by the FEC. A frame that contained a number of bits not divisible by 8 was received, and the CRC check that occurred at the preceding byte boundary generated an error. This bit is valid only if the L-bit is set. If this bit is set, the CR bit is not set.

Reserved, must be cleared.

Receive CRC error. Written by the FEC. This frame contains a CRC error and is an integral number of octets in length. This bit is valid only if the L-bit is set.

Offset + 0

Offset + 2

0ffset + 4

15–0

Data

Length

15–0

A[31:16]

Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M, LG, NO, CR, and CL lose their normal meaning and are zero. This bit is valid only if the L-bit is set.

Set if the receive frame is truncated (frame length > 2047 bytes). If the TR bit is set, the frame must be discarded and the other error bits must be ignored as they may be incorrect.

Data length. Written by the FEC. Data length is the number of octets written by the FEC into this

BD’s data buffer if L equals 0 (the value is equal to EMRBR), or the length of the frame including

CRC if L is set. It is written by the FEC once as the BD is closed.

RX data buffer pointer, bits [31:16]

Offset + 6 15–0

A[15:0]

RX data buffer pointer, bits [15:0]

The receive buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC. The Ethernet controller never modifies this value.

NOTE

When the software driver sets an E bit in one or more receive descriptors, the driver should follow with a write to RDAR.

19.5.1.3

Ethernet Transmit Buffer Descriptor (TxBD)

Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs.

The Ethernet controller confirms transmission by clearing the ready bit (TxBD[R]) when DMA of the buffer is complete. In the TxBD, the user initializes the R, W, L, and TC bits and the length (in bytes) in the first longword and the buffer pointer in the second longword.

The FEC clears the R bit when the buffer is transferred. Status bits for the buffer/frame are not included in the transmit buffer descriptors. Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See

Section 19.4.1, “MIB Block Counters Memory

Map,”

for more details.

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15 14 13 12 11

Offset + 0 R TO1 W TO2 L

Offset + 2

Offset + 4

Offset + 6

10 9 8

TC ABC —

—

Data Length

Tx Data Buffer Pointer - A[31:16]

Tx Data Buffer Pointer - A[15:0]

—

Figure 19-26. Transmit Buffer Descriptor (TxBD)

—

Table 19-30. Transmit Buffer Descriptor Field Definitions

Word Field Description

Offset + 0

TO1

Ready. Written by the FEC and you.

0 The data buffer associated with this BD is not ready for transmission. You are free to manipulate this BD or its associated data buffer. The FEC clears this bit after the buffer has been transmitted or after an error condition is encountered.

1 The data buffer, prepared for transmission by you, has not been transmitted or currently transmits.

You may write no fields of this BD after this bit is set.

Transmit software ownership. This field is reserved for software use. This read/write bit is not modified by hardware nor does its value affect hardware.

Wrap. Written by user.

0 The next buffer descriptor is found in the consecutive location

1 The next buffer descriptor is found at the location defined in ETDSR.

Transmit software ownership. This field is reserved for use by software. This read/write bit is not modified by hardware nor does its value affect hardware.

Offset + 0

Offset + 2

Offset + 4

TO2

ABC

8–0

15–0

Data

Length

15–0

A[31:16]

Last in frame. Written by user.

0 The buffer is not the last in the transmit frame

1 The buffer is the last in the transmit frame

Transmit CRC. Written by user (only valid if L is set).

0 End transmission immediately after the last data byte

1 Transmit the CRC sequence after the last data byte

Append bad CRC. Written by user (only valid if L is set).

0 No effect

1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value)

Reserved, must be cleared.

Data length, written by user.

Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modified by the FEC.

Tx data buffer pointer, bits [31:16]

Offset + 6 15–0

A[15:0]

Tx data buffer pointer, bits [15:0]

The transmit buffer pointer, containing the address of the associated data buffer, must always be evenly divisible by 4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.

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NOTE

After the software driver has set up the buffers for a frame, it should set up the corresponding BDs. The last step in setting up the BDs for a transmit frame is setting the R bit in the first BD for the frame. The driver must follow that with a write to TDAR that triggers the FEC to poll the next BD in the ring.

19.5.2 Initialization Sequence

This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC, and what locations you must initialize prior to enabling the FEC.

19.5.2.1

Hardware Controlled Initialization

In the FEC, hardware resets registers and control logic that generate interrupts. A hardware reset negates output signals and resets general configuration bits.

Other registers reset when the ECR[ETHER_EN] bit is cleared (which is accomplished by a hard reset or software to halt operation). By clearing ECR[ETHER_EN], configuration control registers such as the

TCR and RCR are not reset, but the entire data path is reset.

Table 19-31. ECR[ETHER_EN] De-Assertion Effect on FEC

Register/Machine

XMIT block

RECV block

DMA block

RDAR

TDAR

Descriptor Controller block

Reset Value

Transmission is aborted (bad CRC appended)

Receive activity is aborted

All DMA activity is terminated

Cleared

Halt operation

19.5.3 User Initialization (Prior to Setting ECR[ETHER_EN])

You need to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact values depend on the particular application. The sequence is not important.

Table 19-32

defines Ethernet MAC registers requiring initialization.

Table 19-32. User Initialization (Before ECR[ETHER_EN])

Description

Initialize EIMR

Clear EIR (write 0xFFFF_FFFF)

TFWR (optional)

IALR / IAUR

GAUR / GALR

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Table 19-32. User Initialization (Before ECR[ETHER_EN]) (continued)

Description

PALR / PAUR (only needed for full duplex flow control)

OPD (only needed for full duplex flow control)

RCR

TCR

MSCR (optional)

Clear MIB_RAM

Table 19-33

defines FEC FIFO/DMA registers that require initialization.

Table 19-33. FEC User Initialization (Before ECR[ETHER_EN])

Description

Initialize FRSR (optional)

Initialize EMRBR

Initialize ERDSR

Initialize ETDSR

Initialize (Empty) Transmit Descriptor ring

Initialize (Empty) Receive Descriptor ring

19.5.4 Microcontroller Initialization

In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted.

After the microcontroller initialization sequence is complete, hardware is ready for operation.

Table 19-34

shows microcontroller initialization operations.

Table 19-34. Microcontroller Initialization

Description

Initialize BackOff Random Number Seed

Activate Receiver

Activate Transmitter

Clear Transmit FIFO

Clear Receive FIFO

Initialize Transmit Ring Pointer

Initialize Receive Ring Pointer

Initialize FIFO Count Registers

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19.5.5 User Initialization (After Setting ECR[ETHER_EN])

After setting ECR[ETHER_EN], you can set up the buffer/frame descriptors and write to TDAR and

RDAR. Refer to

Section 19.5.1, “Buffer Descriptors,”

for more details.

19.5.6 Network Interface Options

The FEC supports an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps

Ethernet. The RCR[MII_MODE] bit select the interface mode. In MII mode (RCR[MII_MODE] set), there are 18 signals defined by the IEEE 802.3 standard and supported by the EMAC.

Table 19-35 shows

these signals.

Table 19-35. MII Mode

Signal Description

Transmit Clock

Transmit Enable

Transmit Data

Transmit Error

Collision

Carrier Sense

Receive Clock

Receive Data Valid

Receive Data

Receive Error

Management Data Clock

Management Data

Input/Output

EMAC pin

FEC_TXCLK

FEC_TXEN

FEC_TXD[3:0]

FEC_TXER

FEC_COL

FEC_CRS

FEC_RXCLK

FEC_RXDV

FEC_RXD[3:0]

FEC_RXER

FEC_MDC

FEC_MDIO

The 7-wire serial mode interface (RCR[MII_MODE] cleared) is generally referred to as AMD mode.

Table 19-36

shows the 7-wire mode connections to the external transceiver.

Table 19-36. 7-Wire Mode Configuration

EMAC Pin Signal description

Transmit Clock

Transmit Enable

Transmit Data

Collision

Receive Clock

FEC_ TXCLK

FEC_ TXEN

FEC_ TXD[0]

FEC_ COL

FEC_ RXCLK

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Table 19-36. 7-Wire Mode Configuration (continued)

EMAC Pin Signal description

Receive Data Valid

Receive Data

FEC_ RXDV

FEC_ RXD[0]

19.5.7 FEC Frame Transmission

The Ethernet transmitter is designed to work with almost no intervention from software. After

ECR[ETHER_EN] is set and data appears in the transmit FIFO, the Ethernet MAC can transmit onto the network. The Ethernet controller transmits bytes least significant bit (lsb) first.

When the transmit FIFO fills to the watermark (defined by TFWR), MAC transmit logic asserts

FEC_TXEN and starts transmitting the preamble (PA) sequence, the start frame delimiter (SFD), and then the frame information from the FIFO. However, the controller defers the transmission if the network is busy (FEC_CRS is asserted). Before transmitting, the controller waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit times. If so, transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). See

Section 19.5.15.1,

“Transmission Errors,”

for more details.

If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so they do not have to be retrieved from system memory in case of a collision. This improves bus utilization and latency in case immediate retransmission is necessary.

When all the frame data is transmitted, FCS (frame check sequence) or 32-bit cyclic redundancy check

(CRC) bytes are appended if the TC bit is set in the transmit frame control word. If the ABC bit is set in the transmit frame control word, a bad CRC is appended to the frame data regardless of the TC bit value.

Following the transmission of the CRC, the Ethernet controller writes the frame status information to the

MIB block. Transmit logic automatically pads short frames (if the TC bit in the transmit buffer descriptor for the end of frame buffer is set).

Settings in the EIMR determine interrupts generated to the buffer (TXB) and frame (TFINT).

The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If the transmit frame length exceeds MAX_FL bytes, BABT interrupt is asserted. However, the entire frame is transmitted (no truncation).

To pause transmission, set TCR[GTS] (graceful transmit stop). The FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues transmission until the current frame finishes or terminates with a collision. After the transmitter has stopped, the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes transmission with the next frame.

19.5.7.1

Duplicate Frame Transmission

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Fast Ethernet Controller (FEC)

processed internally (as a result of a wrap). As the FEC nears the end of the transmission of one frame, it begins to DMA the data for the next frame. To remain one BD ahead of the DMA, it also fetches the TxBD for the next frame. It is possible that the FEC fetches from memory a BD that has already been processed but not yet written back (it is read a second time with the R bit remains set). In this case, the data is fetched and transmitted again.

Using at least three TxBDs fixes this problem for large frames, but not for small frames. To ensure correct operation for large or small frames, one of the following must be true:

• The FEC software driver ensures that there is always at least one TxBD with the ready bit cleared.

• Every frame uses more than one TxBD and every TxBD but the last is written back immediately after the data is fetched.

• The FEC software driver ensures a minimum frame size, n. The minimum number of TxBDs is then (Tx FIFO Size

÷ (n + 4)) rounded up to the nearest integer (though the result cannot be less than three). The default Tx FIFO size is 192 bytes; this size is programmable.

19.5.8 FEC Frame Reception

The FEC receiver works with almost no intervention from the host and can perform address recognition,

CRC checking, short frame checking, and maximum frame length checking. The Ethernet controller receives serial data lsb first.

When the driver enables the FEC receiver by setting ECR[ETHER_EN], it immediately starts processing receive frames. When FEC_RXDV is asserted, the receiver first checks for a valid PA/SFD header. If the

PA/SFD is valid, it is stripped and the receiver processes the frame. If a valid PA/SFD is not found, the frame is ignored.

In serial mode, the first 16 bit times of RX_D0 following assertion of FEC_RXDV are ignored. Following the first 16 bit times, the data sequence is checked for alternating 1/0s. If a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is detected, the PA/SFD sequence is complete.

In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur, but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.

After the first 6 bytes of the frame are received, the FEC performs address recognition on the frame.

After a collision window (64 bytes) of data is received and if address recognition has not rejected the frame, the receive FIFO signals the frame is accepted and may be passed on to the DMA. If the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified to reject the frame.

Therefore, no collision fragments are presented to you except late collisions, which indicate serious LAN problems.

During reception, the Ethernet controller checks for various error conditions and after the entire frame is written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the

M, BC, MC, LG, NO, CR, OV, and TR status bits, and the frame length. See

Section 19.5.15.2, “Reception

Errors,”

for more details.

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Receive buffer (RXB) and frame interrupts (RFINT) may be generated if enabled by the EIMR register. A receive error interrupt is a babbling receiver error (BABR). Receive frames are not truncated if they exceed the max frame length (MAX_FL); however, the BABR interrupt occurs and the LG bit in the receive buffer descriptor (RxBD) is set. See

Section 19.5.1.2, “Ethernet Receive Buffer Descriptor (RxBD),”

for more details.

When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame is received and is in memory. The

Ethernet controller then waits for a new frame.

19.5.9 Ethernet Address Recognition

The FEC filters the received frames based on destination address (DA) type — individual (unicast), group

(multicast), or broadcast (all-ones group address). The difference between an individual address and a group address is determined by the I/G bit in the destination address field. A flowchart for address recognition on received frames appears in the figures below.

Address recognition is accomplished through the use of the receive block and microcode running on the microcontroller. The flowchart shown in

Figure 19-27

illustrates the address recognition decisions made by the receive block, while

Figure 19-28

illustrates the decisions made by the microcontroller.

If the DA is a broadcast address and broadcast reject (RCR[BC_REJ]) is cleared, then the frame is

accepted unconditionally, as shown in Figure 19-27 . Otherwise, if the DA is not a broadcast address, then

the microcontroller runs the address recognition subroutine, as shown in Figure 19-28 .

If the DA is a group (multicast) address and flow control is disabled, then the microcontroller performs a group hash table lookup using the 64-entry hash table programmed in GAUR and GALR. If a hash match occurs, the receiver accepts the frame.

If flow control is enabled, the microcontroller does an exact address match check between the DA and the designated PAUSE DA (01:80:C2:00:00:01). If the receive block determines the received frame is a valid

PAUSE frame, the frame is rejected. The receiver detects a PAUSE frame with the DA field set to the designated PAUSE DA or the unicast physical address.

If the DA is the individual (unicast) address, the microcontroller performs an individual exact match comparison between the DA and 48-bit physical address that you program in the PALR and PAUR registers. If an exact match occurs, the frame is accepted; otherwise, the microcontroller does an individual hash table lookup using the 64-entry hash table programmed in registers, IAUR and IALR. In the case of an individual hash match, the frame is accepted. Again, the receiver accepts or rejects the frame based on

PAUSE frame detection, shown in Figure 19-27 .

If neither a hash match (group or individual) nor an exact match (group or individual) occur, and if promiscuous mode is enabled (RCR[PROM] set), the frame is accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame is rejected.

Similarly, if the DA is a broadcast address, broadcast reject (RCR[BC_REJ]) is asserted, and promiscuous mode is enabled, the frame is accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame is rejected.

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Fast Ethernet Controller (FEC)

In general, when a frame is rejected, it is flushed from the FIFO.

Accept/Reject

Frame

True

Broadcast Addr

False

Receive

Address

Recognition

False

Receive Frame

Set BC bit in RCV BD

BC_REJ = 1

True

False

Reject Frame

Flush from FIFO

Notes:

BC_REJ - field in RCR register (BroadCast REJect)

PROM - field in RCR register (PROMiscous mode)

Pause Frame - valid PAUSE frame received

PROM = 1

True

Hash Match

True

False

Exact Match

Receive Frame

Set MC bit in RCV BD if multicast

True

False

Pause Frame

False

True

Reject Frame

Flush from FIFO

Receive Frame

Set M (Miss) bit in Rcv BD

Set MC bit in Rcv BD if multicast

Set BC bit in Rcv BD if broadcast

Figure 19-27. Ethernet Address Recognition—Receive Block Decisions

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Fast Ethernet Controller (FEC)

Receive Address

Recognition

Group

I/G Address

FCE

False

True

False

Pause Address

True

Receive Frame

Hash Search

Group Table

Individual

False

Hash Search

Individual Table

Exact Match

True

Receive Frame

Match

False

True

Receive Frame

True

Match

False

Reject Frame

Flush from FIFO

Receive Frame

Notes:

FCE - field in RCR register (flow control enable)

Reject Frame

Flush from FIFO

I/G - Individual/Group bit in destination address (lsb in first byte received in MAC frame)

Figure 19-28. Ethernet Address Recognition—Microcode Decisions

19.5.10 Hash Algorithm

The hash table algorithm used in the group and individual hash filtering operates as follows. The 48-bit destination address is mapped into one of 64 bits, represented by 64 bits stored in GAUR, GALR (group address hash match), or IAUR, IALR (individual address hash match). This mapping is performed by passing the 48-bit address through the on-chip 32-bit CRC generator and selecting the six most significant bits of the CRC-encoded result to generate a number between 0 and 63. The msb of the CRC result selects

GAUR (msb = 1) or GALR (msb = 0). The five least significant bits of the hash result select the bit within the selected register. If the CRC generator selects a bit set in the hash table, the frame is accepted; otherwise, it is rejected.

For example, if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses.

The effectiveness of the hash table declines as the number of addresses increases.

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Fast Ethernet Controller (FEC)

The user must initialize the hash table registers. Use this CRC32 polynomial to compute the hash:

Eqn. 19-2

+ X

+ X + 1

Table 19-37

contains example destination addresses and corresponding hash values.

Table 19-37. Destination Address to 6-Bit Hash

48-bit DA

65FF_FFFF_FFFF

55FF_FFFF_FFFF

15FF_FFFF_FFFF

35FF_FFFF_FFFF

B5FF_FFFF_FFFF

95FF_FFFF_FFFF

D5FF_FFFF_FFFF

F5FF_FFFF_FFFF

DBFF_FFFF_FFFF

FBFF_FFFF_FFFF

BBFF_FFFF_FFFF

8BFF_FFFF_FFFF

0BFF_FFFF_FFFF

3BFF_FFFF_FFFF

7BFF_FFFF_FFFF

5BFF_FFFF_FFFF

27FF_FFFF_FFFF

07FF_FFFF_FFFF

57FF_FFFF_FFFF

77FF_FFFF_FFFF

F7FF_FFFF_FFFF

C7FF_FFFF_FFFF

97FF_FFFF_FFFF

A7FF_FFFF_FFFF

99FF_FFFF_FFFF

B9FF_FFFF_FFFF

F9FF_FFFF_FFFF

C9FF_FFFF_FFFF

6-bit Hash

(in hex)

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0xC

0xD

0xE

0xF

0x8

0x9

0xA

0xB

0x4

0x5

0x6

0x7

0x0

0x1

0x2

0x3

Hash Decimal

Value

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BFFF_FFFF_FFFF

9FFF_FFFF_FFFF

DFFF_FFFF_FFFF

EFFF_FFFF_FFFF

93FF_FFFF_FFFF

B3FF_FFFF_FFFF

F3FF_FFFF_FFFF

D3FF_FFFF_FFFF

53FF_FFFF_FFFF

73FF_FFFF_FFFF

23FF_FFFF_FFFF

13FF_FFFF_FFFF

3DFF_FFFF_FFFF

0DFF_FFFF_FFFF

5DFF_FFFF_FFFF

7DFF_FFFF_FFFF

59FF_FFFF_FFFF

79FF_FFFF_FFFF

29FF_FFFF_FFFF

19FF_FFFF_FFFF

D1FF_FFFF_FFFF

F1FF_FFFF_FFFF

B1FF_FFFF_FFFF

91FF_FFFF_FFFF

11FF_FFFF_FFFF

31FF_FFFF_FFFF

71FF_FFFF_FFFF

51FF_FFFF_FFFF

7FFF_FFFF_FFFF

4FFF_FFFF_FFFF

1FFF_FFFF_FFFF

3FFF_FFFF_FFFF

Table 19-37. Destination Address to 6-Bit Hash (continued)

48-bit DA

6-bit Hash

(in hex)

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

Hash Decimal

Value

Fast Ethernet Controller (FEC)

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Fast Ethernet Controller (FEC)

Table 19-37. Destination Address to 6-Bit Hash (continued)

48-bit DA

FDFF_FFFF_FFFF

DDFF_FFFF_FFFF

9DFF_FFFF_FFFF

BDFF_FFFF_FFFF

6-bit Hash

(in hex)

0x3C

0x3D

0x3E

0x3F

Hash Decimal

Value

19.5.11 Full Duplex Flow Control

Full-duplex flow control allows you to transmit pause frames and to detect received pause frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.

To enable PAUSE frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] set) with flow control (RCR[FCE] set). The FEC detects a pause frame when the fields of the incoming frame match the

pause frame specifications, as shown in Table 19-38

. In addition, the receive status associated with the frame should indicate that the frame is valid.

Table 19-38. PAUSE Frame Field Specification

48-bit Destination Address

0x0180_C200_0001 or Physical Address

48-bit Source Address

Any

16-bit Type

0x8808

16-bit Opcode

0x0001

16-bit PAUSE Duration

0x0000 – 0xFFFF

The receiver and microcontroller modules perform PAUSE frame detection. The microcontroller runs an address recognition subroutine to detect the specified pause frame destination address, while the receiver detects the type and opcode pause frame fields. On detection of a pause frame, TCR[GTS] is set by the

FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer begins to increment. The pause timer uses the transmit backoff timer hardware for tracking the appropriate collision backoff time in half-duplex mode. The pause timer increments once every slot time, until

OPD[PAUSE_DUR] slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is cleared allowing MAC data frame transmission to resume. The receive flow control pause status bit

(TCR[RFC_PAUSE]) is set while the transmitter pauses due to reception of a pause frame.

To transmit a pause frame, the FEC must operate in full-duplex mode and you must set flow control pause

(TCR[TFC_PAUSE]). After TCR[TFC_PAUSE] is set, the transmitter sets TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts and the pause frame is transmitted. TCR[TFC_PAUSE,GTS] are then cleared internally.

You must specify the desired pause duration in the OPD register.

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Fast Ethernet Controller (FEC)

When the transmitter pauses due to receiver/microcontroller pause frame detection, TCR[TFC_PAUSE] may remain set and cause the transmission of a single pause frame. In this case, the EIR[GRA] interrupt is not asserted.

19.5.12 Inter-Packet Gap (IPG) Time

The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a transmission or after the backoff algorithm completes, the transmitter waits for carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times, it is ignored and a collision occurs.

The receiver accepts back-to-back frames with a minimum spacing of at least 28 bit times. If an inter-packet gap between receive frames is less than 28 bit times, the receiver may discard the following frame.

19.5.13 Collision Managing

If a collision occurs during frame transmission, the Ethernet controller continues the transmission for at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the collision occurs during the preamble sequence, a JAM pattern is sent after the end of the preamble sequence.

If a collision occurs within 512 bit times (one slot time), the retry process is initiated. The transmitter waits a random number of slot times. If a collision occurs after 512 bit times, then no retransmission is performed and the end of frame buffer is closed with a Late Collision (LC) error indication.

19.5.14 MII Internal and External Loopback

Internal and external loopback are supported by the Ethernet controller. In loopback mode, both of the

FIFOs are used and the FEC actually operates in a full-duplex fashion. Internal and external loopback are configured using combinations of the RCR[LOOP, DRT] and TCR[FDEN] bits.

Set FDEN for internal and external loopback.

For internal loopback, set RCR[LOOP] and clear RCR[DRT]. FEC_TXEN and FEC_TXER do not assert during internal loopback. During internal loopback, the transmit/receive data rate is higher than in normal operation because the transmit and receive blocks use the internal bus clock instead of the clocks from the external transceiver. This causes an increase in the required system bus bandwidth for transmit and receive data being DMA’d to/from external memory. It may be necessary to pace the frames on the transmit side and/or limit the size of the frames to prevent transmit FIFO underruns and receive FIFO overflows.

For external loopback, clear RCR[LOOP] and RCR[DRT], and configure the external transceiver for loopback.

19.5.15 Ethernet Error-Managing Procedure

The Ethernet controller reports frame reception and transmission error conditions using the MIB block counters, the FEC RxBDs, and the EIR register.

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Fast Ethernet Controller (FEC)

19.5.15.1 Transmission Errors

19.5.15.1.1

Transmitter Underrun

If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame are then flushed and closed, and EIR[UN] is set. The FEC then continues to the next transmit buffer descriptor and begin transmitting the next frame. The UN interrupt is asserted if enabled in the EIMR register.

19.5.15.1.2

Retransmission Attempts Limit Expired

When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and EIR[RL] is set. The FEC then continues to the next transmit buffer descriptor and begins transmitting the next frame. The RL interrupt is asserted if enabled in the EIMR register.

19.5.15.1.3

Late Collision

When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and EIR[LC] is set. The FEC then continues to the next transmit buffer descriptor and begin transmitting the next frame. The LC interrupt is asserted if enabled in the EIMR register.

19.5.15.1.4

Heartbeat

Some transceivers have a self-test feature called heartbeat or signal quality error. To signify a good self-test, the transceiver indicates a collision to the FEC within four microseconds after completion of a frame transmitted by the Ethernet controller. This indication of a collision does not imply a real collision error on the network, but is rather an indication that the transceiver continues to function properly. This is the heartbeat condition.

If TCR[HBC] is set and the heartbeat condition is not detected by the FEC after a frame transmission, a heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets EIR[HB], and generates the

HBERR interrupt if it is enabled.

19.5.15.2 Reception Errors

19.5.15.2.1

Overrun Error

If the receive block has data to put into the receive FIFO and the receive FIFO is full, FEC sets RxBD[OV].

All subsequent data in the frame is discarded and subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and space is made available. At this point the receive frame/status word is written into the FIFO with the OV bit set. The driver must discard this frame.

19.5.15.2.2

Non-Octet Error (Dribbling Bits)

The Ethernet controller manages up to seven dribbling bits when the receive frame terminates past an non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error, the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, no error is reported.

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Fast Ethernet Controller (FEC)

19.5.15.2.3

CRC Error

When a CRC error occurs with no dribble bits, FEC closes the buffer and sets RxBD[CR]. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required.

19.5.15.2.4

Frame Length Violation

When the receive frame length exceeds MAX_FL bytes the BABR interrupt is generated, and RxBD[LG] is set. The frame is not truncated unless the frame length exceeds 2047 bytes.

19.5.15.2.5

Truncation

When the receive frame length exceeds 2047 bytes, frame is truncated and RxBD[TR] is set.

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Chapter 20 Watchdog Timer Module

20.1 Introduction

The watchdog timer (WDT) is a 16-bit timer used to help software recover from runaway code. The watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on underflow.

To prevent a reset, software must periodically restart the countdown by servicing the watchdog.

20.1.1 Low-Power Mode Operation

This subsection describes the operation of the watchdog module in low-power modes and halted mode of

operation (by issuing a HALT instruction). Low-power modes are described in Chapter 8, “Power

Management.”

Table 20-1 shows the watchdog module operation in the low-power modes, and shows how

this module may facilitate exit from each mode.

Table 20-1. Watchdog Module Operation in Low-power Modes

Low-power Mode

Wait

Doze

Stop

Watchdog Operation

Normal if WCR[WAIT] cleared, stopped otherwise

Normal if WCR[DOZE] cleared, stopped otherwise

Stopped

Mode Exit

Upon Watchdog reset

No, only via external interrupts

In wait mode, with the watchdog control register’s WAIT bit (WCR[WAIT]) set, watchdog timer operation stops. In wait mode with the WCR[WAIT] bit cleared, the watchdog timer continues to operate normally.

In doze mode with the WCR[DOZE] bit set, the watchdog timer module operation stops. In doze mode with the WCR[DOZE] bit cleared, the watchdog timer continues to operate normally. Watchdog timer operation stops in stop mode. When stop mode is exited, the watchdog timer continues to operate in its pre-stop mode state.

In halted mode (entered by issuing a HALT instruction or asserting BKPT) with the WCR[HALTED] bit set, watchdog timer module operation stops. When halted mode is exited, watchdog timer operation continues from the state it was in before entering halted mode, but any updates made in halted mode remain. If the WCR[HALTED] bit is cleared, the watchdog timer continues to operate normally after executing a HALT instruction. This is a debug feature available for the user

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20.1.2 Block Diagram

Internal Bus

16-bit WCNTR 16-bit WSR

Internal Bus

Clock

(f sys/2

)

Divide by

4096

16-bit Watchdog Counter

Count = 0

Reset

WAIT

DOZE

HALTED

16-bit WMR

Load Counter

Internal Bus

Figure 20-1. Watchdog Timer Block Diagram

20.2 Memory Map/Register Definition

This subsection describes the memory map and registers for the watchdog timer. Refer to Table 20-2

for an overview of the watchdog memory map.

NOTE

Longword accesses to any of the watchdog timer registers result in a bus error. Only byte and word accesses are allowed.

Table 20-2. Watchdog Timer Module Memory Map

Address

Register

Width

(bits)

Access Reset Value Section/Page

Supervisor Only Access

0xFC08_C000 Watchdog Control Register (WCR)

0xFC08_C002 Watchdog Modulus Register (WMR)

Supervisor/User Access

R/W

0x000F

0xFFFF

20.2.1/20-3

20.2.2/20-4

0xFC08_C004 Watchdog Count Register (WCNTR) 16 R 0xFFFF

20.2.3/20-4

0xFC08_C006 Watchdog Service Register (WSR) 16 R/W 0x0000

20.2.4/20-5

Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect.

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20.2.1 Watchdog Control Register (WCR)

The 16-bit WCR configures watchdog timer operation.

Address: 0xFC08_C000

R 0

Reset 0

0 0 0 0 0 0 0 0

Figure 20-2. Watchdog Control Register (WCR)

Access: Supervisor read/write

3 2 1 0

WAIT DOZE HALTED EN

1 1 1 1

Table 20-3. WCR Field Descriptions

Field Description

15–4 Reserved, should be cleared.

WAIT

Wait mode bit. Controls the function of the watchdog timer in wait mode. After written, the WAIT bit is not affected by further writes except in halted mode. Reset sets WAIT.

0 Watchdog timer not affected in wait mode

1 Watchdog timer stopped in wait mode

DOZE

HALTED

Halted mode bit. Controls the function of the watchdog timer in halted/debug mode. After written, the HALTED bit is not affected by further writes except in halted mode.

During halted mode, watchdog timer registers can be written and read normally. When halted mode is exited, timer operation continues from the state it was in before entering halted mode, but any updates made in halted mode remain. If a write-once register is written for the first time in halted mode, the register remains writable when halted mode is exited.

0 Watchdog timer not affected in halted mode

1 Watchdog timer stopped in halted mode

Note: Changing the HALTED bit from 1 to 0 during halted mode starts the watchdog timer. Changing the HALTED bit from 0 to 1 during halted mode stops the watchdog timer.

Doze mode bit. Controls the function of the watchdog timer in doze mode. After written, the DOZE bit is not affected by further writes except in halted mode. Reset sets DOZE.

0 Watchdog timer not affected in doze mode

1 Watchdog timer stopped in doze mode

Watchdog enable bit. Enables the watchdog timer. After written, the EN bit is not affected by further writes except in halted mode. When the watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state. After disabled, the watchdog cannot be re-enabled.

0 Watchdog timer disabled

1 Watchdog timer enabled

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20.2.2 Watchdog Modulus Register (WMR)

The WMR register determines the timer modulus reload value.

Address: 0xFC08_C002 Access: Supervisor read/write

2 1 0 15

Reset 1

12 11 10 9 8

7 6 5 4

1 1 1 1 1 1 1 1

Figure 20-3. Watchdog Modulus Register (WMR)

Table 20-4. WMR Field Descriptions

1 1 1 1

Field

15–0

Description

Watchdog modulus. Contains the modulus that is reloaded into the watchdog counter by a service sequence. After written, the WM[15:0] field is not affected by further writes except in halted mode. Writing to WMR immediately loads the new modulus value into the watchdog counter. The new value is also used at the next and all subsequent reloads.

Reading WMR returns the value in the modulus register.

Reset initializes the WM[15:0] field to 0xFFFF.

Note: The prescaler counter is reset anytime a new value is loaded into the watchdog counter and also during reset.

20.2.3 Watchdog Count Register (WCNTR)

The WCNTR register provides visibility to the watchdog counter value. The timeout value for the watchdog timer is determined from the following equation:

WDT timeout =

Thus, the maximum timeout is 4096

× 2

/ f sys/2

4096

× f

WCNTR

Eqn. 20-1

= 3.22 seconds at 83.3 MHz internal bus frequency.

Address: 0xFC08_C004

14 15

Reset 1 1

12 11 10 9 8

7 6 5 4

1 1 1 1 1 1 1 1 1 1 1 1

Figure 20-4. Watchdog Count Register (WCNTR)

Access: User read/write

2 1 0

Table 20-5. WCNTR Field Descriptions

Field

15–0

Description

Watchdog count field. Reflects the current value in the watchdog counter. Reading the 16-bit WCNTR with two 8-bit reads is not guaranteed to return a coherent value. Writing to WCNTR has no effect, and write cycles are terminated normally.

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20-4 Freescale Semiconductor

Watchdog Timer Module

20.2.4 Watchdog Service Register (WSR)

When the watchdog timer is enabled, writing 0x5555 and then 0xAAAA to WSR before the watchdog counter times out prevents a reset. If WSR is not serviced before the timeout, the watchdog timer sends a signal to the reset controller module that sets the RSR[WDR] bit and asserts a system reset.

Both writes must occur in the order listed before the timeout, but any number of instructions can be executed between the two writes. However, writing any value other than 0x5555 or 0xAAAA to WSR resets the servicing sequence, requiring both values to be written to keep the watchdog timer from causing a reset.

Address: 0xFC08_C006

14 15

Reset 0 0

12 11 10 9 8

7 6 5

0 0 0 0 0 0 0 0

Figure 20-5. Watchdog Service Register (WSR)

Access: User read/write

2 1 0

0 0 0 0

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Watchdog Timer Module

20-6

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Chapter 21 Programmable Interrupt Timers (PIT0–PIT1)

21.1 Introduction

This chapter describes the operation of the two programmable interrupt timer modules: PIT0–PIT1.

21.1.1 Overview

Each PIT is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention. The timer can count down from the value written in the modulus register or it can be a free-running down-counter.

21.1.2 Block Diagram

Internal Bus

Clock (f sys/2

)

Prescaler

PRE[3:0]

DOZE

DBG

16-bit PCNTRn

16-bit PIT Counter

OVW

16-bit PMRn

COUNT = 0

Load

Counter

RLD

PIF

PIE

To Interrupt

Controller

Internal Bus

Figure 21-1. PIT Block Diagram

21.1.3 Low-Power Mode Operation

This subsection describes the operation of the PIT modules in low-power modes and debug mode of operation. Low-power modes are described in the power management module,

Chapter 8, “Power

Management.”

Table 21-1 shows the PIT module operation in low-power modes and how it can exit from

each mode.

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Freescale Semiconductor 21-1

Programmable Interrupt Timers (PIT0–PIT1)

NOTE

The low-power interrupt control register (LPICR) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode.

Table 21-1. PIT Module Operation in Low-power Modes

Low-power Mode

Wait

Doze

Stop

Debug

PIT Operation Mode Exit

Normal N/A

Normal if PCSRn[DOZE] cleared, stopped otherwise

Any interrupt at or above level in LPICR, exit doze mode if PCSRn[DOZE] is set. Otherwise interrupt assertion has no effect.

Stopped No

Normal if PCSRn[DBG] cleared, stopped otherwise

No. Any interrupt is serviced upon normal exit from debug mode

In wait mode, the PIT module continues to operate as in run mode and can be configured to exit the low-power mode by generating an interrupt request. In doze mode with the PCSRn[DOZE] bit set, PIT module operation stops. In doze mode with the PCSRn[DOZE] bit cleared, doze mode does not affect PIT operation. When doze mode is exited, PIT continues operating in the state it was in prior to doze mode. In stop mode, the internal bus clock is absent and PIT module operation stops.

In debug mode with the PCSRn[DBG] bit set, PIT module operation stops. In debug mode with the

PCSRn[DBG] bit cleared, debug mode does not affect PIT operation. When debug mode is exited, the PIT continues to operate in its pre-debug mode state, but any updates made in debug mode remain.

21.2 Memory Map/Register Definition

This section contains a memory map (see Table 21-2

) and describes the register structure for PIT0–PIT1.

NOTE

Longword accesses to any of the programmable interrupt timer registers results in a bus error. Only byte and word accesses are allowed.

Table 21-2. Programmable Interrupt Timer Modules Memory Map

Address

PIT 0

PIT 1

Register

Width

(bits)

Supervisor Access Only Registers

16 0xFC08_0000

0xFC08_4000

0xFC08_0002

0xFC08_4002

PIT Control and Status Register (PCSRn)

PIT Modulus Register (PMRn) 16

Access

R/W

Reset Value Section/Page

0x0000

0xFFFF

21.2.1/21-3

21.2.2/21-4

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Programmable Interrupt Timers (PIT0–PIT1)

Table 21-2. Programmable Interrupt Timer Modules Memory Map (continued)

Address

PIT 0

PIT 1

Register

Width

(bits)

Access

Reset Value Section/Page

User/Supervisor Access Registers

0xFC08_0004

0xFC08_4004

PIT Count Register (PCNTRn) 16 R 0xFFFF

21.2.3/21-5

Accesses to reserved address locations have no effect and result in a cycle termination transfer error.

User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.

21.2.1 PIT Control and Status Register (PCSRn)

The PCSRn registers configure the corresponding timer’s operation.

Address: 0xFC08_0000 (PCSR0)

0xFC08_4000 (PCSR 1 )

R 0

Reset 0

11 10

PRE

9 8 7

6 5 4 3

DOZE DBG OVW PIE

0 0 0 0 0 0

Figure 21-2. PCSRn Register

0 0 0

Table 21-3. PCSRn Field Descriptions

Access: Supervisor read/write

1 0 2

PIF w1c

RLD

Field Description

15–12 Reserved, must be cleared.

11–8

PRE

Prescaler. The read/write prescaler bits select the internal bus clock divisor to generate the PIT clock. To accurately predict the timing of the next count, change the PRE[3:0] bits only when the enable bit (EN) is clear. Changing

PRE[3:0] resets the prescaler counter. System reset and the loading of a new value into the counter also reset the prescaler counter. Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN bit stops the prescaler counter.

PRE

0000

0001

0010

...

1101

1110

1111

Internal Bus Clock

Divisor

...

Decimal

Equivalent

...

8192

16384

32768

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Programmable Interrupt Timers (PIT0–PIT1)

Table 21-3. PCSRn Field Descriptions (continued)

Field

DOZE

DBG

OVW

PIE

PIF

RLD

Description

Reserved, must be cleared.

Doze Mode Bit. The read/write DOZE bit controls the function of the PIT in doze mode. Reset clears DOZE.

0 PIT function not affected in doze mode

1 PIT function stopped in doze mode. When doze mode is exited, timer operation continues from the state it was in before entering doze mode.

Debug mode bit. Controls the function of PIT in halted/debug mode. Reset clears DBG. During debug mode, register read and write accesses function normally. When debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain.

0 PIT function not affected in debug mode

1 PIT function stopped in debug mode

Note: Changing the DBG bit from 1 to 0 during debug mode starts the PIT timer. Likewise, changing the DBG bit from 0 to 1 during debug mode stops the PIT timer.

Overwrite. Enables writing to PMRn to immediately overwrite the value in the PIT counter.

0 Value in PMRn replaces value in PIT counter when count reaches 0x0000.

1 Writing PMRn immediately replaces value in PIT counter.

PIT interrupt enable. This read/write bit enables PIF flag to generate interrupt requests.

0 PIF interrupt requests disabled

1 PIF interrupt requests enabled

PIT interrupt flag. This read/write bit is set when PIT counter reaches 0x0000. Clear PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF.

0 PIT count has not reached 0x0000.

1 PIT count has reached 0x0000.

Reload bit. The read/write reload bit enables loading the value of PMRn into PIT counter when the count reaches

0x0000.

0 Counter rolls over to 0xFFFF on count of 0x0000

1 Counter reloaded from PMRn on count of 0x0000

PIT enable bit. Enables PIT operation. When PIT is disabled, counter and prescaler are held in a stopped state. This bit is read anytime, write anytime.

0 PIT disabled

1 PIT enabled

21.2.2 PIT Modulus Register (PMRn)

The 16-bit read/write PMRn contains the timer modulus value loaded into the PIT counter when the count reaches 0x0000 and the PCSRn[RLD] bit is set.

When the PCSRn[OVW] bit is set, PMRn is transparent, and the value written to PMRn is immediately loaded into the PIT counter. The prescaler counter is reset (0xFFFF) anytime a new value is loaded into the PIT counter and also during reset. Reading the PMRn returns the value written in the modulus latch.

Reset initializes PMRn to 0xFFFF.

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Programmable Interrupt Timers (PIT0–PIT1)

Address: 0xFC08_0002 (PMR0)

0xFC08_4002 (PMR 1 )

14 13 15

Reset 1 1 1

12 11 10 9 8

7 6 5

1 1 1 1 1 1 1 1

Figure 21-3. PIT Modulus Register (PMRn)

Field

15–0

Access: Supervisor read/write

2 1 0

1 1 1

Table 21-4. PMRn Field Descriptions

Description

Timer modulus. The value of this register is loaded into the PIT counter when the count reaches zero and the

PCSRn[RLD] bit is set. However, if PCSRn[OVW] is set, the value written to this field is immediately loaded into the counter. Reading this field returns the value written.

21.2.3 PIT Count Register (PCNTRn)

The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two 8-bit reads is not guaranteed coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally.

Address: 0xFC08_0004 (PCNTR0)

0xFC08_4004 (PCNTR 1 )

14 13 12 15

Reset 1 1 1

11 10 9 8

7 6 5

1 1 1 1 1 1 1 1

Figure 21-4. PIT Count Register (PCNTRn)

Access: User read only

Field

15–0

Table 21-5. PCNTRn Field Descriptions

Description

Counter value. Reading this field with two 8-bit reads is not guaranteed coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally.

21.3 Functional Description

This section describes the PIT functional operation.

21.3.1 Set-and-Forget Timer Operation

This mode of operation is selected when the RLD bit in the PCSR register is set.

When PIT counter reaches a count of 0x0000, PIF flag is set in PCSRn. The value in the modulus register loads into the counter, and the counter begins decrementing toward 0x0000. If the PCSRn[PIE] bit is set, the PIF flag issues an interrupt request to the CPU.

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Programmable Interrupt Timers (PIT0–PIT1)

When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000.

PIT Clock

Counter

Modulus

PIF

0x0002 0x0001

0x0005

0x0000 0x0005

Figure 21-5. Counter Reloading from the Modulus Latch

21.3.2 Free-Running Timer Operation

This mode of operation is selected when the PCSRn[RLD] bit is clear. In this mode, the counter rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement.

When the counter reaches a count of 0x0000, PCSRn[PIF] flag is set. If the PCSRn[PIE] bit is set, PIF flag issues an interrupt request to the CPU.

When the PCSRn[OVW] bit is set, counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000.

PIT CLOCK

COUNTER

MODULUS

PIF

0x0002 0x0001

0x0005

0x0000 0xFFFF

Figure 21-6. Counter in Free-Running Mode

21.3.3 Timeout Specifications

The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the internal bus clock period as selected by the PCSRn[PRE] bits. The PMRn[PM] bits select the timeout period.

Timeout period

PCSRn[PRE]

(PMRn[PM] + 1) f sys/2

Eqn. 21-1

21.3.4 Interrupt Operation

Table 21-6

shows the interrupt request generated by the PIT.

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Programmable Interrupt Timers (PIT0–PIT1)

Table 21-6. PIT Interrupt Requests

Interrupt Request

Timeout

Flag

PIF

Enable Bit

PIE

The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR.

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Chapter 22 DMA Timers (DTIM0–DTIM3)

22.1 Introduction

This chapter describes the configuration and operation of the four direct memory access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or DMA triggers. Additionally, programming examples are included.

NOTE

The designation n appears throughout this section to refer to registers or signals associated with one of the four identical timer modules: DTIM0,

DTIM1, DTIM2, or DTIM3.

22.1.1 Overview

Each DMA timer module has a separate register set for configuration and control. The timers can be configured to operate from the internal bus clock or from an external clocking source using the DTnIN signal. If the internal bus clock is selected, it can be divided by 16 or 1. The selected clock source is routed to an 8-bit programmable prescaler that clocks the actual DMA timer counter register (DTCNn). Using the

DTMRn, DTXMRn, DTCRn, and DTRRn registers, the DMA timer may be configured to assert an output signal, generate an interrupt, or request a DMA transfer on a particular event.

NOTE

The GPIO module must be configured to enable the peripheral function of

the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”

) prior to configuring the DMA Timers.

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22-1

DMA Timers (DTIM0–DTIM3)

Figure 22-1

is a block diagram of one of the four identical timer modules.

Internal Bus to/from DMA Timer Registers

Internal Bus Clock

(÷1 or ÷16

)

DMA Timer

DTnIN

Capture

Detection

DMA Timer

Clock

Generator clock

DMA Timer Mode Register (DTMRn)

Prescaler Mode Bits

7 0

DMA Timer Extended Mode

Divider

DMA Timer Counter Register (DTCNn)

(contains incrementing value)

DMA Timer Capture Register (DTCRn)

(latches DTCN value when triggered by

DTnIN)

0 31

DMA Timer Reference Register (DTRRn)

(reference value for comparison with DTCN)

DMA Timer Event Register (DTERn)

(indicates capture or when DTCN = DTRRn)

DTnOUT

Interrupt Request

DMA Request

Figure 22-1. DMA Timer Block Diagram

22.1.2 Features

Each DMA timer module has:

• Maximum timeout period of 211,106 seconds at 83.33 MHz (~58 hours)

• 12-ns resolution at 83.33 MHz

• Programmable sources for the clock input, including external clock

• Programmable prescaler

• Input-capture capability with programmable trigger edge on input pin

• Programmable mode for the output pin on reference compare

• Free run and restart modes

• Programmable interrupt or DMA request on input capture or reference-compare

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DMA Timers (DTIM0–DTIM3)

22.2 Memory Map/Register Definition

The timer module registers, shown in Table 22-1

, can be modified at any time.

Table 22-1. DMA Timer Module Memory Map

Address

DMA Timer 0

DMA Timer 1

DMA Timer 2

DMA Timer 3

Register

Width

(bits)

0xFC07_0000

0xFC07_4000

0xFC07_8000

0xFC07_C000

DMA Timer n Mode Register (DTMRn) 16

0xFC07_0002

0xFC07_4002

0xFC07_8002

0xFC07_C002

DMA Timer n Extended Mode Register (DTXMRn) 8

8 0xFC07_0003

0xFC07_4003

0xFC07_8003

0xFC07_C003

DMA Timer n Event Register (DTERn)

32 0xFC07_0004

0xFC07_4004

0xFC07_8004

0xFC07_C004

DMA Timer n Reference Register (DTRRn)

0xFC07_0008

0xFC07_4008

0xFC07_8008

0xFC07_C008

DMA Timer n Capture Register (DTCRn)

0xFC07_000C

0xFC07_400C

0xFC07_800C

0xFC07_C00C

DMA Timer n Counter Register (DTCNn)

Access Reset Value Section/Page

R/W

0x0000

0x00

0xFFFF_FFFF

0x0000_0000

22.2.1 DMA Timer Mode Registers (DTMRn)

DTMRs, shown in

Figure 22-2

, program the prescaler and various timer modes.

Address: 0xFC07_0000 ( DTMR0 )

0xFC07_4000 ( DTMR1 )

0xFC07_8000 ( DTMR2 )

0xFC07_C000 ( DTMR3 )

14 13 12 15

Reset 0 0 0 0

11 10 9 8 7

0 0 0 0 0 0

Figure 22-2. DTMRn Registers

5 4 3

OM ORRI FRR

0 0 0

Access: User read/write

CLK

RST

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DMA Timers (DTIM0–DTIM3)

Table 22-2. DTMRn Field Descriptions

Field

15–8

7–6

ORRI

FRR

2–1

CLK

RST

Description

Prescaler value. Divides the clock input (internal bus clock/(16 or 1) or clock on DTnIN).

0x00 1

...

0xFF 256

Capture edge.

00 Disable capture event output

01 Capture on rising edge only

10 Capture on falling edge only

11 Capture on any edge

Output mode.

0 Active-low pulse for one internal bus clock cycle (12-ns resolution at 83.33 MHz).

1 Toggle output.

Output reference request, interrupt enable. If ORRI is set when DTERn[REF] is set, a DMA request or an interrupt occurs, depending on the value of DTXMRn[DMAEN] (DMA request if set, interrupt if cleared).

0 Disable DMA request or interrupt for reference reached (does not affect DMA request or interrupt on capture function).

1 Enable DMA request or interrupt upon reaching the reference value.

Free run/restart

0 Free run. Timer count continues incrementing after reaching the reference value.

1 Restart. Timer count is reset immediately after reaching the reference value.

Input clock source for the timer. Avoid setting CLK when RST is already set. Doing so causes CLK to zero (stop counting).

00 Stop count

01 Internal bus clock divided by 1

10 Internal bus clock divided by 16. This clock source is not synchronized with the timer; therefore, successive time-outs may vary slightly.

11 DTnIN pin (falling edge)

Reset timer. Performs a software timer reset similar to an external reset, although other register values can be written while RST is cleared. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless the timer is enabled.

0 Reset timer (software reset)

1 Enable timer

22.2.2 DMA Timer Extended Mode Registers (DTXMRn)

The DTXMRn register programs DMA request and increment modes for the timers.

Access: User read/write Address: 0x FC07_00 02 ( DTXMR0 )

0x FC07_400 2 ( DTXMR1 )

0x FC07_800 2 ( DTXMR2 )

0x FC07_C00 2 ( DTXMR3 )

DMAEN

MODE16

Figure 22-3. DTXMRn Registers

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DMA Timers (DTIM0–DTIM3)

Table 22-3. DTXMRn Field Descriptions

Field Description

DMAEN

DMA request. Enables DMA request output on counter reference match or capture edge event.

0 DMA request disabled

1 DMA request enabled

6–1 Reserved, must be cleared.

MODE16

Selects the increment mode for the timer. Setting MODE16 is intended to exercise the upper bits of the 32-bit timer in diagnostic software without requiring the timer to count through its entire dynamic range. When set, the counter’s upper 16 bits mirror its lower 16 bits. All 32 bits of the counter remain compared to the reference value.

0 Increment timer by 1

1 Increment timer by 65,537

22.2.3 DMA Timer Event Registers (DTERn)

DTERn, shown in

Figure 22-4

, reports capture or reference events by setting DTERn[CAP] or

DTERn[REF]. This reporting happens regardless of the corresponding DMA request or interrupt enable values, DTXMRn[DMAEN] and DTMRn[ORRI,CE].

Writing a 1 to DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect bit value); both bits can be cleared at the same time. If configured to generate an interrupt request, clear REF and CAP early in the interrupt service routine so the timer module can negate the interrupt request signal to the interrupt controller. If configured to generate a DMA request, processing of the DMA data transfer automatically clears the REF and CAP flags via the internal DMA ACK signal.

Access: User read/write Address: 0xFC07_0003 (DTER0)

0xFC07_4003 (DTER1)

0xFC07_8003 (DTER2)

0xFC07_C003 (DTER3)

0 R

Reset: 0 0

REF w1c

CAP w1c

0 0 0 0

Figure 22-4. DTERn Registers

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DMA Timers (DTIM0–DTIM3)

Table 22-4. DTERn Field Descriptions

Field

7–2

REF

Description

Reserved, must be cleared.

Output reference event. The counter value (DTCNn) equals DTRRn. Writing a 1 to REF clears the event condition.

Writing a 0 has no effect.

REF DTMRn[ORRI] DTXMRn[DMAEN]

No event

No request asserted

Interrupt request asserted

DMA request asserted

CAP

Capture event. The counter value has been latched into DTCRn. Writing a 1 to CAP clears the event condition.

Writing a 0 has no effect.

CAP DTMRn[CE]

DTXMRn

[DMAEN]

No event

Disable capture event output

Capture on rising edge and trigger interrupt

Capture on rising edge and trigger DMA

Capture on falling edge and trigger interrupt

Capture on falling edge and trigger DMA

Capture on any edge and trigger interrupt

Capture on any edge and trigger DMA

22.2.4 DMA Timer Reference Registers (DTRRn)

As part of the output-compare function, each DTRRn contains the reference value compared with the respective free-running timer counter (DTCNn).

The reference value is matched when DTCNn equals DTRRn. The prescaler indicates that DTCNn should be incremented again. Therefore, the reference register is matched after DTRRn + 1 time intervals.

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DMA Timers (DTIM0–DTIM3)

Field

31–0

REF

Address: 0x FC07_00 04 ( DTRR0 )

0x FC07_400 4 ( DTRR1 )

0x FC07_800 4 ( DTRR2 )

0x FC07_C00 4 ( DTRR3 )

Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REF (32-bit reference value)

Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 22-5. DTRRn Registers

Table 22-5. DTRRn Field Descriptions

Description

Reference value compared with the respective free-running timer counter (DTCNn) as part of the output-compare function.

22.2.5 DMA Timer Capture Registers (DTCRn)

Each DTCRn latches the corresponding DTCNn value during a capture operation when an edge occurs on

DTnIN, as programmed in DTMRn. The internal bus clock is assumed to be the clock source. DTnIN cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation results if DTnIN is set as the clock source when the input capture mode is used.

Address: 0x FC07_00 08 ( DTCR0 )

0x FC07_400 8 ( DTCR1 )

0x FC07_800 8 ( DTCR2 )

0x FC07_C00 8 ( DTCR3 )

Access: User read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CAP (32-bit capture counter value)

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 22-6. DTCRn Registers

Table 22-6. DTCRn Field Descriptions

Field

31–0

CAP

Description

Captures the corresponding DTCNn value during a capture operation when an edge occurs on DTnIN, as programmed in DTMRn.

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DMA Timers (DTIM0–DTIM3)

22.2.6 DMA Timer Counters (DTCNn)

The current value of the 32-bit timer counter can be read at anytime without affecting counting. Writes to

DTCNn clear the timer counter. The timer counter increments on the clock source rising edge (internal bus clock divided by 1, internal bus clock divided by 16, or DTnIN).

Address: 0x FC07_00 0C ( DTCN0 )

0x FC07_400 C ( DTCN1 )

0x FC07_800 C ( DTCN2 )

0x FC07_C00 C ( DTCN3 )

Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNT (32-bit timer counter value count)

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 22-7. DMA Timer Counters (DTCNn)

Table 22-7. DTCNn Field Descriptions

Field

31–0

CNT

Description

Timer counter. Can be read at anytime without affecting counting and any write to this field clears it.

22.3 Functional Description

22.3.1 Prescaler

The prescaler clock input is selected from the internal bus clock (f sys/2

divided by 1 or 16) or from the corresponding timer input, DTnIN. DTnIN is synchronized to the internal bus clock, and the synchronization delay is between two and three internal bus clocks. The corresponding DTMRn[CLK] selects the clock input source. A programmable prescaler divides the clock input by values from 1 to 256.

The prescaler output is an input to the 32-bit counter, DTCNn.

22.3.2 Capture Mode

Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value when the corresponding input capture edge detector senses a defined DTnIN transition. The capture edge bits

(DTMRn[CE]) select the type of transition that triggers the capture and sets the timer event register capture event bit, DTERn[CAP]. If DTERn[CAP] and DTXMRn[DMAEN] are set, a DMA request is asserted. If

DTERn[CAP] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted.

22.3.3 Reference Compare

Each DMA timer can be configured to count up to a reference value, at which point DTERn[REF] is set.

If DTMRn[ORRI] is set and DTXMRn[DMAEN] is cleared, an interrupt is asserted. If DTMRn[ORRI] and DTXMRn[DMAEN] are set, a DMA request is asserted. If the free run/restart bit DTMRn[FRR] is set, a new count starts. If it is clear, the timer keeps running.

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DMA Timers (DTIM0–DTIM3)

22.3.4 Output Mode

When a timer reaches the reference value selected by DTRR, it can send an output signal on DTnOUT.

DTnOUT can be an active-low pulse or a toggle of the current output, as selected by the DTMRn[OM] bit.

22.3.5 IEEE 1588 Support

The DMA timers on this device can use the Ethernet assembly’s IEEE-1588 timebase count value as its clock source. This feature supports triggering events via processor interrupts or DMA requests based on network time values.

22.4 Initialization/Application Information

The general-purpose timer modules typically, but not necessarily, follow this program order:

• The DTMRn and DTXMRn registers are configured for the desired function and behavior.

— Count and compare to a reference value stored in the DTRRn register

— Capture the timer value on an edge detected on DTnIN

— Configure DTnOUT output mode

— Increment counter by 1 or by 65,537 (16-bit mode)

— Enable/disable interrupt or DMA request on counter reference match or capture edge

• The DTMRn[CLK] register is configured to select the clock source to be routed to the prescaler.

— Internal bus clock (can be divided by 1 or 16)

— DTnIN, the maximum value of DTnIN is 1/5 of the internal bus clock, as described in the device’s electrical characteristics

NOTE

DTnIN may not be configured as a clock source when the timer capture mode is selected or indeterminate operation results.

• The 8-bit DTMRn[PS] prescaler value is set.

• Using DTMRn[RST], counter is cleared and started.

• Timer events are managed with an interrupt service routine, a DMA request, or by a software polling mechanism.

22.4.1 Code Example

The following code provides an example of how to initialize and use DMA Timer0 for counting time-out periods.

DTMR0 EQU 0xFC07_0000 ;Timer0 mode register

DTMR1 EQU 0xFC07_4000 ;Timer1 mode register

DTRR0 EQU 0xFC07_0004 ;Timer0 reference register

DTRR1 EQU 0xFC07_4004 ;Timer1 reference register

DTCR0 EQU 0xFC07_0008 ;Timer0 capture register

DTCR1 EQU 0xFC07_4008 ;Timer1 capture register

DTCN0 EQU 0xFC07_000C ;Timer0 counter register

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DMA Timers (DTIM0–DTIM3)

DTCN1 EQU 0xFC07_400C ;Timer1 counter register

DTER0 EQU 0xFC07_0003 ;Timer0 event register

DTER1 EQU 0xFC07_4003 ;Timer1 event register

* TMR0 is defined as: *

*[PS] = 0xFF,

*[CE] = 00 divide clock by 256 disable capture event output

*[OM] = 0

*[ORRI] = 0,

*[FRR] = 1,

*[CLK] = 10,

*[RST] = 0, output=active-low pulse disable ref. match output restart mode enabled internal bus clock/16 timer0 disabled move.w #0xFF0C,D0 move.w D0,TMR0 move.l #0x0000,D0;writing to the timer counter with any move.l DO,TCN0 ;value resets it to zero move.l #0xAFAF,DO ;set the timer0 reference to be move.l #D0,TRR0 ;defined as 0xAFAF

The simple example below uses Timer0 to count time-out loops. A time-out occurs when the reference value, 0xAFAF, is reached.

timer0_ex clr.l DO clr.l D1 clr.l D2 move.l #0x0000,D0 move.l D0,TCN0 move.b #0x03,D0 move.b D0,TER0 move.w TMR0,D0 bset #0,D0 move.w D0,TMR0

T0_LOOP move.b TER0,D1 btst #1,D1 beq T0_LOOP addi.l #1,D2 cmp.l #5,D2 beq T0_FINISH move.b #0x02,D0 move.b D0,TER0 jmp T0_LOOP

T0_FINISH

HALT

;reset the counter to 0x0000

;writing ones to TER0[REF,CAP]

;clears the event flags

;save the contents of TMR0 while setting

;the 0 bit. This enables timer 0 and starts counting

;load the value back into the register, setting TMR0[RST]

;load TER0 and see if

;TER0[REF] has been set

;Increment D2

;Did D2 reach 5? (i.e. timer ref has timed)

;If so, end timer0 example. Otherwise jump back.

;writing one to TER0[REF] clears the event flag

;End processing. Example is finished

22.4.2 Calculating Time-Out Values

Equation 22-1

determines time-out periods for various reference values:

Timeout period =

( ) × (

1 or 16

) × (

DTMRn[PS] + 1

) × (

DTRRn[REF] + 1

)

Eqn. 22-1

When calculating time-out periods, add 1 to the prescaler to simplify calculating, because

DTMRn[PS] equals 0x00 yields a prescaler of 1, and DTMRn[PS] equals 0xFF yields a prescaler of 256.

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DMA Timers (DTIM0–DTIM3)

For example, if a 83.33-MHz timer clock is divided by 16, DTMRn[PS] equals 0x7F, and the timer is referenced at 0x13DC3 (81,347 decimal), the time-out period is:

Timeout period =

× (

127 + 1

83.3

) × (

81347 + 1

)

= 2.00 s

Eqn. 22-2

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DMA Timers (DTIM0–DTIM3)

22-12

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Chapter 23 Queued Serial Peripheral Interface (QSPI)

23.1 Introduction

This chapter describes the queued serial peripheral interface (QSPI) module.

23.1.1 Block Diagram

Figure 23-1

illustrates the QSPI module.

Queue Control

Block

Queue

Pointer

Comparator

80-byte

QSPI

RAM

End Queue

Pointer

Done

QSPI

Address

Control Logic

Status

Regs

Control

Regs

Chip

Selects

Logic

Array

Command msb lsb

8/16 Bit Shift Reg.

Rx/Tx Data Reg.

QSPI

Data

QSPI_DIN

QSPI_DOUT

QSPI_CS[2:0]

Delay

Counter

Internal Bus

Clock (f sys/2

)

Divide by 2

Baud Rate

Generator

Figure 23-1. QSPI Block Diagram

QSPI_CLK

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Queued Serial Peripheral Interface (QSPI)

23.1.2 Overview

The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address and data registers.

NOTE

The GPIO module must be configured to enable the peripheral function of

the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”

) prior to configuring the QSPI module.

23.1.3 Features

Features include:

• Programmable queue to support up to 16 transfers without user intervention

— 80 bytes of data storage provided

• Supports transfer sizes of 8 to 16 bits in 1-bit increments

• Three peripheral chip-select lines for control of up to 7 devices (All chip selects may not be

available on all devices. See Chapter 2, “Signal Descriptions,”

for details on which chip-selects are pinned-out.)

• Baud rates from 163.39 Kbps to 20.83 Mbps at 83.33 MHz internal bus frequency

• Programmable delays before and after transfers

• Programmable QSPI clock phase and polarity

• Supports wraparound mode for continuous transfers

23.1.4 Modes of Operation

Because the QSPI module only operates in master mode, the master bit in the QSPI mode register

(QMR[MSTR]) must be set for the QSPI to function properly. If the master bit is not set, QSPI activity is indeterminate. The QSPI can initiate serial transfers but cannot respond to transfers initiated by other QSPI masters.

23.2 External Signal Description

The module provides access to as many as 7 devices with a total of six signals: QSPI_DOUT, QSPI_DIN,

QSPI_CLK, QSPI_CS[2:0].

Peripheral chip-select signals, QSPI_CSn, are used to select an external device as the source or destination for serial data transfer. Signals are asserted when a command in the queue is executed. More than one chip-select signal can be asserted simultaneously.

Although QSPI_CSn signals function as simple chip selects in most applications, up to 7 devices can be selected by decoding them with an external 3-to-8 decoder.

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Table 23-1. QSPI Input and Output Signals and Functions

Signal Name

Data output (QSPI_DOUT)

Data input (QSPI_DIN)

Serial clock (QSPI_CLK)

Peripheral chip selects (QSPI_CSn)

Hi-Z or Actively Driven

Configurable

N/A

Actively driven

Function

Serial data output from QSPI

Serial data input to QSPI

Clock output from QSPI

Peripheral selects from QSPI

23.3 Memory Map/Register Definition

Table 23-2

is the QSPI register memory map. Reading reserved locations returns zeros.

Table 23-2. QSPI Memory Map

Address

Register

0xFC05_C000 QSPI Mode Register (QMR)

0xFC05_C004 QSPI Delay Register (QDLYR)

0xFC05_C008 QSPI Wrap Register (QWR)

0xFC05_C00C QSPI Interrupt Register (QIR)

Width

(bits)

Access Reset Value Section/Page

R/W

0xFC05_C010 QSPI Address Register (QAR) 16

0xFC05_C014 QSPI Data Register (QDR) 16 R/W

Addresses not assigned to a register and undefined register bits are reserved for expansion.

See the register description for special cases. Some bits may be read- or write-only.

0x0104

0x0404

0x0000

23.3.1 QSPI Mode Register (QMR)

The QMR, shown in

Figure 23-2

, determines the basic operating modes of the QSPI module. Parameters such as QSPI_CLK polarity and phase, baud rate, master mode operation, and transfer size are determined by this register.

NOTE

Because the QSPI does not operate in slave mode, the master mode enable bit (QMR[MSTR]) must be set for the QSPI module to operate correctly.

Address: 0xFC05_C000 (QMR)

MSTR

Reset 0

BITS

11 10 9 8

CPOL CPHA

7 6 5

0 0 0 0 1 0 0

Figure 23-2. QSPI Mode Register (QMR)

BAUD

Access: User read/write

2 1 0

0 0 1 0 0

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Queued Serial Peripheral Interface (QSPI)

Table 23-3. QMR Field Descriptions

Field

MSTR

13–10

BITS

Description

Master mode enable.

0 Reserved, do not use.

1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.

Reserved, must be cleared.

Transfer size. Determines the number of bits to be transferred for each entry in the queue.

BITS Bits per Transfer

0000

0001–0111

1000

1001

1010

1011

1100

1101

1110

1111

Reserved

CPOL

CPHA

7–0

BAUD

Clock polarity. Defines the clock polarity of QSPI_CLK.

0 The inactive state value of QSPI_CLK is logic level 0.

1 The inactive state value of QSPI_CLK is logic level 1.

Clock phase. Defines the QSPI_CLK clock-phase.

0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK.

1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.

Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value of zero disables the QSPI.

A value of 1 is an invalid setting. The desired QSPI_CLK baud rate is related to the internal bus clock and

QMR[BAUD] by the following expression:

QMR[BAUD] = f sys/2

/ (2 ×

[desired QSPI_CLK baud rate])

23-4

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Freescale Semiconductor

Figure 23-3

shows an example of a QSPI clocking and data transfer.

QSPI_CLK

Queued Serial Peripheral Interface (QSPI)

QSPI_DOUT

15 14 13 12 11 10 msb

9 8 7 6 5 4 3 2 1 0

QSPI_DIN

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

QSPI_CS

QMR[CPOL] = 0

QMR[CPHA] = 1

QCR[CONT] = 0

Chip selects are active low

A = QDLYR[QCD]

B = QDLYR[DTL]

Figure 23-3. QSPI Clocking and Data Transfer Example

23.3.2 QSPI Delay Register (QDLYR)

The QDLYR is used to initiate master mode transfers and to set various delay parameters.

Address: 0xFC05_C004 (QDLYR)

14 13 15

SPE

Reset 0 0 0

12 11

QCD

10 9 8 7 6 5

0 0 1 0 0 0 0 0

Figure 23-4. QSPI Delay Register (QDLYR)

DTL

Access: User read/write

2 1 0

0 1 0 0

Table 23-4. QDLYR Field Descriptions

Field

SPE

14–8

QCD

7–0

DTL

Description

QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command RAM.

The QSPI clears this bit automatically when a transfer completes. The user can also clear this bit to abort transfer unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT].

QSPI_CLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay from assertion of the chip selects to valid QSPI_CLK transition. See

Section 23.4.3, “Transfer Delays”

for information on setting this bit field.

Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer.

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Queued Serial Peripheral Interface (QSPI)

23.3.3 QSPI Wrap Register (QWR)

The QSPI wrap register provides halt transfer control, wraparound settings, and queue pointer locations.

Address: 0xFC05_C008 (QWR)

15 14 13 12

HALT WREN WRTO CSIV

Reset 0 0 0 0

11 10 9

ENDQP

8 7 6 5

CPTQP

0 0 0 0 0 0

Figure 23-5. QSPI Wrap Register (QWR)

Access: User read/write

2 1 0

NEWQP

0 0 0 0

Table 23-5. QWR Field Descriptions

Field Description

HALT

WREN

WRTO

CSIV

Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands after it has completed execution of the current command.

Wraparound enable. Enables wraparound mode.

0 Execution stops after executing the command pointed to by QWR[ENDQP].

1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed to by

QWR[NEWQP] and continue execution.

Wraparound location. Determines where the QSPI wraps to in wraparound mode.

0 Wrap to RAM entry zero.

1 Wrap to RAM entry pointed to by QWR[NEWQP].

QSPI_CS inactive level.

0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during a transfer (that is, inactive state is 0, chip selects are active high).

1 QSPI chip select outputs return to one when not driven from the value in the current command RAM entry during a transfer (that is, inactive state is 1, chip selects are active low).

11–8

ENDQP

End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.

7–4

CPTQP

Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed.

This field is read only.

3–0

NEWQP

Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer.

23.3.4 QSPI Interrupt Register (QIR)

The QIR contains QSPI interrupt enables and status flags.

Address: 0xFC05_C00C (QIR)

Reset

15 14

WCEFB ABRTB

0 0

ABRTL WCEFE ABRTE

SPIFE

Figure 23-6. QSPI Interrupt Register (QIR)

Access: User read/write

4 3 2 1 0

0 WCEF ABRT 0 SPIF

0 w1c w1c

0 0 0 w1c

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Queued Serial Peripheral Interface (QSPI)

Table 23-6. QIR Field Descriptions

Field Description

WCEFB

Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing the current command is written to by the CPU with the QDR. When this bit is asserted, the write access to QDR results in an access error.

ABRTB

Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer. When set, an attempt to clear QDLYR[SPE] during a transfer results in an access error.

ABRTL

Reserved, must be cleared.

Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR. QDLYR[SPE] is only cleared by the QSPI when a transfer completes.

7–4

WCEF

ABRT

SPIF

WCEFE

Write collision (WCEF) interrupt enable.

0 Write collision interrupt disabled

1 Write collision interrupt enabled

ABRTE

Abort (ABRT) interrupt enable.

0 Abort interrupt disabled

1 Abort interrupt enabled

SPIFE

Reserved, must be cleared.

QSPI finished (SPIF) interrupt enable.

0 SPIF interrupt disabled

1 SPIF interrupt enabled

Reserved, must be cleared.

Write collision error flag. Indicates that an attempt has been made to write to the RAM entry that is currently being executed. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.

Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR rather than by completion of the command queue by the QSPI. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.

Reserved, must be cleared.

QSPI finished flag. Asserted when the QSPI has completed all the commands in the queue. Set on completion of the command pointed to by QWR[ENDQP], and on completion of the current command after assertion of

QWR[HALT]. In wraparound mode, this bit is set every time the command pointed to by QWR[ENDQP] is completed.

Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.

23.3.5 QSPI Address Register (QAR)

The QAR is used to specify the location in the QSPI RAM that read and write operations affect. As shown

in Section 23.4.1, “QSPI RAM”

, the transmit RAM is located at addresses 0x0 to 0xF, the receive RAM is located at 0x10 to 0x1F, and the command RAM is located at 0x20 to 0x2F. (These addresses refer to the QSPI RAM space, not the device memory map.)

NOTE

A read or write to the QSPI RAM causes QAR to increment. However, the

QAR does not wrap after the last queue entry within each section of the

RAM. The application software must manage address range errors.

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Queued Serial Peripheral Interface (QSPI)

Address: 0xFC05_C010 (QAR)

R 0

Reset 0

0 0 0 0 0 0 0

Figure 23-7. QSPI Address Register (QAR)

Table 23-7. QAR Field Descriptions

Field Description

15–6 Reserved, must be cleared.

5–0

ADDR

Address used to read/write the QSPI RAM. Ranges are as follows:

0x00–0x0F Transmit RAM

0x10–0x1F Receive RAM

0x20–0x2F Command RAM

0x30–0x3F Reserved

Access: User read/write

3 2 1 0

ADDR

0 0 0 0 0

23.3.6 QSPI Data Register (QDR)

The QDR is used to access QSPI RAM indirectly. The CPU reads and writes all data from and to the QSPI

RAM through this register.

A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also causes the value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at the address specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.

Address: 0xFC05_C014 (QDR)

14 13 15

Reset 0 0 0

11 10 9 8

DATA

7 6 5 4

Access: User read/write

2 1 0

0 0 0 0 0 0 0 0 0 0

Figure 23-8. QSPI Data Register (QDR)

Table 23-8. QDR Field Descriptions

Field

15–0

DATA

Description

A write to this field causes data to be written to the QSPI RAM entry specified by QAR[ADDR]. Similarly, a read of this field returns the data in the QSPI RAM at the address specified by QAR[ADDR]. During command RAM accesses (QAR[ADDR] = 0x20–0x2F), only the most significant byte of this field is used.

23.3.7 Command RAM Registers (QCR0–QCR15)

The command RAM is accessed using the upper byte of the QDR; the QSPI cannot modify information in command RAM. There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select field enables external peripherals for transfer. The command field provides transfer operations.

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Queued Serial Peripheral Interface (QSPI)

NOTE

The command RAM is accessed only using the most significant byte of

QDR and indirect addressing based on QAR[ADDR].

Address: QAR[ADDR] Access: CPU write-only

15 14 13 12

W CONT BITSE DT DSCK

Reset — — — —

—

10 9 8

—

QSPI_CS

— —

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

— — — — — — — —

Figure 23-9. Command RAM Registers (QCR0–QCR15)

Table 23-9. QCR0–QCR15 Field Descriptions

Field Description

CONT

BITSE

Continuous.

0 Chip selects return to inactive level defined by QWR[CSIV] when a single word transfer is complete.

1 Chip selects return to inactive level defined by QWR[CSIV] only after the transfer of the queue entries (max of 16 words).

Note: To keep the chip selects asserted for transfers beyond 16 words, the QWR[CSIV] bit must be set to control the level that the chip selects return to after the first transfer.

Bits per transfer enable.

0 Eight bits

1 Number of bits set in QMR[BITS]

Delay after transfer enable.

0 Default reset value.

1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have a latency requirement. The delay between transfers is determined by QDLYR[DTL].

DSCK

Chip select to QSPI_CLK delay enable.

0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period.

1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK.

Reserved, must be cleared.

10–8

QSPI_CS

Peripheral chip selects. Used to select an external device for serial data transfer. More than one chip select may be active at once, and more than one device can be connected to each chip select. Bits 10-8 map directly to the corresponding QSPI_CSn pins. If more than three chip selects are needed, then an external demultiplexor can be used with the QSPI_CSn pins.

Note: Not all chip selects may be available on all device packages. See Chapter 2, “Signal Descriptions,”

for details on which chip selects are pinned-out.

7–0 Reserved, must be cleared.

23.4 Functional Description

The QSPI uses a dedicated 80-byte block of static RAM accessible to the module and CPU to perform queued operations. The RAM is divided into three segments:

• 16 command control bytes (command RAM)

• 32 transmit data bytes (transmit data RAM)

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Queued Serial Peripheral Interface (QSPI)

• 32 receive data bytes (receive data RAM)

The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF).

NOTE

Throughout ColdFire documentation, the term word is used to designate a

16-bit data unit. The only exceptions to this appear in discussions of serial communication modules such as QSPI that support variable-length data units. To simplify these discussions, the functional unit is referred to as a word regardless of length.

The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queued commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their completion. As another option, QIR[SPIFE] can be enabled to generate an interrupt.

The QSPI uses four queue pointers. The user can access three of them through fields in QSPI wrap register

(QWR):

• New queue pointer (QWR[NEWQP])—points to the first command in the queue

• Internal queue pointer—points to the command currently being executed

• Completed queue pointer (QWR[CPTQP])—points to the last command executed

• End queue pointer (QWR[ENDQP]) —points to the final command in the queue

The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, the following sequence repeats:

1. The command pointed to by the internal pointer is executed.

2. The value in the internal pointer is copied into QWR[CPTQP].

3. The internal pointer is incremented.

Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed. After each command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs,

QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting QWR[WREN] enables wraparound mode.

QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0 unless another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but is changed to show the last queue entry before the QSPI is enabled. QWR[NEWQP] and QWR[ENDQP] can be written at any time. When the QWR[NEWQP] value changes, the internal pointer value also changes unless a transfer is in progress, in which case the transfer completes normally. Leaving QWR[NEWQP] and

QWR[ENDQP] set to 0x0 causes a single transfer to occur when the QSPI is enabled.

Data is transferred relative to QSPI_CLK, which can be generated in any one of four combinations of phase and polarity using QMR[CPHA,CPOL]. Data is transferred with the most significant bit (msb) first.

The number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]).

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Queued Serial Peripheral Interface (QSPI)

23.4.1 QSPI RAM

The QSPI contains an 80-byte block of static RAM that can be accessed by the user and the QSPI. This

RAM does not appear in the device memory map, because it can only be accessed by the user indirectly through the QSPI address register (QAR) and the QSPI data register (QDR). The RAM is divided into three segments with 16 addresses each:

• Receive data RAM—the initial destination for all incoming data

• Transmit data RAM—a buffer for all out-bound data

• Command RAM—where commands are loaded

The transmit data and command RAM are user write-only. The receive RAM is user read-only.

Figure 23-10

shows the RAM configuration. The RAM contents are undefined immediately after a reset.

The command and data RAM in the QSPI are indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands.

A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and causes the value in QAR to increment. Correspondingly, a read from QDR returns the data in the RAM at the address specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.

Relative

Address

0x00

0x01

...

0x0F

Register Function

QTR0 Transmit RAM

QTR1

...

QTR15

16 bits wide

0x10

0x11

...

0x1F

QRR0 Receive RAM

QRR1

...

QRR15

16 bits wide

0x20

0x21

...

0x2F

QCR0 Command RAM

QCR1

...

QCR15

8 bits wide

Figure 23-10. QSPI RAM Model

23.4.1.1

Receive RAM

Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM space. Read this segment to retrieve data from the QSPI. Data words with less than 16 bits are stored in

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Freescale Semiconductor 23-11

Queued Serial Peripheral Interface (QSPI)

the least significant bits of the RAM. Unused bits in a receive queue entry are set to zero upon completion of the individual queue entry. Receive RAM is not writeable.

QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine which locations in receive RAM contain valid data.

23.4.1.2

Transmit RAM

Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses 0x0 to 0xF.

The user normally writes 1 word into this segment for each queue command to be executed. The user cannot read data in the transmit RAM.

Outbound data must be written to transmit RAM in a right-justified format. The unused bits are ignored.

The QSPI copies the data to its data serializer (shift register) for transmission. The data is transmitted most significant bit first and remains in transmit RAM until overwritten by the user.

23.4.1.3

Command RAM

The CPU writes one byte of control information to this segment for each QSPI command to be executed.

Command RAM, referred to as QCR0–15, is write-only memory from a user’s perspective.

Command RAM consists of 16 bytes, each divided into two fields. The peripheral chip select field controls the QSPI_CS signal levels for the transfer. The command control field provides transfer options.

A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in

QWR[NEWQP] through the address in QWR[ENDQP].

The QSPI executes a queue of commands defined by the control bits in each command RAM entry that sequence the following actions:

• Chip-select pins are activated.

• Data is transmitted from the transmit RAM and received into the receive RAM.

• The synchronous transfer clock QSPI_CLK is generated.

Before any data transfers begin, control data must be written to the command RAM, and any out-bound data must be written to the transmit RAM. Also, the queue pointers must be initialized to the first and last entries in the command queue.

Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity are controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which QSPI_CLK edge is used to drive outgoing data and to latch incoming data.

23.4.2 Baud Rate Selection

The maximum QSPI clock frequency is one-fourth the clock frequency of the internal bus clock (f sys/2

Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to

derive the QSPI_CLK rate from the internal bus clock divided by two. Table 23-10 shows the QSPI_CLK

frequency as a function of internal bus clock and baud rate.

A baud rate value of zero turns off the QSPI_CLK.

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23-12 Freescale Semiconductor

Queued Serial Peripheral Interface (QSPI)

The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression:

QMR[BAUD] = f

-----------------------------------------------------------------------------------

[desired QSPI_CLK baud rate]

Eqn. 23-1

Table 23-10. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate

Internal Bus Clock = 83.33 MHz

QMR [BAUD]

255

QSPI_CLK

20.83 MHz

10.425 MHz

5.208 MHz

2.604 MHz

1.302 MHz

163.39 kHz

23.4.3 Transfer Delays

The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer. The time between QSPI_CS assertion and the leading QSPI_CLK edge, and the time between the end of one transfer and the beginning of the next, are both independently programmable.

The chip select to clock delay enable bit in the command RAM, QCR[DSCK], enables the programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK. QDLYR[QCD] determines the period of delay before the leading edge of QSPI_CLK. The following expression determines the actual delay before the QSPI_CLK leading edge:

QSPI_CS-to-QSPI_CLK delay =

Eqn. 23-2

f sys/2

QDLYR[QCD] has a range of 1–127.

When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the QSPI_CLK period is used.

The command RAM delay after transmit enable bit, QCR[DT], enables the programmable delay period from the negation of the QSPI_CS signals until the start of the next transfer. The delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. There are two transfer delay options: the user can choose to delay a standard period after serial transfer is complete or can specify a delay period.

Writing a value to QDLYR[DTL] specifies a delay period. QCR[DT] determines whether the standard delay period (DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay when DT equals 1:

Delay after transfer =

------------------------------------------------

(DT = 1) f sys/2

Eqn. 23-3

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Freescale Semiconductor 23-13

Queued Serial Peripheral Interface (QSPI)

where QDLYR[DTL] has a range of 1–255. A zero value for DTL causes a delay-after-transfer value of

8192/f sys/2

. Standard delay period (DT = 0) is calculated by the following:

Standard delay after transfer =

(DT = 0) f sys/2

Eqn. 23-4

Adequate delay between transfers must be specified for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay between successive transfers. If the internal bus clock is operating at a slower rate, the delay between transfers must be increased proportionately.

23.4.4 Transfer Length

There are two transfer length options. The user can choose a default value of 8 bits or a programmed value of 8 to 16 bits. The programmed value must be written into QMR[BITS]. The command RAM bits per transfer enable field, QCR[BITSE], determines whether the default value (BITSE = 0) or the BITS[3–0] value (BITSE = 1) is used. QMR[BITS] indicates the required number of bits to be transferred, with the default value of 16 bits.

23.4.5 Data Transfer

The transfer operation is initiated by setting QDLYR[SPE]. Shortly after QDLYR[SPE] is set, the QSPI executes the command at the command RAM address pointed to by QWR[NEWQP]. Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is simultaneously received is stored at the pointer address in receive RAM.

When the proper number of bits has been transferred, the QSPI stores the working queue pointer value in

QWR[CPTQP], increments the working queue pointer, and loads the next data for transfer from the transmit RAM. The command pointed to by the incremented working queue pointer is executed next unless a new value has been written to QWR[NEWQP]. If a new queue pointer value is written while a transfer is in progress, the current transfer is completed normally.

When the CONT bit in the command RAM is set, the QSPI_CSn signals are asserted between transfers.

When CONT is cleared, QSPI_CSn are negated between transfers. The QSPI_CSn signals are not high impedance.

When the QSPI reaches the end of the queue, it asserts the SPIF flag, QIR[SPIF]. If QIR[SPIFE] is set, an interrupt request is generated when QIR[SPIF] is asserted. Then the QSPI clears QDLYR[SPE] and stops, unless wraparound mode is enabled.

Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address 0x0, or to the address specified by QWR[NEWQP], depending on the state of QWR[WRTO].

In wraparound mode, the QSPI cycles through the queue continuously, even while requesting interrupt service. QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in the receive RAM. Each time the end of the queue is reached,

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23-14 Freescale Semiconductor

Queued Serial Peripheral Interface (QSPI)

QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request. Additional interrupt requests during servicing can be prevented by clearing QIR[SPIFE].

There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or setting

QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended because this may abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and stops the first time it reaches the end of the queue after QWR[WREN] is cleared. After QWR[HALT] is set, the QSPI finishes the current transfer, then stops executing commands. After the QSPI stops, QDLYR[SPE] can be cleared.

23.5 Initialization/Application Information

The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of 5.188 MHz.

The QSPI RAM is set up for a queue of 12 transfers. All three QSPI_CS signals are used in this example.

1. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the falling clock edge, and a QSPI_CLK frequency of 5.188 MHz (assuming a 83.33-MHz internal bus clock).

2. Write QDLYR with the desired delays.

3. Write QIR with 0xD00F to enable write collision, abort bus errors, and clear any interrupts.

4. Write QAR with 0x0020 to select the first command RAM entry.

5. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00, 0x7B00,

0x7B00, 0x7B00, and 0x7B00 to set up four transfers for each chip select. The chip selects are active low in this example.

6. Write QAR with 0x0000 to select the first transmit RAM entry.

7. Write QDR with twelve 12-bit words of data.

8. Write QWR with 0x0B00 to set up a queue beginning at entry 0 and ending at entry 11.

9. Set QDLYR[SPE] to enable the transfers.

10. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are complete.

11. Write QAR with 0x0010 to select the first receive RAM entry.

12. Read QDR to get the received data for each transfer.

13. Repeat steps 5 through 13 to do another transfer.

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23-15

Queued Serial Peripheral Interface (QSPI)

23-16

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

Chapter 24 UART Modules

24.1 Introduction

This chapter describes the use of the three universal asynchronous receiver/transmitters (UARTs) and includes programming examples.

NOTE

The designation n appears throughout this section to refer to registers or signals associated with one of the three identical UART modules: UART0,

UART1, or UART2.

24.1.1 Overview

The internal bus clock can clock each of the three independent UARTs, eliminating the need for an external

UART clock. As

Figure 24-1

shows, each UART module interfaces directly to the CPU and consists of:

• Serial communication channel

• Programmable clock generation

• Interrupt control logic and DMA request logic

• Internal channel control logic

Internal Bus

Interrupt Request

(to Interrupt Controller)

Transmit DMA Request

Receive DMA Request

(To DMA Controller)

UART

UART Registers

Internal Channel

Control Logic

Interrupt Control

Logic

DMA Request

Logic

Serial

Communications

Channel

Programmable

Clock

Generation

Figure 24-1. UART Block Diagram

UnCTS

UnRTS

UnRXD

UnTXD

Internal Bus Clock (f sys/2

) or External Clock (DTnIN)

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Freescale Semiconductor 24-1

UART Modules

NOTE

The DTnIN pin can clock UARTn. However, if the timers are operating and the UART uses DTnIN as a clock source, input capture mode is not available for that timer.

The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus clock or an external clock using the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start, stop, and parity bits. It outputs the resulting stream on the transmitter serial data output (UnTXD). See

Section 24.4.2.1, “Transmitter

.”

The receiver converts serial data from the receiver serial data input (UnRXD) to parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the bus during read operations. The receiver may be polled, interrupt driven, or use DMA requests for servicing.

See Section 24.4.2.2, “Receiver

.”

NOTE

The GPIO module must be configured to enable the peripheral function of

the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”

) prior to configuring the UART module.

24.1.2 Features

The device contains three independent UART modules with:

• Each clocked by external clock or internal bus clock (eliminates need for an external UART clock)

• Full-duplex asynchronous/synchronous receiver/transmitter

• Quadruple-buffered receiver

• Double-buffered transmitter

• Independently programmable receiver and transmitter clock sources

• Programmable data format:

— 5–8 data bits plus parity

— Odd, even, no parity, or force parity

— One, one-and-a-half, or two stop bits

• Each serial channel programmable to normal (full-duplex), automatic echo, local loopback, or remote loopback mode

• Automatic wake-up mode for multidrop applications

• Four maskable interrupt conditions

• All three UARTs have DMA request capability

• Parity, framing, and overrun error detection

• False-start bit detection

• Line-break detection and generation

• Detection of breaks originating in the middle of a character

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24-2 Freescale Semiconductor

UART Modules

• Start/end break interrupt/status

24.2 External Signal Description

Table 24-1

briefly describes the UART module signals.

Table 24-1. UART Module External Signals

Signal

UnTXD

UnRXD

UnCTS

UnRTS

Description

Transmitter Serial Data Output. UnTXD is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on UnTXD on the falling edge of the clock source, with the least significant bit (lsb) sent first.

Receiver Serial Data Input. Data received on UnRXD is sampled on the rising edge of the clock source, with the lsb received first.

Clear-to- Send. This input can generate an interrupt on a change of state.

Request-to-Send. This output can be programmed to be negated or asserted automatically by the receiver or the transmitter. When connected to a transmitter’s UnCTS, UnRTS can control serial data flow.

Figure 24-2

shows a signal configuration for a UART/RS-232 interface.

RS-232 Transceiver UART

UnRTS

UnCTS

UnTXD

UnRXD

DI2

DO2

DI1

DO1

Figure 24-2. UART/RS-232 Interface

24.3 Memory Map/Register Definition

This section contains a detailed description of each register and its specific function. Flowcharts in

Section 24.5, “Initialization/Application Information

,” describe basic UART module programming.

Writing control bytes into the appropriate registers controls the operation of the UART module.

NOTE

UART registers are accessible only as bytes.

NOTE

Interrupt can mean an interrupt request asserted to the CPU or a DMA request.

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Freescale Semiconductor 24-3

UART Modules

Table 24-2. UART Module Memory Map

Address

UART0

UART1

UART2

Register

0xFC06_0000

0xFC06_4000

0xFC06_8000

UART Mode Registers

(UMR1n), (UMR2n)

0xFC06_000C

0xFC06_400C

0xFC06_800C

UART Receive Buffers (URBn)

UART Transmit Buffers (UTBn)

0xFC06_0010

0xFC06_4010

0xFC06_8010

UART Input Port Change Register (UIPCRn)

UART Auxiliary Control Register (UACRn)

Width

(bit)

0xFC06_0004

0xFC06_4004

0xFC06_8004

UART Status Register (USRn) 8

UART Clock Select Register

(UCSRn) 8

8 0xFC06_0008

0xFC06_4008

0xFC06_8008

UART Command Registers (UCRn)

Access Reset Value Section/Page

R/W

0x00

0xFF

0x00

See Section

0x00

0xFC06_0014

0xFC06_4014

0xFC06_8014

UART Interrupt Status Register (UISRn)

UART Interrupt Mask Register (UIMRn)

0xFC06_0018

0xFC06_4018

0xFC06_8018

UART Baud Rate Generator Register (UBG1n)

0xFC06_001C

0xFC06_401C

0xFC06_801C

UART Baud Rate Generator Register (UBG2n)

0x00

24.3.10/24-13

24.3.11/24-15

0xFC06_0034

0xFC06_4034

0xFC06_8034

UART Input Port Register (UIPn) 8 R 0xFF

24.3.12/24-15

0xFC06_0038

0xFC06_4038

0xFC06_8038

UART Output Port Bit Set Command Register (UOP1n) 8 W

0x00

0xFC06_003C

0xFC06_403C

0xFC06_803C

UART Output Port Bit Reset Command Register (UOP0n) 8 W

0x00

Section 24.3.5, “UART Command

UMR1n, UMR2n, and UCSRn must be changed only after the receiver/transmitter is issued a software reset command. If operation is not disabled, undesirable results may occur.

Reading this register results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed.

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24-4 Freescale Semiconductor

UART Modules

24.3.1 UART Mode Registers 1 (UMR1n)

The UMR1n registers control UART module configuration. UMR1n can be read or written when the mode register pointer points to it, at RESET or after a

RESET MODE REGISTER POINTER

command using

UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.

Access: User read/write

Address: 0xFC06_0000 (UMR10)

0xFC06_4000 (UMR11)

0xFC06_8000 (UMR12)

1 0 7 6 5 4 3

RXRTS

RXIRQ/

FFULL

ERR PM

Reset: 0 0 0 0 0

After UMR1n is read or written, the pointer points to UMR2n

Figure 24-3. UART Mode Registers 1 (UMR1n)

Table 24-3. UMR1n Field Descriptions

B/C

Field Description

RXRTS

Receiver request-to-send. Allows the UnRTS output to control the UnCTS input of the transmitting device to prevent receiver overrun. If the receiver and transmitter are incorrectly programmed for UnRTS control, UnRTS control is disabled for both. Transmitter RTS control is configured in UMR2n[TXRTS].

0 The receiver has no effect on UnRTS.

1 When a valid start bit is received, UnRTS is negated if the UART's FIFO is full. UnRTS is reasserted when the

FIFO has an empty position available.

RXIRQ/

FFULL

Receiver interrupt select.

0 RXRDY is the source generating interrupt or DMA requests.

1 FFULL is the source generating interrupt or DMA requests.

ERR

4–3

Error mode. Configures the FIFO status bits, USRn[RB,FE,PE].

0 Character mode. The USRn values reflect the status of the character at the top of the FIFO. ERR must be 0 for correct A/D flag information when in multidrop mode.

1 Block mode. The USRn values are the logical OR of the status for all characters reaching the top of the FIFO since the last

RESET ERROR STATUS

command for the UART was issued. See

Registers (UCRn) .”

Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below.

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UART Modules

Table 24-3. UMR1n Field Descriptions (continued)

Field

Description

Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or address character is transmitted (PM = 11).

Parity Mode

With parity

Force parity

No parity

Multidrop mode

Parity Type (PT= 0) Parity Type (PT= 1)

Even parity

Low parity

Odd parity

High parity

N/A

Data character Address character

1–0

B/C

Bits per character. Selects the number of data bits per character to be sent. The values shown do not include start, parity, or stop bits.

00 5 bits

01 6 bits

10 7 bits

11 8 bits

24.3.2 UART Mode Register 2 (UMR2n)

The UMR2n registers control UART module configuration. UMR2n can be read or written when the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses do not update the pointer.

Access: User read/write

Address: 0xFC06_0000 (UMR20)

0xFC06_4000 (UMR21)

0xFC06_8000 (UMR22)

7 6 5 4 3

CM TXRTS TXCTS

Reset: 0 0 0 0 0

After UMR1n is read or written, the pointer points to UMR2n

Figure 24-4. UART Mode Registers 2 (UMR2n)

24-6

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Freescale Semiconductor

UART Modules

Table 24-4. UMR2n Field Descriptions

Field Description

7–6

Channel mode. Selects a channel mode. Section 24.4.3, “Looping Modes ,” describes individual modes.

00 Normal

01 Automatic echo

10 Local loopback

11 Remote loopback

TXRTS

Transmitter ready-to-send. Controls negation of UnRTS to automatically terminate a message transmission.

Attempting to program a receiver and transmitter in the same UART for UnRTS control is not permitted and disables

UnRTS control for both.

0 The transmitter has no effect on UnRTS.

1 In applications where the transmitter is disabled after transmission completes, setting this bit automatically clears

UOP[RTS] one bit time after any characters in the transmitter shift and holding registers are completely sent, including the programmed number of stop bits.

TXCTS

Transmitter clear-to-send. If TXCTS and TXRTS are set, TXCTS controls the operation of the transmitter.

0 UnCTS has no effect on the transmitter.

1 Enables clear-to-send operation. The transmitter checks the state of UnCTS each time it is ready to send a character. If UnCTS is asserted, the character is sent; if it is deasserted, the signal UnTXD remains in the high state and transmission is delayed until UnCTS is asserted. Changes in UnCTS as a character is being sent do not affect its transmission.

3–0

Stop-bit length control. Selects length of stop bit appended to the transmitted character. Stop-bit lengths of 9/16 to

2 bits are programmable for 6–8 bit characters. Lengths of 1-1/16 to 2 bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high condition at the center of the first stop-bit position, one bit time after the last data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing bit 3 selects one stop bit and setting bit 3 selects two stop bits for transmission.

0000

0001

0010

0011

0100

0101

0110

0111

5 Bits 6–8 Bits

1.063

1.125

1.188

1.250

1.313

1.375

1.438

1.500

0.563

0.625

0.688

0.750

0.813

0.875

0.938

1.000

1000

1001

1010

1011

1100

1101

1110

1111

5–8 Bits

1.563

1.625

1.688

1.750

1.813

1.875

1.938

2.000

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UART Modules

24.3.3 UART Status Registers (USRn)

The USRn registers show the status of the transmitter, the receiver, and the FIFO.

Address: 0xFC06_0004 (USR0)

0xFC06_4004 (USR1)

0xFC06_8004 (USR2)

FE R

Reset: 0

TXEMP

TXRDY

0 0 0 0

Figure 24-5. UART Status Registers (USRn)

Table 24-5. USRn Field Descriptions

Access: User read-only

FFULL

RXRDY

Field Description

Received break. The received break circuit detects breaks originating in the middle of a received character. However, a break in the middle of a character must persist until the end of the next detected character time.

0 No break was received.

1 An all-zero character of the programmed length was received without a stop bit. Only a single FIFO position is occupied when a break is received. Further entries to the FIFO are inhibited until UnRXD returns to the high state for at least one-half bit time, which equals two successive edges of the UART clock. RB is valid only when RXRDY is set.

Framing error.

0 No framing error occurred.

1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RXRDY is set.

Parity error. Valid only if RXRDY is set.

0 No parity error occurred.

1 If UMR1n[PM] equals 0x (with parity or force parity), the corresponding character in the FIFO was received with incorrect parity. If UMR1n[PM] equals 11 (multidrop), PE stores the received address or data (A/D) bit. PE is valid only when RXRDY is set.

Overrun error. Indicates whether an overrun occurs.

0 No overrun occurred.

1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. The

RESET ERROR STATUS

command in UCRn clears OE.

TEMP

TXRDY

Transmitter empty.

0 The transmit buffer is not empty. A character is shifted out, or the transmitter is disabled. The transmitter is enabled/disabled by programming UCRn[TC].

1 The transmitter has underrun (the transmitter holding register and transmitter shift registers are empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission.

Transmitter ready.

0 The CPU loaded the transmitter holding register, or the transmitter is disabled.

1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent.

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UART Modules

Table 24-5. USRn Field Descriptions (continued)

Field Description

FFULL

FIFO full.

0 The FIFO is not full but may hold up to two unread characters.

1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full are lost.

RXRDY

Receiver ready.

0 The CPU has read the receive buffer and no characters remain in the FIFO after this read.

1 One or more characters were received and are waiting in the receive buffer FIFO.

24.3.4 UART Clock Select Registers (UCSRn)

The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal bus clock as the clocking source for the transmitter and receiver. See

Section 24.4.1, “Transmitter/Receiver

Clock Source

.” The transmitter and receiver can use different clock sources. To use the internal bus clock for both, set UCSRn to 0xDD.

Field

7–4

RCS

Address: 0xFC06_0004 (UCSR0)

0xFC06_4004 (UCSR1)

0xFC06_8004 (UCSR2)

Access: User write-only

7 6 5 4 3 2 1 0

Reset:

RCS

See Note

TCS

See Note

Note: The RCS and TCS reset values are set so the receiver and transmiter use the prescaled internal bus clock as their clock source.

Figure 24-6. UART Clock Select Registers (UCSRn)

3–0

TCS

Table 24-6. UCSRn Field Descriptions

Description

Receiver clock select. Selects the clock source for the receiver.

1101 Prescaled internal bus clock (f sys/2

)

1110 DTnIN divided by 16

1111 DTnIN

Transmitter clock select. Selects the clock source for the transmitter.

1101 Prescaled internal bus clock (f sys/2

)

1110 DTnIN divided by 16

1111 DTnIN

24.3.5 UART Command Registers (UCRn)

The UCRs supply commands to the UART. Only multiple commands that do not conflict can be specified in a single write to a UCRn. For example,

RESET TRANSMITTER

and

ENABLE TRANSMITTER

cannot be specified in one command.

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Freescale Semiconductor 24-9

UART Modules

Address: 0xFC06_0008 (UCR0)

0xFC06_4008 (UCR1)

0xFC06_8008 (UCR2)

7 6

Reset:

5 4 3 2

MISC

0 0 0

Figure 24-7. UART Command Registers (UCRn)

Access: User write-only

Table 24-7

describes UCRn fields and commands. Examples in Section 24.4.2, “Transmitter and Receiver

Operating Modes

,” show how these commands are used.

Table 24-7. UCRn Field Descriptions

Field

6–4

MISC

Reserved, must be cleared.

MISC Field (this field selects a single command)

Description

Command Description

000

NO COMMAND

—

001

RESET MODE

Causes the mode register pointer to point to UMR1n.

010

011

111

RESET

TRANSMITTER

STOP

RECEIVER

BREAK

Immediately disables the receiver, clears USRn[FFULL,RXRDY], and reinitializes the receiver FIFO pointer. No other registers are altered. Because it places the receiver in a known state, use this command instead of

RECEIVER DISABLE

when reconfiguring the receiver.

Immediately disables the transmitter and clears USRn[TXEMP,TXRDY]. No other registers are altered. Because it places the transmitter in a known state, use this command instead of

TRANSMITTER DISABLE

when reconfiguring the transmitter.

Clears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after a data block is received.

100

RESET ERROR

STATUS

101

RESET BREAK

–

CHANGE INTERRUPT

Clears the delta break bit, UISRn[DB].

110

START BREAK

Forces UnTXD low. If the transmitter is empty, break may be delayed up to one bit time. If the transmitter is active, break starts when character transmission completes. Break is delayed until any character in the transmitter shift register is sent. Any character in the transmitter holding register is sent after the break.

Transmitter must be enabled for the command to be accepted. This command ignores the state of UnCTS.

Causes UnTXD to go high (mark) within two bit times. Any characters in the transmit buffer are sent.

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UART Modules

Table 24-7. UCRn Field Descriptions (continued)

Field

3–2

Description

Transmit command field. Selects a single transmit command.

Command Description

NO ACTION TAKEN

Causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled.

TRANSMITTER

ENABLE

Enables operation of the UART’s transmitter. USRn[TXEMP,TXRDY] are set. If the transmitter is already enabled, this command has no effect.

TRANSMITTER

DISABLE

11 —

Terminates transmitter operation and clears USRn[TXEMP,TXRDY]. If a character is being sent when the transmitter is disabled, transmission completes before the transmitter becomes inactive. If the transmitter is already disabled, the command has no effect.

Reserved, do not use.

1–0

Receive command field. Selects a single receive command.

Command Description

NO ACTION TAKEN

Causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled.

RECEIVER ENABLE

If the UART module is not in multidrop mode (UMR1n[PM]

≠

11),

RECEIVER ENABLE enables the UART's receiver and forces it into search-for-start-bit state. If the receiver is already enabled, this command has no effect.

RECEIVER DISABLE

Disables the receiver immediately. Any character being received is lost. The command does not affect receiver status bits or other control registers. If the

UART module is programmed for local loopback or multidrop mode, the receiver operates even though this command is selected. If the receiver is already disabled, the command has no effect.

11 — Reserved, do not use.

24.3.6 UART Receive Buffers (URBn)

The receive buffers contain one serial shift register and three receiver holding registers, which act as a

FIFO. UnRXD is connected to the serial shift register. The CPU reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift register is full (see

Figure 24-18

). RB contains the character in the receiver.

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MCF5208 Reference Manual, Rev 2

24-11

UART Modules

Address: 0xFC06_000C (URB0)

0xFC06_400C (URB1)

0xFC06_800C (URB2)

7 6

Reset: 1

5 4

3 2

1 1 1 1

Figure 24-8. UART Receive Buffer (URBn)

Access: User read-only

24.3.7 UART Transmit Buffers (UTBn)

The transmit buffers consist of the transmitter holding register and the transmitter shift register. The holding register accepts characters from the bus master if UART’s USRn[TXRDY] is set. A write to the transmit buffer clears USRn[TXRDY], inhibiting any more characters until the shift register can accept more data. When the shift register is empty, it checks if the holding register has a valid character to be sent

(TXRDY = 0). If there is a valid character, the shift register loads it and sets USRn[TXRDY] again. Writes to the transmit buffer when the UART’s TXRDY is cleared and the transmitter is disabled have no effect on the transmit buffer.

Figure 24-9

shows UTBn. TB contains the character in the transmit buffer.

Access: User write-only Address: 0xFC06_000C (UTB0)

0xFC06_400C (UTB1)

0xFC06_800C (UTB2)

7 6

Reset: 0

5 4 3 2

0 0 0

Figure 24-9. UART Transmit Buffer (UTBn)

24.3.8 UART Input Port Change Registers (UIPCRn)

The UIPCRs hold the current state and the change-of-state for UnCTS.

Address: 0xFC06_0010 (UIPCR0)

0xFC06_4010 (UIPCR1)

0xFC06_8010 (UIPCR2)

0 R

Reset: 0

COS

0 0 0 1 1

Figure 24-10. UART Input Port Changed Registers (UIPCRn)

Access: User read-only

CTS

UnCTS

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UART Modules

Table 24-8. UIPCRn Field Descriptions

Field

7–5

COS

3–1

CTS

Description

Reserved

Change of state (high-to-low or low-to-high transition).

0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].

1 A change-of-state longer than 25–50

μ s occurred on the UnCTS input. UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected.

Reserved

Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the state of UnCTS. If

UnCTS is detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled.

0 The current state of the UnCTS input is asserted.

1 The current state of the UnCTS input is deasserted.

24.3.9 UART Auxiliary Control Register (UACRn)

The UACRs control the input enable.

Address: 0xFC06_0010 (UACR0)

0xFC06_4010 (UACR1)

0xFC06_8010 (UACR2)

7 6

Reset:

Figure 24-11. UART Auxiliary Control Registers (UACRn)

Access: User write-only

IEC

Field

7–1

IEC

Table 24-9. UACRn Field Descriptions

Description

Reserved, must be cleared.

Input enable control.

0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].

1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition on the

UnCTS input (if UIMRn[COS] = 1).

24.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)

The UISRs provide status for all potential interrupt sources. UISRn contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, internal interrupt output is asserted. If a UIMRn bit is cleared, state of the corresponding UISRn bit has no effect on the output.

The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits.

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UART Modules

NOTE

True status is provided in the UISRn regardless of UIMRn settings. UISRn is cleared when the UART module is reset.

Address: 0xFC06_0014 (UISR0)

0xFC06_4014 (UISR1)

0xFC06_8014 (UISR2)

(UISRn)

(UIMRn)

Reset:

Access: User read/write

COS

FFULL/

RXRDY

FFULL/

RXRDY

0 0 0 0 0 0

Figure 24-12. UART Interrupt Status/Mask Registers (UISRn/UIMRn)

TXRDY

Table 24-10. UISRn/UIMRn Field Descriptions

Field Description

COS

Change-of-state.

0 UIPCRn[COS] is not selected.

1 Change-of-state occurred on UnCTS and was programmed in UACRn[IEC] to cause an interrupt.

Reserved, must be cleared.

6–3

Delta break.

0 No new break-change condition to report.

Section 24.3.5, “UART Command Registers (UCRn) ,” describes the

RESET BREAK

CHANGE INTERRUPT

command.

1 The receiver detected the beginning or end of a received break.

FFULL/

RXRDY

Status of FIFO or receiver, depending on UMR1[FFULL/RXRDY] bit. Duplicate of USRn[FIFO] and USRn[RXRDY]

UMR1n[FFULL/RXRDY]

UIMRn

[FFULL/RXRDY]

UISRn

[FFULL/RXRDY]

0 (RXRDY) 1 (FIFO)

Receiver not ready

Receiver is ready,

Do not interrupt

Receiver is ready, interrupt

FIFO not full

FIFO is full,

Do not interrupt

FIFO is full, interrupt

TXRDY

Transmitter ready. This bit is the duplication of USRn[TXRDY].

0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TXRDY is cleared are not sent.

1 The transmitter holding register is empty and ready to be loaded with a character.

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UART Modules

24.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)

The UBG1n registers hold the MSB, and the UBG2n registers hold the LSB of the preload value. UBG1n and UBG2n concatenate to provide a divider to the internal bus clock for transmitter/receiver operation,

as described in Section 24.4.1.2.1, “Internal Bus Clock Baud Rates .”

Address: 0xFC06_0018 (UBG10)

0xFC06_4018 (UBG11)

0xFC06_8018 (UBG12)

7 6

Reset: 0 0

4 3

Divider MSB

Figure 24-13. UART Baud Rate Generator Registers (UBG1n)

Access: User write-only

Address: 0xFC06_001C (UBG20)

0xFC06_401C (UBG21)

0xFC06_801C (UBG22)

7 6

Reset:

5 4 3 2

Access: User write-only

Divider LSB

0 0 0 0 0

Figure 24-14. UART Baud Rate Generator Registers (UBG2n)

NOTE

The minimum value loaded on the concatenation of UBG1n with UBG2n is

0x0002. The UBG2n reset value of 0x00 is invalid and must be written to before the UART transmitter or receiver are enabled. UBG1n and UBG2n are write-only and cannot be read by the CPU.

24.3.12 UART Input Port Register (UIPn)

The UIPn registers show the current state of the UnCTS input.

Address: 0xFC06_0034 (UIP0)

0xFC06_4034 (UIP1)

0xFC06_8034 (UIP2)

1 R

Reset: 1

1 1 1 1 1

Figure 24-15. UART Input Port Registers (UIPn)

Access: User read-only

CTS

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UART Modules

Table 24-11. UIPn Field Descriptions

Field

7–1

CTS

Description

Reserved

Current state of clear-to-send. The UnCTS value is latched and reflects the state of the input pin when UIPn is read.

Note: This bit has the same function and value as UIPCRn[CTS].

0 The current state of the UnCTS input is logic 0.

1 The current state of the UnCTS input is logic 1.

24.3.13 UART Output Port Command Registers (UOP1n/UOP0n)

The UnRTS output can be asserted by writing a 1 to UOP1n[RTS] and negated by writing a 1 to

UOP0n[RTS].

Field

7–1

RTS

Address: 0xFC06_0038 (UOP10)

0xFC06_003C (UOP00)

0xFC06_4038 (UOP11)

0xFC06_403C (UOP01)

0xFC06_8038 (UOP12)

0xFC06_803C (UOP02)

7 6

Reset:

Access: User write-only

Figure 24-16. UART Output Port Command Registers (UOP1n/UOP0n)

RTS

Table 24-12. UOP1n/UOP0n Field Descriptions

Description

Reserved, must be cleared.

Output port output. Controls assertion (UOP1)/negation (UOP0) of UnRTS output.

0 Not affected.

1 Asserts UnRTS in UOP1. Negates UnRTS in UOP0.

24.4 Functional Description

This section describes operation of the clock source generator, transmitter, and receiver.

24.4.1 Transmitter/Receiver Clock Source

The internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each UART. The 16-bit divider is used to produce standard UART baud rates.

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UART Modules

24.4.1.1

Programmable Divider

As Figure 24-17 shows, the UARTn transmitter and receiver can use the following clock sources:

• An external clock signal on the DTnIN pin.

When not divided,

DTnIN

provides a synchronous clock; when divided by 16, it is asynchronous.

• The internal bus clock supplies an asynchronous clock source divided by 32 and then divided by the 16-bit value programmed in UBG1n and UBG2n. See

Section 24.3.11, “UART Baud Rate

Generator Registers (UBG1n/UBG2n) .”

The choice of DTIN or internal bus clock is programmed in the UCSR.

DTnOUT

On-Chip

Timer Module

DTnIN

UnTXD

UART

Tx Buffer

Clocking sources programmed in UCSR

TIN

16-bit

Divider

Internal

Bus Clock f sys/2

UnRXD

Rx Buffer

Figure 24-17. Clocking Source Diagram

NOTE

If DTnIN is a clocking source for the timer or UART, that timer module cannot use DTnIN for timer input capture.

24.4.1.2

Calculating Baud Rates

The following sections describe how to calculate baud rates.

24.4.1.2.1

Internal Bus Clock Baud Rates

When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1n and UBG2n registers. The baud-rate calculation is:

Baudrate =

[ f

-----------------------------------

32 x divider

]

Eqn. 24-1

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Freescale Semiconductor 24-17

UART Modules

Using a 83-MHz internal bus clock and letting baud rate equal 9600, then

Divider =

[

83MHz

32 x 9600

]

= 270 decimal

)

0x010E hexadecimal

)

Therefore, UBG1n equals 0x01 and UBG2n equals 0x0E.

Eqn. 24-2

24.4.1.2.2

External Clock

An external source clock (DTnIN) passes through a divide-by-1 or 16 prescaler. If f extc

is the external clock frequency, baud rate can be described with this equation:

Baudrate = f

---------------------

(16 or 1)

Eqn. 24-3

24.4.2 Transmitter and Receiver Operating Modes

Figure 24-18

is a functional block diagram of the transmitter and receiver showing the command and operating registers, which are described generally in the following sections. For detailed descriptions, refer

to Section 24.3, “Memory Map/Register Definition

.”

UARTn

UART Command Register (UCRn) W

UART Mode Register 1 (UMR1n)

UART Mode Register 2 (UMR2n)

R/W

UART Status Register (USRn)

UART

Transmit Buffer

(UTBn)

(2 Registers)

Transmitter Holding Register

Transmitter Shift Register

UART Receive

Buffer (URBn)

(4 Registers)

Receiver Holding Register 1

Receiver Holding Register 2

Receiver Holding Register 3

Receiver Shift Register

FIFO

Figure 24-18. Transmitter and Receiver Functional Diagram

UnTXD

External

Interface

UnRXD

24.4.2.1

Transmitter

The transmitter is enabled through the UART command register (UCRn). When it is ready to accept a character, UART sets USRn[TXRDY]. The transmitter converts parallel data from the CPU to a serial bit stream on UnTXD. It automatically sends a start bit followed by the programmed number of data bits, an

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optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source.

After the stop bits are sent, if no new character is in the transmitter holding register, the UnTXD output remains high (mark condition) and the transmitter empty bit (USRn[TXEMP]) is set. Transmission resumes and TXEMP is cleared when the CPU loads a new character into the UART transmit buffer

(UTBn). If the transmitter receives a disable command, it continues until any character in the transmitter shift register is completely sent.

If the transmitter is reset through a software command, operation stops immediately (see

Section 24.3.5,

“UART Command Registers (UCRn)

”). The transmitter is reenabled through the UCRn to resume operation after a disable or software reset.

If the clear-to-send operation is enabled, UnCTS must be asserted for the character to be transmitted. If

UnCTS is negated in the middle of a transmission, the character in the shift register is sent and UnTXD remains in mark state until UnCTS is reasserted. If transmitter is forced to send a continuous low condition by issuing a

SEND BREAK

command, transmitter ignores the state of UnCTS.

If the transmitter is programmed to automatically negate UnRTS when a message transmission completes,

UnRTS must be asserted manually before a message is sent. In applications in which the transmitter is disabled after transmission is complete and UnRTS is appropriately programmed, UnRTS is negated one bit time after the character in the shift register is completely transmitted. The transmitter must be manually reenabled by reasserting UnRTS before the next message is sent.

Figure 24-19

shows the functional timing information for the transmitter.

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24-19

UART Modules

UnTXD

C1 in transmission

C2 C3 Break C4 C6

Transmitter

Enabled

USRn[TXRDY] internal module select

UnCTS

W W

C3 Start break

W W W

C4 Stop break

C5 not transmitted

UnRTS

Manually asserted by

BIT

SET

command

Cn = transmit characters

W = write

UMR2n[TXCTS] = 1

UMR2n[TXRTS] = 1

Figure 24-19. Transmitter Timing Diagram

Manually asserted

24.4.2.2

Receiver

The receiver is enabled through its UCRn, as described in Section 24.3.5, “UART Command Registers

(UCRn) .”

When the receiver detects a high-to-low (mark-to-space) transition of the start bit on UnRXD, the state of

UnRXD is sampled eight times on the edge of the bit time clock starting one-half clock after the transition

(asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). If

UnRXD is sampled high, start bit is invalid and the search for the valid start bit begins again.

If UnRXD remains low, a valid start bit is assumed. The receiver continues sampling the input at one-bit time intervals at the theoretical center of the bit until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. Data on the UnRXD input is sampled on the rising edge of the programmed clock source. The lsb is received first. The data then transfers to a receiver holding register and USRn[RXRDY] is set. If the character is less than 8 bits, the most significant unused bits in the receiver holding register are cleared.

After the stop bit is detected, receiver immediately looks for the next start bit. However, if a non-zero character is received without a stop bit (framing error) and UnRXD remains low for one-half of the bit period after the stop bit is sampled, receiver operates as if a new start bit were detected. Parity error,

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UART Modules

framing error, overrun error, and received break conditions set the respective PE, FE, OE, and RB error and break flags in the USRn at the received character boundary. They are valid only if USRn[RXRDY] is set.

If a break condition is detected (UnRXD is low for the entire character including the stop bit), a character of all 0s loads into the receiver holding register and USRn[RB,RXRDY] are set. UnRXD must return to a high condition for at least one-half bit time before a search for the next start bit begins.

The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. If the break begins in the middle of a character, receiver places the damaged character in the Rx FIFO and sets the corresponding USRn error bits and USRn[RXRDY]. Then, if the break lasts until the next character time, receiver places an all-zero character into the Rx FIFO and sets

USRn[RB,RXRDY].

Figure 24-20

shows receiver functional timing.

UnRXD

C1 C2 C3 C4 C5 C6 C7

C6, C7, and C8 is lost

Receiver

Enabled

USRn[RXRDY]

USRn[FFULL] internal module select

Status

Data

(C1)

C5 is lost

Overrun

USRn[OE]

UnRTS

Manually asserted first time, automatically negated if overrun occurs

UOP0[RTS] = 1

UMR2n[RXRTS] = 1

Figure 24-20. Receiver Timing Diagram

Status

Data

(C2)

Status

Data

Status

Data

(C3) (C4)

Reset by command

Automatically asserted when ready to receive

24.4.2.3

FIFO

The FIFO is used in the UART’s receive buffer logic. The FIFO consists of three receiver holding registers.

The receive buffer consists of the FIFO and a receiver shift register connected to the UnRXD (see

Figure 24-18

). Data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO. Therefore, data flowing from the receiver to the CPU is quadruple-buffered.

In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break

(RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By

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UART Modules

programming the ERR bit in the UART’s mode register (UMR1n), status is provided in character or block modes.

USRn[RXRDY] is set when at least one character is available to be read by the CPU. A read of the receive buffer produces an output of data from the top of the FIFO. After the read cycle, the data at the top of the

FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom of the FIFO. The FIFO-full status bit (FFULL) is set if all three positions are filled with data. The RXRDY or FFULL bit can be selected to cause an interrupt and TXRDY or RXRDY can be used to generate a DMA request.

The two error modes are selected by UMR1n[ERR]:

• In character mode (UMR1n[ERR] = 0), status is given in the USRn for the character at the top of the FIFO.

• In block mode, the USRn shows a logical OR of all characters reaching the top of the FIFO since the last RESET ERROR STATUS command. Status is updated as characters reach the top of the

FIFO. Block mode offers a data-reception speed advantage where the software overhead of error-checking each character cannot be tolerated. However, errors are not detected until the check is performed at the end of an entire message—the faulting character is not identified.

In either mode, reading the USRn does not affect the FIFO. The FIFO is popped only when the receive buffer is read. The USRn should be read before reading the receive buffer. If all three receiver holding registers are full, a new character is held in the receiver shift register until space is available. However, if a second new character is received, the contents of the character in the receiver shift register is lost, the

FIFOs are unaffected, and USRn[OE] is set when the receiver detects the start bit of the new overrunning character.

To support flow control, the receiver can be programmed to automatically negate and assert UnRTS, in which case the receiver automatically negates UnRTS when a valid start bit is detected and the FIFO is full. The receiver asserts UnRTS when a FIFO position becomes available; therefore, connecting UnRTS to the UnCTS input of the transmitting device can prevent overrun errors.

NOTE

The receiver continues reading characters in the FIFO if the receiver is disabled. If the receiver is reset, the FIFO, UnRTS control, all receiver status bits, interrupts, and DMA requests are reset. No more characters are received until the receiver is reenabled.

24.4.3 Looping Modes

The UART can be configured to operate in various looping modes. These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs and in

Section 24.3, “Memory Map/Register Definition.”

The UART’s transmitter and receiver should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted.

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24.4.3.1

Automatic Echo Mode

In automatic echo mode, shown in

Figure 24-21

, the UART automatically resends received data bit by bit.

The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled. In this mode, received data is clocked on the receiver clock and re-sent on UnTXD. The receiver must be enabled, but the transmitter need not be.

CPU

Disabled

Figure 24-21. Automatic Echo

UnTXD Output

Because the transmitter is inactive, USRn[TXEMP,TXRDY] is inactive and data is sent as it is received.

Received parity is checked but not recalculated for transmission. Character framing is also checked, but stop bits are sent as they are received. A received break is echoed as received until the next valid start bit is detected.

24.4.3.2

Local Loopback Mode

Figure 24-22

shows how UnTXD and UnRXD are internally connected in local loopback mode. This mode is for testing the operation of a UART by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations.

Disabled

UnRXD Input

CPU

Disabled

UnTXD Output

Figure 24-22. Local Loopback

Features of this local loopback mode are:

• Transmitter and CPU-to-receiver communications continue normally in this mode.

• UnRXD input data is ignored.

• UnTXD is held marking.

• The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be.

24.4.3.3

Remote Loopback Mode

In remote loopback mode, shown in Figure 24-23 , the UART automatically transmits received data bit by

bit on the UnTXD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote UART. For this mode, transmitter uses the receiver clock.

Because the receiver is not active, received data cannot be read by the CPU and all status conditions are inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are sent as they are received. A received break is echoed as received until next valid start bit is detected.

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Freescale Semiconductor 24-23

UART Modules

Disabled

CPU

Disabled

UnRXD Input

Disabled UnTXD Output

Figure 24-23. Remote Loopback

24.4.4 Multidrop Mode

Setting UMR1n[PM] programs the UART to operate in a wake-up mode for multidrop or multiprocessor applications. In this mode, a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations.

Although slave stations have their receivers disabled, they continuously monitor the master’s data stream.

When the master sends an address character, the slave receiver notifies its respective CPU by setting

USRn[RXRDY] and generating an interrupt (if programmed to do so). Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. Unaddressed slave stations continue monitoring the data stream. Data fields in the data stream are separated by an address character. After a slave receives a block of data, its CPU disables the receiver and repeats the process. Functional timing

information for multidrop mode is shown in Figure 24-24 .

24-24

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Freescale Semiconductor

UART Modules

UnTXD

A/D

ADD1 1

Master Station

A/D

Transmitter

Enabled

USRn[TXRDY] internal module select

UMR1n[PM] = 11

UMR1n[PT] = 1

ADD 1 C0

UMR1n[PT] = 0

UnRXD

A/D

ADD1 1

Peripheral Station

A/D

ADD 2

UMR1n[PT] = 1

Receiver

Enabled

A/D

ADD2 1

A/D

ADD2 1

A/D

USRn[RXRDY] internal module select

UMR1

[PM] = 11 ADD 1 Status Data

(C0)

Figure 24-24. Multidrop Mode Timing Diagram

Status Data

(ADD 2)

A character sent from the master station consists of a start bit, a programmed number of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. A/D equals 1 indicates an address character; A/D equals 0 indicates a data character. The polarity of A/D is selected through UMR1n[PT].

UMR1n should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer.

In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the RXRDY bit and loads the character into the receiver holding register FIFO provided the received A/D bit is a 1 (address tag). The character is discarded if the received A/D bit is 0 (data tag). If the receiver is enabled, all received characters are transferred to the CPU through the receiver holding register during read operations.

In either case, data bits load into the data portion of the FIFO while the A/D bit loads into the status portion of the FIFO normally used for a parity error (USRn[PE]).

Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode may continues containing error detection and correction information. If 8-bit characters are not required, one way to provide error detection is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character.

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 24-25

UART Modules

24.4.5 Bus Operation

This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module.

24.4.5.1

Read Cycles

The UART module responds to reads with byte data. Reserved registers return zeros.

24.4.5.2

Write Cycles

The UART module accepts write data as bytes only. Write cycles to read-only or reserved registers complete normally without an error termination, but data is ignored.

24.5 Initialization/Application Information

The software flowchart,

Figure 24-25

, consists of:

•

UART module initialization—These routines consist of SINIT and CHCHK (See Sheet 1 p. 24-29

and Sheet 2 p. 24-30). Before SINIT is called at system initialization, the calling routine allocates

2 words on the system FIFO. On return to the calling routine, SINIT passes UART status data on the FIFO. If SINIT finds no errors, the transmitter and receiver are enabled. SINIT calls CHCHK to perform the checks. When called, SINIT places the UART in local loopback mode and checks for the following errors:

— Transmitter never ready

— Receiver never ready

— Parity error

— Incorrect character received

•

I/O driver routine—This routine (See Sheet 4 p. 24-32 and Sheet 5 p. 24-33) consists of INCH, the

terminal input character routine which gets a character from the receiver, and OUTCH, which sends a character to the transmitter.

•

Interrupt handling—This consists of SIRQ (See Sheet 4 p. 24-32), which is executed after the

UART module generates an interrupt caused by a change-in-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor.

24.5.1 Interrupt and DMA Request Initialization

24.5.1.1

Setting up the UART to Generate Core Interrupts

The list below provides steps to properly initialize the UART to generate an interrupt request to the

processor’s interrupt controller. See Section 14.2.9.1, “Interrupt Sources,”

for details on interrupt assignments for the UART modules.

1. Initialize the appropriate ICRx register in the interrupt controller.

2. Unmask appropriate bits in IMR in the interrupt controller.

MCF5208 Reference Manual, Rev 2

24-26 Freescale Semiconductor

UART Modules

3. Unmask appropriate bits in the core’s status register (SR) to enable interrupts.

4. If TXRDY or RXRDY generates interrupt requests, verify that the corresponding UART DMA channels are not enabled.

5. Initialize interrupts in the UART, see

Table 24-13

Table 24-13. UART Interrupts

Register

UMR1n

UIMRn

Bit

Interrupt

RxIRQ

Change of State (COS)

Delta Break

RxFIFO Full

TXRDY

24.5.1.2

Setting up the UART to Request DMA Service

The UART is capable of generating two internal DMA request signals: transmit and receive.

The transmit DMA request signal is asserted when the TXRDY (transmitter ready) in the UART interrupt status register (UISRn[TXRDY]) is set. When the transmit DMA request signal is asserted, the DMA can initiate a data copy, reading the next character transmitted from memory and writing it into the UART transmit buffer (UTBn). This allows the DMA channel to stream data from memory to the UART for transmission without processor intervention. After the entire message has been moved into the UART, the

DMA would typically generate an end-of-data-transfer interrupt request to the CPU. The resulting interrupt service routine (ISR) could query the UART programming model to determine the end-of-transmission status.

Similarly, the receive DMA request signal is asserted when the FIFO full or receive ready

(FFULL/RXRDY) flag in the interrupt status register (UISRn[FFULL/RXRDY]) is set. When the receive

DMA request signal is asserted, the DMA can initiate a data move, reading the appropriate characters from the UART receive buffer (URBn) and storing them in memory. This allows the DMA channel to stream data from the UART receive buffer into memory without processor intervention. After the entire message has been moved from the UART, the DMA would typically generate an end-of-data-transfer interrupt request to the CPU. The resulting interrupt service routine (ISR) should query the UART programming model to determine the end-of-transmission status. In typical applications, the receive DMA request should be configured to use RXRDY directly (and not FFULL) to remove any complications related to retrieving the final characters from the FIFO buffer.

The implementation described in this section allows independent DMA processing of transmit and receive data while continuing to support interrupt notification to the processor for CTS change-of-state and delta break error managing.

Table 24-14

shows the DMA requests.

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 24-27

UART Modules

Register

UISRn

Bit

Table 24-14. UART DMA Requests

Receive DMA request

Transmit DMA request

DMA Request

24.5.2 UART Module Initialization Sequence

The following shows the UART module initialization sequence.

1. UCRn: a) Reset the receiver and transmitter.

b) Reset the mode pointer (MISC[2–0] = 0b001).

2. UIMRn: Enable the desired interrupt sources.

3. UACRn: Initialize the input enable control (IEC bit).

4. UCSRn: Select the receiver and transmitter clock. Use timer as source if required.

5. UMR1n: a) If preferred, program operation of receiver ready-to-send (RXRTS bit).

a) Select receiver-ready or FIFO-full notification (RXRDY/FFULL bit).

b) Select character or block error mode (ERR bit).

c) Select parity mode and type (PM and PT bits).

d) Select number of bits per character (B/Cx bits).

6. UMR2n: a) Select the mode of operation (CM bits).

b) If preferred, program operation of transmitter ready-to-send (TXRTS).

c) If preferred, program operation of clear-to-send (TXCTS bit).

d) Select stop-bit length (SB bits).

7. UCRn: Enable transmitter and/or receiver.

24-28

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

Serial Module

SINIT

Initiate:

Channel

Interrupts

CHK1

Call CHCHK

Save Channel

Status

Enable

Any

Errors?

Enable Receiver

Assert

Request To Send

SINITR

Return

Figure 24-25. UART Mode Programming Flowchart (Sheet 1 of 5)

UART Modules

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

24-29

UART Modules

CHCHK

Place Channel In

Local Loopback

Mode

Enable

Transmitter Clear

Status Word

TxCHK

Transmitter

Ready?

SNDCHR

Send Character

To Transmitter

RxCHK

Has

Character Been

Received?

Waited

Too Long?

Waited

Too Long?

Set Transmitter-

Never-ready Flag

Set Receiver-

Never-ready Flag

Figure 24-25. UART Mode Programming Flowchart (Sheet 2 of 5)

24-30

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

FRCHK

Have

Framing Error?

Set Framing

Error Flag

PRCHK

Have

Parity Error?

Set Parity

Error Flag

CHRCHK

Get Character

From Receiver

Same As

Transmitted

Character?

Set Incorrect

Character Flag

RSTCHN

Disable

Transmitter

Restore

To Original Mode

Return

Figure 24-25. UART Mode Programming Flowchart (Sheet 3 of 5)

UART Modules

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

24-31

UART Modules

ABRKI

SIRQ

Was

IRQ Caused

By Beginning

Of A Break?

Clear Change-in-

Break Status Bit

ABRKI1

Has

End-of-break

IRQ Arrived

Yet?

Clear Change-in-

Break Status Bit

Remove Break

Character From

Receiver FIFO

INCH

Does

Channel A

Receiver Have A

Character?

Place Character

In D0

Return

Replace Return

Address On System

Stack And Monitor

Warm Start Address

SIRQR

RTE

Figure 24-25. UART Mode Programming Flowchart (Sheet 4 of 5)

24-32

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

OUTCH

Transmitter

Ready?

Send Character

To Transmitter

Return

Figure 24-25. UART Mode Programming Flowchart (Sheet 5 of 5)

UART Modules

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

24-33

UART Modules

24-34

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

I

Chapter 25 C Interface

25.1 Introduction

This chapter describes the I

C module, clock synchronization, and I

C programming model registers. It also provides extensive programming examples.

25.1.1 Block Diagram

Figure 25-1

is a I

C module block diagram, illustrating the interaction of the registers described in

Section 25.2, “Memory Map/Register Definition”.

IRQ

Internal Bus

Address Data

Registers and Slave Interface

Address Decode Data MUX

C Frequency

Divider Register

(I2FDR)

Clock

Control

C Control

(I2CR)

Start, Stop, and

Arbitration

Control

C Status

(I2SR)

C Data

I/O Register

(I2DR)

C Address

(I2ADR)

In/Out

Data

Shift

Input

Sync

Address

Compare

Freescale Semiconductor

I2C_SCL I2C_SDA

Figure 25-1. I

C Module Block Diagram

MCF5208 Reference Manual, Rev 2

25-1

C Interface

25.1.2 Overview

C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications that require occasional communication between many devices over a short distance. The flexible I

C bus allows additional devices to connect to the bus for expansion and system development.

The interface operates up to 100 Kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of the internal bus clock divided by 20, with reduced bus loading. The maximum communication length and the number of devices connected are limited by a maximum bus capacitance of 400 pF.

The I

C system is a true multiple-master bus; it uses arbitration and collision detection to prevent data corruption in the event that multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer.

NOTE

The I

C module is compatible with the Philips I

C bus protocol. For information on system configuration, protocol, and restrictions, see The I

Bus Specification, Version 2.1.

NOTE

The GPIO module must be configured to enable the peripheral function of

the appropriate pins (refer to Chapter 13, “General Purpose I/O Module”

) prior to configuring the I

C module.

25.1.3 Features

The I

C module has these key features:

• Compatibility with I

C bus standard version 2.1

• Support for 3.3-V tolerant devices

• Multiple-master operation

• Software-programmable for one of 50 different serial clock frequencies

• Software-selectable acknowledge bit

• Interrupt-driven, byte-by-byte data transfer

• Arbitration-lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• START and STOP signal generation/detection

• Repeated START signal generation

• Acknowledge bit generation/detection

• Bus-busy detection

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25-2 Freescale Semiconductor

C Interface

25.2 Memory Map/Register Definition

The below table lists the configuration registers used in the I

C interface.

Table 25-1. I

C Module Memory Map

Address Register

0xFC05_8000 I

C Address Register (I2ADR)

0xFC05_8004 I

C Frequency Divider Register (I2FDR)

0xFC05_8008 I

C Control Register (I2CR)

0xFC05_800C I

C Status Register (I2SR)

0xFC05_8010 I

C Data I/O Register (I2DR)

Access Reset Value Section/Page

R/W

0x00

0x81

0x00

25.2.1 I

C Address Register (I2ADR)

I2ADR holds the address the I

C responds to when addressed as a slave. It is not the address sent on the bus during the address transfer when the module is performing a master transfer.

Field

7–1

ADR

Address: 0xFC05_8000 (I2ADR)

7 6

Reset: 0

5 4

ADR

3 2

0 0 0 0

Figure 25-2. I

C Address Register (I2ADR)

Access: User read/write

1 0

0 0

Table 25-2. I2ADR Field Descriptions

Description

Slave address. Contains the specific slave address to be used by the I

C module. Slave mode is the default I

C mode for an address match on the bus.

Reserved, must be cleared.

25.2.2 I

C Frequency Divider Register (I2FDR)

The I2FDR, shown in Figure 25-3 , provides a programmable prescaler to configure the I

C clock for bit-rate selection.

Address: 0xFC05_8004 (I2FDR)

0 R

Reset: 0

5 4 3

0 0 0 0 0

Figure 25-3. I

C Frequency Divider Register (I2FDR)

Access: User read/write

1 0

0 0

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 25-3

C Interface

Table 25-3. I2FDR Field Descriptions

Field

7–6

5–0

Description

Reserved, must be cleared.

C clock rate. Prescales the clock for bit-rate selection. The serial bit clock frequency is equal to the internal bus clock divided by the divider shown below. Due to potentially slow I2C_SCL and I2C_SDA rise and fall times, bus signals are sampled at the prescaler frequency.

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Divider

144

160

192

240

104

128

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

Divider IC

1152

1280

1536

1920

2304

2560

3072

3840

576

640

768

960

288

320

384

480

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

Divider

112

128

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

Divider

640

768

896

1024

1280

1536

1792

2048

320

384

448

512

160

192

224

256

25.2.3 I

C Control Register (I2CR)

I2CR enables the I

C module and the I

C interrupt. It also contains bits that govern operation as a slave or a master.

Address: 0xFC05_8008 (I2CR)

7 6

Reset:

IEN

IIEN

MSTA

MTX

TXAK

RSTA

0 0 0

Figure 25-4. I

C Control Register (I2CR)

Access: User read/write

0 0

MCF5208 Reference Manual, Rev 2

25-4 Freescale Semiconductor

C Interface

Table 25-4. I2CR Field Descriptions

Field

IEN

IIEN

MSTA

MTX

TXAK

RSTA

Description

C enable. Controls the software reset of the entire I

C module. If the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is detected.

Master mode is not aware that the bus is busy; initiating a start cycle may corrupt the current bus cycle, ultimately causing the current master or the I

C module to lose arbitration, after which bus operation returns to normal.

0 The I

C module is disabled, but registers can be accessed.

1 The I

C module is enabled. This bit must be set before any other I2CR bits have any effect.

C interrupt enable.

0 I

C module interrupts are disabled, but currently pending interrupt condition is not cleared.

1 I

C module interrupts are enabled. An I

C interrupt occurs if I2SR[IIF] is also set.

Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a STOP signal.

0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.

1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.

Transmit/receive mode select bit. Selects the direction of master and slave transfers.

0 Receive

1 Transmit. When the device is addressed as a slave, software must set MTX according to I2SR[SRW]. In master mode, MTX must be set according to the type of transfer required. Therefore, when the MCU addresses a slave device, MTX is always 1.

Transmit acknowledge enable. Specifies the value driven onto I2C_SDA during acknowledge cycles for master and slave receivers. Writing TXAK applies only when the I

C bus is a receiver.

0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.

1 No acknowledge signal response is sent (acknowledge bit = 1).

Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration.

0 No repeat start

1 Generates a repeated START condition.

Reserved, must be cleared.

25.2.4 I

C Status Register (I2SR)

I2SR contains bits that indicate transaction direction and status.

Address: 0xFC05_800C (I2SR)

ICF

IAAS R

Reset: 1 0

IBB

IAL

SRW

0 0 0

Figure 25-5. I

C Status Register (I2SR)

Access: User read/write

1 0

RXAK

IIF

0 1

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MCF5208 Reference Manual, Rev 2

25-5

C Interface

Table 25-5. I2SR Field Descriptions

Field

ICF

IAAS

IBB

IAL

SRW

IIF

RXAK

Description

C Data transferring bit. While one byte of data is transferred, ICF is cleared.

0 Transfer in progress

1 Transfer complete. Set by falling edge of ninth clock of a byte transfer.

C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit.

0 Not addressed.

1 Addressed as a slave. Set when its own address (IADR) matches the calling address.

C bus busy bit. Indicates the status of the bus.

0 Bus is idle. If a STOP signal is detected, IBB is cleared.

1 Bus is busy. When START is detected, IBB is set.

C arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by writing zero to it.)

• I2C_SDA sampled low when the master drives high during an address or data-transmit cycle.

• I2C_SDA sampled low when the master drives high during the acknowledge bit of a data-receive cycle.

• A start cycle is attempted when the bus is busy.

• A repeated start cycle is requested in slave mode.

• A stop condition is detected when the master did not request it.

Reserved, must be cleared.

Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling address sent from the master. SRW is valid only when a complete transfer has occurred, no other transfers have been initiated, and the I

C module is a slave and has an address match.

0 Slave receive, master writing to slave.

1 Slave transmit, master reading from slave.

C interrupt. Must be cleared by software by writing a 0 in the interrupt routine.

0 No I

C interrupt pending

1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of the following occurs:

• Complete one byte transfer (set at the falling edge of the ninth clock)

• Reception of a calling address that matches its own specific address in slave-receive mode

• Arbitration lost

Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle.

0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus

1 No acknowledge signal was detected at the ninth clock.

25.2.5 I

C Data I/O Register (I2DR)

In master-receive mode, reading I2DR allows a read to occur and for the next data byte to be received. In slave mode, the same function is available after the I

C has received its slave address.

25-6

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

C Interface

Address: 0xFC05_8010 (I2DR)

7 6

Reset: 0 0

5 4

DATA

3 2

0 0 0

Figure 25-6. I

C Data I/O Register (I2DR)

Access: User read/write

1 0

0 0

Field

7–0

DATA

Table 25-6. I2DR Field Description

Description

C data. When data is written to this register in master transmit mode, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates the reception of the next byte of data. In slave mode, the same functions are available after an address match has occurred.

Note: In master transmit mode, the first byte of data written to I2DR following assertion of I2CR[MSTA] is used for the address transfer and should comprise the calling address (in position D7–D1) concatenated with the required R/W bit (in position D0). This bit (D0) is not automatically appended by the hardware, software must provide the appropriate R/W bit.

Note: I2CR[MSTA] generates a start when a master does not already own the bus. I2CR[RSTA] generates a start

(restart) without the master first issuing a stop (i.e., the master already owns the bus). To start the read of data, a dummy read to this register starts the read process from the slave. The next read of the I2DR register contains the actual data.

25.3 Functional Description

The I

C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL) for data transfer. For

C compliance, all devices connected to these two signals must have open drain or open collector outputs.

The logic AND function is exercised on both lines with external pull-up resistors.

Out of reset, the I

C default state is as a slave receiver. Therefore, when not programmed to be a master or responding to a slave transmit address, the I

C module should return to the default slave receiver state. See

Section 25.4.1, “Initialization Sequence,”

for exceptions.

Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer, and STOP signal. These are discussed in the following sections.

25.3.1 START Signal

When no other device is bus master (I2C_SCL and I2C_SDA lines are at logic high), a device can initiate communication by sending a START signal (see A in

Figure 25-7

). A START signal is defined as a high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves.

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

25-7

C Interface

I2C_SCL msb

1 2 3 4 5 6 7

Interrupt bit set

(Byte complete) lsb

I2C_

SCL held low while

Interrupt is serviced msb

2 3 4 5 6 7 lsb

I2C_SDA

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

START

Signal

Calling Address

XXX D7 D6 D5 D4 D3 D2 D1 D0

Data Byte

R/W

ACK

Bit

Figure 25-7. I

C Standard Communication Protocol

ACK

Bit

STOP

Signal

25.3.2 Slave Address Transmission

The master sends the slave address in the first byte after the START signal (B). After the seven-bit calling address, it sends the R/W bit (C), which tells the slave data transfer direction (0 equals write transfer, 1 equals read transfer).

Each slave must have a unique address. An I

C master must not transmit its own slave address; it cannot be master and slave at the same time.

The slave whose address matches that sent by the master pulls I2C_SDA low at the ninth serial clock (D) to return an acknowledge bit.

25.3.3 Data Transfer

When successful slave addressing is achieved, data transfer can proceed (see E in Figure 25-7 ) on a

byte-by-byte basis in the direction specified by the R/W bit sent by the calling master.

Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high, as

Figure 25-7

shows. I2C_SCL is pulsed once for each data bit, with the msb being sent first. The receiving device must acknowledge each byte by pulling I2C_SDA low at the ninth clock; therefore, a data byte

transfer takes nine clock pulses. See Figure 25-8 .

I2C_

SCL held low while

Interrupt is serviced

I2C_SCL

1 2 3 4 5 6 7 8 9 1 2 3

Interrupt Bit Set

(Byte Complete)

4 5 6 7 8 9

I2C_SDA

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1

Bit0

R/W

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Slave Address Data Byte

START

Signal

ACK from

Receiver

Figure 25-8. Data Transfer

ACK Bit

STOP

Signal

MCF5208 Reference Manual, Rev 2

25-8 Freescale Semiconductor

C Interface

25.3.4 Acknowledge

The transmitter releases the I2C_SDA line high during the acknowledge clock pulse as shown in

Figure 25-9

. The receiver pulls down the I2C_SDA line during the acknowledge clock pulse so that it remains stable low during the high period of the clock pulse.

If it does not acknowledge the master, the slave receiver must leave I2C_SDA high. The master can then generate a STOP signal to abort data transfer or generate a START signal (repeated start, shown in

Figure 25-10

and discussed in Section 25.3.6, “Repeated START”

) to start a new calling sequence.

I2C_SCL

I2C_SDA by Transmitter

1 2 3 4 5 6 7 8

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1

Bit0

R/W

I2C_SDA by Receiver

START Signal

Figure 25-9. Acknowledgement by Receiver

ACK

If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means end-of-data to the slave. The slave releases I2C_SDA for the master to generate a STOP or START signal

(

Figure 25-9

25.3.5 STOP Signal

The master can terminate communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of I2C_SDA while I2C_SCL is at logical high (see F in

Figure 25-7

The master can generate a STOP even if the slave has generated an acknowledgment, at which point the slave must release the bus. The master may also generate a START signal following a calling address, without first generating a STOP signal. Refer to

Section 25.3.6, “Repeated START.”

25.3.6 Repeated START

A repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication, as shown in

Figure 25-10

. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

25-9

C Interface

I2C_SCL msb

1 2 3 4 5 6 lsb

7 8 9 msb

1 2 3 4 5 6 lsb

7 8 9

I2C_SDA

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

START

Signal

Calling Address

R/W

ACK

Bit

Repeated

START

Signal

New Calling Address

R/W

ACK

Bit

STOP

Signal

Figure 25-10. Repeated START

Various combinations of read/write formats are then possible:

• The first example in

Figure 25-11 is the case of master-transmitter transmitting to slave-receiver.

The transfer direction is not changed.

• The second example in

Figure 25-11 is the master reading the slave immediately after the first byte.

At the moment of the first acknowledge, the master-transmitter becomes a master-receiver and the slave-receiver becomes slave-transmitter.

•

In the third example in Figure 25-11

, START condition and slave address are repeated using the repeated START signal. This is to communicate with same slave in a different mode without releasing the bus. The master transmits data to the slave first, and then the master reads data from slave by reversing the R/W bit.

ST = Start

SP = Stop

A = Acknowledge (

I2C_

SDA low)

A = Not Acknowledge (

I2C_

SDA high)

Rept ST = Repeated Start

Example 1:

R/W

From Master to Slave

From Slave to Master

7bit Slave Address 0 A

Data

A Data A/A SP

Example 2:

ST 7bit Slave Address

Note: No acknowledge on the last byte

Example 3:

7-bit Slave

Address

R/W

1 A

Data

R/W

1 A

Data

7-bit Slave

Address

A Data

R/W

Data

A SP

A Data

A/A SP

Master Reads from Slave

Master Writes to Slave

Figure 25-11. Data Transfer, Combined Format

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C Interface

25.3.7 Clock Synchronization and Arbitration

C is a true multi-master bus that allows more than one master connected to it. If two or more master devices simultaneously request control of the bus, a clock synchronization procedure determines the bus clock. Because wire-AND logic is performed on the I2C_SCL line, a high-to-low transition on the

I2C_SCL line affects all the devices connected on the bus. The devices start counting their low period and after a device’s clock has gone low, it holds the I2C_SCL line low until the clock high state is reached.

However, change of low to high in this device’s clock may not change the state of the I2C_SCL line if another device clock remains within its low period. Therefore, synchronized clock I2C_SCL is held low by the device with the longest low period.

Devices with shorter low periods enter a high wait state during this time (see

Figure 25-12

). When all devices concerned have counted off their low period, the synchronized clock (I2C_SCL) line is released and pulled high. At this point, the device clocks and the I2C_SCL line are synchronized, and the devices start counting their high periods. The first device to complete its high period pulls the I2C_SCL line low again.

Start counting high period

Wait

I2C_SCL1

I2C_SCL2

I2C_SCL

Internal Counter Reset

Figure 25-12. Clock Synchronization

A data arbitration procedure determines the relative priority of the contending masters. A bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving I2C_SDA output (see

Figure 25-13

). In this case, transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets

I2SR[IAL] to indicate loss of arbitration.

I2C_SCL

I2C_SDA by

Master1

I2C_SDA by

Master2

I2C_SDA

Master 2 Loses Arbitration, and becomes slave-receiver

Figure 25-13. Arbitration Procedure

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C Interface

25.3.8 Handshaking and Clock Stretching

The clock synchronization mechanism can acts as a handshake in data transfers. Slave devices can hold

I2C_SCL low after completing one byte transfer. In such a case, the clock mechanism halts the bus clock and forces the master clock into wait states until the slave releases I2C_SCL.

Slaves may also slow down the transfer bit rate. After the master has driven I2C_SCL low, the slave can drive I2C_SCL low for the required period and then release it. If the slave I2C_SCL low period is longer than the master I2C_SCL low period, the resulting I2C_SCL bus signal low period is stretched.

25.4 Initialization/Application Information

The following examples show programming for initialization, signaling START, post-transfer software response, signaling STOP, and generating a repeated START.

25.4.1 Initialization Sequence

Before the interface can transfer serial data, registers must be initialized:

1. Set I2FDR[IC] to obtain I2C_SCL frequency from the system bus clock. See

Section 25.2.2, “I

Frequency Divider Register (I2FDR).”

2. Update the I2ADR to define its slave address.

3. Set I2CR[IEN] to enable the I

C bus interface system.

4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and interrupt-enable or not.

NOTE

If I2SR[IBB] is set when the I

C bus module is enabled, execute the following pseudocode sequence before proceeding with normal initialization code. This issues a STOP command to the slave device, placing it in idle state as if it were power-cycled on.

I2CR = 0x0

I2CR = 0xA0 dummy read of I2DR

I2SR = 0x0

I2CR = 0x0

I2CR = 0x80 ; re-enable

25.4.2 Generation of START

After completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode. On a multiple-master bus system, I2SR[IBB] must be tested to determine whether the serial bus is free. If the bus is free (IBB is cleared), the START signal and the first byte (the slave address) can be sent. The data written to the data register comprises the address of the desired slave and the lsb indicates the transfer direction.

The free time between a STOP and the next START condition is built into the hardware that generates the

START cycle. Depending on the relative frequencies of the system clock and the I2C_SCL period, the

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C Interface

processor may need to wait until the I2C is busy after writing the calling address to the I2DR before proceeding with the following instructions.

The following example signals START and transmits the first byte of data (slave address):

1. Check I2SR[IBB]. If it is set, wait until it is clear.

2. After cleared, set to transmit mode by setting I2CR[MTX].

3. Set master mode by setting I2CR[MSTA]. This generates a START condition.

4. Transmit the calling address via the I2DR.

5. Check I2SR[IBB]. If it is clear, wait until it is set and go to step #1.

25.4.3 Post-Transfer Software Response

Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is finished.

I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during initialization by setting I2CR[IIEN]. Software must first clear I2SR[IIF] in the interrupt routine. Reading from I2DR in receive mode or writing to I2DR in transmit mode can clear I2SR[ICF].

Software can service the I

C I/O in the main program by monitoring the IIF bit if the interrupt function is disabled. Polling should monitor IIF rather than ICF, because that operation is different when arbitration is lost.

When an interrupt occurs at the end of the address cycle, the master is always in transmit mode; the address is sent. If master receive mode is required, I2CR[MTX] should be toggled.

During slave-mode address cycles (I2SR[IAAS] = 1), I2SR[SRW] is read to determine the direction of the next transfer. MTX is programmed accordingly. For slave-mode data cycles (IAAS = 0), SRW is invalid.

MTX should be read to determine the current transfer direction.

The following is an example of a software response by a master transmitter in the interrupt routine (see

Figure 25-14

1. Clear the I2CR[IIF] flag.

2. Check if acknowledge has been received, I2SR[RXAK].

3. If no ACK, end transmission. Else, transmit next byte of data via I2DR.

25.4.4 Generation of STOP

A data transfer ends when the master signals a STOP, which can occur after all data is sent, as in the following example.

1. Check if acknowledge has been received, I2SR[RXAK]. If no ACK, end transmission and go to

step #5.

2. Get value from transmitting counter, TXCNT. If no more data, go to step #5.

3. Transmit next byte of data via I2DR.

4. Decrement TXCNT and go to step #1

5. Generate a stop condition by clearing I2CR[MSTA].

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C Interface

For a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last byte. Before the last byte is read, a STOP signal must be generated, as in the following example.

1. Decrement RXCNT.

2. If last byte (RXCNT = 0) go to step #4.

3. If next to last byte (RXCNT = 1), set I2CR[TXAK] to disable ACK and go to step #5.

4. This is last byte, so clear I2CR[MSTA] to generate a STOP signal.

5. Read data from I2DR.

6. If there is more data to be read (RXCNT

≠ 0), go to step #1 if desired.

25.4.5 Generation of Repeated START

If the master wants the bus after the data transfer, it can signal another START followed by another slave address without signaling a STOP, as in the following example.

1. Generate a repeated START by setting I2CR[RSTA].

2. Transmit the calling address via I2DR.

25.4.6 Slave Mode

In the slave interrupt service routine, software must poll the I2SR[IAAS] bit to determine if the controller has received its slave address. If IAAS is set, software must set the transmit/receive mode select bit

(I2CR[MTX]) according to the I2SR[SRW]. Writing to I2CR clears IAAS automatically. The only time

IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred; interrupts resulting from subsequent data transfers have IAAS cleared. A data transfer can now be initiated by writing information to I2DR for slave transmits, or read from I2DR in slave-receive mode. A dummy read of I2DR in slave/receive mode releases I2C_SCL, allowing the master to send data.

In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data. Setting

RXAK means an end-of-data signal from the master receiver, after which software must switch it from transmitter to receiver mode. Reading I2DR releases I2C_SCL so the master can generate a STOP signal.

25.4.7 Arbitration Lost

If several devices try to engage the bus at the same time, one becomes master. Hardware immediately switches devices that lose arbitration to slave receive mode. Data output to I2C_SDA stops, but I2C_SCL continues generating until the end of the byte during which arbitration is lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with I2SR[IAL] set and I2CR[MSTA] cleared.

If a non-master device tries to transmit or execute a START, hardware inhibits the transmission, clears

MSTA without signaling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed attempt to engage the bus. When considering these cases, slave service routine should first test IAL and software should clear it if it is set.

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C Interface

Clear

IIF

Master

Mode?

TX/Rx

Arbitration

Lost?

Last Byte

Transmitted

RXAK= 0

End of

ADDR Cycle

(Master RX)

Write Next

Byte to I2DR

Last

Byte to be

Read

2nd Last

Byte to be

Read?

Set TXAK =1

Generate

STOP Signal

Clear IAL

IAAS=1

Address

Cycle

(Read)

SRW=1

N (WRITE)

IAAS=1

Data

Cycle

Tx/Rx

Set TX

Mode

Write Data to I2DR

Tx Next

Byte

ACK from

Receiver

Read Data from I2DR and Store

Switch to

Rx Mode

Set RX

Mode

Switch to

Rx Mode

Dummy Read from I2DR

Generate

STOP Signal

Read Data from I2DR

And Store

Dummy Read from I2DR

RTE

Figure 25-14. Flow-Chart of Typical I

C Interrupt Routine

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Chapter 26 Debug Module

26.1 Introduction

This chapter describes the revision B+ enhanced hardware debug module.

26.1.1 Block Diagram

The debug module is shown in

Figure 26-1

ColdFire CPU Core

High-speed local bus

Debug Module

Control

BKPT

Trace Port

PST[3:0],

DDATA[3:0]

PSTCLK

Communication Port

DSCLK, DSI, DSO

Figure 26-1. Processor/Debug Module Interface

26.1.2 Overview

Debug support is divided into three areas:

• Real-time trace support—The ability to determine the dynamic execution path through an application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel output bus that reports processor execution status and data to an external emulator system. See

Section 26.4.4, “Real-Time Trace Support”

• Background debug mode (BDM)—Provides low-level debugging in the ColdFire processor complex. In BDM, the processor complex is halted and a variety of commands can be sent to the processor to access memory, registers, and peripherals. The external emulator uses a three-pin, serial, full-duplex channel. See

Section 26.4.1, “Background Debug Mode (BDM),”

and

Section 26.3, “Memory Map/Register Definition”.

• Real-time debug support—BDM requires the processor to be halted, which many real-time embedded applications cannot do. Debug interrupts let real-time systems execute a unique service routine that can quickly save the contents of key registers and variables and return the system to normal operation. External development systems can access saved data, because the hardware supports concurrent operation of the processor and BDM-initiated commands. In addition, the

option allows interrupts to occur. See Section 26.4.2, “Real-Time Debug Support”.

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Debug Module

The first version 2 ColdFire core devices implemented the original debug architecture, now called revision

A. Based on feedback from customers and third-party developers, enhancements have been added to

succeeding generations of ColdFire cores. For revision A, CSR[HRL] is 0. See Section 26.3.2,

“Configuration/Status Register (CSR)”

Revision B (and B+) of the debug architecture offers more flexibility for configuring the hardware breakpoint trigger registers and removing the restrictions involving concurrent BDM processing while hardware breakpoint registers are active. Revision B+ adds three new PC breakpoint registers. For revision B, CSR[HRL] is 1, and for revision B+, CSR[HRL] is 0x9.

The following table summarizes the various debug revisions.

Table 26-1. Debug Revision Summary

Revision CSR[HRL]

0000

0001

B+ 1001

—

Enhancements

Initial debug revision

BDM command execution does not affect hardware breakpoint logic

Added BDM address attribute register (BAAR)

BKPT configurable interrupt (CSR[BKD])

Level 1 and level 2 triggers on OR condition, in addition to AND

SYNC

command to display the processor’s current PC

3 new PC breakpoint registers PBR1–3

26.2 Signal Descriptions

Table 26-2

describes debug module signals. All ColdFire debug signals are unidirectional and related to a rising edge of the processor core’s clock signal. The standard 26-pin debug connector is shown in

Section 26.4.6, “Freescale-Recommended BDM Pinout”

Table 26-2. Debug Module Signals

Signal Description

Development Serial

Clock (DSCLK)

Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two consecutive rising bus clock edges.) Clocks the serial communication port to the debug module during packet transfers. Maximum frequency is 1/5 the processor status clock (PSTCLK). At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.

Development Serial

Input (DSI)

Internally synchronized input that provides data input for the serial communication port to the debug module after the DSCLK has been seen as high (logic 1).

Development Serial

Output (DSO)

Provides serial output communication for debug module responses. DSO is registered internally. The output is delayed from the validation of DSCLK high.

Breakpoint (BKPT) Input requests a manual breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status signals (PST[3:0]) as the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a debug interrupt exception in the processor.

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Table 26-2. Debug Module Signals (continued)

Signal

Processor Status

Clock (PSTCLK)

Description

Delayed version of the processor clock. Its rising edge appears in the center of valid PST and DDATA output. PSTCLK indicates when the development system should sample PST and DDATA values.

The following figure shows PSTCLK timing with respect to PSTD and DATA.

PSTCLK

PST

DDATA

Debug Data

(DDATA[3:0])

Processor Status

(PST[3:0])

If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, PST and DDATA outputs from toggling without disabling triggers. Non-quiescent operation can be reenabled by clearing CSR[PCD], although the external development systems must resynchronize with the PST and DDATA outputs.

PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs during

system reset exception processing. Table 26-24

describes PST values.

These output signals display the register breakpoint status as a default, or optionally, captured address and operand values. The capturing of data values is controlled by the setting of the CSR.

Additionally, execution of the WDDATA instruction by the processor captures operands that are displayed on DDATA. These signals are updated each processor cycle. These signals are not implemented on the QFP devices (MCF5207CABxxx and MCF5208CABxxx).

These output signals report the processor status.

Table 26-24 shows the encoding of these signals.

These outputs indicate the current status of the processor pipeline and, as a result, are not related to the current bus transfer. The PST value is updated each processor cycle. These signals are not implemented on the QFP devices (MCF5207CABxxx and MCF5208CABxxx).

All Processor Status

Outputs (ALLPST)

ALLPST is a logical AND of the four PST signals. PST[3:0] and DDATA[3:0] are not available on the

QFP devices (MCF5207CABxxx and MCF5208CABxxx). When asserted, reflects that the core is halted.

26.3 Memory Map/Register Definition

In addition to the existing BDM commands that provide access to the processor’s registers and the memory subsystem, the debug module contain a number of registers to support the required functionality. These registers are also accessible from the processor’s supervisor programming model by executing the

WDEBUG instruction (write only). Therefore, the breakpoint hardware in debug module can be read or written by the external development system using the debug serial interface or written by the operating system running on the processor core. Software guarantees that accesses to these resources are serialized and logically consistent. Hardware provides a locking mechanism in CSR to allow external development system to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]).

BDM commands must not be issued if the ColdFire processor is using the WDEBUG instruction to access debug module registers, or the resulting behavior is undefined. The DSCLK must be quiescent during operation of the WDEBUG command.

These registers, shown in Table 26-3 , are treated as 32-bit quantities, regardless of the number of

implemented bits. These registers are also accessed through the BDM port by the commands,

WDMREG and

RDMREG

, described in Section 26.4.1.5, “BDM Command Set”.

These commands contain a 5-bit field,

DRc, that specifies the register, as shown in Table 26-3

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Table 26-3. Debug Module Memory Map

DRc[4–0] Register Name

Width

(bits)

Access Reset Value

Section/

Page

0x00

0x05

0x06

0x07

0x08

0x09

0x0C

0x0D

0x0E

0x0F

0x18

Configuration/status register (CSR)

BDM address attribute register (BAAR)

Address attribute trigger register (AATR)

Trigger definition register (TDR)

PC breakpoint register 0 (PBR0)

PC breakpoint mask register (PBMR)

Address breakpoint high register (ABHR)

Address breakpoint low register (ABLR)

Data breakpoint register (DBR)

Data breakpoint mask register (DBMR)

PC breakpoint register 1 (PBR1)

R/W

See Note

0x0090_0000

26.3.2/26-5

0x05

0x0005

0x0000_0000

26.3.5/26-10

Undefined

See Section

0x1A PC breakpoint register 2 (PBR2) 32 W See Section

0x1B PC breakpoint register 3 (PBR3) 32 W See Section

Section 26.4.2.2, “Emulator Mode”

Each debug register is accessed as a 32-bit register; reserved fields are not used (don’t care).

NOTE

Debug control registers can be written by the external development system or the CPU through the WDEBUG instruction. These control registers are write-only from the programming model and they can be written through the

BDM port using the

WDMREG

command. In addition, the configuration/status register (CSR) can be read through the BDM port using the

RDMREG

command.

The ColdFire debug architecture supports a number of hardware breakpoint registers, that can be configured into single- or double-level triggers based on the PC or operand address ranges with an optional inclusion of specific data values.

26.3.1 Shared Debug Resources

The debug module revision A implementation provides a common hardware structure for BDM and breakpoint functionality. Certain hardware structures are used for BDM and breakpoint purposes as shown

in Table 26-4 .

26-4

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Debug Module

Table 26-4. Shared BDM/Breakpoint Hardware

Register

AATR

ABHR

DBR

BDM Function Breakpoint Function

Bus attributes for all memory commands Attributes for address breakpoint

Address for all memory commands Address for address breakpoint

Data for all BDM write commands Data for data breakpoint

Therefore, loading a register to perform a specific function that shares hardware resources is destructive to the shared function. For example, if an operand address breakpoint is loaded into the debug module, a

BDM command to access memory overwrites an address breakpoint in ABHR. If a data breakpoint is configured, a BDM write command overwrites the data breakpoint in DBR.

Revision B added hardware registers to eliminate these shared functions. The BAAR is used to specify bus attributes for BDM memory commands and has the same format as the LSB of the AATR. The registers containing the BDM memory address and the BDM data are not program visible.

26.3.2 Configuration/Status Register (CSR)

The CSR defines the debug configuration for the processor and memory subsystem and contains status information from the breakpoint logic. CSR is write-only from the programming model. It can be read from and written to through the BDM port. CSR is accessible in supervisor mode as debug control register

0x00 using the WDEBUG instruction and through the BDM port using the

RDMREG

and

WDMREG commands.

DRc[4:0]: 0x00 (CSR)

Reset 0

30 29

BSTAT

0 0

15 14 13

MAP TRC EMU

Reset 0 0 0

28 27 26 25 24

FOF TRG HALT BKPT

0 0

DDC

UHE

BTB

HRL

0 0

Access: Supervisor write-only

BDM read/write

18 17 16

BKD PCD IPW

1 0 0 0 0

6 5 4

NPL IPI SSM

0 0 0 0 0 0 0 0

Figure 26-2. Configuration/Status Register (CSR)

1 0

FDBG DBGH

0 0

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26-5

Debug Module

FOF

TRG

HALT

BKPT

23–20

HRL

Field

31–28

BSTAT

BKD

PCD

Table 26-5. CSR Field Descriptions

Description

Breakpoint Status. Provides read-only status (from the BDM port only) information concerning hardware breakpoints. BSTAT is cleared by a TDR write or by a CSR read when a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled.

0000 No breakpoints enabled

0001 Waiting for level-1 breakpoint

0010 Level-1 breakpoint triggered

0101 Waiting for level-2 breakpoint

0110 Level-2 breakpoint triggered

Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM. FOF is cleared when CSR is read (from the BDM port only).

Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and forced entry into

BDM. Reset, the debug

command or reading CSR (from the BDM port only) clear TRG.

Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset, the debug

GO command, or reading CSR (from the BDM port only) clear HALT.

Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM. Reset, the debug

GO command, or reading CSR (from the BDM port only) clear BKPT.

Hardware revision level. Indicates, from the BDM port only, the level of debug module functionality. An emulator could use this information to identify the level of functionality supported.

0000 Revision A

0001 Revision B

0010 Revision C

0011 Revision D

1001 Revision B+ (This is the value used for this device)

1011 Revision D+

Reserved, must be cleared.

Breakpoint disable. Disables the normal BKPT input signal functionality, and allows the assertion of this pin to generate a debug interrupt.

0 Normal operation

1 BKPT is edge-sensitive: a high-to-low edge on BKPT signals a debug interrupt to the ColdFire core. The processor makes this interrupt request pending until the next sample point occurs, when the exception is initiated. In the ColdFire architecture, the interrupt sample point occurs once per instruction. There is no support for nesting debug interrupts.

PSTCLK disable.

0 PSTCLK is fully operational

1 Disables the generation of the PSTCLK and PSTDDATA output signals, and forces these signals to remain quiescent

Note: When PCD is set, do not execute a wddata instruction or perform any debug captures. Doing so, hangs the device.

IPW

MAP

Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s programming model registers. Only commands from the external development system can modify IPW.

Force processor references in emulator mode.

0 All emulator-mode references are mapped into supervisor code and data spaces.

1 The processor maps all references while in emulator mode to a special address space, TT equals 10,

TM equals 101 or 110. The internal SRAM and caches are disabled.

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Field

TRC

EMU

12–11

DDC

UHE

9–8

BTB

NPL

IPI

SSM

3–2

Debug Module

Table 26-5. CSR Field Descriptions (continued)

Description

Force emulation mode on trace exception.

0 The processor enters supervisor mode

1 The processor enters emulator mode when a trace exception occurs

Force emulation mode.

0 Do not force emulator mode

1 The processor begins executing in emulator mode. See

Debug data control. Controls operand data capture for DDATA, which displays the number of bytes defined by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long displays 32

bits (one nibble at a time across multiple PSTCLK clock cycles). See Table 26-24

00 No operand data is displayed.

01 Capture all write data.

10 Capture all read data.

11 Capture all read and write data.

User halt enable. Selects the CPU privilege level required to execute the HALT instruction.

0 HALT is a supervisor-only instruction.

1 HALT is a supervisor/user instruction.

Branch target bytes. Defines the number of bytes of branch target address DDATA displays.

00 0 bytes

01 Lower 2 bytes of the target address

10 Lower 3 bytes of the target address

11 Entire 4-byte target address

See

Section 26.4.4.1, “Begin Execution of Taken Branch (PST = 0x5)”

Reserved, must be cleared.

Non-pipelined mode. Determines whether the core operates in pipelined mode or not.

0 Pipelined mode

1 Non-pipelined mode. The processor effectively executes one instruction at a time with no overlap. This adds at least 5 cycles to the execution time of each instruction. Given an average execution latency of 1.6 cycles/instruction, throughput in non-pipeline mode would be 6.6 cycles/instruction, approximately 25% or less of pipelined performance.

Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering instruction executes. In normal pipeline operation, occurrence of an address and/or data breakpoint trigger is imprecise. In non-pipeline mode, triggers are always reported before the next instruction begins execution and trigger reporting can be considered precise.

An address or data breakpoint should always occur before the next instruction begins execution. Therefore, the occurrence of the address/data breakpoints should be guaranteed.

Ignore pending interrupts.

0 Core services any pending interrupt requests that were signalled while in single-step mode.

1 Core ignores any pending interrupt requests signalled while in single-instruction-step mode.

Single-Step Mode. Setting SSM puts the processor in single-step mode.

0 Normal mode.

1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed. On receipt of the

command, the processor executes the next instruction and halts again.

This process continues until SSM is cleared.

Reserved, must be cleared.

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Field

FDBG

DBGH

Table 26-5. CSR Field Descriptions (continued)

Description

Force the debug mode core output signal (to the on-chip peripherals). The debug mode output is logically defined as:

Debug mode output = CSR[FDBG] | (CSR[DBGH] and Core is halted)

0 Debug mode output is not forced asserted.

1 Debug mode output core output signal is asserted.

Disable debug signal assertion during core halt. The debug mode output (to the on-chip peripherals) is logically defined as:

Debug mode output = CSR[FDBG] | (CSR[DBGH] and Core is halted)

0 Debug mode output is asserted when the core is halted.

1 Debug mode output is not asserted when the core is halted.

26.3.3 BDM Address Attribute Register (BAAR)

The BAAR register defines the address space for memory-referencing BDM commands. BAAR[R, SZ] are loaded directly from the BDM command, while the low-order 5 bits can be programmed from the external development system. To maintain compatibility with revision A, BAAR is loaded any time the

AATR is written. The BAAR is initialized to a value of 0x05, setting supervisor data as the default address space.

DRc[4:0]: 0x05 (BAAR)

7 6 5 4 3 2

Access: Supervisor write-only

BDM write-only

1 0

Field

6–5

4–3

2–0

Reset:

SZ TT

0 0 0 0 1

Figure 26-3. BDM Address Attribute Register (BAAR)

0 1

Table 26-6. BAAR Field Descriptions

Description

Read/Write.

0 Write

1 Read

Size.

00 Longword

01 Byte

10 Word

11 Reserved

Transfer Type. See the TT definition in the AATR description,

Section 26.3.4, “Address Attribute Trigger Register

(AATR)”

Transfer Modifier. See the TM definition in the AATR description,

Section 26.3.4, “Address Attribute Trigger Register

(AATR)”

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26.3.4 Address Attribute Trigger Register (AATR)

The AATR defines address attributes and a mask to be matched in the trigger. The register value is compared with address attribute signals from the processor’s local high-speed bus, as defined by the setting of the trigger definition register (TDR). AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the

WDMREG

command.

DRc[4:0]: 0x06 (AATR)

Field

14–13

SZM

12–11

TTM

10–8

TMM

6–5

W RM

Reset 0

14 13 12 11 10 9 8 7 6 5

SZM

0 0

TTM

0 0

TMM

0 0

Figure 26-4. Address Attribute Trigger Register (AATR)

Table 26-7. AATR Field Descriptions

Description

Read/write Mask. Setting RM masks R in address comparisons.

Size Mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.

Transfer Type Mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.

Read/Write. R is compared with the R/W signal of the processor’s local bus.

Size. Compared to the processor’s local bus size signals.

00 Longword

01 Byte

10 Word

11 Reserved

Access: Supervisor write-only

BDM write-only

3 2 1 0

Transfer Modifier Mask. Setting a TMM bit masks the corresponding TM bit in address comparisons.

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Field

4–3

2–0

Table 26-7. AATR Field Descriptions (continued)

Description

Transfer Type. Compared with the local bus transfer type signals.

00 Normal processor access

01 Reserved

10 Emulator mode access

These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding indicates an external or DMA access (for backward compatibility). These bits affect the TM bits.

Transfer Modifier. Compared with the local bus transfer modifier signals, which give supplemental information for each transfer type. These bits also define the TM encoding for BDM memory commands (for backward compatibility).

000

001

010

011

100

101

110

111

TT=00

(normal mode)

Explicit cache line push

User data access

User code access

Reserved

Supervisor data access

Supervisor code access

Reserved

TT=10

(emulator mode)

Reserved

Emulator mode access

Emulator code access

Reserved

26.3.5 Trigger Definition Register (TDR)

The TDR configures the operation of the hardware breakpoint logic corresponding with the

ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug module. TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured as a one- or two-level trigger. TDR[31–16] bits define second-level trigger, and bits 15–0 define first-level trigger.

NOTE

The debug module has no hardware interlocks to prevent spurious breakpoint triggers while the breakpoint registers are being loaded. Disable

TDR (by clearing TDR[29,13]) before defining triggers.

A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the

WDMREG command.

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DRc[4:0]: 0x07 (TDR) Access: Supervisor write-only

BDM write-only

Second Level Trigger

23 22 21 31 30

Reset 0

TRC

L2EBL

L2ED

0 0 0 0

First Level Trigger

L2DI

8 7 6 5 15 14 13

W L2T L1T L1EBL

Reset 0 0 0

12 11 10 9

0 0 0

L1ED

0 0 0 0

L1DI

Figure 26-5. Trigger Definition Register (TDR)

L2EA

L1EA

17 16

L2EPC L2PCI

0 0

1 0

L1EPC L1PCI

0 0

Table 26-8. TDR Field Descriptions

Field Description

31–30

TRC

L2EBL

28–22

L2ED

Trigger Response Control. Determines how the processor responds to a completed trigger condition. The trigger response is always displayed on DDATA.

00 Display on DDATA only

01 Processor halt

10 Debug interrupt

11 Reserved

Enable Level 2 Breakpoint. Global enable for the breakpoint trigger.

0 Disables all level 2 breakpoints

1 Enables all level 2 breakpoint triggers

Enable Level 2 Data Breakpoint. Setting an L2ED bit enables the corresponding data breakpoint condition based on the size and placement on the processor’s local data bus. Clearing all ED bits disables data breakpoints.

TDR Bit

Description

Data longword. Entire processor’s local data bus.

Lower data word.

Upper data word.

Lower lower data byte. Low-order byte of the low-order word.

Lower middle data byte. High-order byte of the low-order word.

Upper middle data byte. Low-order byte of the high-order word.

Upper upper data byte. High-order byte of the high-order word.

L2DI

Level 2 Data Breakpoint Invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value other than the DBR contents.

0 No inversion

1 Invert data breakpoint comparators.

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Table 26-8. TDR Field Descriptions (continued)

Field

20–18

L2EA

Description

Enable Level 2 Address Breakpoint. Setting an L2EA bit enables the corresponding address breakpoint. Clearing all three bits disables the breakpoint.

TDR Bit

Description

Address breakpoint inverted. Breakpoint is based outside the range between ABLR and ABHR.

Address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR.

Address breakpoint low. The breakpoint is based on the address in the ABLR.

L2EPC

Enable Level 2 PC Breakpoint.

0 Disable PC breakpoint

1 Enable PC breakpoint where the trigger is defined by the logical summation of:

L2PCI

L2T

L1T

L1EBL

(PBR0 and PBMR) | PBR1 | PBR2 | PBR3

Level 2 PC Breakpoint Invert.

0 The PC breakpoint is defined within the region defined by PBRn and PBMR.

1 The PC breakpoint is defined outside the region defined by PBRn and PBMR.

Eqn. 26-1

Level 2 Trigger. Determines the logic operation for the trigger between the PC_condition and the (Address_range &

Data_condition) where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the creation of single or double-level triggers.

0 Level 2 trigger = PC_condition & Address_range & Data_condition

1 Level 2 trigger = PC_condition | (Address_range & Data_condition)

Note: Debug Rev A only had the AND condition available for the triggers.

Level 1 Trigger. Determines the logic operation for the trigger between the PC_condition and the (Address_range &

Data_condition) where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the creation of single or double-level triggers.

0 Level 1 trigger = PC_condition & Address_range & Data_condition

1 Level 1 trigger = PC_condition | (Address_range & Data_condition)

Note: Debug Rev A only had the AND condition available for the triggers.

Enable Level 1 Breakpoint. Global enable for the breakpoint trigger.

0 Disables all level 1 breakpoints

1 Enables all level 1 breakpoint triggers

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Table 26-8. TDR Field Descriptions (continued)

Field

12–6

L1ED

Description

Enable Level 1 Data Breakpoint. Setting an L1ED bit enables the corresponding data breakpoint condition based on the size and placement on the processor’s local data bus. Clearing all L1ED bits disables data breakpoints.

TDR Bit

Description

Data longword. Entire processor’s local data bus.

Lower data word.

Upper data word.

Lower lower data byte. Low-order byte of the low-order word.

Lower middle data byte. High-order byte of the low-order word.

Upper middle data byte. Low-order byte of the high-order word.

Upper upper data byte. High-order byte of the high-order word.

L1DI

4–2

L1EA

Level 1 Data Breakpoint Invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value other than the DBR contents.

0 No inversion

1 Invert data breakpoint comparators.

Enable Level 1 Address Breakpoint. Setting an L1EA bit enables the corresponding address breakpoint. Clearing all three bits disables the address breakpoint.

TDR Bit

Description

Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR and ABHR.

Enable address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR.

Enable address breakpoint low. The breakpoint is based on the address in the ABLR.

L1EPC

Enable Level 1 PC breakpoint.

0 Disable PC breakpoint

1 Enable PC breakpoint

L1PCI

Level 1 PC Breakpoint Invert.

0 The PC breakpoint is defined within the region defined by PBRn and PBMR.

1 The PC breakpoint is defined outside the region defined by PBRn and PBMR.

26.3.6 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR)

The PBRn registers define an instruction address for use as part of the trigger. These registers’ contents are compared with the processor’s program counter register when the appropriate valid bit is set (for

PBR1–3) and TDR is configured appropriately. PBR0 bits are masked by setting corresponding PBMR bits (PBMR has no effect on PBR1–3). Results are compared with the processor’s program counter register, as defined in TDR. Breakpoint registers, PBR1–3, have no masking associated with them. The

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contents of the breakpoint registers are compared with the processor’s program counter register when TDR is configured appropriately.

The PC breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the

WDMREG

command using values shown in Section 26.4.1.5, “BDM

Command Set”

DRc[4:0]: 0x08 (PBR0) Access: Supervisor write-only

BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W Address

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 26-6. PC Breakpoint Register (PBR0)

Table 26-9. PBR0 Field Descriptions

Field Description

31–0

Address

PC Breakpoint Address. The address to be compared with the PC as a breakpoint trigger.

Note: PBR0[0] should always be loaded with a 0.

DRc[4:0]: 0x18 (PBR1)

0x1A (PBR2)

0x1B (PBR3)

Access: Supervisor write-only

BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W Address V

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0 0 0

Figure 26-7. PC Breakpoint Register n (PBRn)

Table 26-10. PBRn Field Descriptions

Field Description

31–1

Address

PC Breakpoint Address. The 31-bit address to be compared with the PC as a breakpoint trigger.

Valid Bit. This bit must be set for the PC breakpoint to occur at the address specified in the Address field.

0 PBR is disabled.

1 PBR is enabled.

Figure 26-8

shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and via the BDM port using the

WDMREG

command. PBMR only masks PBR0.

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Field

31–0

Mask

DRc[4:0]: 0x09 (PBMR) Access: Supervisor write-only

BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W Mask

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 26-8. PC Breakpoint Mask Register (PBMR)

Table 26-11. PBMR Field Descriptions

Description

PC Breakpoint Mask.

0 The corresponding PBR0 bit is compared to the appropriate PC bit.

1 The corresponding PBR0 bit is ignored.

26.3.7 Address Breakpoint Registers (ABLR, ABHR)

The ABLR and ABHR define regions in the processor’s data address space that can act as part of the trigger. These register values are compared with the address for each transfer on the processor’s high-speed local bus. The trigger definition register (TDR) identifies the trigger as one of three cases:

• Identically the value in ABLR

• Inside the range bound by ABLR and ABHR inclusive

• Outside that same range

ABLR and ABHR are accessible in supervisor mode using the WDEBUG instruction and via the BDM port using the

WDMREG command.

DRc[4:0]: 0x0C (ABHR)

0x0D (ABLR)

Access: Supervisor write-only

BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W Address

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 26-9. Address Breakpoint Registers (ABLR, ABHR,)

Table 26-12. ABLR Field Description

Field Description

31–0

Address

Low Address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for specific single addresses are programmed into ABLR.

Table 26-13. ABHR Field Description

Field Description

31–0

Address

High Address. Holds the 32-bit address marking the upper bound of the address breakpoint range.

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26.3.8 Data Breakpoint and Mask Registers (DBR, DBMR)

The data breakpoint register (DBR), specify data patterns used as part of the trigger into debug mode. DBR bits are masked by setting corresponding DBMR bits, as defined in TDR.

DBR and DBMR are accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the

WDMREG

command.

DRc[4:0]: 0x0E (DBR) Access: Supervisor write-only

BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W Data

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 26-10. Data Breakpoint Registers (DBR)

Field

31–0

Data

Table 26-14. DBR Field Descriptions

Description

Data Breakpoint Value. Contains the value to be compared with the data value from the processor’s local bus as a breakpoint trigger.

Field

31–0

Mask

DRc[4:0]: 0x0F (DBMR) Access: Supervisor write-only

BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W Mask

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 26-11. Data Breakpoint Mask Registers (DBMR)

Table 26-15. DBMR Field Descriptions

Description

Data Breakpoint Mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBMR bit allows the corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a DBMR bit causes that bit to be ignored.

The DBR supports aligned and misaligned references.

Table 26-16 shows relationships between processor

address, access size, and location within the 32-bit data bus.

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Table 26-16. Address, Access Size, and Operand Data Location

Address[1:0]

1x xx

Access Size

Byte

Word

Longword

Operand Location

D[31:24]

D[23:16]

D[15:8]

D[7:0]

D[31:16]

D[15:0]

D[31:0]

26.4 Functional Description

26.4.1 Background Debug Mode (BDM)

The ColdFire family implements a low-level system debugger in the microprocessor in a dedicated hardware module. Communication with the development system is managed through a dedicated, high-speed serial command interface. Although some BDM operations, such as CPU register accesses, require the CPU to be halted, other BDM commands, such as memory accesses, can be executed while the processor is running.

BDM is useful because:

• In-circuit emulation is not needed, so physical and electrical characteristics of the system are not affected.

• BDM is always available for debugging the system and provides a communication link for upgrading firmware in existing systems.

• Provides high-speed cache downloading (500 Kbytes/sec), especially useful for flash programming

• Provides absolute control of the processor, and thus the system. This feature allows quick hardware debugging with the same tool set used for firmware development.

26.4.1.1

CPU Halt

Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority:

1. A catastrophic fault-on-fault condition automatically halts the processor.

2. A hardware breakpoint trigger can generate a pending halt condition similar to the assertion of

BKPT. This type of halt is always first marked as pending in the pocessor, which samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted,

the processor halts execution at the next sample point. See Section 26.4.2.1, “Theory of

Operation”

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3. The execution of a HALT instruction immediately suspends execution. Attempting to execute

HALT in user mode while CSR[UHE] is cleared generates a privilege violation exception. If

CSR[UHE] is set, HALT can be executed in user mode. After HALT executes, the processor can be restarted by serial shifting a

command into the debug module. Execution continues at the instruction after HALT.

4. The assertion of the BKPT input is treated as a pseudo-interrupt; asserting BKPT creates a pending halt postponed until the processor core samples for halts/interrupts. The processor samples for these conditions once during the execution of each instruction; if a pending halt is detected, the processor suspends execution and enters the halted state.

The are two special cases involving the assertion of BKPT:

• After the system reset signal is negated, the processor waits for 16 processor clock cycles before beginning reset exception processing. If the BKPT input is asserted within eight cycles after

RESET is negated, the processor enters the halt state, signaling halt status (0xF) on the PST outputs. While the processor is in this state, all resources accessible through the debug module can be referenced. This is the only chance to force the processor into emulation mode through

CSR[EMU].

• After system initialization, the processor’s response to the

command depends on the set of

BDM commands performed while it is halted for a breakpoint. Specifically, if the PC register was loaded, the

command causes the processor to exit halted state and pass control to the instruction address in the PC, bypassing normal reset exception processing. If the PC was not loaded, the

GO command causes the processor to exit halted state and continue reset exception processing.

• The ColdFire architecture also manages a special case of BKPT asserted while the processor is stopped by execution of the STOP instruction. For this case, the processor exits the stopped mode and enters the halted state, at which point all BDM commands may be exercised. When restarted, the processor continues by executing the next sequential instruction, which follows the STOP opcode.

The CSR[27–24] bits indicate the halt source, showing the highest priority source for multiple halt conditions.

26.4.1.2

BDM Serial Interface

When the CPU is halted and PST reflects the halt status, the development system can send unrestricted commands to the debug module. The debug module implements a synchronous serial protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a delay relative to the rising edge of the processor clock. See

Table 26-2

. The development system serves as the serial communication channel master and must generate DSCLK.

The serial channel operates at a frequency from DC to 1/5 of the PSTCLK frequency. The channel uses full-duplex mode, where data is sent and received simultaneously by master and slave devices. The transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. As shown

in Figure 26-12 , all state transitions are enabled on a rising edge of the PSTCLK clock when DSCLK is

high; DSI is sampled and DSO is driven.

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C0 C1 C2 C3 C4

PSTCLK

DSCLK

DSI Current Next

BDM State

Machine

DSO

Current State

Past

Next State

Current

Figure 26-12. Maximum BDM Serial Interface Timing

DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled, along with DSI, on the rising edge of PSTCLK. DSO is delayed from the DSCLK-enabled PSTCLK rising edge

(registered after a BDM state machine state change). All events in the debug module’s serial state machine are based on the PSTCLK rising edge. DSCLK must also be sampled low (on a positive edge of PSTCLK) between each bit exchange. The msb is sent first. Because DSO changes state based on an internally recognized rising edge of DSCLK, DSO cannot be used to indicate the start of a serial transfer. The development system must count clock cycles in a given transfer. C0–C4 are described as:

• C0: Set the state of the DSI bit

• C1: First synchronization cycle for DSI (DSCLK is high)

• C2: Second synchronization cycle for DSI (DSCLK is high)

• C3: BDM state machine changes state depending upon DSI and whether the entire input data transfer has been transmitted

• C4: DSO changes to next value

NOTE

A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.

26.4.1.3

Receive Packet Format

The basic receive packet consists of 16 data bits and 1 status bit

15 14 13 12 16

11 10 9 8 7 6

Data

Figure 26-13. Receive BDM Packet

5 4 3 2 1 0

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Table 26-17. Receive BDM Packet Field Description

Field

Description

Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.

Data

xxxx

FFFF

0000

0001

FFFF

Message

Valid data transfer

Status OK

Not ready with response; come again

Error-Terminated bus cycle; data invalid

Illegal Command

15–0

Data

Data. Contains the message to be sent from the debug module to the development system. The response message is always a single word, with the data field encoded as shown above.

26.4.1.3.1

Transmit Packet Format

The basic transmit packet consists of 16 data bits and 1 reserved bit.

—

15 14 13 12 11 10 9 8

Data

7 6 5

Figure 26-14. Transmit BDM Packet

4 3 2

Field

15–0

Data

Table 26-18. Transmit BDM Packet Field Description

Description

Reserved, must be cleared.

Data bits 15–0. Contains the data to be sent from the development system to the debug module.

1 0

26.4.1.3.2

BDM Command Format

All ColdFire family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words.

15 14 13 12

Operation

11 10 9

R/W

7 6

Op Size

Extension Word(s)

Figure 26-15. BDM Command Format

A/D

2 1

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Table 26-19. BDM Field Descriptions

Field Description

15–10

Operation

Specifies the command. These values are listed in Table 26-20

R/W

Reserved, must be cleared.

Direction of operand transfer.

0 Data is written to the CPU or to memory from the development system.

1 The transfer is from the CPU to the development system.

7–6

Op Size

Operand Data Size for Sized Operations. Addresses are expressed as 32-bit absolute values. A command performing a byte-sized memory read leaves the upper 8 bits of the response data undefined. Referenced data is returned in the lower 8 bits of the response.

Operand Size

Byte

Word

Longword

Reserved

Bit Values

8 bits

16 bits

32 bits

—

5–4

A/D

Reserved, must be cleared.

Address/Data. Determines whether the register field specifies a data or address register.

0 Data register.

1 Address register.

2–0

Contains the register number in commands that operate on processor registers. See

Table 26-21 .

26.4.1.3.3

Extension Words as Required

Some commands require extension words for addresses and/or immediate data. Addresses require two extension words because only absolute long addressing is permitted. Longword accesses are forcibly longword-aligned and word accesses are forcibly word-aligned. Immediate data can be 1 or 2 words long.

Byte and word data each requires a single extension word, while longword data requires two extension words.

Operands and addresses are transferred most-significant word first. In the following descriptions of the

BDM command set, the optional set of extension words is defined as address, data, or operand data.

26.4.1.4

Command Sequence Diagrams

The command sequence diagram in Figure 26-16 shows serial bus traffic for commands. Each bubble

represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands. Command and result transactions overlap to minimize latency.

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Commands transmitted to the debug module

Command code transmitted during this cycle

High-order 16 bits of memory address

Low-order 16 bits of memory address

Non-serial-related activity

Sequence taken if operation has not completed

READ (LONG)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

READ

MEMORY

LOCATION

XXX

’NOT READY’

Command

Code

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

XXX

MS RESULT

NEXT CMD

LS RESULT

Data used from this transfer

XXX

BERR

NEXT CMD

’NOT READY’

Sequence taken if illegal command is received by debug module

Results from previous command

Sequence taken if bus error occurs on memory access

Responses from the debug module

Figure 26-16. Command Sequence Diagram

High- and low-order 16 bits of result

The sequence is as follows:

• In cycle 1, the development system command is issued (

READ

in this example). The debug module responds with the low-order results of the previous command or a command complete status of the previous command, if no results are required.

• In cycle 2, the development system supplies the high-order 16 address bits. The debug module returns a not-ready response unless the received command is decoded as unimplemented, which is indicated by the illegal command encoding. If this occurs, the development system should retransmit the command.

NOTE

A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.

• In cycle 3, the development system supplies the low-order 16 address bits. The debug module always returns a not-ready response.

• At the completion of cycle 3, the debug module initiates a memory read operation. Any serial transfers that begin during a memory access return a not-ready response.

• Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is sent to the debug module during the final transfer. If a bus error terminates a memory or register access, error status (S = 1, DATA = 0x0001) returns instead of result data.

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26-22 Freescale Semiconductor

Debug Module

26.4.1.5

BDM Command Set

Table 26-20

summarizes the BDM command set. Subsequent sections contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior. See

Table 26-21 for register address encodings.

Table 26-20. BDM Command Summary

Command Mnemonic Description

CPU

State

Section/Page

Command

(Hex)

Read A/D register

Write A/D register

Read memory location

Write memory location

Dump memory block

Fill memory block

RAREG

RDREG

WAREG

WDREG

READ

WRITE

DUMP

FILL

/ Read the selected address or data register and return the results through the serial interface.

Write the data operand to the specified address or data register.

Read the data at the memory location specified by the longword address.

Write the operand data to the memory location specified by the longword address.

Used with

READ

to dump large blocks of memory. An initial

READ

executes to set up the starting address of the block and to retrieve the first result. A

DUMP command retrieves subsequent operands.

Used with

WRITE

to fill large blocks of memory. An initial

WRITE

executes to set up the starting address of the block and to supply the first operand. A

FILL command writes subsequent operands.

Halted

26.4.1.5.1/26-24

0x218 {A/D,

Reg[2:0]}

Halted

26.4.1.5.2/26-24

0x208 {A/D,

Reg[2:0]}

Steal

26.4.1.5.3/26-25

0x1900—byte

0x1940—word

0x1980—lword

Steal

26.4.1.5.4/26-26

0x1800—byte

0x1840—word

0x1880—lword

Steal

26.4.1.5.5/26-28

0x1D00—byte

0x1D40—word

0x1D80—lword

Steal

26.4.1.5.6/26-30

0x1C00—byte

0x1C40—word

0x1C80—lword

Resume execution

No operation

Output the current PC

Read control register

NOP

Perform no operation; may be used as a null command.

SYNC

Capture the current PC and display it on the

PST/DDATA outputs.

RCREG

The pipeline is flushed and refilled before resuming instruction execution at the current PC.

Halted

26.4.1.5.7/26-31

0x0C00

Parallel

26.4.1.5.8/26-32

0x0000

Read the system control register.

Parallel

Halted

26.4.1.5.9/26-32

26.4.1.5.10/26-33

0x0001

0x2980

Write control register

WCREG

Write the operand data to the system control register.

Halted

26.4.1.5.13/26-35

0x2880

Read debug module register

RDMREG

Read the debug module register.

Parallel

26.4.1.5.14/26-36

0x2D {0x4

DRc[4:0]}

Write debug module register

WDMREG

Write the operand data to the debug module register.

Parallel

General command effect and/or requirements on CPU operation:

- Halted: The CPU must be halted to perform this command.

- Steal: Command generates bus cycles that can be interleaved with bus accesses.

- Parallel: Command is executed in parallel with CPU activity.

26.4.1.5.15/26-37

0x2C {0x4

DRc[4:0]}

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Freescale Semiconductor 26-23

Debug Module

0x4 is a three-bit field.

Freescale reserves unassigned command opcodes. All unused command formats within any revision level perform a

NOP

and return the illegal command response.

The following sections describe the commands summarized in

Table 26-20 .

NOTE

The BDM status bit (S) is 0 for normally completed commands. S is set for illegal commands, not-ready responses, and transfers with bus-errors.

Section 26.4.1.2, “BDM Serial Interface ,” describes the receive packet

format.

26.4.1.5.1

Read A/D Register (

RAREG

RDREG

)

Read the selected address or data register and return the 32-bit result. A bus error response is returned if the CPU core is not halted.

Command/Result Formats:

Command

Result

Command Sequence:

0x2

13 12 11 10

0x1

9 8 7 6

0x8

D[31:16]

D[15:0]

Figure 26-17.

RAREG

RDREG

Command Format

RAREG/RDREG

???

XXX

MS RESULT

NEXT CMD

LS RESULT

A/D

2 1

Operand Data:

Result Data:

XXX

BERR

NEXT CMD

’NOT READY’

Figure 26-18.

RAREG

RDREG

Command Sequence

None

The contents of the selected register are returned as a longword value, most-significant word first.

26.4.1.5.2

Write A/D Register (

WAREG

WDREG

)

The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted.

Command Format:

MCF5208 Reference Manual, Rev 2

26-24 Freescale Semiconductor

Debug Module

15 14

0x2

13 12 11 10 9 8 7 6 5 4

0x0 0x8

D[31:16]

D[15:0]

Figure 26-19.

WAREG

WDREG

Command Format

A/D

2 1

Command Sequence:

WAREG/WDREG

???

MS DATA

’NOT READY’

LS DATA

’NOT READY’

NEXT CMD

’CMD COMPLETE’

Operand Data:

Result Data:

XXX

BERR

NEXT CMD

’NOT READY’

Figure 26-20.

WAREG

WDREG

Command Sequence

Longword data is written into the specified address or data register. The data is supplied most-significant word first.

Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete.

26.4.1.5.3

Read Memory Location (

READ

)

Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.

Command/Result Formats:

4 3 2

0x0

1 0

Byte

Command

Result

Word Command

Result

Longword Command

Result

15 14

0x1

13 12 11 10

0x9

9 8 7 6

0x0

A[31:16]

A[15:0]

X X

0x1

X X X X

0x9

0x4

A[31:16]

A[15:0]

D[15:0]

0x1 0x9 0x8

A[31:16]

A[15:0]

D[31:16]

D[15:0]

Figure 26-21.

READ

Command/Result Formats

D[7:0]

0x0

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 26-25

Debug Module

Command Sequence:

READ (B/W)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

READ

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

RESULT

XXX

BERR

NEXT CMD

’NOT READY’

READ (LONG)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

READ

MEMORY

LOCATION

XXX

’NOT READY’

XXX

MS RESULT

NEXT CMD

LS RESULT

Operand Data:

Result Data:

XXX

BERR

NEXT CMD

’NOT READY’

Figure 26-22.

READ

Command Sequence

The only operand is the longword address of the requested location.

Word results return 16 bits of data; longword results return 32. Bytes are returned in the LSB of a word result; the upper byte is undefined. 0x0001 (S = 1) is returned if a bus error occurs.

26.4.1.5.4

Write Memory Location (

WRITE

)

Write data to the memory location specified by the longword address. BAAR[TT,TM] defines address space. Hardware forces low-order address bits to 0s for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.

26-26

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

Debug Module

Command Formats:

Byte

Word

Longword

15 14

0x1

X X

0x1

12 11 10

0x8

9 8 7 6

0x0

X X X X

A[31:16]

A[15:0]

0x8 0x4

A[31:16]

A[15:0]

D[15:0]

0x8 0x8

A[31:16]

A[15:0]

D[31:16]

D[15:0]

Figure 26-23.

WRITE

Command Format

5 4

D[7:0]

3 2

0x0

1 0

0x0

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

26-27

Debug Module

Command Sequence:

WRITE (B/W)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

DATA

’NOT READY’

WRITE

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

NEXT CMD

’NOT READY’

WRITE (LONG)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

MS DATA

’NOT READY’

LS DATA

’NOT READY’

WRITE

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

Operand Data:

Result Data:

NEXT CMD

’NOT READY’

Figure 26-24.

WRITE

Command Sequence

This two-operand instruction requires a longword absolute address that specifies a location the data operand is written. Byte data is sent as a 16-bit word, justified in the LSB; 16- and 32-bit operands are sent as 16 and 32 bits, respectively.

Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete. A value of 0x0001 (with S set) is returned if a bus error occurs.

26.4.1.5.5

Dump Memory Block (

DUMP

)

DUMP

is used with the

READ

command to access large blocks of memory. An initial

READ

is executed to set up the starting address of the block and to retrieve the first result. If an initial

READ

is not executed before the first

DUMP

, an illegal command response is returned. The

DUMP

command retrieves subsequent operands. The initial address increments by the operand size (1, 2, or 4) and saves in a temporary register.

Subsequent

DUMP

commands use this address, perform the memory read, increment it by the current operand size, and store the updated address in the temporary register.

MCF5208 Reference Manual, Rev 2

26-28 Freescale Semiconductor

Debug Module

NOTE

DUMP

does not check for a valid address; it is a valid command only when preceded by

NOP

READ

, or another

DUMP

command. Otherwise, an illegal command response is returned.

NOP

can be used for intercommand padding without corrupting the address pointer.

The size field is examined each time a

DUMP

command is processed, allowing the operand size to be dynamically altered.

Command/Result Formats:

Byte Command

Word

Result

Command

Result

Longword Command

Result

0x1

X X

0x1

0xD

X X

0xD

7 6

0x0

0x4

D[15:0]

0x1 0xD 0x8

D[31:16]

D[15:0]

Figure 26-25.

DUMP

Command/Result Formats

D[7:0]

3 2

0x0

Command Sequence:

DUMP (B/W)

???

READ

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

RESULT

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

XXX

BERR

NEXT CMD

’NOT READY’

DUMP (LONG)

???

Operand Data:

READ

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

MS RESULT

None

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

Figure 26-26.

DUMP

Command Sequence

XXX

BERR

NEXT CMD

LS RESULT

NEXT CMD

’NOT READY’

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 26-29

Debug Module

Result Data: Requested data is returned as a word or longword. Byte data is returned in the least-significant byte of a word result. Word results return 16 bits of significant data; longword results return 32 bits. A value of 0x0001 (with S set) is returned if a bus error occurs.

26.4.1.5.6

Fill Memory Block (

FILL

)

FILL

command is used with the

WRITE

command to access large blocks of memory. An initial

WRITE

is executed to set up the starting address of the block and to supply the first operand. The

FILL

command writes subsequent operands. The initial address increments by the operand size (1, 2, or 4) and saves in a temporary register after the memory write. Subsequent

FILL

commands use this address, perform the write, increment it by the current operand size, and store the updated address in the temporary register.

If an initial

WRITE

is not executed preceding the first

FILL

command, the illegal command response is returned.

NOTE

The

FILL

command does not check for a valid address:

FILL

is a valid command only when preceded by another

FILL

, a

NOP

, or a

WRITE

command.

Otherwise, an illegal command response is returned. The

NOP

command can be used for intercommand padding without corrupting the address pointer.

The size field is examined each time a

FILL

command is processed, allowing the operand size to be altered dynamically.

Command Formats:

Byte

Word

Longword

0x1

X X

0x1

0xC

X X

0xC

7 6

0x0

0x4

D[15:0]

0xC 0x8

D[31:16]

D[15:0]

Figure 26-27.

FILL

Command Format

D[7:0]

3 2

0x0

26-30

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

Debug Module

Command Sequence:

FILL (LONG)

???

MS DATA

’NOT READY’

XXX

’ILLEGAL’

LS DATA

’NOT READY’

NEXT CMD

’NOT READY’

WRITE

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

NEXT CMD

’NOT READY’

FILL (B/W)

???

DATA

’NOT READY’

WRITE

MEMORY

LOCATION

XXX

’NOT READY’

Operand Data:

Result Data:

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

Figure 26-28.

FILL

Command Sequence

NEXT CMD

’NOT READY’

A single operand is data to be written to the memory location. Byte data is sent as a 16-bit word, justified in the least-significant byte; 16- and 32-bit operands are sent as 16 and 32 bits, respectively.

Command complete status (0xFFFF) is returned when the register write is complete. A value of 0x0001 (with S set) is returned if a bus error occurs.

26.4.1.5.7

Resume Execution (

)

The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes.

If a

command issues and the CPU is not halted, the command is ignored.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x0 0xC 0x0 0x0

Figure 26-29.

Command Format

Command Sequence:

???

NEXT CMD

’CMD COMPLETE’

Figure 26-30.

Command Sequence

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 26-31

Debug Module

Operand Data:

Result Data:

None

The command-complete response (0xFFFF) is returned during the next shift operation.

26.4.1.5.8

No Operation (

NOP

)

NOP

performs no operation and may be used as a null command where required.

Command Formats:

15 14

0x0

13 12 11 10 9 8 7 6 5

0x0 0x0

Figure 26-31.

NOP

Command Format

4 3 2

0x0

1 0

Command Sequence:

NOP

???

NEXT CMD

’CMD COMPLETE’

Operand Data:

Result Data:

Figure 26-32.

NOP

Command Sequence

None

The command-complete response, 0xFFFF (with S cleared), is returned during the next shift operation.

26.4.1.5.9

Synchronize PC to the PST/DDATA Lines (

SYNC

)

The

SYNC

command captures the current PC and displays it on the PST

DDATA outputs. After the debug module receives the command, it sends a signal to the ColdFire processor that the current PC must be displayed. The processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of the CSR[BTB] bits. The specific sequence of PST and DDATA values is defined below:

1. Debug signals a

SYNC

command is pending.

2. CPU completes the current instruction.

3. CPU forces an instruction fetch to the next PC, generates a PST equaling 0x5 value indicating a taken branch and signals the capture of DDATA.

4. The instruction address corresponding to the PC is captured.

5. The PST marker (0x9–0xB) is generated and displayed as defined by the CSR[BTB] bit followed by the captured PC address.

The

SYNC

command can be used to dynamically access the PC for performance monitoring. The execution of this command is considerably less obtrusive to the real-time operation of an application than a

HALT

CPU

READ

RESUME

command sequence.

Command Formats:

MCF5208 Reference Manual, Rev 2

26-32 Freescale Semiconductor

Debug Module

15 14

0x0

13 12 11 10 9 8 7 6 5

0x0 0x0

Figure 26-33.

SYNC

Command Format

4 3 2

0x1

1 0

Command Sequence:

Operand Data:

Result Data:

SYNC_PC

???

NEXT CMD

CMD COMPLETE

Figure 26-34.

SYNC

Command Sequence

None

Command complete status (0xFFFF) is returned when the register write is complete.

26.4.1.5.10

Read Control Register (

RCREG

)

Read the selected control register and return the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same the processor’s MOVEC instruction uses.

Command/Result Formats:

Command

Result

15 14

0x2

0x0

12 11 10

0x9

0x0

8 7 6

0x8

0x0

D[31:16]

D[15:0]

Figure 26-35.

RCREG

Command/Result Formats

Command Sequence:

3 2

0x0

1 0

RCREG

???

MS ADDR

’NOT READY’

MS ADDR

’NOT READY’

READ

CONTROL

XXX

’NOT READY’

NEXT CMD

MS RESULT

NEXT CMD

LS RESULT

Operand Data:

XXX

BERR

Figure 26-36.

RCREG

Command Sequence

The only operand is the 32-bit Rc control register select field.

NEXT CMD

’NOT READY’

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Freescale Semiconductor 26-33

Debug Module

Result Data: Control register contents are returned as a longword, most-significant word first.

The implemented portion of registers smaller than 32 bits is guaranteed correct; other bits are undefined.

Rc encoding: See Table 26-21 .

Table 26-21. Control Register Map

Rc Register Definition

0x002

0x004

0x005

0x009

0x(0,1)80 – 0x(0,1)87

0x(0,1)88 – 0x(0,1)8F

Cache Control Register (CACR)

Access Control Register (ACR0)

Access Control Register (ACR1)

RGPIO Base Address Register (RGPIOBAR)

Data Registers 0–7 (0 = load, 1 = store)

0x800

0x801

0x804

0x805

0x806

0x807

0x808

0x809

0x80A

0x80B

0x80E

0x80F

Address Registers 0–7 (0 = load, 1 = store)

(A7 is user stack pointer)

Other Stack Pointer (OTHER_A7)

Vector Base Register (VBR)

MAC Status Register (MACSR)

MAC Mask Register (MASK)

MAC Accumulator 0 (ACC0)

MAC Accumulator 0,1 Extension Bytes (ACCEXT01)

MAC Accumulator 2,3 Extension Bytes (ACCEXT23)

MAC Accumulator 1 (ACC1)

MAC Accumulator 2 (ACC2)

MAC Accumulator 3 (ACC3)

Status Register (SR)

Program Register (PC)

0xC05 RAM Base Address Register (RAMBAR)

If an RGPIO module is available on this device.

26.4.1.5.11

BDM Accesses of the Stack Pointer Registers (A7: SSP and USP)

The ColdFire core supports two unique stack pointer (A7) registers: the supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two programmable-visible 32-bit registers does not uniquely identify one as the SSP and the other as the USP. Rather, the hardware uses one

32-bit register as the currently-active A7; the other is named the OTHER_A7. Therefore, the contents of the two hardware registers is a function of the operating mode of the processor: if SR[S] = 1 then else

A7 = Supervisor Stack Pointer

OTHER_A7 = User Stack Pointer

A7 = User Stack Pointer

OTHER_A7 = Supervisor Stack Pointer

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26-34 Freescale Semiconductor

Debug Module

The BDM programming model supports reads and writes to A7 and OTHER_A7 directly. It is the responsibility of the external development system to determine the mapping of A7 and OTHER_A7 to the two program-visible definitions (supervisor and user stack pointers), based on the SR[S] bit.

26.4.1.5.12

BDM Accesses of the EMAC Registers

The presence of rounding logic in the output datapath of the EMAC requires special care for

BDM-initiated reads and writes of its programming model. In particular, any result rounding modes must be disabled during the read/write process so the exact bit-wise EMAC register contents are accessed.

For example, a BDM read of an accumulator (ACCx) must be preceded by two commands accessing the

MAC status register, as shown in the following sequence:

BdmReadACCx ( rcreg wcreg macsr;

#0,macsr;

// read current macsr contents and save

// disable all rounding modes rcreg ACCx; // read the desired accumulator wcreg #saved_data,macsr;// restore the original macsr

)

Likewise, to write an accumulator register, the following BDM sequence is needed:

BdmWriteACCx ( rcreg macsr; wcreg #0,macsr; wcreg #data,ACCx;

// read current macsr contents and save

// disable all rounding modes

// write the desired accumulator wcreg #saved_data,macsr;// restore the original macsr

)

Additionally, writes to the accumulator extension registers must be performed after the corresponding accumulators are updated because a write to any accumulator alters the corresponding extension register contents.

For more information on saving and restoring the complete EMAC programming model, see

Section 4.3.1.2, “Saving and Restoring the EMAC Programming Model.”

26.4.1.5.13

Write Control Register (

WCREG

)

The operand (longword) data is written to the specified control register. The write alters all 32 register bits.

See the RCREG instruction description for the Rc encoding and for additional notes on writes to the A7 stack pointers and the EMAC programming model.

Command/Result Formats:

Command

Result

15 14

0x2

0x0

12 11 10

0x8

0x0

8 7 6

0x8

0x0

D[31:16]

D[15:0]

Figure 26-37.

WCREG

Command/Result Formats

4 3 2

0x0

1 0

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Freescale Semiconductor 26-35

Debug Module

Command Sequence:

WCREG

???

MS ADDR

’NOT READY’

MS ADDR

’NOT READY’

MS DATA

’NOT READY’

LS DATA

’NOT READY’

WRITE

CONTROL

XXX

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

Operand Data:

Result Data:

NEXT CMD

’NOT READY’

Figure 26-38.

WCREG

Command Sequence

This instruction requires two longword operands. The first selects the register to the operand data writes to; the second contains the data.

Successful write operations return 0xFFFF. Bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of

0x0001.

26.4.1.5.14

Read Debug Module Register (

RDMREG

)

Read the selected debug module register and return the 32-bit result. The only valid register selection for the RDMREG command is CSR.

Command/Result Formats:

Command

Result

15 14

0x2

13 12 11 10

0xD

9 8 7 6

100

5 4

D[31:16]

D[15:0]

Figure 26-39.

RDMREG

Command/Result Formats

3 2

DRc

1 0

Table 26-22

shows the definition of DRc encoding.

Table 26-22. Definition of DRc Encoding—Read

DRc[4:0]

0x00

Debug Register Definition

Configuration/Status

Mnemonic

CSR

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26-36 Freescale Semiconductor

Debug Module

Command Sequence:

Operand Data:

Result Data:

RDMREG

???

XXX

MS RESULT

NEXT CMD

LS RESULT

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

Operand Data:

Result Data:

Figure 26-40.

RDMREG

Command Sequence

None

The contents of the selected debug register are returned as a longword value. The data is returned most-significant word first.

26.4.1.5.15

Write Debug Module Register (

WDMREG

)

The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction.

Command Format:

Figure 26-41.

WDMREG

BDM Command Format

15 14

0x2

13 12 11 10

0xC

9 8 7 6

100

5 4 3 2

DRc

1 0

D[31:16]

D[15:0]

Table 26-3

shows the definition of the DRc write encoding.

Command Sequence:

WDMREG

???

MS DATA

’NOT READY’

LS DATA

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

Figure 26-42.

WDMREG

Command Sequence

Longword data is written into the specified debug register. The data is supplied most-significant word first.

Command complete status (0xFFFF) is returned when register write is complete.

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26.4.2 Real-Time Debug Support

The ColdFire family provides support debugging real-time applications. For these types of embedded systems, the processor must continue to operate during debug. The foundation of this area of debug support is that while the processor cannot be halted to allow debugging, the system can generally tolerate the small intrusions of the BDM inserting instructions into the pipeline with minimal effect on real-time operation.

The debug module provides four types of breakpoints: PC with mask, PC without mask, operand address range, and data with mask. These breakpoints can be configured into one- or two-level triggers with the exact trigger response also programmable. The debug module programming model can be written from the external development system using the debug serial interface or from the processor’s supervisor programming model using the WDEBUG instruction. Only CSR is readable using the external development system.

26.4.2.1

Theory of Operation

Breakpoint hardware can be configured through TDR[TCR] to respond to triggers by displaying DDATA,

initiating a processor halt, or generating a debug interrupt. As shown in Table 26-23

, when a breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status, operands, or branch addresses.

Table 26-23. DDATA[3:0]/CSR[BSTAT] Breakpoint Response

DDATA[3:0]

CSR[BSTAT]

Breakpoint Status

0000

0010

0100

1010

0000

0001

0010

0101

No breakpoints enabled

Waiting for level-1 breakpoint

Level-1 breakpoint triggered

Waiting for level-2 breakpoint

1100 0110 Level-2 breakpoint triggered

Encodings not shown are reserved for future use.

The breakpoint status is also posted in the CSR. CSR[BSTAT] is cleared by a CSR read when a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. Status is also cleared by writing to TDR to disable trigger options.

BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates, a breakpoint trigger generates the response defined in TDR.

PC breakpoints are treated in a precise manner—exception recognition and processing are initiated before the excepting instruction executes. All other breakpoint events are recognized on the processor’s local bus, but are made pending to the processor and sampled like other interrupt conditions. As a result, these interrupts are imprecise.

In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] equals 01, a breakpoint trigger causes the core to halt (PST = 0xF).

If the processor core cannot be halted, the debug interrupt can be used. With this configuration,

TDR[TRC] equals 10, breakpoint trigger becomes a debug interrupt to the processor, which is treated

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higher than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC breakpoint to occur before the targeted instruction executes and is precise. This is possible because the PC breakpoint is enabled when interrupt sampling occurs. For address and data breakpoints, reporting is considered imprecise, because several instructions may execute after the triggering address or data is detected.

As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for multiple cycles. The core enters emulator mode when exception processing begins. After the standard

8-byte exception stack is created, the processor fetches a unique exception vector, 12, from the vector table.Refer to the ColdFire Programmer’s Reference Manual. for more information.

Execution continues at the instruction address in the vector corresponding to the debug interrupt. All interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use supervisor instructions to save the necessary context, such as the state of all program-visible registers into a reserved memory area.

When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator mode. After the debug interrupt handler completes execution, the external development system can use

BDM commands to read the reserved memory locations.

In revision B/B+, the hardware inhibits generation of another debug interrupt during the first instruction after the RTE exits emulator mode. This behavior is consistent with the logic involving trace mode where the first instruction executes before another trace exception is generated. Thus, all hardware breakpoints are disabled until the first instruction after the RTE completes execution, regardless of the programmed trigger response.

26.4.2.2

Emulator Mode

Emulator mode facilitates non-intrusive emulator functionality. This mode can be entered in three different ways:

• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is negated and the processor begins reset exception processing. It can be set while the processor is halted before reset exception processing begins. See

Section 26.4.1.1, “CPU Halt”

• A debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins.

• Setting CSR[TRC] forces the processor into emulation mode when trace exception processing begins.

While operating in emulation mode, the processor exhibits the following properties:

• All interrupts are ignored, including level-7 interrupts.

• If CSR[MAP] is set, all caching of memory and the SRAM module are disabled. All memory accesses are forced into a specially mapped address space signaled by TT equals 0x2,

TM equals 0x5, or 0x6. This includes stack frame writes and vector fetch for the exception that forced entry into this mode.

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The RTE instruction exits emulation mode. The processor status output port provides a unique encoding for emulator mode entry (0xD) and exit (0x7).

26.4.3 Concurrent BDM and Processor Operation

The debug module supports concurrent operation of the processor and most BDM commands. BDM commands may be executed while the processor is running, except these following operations that access processor/memory registers:

• Read/write address and data registers

• Read/write control registers

For BDM commands that access memory, the debug module requests the processor’s local bus. The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access. After the debug module bus cycle, the processor reclaims the bus.

NOTE

Breakpoint registers must be carefully configured in a development system if the processor is executing. The debug module contains no hardware interlocks, so TDR should be disabled while breakpoint registers are loaded, after which TDR can be written to define the exact trigger. This prevents spurious breakpoint triggers.

Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU is writing the debug’s registers (DSCLK must be inactive).

NOTE

The debug module requires the use of the internal bus to perform BDM commands. For this processor core, if the processor is executing a tight loop contained within a single aligned longword, the processor may never grant the internal bus to the debug module, for example: align4 label1: nop bra.b label1 or align4 label2: bra.w label2

The processor grants the internal bus if these loops are forced across two longwords.

26.4.4 Real-Time Trace Support

Real-time trace, which defines the dynamic execution path and is also known as instruction trace, is a fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system. This port is partitioned into two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and the other allows operand data to

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be displayed (debug data, DDATA). The processor status may not be related to the current bus transfer, due to the decoupling FIFOs.

External development systems can use PST outputs with an external image of the program to completely track the dynamic execution path. This tracking is complicated by any change in flow, where branch target address calculation is based on the contents of a program-visible register (variant addressing). DDATA outputs can display the target address of such instructions in sequential nibble increments across multiple

processor clock cycles, as described in Section 26.4.4.1, “Begin Execution of Taken Branch (PST = 0x5)”

Two 32-bit storage elements form a FIFO buffer connecting the processor’s high-speed local bus to the external development system through PST[3:0] and DDATA[3:0]. The buffer captures branch target addresses and certain data values for eventual display on the DDATA port, one nibble at a time starting with the least significant bit (lsb).

Execution speed is affected only when both storage elements contain valid data to be dumped to the

DDATA port. The core stalls until one FIFO entry is available.

Table 26-24

shows the encoding of these signals.

Table 26-24. Processor Status Encoding

PST[3:0]

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8–

0xB

Definition

Continue execution. Many instructions execute in one processor cycle. If an instruction requires more clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.

Begin execution of one instruction. For most instructions, this encoding signals the first processor clock cycle of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions, generate different encodings.

Reserved

Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to enter user mode.

Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to the DDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is signaled on the PST port, followed by the appropriate marker, and then the data transfer on the DDATA port.

Transfer length depends on the WDDATA operand size.

Begin execution of taken branch or SYNC_PC command issued. For some opcodes, a branch target address may be displayed on DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins the data output. See

Section 26.4.4.1, “Begin Execution of Taken Branch (PST = 0x5)”

. Also indicates that the

SYNC_PC command has been issued.

Reserved

Begin execution of return from exception (RTE) instruction.

Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles. The value is driven onto the PST port one PSTCLK cycle before the data is displayed on DDATA.

0x8 Begin 1-byte transfer on DDATA.

0x9 Begin 2-byte transfer on DDATA.

0xA Begin 3-byte transfer on DDATA.

0xB Begin 4-byte transfer on DDATA.

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Table 26-24. Processor Status Encoding (continued)

PST[3:0]

0xC

0xD

0xE

0xF

Definition

Normal exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace) generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle mode, PST outputs are driven with 0xC until exception processing completes.

Emulator mode exception processing.

Displayed during emulation mode (debug interrupt or optionally trace). Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception processing completes.

Processor is stopped. Appears in multiple-cycle format when the processor executes a STOP instruction.

The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the stopped mode is exited.

Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF until

the processor is restarted or reset. See Section 26.4.1.1, “CPU Halt

”.

26.4.4.1

Begin Execution of Taken Branch (PST = 0x5)

PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed on DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data output.

Multiple byte DDATA values are displayed in least-to-most-significant order. The processor captures only those target addresses associated with taken branches that use a variant addressing mode (RTE and RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and all exception vectors).

The simplest example of a branch instruction using a variant address is the compiled code for a C language case statement. Typically, the evaluation of this statement uses the variable of an expression as an index into a table of offsets, where each offset points to a unique case within the structure. For such change-of-flow operations, the ColdFire processor uses the debug pins to output the following sequence of information on two successive processor clock cycles:

1. Use PST (0x5) to identify that a taken branch is executed.

2. Using the PST pins, optionally signal the target address to be displayed sequentially on the DDATA pins. Encodings 0x9–0xB identify the number of bytes displayed.

3. The new target address is optionally available on subsequent cycles using the DDATA port. The number of bytes of displayed on this port is configurable (2, 3, or 4 bytes, where the DDATA encoding is 0x9, 0xA, and 0xB, respectively).

Another example of a variant branch instruction would be a JMP (A0) instruction.

Figure 26-43

shows the

PST and DDATA outputs that indicate a JMP (A0) execution, assuming the CSR was programmed to display the lower 2 bytes of an address.

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PSTCLK

PST

0x5 0x9 default default default default

DDATA 0x0 0x0 A[3:0] A[7:4] A[11:8] A[15:12]

Figure 26-43. Example JMP Instruction Output on PST/DDATA

PST of 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Therefore, the subsequent 4 nibbles of DDATA display the lower two bytes of address register A0 in least-to-most-significant nibble order. The PST output after the JMP instruction completes depends on the target instruction. The PST can continue with the next instruction before the address has completely displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO.

26.4.5 Processor Status, Debug Data Definition

This section specifies the ColdFire processor and debug module’s generation of the processor status (PST) and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA output for an instruction is defined as follows:

PST = 0x1, {PST = [0x89B], DDATA = operand} where the {...} definition is optional operand information defined by the setting of the CSR.

The CSR provides capabilities to display operands based on reference type (read, write, or both). A PST value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to follow on the DDATA output {1,

2, or 4 bytes}. Additionally, for certain change-of-flow branch instructions, CSR[BTB] provides the capability to display the target instruction address on the DDATA output {2, 3, or 4 bytes} using a PST value of {0x9, 0xA, or 0xB}.

26.4.5.1

User Instruction Set

Table 26-25

shows the PST/DDATA specification for user-mode instructions. Rn represents any {Dn, An} register. In this definition, the y suffix generally denotes the source, and x denotes the destination operand.

For a given instruction, the optional operand data is displayed only for those effective addresses referencing memory. The DD nomenclature refers to the DDATA outputs.

Table 26-25. PST/DDATA Specification for User-Mode Instructions

Instruction Operand Syntax

add.l

adda.l

addi.l

<ea>y,Dx

Dy,<ea>x

<ea>y,Ax

#<data>,Dx

PST/DDATA

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1

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Table 26-25. PST/DDATA Specification for User-Mode Instructions (continued)

cmpa.l

cmpi.l

divs.l

divs.w

divu.l

divu.w

eor.l

eori.l

ext.l

bsr.{b,w} btst.{b,l} btst.{b,l} byterev.l

clr.b

clr.l

clr.w

cmp.l

bchg.{b,l} bchg.{b,l} bclr.{b,l} bclr.{b,l} bitrev.l

bra.{b,w} bset.{b,l} bset.{b,l} addq.l

addx.l

and.l

andi.l

asl.l

asr.l

bcc.{b,w}

Instruction Operand Syntax

#<data>,<ea>x

Dy,Dx

<ea>y,Dx

Dy,<ea>x

#<data>,Dx

{Dy,#<data>},Dx

#<data>,<ea>x

Dy,<ea>x

#<data>,<ea>x

Dy,<ea>x

#<data>,<ea>x

Dy,<ea>x

#<data>,<ea>x

Dy,<ea>x

<ea>x

<ea>y,Dx

<ea>y,Ax

#<data>,Dx

<ea>y,Dx

Dy,<ea>x

#<data>,Dx

PST/DDATA

PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}

PST = 0x1

PST = 0x1 if taken, then PST = 0x5, else PST = 0x1

PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}

PST = 0x1

PST = 0x5

PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}

PST = 0x5, {PST = 0xB, DD = destination operand}

PST = 0x1, {PST = 0x8, DD = source operand}

PST = 0x1

PST = 0x1, {PST = 0x8, DD = destination operand}

PST = 0x1, {PST = 0xB, DD = destination operand}

PST = 0x1, {PST = 0x9, DD = destination operand}

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0x9, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0x9, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}

PST = 0x1

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Table 26-25. PST/DDATA Specification for User-Mode Instructions (continued)

nop not.l

or.l

mulu.l

mulu.w

neg.l

negx.l

ori.l

pea.l

pulse move.w

movea.l

movea.w

movem.l

moveq.l

muls.l

muls.w

lea.l

link.w

lsl.l

lsr.l

move.b

move.l

move.w

Instruction Operand Syntax

ext.w

extb.l

illegal jmp jsr

<ea>y

PST/DDATA

PST = 0x1

PST = 0x5, {PST = [0x9AB], DD = target address}

PST = 0x5, {PST = [0x9AB], DD = target address},

{PST = 0xB, DD = destination operand}

<ea>y,Ax PST = 0x1

Ay,#<displacement> PST = 0x1, {PST = 0xB, DD = destination operand}

{Dy,#<data>},Dx

PST = 0x1

<ea>y,<ea>x

CCR,Dx

PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}

PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}

PST = 0x1, {PST = 0x9, DD = source}, {PST = 0x9, DD = destination}

PST = 0x1

{Dy,#<data>},CCR PST = 0x1

<ea>y,Ax PST = 0x1, {PST = 0xB, DD = source}

<ea>y,Ax

#list,<ea>x

<ea>y,#list

#<data>,Dx

<ea>y,Dx

PST = 0x1, {PST = 0x9, DD = source}

PST = 0x1, {PST = 0xB, DD = destination},...

PST = 0x1, {PST = 0xB, DD = source},...

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0x9, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0x9, DD = source operand}

PST = 0x1

<ea>y,Dx

Dy,<ea>x

#<data>,Dx

<ea>y

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}

PST = 0x1

PST = 0x1, {PST = 0xB, DD = destination operand}

PST = 0x4

Debug Module

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Table 26-25. PST/DDATA Specification for User-Mode Instructions (continued)

tpf tpf.l

tpf.w

trap tst.b

tst.l

tst.w

unlk scc.b

sub.l

suba.l

subi.l

subq.l

subx.l

swap.w

wddata.b

wddata.l

wddata.w

Instruction Operand Syntax

rems.l

remu.l

rts

<ea>y,Dw:Dx

<ea>y,Dx

Dy,<ea>x

<ea>y,Ax

#<data>,Dx

#<data>,<ea>x

Dy,Dx

#<data>

<ea>x

<ea>y

PST/DDATA

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source operand},

PST = 0x5, {PST = [0x9AB], DD = target address}

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}

PST = 0x1

PST = 0x1, {PST = 0x8, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0x9, DD = source operand}

PST = 0x1, {PST = 0xB, DD = destination operand}

PST = 0x4, {PST = 0x8, DD = source operand

PST = 0x4, {PST = 0xB, DD = source operand

PST = 0x4, {PST = 0x9, DD = source operand

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During normal exception processing, the PST output is driven to a 0xC indicating the exception processing state.

The exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed.

Exception Processing:

PST = 0xC,

{PST = 0xB,DD = destination},

{PST = 0xB,DD = source},

// stack frame

// vector read

PST = 0x5,{PST = [0x9AB],DD = target}// handler PC

The PST

DDATA specification for the reset exception is shown below:

Exception Processing:

PST = 0xC,

The initial references at address 0 and 4 are never captured nor displayed because these accesses are treated as instruction fetches.

For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST output is needed for one of the optional marker values or for the taken branch indicator (0x5).

For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi),

(d8,PC,Xi).

For move multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the operand address reaches a 0-modulo-16 boundary and there are four or more registers to be transferred. For these line-sized transfers, the operand data is never captured nor displayed, regardless of the CSR value.

The automatic line-sized burst transfers are provided to maximize performance during these sequential memory access operations.

Table 26-26

shows the PST/DDATA specification for multiply-accumulate instructions.

Table 26-26. PST/DDATA Values for User-Mode Multiply-Accumulate Instructions

Instruction

move.l

mac.l

mac.w

move.l

Operand Syntax PST/DDATA

Ry,Rx,ACCx

Ry,Rx,<ea>y,Rw,ACCx

Ry,Rx,ACCx

Ry,Rx,ea,Rw,ACCx

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source operand}

{Ry,#<data>},ACCx PST = 0x1

{Ry,#<data>},MACSR PST = 0x1

{Ry,#<data>},MASK PST = 0x1

{Ry,#<data>},ACCext01 PST = 0x1

{Ry,#<data>},ACCext23 PST = 0x1

ACCext01,Rx PST = 0x1

ACCext23,Rx PST = 0x1

ACCy,ACCx PST = 0x1

ACCy,Rx PST = 0x1

MACSR,CCR PST = 0x1

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Table 26-26. PST/DDATA Values for User-Mode Multiply-Accumulate Instructions (continued)

Instruction

move.l

msac.l

msac.w

Operand Syntax PST/DDATA

MACSR,Rx PST = 0x1

MASK,Rx PST = 0x1

Ry,Rx,ACCx

Ry,Rx,<ea>y,Rw,ACCx

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source operand}

Ry,Rx,ACCx

Ry,Rx,<ea>y,Rw,ACCx

PST = 0x1

PST = 0x1, {PST = 0xB, DD = source operand}

26.4.5.2

Supervisor Instruction Set

The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below. The PST/DDATA specification for these opcodes is shown in

Table 26-27 .

Table 26-27. PST/DDATA Specification for Supervisor-Mode Instructions

Instruction Operand Syntax PST/DDATA

cpushl halt

(Ax) move.l Ay,USP move.l USP,Ax move.w

move.w

SR,Dx

PST = 0x1

{Dy,#<data>},SR PST = 0x1, {PST = 0x3} movec.l

rte

Ry,Rc

PST = 0x1

PST = 0x1,

PST = 0xF stldsr.w

stop wdebug.l

#imm

#<data>

<ea>y

PST = 0x1

PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 0x3}, { PST = 0xB,

DD =source operand},

PST = 0x5, {[PST = 0x9AB], DD = target address}

PST = 0x1, {PST = 0xA, DD = destination operand, PST = 0x3}

PST = 0x1,

PST = 0xE

PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}

The move-to-SR and RTE instructions include an optional PST = 0x3 value, indicating an entry into user mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, a multiple-cycle status of 0xD is signaled.

Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state (PST = 0xFF) display this status throughout the entire time the ColdFire processor is in the given mode.

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26.4.6 Freescale-Recommended BDM Pinout

The ColdFire BDM connector is a 26-pin Berg connector arranged 2 x 13 as shown below.

Developer reserved

GND

RESET

EVDD

GND

PST2

PST0

DDATA2

DDATA0

Freescale reserved

GND

IVDD

BKPT

DSCLK

Developer reserved

DSI

DSO

PST3

PST1

DDATA3

DDATA1

GND

Freescale reserved

PSTCLK

Pins reserved for BDM developer use.

Supplied by target

Figure 26-44. Recommended BDM Connector

Debug Module

Freescale Semiconductor

MCF5208 Reference Manual, Rev 2

26-49

Debug Module

26-50

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Freescale Semiconductor

Chapter 27 IEEE 1149.1 Test Access Port (JTAG)

27.1 Introduction

The Joint Test Action Group (JTAG) is a dedicated user-accessible test logic compliant with the

IEEE 1149.1 standard for boundary-scan testability, which helps with system diagnostic and manufacturing testing.

This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST.

27.1.1 Block Diagram

Figure 27-1

shows the block diagram of the JTAG module.

TAP Controller

1-bit Bypass Register

TDI/DSI

Boundary Scan Register

32-bit IDCODE Register

1-bit TEST_CTRL Register

5-bit TAP Instruction Decoder

5-bit TAP Instruction Register

TDO/DSO

JTAG_EN

TCLK

TMS/BKPT

TRST/DSCLK

JTAG Module

Disable DSCLK

Force BKPT = 1

DSI = 0

DSO to Debug Module

Figure 27-1. JTAG Block Diagram

DSI

BKPT

DSCLK

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Freescale Semiconductor 27-1

IEEE 1149.1 Test Access Port (JTAG)

27.1.2 Features

The basic features of the JTAG module are the following:

• Performs boundary-scan operations to test circuit board electrical continuity

• Bypasses instruction to reduce the shift register path to a single cell

• Sets chip output pins to safety states while executing the bypass instruction

• Samples the system pins during operation and transparently shifts out the result

• Selects between JTAG TAP controller and Background Debug Module (BDM) using a dedicated

JTAG_EN pin

27.1.3 Modes of Operation

The JTAG_EN pin can select between the following modes of operation:

• JTAG mode (JTAG_EN = 1)

•

Background debug mode (BDM)—for more information, refer to Section 26.4.1, “Background

Debug Mode (BDM)”

; (JTAG_EN = 0).

27.2 External Signal Description

The JTAG module has five input and one output external signals, as described in

Table 27-1 .

Table 27-1. Signal Properties

Name

JTAG_EN

TCLK

TMS/BKPT

TDI/DSI

TRST/DSCLK

TDO/DSO

Direction

Input

Output

Function

JTAG/BDM selector input

JTAG Test clock input

JTAG Test mode select / BDM Breakpoint

JTAG Test data input / BDM Development serial input

JTAG Test reset input / BDM Development serial clock

JTAG Test data output / BDM Development serial output

Reset State

—

Hi-Z / 0

Pull up

—

Active

—

27.2.1 JTAG Enable (JTAG_EN)

The JTAG_EN pin selects between the debug module and JTAG. If JTAG_EN is low, the debug module is

selected; if it is high, the JTAG is selected. Table 27-2

summarizes the pin function selected depending on

JTAG_EN logic state.

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MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

IEEE 1149.1 Test Access Port (JTAG)

Module selected

Pin Function

Table 27-2. Pin Function Selected

JTAG_EN = 0

BDM

—

BKPT

DSI

DSO

DSCLK

JTAG_EN = 1

JTAG

TCLK

TMS

TDI

TDO

TRST

Pin Name

—

TCLK

BKPT

DSI

DSO

DSCLK

When one module is selected, the inputs into the other module are disabled or forced to a known logic

level, as shown in Table 27-3 , to disable the corresponding module.

Table 27-3. Signal State to the Disable Module

Disabling JTAG

Disabling BDM

JTAG_EN = 0

TRST = 0

TMS = 1

—

JTAG_EN = 1

—

Disable DSCLK

DSI = 0

BKPT = 1

NOTE

The JTAG_EN does not support dynamic switching between JTAG and

BDM modes.

27.2.2 Test Clock Input (TCLK)

The TCLK pin is a dedicated JTAG clock input to synchronize the test logic. Pulses on TCLK shift data and instructions into the TDI pin on the rising edge and out of the TDO pin on the falling edge. TCLK is independent of the processor clock. The TCLK pin has an internal pull-up resistor, and holding TCLK high or low for an indefinite period does not cause JTAG test logic to lose state information.

27.2.3 Test Mode Select/Breakpoint (TMS/BKPT)

The TMS pin is the test mode select input that sequences the TAP state machine. TMS is sampled on the rising edge of TCLK. The TMS pin has an internal pull-up resistor.

The BKPT pin is used to request an external breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes.

27.2.4 Test Data Input/Development Serial Input (TDI/DSI)

The TDI pin receives serial test and data, which is sampled on the rising edge of TCLK. Register values are shifted in least significant bit (lsb) first. The TDI pin has an internal pull-up resistor.

The DSI pin provides data input for the debug module serial communication port.

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor 27-3

IEEE 1149.1 Test Access Port (JTAG)

27.2.5 Test Reset/Development Serial Clock (TRST/DSCLK)

The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the

TAP controller to the test-logic-reset state.

The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency is 1/5 the processor clock speed. At the rising edge of DSCLK, data input on DSI is sampled and DSO changes state.

27.2.6 Test Data Output/Development Serial Output (TDO/DSO)

The TDO pin is the lsb-first data output. Data is clocked out of TDO on the falling edge of TCLK. TDO is tri-stateable and actively driven in the shift-IR and shift-DR controller states.

The DSO pin provides serial output data in BDM mode.

27.3 Memory Map/Register Definition

The JTAG module registers are not memory mapped and are only accessible through the TDO/DSO pin.

27.3.1 Instruction Shift Register (IR)

The JTAG module uses a 5-bit shift register with no parity. The IR transfers its value to a parallel hold register and applies an instruction on the falling edge of TCLK when the TAP state machine is in the update-IR state. To load an instruction into the shift portion of the IR, place the serial data on the TDI pin before each rising edge of TCLK. The msb of the IR is the bit closest to the TDI pin, and the lsb is the bit

closest to the TDO pin. See Section 27.4.3, “JTAG Instructions”

for a list of possible instruction codes.

TAP state: Update-IR

Reset

Access: User read/write

Instruction Code

0 0 0

Figure 27-2. 5-Bit Instruction Register (IR)

27-4

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Freescale Semiconductor

IEEE 1149.1 Test Access Port (JTAG)

27.3.2 IDCODE Register

The IDCODE is a read-only register; its value is chip dependent. For more information, see

Section 27.4.3.1, “IDCODE Instruction”

IR[4:0]: 0_0001 (IDCODE) Access: User read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRN DC PIN JEDEC ID

Reset See note

See note

The reset values for PRN and PIN are device-dependent.

Varies, depending on design center location.

0 0 0 0 0 0 0 1 1 1 0 1

Figure 27-3. IDCODE Register

Table 27-4. IDCODE Field Descriptions

Field

31–28

PRN

27–22

21–12

Description

Part revision number. Indicate the revision number of the device.

Freescale design center number.

Part identification number. Indicate the device number.

0x044 MCF5208

0x045 MCF5207

11–1

JEDEC

Joint Electron Device Engineering Council ID bits. Indicate the reduced JEDEC ID for Freescale (0x0E).

IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and not the bypass register according to the IEEE standard 1149.1.

27.3.3 Bypass Register

The bypass register is a single-bit shift register path from TDI to TDO when the BYPASS, CLAMP, or

HIGHZ instructions are selected. After entry into the capture-DR state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the bypass register is always a logic 0.

27.3.4 TEST_CTRL Register

The TEST_CTRL register is a 1-bit shift register path from TDI to TDO when the

ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold register on the rising edge of TCLK when the TAP state machine is in the update-DR state. The DSE bit selects the drive strength used in JTAG mode.

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Freescale Semiconductor 27-5

IEEE 1149.1 Test Access Port (JTAG)

IR[4:0]: 0_0110 Access: User read-only

Reset

DSE

Figure 27-4. 1-Bit TEST_CTRL Register

27.3.5 Boundary Scan Register

The boundary scan register is connected between TDI and TDO when the EXTEST or

SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on output pins, and selects a logic value and direction for bidirectional pins or high impedance for tri-stated pins.

The boundary scan register contains bits for bonded-out and non bonded-out signals, excluding JTAG signals, analog signals, power supplies, compliance enable pins, device configuration pins, and clock signals.

27.4 Functional Description

27.4.1 JTAG Module

The JTAG module consists of a TAP controller state machine, which is responsible for generating all control signals that execute the JTAG instructions and read/write data registers.

27.4.2 TAP Controller

The TAP controller is a state machine that changes state based on the sequence of logical values on the

TMS pin. Figure 27-5 shows the machine’s states. The value shown next to each state is the value of the

TMS signal sampled on the rising edge of the TCLK signal.

Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state. As

Figure 27-5

shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state.

27-6

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor

IEEE 1149.1 Test Access Port (JTAG)

1 TEST-LOGIC-RESET

0 RUN-TEST/IDLE

SELECT DR-SCAN

CAPTURE-DR

SHIFT-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

1 0

SELECT IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

1 0

Figure 27-5. TAP Controller State Machine Flow

27.4.3 JTAG Instructions

Table 27-5

describes public and private instructions.

Table 27-5. JTAG Instructions

Instruction

IDCODE

SAMPLE/PRELOAD

SAMPLE

IR[4:0] Instruction Summary

00001 Selects IDCODE register for shift

00010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation

00011 Selects boundary scan register for shifting and sampling without disturbing functional operation

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Freescale Semiconductor 27-7

IEEE 1149.1 Test Access Port (JTAG)

Table 27-5. JTAG Instructions (continued)

Instruction IR[4:0] Instruction Summary

EXTEST

ENABLE_TEST_CTRL

HIGHZ

CLAMP

00100 Selects boundary scan register while applying preloaded values to output pins and asserting functional reset

00110 Selects TEST_CTRL register

01001 Selects bypass register while tri-stating all output pins and asserting functional reset

01100 Selects bypass while applying fixed values to output pins and asserting functional reset

BYPASS

Reserved

11111 Selects bypass register for data operations all others

Decoded to select bypass register

Freescale reserves the right to change the decoding of the unused opcodes in the future.

27.4.3.1

IDCODE Instruction

The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path between the

TDI and TDO pin. This instruction allows interrogation of the MCU to determine its version number and other part identification data. The shift register lsb is forced to logic 1 on the rising edge of TCLK following entry into the capture-DR state. Therefore, the first bit to be shifted out after selecting the

IDCODE register is always a logic 1. The remaining 31 bits are also forced to fixed values on the rising edge of TCLK following entry into the capture-DR state.

IDCODE is the default instruction placed into the instruction register when the TAP resets. Thus, after a

TAP reset, the IDCODE register is selected automatically.

27.4.3.2

SAMPLE/PRELOAD Instruction

The SAMPLE/PRELOAD instruction has two functions:

•

SAMPLE - See Section 27.4.3.3, “SAMPLE Instruction,”

for description of this function.

• PRELOAD - initialize the boundary scan register update cells before selecting EXTEST or

CLAMP. This is achieved by ignoring the data shifting out on the TDO pin and shifting in initialization data. The update-DR state and the falling edge of TCLK can then transfer this data to the update cells. The data is applied to the external output pins by the EXTEST or CLAMP instruction.

27.4.3.3

SAMPLE Instruction

The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input pins and before the boundary scan cell at the output pins. This sampling occurs on the rising edge of TCLK in the capture-DR state when the IR contains the 0x2 opcode. The sampled data is accessible by shifting it through the boundary scan register to the TDO output by using the shift-DR state. The data capture and the shift operation are transparent to system operation.

MCF5208 Reference Manual, Rev 2

27-8 Freescale Semiconductor

IEEE 1149.1 Test Access Port (JTAG)

NOTE

External synchronization is required to achieve meaningful results because there is no internal synchronization between TCLK and the system clock.

27.4.3.4

EXTEST Instruction

The external test (EXTEST) instruction selects the boundary scan register. It forces all output pins and bidirectional pins configured as outputs to the values preloaded with the SAMPLE/PRELOAD instruction and held in the boundary scan update registers. EXTEST can also configure the direction of bidirectional pins and establish high-impedance states on some pins. EXTEST asserts internal reset for the MCU system logic to force a predictable internal state while performing external boundary scan operations.

27.4.3.5

ENABLE_TEST_CTRL Instruction

The ENABLE_TEST_CTRL instruction selects a 1-bit shift register (TEST_CTRL) for connection as a shift path between the TDI and TDO pin. When the user transitions the TAP controller to the UPDATE_DR state, the register transfers its value to a parallel hold register.

27.4.3.6

HIGHZ Instruction

The HIGHZ instruction eliminates the need to backdrive the output pins during circuit-board testing.

HIGHZ turns off all output drivers, including the 2-state drivers, and selects the bypass register. HIGHZ also asserts internal reset for the MCU system logic to force a predictable internal state.

27.4.3.7

CLAMP Instruction

The CLAMP instruction selects the 1-bit bypass register and asserts internal reset while simultaneously forcing all output pins and bidirectional pins configured as outputs to the fixed values that are preloaded and held in the boundary scan update register. CLAMP enhances test efficiency by reducing the overall shift path to a single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary scan register.

27.4.3.8

BYPASS Instruction

The BYPASS instruction selects the bypass register, creating a single-bit shift register path from the TDI pin to the TDO pin. BYPASS enhances test efficiency by reducing the overall shift path when a device other than the ColdFire processor is the device under test on a board design with multiple chips on the overall boundary scan chain. The shift register lsb is forced to logic 0 on the rising edge of TCLK after entry into the capture-DR state. Therefore, the first bit shifted out after selecting the bypass register is always logic 0. This differentiates parts that support an IDCODE register from parts that support only the bypass register.

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MCF5208 Reference Manual, Rev 2

27-9

IEEE 1149.1 Test Access Port (JTAG)

27.5 Initialization/Application Information

27.5.1 Restrictions

The test logic is a static logic design, and TCLK can be stopped in a high or low state without loss of data.

However, the system clock is not synchronized to TCLK internally. Any mixed operation using the test logic and system functional logic requires external synchronization.

Using the EXTEST instruction requires a circuit-board test environment that avoids device-destructive configurations in which MCU output drivers are enabled into actively driven networks.

Low-power stop mode considerations:

• The TAP controller must be in the test-logic-reset state to enter or remain in the low-power stop mode. Leaving the test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality.

• The TCLK input is not blocked in low-power stop mode. To consume minimal power, the TCLK input should be externally connected to EV

• The TMS, TDI, and TRST pins include on-chip pull-up resistors. For minimal power consumption in low-power stop mode, these three pins should be connected to EV

or left unconnected.

27.5.2 Nonscan Chain Operation

Keeping the TAP controller in the test-logic-reset state ensures that the scan chain test logic is transparent to the system logic. It is recommended that TMS, TDI, TCLK, and TRST be pulled up. TRST could be connected to ground. However, because there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST.

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Appendix A

Register Memory Map Quick Reference

A.1 Register Memory Map

Table A-1 illustrates the overall device memory map. Table A-2

lists the base address for each peripheral within the peripheral controller space. Each module is then detailed in

summarize the ColdFire core and debug registers, which are not accessible through the memory map but are included here for completeness.

Table A-1. Device Memory Map Overview

Address Range Module Size

0x0000_0000–0x3FFF_FFFF

0x4000_0000–0x7FFF_FFFF

FlexBus

SDRAM Controller

1024 MB

0x8000_0000–0x8FFF_FFFF Internal SRAM Backdoor 256 MB

0xC000_0000–0xDFFF_FFFF

0xF000_0000–0xFFFF_FFFF

FlexBus

On-chip Peripheral Controller 0

512 MB

256 MB

See the various tables below or the peripheral chapters for their memory maps. Any unused space by these peripherals within this memory range is reserved and should not be accessed.

NOTE

This memory map provides two disjoint regions mapped to the FlexBus controller to support glueless connections to external memories (e.g., flash and SRAM) as well as a second space with one (or more) unique chip-selects that can be used for non-cacheable, non-memory devices

(addresses 0xC000_0000–0xDFFF_FFFF). Additionally, this mapping is selected because it easily maps into the ColdFire access control registers, which provide a coarse association between memory addresses and their attributes (e.g., cacheable, non-cacheable). For this device, one possible configuration defines the default memory attribute as non-chacheable, and one ACR is then used to identify cacheable addresses, e.g., ADDR[31]=0 identifies the cacheable space.

Table A-2. Peripheral Controller 0 Base Addresses

Base Address

0xFC00_0000

0xFC00_4000

Slot Number

Peripheral

SCM (MPR1, PACRs, & BMT1)

Cross-bar switch

Module Memory Map

Table A-5

Table A-6

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor A-1

Register Memory Map Quick Reference

Base Address

0xFC00_8000

0xFC03_0000

0xFC04_0000

0xFC04_4000

0xFC04_8000

0xFC05_4000

0xFC05_8000

0xFC05_C000

0xFC06_0000

0xFC06_4000

0xFC06_8000

0xFC07_0000

0xFC07_4000

0xFC07_8000

0xFC07_C000

0xFC08_0000

0xFC08_4000

0xFC08_8000

0xFC08_C000

0xFC09_0000

0xFC0A_0000

0xFC0A_4000

0xFC0A_8000

Slot Number

Table A-2. Peripheral Controller 0 Base Addresses (continued)

Peripheral

FlexBus

FEC

SCM (CWT & Core Fault Registers) eDMA Controller

Interrupt Controller 0

Interrupt Controller IACK

QSPI

UART0

UART1

UART2

DMA Timer 0

DMA Timer 1

DMA Timer 2

DMA Timer 3

PIT 0

PIT 1

Edge Port

On-chip Watchdog Timer

PLL

CCM, Reset Controller, Power Management

GPIO Module

SDRAM Controller

Module Memory Map

BDM

Table A-3. ColdFire Core Programming Model

Register

Data Register 0 (D0)

Width

(bits)

Access Reset Value

Written with

MOVEC

Section/Page

Supervisor/User Access Registers

32 R/W 0xCF20_60 No

3.2.1/3-4

Load: 0x080

Store: 0x180

Load: 0x081

Store: 0x181

Data Register 1 (D1) 32 R/W 0x1500_1060 No

3.2.1/3-4

MCF5208 Reference Manual, Rev 2

A-2 Freescale Semiconductor

Register Memory Map Quick Reference

Table A-3. ColdFire Core Programming Model (continued)

BDM

Register

Width

(bits)

Access Reset Value

Written with

MOVEC

Section/Page

3.2.1/3-4

Load: 0x082–7

Store: 0x182–7

Data Register 2–7 (D2–D7)

Load: 0x088–8E

Store: 0x188–8E

Address Register 0–6 (A0–A6)

Load: 0x08F

Store: 0x18F

Supervisor/User A7 Stack Pointer (A7)

0x804

0x805

0x806, 0x809,

0x80A, 0x80B

0x807

MAC Status Register (MACSR)

MAC Address Mask Register (MASK)

MAC Accumulators 0–3 (ACC0–3)

0x808

0x80E

0x80F

MAC Accumulator 0,1 Extension Bytes

(ACCext01)

MAC Accumulator 2,3 Extension Bytes

(ACCext23)

Condition Code Register (CCR)

Program Counter (PC)

R/W

Undefined

0x0000_0000

0xFFFF_FFFF

Undefined

R/W

Supervisor Access Only Registers

Undefined

Contents of location

0x0000_0004

0x002

0x004–5

0x800

Cache Control Register (CACR)

Access Control Register 0–1 (ACR0–1)

User/Supervisor A7 Stack Pointer

(OTHER_A7)

R/W 0x0000_0000

R/W See Section

R/W Contents of location

0x0000_0000

Yes

3.2.6/3-7

3.2.7/3-7

3.2.3/3-5

0x801

0x80E

Vector Base Register (VBR)

Status Register (SR)

R/W

0x0000_0000

0x27--

Yes

3.2.8/3-7

3.2.9/3-8

0xC05 RAM Base Address Register (RAMBAR) 32 R/W See Section Yes

3.2.10/3-8

The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more information see

Chapter 26, “Debug Module”

DRc[4–0]

0x00

0x05

0x06

Table A-4. Debug Module Memory Map

Register Name

Configuration/status register (CSR)

BDM address attribute register (BAAR)

Address attribute trigger register (AATR)

Width

(bits)

Access Reset Value

Section/

Page

R/W

See Note

0x0090_0000

26.3.2/26-5

0x05

0x0005

26.3.3/26-8

26.3.4/26-9

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Freescale Semiconductor A-3

Register Memory Map Quick Reference

Table A-4. Debug Module Memory Map (continued)

DRc[4–0] Register Name

Width

(bits)

Access Reset Value

Section/

Page

0x07

0x08

0x09

0x0C

0x0D

0x0E

0x0F

0x18

Trigger definition register (TDR)

PC breakpoint register 0 (PBR0)

PC breakpoint mask register (PBMR)

Address breakpoint high register (ABHR)

Address breakpoint low register (ABLR)

Data breakpoint register (DBR)

Data breakpoint mask register (DBMR)

PC breakpoint register 1 (PBR1)

0x0000_0000

26.3.5/26-10

Undefined

See Section

0x1A PC breakpoint register 2 (PBR2) 32 W See Section

0x1B PC breakpoint register 3 (PBR3) 32 W See Section

The WCR register is described in Chapter 8, “Power Management.”

Each debug register is accessed as a 32-bit register; reserved fields are not used (don’t care).

Address

NOTE

Debug control registers can be written by the external development system or the CPU through the WDEBUG instruction. CSR is write-only from the programming model. It can be read or written through the BDM port using the

RDMREG

and

WDMREG

commands.

Table A-5. SCM Memory Map

Register

0xFC00_0000 Master Privilege Register (MPR)

0xFC00_0020 Peripheral Access Control Register A (PACRA)

0xFC00_0024 Peripheral Access Control Register B (PACRB)

0xFC00_0028 Peripheral Access Control Register C (PACRC)

0xFC00_002C Peripheral Access Control Register D (PACRD)

0xFC00_0040 Peripheral Access Control Register E (PACRE)

0xFC00_0044 Peripheral Access Control Register F (PACRF)

0xFC00_0054 Bus Monitor Timeout (BMT)

0xFC04_0013 Wakeup Control Register (WCR)

0xFC04_0016 Core Watchdog Control Register (CWCR)

0xFC04_001B Core Watchdog Service Register (CWSR)

0xFC04_001F SCM Interrupt Status Register (SCMISR)

0xFC04_0070 Core Fault Address Register (CFADR)

Width

(bits)

Access Reset Value Section/Page

R/W 0x7777_7777

R/W 0x5444_4444

R/W 0x4444_4444

R/W 0x4444_4444

R/W 0x4444_4444

R/W 0x4444_4444

R/W 0x4444_4444

R/W 0x0000_0008

R/W

0x00

0x0000

Undefined

0x00

0x0000_0000

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A-4 Freescale Semiconductor

Register Memory Map Quick Reference

Address

Table A-5. SCM Memory Map (continued)

Register

0xFC04_0075 Core Fault Interrupt Enable Register (CFIER)

0xFC04_0076 Core Fault Location Register (CFLOC)

0xFC04_0077 Core Fault Attributes Register (CFATR)

0xFC04_007C Core Fault Data Register (CFDTR)

Width

(bits)

Access Reset Value Section/Page

R/W

0x00

Undefined

Address

Table A-6. XBS Memory Map

Register

0xFC00_4100 Priority Register Slave 1 (XBS_PRS1)

0xFC00_4110 Control Register Slave 1 (XBS_CRS1)

0xFC00_4400 Priority Register Slave 4 (XBS_PRS4)

0xFC00_4410 Control Register Slave 4 (XBS_CRS4)

0xFC00_4700 Priority Register Slave 7 (XBS_PRS7)

0xFC00_4710 Control Register Slave 7 (XBS_CRS7)

Width

(bits)

Access Reset Value Section/Page

R/W

0x3000_0210

0x0000_0000

0x3000_0210

0x0000_0000

0x3000_0210

0x0000_0000

Address

Table A-7. FlexBus Chip Select Memory Map

Register

Width

(bits)

Access Reset Value

Section/

Page

R/W 0x0000_0000

17.3.1/17-4

0xFC00_8000

+ (n

0xC)

Chip-Select Address Register (CSARn)

n = 0 – 5

0xFC00_8004

+ (n

0xC)

Chip-Select Mask Register (CSMRn)

n = 0 – 5

0xFC00_8008

+ (n

0xC)

Chip-Select Control Register (CSCRn)

n = 0 – 5

R/W 0x0000_0000

17.3.2/17-5

R/W See Section

17.3.3/17-6

FlexCAN

0x000

0x004

Register

Table A-8. FlexCAN Memory Map

Width

(bits)

Affected by Hard

Reset

Affected by Soft

Reset

Access Reset Value Section/Page

FlexCAN Module Configuration

Supervisor-only Access Registers

32 Y Y

FlexCAN Control Register

(CANCTRL)

Supervisor/User Access Registers

32 Y N

R/W 0xD890_000F 23.3.1/23-6

R/W 0x0000_0000 23.3.2/23-8

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor A-5

Register Memory Map Quick Reference

FlexCAN

0x008

0x010

0x014

0x018

0x01C

0x020

0x028

0x030

0x080

Table A-8. FlexCAN Memory Map (continued)

Register

Free Running Timer (TIMER)

Rx Global Mask (RXGMASK)

Rx Buffer 14 Mask (RX14MASk)

Rx Buffer 15 Mask (RX15MASK)

Error Counter Register (ERRCNT)

Error and Status Register

(ERRSTAT)

Interrupt Mask Register (IMASK)

Interrupt Flag Register (IFLAG)

Message Buffers 0–15 (MB0–15)

Width

(bits)

Affected by Hard

Reset

Affected by Soft

Reset

Access Reset Value Section/Page

R/W

0x0000_0000

0x1FFF_FFFF

0x0000_0000

23.3.3/23-10

23.3.4/23-11

23.3.5/23-12

23.3.6/23-13

2048

R/W 0x0000_0000 23.3.7/23-15

R/W 0x0000_0000 23.3.8/23-16

R/W — 23.3.8/23-16

Table A-9. FEC Register Memory Map

Address Register

Width

(bits)

Access Reset Value

0xFC03_0004 Interrupt Event Register (EIR)

0xFC03_0008 Interrupt Mask Register (EIMR)

0xFC03_0010 Receive Descriptor Active Register (RDAR)

0xFC03_0014 Transmit Descriptor Active Register (TDAR)

0xFC03_0024 Ethernet Control Register (ECR)

0xFC03_0040 MII Management Frame Register (MMFR)

0xFC03_0044 MII Speed Control Register (MSCR)

0xFC03_0064 MIB Control/Status Register (MIBC)

0xFC03_0084 Receive Control Register (RCR)

0xFC03_00C4 Transmit Control Register (TCR)

0xFC03_00E4 Physical Address Low Register (PALR)

0xFC03_00E8 Physical Address High Register (PAUR)

0xFC03_00EC Opcode/Pause Duration (OPD) 32

0xFC03_0118 Descriptor Individual Upper Address Register (IAUR) 32

0xFC03_011C Descriptor Individual Lower Address Register (IALR) 32

0xFC03_0120 Descriptor Group Upper Address Register (GAUR) 32

0xFC03_0124 Descriptor Group Lower Address Register (GALR)

0xFC03_0144 Transmit FIFO Watermark (TFWR)

R/W

Section/Page

0x0000_0000

0xF000_0000

Undefined

0x0000_0000

0x05EE_0001

0x0000_0000

Undefined

See Section

19.4.12/19-18

19.4.13/19-19

See Section

Undefined

Undefined

0x0000_0000

MCF5208 Reference Manual, Rev 2

A-6 Freescale Semiconductor

Register Memory Map Quick Reference

Address

Table A-9. FEC Register Memory Map (continued)

Register

0xFC03_014C FIFO Receive Bound Register (FRBR)

0xFC03_0150 FIFO Receive FIFO Start Register (FRSR)

0xFC03_0180 Pointer to Receive Descriptor Ring (ERDSR)

0xFC03_0184 Pointer to Transmit Descriptor Ring (ETDSR)

0xFC03_0188 Maximum Receive Buffer Size (EMRBR)

Width

(bits)

Access Reset Value

R/W

0x0000_0600

0x0000_0500

Undefined

Section/Page

Address

Table A-10. eDMA Controller Memory Map

Register

0xFC04_4000 eDMA Control Register (EDMA_CR)

0xFC04_4004 eDMA Error Status Register (EDMA_ES)

0xFC04_400E eDMA Enable Request Register (EDMA_ERQ)

0xFC04_4016 eDMA Enable Error Interrupt Register (EDMA_EEI)

0xFC04_4018 eDMA Set Enable Request (EDMA_SERQ)

0xFC04_4019 eDMA Clear Enable Request (EDMA_CERQ)

0xFC04_401A eDMA Set Enable Error Interrupt Register (EDMA_SEEI)

0xFC04_401B eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)

0xFC04_401C eDMA Clear Interrupt Request Register (EDMA_CINT)

0xFC04_401D eDMA Clear Error Register (EDMA_CERR)

0xFC04_401E eDMA Set START Bit Register (EDMA_SSRT)

0xFC04_401F eDMA Clear DONE Status Bit Register (EDMA_CDNE)

0xFC04_4026 eDMA Interrupt Request Register (EDMA_INT)

0xFC04_402E eDMA Error Register (EDMA_ERR)

0xFC04_4100

+ hex(n) eDMA Channel n Priority Register (DCHPRIn) for n = 0 – 15

0xFC04_5000

+ hex(32

Transfer Control Descriptor (TCDn) for n = 0 – 15

Width

(bits)

Access Reset Value Section/Page

R/W 0x0000_0000

16.6.1/16-4

R 0x0000_0000

16.6.2/16-5

R/W

0x0000

16.6.3/16-8

16.6.4/16-9

R/W

0x00

0x0000

See Section

256 R/W See Section

Address

0xFC04_8000

0xFC04_8004

Table A-11. Interrupt Controller Memory Map

Register

Width

(bits)

Access Reset Value

Interrupt Controller 0

Interrupt Pending Register High (IPRH)

Interrupt Pending Register Low (IPRL)

Section/

Page

0x0000_0000

14.2.1/14-3

0x0000_0000

14.2.1/14-3

MCF5208 Reference Manual, Rev 2

Freescale Semiconductor A-7

Register Memory Map Quick Reference

Address

Table A-11. Interrupt Controller Memory Map (continued)

Register

0xFC04_8008 Interrupt Mask Register High (IMRH)

0xFC04_800C Interrupt Mask Register Low (IMRL)

0xFC04_8010

0xFC04_8014

Interrupt Force Register High (INTFRCH)

Interrupt Force Register Low (INTFRCL)

0xFC04_801A Interrupt Configuration Register (ICONFIG)

0xFC04_801C Set Interrupt Mask (SIMR)

0xFC04_801D Clear Interrupt Mask (CIMR)

0xFC04_801E Current Level Mask (CLMASK)

0xFC04_801F Saved Level Mask (SLMASK)

0xFC04_8040 + n

(n=0:63)

Interrupt Control Registers (ICRn)

0xFC04_80E0 Software Interrupt Acknowledge (SWIACK)

0xFC04_80E0 + 4n

(n=1:7)

Level n Interrupt Acknowledge Registers (LnIACK)

Width

(bits)

Access Reset Value

Section/

Page

R/W 0xFFFF_FFFF

14.2.2/14-4

R/W 0xFFFF_FFFF

14.2.2/14-4

R/W

0x0000_0000

0x0000

0x00

0x0F

0x00

0x00

0x18

14.2.10/14-12

Table A-12. I

C Module Memory Map

Address Register

0xFC05_8000 I

C Address Register (I2ADR)

0xFC05_8004 I

C Frequency Divider Register (I2FDR)

0xFC05_8008 I

C Control Register (I2CR)

0xFC05_800C I

C Status Register (I2SR)

0xFC05_8010 I

C Data I/O Register (I2DR)

Access Reset Value Section/Page

R/W

0x00

0x81

0x00

Table A-13. QSPI Memory Map

Address

Register

0xFC05_C000 QSPI Mode Register (QMR)

0xFC05_C004 QSPI Delay Register (QDLYR)

0xFC05_C008 QSPI Wrap Register (QWR)

0xFC05_C00C QSPI Interrupt Register (QIR)

Width

(bits)

Access Reset Value Section/Page

R/W

0xFC05_C010 QSPI Address Register (QAR) 16

0xFC05_C014 QSPI Data Register (QDR) 16 R/W

Addresses not assigned to a register and undefined register bits are reserved for expansion.

See the register description for special cases. Some bits may be read- or write-only.

0x0104

0x0404

0x0000

MCF5208 Reference Manual, Rev 2

A-8 Freescale Semiconductor

Register Memory Map Quick Reference

Table A-14. UART Module Memory Map

Address

UART0

UART1

UART2

Register

0xFC06_0000

0xFC06_4000

0xFC06_8000

UART Mode Registers

(UMR1n), (UMR2n)

0xFC06_000C

0xFC06_400C

0xFC06_800C

UART Receive Buffers (URBn)

UART Transmit Buffers (UTBn)

0xFC06_0010

0xFC06_4010

0xFC06_8010

UART Input Port Change Register (UIPCRn)

UART Auxiliary Control Register (UACRn)

Width

(bit)

0xFC06_0004

0xFC06_4004

0xFC06_8004

UART Status Register (USRn) 8

UART Clock Select Register

(UCSRn) 8

8 0xFC06_0008

0xFC06_4008

0xFC06_8008

UART Command Registers (UCRn)

Access Reset Value Section/Page

R/W

0x00

0xFF

0x00

See Section

0x00

0xFC06_0014

0xFC06_4014

0xFC06_8014

UART Interrupt Status Register (UISRn)

UART Interrupt Mask Register (UIMRn)

0xFC06_0018

0xFC06_4018

0xFC06_8018

UART Baud Rate Generator Register (UBG1n)

0xFC06_001C

0xFC06_401C

0xFC06_801C

UART Baud Rate Generator Register (UBG2n)

0x00

24.3.10/24-13

24.3.11/24-15

0xFC06_0034

0xFC06_4034

0xFC06_8034

UART Input Port Register (UIPn) 8 R 0xFF

24.3.12/24-15

0xFC06_0038

0xFC06_4038

0xFC06_8038

UART Output Port Bit Set Command Register (UOP1n) 8 W

0x00

0xFC06_003C

0xFC06_403C

0xFC06_803C

UART Output Port Bit Reset Command Register (UOP0n) 8 W

0x00