NXP MCF527X ColdFire® V2 Integrated Microprocessor Reference Manual

MCF5275 Reference Manual
Devices Supported:
MCF5274
MCF5274L
MCF5275
MCF5275L
Document Number: MCF5275RM
Rev. 2
07/2006
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MCF5275RM
Rev. 2
07/2006
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
General Purpose I/O Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Synchronous DRAM Controller
DMA Controller Module
Fast Ethernet Controller (FEC)
Universal Serial Bus Device (USB)
Watchdog Timer Module
PWM Module
Programmable Interrupt Timers (PITs)
DMA Timers
Queued Serial Peripheral Interface (QSPI)
UART Modules
I2C interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Debug Support
Register Memory Map Quick Reference
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
IND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
IND
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
General Purpose I/O Module
Interrupt Controller Modules
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Synchronous DRAM Controller
DMA Controller Module
Fast Ethernet Controller (FEC)
Universal Serial Bus Device (USB)
Watchdog Timer Module
PWM Module
Programmable Interrupt Timers (PITs)
DMA Timers
Queued Serial Peripheral Interface (QSPI)
UART Modules
I2C interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Debug Support
Register Memory Map Quick Reference
Index
Contents
Paragraph
Number
Title
Page
Number
Chapter 1
Overview
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.5.1
1.3.5.2
1.3.6
1.3.7
1.3.8
1.3.9
1.3.10
1.3.11
1.3.12
1.3.13
1.3.14
1.3.15
1.3.16
1.3.17
1.3.18
1.3.19
1.3.20
1.3.21
1.3.22
1.4
MCF5275 Family Configurations................................................................................... 1-1
Block Diagram ................................................................................................................ 1-2
Features ........................................................................................................................... 1-4
Feature Overview........................................................................................................ 1-4
V2 Core Overview ...................................................................................................... 1-8
Integrated Debug Module ........................................................................................... 1-8
JTAG........................................................................................................................... 1-9
On-chip Memories ...................................................................................................... 1-9
Cache ...................................................................................................................... 1-9
SRAM ................................................................................................................... 1-10
Fast Ethernet Controller (FEC)................................................................................. 1-10
Universal Serial Bus (USB)...................................................................................... 1-10
UARTs ...................................................................................................................... 1-10
I2C Bus...................................................................................................................... 1-10
QSPI.......................................................................................................................... 1-11
Cryptography ............................................................................................................ 1-11
DMA Timers (DTIM0-DTIM3) ............................................................................... 1-11
Pulse Width Modulation (PWM) Module ................................................................ 1-11
Periodic Interrupt Timers (PIT0-PIT3)..................................................................... 1-11
Software Watchdog Timer........................................................................................ 1-12
Clock Module and Phase Locked Loop (PLL) ......................................................... 1-12
Interrupt Controllers (INTC0, INTC1) ..................................................................... 1-12
DMA Controller........................................................................................................ 1-12
External Interface Module (EIM) ............................................................................. 1-12
Double Data Rate (DDR) Synchronous DRAM (SDRAM) Controller ................... 1-13
Reset.......................................................................................................................... 1-13
GPIO ......................................................................................................................... 1-13
Documentation.............................................................................................................. 1-14
Chapter 2
Signal Descriptions
2.1
2.1.1
2.2
Introduction..................................................................................................................... 2-1
Overview..................................................................................................................... 2-1
Signal Properties Summary ............................................................................................ 2-3
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Contents
Paragraph
Number
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
2.3.11
2.3.12
2.3.13
2.3.14
2.3.15
2.3.16
2.4
Title
Page
Number
External Signal Descriptions .......................................................................................... 2-8
Reset Signals............................................................................................................... 2-8
PLL and Clock Signals ............................................................................................... 2-9
Mode Selection ........................................................................................................... 2-9
External Memory Interface Signals ............................................................................ 2-9
DDR SDRAM Controller Signals............................................................................. 2-10
External Interrupt Signals ......................................................................................... 2-11
Fast Ethernet Controller Signals ............................................................................... 2-11
Queued Serial Peripheral Interface (QSPI)............................................................... 2-12
I2C I/O SIGNALS .................................................................................................... 2-13
UART Module Signals ............................................................................................. 2-13
USB Signals.............................................................................................................. 2-14
DMA Timer Signals.................................................................................................. 2-15
Pulse Width Modulator Signals ................................................................................ 2-15
Debug Support Signals ............................................................................................. 2-16
Test Signals............................................................................................................... 2-17
Power and Ground Pins ............................................................................................ 2-17
External Boot Mode...................................................................................................... 2-18
Chapter 3
ColdFire Core
3.1
3.2
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.1.4
3.2.1.5
3.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.3.3
3.2.3.4
3.2.3.5
3.2.3.6
3.3
3.4
3.5
Processor Pipelines .........................................................................................................
Processor Register Description .......................................................................................
User Programming Model ..........................................................................................
Data Registers (D0–D7) .........................................................................................
Address Registers (A0–A6)....................................................................................
Stack Pointer (A7) ..................................................................................................
Program Counter (PC) ............................................................................................
Condition Code Register (CCR).............................................................................
EMAC Register Description.......................................................................................
Supervisor Register Description .................................................................................
Status Register (SR)................................................................................................
Supervisor/User Stack Pointers (A7 and OTHER_A7)..........................................
Vector Base Register (VBR) ..................................................................................
Cache Control Register (CACR) ............................................................................
Access Control Registers (ACR0, ACR1)..............................................................
SRAM Base Address Register (RAMBAR)...........................................................
Memory Map/Register Definition ..................................................................................
Additions to the Instruction Set Architecture .................................................................
Exception Processing Overview .....................................................................................
3-1
3-2
3-2
3-2
3-3
3-3
3-3
3-4
3-4
3-5
3-6
3-7
3-7
3-7
3-8
3-8
3-8
3-9
3-9
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Contents
Paragraph
Number
3.6
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.7.9
3.7.10
3.7.11
3.7.12
3.7.13
3.7.14
3.8
3.8.1
3.8.2
3.9
3.10
3.11
3.12
3.13
3.14
Title
Page
Number
Exception Stack Frame Definition................................................................................
Processor Exceptions ....................................................................................................
Access Error Exception ............................................................................................
Address Error Exception...........................................................................................
Illegal Instruction Exception.....................................................................................
Divide-By-Zero.........................................................................................................
Privilege Violation....................................................................................................
Trace Exception ........................................................................................................
Unimplemented Line-A Opcode...............................................................................
Unimplemented Line-F Opcode ...............................................................................
Debug Interrupt.........................................................................................................
RTE and Format Error Exception.............................................................................
TRAP Instruction Exception.....................................................................................
Interrupt Exception ...................................................................................................
Fault-on-Fault Halt ...................................................................................................
Reset Exception ........................................................................................................
Instruction Execution Timing .......................................................................................
Timing Assumptions.................................................................................................
MOVE Instruction Execution Times ........................................................................
Standard One Operand Instruction Execution Times ...................................................
Standard Two Operand Instruction Execution Times...................................................
Miscellaneous Instruction Execution Times.................................................................
EMAC Instruction Execution Times ............................................................................
Branch Instruction Execution Times ............................................................................
ColdFire Instruction Set Architecture Enhancements ..................................................
3-11
3-13
3-13
3-13
3-13
3-14
3-14
3-14
3-15
3-15
3-15
3-15
3-15
3-15
3-16
3-16
3-19
3-19
3-20
3-21
3-22
3-24
3-25
3-26
3-26
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
4.1
4.2
4.3
4.4
4.4.1
4.4.1.1
4.4.2
4.5
4.5.1
4.5.2
4.5.3
Multiply-Accumulate Unit.............................................................................................. 4-1
Introduction to the MAC................................................................................................. 4-2
General Operation........................................................................................................... 4-3
Memory Map/Register Definition .................................................................................. 4-6
MAC Status Register (MACSR)................................................................................. 4-6
Fractional Operation Mode..................................................................................... 4-9
Mask Register (MASK) ............................................................................................ 4-11
EMAC Instruction Set Summary .................................................................................. 4-12
EMAC Instruction Execution Times ........................................................................ 4-13
Data Representation.................................................................................................. 4-14
MAC Opcodes .......................................................................................................... 4-14
MCF5275 Reference Manual, Rev. 1.1
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Contents
Paragraph
Number
Title
Page
Number
Chapter 5
Cache
5.1
5.1.1
5.1.2
5.1.3
5.1.3.1
5.1.3.2
5.1.3.3
5.1.3.4
5.1.3.5
5.2
5.2.1
5.2.1.1
5.2.1.2
Introduction..................................................................................................................... 5-1
Features....................................................................................................................... 5-1
Physical Organization ................................................................................................. 5-1
Operation .................................................................................................................... 5-3
Interaction with Other Modules.............................................................................. 5-3
Memory Reference Attributes ................................................................................ 5-4
Cache Coherency and Invalidation......................................................................... 5-4
Reset ....................................................................................................................... 5-5
Cache Miss Fetch Algorithm/Line Fills ................................................................. 5-5
Memory Map/Register Definition .................................................................................. 5-6
Registers Description.................................................................................................. 5-7
Cache Control Register (CACR) ............................................................................ 5-7
Access Control Registers (ACR0, ACR1)............................................................ 5-10
Chapter 6
Static RAM (SRAM)
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
6.2.3
6.2.4
Introduction.....................................................................................................................
Features.......................................................................................................................
Operation ....................................................................................................................
Register Description .......................................................................................................
SRAM Base Address Register (RAMBAR)...............................................................
SRAM Initialization....................................................................................................
SRAM Initialization Code ..........................................................................................
Power Management ....................................................................................................
6-1
6-1
6-1
6-1
6-2
6-4
6-4
6-5
Chapter 7
Clock Module
7.1
7.1.1
7.1.2
7.1.3
7.1.3.1
7.1.3.2
7.1.3.3
7.1.3.4
Introduction.....................................................................................................................
Block Diagram............................................................................................................
Features.......................................................................................................................
Modes of Operation ....................................................................................................
Normal PLL Mode with Crystal Reference............................................................
Normal PLL Mode with External Reference..........................................................
1:1 PLL Mode.........................................................................................................
External Clock Mode (Bypass Mode) ....................................................................
7-1
7-2
7-4
7-4
7-5
7-5
7-5
7-5
MCF5275 Reference Manual, Rev. 1.1
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Contents
Paragraph
Number
7.1.3.5
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.3.1.1
7.3.1.2
7.4
7.4.1
7.4.2
7.4.2.1
7.4.2.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.6.1
7.4.6.2
7.4.6.3
7.4.6.4
7.4.6.5
7.4.6.6
7.4.6.7
7.4.6.8
7.4.6.9
7.4.6.10
7.4.6.11
7.4.6.12
7.4.6.13
7.5
Title
Page
Number
Low-power Mode Operation .................................................................................. 7-6
External Signal Descriptions .......................................................................................... 7-6
EXTAL ....................................................................................................................... 7-7
XTAL.......................................................................................................................... 7-7
CLKOUT .................................................................................................................... 7-7
CLKMOD[1:0] ........................................................................................................... 7-7
RSTOUT..................................................................................................................... 7-7
Memory Map/Register Definition .................................................................................. 7-8
Register Descriptions.................................................................................................. 7-8
Synthesizer Control Register (SYNCR) ................................................................. 7-8
Synthesizer Status Register (SYNSR) .................................................................. 7-11
Functional Description.................................................................................................. 7-13
System Clock Modes ................................................................................................ 7-13
Clock Operation During Reset.................................................................................. 7-14
Power-On Reset (POR)......................................................................................... 7-14
External Reset....................................................................................................... 7-15
System Clock Generation ......................................................................................... 7-15
Programming the Frequency Modulation ................................................................. 7-16
Frequency Modulation Depth Calibration ................................................................ 7-18
PLL Operation .......................................................................................................... 7-21
Phase and Frequency Detector (PFD)................................................................... 7-22
Charge Pump/Loop Filter ..................................................................................... 7-23
Current Controlled Oscillator (ICO)..................................................................... 7-23
Multiplication Factor Divider (MFD)................................................................... 7-23
PLL Lock Detection ............................................................................................. 7-23
PLL Loss-of-Lock Conditions.............................................................................. 7-24
PLL Loss-of-Lock Reset....................................................................................... 7-25
PLL Loss-of-Lock Interrupt Request.................................................................... 7-25
Loss-of-Clock Detection....................................................................................... 7-25
Loss-of-Clock Reset ............................................................................................. 7-25
Loss-of-Clock Interrupt Request .......................................................................... 7-26
Alternate Clock Selection ..................................................................................... 7-26
Loss-of-Clock in Stop Mode ................................................................................ 7-26
Interrupts ....................................................................................................................... 7-30
Chapter 8
Power Management
8.1
8.1.1
8.2
Introduction..................................................................................................................... 8-1
Features....................................................................................................................... 8-1
Memory Map/Register Definition .................................................................................. 8-1
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Contents
Paragraph
Number
8.2.1
8.2.1.1
8.2.1.2
8.3
8.3.1
8.3.1.1
8.3.1.2
8.3.1.3
8.3.1.4
8.3.1.5
8.3.2
8.3.2.1
8.3.2.2
8.3.2.3
8.3.2.4
8.3.2.5
8.3.2.6
8.3.2.7
8.3.2.8
8.3.2.9
8.3.2.10
8.3.2.11
8.3.2.12
8.3.2.13
8.3.2.14
8.3.2.15
8.3.2.16
8.3.2.17
8.3.2.18
8.3.2.19
8.3.2.20
8.3.2.21
8.3.2.22
8.3.2.23
8.3.3
Title
Page
Number
Register Descriptions.................................................................................................. 8-1
Low-Power Interrupt Control Register (LPICR).................................................... 8-2
Low-Power Control Register (LPCR) .................................................................... 8-3
Functional Description.................................................................................................... 8-4
Low-Power Modes...................................................................................................... 8-4
Run Mode ............................................................................................................... 8-5
Wait Mode .............................................................................................................. 8-5
Doze Mode.............................................................................................................. 8-5
Stop Mode............................................................................................................... 8-5
Peripheral Shut Down............................................................................................. 8-6
Peripheral Behavior in Low-Power Modes ................................................................ 8-6
ColdFire Core ......................................................................................................... 8-6
Static Random-Access Memory (SRAM) .............................................................. 8-6
System Control Module (SCM).............................................................................. 8-6
DDR SDRAM Controller (SDRAMC)................................................................... 8-6
Chip Select Module ................................................................................................ 8-7
DMA Controller (DMA0–DMA3) ......................................................................... 8-7
UART Modules (UART0, UART1, and UART2) ................................................. 8-7
I2C Module............................................................................................................. 8-7
Queued Serial Peripheral Interface (QSPI)............................................................. 8-8
DMA Timers (DTIM0–DTIM3)............................................................................. 8-8
Interrupt Controllers (INTC0, INTC1) ................................................................... 8-8
Fast Ethernet Controller (FEC)............................................................................... 8-9
I/O Ports.................................................................................................................. 8-9
Reset Controller ...................................................................................................... 8-9
Chip Configuration Module.................................................................................... 8-9
Clock Module ....................................................................................................... 8-10
Edge Port .............................................................................................................. 8-10
Watchdog Timer ................................................................................................... 8-10
Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3) ............................ 8-10
USB Module ......................................................................................................... 8-10
PWM Module ....................................................................................................... 8-11
BDM ..................................................................................................................... 8-11
JTAG..................................................................................................................... 8-11
Summary of Peripheral State During Low-Power Modes ........................................ 8-11
Chapter 9
Chip Configuration Module (CCM)
9.1
9.1.1
Introduction..................................................................................................................... 9-1
Block Diagram............................................................................................................ 9-1
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Contents
Paragraph
Number
9.1.2
9.1.3
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.3.1
9.3.3.2
9.3.3.3
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.5
Title
Page
Number
Features....................................................................................................................... 9-1
Modes of Operation .................................................................................................... 9-2
External Signal Descriptions .......................................................................................... 9-2
RCON ......................................................................................................................... 9-2
CLKMOD[1:0] ........................................................................................................... 9-2
D[25:24, 21:19, 16] (Reset Configuration Override) ................................................. 9-2
Memory Map/Register Definition .................................................................................. 9-3
Programming Model ................................................................................................... 9-3
Memory Map .............................................................................................................. 9-3
Register Descriptions.................................................................................................. 9-4
Chip Configuration Register (CCR) ....................................................................... 9-4
Reset Configuration Register (RCON)................................................................... 9-5
Chip Identification Register (CIR) ......................................................................... 9-7
Functional Description.................................................................................................... 9-7
Reset Configuration .................................................................................................... 9-7
Chip Mode Selection .................................................................................................. 9-9
Boot Device Selection .............................................................................................. 9-10
Output Pad Strength Configuration .......................................................................... 9-10
Clock Mode Selection............................................................................................... 9-10
Chip Select Configuration ........................................................................................ 9-10
Reset.............................................................................................................................. 9-11
Chapter 10
Reset Controller Module
10.1
10.1.1
10.1.2
10.2
10.2.1
10.2.2
10.3
10.3.1
10.3.2
10.4
10.4.1
10.4.1.1
10.4.1.2
10.4.1.3
10.4.1.4
10.4.1.5
Introduction...................................................................................................................
Block Diagram..........................................................................................................
Features.....................................................................................................................
External Signal Description ..........................................................................................
RESET ......................................................................................................................
RSTOUT...................................................................................................................
Memory Map/Register Definition ................................................................................
Reset Control Register (RCR) ..................................................................................
Reset Status Register (RSR) .....................................................................................
Functional Description..................................................................................................
Reset Sources............................................................................................................
Power-On Reset ....................................................................................................
External Reset.......................................................................................................
Watchdog Timer Reset .........................................................................................
Loss-of-Clock Reset .............................................................................................
Loss-of-Lock Reset...............................................................................................
10-1
10-1
10-1
10-2
10-2
10-2
10-2
10-2
10-3
10-4
10-4
10-5
10-5
10-5
10-5
10-6
MCF5275 Reference Manual, Rev. 1.1
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Contents
Paragraph
Number
10.4.1.6
10.4.2
10.4.2.1
10.4.2.2
10.4.2.3
10.4.3
10.4.3.1
10.4.3.2
Title
Page
Number
Software Reset ......................................................................................................
Reset Control Flow ...................................................................................................
Synchronous Reset Requests ................................................................................
Internal Reset Request ..........................................................................................
Power-On Reset ....................................................................................................
Concurrent Resets .....................................................................................................
Reset Flow ............................................................................................................
Reset Status Flags .................................................................................................
10-6
10-6
10-8
10-8
10-8
10-8
10-8
10-9
Chapter 11
System Control Module (SCM)
11.1
11.1.1
11.1.2
11.2
11.2.1
11.2.1.1
11.2.1.2
11.2.1.3
11.2.1.4
11.2.1.5
11.3
11.3.1
11.3.2
11.3.2.1
11.3.2.2
11.3.3
11.4
11.4.1
11.4.2
11.4.3
11.4.3.1
11.4.3.2
11.4.3.3
Introduction................................................................................................................... 11-1
Overview................................................................................................................... 11-1
Features..................................................................................................................... 11-1
Memory Map/Register Definition ................................................................................ 11-2
Register Descriptions................................................................................................ 11-3
Internal Peripheral System Base Address Register (IPSBAR)............................. 11-3
Memory Base Address Register (RAMBAR) ...................................................... 11-4
Core Reset Status Register (CRSR)...................................................................... 11-6
Core Watchdog Control Register (CWCR) .......................................................... 11-7
Core Watchdog Service Register (CWSR)........................................................... 11-8
Internal Bus Arbitration ................................................................................................ 11-9
Overview................................................................................................................. 11-10
Arbitration Algorithms ........................................................................................... 11-10
Round-Robin Mode ............................................................................................ 11-10
Fixed Mode......................................................................................................... 11-11
Bus Master Park Register (MPARK)...................................................................... 11-11
System Access Control Unit (SACU)......................................................................... 11-13
Overview................................................................................................................. 11-13
Features................................................................................................................... 11-13
Memory Map/Register Definition .......................................................................... 11-14
Master Privilege Register (MPR) ....................................................................... 11-15
Peripheral Access Control Registers (PACR0–PACR8).................................... 11-15
Grouped Peripheral Access Control Register (GPACR) .................................... 11-17
Chapter 12
General Purpose I/O Module
12.1
Introduction................................................................................................................... 12-1
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Contents
Paragraph
Number
12.1.1
12.1.2
12.2
12.3
12.3.1
12.3.1.1
12.3.1.2
12.3.1.3
12.3.1.4
12.3.1.5
12.3.1.6
12.3.1.7
12.3.1.8
12.4
12.4.1
12.4.2
12.5
Title
Page
Number
Overview................................................................................................................... 12-3
Features..................................................................................................................... 12-3
External Signal Description .......................................................................................... 12-3
Memory Map/Register Definition .............................................................................. 12-10
Register Descriptions.............................................................................................. 12-11
Port Output Data Registers (PODR_x)............................................................... 12-11
Port Data Direction Registers (PDDR_x)........................................................... 12-14
Port Pin Data/Set Data Registers (PPDSDR_x) ................................................. 12-16
Port Clear Output Data Registers (PCLRR_x) ................................................... 12-19
Pin Assignment Registers (PAR_x).................................................................... 12-21
Timer Pin Assignment Registers (PAR_TIMERH & PAR_TIMERL).............. 12-30
USB Pin Assignment Register (PAR_USB)....................................................... 12-32
FEC0 & FEC1 Pin Assignment Registers (PAR_FEC0 & PAR_FEC1) ........... 12-33
Functional Description................................................................................................ 12-34
Overview................................................................................................................. 12-34
Port Digital I/O Timing........................................................................................... 12-35
Initialization/Application Information ........................................................................ 12-35
Chapter 13
Interrupt Controller Modules
13.1
13.1.1
13.1.2
13.1.2.1
13.1.2.2
13.1.2.3
13.2
13.2.1
13.2.1.1
13.2.1.2
13.2.1.3
13.2.1.4
13.2.1.5
13.2.1.6
13.2.1.7
13.3
13.4
Introduction................................................................................................................... 13-1
68K/ColdFire Interrupt Architecture Overview ....................................................... 13-1
Interrupt Controller Theory of Operation ................................................................. 13-2
Interrupt Recognition............................................................................................ 13-3
Interrupt Prioritization .......................................................................................... 13-3
Interrupt Vector Determination ............................................................................ 13-4
Memory Map/Register Definition ................................................................................ 13-4
Register Descriptions................................................................................................ 13-6
Interrupt Pending Registers (IPRHn, IPRLn)....................................................... 13-6
Interrupt Mask Register (IMRHn, IMRLn).......................................................... 13-7
Interrupt Force Registers (INTFRCHn, INTFRCLn)........................................... 13-9
Interrupt Request Level Register (IRLRn) ......................................................... 13-11
Interrupt Acknowledge Level and Priority Register (IACKLPRn).................... 13-11
Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)) ......................................... 13-12
Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)......... 13-15
Prioritization Between Interrupt Controllers .............................................................. 13-16
Low-Power Wakeup Operation .................................................................................. 13-16
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Contents
Paragraph
Number
Title
Page
Number
Chapter 14
Edge Port Module (EPORT)
14.1
14.2
14.3
14.4
14.4.1
14.4.1.1
14.4.1.2
14.4.1.3
14.4.1.4
14.4.1.5
14.4.1.6
Introduction...................................................................................................................
Low-Power Mode Operation ........................................................................................
Interrupt/General-Purpose I/O Pin Descriptions...........................................................
Memory Map/Register Definition ................................................................................
Register Description .................................................................................................
EPORT Pin Assignment Register (EPPAR).........................................................
EPORT Data Direction Register (EPDDR)..........................................................
Edge Port Interrupt Enable Register (EPIER) ......................................................
Edge Port Data Register (EPDR)..........................................................................
Edge Port Pin Data Register (EPPDR) .................................................................
Edge Port Flag Register (EPFR)...........................................................................
14-1
14-1
14-2
14-2
14-3
14-3
14-4
14-5
14-5
14-6
14-6
Chapter 15
Chip Select Module
15.1
15.1.1
15.2
15.2.1
15.2.2
15.2.3
15.3
15.3.1
15.3.1.1
15.3.2
15.3.2.1
15.4
15.4.1
15.4.1.1
15.4.1.2
15.4.1.3
15.5
Introduction................................................................................................................... 15-1
Overview................................................................................................................... 15-1
External Signal Description .......................................................................................... 15-1
Chip Selects (CS[7:0]) .............................................................................................. 15-1
Output Enable (OE) .................................................................................................. 15-1
Byte Strobes (BS[3:2]).............................................................................................. 15-2
Chip Select Operation ................................................................................................... 15-3
General Chip Select Operation ................................................................................. 15-3
8- and 16-Bit Port Sizing ...................................................................................... 15-4
Enhanced Wait State Operation................................................................................ 15-4
External Boot Chip Select Operation ................................................................... 15-5
Memory Map/Register Definition ................................................................................ 15-6
Chip Select Module Registers................................................................................... 15-7
Chip Select Address Registers (CSAR0–CSAR7) ............................................... 15-7
Chip Select Mask Registers (CSMR0–CSMR7) .................................................. 15-8
Chip Select Control Registers (CSCR0–CSCR7)................................................. 15-9
Code Example............................................................................................................. 15-11
Chapter 16
External Interface Module (EIM)
16.1
Introduction................................................................................................................... 16-1
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Contents
Paragraph
Number
16.1.1
16.2
16.3
16.4
16.5
16.5.1
16.5.2
16.5.3
16.5.4
16.5.5
16.5.6
16.5.7
16.5.7.1
16.5.7.2
16.5.7.3
16.6
16.7
Title
Page
Number
Features..................................................................................................................... 16-1
Bus and Control Signals ............................................................................................... 16-1
Bus Characteristics ....................................................................................................... 16-2
Bus Errors ..................................................................................................................... 16-3
Data Transfer Operation ............................................................................................... 16-3
Bus Cycle Execution................................................................................................. 16-4
Data Transfer Cycle States ....................................................................................... 16-5
Read Cycle................................................................................................................ 16-7
Write Cycle ............................................................................................................... 16-8
Fast Termination Cycles ........................................................................................... 16-9
Back-to-Back Bus Cycles ....................................................................................... 16-10
Burst Cycles............................................................................................................ 16-11
Line Transfers..................................................................................................... 16-12
Line Read Bus Cycles......................................................................................... 16-12
Line Write Bus Cycles........................................................................................ 16-14
Secondary Wait State Operation................................................................................. 16-17
Misaligned Operands .................................................................................................. 16-17
Chapter 17
SDRAM Controller (SDRAMC)
17.1
17.1.1
17.1.2
17.1.3
17.2
17.3
17.3.1
17.3.2
17.3.3
17.3.3.1
17.4
17.4.1
17.4.1.1
17.4.1.2
17.4.1.3
17.4.1.4
17.4.1.5
17.4.1.6
17.4.1.7
17.4.2
Introduction................................................................................................................... 17-1
Features..................................................................................................................... 17-1
Terminology.............................................................................................................. 17-1
Block Diagram.......................................................................................................... 17-2
External Signal Description .......................................................................................... 17-4
Interface Recommendations ......................................................................................... 17-4
Supported Memory Configurations .......................................................................... 17-4
SDRAM Connection Block Diagram ....................................................................... 17-7
DDR SDRAM Layout Considerations ..................................................................... 17-7
Termination Example ........................................................................................... 17-8
SDRAM Overview ....................................................................................................... 17-8
SDRAM Commands ................................................................................................. 17-8
Activate Command (ACTV)................................................................................. 17-9
Read Command (READ)...................................................................................... 17-9
Write Command (WRITE) ................................................................................. 17-10
Precharge All Banks Command (PALL)............................................................ 17-10
Load Mode/Extended Mode Register Command (LMR, LEMR)...................... 17-10
Auto Refresh Command (REF) .......................................................................... 17-12
Self Refresh (SREF) and Power Down (PDWN) Commands............................ 17-12
Power-Up Initialization........................................................................................... 17-13
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Paragraph
Number
17.5
17.5.1
17.5.2
17.5.3
17.5.4
17.5.5
17.5.6
17.6
17.6.1
17.6.2
17.7
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
17.7.7
17.8
17.8.1
17.8.2
17.8.3
Title
Page
Number
Memory Map/Register Definition ..............................................................................
SDRAM Mode/Extended Mode Register (SDMR) ................................................
SDRAM Control Register (SDCR).........................................................................
SDRAM Configuration Register 1 (SDCFG1).......................................................
SDRAM Configuration Register 2 (SDCFG2).......................................................
SDRAM Base Address Registers (SDBAR0 & SDBAR1) ....................................
SDRAM Address Mask Registers (SDMR0 & SDMR1).......................................
Functional Overview...................................................................................................
Page Management...................................................................................................
Transfer Size ...........................................................................................................
DDR SDRAM Example..............................................................................................
SDRAM Chip Select Settings.................................................................................
SDRAM Configuration 1 Register Settings............................................................
SDRAM Configuration 2 Register Settings............................................................
SDRAM Control Register Settings and PALL command ......................................
Set the Extended Mode Register.............................................................................
Set the Mode Register and Reset DLL ...................................................................
Issue a PALL command..........................................................................................
Perform Two Refresh Cycles......................................................................................
Clear the Reset DLL Bit in the Mode Register.......................................................
Enable Automatic Refresh and Lock Mode Register .............................................
Initialization Code...................................................................................................
17-14
17-14
17-15
17-17
17-19
17-20
17-20
17-21
17-21
17-22
17-23
17-24
17-25
17-26
17-27
17-28
17-29
17-29
17-30
17-32
17-32
17-33
Chapter 18
DMA Controller Module
18.1
18.1.1
18.1.2
18.2
18.3
18.3.1
18.3.2
18.3.3
18.3.4
18.3.4.1
18.3.5
18.4
18.4.1
18.4.2
18.4.3
Introduction................................................................................................................... 18-1
Overview................................................................................................................... 18-1
Features..................................................................................................................... 18-3
DMA Transfer Overview.............................................................................................. 18-4
Memory Map/Register Definition ................................................................................ 18-5
DMA Request Control (DMAREQC) ...................................................................... 18-6
Source Address Registers (SAR0–SAR3) ................................................................ 18-7
Destination Address Registers (DAR0–DAR3) ....................................................... 18-8
Byte Count Registers (BCR0–BCR3) and DMA Status Registers (DSR0–DSR3) . 18-8
DMA Status Registers (DSR0–DSR3) ................................................................. 18-9
DMA Control Registers (DCR0–DCR3)................................................................ 18-10
Functional Description................................................................................................ 18-13
Transfer Requests (Cycle-Steal and Continuous Modes) ....................................... 18-14
Dual-Address Data Transfer Mode......................................................................... 18-14
Channel Initialization and Startup .......................................................................... 18-15
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Contents
Paragraph
Number
18.4.3.1
18.4.3.2
18.4.4
18.4.4.1
18.4.4.2
18.4.4.3
18.4.5
Title
Page
Number
Channel Prioritization.........................................................................................
Programming the DMA Controller Module .......................................................
Data Transfer ..........................................................................................................
External Request and Acknowledge Operation..................................................
Auto-Alignment..................................................................................................
Bandwidth Control..............................................................................................
Termination.............................................................................................................
18-15
18-15
18-16
18-16
18-19
18-20
18-20
Chapter 19
Fast Ethernet Controllers (FEC0 & FEC1)
19.1
19.1.1
19.1.2
19.1.3
19.1.4
19.1.4.1
19.1.5
19.1.5.1
19.1.5.2
19.1.6
19.1.7
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.2.4.1
19.2.4.2
19.2.4.3
19.2.4.4
19.2.4.5
19.2.4.6
19.2.4.7
19.2.4.8
19.2.4.9
19.2.4.10
19.2.4.11
19.2.4.12
19.2.4.13
19.2.4.14
Introduction................................................................................................................... 19-1
Overview................................................................................................................... 19-1
Block Diagram.......................................................................................................... 19-1
Features..................................................................................................................... 19-3
Modes of Operation .................................................................................................. 19-4
Full and Half Duplex Operation ........................................................................... 19-4
Interface Options....................................................................................................... 19-4
10 Mbps and 100 Mbps MII Interface.................................................................. 19-4
10 Mpbs 7-Wire Interface Operation.................................................................... 19-5
Address Recognition Options ................................................................................... 19-5
Internal Loopback ..................................................................................................... 19-5
Memory Map/Register Definition ................................................................................ 19-5
High-Level Module Memory Map ........................................................................... 19-5
Register Memory Map .............................................................................................. 19-6
MIB Block Counters Memory Map.......................................................................... 19-7
Register Description ................................................................................................. 19-9
Ethernet Interrupt Event Register (EIR) ............................................................... 19-9
Interrupt Mask Registers (EIMR0 & EIMR1).................................................... 19-10
Receive Descriptor Active Registers (RDAR0 & RDAR1) ............................... 19-11
Transmit Descriptor Active Registers (TDAR0 & TDAR1).............................. 19-12
Ethernet Control Registers (ECR0 & ECR1) ..................................................... 19-13
MII Management Frame Registers (MMFR0 & MMFR1) ................................ 19-14
MII Speed Control Registers (MSCR0 & MSCR1) ........................................... 19-16
MIB Control Registers (MIBC0 & MIBC1) ...................................................... 19-17
Receive Control Registers (RCR0 & RCR1)...................................................... 19-18
Transmit Control Registers (TCR0 & TCR1) ................................................... 19-19
Physical Address Low Registers (PALR0 & PALR1) ...................................... 19-20
Physical Address High Registers (PAUR0 & PAUR1)..................................... 19-21
Opcode/Pause Duration Registers (OPD0 & OPD1)......................................... 19-21
Descriptor Individual Upper Address Registers (IAUR0 & IAUR1)............... 19-22
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Paragraph
Number
19.2.4.15
19.2.4.16
19.2.4.17
19.2.4.18
19.2.4.19
19.2.4.20
19.2.4.21
19.2.4.22
19.2.4.23
19.2.5
19.2.5.1
19.2.5.2
19.2.5.3
19.3
19.3.1
19.3.1.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
19.3.9
19.3.10
19.3.11
19.3.12
19.3.13
19.3.14
19.3.14.1
19.3.14.2
Title
Page
Number
Descriptor Individual Lower Address Registers (IALR0 & IALR1) ................
Descriptor Group Upper Address Registers (GAUR0 & GAUR1)...................
Descriptor Group Lower Address Registers (GALR0 & GALR1) ..................
FIFO Transmit FIFO Watermark Registers (TFWR0 & TFWR1)....................
FIFO Receive Bound Registers (FRBR0 & FRBR1) ........................................
FIFO Receive Start Registers (FRSR0 & FRSR1) ............................................
Receive Descriptor Ring Start Registers (ERDSR0 & ERDSR1).....................
Transmit Buffer Descriptor Ring Start Registers (ETSDR0 & ETSDR1) .......
Receive Buffer Size Registers (EMRBR0 & EMRBR1) ..................................
Buffer Descriptors...................................................................................................
Driver/DMA Operation with Buffer Descriptors ...............................................
Ethernet Receive Buffer Descriptors (RxBD0 & RxBD1).................................
Ethernet Transmit Buffer Descriptors (TxBD0 & TxBD1)................................
Functional Description................................................................................................
Initialization Sequence............................................................................................
Hardware Controlled Initialization .....................................................................
User Initialization (Prior to Setting ECRn[ETHER_EN])......................................
Microcontroller Initialization..................................................................................
User Initialization (After Asserting ECRn[ETHER_EN]) .....................................
Network Interface Options......................................................................................
FEC Frame Transmission .......................................................................................
FEC Frame Reception.............................................................................................
Ethernet Address Recognition ................................................................................
Hash Algorithm.......................................................................................................
Full Duplex Flow Control......................................................................................
Inter-Packet Gap (IPG) Time.................................................................................
Collision Handling.................................................................................................
Internal and External Loopback.............................................................................
Ethernet Error-Handling Procedure .......................................................................
Transmission Errors...........................................................................................
Reception Errors ................................................................................................
19-23
19-23
19-24
19-25
19-25
19-26
19-27
19-27
19-28
19-29
19-29
19-31
19-33
19-35
19-35
19-35
19-36
19-36
19-37
19-37
19-38
19-39
19-40
19-43
19-46
19-47
19-47
19-47
19-48
19-48
19-49
Chapter 20
Universal Serial Bus
20.1
20.1.1
20.1.2
20.1.3
20.1.4
20.2
Introduction...................................................................................................................
Block Diagram..........................................................................................................
Overview...................................................................................................................
Features.....................................................................................................................
Modes of Operation ..................................................................................................
External Signal Description ..........................................................................................
20-1
20-1
20-1
20-2
20-2
20-3
MCF5275 Reference Manual, Rev. 1.1
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Contents
Paragraph
Number
20.2.1
20.2.2
20.2.3
20.2.4
20.2.5
20.2.6
20.2.7
20.3
20.3.1
20.3.1.1
20.3.1.2
20.3.1.3
20.3.1.4
20.3.1.5
20.3.1.6
20.3.1.7
20.3.1.8
20.3.1.9
20.3.1.10
20.3.1.11
20.3.1.12
20.3.1.13
20.3.1.14
20.3.1.15
20.3.1.16
20.3.1.17
20.3.1.18
20.3.1.19
20.3.1.20
20.4
20.4.1
20.4.1.1
20.4.1.2
20.5
20.5.1
20.5.2
20.5.2.1
20.5.2.2
20.6
20.6.1
20.6.2
Title
Page
Number
USB Clock (USB_CLK)........................................................................................... 20-3
USB Speed (USB_SPEED) ...................................................................................... 20-3
USB Negative/Positive Receive Signal Inputs (USB_RN & USB_RP) .................. 20-4
USB Receive Data (USB_RXD) .............................................................................. 20-4
USB Suspended (USB_SUSP) ................................................................................. 20-4
USB Negative/Positive Transmit Signal Output (USB_TN & USB_TP) ................ 20-4
USB Transmit Enable (USB_TXEN) ....................................................................... 20-4
Memory Map/Register Definition ................................................................................ 20-4
Register Descriptions................................................................................................ 20-5
USB Frame Number and Match Register (USB_FRAME).................................. 20-6
USB Specification/Release Number Register (USB_SPEC) ............................... 20-6
USB Status Register (USB_SR) ........................................................................... 20-7
USB Control Register (USB_CR) ........................................................................ 20-7
USB Descriptor RAM Address Register (USB_DAR) ........................................ 20-9
USB Descriptor RAM/Endpoint Buffer Data Register (USB_DDR)................. 20-10
USB Interrupt Status Register (USB_ISR)......................................................... 20-10
USB Interrupt Mask Register (USB_IMR) ........................................................ 20-12
USB FIFO Memory Control Register (USB_MCR) .......................................... 20-13
Endpoint n Status/Control Register (USB_EPnSR).......................................... 20-13
Endpoint n Interrupt Status Register (USB_EPnISR) ........................................ 20-15
Endpoint n Interrupt Mask Register (USB_EPnIMR) ....................................... 20-17
Endpoint n FIFO Data Register (USB_EPnFDR).............................................. 20-17
Endpoint n FIFO Status Register (USB_EPnFSR) ............................................ 20-18
Endpoint n FIFO Control Register (USB_EPnFCR) ......................................... 20-19
Endpoint n Last Read Frame Pointer (USB_EPnLRFP).................................... 20-21
Endpoint n Last Write Frame Pointer (USB_EPnLWFP).................................. 20-21
Endpoint n FIFO Alarm Register (USB_EPnFAR) ........................................... 20-22
Endpoint n FIFO Read Pointer (USB_EPnFRP)................................................ 20-23
Endpoint n FIFO Write Pointer (USB_EPnFWP).............................................. 20-24
Functional Description................................................................................................ 20-25
USB Components ................................................................................................... 20-25
Descriptor RAM ................................................................................................. 20-25
FIFO Controller .................................................................................................. 20-25
Reset Strategy ............................................................................................................. 20-25
Description of Reset Operation............................................................................... 20-26
Hard Reset............................................................................................................... 20-26
USB Device Reset ............................................................................................. 20-26
USB Bus Reset ................................................................................................. 20-26
Interrupts ..................................................................................................................... 20-27
Description of Interrupt Operation ......................................................................... 20-27
Detailed Interrupt Descriptions............................................................................... 20-27
MCF5275 Reference Manual, Rev. 1.1
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Paragraph
Number
20.6.2.1
20.6.2.2
20.6.2.3
20.7
20.7.1
20.7.1.1
20.7.1.2
20.7.1.3
20.7.1.4
20.7.1.5
20.7.1.6
20.7.1.7
20.7.2
20.7.2.1
20.7.2.2
20.7.2.3
20.7.2.4
20.7.3
20.7.3.1
20.7.3.2
20.7.3.3
20.7.3.4
20.7.3.5
20.7.3.6
Title
Page
Number
USB Global Interrupt..........................................................................................
Endpoint Interrupts .............................................................................................
Interrupts, Missed Interrupts, and the USB Device............................................
Software Interface.......................................................................................................
Device Initialization................................................................................................
Configuration Download ....................................................................................
USB Endpoint to FIFO Mapping........................................................................
USB Descriptor Download .................................................................................
USB Interrupt Register .......................................................................................
Endpoint Registers..............................................................................................
FIFO Sizes .........................................................................................................
Enable the Device ...............................................................................................
Exception Handling ................................................................................................
Unable to Complete Device Request..................................................................
Aborted Device Request .....................................................................................
Unable to Fill or Empty FIFO Due to Temporary Problem ...............................
Catastrophic Error...............................................................................................
Data Transfer Operations........................................................................................
USB Packets .......................................................................................................
USB Transfers ....................................................................................................
Control Transfers ................................................................................................
Bulk Traffic ........................................................................................................
Interrupt Traffic ..................................................................................................
Isochronous Operations ......................................................................................
20-27
20-29
20-30
20-31
20-31
20-32
20-34
20-35
20-36
20-36
20-36
20-36
20-37
20-37
20-37
20-37
20-38
20-38
20-38
20-39
20-40
20-41
20-42
20-42
Chapter 21
Watchdog Timer Module
21.1
21.1.1
21.1.2
21.2
21.2.1
21.2.1.1
21.2.1.2
21.2.1.3
21.2.1.4
Introduction...................................................................................................................
Low-Power Mode Operation ....................................................................................
Block Diagram..........................................................................................................
Memory Map/Register Definition ................................................................................
Register Description .................................................................................................
Watchdog Control Register (WCR)......................................................................
Watchdog Modulus Register (WMR)...................................................................
Watchdog Count Register (WCNTR)...................................................................
Watchdog Service Register (WSR) ......................................................................
21-1
21-1
21-2
21-2
21-2
21-3
21-4
21-4
21-4
MCF5275 Reference Manual, Rev. 1.1
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Paragraph
Number
Title
Page
Number
Chapter 22
Pulse Width Modulation (PWM) Module
22.1
22.1.1
22.2
22.2.1
22.2.2
22.2.3
22.2.4
22.2.5
22.2.6
22.2.7
22.2.8
22.2.9
22.2.10
22.2.11
22.3
22.3.1
22.3.1.1
22.3.1.2
22.3.1.3
22.3.2
22.3.2.1
22.3.2.2
22.3.2.3
22.3.2.4
22.3.2.5
22.3.2.6
22.3.2.7
22.3.2.8
Introduction................................................................................................................... 22-1
Overview................................................................................................................... 22-1
Memory Map/Register Definition ................................................................................ 22-2
PWM Enable Register (PWME)............................................................................... 22-2
PWM Polarity Register (PWMPOL) ........................................................................ 22-3
PWM Clock Select Register (PWMCLK) ................................................................ 22-4
PWM Prescale Clock Select Register (PWMPRCLK)............................................. 22-4
PWM Center Align Enable Register (PWMCAE) ................................................... 22-5
PWM Control Register (PWMCTL)......................................................................... 22-6
PWM Scale A Register (PWMSCLA)...................................................................... 22-7
PWM Scale B Register (PWMSCLB) ...................................................................... 22-7
PWM Channel Counter Registers (PWMCNTn)...................................................... 22-8
PWM Channel Period Registers (PWMPERn)......................................................... 22-9
PWM Channel Duty Registers (PWMDTYn) ........................................................ 22-10
Functional Description................................................................................................ 22-10
PWM Clock Select.................................................................................................. 22-10
Prescaled Clock (A or B)................................................................................... 22-11
Scaled Clock (SA or SB) .................................................................................... 22-11
Clock Select ........................................................................................................ 22-12
PWM Channel Timers ............................................................................................ 22-12
PWM Enable....................................................................................................... 22-13
PWM Polarity ..................................................................................................... 22-13
PWM Period and Duty........................................................................................ 22-13
PWM Timer Counters......................................................................................... 22-14
Left Aligned Outputs .......................................................................................... 22-15
Center Aligned Outputs ...................................................................................... 22-16
PWM 16-Bit Functions....................................................................................... 22-18
PWM Boundary Cases........................................................................................ 22-19
Chapter 23
Programmable Interrupt Timer Modules (PIT0–PIT3)
23.1
23.1.1
23.1.2
23.1.3
23.2
23.2.1
Introduction...................................................................................................................
Overview...................................................................................................................
Block Diagram..........................................................................................................
Low-Power Mode Operation ....................................................................................
Memory Map/Register Definition ................................................................................
Register Description .................................................................................................
23-1
23-1
23-1
23-2
23-2
23-3
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Paragraph
Number
23.2.1.1
23.2.1.2
23.2.1.3
23.3
23.3.1
23.3.2
23.3.3
23.3.4
Page
Number
Title
PIT Control and Status Register (PCSRn)............................................................
PIT Modulus Register (PMRn) ............................................................................
PIT Count Register (PCNTRn) ............................................................................
Functional Description..................................................................................................
Set-and-Forget Timer Operation...............................................................................
Free-Running Timer Operation ................................................................................
Timeout Specifications .............................................................................................
Interrupt Operation ...................................................................................................
23-3
23-5
23-5
23-6
23-6
23-6
23-7
23-7
Chapter 24
Queued Serial Peripheral Interface (QSPI) Module
24.1
24.1.1
24.1.2
24.1.3
24.1.3.1
24.1.4
24.2
24.2.1
24.2.1.1
24.2.1.2
24.2.1.3
24.2.2
24.2.3
24.2.4
24.2.5
24.3
24.3.1
24.3.2
24.3.3
24.3.4
24.3.5
24.3.6
24.3.7
24.3.8
Introduction................................................................................................................... 24-1
Overview................................................................................................................... 24-1
Features..................................................................................................................... 24-1
Module Description .................................................................................................. 24-1
Interface and Signals............................................................................................. 24-2
Internal Bus Interface................................................................................................ 24-3
Operation ...................................................................................................................... 24-3
QSPI RAM................................................................................................................ 24-4
Receive RAM ....................................................................................................... 24-5
Transmit RAM...................................................................................................... 24-5
Command RAM.................................................................................................... 24-6
Baud Rate Selection.................................................................................................. 24-6
Transfer Delays......................................................................................................... 24-7
Transfer Length......................................................................................................... 24-8
Data Transfer ............................................................................................................ 24-8
Memory Map/Register Definition ................................................................................ 24-9
QSPI Mode Register (QMR) .................................................................................... 24-9
QSPI Delay Register (QDLYR) ............................................................................. 24-11
QSPI Wrap Register (QWR)................................................................................... 24-12
QSPI Interrupt Register (QIR)................................................................................ 24-12
QSPI Address Register (QAR) ............................................................................... 24-14
QSPI Data Register (QDR)..................................................................................... 24-14
Command RAM Registers (QCR0–QCR15).......................................................... 24-14
Programming Example ........................................................................................... 24-16
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Title
Page
Number
Chapter 25
DMA Timers (DTIM0–DTIM3)
25.1
25.1.1
25.1.2
25.2
25.2.1
25.2.2
25.2.3
25.2.4
25.2.5
25.2.6
25.2.7
25.2.8
25.2.9
25.2.10
25.2.11
25.3
25.3.1
25.3.2
Introduction................................................................................................................... 25-1
Overview................................................................................................................... 25-1
Features..................................................................................................................... 25-2
Memory Map/Register Definition ................................................................................ 25-2
Prescaler.................................................................................................................... 25-2
Capture Mode ........................................................................................................... 25-3
Reference Compare................................................................................................... 25-3
Output Mode ............................................................................................................. 25-3
Memory Map ............................................................................................................ 25-3
DMA Timer Mode Registers (DTMRn)................................................................... 25-4
DMA Timer Extended Mode Registers (DTXMRn)................................................ 25-5
DMA Timer Event Registers (DTERn).................................................................... 25-6
DMA Timer Reference Registers (DTRRn)............................................................. 25-7
DMA Timer Capture Registers (DTCRn) ............................................................... 25-8
DMA Timer Counters (DTCNn) ............................................................................. 25-8
Using the DMA Timer Modules ................................................................................... 25-9
Code Example......................................................................................................... 25-10
Calculating Time-Out Values ................................................................................. 25-11
Chapter 26
I C Interface
2
26.1
26.2
26.3
26.4
26.4.1
26.4.2
26.4.3
26.4.4
26.4.5
26.4.6
26.4.7
26.4.8
26.5
26.5.1
26.5.2
26.5.3
Introduction................................................................................................................... 26-1
Overview....................................................................................................................... 26-1
Features ......................................................................................................................... 26-1
I2C System Configuration............................................................................................. 26-3
START Signal........................................................................................................... 26-3
Slave Address Transmission..................................................................................... 26-4
Data Transfer ............................................................................................................ 26-4
Acknowlege .............................................................................................................. 26-4
STOP Signal ............................................................................................................. 26-5
Repeated START...................................................................................................... 26-5
Clock Synchronization and Arbitration .................................................................... 26-6
Handshaking and Clock Stretching........................................................................... 26-8
Memory Map/Register Definition ................................................................................ 26-8
I2C Address Register (I2ADR) ................................................................................. 26-8
I2C Frequency Divider Register (I2FDR)................................................................. 26-9
I2C Control Register (I2CR)................................................................................... 26-10
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Paragraph
Number
26.5.4
26.5.5
26.6
26.6.1
26.6.2
26.6.3
26.6.4
26.6.5
26.6.6
26.6.7
Title
Page
Number
I2C Status Register (I2SR)......................................................................................
I2C Data I/O Register (I2DR) .................................................................................
I2C Programming Examples .......................................................................................
Initialization Sequence............................................................................................
Generation of START.............................................................................................
Post-Transfer Software Response...........................................................................
Generation of STOP................................................................................................
Generation of Repeated START.............................................................................
Slave Mode .............................................................................................................
Arbitration Lost.......................................................................................................
26-11
26-12
26-13
26-13
26-14
26-14
26-15
26-16
26-16
26-16
Chapter 27
UART Modules
27.1
27.1.1
27.1.2
27.2
27.3
27.3.1
27.3.2
27.3.3
27.3.4
27.3.5
27.3.6
27.3.7
27.3.8
27.3.9
27.3.10
27.3.11
27.3.12
27.3.13
27.4
27.4.1
27.4.1.1
27.4.1.2
27.4.2
27.4.2.1
27.4.2.2
27.4.2.3
27.4.3
Introduction................................................................................................................... 27-1
Overview................................................................................................................... 27-1
Features..................................................................................................................... 27-2
External Signal Description .......................................................................................... 27-3
Memory Map/Register Definition ................................................................................ 27-4
UART Mode Registers 1 (UMR1n) ......................................................................... 27-5
UART Mode Register 2 (UMR2n)........................................................................... 27-7
UART Status Registers (USRn) ............................................................................... 27-8
UART Clock Select Registers (UCSRn) ................................................................ 27-10
UART Command Registers (UCRn)...................................................................... 27-10
UART Receive Buffers (URBn)............................................................................. 27-12
UART Transmit Buffers (UTBn) ........................................................................... 27-12
UART Input Port Change Registers (UIPCRn)...................................................... 27-13
UART Auxiliary Control Register (UACRn)......................................................... 27-13
UART Interrupt Status/Mask Registers (UISRn/UIMRn) ..................................... 27-14
UART Baud Rate Generator Registers (UBG1n/UBG2n)..................................... 27-15
UART Input Port Register (UIPn).......................................................................... 27-16
UART Output Port Command Registers (UOP1n/UOP0n) ................................... 27-16
Functional Description................................................................................................ 27-17
Transmitter/Receiver Clock Source........................................................................ 27-17
Programmable Divider........................................................................................ 27-17
Calculating Baud Rates....................................................................................... 27-18
Transmitter and Receiver Operating Modes........................................................... 27-19
Transmitter.......................................................................................................... 27-19
Receiver .............................................................................................................. 27-21
FIFO.................................................................................................................... 27-23
Looping Modes ....................................................................................................... 27-24
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27.4.3.1
27.4.3.2
27.4.3.3
27.4.4
27.4.5
27.4.5.1
27.4.5.2
27.4.6
27.4.6.1
27.4.6.2
Title
Page
Number
Automatic Echo Mode........................................................................................
Local Loop-Back Mode......................................................................................
Remote Loop-Back Mode...................................................................................
Multidrop Mode......................................................................................................
Bus Operation .........................................................................................................
Read Cycles ........................................................................................................
Write Cycles .......................................................................................................
Programming ..........................................................................................................
Interrupt and DMA Request Initialization..........................................................
UART Module Initialization Sequence ..............................................................
27-24
27-24
27-25
27-25
27-27
27-27
27-27
27-27
27-28
27-30
Chapter 28
Message Digest Hardware Accelerator (MDHA)
28.1
28.1.1
28.1.2
28.1.3
28.2
28.2.1
28.2.1.1
28.2.2
28.2.3
28.2.4
28.2.5
28.2.6
28.2.7
28.2.8
28.2.9
28.2.10
28.3
28.3.1
28.3.2
28.3.3
28.3.3.1
28.3.3.2
28.3.3.3
28.3.3.4
28.3.3.5
28.3.3.6
28.4
Introduction................................................................................................................... 28-1
Overview................................................................................................................... 28-1
Features..................................................................................................................... 28-1
Modes of Operation .................................................................................................. 28-2
Memory Map/Register Definition ................................................................................ 28-3
MDHA Mode Register (MDMR) ............................................................................. 28-4
Invalid Modes ....................................................................................................... 28-6
MDHA Control Register (MDCR) ........................................................................... 28-6
MDHA Command Register (MDCMR) ................................................................... 28-7
MDHA Status Register (MDSR) .............................................................................. 28-8
MDHA Interrupt Status & Mask Registers (MDISR and MDIMR) ...................... 28-10
MDHA Data Size Register (MDDSR).................................................................... 28-11
MDHA Input FIFO (MDIN)................................................................................... 28-12
MDHA Message Digest Registers 0 (MDx0)......................................................... 28-12
MDHA Message Data Size Register (MDMDS).................................................... 28-12
MDHA Message Digest Registers 1 (MDx1)......................................................... 28-13
Functional Description................................................................................................ 28-13
MDHA Top Control................................................................................................ 28-14
FIFO........................................................................................................................ 28-14
MDHA Logic.......................................................................................................... 28-14
Address Decoder................................................................................................. 28-14
Interface Control................................................................................................. 28-14
Auto-Padder........................................................................................................ 28-14
Hashing Engine................................................................................................... 28-14
Hashing Engine Control ..................................................................................... 28-15
Status Interrupt.................................................................................................... 28-15
Initialization/Application Information ........................................................................ 28-15
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28.4.1
28.4.2
28.4.2.1
28.4.2.2
28.4.2.3
28.4.3
28.4.4
28.4.5
Title
Page
Number
Performing a Standard HASH Operation ...............................................................
Performing a HMAC Operation Without the MACFULL Bit ...............................
Generation of Key with IPAD ............................................................................
Generation of Key with OPAD...........................................................................
HMAC Hash .......................................................................................................
Performing a SHA-1 EHMAC................................................................................
Performing a MAC Operation With the MACFULL Bit .......................................
Performing an NMAC ............................................................................................
28-15
28-15
28-16
28-16
28-17
28-17
28-18
28-19
Chapter 29
Symmetric Key Hardware Accelerator (SKHA)
29.1
29.1.1
29.1.2
29.1.2.1
29.1.2.2
29.1.2.3
29.1.2.4
29.1.2.5
29.2
29.2.1
29.2.1.1
29.2.1.2
29.2.1.3
29.2.1.4
29.2.1.5
29.2.1.6
29.2.1.7
29.2.1.8
29.2.1.9
29.2.1.10
29.2.1.11
29.2.1.12
29.3
29.3.1
29.3.2
29.3.3
29.3.4
29.3.4.1
29.3.4.2
Introduction................................................................................................................... 29-1
Features..................................................................................................................... 29-1
Modes of Operation .................................................................................................. 29-1
Data Ecryption Standard (DES & 3DES) Algorithm ........................................... 29-1
Advanced Encryption Standard (AES) Algorithm ............................................... 29-3
Electronic Code Book (ECB) Cipher Mode ......................................................... 29-3
Cipher Block Chaining (CBC) Cipher Mode ....................................................... 29-4
Counter (CTR) Cipher Mode................................................................................ 29-5
Memory Map/Register Definition ................................................................................ 29-6
Register Descriptions................................................................................................ 29-7
SKHA Mode Register (SKMR)............................................................................ 29-7
SKHA Control Register (SKCR).......................................................................... 29-8
SKHA Command Register (SKCMR).................................................................. 29-9
SKHA Status Register (SKSR)........................................................................... 29-10
SKHA Error Status Register (SKESR)............................................................... 29-11
SKHA Error Status Mask Register (SKESMR) ................................................. 29-12
SKHA Key Size Register (SKKSR) ................................................................... 29-13
SKHA Data Size Register (SKDSR) .................................................................. 29-13
SKHA Input FIFO .............................................................................................. 29-14
SKHA Output FIFO........................................................................................... 29-14
SKHA Key Data Registers (SKKDRn) ............................................................. 29-14
SKHA Context Registers (SKCRn)................................................................... 29-15
Functional Description................................................................................................ 29-16
Transmit FIFO Interface Block............................................................................... 29-17
Receive FIFO Interface Block ................................................................................ 29-17
Top Control Block .................................................................................................. 29-17
SKHA Logic Block................................................................................................. 29-17
Address Decode Logic........................................................................................ 29-18
Error Interrupt/Status Logic................................................................................ 29-18
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29.3.4.3
29.3.5
29.4
29.4.1
29.4.2
Title
Page
Number
SKHA Core.........................................................................................................
Security Assurance Features...................................................................................
Initialization/Application Information ........................................................................
General Operation...................................................................................................
Operation with Context Switch...............................................................................
29-18
29-19
29-19
29-19
29-20
Chapter 30
Random Number Generator (RNG)
30.1
30.1.1
30.2
30.2.1
30.2.2
30.2.3
30.2.4
30.3
30.3.1
30.3.2
30.3.3
30.3.4
30.4
Introduction...................................................................................................................
Overview...................................................................................................................
Memory Map/Register Definition ................................................................................
RNG Control Register (RNGCR) .............................................................................
RNG Status Register (RNGSR)................................................................................
RNG Entropy Register (RNGER).............................................................................
RNG Output FIFO (RNGOUT)................................................................................
Functional Description..................................................................................................
Output FIFO..............................................................................................................
RNG Core/Control Logic Block ...............................................................................
RNG Control Block ..................................................................................................
RNG Core Engine.....................................................................................................
Initialization/Application Information ..........................................................................
30-1
30-1
30-1
30-1
30-2
30-3
30-4
30-5
30-5
30-5
30-5
30-6
30-6
Chapter 31
Debug Support
31.1
31.1.1
31.2
31.3
31.3.1
31.4
31.4.1
31.4.2
31.4.3
31.4.4
31.4.5
31.4.6
31.4.7
31.5
Introduction................................................................................................................... 31-1
Overview................................................................................................................... 31-1
External Signal Description .......................................................................................... 31-2
Real-Time Trace Support.............................................................................................. 31-2
Begin Execution of Taken Branch (PST = 0x5) ....................................................... 31-4
Memory Map/Register Definition ................................................................................ 31-5
Revision A Shared Debug Resources ....................................................................... 31-7
Address Attribute Trigger Register (AATR) ............................................................ 31-7
Address Breakpoint Registers (ABLR, ABHR) ....................................................... 31-8
Configuration/Status Register (CSR)........................................................................ 31-9
Data Breakpoint/Mask Registers (DBR, DBMR)................................................... 31-12
Program Counter Breakpoint/Mask Registers (PBR, PBMR)................................ 31-13
Trigger Definition Register (TDR) ......................................................................... 31-14
Background Debug Mode (BDM) .............................................................................. 31-16
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31.5.1
31.5.2
31.5.2.1
31.5.2.2
31.5.3
31.5.3.1
31.5.3.2
31.5.3.3
31.6
31.6.1
31.6.1.1
31.6.2
31.7
31.7.1
31.7.2
31.8
Title
Page
Number
CPU Halt.................................................................................................................
BDM Serial Interface..............................................................................................
Receive Packet Format .......................................................................................
Transmit Packet Format......................................................................................
BDM Command Set................................................................................................
ColdFire BDM Command Format......................................................................
Command Sequence Diagrams...........................................................................
Command Set Descriptions ................................................................................
Real-Time Debug Support ..........................................................................................
Theory of Operation................................................................................................
Emulator Mode ...................................................................................................
Concurrent BDM and Processor Operation ............................................................
Processor Status, DDATA Definition.........................................................................
User Instruction Set ................................................................................................
Supervisor Instruction Set.......................................................................................
Freescale-Recommended BDM Pinout ......................................................................
31-16
31-17
31-18
31-19
31-19
31-21
31-22
31-23
31-37
31-37
31-39
31-39
31-40
31-40
31-44
31-45
Chapter 32
IEEE 1149.1 Test Access Port (JTAG)
32.1
32.1.1
32.1.2
32.1.3
32.2
32.2.1
32.2.2
32.2.3
32.2.4
32.2.5
32.2.6
32.3
32.3.1
32.3.1.1
32.3.1.2
32.3.1.3
32.3.1.4
32.3.1.5
32.4
32.4.1
32.4.2
Introduction...................................................................................................................
Block Diagram..........................................................................................................
Features.....................................................................................................................
Modes of Operation ..................................................................................................
External Signal Description ..........................................................................................
JTAG Enable (JTAG_EN)........................................................................................
Test Clock Input (TCLK) .........................................................................................
Test Mode Select/Breakpoint (TMS/BKPT).............................................................
Test Data Input/Development Serial Input (TDI/DSI) .............................................
Test Reset/Development Serial Clock (TRST/DSCLK) ..........................................
Test Data Output/Development Serial Output (TDO/DSO).....................................
Memory Map/Register Definition ................................................................................
Register Descriptions................................................................................................
Instruction Shift Register (IR) ..............................................................................
IDCODE Register.................................................................................................
Bypass Register ....................................................................................................
TEST_CTRL Register ..........................................................................................
Boundary Scan Register .......................................................................................
Functional Description..................................................................................................
JTAG Module ...........................................................................................................
TAP Controller .........................................................................................................
32-1
32-1
32-2
32-3
32-3
32-3
32-4
32-4
32-4
32-4
32-5
32-5
32-5
32-5
32-5
32-6
32-6
32-7
32-7
32-7
32-7
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32.4.3
32.4.3.1
32.4.3.2
32.4.3.3
32.4.3.4
32.4.3.5
32.4.3.6
32.4.3.7
32.5
32.5.1
32.5.2
Title
Page
Number
JTAG Instructions..................................................................................................... 32-8
EXTEST Instruction ............................................................................................. 32-9
IDCODE Instruction............................................................................................. 32-9
SAMPLE/PRELOAD Instruction......................................................................... 32-9
ENABLE_TEST_CTRL Instruction .................................................................. 32-10
HIGHZ Instruction.............................................................................................. 32-10
CLAMP Instruction ............................................................................................ 32-10
BYPASS Instruction........................................................................................... 32-10
Initialization/Application Information ........................................................................ 32-11
Restrictions ............................................................................................................. 32-11
Nonscan Chain Operation....................................................................................... 32-11
Appendix A
Register Memory Map Quick Reference
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MCF5275 Reference Manual, Rev. 1.1
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About This Book
The primary objective of this reference manual is to define the functionality of the MCF5275
processor for use by software and hardware developers. In addition, this manual supports the
MCF5274. This book is written from the perspective of the MCF5275, and unless otherwise noted,
the information applies also to the MCF5274. The MCF5274 has the same functionality as the
MCF5275 and any differences in data regarding bus timing, signal behavior, and AC, DC, and
thermal characteristics are in the hardware specifications. Please refer to Section 1.1, “MCF5275
Family Configurations,” to see a summary of the differences.
The information in this book is subject to change without notice, as described in the disclaimers
on the title page. As with any technical documentation, it is the reader’s responsibility to be sure
he is using the most recent version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com/coldfire.
Audience
This manual is intended for system software and hardware developers and applications
programmers who want to develop products with the MCF5275. It is assumed that the reader
understands operating systems, microprocessor system design, basic principles of software and
hardware, and basic details of the ColdFire® architecture.
Organization
Following is a summary and brief description of the major sections of this manual:
•
•
•
•
Chapter 1, “Overview,” includes general descriptions of the modules and features
incorporated in the MCF5275, focussing in particular on new features.
Chapter 2, “Signal Descriptions,” describes MCF5275 signals. It includes a listing of
signals that characterizes each signal as an input or output, defines its state at reset, and
identifies whether a pull-up resistor should be used.
Chapter 3, “ColdFire Core,” provides an overview of the microprocessor core of the
MCF5275. The chapter describes the organization of the Version 2 (V2) ColdFire processor
core and an overview of the program-visible registers (the programming model) as they are
implemented on the MCF5275.
Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC),” describes the MCF5275
multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and
miscellaneous register instructions. The EMAC is integrated into the operand execution
pipeline (OEP).
MCF5275 Reference Manual, Rev. 2
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About This Book
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Chapter 5, “Cache,” describes the MCF5275 cache implementation, including
organization, configuration, and coherency. It describes cache operations and how the
cache interacts with other memory structures.
Chapter 6, “Static RAM (SRAM),” describes the MCF5275 on-chip static RAM (SRAM)
implementation. It covers general operations, configuration, and initialization. It also
provides information and examples of how to minimize power consumption when using the
SRAM.
Chapter 7, “Clock Module,” describes the MCF5275’s different clocking methods. It also
describes clock module operation in low power modes.
Chapter 8, “Power Management,” describes the low power operation of the MCF5275 and
peripheral behavior in low power modes.
Chapter 9, “Chip Configuration Module (CCM),” describes CCM functionality, detailing
the two modes of chip operation: master mode and single-chip mode. This chapter provides
a description of signals used by the CCM and a programming model.
Chapter 10, “Reset Controller Module,” describes the operation of the reset controller
module, detailing the different types of reset that can occur.
Chapter 11, “System Control Module (SCM),” describes the functionality of the SCM,
which provides the programming model for the System Access Control Unit (SACU), the
system bus arbiter, a 32-bit Core Watchdog Timer (CWT), and the system control registers
and logic.
Chapter 12, “General Purpose I/O Module,” describes the operation and programming
model of the general purpose I/O (GPIO) ports on the MCF5275.
Chapter 13, “Interrupt Controller Modules,” describes operation of the interrupt controller
portion of the SCM. Includes descriptions of the registers in the interrupt controller
memory map and the interrupt priority scheme.
Chapter 14, “Edge Port Module (EPORT),” describes EPORT module functionality,
including operation in low power mode.
Chapter 15, “Chip Select Module,” describes the MCF5275 chip-select implementation,
including the operation and programming model, which includes the chip-select address,
mask, and control registers.
Chapter 16, “External Interface Module (EIM),” describes data-transfer operations, error
conditions, bus arbitration, and reset operations.
Chapter 17, “SDRAM Controller (SDRAMC),” describes the configuration and operation
of the SDRAM controller. It begins with a general description and brief glossary, and
includes a description of signals involved in DRAM operations. The remainder of the
chapter describes the programming model and signal timing, as well as the command set
required for synchronous operations.
Chapter 18, “DMA Controller Module,” describes the MCF5275 Direct Memory Access
(DMA) controller module. It provides an overview of the module and describes in detail its
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Organization
•
•
•
•
•
•
•
•
•
•
•
signals and registers. The latter sections of this chapter describe operations, features, and
supported data transfer modes in detail.
Chapter 19, “Fast Ethernet Controllers (FEC0 & FEC1),” provides a feature-set overview,
a functional block diagram, and transceiver connection information for both MII (Media
Independent Interface) and 7-wire serial interfaces. It also provides describes operation and
the programming model.
Chapter 20, “Universal Serial Bus,” provides an overview of the universal serial bus (USB)
device module. The USB Specification, Revision 2.0 is a recommended supplement to this
chapter.
Chapter 21, “Watchdog Timer Module,” describes Watchdog timer functionality, including
operation in low power mode.
Chapter 22, “Pulse Width Modulation (PWM) Module,” describes the configuration and
operation of the pulse width modulation (PWM) module. It includes a block diagram,
programming model, and functional description.
Chapter 23, “Programmable Interrupt Timer Modules (PIT0–PIT3),” describes the
functionality of the four PIT timers, including operation in low power mode.
Chapter 25, “DMA Timers (DTIM0–DTIM3),” describes the configuration and operation
of the four DMA timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit
timers provide input capture and reference compare capabilities with optional signaling of
events using interrupts or triggers. This chapter also provides programming examples.
Chapter 24, “Queued Serial Peripheral Interface (QSPI) Module,” provides a feature-set
overview and a description of operation, including details of the QSPI’s internal storage
organization. The chapter concludes with the programming model and a timing diagram.
Chapter 27, “UART Modules,” describes the use of the universal asynchronous
receiver/transmitters (UARTs) implemented on the MCF5275 and includes programming
examples.
Chapter 26, “I2C Interface,” describes the MCF5275 I2C module, including I2C protocol,
clock synchronization, and I2C programming model registers. It also provides extensive
programming examples.
Chapter 28, “Message Digest Hardware Accelerator (MDHA),” describes implementation
of two of the world’s most popular cryptographic hash functions: SHA-1 and MD5.
Accelerators for either algorithm separately have been designed, however the MDHA
combines similar functions of the two algorithms into one small, optimized area of silicon
on the MCF5275 device.
Chapter 30, “Random Number Generator (RNG),” describes the 32-bit Random Number
Generator (RNG), including a programming model, functional description, and application
information.
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•
•
•
Chapter 29, “Symmetric Key Hardware Accelerator (SKHA),” describes the cryptographic
hardware coprocessor designed to implement two widely used symmetric key block cipher
algorithms, AES and DES.
Chapter 32, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and
operation of the MCF5275 Joint Test Action Group (JTAG) implementation. It describes
those items required by the IEEE 1149.1 standard and provides additional information
specific to the MCF5275. For internal details and sample applications, see the IEEE 1149.1
document.
Chapter 31, “Debug Support,” describes the Revision A enhanced hardware debug support
in the MCF5275.
This manual includes the following appendix:
•
Appendix A, “Register Memory Map Quick Reference,” provides the entire address-map
for MCF5275 memory-mapped registers.
Suggested Reading
This section lists additional reading that provides background for the information in this manual
as well as general information about the ColdFire architecture.
Hardware Specification
The MCF5275EC document contains the mechanical and electrical specifications of the
MCF5275. It can be found at http://www.freescale.com/coldfire.
General Information
The following documentation provides useful information about the ColdFire architecture and
computer architecture in general:
•
•
•
•
ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD)
Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray,
Ross Bannatyne, Joseph D. Greenfield
Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy
and David A. Patterson.
Computer Organization and Design: The Hardware/Software Interface, Second Edition,
David A. Patterson and John L. Hennessy.
ColdFire Documentation
ColdFire documentation is available from the sources listed on the back cover of this manual.
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Conventions
•
•
•
•
•
Reference manuals (formerly called user’s manuals)—These books provide details about
individual ColdFire implementations and are intended to be used in conjunction with The
ColdFire Programmers Reference Manual.
Addenda/errata to reference manuals—Because some processors have follow-on parts, an
addendum is provided that describes the additional features and functionality changes.
Also, if mistakes are found within a reference manual, an errata document will be issued
before the next published release of the reference manual. These addenda/errata are
intended for use with the corresponding reference manuals.
Hardware specifications—Hardware specifications provide specific data regarding bus
timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design
considerations.
Product briefs—Each device has a product brief that provides an overview of its features.
This document is roughly equivalent to the overview (Chapter 1) of an implementation’s
reference manual.
Application notes—These short documents address specific design issues useful to
programmers and engineers working with Freescale Semiconductor processors.
Additional literature is published as new processors become available. For a current list of
ColdFire documentation, refer to http://www.freescale.com/coldfire.
Conventions
This document uses the following notational conventions:
MNEMONICS
In text, instruction mnemonics are shown in uppercase.
mnemonics
In code and tables, instruction mnemonics are shown in lowercase.
italics
Italics indicate variable command parameters.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
REG[FIELD]
Abbreviations for registers are shown in uppercase. Specific bits, fields, or
ranges appear in brackets. For example, RAMBAR[BA] identifies the base
address field in the RAM base address register.
nibble
A 4-bit data unit
byte
An 8-bit data unit
word
A 16-bit data unit1
longword
A 32-bit data unit
1. The only exceptions to this appear in the discussion of serial communication modules that support variable-length data
transmission units. To simplify the discussion these units are referred to as words regardless of length.
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About This Book
x
In some contexts, such as signal encodings, x indicates a don’t care.
n
Used to express an undefined numerical value
~
NOT logical operator
&
AND logical operator
|
OR logical operator
Acronyms and Abbreviations
Table i lists acronyms and abbreviations used in this document.
Table i. Acronyms and Abbreviated Terms
Term
Meaning
ADC
Analog-to-digital conversion
ALU
Arithmetic logic unit
BDM
Background debug mode
BIST
Built-in self test
BSDL
Boundary-scan description language
CODEC
Code/decode
DAC
Digital-to-analog conversion
DMA
Direct memory access
DSP
Digital signal processing
EA
Effective address
FIFO
First-in, first-out
GPIO
General-purpose I/O
I2C
Inter-integrated circuit
IEEE
Institute for Electrical and Electronics Engineers
IFP
Instruction fetch pipeline
IPL
Interrupt priority level
JEDEC
Joint Electron Device Engineering Council
JTAG
Joint Test Action Group
LIFO
Last-in, first-out
LRU
Least recently used
LSB
Least-significant byte
lsb
MAC
MBAR
Least-significant bit
Multiply accumulate unit, also Media access controller
Memory base address register
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Terminology Conventions
Table i. Acronyms and Abbreviated Terms (Continued)
Term
Meaning
MSB
Most-significant byte
msb
Most-significant bit
Mux
Multiplex
NOP
No operation
OEP
Operand execution pipeline
PC
Program counter
PCLK
Processor clock
PLIC
Physical layer interface controller
PLL
Phase-locked loop
POR
Power-on reset
PQFP
Plastic quad flat pack
PWM
Pulse width modulation
QSPI
Queued serial peripheral interface
RISC
Reduced instruction set computing
Rx
Receive
SIM
System integration module
SOF
Start of frame
TAP
Test access port
TTL
Transistor transistor logic
Tx
UART
USB
Transmit
Universal asynchronous/synchronous receiver transmitter
Universal serial bus
Terminology Conventions
Table ii shows terminology conventions used throughout this document.
Table ii. Notational Conventions
Instruction
Operand Syntax
Opcode Wildcard
cc
Logical condition (example: NE for not equal)
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Table ii. Notational Conventions (Continued)
Instruction
Operand Syntax
Register Specifications
An
Ay,Ax
Any address register n (example: A3 is address register 3)
Source and destination address registers, respectively
Dn
Any data register n (example: D5 is data register 5)
Dy,Dx
Source and destination data registers, respectively
Rc
Any control register (example VBR is the vector base register)
Rm
MAC registers (ACC, MAC, MASK)
Rn
Any address or data register
Rw
Destination register w (used for MAC instructions only)
Ry,Rx
Xi
Any source and destination registers, respectively
Index register i (can be an address or data register: Ai, Di)
Register Names
ACC
MAC accumulator register
CCR
Condition code register (lower byte of SR)
MACSR
MAC status register
MASK
MAC mask register
PC
Program counter
SR
Status register
Port Name
DDATA
PST
Debug data port
Processor status port
Miscellaneous Operands
#<data>
<ea>
<ea>y,<ea>x
<label>
Immediate data following the 16-bit operation word of the instruction
Effective address
Source and destination effective addresses, respectively
Assembly language program label
<list>
List of registers for MOVEM instruction (example: D3–D0)
<shift>
Shift operation: shift left (<<), shift right (>>)
<size>
Operand data size: byte (B), word (W), longword (L)
bc
Both instruction and data caches
dc
Data cache
ic
Instruction cache
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Terminology Conventions
Table ii. Notational Conventions (Continued)
Instruction
# <vector>
<>
<xxx>
Operand Syntax
Identifies the 4-bit vector number for trap instructions
identifies an indirect data address referencing memory
identifies an absolute address referencing memory
dn
Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
SF
Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Operations
+
Arithmetic addition or postincrement indicator
–
Arithmetic subtraction or predecrement indicator
x
Arithmetic multiplication
/
Arithmetic division
~
Invert; operand is logically complemented
&
Logical AND
|
Logical OR
^
Logical exclusive OR
<<
Shift left (example: D0 << 3 is shift D0 left 3 bits)
>>
Shift right (example: D0 >> 3 is shift D0 right 3 bits)
→
Source operand is moved to destination operand
←→
Two operands are exchanged
sign-extended
All bits of the upper portion are made equal to the high-order bit of the lower portion
If <condition>
then
<operations>
else
<operations>
Test the condition. If true, the operations after ‘then’ are performed. If the condition is false and the
optional ‘else’ clause is present, the operations after ‘else’ are performed. If the condition is false
and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description
as an example.
MCF5275 Reference Manual, Rev. 2
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About This Book
Table ii. Notational Conventions (Continued)
Instruction
Operand Syntax
Subfields and Qualifiers
{}
Optional operation
()
Identifies an indirect address
dn
Displacement value, n-bits wide (example: d16 is a 16-bit displacement)
Address
Calculated effective address (pointer)
Bit
Bit selection (example: Bit 3 of D0)
lsb
Least significant bit (example: lsb of D0)
LSB
Least significant byte
LSW
Least significant word
msb
Most significant bit
MSB
Most significant byte
MSW
Most significant word
Condition Code Register Bit Names
C
Carry
N
Negative
V
Overflow
X
Extend
Z
Zero
Revision History
Table iii provides a revision history for this document.
Table iii. MCF5275RM Revision History
Location
Substantive Changes
Revision 0, 04/26/2004
—
Initial customer-release version.
Revision 1.0, 08/16/2004
—
Various updates and formatting changes.
Revision 1.1, 05/2005
—
Changes are noted in revision 1.3 or later of the MCF5275RMAD document.
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Revision History
Table iii. MCF5275RM Revision History (Continued)
Location
Substantive Changes
Revision 2, 07/2006
—
Changes are noted in revision 1.8 or later of the MCF5275RMAD document.
MCF5275 Reference Manual, Rev. 2
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About This Book
MCF5275 Reference Manual, Rev. 2
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Chapter 1
Overview
The MCF5275 family is a highly integrated implementation of the ColdFire® family of reduced
instruction set computing (RISC) microprocessors. This document describes pertinent features
and functions characteristics of the MCF5275 family. The MCF5275 family includes the
MCF5275, MCF5275L, MCF5274 and MCF5274L microprocessors. The differences between
these parts are summarized below in Table 1-1. This document is written from the perspective of
the MCF5275 and unless otherwise noted, the information applies also to the MCF5275L,
MCF5274 and MCF5274L.
The MCF5275 family delivers a new level of performance and integration on the popular version
2 ColdFire core with up to 144 (Dhrystone 2.1) MIPS @ 150MHz. These highly integrated
microprocessors build upon the widely used peripheral mix on the popular MCF5272 ColdFire
microprocessor (10/100 Mbps Ethernet MAC and USB device) by adding a second 10/100 Mbps
Ethernet MAC (MCF5274 & MCF5275) and hardware encryption (MCF5275L and MCF5275).
In addition, the MCF5275 family features an Enhanced Multiply Accumulate Unit (EMAC), large
on-chip memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM
memory controller.
These devices are ideal for cost-sensitive applications requiring significant control processing for
file management, connectivity, data buffering, and user interface, as well as signal processing in a
variety of key markets such as security, imaging, networking, gaming, and medical. This leading
package of integration and high performance allows fast time to market through easy code reuse
and extensive third party tool support.
To locate any published errata or updates for this document, refer to the ColdFire products website
at http://www.freescale.com/coldfire.
1.1
MCF5275 Family Configurations
Table 1-1. MCF5275 Family Configurations
Module
ColdFire Version 2 Core with EMAC (Enhanced
Multiply-Accumulate Unit)
5274L
5275L
5274
5275
x
x
x
x
System Clock
up to 150 MHz
Performance (Dhrystone/2.1 MIPS)
144
Instruction/Data Cache
16 Kbytes (configurable)
Static RAM (SRAM)
64 Kbytes
Interrupt Controllers (INTC)
2
2
2
2
Edge Port Module (EPORT)
x
x
x
x
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1-1
Overview
Table 1-1. MCF5275 Family Configurations (Continued)
Module
5274L
5275L
5274
5275
External Interface Module (EIM)
x
x
x
x
4-channel Direct-Memory Access (DMA)
x
x
x
x
DDR SDRAM Controller
x
x
x
x
Fast Ethernet Controller (FEC)
1
1
2
2
Watchdog Timer Module (WDT)
x
x
x
x
4-channel Programmable Interval Timer Module (PIT)
x
x
x
x
32-bit DMA Timers
4
4
4
4
USB
x
x
x
x
QSPI
x
x
x
x
UART(s)
up to 3
up to 3
3
3
I2 C
x
x
x
x
PWM
4
4
4
4
General Purpose I/O Module (GPIO)
x
x
x
x
CIM = Chip Configuration Module + Reset Controller Module
x
x
x
x
Debug BDM
x
x
x
x
JTAG - IEEE 1149.1 Test Access Port
x
x
x
x
Cryptography Hardware Accelerators
—
x
—
x
196
MAPBGA
196
MAPBGA
256
MAPBGA
256
MAPBGA
Package
1.2
Block Diagram
The superset device in the MCF5275 family comes in a 256 mold array process ball grid array
(MAPBGA) package. Figure 1-1 shows a top-level block diagram of the MCF5275.
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Freescale Semiconductor
Block Diagram
DDR
EIM
QSPI
I2C_SDA
CHIP
SELECTS
(To/From SRAM backdoor)
I2C_SCL
UnTXD
UnRXD
INTC0
Arbiter
EBI
INTC1
UnRTS
UnCTS
DTnOUT
DTnIN
FAST ETHERNET
CONTROLLER
(FEC0)
FEC0
UART
0
FAST ETHERNET
CONTROLLER
(FEC1)
(To/From PADI)
UART
1
DTIM
0
(To/From
PADI)
UART
2
DTIM
1
I2 C
QSPI
SDRAMC
DTIM
3
DTIM
2
PADI – Pin Muxing
(To/From PADI)
FEC1
USB
PWMn
D[31:16]
A[23:0]
R/W
CS[3:0]
4 CH DMA
TA
JTAG_EN
TRST
DACK[3:0]
BDM
DREQ[1:0]
JTAG
TAP
V2 ColdFire CPU
TCLK
TMS
EMAC
DIV
TDI
MUX
TDO
TSIZ[1:0]
JTAG_EN
TEA
BS[3:2]
64 Kbytes
SRAM
(8Kx16)x4
(To/From
PADI)
(To/From PADI)
16 Kbytes
CACHE
(1Kx32)x4
4 CH PWM
PORTS
(GPIO)
CIM
(To/From Arbiter backdoor)
Watchdog
Timer
SKHA
PLL
CLKGEN
RNGA
USB 2.0
Full Speed
MDHA
(To/From PADI)
PIT0
PIT1
PIT2
PIT3
(To/From INTC)
Edge
Port
Cryptography
Modules
Figure 1-1. MCF5275 Block Diagram
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1-3
Overview
1.3
Features
1.3.1
Feature Overview
•
•
•
•
•
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data path on-chip
— Processor core runs at twice the internal bus frequency
— Sixteen general-purpose 32-bit data and address registers
— Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to
support the user stack pointer register, and 4 new instructions for improved bit
processing
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support
32-bit signal processing algorithms
— Illegal instruction decode that allows for 68K emulation support
System debug support
— Real time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with two user-visible hardware breakpoint registers (PC and
address with optional data) that can be configured into a 1- or 2-level trigger
On-chip memories
— 16-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus
masters (e.g., DMA, FEC)
Two Fast Ethernet Controllers (FEC)
— 10 BaseT capability, half duplex or full duplex
— 100 BaseT capability, half duplex or full duplex
— On-chip transmit and receive FIFOs
— Built-in dedicated DMA controller
— Memory-based flexible descriptor rings
— Media independent interface (MII) to external transceiver (PHY)
USB Device Module
— Supports full-speed 12-Mbps and low-speed 1.5-Mbps USB devices
— Automatic hardware processing of USB standard device requests
— Requires external transceiver
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Features
•
•
•
•
— Protocol control and administration for up to four endpoints (programmable types)
— One FIFO RAM per endpoint (2-Kbyte total)
— Dedicated 1-Kbyte descriptor RAM
— Remote wake-up
Three Universal Asynchronous Receiver Transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic
— Maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (UnRTS) and clear-to-send (UnCTS) lines for
two UARTs
— Transmit and receive FIFO buffers
I2C Module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master or slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued Serial Peripheral Interface (QSPI)
— Full-duplex, three-wire synchronous transfers
— Up to four chip selects available
— Master mode operation only
— Programmable master bit rates
— Up to 16 pre-programmed transfers
Four 32-bit DMA Timers
— 12-ns resolution at 83 MHz
— Programmable sources for clock input, including an external clock option
— Programmable prescaler
— Input-capture capability with programmable trigger edge on input pin
— Output-compare with programmable mode for the output pin
— Free run and restart modes
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1-5
Overview
•
•
•
•
•
•
— Maskable interrupts on input capture or reference-compare
— DMA trigger capability on input capture or reference-compare
Pulse width modulation (PWM) unit
— Four independent channels with programmable period and duty cycle
Four Periodic Interrupt Timers (PITs)
— 16-bit counter
— Selectable as free running or count down
Software Watchdog Timer
— 16-bit counter
— Low power mode support
Phase Locked Loop (PLL)
— Crystal or external oscillator reference
— 8 to 25 MHz reference frequency for normal PLL mode
— 24 to 75 MHz oscillator reference frequency for 1:1 mode (input freq = core freq = 2 ×
CLKOUT)
— Separate clock output pins
Interrupt Controllers (x2)
— Support for up to 110 interrupt sources per interrupt controller organized as follows:
– 103 fully-programmable interrupt sources
– 7 fixed-level interrupt sources
— Seven external interrupt signals
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
DMA Controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16- and 32-bit data capability along with support
for 16-byte (4 x 32-bit) burst transfers
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
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Freescale Semiconductor
Features
•
•
•
•
— Software-programmable connections between the four DMA channels and the 14 DMA
requesters in the UARTs (6), 32-bit timers (4), and external logic (4)
External Bus Interface
— Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)
— Support for n-1-1-1 burst fetches from page mode Flash
— Glueless interface to SRAM devices with or without byte strobe inputs
— Programmable wait state generator
— 16-bit bidirectional data bus
— 24-bit address bus
— Up to eight chip selects available
— Byte/write enables (byte strobes)
— Ability to boot from external memories that are 8 or 16 bits wide
DDR SDRAM controller
— Supports 16-bit wide memory devices
— Supports Dual Data Rate (DDR) SDRAM.
— Page mode support
— Programmable refresh interval timer.
— Sleep mode and self-refresh.
— Supports 16-byte (4-beat, 4-byte or 8-beat, 2-byte) critical-word-first burst transfer.
— Up to two chip selects available supporting 8 Mbyte to 128 MByte each.
— 150 MHz data transfer rate (DDR)
Chip Integration Module (CIM)
— System configuration during reset
— Selects one of four clock modes
— Sets boot device and its data port width
— Configures output pad drive strength
— Unique part identification number and part revision number
— Reset
– Separate reset in and reset out signals
– Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss
of clock, PLL loss of lock
– Status flag indication of source of last reset
General Purpose I/O interface
— Up to 65 bits of general purpose I/O
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1-7
Overview
•
1.3.2
— Bit manipulation supported via set/clear functions
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
V2 Core Overview
The processor core is comprised of two separate pipelines that are decoupled by an instruction
buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address
generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that
holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The
OEP includes two pipeline stages. The first stage decodes instructions and selects operands
(DSOC); the second stage (AGEX) performs instruction execution and calculates operand
effective addresses, if needed.
The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support
for a separate user stack pointer register and four new instructions to assist in bit processing.
Additionally, the MCF5275 core includes the enhanced multiply-accumulate unit (EMAC) for
improved signal processing capabilities. The EMAC implements a 4-stage execution pipeline,
optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. Supported
operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands
and a complete set of instructions to process these data types. The EMAC provides superb support
for execution of DSP operations within the context of a single processor at a minimal hardware
cost.
1.3.3
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging in
conjunction with low-cost debug and emulator development tools. Through a standard debug
interface, users can access real-time trace and debug information. This allows the processor and
system to be debugged at full speed without the need for costly in-circuit emulators. The debug
interface is a superset of the BDM interface provided on the 683xx family of parts.
The on-chip breakpoint resources include a total of 8 programmable registers—a set of address
registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit
data mask register), an address attribute register, a trigger definition register, and one 32-bit PC
register plus a 32-bit PC mask register. These registers can be accessed through the dedicated
debug serial communication channel or from the processor’s supervisor mode programming
model. The breakpoint registers can be configured to generate triggers by combining the address,
data, and PC conditions in a variety of single or dual-level definitions. The trigger event can be
programmed to generate a processor halt or initiate a debug interrupt exception.
To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and
debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status,
MCF5275 Reference Manual, Rev. 2
1-8
Freescale Semiconductor
Features
captured operand data, and branch target addresses defining processor activity at the CPU’s clock
rate.
1.3.4
JTAG
The MCF5275 supports circuit board test strategies based on the Test Technology Committee of
IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP)
consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass
register, a 326-bit boundary-scan register, and a 32-bit ID register). The boundary scan register
links the device’s pins into one shift register. Test logic, implemented using static logic design, is
independent of the device system logic.
The MCF5275 implementation can do the following:
•
•
•
•
•
Perform boundary-scan operations to test circuit board electrical continuity
Sample MCF5275 system pins during operation and transparently shift out the result in the
boundary scan register
Bypass the MCF5275 for a given circuit board test by effectively reducing the
boundary-scan register to a single bit
Disable the output drive to pins during circuit-board testing
Drive output pins to stable levels
1.3.5
1.3.5.1
On-chip Memories
Cache
The 16-Kbyte cache can be configured into one of three possible organizations: an 16-Kbyte
instruction cache, an 16-Kbyte data cache or a split 8-Kbyte instruction/8-Kbyte data cache. The
configuration is software-programmable by control bits within the privileged Cache Configuration
Register (CACR). In all configurations, the cache is a direct-mapped single-cycle memory,
organized as 1024 lines, each containing 16 bytes of data. The memories consist of a 1024-entry
tag array (containing addresses and control bits) and a 16-Kbyte data array, organized as 4096 x
32 bits.
If the desired address is mapped into the cache memory, the output of the data array is driven onto
the ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped
into the tag memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch.
The cache module includes a 16-byte line fill buffer used as temporary storage during miss
processing. For all data cache configurations, the memory operates in write-through mode and all
operand writes generate an external bus cycle.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
1-9
Overview
1.3.5.2
SRAM
The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core
can access in a single cycle. The location of the memory block can be set to any 64-Kbyte
boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data
structures, for use as the system stack, or for storing FEC data buffers. Because the SRAM module
is physically connected to the processor's high-speed local bus, it can quickly service core-initiated
accesses or memory-referencing commands from the debug module.
The SRAM module is also accessible by the DMA and FEC non-core bus masters. The dual-ported
nature of the SRAM makes it ideal for implementing applications with double-buffer schemes,
where the processor and a DMA device operate in alternate regions of the SRAM to maximize
system performance. As an example, system performance can be increased significantly if
Ethernet packets are moved from the FEC into the SRAM (rather than external memory) prior to
any processing.
1.3.6
Fast Ethernet Controller (FEC)
The MCF5275 contains up to two Fast Ethernet Controllers (FEC) which perform the full set of
IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions. The FECs
support connection and functionality for the 10/100 Mbps 802.3 media independent interface
(MII). It requires an external transceiver (PHY) to complete the interface to the media.
1.3.7
Universal Serial Bus (USB)
The USB controller supports device mode data communications with a USB host (typically a PC).
The programmable USB registers allow the user to enable or disable the module, control
characteristics of individual endpoints, and monitor traffic flow through the module without ever
seeing the low-level details of the USB protocol.
1.3.8
UARTs
The MCF5275 contains three full-duplex UARTs that function independently. The three UARTs
can be clocked by the system bus clock, eliminating the need for an externally supplied clock.
They can use DMA requests on transmit-ready and receive-ready as well as interrupt requests for
servicing. Flow control via UnCTS and UnRTS pins is provided on all three UARTS.
1.3.9
I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
exchange, minimizing the interconnection between devices. This bus is suitable for applications
requiring occasional communications over a short distance between many devices.
MCF5275 Reference Manual, Rev. 2
1-10
Freescale Semiconductor
Features
1.3.10 QSPI
The queued serial peripheral interface module provides a high-speed synchronous serial peripheral
interface with queued transfer capability. It allows up to 16 transfers to be queued at once,
eliminating CPU intervention between transfers.
1.3.11 Cryptography
The superset device, MCF5275, incorporates small, fast, dedicated hardware accelerators for
random number generation, message digest and hashing, and the DES, 3DES, and AES block
cipher functions allowing for the implementation of common Internet security protocol
cryptography operations with performance well in excess of software-only algorithms.
1.3.12 DMA Timers (DTIM0-DTIM3)
There are four independent, DMA-transfer-generating 32-bit timers (DTIM[3:0]) on the
MCF5275. Each timer module incorporates a 32-bit timer with a separate register set for
configuration and control. The timers can be configured to operate from the system clock or from
an external clock source using one of the DTINn signals. If the system clock is selected, it can be
divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler
which clocks the actual timer counter register (TCRn). Each of these timers can be configured for
input capture or reference compare mode. By configuring the internal registers, each timer may be
configured to assert an external signal, generate an interrupt on a particular event or cause a DMA
transfer.
1.3.13 Pulse Width Modulation (PWM) Module
The Pulse Width Modulation (PWM) module generates a synchronous series of pulses having
programmable duty cycle. With a suitable low-pass filter, the PWM can be used as a
digital-to-analog converter.
The PWM module has four channels, each having a programmable period and duty cycle as well
as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources
to be used with the counters. Each of the modulators can create independent continuous
waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs can be
programmed as left aligned outputs or center aligned outputs
1.3.14 Periodic Interrupt Timers (PIT0-PIT3)
The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at
regular intervals with minimal processor intervention. Each timer can either count down from the
value written in its PIT modulus register, or it can be a free-running down-counter.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
1-11
Overview
1.3.15 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog
counter is a free-running down-counter that generates a reset on underflow. To prevent a reset,
software must periodically restart the countdown.
1.3.16 Clock Module and Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced
frequency divider (RFD), status/control registers, and control logic. To improve noise immunity,
the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits
are powered by the normal supply pins, VDD, VSS, OVDD, and OVSS.
1.3.17 Interrupt Controllers (INTC0, INTC1)
There are two interrupt controllers on the MCF5275, each of which can support up to 63 interrupt
sources each for a total of 126. Each interrupt controller is organized as 7 levels with 9 interrupt
sources per level. Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of
a given controller provide a programmable level [1-7] and priority within the level.
1.3.18 DMA Controller
The Direct Memory Access (DMA) Controller Module provides an efficient way to move blocks
of data with minimal processor interaction. The DMA module provides four channels
(DMA0-DMA3) that allow byte, word, longword or 16-byte burst line transfers. These transfers
are triggered by software explicitly setting a DCRn[START] bit. Other sources include the DMA
timer, external sources via the DREQ signal, and UARTs. The DMA controller supports dual
address to off-chip or on-chip devices.
1.3.19 External Interface Module (EIM)
The external bus interface handles the transfer of information between the core and memory,
peripherals, or other processing elements in the external address space. Features have been added
to support external Flash modules, for secondary wait states on reads and writes, and a signal to
support Active-Low Address Valid (a signal on most Flash memories).
Programmable chip-select outputs provide signals to enable external memory and peripheral
circuits, providing all handshaking and timing signals for automatic wait-state insertion and data
bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the
starting address must be on a boundary that is a multiple of the block size. Each chip select can be
configured to provide read and write enable signals suitable for use with most popular static RAMs
MCF5275 Reference Manual, Rev. 2
1-12
Freescale Semiconductor
Features
and peripherals. Data bus width (8-bit or 16-bit) is programmable on all chip selects, and further
decoding is available for protection from read-only access.
1.3.20 Double Data Rate (DDR) Synchronous DRAM (SDRAM)
Controller
The SDRAMC provides a 16-bit external interface to double-data-rate (DDR) SDRAM memory
devices. It enables a glueless interface to DDR SDRAM memory devices. It is responsible for
providing address, data and control signals for up to two independent chip-selects.
1.3.21 Reset
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals
to the system, and keep track of what caused the last reset. The power management registers for
the internal low-voltage detect (LVD) circuit are implemented in the reset module. There are six
sources of reset:
•
•
•
•
•
•
External
Power-on reset (POR)
Watchdog timer
Phase locked-loop (PLL) loss of lock
PLL loss of clock
Software
External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are
also software-readable status flags indicating the cause of the last reset.
1.3.22 GPIO
Like the MC68332, unused bus interface and peripheral pins on the MCF5275 can be used as
discrete general-purpose inputs and outputs. These are managed by a dedicated GPIO module that
logically groups all pins into ports located within a contiguous block of memory-mapped control
registers.
All of the pins associated with the external bus interface may be used for several different
functions. Their primary function is to provide an external memory interface to access off-chip
resources. When not used for this, all of the pins may be used as general-purpose digital I/O pins.
In some cases, the pin function is set by the operating mode, and the alternate pin functions are not
supported.
The digital I/O pins on the MCF5275 are grouped into 8-bit ports. Some ports do not use all eight
bits. Each port has registers that configure, monitor, and control the port pins.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
1-13
Overview
1.4
Documentation
Documentation is available from a local Freescale distributor, a Freescale sales office, the
Freescale Literature Distribution Center, or through the Freescale world-wide web address at
http://www.freescale.com/coldfire.
MCF5275 Reference Manual, Rev. 2
1-14
Freescale Semiconductor
Chapter 2
Signal Descriptions
2.1 Introduction
This chapter describes MCF5275 signals. It includes an alphabetical listing of signals that
characterizes each signal as an input or output, defines its state at reset, and identifies whether a
pull-up resistor should be used. Chapter 16, “External Interface Module (EIM),” describes how
these signals interact.
NOTE:
The terms ‘assertion’ and ‘negation’ are used to avoid confusion when
dealing with a mixture of active-low and active-high signals. The term
‘asserted’ indicates that a signal is active, independent of the voltage
level. The term ‘negated’ indicates that a signal is inactive.
Active-low signals, such as SD_SRAS and TA, are indicated with an
overbar.
2.1.1 Overview
Figure 2-1 shows the block diagram of the MCF5275 with the signal interface.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
2-1
CLKMOD1
RESET
Reset
Controller
RSTOUT
TDO/DSO
TCLK
TMS/BKPT
JTAG
Port
TDI/DSI
TRST/DSCLK
TA
JTAG_EN
4
TEA
TS
BS[3:2]
2
OE
TSIZ[1:0]
TEST
Chip
Configuration
PST[3:0]
RCON
CLKMOD0
Power
Management
Signal Descriptions
2
Test
Controller
Debug Module
External
Interface
Module
Ports
Module
4
ColdFire V2 Core
R/W
DDATA[3:0]
64-Kbyte
SRAM
TIP
16
D[31:16]
DIV
EMAC
24
A[23:0]
Interrupt
Controller 0
Interrupt
Controller 1
2
DMA
Controller
Edgeport
IRQ[7:1]
SD_CS[1:0]
Chip
Selects
Internal Bus
Arbiter
8
System
Control
Module (SCM)
CS[7:0]
16-Kbyte
D-Cache/I-Cache
SD_WE
SD_SRAS
SD_SCAS
DDR SDRAM
Controller
SD_CKE
FECn_COL
I2C_SCL
FECn_TXDO
4
Watchdog
Timer
I2C_SDA
UnTXD
UnRXD
UnRTS
3
3
3
3
XTAL
FECn_TXCLK
FECn_TXEN
I2C
Module
4
Clock Module
(PLL)
DTnIN
EXTAL
UnCTS
CLKOUT
DMA
Timer
Modules
(DTIM0–
DTIM3)
UART
Serial I/O
Modules
(UART0–
UART2)
DTnOUT
SD_A10
DDR_CLKOUT
DDR_CLKOUT
FECn_RXCLK
FECn_RXDV
FECn_RXD0
FECn_CRS
FECs
(FEC0–
FEC1)
FECn_TXD[3:1]
PIT
Timers
(PIT0–
PIT3)
USB
QSPI
FECn_TXER
PWMs
(PWM0–
PWM3)
FECn_RXD[3:1]
PWM[0:3]
USB_TP
USB_TXEN
USB_RP
USB_RXD
USB_TN
USB_RN
USB_CLK
USB_SUSP
USB_SPEED
QSPI_CLK
QSPI_CS[1:0]
FECn_MDC
QSPI_DIN
FECn_MDIO
QSPI_DOUT
FECn_RXER
Figure 2-1. MCF5275 Block Diagram with Signal Interfaces
MCF5275 Reference Manual, Rev. 2
2-2
Freescale Semiconductor
Signal Properties Summary
2.2 Signal Properties Summary
Table 2-1 lists the MCF5275 signals grouped by functionality.
NOTE:
In this table and throughout this document a single signal within a
group is designated without square brackets (i.e., A24), while
designations for multiple signals within a group use brackets (i.e.,
A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.
NOTE:
The primary functionality of a pin is not necessarily its default
functionality. Pins that are muxed with GPIO will default to their
GPIO functionality.
Table 2-1. MCF5274 and MCF5275 Signal Information and Muxing
Signal Name
GPIO
Alternate1
Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
Reset
RESET
—
—
—
I
N15
K12
RSTOUT
—
—
—
O
N14
L12
Clock
EXTAL
—
—
—
I
L16
M14
XTAL
—
—
—
O
M16
N14
CLKOUT
—
—
—
O
T12
P9
Mode Selection
CLKMOD[1:0]
—
—
—
I
N13, P13
M11, N11
RCON
—
—
—
I
P8
M6
External Memory Interface and Ports
A[23:21]
PADDR[7:5]
CS[6:4]
—
O
A11, B11, C11
A8, B8, C8
A[20:0]
—
—
—
O
A12, B12, C12,
A13, B13, C13,
A14, B14, C14,
B15, C15, B16,
C16, D14, D15,
E14:16, F14:16
B9, D9, C9,
C10, B10, A11,
C11, B11, A12,
D11, C12, B13,
C13, D12, E11,
D13, E12, F11,
D14, E13, F13
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
2-3
Signal Descriptions
Table 2-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
O
M1, N1, N2, N3,
P1, P2, R1, R2,
P3, R3, T3, N4,
P4, R4, T4, N5
J3, L1, K2, K3,
M1, L2, L3, L4,
K4, J4, M2, N1,
N2, M3, M4, N3
—
O
M3, R5
K1, L5
—
—
O
K1
H4
PBUSCTL[6]
—
—
I
L13
K14
TEA
PBUSCTL[5]
DREQ1
—
I
T8
—
R/W
PBUSCTL[4]
—
—
O
P7
L6
TSIZ1
PBUSCTL[3]
DACK1
—
O
D16
B14
TSIZ0
PBUSCTL[2]
DACK0
—
O
G16
E14
TS
PBUSCTL[1]
DACK2
—
O
L4
H2
TIP
PBUSCTL[0]
DREQ0
—
O
P6
—
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
D[31:16]
—
—
—
BS[3:2]
PBS[3:2]
CAS[3:2]
OE
PBUSCTL[7]
TA
Chip Selects
CS[7:1]
PCS[7:1]
—
—
O
D10:13, E13,
F13, N7
D8, A9, A10,
D10, B12, C14,
P4
CS0
—
—
—
O
R6
N5
DDR SDRAM Controller
DDR_CLKOUT
—
—
—
O
T7
P6
DDR_CLKOUT
—
—
—
O
T6
P5
SD_CS[1:0]
PSDRAM[7:6]
CS[3:2]
—
O
M2, T5
H3, M5
SD_SRAS
PSDRAM[5]
—
—
O
L2
H1
SD_SCAS
PSDRAM[4]
—
—
O
L1
G3
SD_WE
PSDRAM[3]
—
—
O
K2
G4
SD_A10
—
—
—
O
N6
N4
SD_DQS[3:2]
PSDRAM[2:1]
—
—
I/O
M4, P5
J2, P3
SD_CKE
PSDRAM[0]
—
—
O
L3
J1
SD_VREF
—
—
—
I
A15, T2
A13, P2
External Interrupts Port
IRQ[7:5]
PIRQ[7:5]
—
—
I
G13, H16, H15
F14, G13, G14
IRQ[4]
PIRQ[4]
DREQ2
—
I
H14
H11
IRQ[3:2]
PIRQ[3:2]
DREQ[3:2]
—
I
J14, J13
H14, H12
MCF5275 Reference Manual, Rev. 2
2-4
Freescale Semiconductor
Signal Properties Summary
Table 2-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
Signal Name
GPIO
Alternate1
IRQ1
PIRQ[1]
—
Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
—
I
K13
J13
FEC0
FEC0_MDIO
PFECI2C[5]
I2C_SDA
U2RXD
I/O
A7
A3
FEC0_MDC
PFECI2C[4]
I2C_SCL
U2TXD
O
B7
C5
FEC0_TXCLK
PFEC0H[7]
—
—
I
C3
C1
FEC0_TXEN
PFEC0H[6]
—
—
O
D4
C3
FEC0_TXD[0]
PFEC0H[5]
—
—
O
G4
D2
FEC0_COL
PFEC0H[4]
—
—
I
A6
B4
FEC0_RXCLK
PFEC0H[3]
—
—
I
B6
B3
FEC0_RXDV
PFEC0H[2]
—
—
I
B5
C4
FEC0_RXD[0]
PFEC0H[1]
—
—
I
C6
D5
FEC0_CRS
PFEC0H[0]
—
—
I
C7
A2
FEC0_TXD[3:1]
PFEC0L[7:5]
—
—
O
E3, F3, F4
D1, E3, D3
FEC0_TXER
PFEC0L[4]
—
—
O
D3
C2
FEC0_RXD[3:1]
PFEC0L[3:1]
—
—
I
D5, C5, D6
D4, B1, B2
FEC0_RXER
PFEC0L[0]
—
—
I
C4
E4
FEC1
FEC1_MDIO
PFECI2C[3]
—
—
I/O
G1
—
FEC1_MDC
PFECI2C[2]
—
—
O
G2
—
FEC1_TXCLK
PFEC1H[7]
—
—
I
C1
—
FEC1_TXEN
PFEC1H[6]
—
—
O
D2
—
FEC1_TXD[0]
PFEC1H[5]
—
—
O
F1
—
FEC1_COL
PFEC1H[4]
—
—
I
A5
—
FEC1_RXCLK
PFEC1H[3]
—
—
I
B4
—
FEC1_RXDV
PFEC1H[2]
—
—
I
A3
—
FEC1_RXD[0]
PFEC1H[1]
—
—
I
B3
—
FEC1_CRS
PFEC1H[0]
—
—
I
A4
—
FEC1_TXD[3:1]
PFEC1L[7:5]
—
—
O
E1, E2, F2
—
FEC1_TXER
PFEC1L[4]
—
—
O
D1
—
FEC1_RXD[3:1]
PFEC1L[3:1]
—
—
I
B1, B2, A2
—
FEC1_RXER
PFEC1L[0]
—
—
I
C2
—
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
2-5
Signal Descriptions
Table 2-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
Signal Name
GPIO
Alternate1
Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
I2C
I2C_SDA
PFECI2C[1]
U2RXD
—
I/O
B10
B7
I2C_SCL
PFECI2C[0]
U2TXD
—
I/O
C10
A7
—
—
DMA
DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads.
Please refer to the following pins for muxing:
PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for
DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for
DREQ2, TEA for DREQ1, and TIP for DREQ0.
QSPI
QSPI_CS[3:2]
PQSPI[6:5]
PWM[3:2]
DACK[3:2]
O
R13, N12
P10, N9
QSPI_CS1
PQSPI[4]
—
—
O
T14
N10
QSPI_CS0
PQSPI[3]
—
—
O
P12
M9
QSPI_CLK
PQSPI[2]
I2C_SCL
—
O
T15
L11
QSPI_DIN
PQSPI[1]
I2C_SDA
—
I
T13
M10
QSPI_DOUT
PQSPI[0]
—
—
O
R12
L10
UARTs
U2RXD
PUARTH[3]
—
—
I
T9
—
U2TXD
PUARTH[2]
—
—
O
R9
—
U2CTS
PUARTH[1]
PWM1
—
I
P9
—
U2RTS
PUARTH[0]
PWM0
—
O
R8
—
U1RXD
PUARTL[7]
—
—
I
A9
A6
U1TXD
PUARTL[6]
—
—
O
B9
D7
U1CTS
PUARTL[5]
—
—
I
C9
C7
U1RTS
PUARTL[4]
—
—
O
D9
B6
U0RXD
PUARTL[3]
—
—
I
A8
A4
U0TXD
PUARTL[2]
—
—
O
B8
A5
U0CTS
PUARTL[1]
—
—
I
C8
C6
U0RTS
PUARTL[0]
—
—
O
D7
B5
USB
USB_SPEED
PUSBH[0]
—
—
I/O
G14
G11
USB_CLK
PUSBL[7]
—
—
I
G15
F12
MCF5275 Reference Manual, Rev. 2
2-6
Freescale Semiconductor
Signal Properties Summary
Table 2-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
I
J16
H13
—
I
J15
J11
—
—
I
L15
L14
PUSBL[3]
—
—
O
M13
N13
USB_TN
PUSBL[2]
—
—
O
K14
J14
USB_TP
PUSBL[1]
—
—
O
K15
J12
USB_TXEN
PUSBL[0]
—
—
O
L14
K13
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
USB_RN
PUSBL[6]
—
—
USB_RP
PUSBL[5]
—
USB_RXD
PUSBL[4]
USB_SUSP
Timers (and PWMs)
DT3IN
PTIMERH[3]
DT3OUT
U2RTS
I
J4
G2
DT3OUT
PTIMERH[2]
PWM3
U2CTS
O
K3
G1
DT2IN
PTIMERH[1]
DT2OUT
—
I
J2
F3
DT2OUT
PTIMERH[0]
PWM2
—
O
J3
F4
DT1IN
PTIMERL[3]
DT1OUT
—
I
H1
F1
DT1OUT
PTIMERL[2]
PWM1
—
O
H2
F2
DT0IN
PTIMERL[1]
DT0OUT
—
I
H3
E1
DT0OUT
PTIMERL[0]
PWM0
—
O
G3
E2
BDM/JTAG2
DSCLK
—
TRST
—
I
P14
P13
PSTCLK
—
TCLK
—
O
P16
P12
BKPT
—
TMS
—
I
R15
N12
DSI
—
TDI
—
I
R16
M12
DSO
—
TDO
—
O
P15
K11
JTAG_EN
—
—
—
I
R14
P11
DDATA[3:0]
—
—
—
O
P10, N10, P11, M7, N7, P8, L9
N11
PST[3:0]
—
—
—
O
T10, R10, T11,
R11
P7, L8, M8, N8
Test
TEST
—
—
—
I
N9
N6
PLL_TEST
—
—
—
I
M14
—
Power Supplies
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
2-7
Signal Descriptions
Table 2-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
I
M15
M13
—
I
K16
L13
—
—
I
A1, A10, A16,
E5, E12, F6,
F11, G7:10,
H7:10, J1,
J7:10, K7:10,
L6, L11, M5,
N16, R7, T1,
T16
F7, F8, G6:9,
H6:9, J7, J8
—
—
—
I
E6:8, F5, F7,
F8, G5, G6, H5,
H6, J11, J12,
K11, K12, L9,
L10, L12, M9:11
E5:7, F5, F6,
H10, J9, J10,
K8:10
VDD
—
—
—
I
D8, H13, K4, N8
D6, G5, G12,
L7
SD_VDD
—
—
—
I
E9:11, F9, F10, E8:10, F9, F10,
F12, G11, G12, G10, H5, J5, J6,
H11, H12, J5,
K5:7
J6, K5, K6, L5,
L7, L8, M6, M7,
M8
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
VDDPLL
—
—
—
VSSPLL
—
—
VSS
—
OVDD
1
Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled
in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.
2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module
is not responsible for assigning these pins.
2.3 External Signal Descriptions
2.3.1 Reset Signals
Table 2-2 describes signals that are used to either reset the chip or as a reset indication.
Table 2-2. Reset Signals
Signal Name
Abbreviation
Function
I/O
Reset In
RESET
Primary reset input to the device. Asserting RESET immediately
resets the CPU and peripherals.
I
Reset Out
RSTOUT
Driven low for 128 CPU clocks when the soft reset bit of the system
configuration register (SCR[SOFTRST]) is set. It is driven low for 32K
CPU clocks when the software watchdog timer times out or when a
low input level is applied to RESET.
O
MCF5275 Reference Manual, Rev. 2
2-8
Freescale Semiconductor
External Signal Descriptions
2.3.2 PLL and Clock Signals
Table 2-3 describes signals that are used to support the on-chip clock generation circuitry.
Table 2-3. PLL and Clock Signals
Signal Name
Abbreviation
Function
I/O
External Clock In
EXTAL
Always driven by an external clock input except when used as a
connection to the external crystal when the internal oscillator circuit is
used. The clock source is configured during reset by CLKMOD[1:0].
I
Crystal
XTAL
Used as a connection to the external crystal when the internal
oscillator circuit is used to drive the crystal.
O
Clock Out
CLKOUT
This output signal reflects the internal system clock.
O
2.3.3 Mode Selection
Table 2-4 describes signals used in mode selection.
Table 2-4. Mode Selection Signals
Signal Name
Abbreviation
Function
I/O
Clock Mode Selection
CLKMOD[1:0] Configure the clock mode after reset.
I
Reset Configuration
RCON
I
Indicates whether the external D[31:16] pin states affect chip
configuration at reset.
2.3.4 External Memory Interface Signals
These signals are used for doing transactions on the external bus.
Table 2-5 describes signals that are used for doing transactions on the external bus.
Table 2-5. External Memory Interface Signals
Signal Name
Abbreviation
Function
I/O
Address Bus
A[23:0]
The 24 dedicated address signals define the address of external byte,
word, and longword accesses. These three-state outputs are the 24
lsbs of the internal 32-bit address bus and multiplexed with the
SDRAM controller row and column addresses.
O
Data Bus
D[31:16]
These three-state bidirectional signals provide the general purpose
data path between the processor and all other devices.
I/O
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
2-9
Signal Descriptions
Table 2-5. External Memory Interface Signals (Continued)
Signal Name
Byte Strobes
Abbreviation
BS[3:2]
Function
I/O
Define the flow of data on the data bus. During SRAM and peripheral
accesses, these output signals indicate that data is to be latched or
driven onto a byte of the data when driven low. The BS[3:2] signals are
asserted only to the memory bytes used during a read or write access.
BS2 controls access to the least significant byte lane of data, and BS3
controls access to the most significant byte lane of data.
The BS[3:2] signals are asserted during accesses to on-chip
peripherals but not to on-chip SRAM, or cache. During SDRAM
accesses, these signals act as the CAS[3:2] signals, which indicate a
byte transfers between SDRAM and the chip when driven high.
O
For SRAM or Flash devices, the BS[3:2] outputs should be connected
to individual byte strobe signals.
For SDRAM devices, the BS[3:2] should be connected to individual
SDRAM DQM signals. Note that most SDRAMs associate DQM1 with
the MSB, in which case BS3 should be connected to the SDRAM's
DQM1 input.
Output Enable
OE
Indicates when an external device can drive data during external read
cycles.
O
Transfer Acknowledge
TA
Indicates that the external data transfer is complete. During a read
cycle, when the processor recognizes TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes TA, the bus cycle is terminated.
I
Transfer Error
Acknowledge
TEA
Indicates an error condition exists for the bus transfer. The bus cycle
is terminated and the CPU begins execution of the access error
exception.
I
Read/Write
R/W
Indicates the direction of the data transfer on the bus for SRAM (R/W)
and SDRAM (SD_WE) accesses. A logic 1 indicates a read from a
slave device and a logic 0 indicates a write to a slave device
O
Transfer Size
TSIZ[1:0]
When the device is in normal mode, dynamic bus sizing lets the
programmer change data bus width between 8, 16, and 32 bits for
each chip select. The initial width for the bootstrap program chip
select, CS0, is determined by the state of TSIZ[1:0]. The program
should select bus widths for the other chip selects before accessing
the associated memory space. These pins our output pins.
O
Transfer Start
TS
Bus control output signal indicating the start of a transfer.
O
Transfer in Progress
TIP
Bus control output signal indicating bus transfer in progress.
O
Chip Selects
CS[7:0]
These output signals select external devices for external bus
transactions. The CS[3:2] can also be configured to function as
SDRAM chip selects SD_CS[1:0].
O
2.3.5 DDR SDRAM Controller Signals
Table 6 describes signals that are used for DDR SDRAM accesses.
MCF5275 Reference Manual, Rev. 2
2-10
Freescale Semiconductor
External Signal Descriptions
Table 6. SDRAM Controller Signals
Signal Name
Abbreviation
Function
I/O
SDRAM Clock Out
DDR_CLKOUT This output signal reflects the internal system clock.
O
SDRAM Inverted
Clock Out
DDR_CLKOUT This output signal reflects the inverted internal system clock.
O
SDRAM Synchronous
Row Address Strobe
SD_SRAS
SDRAM synchronous row address strobe.
O
SDRAM Synchronous SD_SCAS
Column Address Strobe
SDRAM synchronous column address strobe.
O
SDRAM Write Enable
SD_WE
SDRAM write enable.
O
SDRAM A10
SD_A10
SDRAM address bit 10 or command.
O
SDRAM Chip Selects
SD_CS[1:0]
SDRAM chip select signals.
O
SDRAM Clock Enable
SD_CKE
SDRAM clock enable.
O
SDRAM Data Strobes
SD_DQS[3:2]
SDRAM byte-lane read/write data strobe signals.
O
2.3.6 External Interrupt Signals
Table 2-7 describes the external interrupt signals.
Table 2-7. External Interrupt Signals
Signal Name
External Interrupts
Abbreviation
IRQ[7:1]
Function
I/O
External interrupt sources.
IRQ[3:2] can also be configured as DMA request signals DREQ[3:2].
IRQ4 can also be configured as DMA request signals DREQ2.
I
2.3.7 Fast Ethernet Controller Signals
The following signals are used by the Ethernet modules for data and clock signals.
Table 2-8. Ethernet Module (FEC) Signals
Signal Name
Abbreviation
Function
I/O
Management Data
FECn_MDIO
Transfers control information between the external PHY and the
media-access controller. Data is synchronous to FECn_MDC. Applies
to MII mode operation. This signal is an input after reset. When the
FEC is operated in 10Mbps 7-wire interface mode, this signal should
be connected to VSS.
I/O
Management Data
Clock
FECn_MDC
In Ethernet mode, FECn_MDC is an output clock which provides a
timing reference to the PHY for data transfers on the FECn_MDIO
signal. Applies to MII mode operation.
O
Transmit Clock
FECn_TXCLK
Input clock which provides a timing reference for FECn_TXEN,
FECn_TXD[3:0] and FECn_TXER
I
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
2-11
Signal Descriptions
Table 2-8. Ethernet Module (FEC) Signals (Continued)
Signal Name
Abbreviation
Function
I/O
Transmit Enable
FECn_TXEN
Indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the
first FECn_TXCLK following the final nibble of the frame.
O
Transmit Data 0
FECn_TXD0
FECn_TXD0 is the serial output Ethernet data and is only valid during
the assertion of FECn_TXEN. This signal is used for 10-Mbps
Ethernet data. It is also used for MII mode data in conjunction with
FECn_TXD[3:1].
O
Collision
FECn_COL
Asserted upon detection of a collision and remains asserted while the
collision persists. This signal is not defined for full-duplex mode.
I
Receive Clock
FECn_RXCLK
Provides a timing reference for FECn_RXDV, FECn_RXD[3:0], and
FECn_RXER.
I
Receive Data Valid
FECn_RXDV
Asserting the receive data valid (FECn_RXDV) input indicates that the
PHY has valid nibbles present on the MII. FECn_RXDV should remain
asserted from the first recovered nibble of the frame through to the last
nibble. Assertion of FECn_RXDV must start no later than the SFD and
exclude any EOF.
I
Receive Data 0
FECn_RXD0
FECn_RXD0 is the Ethernet input data transferred from the PHY to
the media-access controller when FECn_RxDV is asserted. This
signal is used for 10-Mbps Ethernet data. This signal is also used for
MII mode Ethernet data in conjunction with FECn_RXD[3:1].
I
When asserted, indicates that transmit or receive medium is not idle.
Applies to MII mode operation.
I
Transmit Data 1–3
FECn_TXD[3:1] In Ethernet mode, these pins contain the serial output Ethernet data
and are valid only during assertion of FECn_TXEN in MII mode.
O
Transmit Error
FECn_TXER
O
Receive Data 1–3
FECn_RXD[3:1] In Ethernet mode, these pins contain the Ethernet input data
transferred from the PHY to the Media Access Controller when
FECn_RXDV is asserted in MII mode operation.
I
Receive Error
FECn_RXER
I
Carrier Receive Sense FECn_CRS
In Ethernet mode, when FECn_TXER is asserted for one or more
clock cycles while FECn_TXEN is also asserted, the PHY sends one
or more illegal symbols. FECn_TXER has no effect at 10 Mbps or
when FECn_TXEN is negated. Applies to MII mode operation.
In Ethernet mode, FECn_RXER—when asserted with
FECn_RXDV—indicates that the PHY has detected an error in the
current frame. When FECn_RXDV is not asserted FECn_RXER has
no effect. Applies to MII mode operation.
2.3.8 Queued Serial Peripheral Interface (QSPI)
Table 2-9 describes QSPI signals.
MCF5275 Reference Manual, Rev. 2
2-12
Freescale Semiconductor
External Signal Descriptions
Table 2-9. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name
Abbreviation
Function
I/O
QSPI Syncrhonous
Serial Output
QSPI_DOUT
Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK. Each byte is sent
msb first.
O
QSPI Synchronous
Serial Data Input
QSPI_DIN
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK. Each byte is
written to RAM lsb first.
I
QSPI Serial Clock
QSPI_CLK
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable. The output frequency is programmed
according to the following formula, in which n can be any value
between 1 and 255:
SPI_CLK = fsys/2 ÷ n
O
Synchronous Peripheral QSPI_CS[1:0] Provide QSPI peripheral chip selects that can be programmed to be
Chip Selects
active high or low. QSPI_CS1 can also be configured as SDRAM clock
enable signal SD_CKE.
O
2.3.9 I2C I/O SIGNALS
Table 2-10 describes the I2C serial interface module signals.
Table 2-10. I2C I/O Signals
Signal Name
Abbreviation
Function
I/O
Serial Clock
I2C_SCL
Open-drain clock signal for the for the I2C interface. Either it is driven
by the I2C module when the bus is in the master mode or it becomes
the clock input when the I2C is in the slave mode.
I/O
Serial Data
I2C_SDA
Open-drain signal that serves as the data input/output for the I2C
interface.
I/O
2.3.10 UART Module Signals
The UART modules use the signals in this section for data. The baud rate clock inputs are not
supported.
Table 2-11. UART Module Signals
Signal Name
Abbreviation
Function
I/O
Transmit Serial Data
Output
UnTXD
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, lsb first, on this pin at the
falling edge of the serial clock source.
O
Receive Serial Data
Input
UnRXD
Receiver serial data inputs for the UART modules. Data received on
this pin is sampled on the rising edge of the serial clock source lsb
first. When the UART clock is stopped for power-down mode, any
transition on this pin restarts it.
I
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
2-13
Signal Descriptions
Table 2-11. UART Module Signals (Continued)
Signal Name
Abbreviation
Function
I/O
Clear-to-Send
UnCTS
Indicate to the UART modules that they can begin data transmission.
I
Request-to-Send
UnRTS
Automatic request-to-send outputs from the UART modules. UnRTS
can also be configured to be asserted and negated as a function of
the RxFIFO level.
O
2.3.11 USB Signals
Table 2-12 describes the USB serial interface module signals.
Table 2-12. USB Module Signals
Signal Name
Abbreviation
Function
I/O
USB Clock
USB_CLK
This 48MHz (or 6MHz) clock is used by the USB module for both
clock recovery and generation of a 12Mhz (or 1.5MHz) internal bit
clock.
I
USB Speed
USB_SPEED Applications which make use of low speed USB signalling must be
able to switch the USB transceiver between low speed and full speed
operations. Software has control of this function by driving the state
of the USB_SPD bit in the USB_CTRL register onto the
USB_SPEED pin.
USB Received D-
USB_RN
This signal is one half of the differential USB signal, and is extracted
from the USB cable via a single ended input buffer on the analog
front end. This signal is used by the module for detecting the single
ended 0 (SE0) USB bus state.
I
USB Received D+
USB_RP
This signal is one half of the differential USB signal, and is extracted
from the USB cable via a single ended input buffer on the analog
front end. This signal is used by the module for detecting the single
ended 0 (SE0) USB bus state.
I
USB Receive Data
USB_RXD
Input data from the differential input receiver. USB_RXD is the
single-ended data extracted from the USB_RP and USB_RN signals
via a differential input buffer.
I
USB Suspended
USB_SUSP
After a long period of inactivity (3.0ms minimum), the USB will enter
suspend mode, indicated on the interface by an active state on
USB_SUSP. During this mode, the device is supposed to enter a low
power state while waiting for a wake-up from the USB Host. When
the device enters suspend mode, it asserts the suspend signal which
forces the analog front end into a low power state. When the device
leaves suspend mode, USB_SUSP is deasserted, enabling the
analog front end for normal USB operations.
O
USB Transmitted D-
USB_TN
This signal is one half of the differential NRZI formatted output from
the USB module. It is fed to the transmitted D- input of the analog
front end.
O
I/O
MCF5275 Reference Manual, Rev. 2
2-14
Freescale Semiconductor
External Signal Descriptions
Table 2-12. USB Module Signals (Continued)
Signal Name
Abbreviation
Function
I/O
USB Transmitted D+
USB_TP
This signal is one half of the differential NRZI formatted output from
the module. It is fed to the transmitted D+ input of the analog front
end.
O
USB Transmit Enable
USB_TXEN
This signal is an active low output enable for the differential drivers on
the analog front end. When this signal is active, the differential drivers
will drive the USB. When this signal is inactive, the differential drivers
will tristate their outputs.
O
2.3.12 DMA Timer Signals
Table 2-13 describes the signals of the four DMA timer modules.
Table 2-13. DMA Timer Signals
Signal Name
Abbreviation
Function
I/O
DMA Timer 0 Input
DT0IN
Can be programmed to cause events to occur in first platform timer. It
can either clock the event counter or provide a trigger to the timer
value capture logic.
I
DMA Timer 0 Output
DT0OUT
The output from first platform timer.
O
DMA Timer 1 Input
DT1IN
Can be programmed to cause events to occur in the second platform
timer. This can either clock the event counter or provide a trigger to the
timer value capture logic.
I
DMA Timer 1 Output
DT1OUT
The output from the second platform timer.
O
DMA Timer 2 Input
DT2IN
Can be programmed to cause events to occur in the third platform
timer. It can either clock the event counter or provide a trigger to the
timer value capture logic.
I
DMA Timer 2 Output
DT2OUT
The output from the third platform timer.
I
DMA Timer 3 Input
DT3IN
Can be programmed as an input that causes events to occur in the
fourth platform timer. This can either clock the event counter or
provide a trigger to the timer value capture logic.
I
DMA Timer 3 Output
DT3OUT
The output from the fourth platform timer.
O
2.3.13 Pulse Width Modulator Signals
Table 2-14 describes the PWM signals. Note that the primary functions of these pins are DMA
Timer outputs (DTnOUT).
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
2-15
Signal Descriptions
Table 2-14. PWM Signals
Signal Name
Abbreviation
Function
I/O
PWM Output Channel 0 PWM0
Pulse width modulated output for PWM channel 0.
O
PWM Output Channel 1 PWM1
Pulse width modulated output for PWM channel 1.
O
PWM Output Channel 2 PWM2
Pulse width modulated output for PWM channel 2.
O
PWM Output Channel 3 PWM3
Pulse width modulated output for PWM channel 3.
O
2.3.14 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the
BDM logic.
Table 2-15. Debug Support Signals
Signal Name
Abbreviation
Function
I/O
Test Reset
TRST
This active-low signal is used to initialize the JTAG logic
asynchronously.
I
Test Clock
TCLK
Used to synchronize the JTAG logic.
I
Test Mode Select
TMS
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
I
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is three-stateable and
is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
Clocks the serial communication port to the BDM module during
packet transfers.
I
Breakpoint
BKPT
Used to request a manual breakpoint.
I
Development Serial
Input
DSI
This internally-synchronized signal provides data input for the serial
communication port to the BDM module.
I
Development Serial
Output
DSO
This internally-registered signal provides serial output communication
for BDM module responses.
O
Debug Data
DDATA[3:0]
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
O
Processor Status
Outputs
PST[3:0]
Indicate core status, as shown in Table 2-16. Debug mode timing is
synchronous with the processor clock; status is unrelated to the
current bus transfer. The CLKOUT signal can be used by the
development system to know when to sample PST[3:0].
O
PSTCLK indicates when the development systems should sample
PST and DDATA values.
O
Processor Status Clock PSTCLK
MCF5275 Reference Manual, Rev. 2
2-16
Freescale Semiconductor
External Signal Descriptions
Table 2-16. Processor Status
PST[3:0]
Processor Status
0000
Continue execution
0001
Begin execution of one instruction
0010
Reserved
0011
Entry into user mode
0100
Begin execution of PULSE and WDDATA instructions
0101
Begin execution of taken branch
0110
Reserved
0111
Begin execution of RTE instruction
1000
Begin one-byte transfer on DDATA
1001
Begin two-byte transfer on DDATA
1010
Begin three-byte transfer on DDATA
1011
Begin four-byte transfer on DDATA
1100
Exception processing
1101
Reserved
1110
Processor is stopped
1111
Processor is halted
2.3.15 Test Signals
Table 2-17 describes test signals.
Table 2-17. Test Signals
Signal Name
Abbreviation
Function
I/O
Test
TEST
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of test
functions.
I
PLL Test
PLL_TEST
Reserved for factory testing only and should be treated as a
no-connect (NC).
I
2.3.16 Power and Ground Pins
The pins described in Table 2-18 provide system power and ground to the chip. Multiple pins are
provided for adequate current capability. All power supply pins must have adequate bypass
capacitance for high-frequency noise suppression.
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Signal Descriptions
Table 2-18. Power and Ground Pins
Signal Name
Abbreviation
Function
I/O
PLL Analog Supply
VDDPLL,
VSSPLL
Dedicated power supply signals to isolate the sensitive PLL analog
circuitry from the normal levels of noise present on the digital power
supply.
I
Positive Supply
VDDO
These pins supply positive power to the I/O pads.
I
Positive Supply
VDD
These pins supply positive power to the core logic.
I
Ground
VSS
This pin is the negative supply (ground) to the chip.
2.4 External Boot Mode
When booting from external memory, the address bus, data bus, and bus control signals will
default to their bus functionalities as shown in Table 2-19. All other signals will default to GPIO
inputs.
Table 2-19. Default Signal Functions After System Reset (External Boot Mode)
Signal
Reset
I/O
A[23:0]
A[23:0]
O
D[31:16]
—
I/O
BS[3:2]
High
O
OE
High
O
TA
—
I
TEA
—
I
R/W
High
O
SIZ[1:0]
High
O
TS
High
O
TIP
High
O
CS[7:0]
High
O
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Chapter 3
ColdFire Core
This section describes the organization of the Version 2 (V2) ColdFire® processor core and an
overview of the program-visible registers. For detailed information on instructions, see the
ColdFire Family Programmer’s Reference Manual.
3.1
Processor Pipelines
Figure 3-1 is a block diagram showing the processor pipelines of a V2 ColdFire core.
IAG
Instruction
Address
Generation
IC
Instruction
Fetch Cycle
IB
FIFO
Instruction Buffer
Address [31:0]
Instruction
Fetch
Pipeline
Operand
Execution
Pipeline
& Select,
DSOC Decode
Operand Fetch
Read Data[31:0]
Write Data[31:0]
AGEX
Address
Generation,
Execute
Figure 3-1. ColdFire Processor Core Pipelines
The processor core is comprised of two separate pipelines that are decoupled by an instruction
buffer.
The Instruction Fetch Pipeline (IFP) is a two-stage pipeline for prefetching instructions. The
prefetched instruction stream is then gated into the two-stage Operand Execution Pipeline (OEP),
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ColdFire Core
which decodes the instruction, fetches the required operands and then executes the required
function. Since the IFP and OEP pipelines are decoupled by an instruction buffer which serves as
a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP
thereby minimizing time stalled waiting for instructions.
The Instruction Fetch Pipeline consists of two stages with an instruction buffer stage:
•
•
•
Instruction Address Generation (IAG Cycle)
Instruction Fetch Cycle (IC Cycle)
Instruction Buffer (IB Cycle)
When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the
Operand Execution Pipeline. If the buffer is not empty, the IFP stores the contents of the fetch
cycle in the FIFO queue until it is required by the OEP. In the Version 2 implementation, the
instruction buffer contains three 32-bit longwords of storage.
The Operand Execution Pipeline is implemented in a two-stage pipeline featuring a traditional
RISC datapath with a dual-read-ported register file (RGF) feeding an arithmetic/logic unit. In this
design, the pipeline stages have multiple functions:
•
•
Decode & Select/Operand Cycle (DSOC Cycle)
Address Generation/Execute Cycle (AGEX Cycle)
3.2
Processor Register Description
The following paragraphs describe the processor registers in the user and supervisor programming
models. The appropriate programming model is selected based on the privilege level (user mode
or supervisor mode) of the processor as defined by the S bit of the status register (SR).
3.2.1
User Programming Model
Figure 3-2 illustrates the user programming model. The model is the same as the M68000 family
microprocessors, consisting of the following registers:
•
•
•
16 general-purpose 32-bit registers (D0–D7, A0–A7)
32-bit program counter (PC)
8-bit condition code register (CCR)
3.2.1.1
Data Registers (D0–D7)
Registers D0–D7 are used as data registers for bit (1-bit), byte (8-bit), word (16-bit) and longword
(32-bit) operations; they can also be used as index registers.
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Processor Register Description
3.2.1.2
Address Registers (A0–A6)
These registers can be used as software stack pointers, index registers, or base address registers;
they can also be used for word and longword operations.
3.2.1.3
Stack Pointer (A7)
Certain ColdFire implementations, including the MCF5275, support two unique stack pointer
(A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP). This support
provides the required isolation between operating modes of the processor. The SSP is described in
Section 3.2.3.2, “Supervisor/User Stack Pointers (A7 and OTHER_A7).”
A subroutine call saves the PC on the stack and the return restores it from the stack. Both the PC
and the SR are saved on the supervisor stack during the processing of exceptions and interrupts.
The return from exception (RTE) instruction restores the SR and PC values from the supervisor
stack.
3.2.1.4
Program Counter (PC)
The PC contains the address of the currently executing instruction. During instruction execution
and exception processing, the processor automatically increments the contents of the PC or places
a new value in the PC, as appropriate. For some addressing modes, the PC is used as a base address
for PC-relative operand addressing.
31
15
7
0
D0
D1
D2
D3
D4
D5
D6
D7
15
7
Data
Registers
A0
A1
A2
A3
A4
A5
A6
Address
registers
A7
USERStack
Pointer
PC
Program
Counter
CCR
ConditionCode
Register
0
Figure 3-2. User Programming Model
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3.2.1.5
Condition Code Register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. Bit 4, the extend bit (X bit), is also used as an input operand
during multiprecision arithmetic computations.
7
6
5
4
3
2
1
0
Field
0
0
0
X
N
Z
V
C
Reset
0
0
0
0
0
0
0
0
Address
LSB of Status Register (SR)
Figure 3-3. Condition Code Register (CCR)
Table 3-1. CCR Field Descriptions
3.2.2
Bits
Name
Description
7–5
—
Reserved, should be cleared
4
X
Extend condition code bit. Set to the value of the C-bit for arithmetic operations;
otherwise not affected or set to a specified result.
3
N
Negative condition code bit. Set if the most significant bit of the result is set;
otherwise cleared.
2
Z
Zero condition code bit. Set if the result equals zero; otherwise cleared.
1
V
Overflow condition code bit. Set if an arithmetic overflow occurs implying that the
result cannot be represented in the operand size; otherwise cleared.
0
C
Carry condition code bit. Set if a carry out of the operand msb occurs for an
addition, or if a borrow occurs in a subtraction; otherwise cleared
Set to the value of the C bit for arithmetic operations; otherwise not affected.
EMAC Register Description
The registers in the EMAC portion of the user programming model, are described in Chapter 4,
“Enhanced Multiply-Accumulate Unit (EMAC),” and include the following registers:
•
•
•
Four 48-bit accumulator registers partitioned as follows:
— Four 32-bit accumulators (ACC0–ACC3)
— Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into
two 32-bit values for load and store operations (ACCEXT01 and ACCEXT23).
Accumulators and extension bytes can be loaded, copied, and stored, and results from
EMAC arithmetic operations generally affect the entire 48-bit destination.
Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values
for load and store operations (ACCext01 and ACCext23)
One 16-bit mask register (MASK)
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Processor Register Description
•
One 32-bit status register (MACSR) including four indicator bits signaling product or
accumulation overflow (one for each accumulator: PAV0–PAV3)
These registers are shown in Table 3-2.
Table 3-2. EMAC Register Set
31:24
3.2.3
23:16
15:8
7:0
Mnemonic
MAC Status Register
MACSR
MAC Accumulator 0
ACC0
MAC Accumulator 1
ACC1
MAC Accumulator 2
ACC2
MAC Accumulator 3
ACC3
Extensions for ACC0 and ACC1
ACCext01
Extensions for ACC2 and ACC3
ACCext23
MAC Mask Register
MASK
Supervisor Register Description
Only system control software is intended to use the supervisor programming model to implement
restricted operating system functions, I/O control, and memory management. All accesses that
affect the control features of ColdFire processors are in the supervisor programming model, which
consists of registers available in user mode as well as the following control registers:
•
•
•
•
•
•
16-bit status register (SR)
32-bit supervisor stack pointer (SSP)
32-bit vector base register (VBR)
32-bit cache control register (CACR)
Two 32-bit access control registers (ACR0, ACR1)
Two 32-bit base address registers (RAMBAR)
Table 3-3. Supervisor Programming Model
31:24
23:16
—
15:8
7:0
Status Register
Mnemonic
SR
Supervisor/User A7 Stack Pointer
A7
User/Supervisor A7 Stack Pointer
OTHER_A7
Vector Base Register
VBR
Cache Control Register
CACR
Access Control Register 0
ACR0
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ColdFire Core
Table 3-3. Supervisor Programming Model
31:24
23:16
15:8
7:0
Mnemonic
Access Control Register 1
ACR1
RAM Base Address Register
RAMBAR1
The following paragraphs describe the supervisor programming model registers.
3.2.3.1
Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other
control bits. In supervisor mode, software can access the entire SR. In user mode, only the lower
8 bits are accessible (CCR). The control bits indicate the following states for the processor: trace
mode (T bit), supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits
in the SR have read/write access when in supervisor mode.
System Byte
15
14
13
12
11
Field
T
—
S
M
—
Reset
0
0
0
0
0
Condition Code Register (CCR)
10
9
8
7
I
0
Address
6
5
—
0
0
0
0
0
4
3
2
1
0
X
N
Z
V
C
0
0
0
0
0
CPU @ 0x80E
Figure 3-4. Status Register (SR)
Table 3-4. SR Field Descriptions
Bits
Name
Description
15
T
Trace enable. When set, the processor performs a trace exception after every instruction.
14
—
Reserved, should be cleared.
13
S
Supervisor/user state. Denotes whether the processor is in supervisor mode (S = 1) or user
mode (S = 0).
12
M
Master/interrupt state. This bit is cleared by an interrupt exception, and can be set by
software during execution of the RTE or move to SR instructions.
11
—
Reserved, should be cleared.
10–8
I
7–5
—
4–0
CCR
Interrupt level mask. Defines the current interrupt level. Interrupt requests are inhibited for
all priority levels less than or equal to the current level, except the edge-sensitive level 7
request, which cannot be masked.
Reserved, should be cleared.
Refer to Table 3-1.
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Processor Register Description
3.2.3.2
Supervisor/User Stack Pointers (A7 and OTHER_A7)
The MCF5275 architecture supports two independent stack pointer (A7) registers—the supervisor
stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two
programmable-visible 32-bit registers does not identify one as the SSP and the other as the USP.
Instead, the hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus,
the register contents are a function of the processor operation mode, as shown in the following:
if SR[S] = 1
then
A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer
else
A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the
responsibility of the external development system to determine, based on the setting of SR[S], the
mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP). This
functionality is enabled by setting the enable user stack pointer bit, CACR[EUSP]. If this bit is
cleared, only the stack pointer (A7), defined for previous ColdFire versions, is available. EUSP is
zero at reset.
If EUSP is set, the appropriate stack pointer register (SSP or USP) is accessed as a function of the
processor’s operating mode. To support dual stack pointers, the following two privileged M68000
instructions are added to the ColdFire instruction set architecture to load/store the USP:
move.l Ay, USP; move to USP
move.l USP, Ax; move from USP
These instructions are described in the ColdFire Family Programmer’s Reference Manual.
3.2.3.3
Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in memory. To access the vector
table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of
the VBR are not implemented by ColdFire processors; they are assumed to be zero, forcing the
table to be aligned on a 1 MByte boundary.
3.2.3.4
Cache Control Register (CACR)
The CACR controls operation of the instruction/data cache memories. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode
and write-protect fields. The CACR is described in Section 5.2.1.1, “Cache Control Register
(CACR).”
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3.2.3.5
Access Control Registers (ACR0, ACR1)
The access control registers, ACR0 and ACR1, define attributes for two user-defined memory
regions. These attributes include the definition of cache mode, write protect, and buffer write
enables. The ACRs are described in Section 5.2.1.2, “Access Control Registers (ACR0, ACR1).”
3.2.3.6
SRAM Base Address Register (RAMBAR)
The RAMBAR register is used to specify the base address of the internal SRAM and indicate the
types of references mapped to it. The base address register includes a base address, write-protect
bit, address space mask bits, and an enable bit. For more information, refer to Section 6.2.1,
“SRAM Base Address Register (RAMBAR)”.
3.3
Memory Map/Register Definition
Table 3-5 lists register names, the CPU space location, and whether the register is written from the
processor using the MOVEC instruction.
Table 3-5. ColdFire CPU Registers
Name
CPU Space (Rc)
Written with
MOVEC
Register Name
Memory Management Control Registers
CACR
0x002
Yes
Cache control register
ACR0, ACR1
0x004–0x005
Yes
Access control registers 0 and 1
Processor General-Purpose Registers
D0–D7
0x(0,1)80–0x(0,1)87
No
Data registers 0-7 (0 = load, 1 = store)
A0–A7
0x(0,1)88–0x(0,1)8F
No
Address registers 0-7 (0 = load, 1 = store)
A7 is user stack pointer
Processor Miscellaneous Registers
OTHER_A7
0x800
No
Other stack pointer
VBR
0x801
Yes
Vector base register
MACSR
0x804
No
MAC status register
MASK
0x805
No
MAC address mask register
ACC0–ACC3
0x806, 0x809,
0x80A, 0x80B
No
MAC accumulators 0-3
ACCext01
0x807
No
MAC accumulator 0, 1 extension bytes
ACCext23
0x808
No
MAC accumulator 2, 3 extension bytes
SR
0x80E
No
Status register
PC
0x80F
Yes
Program counter
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Additions to the Instruction Set Architecture
Table 3-5. ColdFire CPU Registers (Continued)
Name
CPU Space (Rc)
Written with
MOVEC
Register Name
Local Memory Registers
RAMBAR
3.4
0xC05
Yes
SRAM base address register
Additions to the Instruction Set Architecture
The original ColdFire instruction set architecture (ISA) was derived from the M68000-family
opcodes based on extensive analysis of embedded application code. After the initial ColdFire
compilers were created, developers identified ISA additions that would enhance both code density
and overall performance. Additionally, as users implemented ColdFire-based designs into a wide
range of embedded systems, they identified frequently used instruction sequences that could be
improved by the creation of new instructions. This observation was especially prevalent in
development environments that made use of substantial amounts of assembly language code.
Table 3-6 summarizes the new instructions added to Revision A+ ISA. For more details see
Section 3.14, “ColdFire Instruction Set Architecture Enhancements.”
Table 3-6. ISA Revision A+ New Instructions
Instruction
Description
BITREV
The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0],
new Dx[30] = old Dx[1], ..., new Dx[0] = old Dx[31].
BYTEREV
3.5
The contents of the destination data register are byte-reversed; that is, new Dx[31:24] = old
Dx[7:0], ..., new Dx[7:0] = old Dx[31:24].
FF1
The data register, Dx, is scanned, beginning from the most-significant bit (Dx[31]) and ending
with the least-significant bit (Dx[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.
STLDSR
Pushes the contents of the status register onto the stack and then reloads the status register
with the immediate data value.
Exception Processing Overview
Exception processing for ColdFire processors is streamlined for performance. The ColdFire
processors differ from the M68000 family in that they include:
•
•
•
•
A simplified exception vector table
Reduced relocation capabilities using the vector base register
A single exception stack frame format
Use of a single self-aligning system stack
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ColdFire Core
All ColdFire processors use an instruction restart exception model, but certain microarchitectures
(V2 and V3) require more software support to recover from certain access errors. See
Section 3.7.1, “Access Error Exception” for details.
Exception processing includes all actions from the detection of the fault condition to the initiation
of fetch for the first handler instruction. Exception processing is comprised of four major steps
First, the processor makes an internal copy of the SR and then enters supervisor mode by asserting
the S bit and disabling trace mode by negating the T bit. The occurrence of an interrupt exception
also forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current
interrupt request.
Second, the processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on the exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller. The IACK cycle is mapped to a special acknowledge address space with the
interrupt level encoded in the address.
Third, the processor saves the current context by creating an exception stack frame on the
supervisor system stack. As a result, the exception stack frame is created at a 0-modulo-4 address
on the top of the current system stack. Additionally, the processor uses a simplified fixed-length
stack frame for all exceptions. The exception type determines whether the program counter placed
in the exception stack frame defines the location of the faulting instruction (fault) or the address
of the next instruction to be executed (next).
Fourth, the processor calculates the address of the first instruction of the exception handler. By
definition, the exception vector table is aligned on a 1 Mbyte boundary. This instruction address
is generated by fetching an exception vector from the table located at the address defined in the
vector base register. The index into the exception table is calculated as (4 x vector number). Once
the exception vector has been fetched, the contents of the vector determine the address of the first
instruction of the desired handler. After the instruction fetch for the first opcode of the handler has
been initiated, exception processing terminates and normal instruction processing continues in the
handler.
All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address
boundary (see Table 3-7). The table contains 256 exception vectors; the first 64 are defined by
Freescale and the remaining 192 are user-defined interrupt vectors.
Table 3-7. Exception Vector Assignments
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
0
0x000
—
Initial stack pointer
1
0x004
—
Initial program counter
2
0x008
Fault
Access error
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Exception Stack Frame Definition
Table 3-7. Exception Vector Assignments (Continued)
Vector
Number(s)
Vector
Offset (Hex)
Stacked
Program
Counter
Assignment
3
0x00C
Fault
Address error
4
0x010
Fault
Illegal instruction
5
0x014
Fault
Divide by zero
6–7
0x018–0x01C
—
Reserved
8
0x020
Fault
Privilege violation
9
0x024
Next
Trace
10
0x028
Fault
Unimplemented line-a opcode
11
0x02C
Fault
Unimplemented line-f opcode
12
0x030
Next
Debug interrupt
13
0x034
—
Reserved
14
0x038
Fault
Format error
15–23
0x03C–0x05C
—
Reserved
24
0x060
Next
Spurious interrupt
25–31
0x064–0x07C
—
Reserved
32–47
0x080–0x0BC
Next
Trap # 0-15 instructions
48–63
0x0C0–0x0FC
—
Reserved
64–255
0x100–0x3FC
Next
User-defined interrupts
“Fault” refers to the PC of the instruction that caused the exception; “Next” refers to the
PC of the next instruction that follows the instruction that caused the fault.
All ColdFire processors inhibit interrupt sampling during the first instruction of all exception
handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the
interrupt mask level contained in the status register. In addition, the V2 core includes a new
instruction (STLDSR) that stores the current interrupt mask level and loads a value into the SR.
This instruction is specifically intended for use as the first instruction of an interrupt service
routine which services multiple interrupt requests with different interrupt levels. For more details
see Section 3.14, “ColdFire Instruction Set Architecture Enhancements.”
3.6
Exception Stack Frame Definition
The exception stack frame is shown in Figure 3-5. The first longword of the exception stack frame
contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the second
longword contains the 32-bit program counter address.
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ColdFire Core
31
SSP
27
FORMAT
17
25
FS[3:2]
+ 0x4
VECTOR[7:0]
0
15
FS[1:0]
Status Register
Program Counter[31:0]
Figure 3-5. Exception Stack Frame Form
The 16-bit format/vector word contains 3 unique fields:
•
A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6,
or 7 by the processor indicating a two-longword frame format. See Table 3-8.
Table 3-8. Format Field Encodings
•
Original SSP @ Time
of Exception, Bits 1:0
SSP @ 1st
Instruction of
Handler
Format Field
00
Original SSP - 8
4
01
Original SSP - 9
5
10
Original SSP - 10
6
11
Original SSP - 11
7
There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined
for access and address errors only and written as zeros for all other types of exceptions. See
Table 3-9.
Table 3-9. Fault Status Encodings
•
FS[3:0]
Definition
00xx
Reserved
0100
Error on instruction fetch
0101
Reserved
011x
Reserved
1000
Error on operand write
1001
Attempted write to write-protected space
101x
Reserved
1100
Error on operand read
1101
Reserved
111x
Reserved
The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the
processor for all internal faults and represents the value supplied by the interrupt controller
in the case of an interrupt. Refer to Table 3-7.
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Processor Exceptions
3.7
3.7.1
Processor Exceptions
Access Error Exception
The exact processor response to an access error depends on the type of memory reference being
performed. For an instruction fetch, the processor postpones the error reporting until the faulted
reference is needed by an instruction for execution. Therefore, faults that occur during instruction
prefetches that are then followed by a change of instruction flow do not generate an exception.
When the processor attempts to execute an instruction with a faulted opword and/or extension
words, the access error is signaled and the instruction aborted. For this type of exception, the
programming model has not been altered by the instruction generating the access error.
If the access error occurs on an operand read, the processor immediately aborts the current
instruction’s execution and initiates exception processing. In this situation, any address register
updates attributable to the auto-addressing modes, (for example, (An)+,-(An)), have already been
performed, so the programming model contains the updated An value. In addition, if an access
error occurs during the execution of a MOVEM instruction loading from memory, any registers
already updated before the fault occurs contain the operands from memory.
The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand
writes. Because the actual write cycle may be decoupled from the processor’s issuing of the
operation, the signaling of an access error appears to be decoupled from the instruction that
generated the write. Accordingly, the PC contained in the exception stack frame merely represents
the location in the program when the access error was signaled. All programming model updates
associated with the write instruction are completed. The NOP instruction can collect access errors
for writes. This instruction delays its execution until all previous operations, including all pending
write operations, are complete. If any previous write terminates with an access error, it is
guaranteed to be reported on the NOP instruction.
3.7.2
Address Error Exception
Any attempted execution transferring control to an odd instruction address (that is, if bit 0 of the
target address is set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of 8 on an indexed
effective addressing mode generates an address error as does an attempted execution of a
full-format indexed addressing mode.
3.7.3
Illegal Instruction Exception
Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes)
generates an illegal instruction exception (vector 4). Additionally, any attempted execution of any
non-MAC line-A and most line-F opcode generates their unique exception types, vector numbers
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ColdFire Core
10 and 11, respectively. The V2 core does not provide illegal instruction detection on the extension
words on any instruction, including MOVEC.
3.7.4
Divide-By-Zero
Attempting to divide by zero causes an exception (vector 5, offset = 0x014).
3.7.5
Privilege Violation
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. See the ColdFire Programmer’s Reference Manual for lists of supervisor- and
user-mode instructions.
3.7.6
Trace Exception
To aid in program development, all ColdFire processors provide an instruction-by-instruction
tracing capability. While in trace mode, indicated by the assertion of the T-bit in the status register
(SR[15] = 1), the completion of an instruction execution (for all but the STOP instruction) signals
a trace exception. This functionality allows a debugger to monitor program execution.
The STOP instruction has the following effects:
1. The instruction before the STOP executes and then generates a trace exception. In the
exception stack frame, the PC points to the STOP opcode.
2. When the trace handler is exited, the STOP instruction is executed, loading the SR with
the immediate operand from the instruction.
3. The processor then generates a trace exception. The PC in the exception stack frame
points to the instruction after the STOP, and the SR reflects the value loaded in the
previous step.
If the processor is not in trace mode and executes a STOP instruction where the immediate operand
sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack
frame points to the instruction after the STOP, and the SR reflects the value loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception
types. As an example, consider the execution of a TRAP instruction while in trace mode. The
processor will initiate the TRAP exception and then pass control to the corresponding handler. If
the system requires that a trace exception be processed, it is the responsibility of the TRAP
exception handler to check for this condition (SR[15] in the exception stack frame asserted) and
pass control to the trace handler before returning from the original exception.
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Processor Exceptions
3.7.7
Unimplemented Line-A Opcode
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated
by the attempted execution of an undefined line-A opcode.
3.7.8
Unimplemented Line-F Opcode
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated
by attempted execution of an undefined line-F opcode.
3.7.9
Debug Interrupt
This special type of program interrupt is discussed in detail in Chapter 32, “Debug Support.” This
exception is generated in response to a hardware breakpoint register trigger. The processor does
not generate an IACK cycle but rather calculates the vector number internally (vector number 12).
3.7.10 RTE and Format Error Exception
When an RTE instruction is executed, the processor first examines the 4-bit format field to validate
the frame type. For a ColdFire core, any attempted RTE execution where the format is not equal
to {4,5,6,7} generates a format error. The exception stack frame for the format error is created
without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code from
M68000 applications. On M68000 family processors, the SR was located at the top of the stack.
On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero.
Thus, if an RTE is attempted using this “old” format, it generates a format error on a ColdFire
processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the
second longword operand, (3) adjusts the stack pointer by adding the format value to the
auto-incremented address after the fetch of the first longword, and then (4) transfers control to the
instruction address defined by the second longword operand within the stack frame.
3.7.11 TRAP Instruction Exception
The TRAP #n instruction always forces an exception as part of its execution and is useful for
implementing system calls.
3.7.12 Interrupt Exception
Interrupt exception processing includes interrupt recognition and the fetch of the appropriate
vector from the interrupt controller using an IACK cycle. See Chapter 13, “Interrupt Controller
Modules,” for details on the interrupt controller.
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ColdFire Core
3.7.13 Fault-on-Fault Halt
If a ColdFire processor encounters any type of fault during the exception processing of another
fault, the processor immediately halts execution with the catastrophic “fault-on-fault” condition.
A reset is required to force the processor to exit this halted state.
3.7.14 Reset Exception
Asserting the reset input signal to the processor causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from
catastrophic failure. Reset also aborts any processing in progress when the reset input is
recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the S-bit and disables
tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets the processor’s
interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero
(0x00000000). The control registers specifying the operation of any memories (e.g., cache and/or
RAM modules) connected directly to the processor are disabled.
NOTE
Other implementation-specific supervisor registers are also affected.
Refer to each of the modules in this user’s manual for details on these
registers.
Once the processor is granted the bus, it then performs two longword read bus cycles. The first
longword at address 0 is loaded into the stack pointer and the second longword at address 4 is
loaded into the program counter. After the initial instruction is fetched from memory, program
execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault halted state.
ColdFire processors load hardware configuration information into the D0 and D1 general-purpose
registers after system reset. The hardware configuration information is loaded immediately after
the reset-in signal is negated. This allows an emulator to read out the contents of these registers
via BDM to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in Figure 3-6.
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Processor Exceptions
31
30
29
28
R
27
26
25
24
23
22
PF
21
20
19
18
VER
17
16
REV
W
Reset
1
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R MAC
DIV EMAC FPU MMU
—
ISA
DEBUG
W
Reset
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
Figure 3-6. D0 Hardware Configuration Info
Table 3-10. D0 Hardware Configuration Info Field Description
Bits
Name
Description
31–24
PF
23–20
VER
ColdFire core version number. This field is fixed to a hex value of 0x2 indicating a Version
2 ColdFire core.
19–16
REV
Processor revision number.
15
MAC
MAC execute engine status.
0 MAC execute engine not present in core. (This is the value used for MCF5275 .)
1 MAC execute engine is present in core.
14
DIV
Divide execute engine status.
0 Divide execute engine not present in core.
1 Divide execute engine is present in core. (This is the value used for MCF5275 .)
13
EMAC
EMAC execute engine status.
0 EMAC execute engine not present in core.
1 EMAC execute engine is present in core. (This is the value used for MCF5275)
12
FPU
FPU execute engine status.
0 FPU execute engine not present in core. (This is the value used for MCF5275)
1 FPU execute engine is present in core.
11
MMU
Virtual memory management unit status.
0 MMU execute engine not present in core. (This is the value used for MCF5275)
1 MMU execute engine is present in core.
10–8
—
Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is
present.
Reserved.
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ColdFire Core
Table 3-10. D0 Hardware Configuration Info Field Description (Continued)
Bits
Name
7–4
ISA
3–0
DEBUG
Description
Instruction set architecture (ISA) revision number.
0000 ISA_A
0001 ISA_B
0010 ISA_C
1000 ISA_A+ (ISA_A with the addition of the BYTEREV, BITREV, FF1, and STLDSR
instructions. This is the value used for MCF5275.)
0011-1111 Reserved.
Debug module revision number.
0000 DEBUG_A (This is the value used for MCF5275)
0001 DEBUG_B
0010 DEBUG_C
0011 DEBUG_D
0100 DEBUG_E
0101–1111 Reserved.
Information loaded into D1 defines the local memory hardware configuration as shown in
Figure 3-7.
31
R
30
29
CL
28
27
ICA
26
25
24
23
22
21
20
ICSIZ
19
18
17
16
—
W
Reset
R
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BUSW
DCA
DCSIZ
RAM1SIZ
ROM1SIZ
W
Reset
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
Figure 3-7. D1 Hardware Configuration Info
Table 3-11. D1 Local Memory Hardware Configuration Information Field Description
Bits
Name
Description
31–30
CL
Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.
29–28
ICA
Instruction cache associativity.
00 Four-way.
01 Direct mapped. (This is the value used for MCF5275)
27–24
ICSIZ
23–16
—
15–14
BUSW
Instruction cache size.
0101 8KB instruction cache. (This is the value used for MCF5275)
All other values do not apply for MCF5275.
Reserved for MCF5275.
Encoded bus data width.
00 32-bit data bus (only configuration currently in use).
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Instruction Execution Timing
Table 3-11. D1 Local Memory Hardware Configuration Information Field Description
Bits
Name
13–12
DCA
11–8
DCSIZ
7–4
RAM1SIZ
RAM bank 1 size.
1000 64KB RAM. (This is the value used for MCF5275)
All other values do not apply for MCF5275.
3–0
ROM1SIZ
ROM bank 1 size.
0x0–0x3 No ROM. (This is the value used for MCF5275)
All other values do not apply for MCF5275.
3.8
Description
Data cache associativity.
00 Four-way.
01 Direct mapped. (This is the value used for MCF5275)
Data cache size.
0000 No data cache. (This is the value used for MCF5275)
All other values do not apply for MCF5275.
Instruction Execution Timing
This section presents V2 processor instruction execution times in terms of processor core clock
cycles. The number of operand references for each instruction is enclosed in parentheses following
the number of processor clock cycles. Each timing entry is presented as C(R/W) where:
•
•
C is the number of processor clock cycles, including all applicable operand fetches and
writes, and all internal core cycles required to complete the instruction execution.
R/W is the number of operand reads (R) and writes (W) required by the instruction. An
operation performing a read-modify-write function is denoted as (1/1).
This section includes the assumptions concerning the timing values and the execution time details.
3.8.1
Timing Assumptions
For the timing data presented in this section, the following assumptions apply:
1. The operand execution pipeline (OEP) is loaded with the opword and all required extension
words at the beginning of each instruction execution. This implies that the OEP does not
wait for the instruction fetch pipeline (IFP) to supply opwords and/or extension words.
2. The OEP does not experience any sequence-related pipeline stalls. For V2 ColdFire
processors, the most common example of this type of stall involves consecutive store
operations, excluding the MOVEM instruction. For all STORE operations (except
MOVEM), certain hardware resources within the processor are marked as “busy” for two
processor clock cycles after the final DSOC cycle of the store instruction. If a subsequent
STORE instruction is encountered within this 2-cycle window, it will be stalled until the
resource again becomes available. Thus, the maximum pipeline stall involving
consecutive STORE operations is 2 cycles. The MOVEM instruction uses a different set
of resources and this stall does not apply.
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ColdFire Core
3. The OEP completes all memory accesses without any stall conditions caused by the
memory itself. Thus, the timing details provided in this section assume that an infinite
zero-wait state memory is attached to the processor core.
4. All operand data accesses are aligned on the same byte boundary as the operand size: that
is, 16 bit operands aligned on 0-modulo-2 addresses and 32 bit operands aligned on
0-modulo-4 addresses.
If the operand alignment fails these guidelines, it is misaligned. The processor core decomposes
the misaligned operand reference into a series of aligned accesses as shown in Table 3-12.
Table 3-12. Misaligned Operand References
3.8.2
Address[1:0]
Size
Kbus
Operations
Additional
C(R/W)
X1
Word
Byte, Byte
2(1/0) if read
1(0/1) if write
X1
Long
Byte, Word,
Byte
3(2/0) if read
2(0/2) if write
10
Long
Word, Word
2(1/0) if read
1(0/1) if write
MOVE Instruction Execution Times
The execution times for the MOVE.{B,W} instructions are shown in Table 3-13, while Table 3-14
provides the timing for MOVE.L.
For all tables in this section, the execution time of any instruction using the PC-relative effective
addressing modes is the same for the comparable An-relative mode.
The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l.
Table 3-13. Move Byte and Word Execution Times
Destination
Source
Rx
(Ax)
(Ax)+
-(Ax)
(d16,Ax)
(d8,Ax,Xi)
(xxx).wl
Dn
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
An
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
(An)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
(An)+
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
-(An)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
(d16,An)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
—
—
(d8,An,Xi)
4(1/0)
4(1/1)
4(1/1)
4(1/1)
—
—
—
(xxx).w
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
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Standard One Operand Instruction Execution Times
Table 3-13. Move Byte and Word Execution Times (Continued)
Destination
Source
Rx
(Ax)
(Ax)+
-(Ax)
(d16,Ax)
(d8,Ax,Xi)
(xxx).wl
(xxx).l
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
(d16,PC)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
—
—
(d8,PC,Xi)
4(1/0)
4(1/1)
4(1/1)
4(1/1)
—
—
—
#<xxx>
1(0/0)
3(0/1)
3(0/1)
3(0/1)
—
—
—
Table 3-14. Move Long Execution Times
Destination
Source
Rx
(Ax)
(Ax)+
-(Ax)
(d16,Ax)
(d8,Ax,Xi)
(xxx).wl
Dn
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
An
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
(An)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
(An)+
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
-(An)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
(d16,An)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,An,Xi)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
(xxx).w
2(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
(xxx).l
2(1/0)
2(1/1)
2(1/1)
2(1/1)
—
—
—
(d16,PC)
2(1/0)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
—
—
(d8,PC,Xi)
3(1/0)
3(1/1)
3(1/1)
3(1/1)
—
—
—
#<xxx>
1(0/0)
2(0/1)
2(0/1)
2(0/1)
—
—
—
3.9
Standard One Operand Instruction Execution Times
Table 3-15. One Operand Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn*SF)
xxx.wl
#xxx
bitrev
Dx
1(0/0)
—
—
—
—
—
—
—
byterev
Dx
1(0/0)
—
—
—
—
—
—
—
clr.b
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
clr.w
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
clr.l
<ea>
1(0/0)
1(0/1)
1(0/1)
1(0/1)
1(0/1)
2(0/1)
1(0/1)
—
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ColdFire Core
Table 3-15. One Operand Instruction Execution Times (Continued)
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn*SF)
xxx.wl
#xxx
ext.w
Dx
1(0/0)
—
—
—
—
—
—
—
ext.l
Dx
1(0/0)
—
—
—
—
—
—
—
extb.l
Dx
1(0/0)
—
—
—
—
—
—
—
ff1
Dx
1(0/0)
—
—
—
—
—
—
—
neg.l
Dx
1(0/0)
—
—
—
—
—
—
—
negx.l
Dx
1(0/0)
—
—
—
—
—
—
—
not.l
Dx
1(0/0)
—
—
—
—
—
—
—
scc
Dx
1(0/0)
—
—
—
—
—
—
—
stldsr
#imm
—
—
—
—
—
—
—
5(0/1)
swap
Dx
1(0/0)
—
—
—
—
—
—
—
tst.b
<ea>
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
tst.w
<ea>
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
tst.l
<ea>
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
1(0/0)
3.10 Standard Two Operand Instruction Execution Times
Table 3-16. Two Operand Instruction Execution Times
Effective Address
Opcode
<EA>
add.l
(d16,An) (d8,An,Xn*SF)
(d16,PC) (d8,PC,Xn*SF)
Rn
(An)
(An)+
-(An)
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
add.l
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
addi.l
#imm,Dx
1(0/0)
—
—
addq.l
#imm,<ea>
1(0/0)
3(1/1)
addx.l
Dy,Dx
1(0/0)
and.l
<ea>,Rx
and.l
xxx.wl
#xxx
4(1/0)
3(1/0)
1(0/0)
3(1/1)
4(1/1)
3(1/1)
—
—
—
—
—
—
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
—
—
—
—
—
—
—
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
andi.l
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
asl.l
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
asr.l
<ea>,Dx
1(0/0)
—
—
—
—
—
—
1(0/0)
bchg
Dy,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
5(1/1)
4(1/1)
—
bchg
#imm,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
—
—
—
bclr
Dy,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
5(1/1)
4(1/1)
—
bclr
#imm,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
4(1/1)
—
—
—
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Standard Two Operand Instruction Execution Times
Table 3-16. Two Operand Instruction Execution Times (Continued)
Effective Address
1
Opcode
<EA>
bset
(d16,An) (d8,An,Xn*SF)
(d16,PC) (d8,PC,Xn*SF)
Rn
(An)
(An)+
-(An)
Dy,<ea>
2(0/0)
4(1/1)
41/1)
4(1/1)
4(1/1)
bset
#imm,<ea>
2(0/0)
4(1/1)
4(1/1)
4(1/1)
btst
Dy,<ea>
2(0/0)
3(1/1)
3(1/1)
btst
#imm,<ea>
1(0/0)
3(1/1)
cmp.l
<ea>,Rx
1(0/0)
cmpi.l
#imm,Dx
divs.w1
divu.w1
divs.l1
divu.l1
eor.l
Dy,<ea>
1(0/0)
3(1/1)
3(1/1)
3(1/1)
eori.l
#imm,Dx
1(0/0)
—
—
lea
<ea>,Ax
—
1(0/0)
lsl.l
<ea>,Dx
1(0/0)
lsr.l
<ea>,Dx
moveq
xxx.wl
#xxx
5(1/1)
4(1/1)
—
4(1/1)
—
—
—
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
3(1/1)
3(1/1)
3(1/1)
—
—
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
1(0/0)
—
—
—
—
—
—
—
<ea>,Dx
20(0/0)
23(1/0)
23(1/0)
23(1/0)
23(1/0)
24(1/0)
23(1/0)
20(0/0)
<ea>,Dx
20(0/0)
23(1/0)
23(1/0)
23(1/0)
23(1/0)
24(1/0)
23(1/0)
20(0/0)
<ea>,Dx
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
—
—
—
<ea>,Dx
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
—
—
—
3(1/1)
4(1/1)
3(1/1)
—
—
—
—
—
—
—
—
1(0/0)
2(0/0)
1(0/0)
—
—
—
—
—
—
—
1(0/0)
1(0/0)
—
—
—
—
—
—
1(0/0)
#imm,Dx
—
—
—
—
—
—
—
1(0/0)
muls.w
<ea>y, Dx
4(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
7(1/0)
6(1/0)
4(1/0)
mulu.w
<ea>y, Dx
4(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
7(1/0)
6(1/0)
4(1/0)
muls.l
<ea>y, Dx
4(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
—
—
—
mulu.l
<ea>y, Dx
4(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
—
—
—
or.l
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
or.l
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
ori.l
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
rems.l1
<ea>,Dx
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
—
—
—
1
remu.l
<ea>,Dx
≤35(0/0) ≤38(1/0) ≤38(1/0) ≤38(1/0) ≤38(1/0)
—
—
—
sub.l
<ea>,Rx
1(0/0)
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
1(0/0)
sub.l
Dy,<ea>
—
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
subi.l
#imm,Dx
1(0/0)
—
—
—
—
—
—
—
subq.l
#imm,<ea>
1(0/0)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
—
subx.l
Dy,Dx
1(0/0)
—
—
—
—
—
—
—
For divide and remainder instructions the times listed represent the worst-case timing. Depending on the operand
values, the actual execution time may be less.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
3-23
ColdFire Core
3.11 Miscellaneous Instruction Execution Times
Table 3-17. Miscellaneous Instruction Execution Times
Effective Address
Opcode
<EA>
link.w
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,Xn*SF
)
xxx.wl
#xxx
Ay,#imm
2(0/1)
—
—
—
—
—
—
—
move.w
CCR,Dx
1(0/0)
—
—
—
—
—
—
—
move.w
<ea>,CC
R
1(0/0)
—
—
—
—
—
—
1(0/0)
move.w
SR,Dx
1(0/0)
—
—
—
—
—
—
—
move.w
<ea>,SR
7(0/0)
—
—
—
—
—
—
7(0/0) 2
movec
Ry,Rc
9(0/1)
—
—
—
—
—
—
—
movem.l
<ea>,&list
—
1+n(n/0)
—
—
1+n(n/0)
—
—
—
movem.l
&list,<ea>
—
1+n(0/n)
—
—
1+n(0/n)
—
—
—
3(0/0)
—
—
—
—
—
—
—
2(0/1)
—
nop
pea
<ea>
pulse
2(0/1)
4
5
—
2(0/1)
—
—
1(0/0)
—
—
—
—
—
—
—
3(0/1)
stop
#imm
—
—
—
—
—
—
—
3(0/0) 3
trap
#imm
—
—
—
—
—
—
—
15(1/2)
trapf
1(0/0)
—
—
—
—
—
—
—
trapf.w
1(0/0)
—
—
—
—
—
—
—
trapf.l
1(0/0)
—
—
—
—
—
—
—
unlk
Ax
2(1/0)
—
—
—
—
—
—
—
wddata
<ea>
—
3(1/0)
3(1/0)
3(1/0)
3(1/0)
4(1/0)
3(1/0)
3(1/0)
wdebug
<ea>
—
5(2/0)
—
—
5(2/0)
—
—
—
1n
is the number of registers moved by the MOVEM opcode.
a MOVE.W #imm,SR instruction is executed and imm[13] = 1, the execution time is 1(0/0).
3The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
4
PEA execution times are the same for (d16,PC).
5 PEA execution times are the same for (d8,PC,Xn*SF).
2If
3.12 EMAC Instruction Execution Times
Table 3-18. EMAC Instruction Execution Times
Effective Address
Opcode
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,X
n*SF)
xxx.wl
#xxx
muls.w
<ea>y, Dx
4(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
7(1/0)
6(1/0)
4(1/0)
mulu.w
<ea>y, Dx
4(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
7(1/0)
6(1/0)
4(1/0)
MCF5275 Reference Manual, Rev. 2
3-24
Freescale Semiconductor
EMAC Instruction Execution Times
Table 3-18. EMAC Instruction Execution Times (Continued)
Effective Address
Opcode
1
2
<EA>
Rn
(An)
(An)+
-(An)
(d16,An)
(d8,An,X
n*SF)
xxx.wl
#xxx
muls.l
<ea>y, Dx
4(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
—
—
—
mulu.l
<ea>y, Dx
4(0/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
—
—
—
mac.w
Ry, Rx, Raccx
1(0/0)
—
—
—
—
—
—
—
mac.l
Ry, Rx, Raccx
1(0/0)
—
—
—
—
—
—
—
msac.w
Ry, Rx, Raccx
1(0/0)
—
—
—
—
—
—
—
msac.l
Ry, Rx, Raccx
1(0/0)
—
—
—
—
—
—
—
1
—
—
—
mac.w
Ry, Rx, <ea>, Rw,
Raccx
—
2(1/0)
2(1/0)
2(1/0)
2(1/0)
mac.l
Ry, Rx, <ea>, Rw,
Raccx
—
2(1/0)
2(1/0)
2(1/0)
2(1/0)1
—
—
—
msac.w
Ry, Rx, <ea>, Rw
—
2(1/0)
2(1/0)
2(1/0)
2(1/0)1
—
—
—
—
—
—
msac.l
Ry, Rx, <ea>, Rw,
Raccx
—
2(1/0)
2(1/0)
2(1/0)
2(1/0)1
mov.l
<ea>y, Raccx
1(0/0)
—
—
—
—
—
—
1(0/0)
mov.l
Raccy,Raccx
1(0/0)
—
—
—
—
—
—
—
mov.l
<ea>y, MACSR
5(0/0)
—
—
—
—
—
—
5(0/0)
mov.l
<ea>y, Rmask
4(0/0)
—
—
—
—
—
—
4(0/0)
mov.l
<ea>y,Raccext01
1(0/0)
—
—
—
—
—
—
1(0/0)
mov.l
<ea>y,Raccext23
1(0/0)
—
—
—
—
—
—
1(0/0)
mov.l
Raccx,<ea>x
1(0/0)2
—
—
—
—
—
—
—
mov.l
MACSR,<ea>x
1(0/0)
—
—
—
—
—
—
—
mov.l
Rmask, <ea>x
1(0/0)
—
—
—
—
—
—
—
mov.l
Raccext01,<ea.x
1(0/0)
—
—
—
—
—
—
—
mov.l
Raccext23,<ea>x
1(0/0)
—
—
—
—
—
—
—
Effective address of (d16,PC) not supported
Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional
rounding is performed (MACSR[7:4] = 1---, -11-, --11)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
3-25
ColdFire Core
NOTE
The execution times for moving the contents of the Racc,
Raccext[01,23], MACSR, or Rmask into a destination location <ea>x
shown in this table represent the best-case scenario when the store
instruction is executed and there are no load or M{S}AC instructions
in the EMAC execution pipeline. In general, these store operations
require only a single cycle for execution, but if preceded immediately
by a load, MAC, or MSAC instruction, the depth of the EMAC
pipeline is exposed and the execution time is four cycles.
3.13 Branch Instruction Execution Times
Table 3-19. General Branch Instruction Execution Times
Effective Address
Opcod
e
<EA>
bsr
Rn
(An)
(An)+
-(An)
(d16,An)
(d16,PC)
(d8,An,Xi*SF)
(d8,PC,Xi*SF)
xxx.wl
#xxx
—
—
—
—
3(0/1)
—
—
—
jmp
<ea>
—
3(0/0)
—
—
3(0/0)
4(0/0)
3(0/0)
—
jsr
<ea>
—
3(0/1)
—
—
3(0/1)
4(0/1)
3(0/1)
—
rte
—
—
10(2/0)
—
—
—
—
—
rts
—
—
5(1/0)
—
—
—
—
—
Table 3-20. BRA, Bcc Instruction Execution Times
Opcode
Forward
Taken
Forward
Not Taken
Backward
Taken
Backward
Not Taken
bra
2(0/0)
—
2(0/0)
—
bcc
3(0/0)
1(0/0)
2(0/0)
3(0/0)
3.14 ColdFire Instruction Set Architecture Enhancements
This section describes the new opcodes implemented as part of the Revision A+ enhancements to
the basic ColdFire ISA.
MCF5275 Reference Manual, Rev. 2
3-26
Freescale Semiconductor
ColdFire Instruction Set Architecture Enhancements
BITREV
BITREV
Bit Reverse Register
(Supported Starting with ISA A+)
Operation:
Bit Reversed Dx → Dx
Assembler Syntax:
BITREV.L Dx
Attributes:
Size = longword
Instruction
Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
1
1
0
0
0
2
1
0
Register, Dx
The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0], new
Dx[30] = old Dx[1], ..., new Dx[0] = old Dx[31].
Condition Codes:
Not affected
Instruction Field:
•
Register field—Specifies the destination data register, Dx.
BITREV
V2, V3 Core (ISA_A)
V4 Core (ISA_B)
V2 Core (ISA_A+)
Opcode present
No
No
Yes
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
3-27
ColdFire Core
BYTEREV
BYTEREV
Byte Reverse Register
(Supported Starting with ISA A+)
Operation:
Byte Reversed Dx → Dx
Assembler Syntax:
BYTEREV.L Dx
Attributes:
Size = longword
Instruction
Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
1
0
1
1
0
0
0
2
1
0
Register, Dx
The contents of the destination data register are byte-reversed as defined below:
Condition Codes:
new Dx[31:24]
= old Dx[7:0]
new Dx[23:16]
= old Dx[15:8]
new Dx[15:8]
= old Dx[23:16]
new Dx[7:0]
= old Dx[31:24]
Not affected
Instruction Field:
•
Register field—Specifies the destination data register, Dx.
BYTEREV
V2, V3 Core (ISA_A)
V4 Core (ISA_B)
V2 Core (ISA_A+)
Opcode present
No
No
Yes
MCF5275 Reference Manual, Rev. 2
3-28
Freescale Semiconductor
ColdFire Instruction Set Architecture Enhancements
FF1
FF1
Find First One in Register
(Supported Starting with ISA A+)
Operation:
Bit Offset of the First Logical One in Register → Destination
Assembler Syntax:
FF1.L Dx
Attributes:
Size = longword
Instruction
Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
1
0
0
1
1
0
0
0
2
1
0
Destination
Register, Dx
The data register, Dx, is scanned, beginning from the most-significant bit (Dx[31]) and ending
with the least-significant bit (Dx[0]), searching for the first set bit. The data register is then loaded
with the offset count from bit 31 where the first set bit appears, as shown below. If the source
data is zero, then an offset of 32 is returned.
Condition
Codes:
X
—
N
∗
Z
∗
Old Dx[31:0]
New Dx[31:0]
0b1---- . . . ----
0x0000 0000
0b01--- . . . ----
0x0000 0001
0b001-- . . . ----
0x0000 0002
...
...
0b00000 . . . 0010
0x0000 001E
0b00000 . . . 0001
0x0000 001F
0b00000 . . . 0000
0x0000 0020
V
0
C
0
X Not affected
N Set if the msb of the source operand is set; cleared
otherwise
Z Set if the source operand is zero; cleared otherwise
V Always cleared
C Always cleared
Instruction Field:
•
Destination Register field—Specifies the destination data register, Dx.
FF1
V2, V3 Core (ISA_A)
V4 Core (ISA_B)
V2 Core (ISA_A+)
Opcode present
No
No
Yes
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
3-29
ColdFire Core
STRLDSR
STRLDSR
Store/Load Status Register
(Supported Starting with ISA A+)
Operation:
If Supervisor State
Then SP - 4 → SP; zero-filled SR → (SP); immediate data → SR
Else TRAP
Assembler Syntax:STRLDSR #<data>
Attributes:
Size = word
Instruction
Format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
1
0
0
0
1
1
0
1
1
1
1
1
1
0
0
Immediate Data
Description: Pushes the contents of the Status Register onto the stack and then reloads the
Status Register with the immediate data value. This instruction is intended for use as the first
instruction of an interrupt service routine shared across multiple interrupt request levels. It allows
the level of the just-taken interrupt request to be stored in memory (using the SR[IML] field), and
then masks interrupts by loading the SR[IML] field with 0x7 (if desired). If execution is attempted
with bit 13 of the immediate data cleared (attempting to place the processor in user mode), a
privilege violation exception is generated. The opcode for STRLDSR is 0x40E7 46FC.
Condition
Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X
N
Z
V
C
Set to the value of bit 4 of the immediate operand
Set to the value of bit 3 of the immediate operand
Set to the value of bit 2 of the immediate operand
Set to the value of bit 1 of the immediate operand
Set to the value of bit 0 of the immediate operand
STRLDSR
V2, V3 Core (ISA_A)
V4 Core (ISA_B)
V2 Core (ISA_A+)
Opcode present
No
No
Yes
MCF5275 Reference Manual, Rev. 2
3-30
Freescale Semiconductor
Chapter 4
Enhanced Multiply-Accumulate Unit (EMAC)
This chapter describes the functionality, microarchitecture, and performance of the enhanced
multiply-accumulate (EMAC) unit in the ColdFire family of processors.
4.1
Multiply-Accumulate Unit
The MAC design provides a set of DSP operations which can be used to improve the performance
of embedded code while supporting the integer multiply instructions of the baseline ColdFire
architecture.
The MAC provides functionality in three related areas:
•
•
•
Signed and unsigned integer multiplies
Multiply-accumulate operations supporting signed and unsigned integer operands as well
as signed, fixed-point, fractional operands
Miscellaneous register operations
The ColdFire family supports two MAC implementations with different performance levels and
capabilities. The original MAC uses a three-stage execution pipeline optimized for 16-bit
operands and featuring a 16x16 multiply array with a single 32-bit accumulator. The EMAC
features a four-stage pipeline optimized for 32-bit operands, with a fully pipelined 32 × 32
multiply array and four 48-bit accumulators.
The first ColdFire MAC supported signed and unsigned integer operands and was optimized for
16x16 operations, such as those found in a variety of applications including servo control and
image compression. As ColdFire-based systems proliferated, the desire for more precision on
input operands increased. The result was an improved ColdFire MAC with user-programmable
control to optionally enable use of fractional input operands.
EMAC improvements target three primary areas:
•
•
•
Improved performance of 32 × 32 multiply operations.
Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges
between the accumulator and the pipeline’s general-purpose registers.
A 48-bit accumulation data path to allow the use of a 40-bit product plus the addition of 8
extension bits to increase the dynamic number range when implementing signal processing
algorithms.
The three areas of functionality are addressed in detail in following sections. The logic required to
support this functionality is contained in a MAC module, as shown in Figure 4-1.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
4-1
Enhanced Multiply-Accumulate Unit (EMAC)
Operand Y
Operand X
X
Shift 0,1,-1
+/-
Accumulator(s)
Figure 4-1. Multiply-Accumulate Functionality Diagram
4.2
Introduction to the MAC
The MAC is an extension of the basic multiplier found in most microprocessors. It is typically
implemented in hardware within an architecture and supports rapid execution of signal processing
algorithms in fewer cycles than comparable non-MAC architectures. For example, small digital
filters can tolerate some variance in an algorithm’s execution time, but larger, more complicated
algorithms such as orthogonal transforms may have more demanding speed requirements beyond
the scope of any processor architecture and may require full DSP implementation.
To strike a balance between speed, size, and functionality, the ColdFire MAC is optimized for a
small set of operations that involve multiplication and cumulative additions. Specifically, the
multiplier array is optimized for single-cycle pipelined operations with a possible accumulation
after product generation. This functionality is common in many signal processing applications.
The ColdFire core architecture also has been modified to allow an operand to be fetched in parallel
with a multiply, increasing overall performance for certain DSP operations.
Consider a typical filtering operation where the filter is defined as in Figure 4-2.
N–1
y(i) =
N–1
∑ a ( k )y ( i – k ) + ∑ b ( k )x ( i – k )
k=1
k=0
Figure 4-2. Infinite Impulse Response (IIR) Filter
Here, the output y(i) is determined by past output values and past input values. This is the general
form of an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be
obtained by setting coefficients a(k) to zero. In either case, the operations involved in computing
such a filter are multiplies and product summing. To show this point, reduce the above equation to
a simple, four-tap FIR filter, shown in Figure 4-3, in which the accumulated sum is a sum of past
data values and coefficients.
MCF5275 Reference Manual, Rev. 2
4-2
Freescale Semiconductor
General Operation
3
y(i) =
∑ b ( k )x ( i – k ) = b ( 0 )x ( i ) + b ( 1 )x ( i – 1 ) + b ( 2 )x ( i – 2 ) + b ( 3 )x ( i – 3 )
k=0
Figure 4-3. Four-Tap FIR Filter
4.3
General Operation
The MAC speeds execution of ColdFire integer multiply instructions (MULS and MULU) and
provides additional functionality for multiply-accumulate operations. By executing MULS and
MULU in the MAC, execution times are minimized and deterministic compared to the 2-bit/cycle
algorithm with early termination that the OEP normally uses if no MAC hardware is present.
The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers,
followed by the addition or subtraction of the product to or from the value in an accumulator.
Optionally, the product may be shifted left or right by 1 bit before addition or subtraction.
Hardware support for saturation arithmetic can be enabled to minimize software overhead when
dealing with potential overflow conditions. Multiply-accumulate operations support 16- or 32-bit
input operands of the following formats:
•
•
•
Signed integers
Unsigned integers
Signed, fixed-point, fractional numbers
The EMAC is optimized for single-cycle, pipelined 32 × 32 multiplications. For word- and
longword-sized integer input operands, the low-order 40 bits of the product are formed and used
with the destination accumulator. For fractional operands, the entire 64-bit product is calculated
and either truncated or rounded to the most-significant 40-bit result using the round-to-nearest
(even) method before it is combined with the destination accumulator.
For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension
for signed integer and fractional operands, zero-fill for unsigned integer operands) before being
combined with the 48-bit destination accumulator.
Figure 4-4 and Figure 4-5 show relative alignment of input operands, the full 64-bit product, the
resulting 40-bit product used for accumulation, and 48-bit accumulator formats.
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Enhanced Multiply-Accumulate Unit (EMAC)
X
Product
OperandY
32
OperandX
32
23
40
Extended Product
8
40
8
40
“0”
+
Accumulator
8
Extension Byte Upper [7:0]
Accumulator [31:0]
Extension Byte Lower [7:0]
Figure 4-4. Fractional Alignment
X
Product
Extended Product
OperandY
32
OperandX
32
8
32
8
8
32
8
8
32
24
+
Accumulator
Extension Byte Upper [7:0]
Accumulator [31:0]
Extension Byte Lower [7:0]
Figure 4-5. Signed and Unsigned Integer Alignment
Thus, the 48-bit accumulator definition is a function of the EMAC operating mode. Given that
each 48-bit accumulator is the concatenation of 16-bit accumulator extension register (ACCextn)
contents and 32-bit ACCn contents, the specific definitions are as follows:
if MACSR[6:5] == 00/* signed integer mode */
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
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General Operation
if MACSR[6:5] == -1/* signed fractional mode */
Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]}
if MACSR[6:5] == 10/* unsigned integer mode */
Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]}
The four accumulators are represented as an array, ACCn, where n selects the register.
Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC
instructions have an effective issue rate of 1 cycle, regardless of input operand size or type.
All arithmetic operations use register-based input operands, and summed values are stored
internally in an accumulator. Thus, an additional move instruction is needed to store data in a
general-purpose register. One new feature found in EMAC instructions is the ability to choose the
upper or lower word of a register as a 16-bit input operand. This is useful in filtering operations if
one data register is loaded with the input data and another is loaded with the coefficient. Two 16-bit
multiply accumulates can be performed without fetching additional operands between instructions
by alternating the word choice during the calculations.
The EMAC has four accumulator registers versus the MAC’s single accumulator. The additional
registers improve the performance of some algorithms by minimizing pipeline stalls needed to
store an accumulator value back to general-purpose registers. Many algorithms require multiple
calculations on a given data set. By applying different accumulators to these calculations, it is
often possible to store one accumulator without any stalls while performing operations involving
a different destination accumulator.
The need to move large amounts of data presents an obstacle to obtaining high throughput rates in
DSP engines. New and existing ColdFire instructions can accommodate these requirements. A
MOVEM instruction can move large blocks of data efficiently by generating line-sized burst
references. The ability to simultaneously load an operand from memory into a register and execute
a MAC instruction makes some DSP operations such as filtering and convolution more
manageable.
The programming model includes a 16-bit mask register (MASK), which can optionally be used
to generate an operand address during MAC + MOVE instructions. The application of this register
with auto-increment addressing mode supports efficient implementation of circular data queues
for memory operands.
The additional MAC status register (MACSR) contains a 4-bit operational mode field and
condition flags. Operational mode bits control whether operands are signed or unsigned and
whether they are treated as integers or fractions. These bits also control the overflow/saturation
mode and the way in which rounding is performed. Negative, zero, and multiple overflow
condition flags are also provided.
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Enhanced Multiply-Accumulate Unit (EMAC)
4.4
Memory Map/Register Definition
The EMAC provides the following program-visible registers:
•
•
Four 32-bit accumulators (ACCn = ACC0, ACC1, ACC2, and ACC3)
Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values
for load and store operations (ACCext01 and ACCext23)
One 16-bit mask register (MASK)
One 32-bit MAC status register (MACSR) including four indicator bits signaling product
or accumulation overflow (one for each accumulator: PAV0–PAV3)
•
•
These registers are shown in Figure 4-6.
31
0
MACSR
ACC0
ACC1
ACC2
ACC3
ACCext01
ACCext23
MASK
MAC status register
MAC accumulator 0
MAC accumulator 1
MAC accumulator 2
MAC accumulator 3
Extensions for ACC0 and ACC1
Extensions for ACC2 and ACC3
MAC mask register
Figure 4-6. EMAC Register Set
4.4.1
MAC Status Register (MACSR)
MACSR functionality is organized as follows:
•
•
•
MACSR[11–8] contains one product/accumulation overflow flag per accumulator.
MACSR[7–4] defines the operating configuration of the MAC unit.
MACSR[3–0] contains indicator flags from the last MAC instruction execution.
31
12
11–8
7
Prod/acc overflow flags
Field
Reset
—
PAVx
6
5
4
3
Operational Mode
OM
C
S/U
F/I
R/T
2
1
0
Flags
N
Z
V
EV
0000_0000_0000_0000_0000_0000_0000_0000
R/W
R/W
Figure 4-7. MAC Status Register (MACSR)
Table 4-1 describes MACSR fields.
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Memory Map/Register Definition
Table 4-1. MACSR Field Descriptions
Bits
Name
31–12
—
11–8
PAVx
7–4
Description
Reserved, should be cleared.
Product/accumulation overflow flags. Contains four flags, one per accumulator, that
indicate if past MAC or MSAC instructions generated an overflow during product calculation
or the 48-bit accumulation. When a MAC or MSAC instruction is executed, the PAVx flag
associated with the destination accumulator is used to form the general overflow flag,
MACSR[V]. Once set, each flag remains set until V is cleared by a MOV.L , MACSR
instruction or the accumulator is loaded directly.
Operational Mode Fields
7
OMC
Overflow/saturation mode. Used to enable or disable saturation mode on overflow. If set,
the accumulator is set to the appropriate constant on any operation which overflows the
accumulator. Once saturated, the accumulator remains unaffected by any other MAC or
MSAC instructions until either the overflow bit is cleared or the accumulator is directly
loaded.
6
S/U
Signed/unsigned operations.
In integer mode:
S/U determines whether operations performed are signed or unsigned. It also determines
the accumulator value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, an accumulator saturates to the most
positive (0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on
both the instruction and the value of the product that overflowed.
1 Unsigned numbers. On overflow, if OMC is enabled, an accumulator saturates to the
smallest value (0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the
instruction.
In fractional mode:
S/U controls rounding while storing an accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a
general-purpose register as a 32-bit value.
1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method
when it is moved to a general-purpose register. See Section 4.4.1.1.1, “Rounding.” The
resulting 16-bit value is stored in the lower word of the destination register. The upper
word is zero-filled. The accumulator value is not affected by this rounding procedure.
5
F/I
Fractional/integer mode Determines whether input operands are treated as fractions or
integers.
0 Integers can be represented in either signed or unsigned notation, depending on the
value of S/U.
1 Fractions are represented in signed, fixed-point, two’s complement notation. Values
range from -1 to 1- 2-15 for 16-bit fractions and -1 to 1 - 2-31 for 32-bit fractions. See
Section 4.5.2, “Data Representation."
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Enhanced Multiply-Accumulate Unit (EMAC)
Table 4-1. MACSR Field Descriptions (Continued)
Bits
Name
Description
4
R/T
Round/truncate mode. Controls the rounding procedure for MOV.L ACCx,Rx, or MSAC.L
instructions when operating in fractional mode.
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator.
Additionally, when a store accumulator instruction is executed (MOV.L ACCx,Rx), the 8
lsbs of the 48-bit accumulator logic are simply truncated.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is
rounded to the nearest 40-bit value. If the low-order 24 bits equal 0x80_0000, the upper
40 bits are rounded to the nearest even (lsb = 0) value. See Section 4.4.1.1.1,
“Rounding.” Additionally, when a store accumulator instruction is executed (MOV.L
ACCx,Rx), the lsbs of the 48-bit accumulator logic are used to round the resulting 16- or
32-bit value. If MACSR[S/U] = 0 and MACSR[R/T] = 1, the low-order 8 bits are used to
round the resulting 32-bit fraction. If MACSR[S/U] = 1, the low-order 24 bits are used to
round the resulting 16-bit fraction.
3–0
Flags
3
N
Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC,
MSAC, and load operations; it is not affected by MULS and MULU instructions.
2
Z
Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC,
MSAC, and load operations; it is not affected by MULS and MULU instructions.
1
V
Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that
the result cannot be represented in the limited width of the EMAC. V is set only if a product
overflow occurs or the accumulation overflows the 48-bit structure. V is evaluated on each
MAC or MSAC operation and uses the appropriate PAVx flag in the next-state V evaluation.
0
EV
Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs
in integer mode or the 40 lsbs in fractional mode of the destination accumulator. However,
the result is still accurately represented in the combined 48-bit accumulator structure.
Although an overflow has occurred, the correct result, sign, and magnitude are contained
in the 48-bit accumulator. Subsequent MAC or MSAC operations may return the
accumulator to a valid 32/40-bit result.
Table 4-2 summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.
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Memory Map/Register Definition
Table 4-2. Summary of S/U, F/I, and R/T Control Bits
4.4.1.1
S/U
F/I
R/T
Operational Modes
0
0
x
Signed, integer
0
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
No round on accumulator stores
0
1
1
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-32-bits on accumulator stores
1
0
x
Unsigned, integer
1
1
0
Signed, fractional
Truncate on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
1
1
1
Signed, fractional
Round on MAC.L and MSAC.L
Round-to-16-bits on accumulator stores
Fractional Operation Mode
This section describes behavior when the fractional mode is used (MACSR[F/I] is set).
4.4.1.1.1
Rounding
When the processor is in fractional mode, there are two operations during which rounding can
occur.
•
•
Execution of a store accumulator instruction (MOV.L ACCx,Rx). The lsbs of the 48-bit
accumulator logic are used to round the resulting 16- or 32-bit value. If MACSR[S/U] is
cleared, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U]
is set, the low-order 24 bits are used to round the resulting 16-bit fraction.
Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero,
multiplying two 32-bit numbers creates a 64-bit product that is truncated to the upper 40
bits; otherwise, it is rounded using round-to-nearest (even) method.
To understand the round-to-nearest-even method, consider the following example involving the
rounding of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is
rounded to the closest 16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and
the low-order 16 bits be R0.L.
•
•
•
If R0.L is less than 0x8000, the result is truncated to the value of R0.U.
If R0.L is greater than 0x8000, the upper word is incremented (rounded up).
If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is
based on the lsb of R0.U, so the result is always even (lsb = 0).
— If the lsb of R0.U = 1 and R0.L = 0x8000, the number is rounded up.
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Enhanced Multiply-Accumulate Unit (EMAC)
— If the lsb of R0.U = 0 and R0.L =0x8000, the number is rounded down.
This method minimizes rounding bias and creates as statistically correct an answer as possible.
The rounding algorithm is summarized in the following pseudocode:
if R0.L < 0x8000
then Result = R0.U
else if R0.L > 0x8000
then Result = R0.U + 1
else if lsb of R0.U = 0
then Result = R0.U
else Result = R0.U + 1
/* R0.L = 0x8000 */
The round-to-nearest-even technique is also known as convergent rounding.
4.4.1.1.2
Saving and Restoring the EMAC Programming Model
The presence of rounding logic in the output datapath of the EMAC requires that special care be
taken during the EMAC’s save/restore process. In particular, any result rounding modes must be
disabled during the save/restore process so the exact bit-wise contents of the EMAC registers are
accessed. Consider the following memory structure containing the EMAC programming model:
struct
macState {
int acc0;
int acc1;
int acc2;
int acc3;
int accext01;
int accext02;
int mask;
int macsr;
} macState;
The following assembly language routine shows the proper sequence for a correct EMAC state
save. This code assumes all Dn and An registers are available for use and the memory location of
the state save is defined by A7.
EMAC_state_save:
move.l macsr,d7
clr.l
d0
move.l d0,macsr
move.l acc0,d0
move.l acc1,d1
move.l acc2,d2
move.l acc3,d3
move.l accext01,d4
move.l accext23,d5
move.l mask,d6
movem.l #0x00ff,(a7)
;
;
;
;
save the macsr
zero the register to ...
disable rounding in the macsr
save the accumulators
; save the accumulator extensions
; save the address mask
; move the state to memory
The following code performs the EMAC state restore:
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Memory Map/Register Definition
EMAC_state_restore:
movem.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
(a7),#0x00ff
#0,macsr
d0,acc0
d1,acc1
d2,acc2
d3,acc3
d4,accext01
d5,accext23
d6,mask
d7,macsr
; restore the state from memory
; disable rounding in the macsr
; restore the accumulators
; restore the accumulator extensions
; restore the address mask
; restore the macsr
By executing this type of sequence, the exact state of the EMAC programming model can be
correctly saved and restored.
4.4.1.1.3
MULS/MULU
MULS and MULU are unaffected by fractional mode operation; operands are still assumed to be
integers.
4.4.1.1.4
Scale Factor in MAC or MSAC Instructions
The scale factor is ignored while the MAC is in fractional mode.
4.4.2
Mask Register (MASK)
The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications
involved with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits
of the source operand are actually loaded into the register. When it is stored, the upper 16 bits are
all forced to ones.
This register performs a simple AND with the operand address for MAC instructions. That is, the
processor calculates the normal operand address and, if enabled, that address is then ANDed with
{0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the
operand address can be constrained to a certain memory region. This is used primarily to
implement circular queues in conjunction with the (An)+ addressing mode.
This feature minimizes the addressing support required for filtering, convolution, or any routine
that implements a data array as a circular queue. For MAC + MOVE operations, the MASK
contents can optionally be included in all memory effective address calculations. The syntax is as
follows:
MAC.sz
Ry,RxSF,<ea>y&,Rw
The & operator enables the use of MASK and causes bit 5 of the extension word to be set. The
exact algorithm for the use of MASK is as follows:
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Enhanced Multiply-Accumulate Unit (EMAC)
if extension word, bit [5] = 1, the MASK bit, then
if <ea> = (An)
oa = An & {0xFFFF, MASK}
if <ea> = (An)+
oa = An
An = (An + 4) & {0xFFFF, MASK}
if <ea> =-(An)
oa = (An - 4) & {0xFFFF, MASK}
An = (An - 4) & {0xFFFF, MASK}
if <ea> = (d16,An)
oa = (An + se_d16) & {0xFFFF0x, MASK}
Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For
auto-addressing modes of post-increment and pre-decrement, the calculation of the updated An
value is also shown.
Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular
queue implementations.
4.5
EMAC Instruction Set Summary
Table 4-3 summarizes EMAC unit instructions.
Table 4-3. EMAC Instruction Summary
Command
Mnemonic
Description
Multiply Signed
MULS <ea>y,Dx
Multiplies two signed operands yielding a signed result
Multiply Unsigned
MULU <ea>y,Dx
Multiplies two unsigned operands yielding an unsigned result
Multiply Accumulate
MAC Ry,RxSF,ACCx
MSAC Ry,RxSF,ACCx
Multiplies two operands and adds/subtracts the product
to/from an accumulator
Multiply Accumulate
with Load
MAC Ry,Rx,<ea>y,Rw,ACCx Multiplies two operands and combines the product to an
MSAC Ry,Rx,<ea>y,Rw,ACCx accumulator while loading a register with the memory operand
Load Accumulator
MOV.L {Ry,#imm},ACCx
Loads an accumulator with a 32-bit operand
Store Accumulator
MOV.L ACCx,Rx
Writes the contents of an accumulator to a CPU register
Copy Accumulator
MOV.L ACCy,ACCx
Copies a 48-bit accumulator
Load MACSR
MOV.L {Ry,#imm},MACSR
Writes a value to MACSR
Store MACSR
MOV.L MACSR,Rx
Write the contents of MACSR to a CPU register
Store MACSR to CCR
MOV.L MACSR,CCR
Write the contents of MACSR to the CCR
Load MAC Mask Reg
MOV.L {Ry,#imm},MASK
Writes a value to the MASK register
Store MAC Mask Reg
MOV.L MASK,Rx
Writes the contents of the MASK to a CPU register
Load AccExtensions01
MOV.L {Ry,#imm},ACCext01
Loads the accumulator 0,1 extension bytes with a 32-bit
operand
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EMAC Instruction Set Summary
Table 4-3. EMAC Instruction Summary (Continued)
Command
Mnemonic
Load AccExtensions23
Description
MOV.L {Ry,#imm},ACCext23
Loads the accumulator 2,3 extension bytes with a 32-bit
operand
Store AccExtensions01 MOV.L ACCext01,Rx
Writes the contents of accumulator 0,1 extension bytes into a
CPU register
Store AccExtensions23 MOV.L ACCext23,Rx
Writes the contents of accumulator 2,3 extension bytes into a
CPU register
4.5.1
EMAC Instruction Execution Times
The instruction execution times for the EMAC can be found in Section 3.12, “EMAC Instruction
Execution Times.”
The EMAC execution pipeline overlaps the AGEX stage of the OEP; that is, the first stage of the
EMAC pipeline is the last stage of the basic OEP. EMAC units are designed for sustained,
fully-pipelined operation on accumulator load, copy, and multiply-accumulate instructions.
However, instructions that store contents of the multiply-accumulate programming model can
generate OEP stalls that expose the EMAC execution pipeline depth, as in the following:
mac.w
Ry, Rx, Acc0
mov.l
Acc0, Rz
The mov.l instruction that stores the accumulator to an integer register (Rz) stalls until the
program-visible copy of the accumulator is available. Figure 4-8 shows EMAC timing.
Three-cycle
regBusy stall
DSOC
AGEX
mac
EMAC EX1
EMAC EX2
EMAC EX3
EMAC EX4
Accumulator 0
mov
mov
mac
mov
mac
mov
mac
mac
mac
old
new
Figure 4-8. EMAC-Specific OEP Sequence Stall
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Enhanced Multiply-Accumulate Unit (EMAC)
In Figure 4-8, the OEP stalls the store-accumulator instruction for 3 cycles: the depth of the EMAC
pipeline minus 1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by
a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the
operation is performed, the just-updated accumulator 0 value is available.
As with change or use stalls between accumulators and general-purpose registers, introducing
intervening instructions that do not reference the busy register can reduce or eliminate
sequence-related store-MAC instruction stalls. In fact, a major benefit of the EMAC is the addition
of three accumulators to minimize stalls caused by exchanges between the accumulator(s) and the
general-purpose registers.
4.5.2
Data Representation
MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique
operand type.
•
•
•
Two’s complement signed integer: In this format, an N-bit operand value lies in the range
-2(N-1) < operand < 2(N-1) - 1. The binary point is right of the lsb.
Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2N
- 1. The binary point is right of the lsb.
Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The
remaining bits signify the first N-1 bits after the binary point. Given an N-bit number,
aN-1aN-2aN-3... a2a1a0, its value is given by the equation in Figure 4-9.
N–2
value = – ( 1 ⋅ a N – 1 ) +
∑2
(i + 1 – N)
⋅ ai
i=0
Figure 4-9. Two’s Complement, Signed Fractional Equation
This format can represent numbers in the range -1 < operand < 1 - 2(N-1).
For words and longwords, the largest negative number that can be represented is -1, whose internal
representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or
(1 - 2-15); the most positive longword is 0x7FFF_FFFF or (1 - 2-31).
4.5.3
MAC Opcodes
MAC opcodes are described in the ColdFire Programmer’s Reference Manual.
Note the following:
•
Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final
operation that involves the product and the accumulator.
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EMAC Instruction Set Summary
•
•
•
The overflow (V) flag is handled differently. It is set if the complete product cannot be
represented as a 40-bit value (this applies to 32 × 32 integer operations only) or if the
combination of the product with an accumulator cannot be represented in the given number
of bits. The EMAC design includes an additional product/accumulation overflow bit for
each accumulator that are treated as sticky indicators and are used to calculate the V bit on
each MAC or MSAC instruction. See Section 4.4.1, “MAC Status Register (MACSR).”
For the MAC design, the assembler syntax of the MAC (multiply and add to accumulator)
and MSAC (multiply and subtract from accumulator) instructions does not include a
reference to the single accumulator. For the EMAC, it is expected that assemblers support
this syntax and that no explicit reference to an accumulator is interpreted as a reference to
ACC0. These assemblers would also support syntaxes where the destination accumulator
is explicitly defined.
The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where
<<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the
product is added to or subtracted from the accumulator. Without this operator, the product
is not shifted. If the EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and
no shift is performed. Because a product can overflow, the following guidelines are
implemented:
— For unsigned word and longword operations, a zero is shifted into the product on right
shifts.
— For signed, word operations, the sign bit is shifted into the product on right shifts unless
the product is zero. For signed, longword operations, the sign bit is shifted into the
product unless an overflow occurs or the product is zero, in which case a zero is shifted
in.
— For all left shifts, a zero is inserted into the lsb position.
The following pseudocode explains basic MAC or MSAC instruction functionality. This example
is presented as a case statement covering the three basic operating modes with signed integers,
unsigned integers, and signed fractionals. Throughout this example, a comma-separated list in
curly brackets, {}, indicates a concatenation operation.
switch (MACSR[6:5])
/* MACSR[S/U, F/I] */
{
case 0:
/* signed integers */
if (MACSR.OMC == 0 || MACSR.PAVx == 0)
then {
MACSR.PAVx = 0
/* select the input operands */
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]}
else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]}
if (U/Lx == 1)
then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}
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Enhanced Multiply-Accumulate Unit (EMAC)
else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]}
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
if ((product[63:39] != 0x0000_00_0) && (product[63:39] != 0xffff_ff_1))
then {
/* product overflow */
MACSR.PAVx = 1
MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then if (product[63] == 1)
then result[47:0] = 0x0000_7fff_ffff
else result[47:0] = 0xffff_8000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
if (product[63] == 1)
then result[47:0] = 0xffff_8000_0000
else result[47:0] = 0x0000_7fff_ffff
}
/* sign-extend to 48 bits before performing any scaling */
product[47:40] = {8{product[39]}}
/* sign-extend */
/* scale product before combining with accumulator */
switch (SF)
/* 2-bit scale factor */
{
case 0:
/* no scaling specified */
break;
case 1:
/* SF = “<< 1” */
product[40:0] = {product[39:0], 0}
break;
case 2:
/* reserved encoding */
break;
case 3:
/* SF = “>> 1” */
product[39:0] = {product[39], product[39:1]}
break;
}
if (MACSR.PAVx == 0)
then {if (inst == MSAC)
then result[47:0] = ACCx[47:0] - product[47:0]
else result[47:0] = ACCx[47:0] + product[47:0]
}
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.PAVx = 1
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EMAC Instruction Set Summary
MACSR.V = 1
if (MACSR.OMC == 1)
then /* accumulation overflow,
saturationMode enabled */
if (result[47] == 1)
then result[47:0] = 0x0000_7fff_ffff
else result[47:0] = 0xffff_8000_0000
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVx
MACSR.N = ACCx[47]
if (ACCx[47:0] == 0x0000_0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
if ((ACCx[47:31] == 0x0000_0) || (ACCx[47:31] == 0xffff_1))
then MACSR.EV = 0
else MACSR.EV = 1
break;
case 1,3:
/* signed fractionals */
if (MACSR.OMC == 0 || MACSR.PAVx == 0)
then {
MACSR.PAVx = 0
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {Ry[31:16], 0x0000}
else operandY[31:0] = {Ry[15:0], 0x0000}
if (U/Lx == 1)
then operandX[31:0] = {Rx[31:16], 0x0000}
else operandX[31:0] = {Rx[15:0], 0x0000}
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
/* perform the multiply */
product[63:0] = (operandY[31:0] * operandX[31:0]) << 1
/* check for product rounding */
if (MACSR.R/T == 1)
then { /* perform convergent rounding */
if (product[23:0] > 0x80_0000)
then product[63:24] = product[63:24] + 1
else if ((product[23:0] == 0x80_0000) && (product[24] == 1))
then product[63:24] = product[63:24] + 1
}
/* sign-extend to 48 bits and combine with accumulator */
/* check for the -1 * -1 overflow case */
if ((operandY[31:0] == 0x8000_0000) && (operandX[31:0] == 0x8000_0000))
then product[71:64] = 0x00
/* zero-fill */
else product[71:64] = {8{product[63]}}
/* sign-extend */
if (inst == MSAC)
then result[47:0] = ACCx[47:0] - product[71:24]
else result[47:0] = ACCx[47:0] + product[71:24]
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Enhanced Multiply-Accumulate Unit (EMAC)
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.PAVx = 1
MACSR.V = 1
if (MACSR.OMC == 1)
then /* accumulation overflow,
saturationMode enabled */
if (result[47] == 1)
then result[47:0] = 0x007f_ffff_ff00
else result[47:0] = 0xff80_0000_0000
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVx
MACSR.N = ACCx[47]
if (ACCx[47:0] == 0x0000_0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
if ((ACCx[47:39] == 0x00_0) || (ACCx[47:39] == 0xff_1))
then MACSR.EV = 0
else MACSR.EV = 1
break;
case 2:
/* unsigned integers */
if (MACSR.OMC == 0 || MACSR.PAVx == 0)
then {
MACSR.PAVx = 0
/* select the input operands */
if (sz == word)
then {if (U/Ly == 1)
then operandY[31:0] = {0x0000,
else operandY[31:0] = {0x0000,
if (U/Lx == 1)
then operandX[31:0] = {0x0000,
else operandX[31:0] = {0x0000,
}
else {operandY[31:0] = Ry[31:0]
operandX[31:0] = Rx[31:0]
}
Ry[31:16]}
Ry[15:0]}
Rx[31:16]}
Rx[15:0]}
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
if (product[63:40] != 0x0000_00)
then {
/* product overflow */
MACSR.PAVx = 1
MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then result[47:0] = 0x0000_0000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
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EMAC Instruction Set Summary
result[47:0] = 0xffff_ffff_ffff
}
/* zero-fill to 48 bits before performing any scaling */
product[47:40] = 0
/* zero-fill upper byte */
/* scale product before combining with accumulator */
switch (SF)
/* 2-bit scale factor */
{
case 0:
/* no scaling specified */
break;
case 1:
/* SF = “<< 1” */
product[40:0] = {product[39:0], 0}
break;
case 2:
/* reserved encoding */
break;
case 3:
/* SF = “>> 1” */
product[39:0] = {0, product[39:1]}
break;
}
/* combine with accumulator */
if (MACSR.PAVx == 0)
then {if (inst == MSAC)
then result[47:0] = ACCx[47:0] - product[47:0]
else result[47:0] = ACCx[47:0] + product[47:0]
}
/* check for accumulation overflow */
if (accumulationOverflow == 1)
then {MACSR.PAVx = 1
MACSR.V = 1
if (inst == MSAC && MACSR.OMC == 1)
then result[47:0] = 0x0000_0000_0000
else if (MACSR.OMC == 1)
then /* overflowed MAC,
saturationMode enabled */
result[47:0] = 0xffff_ffff_ffff
}
/* transfer the result to the accumulator */
ACCx[47:0] = result[47:0]
}
MACSR.V = MACSR.PAVx
MACSR.N = ACCx[47]
if (ACCx[47:0] == 0x0000_0000_0000)
then MACSR.Z = 1
else MACSR.Z = 0
if (ACCx[47:32] == 0x0000)
then MACSR.EV = 0
else MACSR.EV = 1
break;
}
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Enhanced Multiply-Accumulate Unit (EMAC)
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 5
Cache
5.1
Introduction
This chapter describes the MCF5275 cache operation.
5.1.1
•
•
•
•
•
•
•
5.1.2
Features
Configurable as instruction, data, or split instruction/data cache
16-Kbyte direct-mapped cache
Single-cycle access on cache hits
Physically located on the Coldfire core's high-speed local bus
Nonblocking design to maximize performance
Separate instruction and data 16-Byte line-fill buffers
Configurable instruction cache miss-fetch algorithm
Physical Organization
The cache is a direct-mapped single-cycle memory. It may be configured as an instruction cache,
a write-through data cache, or a split instruction/data cache. The cache storage is organized as
1024 lines, each containing 16 bytes. The memory storage consists of a 1024-entry tag array
(containing addresses and a valid bit), and a data array containing 16 Kbytes, organized as 4096 ×
32 bits.
Cache configuration is controlled by bits in the cache control register (CACR) that is detailed later
in this chapter. For the instruction or data-only configurations, only the associated instruction or
data line-fill buffer is used. For the split cache configuration, one-half of the tag and storage arrays
is used for an instruction cache and one-half is used for a data cache. The split cache configuration
uses both the instruction and the data line-fill buffers. The core’s local bus is a unified bus used for
both instruction and data fetches. Therefore, the cache can have only one fetch, either instruction
or data, active at one time.
For the instruction- or data-only configurations, the cache tag and storage arrays are accessed in
parallel: fetch address bits [13:4] addressing the tag array and fetch address bits [13:2] addressing
the storage array. For the split cache configuration, the cache tag and storage arrays are accessed
in parallel. The msb of the tag array address is set for instruction fetches and cleared for operand
fetches; fetch address bits [12:4] provide the rest of the tag array address. The tag array outputs the
address mapped to the given cache location along with the valid bit for the line. This address field
is compared to bits [31:14] for instruction- or data-only configurations and to bits [31:13] for a
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5-1
Cache
split configuration of the fetch address from the local bus to determine if a cache hit has occurred.
If the desired address is mapped into the cache memory, the output of the storage array is driven
onto the ColdFire core's local data bus, thereby completing the access in a single cycle.
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are
loaded into the cache.
The cache also contains separate 16-byte instruction and data line-fill buffers that provide
temporary storage for the last line fetched in response to a cache miss. With each fetch, the
contents of the associated line fill buffer are examined. Thus, each fetch address examines both
the tag memory array and the associated line fill buffer to see if the desired address is mapped into
either hardware resource. A cache hit in either the memory array or the associated line-fill buffer
is serviced in a single cycle. Because the line fill buffer maintains valid bits on a longword basis,
hits in the buffer can be serviced immediately without waiting for the entire line to be fetched.
If the referenced address is not contained in the memory array or the associated line-fill buffer, the
cache initiates the required external fetch operation. In most situations, this is a 16-byte line-sized
burst reference.
The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is
released after the initial access of a miss. Thus, the cache or the SRAM module can service
subsequent requests while the remainder of the line is being fetched and loaded into the fill buffer.
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Introduction
External Data[31:0]
Local Address Bus
13
31
31
4 3 21 0
4
I or D Line Buffer Storage
Buffer
Address
I or D Line
MUX
=
Fill Hit
14
31
TAG
VALID
0
31
0
0
DATA
4095
1023
=
MUX
Tag Hit
Local Data Bus
Figure 5-1. Cache Block Diagram
5.1.3
Operation
The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches
from the ColdFire core and certain memory fetches initiated by the debug module. Typically, the
debug module's memory references appear as supervisor data accesses but the unit can be
programmed to generate user-mode accesses and/or instruction fetches. The cache processes any
fetch access in the normal manner.
5.1.3.1
Interaction with Other Modules
Because both the cache and high-speed SRAM module are connected to the ColdFire core's local
data bus, certain user-defined configurations can result in simultaneous fetch processing.
If the referenced address is mapped into the SRAM module, that module will service the request
in a single cycle. In this case, data accessed from the cache is simply discarded and no external
memory references are generated. If the address is not mapped into the SRAM space, the cache
handles the request in the normal fashion.
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5-3
Cache
5.1.3.2
Memory Reference Attributes
For every memory reference the ColdFire core or the debug module generates, a set of “effective
attributes” is determined based on the address and the access control registers (ACRs). This set of
attributes includes the cacheable/noncacheable definition, the precise/imprecise handling of
operand write, and the write-protect capability.
In particular, each address is compared to the values programmed in the ACRs. If the address
matches one of the ACR values, the access attributes from that ACR are applied to the reference.
If the address does not match either ACR, then the default value defined in the cache control
register (CACR) is used. The specific algorithm is as follows:
if (address == ACR0_address including mask)
Effective Attributes = ACR0 attributes
else if (address == ACR1_address including mask)
Effective Attributes = ACR1 attributes
else Effective Attributes = CACR default attributes
5.1.3.3
Cache Coherency and Invalidation
The cache does not monitor ColdFire core data references for accesses to cached instructions.
Therefore, software must maintain instruction cache coherency by invalidating the appropriate
cache entries after modifying code segments if instructions are cached.
The cache invalidation can be performed in several ways. For the instruction- or data-only
configurations, setting CACR[CINV] forces the entire cache to be marked as invalid. The
invalidation operation requires 1024 cycles because the cache sequences through the entire tag
array, clearing a single location each cycle. For the split configuration, CACR[INVI] and
CACR[INVD] can be used in addition to CACR[CINV] to clear the entire cache, only the
instruction half, or only the data half. Any subsequent fetch accesses are postponed until the
invalidation sequence is complete.
The privileged CPUSHL instruction can invalidate a single cache line. When this instruction is
executed, the cache entry defined by bits [13:4] of the source address register is invalidated,
provided CACR[CPDI] is cleared. For the split data/instruction cache configuration, software
directly controls bit 13 which selects whether an instruction cache or data cache line is being
accessed.
These invalidation operations can be initiated from the ColdFire core or the debug module.
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Introduction
5.1.3.4
Reset
A hardware reset clears the CACR and disables the cache. The contents of the tag array are not
affected by the reset. Accordingly, the system startup code must explicitly perform a cache
invalidation by setting CACR[CINV] before the cache can be enabled.
5.1.3.5
Cache Miss Fetch Algorithm/Line Fills
As discussed in Section 5.1.2, “Physical Organization,” the cache hardware includes a 16-byte
line-fill buffer for providing temporary storage for the last fetched line.
With the cache enabled as defined by CACR[CENB], a cacheable fetch that misses in both the tag
memory and the line-fill buffer generates an external fetch. For data misses, the size of the external
fetch is always 16 bytes. For instruction misses, the size of the external fetch is determined by the
value contained in the 2-bit CLNF field of the CACR and the miss address. Table 5-1 shows the
relationship between the CLNF bits, the miss address, and the size of the external fetch.
Table 5-1. Initial Fetch Offset vs. CLNF Bits
CLNF[1:0
]
Longword Address Bits
00
01
10
11
00
Line
Line
Line
Longword
01
Line
Line
Longword
Longword
1X
Line
Line
Line
Line
Depending on the runtime characteristics of the application and the memory response speed,
overall performance may be increased by programming the CLNF bits to values {00, 01}.
For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss address is
accessed first followed by the remaining three longwords that are accessed by incrementing the
longword address in a modulo-16 fashion as shown below:
if miss address[3:2] = 00
fetch sequence = {0x0, 0x4, 0x8, 0xC}
if miss address[3:2] = 01
fetch sequence = {0x4, 0x8, 0xC, 0x0}
if miss address[3:2] = 10
fetch sequence = {0x8, 0xC, 0x0, 0x4}
if miss address[3:2] = 11
fetch sequence = {0xC, 0x0, 0x4, 0x8}
Once an external fetch has been initiated and the data is loaded into the line-fill buffer, the cache
maintains a special “most-recently-used” indicator that tracks the contents of the associated
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5-5
Cache
line-fill buffer versus its corresponding cache location. At the time of the miss, the hardware
indicator is set, marking the line-fill buffer as “most recently used.” If a subsequent access occurs
to the cache location defined by bits [13:4] (or bits [12:4] for split configurations of the fill buffer
address), the data in the cache memory array is now most recently used, so the hardware indicator
is cleared. In all cases, the indicator defines whether the contents of the line-fill buffer or the
memory data array are most recently used. At the time of the next cache miss, the contents of the
line-fill buffer are written into the memory array if the entire line is present, and the line-fill buffer
data is still most recently used compared to the memory array.
Generally, longword references are used for sequential instruction fetches. If the processor
branches to an odd word address, a word-sized instruction fetch is generated.
For instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts
of non-cacheable references under control of CACR[CEIB]. With this bit set, a noncacheable
instruction fetch is processed as defined by Table 5-2. For this condition, the line-fill buffer is
loaded and subsequent references can hit in the buffer, but the data is never loaded into the memory
array.
Table 5-2 shows the relationship between CACR bits CENB and CEIB and the type of instruction
fetch.
Table 5-2. Instruction Cache Operation as Defined by CACR
5.2
CACR
[CENB]
CACR
[CEIB]
Type of
Instruction Fetch
0
0
N/A
Cache is completely disabled; all instruction fetches
are word or longword in size.
0
1
N/A
All instruction fetches are word or longword in size
1
X
Cacheable
1
0
Noncacheable
All instruction fetches are word or longword in size,
and not loaded into the line-fill buffer
1
1
Noncacheable
Instruction fetch size is defined by Table 5-1 and
loaded into the line-fill buffer, but are never written
into the memory array.
Description
Fetch size is defined by Table 5-1 and contents of the
line-fill buffer can be written into the memory array
Memory Map/Register Definition
Three supervisor registers define the operation of the cache and local bus controller: the cache
control register (CACR) and two access control registers (ACR0, ACR1). Table 5-3 below shows
the memory map of the cache and access control registers.
The following lists several keynotes regarding the programming model table:
•
The CACR and ACRs can only be accessed in supervisor mode using the MOVEC
instruction with an Rc value of 0x002, 0x004 and 0x005, respectively.
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Memory Map/Register Definition
•
Addresses not assigned to the registers and undefined register bits are reserved for future
expansion. The user should write zeros to these reserved address spaces and read accesses
will return zeros.
The reset value column indicates the register initial value at reset. Certain registers may be
uninitialized upon reset; that is, they may contain random values after reset.
The access column indicates if the corresponding register allows both read/write
functionality (R/W), read-only functionality (R), or write-only functionality (W). If a read
access to a write-only register is attempted, zeros will be returned. If a write access to a
read-only register is attempted, the access will be ignored and no write will occur.
•
•
Table 5-3. Memory Map of Cache Registers
Address
Width
MOVEC with 0x002
CACR
32
Cache Control Register
0x0000_0000
W
MOVEC with 0x004
ACR0
32
Access Control Register 0
0x0000_0000
W
MOVEC with 0x005
ACR1
32
Access Control Register 1
0x0000_0000
W
1
5.2.1
Description
Reset Value
Access
Name
1
Readable through debug
Registers Description
5.2.1.1
Cache Control Register (CACR)
The CACR controls the operation of the cache. The CACR provides a set of default memory
access attributes used when a reference address does not map into the spaces defined by the ACRs.
The CACR is a 32-bit write-only supervisor control register. It is accessed in the CPU address
space via the MOVEC instruction with an Rc encoding of 0x002. The CACR can be read when in
background debug mode (BDM). At system reset, the entire register is cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W CENB
Reset
—
CPD CFRZ
—
CINV
DISI DISD INVI INVD
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
—
0
0
Address
0
CEIB DCM DBWE
0
0
0
0
0
—
0
DWP EUSP
0
0
0
—
0
CLNF
0
0
0
MOVEC with 0x002
Figure 5-2. Cache Control Register (CACR)
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5-7
Cache
Table 5-4. CACR Field Descriptions
Bits
Name
Description
31
CENB
Cache enable. The memory array of the cache is enabled only if CENB is asserted. This
bit, along with the DISI (disable instruction caching) and DISD (disable data caching) bits,
control the cache configuration.
0 Cache disabled
1 Cache enabled
Table 5-5 describes cache configuration.
30–29
—
28
CPDI
Disable CPUSHL invalidation. When the privileged CPUSHL instruction is executed, the
cache entry defined by bits [13:4] of the address is invalidated if CPDI = 0. If CPDI = 1, no
operation is performed.
0 Enable invalidation
1 Disable invalidation
27
CFRZ
Cache freeze. This field allows the user to freeze the contents of the cache. When CFRZ
is asserted line fetches can be initiated and loaded into the line-fill buffer, but a valid cache
entry can not be overwritten. If a given cache location is invalid, the contents of the line-fill
buffer can be written into the memory array while CFRZ is asserted.
0 Normal Operation
1 Freeze valid cache lines
26–25
—
24
CINV
Cache invalidate. The cache invalidate operation is not a function of the CENB state (that
is, this operation is independent of the cache being enabled or disabled). Setting this bit
forces the cache to invalidate all, half, or none of the tag array entries depending on the
state of the DISI, DISD, INVI, and INVD bits. The invalidation process requires several
cycles of overhead plus 1024 machine cycles to clear all tag array entries and 64512
cycles to clear half of the tag array entries, with a single cache entry cleared per machine
cycle. The state of this bit is always read as a zero. After a hardware reset, the cache must
be invalidated before it is enabled.
0 No operation
1 Invalidate all cache locations
Table 5-6 describes how to set the cache invalidate all bit.
23
DISI
Disable instruction caching. When set, this bit disables instruction caching. This bit, along
with the CENB (cache enable) and DISD (disable data caching) bits, control the cache
configuration. See the CENB definition for a detailed description.
0 Do not disable instruction caching
1 Disable instruction caching
Table 5-5 describes cache configuration and Table 5-6 describes how to set the cache
invalidate all bit.
22
DISD
Disable data caching. When set, this bit disables data caching. This bit, along with the
CENB (cache enable) and DISI (disable instruction caching) bits, control the cache
configuration. See the CENB definition for a detailed description.
0 Do not disable data caching
1 Disable data caching
Table 5-5 describes cache configuration and Table 5-6 describes how to set the cache
invalidate all bit.
Reserved, should be cleared.
Reserved, should be cleared.
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Memory Map/Register Definition
Table 5-4. CACR Field Descriptions (Continued)
Bits
Name
Description
21
INVI
CINV instruction cache only. This bit can not be set unless the cache configuration is split
(both DISI and DISD cleared). For instruction or data cache configurations this bit is a
don’t-care. For the split cache configuration, this bit is part of the control for the invalidate
all operation. See the CINV definition for a detailed description
Table 5-6 describes how to set the cache invalidate all bit.
20
INVD
CINV data cache only. This bit can not be set unless the cache configuration is split (both
DISI and DISD cleared). For instruction or data cache configurations this bit is a don’t-care.
For the split cache configuration, this bit is part of the control for the invalidate all operation.
See the CINV definition for a detailed description
Table 5-6 describes how to set the cache invalidate all bit.
19–11
—
10
CEIB
Cache enable noncacheable instruction bursting. Setting this bit enables the line-fill buffer
to be loaded with burst transfers under control of CLNF[1:0] for noncacheable accesses.
Noncacheable accesses are never written into the memory array. See Table 5-2.
0 Disable burst fetches on noncacheable accesses
1 Enable burst fetches on noncacheable accesses
9
DCM
Default cache mode. This bit defines the default cache mode: 0 is cacheable, 1 is
noncacheable. For more information on the selection of the effective memory attributes,
see Section 5.1.3.2, “Memory Reference Attributes.
0 Caching enabled
1 Caching disabled
8
DBWE
Default buffered write enable. This bit defines the default value for enabling buffered writes.
If DBWE = 0, the termination of an operand write cycle on the processor's local bus is
delayed until the external bus cycle is completed. If DBWE = 1, the write cycle on the local
bus is terminated immediately and the operation buffered in the bus controller. In this
mode, operand write cycles are effectively decoupled between the processor's local bus
and the external bus. Generally, enabled buffered writes provide higher system
performance but recovery from access errors can be more difficult. For the ColdFire core,
reporting access errors on operand writes is always imprecise and enabling buffered writes
further decouples the write instruction and the signaling of the fault
0 Disable buffered writes
1 Enable buffered writes
7–6
—
5
DWP
Default write protection
0 Read and write accesses permitted
1 Only read accesses permitted
4
EUSP
Enable user stack pointer. See Section 3.2.3.2, “Supervisor/User Stack Pointers (A7 and
OTHER_A7)," for more information on the dual stack pointer implementation.
0 Disable the processor’s use of the User Stack Pointer
1 Enable the processor’s use of the User Stack Pointer
3–2
—
1–0
CLNF
Reserved, should be cleared.
Reserved, should be cleared.
Reserved, should be cleared.
Cache line fill. These bits control the size of the memory request the cache issues to the
bus controller for different initial instruction line access offsets. See Table 5-1 for external
fetch size based on miss address and CLNF.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
5-9
Cache
Table 5-5 shows the relationship between CACR bits CENB, DISI, & DISD and the cache
configuration.
Table 5-5. Cache Configuration as Defined by CACR
CACR
[CENB]
CACR
[DISI]
CACR
[DISD]
Configuration
0
x
x
N/A
1
0
0
Split Instruction/
Data Cache
8 KByte direct-mapped instruction cache (uses lower
half of tag and storage arrays) and 8 KByte
direct-mapped write-through data cache (uses upper
half of tag and storage arrays)
1
0
1
Instruction Cache
16 KByte direct-mapped instruction cache (uses all of
tag and storage arrays)
1
1
0
Data Cache
Description
Cache is completely disabled
16 KByte direct-mapped write-through data cache
(uses all of tag and storage arrays)
Table 5-6 shows the relationship between CACR bits DISI, DISD, INVI, & INVD and setting the
cache invalidate all bit.
Table 5-6. Cache Invalidate All as Defined by CACR
5.2.1.2
CACR
[DISI]
CACR
[DISD]
CACR
[INVI]
CACR
[INVD]
0
0
0
0
Split Instruction/
Data Cache
Invalidate all entries in both 8 KByte
instruction cache and 8 KByte data cache
0
0
0
1
Split Instruction/
Data Cache
Invalidate only 8 KByte data cache
0
0
1
0
Split Instruction
Data Cache
Invalidate only 8 KByte instruction cache
0
0
1
1
Split Instruction/
Data Cache
No invalidate
1
0
x
x
Instruction Cache
Invalidate 16 KByte instruction cache
0
1
x
x
Data Cache
Invalidate 16 KByte data cache
Configuration
Operation
Access Control Registers (ACR0, ACR1)
The ACRs provide a definition of memory reference attributes for two memory regions (one per
ACR). This set of effective attributes is defined for every memory reference using the ACRs or
the set of default attributes contained in the CACR. The ACRs are examined for every processor
memory reference that is not mapped to the SRAM memories.
The ACRs are 32-bit write-only supervisor control register. They are accessed in the CPU address
space via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The ACRs can be
read when in background debug mode (BDM). At system reset, both registers are cleared.
MCF5275 Reference Manual, Rev. 2
5-10
Freescale Semiconductor
Memory Map/Register Definition
NOTE
IPSBAR space cannot be cached. Ensure that ACR[AB] does not fall
within this space.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
AB
AM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CM
BWE
0
0
R
W
Reset
EN
0
SM
0
—
0
Address
0
0
0
0
0
0
—
0
WP
0
0
—
0
0
MOVEC with 0x004, MOVEC with 0x005
Figure 5-3. Access Control Registers (ACR0, ACR1)
Table 5-7. ACR Field Descriptions
Bits
Name
Description
31–24
AB
Address base. This 8-bit field is compared to address bits [31:24] from the processor's local
bus under control of the ACR address mask. If the address matches, the attributes for the
memory reference are sourced from the given ACR.
23–16
AM
Address mask. This 8-bit field can mask any bit of the AB field comparison. If a bit in the
AM field is set, then the corresponding bit of the address field comparison is ignored.
15
EN
ACR Enable. The EN bit defines the ACR enable. Hardware reset clears this bit, disabling
the ACR.
0 ACR disabled
1 ACR enabled
14–13
SM
Supervisor mode. This two-bit field allows the given ACR to be applied to references based
on operating privilege mode of the ColdFire processor. The field uses the ACR for user
references only, supervisor references only, or all accesses.
00 Match if user mode
01 Match if supervisor mode
1x Match always—ignore user/supervisor mode
12–7
—
Reserved, should be cleared.
6
CM
Cache mode. This bit defines the cache mode: 0 is cacheable, 1 is noncacheable.
0 Caching enabled
1 Caching disabled
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
5-11
Cache
Table 5-7. ACR Field Descriptions (Continued)
Bits
Name
Description
5
BWE
Buffered write enable. This bit defines the value for enabling buffered writes. If BWE = 0,
the termination of an operand write cycle on the processor's local bus is delayed until the
external bus cycle is completed. If BWE = 1, the write cycle on the local bus is terminated
immediately and the operation is then buffered in the bus controller. In this mode, operand
write cycles are effectively decoupled between the processor's local bus and the external
bus.
Generally, the enabling of buffered writes provides higher system performance but
recovery from access errors may be more difficult. For the V2 ColdFire core, the reporting
of access errors on operand writes is always imprecise, and enabling buffered writes
simply decouples the write instruction from the signaling of the fault even more.
0 Writes are not buffered.
1 Writes are buffered.
4–3
—
2
WP
1–0
—
Reserved, should be cleared.
Write protect. The WP bit defines the write-protection attribute. If the effective memory
attributes for a given access select the WP bit, an access error terminates any attempted
write with this bit set.
0 Read and write accesses permitted
1 Only read accesses permitted
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
5-12
Freescale Semiconductor
Chapter 6
Static RAM (SRAM)
6.1
Introduction
This chapter is a description of the on-chip static RAM (SRAM) implementation that covers
general operations, configuration, and initialization. It also provides information and examples
showing how to minimize power consumption when using the SRAM.
6.1.1
•
•
•
•
•
6.1.2
Features
One 64-Kbyte SRAM
Single-cycle access
Physically located on processor's high-speed local bus
Memory location programmable on any 0-modulo-64 Kbyte address
Byte, word, longword address capabilities
Operation
The SRAM module provides a general-purpose memory block that the ColdFire processor can
access in a single cycle. The location of the memory block can be specified to any 0-modulo-64K
address within the 4-Gbyte address space. The memory is ideal for storing critical code or data
structures or for use as the system stack. Because the SRAM module is physically connected to
the processor's high-speed local bus, it can service processor-initiated access or
memory-referencing commands from the debug module.
Depending on configuration information, instruction fetches may be sent to both the cache and the
SRAM block simultaneously. If the reference is mapped into the region defined by the SRAM, the
SRAM provides the data back to the processor, and the cache data is discarded. Accesses from the
SRAM module are not cached.
The SRAM is dual-ported to provide DMA or FEC access. The SRAM is partitioned into two
physical memory arrays to allow simultaneous access to both arrays by the processor core and
another bus master. See Section 11.3, “Internal Bus Arbitration,” for more information.
6.2
Register Description
The SRAM programming model includes a description of the SRAM base address register
(RAMBAR), SRAM initialization, and power management.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
6-1
Static RAM (SRAM)
6.2.1
SRAM Base Address Register (RAMBAR)
The configuration information in the SRAM base address register (RAMBAR) controls the
operation of the SRAM module.
•
•
•
•
The RAMBAR holds the base address of the SRAM. The MOVEC instruction provides
write-only access to this register.
The RAMBAR can be read or written from the debug module in a similar manner.
All undefined bits in the register are reserved. These bits are ignored during writes to the
RAMBAR, and return zeroes when read from the debug module.
The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are
unaffected.
NOTE
Do not confuse this RAMBAR with the SCM RAMBAR in
Section 11.2.1.2, “Memory Base Address Register (RAMBAR).”
Although similar, this core RAMBAR enables core access to the
SRAM memory, while the SCM RAMBAR enables peripheral (e.g.
DMA and FEC) access to the SRAM.
The RAMBAR contains several control fields. These fields are shown in Figure 6-1.
31
30
29
28
27
26
25
24
23
R
See Note
W
BA
Reset
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
See Note
W
0
0
0
0
Reset
—
—
—
—
PRI1 PRI0 SPV
—
Address
—
—
WP
0
0
C/I
SC
SD
UC
UD
V
—
—
—
—
—
—
—
—
0
CPU + 0x0C05
Note: W for Core; R/W for Debug
Figure 6-1. SRAM Base Address Register (RAMBAR)
Table 6-1. RAMBAR Field Descriptions
Bits
Name
Description
31–16
BA
Base address. Defines the 0-modulo-64K base address of the SRAM module. By
programming this field, the SRAM may be located on any 64-Kbyte boundary within the
processor’s 4-Gbyte address space.
15–12
—
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
6-2
Freescale Semiconductor
Register Description
Table 6-1. RAMBAR Field Descriptions (Continued)
Bits
Name
Description
11–10
PRI1
PRI0
Priority bit. PRI1 determines if DMA/FEC or CPU has priority in upper 32k bank of memory.
PRI0 determines if DMA/FEC or CPU has priority in lower 32k bank of memory. If bit is set,
DMA/FEC has priority. If bit is cleared, CPU has priority. Priority is determined according
to the following table.
PRI[1:0]
Upper Bank Priority
Lower Bank Priority
00
01
10
11
CPU Accesses
CPU Accesses
DMA/FEC Accesses
DMA/FEC Accesses
CPU Accesses
DMA/FEC Accesses
CPU Accesses
DMA/FEC Accesses
Note: The recommended setting for the priority bits is 00.
9
SPV
Secondary port valid. Allows access by DMA and FEC
0 DMA and FEC access to memory is disabled.
1 DMA and FEC access to memory is enabled.
Note: The BDE bit in the second RAMBAR register must also be set to allow dual port
access to the SRAM. For more information, see Section 11.2.1.2, “Memory Base Address
Register (RAMBAR).”
8
WP
Write protect. Allows only read accesses to the SRAM. When this bit is set, any attempted
write access will generate an access error exception to the ColdFire processor core.
0 Allows read and write accesses to the SRAM module
1 Allows only read accesses to the SRAM module
7–6
5–1
—
Reserved, should be cleared.
C/I, SC, SD, Address space masks (ASn)
UC, UD
These five bit fields allow certain types of accesses to be “masked,” or inhibited from
accessing the SRAM module. The address space mask bits are:
C/I = CPU space/interrupt acknowledge cycle mask
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each address space bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address
space is made, it is inhibited from accessing the SRAM module, and is processed like
any other non-SRAM reference.
These bits are useful for power management as detailed in Section 6.2.4, “Power
Management.”
0
V
Valid. A hardware reset clears this bit. When set, this bit enables the SRAM module;
otherwise, the module is disabled.
0 Contents of RAMBAR are not valid
1 Contents of RAMBAR are valid
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
6-3
Static RAM (SRAM)
6.2.2
SRAM Initialization
After a hardware reset, the contents of the SRAM module are undefined. The valid bit of the
RAMBAR is cleared, disabling the module. If the SRAM requires initialization with instructions
or data, the following steps should be performed:
1. Load the RAMBAR mapping the SRAM module to the desired location within the address
space.
2. Read the source data and write it to the SRAM. There are various instructions to support
this function, including memory-to-memory move instructions, or the MOVEM opcode.
The MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16
addresses, so this opcode generally provides maximum performance.
3. After the data has been loaded into the SRAM, it may be appropriate to load a revised
value into the RAMBAR with a new set of attributes. These attributes consist of the
write-protect and address space mask fields.
The ColdFire processor or an external emulator using the debug module can perform these
initialization functions.
6.2.3
SRAM Initialization Code
The following code segment describes how to initialize the SRAM. The code sets the base address
of the SRAM at 0x2000_0000 and then initializes the SRAM to zeros.
RAMBASE
EQU $20000000
;set this variable to $20000000
RAMVALID
EQU $00000001
move.l
#RAMBASE+RAMVALID,D0
;load RAMBASE + valid bit into D0.
movec.l
D0, RAMBAR
;load RAMBAR and enable SRAM
The following loop initializes the entire SRAM to zero
lea.l
RAMBASE,A0
;load pointer to SRAM
move.l
#16384,D0
;load loop counter into D0
clr.l
(A0)+
;clear 4 bytes of SRAM
subq.l
#1,D0
;decrement loop counter
bne.b
SRAM_INIT_LOOP
;if done, then exit; else continue looping
SRAM_INIT_LOOP:
MCF5275 Reference Manual, Rev. 2
6-4
Freescale Semiconductor
Register Description
6.2.4
Power Management
As noted previously, depending on the configuration defined by the RAMBAR, instruction fetch
and operand read accesses may be sent to the SRAM and cache simultaneously. If the access is
mapped to the SRAM module, it sources the read data and the unified cache access is discarded.
If the SRAM is used only for data operands, setting the ASn bits associated with instruction fetches
can decrease power dissipation. Additionally, if the SRAM contains only instructions, masking
operand accesses can reduce power dissipation. Table 6-2 shows some examples of typical
RAMBAR settings.
Table 6-2. Typical RAMBAR Setting Examples
Data Contained in SRAM
RAMBAR[7:0]
Instruction Only
0x2B
Data Only
0x35
Both Instructions And Data
0x21
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
6-5
Static RAM (SRAM)
MCF5275 Reference Manual, Rev. 2
6-6
Freescale Semiconductor
Chapter 7
Clock Module
7.1
Introduction
The clock module allows the MCF5275 to be configured for one of several clocking methods.
Clocking modes include internal frequency modulated phase-locked loop (PLL) clocking with
either an external clock reference or an external crystal reference supported by an internal crystal
amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device
directly. The clock module contains:
•
•
•
•
•
Crystal amplifier and oscillator (OSC)
Frequency Modulated Phase-locked loop (PLL)
Reduced frequency divider (RFD)
Status and control registers
Control logic
NOTE
Throughout this manual, fsys refers to the core frequency and fsys/2
refers to the internal bus frequency.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-1
Clock Module
PLL
1
1
0
x2
ColdFire V2 Core
PLLMODE
fsys
BDM
0
PLLSEL
÷2
DMA
SDRAMC
EIM
PLLREF
0
Chip Selects
1
Watchdog
Oscillator
EXTAL
Clock Module
Peripheral Bus Clock fsys/2
XTAL
PIT
DMA Timers
QSPI
UART
I2C
RNG
MDHA
SKHA
FECs
USB
PWM
GPIO
Figure 7-1. MCF5275 Clock Connections
7.1.1
Block Diagram
Figure 7-2 shows a block diagram of the entire clock module. The PLL block in this diagram is
expanded in detail in Figure 7-3.
MCF5275 Reference Manual, Rev. 2
7-2
Freescale Semiconductor
Introduction
CLKMOD[1:0]
EXTAL
RSTOUT
CLKOUT
LOCKS
XTAL
MFD
PLLMODE
LOCK
External Clock
Reference
Clock
LOCS
PLL
OSC
RFD[2:0]
To Reset
Module
PLLREF
LOCEN
LOLRE
LOCRE
PLL Clock Out
STPMD
Scaled PLL Clock Out
CLKGEN
Internal Clock
Stop Mode
PLLSEL
CLKOUT
DISCLK
Internal
Clocks
STOP MODE
PLLMODE
LOCK
FWKUP
Figure 7-2. Clock Module Block Diagram
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-3
Clock Module
Successive
Approximation
Frequency
Search
FM
Control
EXTAL
XTAL
OSC
PFD/
Charge Pumps
PLL OUT
Filter
ICO
MFD
Bus Interface
CLKMOD[1:0]
Control/Status
Registers
Figure 7-3. PLL Block Diagram
7.1.2
Features
Features of the clock module include:
•
•
•
•
•
•
•
7.1.3
8- to 25-MHz reference crystal oscillator
Current controlled oscillator range from 50 MHz to 166 MHz
Reduced frequency divider for reduced frequency operation without forcing the PLL to
re-lock
Programmable frequency modulation
Support for low-power modes
Self-clocked mode operation
Separate clock out signal
Modes of Operation
The PLL operational mode must be configured during reset. The CLKMOD[1:0] package pins
must be driven to the appropriate state for the desired mode from the time RSTOUT asserts until
it negates. Refer to Table 7-3 for valid states of CLKMOD[1:0]. If CLKMOD[1:0] are not asserted
during reset, the PLL will not default to any mode (so these pins must be hard-tied to power or
ground for desired mode).
The clock module can be operated in normal PLL mode with crystal reference, normal PLL mode
with external reference, 1:1 PLL mode, or external clock mode.
MCF5275 Reference Manual, Rev. 2
7-4
Freescale Semiconductor
Introduction
7.1.3.1
Normal PLL Mode with Crystal Reference
In normal mode with a crystal reference, the PLL receives an input clock frequency from the
crystal oscillator circuit and multiplies the frequency to create the PLL output clock. It can
synthesize frequencies ranging from 4x to 18x the reference frequency and has a post divider
capable of reducing this synthesized frequency without disturbing the PLL. The user must supply
a crystal oscillator that is within the appropriate input frequency range, the crystal manufacture’s
recommended external support circuitry, and short signal route from the device to the crystal. In
normal mode, the PLL can generate a frequency modulated clock or a non-modulated clock
(locked on a single frequency). The modulation rate, modulation depth, output clock divide ratio
(RFD), and whether the PLL is modulating or not can be programmed by writing to the PLL
registers through the bus interface.
7.1.3.2
Normal PLL Mode with External Reference
Same as Section 7.1.3.1, “Normal PLL Mode with Crystal Reference,” except EXTAL is driven
by an external clock generator rather than a crystal oscillator. However, the input frequency range
is the same as the crystal reference. To enter normal mode with external clock Generator reference,
the PLL configuration must be set by following the procedure outlined in Section 7.4.3, “System
Clock Generation.”
7.1.3.3
1:1 PLL Mode
When 1:1 PLL mode is selected, the PLL synthesizes a core clock frequency equal to two times
the input reference frequency (fsys=2×fref and fsys/2=fref) The post divider is not active and the
frequency modulation capability is not available. Further, modulation must not be present on the
input reference clock. The input reference frequency is an external clock reference from a master
MCU CLKOUT pin or other external clock generator source. To enter 1:1 PLL mode, the PLL
must be set by following the procedure outlined in Section 7.4.3, “System Clock Generation.”
NOTE
When configured for 1:1 PLL mode, it is imperative that the
CLKOUT clock divider not be changed from its reset state of
divide-by-2. Increasing or decreasing this divide ratio will produce
unpredictable results from the PLL.
7.1.3.4
External Clock Mode (Bypass Mode)
During external clock mode, the PLL is completely bypassed and the user must supply an external
clock on the EXTAL pin. The external clock is used directly to produce the internal core clocks.
Refer to the Hardware Specification document for external clock input requirements. In external
clock mode, the analog portion of the PLL is disabled and no clocks are generated at the PLL
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-5
Clock Module
output. Consequently, frequency modulation is not available. To enter external clock mode, the
PLL must be set by following the procedure outlined in Section 7.4.3, “System Clock Generation.”
NOTE
XTAL must be tied low in external clock mode when reset is asserted.
If it is not, clocks could be suspended indefinitely.
7.1.3.5
Low-power Mode Operation
This subsection describes the operation of the clock module in low-power and halted modes of
operation. Low-power modes are described in Chapter 8, “Power Management.” Table 7-1 shows
the clock module operation in low-power modes.
Table 7-1. Clock Module Operation in Low-power Modes
Low-power Mode
Clock Operation
Mode Exit
Wait
Clocks sent to peripheral modules only
Exit not caused by clock module, but normal
clocking resumes upon mode exit
Doze
Clocks sent to peripheral modules only
Exit not caused by clock module, but normal
clocking resumes upon mode exit
Stop
All system clocks disabled, but clock module
continues to run
Exit not caused by clock module, but clock
sources are re-enabled and normal clocking
resumes upon mode exit
In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the
CPU, and SRAM are stopped. Each module can disable its clock locally at the module level.
During stop mode, the PLL continues to run. The external CLKOUT signal may be enabled or
disabled when the device enters stop mode, depending on the LPCR[STPMD] bit settings.
The external CLKOUT output pin may be disabled to lower power consumption via the
SYNCR[DISCLK] bit. The external CLKOUT pin function is enabled by default at reset.
7.2
External Signal Descriptions
The clock module signals are summarized in Table 7-2 and a brief description follows. For more
detailed information, refer to Chapter 14, “Signal Descriptions.”
Table 7-2. Signal Properties
Name
Function
EXTAL
Oscillator or clock input
XTAL
Oscillator output
CLKOUT
Internal bus clock output
MCF5275 Reference Manual, Rev. 2
7-6
Freescale Semiconductor
External Signal Descriptions
Table 7-2. Signal Properties (Continued)
Name
7.2.1
Function
CLKMOD[1:0]
Clock mode select inputs
RSTOUT
Reset signal from reset controller
EXTAL
This input is driven by an external clock except when used as a connection to the external crystal
when using the internal oscillator.
7.2.2
XTAL
This output is an internal oscillator connection to the external crystal.
7.2.3
CLKOUT
This output reflects the internal bus clock.
7.2.4
CLKMOD[1:0]
The clock mode is selected during reset and reflected in the PLLMODE, PLLSEL, and PLLREF
bits of the synthesizer status. Once reset is exited, the clock mode cannot be changed.
The clock mode selection during reset configuration is summarized in Table 7-3.
Table 7-3. Clock Mode Selection
Signals
Clock Mode
1
7.2.5
CLKMOD[1]
CLKMOD[0]
0
0
PLL Bypass Mode (external clock mode)
0
1
1:1 Mode1
1
0
Normal mode with external reference
1
1
Normal mode with crystal reference
In 1:1 mode for the MCF5275, fsys = 2×fref_1:1
RSTOUT
The RSTOUT pin is asserted by one of the following:
•
•
Internal system reset signal
FRCRSTOUT bit in the reset control status register (RCR); see Section 10.3.1, “Reset
Control Register (RCR).”
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-7
Clock Module
7.3
Memory Map/Register Definition
The clock module programming model consists of these registers:
•
•
Synthesizer control register (SYNCR), which defines clock operation
Synthesizer status register (SYNSR), which reflects clock status
Table 7-4. Clock Module Memory Map
1
7.3.1
IPSBAR Offset
Register Name
Access1
0x12_0000
Synthesizer Control Register (SYNCR)
S
0x12_0004
Synthesizer Status Register (SYNSR)
S
S = CPU supervisor mode access only.
Register Descriptions
This subsection provides a description of the clock module registers.
7.3.1.1
Synthesizer Control Register (SYNCR)
31
30
R
29
28
27
26
—
25
24
23
MFD[2:0]
22
21
—
20
19
RFD[2:0]
18
17
16
LOCEN LOLRE LOCRE
W
Reset
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
R DISCLK LOLIRQ LOCIRQ RATE
DEPTH
EXP[9:0]
W
Reset
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x0012_0000
Figure 7-4. Synthesizer Control Register (SYNCR)
MCF5275 Reference Manual, Rev. 2
7-8
Freescale Semiconductor
Memory Map/Register Definition
Table 7-5. SYNCR Field Descriptions
Bits
Name
31–27
Reserved
26–24
MFD[2:0]
Description
Multiplication factor divider. The MFD bits control the value of the divider in the PLL
feedback loop. The value specified by the MFD bits establish the multiplication factor
applied to the reference frequency. The bit field encoding is shown in row one of the table
below.
Note: Frequency modulation should be disabled (see DEPTH bits) prior to making a
change to the MFD.
The following table illustrates the system frequency multiplier of the reference
frequency1 in normal PLL mode.
RFD[2:0]
MFD[2:0]
0002
(4x)
001
(6x)(3)
000 (÷ 1)
4
6
001 (÷ 2)
2
010 (÷ 4)3
010
(8x)
011
(10x)
100
(12x)
101
(14x)
110
(16x)
111
(18x)
8
10
12
14
16
18
3
4
5
6
7
8
9
1
3/2
2
5/2
3
7/2
4
9/2
011 (÷ 8)
1/2
3/4
1
5/4
3/2
7/4
2
9/4
100 (÷ 16)
1/4
3/8
1/2
5/8
3/4
7/8
1
9/8
101 (÷ 32)
1/8
3/16
1/4
5/16
3/8
7/16
1/2
9/16
110 (÷ 64)
1/16
3/32
1/8
5/32
3/16
7/32
1/4
9/32
111 (÷ 128)
1/32
3/64
1/16
5/64
3/32
7/64
1/8
9/64
1
2)/2RFD;
fsys = fref × 2(MFD +
fref × 2(MFD + 2) ≤ 166MHz, fsys/2 ≤ 83MHz
MFD = 000 not valid for fref < 3 MHz
3 Default value out of reset
2
23–22
—
Reserved
21–19
RFD
18
LOCEN
Enables the loss-of-clock function. LOCEN does not affect the loss-of-lock function.
0 Loss-of-clock function disabled
1 Loss-of-clock function enabled
Note: In external clock mode, the LOCEN bit has no effect.
17
LOLRE
Loss-of-lock reset enable. This bit determines how the integration module handles a
loss-of-lock indication. When operation in normal or 1:1 mode, the PLL must be locked
before setting the LOLRE bit. Otherwise reset is immediately asserted.
0 Ignore loss-of-clock – no reset
1 Reset on loss-of-lock
Note: In external clock mode, the LOLRE bit has no effect.
Reduced frequency divider field. The binary value written to RFD[2:0] is the PLL frequency
divisor. See table in MFD bit description. Changing RFD[2:0] does not affect the PLL or
cause a relock delay. Changes in clock frequency are synchronized to the next falling edge
of the current core clock. To avoid surpassing the allowable core operating frequency, write
to RFD[2:0] only when the LOCK bit is set.
Note: In external clock mode, the RFD bits have no affect.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-9
Clock Module
Table 7-5. SYNCR Field Descriptions (Continued)
Bits
Name
Description
16
LOCRE
Loss-of-clock reset enable. Determines how the system handles a loss-of-clock condition.
When the LOCEN bit is clear, LOCRE has no effect. If the LOCS flag in SYNSR indicates
a loss-of-clock condition, setting the LOCRE bit causes an immediate reset. To prevent an
immediate reset, the LOCRE bit must be cleared before entering stop mode with the PLL
disabled.
0 No reset on loss-of-clock
1 Reset on loss-of-clock
Note: In external clock mode, the LOCRE bit has no effect.
15
DISCLK
Disable CLKOUT. This bit determines whether CLKOUT is active. When CLKOUT is
disabled it is driven low.
0 CLKOUT driven normally
1 CLKOUT driven low (disabled).
14
LOLIRQ
Loss-of-lock interrupt request. This bit determines if a loss-of-lock is ignored or if an
interrupt is requested. When operating in normal or 1:1 PLL mode, the PLL must be locked
before setting the LOLIRQ bit. Otherwise an interrupt is immediately requested.
0 Ignore loss-of-lock – no interrupt requested
1 Request interrupt on loss-of-lock
Note: In external clock mode, the LOLIRQ bit has no effect.
13
LOCIRQ
Loss-of-clock interrupt request. This bit determines if a loss-of-clock is ignored or if an
interrupt is requested. LOCIRQ has no effect when LOCEN is cleared. If the LOCF flag in
SYNSR indicates a loss-of-clock condition, setting (or having previously set) the LOCIRQ
bit causes an interrupt to be immediately requested.
0 Ignore loss-of-clock – no interrupt requested
1 Request interrupt on loss-of-clock
Note: In external clock mode, the LOCIRQ bit has no effect.
12
RATE
Modulation rate. This bit controls the rate of frequency modulation applied to the core
frequency. Changing the rate by writing to the RATE bit will initiate the FM calibration
sequence.
0 Fm = Fref / 80
1 Fm = Fref / 40
Note: Frequency modulation should be disabled prior to making a change to the RATE.
11–10
DEPTH
Frequency modulation depth and enable.This bit field controls depth and enables the
frequency modulation. When set to a value other than 0x0, the frequency modulation is
automatically enabled.
00 Modulation Depth (% of fsys/2) = 0
01 Modulation Depth (% of fsys/2) = 1.0 ± 0.2
10 Modulation Depth (% of fsys/2) = 2.0 ± 0.2
11 Reserved
Note: Frequency modulation should be disabled prior to making a change to the DEPTH.
9–0
EXP
Expected difference value. Writing to this field enables Frequency Modulation (FM). This
bit field holds the expected value of the difference between the reference and feedback
counters. See Section 7.4.5, “Frequency Modulation Depth Calibration,” for details on how
to calculate this value. Entering FM calibration mode requires the user to program the EXP
field.
MCF5275 Reference Manual, Rev. 2
7-10
Freescale Semiconductor
Memory Map/Register Definition
7.3.1.2
Synthesizer Status Register (SYNSR)
In the SYNSR, only the LOLF and LOCF flag bits are writeable. Writes to bits other than LOLF
and LOCF have no effect.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
6
5
4
2
1
0
—
W
Reset
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
R
—
LOLF LOC MODE
1
3
1
2
PLL PLL LOCKS LOCK LOCF CAL CAL
SEL1 REF1
DONE PASS
W
Reset
0
0
0
0
0
Address
0
0
0
See Note 1
See
Note 2
0
0
0
IPSBAR + 0x0012_0004
1
2
Reset state determined during reset configuration
Reset state determined during reset
Figure 7-5. Synthesizer Status Register (SYNSR)
Table 7-6. SYNSR Field Descriptions
Bits
Name
Description
31–10
—
9
LOLF
Loss-of-lock flag. This bit provides the interrupt request flag. To clear the flag, write a 1 to
this bit. Writing 0 has no effect.
This flag will not be set and an interrupt will not be requested under any one of the following
conditions: (1) loss-of-lock caused by system reset, (2) writing to the SYNCR to modify the
MFD bits, or (3) enabling frequency modulation. The only way to clear this flag is to reset
the part or write a 1 to this bit.
0 Interrupt service not requested
1 Interrupt service requested
8
LOC
Loss-of-clock status. This bit is an indication of whether a loss-of-clock condition is present
when operating in normal and 1:1 PLL modes. If LOC = 0, the system clocks are operating
normally. If LOC = 1, the system clocks have failed due to a reference failure or a PLL
failure. If the read of the LOC bit and the loss-of-clock condition occur simultaneously, the
bit does not reflect the current loss-of-clock condition. If a loss-of-clock condition occurs
which sets this bit and the clocks later return to normal, this bit will be cleared.
A loss-of-clock condition can only be detected if LOCEN = 1. See Section 7.4.2, “Clock
Operation During Reset.”
Note: LOC is always cleared in external clock mode.
0 Clocks are operating normally
1 Clocks are not operating normally.
Reserved
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-11
Clock Module
Table 7-6. SYNSR Field Descriptions (Continued)
Bits
7
Name
Description
PLLMODE Clock mode. This bit is determined at reset and indicates which clock mode the system is
utilizing (see Table 7-7). See Section 7.4.3, “System Clock Generation,” for details on how
to configure the system clock mode during reset.
0 External clock mode
1 PLL clock mode
6
PLLSEL
PLL mode select. This bit is determined at reset and indicates which mode the PLL
operates in. PLLSEL is cleared in 1:1 PLL mode and external clock mode. See Chapter 10,
“Reset Controller Module,” for details on how to configure the system clock mode during
reset.
1 Normal PLL mode (see Table 7-7)
0 1:1 PLL mode
5
PLLREF
PLL clock reference source. Configured at reset and reflects the PLL reference source in
normal PLL mode as shown in Table 7-7.
1 Crystal clock reference
0 External clock reference
4
LOCKS
Sticky indication of PLL lock status. The lock detect function sets the LOCKS bit when the
PLL achieves lock after:
• A system reset
• A write to SYNCR that changes the MFD[2:0] bits
• Frequency modulation is enabled
When the PLL loses lock, LOCKS is cleared. When the PLL relocks, LOCKS remains
cleared until one of the three listed events occurs.
Furthermore, reading the LOCKS bit at the same time that the PLL loses lock does not
reflect the current loss-of-lock condition.
In external clock mode, LOCKS remains cleared after reset. In normal PLL mode and 1:1
PLL mode, LOCKS is set after reset.
0 PLL loss-of-lock since last system reset or MFD change or currently not locked due to
exit from STOP with FWKUP set
1 No unintentional PLL loss-of-lock since last system reset or MFD change
3
LOCK
PLL lock status bit. Set when the PLL is locked. PLL lock occurs when the synthesized
frequency is within approximately 0.75 percent of the programmed frequency. The PLL
loses lock when a frequency deviation of greater than approximately 1.5 percent occurs.
Reading the LOCK bit at the same time that the PLL loses lock or acquires lock does not
reflect the current condition of the PLL. The power-on reset circuit uses the LOCK bit as a
condition for releasing reset.
If operating in external clock mode, LOCK remains cleared after reset.
0 PLL not locked
1 PLL locked
2
LOCF
Loss-of-clock flag. This bit provides the interrupt request flag. Write a 1 to this bit to clear
the flag. Writing 0 has no effect. Asserting reset will clear the flag. This flag is sticky in the
sense that if clocks return to normal after the flag has been set, the bit will remain set until
cleared by either writing 1 or asserting reset.
0 Interrupt service not requested
1 Interrupt service request
MCF5275 Reference Manual, Rev. 2
7-12
Freescale Semiconductor
Functional Description
Table 7-6. SYNSR Field Descriptions (Continued)
Bits
Name
Description
1
CALDONE Calibration complete. This bit indicates whether the calibration sequence has been
completed since the last time frequency modulation was enabled. If CALDONE = 0, the
calibration sequence is either in progress or modulation is disabled. If CALDONE=1 then
the calibration sequence has been completed, and frequency modulation is operating.
0 Calibration not complete
1 Calibration complete
0
CALPASS
Calibration passed. The CALPASS bit tells whether the calibration routine was successful.
CALPASS CALDONE
0
1
unsuccessful
1
1
successful
When the calibration routine is initiated, CALPASS is set and remains set until either
modulation is disabled (by clearing the DEPTH bits in the SYNCR) or a failure occurs within
the frequency modulation calibration sequence.
0 Calibration unsuccessful
1 Calibration successful
Table 7-7. System Clock Modes
PLLMODE:PLLSEL:PLLREF
7.4
Clock Mode
000
External clock mode (bypass PLL)
100
1:1 PLL mode
110
Normal PLL mode with external clock reference
111
Normal PLL mode with crystal reference
Functional Description
This subsection provides a functional description of the clock module.
7.4.1
System Clock Modes
The system clock source is determined during reset (seeTable 7-3 and Table 9-11). The values of
the CLKMOD signals are latched during reset and are of no importance after reset is negated. If
CLKMOD1 or CLKMOD0 is changed during a reset other than power-on reset, the internal clocks
may glitch as the system clock source is changed between external clock mode and PLL clock
mode. Whenever CLKMOD1 or CLKMOD0 is changed in reset, an immediate loss-of-lock
condition occurs.
Table 7-8 shows the clock-out frequency to clock-in frequency relationships for the possible
system clock modes. Refer to Section 7.1.3, “Modes of Operation,” for details on each mode.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-13
Clock Module
Table 7-8. Clock Out and Clock In Relationships
System Clock Mode
Normal PLL clock mode
PLL Options1
- without frequency modulation
enabled:
2f ref × ( MFD + 2 )
f sys = -----------------------------------------RFD
2
Cross-Reference
Section 7.1.3.1, “Normal PLL Mode with
Crystal Reference” and Section 7.1.3.2,
“Normal PLL Mode with External Reference”
- with frequency modulation:
f ref × ( MFD + 2 ) ± ∆F m
f sys = -------------------------------------------------------RFD
2
1:1 PLL clock mode
fsys/2 = 2 × fref_1:1
Section 7.1.3.3, “1:1 PLL Mode”
External clock mode
fsys/2 = fref
Section 7.1.3.4, “External Clock Mode
(Bypass Mode)”
1
7.4.2
fref = input reference frequency
fsys/2 = CLKOUT frequency
MFD ranges from 0 to 7
RFD ranges from 0 to 7
fref in external clock mode must not exceed 166MHz
∆F m = f sys/2 × k where k = 2±0.6, 4±0.6, or 6±0.6%.
Clock Operation During Reset
In external clock mode, the system is static and does not recognize reset until clocks are applied
to EXTAL and XTAL.
In PLL mode, the PLL operates in self-clocked mode (SCM) during reset until the input reference
clock to the PLL begins operating within the limits given in the electrical specifications.
If a PLL failure causes a reset, the system enters reset using the reference clock. Then the system
clock source changes to the PLL operating in SCM. If SCM is not functional, the system becomes
static. Alternately, if the LOCEN bit in SYNCR is cleared when the PLL fails, the system becomes
static. If external reset is asserted, the system cannot enter reset unless the PLL is capable of
operating in SCM.
7.4.2.1
Power-On Reset (POR)
When a POR is detected, the PLL registers will be initialized to their default state. The PLL will
not begin operating until the VDDPLL POR signal has negated. At this point, the PLL will begin
operating in SCM until a valid reference clock becomes present as indicated by the loss-of-clock
circuit. Refer to Section 10.4.1.1, “Power-On Reset,” for more information.
MCF5275 Reference Manual, Rev. 2
7-14
Freescale Semiconductor
Functional Description
7.4.2.2
External Reset
Once POR for both the device and the VDDPLL supplies have negated, the PLL will begin its lock
detect algorithm. However, if a valid reference is not present, the PLL will continue to operate in
SCM until one is present. The system will not come out of reset until a valid reference is present
and the PLL has acquired lock at the default MFD (see Table 7-5 for the default MFD value).
Following the initial lock with the default MFD, the MFD in the SYNCR may be modified for the
desired operating frequency. If the PLL is not able to lock due to an MFD and crystal frequency
combination that attempts to force the current controlled oscillator (ICO) outside of its operating
range, reset will not negate.
Refer to Section 10.4.1.1, “Power-On Reset,” for more information.
NOTE
When running in an unlocked state, the clocks generated by the PLL
are not guaranteed to be stable and may exceed the maximum
specified frequency of the device. It is always recommended that the
RFD be used as described in Section 7.4.3, “System Clock
Generation,” to insulate the system from any potential frequency
overshoot of the PLL clocks.
7.4.3
System Clock Generation
In normal PLL clock mode, the default core frequency is one and a half times (1.5x) the reference
frequency after reset. The RFD[2:0] and MFD[2:0] bits in the SYNCR select the frequency
multiplier with default values of RFD = 0b010 (÷4) and MFD = 0b001 (×6) (see Table 7-5).
When programming the PLL, do not exceed the maximum system clock frequency listed in the
electrical specifications. Use this procedure to accommodate the frequency overshoot that occurs
when the MFD bits are changed. If frequency modulation is going to be enabled, the maximum
allowable frequency must be reduced by the programmed ∆Fm.
1. Determine the appropriate value for the MFD and RFD fields in the SYNCR; remember to
include the ∆Fm if frequency modulation is enabled. The amount of jitter in the system
clocks can be minimized by selecting the maximum MFD factor that can be paired with an
RFD factor to provide the required frequency. See Table 7-5.
2. Write a value of RFD factor (from step 1) + 1 to the RFD field of the SYNCR.
3. If frequency modulation is enabled (by writing to the EXP bit field), disable frequency
modulation by writing 0x0 to the DEPTH field of the SYNCR.
4. If programming the MFD, write the MFD value from step 1 to the SYNCR. If enabling
frequency modulation, skip this step.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-15
Clock Module
5. Monitor the LOCK flag in SYNSR. When the PLL achieves lock, write the RFD value
from step 1 to the RFD field of the SYNCR. This changes the system clocks frequency to
the required frequency.
6. If frequency modulation was enabled initially, it can be re-enabled following the steps
listed in Section 7.4.4, “Programming the Frequency Modulation.”
NOTE
Keep the maximum system clock frequency below the limit given in
the Electrical Characteristics.
7.4.4
Programming the Frequency Modulation
Frequency modulation is useful for spreading the energy over a broader frequency spectrum in
order to reduce EMI.
In normal PLL clock mode, the default synthesis mode is without frequency modulation enabled.
When frequency modulation (FM) is enabled three parameters must be set to generate the desired
level of modulation: the RATE, DEPTH, and EXP bit fields of the SYNCR. RATE and DEPTH
determine the modulation rate and the modulation depth. The EXP field controls the FM
calibration routine described in Section 7.4.5, “Frequency Modulation Depth Calibration.” The
equation that shows how to obtain the values to be programmed for EXP is as follows (see
Section 7.4.5, “Frequency Modulation Depth Calibration,” for details):
( 2× ( MFD + 2 )×M×P )
EXP = -------------------------------------------------------100
Figure 7-6 illustrates the affects of the parameters and the modulation waveform built into the
modulation hardware. The modulation waveform is always a triangle wave and its shape is not
programmable.
Note, the modulation rates given are specific to a reference frequency of 8 MHz. Fmod = Fref ⁄ Q
where Q = {40,80} giving modulation rates of 200 kHz, and 100 kHz. Therefore, the utilization of
a non 8 MHz reference will result in scaled modulation rates.
The following steps should be used for proper programming of the frequency modulation mode.
These steps ensure proper operation of the calibration routine and prevent frequency overshoot
from the sequence.
1. Determine the appropriate value for the EXP field, based upon the selected MFD and
desired depth, in the synthesizer control register (SYNCR), as shown in the equation above.
Write this value to the EXP field of the SYNCR. The MFD should be programmed to the
appropriate value prior to Step 2.
2. Disable modulation by clearing the DEPTH field in the SYNCR.
3. Monitor LOCK bit. Do not proceed until the PLL is locked in non-modulation mode.
MCF5275 Reference Manual, Rev. 2
7-16
Freescale Semiconductor
Functional Description
4. Write a value of RFD = RFD + 1 to the RFD field of the SYNCR to ensure the maximum
system frequency is not exceeded during the calibration routine.
5. Program the desired modulation rates and depths to the RATE and DEPTH fields in the
SYNCR. This action initiates the calibration sequence.
6. Allow time for the calibration sequence. Wait for the PLL to lock (the LOCK bit to set in
the SYNSR). At this time CALDONE should be asserted. CALPASS will be asserted if
the calibration was successful. If not, the calibration can be re-initiated by repeating from
step 2. When the PLL achieves lock, write the desired RFD value.
Please note that the frequency modulation system is dependent upon several factors. The
accuracies of the VDDPLL/VSSPLL voltage, of the crystal oscillator frequency, and of the
manufacturing variation.
For example, if a 5% accurate supply voltage is utilized, then a 5% modulation depth error will
result. If the crystal oscillator frequency is skewed from 8MHz, the resulting modulation
frequency will be proportionally skewed. Finally, the error due to the manufacturing and
environment variation alone can cause the frequency modulation depth error to be greater than
20%.
f
Fmax
∆Fm
t
∆Fm
Fmin
1
∆t = -----------F mod
Fmax = fsys/2 + {1%, 2%}
Fmin = fsys/2 - {1%, 2%}
Fmod = Fref/Q where Q = {40, 80}
Figure 7-6. Frequency Modulation Waveform
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-17
Clock Module
7.4.5
Frequency Modulation Depth Calibration
The frequency modulation calibration system tunes a reference current into the modulation D/A
so that the modulation depth (Fmax and Fmin) remains within specification. Frequency modulation
should be disabled prior to making a change to either the MFD, DEPTH, or RATE. Upon enabling
frequency modulation a new calibration sequence is performed. A change to MFD, DEPTH, or
RATE while in modulation will invalidate calibration results.
Entering the FM calibration mode requires the user to program the EXP field of the SYNCR.
Values for EXP can be found using the following equation:
( 2× ( MFD + 2 )×M×P )
EXP = -------------------------------------------------------100
Example:
For the value of MFD = 4, the number of reference clock cycles to be counted (M) would
be 480. Refer to Figure 7-8 for a complete list of values to be used for the variable (M)
based on MFD setting. To obtain a percent modulation (P) of 1%, the EXP field would have
EXP = ( 2× ( 4 + 2 )×480×1 ) ⁄ 100 = 57.6
to be set at:
Rounding this value to the closest integer yields the value of 58 that should be entered into
the EXP field for this example.
This routine will correct for process variations, but as temperature can change after the calibration
has been performed, variation due to temperature drift is not eliminated. This system is also
voltage dependent, so if supply voltages change after the sequence takes place, error incurred will
not be corrected. The calibration system reuses the two counters in the lock detect circuit: the
reference and feedback counters. The reference counter is still clocked by the reference clock, but
the feedback counter is clocked by the ICO clock.
When the calibration routine is initiated (writing to the DEPTH bits), the CALPASS status bit is
immediately set and the CALDONE status bit is immediately cleared.
When calibration is induced the ICO is given time to settle. Then both the feedback and reference
counters start counting. Full ICO clock cycles are counted by the feedback counter during this time
to give the initial center frequency count. When the reference counter has counted to the
programmed number of reference count cycles, the input to the feedback counter is disabled and
the result is placed in the COUNT0 register. The calibration system then enables modulation at
programmed ∆Fm. The ICO is given time to settle. Both counters are reset and restarted. The
feedback counter begins to count full ICO clock cycles again to obtain the delta-frequency count.
When the reference counter has counted to the new programmed number of reference count cycles,
the feedback counter is stopped again.
The delta-frequency count minus the center frequency count (COUNT0) results in a delta count
proportional to the reference current into the modulation D/A. That delta count is subtracted from
the expected value given in the EXP field of the SYNCR register resulting in an error count. The
MCF5275 Reference Manual, Rev. 2
7-18
Freescale Semiconductor
Functional Description
sign of this error count determines the direction taken by the calibration D/A to update the
calibration current. After obtaining the error count for the present iteration, both counters are
cleared. The stored count of COUNT0 is preserved while a new feedback count is obtained, and
the process to determine the error count is repeated. The calibration system repeats this process
eight times, once for each bit of the calibration D/A.
After the last decision is made the CALDONE bit of the SYNSR is set. If an error occurs during
the calibration routine, then CALPASS is immediately cleared. If the routine completed
successfully then CALPASS remains set.
Figure 7-7 shows a block diagram of the calibration circuitry and its associated registers.
Figure 7-8 shows a flow chart showing the steps taken by the calibration circuit.
Count 0
Reference Counter
Expected (EXP)
Error (ERR)
13
Control
13
10
ICO Counter
13
A
B
10
10
D
C
A–B=
delta
count
C–D=error count
Figure 7-7. FM Auto-Calibration Data Flow
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-19
Clock Module
Enter Calibration
Mode; Set PCALPASS=1
For MFD=0,1: M=960.
For MFD=2,3,4: M=480.
For MFD=5,6,7: M=240.
A
YES
N=0?
Count M reference
clock cycles. Store value of
feedback counter in CAL0.
NO
N=N-1
Enable FM. N=7.
CAL[N] = 1
CALDONE=1
Allow system 3×384
reference counts to settle.
DONE
Count M reference
clock cycles. CALX = value in
feedback counter.
let DIFF=CALX-CAL0
NO
DIFF>0
PCALPASS=0
YES
let ERR=DIFF-EXP
ERR>0
YES
CAL[N]=0
NO
A
Figure 7-8. FM Auto-calibration Flow Chart
MCF5275 Reference Manual, Rev. 2
7-20
Freescale Semiconductor
Functional Description
7.4.6
PLL Operation
In PLL mode, the PLL synthesizes the system clocks. The PLL can multiply the reference clock
frequency by 4x to 18x, provided that the system clock frequency remains within the range listed
in the electrical specifications. For example, if the reference frequency is 8 MHz, the PLL can
synthesize frequencies of 32 MHz to 144 MHz. In addition, the RFD can reduce the system
frequency by dividing the output of the PLL. The RFD is not in the feedback loop of the PLL, so
changing the RFD divisor does not affect PLL operation. Finally, the PLL can be frequency
modulated to reduce electromagnetic interference often associated with clock circuitry.
Figure 7-9 shows the external support circuitry for the crystal oscillator with example component
values. Actual component values depend on crystal specifications.
C2
C1
VSSPLL
EXTAL
XTAL
ON-CHIP
8-MHz Crystal Configuration
C1 = C2 = 16 pF
RF ≥ 1 MΩ
RS = 470 Ω
VSSPLL
RS
RF
Figure 7-9. Crystal Oscillator Example
The following subsections describe each major block of the PLL. Refer to Figure 7-10 to see how
these functional sub-blocks interact.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-21
Clock Module
Lock
Detect
LOCK
FM
Modulation
Control
Loss of
Clock Detect
LOC
Charge
Pump
EXTAL
reference
clock
feedback
up
PFD
Charge
Pump
down
ICO clkout
Filter
ICO
VDDPLL / VSSPLL
MFD
VDDI / VSSI
Figure 7-10. Frequency Modulated PLL Block Diagram
7.4.6.1
Phase and Frequency Detector (PFD)
The PFD is a dual-latch phase-frequency detector. It compares both the phase and frequency of the
reference and feedback clocks. The reference clock comes from either the crystal oscillator or an
external clock source.
The feedback clock comes from one of the following:
•
•
•
CLKOUT in 1:1 PLL mode
ICO output divided by two if CLKOUT is disabled in 1:1 PLL mode
ICO output divided by the MFD in normal PLL mode
When the frequency of the feedback clock equals the frequency of the reference clock, the PLL is
frequency-locked. If the falling edge of the feedback clock lags the falling edge of the reference
clock, the PFD pulses the UP signal. If the falling edge of the feedback clock leads the falling edge
of the reference clock, the PFD pulses the DOWN signal. The width of these pulses relative to the
reference clock depends on how much the two clocks lead or lag each other. Once phase lock is
achieved, the PFD continues to pulse the UP and DOWN signals for very short durations during
each reference clock cycle. These short pulses continually update the PLL and prevent the
frequency drift phenomenon known as dead-banding. “Dead-band” is a term used to describe the
minimum amount of phase error between the reference and feedback clocks that a phase detector
cannot correct.
MCF5275 Reference Manual, Rev. 2
7-22
Freescale Semiconductor
Functional Description
7.4.6.2
Charge Pump/Loop Filter
In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode the current magnitude of
the charge pump varies with the MFD as shown in Table 7-9.
Table 7-9. Charge Pump Current and MFD in Normal Mode Operation
Charge Pump Current
MFD
1X
0 ≤ MFD < 2
2X
2 ≤ MFD < 6
4X
6 ≤ MFD
The UP and DOWN signals from the PFD control whether the charge pump applies or removes
charge, respectively, from the loop filter. The filter is integrated on the chip.
7.4.6.3
Current Controlled Oscillator (ICO)
The current into the ICO controls the frequency of the ICO output. The frequency-to-current
relationship (ICO gain) is positive.
7.4.6.4
Multiplication Factor Divider (MFD)
When the PLL is not in 1:1 PLL mode, the MFD divides the output of the ICO and feeds it back
to the PFD. The PFD controls the ICO frequency via the charge pump and loop filter such that the
reference and feedback clocks have the same frequency and phase. Thus, the frequency of the
input to the MFD, which is also the output of the ICO, is the reference frequency multiplied by the
same amount that the MFD divides by. For example, if the MFD divides the ICO frequency by six,
the PLL is frequency locked when the ICO frequency is six times the reference frequency. The
presence of the MFD in the loop allows the PLL to perform frequency multiplication, or synthesis.
In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication factor is two.
7.4.6.5
PLL Lock Detection
The lock detect logic monitors the reference frequency and the PLL feedback frequency to
determine when frequency lock is achieved. Phase lock is inferred by the frequency relationship,
but is not guaranteed. The LOCK flag in the SYNSR reflects the PLL lock status. A sticky lock
flag, LOCKS, is also provided.
The lock detect function uses two counters. One is clocked by the reference and the other is
clocked by the PLL feedback. When the reference counter has counted N cycles, its count is
compared to that of the feedback counter. If the feedback counter has also counted N cycles, the
process is repeated for N + K counts. Then, if the two counters still match, the lock criteria is
relaxed by one count and the system is notified that the PLL has achieved frequency lock.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-23
Clock Module
After lock is detected, the lock circuit continues to monitor the reference and feedback frequencies
using the alternate count and compare process. If the counters do not match at any comparison
time, then the LOCK flag is cleared to indicate that the PLL has lost lock. At this point, the lock
criteria is tightened and the lock detect process is repeated.
The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL
tries to lock. Alternating between tight and relaxed lock criteria prevents the lock detect function
from randomly toggling between locked and non-locked status due to phase sensitivities.
Figure 7-11 shows the sequence for detecting locked and non-locked conditions.
In external clock mode, the PLL is disabled and cannot lock.
Start
with Tight Lock
Criteria
Loss-of-Lock Detected
Set Tight Lock Criteria
and Notify System of Loss
of Lock Condition
Reference Count
Reference Count
≠ Feedback Count
≠ Feedback Count
Count N
Reference Cycles
and Compare
Number of Feedback
Cycles Elapsed
Reference Count =
Feedback Count = N
In Same Count/Compare Sequence
Lock Detected.
Set Relaxed Lock
Condition and Notify
System of Lock
Condition
Count N + K
Reference Cycles
and Compare Number
of Feedback Cycles
Elapsed
Reference Count =
Feedback Count = N + K
IN Same Count/Compare Sequence
Figure 7-11. Lock Detect Sequence
7.4.6.6
PLL Loss-of-Lock Conditions
Once the PLL acquires lock after reset, the LOCK and LOCKS flags are set. If the MFD is
changed, or if an unexpected loss-of-lock condition occurs, the LOCK and LOCKS flags are
cleared. While the PLL is in the non-locked condition, the system clocks continue to be sourced
from the PLL as the PLL attempts to relock. Consequently, during the relocking process, the
system clocks frequency is not well defined and may exceed the maximum system frequency,
violating the system clock timing specifications.
However, once the PLL has relocked, the LOCK flag is set. The LOCKS flag remains cleared if
the loss-of-lock is unexpected. The LOCKS flag is set when the loss-of-lock is caused by changing
MCF5275 Reference Manual, Rev. 2
7-24
Freescale Semiconductor
Functional Description
MFD. If the PLL is intentionally disabled during stop mode, then after exit from stop mode, the
LOCKS flag reflects the value prior to entering stop mode once lock is regained.
7.4.6.7
PLL Loss-of-Lock Reset
If the LOLRE bit in the SYNCR is set, a loss-of-lock condition asserts reset. Reset reinitializes the
LOCK and LOCKS flags. Therefore, software must read the LOL bit in the reset status register
(RSR) to determine if a loss-of-lock caused the reset. See Section 10.3.2, “Reset Status Register
(RSR).”
To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock.
In external clock mode, the PLL cannot lock. Therefore, a loss-of-lock condition cannot occur, and
the LOLRE bit has no effect.
7.4.6.8
PLL Loss-of-Lock Interrupt Request
The PLL provides the ability to request an interrupt when a loss-of-lock condition occurs by
programming the LOLIRQ bit in the SYNCR. An interrupt is requested by the PLL if LOLIRQ is
set.
In external clock mode, the PLL cannot lock. Therefore, a loss-of-lock condition cannot occur, and
the LOLIRQ bit has no effect.
7.4.6.9
Loss-of-Clock Detection
The LOCEN bit in the SYNCR enables the loss-of-clock detection circuit to monitor the input
clocks to the phase and frequency detector (PFD). When either the reference or feedback clock
frequency falls below the minimum frequency (see electrical specification for this value), the
loss-of-clock circuit sets the sticky LOCF bit, and non-sticky LOC bit, in the SYNSR.
In external clock mode, the loss-of-clock circuit is disabled.
7.4.6.10 Loss-of-Clock Reset
The clock module can assert a reset when a loss-of-clock or loss-of-lock occurs. When a
loss-of-clock condition is recognized, reset is asserted if the LOCRE bit in SYNCR is set. The
LOCS bit in SYNSR is cleared after reset. Therefore, the LOC bit must be read in the RSR to
determine that a loss-of-clock condition occurred. LOCRE has no effect in external clock mode.
To exit reset in PLL mode, the reference must be present, and the PLL must acquire lock.
Reset initializes the clock module registers to a known startup state as described in Section 7.3,
“Memory Map/Register Definition.”
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-25
Clock Module
7.4.6.11 Loss-of-Clock Interrupt Request
When a loss-of-clock condition is detected, the PLL will request an interrupt if the LOCIRQ bit in
the SYNCR is set. The LOCIRQ bit has no affect in external clock mode or if LOCEN is cleared.
7.4.6.12 Alternate Clock Selection
Depending on which clock source fails, the loss-of-clock circuit switches the system clocks source
to the remaining operational clock. The alternate clock source generates the system clocks until
reset is asserted. As Table 7-10 shows, if the reference fails, the PLL goes out of lock and into
self-clocked mode (SCM). The PLL remains in SCM until the next reset. When the PLL is
operating in SCM, the system frequency depends on the value in the RFD field. The SCM system
frequency stated in electrical specifications assumes that the RFD has been programmed to binary
000. If the loss-of-clock condition is due to PLL failure, the PLL reference becomes the system
clocks source until the next reset, even if the PLL regains and relocks.
Table 7-10. Loss-of-Clock Summary
1
Clock
Mode
System Clock Source
Before Failure
Reference Failure Alternate
Clock Selected by LOC
Circuit1 Until Reset
PLL Failure Alternate
Clock Selected by LOC
Circuit Until Reset
PLL
PLL
PLL self-clocked mode
PLL reference
External
External clock
None
NA
The LOC circuit monitors the reference and feedback inputs to the PFD. See Figure 7-10.
A special loss-of-clock condition occurs when both the reference and the PLL fail. The failures
may be simultaneous, or the PLL may fail first. In either case, the reference clock failure takes
priority and the PLL attempts to operate in SCM. If successful, the PLL remains in SCM until the
next reset. If the PLL cannot operate in SCM, the system remains static until the next reset. Both
the reference and the PLL must be functioning properly to exit reset.
7.4.6.13 Loss-of-Clock in Stop Mode
Table 7-11 shows the resulting actions for a loss-of-clock in Stop Mode when the device is being
clocked by the various clocking methods.
PLL
OSC
FWKUP
X
X
X
X
X
—
—
Lose reference
clock
MODE
Out
EXT
Stuck
0
0
—
LOCS
LOLRE
X
PLL Action
During Stop
LOCK
LOCRE
EXT
Expected
PLL
Action at
Stop
LOCKSS
MODE
In
LOCEN
Table 7-11. Stop Mode Operation (Sheet 1 of 5)
Comments
0
—
—
MCF5275 Reference Manual, Rev. 2
7-26
Freescale Semiconductor
Functional Description
0
Off Off 0
NRM
NRM
NRM
X
0
0
0
0
0
0
0
0
Off Off 1
Off On 0
Off On 1
MODE
Out
Regain
NRM
No regain
Stuck
Lose lock,
f.b. clock,
reference
clock
Regain clocks, but SCM–>
don’t regain lock unstable
NRM
0–>‘LK 0–>1 1–>‘LC Block LOCS and
LOCKS until
clock and lock
respectively
regain; enter
SCM regardless
of LOCEN bit
until reference
regained
No reference
clock regain
SCM–>
0–>
No f.b. clock
regain
Stuck
Regain
NRM
Lose reference
clock or no lock
regain
Stuck
Lose reference
clock,
regain
NRM
‘LK
‘LC
Block LOCKS
from being
cleared
No lock regain
Unstable
NRM
0–>‘LK 0–>1 ‘LC
Block LOCKS
until lock
regained
Lose reference
clock or no f.b.
clock regain
Stuck
Lose reference
clock, regain
Unstable
NRM
Lose lock
1
Comments
Lose lock,
f.b. clock,
reference
clock
Lose lock
‘LK
LOCS
PLL
0
PLL Action
During Stop
LOCK
LOLRE
0
Expected
PLL
Action at
Stop
LOCKSS
LOCRE
NRM
OSC
MODE
In
LOCEN
FWKUP
Table 7-11. Stop Mode Operation (Sheet 2 of 5) (Continued)
—
—
0–>
—
‘LK
—
1
—
—
‘LC
—
1–>
—
‘LC
—
1
—
Block LOCS and
LOCKS until
clock and lock
respectively
regain; enter
SCM regardless
of LOCEN bit
Block LOCKS
from being
cleared
—
—
0–>‘LK 0–>1 ‘LC
LOCS not set
because
LOCEN = 0
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-27
Clock Module
0
On On 0
—
—
MODE
Out
NRM
‘LK
Lose lock or clock Stuck
NRM
0
0
0
On On 1
NRM
X
X
1
Off X
X
NRM
0
0
1
On On X
—
NRM
1
1
0
0
0
0
Off Off 0
1
‘LC
Lose clock and
lock, regain
NRM
0
1
‘LC
NRM
‘LK
1
‘LC
Lose lock
Unstable
NRM
0
0–>1 ‘LC
Lose lock, regain
NRM
0
1
Lose clock
Stuck
—
Off On 0
—
0–>1 ‘LC
Lose clock, regain NRM
with lock
0
1
RESET
—
Lose lock,
f.b. clock
—
0
RESET
NRM
—
‘LK
Regain
NRM
No regain
Stuck
Regain
NRM
No f.b. clock or
lock regain
Stuck
Lose reference
clock
SCM
‘LK
1
—
‘LC
—
1
Reset
immediately
REF not entered
during stop;
SCM entered
during stop only
during oscillator
startup
—
‘LC
—
0
Reset
immediately
‘LC
1
—
0
—
—
—
‘LK
‘LC
—
—
LOCS not set
because
LOCEN = 0
‘LC
Lose clock, regain Unstable
without lock
NRM
—
Lose lock,
f.b. clock,
reference
clock
—
0
Lose lock or clock RESET
NRM
—
NRM
—
Comments
‘LC
Lose lock, regain
—
Lose lock,
f.b. clock,
reference
clock
1
LOCS
PLL
0
PLL Action
During Stop
LOCK
LOLRE
0
Expected
PLL
Action at
Stop
LOCKSS
LOCRE
NRM
OSC
MODE
In
LOCEN
FWKUP
Table 7-11. Stop Mode Operation (Sheet 3 of 5) (Continued)
REF mode not
entered during
stop
—
1
Wakeup without
lock
MCF5275 Reference Manual, Rev. 2
7-28
Freescale Semiconductor
Functional Description
0
Off On 1
NRM
NRM
NRM
1
1
1
0
0
0
0
0
1
On On 0
On On 1
On On X
NRM
1
1
X
Off X
X
NRM
1
1
0
On On 0
Lose lock,
f.b. clock
Unstable
NRM
No f.b. clock
regain
Stuck
Lose reference
clock
SCM
0
0
1
NRM
‘LK
1
‘LC
Lose reference
clock
SCM
0
0
1
Wakeup without
lock
Lose f.b. clock
REF
0
X
1
Wakeup without
lock
Lose lock
Stuck
Lose lock, regain
NRM
0
1
‘LC
—
NRM
‘LK
1
‘LC
Lose reference
clock
SCM
0
0
1
Wakeup without
lock
Lose f.b. clock
REF
0
X
1
Wakeup without
lock
Lose lock
Unstable
NRM
0
0–>1 ‘LC
NRM
‘LK
1
—
—
—
—
—
0–>‘LK 0–>1 ‘LC
Comments
Regain f.b. clock
—
Lose lock,
f.b. clock,
reference
clock
MODE
Out
LOCS
PLL
0
PLL Action
During Stop
LOCK
LOLRE
1
Expected
PLL
Action at
Stop
LOCKSS
LOCRE
NRM
OSC
MODE
In
LOCEN
FWKUP
Table 7-11. Stop Mode Operation (Sheet 4 of 5) (Continued)
—
—
—
REF mode not
entered during
stop
—
—
Wakeup without
lock
—
‘LC
Lose lock or clock RESET
—
—
—
Reset
immediately
RESET
—
—
—
Reset
immediately
RESET
—
NRM
‘LK
1
‘LC
Lose clock
RESET
—
—
—
Lose lock
Stuck
—
—
—
Lose lock, regain
NRM
0
1
Reset
immediately
‘LC
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
7-29
Clock Module
0
On On 1
NRM
1
1
1
On On X
—
—
—
MODE
Out
NRM
1
0
0
X
X
X
—
Lose lock
Unstable
NRM
0
0–>1 ‘LC
Lose lock, regain
NRM
0
1
‘LC
—
NRM
‘LK
1
‘LC
—
—
—
0
X
1
—
1
0
0
On On 0
—
—
Lose reference
clock
REF
—
Stuck
SCM
SCM
—
—
0
—
—
0
Comments
‘LC
RESET
Lose reference
clock
SCM
1
Lose clock
Lose clock or lock RESET
REF
‘LK
LOCS
PLL
1
PLL Action
During Stop
LOCK
LOLRE
1
Expected
PLL
Action at
Stop
LOCKSS
LOCRE
NRM
OSC
MODE
In
LOCEN
FWKUP
Table 7-11. Stop Mode Operation (Sheet 5 of 5) (Continued)
Reset
immediately
Reset
immediately
—
1
Wakeup without
lock
Note:
PLL = PLL enabled during STOP mode.
OSC = Oscillator enabled during STOP mode.
MODES
NRM = normal PLL crystal clock reference or normal PLL external reference or PLL 1:1 mode. During PLL 1:1 or normal external
reference mode, the oscillator is never enabled. Therefore, during these modes, refer to the OSC = On case regardless of
STPMD values.
EXT=external clock mode
REF=PLL reference mode due to losing PLL clock or lock from NRM mode
SCM=PLL self-clocked mode due to losing reference clock from NRM mode
RESET= immediate reset
LOCKS
‘LK= expecting previous value of LOCKS before entering stop
0–>‘LK= current value is 0 until lock is regained which then will be the previous value before entering stop
0–> = current value is 0 until lock is regained but lock is never expected to regain
LOCS
‘LC=expecting previous value of LOCS before entering stop
1–>‘LC= current value is 1 until clock is regained which then will be the previous value before entering stop
1–> =current value is 1 until clock is regained but CLK is never expected to regain
7.5
Interrupts
Refer to Section 7.4.6.8, “PLL Loss-of-Lock Interrupt Request,” and Section 7.4.6.11,
“Loss-of-Clock Interrupt Request.”
MCF5275 Reference Manual, Rev. 2
7-30
Freescale Semiconductor
Chapter 8
Power Management
8.1
Introduction
This chapter explains the low-power operation of the MCF5275.
8.1.1
Features
The following features support low-power operation.
•
•
•
Four modes of operation: Run, Wait, Doze, and Stop
Ability to shut down most peripherals independently
Ability to shut down the external CLKOUT pin
8.2
Memory Map/Register Definition
The PM programming model consists of one register:
•
The low-power control register (LPCR) specifies the low-power mode entered when the
STOP instruction is issued, and controls clock activity in this low-power mode.
Table 8-1. Chip Configuration Module Memory Map
Access
IPSBAR Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x00_0010
Core Reset Status
Register (CRSR)2
Core Watchdog
Control Register
(CWCR)
Low-Power
Interrupt Control
Register (LPICR)
Core Watchdog
Service Register
(CWSR)
S
0x11_0004
Chip Configuration Register (CCR)3
Reserved
Low-Power Control
Register (LPCR)
S
1
1
S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result
in a cycle termination transfer error.
2 The CRSR, CWCR, and CWSR are described in the System Control Module. They are shown here only to warn
against accidental writes to these registers when accessing the LPICR.
3
The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to
this register when accessing the LPCR.
8.2.1
Register Descriptions
The following subsection describes the PM registers.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
8-1
Power Management
8.2.1.1
Low-Power Interrupt Control Register (LPICR)
Implementation of low-power stop mode and exit from a low-power mode via an interrupt require
communication between the CPU and logic associated with the interrupt controller. The LPICR is
an 8-bit register that enables entry into low-power stop mode, and includes the setting of the
interrupt level needed to exit a low-power mode.
NOTE
The setting of the low-power mode select (LPMD) field in the power
management module’s low-power control register (LPCR) determines
which low-power mode the device enters when a STOP instruction is
issued.
If this field is set to enter stop mode, then the ENBSTOP bit in the
LPICR must also be set.
The following is the sequence of operations needed to enable this functionality:
1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired
low-power mode) and loading the appropriate interrupt priority level.
2. At the appropriate time, the processor executes the privileged STOP instruction. Once the
processor has stopped execution, it asserts a specific Processor Status (PST) encoding.
Issuing the STOP instruction when the LPICR[ENBSTOP] bit is set causes the SCM to
enter stop mode.
3. The entry into a low-power mode is processed by the low-power mode control logic, and
the appropriate clocks (usually those related to the high-speed processor core) are
disabled.
4. After entering the low-power mode, the interrupt controller enables a combinational logic
path which evaluates any unmasked interrupt requests. The device waits for an event to
generate an interrupt request with a priority level greater than the value programmed in
LPICR[XLPM_IPL[2:0]].
NOTE
Only a fixed (external) interrupt can bring a device out of stop mode.
To exit from other low-power modes, such as doze or wait, either fixed
or programmable interrupts may be used; however, the module
generating the interrupt must be enabled in that particular low-power
mode.
5. Once an appropriately high interrupt request level arrives, the interrupt controller signals
its presence, and the SCM responds by asserting the request to exit low-power mode.
6. The low-power mode control logic senses the request signal and re-enables the appropriate
clocks.
7. With the processor clocks enabled, the core processes the pending interrupt request.
MCF5275 Reference Manual, Rev. 2
8-2
Freescale Semiconductor
Memory Map/Register Definition
7
6
R ENBSTOP
5
4
XLPM_IPL[2:0]
3
2
1
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
Address
0
IPSBAR + 0x00_0012
Figure 8-1. Low-Power Interrupt Control Register (LPICR)
Table 8-2. LPICR Field Description
Bits
7
6–4
3–0
Name
Description
ENBSTOP Enable low-power stop mode.
0 Low-power stop mode disabled
1 Low-power stop mode enabled. Once the core is stopped and the signal to enter stop
mode is asserted, processor clocks can be disabled.
XLPM_IPL Exit low-power mode interrupt priority level. This field defines the interrupt priority level
[2:0]
needed to exit the low-power mode.Refer to Table 8-3.
—
Reserved, should be cleared.
Table 8-3. XLPM_IPL Settings
8.2.1.2
XLPM_IPL[2:0]
Interrupts Level Needed to Exit Low-Power Mode
000
Any interrupt request exits low-power mode
001
Interrupt request levels [2-7] exit low-power mode
010
Interrupt request levels [3-7] exit low-power mode
011
Interrupt request levels [4-7] exit low-power mode
100
Interrupt request levels [5-7] exit low-power mode
101
Interrupt request levels [6-7] exit low-power mode
11x
Interrupt request level [7] exits low-power mode
Low-Power Control Register (LPCR)
The LPCR controls chip operation and module operation during low-power modes.
7
R
6
LPMD
5
4
3
2
1
0
0
0
STPMD
0
0
0
0
0
0
0
0
0
W
Reset
Address
0
0
IPSBAR + 0x11_0007
Figure 8-2. Low-Power Control Register (LPCR)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
8-3
Power Management
Table 8-4. LPCR Field Descriptions
Bits
Name
Description
7–6
LPMD
Low-power mode select. Used to select the low-power mode the chip enters once the
ColdFire CPU executes the STOP instruction. These bits must be written prior to
instruction execution for them to take effect. The LPMD[1:0] bits are readable and writable
in all modes. Below illustrates the four different power modes that can be configured with
the LPMD bit field.
LPMD[1:0]
Mode
11
STOP
10
WAIT
01
DOZE
00
RUN
Note: If LPCR[LPMD] is cleared, then the MCF5275 will stop executing code upon issue
of a STOP instruction. However, no clocks will be disabled.
8.3
5–4
—
3
STPMD
2–0
—
Reserved, should be cleared.
CLKOUT stop mode. Controls CLKOUT operation during stop mode.
0 CLKOUT enabled during stop mode.
1 CLKOUT disabled during stop mode.
Reserved, should be cleared.
Functional Description
The functions and characteristics of the low-power modes, and how each module is affected by, or
affects these modes are discussed in this section.
8.3.1
Low-Power Modes
The system enters a low-power mode by executing a STOP instruction. Which mode the device
actually enters (either stop, wait, or doze) depends on what is programmed in LPCR[LPMD].
Entry into any of these modes idles the CPU with no cycles active, powers down the system and
stops all internal clocks appropriately. During stop mode, the system clock is stopped low.
For entry into stop mode, the LPICR[ENBSTOP] bit must be set before a STOP instruction is
issued.
A wakeup event is required to exit a low-power mode and return to run mode. Wakeup events
consist of any of these conditions:
•
•
Any type of reset
Any valid, enabled interrupt request
Exiting from low power mode via an interrupt request requires:
MCF5275 Reference Manual, Rev. 2
8-4
Freescale Semiconductor
Functional Description
•
•
•
•
An interrupt request whose priority is higher than the value programmed in the XLPM_IPL
field of the LPICR.
An interrupt request whose priority higher than the value programmed in the interrupt
priority mask (I) field of the core’s status register.
An interrupt request from a source which is not masked in the interrupt controller’s
interrupt mask register.
An interrupt request which has been enabled at the module of the interrupt’s origin.
8.3.1.1
Run Mode
Run mode is the normal system operating mode. Current consumption in this mode is related
directly to the system clock frequency.
8.3.1.2
Wait Mode
Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event
is detected. In this mode, peripherals may be programmed to continue operating and can generate
interrupts, which cause the CPU to exit from wait mode.
8.3.1.3
Doze Mode
Doze mode affects the CPU in the same manner as wait mode, except that each peripheral defines
individual operational characteristics in doze mode. Peripherals which continue to run and have
the capability of producing interrupts may cause the CPU to exit the doze mode and return to run
mode. Peripherals which are stopped will restart operation on exit from doze mode as defined for
each peripheral.
8.3.1.4
Stop Mode
Stop mode affects the CPU in the same manner as the wait and doze modes, except that all clocks
to the system are stopped and the peripherals cease operation.
Stop mode must be entered in a controlled manner to ensure that any current operation is properly
terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume
operation.
The following subsections specify the operation of each module while in and when exiting
low-power modes.
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Freescale Semiconductor
8-5
Power Management
NOTE
Entering stop mode will disable the SDRAMC including the refresh
counter. If SDRAM is used, then code is required to insure proper
entry and exit from stop mode. See Section 8.3.2.4, “DDR SDRAM
Controller (SDRAMC)” for more information.
8.3.1.5
Peripheral Shut Down
Most peripherals may be disabled by software in order to cease internal clock generation and
remain in a static state. Each peripheral has its own specific disabling sequence (refer to each
peripheral description for further details). A peripheral may be disabled at any time and will
remain disabled during any low-power mode of operation.
8.3.2
8.3.2.1
Peripheral Behavior in Low-Power Modes
ColdFire Core
The ColdFire core is disabled during any low-power mode. No recovery time is required when
exiting any low-power mode.
8.3.2.2
Static Random-Access Memory (SRAM)
SRAM is disabled during any low-power mode. No recovery time is required when exiting any
low-power mode.
8.3.2.3
System Control Module (SCM)
The SCM’s core watchdog timer can bring the device out of all low-power modes except stop
mode. In stop mode, all clocks stop, and the core watchdog does not operate.
When enabled, the core watchdog can bring the device out of low-power mode via a core
watchdog interrupt. This system setup must meet the conditions specified in Section 8.3.1,
“Low-Power Modes” for the core watchdog interrupt to bring the part out of low-power mode.
8.3.2.4
DDR SDRAM Controller (SDRAMC)
DDR SDRAM Controller operation is unaffected by either the wait or doze modes; however, the
SDRAMC is disabled by stop mode. Since all clocks to the SDRAMC are disabled by stop mode,
the SDRAMC will not generate refresh cycles.
To prevent loss of data the SDRAMC should be placed in self-refresh mode by clearing
SDRAM_CONTROL[CKE] and setting SDRAMC_CONTROL[REF_EN]. The SDRAM
self-refresh mode allows the SDRAM to enter a low-power state where internal refresh operations
are used to maintain the integrity of the data stored in the SDRAM.
MCF5275 Reference Manual, Rev. 2
8-6
Freescale Semiconductor
Functional Description
When stop mode is exited setting the SDRAM_CONTROL[CKE] bit will cause the SDRAM to
exit the self-refresh mode and allow bus cycles to the SDRAM to resume.
NOTE
The SDRAM is inaccessible while in the self-refresh mode.
Therefore, if stop mode is used the vector table and any interrupt
handlers that could wake the processor should not be stored in or
attempt to access SDRAM.
8.3.2.5
Chip Select Module
In wait and doze modes, the chip select module continues operation but does not generate
interrupts; therefore it cannot bring a device out of a low-power mode. This module is stopped in
stop mode.
8.3.2.6
DMA Controller (DMA0–DMA3)
In wait and doze modes, the DMA controller is capable of bringing the device out of a low-power
mode by generating an interrupt either upon completion of a transfer or upon an error condition.
The completion of transfer interrupt is generated when DMA interrupts are enabled by the setting
of the DCR[INT] bit, and an interrupt is generated when the DSR[DONE] bit is set. The interrupt
upon error condition is generated when the DCR[INT] bit is set, and an interrupt is generated when
either the CE, BES or BED bit in the DSR becomes set.
The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power
mode.
8.3.2.7
UART Modules (UART0, UART1, and UART2)
In wait and doze modes, the UART may generate an interrupt to exit the low-power modes.
•
•
Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART
functions.
The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode.
In stop mode, the UARTs stop immediately and freeze their operation, register values, state
machines, and external pins. During this mode, the UART clocks are shut down. Coming out of
stop mode returns the UARTs to operation from the state prior to the low-power mode entry.
8.3.2.8
I2C Module
When the I2C Module is enabled by the setting of the I2CR[IEN] bit and when the device is not in
stop mode, the I2C module is operable and may generate an interrupt to bring the device out of a
low-power mode. For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and
the setting of the I2SR[IIF] generates the interrupt signal to the CPU and interrupt controller. The
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
8-7
Power Management
setting of I2SR[IIF] signifies either the completion of one byte transfer or the reception of a calling
address matching its own specified address when in slave receive mode.
In stop mode, the I2C Module stops immediately and freezes operation, register values, and
external pins. Upon exiting stop mode, the I2C resumes operation unless stop mode was exited by
reset.
8.3.2.9
Queued Serial Peripheral Interface (QSPI)
In wait and doze modes, the queued serial peripheral interface (QSPI) may generate an interrupt
to exit the low-power modes.
•
•
Clearing the QSPI enable bit (SPE) disables the QSPI function.
The QSPI is unaffected by wait mode and may generate an interrupt to exit this mode.
In stop mode, the QSPI stops immediately and freezes operation, register values, state machines,
and external pins. During this mode, the QSPI clocks are shut down. Coming out of stop mode
returns the QSPI to operation from the state prior to the low-power mode entry.
8.3.2.10 DMA Timers (DTIM0–DTIM3)
In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power mode.
This interrupt can be generated when the DMA Timer is in either input capture mode or reference
compare mode.
In input capture mode, where the capture enable (CE) field of the timer mode register (DTMR) has
a non-zero value and the DMA enable (DMAEN) bit of the DMA timer extended mode register
(DTXMR) is cleared, an interrupt is issued upon a captured input. In reference compare mode,
where the output reference request interrupt enable (ORRI) bit of DTMR is set and the
DTXMR[DMAEN] bit is cleared, an interrupt is issued when the timer counter reaches the
reference value.
DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either the wait
or doze modes and may generate an interrupt to exit these modes. Upon exiting stop mode, the
timer will resume operation unless stop mode was exited by reset.
8.3.2.11 Interrupt Controllers (INTC0, INTC1)
The interrupt controller is not affected by any of the low-power modes. All logic between the input
sources and generating the interrupt to the processor will be combinational to allow the ability to
wake up the CPU processor during low-power stop mode when all system clocks are stopped.
An interrupt request will cause the CPU to exit a low-power mode only if that interrupt’s priority
level is at or above the level programmed in the interrupt priority mask field of the CPU’s status
register (SR). The interrupt must also be enabled in the interrupt controller’s interrupt mask
register as well as at the module from which the interrupt request would originate.
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Functional Description
8.3.2.12 Fast Ethernet Controller (FEC)
In wait and doze modes, the FEC may generate an interrupt to exit the low-power modes.
•
•
Clearing the ECNTRL[ETHER_EN] bit disables the FEC function.
The FEC is unaffected by wait mode and may generate an interrupt to exit this mode.
In stop mode, the FEC stops immediately and freezes operation, register values, state machines,
and external pins. During this mode, the FEC clocks are shut down. Coming out of stop mode
returns the FEC to operation from the state prior to the low-power mode entry.
8.3.2.13 I/O Ports
The I/O ports are unaffected by entry into a low-power mode. These pins may impact low-power
current draw if they are configured as outputs and are sourcing current to an external load. If
low-power mode is exited by a reset, the state of the I/O pins will revert to their default direction
settings.
8.3.2.14 Reset Controller
A power-on reset (POR) will always cause a chip reset and exit from any low-power mode.
In wait and doze modes, asserting the external RESET pin for at least four clocks will cause an
external reset that will reset the chip and exit any low-power modes.
In stop mode, the RESET pin synchronization is disabled and asserting the external RESET pin
will asynchronously generate an internal reset and exit any low-power modes. Registers will lose
current values and must be reconfigured from reset state if needed.
If the phase lock loop (PLL) in the clock module is active and if the appropriate (LOCRE, LOLRE)
bits in the synthesizer control register are set, then any loss-of-clock or loss-of-lock will reset the
chip and exit any low-power modes.
If the watchdog timer is still enabled during wait or doze modes, then a watchdog timer timeout
may generate a reset to exit these low-power modes.
When the CPU is inactive, a software reset cannot be generated to exit any low-power mode.
8.3.2.15 Chip Configuration Module
The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode
is exited by a reset, chip configuration may be executed if configured to do so.
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Freescale Semiconductor
8-9
Power Management
8.3.2.16 Clock Module
In wait and doze modes, the clocks to the CPU and SRAM will be stopped and the system clocks
to the peripherals are enabled. Each module may disable the module clocks locally at the module
level. In stop mode, all clocks to the system will be stopped.
During stop mode, the PLL continues to run. The external CLKOUT signal may be enabled or
disabled when the device enters stop mode, depending on the LPCR[STPMD] bit settings.
The external CLKOUT output pin may be disabled to lower power consumption via the
SYNCR[DISCLK] bit. The external CLKOUT pin function is enabled by default at reset.
8.3.2.17 Edge Port
In wait and doze modes, the edge port continues to operate normally and may be configured to
generate interrupts (either an edge transition or low level on an external pin) to exit the low-power
modes.
In stop mode, there is no system clock available to perform the edge detect function. Thus, only
the level detect logic is active (if configured) to allow any low level on the external interrupt pin
to generate an interrupt (if enabled) to exit the stop mode.
8.3.2.18 Watchdog Timer
In stop mode (or in wait/doze mode, if so programmed), the watchdog ceases operation and freezes
at the current value. When exiting these modes, the watchdog resumes operation from the stopped
value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the watchdog may generate a reset to exit the low-power modes.
8.3.2.19 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3)
In stop mode (or in doze mode, if so programmed), the programmable interrupt timer (PIT) ceases
operation, and freezes at the current value. When exiting these modes, the PIT resumes operation
from the stopped value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the PIT may generate an interrupt to exit the low-power modes.
8.3.2.20 USB Module
The USB device module is clocked externally, so it operates normally in wait, doze, and stop
modes. It is capable of generating an interrupt to wake up the core from the wait and doze modes.
The USB block contains an automatic low power mode in which the module enters suspend mode
after a 6.0 ms minimum period of inactivity. When the module receives a wake-up from the USB
Host, the transceiver will be re-enabled for normal USB operations.
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Freescale Semiconductor
Functional Description
8.3.2.21 PWM Module
The PWM module is user programmable as to how it behaves when the device enters wait mode
(PWMCTL[PSWAI]) and doze mode (PWMCTL[PFRZ]). If either of these bits are set the PWM
input clock to the prescalar will be disabled during the respective low power mode.
In stop mode the input clock is disabled and PWM generation is halted.
8.3.2.22 BDM
Entering halt mode via the BDM port (by asserting the external BKPT pin) will cause the CPU to
exit any low-power mode.
8.3.2.23 JTAG
The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not
affected by the system clock. The JTAG cannot generate an event to cause the CPU to exit any
low-power mode. Toggling TCLK during any low-power mode will increase the system current
consumption.
8.3.3
Summary of Peripheral State During Low-Power Modes
The functionality of each of the peripherals and CPU during the various low-power modes is
summarized in Table 8-5. The status of each peripheral during a given mode refers to the condition
the peripheral automatically assumes when the STOP instruction is executed and the
LPCR[LPMD] field is set for the particular low-power mode. Individual peripherals may be
disabled by programming its dedicated control bits. The wakeup capability field refers to the
ability of an interrupt or reset by that peripheral to force the CPU into run mode.
Table 8-5. CPU and Peripherals in Low-Power Modes
Peripheral Status1 / Wakeup Capability
Module
Wait Mode
Doze Mode
Stop Mode
CPU
Stopped
No
Stopped
No
Stopped
No
SRAM
Stopped
No
Stopped
No
Stopped
No
System Control Module
Enabled
Yes 3
Enabled
Yes 3
Stopped
No
SDRAM Controller
Enabled
No
Enabled
No
Stopped
No
Chip Select Module
Enabled
No
Enabled
No
Stopped
No
DMA Controller
Enabled
Yes
Enabled
Yes
Stopped
No
UART0, UART1 and UART2
Enabled
Yes2
Enabled
Yes2
Stopped
No
I2C Module
Enabled
Yes2
Enabled
Yes2
Stopped
No
Enabled
Yes2
Enabled
Yes2
Stopped
No
QSPI
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
8-11
Power Management
Table 8-5. CPU and Peripherals in Low-Power Modes (Continued)
Peripheral Status1 / Wakeup Capability
Module
Wait Mode
Doze Mode
Stop Mode
DMA Timers
Enabled
Yes2
Enabled
Yes2
Stopped
No
Interrupt controller
Enabled
Yes2
Enabled
Yes2
Enabled
Yes2
Fast Ethernet Controller
Enabled
Yes2
Enabled
Yes2
Stopped
No
I/O Ports
Enabled
No
Enabled
No
Enabled
No
Reset Controller
Enabled
Yes3
Enabled
Yes3
Enabled
Yes3
Chip Configuration Module
Enabled
No
Enabled
No
Stopped
No
Power Management
Enabled
No
Enabled
No
Stopped
No
Clock Module
Enabled
Yes2
Enabled
Yes2
Enabled
Yes2
Edge port
Enabled
Yes2
Enabled
Yes2
Stopped
Yes2
Watchdog timer
Program
Yes3
Program
Yes3
Stopped
No
Programmable Interrupt Timers
Enabled
Yes2
Program
Yes2
Stopped
No
USB
Enabled
Yes2
Enabled
Yes2
Enabled
No
PWM
Program
No
Program
No
Stopped
No
BDM
Enabled
Yes4
Enabled
Yes4
Enabled
Yes4
JTAG
Enabled
No
Enabled
No
Enabled
No
1
“Program” Indicates that the peripheral function during the low-power mode is dependent on programmable bits in the
peripheral register map.
2 These modules can generate a interrupt which will exit a low-power mode. The CPU will begin to service the interrupt
exception after wakeup.
3 These modules can generate a reset which will exit any low-power mode.
4 The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode.
Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain
in effect.
MCF5275 Reference Manual, Rev. 2
8-12
Freescale Semiconductor
Chapter 9
Chip Configuration Module (CCM)
9.1
Introduction
The Chip Configuration Module (CCM) controls the chip configuration and mode of operation for
the MCF5275.
9.1.1
Block Diagram
Reset
Configuration
Output Pad
Strength Selection
Chip Mode
Selection
Clock Mode
Selection
Boot Device / Port
Size Selection
Chip Select
Configuration
Chip Configuration Register
Reset Configuration Register
Chip Identification Register
Chip Test Register
Figure 9-1. Chip Configuration Module Block Diagram
9.1.2
Features
The CCM performs these operations.
•
•
•
•
•
Selects the chip operating mode
Selects external clock or phase-lock loop (PLL) mode with internal or external reference
Selects output pad drive strength
Selects boot device and data port size
Selects bus monitor configuration
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
9-1
Chip Configuration Module (CCM)
•
•
•
•
9.1.3
Selects low-power configuration
Selects transfer size function of the external bus
Selects processor status (PSTAT) and processor debug data (DDATA) functions
Selects BDM or JTAG mode
Modes of Operation
The MCF5275 device only operates in master mode. In master mode, the central processor unit
(CPU) can access external memories and peripherals.The external bus consists of a 16-bit data bus
and 24 address lines. The available bus control signals include R/W, TS, TIP, TSIZ[1:0], TA, TEA,
OE, and BS[1:0]. Up to eight chip selects can be programmed to select and control external
devices and to provide bus cycle termination..
9.2
External Signal Descriptions
Table 9-1 provides an overview of the CCM signals.
Table 9-1. Signal Properties
Name
1
9.2.1
Function
Reset State
RCON
Reset configuration select
CLKMOD[1:0]
Clock mode select1
—
D[25:24, 21:19, 16]
Reset configuration override pins
—
Internal weak pull-up device
Refer to Chapter 7, “Clock Module” for more information.
RCON
If the external RCON pin is asserted during reset, then various chip functions, including the reset
configuration pin functions after reset, are configured according to the levels driven onto the
external data pins (see Section 9.4, “Functional Description”). The internal configuration signals
are driven to reflect the levels on the external configuration pins to allow for module configuration.
9.2.2
CLKMOD[1:0]
The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset. Refer to
Chapter 7, “Clock Module” for more information.
9.2.3
D[25:24, 21:19, 16] (Reset Configuration Override)
If the external RCON pin is asserted during reset, then the states of these data pins during reset
determine the chip mode of operation, boot device, clock mode, and certain module configurations
after reset.
MCF5275 Reference Manual, Rev. 2
9-2
Freescale Semiconductor
Memory Map/Register Definition
9.3
Memory Map/Register Definition
This subsection provides a description of the memory map and registers.
9.3.1
Programming Model
The CCM programming model consists of these registers:
•
•
•
The chip configuration register (CCR) controls the main chip configuration.
The reset configuration register (RCON) indicates the default chip configuration.
The chip identification register (CIR) contains a unique part number.
Some control register bits are implemented as write-once bits. These bits are always readable, but
once the bit has been written, additional writes have no effect, except during debug and test
operations.
Some write-once bits can be read and written while in debug mode. When debug mode is exited,
the chip configuration module resumes operation based on the current register values. If a write to
a write-once register bit occurs while in debug mode, the register bit remains writable on exit from
debug or test mode. Table 9-2 shows the accessibility of write-once bits.
Table 9-2. Write-Once Bits Read/Write Accessibility
9.3.2
Configuration
Read/Write Access
All configurations
Read-always
Debug operation
Write-always
Master mode
Write-once
Memory Map
Table 9-3. Chip Configuration Module Memory Map
IPSBAR Offset
[31:24]
[23:16]
[15:8]
0x11_0004
Chip Configuration Register (CCR)
0x11_0008
Reset Configuration Register (RCON)
0x11_000C
0x11_0010
[7:0]
Access1
Low-Power Control Register (LPCR)2
S
Chip Identification Register (CIR)
S
Reserved
3
Unimplemented
S
4
—
1
S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in
a cycle termination transfer error.
2
See Chapter 8, “Power Management,” for a description of the LPCR. It is shown here only to warn against accidental
writes to this register.
3 Writing to reserved addresses with values other than 0 could put the device in a test mode; reading returns 0s.
4 Accessing an unimplemented address has no effect and causes a cycle termination transfer error.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
9-3
Chip Configuration Module (CCM)
NOTE
To safeguard against unintentionally activating test logic, write
0x0000 to the above reserved location during initialization
(immediately after reset) to lock out test features. Setting any bits in
the CCR may lead to unpredictable results.
9.3.3
Register Descriptions
The following subsection describes the CCM registers.
9.3.3.1
R
Chip Configuration Register (CCR)
15
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
SZEN PSTEN
4
3
2
0
BME
0
1
1
0
BMT
W
Reset
Address
0
1
0
0
0
IPSBAR + 0x11_0004
Figure 9-2. Chip Configuration Register (CCR)
Table 9-4. CCR Field Descriptions
Bits
Name
Description
15–7
—
6
SZEN
TSIZ[1:0] enable. This read/write bit enables the TSIZ[1:0] function of the external pins.
0 TSIZ[1:0] function disabled. DMA Acknowlede function enabled on the TSIZ[1:0] pins.
1 TSIZ[1:0] function enabled. DMA Acknowlede function disabled on the TSIZ[1:0] pins.
5
PSTEN
PST[3:0]/DDATA[3:0] enable. This read/write bit enables the Processor Status (PST) and
Debug Data (DDATA)n functions of the external pins.
0 PST/DDATA function disabled.
1 PST/DDATA function enabled.
4
—
Reserved, should be cleared.
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
9-4
Freescale Semiconductor
Memory Map/Register Definition
Table 9-4. CCR Field Descriptions (Continued)
Bits
Name
Description
3
BME
Bus monitor enable. This read/write bit enables the bus monitor to operate during external
bus cycles.
0 Bus monitor disabled for external bus cycles.
1 Bus monitor enabled for external bus cycles.
Table 9-2 shows the read/write accessibility of this write-once bit.
2–0
BMT
Bus monitor timing. This field selects the timeout period (in system clocks) for the bus
monitor.
000 65536
001 32768
010 16384
011 8192
100 4096
101 2048
110 1024
111 512
Table 9-2 shows the read/write accessibility of this write-once bit.
9.3.3.2
Reset Configuration Register (RCON)
At reset, RCON determines the default operation of certain chip functions. All default functions
defined by the RCON values can only be overridden during reset configuration (see Section 9.4.1,
“Reset Configuration”) if the external RCON pin is asserted. RCON is a read-only register.
R
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
9
8
RCSC
7
6
5
0
0
RLOAD
0
0
0
4
3
BOOTPS
2
1
0
0
0
MODE
0
0
1
W
Reset
Address
0
0
0
1
IPSBAR + 0x11_0008
Figure 9-3. Reset Configuration Register (RCON)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
9-5
Chip Configuration Module (CCM)
Table 9-5. RCON Field Descriptions
Bits
Name
15–10
—
9–8
RCSC
Description
Reserved, should be cleared.
Chip select configuration. Reflects the default chip select configuration. The default
function of the chip select configuration can be overridden during reset configuration.
RCSC
1
7–6
—
5
RLOAD
4–3
BOOTPS
—
0
MODE
001
PADDR[7:5] = A[23:21]
01
PADDR[7] = CS6
PADDR[6:5] = A[22:21]
10
PADDR[7:6] = CS[6:5]
PADDR[5] = A[21]
11
PADDR[7:5] = CS[6:4]
This is the default value used for the MCF5275.
Reserved, should be cleared.
Pad driver load. Reflects the default pad driver strength configuration.
0 Partial drive strength (This is the default value used for the MCF5275.)
1 Full drive strength
Boot port size. Reflects the default selection for the boot port size. The below table shows
the different port configurations for BOOTPS. The default function of the boot port size can
be overridden during reset configuration.
1
2–1
Chip Select Configuration
BOOTPS[1:0]
Boot Port Size
00, 11
Reserved
011
External 16 bits
10
External 8 bits
This is the default value used for the MCF5275
Reserved, should be cleared.
Chip configuration mode. Reflects the default chip configuration mode.
0 Reserved
1 Master mode (This is the only value available for the MCF5275.)
The default mode cannot be overridden during reset configuration.
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Freescale Semiconductor
Functional Description
9.3.3.3
Chip Identification Register (CIR)
15
14
13
12
11
R
10
9
8
7
6
5
4
3
PIN
2
1
0
0
0
0
PRN
W
Reset
0
0
1
0
0
0
Address
0
0
0
0
0
0
0
IPSBAR + 0x11_000A
Figure 9-4. Chip Identification Register (CIR)
Table 9-6. CIR Field Description
9.4
Bits
Name
Description
15–6
PIN
Part identification number. Contains a unique identification number for the
device.
5–0
PRN
Part revision number. This number is increased by one for each new
full-layer mask set of this part. The revision numbers are assigned in
chronological order.
Functional Description
Six functions are defined within the chip configuration module:
1.
2.
3.
4.
5.
6.
Reset configuration
Chip mode selection
Boot device selection
Output pad strength configuration
Clock mode selections
Chip select configuration
These functions are described here.
9.4.1
Reset Configuration
During reset, the pins for the reset override functions are immediately configured to known states.
Table 9-7 shows the states of the external pins while in reset.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
9-7
Chip Configuration Module (CCM)
Table 9-7. Reset Configuration Pin States During Reset
Pin
Function1
Pin
I/O
Output
State
Input
State
D[25:24, 21:19, 16],
Primary
function
Input
—
Must be driven
by external logic
RCON
RCON function for all
modes2
Input
—
Internal weak
pull-up device
CLKMOD1, CLKMOD0
Not affected
Input
—
Must be driven by
external logic
1
If the external RCON pin is not asserted during reset, pin functions are determined by the
default operation mode defined in the RCON register. If the external RCON pin is asserted, pin
functions are determined by the override values driven on the external data bus pins.
2 During reset, the external RCON pin assumes its RCON pin function, but this pin changes to
the function defined by the chip operation mode immediately after reset. See Table 9-8.
If the RCON pin is not asserted during reset, the chip configuration and the reset configuration pin
functions after reset are determined by RCON or fixed defaults, regardless of the states of the
external data pins. The internal configuration signals are driven to levels specified by the RCON
register’s reset state for default module configuration.
If the RCON pin is asserted during reset, then various chip functions, including the reset
configuration pin functions after reset, are configured according to the levels driven onto the
external data pins. (See Table 9-8) The internal configuration signals are driven to reflect the levels
on the external configuration pins to allow for module configuration.
Table 9-8. Configuration During Reset1
Pin(s) Affected
D[31:0], R/W, TA, TEA,
TSIZ[1:0], TS, TIP, OE,
A[23:0], BS[3:0], CS[3:0]
CS0
All output pins
Default
Configuration
Override Pins
in Reset2,3
Function
RCON0 = 0
D16
Chip Mode Selected
1
Master mode4
0
Reserved
D[20:19]
Boot Device
00,11
Reserved
10
External with 8-bit port
01
External with 16-bit port
D21
Output Pad Drive Strength
0
Partial strength4
1
Full strength
RCON[4:3] = 00
RCON[5] = 1
MCF5275 Reference Manual, Rev. 2
9-8
Freescale Semiconductor
Functional Description
Table 9-8. Configuration During Reset1 (Continued)
Pin(s) Affected
Default
Configuration
Override Pins
in Reset2,3
Function
Clock mode
No default5
CLKMOD1, CLKMOD0
Clock Mode
00
External clock mode (PLL disabled)
01
1:1 PLL mode
10
Normal PLL mode with external
clock reference
11
Normal PLL mode w/crystal
reference
D[25:24]
Chip Select Configuration
00
PADDR[7:5] = A[23:21]4
10
PADDR[7] = CS6
PADDR[6:5] = A[22:21]
01
PADDR[7:6] = CS[6:5]
PADDR[5] = A[21]
11
PADDR[7:5] = CS[6:4]
A[23:21]/CS[6:4]
RCON[9:8] = 00
1
Modifying the default configurations is possible only if the external RCON pin is asserted.
The D[31:26, 23:22, 18:17, 15:0] pins do not affect reset configuration.
3 The external reset override circuitry drives the data bus pins with the override values while RSTOUT is asserted. It
must stop driving the data bus pins within one CLKOUT cycle after RSTOUT is negated. To prevent contention with
the external reset override circuitry, the reset override pins are forced to inputs during reset and do not become
outputs until at least one CLKOUT cycle after RSTOUT is negated. RCON must also be negated within one cycle
after RSTOUT is negated.
4 Default configuration
5 There is no default configuration for clock mode selection. The actual values for the CLKMOD pins must always be
driven during reset. Once out of reset, the CLKMOD pins have no effect on the clock mode selection.
2
9.4.2
Chip Mode Selection
The chip mode is selected during reset and reflected in the MODE field of the reset configuration
register (RCON). See Section 9.3.3.2, “Reset Configuration Register (RCON).” For the
MCF5275, there is only one valid chip mode setting.
Table 9-9. Chip Configuration Mode Selection
Chip Configuration
Mode
RCON[MODE]
Master mode
D16 driven high
Reserved
D16 driven low
During reset, certain module configurations depend on whether emulation mode is active as
determined by the state of the internal emulation signal.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
9-9
Chip Configuration Module (CCM)
9.4.3
Boot Device Selection
During reset configuration, the CS0 chip select pin is configured to select an external boot device.
In this case, the V (valid) bit in the CSMR0 register is ignored, and CS0 is enabled after reset. CS0
is asserted for the initial boot fetch accessed from address 0x0000_0000 for the Stack Pointer and
address 0x0000_0004 for the program counter (PC). It is assumed that the reset vector loaded from
address 0x0000_0004 causes the CPU to start executing from external memory space decoded by
CS0.
9.4.4
Output Pad Strength Configuration
Output pad strength is determined during reset configuration as shown in Table 9-10.
Table 9-10. Output Pad Driver Strength Selection1
Optional Pin Function Selection
Output pads configured for partial strength
D21 driven low
Output pads configured for full strength
D21 driven high
1
9.4.5
RCON[RLOAD]
Modifying the default configurations is possible only if the external RCON pin is asserted low.
Clock Mode Selection
The clock mode is selected during reset and reflected in the PLLMODE, PLLSEL, and PLLREF
bits of SYNSR. Once reset is exited, the clock mode cannot be changed. Table 9-11 summarizes
clock mode selection during reset configuration.
Table 9-11. Clock Mode Selection1
PLL SYNSR Bits
Clock Mode
CLKMOD[1] CLKMOD[0]
PLLMODE
PLLSEL
PLLREF
External clock mode; PLL disabled
0
0
0
0
0
1:1 PLL mode
0
1
1
0
0
Normal PLL mode; external clock reference
1
0
1
1
0
Normal PLL mode; crystal oscillator reference
1
0
1
1
1
1
There is no default configuration for clock mode selection. The actual values for the CLKMOD pins must always be driven
during reset. Once out of reset, the CLKMOD pins have no effect on the clock mode selection.
9.4.6
Chip Select Configuration
The chip select configuration (CS[6:4]) is selected during reset and reflected in the RCSC field of
the CCR. Once reset is exited, the chip select configuration cannot be changed. Table 9-8 shows
the different chip select configurations that can be implemented during reset configuration.
MCF5275 Reference Manual, Rev. 2
9-10
Freescale Semiconductor
Reset
9.5
Reset
Reset initializes CCM registers to a known startup state as described in Section 9.3, “Memory
Map/Register Definition.” The CCM controls chip configuration at reset as described in
Section 9.4, “Functional Description.”
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
9-11
Chip Configuration Module (CCM)
MCF5275 Reference Manual, Rev. 2
9-12
Freescale Semiconductor
Chapter 10
Reset Controller Module
10.1
Introduction
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals
to the system, and then to keep a history of what caused the reset.
10.1.1 Block Diagram
Figure 10-1 illustrates the reset controller and is explained in the following sections.
RESET
Pin
Power-On
Reset
Watchdog
Timer Timeout
PLL
Loss of Clock
RSTOUT
Pin
Reset
Controller
To Internal Resets
PLL
Loss of Lock
Software
Reset
Figure 10-1. Reset Controller Block Diagram
10.1.2 Features
Module features include:
•
•
•
Six sources of reset:
— External
— Power-on reset (POR)
— Watchdog timer
— Phase locked-loop (PLL) loss of lock
— PLL loss of clock
— Software
Software-assertable RESET pin independent of chip reset state
Software-readable status flags indicating the cause of the last reset
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
10-1
Reset Controller Module
10.2
External Signal Description
Table 10-1 provides a summary of the reset controller signal properties. The signals are described
in the following paragraphs.
Table 10-1. Reset Controller Signal Properties
Direction
Input
Hysteresis
Input
Synchronization
RESET
I
Y
Y1
RSTOUT
O
—
—
Name
1
RESET is always synchronized except when in low-power stop mode.
10.2.1 RESET
Asserting the external RESET for at least four rising CLKOUT edges causes the external reset
request to be recognized and latched.
10.2.2 RSTOUT
This active-low output signal is driven low when the internal reset controller module resets the
chip. When RSTOUT is active, the user can drive override options on the data bus.
10.3
Memory Map/Register Definition
The reset controller programming model consists of these registers:
•
•
Reset control register (RCR), which selects reset controller functions
Reset status register (RSR), which reflects the state of the last reset source
See Table 10-2 for the memory map and the following paragraphs for a description of the registers.
Table 10-2. Reset Controller Memory Map
1
2
IPSBAR Offset
[31:24]
[23:16]
[15:8]
[7:0]
Access1
0x11_0000
RCR
RSR
Reserved2
Reserved2
S/U
S/U = supervisor or user mode access.
Writes to reserved address locations have no effect and reads return 0s.
10.3.1 Reset Control Register (RCR)
The RCR allows software control for requesting a reset and for independently asserting the
external RSTOUT pin.
MCF5275 Reference Manual, Rev. 2
10-2
Freescale Semiconductor
Memory Map/Register Definition
7
6
R SOFTRST FRCRSTOUT
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
Address
IPSBAR + 0x11_0000
Figure 10-2. Reset Control Register (RCR)
Table 10-3. RCR Field Descriptions
Bits
Name
7
SOFTRST
6
5–0
Description
Allows software to request a reset. The reset caused by setting this bit clears this bit.
1 Software reset request
0 No software reset request
FRCRSTOUT Allows software to assert or negate the external RSTOUT pin.
1 Assert RSTOUT pin
0 Negate RSTOUT pin
CAUTION: External logic driving reset configuration data during reset needs to be
considered when asserting the RSTOUT pin when setting FRCRSTOUT.
—
Reserved, should be cleared.
10.3.2 Reset Status Register (RSR)
The RSR contains a status bit for every reset source. When reset is entered, the cause of the reset
condition is latched along with a value of 0 for the other reset sources that were not pending at the
time of the reset condition. These values are then reflected in RSR. One or more status bits may
be set at the same time. The cause of any subsequent reset is also recorded in the register,
overwriting status from the previous reset condition.
RSR can be read at any time. Writing to RSR has no effect.
R
7
6
5
4
3
2
1
0
0
0
SOFT
WDR
POR
EXT
LOC
LOL
0
0
W
Reset
Address
Reset Dependent
IPSBAR + 0x11_0001
Figure 10-3. Reset Status Register (RSR)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
10-3
Reset Controller Module
Table 10-4. RSR Field Descriptions
10.4
Bits
Name
Description
7–6
—
5
SOFT
Software reset flag. Indicates that the last reset was caused by software.
0 Last reset not caused by software
1 Last reset caused by software
4
WDR
Watchdog timer reset flag. Indicates that the last reset was caused by a watchdog timer
timeout.
0 Last reset not caused by watchdog timer timeout
1 Last reset caused by watchdog timer timeout
3
POR
Power-on reset flag. Indicates that the last reset was caused by a power-on reset.
0 Last reset not caused by power-on reset
1 Last reset caused by power-on reset
2
EXT
External reset flag. Indicates that the last reset was caused by an external device asserting
the external RESET pin.
0 Last reset not caused by external reset
1 Last reset state caused by external reset
1
LOC
Loss-of-clock reset flag. Indicates that the last reset state was caused by a PLL loss of
clock.
0 Last reset not caused by loss of clock
1 Last reset caused by loss of clock
0
LOL
Loss-of-lock reset flag. Indicates that the last reset state was caused by a PLL loss of lock.
0 Last reset not caused by loss of lock
1 Last reset caused by a loss of lock
Reserved, should be cleared.
Functional Description
10.4.1 Reset Sources
Table 10-5 defines the sources of reset and the signals driven by the reset controller.
Table 10-5. Reset Source Summary
Source
Type
Power on
Asynchronous
External RESET pin (not stop mode)
Synchronous
External RESET pin (during stop mode)
Asynchronous
Watchdog timer
Synchronous
Loss of clock
Asynchronous
Loss of lock
Asynchronous
Software
Synchronous
MCF5275 Reference Manual, Rev. 2
10-4
Freescale Semiconductor
Functional Description
To protect data integrity, a synchronous reset source is not acted upon by the reset control logic
until the end of the current bus cycle. Reset is then asserted on the next rising edge of the system
clock after the cycle is terminated. Whenever the reset control logic must synchronize reset to the
end of the bus cycle, the internal bus monitor is automatically enabled regardless of the BME bit
state in the chip configuration register (CCR). Then, if the current bus cycle is not terminated
normally the bus monitor terminates the cycle based on the length of time programmed in the BMT
field of the CCR.
Internal byte, word, or longword writes are guaranteed to complete without data corruption when
a synchronous reset occurs. External writes, including longword writes to 16-bit ports, are also
guaranteed to complete.
Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control
logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the
system.
10.4.1.1 Power-On Reset
At power up, the reset controller asserts RSTOUT. RSTOUT continues to be asserted until VDD
has reached a minimum acceptable level and, if PLL clock mode is selected, until the PLL
achieves phase lock. Then after approximately another 512 cycles, RSTOUT is negated and the
part begins operation.
10.4.1.2 External Reset
Asserting the external RESET for at least four rising CLKOUT edges causes the external reset
request to be recognized and latched. The bus monitor is enabled and the current bus cycle is
completed. The reset controller asserts RSTOUT for approximately 512 cycles after RESET is
negated and the PLL has acquired lock. The part then exits reset and begins operation.
In low-power stop mode, the system clocks are stopped. Asserting the external RESET in stop
mode causes an external reset to be recognized.
10.4.1.3 Watchdog Timer Reset
A watchdog timer timeout causes timer reset request to be recognized and latched. The bus
monitor is enabled and the current bus cycle is completed. If the RESET is negated and the PLL
has acquired lock, the reset controller asserts RSTOUT for approximately 512 cycles. Then the
part exits reset and begins operation.
10.4.1.4 Loss-of-Clock Reset
This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set and
either the PLL reference or the PLL itself fails. The reset controller asserts RSTOUT for
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
10-5
Reset Controller Module
approximately 512 cycles after the PLL has acquired lock. The part then exits reset and begins
operation.
10.4.1.5 Loss-of-Lock Reset
This reset condition occurs in PLL clock mode when the LOLRE bit in the SYNCR is set and the
PLL loses lock. The reset controller asserts RSTOUT for approximately 512 cycles after the PLL
has acquired lock. The part then exits reset and resumes operation.
10.4.1.6 Software Reset
A software reset occurs when the SOFTRST bit is set. If the RESET is negated and the PLL has
acquired lock, the reset controller asserts RSTOUT for approximately 512 cycles. Then the part
exits reset and resumes operation.
10.4.2 Reset Control Flow
The reset logic control flow is shown in Figure 10-4. In this figure, the control state boxes have
been numbered, and these numbers are referred to (within parentheses) in the flow description that
follows. All cycle counts given are approximate.
MCF5275 Reference Manual, Rev. 2
10-6
Freescale Semiconductor
Functional Description
POR
0
1
Y
LOSS OF CLOCK?
N
2
Y
LOSS OF LOCK?
5
ENABLE BUS MONITOR
N
3
RESET
PIN OR WD TIMEOUT
OR SW RESET?
Y
6
N
BUS CYCLE
COMPLETE?
N
4
ASSERT RSTOUT AND
LATCH RESET STATUS
Y
7
ASSERT RSTOUT AND
LATCH RESET STATUS
8
N
RESET NEGATED?
Y
9
PLL MODE?
Y
9A
N
PLL LOCKED?
Y
N
10
12
NEGATE RSTOUT
WAIT 512 CLKOUT CYCLES
11A
11
RCON ASSERTED?
Y
LATCH CONFIGURATION
N
Figure 10-4. Reset Control Flow
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
10-7
Reset Controller Module
10.4.2.1 Synchronous Reset Requests
In this discussion, the reference in parentheses refer to the state numbers in Figure 10-4. All cycle
counts given are approximate.
If the external RESET signal is asserted by an external device for at least four rising CLKOUT
edges (3), if the watchdog timer times out, or if software requests a reset, the reset control logic
latches the reset request internally and enables the bus monitor (5). When the current bus cycle is
completed (6), RSTOUT is asserted (7). The reset control logic waits until the RESET signal is
negated (8) and for the PLL to attain lock (9, 9A) before waiting 512 CLKOUT cycles (1). The
reset control logic may latch the configuration according to the RCON signal level (11, 11A)
before negating RSTOUT (12).
If the external RESET signal is asserted by an external device for at least four rising CLKOUT
edges during the 512 count (10) or during the wait for PLL lock (9A), the reset flow switches to
(8) and waits for the RESET signal to be negated before continuing.
10.4.2.2 Internal Reset Request
If reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss of lock
(2), the reset control logic asserts RSTOUT (4). The reset control logic waits for the PLL to attain
lock (9, 9A) before waiting 512 CLKOUT cycles (1). Then the reset control logic may latch the
configuration according to the RCON pin level (11, 11A) before negating RSTOUT (12).
If loss of lock occurs during the 512 count (10), the reset flow switches to (9A) and waits for the
PLL to lock before continuing.
10.4.2.3 Power-On Reset
When the reset sequence is initiated by power-on reset (0), the same reset sequence is followed as
for the other asynchronous reset sources.
10.4.3 Concurrent Resets
This section describes the concurrent resets. As in the previous discussion references in
parentheses refer to the state numbers in Figure 10-4.
10.4.3.1 Reset Flow
If a power-on reset is detected during any reset sequence, the reset sequence starts immediately (0).
If the external RESET pin is asserted for at least four rising CLKOUT edges while waiting for PLL
lock or the 512 cycles, the external reset is recognized. Reset processing switches to wait for the
external RESET pin to negate (8).
MCF5275 Reference Manual, Rev. 2
10-8
Freescale Semiconductor
Functional Description
If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to
complete (5, 6) for an external reset request, the cycle is terminated. The reset status bits are
latched (7) and reset processing waits for the external RESET pin to negate (8).
If a loss-of-clock or loss-of-lock condition is detected during the 512 cycle wait, the reset sequence
continues after a PLL lock (9, 9A).
10.4.3.2 Reset Status Flags
For a POR reset, the POR bit in the RSR are set, and the SOFT, WDR, EXT, LOC, and LOL bits
are cleared even if another type of reset condition is detected during the reset sequence for the
POR.
If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to
complete (5, 6) for an external reset request, the EXT, SOFT, and/or WDR bits along with the LOC
and/or LOL bits are set.
If the RSR bits are latched (7) during the EXT, SOFT, and/or WDR reset sequence with no other
reset conditions detected, only the EXT, SOFT, and/or WDR bits are set.
If the RSR bits are latched (4) during the internal reset sequence with the RESET pin not asserted
and no SOFT or WDR event, then the LOC and/or LOL bits are the only bits set.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
10-9
Reset Controller Module
MCF5275 Reference Manual, Rev. 2
10-10
Freescale Semiconductor
Chapter 11
System Control Module (SCM)
11.1 Introduction
This section details the functionality of the System Control Module (SCM) which provides the
programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit
core watchdog timer (CWT), and the system control registers and logic. Specifically, the system
control includes the internal peripheral system (IPS) base address register (IPSBAR), the
processor’s dual-port RAM base address register (RAMBAR), and system control registers that
include the core watchdog timer control.
11.1.1 Overview
The SCM provides the control and status for a variety of functions including base addressing and
address space masking for both the IPS peripherals and resources (IPSBAR) and the ColdFire core
memory space (RAMBAR). The MCF5275 CPU core supports one memory bank for the internal
SRAM.
The SACU provides the mechanism needed to implement secure bus transactions to the system
address space.
The programming model for the system bus arbitration resides in the SCM. The SCM sources the
necessary control signals to the arbiter for bus master management.
The CWT provides a means of preventing system lockup due to uncontrolled software loops via a
special software service sequence. If periodic software servicing action does not occur, the CWT
times out with a programmed response (interrupt) to allow recovery or corrective action to be
taken.
NOTE
The core watchdog timer is available to provide compatibility with the
watchdog timer implemented on previous ColdFire devices. However,
there is a second watchdog timer available on the MCF5275 that has
new features. See Chapter 21, “Watchdog Timer Module” for more
information. Please note that the core watchdog timer is unable to
reset the device. It is only permitted to assert an interrupt. For
resetting the device, use the second watchdog timer.
11.1.2 Features
The SCM includes these distinctive features:
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
11-1
System Control Module (SCM)
•
•
•
•
•
IPS base address register (IPSBAR)
— Base address location for 1-Gbyte peripheral space
— User control bits
Processor-local memory base address register (RAMBAR)
System control registers
— Core reset status register (CRSR) indicates type of last reset
— Core watchdog control register (CWCR) for watchdog timer control
— Core watchdog service register (CWSR) to service watchdog timer
System bus master arbitration programming model (MPARK)
System access control unit (SACU) programming model
— Master privilege register (MPR)
— Peripheral access control registers (PACRs)
— Grouped peripheral access control register (GPACR)
11.2 Memory Map/Register Definition
The memory map for the SCM registers is shown in Table 11-1. All the registers in the SCM are
memory-mapped as offsets within the 1-Gbyte IPS address space and accesses are controlled to
these registers by the control definitions programmed into the SACU.
Table 11-1. SCM Register Map
IPSBAR
Offset
[31:24]
[23:16]
0x00_0000
IPSBAR
0x00_0004
—
0x00_0008
RAMBAR
0x00_000C
—
0x00_0010
CRSR
CWCR
[15:8]
[7:0]
LPICR1
CWSR
0x00_0014
DMAREQC2
0x00_0018
—
0x00_001C
MPARK
0x00_0020
MPR
—
0x00_0024
PACR0
PACR1
PACR2
PACR3
0x00_0028
PACR4
—
PACR5
PACR6
0x00_002C
PACR7
—
PACR8
—
MCF5275 Reference Manual, Rev. 2
11-2
Freescale Semiconductor
Memory Map/Register Definition
Table 11-1. SCM Register Map (Continued)
IPSBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x00_0030
GPACR
—
—
—
0x00_0034
—
—
—
—
0x00_0038
—
—
—
—
0x00_003C
—
—
—
—
1
2
The LPICR register is described in Chapter 8, “Power Management."
The DMAREQC register is described in Chapter 18, “DMA Controller Module.”
11.2.1 Register Descriptions
11.2.1.1 Internal Peripheral System Base Address Register (IPSBAR)
The IPSBAR specifies the base address for the 1 Gbyte memory space associated with the on-chip
peripherals. At reset, the base address is loaded with a default location of 0x4000_0000 and
marked as valid (IPSBAR[V]=1). If desired, the address space associated with the internal
modules can be moved by loading a different value into the IPSBAR at a later time.
If an address “hits” in overlapping memory regions, the following priority is used to determine
what memory is accessed:
1.
2.
3.
4.
5.
IPSBAR
RAMBAR
Cache
SDRAM
Chip Selects
NOTE
This is the list of memory access priorities when viewed from the
processor core.
See Figure 11-1 and Table 11-2 for descriptions of the bits in IPSBAR.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
11-3
System Control Module (SCM)
31
R
30
BA
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
W
Reset
Address
IPSBAR + 0x000
Figure 11-1. IPS Base Address Register (IPSBAR)
Table 11-2. IPSBAR Field Description
Bits
Name
Description
31–30
BA
Base address. Defines the base address of the 1-Gbyte internal peripheral space. This is
the starting address for the IPS registers when the valid bit is set.
29–1
—
Reserved, should be cleared.
0
V
Valid. Enables/disables the IPS Base address region. V is set at reset.
0 IPS Base address is not valid.
1 IPS Base address is valid.
11.2.1.2 Memory Base Address Register (RAMBAR)
The MCF5275 supports dual-ported local SRAM memory. This processor-local memory can be
accessed directly by the core and/or other system bus masters. Since this memory provides
single-cycle accesses at processor speed, it is ideal for applications where double-buffer schemes
can be used to maximize system-level performance. For example, a DMA channel in a typical
double-buffer (also known as a ping-pong scheme) application may load data into one portion of
the dual-ported SRAM while the processor is manipulating data in another portion of the SRAM.
Once the processor completes the data calculations, it begins processing the just-loaded buffer
while the DMA moves out the just-calculated data from the other buffer, and reloads the next data
block into the just-freed memory region. The process repeats with the processor and the DMA
“ping-ponging” between alternate regions of the dual-ported SRAM.
The MCF5275 design implements the dual-ported SRAM in the memory space defined by the
RAMBAR register. There are two physical copies of the RAMBAR register: one located in the
processor core and accessible only via the privileged MOVEC instruction at CPU space address
0xC05, and another located in the SCM at IPSBAR + 0x008. ColdFire core accesses to this
memory are controlled by the processor-local copy of the RAMBAR, while (e.g., DMA, FEC, etc.)
module accesses are enabled by the SCM's RAMBAR.
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Freescale Semiconductor
Memory Map/Register Definition
The physical base address programmed in both copies of the RAMBAR is typically the same
value; however, they can be programmed to different values. By definition, the base address must
be a 0-modulo-size value.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
BA
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
BDE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x008
Figure 11-2. Memory Base Address Register (RAMBAR)
Table 11-3. RAMBAR Field Description
Bits
Name
Description
31–16
BA
Base address. Defines the memory module's base address on a 64-Kbyte boundary
corresponding to the physical array location within the 4 Gbyte address space supported
by ColdFire.
15–10
—
Reserved, should be cleared.
9
BDE
8–0
—
Back door enable. Qualifies the DMA module accesses to the SRAM memory.
0 Disables DMA module accesses to the SRAM module.
1 Enables DMA module accesses to the SRAM module.
NOTE: The SPV bit in the CPU’s RAMBAR must also be set to allow dual port access to
the SRAM. For more information, see Section 6.2.1, “SRAM Base Address Register
(RAMBAR).”
Reserved, should be cleared.
The SRAM module is configured through the RAMBAR shown in Figure 11-2.
•
•
•
RAMBAR specifies the base address of the SRAM.
All undefined bits are reserved. These bits are ignored during writes to the RAMBAR and
return zeros when read.
The back door enable bit, RAMBAR[BDE], is cleared at reset, disabling the DMA module
access to the SRAM.
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11-5
System Control Module (SCM)
NOTE
The SCM RAMBAR default value of 0x0000_0000 is invalid. The
RAMBAR located in the processor’s CPU space must be initialized
with the valid bit, RAMBAR[V], set before the CPU (or modules) can
access the on-chip SRAM (see 6.2.1, “SRAM Base Address Register
(RAMBAR)” for more information. The SCM RAMBAR is
implemented as 32 bits, all bits may be written and read. Bit fields
[15:10] and [8:0] are not used in the access decode.
For details on the processor's view of the local SRAM memories, see Section 6.2.1, “SRAM Base
Address Register (RAMBAR).”
11.2.1.3 Core Reset Status Register (CRSR)
The CRSR contains a bit for two of the reset sources to the CPU. A bit set to 1 indicates the last
type of reset that occurred. The CRSR is updated by the control logic when the reset is complete.
Only one bit is set at any one time in the CRSR. The register reflects the cause of the most recent
reset. To clear a bit, a logic 1 must be written to the bit location; writing a zero has no effect.
NOTE
The reset status register (RSR) in the reset controller module (see
Chapter 10, “Reset Controller Module”) provides indication of all
reset sources except the core watchdog timer.
R
7
6
5
4
3
2
1
0
EXT
0
0
0
0
0
0
0
W
Reset
Address
See Note
IPSBAR + 0x010
Note: The reset value of EXT depends on the last reset source. All other
bits are initialized to zero.
Figure 11-3. Core Reset Status Register (CRSR)
Table 11-4. CRSR Field Descriptions
Bits
Name
7
EXT
6–0
—
Description
External reset.
1 An external device driving RESET caused the last reset. Assertion of reset by an
external device causes the processor core to initiate reset exception processing. All
registers are forced to their initial state.
Reserved, should be cleared.
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Memory Map/Register Definition
11.2.1.4 Core Watchdog Control Register (CWCR)
The core watchdog timer prevents system lockup if the software becomes trapped in a loop with
no controlled exit. The core watchdog timer can be enabled or disabled through CWCR[CWE].
By default it is disabled. If enabled, the watchdog timer requires the periodic execution of a core
watchdog servicing sequence. If this periodic servicing action does not occur, the timer times out,
resulting in a watchdog timer interrupt. If the timer times out and the core watchdog transfer
acknowledge enable bit (CWCR[CWTA]) is set, a watchdog timer interrupt is asserted. If a core
watchdog timer interrupt acknowledge cycle has not occurred after another timeout, CWT TA is
asserted in an attempt to allow the interrupt acknowledge cycle to proceed by terminating the bus
cycle. The setting of CWCR[CWTAVAL] indicates that the watchdog timer TA was asserted.
To prevent the core watchdog timer from interrupting, the CWSR must be serviced by performing
the following sequence:
1. Write 0x55 to CWSR.
2. Write 0xAA to the CWSR.
Both writes must occur in order before the time-out, but any number of instructions can be
executed between the two writes. This order allows interrupts and exceptions to occur, if
necessary, between the two writes. Caution should be exercised when changing CWCR values
after the software watchdog timer has been enabled with the setting of CWCR[CWE], because it
is difficult to determine the state of the core watchdog timer while it is running. The countdown
value is constantly compared with the time-out period specified by CWCR[CWT]. The following
steps must be taken to change CWT:
1.
2.
3.
4.
Disable the core watchdog timer by clearing CWCR[CWE].
Reset the counter by writing 0x55 and then 0xAA to CWSR.
Update CWCR[CWT].
Re-enable the core watchdog timer by setting CWCR[CWE]. This step can be performed
in step 3.
The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer
transfer acknowledge. The register can be read at any time, but can be written only if the CWT is
not pending. At system reset, the software watchdog timer is disabled.
R
7
6
CWE
CWRI
0
0
5
4
3
CWT
Address
0
0
1
0
CWTA CWTAV CWTIC
AL
W
Reset
2
0
0
0
0
IPSBAR + 0x011
Figure 11-4. Core Watchdog Control Register (CWCR)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
11-7
System Control Module (SCM)
Table 11-5. CWCR Field Description
Bits
Name
7
CWE
Core watchdog enable.
0 SWT disabled.
1 SWT enabled.
6
CWRI
Core watchdog reset/interrupt select.
0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt
level for the CWT is programmed in the interrupt control register 7 (ICR7) of INTC0.
1 Reserved. Please note that unlike legacy devices, this bit is not available since the core
watchdog is unable to reset the device.
5–3
CWT
Core watchdog timing delay. These bits select the timeout period for the CWT. At system
reset, the CWT field is cleared signaling the minimum time-out period but the watchdog is
disabled (CWCR[CWE] = 0).
2
CWTA
1
CWTAVAL
0
CWTIF
Description
CWT [2:0]
CWT Time-Out Period
000
29 Bus clock frequency
001
211 Bus clock frequency
010
213 Bus clock frequency
011
215 Bus clock frequency
100
219 Bus clock frequency
101
223 Bus clock frequency
110
227 Bus clock frequency
111
231 Bus clock frequency
Core watchdog transfer acknowledge enable.
0 CWTA Transfer acknowledge disabled.
1 CWTA Transfer Acknowledge enabled. After one CWT time-out period of the
unacknowledged assertion of the CWT interrupt, the transfer acknowledge asserts,
which allows CWT to terminate a bus cycle and allow the interrupt acknowledge to
occur.
Core watchdog transfer acknowledge valid.
0 CWTA Transfer Acknowledge has not occurred.
1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit.
Core watchdog timer interrupt flag.
0 CWT interrupt has not occurred
1 CWT interrupt has occurred. Write a 1 to clear the interrupt request.
11.2.1.5 Core Watchdog Service Register (CWSR)
The software watchdog service sequence must be performed using the CWSR as a data register to
prevent a CWT time-out. The service sequence requires two writes to this data register: first a write
of 0x55 followed by a write of 0xAA. Both writes must be performed in this order prior to the
CWT time-out, but any number of instructions or accesses to the CWSR can be executed between
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11-8
Freescale Semiconductor
Internal Bus Arbitration
the two writes. If the CWT has already timed out, writing to this register has no effect in negating
the CWT interrupt. Figure 11-5 illustrates the CWSR. At system reset, the contents of CWSR are
uninitialized.
7
6
5
4
R
3
2
1
0
—
—
—
CWSR[7:0]
W
Reset
—
—
—
—
Address
—
IPSBAR + 0x013
Figure 11-5. Core Watchdog Service Register (CWSR)
11.3 Internal Bus Arbitration
The internal bus arbitration is performed by the on-chip bus arbiter, which containing the
arbitration logic that controls which of up to four MBus masters (M0–M3 in Figure 11-6) has
access to the external buses. The function of the arbitration logic is described in this section.
“back door” to SRAM
SRAM1
MPARK
RAMBAR
CPU
M0
DMA
M2
EIM
MARB
FEC1
M1
FEC0
Internal
Modules
SDRAMC
M3
Figure 11-6. Arbiter Module Functions
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11-9
System Control Module (SCM)
11.3.1 Overview
The basic functionality is that of a 4-port, pipelined internal bus arbitration module with the
following attributes:
•
•
•
•
•
•
The master pointed to by the current arbitration pointer may get on the bus with zero latency
if the address phase is available. All other requesters face at least a one cycle arbitration
pipeline delay in order to meet bus timing constraints on address phase hold.
If a requester will get an immediate address phase (that is, it is pointed to by the current
arbitration pointer and the bus address phase is available), it will be the current bus master
and is ignored by arbitration. All remaining requesting ports are evaluated by the arbitration
algorithm to determine the next-state arbitration pointer.
There are two arbitration algorithms, fixed and round-robin. Fixed arbitration sets the
next-state arbitration pointer to the highest priority requester. Round-robin arbitration sets
the next-state arbitration pointer to the highest priority requester (calculated by adding a
requester's fixed priority to the current bus master’s fixed priority and then taking this sum
modulo the number of possible bus masters).
The default priority is FEC0/1 (M3) > DMA (M2) > internal master (M1) > CPU (M0),
where M3 is the highest and M0 the lowest priority.
There are two actions for an idle arbitration cycle, either leave the current arbitration
pointer as is or set it to the lowest priority requester.
The anti-lock-out logic for the fixed priority scheme forces the arbitration algorithm to
round-robin if any requester has been held for longer than a specified cycle count.
11.3.2 Arbitration Algorithms
There are two modes of arbitration: fixed and round-robin. This section discusses the differences
between them.
11.3.2.1 Round-Robin Mode
Round-robin arbitration is the default mode after reset. This scheme cycles through the sequence
of masters as specified by MPARK[Mn_PRTY] bits. Upon completion of a transfer, the master is
given the lowest priority and the priority for all other masters is increased by one.
next +1
next +2
next +3
M3 = 11 M2 =01 M1 = 10 M0 = 00
M3 = 00 M2 =10 M1 = 11 M0 = 01
M3 = 01 M2 =11 M1 = 00 M0 = 10
M3 = 10 M2 =00 M1 = 01 M0 = 11
If no masters are requesting, the arbitration unit must “park”, pointing at one of the masters. There
are two possibilities, park the arbitration unit on the last active master, or park pointing to the
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Freescale Semiconductor
Internal Bus Arbitration
highest priority master. Setting MPARK[PRK_LAST] causes the arbitration pointer to be parked
on the highest priority master. In round-robin mode, programming the timeout enable and lockout
bits MPARK[13,11:8] will have no effect on the arbitration.
11.3.2.2 Fixed Mode
In fixed arbitration the master with highest priority (as specified by the MPARK[Mn_PRTY] bits)
will win the bus. That master will relinquish the bus when all transfers to that master are complete.
If MPARK[TIMEOUT] is set, a counter will increment for each master for every cycle it is denied
access. When a counter reaches the limit set by MPARK[LCKOUT_TIME], the arbitration
algorithm will be changed to round-robin arbitration mode until all locks are cleared. The
arbitration will then return to fixed mode and the highest priority master will be granted the bus.
As in round-robin mode, if no masters are requesting, the arbitration pointer will park on the
highest priority master if MPARK[PRK_LAST] is set, or will park on the master which last
requested the bus if cleared.
11.3.3 Bus Master Park Register (MPARK)
The MPARK controls the operation of the system bus arbitration module. The platform bus master
connections are defined as:
•
•
•
•
Master 3 (M3): Fast Ethernet Controller 1 (FEC0)
Master 2 (M2): 4-channel DMA
Master 1 (M1): Fast Ethernet Controller 2 (FEC1)
Master 0 (M0): V2 ColdFire Core
R
31
30
29
28
27
26
25
24
0
0
0
0
0
0
M2_P
_EN
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
0
W
Reset
0
FIXED TIME PRK
OUT LAST
0
0
Address
0
LCKOUT_TIME
0
0
0
0
23
22
M3_PRTY
21
20
M2_PRTY
19
18
M0_PRTY
17
16
M1_PRTY
IPSBAR + 0x01C
Figure 11-7. Default Bus Master Park Register (MPARK)
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Freescale Semiconductor
11-11
System Control Module (SCM)
Table 11-6. MPARK Field Description
Bits
Name
Description
31–26
—
25
M2_P_EN
24
—
23–22
M3_PRTY
Master priority level for master 3 (Fast Ethernet Controller 1)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
21–20
M2_PRTY
Master priority level for master 2 (DMA Controller)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
19–18
M0_PRTY
Master priority level for master 0 (ColdFire Core)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
17–16
M1_PRTY
Master priority level for master 1 (Fast Ethernet Controller 2)
00 fourth (lowest) priority
01 third priority
10 second priority
11 first (highest) priority
15
—
14
FIXED
13
TIMEOUT
Timeout Enable
0 disable count for when a master is locked out by other masters.
1 enable count for when a master is locked out by other masters and allow access when
LCKOUT_TIME is reached.
12
PRKLAST
Park on the last active master or highest priority master if no masters are active
0 park on last active master
1 park on highest priority master
11–8
LCKOUT_
TIME
Lock-out Time. Lock-out time for a master being denied the bus.
The lock out time is defined as 2^ LCKOUT_TIME[3:0].
7–0
—
Reserved, should be cleared.
DMA bandwidth control enable
0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
1 enable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
Reserved, should be cleared.
Reserved, should be cleared.
Fixed or round robin arbitration
0 round robin arbitration
1 fixed arbitration
Reserved, should be cleared.
The initial state of the master priorities is M3 > M2 > M1 > M0. System software should guarantee
that the programmed Mn_PRTY fields are unique, otherwise the hardware defaults to the
initial-state priorities.
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System Access Control Unit (SACU)
NOTE
The M1_PRTY field should not be set for a priority higher than third
(default).
11.4 System Access Control Unit (SACU)
This section details the functionality of the System Access Control Unit (SACU) which provides
the mechanism needed to implement secure bus transactions to the address space mapped to the
internal modules.
11.4.1 Overview
The SACU supports the traditional model of two privilege levels: supervisor and user. Typically,
memory references with the supervisor attribute have total accessibility to all the resources in the
system, while user mode references cannot access system control and configuration registers. In
many systems, the operating system executes in supervisor mode, while application software
executes in user mode.
The SACU further partitions the access control functions into two parts: one control register
defines the privilege level associated with each bus master, and another set of control registers
define the access levels associated with the peripheral modules and the memory space.
The SACU’s programming model is physically implemented as part of the System Control
Module (SCM) with the actual access control logic included as part of the arbitration controller.
Each bus transaction targeted for the IPS space is first checked to see if its privilege rights allow
access to the given memory space. If the privilege rights are correct, the access proceeds on the
bus. If the privilege rights are insufficient for the targeted memory space, the transfer is
immediately aborted and terminated with an exception, and the targeted module not accessed.
11.4.2 Features
Each bus transfer can be classified by its privilege level and the reference type. The complete set
of access types includes:
•
•
•
•
•
•
Supervisor instruction fetch
Supervisor operand read
Supervisor operand write
User instruction fetch
User operand read
User operand write
Instruction fetch accesses are associated with the execute attribute.
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Freescale Semiconductor
11-13
System Control Module (SCM)
It should be noted that while the bus does not implement the concept of reference type (code versus
data) and only supports the user/supervisor privilege level, the reference type attribute is supported
by the system bus. Accordingly, the access checking associated with both privilege level and
reference type is performed in the IPS controller using the attributes associated with the reference
from the system bus.
The SACU partitions the access control mechanisms into three distinct functions:
•
•
•
Master privilege register (MPR)
— Allows each bus master to be assigned a privilege level:
– Disable the master’s user/supervisor attribute and force to user mode access
– Enable the master’s user/supervisor attribute
— The reset state provides supervisor privilege to the processor core (bus master 0).
— Input signals allow the non-core bus masters to have their user/supervisor attribute
enabled at reset. This is intended to support the concept of a trusted bus master, and also
controls the ability of a bus master to modify the register state of any of the SACU
control registers; that is., only trusted masters can modify the control registers.
Peripheral access control registers (PACRs)
— Nine 8-bit registers control access to 17 of the on-chip peripheral modules.
— Provides read/write access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to these modules
Grouped peripheral access control registers (GPACR0)
— One single register (GPACR) controls access to 14 of the on-chip peripheral modules
— Provide read/write/execute access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to each of these peripheral spaces
11.4.3 Memory Map/Register Definition
The memory map for the SACU program-visible registers within the System Control Module
(SCM) is shown in Figure 11-7. The MPR, PACR, and GPACR are 8 bits in width.
Table 11-7. SACU Register Memory Map
IPSBA
R
Offset
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
—
—
—
—
—
—
0x020
MPR
0x024
PACR0
PACR1
PACR2
PACR3
0x028
PACR4
—
PACR5
PACR6
0x02c
PACR7
—
PACR8
—
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System Access Control Unit (SACU)
Table 11-7. SACU Register Memory Map (Continued)
IPSBA
R
Offset
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
0x030
GPACR
—
—
—
0x034
—
—
—
—
0x038
—
—
—
—
0x03C
—
—
—
—
11.4.3.1 Master Privilege Register (MPR)
The MPR specifies the access privilege level associated with each bus master in the platform. The
register provides one bit per bus master, where bit 3 corresponds to master 3 (Fast Ethernet
Controller 1), bit 2 to master 2 (DMA Controller), bit 1 to master 1 (Fast Ethernet Controller 2),
and bit 0 to master 0 (ColdFire core).
R
7
6
5
4
3
2
1
0
0
0
0
0
MPR3
MPR2
MPR1
MPR0
0
0
0
0
0
0
1
1
W
Reset
Address
IPSBAR + 0x020
Figure 11-8. Master Privilege Register (MPR)
Table 11-8. MPR Field Descriptions
Bits
Name
7–4
—
3–0
MPRn
Description
Reserved. Should be cleared.
Each 1-bit field defines the access privilege level of the given bus master n.
0 All bus master accesses are in user mode.
1 All bus master accesses use the sourced user/supervisor attribute.
Only trusted bus masters can modify the access control registers. If a non-trusted bus master
attempts to write any of the SACU control registers, the access is aborted with an error termination
and the registers remain unaffected.
The processor core is connected to bus master 0 and is always treated as a trusted bus master.
Accordingly, MPR0 is forced to 1 at reset.
11.4.3.2 Peripheral Access Control Registers (PACR0–PACR8)
Access to several on-chip peripherals is controlled by shared peripheral access control registers.
A single PACR defines the access level for each of the two modules. These modules only support
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11-15
System Control Module (SCM)
operand reads and writes. Each PACR follows the format illustrated in Figure 11-10. For a list of
PACRs and the modules that they control, refer to Table 11-11.
7
R LOCK1
6
5
4
3
ACCESS_CTRL1
2
LOCK0
1
0
ACCESS_CTRL0
W
Reset
0
0
0
Address
0
0
0
0
0
IPSBAR + 0x24 + Offset
Figure 11-9. Peripheral Access Control Register (PACRn)
Table 11-9. PACRn Field Descriptions
Bits
Name
Description
7
LOCK1
This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted write to
the PACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
6–4
ACCESS_
CTRL1
3
LOCK0
2–0
ACCESS_
CTRL0
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in Table 11-10.
This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted write to
the PACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in Table 11-10.
Table 11-10. PACR ACCESS_CTRL Bit Encodings
Supervisor Mode
User Mode
Bits
Read
Write
Read
Write
000
x
x
—
—
001
x
—
—
—
010
x
—
x
—
011
x
—
—
—
100
x
x
x
x
101
x
x
x
—
110
x
x
x
x
111
—
—
—
—
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System Access Control Unit (SACU)
Table 11-11. Peripheral Access Control Registers (PACRn)
Modules Controlled
IPSBAR Offset
Name
ACCESS_CTRL1
ACCESS_CTRL0
0x024
PACR0
SCM
SDRAMC
0x025
PACR1
EIM
DMA
0x026
PACR2
UART0
UART1
0x027
PACR3
UART2
—
0x028
PACR4
I2C
QSPI
0x029
—
—
—
0x02A
PACR5
DTIM0
DTIM1
0x02B
PACR6
DTIM2
DTIM3
0x02C
PACR7
INTC0
INTC1
0x02D
—
—
—
0x02E
PACR8
FEC0
FEC1
At reset, these on-chip modules are configured to have only supervisor read/write access
capabilities. If an instruction fetch access to any of these peripheral modules is attempted, the IPS
bus cycle is immediately terminated with an error.
11.4.3.3 Grouped Peripheral Access Control Register (GPACR)
The on-chip peripheral space starting at IPSBAR is subdivided into sixteen 64-Mbyte regions. The
first region has a unique access control register associated with it. The other fifteen regions are in
reserved space; the access control registers for these regions are not implemented. The access
control register is 8 bits in width so that read, write, and execute attributes may be assigned to the
given IPS region.
NOTE
The access control for modules with memory space protected by
PACR0–PACR8 are determined by the PACR0–PACR8 settings. The
access control is not affected by GPACR, even though the modules are
mapped in its 64-Mbyte address space.
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Freescale Semiconductor
11-17
System Control Module (SCM)
7
R LOCK
6
5
4
0
0
0
0
0
0
3
2
1
0
ACCESS_CTRL
W
Reset
0
Address
0
0
0
0
IPSBAR + 0x030
Figure 11-10. Grouped Peripheral Access Control Register (GPACR)
Table 11-12. (GPACR) Field Descriptions
Bits
Name
Description
7
LOCK
This bit, once set, prevents subsequent writes to the GPACR. Any attempted write to the
GPACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
6–4
—
3–0
ACCESS_
CTRL
Reserved, should be cleared.
This 4-bit field defines the access control for the given memory region.
The encodings for this field are shown in Table 11-13.
At reset, these on-chip modules are configured to have only supervisor read/write access
capabilities. Bit encodings for the ACCESS_CTRL field in the GPACR are shown in Table 11-13.
Table 11-14 shows the memory space protected by the GPACR and the modules mapped to this
space.
Table 11-13. GPACR ACCESS_CTRL Bit Encodings
Supervisor Mode
User Mode
Bits
Read
Write
Execute
Read
Write
Execute
0000
x
x
—
—
—
—
0001
x
—
—
—
—
—
0010
x
—
—
x
—
—
0011
x
—
—
—
—
—
0100
x
x
—
x
x
—
0101
x
x
—
x
—
—
0110
x
x
—
x
x
—
0111
—
—
—
—
—
—
1000
x
x
x
—
—
—
1001
x
—
x
—
—
—
1010
x
—
x
x
—
x
1011
—
—
x
—
—
—
1100
x
x
x
x
x
x
MCF5275 Reference Manual, Rev. 2
11-18
Freescale Semiconductor
System Access Control Unit (SACU)
Table 11-13. GPACR ACCESS_CTRL Bit Encodings (Continued)
Supervisor Mode
User Mode
Bits
Read
Write
Execute
Read
Write
Execute
1101
x
x
x
x
—
x
1110
x
x
—
x
—
—
1111
x
x
x
—
—
x
Table 11-14. GPACR Address Space
Register
Space Protected
(IPSBAR Offset)
Modules Protected
GPACR
0x0000_0000–0x03FF_FFFF
All
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
11-19
System Control Module (SCM)
MCF5275 Reference Manual, Rev. 2
11-20
Freescale Semiconductor
Chapter 12
General Purpose I/O Module
12.1
Introduction
Many of the pins associated with the MCF5275 external interface may be used for several different
functions. Their primary functions are to provide external interfaces to access off-chip resources.
When not used for their primary function, many of the pins may be used as general-purpose digital
I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin
functions are not supported.
The general purpose I/O pins on the MCF5275 are grouped into 8-bit ports. Some ports do not use
all 8 bits. Each GPIO port has registers that configure, monitor, and control the port pins.
Figure 12-1 is a block diagram of the MCF5275 ports.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-1
General Purpose I/O Module
PORT
ADDR
A[23:21] / CS[6:4] / PADDR[7:5]
PORT
FECnH
FECn_TXCLK / PFECnH[7]
FECn_TXEN / PFECnH[6]
FECn_TXD[0] / PFECnH[5]
FECn_COL / PFECnH[4]
FECn_RXCLK / PFECnH[3]
FECn_RXDV / PFECnH[2]
FECn_RXD[0] / PFECnH[1]
FECn_CRS / PFECnH[0]
FEC0_EMDIO / I2C_SDA / U2RXD / PFECI2C[5]
FEC0_EMDC / I2C_SCL / U2TXD / PFECI2C[4]
PORT
FECI2C
FECn_TXD[3:1] / PFECnL[7:5]
PORT
FECnL
PORT
UARTH
FECn_TXER / PFECnL[4]
FECn_RXD[3:1] / PFECnL[3:1]
FECn_RXER / PFECnL[0]
PORT
IRQ
PORT
BUSCTL
IRQ[7:5] / PIRQ[7:5]
IRQ4 / DREQ2 / PIRQ4
IRQ[3:2] / DREQ[3:2] / PIRQ[3:2]
IRQ1 / PIRQ1
OE / PBUSCTL[7]
TA / PBUSCTL[6]
TEA / DREQ1 / PBUSCTL[5]
R/W / PBUSCTL[4]
TSIZ[1:0] / DACK[1:0] / PBUSCTL[3:2]
TS / DACK2 / PBUSCTL[1]
TIP / DREQ0 / PBUSCTL[0]
PORT
BS
PORT
CS
PORT
QSPI
PORT
TIMERH
BS[3:2]/CAS[3:2] / PBS[3:2]
PORT
TIMERL
CS[7:1] / PCS[7:1]
SD_CS[1:0] / CS[3:2] / PSDRAM[7:6]
PORT
SDRAM
PORT
UARTL
PORT
USBH
SD_SRAS / PSDRAM[5]
SD_SCAS / PSDRAM[4]
PORT
USBL
SD_WE / PSDRAM[3]
SD_DQS[3:2] / PSDRAM[2:1]
SD_CKE / PSDRAM[0]
FEC1_EMDIO / PFECI2C[3]
FEC1_EMDC / PFECI2C[2]
I2C_SDA / U2RXD / PFECI2C[1]
I2C_SCL / U2TXD / PFECI2C[0]
U2RXD / PUARTH[3]
U2TXD / PUARTH[2]
U2CTS / PWM1 / PUARTH[1]
U2RTS / PWM0 / PUARTH[0]
U1RXD / PUARTL[7]
U1TXD / PUARTL[6]
U1CTS / PUARTL[5]
U1RTS / PUARTL[4]
U0RXD / PUARTL[3]
U0TXD / PUARTL[2]
U0CTS / PUARTL[1]
U0RTS / PUARTL[0]
QSPI_PCS[3:2] / PWM[3:2] / DACK[3:2] / PQSPI[6:5]
QSPI_PCS[1] / PQSPI[4]
QSPI_PCS[0] / PQSPI[3]
QSPI_SCK / I2C_SCL / PQSPI[2]
QSPI_DIN / I2C_SDA / PQSPI[1]
QSPI_DOUT / PQSPI[0]
T3IN / T3OUT / U2RTS / PTIMERH[3]
T3OUT / PWM3 / U2CTS / PTIMERH[2]
T2IN / T2OUT / PTIMERH[1]
T2OUT / PWM2 / PTIMERH[0]
T1IN / T1OUT / PTIMERL[3]
T1OUT / PWM1 / PTIMERL[2]
T0IN / T0OUT / PTIMERL[1]
T0OUT / PWM0 / PTIMERL[0]
USB_SPEED / PUSBLH[0]
USB_CLK / PUSBL[7]
USB_RN / PUSBL[6]
USB_RP / PUSBL[5]
USB_RXD / PUSBL[4]
USB_SUSP / PUSBL[3]
USB_TN / PUSBL[2]
USB_TP / PUSBL[1]
USB_TXEN / PUSBL[0]
PIN ASSIGNMENT CONTROL
Internal Bus
Figure 12-1. MCF5275 Ports Module Block Diagram
MCF5275 Reference Manual, Rev. 2
12-2
Freescale Semiconductor
External Signal Description
12.1.1 Overview
The MCF5275 ports module controls the configuration for various external pins, including those
used for:
•
•
•
•
•
•
•
External bus accesses
External device selection
Ethernet data and control
I2C serial control
QSPI
32-bit platform timers
USB
12.1.2 Features
The MCF5275 ports includes these distinctive features:
•
•
12.2
Control of primary function use
— On all supported GPIO ports
General purpose I/O support for all ports
— Registers for storing output pin data
— Registers for controlling pin data direction
— Registers for reading current pin state
— Registers for setting and clearing output pin data registers
External Signal Description
The MCF5275 ports control the functionality of several external pins. These pins are listed in
Table 12-2 under the GPIO column.
After reset ports ADDR, DATAH, DATAL, BUSCTL, BS and CS are configured for external
memory. They are available for the user as GPIO if the corresponding registers are set
appropriately. All other ports default to GPIO after reset.
NOTE
In this table and throughout this document a single signal within a
group is designated without square brackets (i.e., A24), while
designations for multiple signals within a group use brackets (i.e.,
A[23:21]) and is meant to include all signals within the two bracketed
numbers when these numbers are separated by a colon.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-3
General Purpose I/O Module
NOTE
The primary functionality of a pin is not necessarily its default
functionality. Pins that are muxed with GPIO will default to their
GPIO functionality.
Table 12-1. MCF5274 and MCF5275 Signal Information and Muxing
Signal Name
GPIO
Alternate1
Alternate2 Dir.1
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
Reset
RESET
—
—
—
I
N15
K12
RSTOUT
—
—
—
O
N14
L12
Clock
EXTAL
—
—
—
I
L16
M14
XTAL
—
—
—
O
M16
N14
CLKOUT
—
—
—
O
T12
P9
Mode Selection
CLKMOD[1:0]
—
—
—
I
N13, P13
M11, N11
RCON
—
—
—
I
P8
M6
External Memory Interface and Ports
A[23:21]
PADDR[7:5]
CS[6:4]
—
O
A11, B11, C11
A8, B8, C8
A[20:0]
—
—
—
O
A12, B12, C12,
A13, B13, C13,
A14, B14, C14,
B15, C15, B16,
C16, D14, D15,
E14:16, F14:16
B9, D9, C9,
C10, B10, A11,
C11, B11, A12,
D11, C12, B13,
C13, D12, E11,
D13, E12, F11,
D14, E13, F13
D[31:16]
—
—
—
O
M1, N1, N2, N3,
P1, P2, R1, R2,
P3, R3, T3, N4,
P4, R4, T4, N5
J3, L1, K2, K3,
M1, L2, L3, L4,
K4, J4, M2, N1,
N2, M3, M4, N3
BS[3:2]
PBS[3:2]
CAS[3:2]
—
O
M3, R5
K1, L5
OE
PBUSCTL[7]
—
—
O
K1
H4
TA
PBUSCTL[6]
—
—
I
L13
K14
TEA
PBUSCTL[5]
DREQ1
—
I
T8
—
R/W
PBUSCTL[4]
—
—
O
P7
L6
TSIZ1
PBUSCTL[3]
DACK1
—
O
D16
B14
TSIZ0
PBUSCTL[2]
DACK0
—
O
G16
E14
MCF5275 Reference Manual, Rev. 2
12-4
Freescale Semiconductor
External Signal Description
Table 12-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
O
L4
H2
O
P6
—
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
TS
PBUSCTL[1]
DACK2
—
TIP
PBUSCTL[0]
DREQ0
—
Chip Selects
CS[7:1]
PCS[7:1]
—
—
O
D10:13, E13,
F13, N7
D8, A9, A10,
D10, B12, C14,
P4
CS0
—
—
—
O
R6
N5
DDR SDRAM Controller
DDR_CLKOUT
—
—
—
O
T7
P6
DDR_CLKOUT
—
—
—
O
T6
P5
SD_CS[1:0]
PSDRAM[7:6]
CS[3:2]
—
O
M2, T5
H3, M5
SD_SRAS
PSDRAM[5]
—
—
O
L2
H1
SD_SCAS
PSDRAM[4]
—
—
O
L1
G3
SD_WE
PSDRAM[3]
—
—
O
K2
G4
SD_A10
—
—
—
O
N6
N4
SD_DQS[3:2]
PSDRAM[2:1]
—
—
I/O
M4, P5
J2, P3
SD_CKE
PSDRAM[0]
—
—
O
L3
J1
SD_VREF
—
—
—
I
A15, T2
A13, P2
External Interrupts Port
IRQ[7:5]
PIRQ[7:5]
—
—
I
G13, H16, H15
F14, G13, G14
IRQ[4]
PIRQ[4]
DREQ2
—
I
H14
H11
IRQ[3:2]
PIRQ[3:2]
DREQ[3:2]
—
I
J14, J13
H14, H12
IRQ1
PIRQ[1]
—
—
I
K13
J13
FEC0
FEC0_MDIO
PFECI2C[5]
I2C_SDA
U2RXD
I/O
A7
A3
FEC0_MDC
PFECI2C[4]
I2C_SCL
U2TXD
O
B7
C5
FEC0_TXCLK
PFEC0H[7]
—
—
I
C3
C1
FEC0_TXEN
PFEC0H[6]
—
—
O
D4
C3
FEC0_TXD[0]
PFEC0H[5]
—
—
O
G4
D2
FEC0_COL
PFEC0H[4]
—
—
I
A6
B4
FEC0_RXCLK
PFEC0H[3]
—
—
I
B6
B3
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-5
General Purpose I/O Module
Table 12-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
I
B5
C4
—
I
C6
D5
—
—
I
C7
A2
PFEC0L[7:5]
—
—
O
E3, F3, F4
D1, E3, D3
FEC0_TXER
PFEC0L[4]
—
—
O
D3
C2
FEC0_RXD[3:1]
PFEC0L[3:1]
—
—
I
D5, C5, D6
D4, B1, B2
FEC0_RXER
PFEC0L[0]
—
—
I
C4
E4
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
FEC0_RXDV
PFEC0H[2]
—
—
FEC0_RXD[0]
PFEC0H[1]
—
FEC0_CRS
PFEC0H[0]
FEC0_TXD[3:1]
FEC1
FEC1_MDIO
PFECI2C[3]
—
—
I/O
G1
—
FEC1_MDC
PFECI2C[2]
—
—
O
G2
—
FEC1_TXCLK
PFEC1H[7]
—
—
I
C1
—
FEC1_TXEN
PFEC1H[6]
—
—
O
D2
—
FEC1_TXD[0]
PFEC1H[5]
—
—
O
F1
—
FEC1_COL
PFEC1H[4]
—
—
I
A5
—
FEC1_RXCLK
PFEC1H[3]
—
—
I
B4
—
FEC1_RXDV
PFEC1H[2]
—
—
I
A3
—
FEC1_RXD[0]
PFEC1H[1]
—
—
I
B3
—
FEC1_CRS
PFEC1H[0]
—
—
I
A4
—
FEC1_TXD[3:1]
PFEC1L[7:5]
—
—
O
E1, E2, F2
—
FEC1_TXER
PFEC1L[4]
—
—
O
D1
—
FEC1_RXD[3:1]
PFEC1L[3:1]
—
—
I
B1, B2, A2
—
FEC1_RXER
PFEC1L[0]
—
—
I
C2
—
I2C
I2C_SDA
PFECI2C[1]
U2RXD
—
I/O
B10
B7
I2C_SCL
PFECI2C[0]
U2TXD
—
I/O
C10
A7
—
—
DMA
DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads.
Please refer to the following pins for muxing:
PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for
DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for
DREQ2, TEA for DREQ1, and TIP for DREQ0.
QSPI
MCF5275 Reference Manual, Rev. 2
12-6
Freescale Semiconductor
External Signal Description
Table 12-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
O
R13, N12
P10, N9
—
O
T14
N10
—
—
O
P12
M9
PQSPI[2]
I2C_SCL
—
O
T15
L11
QSPI_DIN
PQSPI[1]
I2C_SDA
—
I
T13
M10
QSPI_DOUT
PQSPI[0]
—
—
O
R12
L10
Signal Name
GPIO
Alternate1
Alternate2 Dir.1
QSPI_CS[3:2]
PQSPI[6:5]
PWM[3:2]
DACK[3:2]
QSPI_CS1
PQSPI[4]
—
QSPI_CS0
PQSPI[3]
QSPI_CLK
UARTs
U2RXD
PUARTH[3]
—
—
I
T9
—
U2TXD
PUARTH[2]
—
—
O
R9
—
U2CTS
PUARTH[1]
PWM1
—
I
P9
—
U2RTS
PUARTH[0]
PWM0
—
O
R8
—
U1RXD
PUARTL[7]
—
—
I
A9
A6
U1TXD
PUARTL[6]
—
—
O
B9
D7
U1CTS
PUARTL[5]
—
—
I
C9
C7
U1RTS
PUARTL[4]
—
—
O
D9
B6
U0RXD
PUARTL[3]
—
—
I
A8
A4
U0TXD
PUARTL[2]
—
—
O
B8
A5
U0CTS
PUARTL[1]
—
—
I
C8
C6
U0RTS
PUARTL[0]
—
—
O
D7
B5
USB
USB_SPEED
PUSBH[0]
—
—
I/O
G14
G11
USB_CLK
PUSBL[7]
—
—
I
G15
F12
USB_RN
PUSBL[6]
—
—
I
J16
H13
USB_RP
PUSBL[5]
—
—
I
J15
J11
USB_RXD
PUSBL[4]
—
—
I
L15
L14
USB_SUSP
PUSBL[3]
—
—
O
M13
N13
USB_TN
PUSBL[2]
—
—
O
K14
J14
USB_TP
PUSBL[1]
—
—
O
K15
J12
USB_TXEN
PUSBL[0]
—
—
O
L14
K13
I
J4
G2
Timers (and PWMs)
DT3IN
PTIMERH[3]
DT3OUT
U2RTS
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-7
General Purpose I/O Module
Table 12-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
O
K3
G1
—
I
J2
F3
PWM2
—
O
J3
F4
PTIMERL[3]
DT1OUT
—
I
H1
F1
DT1OUT
PTIMERL[2]
PWM1
—
O
H2
F2
DT0IN
PTIMERL[1]
DT0OUT
—
I
H3
E1
DT0OUT
PTIMERL[0]
PWM0
—
O
G3
E2
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
DT3OUT
PTIMERH[2]
PWM3
U2CTS
DT2IN
PTIMERH[1]
DT2OUT
DT2OUT
PTIMERH[0]
DT1IN
BDM/JTAG2
DSCLK
—
TRST
—
I
P14
P13
PSTCLK
—
TCLK
—
O
P16
P12
BKPT
—
TMS
—
I
R15
N12
DSI
—
TDI
—
I
R16
M12
DSO
—
TDO
—
O
P15
K11
JTAG_EN
—
—
—
I
R14
P11
DDATA[3:0]
—
—
—
O
P10, N10, P11, M7, N7, P8, L9
N11
PST[3:0]
—
—
—
O
T10, R10, T11,
R11
P7, L8, M8, N8
Test
TEST
—
—
—
I
N9
N6
PLL_TEST
—
—
—
I
M14
—
Power Supplies
VDDPLL
—
—
—
I
M15
M13
VSSPLL
—
—
—
I
K16
L13
VSS
—
—
—
I
A1, A10, A16,
E5, E12, F6,
F11, G7:10,
H7:10, J1,
J7:10, K7:10,
L6, L11, M5,
N16, R7, T1,
T16
F7, F8, G6:9,
H6:9, J7, J8
MCF5275 Reference Manual, Rev. 2
12-8
Freescale Semiconductor
External Signal Description
Table 12-1. MCF5274 and MCF5275 Signal Information and Muxing (Continued)
MCF5274
MCF5275
256 MAPBGA
MCF5274L
MCF5275L
196 MAPBGA
I
E6:8, F5, F7, F8,
G5, G6, H5, H6,
J11, J12, K11,
K12, L9, L10,
L12, M9:11
E5:7, F5, F6,
H10, J9, J10,
K8:10
—
I
D8, H13, K4, N8 D6, G5, G12, L7
—
I
E9:11, F9, F10, E8:10, F9, F10,
F12, G11, G12, G10, H5, J5, J6,
H11, H12, J5,
K5:7
J6, K5, K6, L5,
L7, L8, M6, M7,
M8
Alternate2 Dir.1
Signal Name
GPIO
Alternate1
OVDD
—
—
—
VDD
—
—
SD_VDD
—
—
1
Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in
GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.
2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not
responsible for assigning these pins.
Refer to the Chapter 2, “Signal Descriptions,” for more detailed descriptions of these pins and
other pins not controlled by the ports module. The function of most of the pins (primary function,
GPIO, etc.) is determined by the ports module pin assignment registers. Refer to Section 2.3,
“External Signal Descriptions” for detailed descriptions of pin functions.
It should be noted from Table 12-2 that there are several cases where a function is available on
more than one pin. While it is possible to enable the function on more than one pin simultaneously,
this type of programming should be avoided for input functions to prevent unexpected behavior.
All multiple-pin functions are listed in Table 12-2.
Table 12-2. MCF5275 Multiple-Pin Functions
Function
Direction
Associated Pins
Chip select 6 (CS6)
O
CS6, A23
Chip select 5 (CS5)
O
CS5, A22
Chip select 4 (CS4)
O
CS4, A21
SDRAM Chip select 1(SD_CS1)
O
CS3, SD_CS1
SDRAM Chip select 0 (SD_CS0)
O
CS2, SD_CS0
SDRAMC clock enable (SD_CKE)
O
SD_CKE, QSPI_CS1
I2C serial data (I2C_SDA)
I/O
I2C_SDA, QSPI_DIN, FEC0_MDIO
2
I C serial clock (I2C_SCL)
I/O
I2C_SCL, QSPI_CLK, FEC0_MDC
DMA request 2 (DREQ2)
I
IRQ2, DIRQ[4]
DMA acknowledge 2 (DACK2)
O
TS, QSPI_PCS2
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-9
General Purpose I/O Module
Table 12-2. MCF5275 Multiple-Pin Functions (Continued)
12.3
Function
Direction
Associated Pins
UART2 transmit data (U2TXD)
O
U2TXD, I2C_SCL, FEC0_MDC
UART2 receive data (U2RXD)
I
U2RXD, I2C_SDA, FEC0_MDIO
UART2 clear-to-send (U2CTS)
I
DT3OUT, U2CTS
UART2 request-to-send (U2RTS)
O
DT3IN, U2RTS
Timer output 3 (T3OUT)
O
T3OUT, T3IN
Timer output 2 (DT2OUT)
O
DT2OUT, DT2IN
Timer output 1 (DT1OUT)
O
DT1OUT, DT1IN
PWM output 3
O
T3OUT, QSPI_PCS3
PWM output 2
O
T2OUT, QSPI_PCS2
PWM output 1
O
T1OUT, U2CTS
PWM output 0
O
T0OUT, U2RTS
Memory Map/Register Definition
Table 12-3 summarizes all the registers in the MCF5275 ports address space.
Table 12-3. MCF5275 Ports Module Memory Map
IPSBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
Access1
Port Output Data Registers
Reserved2
0x10_0000
S/U
Reserved2
0x10_0004
PODR_BUSCTL
PODR_ADDR
S/U
0x10_0008
PODR_CS
Reserved2
PODR_FEC0H
PODR_FEC0L
S/U
0x10_000C
PODR_FECI2C
PODR_QSPI
PODR_SDRAM
PODR_TIMERH
S/U
0x10_0010
PODR_TIMERL
PODR_UARTL
PODR_FEC1H
PODR_FEC1L
S/U
0x10_0014
PODR_BS
PODR_IRQ
PODR_USBH
PODR_USBL
S/U
0x10_0018
PODR_UARTH
Reserved2
S/U
Port Data Direction Registers
Reserved2
0x10_001C
S/U
Reserved2
0x10_0020
PDDR_BUSCTL
PDDR_ADDR
S/U
0x10_0024
PDDR_CS
Reserved2
PDDR_FEC0H
PDDR_FEC0L
S/U
0x10_0028
PDDR_FECI2C
PDDR_QSPI
PDDR_SDRAM
PDDR_TIMERH
S/U
0x10_002C
PDDR_TIMERL
PDDR_UARTL
PDDR_FEC1H
PDDR_FEC1L
S/U
0x10_0030
PDDR_BS
PDDR_IRQ
PDDR_USBH
PDDR_USBL
S/U
MCF5275 Reference Manual, Rev. 2
12-10
Freescale Semiconductor
Memory Map/Register Definition
Table 12-3. MCF5275 Ports Module Memory Map (Continued)
IPSBAR
Offset
[31:24]
0x10_0034
PDDR_UARTH
[23:16]
[15:8]
[7:0]
Reserved2
Access1
S/U
Port Pin Data/Set Data Registers
Reserved2
0x10_0038
S/U
Reserved
2
0x10_003C
PPDSDR_BUSCTL
PPDSDR_ADDR
0x10_0040
PPDSDR_CS
Reserved2
PPDSDR_FEC0H
PPDSDR_FEC0L
S/U
0x10_0044
PPDSDR_FECI2C
PPDSDR_QSPI
PPDSDR_SDRAM
PPDSDR_TIMERH
S/U
0x10_0048
PPDSDR_TIMERL
PPDSDR_UARTL
PPDSDR_FEC1H
PPDSDR_FEC1L
S/U
0x10_004C
PPDSDR_BS
PPDSDR_IRQ
PPDSDR_USBH
PPDSDR_USBL
S/U
0x10_0050
PPDSDR_UARTH
Reserved2
S/U
S/U
Port Clear Output Data Registers
Reserved3
0x10_0054
S/U
Reserved3
0x10_0058
PCLRR_BUSCTL
PCLRR_ADDR
0x10_005C
PCLRR_CS
Reserved2
PCLRR_FEC0H
PCLRR_FEC0L
S/U
0x10_0060
PCLRR_FECI2C
PCLRR_QSPI
PCLRR_SDRAM
PCLRR_TIMERH
S/U
0x10_0064
PCLRR_TIMERL
PCLRR_UARTL
PCLRR_FEC1H
PCLRR_FEC1L
S/U
0x10_0068
PCLRR_BS
PCLRR_IRQ
PCLRR_USBH
PCLRR_USBL
S/U
0x10_006C
PCLRR_UARTH
Reserved2
S/U
S/U
Port Pin Assignment Registers
0x10_0070
PAR_ADDR
0x10_0074
0x10_0078
2
PAR_BUSCTL
S/U
PAR_USB
S/U
PAR_IRQ
PAR_FEC0HL
PAR_FEC1HL
0x10_007C
PAR_UART
0x10_0080
PAR_SDRAM
0x10_0084
1
PAR_CS
PAR_BS
PAR_TIMERH
Reserved
PAR_TIMERL
S/U
PAR_QSPI
S/U
PAR_FEC12C
S/U
2
S/U
S/U = supervisor or user mode access.
Writing to reserved address locations has no effect and reading returns 0s.
12.3.1 Register Descriptions
12.3.1.1 Port Output Data Registers (PODR_x)
The PODR_x registers store the data to be driven on the corresponding port pins when the pins are
configured for general purpose output. The PODR_x registers are each 8 bits wide, but not all ports
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-11
General Purpose I/O Module
use all 8 bits. The register definitions for all ports are shown in Figure 12-2 through Figure 12-5.
The PODR_x registers are read/write. At reset, all implemented bits in the PODR_x registers are
set. Reserved bits always remain cleared.
Reading a PODR_x register returns the current values in the register, not the port x pin values. To
set bits in a PODR_x register, write 1s to the PODR_x bits, or write 1s to the corresponding bits in
the PPDSDR_x register. To clear bits in a PODR_x register, write 0s to the PODR_x bits, or write
0s to the corresponding bits in the PCLRR_x register.
7
6
5
4
R
3
2
1
0
1
1
1
1
PODR_x
W
Reset
1
1
1
1
Address IPSBAR + 0x10_0004 (PODR_BUSCTL); IPSBAR + 0x10_000A (PODR_FEC0H);
IPSBAR + 0x10_000B (PODR_FEC0L); IPSBAR + 0x10_000E (PODR_SDRAM);
IPSBAR + 0x10_00011 (PODR_UARTL); IPSBAR + 0x10_0012 (PODR_FEC1H);
IPSBAR + 0x10_0013 (PODR_FEC1L); IPSBAR + 0x10_0017 (PODR_USBL)
Figure 12-2. Port x Output Data Registers (PODR_x)
R
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
1
1
PODR_x
W
Reset
Address
1
1
;
IPSBAR + 0x10_000F (PODR_TIMERH); IPSBAR + 0x10_0010 (PODR_TIMERL);
IPSBAR + 0x10_0018 (PODR_UARTH)
Figure 12-3. Port x Output Data Registers (PODR_x)
7
R
6
5
PODR_ADDR
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
1
1
1
IPSBAR + 0x10_0005 (PODR_ADDR)
Figure 12-4. Port ADDR Output Data Register (PODR_ADDR)
MCF5275 Reference Manual, Rev. 2
12-12
Freescale Semiconductor
Memory Map/Register Definition
7
6
5
R
4
3
2
1
PODR_CS
0
0
W
Reset
1
1
Address
1
1
1
1
1
0
IPSBAR + 0x10_0008 (PODR_CS)
Figure 12-5. Port CS Output Data Register (PODR_CS)
R
7
6
0
0
0
0
5
4
3
2
1
0
1
1
PODR_FECI2C
W
Reset
Address
1
1
1
1
IPSBAR + 0x10_000C (PODR_FECI2C)
Figure 12-6. Port FECI2C Output Data Register (PODR_FECI2C)
7
R
6
5
4
0
3
2
1
0
1
1
1
PODR_QSPI
W
Reset
0
1
Address
1
1
1
IPSBAR + 0x10_000D (PODR_QSPI)
Figure 12-7. Port QSPI Output Data Register (PODR_QSPI)
R
7
6
5
4
3
2
1
0
0
0
0
0
PODR_BS
0
0
0
0
0
0
1
0
0
W
Reset
Address
1
IPSBAR + 0x10_0014 (PODR_BS)
Figure 12-8. Port BS Output Data Register (PODR_BS)
7
6
5
R
4
3
2
1
PODR_IRQ
0
0
W
Reset
Address
1
1
1
1
1
1
1
0
IPSBAR + 0x10_0015 (PODR_IRQ)
Figure 12-9. Port IRQ Output Data Register (PODR_IRQ)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-13
General Purpose I/O Module
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PODR_
USBH
0
0
0
0
0
0
0
1
W
Reset
Address
IPSBAR + 0x10_0016 (PODR_USBH)
Figure 12-10. Port USBH Output Data Register (PODR_USBH)
Table 12-4. PODR_x Field Descriptions
Name
Description
—
Reserved, should be cleared.
PODR_x
Port x output data bits.
0 Drives 0 when the port x pin is general purpose output
1 Drives 1 when the port x pin is general purpose output
Note: See above figures for bit field positions.
12.3.1.2 Port Data Direction Registers (PDDR_x)
The PDDRs control the direction of the port x pin drivers when the pins are configured for general
purpose I/O. The PDDR_x registers are each eight bits wide, but not all ports use all eight bits. The
register definitions for all ports are shown in Figure 12-11 through Figure 12-19.
The PDDRs are read/write. At reset, all bits in the PDDRs are cleared. Setting any bit in a PDDR_x
register configures the corresponding port x pin as an output. Clearing any bit in a PDDR_x
register configures the corresponding pin as an input.
7
6
5
4
R
3
2
1
0
0
0
0
0
PDDR_x
W
Reset
Address
0
0
0
0
IPSBAR + 0x10_0020 (PDDR_BUSCTL); IPSBAR + 0x10_0026 (PDDR_FEC0H);
IPSBAR + 0x10_0027 (PDDR_FEC0L); IPSBAR + 0x10_002A (PDDR_SDRAM);
IPSBAR + 0x10_002D (PDDR_UARTL);IPSBAR + 0x10_002E (PDDR_FEC1H);
IPSBAR + 0x10_002F (PDDR_FEC1L); IPSBAR + 0x10_0033 (PDDR_USBL)
Figure 12-11. Port Data Direction Registers (PDDR_x)
MCF5275 Reference Manual, Rev. 2
12-14
Freescale Semiconductor
Memory Map/Register Definition
R
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
0
0
PDDR_x
W
Reset
0
0
Address IPSBAR + 0x10_002B (PDDR_TIMERH); IPSBAR + 0x10_002C (PDDR_TIMERL);
IPSBAR + 0x10_0034 (PDDR_UARTH)
Figure 12-12. Port Data Direction Registers (PDDR_x)
7
R
6
5
PDDR_ADDR
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
Address
0
IPSBAR + 0x10_0021 (PDDR_ADDR)
Figure 12-13. Port ADDR Data Direction Register (PDDR_ADDR)
7
6
5
R
4
3
2
1
PDDR_CS
0
0
W
Reset
0
0
Address
0
0
0
0
0
0
IPSBAR + 0x10_0024 (PDDR_CS)
Figure 12-14. Port CS Data Direction Register (PDDR_CS)
R
7
6
0
0
0
0
5
4
3
2
1
0
0
0
PDDR_FECI2C
W
Reset
Address
0
0
0
0
IPSBAR + 0x10_0028 (PDDR_FECI2C)
Figure 12-15. Port FECI2C Data Direction Register (PDDR_FECI2C)
7
R
6
5
4
0
3
2
1
0
0
0
0
PDDR_QSPI
W
Reset
Address
0
0
0
0
0
IPSBAR + 0x10_0029 (PDDR_QSPI)
Figure 12-16. Port QSPI Data Direction Register (PDDR_QSPI)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-15
General Purpose I/O Module
R
7
6
5
4
3
2
1
0
0
0
0
0
PDDR_BS
0
0
0
0
0
0
0
0
0
W
Reset
Address
0
IPSBAR + 0x10_0030 (PDDR_BS)
Figure 12-17. Port BS Data Direction Register (PDDR_BS)
7
6
5
R
4
3
2
1
PDDR_IRQ
0
0
W
Reset
0
0
Address
0
0
0
0
0
0
IPSBAR + 0x10_0031 (PDDR_IRQ)
Figure 12-18. Port IRQ Data Direction Register (PDDR_IRQ)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PDDR_
USBH
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x10_0032 (PDDR_USBH)
Figure 12-19. Port USBH Data Direction Register (PDDR_USBH)
Table 12-5. PDDR_x Field Descriptions
Name
—
PDDR_x
Description
Reserved, should be cleared.
Port x output data direction bits.
1 Port x pin configured as output
0 Port x pin configured as input
Note: See above figures for bit field positions.
12.3.1.3 Port Pin Data/Set Data Registers (PPDSDR_x)
The PPDSDR_x registers reflect the current pin states and control the setting of output pins when
the pin is configured for general purpose I/O. The PPDSDR_x registers are each eight bits wide,
but not all ports use all eight bits. The register definitions for all ports are shown in Figure 12-20
through Figure 12-28.
The PPDSDR_x registers are read/write. At reset, the bits in the PPDSDR_x registers are set to the
current pin states. Reading a PPDSDR_x register returns the current state of the port x pins. Setting
a PPDSDR_x register sets the corresponding bits in the PODR_x register. Writing 0s has no effect.
MCF5275 Reference Manual, Rev. 2
12-16
Freescale Semiconductor
Memory Map/Register Definition
7
6
5
4
R
3
2
1
0
PPDSDR_x
W
Reset
Address
Current Pin State
IPSBAR + 0x10_003C (PPDSDR_BUSCTL); IPSBAR + 0x10_0042 (PPDSDR_FEC0H);
IPSBAR + 0x10_0043 (PPDSDR_FEC0L); IPSBAR + 0x10_0046 (PPDSDR_SDRAM);
IPSBAR + 0x10_0049 (PPDSDR_UARTL); IPSBAR + 0x10_004A (PPDSDR_FEC1H);
IPSBAR + 0x10_004B (PPDSDR_FEC1L); IPSBAR + 0x10_004F (PPDSDR_USBL)
Figure 12-20. Port Pin Data/Set Data Registers (PPDSDR_x)
R
7
6
5
4
3
2
1
0
0
0
0
0
PPDSDR_x
0
0
0
0
Current Pin State
W
Reset
Address IPSBAR + 0x10_0047 (PPDSDR_TIMERH); IPSBAR + 0x10_0048 (PPDSDR_TIMERL);
IPSBAR + 0x10_0050 (PPDSDR_UARTH)
Figure 12-21. Port Pin Data/Set Data Registers (PPDSDR_x)
7
4
3
2
1
0
PPDSDR_ADDR
0
0
0
0
0
Current Pin State
0
0
0
0
0
R
6
5
W
Reset
Address
IPSBAR + 0x10_003D (PPDSDR_ADDR)
Figure 12-22. Port ADDR Pin Data/Set Data Register (PPDSDR_ADDR)
7
R
6
5
4
3
2
1
0
PPDSDR_CS
0
Current pin state
0
W
Reset
Address
IPSBAR + 0x10_0040 (PPDSDR_CS)
Figure 12-23. Port CS Pin Data/Set Data Register (PPDSDR_CS)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-17
General Purpose I/O Module
R
7
6
5
4
3
2
0
0
PDDR_FECI2C
0
0
Current pin state
1
0
W
Reset
Address
IPSBAR + 0x10_0044 (PPDSDR_FECI2C)
Figure 12-24. Port FECI2C Pin Data/Set Data Register (PPDSDR_FECI2C)
7
R
6
5
4
3
2
0
PPDSDR_QSPI
0
Current Pin State
1
0
W
Reset
Address
IPSBAR + 0x10_0045 (PPDSDR_QSPI)
Figure 12-25. Port QSPI Pin Data/Set Data Register (PPDSDR_QSPI)
R
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
PPDSDR_BS
0
0
Current Pin State
0
0
W
Reset
Address
IPSBAR + 0x10_004C (PPDSDR_BS)
Figure 12-26. Port BS Pin Data/Set Data Register (PPDSDR_BS)
7
6
5
R
4
3
2
1
0
PPDSDR_IRQ
0
Current pin state
0
W
Reset
Address
IPSBAR + 0x10_004D (PPDSDR_IRQ)
Figure 12-27. Port IRQ Pin Data/Set Data Register (PPDSDR_IRQ)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PPDSDR_
USBH
0
0
0
0
0
0
0
Current
pin state
W
Reset
Address
IPSBAR + 0x10_004E (PPDSDR_USBH)
Figure 12-28. Port USBH Pin Data/Set Data Register (PPDSDR_USBH)
MCF5275 Reference Manual, Rev. 2
12-18
Freescale Semiconductor
Memory Map/Register Definition
Table 12-6. PPDSDR_x Field Descriptions
Name
—
PPDSDR_x
Description
Reserved, should be cleared.
Port x Pin Data/Set Data Bits.
0 Port x pin state is 0 (read)
1 Port x pin state is 1 (read); set corresponding PODR_x bit (write)
Note: See above figures for bit field positions.
12.3.1.4 Port Clear Output Data Registers (PCLRR_x)
Clearing a PCLRR_x register clears the corresponding bits in the PODR_x register. Setting it has
no effect. Reading the PCLRR_x register returns 0s. Most PODR_x registers have a full 8-bit
implementation, as shown in Figure 12-29. The remaining PODR_x registers use fewer than eight
bits. Their bit definitions are shown in Figure 12-30 through Figure 12-37.
The PCLRR_x registers are read/write accessible.
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
PCLRR_x
0
0
0
0
0
IPSBAR + 0x10_0058 (PCLRR_BUSCTL); IPSBAR + 0x10_005E (PCLRR_FEC0H);
IPSBAR + 0x10_005F (PCLRR_FEC0L); IPSBAR + 0x10_0062 (PCLRR_SDRAM);
IPSBAR + 0x10_0065 (PCLRR_UARTL); IPSBAR + 0x10_0066 (PCLRR_FEC1H);
IPSBAR + 0x10_0067 (PCLRR_FEC1L); IPSBAR + 0x10_006B (PCLRR_USBL)
Figure 12-29. Port Clear Output Data Registers (PCLRR_x)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
Reset
PCLRR_x
0
0
0
0
0
0
0
0
Address IPSBAR + 0x10_0063 (PCLRR_TIMERH); IPSBAR + 0x10_0064 (PCLRR_TIMERL);
IPSBAR + 0x10_006C (PCLRR_UARTH)
Figure 12-30. Port Clear Output Data Registers (PCLRR_x)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-19
General Purpose I/O Module
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
PCLRR_ADDR
0
0
Address
IPSBAR + 0x10_0059 (PCLRR_ADDR)
Figure 12-31. Port ADDR Clear Output Data Register (PCLRR_ADDR)()
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
PCLRR_CS
0
0
Address
0
0
IPSBAR + 0x10_005C (PCLRR_CS)
Figure 12-32. Port CS Clear Output Data Register (PCLRR_CS)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
PCLRR_QSPI
0
0
Address
0
0
0
IPSBAR + 0x10_0060 (PCLRR_QSPI)
Figure 12-33. Port QSPI Clear Output Data Register (PCLRR_QSPI)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
PCLRR_FECI2C
0
0
Address
0
0
0
0
IPSBAR + 0x10_0060 (PCLRR_FECI2C)
Figure 12-34. Port FECI2C Clear Output Data Register (PCLRR_FECI2C)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
PCLRR_BS
0
0
0
0
0
0
IPSBAR + 0x10_0068 (PCLRR_BS)
Figure 12-35. Port BS Clear Output Data Register (PCLRR_BS)
MCF5275 Reference Manual, Rev. 2
12-20
Freescale Semiconductor
Memory Map/Register Definition
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
PCLRR_IRQ
Reset
0
0
Address
0
0
IPSBAR + 0x10_0069 (PCLRR_IRQ)
Figure 12-36. Port IRQ Clear Output Data Register (PCLRR_IRQ)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
W
Reset
PPDSDR_
USBH
0
Address
0
0
0
0
0
0
0
IPSBAR + 0x10_006A (PCLRR_USBH)
Figure 12-37. Port USBH Clear Output Data Register (PCLRR_USBH)
Table 12-7. PCLRR_x Field Descriptions
Name
—
PCLRR_x
Description
Reserved, should be cleared.
Port x clear Data Bits.
0 Always returned for reads; clears corresponding
PODR_x bit for writes
1 Never returned for reads; no effect for writes
Note: See above figures for bit field positions.
12.3.1.5 Pin Assignment Registers (PAR_x)
The pin assignment registers control which functions are currently active on the external pins. All
pin assignment registers are read/write.
12.3.1.5.1 Address Pin Assignment Register (PAR_AD)
The PAR_AD register controls the functions of the A[23:21] pins.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-21
General Purpose I/O Module
7
R
W
6
4
3
2
1
0
PAR_
PAR_
PAR_
ADDR23 ADDR22 ADDR21
0
0
0
0
0
See Note
0
0
0
0
0
Reset
5
Address
IPSBAR + 0x10_0070
Note: Reset state determined during reset configuration as shown in Table 12-8.
Figure 12-38. Address/Data Pin Assignment Register (PAR_AD)
Table 12-8. Reset Values for PAR_AD Bits
Mode of
Operation
Port Size of
External Boot
Device
PAR_ADDR23
Reset Value
PAR_ADDR22
Reset Value
PAR_ADDR21
Reset Value
Master mode
8-bit
1
1
1
16-bit
1
1
1
Table 12-9. PAR_AD Field Descriptions
1
Bits
Name
Description
7–5
PAR_ADDR
The PAR_ADDR bits configure each of the A[23:21] pins for one of their primary functions
or GPIO.
0 A[23:21] pin configured for GPIO
1 A[23:21] pin configured for address bit 23–21 function or CS[6:4] function1
4–0
—
Reserved, should be cleared.
The selection between the address function and chip select function on each of the A[23:21] pins is determined by the
value of the RCSC field in the CIM reset configuration register.
12.3.1.5.2 External Bus Control Pin Assignment Register (PAR_BUSCTL)
The PAR_BUSCTL register controls the functions of the external bus control signal pins.
R
15
14
0
0
0
0
W
Reset
Address
13
12
11
10
9
PAR_ PAR_ PAR_TEA PAR_
OE
TA
RWB
1
1
1
1
1
8
0
0
7
6
5
4
PAR_TSIZ1 PAR_TSIZ0
1
1
1
1
3
2
1
0
PAR_TS
PAR_TIP
1
1
1
1
IPSBAR + 0x10_0072
Figure 12-39. External Bus Control Pin Assignment (PAR_BUSCTL)
MCF5275 Reference Manual, Rev. 2
12-22
Freescale Semiconductor
Memory Map/Register Definition
Table 12-10. PAR_BUSCTL Field Descriptions
Bits
Name
15–14
—
13
PAR_OE
OE pin assignment. The PAR_OE bit configures the OE pin for its primary function or
GPIO.
0 OE pin configured for GPIO
1 OE pin configured for external bus OE function
12
PAR_TA
TA pin assignment. The PAR_TA bit configures the OE pin for its primary function or GPIO.
0 TA pin configured for GPIO
1 TA pin configured for external bus TA function
11–10
PAR_TEA
TEA pin assignment. The PAR_TEA field configures the TEA pin for its primary functions
or GPIO.
0x TEA pin configured for general purposeI/O
10 TEA pin configured for DMA request 1 (DREQ1) function
11 TEA pin configured for external bus TEA function
9
Description
Reserved, should be cleared.
PAR_RWB R/W Pin Assignment Bit
The PAR_RWB bit configures the R/W pin for its primary function or GPIO.
0 R/W pin configured for GPIO
1 R/W pin configured for external bus read/write function
8
—
7–0
Reserved, should be cleared
PAR_TSIZ1 TSIZ[1:0], TS, and TIP pin assignment. These bit fields configure the TSIZ[1:0], TS, and
PAR_TSIZ0 TIP pins for one of their primary functions or GPIO.
PAR_TS
PAR_TIP
PAR_TSIZ1 PAR_TSIZ0
PAR_TS
PAR_TIP
00
GPIO
GPIO
GPIO
GPIO
01
GPIO
GPIO
GPIO
GPIO
10
DACK1
DACK0
DACK2
DREQ0
11
TSIZ1
TSIZ0
TS
TIP
12.3.1.5.3 External IRQ Pin Assignment Register (PAR_IRQ)
The PAR_IRQ register controls the functions of the external IRQn pins. To configure these pins
for GPIO, set the corresponding bits and refer to Chapter 14, “Edge Port Module (EPORT).”
R
15
14
13
12
11
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
10
9
8
7
6
PAR_ PAR_ PAR_ PAR_IRQ4
IRQ7 IRQ6 IRQ5
0
0
0
0
0
5
4
PAR_IRQ3
0
0
3
2
1
PAR_IRQ2 PAR_
IRQ1
0
0
0
0
0
0
IPSBAR + 0x10_0074
Figure 12-40. IRQ Pin Assignment Register (PAR_IRQ)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-23
General Purpose I/O Module
Table 12-11. PAR_IRQ Field Descriptions
Bits
Name
15–11
—
Description
Reserved, should be cleared.
10–8
PAR_IRQ7 IRQ[7:5] pin assignment. Configures the IRQ[7:5] pins for their primary function or GPIO.
PAR_IRQ6 0 IRQ[7:5] configured for GPIO
PAR_IRQ5 1 IRQ[7:5] configured for IRQ[7:5] function
7–2
PAR_IRQ4 IRQ[4:2] pin assignment. The PAR_IRQ[7:2] bits configure the IRQ[4:2] pins for their
PAR_IRQ3 primary or alternate functions.
PAR_IRQ2
PAR_IRQ4
PAR_IRQ3
PAR_IRQ2
1
0
00
Reserved
Reserved
Reserved
01
Reserved
Reserved
Reserved
10
DREQ2
DREQ3
DREQ2
11
IRQ4
IRQ3
IRQ2
PAR_IRQ1 IRQ1 pin assignment. Configures the IRQ1 pin for primary function or GPIO.
0 IRQ1 configured for GPIO
1 IRQ1 configured for IRQ1 function
—
Reserved, should be cleared.
12.3.1.5.4 Byte Strobe Pin Assignment Register (PAR_BS)
The PAR_BS register controls the functions of the byte strobe pins.
R
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
0
0
PAR_BS
W
Reset
Address
1
1
IPSBAR + 0x10_0084
Figure 12-41. Byte Strobe Pin Assignment Register (PAR_BS)
Table 12-12. PAR_BS Field Descriptions
Bits
Name
7–4
—
3–2
PAR_BS
1–0
—
Description
Reserved, should be cleared.
BS[3:2] pin assignment. The PAR_BS[3:2] bits configure the BS[3:2] pins for their primary
function or GPIO.
0 BS[3:2] pin configured for GPIO
1 BS[3:2] pin configured for BS[3:2] function
Refer to Chapter 9, “Chip Configuration Module (CCM)” for more information on reset
configuration.
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
12-24
Freescale Semiconductor
Memory Map/Register Definition
12.3.1.5.5 Chip Select Pin Assignment Register (PAR_CS)
The PAR_CS register controls the functions of the EIM chip select pins.
7
6
5
4
R
3
2
1
0
PAR_CS
0
W
Reset
1
1
1
1
Address
1
1
1
0
IPSBAR + 0x10_0071
Figure 12-42. Chip Select Pin Assignment Register (PAR_CS)
Table 12-13. PAR_CS Field Descriptions
Bits
Name
Description
7–1
PAR_CS
CS[7:1] pin assignment. The PAR_CS[7:1] bits configure the CS[7:1] pins for their primary
functions or GPIO.
0 CS[7:1] pins configured for GPIO
1 CS[7:1] pins configured for EIM CS[7:1] function
0
—
Reserved, should be cleared.
12.3.1.5.6 SDRAM Control Pin Assignment Register (PAR_SDRAM)
The PAR_SDRAM register controls the function of the SDRAM controller pins.
R
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
9
8
7
6
5
4
3
2
1
0
PAR_SDCS1 PAR_SDCS0 PAR_ PAR_ PAR_ PAR_ PAR_SDQS
SRAS SCAS SDWE SCKE
1
1
1
1
1
1
1
1
1
1
IPSBAR + 0x10_0080
Figure 12-43. SDRAM Control Pin Assignment (PAR_SDRAM)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-25
General Purpose I/O Module
Table 12-14. PAR_SDRAM Field Descriptions
Bits
Name
Description
15–10
—
9–6
PAR_SDCS1
PAR_SDCS0
Reserved, should be cleared.
SD_CS[1:0] pin assignment. These bits configure the SD_CS[1:0] pins for their primary
functions or GPIO.
PAR_SDCS1
PAR_SDCS0
00
GPIO
GPIO
01
GPIO
GPIO
10
CS3
CS2
11
SD_CS1
SD_CS0
5
PAR_SRAS
SD_SRAS pin assignment. This bit configures the SD_SRAS pin for its primary function or
GPIO.
0 SD_SRAS pin configured for GPIO
1 SD_SRAS pin configured for SDRAMC RAS function
4
PAR_SCAS
SD_SCAS pin assignment. This bit configures the SD_SCAS pin for its primary function or
GPIO.
0 SD_SCAS pin configured for GPIO
1 SD_SCAS pin configured for SDRAMC CAS function
3
PAR_SDWE
SD_WE pin assignment. This bit configures the SD_WE pin for its primary function or
GPIO.
0 SD_WE pin configured for GPIO
1 SD_WE pin configured for SDRAMC WE function
2
PAR_SCKE
SD_CKE pin assignment. This bit configures the SD_CKE pin for its primary function or
GPIO.
0 SD_CKE pin configured for GPIO
1 SD_CKE pin configured for SDRAMC clock enable function
1–0
PAR_SDQS
SD_DQS[3:2] pin assignment. These bits configure the SD_DQS[3:2] pins for their primary
functions or GPIO.
0 SD_DQS[3:2] pin configured for GPIO
1 SD_DQS[3:2] pin configured for SD_DQS[3:2] function
12.3.1.5.7 FEC/I2C Pin Assignment Register (PAR_FECI2C)
The PAR_FECI2C register controls the functions of the I2C and some of the FEC pins.
R
15
14
13
12
0
0
0
0
0
0
0
0
W
Reset
Address
11
10
9
8
7
PAR_MDIO0 PAR_MDC0 PAR_
MDIO1
0
0
0
0
0
6
5
4
0
PAR_
MDC1
0
0
0
0
3
2
PAR_SDA
0
0
1
0
PAR_SCL
0
0
IPSBAR + 0x10_0082
Figure 12-44. FEC/I2C Pin Assignment (PAR_FECI2C)
MCF5275 Reference Manual, Rev. 2
12-26
Freescale Semiconductor
Memory Map/Register Definition
Table 12-15. PAR_FECI2C Field Descriptions
Bits
Name
15–12
—
11–8
7
Description
Reserved, should be cleared.
PAR_MDIO0 FEC 0 pin assignment. These bit fields configure the FEC0_MDIO and FEC0_MDC pins
PAR_MDC0 for one of their primary functions or GPIO.
PAR_MDIO0
PAR_MDC0
00
GPIO
GPIO
01
U2RXD
U2TXD
10
I2C_SDA
I2C_SCL
11
FEC0_MDIO
FEC0_MDC
PAR_MDIO1 FEC1_MDIO pin assignment. This bit configures the FEC1_MDIO pin for its primary
function or GPIO.
0 FEC1_MDIO pin configured for GPIO
1 FEC1_MDIO pin configured for FEC MDIO function
6
—
5
PAR_MDC1
4
—
3–0
PAR_SDA
PAR_SCL
Reserved, should be cleared.
FEC1_MDC pin assignment. This bit configures the FEC1_MDC pin for its primary
function or GPIO.
0 FEC1_MDC pin configured for GPIO
1 FEC1_MDC pin configured for FEC MDC function
Reserved, should be cleared.
I2C pin assignment. These bit fields configure the I2C_SDA and I2C_SCL pins for one of
their primary functions or GPIO.
PAR_SDA
PAR_SCL
00
GPIO
GPIO
01
U2RXD
U2TXD
10
GPIO
GPIO
11
I2C_SDA
I2C_SCL
12.3.1.5.8 UART Pin Assignment Register (PAR_UART)
The PAR_UART register controls the functions of the UART pins.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-27
General Purpose I/O Module
R
15
14
0
0
0
0
W
Reset
13
12
11
10
9
8
7
6
PAR_ PAR_ PAR_U2CTS PAR_U2RTS PAR_ PAR_
U2RXD U2TXD
U1RXD U1TX
D
0
Address
0
0
0
0
0
0
5
4
PAR_U1CTL
0
0
3
2
PAR_ PAR_
U0RXD U0TXD
0
0
0
1
0
PAR_U0CTL
0
0
IPSBAR + 0x10_007C
Figure 12-45. UART Pin Assignment (PAR_UART)
Table 12-16. PAR_UART Field Descriptions
Bits
Name
15–14
—
Description
Reserved, should be cleared.
13
PAR_U2RXD U2RXD pin assignment. This bit configures the U2RXD pin for its primary function or
GPIO.
0 U2RXD pin configured for GPIO
1 U2RXD pin configured for UART2 receive data function
12
PAR_U2TXD U2TXD pin assignment. This bit configures the U2TXD pin for its primary function or
GPIO.
0 U2TXD pin configured for GPIO
1 U2TXD pin configured for UART2 transmit data function
11–8
PAR_U2CTS UART 2 pin assignment. These bit fields configure the U2CTS, and U2RTS pins for
PAR_U2RTS one of their primary functions or GPIO.
7–6
PAR_U2CTS
PAR_U2RTS
00
GPIO
GPIO
01
GPIO
GPIO
10
PWM1
PWM0
11
U2CTS
U2RTS
PAR_U1RXD UART 1 pin assignment. These bit fields configure the U1RXD and U1TXD pins for
PAR_U1TXD their primary function or GPIO.
PAR_U1RXD PAR_U1TXD
5-4
0
GPIO
GPIO
1
U1RXD
U1TXD
PAR_U1CTL U1CTS and U1RTS pin assignment. These two bits configure the U1CTS and U1RTS
pins for primary function or GPIO.
00 U1CTS and U1RTS pins configured for GPIO
01 Reserved
10 Reserved
11 U1CTS and U1RTS pins configured for UART1 control functions.
MCF5275 Reference Manual, Rev. 2
12-28
Freescale Semiconductor
Memory Map/Register Definition
Table 12-16. PAR_UART Field Descriptions (Continued)
Bits
Name
3–2
Description
PAR_U0RXD UART 0 pin assignment. These bit fields configure the U0RXD and U0TXD pins for
PAR_U0TXD their primary function or GPIO.
PAR_U0RXD PAR_U0TXD
0
GPIO
GPIO
1
U0RXD
U0TXD
PAR_U0CTL U0CTS and U0RTS pin assignment. These two bits configure the U0CTS and U0RTS
pins for primary function or GPIO.
00 U0CTS and U0RTS pins configured for GPIO
01 Reserved
10 Reserved
11 U0CTS and U0RTS pins configured for UART0 control functions.
1-0
12.3.1.5.9 QSPI Pin Assignment Register (PAR_QSPI)
The PAR_QSPI register controls the functions of the QSPI pins.
R
15
14
0
0
0
0
W
Reset
13
12
11
10
9
PAR_PCS3 PAR_PCS2 PAR_
PCS1
0
Address
0
0
0
0
8
7
6
0
PAR_
PCS0
0
0
0
0
5
4
PAR_SCK
0
0
3
2
PAR_DIN
0
0
1
0
PAR_
DOUT
0
0
0
IPSBAR + 0x10_007E
Figure 12-46. QSPI Pin Assignment Register (PAR_QSPI)
Table 12-17. PAR_QSPI Field Descriptions
Bits
Name
15–14
—
13–10
PAR_PCS3
PAR_PCS2
Description
Reserved, should be cleared.
QSPI_PCS[3:2] pin assignment. These fields configure the QSPI_PCS[3:2] pins for one
of their primary functions or GPIO.
PAR_PCS3
PAR_PCS2
00
GPIO
GPIO
01
DACK3
DACK2
10
PWM3
PWM2
11
QSPI_PCS3
QSPI_PCS2
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-29
General Purpose I/O Module
Table 12-17. PAR_QSPI Field Descriptions (Continued)
Bits
Name
9
PAR_PCS1
8
—
7
PAR_PCS0
6
—
5–2
PAR_SCK
PAR_DIN
1
0
Description
QSPI_PCS1 pin assignment. This bit configures the QSPI_PCS1 pin for its primary
function or GPIO.
0 QSPI_PSC1 pin configured for GPIO
1 QSPI_PSC1 pin configured for QSPI PCS1 function
Reserved, should be cleared.
QSPI_PCS0 pin assignment. This bit configures the QSPI_PCS0 pin for its primary
function or GPIO.
0 QSPI_PSC0 pin configured for GPIO
1 QSPI_PSC0 pin configured for QSPI PCS0 function
Reserved, should be cleared.
QSPI_SCK & QSPI_DIN pin assignment. These fields configure the QSPI_SCK &
QSPI_DIN pins for one of their primary functions or GPIO.
PAR_SCK
PAR_DIN
00
GPIO
GPIO
01
GPIO
GPIO
10
I2C_SCL
I2C_SDA
11
QSPI_SCK
QSPI_DIN
PAR_DOUT QSPI_DOUT pin assignment. This bit configures the QSPI_DOUT pin for its primary
function or GPIO.
0 QSPI_DOUT pin configured for GPIO
1 QSPI_DOUT pin configured for QSPI DOUT function
—
Reserved, should be cleared.
12.3.1.6 Timer Pin Assignment Registers (PAR_TIMERH & PAR_TIMERL)
The PAR_TIMERH and PAR_TIMERL registers control the functions of the DMA timer pins.
7
R
6
PAR_T3IN
5
4
PAR_T3OUT
3
2
PAR_T2IN
1
0
PAR_T2OUT
W
Reset
Address
0
0
0
0
0
0
0
0
IPSBAR + 0x10_007A
Figure 12-47. Timer Pin Assignment Register (PAR_TIMERH)
MCF5275 Reference Manual, Rev. 2
12-30
Freescale Semiconductor
Memory Map/Register Definition
Table 12-18. PAR_TIMERH Field Description
Bits
7–4
3–0
Name
Description
PAR_T3IN Timer 3 pin assignment. These bit fields configure the T3IN and T3OUT pins for one of
PAR_T3OUT their primary functions or GPIO.
PAR_T3IN
PAR_T3OUT
00
GPIO
GPIO
01
U2RTS
U2CTS
10
T3OUT
PWM3
11
T3IN
T3OUT
PAR_T2IN Timer 2 pin assignment. These bit fields configure the T2IN and T2OUT pins for one of
PAR_T2OUT their primary functions or GPIO.
7
R
6
PAR_T1IN
5
PAR_T2IN
PAR_T2OUT
00
GPIO
GPIO
01
GPIO
GPIO
10
T2OUT
PWM2
11
T2IN
T2OUT
4
PAR_T1OUT
3
2
PAR_T0IN
1
0
PAR_T0OUT
W
Reset
Address
0
0
0
0
0
0
0
0
IPSBAR + 0x10_007B
Figure 12-48. Timer Pin Assignment Register (PAR_TIMERL)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-31
General Purpose I/O Module
Table 12-19. PAR_TIMERL Field Description
Bits
Name
7–4
Description
PAR_T1IN Timer 1 pin assignment. These bit fields configure the T1IN and T1OUT pins for one of
PAR_T1OUT their primary functions or GPIO.
3–0
PAR_T1IN
PAR_T1OUT
00
GPIO
GPIO
01
GPIO
GPIO
10
T1OUT
PWM1
11
T1IN
T1OUT
PAR_T0IN Timer 1pin assignment. These bit fields configure the T0IN and T0OUT pins for one of
PAR_T0OUT their primary functions or GPIO.
PAR_T0IN
PAR_T0OUT
00
GPIO
GPIO
01
GPIO
GPIO
10
T0OUT
PWM0
11
T0IN
T0OUT
12.3.1.7 USB Pin Assignment Register (PAR_USB)
The PAR_USB register controls the functions of the USB pins.
R
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
8
7
6
5
4
3
2
1
0
PAR_ PAR_ PAR_ PAR_ PAR_ PAR_ PAR_ PAR_ PAR_
USPD UCLK URN URP URX USSP UTN UTP UTXEN
0
0
0
0
0
0
0
0
0
IPSBAR + 0x10_0076
Figure 12-49. USB Pin Assignment Register (PAR_USB)
Table 12-21. PAR_USB Descriptions
Bits
Name
15–9
—
8
PAR_USPD
Description
Reserved, should be cleared.
USB_SPEED pin assignment. This bit configures the USB_SPEED pin for its primary
function or GPIO.
0 USB_SPEED pin configured for GPIO
1 USB_SPEED pin configured for USB SPEED function
MCF5275 Reference Manual, Rev. 2
12-32
Freescale Semiconductor
Memory Map/Register Definition
Table 12-21. PAR_USB Descriptions (Continued)
Bits
Name
Description
7
PAR_UCLK
USB_CLK pin assignment. This bit configures the USB_CLK pin for its primary function
or GPIO.
0 USB_CLK pin configured for GPIO
1 USB_CLK pin configured for USB CLK function
6
PAR_URN
USB_RN pin assignment. This bit configures the USB_RN pin for its primary function or
GPIO.
0 USB_RN pin configured for GPIO
1 USB_RN pin configured for USB RN function
5
PAR_URP
USB_RP pin assignment. This bit configures the USB_RP pin for its primary function or
GPIO.
0 USB_RP pin configured for GPIO
1 USB_RP pin configured for USB RP function
4
PAR_URX
USB_RXD pin assignment. This bit configures the USB_ RXD pin for its primary function
or GPIO.
0 USB_RXD pin configured for GPIO
1 USB_RXD pin configured for USB RX function
3
PAR_USSP
2
PAR_UTN
USB_TN pin assignment. This bit configures the USB_TN pin for its primary function or
GPIO.
0 USB_TN pin configured for GPIO
1 USB_TN pin configured for USB TN function
1
PAR_UTP
USB_TP pin assignment. This bit configures the USB_TP pin for its primary function or
GPIO.
0 USB_TP pin configured for GPIO
1 USB_TP pin configured for USB TP function
0
USB_SUSP pin assignment. This bit configures the USB_SUSP pin for its primary
function or GPIO.
0 USB_SUSP pin configured for GPIO
1 USB_SUSP pin configured for USB SUSP function
PAR_UTXEN USB_TXEN pin assignment. This bit configures the USB_TXEN pin for its primary
function or GPIO.
0 USB_TXEN pin configured for GPIO
1 USB_TXEN pin configured for USB TX EN function
12.3.1.8 FEC0 & FEC1 Pin Assignment Registers (PAR_FEC0 & PAR_FEC1)
The PAR_FEC0 and PAR_FEC1 registers control the functions of the FEC pins.
7
6
R PAR_ PAR_
FEC0H FEC0L
W
Reset
Address
0
0
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x10_0078
Figure 12-50. FEC Pin Assignment Register (PAR_FEC0)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-33
General Purpose I/O Module
7
6
R PAR_ PAR_
FEC1H FEC1L
W
Reset
Address
0
0
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x10_0079
Figure 12-51. FEC Pin Assignment Register (PAR_FEC1)
Table 12-22. PAR_FEC0 & PAR_FEC1 Field Descriptions
Bits
Description
7
PAR_FEC0H FECnH pin assignment. These bits configure the FECnH pins for their primary function
PAR_FEC1H or GPIO.
0 FECnH pins configured for GPIO
1 FECnH pins configured for ethernet 7-wire mode
6
PAR_FEC0L FECnL pin assignment. These bits configure the FECnL pins for their primary function
PAR_FEC1L or GPIO.
0 FECnL pins configured for GPIO
1 FECnL pins configured for ethernet full mode
5–0
12.4
Name
—
Reserved, should be cleared.
Functional Description
12.4.1 Overview
Initial pin function is determined during reset configuration. The pin assignment registers allow
the user to select among various primary functions and general purpose I/O after reset.
Most pins are configured as general purpose I/O by default. The notable exceptions to this are
external bus control pins, address/data pins, and chip select pins. These pins are configured for
their primary functions after reset.
Every general purpose I/O pin is individually configurable as an input or an output via a data
direction register (PDDR_x).
Every GPIO port has an output data register (PODR_x) and a pin data register (PPDSDR_x) to
monitor and control the state of its pins. Data written to a PODR_x register is stored and then
driven to the corresponding port x pins configured as outputs.
Reading a PODR_x register returns the current state of the register regardless of the state of the
corresponding pins.
Reading a PPDSDR_x register returns the current state of the corresponding pins when configured
as general purpose I/O, regardless of whether the pins are inputs or outputs.
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12-34
Freescale Semiconductor
Initialization/Application Information
Every GPIO port has a PPDSDR_x register and a clear register (PCLRR_x) for setting or clearing
individual bits in the PODR_x register.
Initial pin output drive strength is determined during reset configuration. The DSCR_x registers
allow the pin drive strengths to be configured on a per-function basis after reset.
The MCF5275 ports module does not generate interrupt requests.
12.4.2 Port Digital I/O Timing
Input data on all pins configured as general purpose input is synchronized to the rising edge of the
internal bus clock, CLKOUT, as shown in Figure 12-52.
CLKOUT
Input
Pin
Register
Pin Data
Figure 12-52. General Purpose Input Timing
Data written to the PODR_x register of any pin configured as a general purpose output is
immediately driven to its respective pin, as shown in Figure 12-53.
CLKOUT
Output Data
Register
Output Pin
Figure 12-53. General Purpose Output Timing
12.5
Initialization/Application Information
The initialization for the MCF5275 ports module is done during reset configuration. All registers
are reset to a predetermined state. Refer to Section 12.3, “Memory Map/Register Definition,” for
more details on reset and initialization.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
12-35
General Purpose I/O Module
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 13
Interrupt Controller Modules
13.1
Introduction
This section details the functionality for the MCF5275 interrupt controllers (INTC0, INTC1). The
general features of the MCF5275 interrupt controller block include:
•
•
•
•
•
•
58 interrupt sources, organized as:
— 51 fully-programmable interrupt sources
— 7 fixed-level interrupt sources
Each of the 58 sources has a unique interrupt control register (ICRnx) to define the
software-assigned levels and priorities within the level
Unique vector number for each interrupt source
Ability to mask any individual interrupt source, plus global mask-all capability
Supports both hardware and software interrupt acknowledge cycles
“Wake-up” signal from low-power stop modes
The 51 fully-programmable and seven fixed-level interrupt sources for the two interrupt
controllers on the MCF5275 handle the complete set of interrupt sources from all of the modules
on the device. This section describes how the interrupt sources are mapped to the interrupt
controller logic and how interrupts are serviced.
13.1.1 68K/ColdFire Interrupt Architecture Overview
Before continuing with the specifics of the MCF5275 interrupt controllers, a brief review of the
interrupt architecture of the 68K/ColdFire family is appropriate.
The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a
3-bit encoded interrupt priority level sent from the interrupt controller to the core, providing 7
levels of interrupt requests. Level 7 represents the highest priority interrupt level, while level 1 is
the lowest priority. The processor samples for active interrupt requests once per instruction by
comparing the encoded priority level against a 3-bit interrupt mask value (I) contained in bits 10:8
of the machine’s status register (SR). If the priority level is greater than the SR[I] field at the
sample point, the processor suspends normal instruction execution and initiates interrupt exception
processing. Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor,
while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the
SR[I] field. For correct operation, the ColdFire requires that, once asserted, the interrupt source
remain asserted until explicitly disabled by the interrupt service routine.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
13-1
Interrupt Controller Modules
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode
and then fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is
known as the interrupt acknowledge (IACK) cycle with the ColdFire implementation using a
special encoding of the transfer type and transfer modifier attributes to distinguish this data fetch
from a “normal” memory access. The fetched data provides an index into the exception vector
table which contains 256 addresses, each pointing to the beginning of a specific exception service
routine. In particular, vectors 64 - 255 of the exception vector table are reserved for user interrupt
service routines. The first 64 exception vectors are reserved for the processor to handle reset, error
conditions (access, address), arithmetic faults, system calls, etc. Once the interrupt vector number
has been retrieved, the processor continues by creating a stack frame in memory. For ColdFire, all
exception stack frames are 2 longwords in length, and contain 32 bits of vector and status register
data, along with the 32-bit program counter value of the instruction that was interrupted (see
Section 3.6, “Exception Stack Frame Definition” for more information on the stack frame format).
After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from
the exception vector table using the vector number as the offset, and then jumps to that address to
begin execution of the service routine. After the status register is stored in the exception stack
frame, the SR[I] mask field is set to the level of the interrupt being acknowledged, effectively
masking that level and all lower values while in the service routine. For many peripheral devices,
the processing of the IACK cycle directly negates the interrupt request, while other devices require
that request to be explicitly negated during the processing of the service routine.
For the MCF5275, the processing of the interrupt acknowledge cycle is fundamentally different
than previous 68K/ColdFire cores. In the new approach, all IACK cycles are directly handled by
the interrupt controller, so the requesting peripheral device is not accessed during the IACK. As a
result, the interrupt request must be explicitly cleared in the peripheral during the interrupt service
routine. For more information, see Section 13.1.2.3, “Interrupt Vector Determination.”
Unlike the M68000 family, all ColdFire processors guarantee that the first instruction of the
service routine is executed before sampling for interrupts is resumed. By making this initial
instruction a load of the SR, interrupts can be safely disabled, if required.
During the execution of the service routine, the appropriate actions must be performed on the
peripheral to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual
at http://www.freescale.com/coldfire.
13.1.2 Interrupt Controller Theory of Operation
To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63
interrupt sources are organized as 7 levels, with each level supporting up to 9 prioritized requests.
Consider the priority structure within a single interrupt level (from highest to lowest priority) as
shown in Table 13-1.
MCF5275 Reference Manual, Rev. 2
13-2
Freescale Semiconductor
Introduction
Table 13-1. Interrupt Priority Within a Level
ICR[2:0]
Priority
Interrupt
Sources
111
7 (Highest)
8–63
110
6
8–63
101
5
8–63
100
4
8–63
—
Fixed Midpoint Priority
1–7
011
3
8–63
010
2
8–63
001
1
8–63
000
0 (Lowest)
8–63
The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt
source 1–7 (IRQ[1:7] from the Edgeport module) are fixed at the corresponding level’s midpoint
priority. Thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single
interrupt level. The “fixed” interrupt source is hardwired to the given level, and represents the
mid-point of the priority within the level. For the fully-programmable interrupt sources, the 3-bit
level and the 3-bit priority within the level are defined in the 8-bit interrupt control register
(ICRnx).
The operation of the interrupt controller can be broadly partitioned into three activities:
•
•
•
Recognition
Prioritization
Vector determination during IACK
13.1.2.1 Interrupt Recognition
The interrupt controller continuously examines the request sources and the interrupt mask register
to determine if there are active requests. This is the recognition phase.
13.1.2.2 Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level, and the
resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller. The
decoded priority levels from all the interrupt controllers are logically summed together and the
highest enabled interrupt request is then encoded into a 3-bit priority level that is sent to the
processor core during this prioritization phase.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
13-3
Interrupt Controller Modules
13.1.2.3 Interrupt Vector Determination
Once the core has sampled for pending interrupts and begun interrupt exception processing, it
generates an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a
memory-mapped byte read by the processor, and routed to the appropriate interrupt controller.
Next, the interrupt controller extracts the level being acknowledged from address bits[4:2], and
then determines the highest priority interrupt request active for that level, and returns the 8-bit
interrupt vector for that request to complete the cycle. The 8-bit interrupt vector is formed using
the following algorithm:
For INTC0,
vector_number = 64 + interrupt source number
For INTC1,
vector_number = 128 + interrupt source number
Recall vector_numbers 0 - 63 are reserved for the ColdFire processor and its internal exceptions.
Thus, the following mapping of bit positions to vector numbers applies for the INTC0:
if interrupt source 1 is active and acknowledged,then vector_number =
65
if interrupt source 2 is active and acknowledged,then vector_number =
66
...
if interrupt source 8 is active and acknowledged,then vector_number =
72
if interrupt source 9 is active and acknowledged,then vector_number =
73
...
if interrupt source 62 is active and acknowledged,then vector_number = 126
The net effect is a fixed mapping between the bit position within the source to the actual interrupt
vector number.
If there is no active interrupt source for the given level, a special “spurious interrupt” vector
(vector_number = 24) is returned and it is the responsibility of the service routine to handle this
error situation.
Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle
since the interrupt controller completely services the acknowledge. This means the interrupt
source must be explicitly disabled in the interrupt service routine. This design provides unique
vector capability for all interrupt requests, regardless of the “complexity” of the peripheral device.
13.2
Memory Map/Register Definition
The register programming model for the interrupt controllers is memory-mapped to a 256-byte
space. In the following discussion, there are a number of program-visible registers greater than 32
bits in size. For these control fields, the physical register is partitioned into two 32-bit values: a
register “high” (the upper longword) and a register “low” (the lower longword). The nomenclature
<reg_name>H and <reg_name>L is used to reference these values.
MCF5275 Reference Manual, Rev. 2
13-4
Freescale Semiconductor
Memory Map/Register Definition
The registers and their locations are defined in Table 13-3. The offsets listed start from the base
address for each interrupt controller. The base addresses for the interrupt controllers are listed
below:
Table 13-2. Interrupt Controller Base Addresses
1
Interrupt Controller Number
Base Address
INTC0
IPSBAR + 0xC00
INTC1
IPSBAR + 0xD00
Global IACK Registers Space1
IPSBAR + 0xF00
This address space only contains the SWIACK and L1ACK-L7IACK registers. See Section 13.2.1.7,
“Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)" for more information
Table 13-3. Interrupt Controller Memory Map
IPSBAR Offset
Bits[31:24]
Bits[23:16]
Bits[15:8]
Bits[7:0]
0xC00 & 0xD00
Interrupt Pending Register High (IPRH), [63:32]
0xC04 & 0xD04
Interrupt Pending Register Low (IPRL), [31:1]
0xC08 & 0xD08
Interrupt Mask Register High (IMRH), [63:32]
0xC0C & 0xD0C
Interrupt Mask Register Low (IMRL), [31:0]
0xC10 & 0xD10
Interrupt Force Register High (INTFRCH), [63:32]
0xC14 & 0xD14
Interrupt Force Register Low (INTFRCL), [31:1]
0xC18 & 0xD18
IRLR[7:1]
IACKLPR[7:0]
0xC1C - 0xC3C &
0xD1C - 0D3C
Reserved
Reserved
0xC40 & 0xD40
Reserved
ICR01
ICR02
ICR03
0xC44 & 0xD44
ICR04
ICR05
ICR06
ICR07
0xC48 & 0xD48
ICR08
ICR09
ICR10
ICR11
0xC4C & 0xD4C
ICR12
ICR13
ICR14
ICR15
0xC50 & 0xD50
ICR16
ICR17
ICR18
ICR19
0xC54 & 0xD54
ICR20
ICR21
ICR22
ICR23
0xC58 & 0xD58
ICR24
ICR25
ICR26
ICR27
0xC5C & 0xD5C
ICR28
ICR29
ICR30
ICR31
0xC60 & 0xD60
ICR32
ICR33
ICR34
ICR35
0xC64 & 0xD64
ICR36
ICR37
ICR38
ICR39
0xC68 & 0xD68
ICR40
ICR41
ICR42
ICR43
0xC6C & 0xD6C
ICR44
ICR45
ICR46
ICR47
0xC70 & 0xD70
ICR48
ICR49
ICR50
ICR51
0xC74 & 0xD74
ICR52
ICR53
ICR54
ICR55
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
13-5
Interrupt Controller Modules
Table 13-3. Interrupt Controller Memory Map (Continued)
IPSBAR Offset
Bits[31:24]
Bits[23:16]
Bits[15:8]
Bits[7:0]
0xC78 & 0xD78
ICR56
ICR57
ICR58
ICR59
0xC7C & 0xD7C
ICR60
ICR61
ICR62
ICR63
0xC80 - 0xCDC &
0xD80 - & 0xDDC
Reserved
0xCE0 & 0xDE0
SWIACK
Reserved
0xCE4 & 0xDE4
L1IACK
Reserved
0xCE8 & 0xDE8
L2IACK
Reserved
0xCEC & 0xDEC
L3IACK
Reserved
0xCF0 & 0xDF0
L4IACK
Reserved
0xCF4 & 0xDF4
L5IACK
Reserved
0xCF8 & 0xDF8
L6IACK
Reserved
0xCFC & 0xDFC
L7IACK
Reserved
13.2.1 Register Descriptions
13.2.1.1 Interrupt Pending Registers (IPRHn, IPRLn)
The IPRHn and IPRLn registers, Figure 13-1 and Figure 13-2, are each 32 bits in size, and provide
a bit map for each interrupt request to indicate if there is an active request (1 = active request, 0 =
no request) for the given source. The state of the interrupt mask register does not affect the IPRn.
The IPRn is cleared by reset. The IPRn is a read-only register, so any attempted write to this
register is ignored. Bit 0 is not implemented and reads as a zero.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
INT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
INT
W
Reset
Address
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0C00 (INTC0); IPSBAR + 0x00_0D00 (INTC1)
Figure 13-1. Interrupt Pending Register High (IPRHn)
MCF5275 Reference Manual, Rev. 2
13-6
Freescale Semiconductor
Memory Map/Register Definition
Table 13-4. IPRHn Field Descriptions
Bits
Name
Description
31–0
INT
Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn
bit determines whether an interrupt condition can generate an interrupt. At every system
clock, the IPRHn samples the signal generated by the interrupting source. The
corresponding IPRHn bit reflects the state of the interrupt signal even if the corresponding
IMRHn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
INT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INT
0
W
Reset
0
0
0
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0C04 (INTC0), IPSBAR + 0x00_0D04 (INTC1)
Figure 13-2. Interrupt Pending Register Low (IPRLn)
Table 13-5. IPRLn Field Descriptions
Bits
Name
Description
31–1
INT
Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRLn
bit determines whether an interrupt condition can generate an interrupt. At every system
clock, the IPRLn samples the signal generated by the interrupting source. The
corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding
IMRLn bit is set.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
0
—
Reserved, should be cleared.
13.2.1.2 Interrupt Mask Register (IMRHn, IMRLn)
The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each interrupt
to allow the request to be disabled (1 = disable the request, 0 = enable the request). The IMRn is
set to all ones by reset, disabling all interrupt requests. The IMRn can be read and written. A write
that sets bit 0 of the IMR forces the other 63 bits to be set, disabling all interrupt sources, and
providing a global mask-all capability.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
13-7
Interrupt Controller Modules
NOTE
If an interrupt source is being masked in the interrupt controller mask
register (IMR) or a module’s interrupt mask register while the
interrupt mask in the status register (SR[I]) is set to a value lower than
the interrupt’s level, a spurious interrupt may occur. This is because by
the time the status register acknowledges this interrupt, the interrupt
has been masked. A spurious interrupt is generated because the CPU
cannot determine the interrupt source. To avoid this situation for
interrupts sources with levels 1-6, first write a higher level interrupt
mask to the status register, before setting the mask in the IMR or the
module’s interrupt mask register. After the mask is set, return the
interrupt mask in the status register to its previous value. Since level 7
interrupts cannot be disabled in the status register prior to masking,
use of the IMR or module interrupt mask registers to disable level 7
interrupts is not recommended.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
INT_MASK
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
R
INT_MASK
W
Reset
1
1
1
Address
1
1
1
1
1
1
IPSBAR + 0x00_0C08 (INTC0), IPSBAR + 0x00_D08 (INTC1)
Figure 13-3. Interrupt Mask Register High (IMRHn)
Table 13-6. IMRHn Field Descriptions
Bits
31–0
Name
Description
INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRHn bit
determines whether an interrupt condition can generate an interrupt. The corresponding
IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is
set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
MCF5275 Reference Manual, Rev. 2
13-8
Freescale Semiconductor
Memory Map/Register Definition
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
INT_MASK
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INT_MASK
MASK
ALL
W
Reset
1
1
1
Address
1
1
1
1
1
1
1
1
1
1
1
1
1
IPSBAR + 0x00_0C0C (INTC0), IPSBAR + 0x00_0D0C (INTC1)
Figure 13-4. Interrupt Mask Register Low (IMRLn)
Table 13-7. IMRLn Field Descriptions
Bits
31–1
0
Name
Description
INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRLn bit
determines whether an interrupt condition can generate an interrupt. The corresponding
IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
MASKALL
Mask all interrupts. Setting this bit will force the other 63 bits of the IMRHn and IMRLn to
ones, disabling all interrupt sources, and providing a global mask-all capability.
13.2.1.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)
The INTFRCHn and INTFRCLn registers are each 32 bits in size and provide a mechanism to
allow software generation of interrupts for each possible source for functional or debug purposes.
The system design may reserve one or more sources to allow software to self-schedule interrupts
by forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate
INTFRCn register. The assertion of an interrupt request via the INTFRCn register is not affected
by the interrupt mask register. The INTFRCn register is cleared by reset.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
13-9
Interrupt Controller Modules
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
INTFRCH
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
INTFRCH
W
Reset
0
0
0
Address
0
0
0
0
0
0
IPSBAR + 0x00_C10 (INTC0), IPSBAR + 0x00_D10 (INTC1)
Figure 13-5. Interrupt Force Register High (INTFRCHn)
Table 13-8. INTFRCHn Field Descriptions
Bits
Name
31–0
INTFRCH
31
30
Description
Interrupt force. Allows software generation of interrupts for each possible source for
functional or debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
INTFRCL
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
INTFRCL
0
W
Reset
0
0
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0C14 (INTC0), IPSBAR + 0x00_0D14 (INTC1)
Figure 13-6. Interrupt Force Register High (INTFRCHn)
Table 13-9. INTFRCLn Field Descriptions
Bits
Name
31–1
INTFRCL
0
—
Description
Interrupt force. Allows software generation of interrupts for each possible source for
functional or debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
Memory Map/Register Definition
13.2.1.4 Interrupt Request Level Register (IRLRn)
This 7-bit register is updated each machine cycle and represents the current interrupt requests for
each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. This register output
from both interrupt controllers (INTC0 & INTC1) are combined encoded into the 3-bit priority
interrupt level driven to the processor core.
7
6
5
R
4
3
2
1
IRQ
0
0
W
Reset
Address
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0C18 (INTC0); IPSBAR + 0x00_0D18 (INTC1)
Figure 13-7. Interrupt Request Level Register (IRLRn)
Table 13-10. IRQLRn Field Descriptions
Bits
Name
7–1
IRQ
0
—
Description
Interrupt requests. Represents the prioritized active interrupts for each level.
0 There are no active interrupts at this level
1 There is an active interrupt at this level
Reserved
13.2.1.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)
Each time an IACK is performed, the interrupt controller responds with the vector number of the
highest priority source within the level being acknowledged. In addition to providing the vector
number directly for the byte-sized IACK read, this 8-bit register is also loaded with information
about the interrupt level and priority being acknowledged. This register provides the association
between the acknowledged “physical” interrupt request number and the programmed interrupt
level/priority. The contents of this read-only register are described in Figure 13-8 and Table 13-11.
7
R
6
0
5
4
3
2
LEVEL
1
0
0
0
PRI
W
Reset
Address
0
0
0
0
0
0
IPSBAR + 0x00_0C19 (INTC0); IPSBAR + 0x00_0D19 (INTC1)
Figure 13-8. IACK Level and Priority Register (IACKLPRn)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
13-11
Interrupt Controller Modules
Table 13-11. IACKLPRn Field Descriptions
Bits
Name
7
—
6–4
LEVEL
3–0
PRI
Description
Reserved
Interrupt level. Represents the interrupt level currently being acknowledged.
Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently
being acknowledged.
0 Priority 0
1 Priority 1
2 Priority 2
3 Priority 3
4 Priority 4
5 Priority 5
6 Priority 6
7 Priority 7
8 Mid-Point Priority associated with the fixed level interrupts only
13.2.1.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))
Each ICRnx specifies the interrupt level (1–7) and the priority within the level (0–7). All ICRnx
registers can be read, but only ICRn8 to ICRn63 can be written. It is the responsibility of the
software to program the ICRnx registers with unique and non-overlapping level and priority
definitions. Failure to program the ICRnx registers in this manner can result in undefined behavior.
If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and
disabled) state.
R:
7
6
0
0
5
4
Address
2
IL
W
Reset
3
1
0
IP
See Note
0
0
0
0
0
0
0
0
See Table 13-2 and Table 13-3 for register offsets
Note: Read only for ICRn1-ICRn7, else Read/Write
Note: It is the responsibility of the software to program the ICRnx
registers with unique and non-overlapping level and priority definitions.
Failure to program the ICRnx registers in this manner can result in
undefined behavior. If a specific interrupt request is completely unused,
the ICRnx value can remain in its reset (and disabled) state.
Figure 13-9. Interrupt Control Register (ICRnx)
Table 13-12. ICRnx Field Descriptions
Bits
Name
7–6
—
Description
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
13-12
Freescale Semiconductor
Memory Map/Register Definition
Table 13-12. ICRnx Field Descriptions (Continued)
Bits
Name
Description
5–3
IL
Interrupt level. Indicates the interrupt level assigned to each interrupt input.
2–0
IP
Interrupt priority. Indicates the interrupt priority for internal modules within the
interrupt-level assignment. 000 represents the lowest priority and 111 represents the
highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the
level, and the IP field will always read as 000.
13.2.1.6.1 Interrupt Sources
The following tables list the interrupt sources for each interrupt request line for INTC0 and
INTC1.
Table 13-13. Interrupt Source Assignment For INTC0
Sourc
e
Modul
e
Flag
1
EPORT
EPF1
Edge port flag 1
Write EPF1 = 1
2
EPF2
Edge port flag 2
Write EPF2 = 1
3
EPF3
Edge port flag 3
Write EPF3 = 1
4
EPF4
Edge port flag 4
Write EPF4 = 1
5
EPF5
Edge port flag 5
Write EPF5 = 1
6
EPF6
Edge port flag 6
Write EPF6 = 1
7
EPF7
Edge port flag 7
Write EPF7 = 1
Cleared when service complete.
Source Description
Flag Clearing Mechanism
8
SCM
SWTI
Software watchdog timeout
9
DMA
DONE
DMA Channel 0 transfer complete Write DONE = 1
10
DONE
DMA Channel 1 transfer complete Write DONE = 1
11
DONE
DMA Channel 2 transfer complete Write DONE = 1
12
DONE
DMA Channel 3 transfer complete Write DONE = 1
13
UART0
INT
UART0 interrupt
Automatically cleared
14
UART1
INT
UART1 interrupt
Automatically cleared
15
UART2
INT
UART2 interrupt
Automatically cleared
16
Not used
17
2
2
I C
IIF
I C interrupt
Write IIF = 0
18
QSPI
INT
QSPI interrupt
Write 1 to appropriate QIR bit
19
TMR0
INT
TMR0 interrupt
Write 1 to appropriate TER0 bit
20
TMR1
INT
TMR1 interrupt
Write 1 to appropriate TER1 bit
21
TMR2
INT
TMR2 interrupt
Write 1 to appropriate TER2 bit
22
TMR3
INT
TMR3 interrupt
Write 1 to appropriate TER3 bit
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
13-13
Interrupt Controller Modules
Table 13-13. Interrupt Source Assignment For INTC0 (Continued)
Sourc
e
Modul
e
Flag
23
FEC0
X_INTF
Transmit frame interrupt
Write X_INTF = 1
24
X_INTB
Transmit buffer interrupt
Write X_INTB = 1
25
UN
Transmit FIFO underrun
Write UN = 1
26
RL
Collision retry limit
Write RL = 1
27
R_INTF
Receive frame interrupt
Write R_INTF = 1
28
R_INTB
Receive buffer interrupt
Write R_INTB = 1
29
MII
MII interrupt
Write MII = 1
30
LC
Late collision
Write LC = 1
31
HBERR
Heartbeat error
Write HBERR = 1
32
GRA
Graceful stop complete
Write GRA = 1
33
EBERR
Ethernet bus error
Write EBERR = 1
34
BABT
Babbling transmit error
Write BABT = 1
35
BABR
Babbling receive error
Write BABR = 1
Source Description
Flag Clearing Mechanism
36
PIT0
PIF
PIT Interrupt Flag
Write PIF = 1 or write PMR
37
PIT1
PIF
PIT Interrupt Flag
Write PIF = 1 or write PMR
38
PIT2
PIF
PIT Interrupt Flag
Write PIF = 1 or write PMR
39
PIT3
PIF
PIT Interrupt Flag
Write PIF = 1 or write PMR
40
RNG
EI
RNG interrupt flag
Write RNGCR[CI] = 1
41
SKHA
INT
SKHA interrupt flag
Write SKCMR[CI] = 1
42
MDHA
MI
MDHA interrupt flag
Write MDCMR[CI] = 1
43
USB
USB
USB Interrupt
writing a ’1’ to the appropriate bit in USB_INTR
44
EP0
Endpoint 0
writing a ’1’ to the appropriate bit in USB_EP0_INTR
45
EP1
Endpoint 1
writing a ’1’ to the appropriate bit in USB_EP1_INTR
46
EP2
Endpoint 2
writing a ’1’ to the appropriate bit in USB_EP2_INTR
47
EP3
Endpoint 3
writing a ’1’ to the appropriate bit in USB_EP3_INTR
48–63
Not used
Table 13-14. Interrupt Source Assignment for INTC1
Source Module
1–22
Flag
Source Description
Flag Clearing Mechanism
Not used
MCF5275 Reference Manual, Rev. 2
13-14
Freescale Semiconductor
Memory Map/Register Definition
Table 13-14. Interrupt Source Assignment for INTC1 (Continued)
Source Module
23
FEC1
Flag
Source Description
Flag Clearing Mechanism
X_INTF
Transmit frame interrupt
Write X_INTF = 1
24
X_INTB
Transmit buffer interrupt
Write X_INTB = 1
25
UN
Transmit FIFO underrun
Write UN = 1
26
RL
Collision retry limit
Write RL = 1
27
R_INTF
Receive frame interrupt
Write R_INTF = 1
28
R_INTB
Receive buffer interrupt
Write R_INTB = 1
29
MII
MII interrupt
Write MII = 1
30
LC
Late collision
Write LC = 1
31
HBERR
Heartbeat error
Write HBERR = 1
32
GRA
Graceful stop complete
Write GRA = 1
33
EBERR
Ethernet bus error
Write EBERR = 1
34
BABT
Babbling transmit error
Write BABT = 1
35
BABR
Babbling receive error
Write BABR = 1
36–63
Not used
13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a
processor-generated interrupt acknowledge cycle during exception processing. In either case, the
interrupt controller’s actions are very similar.
First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of IACK
arrives in the interrupt controller, the controller examines all the currently-active level n interrupt
requests, determines the highest priority within the level, and then responds with the unique vector
number corresponding to that specific interrupt source. The vector number is supplied as the data
for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt
controller also loads the level and priority number for the level into the IACKLPR register, where
it may be retrieved later.
This interrupt controller design also supports the concept of a software IACK. A software IACK
is a useful concept that allows an interrupt service routine to determine if there are other pending
interrupts so that the overhead associated with interrupt exception processing (including machine
state save/restore functions) can be minimized. In general, the software IACK is performed near
the end of an interrupt service routine, and if there are additional active interrupt sources, the
current interrupt service routine (ISR) passes control to the appropriate service routine, but without
taking another interrupt exception.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
13-15
Interrupt Controller Modules
When the interrupt controller receives a software IACK read, it returns the vector number
associated with the highest level, highest priority unmasked interrupt source for that interrupt
controller. The IACKLPR register is also loaded as the software IACK is performed. If there are
no active sources, the interrupt controller returns an all-zero vector as the operand. For this
situation, the IACKLPR register is also cleared.
In addition to the software IACK registers within each interrupt controller, there are global
software IACK registers. A read from the global SWIACK will return the vector number for the
highest level and priority unmasked interrupt source from all interrupt controllers. A read from one
of the LnIACK registers will return the vector for the highest priority unmasked interrupt within
a level for all interrupt controllers.
7
6
5
R
4
3
2
1
0
0
0
0
VECTOR
W
Reset
Address
0
0
0
0
0
See Table 13-2 and Table 13-3 for register offsets
Figure 13-10. Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
Table 13-15. SWIACK and L1IACK-L7IACK Field Descriptions
13.3
Bits
Name
Description
7–0
VECTOR
Vector number. A read from the SWIACK register returns the vector number associated
with the highest level, highest priority unmasked interrupt source. A read from one of the
LnACK registers returns the highest priority unmasked interrupt source within the level.
Prioritization Between Interrupt Controllers
The interrupt controllers have a fixed priority, where INTC0 has the highest priority, and INTC1
has the lowest priority. If both interrupt controllers have active interrupts at the same level and
priority, then the INTC0 interrupt will be serviced first. If INTC1 has an active interrupt that has
a higher level or priority than the highest INTC0 interrupt, then the INTC1 interrupt will be
serviced first.
13.4
Low-Power Wakeup Operation
The System Control Module (SCM) contains an 8-bit low-power interrupt control register
(LPICR) used explicitly for controlling the low-power stop mode. This register must explicitly be
programmed by software to enter low-power mode.
Each interrupt controller provides a special combinatorial logic path to provide a special wake-up
signal to exit from the low-power stop mode. This special mode of operation works as follows:
MCF5275 Reference Manual, Rev. 2
13-16
Freescale Semiconductor
Low-Power Wakeup Operation
•
First, LPICR[XLPM_IPL] is loaded with the mask level that will be specified while the
core is in stop mode. LPICR[ENBSTOP] must be set to enable this mode of operation.
NOTE
The wakeup mask level taken from LPICR[XLPM_IPL] is adjusted
by hardware to allow a level 7 IRQ to generate a wakeup. That is, the
wakeup mask value used by the interrupt controller must be in the
range of 0–6.
•
Second, the processor executes a STOP instruction which places it in stop mode. Once the
processor is stopped, each interrupt controller enables a special logic path which evaluates
the incoming interrupt sources in a purely combinatorial path; that is, there are no clocked
storage elements. If an active interrupt request is asserted and the resulting interrupt level
is greater than the mask value contained in LPICR[XLPM_IPL], then each interrupt
controller asserts the wake-up output signal, which is routed to the SCM where it is
combined with the wakeup signals from the other interrupt controller and then to the PLL
module to re-enable the device’s clock trees and resume processing.
For more information, see Section 8.2.1.1, “Low-Power Interrupt Control Register (LPICR).”
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
13-17
Interrupt Controller Modules
MCF5275 Reference Manual, Rev. 2
13-18
Freescale Semiconductor
Chapter 14
Edge Port Module (EPORT)
14.1
Introduction
The edge port module (EPORT) has seven external interrupt pins, IRQ7–IRQ1. Each pin can be
configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising
edge, falling edge, or both), or a general-purpose input/output (I/O) pin. See Figure 14-1.
Stop
Mode
EPPAR[2n, 2n + 1]
Edge Detect
Logic
EPFRn
D0
Internal Bus
Q
D0
D1
Q
D1
To Interrupt
Controller
EPPDRn
Synchronizer
Rising Edge
of System Clock
EPIERn
IRQn PIN
EPDRn
EPDDRn
Figure 14-1. EPORT Block Diagram
14.2
Low-Power Mode Operation
This section describes the operation of the EPORT module in low-power modes. For more
information on low-power modes, see Chapter 8, “Power Management.” Table 14-1 shows
EPORT module operation in low-power modes, and describes how this module may exit from each
mode.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
14-1
Edge Port Module (EPORT)
NOTE
The low-power interrupt control register (LPICR) in the System
Control Module specifies the interrupt level at or above which is
needed to bring the device out of a low-power mode.
Table 14-1. Edge Port Module Operation in Low-power Modes
Low-power Mode
EPORT Operation
Mode Exit
Wait
Normal
Any IRQn Interrupt at or above level in LPICR
Doze
Normal
Any IRQn Interrupt at or above level in LPICR
Stop
Level-sensing Only
Any IRQn Interrupt set for level-sensing at or
above level in LPICR
In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may
be configured to exit the low-power modes by generating an interrupt request on either a selected
edge or a low level on an external pin. In stop mode, there are no clocks available to perform the
edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on
the external interrupt pin to generate an interrupt (if enabled) to exit stop mode.
NOTE
The input pin synchronizer is bypassed for the level-detect logic since
no clocks are available.
14.3
Interrupt/General-Purpose I/O Pin Descriptions
All pins default to general-purpose input pins at reset. The pin value is synchronized to the rising
edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values used in the
edge/level detect logic are also synchronized to the rising edge of CLKOUT. These pins use
Schmitt triggered input buffers which have built in hysteresis designed to decrease the probability
of generating false edge-triggered interrupts for slow rising and falling input signals.
When a pin is configured as an output, it is driven to a state whose level is determined by the
corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are high at reset.
14.4
Memory Map/Register Definition
This subsection describes the memory map and register structure. Refer to Table 14-2 for a
description of the EPORT memory map. The EPORT has an IPSBAR offset for base address of
0x0013_0000.
MCF5275 Reference Manual, Rev. 2
14-2
Freescale Semiconductor
Memory Map/Register Definition
Table 14-2. Edge Port Module Memory Map
IPSBAR
Offset
Bits 15–8
Access1
Bits 7–0
0x13_0000
EPORT Pin Assignment Register (EPPAR)
S
0x13_0002
EPORT Data Direction Register (EPDDR) EPORT Interrupt Enable Register (EPIER)
S
0x13_0004
EPORT Data Register (EPDR)
EPORT Pin Data Register (EPPDR)
S/U
0x13_0006
EPORT Flag Register (EPFR)
Reserved2
S/U
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
2
Writing to reserved address locations has no effect, and reading returns 0s.
14.4.1 Register Description
The EPORT programming model consists of these registers:
•
•
•
•
•
•
The EPORT pin assignment register (EPPAR) controls the function of each pin
individually.
The EPORT data direction register (EPDDR) controls the direction of each one of the pins
individually.
The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin
individually.
The EPORT data register (EPDR) holds the data to be driven to the pins.
The EPORT pin data register (EPPDR) reflects the current state of the pins.
The EPORT flag register (EPFR) individually latches EPORT edge events.
14.4.1.1 EPORT Pin Assignment Register (EPPAR)
15
R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EPPA7
EPPA6
EPPA5
EPPA4
EPPA3
EPPA2
EPPA1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
Address
0
0
0
0
0
0
IPSBAR + 0x13_0000
Figure 14-2. EPORT Pin Assignment Register (EPPAR)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
14-3
Edge Port Module (EPORT)
Table 14-3. EPPAR Field Descriptions
Bits
Name
Description
15–2
EPPAn
EPORT pin assignment select fields. The read/write EPPAn fields configure EPORT pins
for level detection and rising and/or falling edge detection.
Pins configured as level-sensitive are inverted so that a logic 0 on the external pin
represents a valid interrupt request. Level-sensitive interrupt inputs are not latched. To
guarantee that a level-sensitive interrupt request is acknowledged, the interrupt source
must keep the signal asserted until acknowledged by software. Level sensitivity must be
selected to bring the device out of stop mode with an IRQn interrupt.
Pins configured as edge-triggered are latched and need not remain asserted for interrupt
generation. A pin configured for edge detection can trigger an interrupt regardless of its
configuration as input or output.
Interrupt requests generated in the EPORT module can be masked by the interrupt
controller module. EPPAR functionality is independent of the selected pin direction.
Reset clears the EPPAn fields.
00 Pin IRQn level-sensitive
01 Pin IRQn rising edge triggered
10 Pin IRQn falling edge triggered
11 Pin IRQn both falling edge and rising edge triggered
1–0
—
Reserved, should be cleared.
14.4.1.2 EPORT Data Direction Register (EPDDR)
15
R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EPDD7
EPDD6
EPDD5
EPDD4
EPDD3
EPDD2
EPDD1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
Address
0
0
0
0
0
0
IPSBAR + 0x13_0002
Figure 14-3. EPORT Data Direction Register (EPDDR)
Table 14-4. EPDD Field Descriptions
Bits
Name
Description
7–1
EPDDn
Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any
bit in EPDDR configures the corresponding pin as an input. Pin direction is independent of
the level/edge detection configuration. Reset clears EPDD7–EPDD1.
To use an EPORT pin as an external interrupt request source, its corresponding bit in
EPDDR must be clear. Software can generate interrupt requests by programming the
EPORT data register when the EPDDR selects output.
0 Corresponding EPORT pin configured as input
1 Corresponding EPORT pin configured as output
0
—
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
14-4
Freescale Semiconductor
Memory Map/Register Definition
14.4.1.3 Edge Port Interrupt Enable Register (EPIER)
7
R EPIE7
6
5
4
3
2
1
0
EPIE6
EPIE5
EPIE4
EPIE3
EPIE2
EPIE1
0
0
0
0
0
0
0
0
W
Reset
0
Address
IPSBAR + 0x13_0003
Figure 14-4. EPORT Port Interrupt Enable Register (EPIER)
Table 14-5. EPIER Field Descriptions
Bits
Name
Description
7–1
EPIEn
Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set,
EPORT generates an interrupt request when:
• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set.
• The corresponding pin level is low and the pin is configured for level-sensitive operation.
Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin.
Reset clears EPIE7–EPIE1.
0 Interrupt requests from corresponding EPORT pin disabled
1 Interrupt requests from corresponding EPORT pin enabled
0
—
Reserved, should be cleared.
14.4.1.4 Edge Port Data Register (EPDR)
7
R EPD7
6
5
4
3
2
1
0
EPD6
EPD5
EPD4
EPD3
EPD2
EPD1
0
1
1
1
1
1
1
1
W
Reset
Address
1
IPSBAR + 0x13_0004
Figure 14-5. EPORT Port Data Register (EPDR)
Table 14-6. EPDR Field Descriptions
Bits
Name
Description
7–1
EPDn
Edge port data bits. Data written to EPDR is stored in an internal register; if any pin of the
port is configured as an output, the bit stored for that pin is driven onto the pin. Reading
EDPR returns the data stored in the register. Reset sets EPD7–EPD1.
0
—
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
14-5
Edge Port Module (EPORT)
14.4.1.5 Edge Port Pin Data Register (EPPDR)
7
6
5
4
3
2
1
R EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1
0
0
W
Reset
Current pin state
Address
0
IPSBAR + 0x13_0005
Figure 14-6. EPORT Port Pin Data Register (EPPDR)
Table 14-7. EPPDR Field Descriptions
Bits
Name
Description
7–1
EPPDn
Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins
IRQ7–IRQ1. Writing to EPPDR has no effect, and the write cycle terminates normally.
Reset does not affect EPPDR.
0
—
Reserved, should be cleared.
14.4.1.6 Edge Port Flag Register (EPFR)
7
R EPF7
6
5
4
3
2
1
0
EPF6
EPF5
EPF4
EPF3
EPF2
EPF1
0
0
0
0
0
0
0
0
W
Reset
Address
0
IPSBAR + 0x13_0006
Figure 14-7. EPORT Port Flag Register (EPFR)
Table 14-8. EPFR Field Descriptions
Bits
Name
Description
7–1
EPFn
Edge port flag bits. When an EPORT pin is configured for edge triggering, its
corresponding read/write bit in EPFR indicates that the selected edge has been detected.
Reset clears EPF7–EPF1.
Bits in this register are set when the selected edge is detected on the corresponding pin.
A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect. If a pin is
configured as level-sensitive (EPPARn = 00), pin transitions do not affect this register.
0 Selected edge for IRQn pin has not been detected.
1 Selected edge for IRQn pin has been detected.
0
—
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
14-6
Freescale Semiconductor
Chapter 15
Chip Select Module
15.1 Introduction
This chapter describes the chip select module, including the operation and programming model of
the chip select registers, which include the chip select address, mask, and control registers.
NOTE
Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT
used for the bus (fsys/2).
15.1.1 Overview
The following list summarizes the key chip select features:
•
•
•
•
Eight independent, user-programmable chip select signals (CS[7:0]) that can interface with
external SRAM, PROM, EPROM, EEPROM, Flash, and peripherals
Address masking for 64-Kbyte to 4-Gbyte memory block sizes
Enhanced secondary wait states
Access error on writes to write-protect (WP) region
15.2 External Signal Description
This section describes the signals used by the chip select module.
15.2.1 Chip Selects (CS[7:0])
Each CSn can be independently programmed for an address location as well as for masking, port
size, read/write burst capability, wait-state generation, and internal/external termination. Only CS0
is initialized at reset and may act as an external boot chip select to allow boot ROM to be at an
external address space. Port size for CS0 is configured by the logic levels of D[20:19] when
RSTOUT negates and RCON is asserted.
15.2.2 Output Enable (OE)
Interfaces to memory or to peripheral devices and enables a read transfer. It is asserted and negated
on the falling edge of the clock. OE is asserted only when one of the chip selects matches for the
current address decode.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
15-1
Chip Select Module
15.2.3 Byte Strobes (BS[3:2])
These signals are individually programmed through the byte-enable mode bit, CSCRn[BEM],
described in Section 15.4.1.3, “Chip Select Control Registers (CSCR0–CSCR7).”
These generated signals provide byte data select signals, which are decoded from the transfer size,
A1, and A0 signals in addition to the programmed port size and burstability of the memory
accessed, as shown below.
The below table also shows the interaction of the byte-enable/byte-write enables with related
signals.
Table 15-1. Byte Enables/Byte Write Enable Signal Settings
BS3
BS2
D[31:24]
D[23:16]
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
0
1
0
1
1
0
1
0
0
1
Transfer Size
Port Size
A1
A0
Byte
8-bit
0
16-bit
Word
8-bit
16-bit
Longword
8-bit
16-bit
Line
8-bit
16-bit
1
1
1
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
0
0
1
0
0
0
MCF5275 Reference Manual, Rev. 2
15-2
Freescale Semiconductor
Chip Select Operation
15.3 Chip Select Operation
Each chip select has a dedicated set of registers for configuration and control.
•
•
•
Chip select address registers (CSARn) control the base address of the chip select. See
Section 15.4.1.1.
Chip select mask registers (CSMRn) provide 16-bit address masking and access control.
See Section 15.4.1.2.
Chip select control registers (CSCRn) provide port size and burst capability indication,
wait-state generation, and automatic acknowledge generation features. See
Section 15.4.1.3.
CS0 is a global chip select after reset and provides relocatable boot ROM capability.
15.3.1 General Chip Select Operation
When a bus cycle is initiated, the MCF5275 first compares its address with the base address and
mask configurations programmed for chip selects 0–7 (configured in CSCR0–CSCR7) and
DRAM blocks 0 and 1 (configured in DACR0 and DACR1). If the driven address matches a
programmed chip select or DRAM block, the appropriate chip select is asserted or the DRAM
block is selected using the specifications programmed in the respective configuration register.
Otherwise, the following occurs:
•
•
•
If the address and attributes do not match in CSAR or DACR, the MCF5275 runs an
external burst-inhibited bus cycle with a default of external termination on a 16-bit port.
Should an address and attribute match in multiple CSCRs, the matching chip select signals
are driven; however, the chip select signals are driven during an external burst-inhibited bus
cycle with external termination on a 16-bit port.
If the address and attribute match both DACRs or a DACR and a CSAR, the operation is
undefined.
Table 15-2 shows the type of access as a function of match in the CSARs and DACRs.
Table 15-2. Accesses by Matches in CSARs and DACRs
Number of CSCR Matches
Number of DACR Matches
Type of Access
0
0
External
1
0
Defined by CSAR
Multiple
0
External, burst-inhibited, 16-bit
0
1
Defined by DACRs
1
1
Undefined
Multiple
1
Undefined
0
Multiple
Undefined
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
15-3
Chip Select Module
Table 15-2. Accesses by Matches in CSARs and DACRs (Continued)
Number of CSCR Matches
Number of DACR Matches
Type of Access
1
Multiple
Undefined
Multiple
Multiple
Undefined
15.3.1.1 8- and 16-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 15.4.1.3 for
more information. Figure 15-1 shows the correspondence between the data bus and the external
byte strobe control lines (BS[3:2]). Note that all byte lanes are driven, although the state of unused
byte lanes is undefined.
BS3
External
data bus
16-bit port
memory
8-bit port
memory
BS2
D[31:24]
D[23:16]
Byte 0
Byte 2
Byte 1
Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
Driven,
undefined
Figure 15-1. Connections for External Memory Port Sizes
15.3.2 Enhanced Wait State Operation
The chip-select logic has been enhanced to add the notion of secondary wait-state counter values
to be used after the initial wait-state value (where the existing wait state field becomes the initial
access wait state) is applied to the first access. Two fields in the Chip-Select Control Registers
(CSCRn) are defined as the secondary read wait state (SRWS) value and the secondary write wait
state (SWWS) value. The application of the secondary wait state values is only enabled when the
auto-acknowledge feature is enabled, i.e., CSCRn[AA] = 1.
High-performance memory devices typically require a x-y-y-y response where x is the initial
wait-state value and y is the secondary wait-state value. For non-SDRAM memory devices likely
to be connected to a MCF5275 device, memory response times of {5-9}-{1-2}-{1-2}-{1-2} are
typical. This function is supported with the secondary wait state counters.
MCF5275 Reference Manual, Rev. 2
15-4
Freescale Semiconductor
Chip Select Operation
S0 S1 S2 S3
WS
S4 S5
WS
S6 S7
WS
S8 S9
WS
S10 S11
CLKOUT
A[23:0]
R/W, TIP
TSIZ[1:0]
TS
CSn, OE, BSn
D[31:0]
Write
Write
Write
Write
TA
Figure 15-2. Secondary Wait State Writes
S0 S1 S2 S3
WS
S4 S5
WS
S6 S7
WS
S8 S9
WS
S10 S11
CLKOUT
A[23:0]
R/W, TIP
TSIZ[1:0]
TS
CSn, OE, BSn
D[31:0]
Write
Write
Write
Write
TA
Figure 15-3. Secondary Wait State Reads
Each CSCR, shown in Figure 15-6, controls the auto-acknowledge, port size, burst capability, and
activation of each chip select.
15.3.2.1 External Boot Chip Select Operation
CS0, the external boot chip select, allows address decoding for boot ROM before system
initialization. Its operation differs from other external chip select outputs after system reset.
After system reset, CS0 is asserted for every external access. No other chip select can be used until
the valid bit, CSMR0[V], is set, at which point CS0 functions as configured and CS[7:1] can be
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
15-5
Chip Select Module
used. At reset, the port size function of the external boot chip select is determined by the logic
levels of the inputs on D[20:19]. Table 15-3 and Table 15-3 list the various reset encodings for the
configuration signals multiplexed with D[20:19].
Table 15-3. D[20:19] External Boot Chip Select Configuration
D[20:19]
Boot Device/Data Port Size
00
01
External (16-bit)
10
External (8-bit)
11
Provided the required address range is in the chip select address register (CSAR0), CS0 can be
programmed to continue decoding for a range of addresses after the CSMR0[V] is set, after which
the external boot chip select can be restored only by a system reset.
15.4 Memory Map/Register Definition
Table 15-4 shows the chip select register memory map. Reading reserved locations returns zeros.
Table 15-4. Chip Select Registers
IPSBAR
Offset
0x00_0080
0x00_0084
[31:24]
[23:16]
[15:8]
[7:0]
Reserved1
Chip select address register—bank 0 (CSAR0)
Chip select mask register—bank 0 (CSMR0)
0x00_0088
Reserved1
Chip select control register—bank 0 (CSCR0)
0x00_008C
Chip select address register—bank 1 (CSAR1)
Reserved1
0x00_0090
Chip select mask register—bank 1 (CSMR1)
0x00_0094
Reserved1
Chip select control register—bank 1 (CSCR1)
0x00_0098
Chip select address register—bank 2 (CSAR2)
Reserved1
0x00_009C
Chip select mask register—bank 2 (CSMR2)
0x00_00A0
Reserved1
Chip select control register—bank 2 (CSCR2)
0x00_00A4
Chip select address register—bank 3 (CSAR3)
Reserved1
0x00_00A8
Chip select mask register—bank 3 (CSMR3)
0x00_00A
C
Reserved1
Chip select control register—bank 3 (CSCR3)
0x00_00B0
Chip select address register—bank 4 (CSAR4)
Reserved1
0x00_00B4
0x00_00B8
Chip select mask register—bank 4 (CSMR4)
Reserved1
Chip select control register—bank 4 (CSCR4)
MCF5275 Reference Manual, Rev. 2
15-6
Freescale Semiconductor
Memory Map/Register Definition
Table 15-4. Chip Select Registers (Continued)
IPSBAR
Offset
[31:24]
0x00_00B
C
[23:16]
[15:8]
Reserved1
Chip select address register—bank 5 (CSAR5)
0x00_00C0
[7:0]
Chip select mask register—bank 5 (CSMR5)
0x00_00C4
Reserved1
Chip select control register—bank 5 (CSCR5)
0x00_00C8
Chip select address register—bank 6 (CSAR6)
Reserved1
0x00_00C
C
Chip select mask register—bank 6 (CSMR6)
0x00_00D0
Reserved1
Chip select control register—bank 6 (CSCR6)
0x00_00D4
Chip-select address register—bank 7 (CSAR7)
Reserved1
0x00_00D8
Chip-select mask register—bank 7 (CSMR7)
Reserved1
0x00_00D
C
1
Chip-select control register—bank 7 (CSCR7)
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these
reserved address spaces and reserved register bits have no effect.
15.4.1 Chip Select Module Registers
The chip select module is programmed through the chip select address registers
(CSAR0–CSAR7), chip select mask registers (CSMR0–CSMR7), and the chip select control
registers (CSCR0–CSCR7).
15.4.1.1 Chip Select Address Registers (CSAR0–CSAR7)
The CSARs, Figure 15-4, specify the chip select base addresses.
15
14
13
12
11
10
9
8
R
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
BA
W
Reset
—
—
Address
—
—
—
—
—
—
IPSBAR + 0x00_0080 (CSAR0); IPSBAR + 0x00_008C (CSAR1);
IPSBAR + 0x00_0098 (CSAR2); IPSBAR + 0x00_00A4 (CSAR3);
IPSBAR + 0x00_00B0 (CSAR4); IPSBAR + 0x00_00BC (CSAR5);
IPSBAR + 0x00_00C8 (CSAR6); IPSBAR + 0x00_00D4 (CSAR7)
Figure 15-4. Chip Select Address Registers (CSARn)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
15-7
Chip Select Module
Table 15-5. CSARn Field Description
Bits
Name
Description
15–0
BA
Base address. Defines the base address for memory dedicated to chip select CS[7:0]. BA
is compared to bits 31–16 on the internal address bus to determine if chip select memory
is being accessed.
15.4.1.2 Chip Select Mask Registers (CSMR0–CSMR7)
The CSMRs, Figure 15-5, are used to specify the address masks for the respective chip selects.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
BAM
W
Reset
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
WP
0
0
0
0
0
0
0
V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
W
Reset
Address
IPSBAR + 0x00_0084 (CSMR0); IPSBAR + 0x00_0090 (CSMR1);
IPSBAR + 0x00_009C (CSMR2); IPSBAR + 0x00_00A8 (CSMR3);
IPSBAR + 0x00_00B4 (CSMR4); IPSBAR + 0x00_00C0 (CSMR5);
IPSBAR + 0x00_00CC (CSMR6); IPSBAR + 0x00_00D8 (CSMR7)
Figure 15-5. Chip Select Mask Registers (CSMRn)
Table 15-6. CSMRn Field Descriptions
Bits
Name
Description
31–16
BAM
Base address mask. Defines the chip select block by masking address bits. Setting a BAM
bit causes the corresponding CSAR bit to be ignored in the decode.
0 Corresponding address bit is used in chip select decode.
1 Corresponding address bit is a don’t care in chip select decode.
The block size for CS[7:0] is 2n where n = (number of bits set in respective
CSMR[BAM]) + 16. For example, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0001, CS0
addresses a 128-Kbyte (217 byte) range from 0x0000–0x1_FFFF. Likewise, for CS0 to
access 32 Mbytes (225 bytes) of address space starting at location 0x0000, and for CS1 to
access 16 Mbytes (224 bytes) of address space starting after the CS0 space, then
CSAR0 = 0x0000, CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and
CSMR1[BAM] = 0x00FF.
8
WP
Write protect. Controls write accesses to the address range in the corresponding CSAR.
Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the
appropriate chip select not being selected and an access error exception will occur.
0 Both read and write accesses are allowed.
1 Only read accesses are allowed.
MCF5275 Reference Manual, Rev. 2
15-8
Freescale Semiconductor
Memory Map/Register Definition
Table 15-6. CSMRn Field Descriptions (Continued)
Bits
Name
Description
7–1
—
Reserved, should be cleared.
0
V
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are
valid. Programmed chip selects do not assert until V is set (except for CS0, which acts as
the global chip select). Reset clears each CSMRn[V].
0 Chip select invalid
1 Chip select valid
15.4.1.3 Chip Select Control Registers (CSCR0–CSCR7)
Each CSCR, shown in Figure 15-6, controls the auto-acknowledge, port size, burst capability, and
activation of each chip select. Note that to support the external boot chip select, CS0, the CSCR0
reset values differ from the other CSCRs. CS0 allows address decoding for boot ROM before
system initialization.
15
R
14
13
12
SRWS
11
10
IWS
9
8
0
AA
7
6
PS
5
4
3
2
BEM BSTR BSTW
1
0
SWWS
W
Reset: CSCR0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
Reset: Other
CSCRs
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Address
IPSBAR + 0x00_008A (CSCR0); IPSBAR + 0x00_0096 (CSCR1);
IPSBAR + 0x00_00A2 (CSCR2); IPSBAR + 0x00_00AE (CSCR3);
IPSBAR + 0x00_00BA (CSCR4); IPSBAR + 0x00_00C6 (CSCR5);
IPSBAR + 0x00_00D2 (CSCR6); IPSBAR + 0x00_00DE (CSCR7)
Figure 15-6. Chip Select Control Registers (CSCRn)
Table 15-7. CSCRn Field Descriptions
Bits
Name
Description
15–14
SRWS
Secondary Read Wait States. The number of wait states applied to all reads after the initial
one if properly enabled (SRSW is non-zero and CSCR[AA] = 1). The default value of this
field is secondary read wait states disabled. See Section 15.3.2, “Enhanced Wait State
Operation,” for timing diagrams.
00 Secondary read wait states are disabled. Use CSCR[IWS] for all accesses.
01 0 wait states for the secondary read accesses
10 1 wait state for the secondary read accesses
11 2 wait states for the secondary read accesses
13–10
IWS
Initial Wait States. The number of wait states inserted before an internal transfer
acknowledge is generated (WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait
states). If AA = 0, TA must be asserted by the external system regardless of the number of
wait states generated. In that case, the external transfer acknowledge ends the cycle. An
external TA supercedes the generation of an internal TA.
9
—
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
15-9
Chip Select Module
Table 15-7. CSCRn Field Descriptions (Continued)
Bits
Name
Description
8
AA
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge
for accesses specified by the chip select address.
0 No internal TA is asserted. Cycle is terminated externally.
1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn
and the external system asserts an external TA before the wait-state countdown asserts
the internal TA, the cycle is terminated. Burst cycles increment the address bus between
each internal termination.
7–6
PS
Port size. Specifies the width of the data associated with each chip select. It determines
where data is driven during write cycles and where data is sampled during read cycles. See
Section 15.3.1.1.
00 Reserved
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
5
BEM
Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables
that must be asserted during reads as well as writes. BEM can be set in the relevant CSCR
to provide the appropriate mode of byte enable in support of these SRAMs.
0 BS is not asserted for read. BS is asserted for data write only.
1 BS is asserted for read and write accesses.
4
BSTR
Burst read enable. Specifies whether burst reads are used for memory associated with
each CSn.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst
reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads
from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8- and 16-bit
ports.
3
BSTW
Burst write enable. Specifies whether burst writes are used for memory associated with
each CSn.
0 Break data larger than the specified port size into individual port-sized, non-burst writes.
For example, a longword write to an 8-bit port takes four byte writes.
1 Enables burst write of data larger than the specified port size, including longword writes
to 8 and 16-bit ports, word writes to 8-bit ports and line writes to 8- and 16-bit ports.
2–0
SWWS
Secondary write wait states. The number of wait states applied to all writes after the initial
one if properly enabled (SWWS is non-zero and CSCR[AA] = 1). The default for this field is
secondary write wait states disabled. See Section 15.3.2, “Enhanced Wait State
Operation,” for timing diagrams. This field is encoded as:
000
001
010
011
100
101
110
111
Secondary write wait states are disabled. Use CSCR[IWS] for all accesses.
0 wait states for the secondary write accesses
1 wait state for the secondary write accesses
2 wait states for the secondary write accesses
3 wait states for the secondary write accesses
4 wait states for the secondary write accesses
5 wait states for the secondary write accesses
6 wait states for the secondary write accesses
MCF5275 Reference Manual, Rev. 2
15-10
Freescale Semiconductor
Code Example
15.5 Code Example
CSAR0 EQU IPSBARx+0x080 ;Chip select 0 address register
CSMR0 EQU IPSBARx+0x084 ;Chip select 0 mask register
CSCR0 EQU IPSBARx+0x08A ;Chip select 0 control register
CSAR1 EQU IPSBARx+0x08C ;Chip select 1 address register
CSMR1 EQU IPSBARx+0x090 ;Chip select 1 mask register
CSCR1 EQU IPSBARx+0x096 ;Chip select 1 control register
CSAR2 EQU IPSBARx+0x098 ;Chip select 2 address register
CSMR2 EQU IPSBARx+0x09C ;Chip select 2 mask register
CSCR2 EQU IPSBARx+0x0A2 ;Chip select 2 control register
CSAR3 EQU IPSBARx+0x0A4 ;Chip select 3 address register
CSMR3 EQU IPSBARx+0x0A8 ;Chip select 3 mask register
CSCR3 EQU IPSBARx+0x0AE ;Chip select 3 control register
CSAR4 EQU IPSBARx+0x0B0 ;Chip select 4 address register
CSAR4 EQU IPSBARx+0x0B4 ;Chip select 4 mask register
CSMR4 EQU IPSBARx+0x0BA ;Chip select 4 control register
CSAR5 EQU IPSBARx+0x0BC ;Chip select 5 address register
CSMR5 EQU IPSBARx+0x0C0 ;Chip select 5 mask register
CSCR5 EQU IPSBARx+0x0C6 ;Chip select 5 control register
CSAR6 EQU IPSBARx+0x0C8 ;Chip select 6 address register
CSMR6 EQU IPSBARx+0x0CC ;Chip select 6 mask register
CSCR6 EQU IPSBARx+0x0D2 ;Chip select 6 control register
CSAR7 EQU IPSBARx+0x0D4 ;Chip select 7 address register
CSMR7 EQU IPSBARx+0x0D8 ;Chip select 7 mask register
CSCR7 EQU IPSBARx+0x0DE ;Chip select 7 control register
; All other chip selects should be programmed and made valid before global
; chip select is de-activated by validating CS0
; Program Chip Select 3 Registers
move.w #0x0040,D0
;CSAR3 base address 0x00400000
move.w D0,CSAR3
move.w
move.w
#0x00A0,D0
D0,CSCR3
;CSCR3 = no wait states, AA=0, PS=16-bit, BEM=1,
;BSTR=0, BSTW=0
move.l #0x001F0101,D0;Address range from 0x00400000 to 0x005FFFFF
move.l D0,CSMR3
;WP,V=1; SC,UC=0
; Program Chip Select 2 Registers
move.w
move.w
#0x0020,D0
D0,CSAR2
;CSAR2 base address 0x00200000 (to 0x003FFFFF)
move.w
move.w
#0x0538,D0
D0,CSCR2
;CSCR2 = 1 wait state, AA=1, PS=32-bit, BEM=1,
;BSTR=1, BSTW=1
move.l
move.l
#0x001F0001,D0
D0,CSMR2
;Address range from 0x00200000 to 0x003FFFFF
;W=0; V=1
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
15-11
Chip Select Module
; Program Chip Select 1 Registers
move.w
move.w
#0x0000,D0
D0,CSAR1
;CSAR1 base addresses 0x00000000 (to 0x001FFFFF)
;and 0x80000000 (to 0x801FFFFF)
move.w
move.w
#0x09B0,D0
D0,CSCR1
;CSCR1 = 2 wait states, AA=1, PS=16-bit, BEM=1,
;BSTR=1, BSTW=0
move.l
move.l
#0x801F0001,D0
D0,CSMR1
;Address range from 0x00000000 to 0x001FFFFF and
;0x80000000 to 0x801FFFFF
;WP=0, V=1
; Program Chip Select 0 Registers
move.w
move.w
#0x0080,D0
D0,CSAR0
;CSAR0 base address 0x00800000 (to 0x009FFFFF)
move.w
move.w
#0x0D80,D0
D0,CSCR0
;CSCR0 = three wait states, AA=1, PS=16-bit, BEM=0,
;BSTR=0, BSTW=0
; Program Chip Select 0 Mask Register (validate chip selects)
move.l
move.l
#0x001F0001,D0
D0,CSMR0
;Address range from 0x00800000 to 0x009FFFFF
;WP=0; V=1
MCF5275 Reference Manual, Rev. 2
15-12
Freescale Semiconductor
Chapter 16
External Interface Module (EIM)
16.1 Introduction
This chapter describes data-transfer operations, error conditions, and reset operations. Chapter 17,
“SDRAM Controller (SDRAMC),” describes DRAM cycles.
NOTE
Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT
used for the bus (fsys/2).
NOTE
The timing diagrams within this chapter show 32 address lines,
A[31:0]. However, only the lowest 24 address signals are available
externally on the MCF5275 device, A[23:0].
16.1.1 Features
The following list summarizes bus operation features:
•
•
•
•
•
•
Up to 24 bits of address and 16 bits of data
Access 8- and 16--bit data port sizes
Generates byte, word, longword, and line-size transfers
Burst and burst-inhibited transfer support
Optional internal termination for external bus cycles
Enhanced secondary wait state
16.2 Bus and Control Signals
Table 16-1 summarizes MCF5275 bus signals described in Chapter 2, “Signal Descriptions.”
Table 16-1. ColdFire Bus Signal Summary
Signal Name
A[23:0]
Description
I/O
CLKOUT Edge
Address bus
O
Rising
1
Byte selects
O
Falling
CS[7:0] 1
Chip selects
O
Falling
D[31:16]
Data bus
I/O
Rising
Output enable
O
Falling
BS[3:2]
OE
1
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
16-1
External Interface Module (EIM)
Table 16-1. ColdFire Bus Signal Summary (Continued)
Signal Name
R/W
I/O
CLKOUT Edge
Read/write
O
Rising
Transfer size
O
Rising
TA
Transfer acknowledge
I
Rising
TIP
Transfer in progress
O
Rising
TS
Transfer start
O
Rising
TSIZ[1:0]
1
Description
These signals change after the falling edge. In the Electrical Specifications, these signals are
specified off of the rising edge because CLKIN is squared up internally.
Table 16-2 explains the transfer size encoding of the TSIZ[1:0] signals.
Table 16-2. Transfer Size Encoding
TSIZ[1:0]
Transfer Size
00
Longword
01
Byte
10
Word
11
16-byte line
16.3 Bus Characteristics
The MCF5275 uses its internal bus clock to generate CLKOUT (see Chapter 7, “Clock Module”).
Therefore, the external bus operates at the same speed as the bus clock rate of fsys/2, where all bus
operations are synchronous to the rising edge of CLKOUT, and some of the bus control signals
(BS, OE, and CSn) are synchronous to the falling edge, shown in Figure 16-1. Bus characteristics
may differ somewhat for interfacing with external DRAM.
MCF5275 Reference Manual, Rev. 2
16-2
Freescale Semiconductor
Bus Errors
CLKOUT
tho
tvo
Rising-Edge
Signals
tvo
tho
Falling-Edge
Signals
tsi
thi
Inputs
tvo=Propagation delay of signal relative to CLKOUT edge
tho=Output hold time relative to CLKOUT edge
tsi =Required input setup time relative to CLKOUT edge
thi=Required input hold time relative to CLKOUT edge
Figure 16-1. Signal Relationship to CLKOUT for Non-DRAM Access
16.4 Bus Errors
Attempting to write to a range of addresses that is write protected (CSARn[WP] = 1) will not
assert the corresponding chip select. Also, an access error exception will occur. See
Section 15.4.1.2, “Chip Select Mask Registers (CSMR0–CSMR7)” and Section 3.7, “Processor
Exceptions” for more details.
16.5 Data Transfer Operation
Data transfers between the MCF5275 and other devices involve the following signals:
•
•
•
•
•
Address bus (A[23:0])
Data bus (D[31:16])
Control signals (TS and TA)
CSn, OE, BSn
Attribute signals (R/W, TSIZ, and TIP)
The address bus, write data, TS, and all attribute signals change on the rising edge of CLKOUT.
Read data is latched into the MCF5275 on the rising edge of CLKOUT.
The MCF5275 bus supports byte, word, and longword operand transfers and allows accesses to 8and 16-bit data ports. Aspects of the transfer, such as the port size, the number of wait states for
the external slave being accessed, and whether internal transfer termination is enabled, can be
programmed in the chip-select control registers (CSCRs) and the SDRAM base address registers
(SDBARs).
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
16-3
External Interface Module (EIM)
Figure 16-2 shows the byte lanes that external memory should be connected to and the sequential
transfers if a longword is transferred for two port sizes. For example, an 8-bit memory should be
connected to D[31:24] (BS3). A longword transfer takes four transfers on D[31:24], starting with
the MSB and going to the LSB.
Byte Enable
BS3
BS2
Processor
External
Data Bus
D[31:24]
D[23:16]
16-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Byte 3
8-Bit Port
Memory
Byte 0
Byte 1
Byte 2
Driven with
indeterminate
values
Byte 3
Figure 16-2. Connections for External Memory Port Sizes
The timing relationship of chip selects (CS[7:0]), byte selects (BS[3:2]), and output enable (OE)
with respect to CLKOUT is similar in that all transitions occur during the low phase of CLKOUT.
However, due to differences in on-chip signal routing, signals may not assert simultaneously.
CLKOUT
CS[7:0]
BS[3:2]
OE
Figure 16-3. Chip-Select Module Output Timing Diagram
16.5.1 Bus Cycle Execution
When a bus cycle is initiated, the MCF5275 first compares the address of that bus cycle with the
base address and mask configurations programmed for chip selects 0–7 (configured in
CSCR0–CSCR7) and DRAM block 0 and 1 address and control registers (configured in DACR0
and DACR1). If the driven address compares with one of the programmed chip selects or DRAM
blocks, the appropriate chip select is asserted or the DRAM block is selected using the
specifications programmed by the user in the respective configuration register. Otherwise, the
following occurs:
•
•
If the address and attributes do not match in CSCR or DACR, the MCF5275 runs an
external burst-inhibited bus cycle with a default of external termination on a 16-bit port.
Should an address and attribute match in multiple CSCRs, the matching chip-select signals
are driven; however, the MCF5275 runs an external burst-inhibited bus cycle with external
termination on a 16-bit port.
MCF5275 Reference Manual, Rev. 2
16-4
Freescale Semiconductor
Data Transfer Operation
•
Should an address and attribute match both DACRs or a DACR and a CSCR, the operation
is undefined.
Table 16-3 shows the type of access as a function of match in the CSCRs and DACRs.
Table 16-3. Accesses by Matches in CSCRs and DACRs
Number of CSCR Matches
Number of DACR Matches
Type of Access
0
0
External
1
0
Defined by CSCR
Multiple
0
External, burst-inhibited, 16-bit
0
1
Defined by DACRs
1
1
Undefined
Multiple
1
Undefined
0
Multiple
Undefined
1
Multiple
Undefined
Multiple
Multiple
Undefined
Basic operation of the MCF5275 bus is a three-clock bus cycle.
1. During the first clock, the address, attributes, and TS are driven.
2. Data and TA are sampled during the second clock of a bus-read cycle. During a read, the
external device provides data and is sampled at the rising edge at the end of the second bus
clock. This data is concurrent with TA, which is also sampled at the rising edge of the
clock.
During a write, the ColdFire device drives data from the rising clock edge at the end of the
first clock to the rising clock edge at the end of the bus cycle. Wait states can be added
between the first and second clocks by delaying the assertion of TA. TA can be configured
to be generated internally through the CSCRs. If TA is not generated internally, the system
must provide it externally.
3. The last clock of the bus cycle uses what would be an idle clock between cycles to provide
hold time for address, attributes and write data. Figure 16-6 and Figure 16-8 show the
basic read and write operations.
16.5.2 Data Transfer Cycle States
The data transfer operation in the MCF5275 is controlled by an on-chip state machine. Each bus
clock cycle is divided into two states. Even states occur when CLKOUT is high and odd states
occur when CLKOUT is low. The state transition diagram for basic and fast termination read and
write cycles are shown in Figure 16-4.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
16-5
External Interface Module (EIM)
Next Cycle
S0
S5
S1
Basic
Read/Write
S4
Fast
Termination
S2
Wait
States
S3
Figure 16-4. Data Transfer State Transition Diagram
Table 16-4 describes the states as they appear in subsequent timing diagrams.
Table 16-4. Bus Cycle States
State
Cycle
CLKOUT
Description
S0
All
High
The read or write cycle is initiated in S0. On the rising edge of CLKOUT, the
MCF5275 places a valid address on the address bus and drives R/W high for a
read and low for a write, if it is not already in the appropriate state. The MCF5275
asserts TIP, TSIZ[1:0], and TS on the rising edge of CLKOUT.
S1
All
Low
The appropriate CSn, BSn, and OE signals assert on the CLKOUT falling edge.
S2
S3
Fast
Termination
TA must be asserted during S1. Data is made available by the external device and
is sampled on the rising edge of CLKOUT with TA asserted.
Read/write
High
(skipped fast
termination)
TS is negated on the rising edge of CLKOUT in S2.
Write
The data bus is driven out of high impedance as data is placed on the bus on the
rising edge of CLKOUT.
Read/write
(skipped for
fast
termination)
Low
Read
S4
All
Read
(including
fast-terminati
on)
The MCF5275 waits for TA assertion. If TA is not sampled as asserted before the
rising edge of CLKOUT at the end of the first clock cycle, the MCF5275 inserts wait
states (full clock cycles) until TA is sampled as asserted.
Data is made available by the external device on the falling edge of CLKOUT and
is sampled on the rising edge of CLKOUT with TA asserted.
High
The external device should negate TA.
The external device can stop driving data after the rising edge of CLKOUT.
However data could be driven through the end of S5.
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16-6
Freescale Semiconductor
Data Transfer Operation
Table 16-4. Bus Cycle States (Continued)
State
S5
Cycle
S5
CLKOUT
Low
Description
CSn, BSn, and OE are negated on the CLKOUT falling edge of S5. The MCF5275
stops driving address lines and R/W on the rising edge of CLKOUT, terminating the
read or write cycle. At the same time, the MCF5275 negates TIP, and TSIZ[1:0] on
the rising edge of CLKOUT.
Note that the rising edge of CLKOUT may be the start of S0 for the next access
cycle.
Read
The external device stops driving data between S4 and S5.
Write
The data bus returns to high impedance on the rising edge of CLKOUT. The rising
edge of CLKOUT may be the start of S0 for the next access.
NOTE
An external device has at most two CLKOUT cycles after the start of
S4 to tristate the data bus. This applies to basic read cycles, fast
termination cycles, and the last transfer of a burst.
16.5.3 Read Cycle
During a read cycle, the MCF5275 receives data from memory or from a peripheral device.
Figure 16-5 is a read cycle flowchart.
System
MCF5275
1.
Set R/W to read
2.
Place address on A[31:0]
3.
Assert TIP, and TSIZ[1:0]
4.
Assert TS
5.
Negate TS
1.
1.
1.
Sample TA low and latch data
Start next cycle
Decode address and select the
appropriate slave device.
2.
Drive data on D[31:16]
3.
Assert TA
1.
Negate TA.
2.
Stop driving D[31:16]
Figure 16-5. Read Cycle Flowchart
The read cycle timing diagram is shown in Figure 16-6.
NOTE
In the following timing diagrams, TA waveforms apply for chip
selects programmed to enable either internal or external termination.
TA assertion should look the same in either case.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
16-7
External Interface Module (EIM)
S0
S1
S2
S3
S4
S5
CLKOUT
R/W
A[31:0], TSIZ[1:0]
TIP
TS
CSn, BSn, OE
D[31:16]
Read
TA
Figure 16-6. Basic Read Bus Cycle
Note the following characteristics of a basic read:
•
•
•
In S3, data is made available by the external device on the falling edge of CLKOUT and is
sampled on the rising edge of CLKOUT with TA asserted.
In S4, the external device can stop driving data after the rising edge of CLKOUT. However
data could be driven up to S5.
For a read cycle, the external device stops driving data between S4 and S5.
States are described in Table 16-4.
16.5.4 Write Cycle
During a write cycle, the MCF5275 sends data to the memory or to a peripheral device. The write
cycle flowchart is shown in Figure 16-7.
MCF5275 Reference Manual, Rev. 2
16-8
Freescale Semiconductor
Data Transfer Operation
System
MCF5275
1.
Set R/W to write
2.
Place address on A[31:0]
3.
Assert TIP and TSIZ[1:0]
4.
Assert TS
5.
Place data on D[31:16]
6.
Negate TS
1.
Sample TA low
2.
Stop driving data from D[31:16]
1.
Start next cycle
1.
Decode address
2.
Store data on D[31:16]
3.
Assert TA
1.
Negate TA
Figure 16-7. Write Cycle Flowchart
The write cycle timing diagram is shown in Figure 16-8.
S0
S1
S2
S3
S4
S5
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn
D[31:16]
Write
TA
Figure 16-8. Basic Write Bus Cycle
Table 16-4 describes the six states of a basic write cycle.
16.5.5 Fast Termination Cycles
Two clock cycle transfers are supported on the MCF5275 bus. In most cases, this is impractical to
use in a system because the termination must take place in the same half-clock during which TS
is asserted. As this is atypical, it is not referred to as the zero-wait-state case but is called the
fast-termination case. Fast termination cycles occur when the external device or memory asserts
TA less than one clock after TS is asserted. This means that the MCF5275 samples TA on the rising
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
16-9
External Interface Module (EIM)
edge of the second cycle of the bus transfer. Figure 16-9 shows a read cycle with fast termination.
Note that fast termination cannot be used with internal termination.
S0
S1
S4
S5
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn, OE
D[31:16]
Read
TA
Figure 16-9. Read Cycle with Fast Termination
Figure 16-10 shows a write cycle with fast termination.
S0
S1
S4
S5
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn
D[31:16]
Write
TA
Figure 16-10. Write Cycle with Fast Termination
16.5.6 Back-to-Back Bus Cycles
The MCF5275 runs back-to-back bus cycles whenever possible. For example, when a longword
read is started on a word-size bus, the processor performs two back-to-back word read accesses.
Back-to-back accesses are distinguished by the continuous assertion of TIP throughout the cycle.
Figure 16-11 shows a read back-to-back with a write.
MCF5275 Reference Manual, Rev. 2
16-10
Freescale Semiconductor
Data Transfer Operation
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn
OE
D[31:16]
Read
Write
TA
Figure 16-11. Back-to-Back Bus Cycles
Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to
the type of operations to be placed back to back. The initiation of a back-to-back cycle is not user
definable.
16.5.7 Burst Cycles
The MCF5275 can be programmed to initiate burst cycles if its transfer size exceeds the size of
the port it is transferring to. For example, a word transfer to an 8-bit port would take a 2-byte burst
cycle. A line transfer to a 16-bit port would take a 8-word burst cycle.
The MCF5275 bus can support 2-1-1-1 burst cycles to maximize cache performance and optimize
DMA transfers. A user can add wait states by delaying termination of the cycle. The initiation of
a burst cycle is encoded on the size pins. For burst transfers to smaller port sizes, TSIZ[1:0]
indicates the size of the entire transfer. For example, if the MCF5275 writes a longword to an 8-bit
port, TSIZ[1:0] = 00 for the first byte transfer and does not change.
The CSCRs can be used to enable bursting for reads, writes, or both. MCF5275 memory space can
be declared burst-inhibited for reads and writes by clearing the appropriate
CSCRn[BSTR,BSTW]. A line access to a burst-inhibited region first accesses the MCF5275 bus
encoded as a line access. The TSIZ[1:0] encoding does not exceed the programmed port size. The
address changes if internal termination is used but does not change if external termination is used,
as shown in Figure 16-12 and Figure 16-13.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
16-11
External Interface Module (EIM)
16.5.7.1 Line Transfers
A line is a 16-byte-aligned, 16-byte value. Despite the alignment, a line access may not begin on
the aligned address; therefore, the bus interface supports line transfers on multiple address
boundaries. Table 16-5 shows allowable patterns for line accesses.
Table 16-5. Allowable Line Access Patterns
A[3:2]
Word Accesses
00
0–2–4–6–8–A–C
01
4–6–8–A–C–E–0
10
8–A–C–E–0–2–4
11
C–E–0–2–4–6–8
16.5.7.2 Line Read Bus Cycles
Figure 16-12 and Figure 16-13 show a line access read with zero wait states. The access starts like
a basic read bus cycle with the first data transfer sampled on the rising edge of S4, but the next
pipelined burst data is sampled a cycle later on the rising edge of S6. Each subsequent pipelined
data burst is single cycle until the last one, which can be held for up to two CLKOUT cycles after
TA is asserted. Note that CSn is asserted throughout the burst transfer. This example shows the
timing for external termination, which differs from the internal termination example in
Figure 16-13 only in that the address lines change only at the beginning (assertion of TS and TIP)
and end (negation of TIP) of the transfer.
S0
S1 S2
S3
S4 S5
S6
S7
S8
S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn, OE
D[31:16]
Read
Read
Read
Read
Read
Read
Read
Read
TA
Figure 16-12. Line Read Burst (2-1-1-1-1-1-1-1), External Termination
Figure 16-13 shows timing when internal termination is used.
MCF5275 Reference Manual, Rev. 2
16-12
Freescale Semiconductor
Data Transfer Operation
S0
S1 S2
S3
S4 S5
S6
S7
S8
S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20
CLKOUT
A[31:0]
TSIZ[1:0]
R/W
TIP
TS
CSn, BSn, OE
D[31:16]
Read
Read
Read
Read
Read
Read
Read
Read
TA
Figure 16-13. Line Read Burst (2-1-1-1-1-1-1-1), Internal Termination
Figure 16-14 shows a line access read with one wait state programmed in CSCRn to give the
peripheral or memory more time to return read data. This figure follows the same execution as a
zero-wait state read burst with the exception of an added wait state.
.
S0
S1
S2
S3
WS
S4
S5
WS
S6
S7
S16 S17
WS
S18 S19 S20
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn, OE
D[31:16]
Read1
Read2
Read7
Read8
TA
Figure 16-14. Line Read Burst (3-2-2-2-2-2-2-2), External Termination
Figure 16-15 shows a burst-inhibited line read access with fast termination. The external device
executes a basic read cycle while determining that a line is being transferred. The external device
uses fast termination for subsequent transfers.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
16-13
External Interface Module (EIM)
S0
S1
S2
S3
S4
S5 S0
S1
S4
S5 S0
S1
S1
S4
S5 S0
S1
S4
S5
CLKOUT
A[31:0]
A[3:1] = 000
A[3:1] = 001
A[3:1] = 110
A[3:1] = 111
R/W
TIP
TSIZ[1:0]
Line
Word=10
TS
CSn, BSn, OE
D[31:16]
Read1
Read2
Read
Read7
Read8
TA
Basic
Fast
Fast
Fast
Fast
Figure 16-15. Line Read Burst-Inhibited, Fast Termination, External Termination
16.5.7.3 Line Write Bus Cycles
Figure 16-16 shows a line access write with zero wait states. It begins like a basic write bus cycle
with data driven one clock after TS. The next pipelined burst data is driven a cycle after the write
data is registered (on the rising edge of S6). Each subsequent burst takes a single cycle. Note that
as with the line read example in Figure 16-12, CSn remain asserted throughout the burst transfer.
This example shows the behavior of the address lines for both internal and external termination.
Note that when external termination is used, the address lines change with TSIZ[1:0].
MCF5275 Reference Manual, Rev. 2
16-14
Freescale Semiconductor
Data Transfer Operation
S0
S1 S2
S3
S4 S5
S6
S7
S8
S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20
CLKOUT
A[31:0]
Internal Termination
A[31:0]
External Termination
TSIZ[1:0]
R/W, TIP
TS
CSn, BSn, OE
D[31:16]
Write
Write
Write
Write
Write
Write
Write
Write
TA
Figure 16-16. Line Write Burst (2-1-1-1-1-1-1-1), Internal/External Termination
Figure 16-17 shows a line burst write with one wait-state insertion.
S0 S1 S2 S3
WS
S4 S5
WS
S6 S7
WS
S8 S9
WS
S10 S11
CLKOUT
A[31:0]
R/W, TIP
TSIZ[1:0]
TS
CSn, OE, BSn
D[31:]
Write
Write
Write
Write
TA
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
16-15
External Interface Module (EIM)
S0
S1
S2
WS
S3
S4
S5
WS
S6
S7
S16 S17
WS
S18 S19 S20
CLKOUT
A[31:0]
R/W, TIP
TSIZ[1:0]
TS
CSn, BSn, OE
D[31:16]
Write #1
Write #2
Write #7
Write #8
TA
Figure 16-17. Line Write Burst (3-2-2-2-2-2-2-2) with One Wait State
Figure 16-18 shows a burst-inhibited line write. The external device executes a basic write cycle
while determining that a line is being transferred. The external device uses fast termination to end
each subsequent transfer.
S0
S1
S2 S3 S4 S5 S0 S1 S4 S5
S0 S1 S4 S5
S0 S1 S4 S5
A[3:2] = 10
A[3:2] = 11
CLKOUT
A[31:0]
A[3:2] = 00
A[3:2] = 01
R/W, TIP
TSIZ[1:0]
Line
Longword
TS
CSn
OE, BSn
D[31:]
Write
Write
Write
Write
TA
Basic
Fast
Fast
Fast
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16-16
Freescale Semiconductor
Secondary Wait State Operation
S0
S1
S2
S3
S4
S5 S0
S1
S4
S5 S0
S1
S1
S4
S5 S0
S1
S4
S5
CLKOUT
A[31:0]
A[3:1] = 000
A[3:1] = 001
A[3:1] = 110
A[3:1] = 111
Write #7
Write #8
R/W, TIP
TSIZ[1:0]
Line
Word = 10
TS
CSn, BSn, OE
D[31:16]
Write #1
Write #2
TA
Basic
Fast
Fast
Fast
Fast
Figure 16-18. Line Write Burst-Inhibited
16.6 Secondary Wait State Operation
Refer to Section 15.3.2, “Enhanced Wait State Operation,” for information and timing diagrams
of the secondary wait state operation.
16.7 Misaligned Operands
Because operands can reside at any byte boundary, unlike opcodes, they are allowed to be
misaligned. A byte operand is properly aligned at any address, a word operand is misaligned at an
odd address, and a longword is misaligned at an address not a multiple of four. Although the
MCF5275 enforces no alignment restrictions for data operands (including program counter (PC)
relative data addressing), additional bus cycles are required for misaligned operands.
Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to
prefetch a misaligned instruction word causes an address error exception.
The MCF5275 converts misaligned, cache-inhibited operand accesses to multiple aligned
accesses. Figure 16-19 shows the transfer of a longword operand from a byte address to a 32-bit
port. In this example, TSIZ[1:0] specify a byte transfer and a byte offset of 0x1. The slave device
supplies the byte and acknowledges the data transfer. When the MCF5275 starts the second cycle,
TSIZ[1:0] specify a word transfer with a byte offset of 0x2. The next two bytes are transferred in
this cycle. In the third cycle, byte 3 is transferred. The byte offset is now 0x0, the port supplies the
final byte, and the operation is complete.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
16-17
External Interface Module (EIM)
31
24 23
16 15
87
0
A[2:0]
Transfer 1
—
Byte 0
—
—
001
Transfer 2
—
—
Byte 1
Byte 2
010
Transfer 3
Byte 3
—
—
—
100
Figure 16-19. Example of a Misaligned Longword Transfer (32-Bit Port)
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded
into the cache. The example in Figure 16-20 differs from that in Figure 16-19 in that the operand
is word-sized and the transfer takes only two bus cycles.
31
24 23
16 15
87
0
A[2:0]
Transfer 1
—
—
—
Byte 0
001
Transfer 2
Byte 1
—
—
—
100
Figure 16-20. Example of a Misaligned Word Transfer (32-Bit Port)
MCF5275 Reference Manual, Rev. 2
16-18
Freescale Semiconductor
Chapter 17
SDRAM Controller (SDRAMC)
17.1
Introduction
This chapter describes configuration and operation of the synchronous DRAM (SDRAM)
controller. It begins with a general overview and includes a description of signals involved in
SDRAM operations. The remainder of the chapter describes the programming model and signal
timing, as well as the command set required for synchronous DRAM operations. It also includes
examples that the designer can follow to better understand how to configure the SDRAM
controller for synchronous operations.
17.1.1 Features
The MCF5275 SDRAM controller contains the following features:
•
•
•
•
•
•
•
•
•
•
Supports a glueless interface to DDR SDRAMs
16-bit fixed memory port width
32-bit internal data bus interface to Coldfire core
16 bytes (8 beat x 16-bit) critical word first burst transfer
Up to 14 row address lines, up to 12 column address lines, maximum of two chip selects.
The maximum row bits plus column bits is 24.
Supported SDRAM devices include: 32, 64, 128, 256, 512Mbit, and 1Gbit per chip select
Minimum memory configuration of 8 Mbyte—12 bit row address (RA), 8 bit column
address (CA), 2 bit bank address (BA) and one chip select
Supports page mode to maximize the data rate
Supports sleep mode and self-refresh mode
Error detect and parity check are not supported
17.1.2 Terminology
The following terminology is used in this chapter:
•
SDRAM block: Any group of DRAM memories selected by one of the MCF5275
SD_CS[1:0] signals. Thus, the MCF5275 can support up to two independent memory
blocks. The base address of each block is programmed in the SDRAM base address and
mask registers.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-1
SDRAM Controller (SDRAMC)
•
•
•
SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit
SDRAM component might be configured as four 512K x 32 banks. Banks are selected
through the BS[3:2] signals.
SDRAM: These are RAMs that operate like asynchronous DRAMs but with a synchronous
clock, a pipelined, multiple-bank architecture, and a faster speed.
Double data rate (DDR) SDRAM: This is SDRAM that latches command information on
the rising edge of the clock, but data is driven/latched on both the rising and falling edges
of the clock rather than on just the rising edge. This doubles data throughput rate without
an increase in frequency.
17.1.3 Block Diagram
Below is the SDRAM memory controller block diagram. It illustrates how the module is
connected to the internal device, as well as the external interface signals.
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Freescale Semiconductor
Data
Generation/
Packing
DATA[31:0]
D[31:16]
SD_DQS[3:2]
Address
Multiplexing
ADDR[31:0]
A[23:0]
Chip Select 0
Hit Logic
SD_SRAS
SD_SCAS
State Machine
SD_WE
and
Control Logic
SD_CS[1:0]
SD_CKE
BS[3:2]
Chip Select 1
External Memory Interface
Internal Interface
Introduction
Internal Interface
Hit Logic
ADDR[4:2]
Register File
Clock
Generator
DATA[31:0]
DDR_CLKOUT
DDR_CLKOUT
Figure 17-1. SDRAM Controller Block Diagram
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-3
SDRAM Controller (SDRAMC)
17.2
External Signal Description
Table 17-1. SDRAM Controller Signals
Signal Name
Abbreviation
Function
I/O
Data Bus
D[31:16]
These three-state bidirectional signals provide the general purpose
data path between the processor and all other devices.Data is
sampled by the MCF5275 on both the rising and falling edge of
DDR_CLKOUT
I/O
Bank Selects
A[15:14]
For SDRAM accesses A[15:14] are always used to provide bank
select signals to the SDRAM. A[15:14] should be connected to
BA[1:0] on the SDRAM device.
O
Address Bus
A[13:11,9:0]
A portion of the 24-bit uni-directional address bus is used for
multiplexed row and column addresses during SDRAM bus cycles.
The address multiplexing supports up to 128 Mbytes of SDRAM per
chip select.
O
SDRAM A10
SD_A10
SDRAM address bit 10 or command.
O
SDRAM Synchronous
Row Address Strobe
SD_SRAS
SDRAM synchronous row address strobe.
O
SDRAM Synchronous SD_SCAS
Column Address Strobe
SDRAM synchronous column address strobe.
O
SDRAM Chip Selects
SD_CS[1:0]
These signals interface to the chip select lines of the SDRAMs within
a memory block.
O
Byte Strobes
BS[3:2]
For SDRAM devices, these signals indicate transfers between
SDRAM and the device when driven high. The BS[3:2] should be
connected to individual SDRAM DM signals. Note that most SDRAMs
associate DM1 with the MSB, in which case BS3 should be connected
to the SDRAM's DM1 input.
O
SDRAM Data Strobes
SD_DQS[3:2]
SDRAM byte-lane read/write data strobe signals.
I/O
SDRAM Clock Out
DDR_CLKOUT This output signal reflects the internal system clock.
O
SDRAM Inverted
Clock Out
DDR_CLKOUT This output signal reflects the inverted internal system clock. used
along with DDR_CLKOUT to provide differential clocks for DDR
SDRAMs.
O
SDRAM Write Enable
SD_WE
Asserted to signify that a DRAM write cycle is underway. A read cycle
is indicated by the deassertion of SD_WE
O
SDRAM Clock Enable
SD_CKE
Deasserts to put the SDRAM into low-power, self-refresh mode.
O
17.3
Interface Recommendations
17.3.1 Supported Memory Configurations
The SDRAM controller supports up to 14 row addresses and up to 12 column addresses. However,
the maximum row and column addresses are not supported at the same time. The number of row
and column addresses must be less than or equal to 24. In addition to row/column address lines,
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
Interface Recommendations
there are always two row bank address bits. Therefore, the greatest possible address space which
can be accessed using a single chip select is (226) x 16 bit, or 128 Mbytes.
Table 17-2 shows the address multiplexing used by the MCF5275 for different configurations.
When the SDRAM controller receives the internal module enable, it latches the internal bus
address lines addr[26:1] and multiplexes them into row, column and row bank addresses. addr[8:1]
are always used for CA[7:0], addr[10:9] are always used for BA[1:0], and addr[22:11] are always
used for RA[11:0]. addr[26:23] can be used for additional row or column address bits, as needed.
NOTE
The SDRAMC only supports an external 16-bit data bus. It is not
possible to connect a smaller device(s) to only part of the SDRAM’s
data bus. For example, if 8-bit wide devices are used, then you must
use two 8-bit devices connected as a 16-bit port.
Table 17-2. SDRAM Address Multiplexing
Device
Size
Configur
ation
Row bit x Number Total
Col bit x of Chips Block
Banks
Used
Size
32 Mbit
4M x 8bit
12 x 8 x 2
2
4M x 16 bit
12 x 8 x 2
64 Mbits
8M x 8bit
16M x 4bit
8M x 16 bit
SDCR
[MUX]
Setting
26
25
24
23
8 MB
00
—
—
—
—
1
8 MB
00
—
—
—
—
2
16 MB
00
—
—
—
CA8
01
—
—
—
RA12
4
32 MB
00
—
—
CA9
CA8
01
—
—
CA8
RA12
1
16 MB
00
—
—
—
CA8
01
—
—
—
RA12
00
—
—
CA9
CA8
01
—
—
CA8
RA12
10
—
—
RA13
RA12
00
—
CA11
CA9
CA8
01
—
CA9
CA8
RA12
00
—
—
CA9
CA8
01
—
—
CA8
RA12
14 x 8 x 2
10
—
—
RA13
RA12
12 x 11 x 2
00
—
CA11
CA9
CA8
01
—
CA9
CA8
RA12
10
—
CA8
RA13
RA12
00
CA12
CA11
CA9
CA8
01
CA11
CA9
CA8
RA12
12 x 9 x 2
13 x 8 x 2
12 x 10 x 4
13 x 9 x 4
12 x 9 x 2
13 x 8 x 2
12 x 10 x 2
128 Mbits
16M x 8 bit
13 x 9 x 2
2
32 MB
14 x 8 x 2
32M x 4 bit
12 x 11 x 4
13 x 10 x 4
4
64 MB
12 x 10 x 2
16M x 16 bit
256 Mbits
32M x 8 bit
13 x 9 x 2
13 x 10 x 2
1
2
32 MB
64 MB
14 x 9 x 2
64M x 4 bit
12 x 12 x 4
13 x 11 x 4
4
128 MB
Internal Address
22-11
10-9
8-1
RA11-0 BA1-0
CA7-0
RA11-0 BA1-0
CA7-0
RA11-0 BA1-0
CA7-0
RA11-0 BA1-0
CA7-0
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-5
SDRAM Controller (SDRAMC)
Table 17-2. SDRAM Address Multiplexing
Device
Size
Configur
ation
Row bit x Number Total
Col bit x of Chips Block
Banks
Used
Size
SDCR
[MUX]
Setting
26
25
24
23
00
—
CA11
CA9
CA8
01
—
CA9
CA8
RA12
14 x 9 x 2
10
—
CA8
RA13
RA12
12 x 12 x 2
00
CA12
CA11
CA9
CA8
01
CA11
CA9
CA8
RA12
14 x 10 x 2
10
CA9
CA8
RA13
RA12
12 x 12 x 2
00
CA12
CA11
CA9
CA8
01
CA11
CA9
CA8
RA12
10
CA9
CA8
RA13
RA12
12 x 11 x 2
32M x 16 bit
512 Mbits
64M x 8bit
1 Gbit
64M x 16 bit
13 x 10x 2
13 x 11 x 2
13 x 11 x 2
14 x 10 x 2
1
2
1
64 MB
128 MB
128 MB
Internal Address
22-11
10-9
8-1
RA11-0 BA1-0
CA7-0
RA11-0 BA1-0
CA7-0
All memory devices of a single chip select block must have the same configuration and
row/column address width; however, this is not necessary between different blocks. If mixing
different memory organizations in different blocks, the following guidelines will ensure that every
block is fully contiguous.
•
•
•
•
•
If all devices’ row address width is 12 bits, the column address can be ≥ 8 bits.
If all devices’ row address width is 13 bits, the column address can be ≥ 8 bits.
If all devices’ column address width is 8 bits, the row address can be ≥ 11 bits.
x8 width memory devices can be mixed (but not in the same space).
x16 data width memory devices cannot be mixed with any other width.
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
Interface Recommendations
17.3.2 SDRAM Connection Block Diagram
Figure 17-2 shows a block diagram of the connections between the MCF5275 and DDR SDRAM
components.
Figure 17-2. MCF5275 Connections to DDR SDRAM
DDR SDRAM
MCF5275
A[13:11, 9:0]
SDA10
A[15:14]
D[15:0]
A[13:11,9:0]
A10
BA[1:0]
DQ[15:0]
SDCSn
CS
RAS
CAS
SDWE
RAS
CAS
WE
DDR_CLKOUT
DDR_CLKOUT
SD_CKE
CLK
CLK
CKE
BS[3:2]
SD_DQS[3:2]
DM[1:0]
DQS[1:0]
17.3.3 DDR SDRAM Layout Considerations
Due to the critical timing for DDR SDRAM there are a number of considerations that should be
taken into account during PCB layout:
•
•
•
•
•
•
•
•
•
Minimize overall trace lengths.
Each SD_DQS, BS, and DQ group must have identical loading and similar routing to
maintain timing integrity.
Control and clock signals are routed point-to-point.
Trace length for clock, address, and command signals should match.
Route DDR signals on layers adjacent to the ground plane
Use a VREF plane under the SDRAM.
VREF is decoupled from both SDVDD and VSS.
To avoid crosstalk keep address and command signals separate from data and data strobes.
Use different resistor packs for command/address and data/data strobes.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-7
SDRAM Controller (SDRAMC)
•
•
•
•
Use single series, single parallel termination (25 Ω series, 50 Ω parallel values are
recommended, but standard resistor packs with similar values can be substituted).
Series termination should be between the MCF5275 and memory, but closest to the
processor.
The parallel termination at end of the signal line (close to the SDRAM).
0.1 uF decoupling for every termination resistor pack.
17.3.3.1 Termination Example
Figure 17-3 shows the recommended termination circuitry for DDR SDRAM signals.
VREF
50 Ω
MCF5275
DDR SDRAM
25 Ω
Figure 17-3. MCF5275 DDR SDRAM Termination Circuit
17.4
SDRAM Overview
17.4.1 SDRAM Commands
When an internal bus master accesses SDRAM address space, the memory controller generates the
corresponding SDRAM command. Table 17-3 lists SDRAM commands supported by the memory
controller.
Table 17-3. SDRAM Commands
Function
Symbol
CKE
CS
RAS
CAS
WE
BA[1:0]
A10
Other A
Command Inhibit
INH
H
H
X
X
X
X
X
X
Read
READ
H
L
H
L
H
V
L
V
Write
WRITE
H
L
H
L
L
V
L
V
Activate
ACTV
H
L
L
H
H
V
V
V
Precharge All Banks
PALL
H
L
L
H
L
X
H
X
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
SDRAM Overview
Table 17-3. SDRAM Commands (Continued)
Function
Symbol
CKE
CS
RAS
CAS
WE
BA[1:0]
A10
Other A
Load Mode Register
LMR
H
L
L
L
L
LL
V
V
Load Extended Mode Register
LEMR
H
L
L
L
L
LH
V
V
CBR Auto Refresh
REF
H
L
L
L
H
X
X
X
Self Refresh
SREF
H→L
L
L
L
H
X
X
X
Power Down
PDWN
H→L
H
X
X
X
X
X
X
H = High
L = Low
V = Valid
X = Don’t care
Many commands require a delay before the next command may be issued; sometimes the delay
depends on the type of the next command. These delay requirements are managed by the values
programmed in the memory controller configuration registers (SDCFG1, SDCFG2).
17.4.1.1 Activate Command (ACTV)
The ACTV command is responsible for latching the row and bank address and activating the
specified row in the memory array. Once the row is activated it can be accessed using subsequent
READ and WRITE commands.
NOTE
The SDRAMC will support one active row for each chip select block.
See Section 17.6.1, “Page Management” for more information.
17.4.1.2 Read Command (READ)
When the SDRAMC receives a read request, it first checks the row and bank of the new access. If
the address falls within the active row of an active bank, it is a page hit, and the READ is issued
as soon as possible (pending any delays required by previous commands). If the address is within
the active row, but the needed bank is inactive, or if there is no active row, the memory controller
will issue an ACTV followed by the READ command. If the address is not within the active row,
the memory controller will issue a PALL command to close the active row. Then the SDRAMC
issues ACTV to activate the necessary bank and row for the new access, followed finally by the
READ to the SDRAM.
The PALL and ACTV commands (if necessary) can sometimes be issued in parallel with an
on-going data movement.
All reads, whether burst or single, must be allowed to complete the entire burst length on the
memory bus. With DDR memory, the data masks are asserted throughout the entire read burst
length; but DDR memory ignores the data masks during reads.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-9
SDRAM Controller (SDRAMC)
17.4.1.3 Write Command (WRITE)
When the memory controller receives a write request, it first checks the row and bank of the new
access. If the address falls within the active row of an active bank, it is a page hit, and the WRITE
is issued as soon as possible (pending any delays required by previous commands). If the address
is within the active row but the needed bank is inactive, or if there is no active row, the memory
controller will issue an ACTV followed by the WRITE command. If the address is not within the
active row, the memory controller will issue a PALL command to close the active row. Then the
SDRAMC issues ACTV to activate the necessary row and bank for the new access, followed
finally by the WRITE command.
The PALL and ACTV commands (if necessary) can sometimes be issued in parallel with an
on-going data movement.
With DDR memory, a read command can be issued overlapping the masked beats at the end of a
previous single write
17.4.1.4 Precharge All Banks Command (PALL)
The precharge command puts SDRAM into an idle state. The SDRAM must be in this idle state
before a REF, LMR, LEMR, or ACTV command to open a new row within a particular bank can
be issued.
The memory controller issues the PALL command only when necessary for one of the following
conditions:
•
•
•
Access to a new row
Refresh interval elapsed
Software commanded precharge
NOTE
The SDRAMC does not support the precharge selected bank memory
command.
17.4.1.5 Load Mode/Extended Mode Register Command (LMR, LEMR)
All SDRAM devices contain mode registers that are used to configure the timing and burst mode
for the SDRAM. These commands are used to access the mode registers that physically reside
within the SDRAM devices. During the LMR or LEMR command the SDRAM will latch the
address bus and load the value into the selected mode register.
NOTE
The LMR and LEMR commands are only used during SDRAM
initialization.
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Freescale Semiconductor
SDRAM Overview
The following steps should be used to write the mode register and extended mode register:
1. Set the SDCR[MODE_EN] bit.
2. Write the SDMR[BA] bits to select the mode register.
3. Write the desired mode register value to the SDMR[ADDR]. Don’t overwrite the
SDMR[BA] values.
4. Set the SDMR[CMD] bit.
5. Perform a dummy read/write access to an address within an SDRAM block.
6. Repeat step 2 for the extended mode register.
7. Clear the SDCR[MODE_EN] bit.
17.4.1.5.1 Mode Register Definition
Figure 17-4 shows the mode register definition. Note that this is the SDRAM’s mode register not
the SDRAMC’s mode/extended mode register (SDMR) defined in Section 17.5.1, “SDRAM
Mode/Extended Mode Register (SDMR).”
Field
BA1
BA0
0
0
A11
A10
A9
A8
A7
A6
A5
A4
CASL
OP_MODE
A3
BT
A2
A1
A0
BLEN
Figure 17-4. Mode Register
Table 17-4. Mode Register Field Descriptions
Address
Line
Description
BA[1:0]
Bank Address. These must both be zero to select the mode register.
A11–A7
Operating Mode.
00000 Normal Operation
00010 Reset DLL
Other values should not be used.
A6–A4
CAS latency. Delay in clocks from issuing a READ to valid data out. Check the SDRAM
manufacturer’s spec as the CASL settings supported can vary from memory to memory.
A3
A2–A0
Burst Type.
0 Sequential
1 Interleaved. This setting should not be used since the SDRAMC does not support interleaved
bursts.
Burst length. Determines the number of locations that are accessed for a single READ or WRITE.
111 8 (This is the only valid setting for the MCF5275.)
All other values reserved.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-11
SDRAM Controller (SDRAMC)
17.4.1.5.2 Extended Mode Register Definition
Figure 17-5 shows the extended mode register used by DDR SDRAMs. Note that this is the
SDRAM’s extended mode register not the SDRAMC’s mode/extended mode register (SDMR)
defined in Section 17.5.1, “SDRAM Mode/Extended Mode Register (SDMR).”
Field
BA1
BA0
0
1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DLL
OPTION
Figure 17-5. Extended Mode Register
Table 17-5. Extended Mode Register Field Descriptions
Address
Line
Description
BA[1:0]
Bank Address.
00 Does not select the extended mode register
01 Selects the extended mode register
1x Reserved
A11–A1
Option. These bits are not defined by the DDR specification. Each DDR SDRAM manufacturer can
use these bits to implement optional features. Check with SDRAM manufacturer to determine if any
optional features have been implemented. For normal operation all bits should be cleared.
A0
Delay locked loop. Controls enabling of the delay locked loop circuitry used for DDR timing.
0 Enabled
1 Disabled.
17.4.1.6 Auto Refresh Command (REF)
The memory controller issues auto refresh commands according to the SDCR[RC] value. Each
time the programmed refresh interval elapses, the memory controller issues a PALL command
followed by a REF command.
If a memory access is in progress at the time the refresh interval elapses, the memory controller
schedules the refresh after the transfer is finished; but the interval timer continues counting so that
the average refresh rate is constant.
After REF, the SDRAM is in an idle state and waits for an ACTV command.
17.4.1.7 Self Refresh (SREF) and Power Down (PDWN) Commands
The memory controller issues either a PDWN or a SREF command if the SDCR[CKE] bit changes
from set to cleared. If the SDCR[REF] bit is set when CKE is cleared, the controller issues a SREF
command; if the REF bit is cleared, the controller issues a PDWN command. The REF bit may be
changed in the same register write that changes the CKE bit; the controller will act upon the new
value of the REF bit.
MCF5275 Reference Manual, Rev. 2
17-12
Freescale Semiconductor
SDRAM Overview
Just like a REF, the controller automatically issues a PALL command before the self refresh
command.
The memory is reactivated from power down or self refresh mode by setting the CKE bit.
If a normal refresh interval elapses while the memory is in self refresh mode, a PALL and REF
will be performed as soon as the memory is reactivated. If the memory is put into and brought out
of self refresh all within a single refresh interval, the next automatic refresh will occur on schedule.
In self refresh mode, the memory does not require an external clock. To restart periodic refresh
when the memory is reactivated, the REF bit must be reasserted; this can be done before the
memory is reactivated, or in the same control register write that sets CKE to exit self refresh mode.
17.4.2 Power-Up Initialization
SDRAMs have a prescribed initialization sequence. The following sections detail the memory
initialization steps for DDR SDRAM. The sequence might change slightly from device-to-device.
Refer to the device datasheet as the most relevant reference.
1. After reset is deactivated, pause for the amount of time indicated in the SDRAM
specification. Usually 100µs or 200µs.
2. Configure the pin multiplex control for the shared SD_CS pins.
3. Write the Base Address and Mask registers (SDBAR0, SDBAR1, SDMR0, and SDMR1)
to setup the address space for each chip-select
4. Program the SDRAM configuration registers (SDCFG1 and SDCFG2) with the correct
delay and timing values.
5. Issue a PALL command. Initialize the SDRAM control register (SDCR) with
SDCR[IPALL] set. The SDCR[REF and IREF] bits should remain cleared for this step.
Perform a single read/write to any of the SDRAM chip select address spaces to issue the
command.
6. Initialize the SDRAM’s extended mode register to enable the DLL. See Section 17.4.1.5,
“Load Mode/Extended Mode Register Command (LMR, LEMR)” for instructions on
issuing an LEMR command.
7. Initialize the SDRAM’s mode register and reset the DLL using the LMR command. See
Section 17.4.1.5, “Load Mode/Extended Mode Register Command (LMR, LEMR)” for
more instruciton on issuing an LMR command. During this step the OP_MODE field of
the mode register should be set to “normal operation/reset DLL.”
8. Pause for the DLL lock time specified by the memory.
9. Issue a second PALL command. Initialize the SDRAM control register (SDCR) with
SDCR[IPALL] set. The SDCR[REF and IREF] bits should remain cleared for this step.
Perform a single read/write to any of the SDRAM chip select address spaces to issue the
command.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-13
SDRAM Controller (SDRAMC)
10. Refresh the SDRAM. The SDRAM spec should indicate a number of refresh cycles to be
performed before issuing an LMR command. Write to the SDCR with the IREF bit set
(SDCR[REF and IPALL] should be cleared). This will force a refresh of the SDRAM each
time the IREF bit is set. Repeat this step until the specified number of refresh cycles have
been completed.
11. Initialize the SDRAM’s mode register using the LMR command. See Section 17.4.1.5,
“Load Mode/Extended Mode Register Command (LMR, LEMR)” for more instruction on
issuing an LMR command. During this step the OP_MODE field of the mode register
should be set to “normal operation.”
12. Set SDCR[REF] to enable automatic refreshing, and clear SDCR[MODE_EN] to lock the
SDMR. SDCR[IREF and IPALL] remain cleared.
17.5
Memory Map/Register Definition
The SDRAM controller containseightprogramming registers.
Table 17-6. SDRAMC Memory Map
IPSBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
Access
0x00_0040
SDRAM Mode/Extended Mode Register (SDMR)
R/W
0x00_0044
SDRAM Control Register (SDCR)
R/W
0x00_0048
SDRAM Configuration Register 1 (SDCFG1)
R/W
0x00_004C
SDRAM Configuration Register 2 (SDCFG2)
R/W
0x00_0050
SDRAM Base Address Register 0 (SDBAR0)
R/W
0x00_0054
SDRAM Address Mask Register 0 (SDMR0)
R/W
0x00_0058
SDRAM Base Address Register 1 (SDBAR1)
R/W
0x00_005C
SDRAM Address Mask Register 1 (SDMR1)
R/W
17.5.1 SDRAM Mode/Extended Mode Register (SDMR)
The SDMR is used to write to the mode and extended mode registers that physically reside within
in the SDRAM chips. These registers must be programmed during SDRAM initialization. See
Section 17.4.2, “Power-Up Initialization” for more information on the initialization sequence.
MCF5275 Reference Manual, Rev. 2
17-14
Freescale Semiconductor
Memory Map/Register Definition
31
R
30
29
28
27
26
25
24
BNKAD
23
22
21
20
19
18
AD
17
16
0
CMD
W
Reset
R
Uninitialized
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x00_0040
Figure 17-6. SDRAM Mode/Extended Mode Register (SDMR)
Table 17-7. SDMR Field Descriptions
Bits
Name
Description
31–30
BNKAD
Bank address. Driven onto SD_BA[1:0] along with a LMR/LEMR command. All SDRAM
chip selects are asserted simultaneously. SDCR[CKE] must be set before attempting to
generate an LMR/LEMR command. The SD_BA[1:0] value is used to select between LMR
and LEMR commands.
00 Load mode register command (LMR)
01 Load extended mode register command (LEMR)
10–11 Reserved
29–18
AD
Address. Driven onto A[11:0] along with an LMR/LEMR command. The AD value is stored
as the mode (or extended mode) register data.
17
—
Reserved. Should be cleared.
16
CMD
15–0
—
Command.
0 Do not generate any command
1 Generate an LMR/LEMR command
Reserved
17.5.2 SDRAM Control Register (SDCR)
The SDCR controls SDRAMC operating modes including the refresh count and address line
muxing.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-15
SDRAM Controller (SDRAMC)
31
30
R MODE CKE
_EN
W
Reset
28
27
26
0
REF
0
0
25
24
MUX
23
22
0
0
21
20
19
18
17
16
RCNT
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
DQS_OE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R DQS_
BP
W
Reset
29
0
0
0
Address
IREF IPAL
L
0
0
0
0
IPSBAR + 0x00_0044
Figure 17-7. SDRAM Control Register (SDCR)
Table 17-8. SDCR Field Descriptions
Bits
31
Name
Description
MODE_EN Mode enable.
0 Mode register locked, cannot be written
1 Mode register enabled, can be written
30
CKE
Clock enable.
0 SDCKE is negated (low)
1 SDCKE is asserted (high)
29
—
Reserved, should be cleared.
28
REF
Refresh enable.
0 Automatic refresh disabled
1 Automatic refresh enabled
27–26
—
Reserved, should be cleared.
25–24
MUX
Muxing control. Selects routing of the internal addr[26:23] signals as row or column address
bits as shown below and in Table 17-2.
Internal address bits
MUX
26
25
24
23
00
CA12
CA11
CA9
CA8
01
CA11
CA9
CA8
RA12
10
CA9
CA8
RA13
RA12
11
23–22
—
Reserved
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
17-16
Freescale Semiconductor
Memory Map/Register Definition
Table 17-8. SDCR Field Descriptions (Continued)
Bits
Name
Description
21–16
RCNT
Automatic Refresh Count. Controls automatic refresh frequency. The number of bus clocks
between refresh cycles is (RC + 1) x 64.
RCNT = (tREF × CLKOUT / 64) - 1, rounded down to the next integer value. Where tREF is the
desired refresh period obtained from the SDRAM device data sheet.
Example:
tREF=5us, CLKOUT=75MHz.
RCNT = floor(5 × 83 / 64) - 1 = 0x04
15
DQS_BP
DQS Clock Recovery Bypass. Bypasses circuitry for read clock recovery from DQS lines.
When bypass is enabled, read clock is generated internally rather than being recovered
from DQS pins.
0 Bypass disabled. Read clock recovered from DQS pins
1 Bypass enabled. Read clock generated internally
14–12
—
11–10
DQS_OE
9–3
—
2
IREF
Initiate Auto-Refresh (REF) command. Used to force a software initiated Auto-Refresh
command.
0 Do not generate an REF command.
1 An REF command is issued when the next single read/write transaction is performed in
the memory controller. All SD_CSn signals are asserted simultaneously. SDCR[CKE] and
SDCR[MODE_EN] must be set before attempting to generate an REF command.
1
IPALL
Initiate Precharge All (PALL) command. Used to force a software initiated PALL command.
0 Do not generate a PALL command.
1 A PALL command is issued when the next single read/write transaction is performed to
the memory controller. All SD_CSn signals are asserted simultaneously. SDCR[CKE] and
SDCR[MODE_EN] must be set before attempting to generate a PALL command.
0
—
Reserved. Should be cleared.
SD_DQS output enable.
00 Disable all SD_DQS outputs
01 Enable only SD_DQS2
10 Enable only SD_DQS3.
11 Enable both SD_DQS pins
Note: For 01 and 10 settings, some 32-bit DDR devices only have a single SD_DQS pin.
Enable one of the signals and disable the other. Then short both pins external to the device.
Reserved, should be cleared.
Reserved, should be cleared.
17.5.3 SDRAM Configuration Register 1 (SDCFG1)
The 32-bit read/write SDRAM configuration register 1 (SDCFG1) stores delay values necessary
between specific SDRAM commands. During initialization, software loads values to the register
according to the selected CLKOUT frequency and SDRAM specifications. This register is reset
only by a power-up reset signal.
The read and write latency fields govern the relative timing of commands and data, and must be
exact values. All other fields govern the relative timing from one command to another, they have
minimum values but any larger value is also legal (but with decreased performance).
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-17
SDRAM Controller (SDRAMC)
31
R
30
29
28
SRD2RW
27
26
0
25
24
23
SWT2RD
22
21
20
RDLAT
19
18
0
17
16
ACT2RW
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PRE2ACT
REF2ACT
0
WTLAT
W
Reset
0
0
Address
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0048
Figure 17-8. SDRAM Configuration Register 1 (SDCFG1)
Table 17-9. SDCFG1 Field Descriptions
Bits
Name
31–28
SRD2RW
Description
Single Read to Read/Write/Precharge delay. Limiting case is usually Write to Precharge.
SRD2RW = Burst Length / 2
Note: This formula provides the most optimum (minimum) value. A larger value is also
valid, but will reduce performance. Smaller values are reserved.
27
—
26–24
SWT2RD
Reserved, should be cleared
Single Write to Read/Write/Precharge delay. Limiting case is Write to Precharge.
SWT2RD = (tWR / tDDR_CLKOUT) + 1 (Round up to nearest integer)
Note: This formula provides the most optimum (minimum) value. A larger value is also
valid, but will reduce performance. Smaller values are reserved.
23–20
RDLAT
Read CAS Latency. Read latency. Read command to read data available delay counter.
RDLAT = 2 × (CASL + 1)
Note: Only values 0x6 and 0x7 are valid, the remaining are reserved.
19
—
18–16
ACT2RW
Reserved, should be cleared.
Active to Read/Write delay. Active command to any following read or write delay counter.
ACT2RW = (tRCD / tDDR_CLKOUT) - 1 (Round up to nearest integer)
15
14–12
—
Reserved. Should be cleared.
PRE2ACT Precharge to Active delay. Precharge command to following Active command delay
counter.
PRE2ACT = (tRP / tDDR_CLKOUT) - 1 (Round up to nearest integer)
Example: If tRP = 20ns and tDDR_CLKOUT = 1 / 83MHz
20ns × 75MHz = 1.5; round to 2; write 0x1.
11–8
REF2ACT Refresh to Active delay. Refresh command to following Active or Refresh command delay
counter.
REF2ACT = (tRFC / tDDR_CLKOUT) - 1 (Round up to nearest integer)
MCF5275 Reference Manual, Rev. 2
17-18
Freescale Semiconductor
Memory Map/Register Definition
Table 17-9. SDCFG1 Field Descriptions (Continued)
Bits
Name
7
—
6–4
WTLAT
Description
Reserved. Should be cleared.
Write CAS latency. Write command to write data delay counter.
WTLAT = tDQSS + 2
Write 0x3 for tDQSS=1. All other values are reserved.
3–0
—
Reserved. Should be cleared.
17.5.4 SDRAM Configuration Register 2 (SDCFG2)
The 32-bit read/write SDRAM configuration register 2 stores delay values necessary between
specific SDRAM commands. During initialization, software loads values to the register according
to the SDRAM information obtained from the data sheet. This register is reset only by a power-up
reset signal.
The burst length (BL) field must be exact. All other fields govern the relative timing from one
command to another, they have minimum values but any larger value is also legal (but with
decreased performance).
All delays in this register are expressed in CLKOUT.
31
R
30
29
28
27
BRD2PRE
26
25
24
23
BWT2RW
22
21
20
19
18
BRD2WT
17
16
BL
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x00_004C
Figure 17-9. SDRAM Configuration Register 2 (SDCFG2)
Table 17-10. SDCFG2 Field Descriptions
Bits
Name
Description
31–28
BRD2PRE Burst Read to Read/Precharge delay. Limiting case is Read to Read.
BRD2PRE = Burst Length / 2
Write 0x4, all other values are reserved.
27–24
BWT2RW
Burst Write to Read/Write/Precharge delay. Limiting case is Write to Precharge.
BWT2RW = (BurstLength / 2 + tWR)
Suggest value = 0x6
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-19
SDRAM Controller (SDRAMC)
Table 17-10. SDCFG2 Field Descriptions (Continued)
Bits
Name
Description
23–20
BRD2WT
19–16
BL
Burst Length.
BL = Burst Length - 1
Write 0x7, all other values are reserved.
15–0
—
Reserved. Should be cleared.
Burst Read to Write delay.
Write 0xB for best performance. All values less than 0xB are reserved.
17.5.5 SDRAM Base Address Registers (SDBAR0 & SDBAR1)
The SDRAM Base Address Registers contain the base address for the address spaces associated
with SD_CS0 (SDBAR0) and SD_CS1 (SDBAR1). The memory controller compares these values
with the current internal address value to decode hits to each CS space. If an address falls within
the address space of both chip selects, then SD_CS0 space will take precedence.
31
30
29
28
27
26
R
25
24
23
22
21
20
19
18
BASE
17
16
0
0
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x00_0050 (SDBAR0) & IPSBAR + 0x00_0058 (SDBAR1)
Figure 17-10. SDRAM Base Address Register (SDBARn)
Table 17-11. SDBARn Field Descriptions
Bits
Name
Description
31–18
BASE
The Base Address together with SDMRn[MASK] determine the address range in which the
associated CS space is located. Each base address bit is compared with the corresponding
system address of the current bus cycle. If all unmasked bits match, the address hits in the
associated CS space.
17–0
—
Reserved. Should be cleared.
17.5.6 SDRAM Address Mask Registers (SDMR0 & SDMR1)
The SDRAM Address Mask Registers mask up to 14 corresponding SDBARn[BASE] bits. The
18 lsbs of the 32bit internal address do not participate in the address matching in selecting a CS
space for access. Masking address bits independently allows external devices of different size
MCF5275 Reference Manual, Rev. 2
17-20
Freescale Semiconductor
Functional Overview
address ranges to be used. Address mask bits can be set or cleared in any order in the field allowing
a resource to reside in more than one area of the address map.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
MASK
17
16
0
0
W
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
WP
0
0
0
0
0
0
0
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x00_0054 (SDMR0); IPSBAR + 0x00_005C (SDMR1)
Figure 17-11. SDRAM Address Mask Register (SDMRn)
Table 17-12. SDMRn Field Descriptions
Bits
Name
31–18
MASK
17–9
—
8
WP
7–1
—
Reserved, should be cleared.
0
V
Chip Select Valid enables the CS space. V is cleared at reset to ensure that the CS space
is not erroneously decoded.
0 Do not decode hits to this CS space
1 Address hits to this CS space can be decoded
17.6
Description
Base Address Mask masks the associated SDBARn[BASE] bits. Lets the memory
controller occupy various address spaces. Mask bits need not be contiguous.
0 The associated address bit is used in decoding a hit to this CS space
1 The associated address bit is not used in the hit decode
Reserved, should be cleared.
Write Protect. If a write is performed to this CS space and WP is enabled, the memory
controller will assert a transfer error interrupt to the core, without executing the transfer on
the external bus.
0 Writes are allowed to this CS space
1 Writes are not allowed to this CS space
Functional Overview
17.6.1 Page Management
SDRAM devices have four internal banks. A particular row and bank of memory must be activated
to allow read and write accesses. The SDRAM controller supports paging mode to maximize the
memory access throughput. During operation, the SDRAM controller maintains an open page
address for each SD_CS block. An open page is composed of the active rows in the internal banks.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-21
SDRAM Controller (SDRAMC)
SDRAMs can have a different row address open in each bank, but the SDRAMC does not support
this. The page size of a SD_CS block is equal to the space size divided by the number of rows; but
the page may not be contiguous in the internal address space because the internal address bits used
for memory column address [11:8] and column address [7:0] are not consecutive.
Because the column address may be split across two portions of the internal address, the
contiguous page size is (number of banks) × (256 columns) × (number of bits). This gives a
contiguous page size of 4 Kbytes. However, the total (possibly fragmented) page size is (number
of banks) × (number of columns) × (number of bits).
If a new access does not fall in the open page of a SD_CS block, the open page must be closed
(PALL) and the new page must be opened (ACTV), then the READ or WRITE command can
proceed. An ACTV command only activates one bank of a page. If another read or write falls in
an inactive bank of the open page, another ACTV is needed but no precharge is needed. If a read
or write falls in any of the active banks of the open page, no PALL or ACTV is needed; the read
or write command can be issued immediately.
A page is kept open until one of the following conditions occurs:
•
•
an access outside the open page
a refresh cycle is started.
All SD_CS blocks are refreshed at the same time; the refresh closes all banks of every SDRAM
block.
17.6.2 Transfer Size
In the MCF5275, the internal data bus is 32 bits wide, while the SDRAM external interface bus is
16 bits wide. Therefore, each internal bus data beat requires two memory data beats. The SDRAM
controller manages the size translation (packing/unpacking) between 32- and 16-bit buses.
The SDRAM controller supports all possible internal bus transfer sizes. SDRAMs are “burst only”
devices; unnecessary beats on the memory bus are masked (write) or discarded (read).
The SDRAMC will perform line bursts (16 byte) for all SDRAM access. This requires eight beats
of 2 bytes (one word) on the memory bus. The SDRAM controller transfers the critical longword
first, followed by the next three sequential longwords.
The burst size and transfer order must be programmed in the SDRAM mode registers during
initialization (SDMR); the burst size also must be programmed in the memory controller
(SDCFG2).
In a write operation, the data masks/byte selects, BS[3:2], are used to inhibit writing unused bytes
of each beat. In a read operation, the excess read data is discarded.
MCF5275 Reference Manual, Rev. 2
17-22
Freescale Semiconductor
DDR SDRAM Example
17.7
DDR SDRAM Example
This example interfaces two 32M × 8-bit DDR SDRAM components to an MCF5275 operating at
a 83 MHz DDR_CLKOUT frequency with a single chip select. Figure 17-12 shows a block
diagram of the connections and Table 17-13 lists design specifications for this example.
MCF5275
BS[3:2]
BS[3]
BS[2]
SD_CS0
SD_SRAS
SD_WE
SD_SCAS
A[15:14]
{A[12:11],SDA10,A[9:0]}
SD_DQS[3:2]
DQS[3]
D[31:16]
DQS[2]
32M x 8
DDR SDRAM
32M x 8
DDR SDRAM
CAS
CS
RAS
WE
BA[1:0]
DM
CKE
CLK
ADDR[12:0]
DQS
CLK DQ[0:7]
CAS
CS
RAS
WE
BA[1:0]
DM
CKE
CLK
ADDR[12:0]
DQS
CLK DQ[0:7]
D[31:24]
D[23:16]
DDR_CLKOUT
SD_CKE
DDR_CLKOUT
Figure 17-12. MCF5275 to 64-Mbyte DDR SDRAM Connection
The devices are organized as 4 internal banks with 13 row address lines 10 column address lines
Table 17-13. SDRAM Example Specifications
Parameter
Specification
13 row and 10 column addresses
Two bank-select lines to access four internal banks
Allowable burst lengths
2, 4, or 8
CAS latency
From SDRAM data sheet
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-23
SDRAM Controller (SDRAMC)
Table 17-13. SDRAM Example Specifications (Continued)
Parameter
Specification
Clock cycle time (tCK)
From SDRAM data sheet
ACTV-to-read/write
From SDRAM data sheet
delay (tRCD)
Write recovery timer (tWR)
From SDRAM data sheet
Precharge command to ACTV command (tRP)
From SDRAM data sheet
Auto refresh command period (tRFC)
From SDRAM data sheet
Average periodic refresh interval (tREFI)
From SDRAM data sheet
17.7.1 SDRAM Chip Select Settings
For this example, the SDRAM will be connected to SD_CS0 with a base address of 0x0. All other
chip selects are unused and do not need to be initialized. The SDBAR0 should be programmed as
shown in Figure 17-13.
31
30
29
28
27
26
25
Field
24
23
22
21
20
19
18
17
BASE
Setting
16
—
0000_0000_0000_0000
(hex)
0
15
14
0
13
12
11
10
0
9
Field
8
7
6
0
5
4
3
2
1
0
—
Setting
0000_0000_0000_0000
(hex)
0
0
0
0
Figure 17-13. SDRAM Chip Select 0 Base Address Register Settings (SDBAR0)
This configuration results in a value of SDBAR0 = 0x0000_0000, as described in Table 17-14.
Table 17-14. SDBAR0 Field Descriptions
Bits
Name
Setting
Description
31–18
BASE
0
Base address is set to 0x0
17–0
—
0
Reserved. Should be cleared.
MCF5275 Reference Manual, Rev. 2
17-24
Freescale Semiconductor
DDR SDRAM Example
31
30
29
28
27
26
25
Field
24
23
22
21
20
19
18
17
MASK
Setting
16
—
0000_0011_1111_1100
(hex)
0
15
14
3
13
12
Field
11
10
F
9
—
8
7
6
C
5
WP
Setting
4
3
2
1
—
0
V
0000_0000_0000_0001
(hex)
0
0
0
1
Figure 17-14. SDRAM Chip Select 0 Mask Register Settings (SDMR0)
This configuration results in a value of SDMR0 = 0x03FC_0001, as described in Table 17-15.
Table 17-15. SDMR0 Field Descriptions
Bits
Name
Setting
Description
31–18
MASK
0x03FC
17–9
—
0
Reserved. Should be cleared.
8
WP
0
Memory space not write protected.
7–1
—
0
Reserved. Should be cleared.
0
V
1
Memory space is valid.
Address mask for a 64MB space.
17.7.2 SDRAM Configuration 1 Register Settings
The SDCFG1 register should be programmed as shown in Figure 17-15.
31
Field
30
29
28
SRD2RW
27
26
—
25
22
21
20
RDLAT
19
18
—
17
16
ACT2RW
0010_0011_0110_0001
(hex)
2
15
—
14
3
13
PRE2ACT
12
11
10
6
9
8
7
6
REF2ACT
Setting
(hex)
23
SWT2RD
Setting
Field
24
1
5
4
3
2
1
WTLAT
—
3
0
0
0001_0110_0011_0000
1
6
Figure 17-15. SDRAM Example Configuration Register 1 Settings (SDCFG1)
This configuration results in a value of SDCFG1 = 0x2361_1630, as described in Table 17-16.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-25
SDRAM Controller (SDRAMC)
Table 17-16. SDCFG1 Field Descriptions
Bits
Name
Setting
Description
31–28
SRD2RW
0010
SRD2RW = burst length/2 = 2
27
—
0
Reserved. Should be cleared.
26–24
SWT2RD
011
SWT2RD = tWR/tDDR_CLKOUT + 1 = 15ns/12ns + 1 = 1.25 + 1 = 2.25 clocks,
rounded up to 3
23–20
RDLAT
0110
0x6 is the recommended value for DDR memory with a CASL of 2
19
—
0
18–16
ACT2RW
001
15
—
0
14–12
PRE2ACT
001
PRE2ACT = tRP/tDDR_CLKOUT - 1 = 18ns/12ns - 1 = 1.5 - 1 = 0.5, rounded up to 1
11–8
REF2ACT
0110
REF2ACT = tRFC/tDDR_CLKOUT - 1 = 75ns/12ns - 1 = 6.25 - 1 = 5.25 rounded up
to 6
7
—
0
6–4
WTLAT
011
3–0
—
0
Reserved. Should be cleared.
ACT2RW = tRCD/tDDR_CLKOUT - 1 = 18ns/12ns - 1 = 1.5 - 1 = 0.5, rounded up to 1
Reserved. Should be cleared.
Reserved. Should be cleared.
0x3 is the recommended value for DDR
Reserved. Should be cleared.
17.7.3 SDRAM Configuration 2 Register Settings
The SDCFG2 register should be programmed as shown in Figure 17-16.
31
Field
30
29
28
27
BRD2PRE
26
25
24
23
BWT2RW
Setting
22
21
20
19
18
BRD2WT
17
16
1
0
BL
0010_0100_0011_0011
(hex)
2
15
14
4
13
12
11
10
3
9
Field
8
7
6
3
5
4
3
2
—
Setting
0000_0000_0000_0000
(hex)
0
0
0
0
Figure 17-16. SDRAM Example Configuration Register 2 Settings (SDCFG2)
This configuration results in a value of SDCFG2 = 0x2433_0000, as described in Table 17-17.
Table 17-17. SDCFG2 Field Descriptions
Bits
Name
Setting
Description
31–28
BRD2PRE
0010
BRD2PRE = burst length/2 = 4/2 = 2
27–24
BWT2RW
0100
BWT2RW = burst length/2 + tWR = 4/2 + 2 = 2 + 2 = 4
23–20
BRD2WT
0011
0x3 is the recommended value for DDR
MCF5275 Reference Manual, Rev. 2
17-26
Freescale Semiconductor
DDR SDRAM Example
Table 17-17. SDCFG2 Field Descriptions
Bits
Name
Setting
19–16
BL
0011
15–0
—
0
Description
BL = burst length - 1 = 4 - 1 = 3
Reserved. Should be cleared.
17.7.4 SDRAM Control Register Settings and PALL command
The SDCR should be programmed as shown in Figure 17-17. Along with the base settings for the
SDCR the MODE_EN and IPALL bits are set to issue a PALL command to the SDRAM and
enable writing of the mode register.
31
30
Field MODE CKE
_EN
29
28
—
REF
27
26
25
—
24
23
MUX
Setting
22
21
20
—
19
18
17
16
RCNT
1100_0001_0000_1001
(hex)
C
15
14
1
13
Field DQS_
BP
12
11
10
0
9
8
DQS_OE
—
7
6
9
5
4
3
—
Setting
2
1
0
IREF IPALL
—
0000_0000_0000_0010
(hex)
0
0
0
2
Figure 17-17. SDRAM Control Register Settings + MODE_EN and IPALL
This configuration results in a value of SDCR = 0xC109_0002, as described in Table 17-18. A
dummy read/write to SDRAM address space is required to actually send the PALL command.
Table 17-18. SDCR + MODE_EN and IPALL Field Descriptions
Bits
Name
Setting
Description
31
MODE_EN
1
Mode register is writable.
30
CKE
1
SDCKE is asserted
29
—
0
Reserved. Should be cleared.
28
REF
0
Automatic refresh is disabled
27–26
—
00
Reserved. Should be cleared.
25–24
MUX
01
01 is the MUX setting for a 13 x 10 x 2 memory. See Table 17-2.
23–22
—
0
Reserved. Should be cleared.
21–16
RCNT
001001
15
DQS_BP
0
14–12
—
000
RCNT = (tREFI/ (SDCLK x 64)) - 1 = (7800ns/(12ns x 64)) - 1 = 9.156, round down
to 9
Bypass disabled. Read clock recovered from DQS pins.
Reserved. Should be cleared.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-27
SDRAM Controller (SDRAMC)
Table 17-18. SDCR + MODE_EN and IPALL Field Descriptions (Continued)
Bits
Name
Setting
Description
11–10
DQS_OE
00
0x0 disables drive for all SDDQS pins for now.
9–3
—
0
Reserved. Should be cleared.
2
IREF
0
Do not initiate a REF command.
1
IPALL
1
Initiate a PALL command.
0
—
0
Reserved. Should be cleared.
17.7.5 Set the Extended Mode Register
The SDMR should be programmed as shown in Figure 17-18. This step enables the DDR
memory’s DLL.
31
Field
30
29
28
27
26
25
BNKAD
24
23
22
21
20
19
OPTION
Setting
18
17
16
DLL
—
CMD
1
0
0100_0000_0000_0001
(hex)
4
15
14
0
13
12
11
10
0
9
Field
8
7
6
1
5
4
3
2
—
Setting
0000_0000_0000_0000
(hex)
0
0
0
0
Figure 17-18. SDRAM Mode/Extended Mode Register Settings (SDMR)
This configuration results in a value of SDMR = 0x4001_0000, as described in Table 17-19. A
dummy read/write to SDRAM address space is required to actually send the LEMR command.
Table 17-19. SDMR Field Descriptions
Bits
Name
Setting
Description
31–30
BNKAD
01
01 selects the extended mode register.
29–18
OPTION
0
Optional operating modes for the DDR. 0 selects normal operation.
18
DLL
0
Enable the DLL.
17
—
0
Reserved. Should be cleared.
16
CMD
1
Initiate the LEMR command.
15–0
—
0
Reserved. Should be cleared.
MCF5275 Reference Manual, Rev. 2
17-28
Freescale Semiconductor
DDR SDRAM Example
17.7.6 Set the Mode Register and Reset DLL
The SDMR should be programmed as shown in Figure 17-19. This step programs the mode
register and resets the DLL.
31
Field
30
29
28
BNKAD
27
26
25
24
23
OP_MODE
22
21
CASL
Setting
20
BT
19
18
BLEN
17
16
—
CMD
1
0
0000_0100_1001_1101
(hex)
0
15
14
4
13
12
11
10
9
9
Field
8
7
6
D
5
4
3
2
—
Setting
0000_0000_0000_0000
(hex)
0
0
0
0
Figure 17-19. SDRAM Mode/Extended Mode Register Settings (SDMR)
This configuration results in a value of SDMR = 0x049D_0000, as described in Table 17-20. A
dummy read/write to SDRAM address space is required to actually send the LMR command.
Table 17-20. SDMR Field Descriptions
Bits
Name
Setting
Description
31–30
BNKAD
00
29–25
OP_MODE
0010
Selects normal operating mode and resets the DLL.
24–22
CASL
010
CAS latency of two clocks.
21
BT
0
Sequential burst type.
20–18
BLEN
111
Burst length of eight.
17
—
0
Reserved. Should be cleared.
16
CMD
1
Initiate the LMR command.
15–0
—
0
Reserved. Should be cleared.
00 selects the mode register.
17.7.7 Issue a PALL command
The SDCR should be programmed as shown in Figure 17-20. This will issue a second PALL
command to the memory. The same SDCR value calculated in Section 17.7.4, “SDRAM Control
Register Settings and PALL command” is used (0xC10D_0002).
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-29
SDRAM Controller (SDRAMC)
31
30
Field MODE CKE
_EN
29
28
—
REF
27
26
25
—
24
23
MUX
Setting
22
21
20
—
19
18
17
16
RCNT
1100_0001_0000_1001
(hex)
C
15
14
1
13
Field DQS_
BP
12
11
10
0
9
8
7
DQS_OE
—
6
9
5
4
3
—
Setting
2
1
IREF IPALL
0
—
0000_0000_0000_0010
(hex)
0
0
0
2
Figure 17-20. SDRAM Control Register Settings + MODE_EN and IPALL
This configuration results in a value of SDCR = 0xC109_0002, as described in Table 17-21. A
dummy read/write to SDRAM address space is required to actually send the PALL command.
Table 17-21. SDCR + MODE_EN and IPALL Field Descriptions
Bits
Name
Setting
31
MODE_EN
1
Mode register is writable.
30
CKE
1
SDCKE is asserted
29
—
0
Reserved. Should be cleared.
28
REF
0
Automatic refresh is disabled
27–26
—
00
Reserved. Should be cleared.
25–24
MUX
01
01 is the MUX setting for a 13 x 10 x 2 memory. See Table 17-2.
23–22
—
0
Reserved. Should be cleared.
21–16
RCNT
001001
15
DQS_BP
0
14–12
—
000
Reserved. Should be cleared.
11–10
DQS_OE
00
0x0 disables drive for all SDDQS pins for now.
9–3
—
0
Reserved. Should be cleared.
2
IREF
0
Do not initiate a REF command.
1
IPALL
1
Initiate a PALL command.
0
—
0
Reserved. Should be cleared.
17.8
Description
RCNT = (tREFI/ (SDCLK x 64)) - 1 = (7800ns/(12ns x 64)) - 1 = 9.156, round down
to 9
Bypass disabled. Read clock recovered from DQS pins.
Perform Two Refresh Cycles
The SDCR should be programmed as shown in Figure 17-21. Along with the base settings for the
SDCR the MODE_EN and IREF bits are set to issue an REF command to the SDRAM and enable
MCF5275 Reference Manual, Rev. 2
17-30
Freescale Semiconductor
Perform Two Refresh Cycles
writing of the mode register. The memory used in this example requires two refresh cycles, so this
step is repeated twice.
31
30
Field MODE CKE
_EN
29
28
—
REF
27
26
25
—
24
23
MUX
Setting
22
21
20
—
19
18
17
16
1
0
RCNT
1100_0001_0000_1001
(hex)
C
15
14
1
13
Field DQS_
BP
12
11
10
0
9
8
7
DQS_OE
—
6
9
5
4
3
—
Setting
2
IREF IPALL
—
0000_0000_0000_0100
(hex)
0
0
0
4
Figure 17-21. SDRAM Control Register Settings + MODE_EN and IREF
This configuration results in a value of SDCR = 0xC109_0004, as described in Table 17-22.
Table 17-22. SDCR + MODE_EN and IREF Field Descriptions
Bits
Name
Setting
Description
31
MODE_EN
1
Mode register is writable.
30
CKE
1
SDCKE is asserted
29
—
0
Reserved. Should be cleared.
28
REF
0
Automatic refresh is disabled
27–26
—
00
Reserved. Should be cleared.
25–24
MUX
01
01 is the MUX setting for a 13 x 10 x 2 memory. See Table 17-2.
23–22
—
0
Reserved. Should be cleared.
21–16
RCNT
001001
15
DQS_BP
0
14–12
—
000
Reserved. Should be cleared.
11–10
DQS_OE
00
0x0 disables drive for all SDDQS pins for now.
9–3
—
0
Reserved. Should be cleared.
2
IREF
1
Initiate a REF command.
1
IPALL
0
Do not initiate a PALL command.
0
—
0
Reserved. Should be cleared.
RCNT = (tREFI/ (SDCLK x 64)) - 1 = (7800ns/(12ns x 64)) - 1 = 9.156, round down
to 9
Bypass disabled. Read clock recovered from DQS pins.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-31
SDRAM Controller (SDRAMC)
17.8.1 Clear the Reset DLL Bit in the Mode Register
The SDMR should be programmed as shown in Figure 17-22. This step programs the mode
register and enables normal operation of the DLL by clearing the “reset DLL” option.
31
Field
30
29
BNKAD
28
27
26
25
24
OP_MODE
22
21
CASL
Setting
20
BT
19
18
BLEN
17
16
—
CMD
1
0
0000_0000_1001_1101
(hex)
0
15
14
0
13
12
11
10
9
9
8
Field
7
6
D
5
4
3
2
—
Setting
(hex)
23
0000_0000_0000_0000
0
0
0
0
Figure 17-22. SDRAM Mode/Extended Mode Register Settings
This configuration results in a value of SDMR = 0x009D_0000, as described in Table 17-23. A
dummy read/write to SDRAM address space is required to actually send the LMR command.
Table 17-23. SDMR Field Descriptions
Bits
Name
Setting
Description
31–30
BNKAD
00
29–25
OP_MODE
0000
Selects normal operating mode.
24–22
CASL
010
CAS latency of two clocks.
21
BT
0
Sequential burst type.
20–18
BLEN
111
Burst length of eight.
17
—
0
Reserved. Should be cleared.
16
CMD
1
Initiate the LMR command.
15–0
—
0
Reserved. Should be cleared.
00 selects the mode register.
17.8.2 Enable Automatic Refresh and Lock Mode Register
The SDCR should be programmed as shown in Figure 17-23. Along with the base settings for the
SDCR the REF bit is set to enable automatic refreshing of the memory. In addition, the
MODE_EN bit is cleared to disable write to the SDMR.
MCF5275 Reference Manual, Rev. 2
17-32
Freescale Semiconductor
Perform Two Refresh Cycles
31
30
Field MODE CKE
_EN
29
28
—
REF
27
26
25
—
24
23
MUX
Setting
22
21
20
—
19
18
17
16
RCNT
0101_0001_0000_1001
(hex)
5
15
1
14
13
Field DQS_
BP
12
11
10
0
9
8
7
6
DQS_OE
—
9
5
4
3
—
Setting
2
1
0
IREF IPALL
—
0000_1100_0000_0000
(hex)
0
C
0
0
Figure 17-23. SDRAM Control Register Settings + REF
This configuration results in a value of SDCR = 0x510D_0C00, as described in Table 17-24.
Table 17-24. SDCR + REF Field Descriptions
Bits
Name
Setting
Description
31
MODE_EN
0
Mode register is not writable.
30
CKE
1
SDCKE is asserted
29
—
0
Reserved. Should be cleared.
28
REF
0
Automatic refresh is disabled
27–26
—
00
Reserved. Should be cleared.
25–24
MUX
01
01 is the MUX setting for a 13 x 10 x 2 memory. See Table 17-2.
23–22
—
0
Reserved. Should be cleared.
21–16
RCNT
001001
15
DQS_BP
0
14–12
—
000
11–10
DQS_OE
11
Enables drive for all SD_DQS pins.
9–3
—
0
Reserved. Should be cleared.
2
IREF
0
Do not initiate a REF command.
1
IPALL
0
Do not initiate a PALL command.
0
—
0
Reserved. Should be cleared.
RCNT = (tREFI/ (SDCLK x 64)) - 1 = (7800ns/(12ns x 64)) - 1 = 9.156, round down
to 9
Bypass disabled. Read clock recovered from DQS pins.
Reserved. Should be cleared.
17.8.3 Initialization Code
The following assembly code initializes the DDR SDRAM using the register values determined
above.
Basic Configuration and Initialization:
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-33
SDRAM Controller (SDRAMC)
move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
#0x00000000,
d0, SDBAR0
#0x03FC0001,
d0, SDMR0
#0x23611630,
d0, SDCFG1
#0x24330000,
d0, SDCFG2
d0 //Initialize SDBAR0
d0 //Initialize SDMR0
d0 //Initialize SDCFG1
d0 //Initialize SDCFG2
Precharge Sequence and enable write to SDMR:
move.l
move.l
#0xC1090002, d0 //Initialize SDCR, send PALL, enable SDMR
d0, SDCR
move.l
move.l
#0x0,a0
#0xdeadbeef,(a0)//dummy write to SDRAM space
Write Extended Mode Register:
move.l
move.l
#0x40010000, d0 //Write LEMR to enable DLL
d0, SDMR
move.l
move.l
#0x0,a0
#0xdeadbeef,(a0)//dummy write to SDRAM space
Write Mode Register and Reset DLL:
move.l
move.l
#0x049D0000, d0 //Write LMR and reset DLL
d0, SDMR
move.l
move.l
#0x0,a0
#0xdeadbeef,(a0)//dummy write to SDRAM space
Precharge Sequence:
move.l
move.l
#0xC1090002, d0 //Send PALL
d0, SDCR
move.l
move.l
#0x0,a0
#0xdeadbeef,(a0)//dummy write to SDRAM space
Refresh Sequence:
move.l
move.l
move.l
move.l
#0xC1090004, d0 //Send first REF command
d0, SDCR
#0xC1090004, d0 //Send second REF command
d0, SDCR
Write Mode Register and Clear Reset DLL:
move.l
move.l
#0x009D0000, d0 //Write LMR and clear reset DLL
d0, SDMR
MCF5275 Reference Manual, Rev. 2
17-34
Freescale Semiconductor
Perform Two Refresh Cycles
move.l
move.l
#0x0,a0
#0xdeadbeef,(a0)//dummy write to SDRAM space
Enable Auto Refresh and Lock SDMR:
move.l
move.l
#0x51090C00, d0 //Enable auto refresh and clear MODE_EN
d0, SDCR
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
17-35
SDRAM Controller (SDRAMC)
MCF5275 Reference Manual, Rev. 2
17-36
Freescale Semiconductor
Chapter 18
DMA Controller Module
18.1
Introduction
This chapter describes the Direct Memory Access (DMA) controller module. It provides an
overview of the module and describes in detail its signals and registers. The latter sections of this
chapter describe operations, features, and supported data transfer modes in detail.
NOTE
The designation “n” is used throughout this section to refer to registers
or signals associated with one of the four identical DMA channels:
DMA0, DMA1, DMA2 or DMA3.
18.1.1 Overview
The DMA controller module provides an efficient way to move blocks of data with minimal
processor interaction. The DMA module, shown in Figure 18-1, provides four channels that allow
byte, word, longword, or 16-byte burst data transfers. Each channel has a dedicated source address
register (SARn), destination address register (DARn), byte count register (BCRn), control register
(DCRn), and status register (DSRn). Transfers are dual address to on-chip devices, such as UART
and SDRAM controller.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
18-1
DMA Controller Module
DREQ0
DREQ1
DREQ2
Channel 0 Channel 1 Channel 2 Channel 3
Internal
Bus
SAR0
SAR1
SAR2
SAR3
DAR0
DAR1
DAR2
DAR3
BCR0
BCR1
BCR2
BCR3
DCR0
DCR1
DCR2
DCR3
DSR0
DSR1
DSR2
DSR3
Channel
Requests
Channel
Attributes
Channel
Enables
System Bus Address
MUX
MUX
Control
Data Path
Read Data Bus
Interrupts
System Bus Size
Current Master Attributes
Arbitration/
Control
Data Path
Control
Write Data Bus
Bus Interface
Registered
Bus Signals
MCF5275 Reference Manual, Rev. 2
18-2
Freescale Semiconductor
Introduction
DREQ0
DREQ1
DREQ2
DREQ3
Channel 0 Channel 1 Channel 2 Channel 3
Internal
Bus
SAR0
SAR1
SAR2
SAR3
DAR0
DAR1
DAR2
DAR3
BCR0
BCR1
BCR2
BCR3
DCR0
DCR1
DCR2
DCR3
DSR0
DSR1
DSR2
DSR3
Channel
Requests
Channel
Attributes
Channel
Enables
System Bus Address
MUX
MUX
Control
Data Path
Read Data Bus
Interrupts
System Bus Size
Current Master Attributes
Arbitration/
Control
Data Path
Control
Write Data Bus
Bus Interface
Registered
Bus Signals
Figure 18-1. DMA Signal Diagram
NOTE
Throughout this chapter “external request” and DREQ are used to
refer to a DMA request from one of the on-chip UARTS, DMA timers,
or DREQ signals. For details on the connections associated with DMA
request inputs, see Section 18.3.1, “DMA Request Control
(DMAREQC).”
18.1.2 Features
The DMA controller module features are as follows:
•
•
•
•
Four independently programmable DMA controller channels
Auto-alignment feature for source or destination accesses
Dual-address transfers
Channel arbitration on transfer boundaries
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
18-3
DMA Controller Module
•
•
•
•
•
•
18.2
Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
Continuous-mode or cycle-steal transfers
Independent transfer widths for source and destination
Independent source and destination address registers
Modulo addressing on source and destination addresses
Automatic channel linking
DMA Transfer Overview
The DMA module can move data within system memory (including memory and peripheral
devices) with minimal processor intervention, greatly improving overall system performance. The
DMA module consists of four independent, functionally equivalent channels, so references to
DMA in this chapter apply to any of the channels. It is not possible to implicitly address all four
channels at once.
The processor generates DMA requests internally by setting DCR[START]; the UART modules
and DMA timers can generate a DMA request by asserting internal DREQ signals. The processor
can program bus bandwidth for each channel. The channels support cycle-steal and continuous
transfer modes; see Section 18.4.1, “Transfer Requests (Cycle-Steal and Continuous Modes).”
The DMA controller supports dual-address transfers. The DMA channels support up to 32 data
bits.
•
Dual-address transfers—A dual-address transfer consists of a read followed by a write and
is initiated by an internal request using the START bit or by asserting DREQn. Two types
of transfer can occur: a read from a source device or a write to a destination device. See
Figure 18-2 for more information.
Control and Data
Memory/
Peripheral
DMA
Control and Data
Memory/
Peripheral
Figure 18-2. Dual-Address Transfer
MCF5275 Reference Manual, Rev. 2
18-4
Freescale Semiconductor
Memory Map/Register Definition
Any operation involving the DMA module follows the same three steps:
1. Channel initialization—Channel registers are loaded with control information, address
pointers, and a byte-transfer count.
2. Data transfer—The DMA accepts requests for operand transfers and provides addressing
and bus control for the transfers.
3. Channel termination—Occurs after the operation is finished, either successfully or due to
an error. The channel indicates the operation status in the channel’s DSR, described in
Section 18.3.4.1, “DMA Status Registers (DSR0–DSR3).”
18.3
Memory Map/Register Definition
This section describes each internal register and its bit assignment. Note that modifying DMA
control registers during a DMA transfer can result in undefined operation. Table 18-1 shows the
mapping of DMA controller registers.
Table 18-1. Memory Map for DMA Controller Module Registers
DMA
Channel
IPSBAR Offset
—
0x00_0014
DMA Request Control Register (DMAREQC)1
0
0x00_0100
Source Address Register 0 (SAR0)
0x00_0104
Destination Address Register 0 (DAR0)
0x00_0108
1
Source Address Register 1 (SAR1)
0x00_0114
Destination Address Register 1 (DAR1)
Status Register 1
(DSR1)
Byte Count Register 1 (BCR1)
0x00_011C
Control Register 1 (DCR1)
0x00_0120
Source Address Register 2 (SAR2)
0x00_0124
Destination Address Register 2 (DAR2)
Status Register 2
(DSR2)
Byte Count Register 2 (BCR2)
0x00_012C
Control Register 2 (DCR2)
0x00_0130
Source Address Register 3 (SAR3)
0x00_0134
Destination Address Register 3 (DAR3)
Status Register 3
(DSR3)
0x00_013C
[7:0]
Byte Count Register 0 (BCR0)
0x00_0110
0x00_0138
1
[15:8]
Control Register 0 (DCR0)
0x00_0128
3
Status Register 0
(DSR0)
[23:16]
0x00_010C
0x00_0118
2
[31:24]
Byte Count Register 3 (BCR3)
Control Register 3 (DCR3)
Located within the SCM, but listed here for clarity.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
18-5
DMA Controller Module
18.3.1 DMA Request Control (DMAREQC)
The DMAREQC register provides a software-controlled connection matrix for DMA requests. It
logically routes DMA requests from the DMA timers and UARTs to the four channels of the DMA
controller. Writing to this register determines the exact routing of the DMA request to the four
channels of the DMA modules. If DCRn[EEXT] is set and the channel is idle, the assertion of the
appropriate DREQn activates channel n.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMAREQC_EXT
W
Reset
R
DMAC3
DMAC2
DMAC1
DMAC0
W
Reset
0
0
0
0
0
Address
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0014
Figure 18-3. DMA Request Control Register (DMAREQC)
Table 18-2. DMAREQC Field Description
Bits
Name
31–20
—
19-16
Description
Reserved, should be cleared.
DMAREQC DMA request control for external (off-chip) requests. The DMAREQC_EXT[3:0] bits
_EXT
correspond to DMA channels 3, 2, 1, and 0. If set, the corresponding DMACn bit field is
ignored. If cleared, refer to the appropriate DMACn bit field for configuring the internal
DMA requestor.
DMAREQC_
EXT[3]
DMAREQC_
EXT[2]
DMAREQC_
EXT[1]
DMAREQC_
EXT[0]
0
See DMAC3
See DMAC2
See DMAC1
See DMAC0
1
External DREQ3
External
DREQ2
External DREQ1
External
DREQ0
Note: GPIO must be configured to enable external DMA requests.
MCF5275 Reference Manual, Rev. 2
18-6
Freescale Semiconductor
Memory Map/Register Definition
Table 18-2. DMAREQC Field Description (Continued)
Bits
Name
Description
15–0
DMACn
DMA channel n. Each four bit field defines the logical connection between the DMA
requestors and that DMA channel.There are ten possible requesters (4 DMA Timers and
6 UARTs). Any request can be routed to any of the DMA channels. Effectively, the
DMAREQC provides a software-controlled routing matrix of the 10 DMA request signals to
the 4 channels of the DMA module. DMAC3 controls DMA channel 3, DMAC2 controls
DMA channel 2, etc.
0100 DMA Timer 0.
0101 DMA Timer 1.
0110 DMA Timer 2.
0111 DMA Timer 3.
1000 UART0 Receive.
1001 UART1 Receive.
1010 UART2 Receive.
1100 UART0 Transmit.
1101 UART1 Transmit.
1110 UART2 Transmit.
All other values are reserved and will not generate a DMA request.
18.3.2 Source Address Registers (SAR0–SAR3)
SARn, shown in Figure 18-4, contains the address from which the DMA controller requests data.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
SAR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
SAR
W
Reset
0
0
Address
0
0
0
0
0
0
IPSBAR + 0x00_0100 (DMA0); IPSBAR + 0x00_0110 (DMA1);
IPSBAR + 0x00_0120 (DMA2); IPSBAR + 0x00_0130 (DMA3)
Figure 18-4. Source Address Registers (SARn)
NOTE
The backdoor enable bit must be set in the SCM RAMBAR as well as
the secondary port valid bit in the Core RAMBAR in order to enable
backdoor accesses from the DMA to SRAM. See Section 11.2.1.2,
“Memory Base Address Register (RAMBAR)” and Section 6.2.1,
“SRAM Base Address Register (RAMBAR)” for more details.
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Freescale Semiconductor
18-7
DMA Controller Module
18.3.3 Destination Address Registers (DAR0–DAR3)
DARn, shown in Figure 18-5, holds the address to which the DMA controller sends data.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
DAR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
DAR
W
Reset
0
0
0
Address
0
0
0
0
0
IPSBAR + 0x00_0104 (DMA0); IPSBAR + 0x00_0114 (DMA1);
IPSBAR + 0x00_0124 (DMA2); IPSBAR + 0x00_0134 (DMA3)
Figure 18-5. Destination Address Registers (DARn)
NOTE
The DMA does not maintain coherency with the cache. Therefore,
DMAs should not transfer data to cacheable memory unless software
is used to maintain the cache coherency.
18.3.4 Byte Count Registers (BCR0–BCR3) and DMA Status
Registers (DSR0–DSR3)
BCRn, shown in Figure 18-6, contains the number of bytes yet to be transferred for a given block.
BCRn decrements on the successful completion of the address transfer of a write transfer. BCRn
decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively.
31
30
29
28
R
27
26
25
24
23
22
21
20
DSR
19
18
17
16
BCR
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
BCR
W
Reset
Address
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0108 (DMA0); IPSBAR + 0x00_0118 (DMA1);
IPSBAR + 0x00_0128 (DMA2); IPSBAR + 0x00_0138 (DMA3)
Figure 18-6. Byte Count Registers (BCRn) and Status Registers (DSRn)
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Freescale Semiconductor
Memory Map/Register Definition
DSRn[DONE], shown in Figure 18-7, is set when the block transfer is complete.
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when the
DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no
transfer occurs. See Section 18.3.4.1, “DMA Status Registers (DSR0–DSR3).”
18.3.4.1 DMA Status Registers (DSR0–DSR3)
In response to an event, the DMA controller writes to the appropriate DSRn bit, Figure 18-7. Only
a write to DSRn[DONE] results in action.
R
7
6
5
4
3
2
1
0
0
CE
BES
BED
0
REQ
BSY
DONE
0
0
0
0
0
0
0
0
W
Reset
Address
See Figure 18-6
Figure 18-7. DMA Status Registers (DSRn)
Table 18-3. DSRn Field Descriptions
Bits
Name
Description
7
—
Reserved, should be cleared.
6
CE
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested
transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at
hardware reset or by writing a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
5
BES
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
4
BED
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
3
—
2
REQ
Reserved, should be cleared.
Request
0 No request is pending or the channel is currently active. Cleared when the channel is
selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
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Freescale Semiconductor
18-9
DMA Controller Module
Table 18-3. DSRn Field Descriptions (Continued)
Bits
Name
Description
1
BSY
0
DONE
Busy
0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.
1 BSY is set the first time the channel is enabled after a transfer is initiated.
Transactions done. Set when all DMA controller transactions complete, as determined by
transfer count or error conditions. When BCR reaches zero, DONE is set when the final
transfer completes successfully. DONE can also be used to abort a transfer by resetting
the status bits. When a transfer completes, software must clear DONE before
reprogramming the DMA.
0 Writing or reading a 0 has no effect.
1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be
used in an interrupt handler to clear the DMA interrupt and error bits.
18.3.5 DMA Control Registers (DCR0–DCR3)
DCRn, shown in Figure 18-8, is used for configuring the DMA controller module.
31
30
R INT EEXT
29
28
CS
AA
27
26
25
BWC
24
23
22
0
0
SINC
21
20
SSIZE
19
18
DINC
17
16
DSIZE
0
W
Reset
START
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D_REQ
0
LINKCC
0
0
0
R
SMOD
DMOD
LCH1
LCH2
W
Reset
0
0
0
Address
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x00_010C (DMA0); IPSBAR + 0x011C (DMA1);
IPSBAR + 0x012C (DMA2); IPSBAR + 0x013C (DMA3)
Figure 18-8. DMA Control Registers (DCRn)
Table 18-4. DCRn Field Descriptions
Bits
Name
31
INT
30
EEXT
Description
Interrupt on completion of transfer. Determines whether an interrupt is generated by
completing a transfer or by the occurrence of an error condition.
0 No interrupt is generated.
1 Internal interrupt signal is enabled.
Enable external request. Care should be taken because a collision can occur between the
START bit and DREQn when EEXT = 1.
0 External request is ignored.
1 Enables external request to initiate transfer. The internal request (initiated by setting the
START bit) is always enabled.
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Freescale Semiconductor
Memory Map/Register Definition
Table 18-4. DCRn Field Descriptions (Continued)
Bits
Name
Description
29
CS
Cycle steal.
0 DMA continuously makes read/write transfers until the BCR decrements to 0.
1 Forces a single read/write transfer per request. The request may be internal by setting
the START bit, or external by asserting DREQn.
28
AA
Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that
is, transfers are optimized based on the address and size. See Section 18.4.4.2,
“Auto-Alignment.”
0 Auto-align disabled
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned;
otherwise, destination accesses are auto-aligned. Source alignment takes precedence
over destination alignment. If auto-alignment is enabled, the appropriate address
register increments, regardless of DINC or SINC.
27–25
BWC
Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count
reaches a multiple of the BWC value, the DMA releases the bus.
BWC
Number of kilobytes per block
000
DMA has priority and does not negate
its request until transfer completes.
001
16 Kbytes
010
32 Kbytes
011
64 Kbytes
100
128 Kbytes
101
256 Kbytes
110
512 Kbytes
111
1024 Kbytes
24-23
—
Reserved, should be cleared.
22
SINC
Source increment. Controls whether a source address increments after each successful
transfer.
0 No change to SAR after a successful transfer.
1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size.
21–20
SSIZE
Source size. Determines the data size of the source bus cycle for the DMA control module.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
19
DINC
Destination increment. Controls whether a destination address increments after each
successful transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.
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Freescale Semiconductor
18-11
DMA Controller Module
Table 18-4. DCRn Field Descriptions (Continued)
Bits
Name
18–17
DSIZE
Destination size. Determines the data size of the destination bus cycle for the DMA
controller.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
16
START
Start transfer.
0 DMA inactive
1 The DMA begins the transfer in accordance to the values in the control registers. START
is cleared automatically after one system clock and is always read as logic 0.
15–12
SMOD
Source address modulo. Defines the size of the source data circular buffer used by the
DMA Controller. If enabled (SMOD is non-zero), the buffer base address will be located
on a boundary of the buffer size. The value of this boundary is based upon the initial
source address (SAR).
11–8
DMOD
Description
SMOD
Circular Buffer Size
0000
Buffer Disabled
0001
16 Bytes
0010
32 Bytes
...
...
1111
256 Kbytes
Destination address modulo. Defines the size of the destination data circular buffer used
by the DMA Controller. If enabled (DMOD value is non-zero), the buffer base address will
be located on a boundary of the buffer size. The value of this boundary depends on the
initial destination address (DAR).
.
7
D_REQ
DMOD
Circular Buffer Size
0000
Buffer Disabled
0001
16 Bytes
0010
32 Bytes
...
...
1111
256 Kbytes
Disable request. DMA hardware automatically clears the corresponding DCRn[EEXT] bit
when the byte count register reaches zero.
0 EEXT bit is not affected.
1 EEXT bit is cleared when the BCR is exhausted.
6
—
Reserved, should be cleared.
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18-12
Freescale Semiconductor
Functional Description
Table 18-4. DCRn Field Descriptions (Continued)
Bits
Name
Description
5–4
LINKCC
Link channel control. Allows DMA channels to have their transfers linked. The current
DMA channel will trigger a DMA request to the linked channels (LCH1 or LCH2) depending
on the condition described by the LINKCC bits.
00 No channel-to-channel linking
01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to
LCH2 after the BCR decrements to zero.
10 Perform a link to channel LCH1 after each cycle-steal transfer
11 Perform a link to channel LCH1 after the BCR decrements to zero
If not in cycle steal mode (DCRn[CS]=0) and LINKCC=01 or 10, then no link to LCH1 will
occur.
If LINKCC = 01, a link to LCH1 is created after each cycle-steal transfer performed by the
current DMA channel is completed. As the last cycle-steal is performed and the BCR
reaches zero, then the link to LCH1 is closed and a link to LCH2 is created.
If the LINKCC field is non-zero, the contents of the bandwidth control field (DCRn[BWC])
are ignored and effectively forced to zero by the DMA hardware. This is done to prevent
any non-zero bandwidth control settings from allowing channel arbitration while any type
of link is to be performed.
18.4
3-2
LCH1
Link channel 1. Indicates the DMA channel assigned as link channel 1. The link channel
number cannot be the same as the currently executing channel, and generates a
configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
1-0
LCH2
Link channel 2. Indicates the DMA channel assigned as link channel 2. The link channel
number cannot be the same as the currently executing channel, and generates a
configuration error if this is attempted (DSRn[CE] is set).
00 DMA Channel 0
01 DMA Channel 1
10 DMA Channel 2
11 DMA Channel 3
Functional Description
In the following discussion, the term ‘DMA request’ implies that DCRn[START] or
DCRn[EEXT] is set, followed by assertion of and internal or external DMA request. The START
bit is cleared when the channel begins an internal access.
Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE,DSIZE] are
consistent with the source and destination addresses. If they are not consistent, the configuration
error bit, DSRn[CE], is set. If misalignment is detected, no transfer occurs, DSRn[CE] is set, and,
depending on the DCR configuration, an interrupt event is issued. Note that if the auto-align bit,
DCRn[AA], is set, error checking is performed on the appropriate registers.
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Freescale Semiconductor
18-13
DMA Controller Module
A read/write transfer reads bytes from the source address and writes them to the destination
address. The number of bytes is the larger of the sizes specified by DCRn[SSIZE] and
DCRn[DSIZE]. See Section 18.3.5, “DMA Control Registers (DCR0–DCR3).”
Source and destination address registers (SARn and DARn) can be programmed in the DCRn to
increment at the completion of a successful transfer. BCRn decrements when an address transfer
write completes for a single-address access (DCRn[SAA] = 0) or when SAA = 1.
18.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)
The DMA channel supports internal and external requests. A request is issued by setting
DCRn[START] or by asserting DREQn. Setting DCRn[EEXT] enables recognition of external
DMA requests. Selecting between cycle-steal and continuous modes minimizes bus usage for
either internal or external requests.
•
•
Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to destination
occurs for each request. If DCRn[EEXT] is set, a request can be either internal or external.
An internal request is selected by setting DCRn[START]. An external request is initiated
by asserting DREQn while DCRn[EEXT] is set. Note that multiple transfers will occur if
DREQn is continuously asserted.
Continuous mode (DCRn[CS] = 0)—After an internal or external request, the DMA
continuously transfers data until BCRn reaches zero or a multiple of DCRn[BWC] or until
DSRn[DONE] is set. If BCRn is a multiple of BWC, the DMA request signal is negated
until the bus cycle terminates to allow the internal arbiter to switch masters. DCRn[BWC]
= 000 specifies the maximum transfer rate; other values specify a transfer rate limit.
The DMA performs the specified number of transfers, then relinquishes bus control. The
DMA negates its internal bus request on the last transfer before BCRn reaches a multiple
of the boundary specified in BWC. On completion, the DMA reasserts its bus request to
regain mastership at the earliest opportunity. The DMA loses bus control for a minimum of
one bus cycle.
18.4.2 Dual-Address Data Transfer Mode
Each channel supports dual-address transfers. Dual-address transfers consist of a source data read
and a destination data write. The DMA controller module begins a dual-address transfer sequence
during a DMA request. If no error condition exists, DSRn[REQ] is set.
•
Dual-address read—The DMA controller drives the SARn value onto the internal address
bus. If DCRn[SINC] is set, the SARn increments by the appropriate number of bytes upon
a successful read cycle. When the appropriate number of read cycles complete (multiple
reads if the destination size is larger than the source), the DMA initiates the write portion
of the transfer.
If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop.
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18-14
Freescale Semiconductor
Functional Description
•
Dual-address write—The DMA controller drives the DARn value onto the address bus. If
DCRn[DINC] is set, DARn increments by the appropriate number of bytes at the
completion of a successful write cycle. BCRn decrements by the appropriate number of
bytes. DSRn[DONE] is set when BCRn reaches zero. If the BCRn is greater than zero,
another read/write transfer is initiated. If the BCRn is a multiple of DCRn[BWC], the DMA
request signal is negated until termination of the bus cycle to allow the internal arbiter to
switch masters.
If a termination error occurs, DSRn[BED,DONE] are set and DMA transactions stop.
18.4.3 Channel Initialization and Startup
Before a block transfer starts, channel registers must be initialized with information describing
configuration, request-generation method, and the data block.
18.4.3.1 Channel Prioritization
The four DMA channels are prioritized in ascending order (channel 0 having highest priority and
channel 3 having the lowest) or in an order determined by DCRn[BWC]. If the BWC encoding for
a DMA channel is 000, that channel has priority only over the channel immediately preceding it.
For example, if DCR3[BWC] = 000, DMA channel 3 has priority over DMA channel 2 (assuming
DCR2[BWC] ≠ 000) but not over DMA channel 1.
If DCR0[BWC] = DCR1[BWC] = 000, DMA0 still has priority over DMA1. In this case,
DCR1[BWC] = 000 does not affect prioritization.
Simultaneous external requests are prioritized either in ascending order or in an order determined
by each channel’s DCRn[BWC] bits.
18.4.3.2 Programming the DMA Controller Module
Note the following general guidelines for programming the DMA:
•
•
No mechanism exists within the DMA module itself to prevent writes to control registers
during DMA accesses.
If the DCRn[BWC] value of sequential channels are equal, the channels are prioritized in
ascending order.
The DMAREQC register is configured to assign peripheral DMA requests or external DMA
request signals to the individual DMA channels.
The SARn is loaded with the source (read) address. If the transfer is from a peripheral device to
memory, the source address is the location of the peripheral data register. If the transfer is from
memory to either a peripheral device or memory, the source address is the starting address of the
data block. This can be any aligned byte address.
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Freescale Semiconductor
18-15
DMA Controller Module
The DARn should contain the destination (write) address. If the transfer is from a peripheral
device to memory, or from memory to memory, the DARn is loaded with the starting address of
the data block to be written. If the transfer is from memory to a peripheral device, DARn is loaded
with the address of the peripheral data register. This address can be any aligned byte address.
SARn and DARn change after each cycle depending on DCRn[SSIZE,DSIZE,
SINC,DINC,SMOD,DMOD] and on the starting address. Increment values can be 1, 2, 4, or 16
for byte, word, longword, or 16-byte line transfers, respectively. If the address register is
programmed to remain unchanged (no count), the register is not incremented after the data
transfer.
BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2,
4, or 16 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared
for channel startup.
As soon as the channel has been initialized, it is started by writing a one to DCRn[START] or
asserting DREQn, depending on the status of DCRn[EEXT]. Programming the channel for
internal requests causes the channel to request the bus and start transferring data immediately. If
the channel is programmed for external request, DREQn must be asserted before the channel
requests the bus.
Changes to DCRn are effective immediately while the channel is active. To avoid problems with
changing a DMA channel setup, write a one to DSRn[DONE] to stop the DMA channel.
18.4.4 Data Transfer
This section describes external requests, auto-alignment, and bandwidth control for DMA
transfers.
18.4.4.1 External Request and Acknowledge Operation
The DMAREQC register in the System Control Module provides a software-controlled
connection matrix between the on- and off-chipplatform DMA request and acknowledge signals.
Writing to this register determines the exact routing of the DMA requests to the four channels of
the DMA module and the acknowledges back to the requesters. If DCRn[EEXT] is set and the
channel is idle, the assertion of the appropriate DREQn or eTPU request activates channel n.
Channels 0, 1, and 2 initiate transfers to an external module by means of DREQ[32:0]. (They are
also available internally to the UART & DTIM interrupt signals.) The request for channel 3 is not
connected externally and is only available internally to the eTPU, UART, and DTIM interrupt
signals. If DCRn[EEXT] = 1 and the channel is idle, the DMA initiates a transfer when DREQn
is asserted or if the eTPU initiates a request.
MCF5275 Reference Manual, Rev. 2
18-16
Freescale Semiconductor
Functional Description
Figure 18-9 shows the minimum 4-clock cycle delay from when DREQn is sampled asserted to
when a DMA bus cycle begins. This delay may be longer, depending on DMA priority, bus
arbitration, and other factors. Figure 18-9 shows the relationship between the assertion of a
properly enabled DREQn, the DMA acknowledge, and the activation of the channel for a transfer
where both the source and destination are mapped to chip select memories on the external bus.
0
1
2
3
4
5
6
7
8
9
10
CLKIN
DREQn
DACKn
TS
CS
TA
R/W
A[23:0]
Read
Write
Figure 18-9. DREQn Timing Constraints, Dual-Address DMA Transfer
Once the DMA module has detected the assertion of a properly-enabled DREQn, it responds with
a 1-cycle assertion of an acknowledge signal. This request/acknowledge handshake is provided so
the request can be negated.
Since bus timings can vary from device to device, the diagrams below are conditionalized for 5210
only. The information is really just a repeat from the EIM/FlexBus and SDRAMC chapters, so the
customers should not need this information. -MH
Figure 18-10 shows a dual-address, external peripheral-to-SDRAM DMA transfer. The DMA is
not parked on the bus, so the diagram shows how the CPU can generate multiple bus cycles during
DMA transfers. In cycle-steal mode, the maximum length of DREQ assertion to maintain a single
transfer is configuration-dependent. To avoid multiple transfers, for single-address accesses, no
hold signal, byte accesses, and idle channels, DREQ may be asserted for no more than four clock
cycles.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
18-17
DMA Controller Module
CLKIN
TS
AS
TIP
A[31:0]
R/W
SIZ[1:0]
D[31:0]
CSx
TA
DRAMW
Precharge
SD_SRAS
SD_SCAS
RAS[1:0]
CAS[3:0]
DREQn
DACKn
CPU
DMA Read
CPU
DMA Write
CPU
Figure 18-10. Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer
Figure 18-11 shows a single-address DMA transfer in which an external peripheral is reading from
memory.
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18-18
Freescale Semiconductor
Functional Description
0
1
2
3
4
5
6
7
8
9
10
11
CLKIN
DREQn
TS
A[31:0], SIZ[1:0]
TIP
R/W
CSx, AS
OE, BE/BWE
TA
D[31:0]
Figure 18-11. Single-Address DMA Transfer
18.4.4.2 Auto-Alignment
Auto-alignment allows block transfers to occur at the optimal size based on the address, byte
count, and programmed size. To use this feature, DCRn[AA] must be set. The source is
auto-aligned if DCRn[SSIZE] indicates a transfer size larger than DCRn[DSIZE]. Source
alignment takes precedence over the destination when the source and destination sizes are equal.
Otherwise, the destination is auto-aligned. The address register chosen for alignment increments
regardless of the increment value. Configuration error checking is performed on registers not
chosen for alignment.
If BCRn is greater than 16, the address determines transfer size. Bytes, words, or longwords are
transferred until the address is aligned to the programmed size boundary, at which time accesses
begin using the programmed size.
If BCRn is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer
size. For example, AA = 1, SARn = 0x0001, BCRn = 0x00F0, SSIZE = 00 (longword), and DSIZE
= 01 (byte). Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on
destination registers. The access sequence is as follows:
1.
2.
3.
4.
5.
Read byte from 0x0001—write 1 byte, increment SARn.
Read word from 0x0002—write 2 bytes, increment SARn.
Read longword from 0x0004—write 4 bytes, increment SARn.
Repeat longwords until SARn = 0x00F0.
Read byte from 0x00F0—write byte, increment SARn.
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Freescale Semiconductor
18-19
DMA Controller Module
If DSIZE is another size, data writes are optimized to write the largest size allowed based on the
address, but not exceeding the configured size.
18.4.4.3 Bandwidth Control
Bandwidth control makes it possible to force the DMA off the bus to allow access to another
device. DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a
multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates.
If a request is pending, the arbiter may then pass bus mastership to another device. If
auto-alignment is enabled, DCRn[AA] = 1, the BCRn may skip over the programmed boundary,
in which case, the DMA bus request is not negated.
If BWC = 000, the request signal remains asserted until BCRn reaches zero. DMA has priority
over the core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus.
See Section 11.3.3, “Bus Master Park Register (MPARK).”
18.4.5 Termination
An unsuccessful transfer can terminate for one of the following reasons:
•
•
Error conditions—When the MCF5275 encounters a read or write cycle that terminates
with an error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write
before the transfer is halted. If the error occurred in a write cycle, data in the internal
holding register is lost.
Interrupts—If DCRn[INT] is set, the DMA drives the appropriate internal interrupt signal.
The processor can read DSRn to determine whether the transfer terminated successfully or
with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE
and error bits.
MCF5275 Reference Manual, Rev. 2
18-20
Freescale Semiconductor
Chapter 19
Fast Ethernet Controllers (FEC0 & FEC1)
19.1
Introduction
This chapter provides a feature-set overview, a functional block diagram, and transceiver
connection information for both the 10 and 100 Mbps MII (Media Independent Interface), as well
as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming
model are included.
19.1.1 Overview
The Ethernet Media Access Controller (MAC) is designed to support both 10 and 100 Mbps
Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are
required to complete the interface to the media. The FECs support three different standard
MAC-PHY (physical) interfaces for connection to an external Ethernet transceiver. The FECs
support the 10/100 Mbps MII and the 10 Mbps-only 7-wire interface, which uses a subset of the
MII pins.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module”) prior to configuring the FECs.
19.1.2 Block Diagram
The block diagram of a single FEC is shown below. The FECs are implemented with a
combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with
industry and IEEE 802.3 standards.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-1
Fast Ethernet Controllers (FEC0 & FEC1)
SIF
Bus
Controller
CSR
Descriptor
Controller
(RISC +
microcode)
RAM
DMA
FIFO
Controller
RAM I/F
FEC Bus
MIB
Counters
MII
MDO
MDEN
Transmit
Receive
MDI
FECn_ETXEN
FECn_ETCLK
FECn_ETXD[3:0] EFECn_CRS
FECn_ETXER
FECn_ECOL
I/O
PAD
FECn_EMDIO FECn_EMDC
FECn_ERXCLK
FECn_ERXDV
FECn_ERXD[3:0]
FECn_ERXER
MII/7-WIRE DATA
OPTION
Figure 19-1. FECn Block Diagram
The descriptor controller is a RISC-based controller that provides the following functions in the
FECs:
•
•
•
•
•
Initialization (those internal registers not initialized by the user or hardware)
High level control of the DMA channels (initiating DMA transfers)
Interpreting buffer descriptors
Address recognition for receive frames
Random number generation for transmit collision backoff timer
MCF5275 Reference Manual, Rev. 2
19-2
Freescale Semiconductor
Introduction
NOTE
DMA references in this section refer to the FEC’s DMA engine. This
DMA engine is for the transfer of FEC data only, and is not related to
the DMA controller described in Chapter 18, “DMA Controller
Module,” nor to the DMA timers described in Chapter 25, “DMA
Timers (DTIM0–DTIM3).”
The RAM is the focal point of all data flow in the Fast Ethernet Controller and is divided into
transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSRn register.
User data flows to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows
from the transmit FIFO into the transmit block and receive data flows from the receive block into
the receive FIFO.
The user controls the FECs by writing, through the SIF (Slave Interface) module, into control
registers located in each block. The CSR (control and status register) block provides global control
(e.g. Ethernet reset and enable) and interrupt handling registers.
The MII block provides a serial channel for control/status communication with the external
physical layer device (transceiver). This serial channel consists of the FECn_EMDC
(Management Data Clock) and FECn_EMDIO (Management Data Input/Output) lines of the MII
interface.
The DMA block provides multiple channels allowing transmit data, transmit descriptor, receive
data and receive descriptor accesses to run independently.
The Transmit and Receive blocks provide the Ethernet MAC functionality (with some assist from
microcode).
The Message Information Block (MIB) maintains counters for a variety of network events and
statistics. It is not necessary for operation of the FEC but provides valuable counters for network
management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and
some of the IEEE 802.3 counters. See Section 19.2.3, “MIB Block Counters Memory Map” for
more information.
19.1.3 Features
The FECs incorporate the following features:
•
•
•
Support for three different Ethernet physical interfaces:
— 100-Mbps IEEE 802.3 MII
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
IEEE 802.3 full duplex flow control
Programmable max frame length supports IEEE 802.1 VLAN tags and priority
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-3
Fast Ethernet Controllers (FEC0 & FEC1)
•
•
•
•
•
Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate
of 50 MHz
Support for half-duplex operation (100Mbps throughput) with a minimum system clock
rate of 25 MHz
Retransmission from transmit FIFO following a collision (no processor bus utilization)
Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no processor bus utilization)
Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
19.1.4 Modes of Operation
The primary operational modes are described in this section.
19.1.4.1 Full and Half Duplex Operation
Full duplex mode is intended for use on point to point links between switches or end node to
switch. Half duplex mode is used in connections between an end node and a repeater or between
repeaters. Selection of the duplex mode is controlled by TCRn[FDEN].
When configured for full duplex mode, flow control may be enabled. Refer to the
TCRn[RFC_PAUSE] and TCRn[TFC_PAUSE] bits, the RCRn[FCE] bit, and Section 19.3.10,
“ Full Duplex Flow Control,” for more details.
19.1.5 Interface Options
The following interface options are supported. A detailed discussion of the interface
configurations is provided in Section 19.3.5, “Network Interface Options”.
19.1.5.1 10 Mbps and 100 Mbps MII Interface
MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100 Mbps
operation. The MAC-PHY interface may be configured to operate in MII mode by asserting
RCRn[MII_MODE].
The speed of operation is determined by the FECn_ETXCLK and FECn_ERXCLK pins which are
driven by the external transceiver. The transceiver will either auto-negotiate the speed or it may be
MCF5275 Reference Manual, Rev. 2
19-4
Freescale Semiconductor
Memory Map/Register Definition
controlled by software via the serial management interface (FECn_EMDC/FECn_EMDIO pins)
to the transceiver. Refer to the MMFRn and MSCRn register descriptions as well as the section on
the MII for a description of how to read and write registers in the transceiver via this interface.
19.1.5.2 10 Mpbs 7-Wire Interface Operation
The FECs support a 7-wire interface as used by many 10 Mbps ethernet transceivers. The
RCR[MII_MODE] bit controls this functionality. If this bit is cleared, the MII mode is disabled
and the 10 Mbps, 7-wire mode is enabled.
19.1.6 Address Recognition Options
The address options supported are promiscuous, broadcast reject, individual address (hash or exact
match), and multicast hash match. Address recognition options are discussed in detail in
Section 19.3.8, “Ethernet Address Recognition.”
19.1.7 Internal Loopback
Internal loopback mode is selected via RCRn[LOOP]. Loopback mode is discussed in detail in
Section 19.3.13, “ Internal and External Loopback.”
19.2
Memory Map/Register Definition
This section gives an overview of the registers, followed by a description of the buffers.
The FECs are programmed by a combination of control/status registers (CSRs) and buffer
descriptors. The CSRs are used for mode control and to extract global status information. The
descriptors are used to pass data buffers and related buffer information between the hardware and
software.
19.2.1 High-Level Module Memory Map
Each FEC implementation requires a 1-Kbyte memory map space. This is divided into 2 sections
of 512 bytes each. The first is used for control/status registers. The second contains event/statistic
counters held in the MIB block. Table 19-1 defines the top level memory map.
Table 19-1. Module Memory Map
Address
Function
IPSBAR + 0x1000–11FF
FEC0 Control/Status Registers
IPSBAR + 0x1200–13FF
FEC0 MIB Block Counters
IPSBAR + 0x1800–19FF
FEC1 Control/Status Registers
IPSBAR + 0x2000–21FF
FEC1 MIB Block Counters
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-5
Fast Ethernet Controllers (FEC0 & FEC1)
19.2.2 Register Memory Map
Table 19-2 shows the FEC register memory map with each register address, name, and a brief
description.
Table 19-2. FEC Register Memory Map
IPSBAR Offset
(FEC0 & FEC1)
Name
Description
Size
(bits)
0x1004 & 0x1804
EIRn
Interrupt Event Register
32
0x1008 & 0x1808
EIMRn
Interrupt Mask Register
32
0x1010 & 0x1810
RDARn
Receive Descriptor Active Register
32
0x1014 & 0x1814
TDARn
Transmit Descriptor Active Register
32
0x1024 & 0x1824
ECRn
Ethernet Control Register
32
0x1040 & 0x1840
MDATAn
MII Data Register
32
0x1044 & 0x1844
MSCRn
MII Speed Control Register
32
0x1064 & 0x1864
MIBCn
MIB Control/Status Register
32
0x1084 & 0x1884
RCRn
Receive Control Register
32
0x10C4 & 0x18C4
TCRn
Transmit Control Register
32
0x10E4 & 0x18E4
PALRn
Physical Address Low Register
32
0x10E8 & 0x18E8
PAURn
Physical Address High+ Type Field
32
0x10EC & 0x18EC
OPDn
Opcode + Pause Duration
32
0x1118 & 0x1918
IAURn
Upper 32 bits of Individual Hash Table
32
0x111C & 0x191C
IALRn
Lower 32 Bits of Individual Hash Table
32
0x1120 & 0x1920
GAURn
Upper 32 bits of Group Hash Table
32
0x1124 & 0x1924
GALRn
Lower 32 bits of Group Hash Table
32
0x1144 & 0x1944
TFWRn
Transmit FIFO Watermark
32
0x114C & 0x194C
FRBRn
FIFO Receive Bound Register
32
0x1150 & 0x1950
FRSRn
FIFO Receive FIFO Start Registers
32
0x1180 & 0x1980
ERDSRn
Pointer to Receive Descriptor Ring
32
0x1184 & 0x1984
ETDSRn
Pointer to Transmit Descriptor Ring
32
0x1188 & 0x1988
EMRBRn
Maximum Receive Buffer Size
32
19.2.3 MIB Block Counters Memory Map
Table 19-3 defines the MIB Counters memory map which defines the locations in the MIB RAM
space where hardware maintained counters reside. These fall in the 0x1200-0x13FF &
0x2000-0x21FF address offset range. The counters are divided into two groups.
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
Memory Map/Register Definition
RMON counters are included which cover the Ethernet Statistics counters defined in RFC 1757.
In addition to the counters defined in the Ethernet Statistics group, a counter is included to count
truncated frames as the FECs only support frame lengths up to 2032 bytes. The RMON counters
are implemented independently for transmit and receive to insure accurate network statistics when
operating in full duplex mode.
IEEE counters are included which support the Mandatory and Recommended counter packages
defined in Section 5 of ANSI/IEEE Std. 802.3 (1998 edition). The IEEE Basic Package objects are
supported by the FECs but do not require counters in the MIB block. In addition, some of the
recommended package objects which are supported do not require MIB counters. Counters for
transmit and receive full duplex flow control frames are included as well.
Table 19-3. MIB Counters Memory Map
IPSBAR Offset
Mnemonic
Description
0x1200 & 0x2000
RMON_T_DROPn
Count of frames not counted correctly
0x1204 & 0x2004
RMON_T_PACKETSn
RMON Tx packet count
0x1208 & 0x2008
RMON_T_BC_PKTn
RMON Tx Broadcast Packets
0x120C & 0x200C
RMON_T_MC_PKTn
RMON Tx Multicast Packets
0x1210 & 0x2010
RMON_T_CRC_ALIGNn
RMON Tx Packets w CRC/Align error
0x1214 & 0x2014
RMON_T_UNDERSIZEn
RMON Tx Packets < 64 bytes, good crc
0x1218 & 0x2018
RMON_T_OVERSIZEn
RMON Tx Packets > MAX_FL bytes, good crc
0x121C & 0x201C
RMON_T_FRAGn
RMON Tx Packets < 64 bytes, bad crc
0x1220 & 0x2020
RMON_T_JABn
RMON Tx Packets > MAX_FL bytes, bad crc
0x1224 & 0x2024
RMON_T_COLn
RMON Tx collision count
0x1228 & 0x2028
RMON_T_P64n
RMON Tx 64 byte packets
0x122C & 0x202C
RMON_T_P65TO127n
RMON Tx 65 to 127 byte packets
0x1230 & 0x2030
RMON_T_P128TO255n
RMON Tx 128 to 255 byte packets
0x1234 & 0x2034
RMON_T_P256TO511n
RMON Tx 256 to 511 byte packets
0x1238 & 0x2038
RMON_T_P512TO1023n
RMON Tx 512 to 1023 byte packets
0x123C & 0x203C
RMON_T_P1024TO2047n
RMON Tx 1024 to 2047 byte packets
0x1240 & 0x2040
RMON_T_P_GTE2048n
RMON Tx packets w > 2048 bytes
0x1244 & 0x2044
RMON_T_OCTETSn
RMON Tx Octets
0x1248 & 0x2048
IEEE_T_DROPn
Count of frames not counted correctly
0x124C & 0x204C
IEEE_T_FRAME_OKn
Frames Transmitted OK
0x1250 & 0x2050
IEEE_T_1COLn
Frames Transmitted with Single Collision
0x1254 & 0x2054
IEEE_T_MCOLn
Frames Transmitted with Multiple Collisions
0x1258 & 0x2058
IEEE_T_DEFn
Frames Transmitted after Deferral Delay
0x125C & 0x205C
IEEE_T_LCOLn
Frames Transmitted with Late Collision
0x1260 & 0x2060
IEEE_T_EXCOLn
Frames Transmitted with Excessive Collisions
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-7
Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-3. MIB Counters Memory Map (Continued)
IPSBAR Offset
Mnemonic
Description
0x1264 & 0x2064
IEEE_T_MACERRn
Frames Transmitted with Tx FIFO Underrun
0x1268 & 0x2068
IEEE_T_CSERRn
Frames Transmitted with Carrier Sense Error
0x126C & 0x206C
IEEE_T_SQEn
Frames Transmitted with SQE Error
0x1270 & 0x2070
IEEE_T_FDXFCn
Flow Control Pause frames transmitted
0x1274 & 0x2074
IEEE_T_OCTETS_OKn
Octet count for Frames Transmitted w/o Error
0x1284 & 0x2084
RMON_R_PACKETSn
RMON Rx packet count
0x1288 & 0x2088
RMON_R_BC_PKTn
RMON Rx Broadcast Packets
0x128C & 0x208C
RMON_R_MC_PKTn
RMON Rx Multicast Packets
0x1290 & 0x2090
RMON_R_CRC_ALIGNn
RMON Rx Packets w CRC/Align error
0x1294 & 0x2094
RMON_R_UNDERSIZEn
RMON Rx Packets < 64 bytes, good crc
0x1298 & 0x2098
RMON_R_OVERSIZEn
RMON Rx Packets > MAX_FL bytes, good crc
0x129C & 0x209C
RMON_R_FRAGn
RMON Rx Packets < 64 bytes, bad crc
0x12A0 & 0x21A0
RMON_R_JABn
RMON Rx Packets > MAX_FL bytes, bad crc
0x12A4 & 0x21A4
RMON_R_RESVD_0n
0x12A8 & 0x21A8
RMON_R_P64n
RMON Rx 64 byte packets
0x12AC & 0x21AC
RMON_R_P65TO127n
RMON Rx 65 to 127 byte packets
0x12B0 & 0x21B0
RMON_R_P128TO255n
RMON Rx 128 to 255 byte packets
0x12B4 & 0x21B4
RMON_R_P256TO511n
RMON Rx 256 to 511 byte packets
0x12B8 & 0x21B8
RMON_R_P512TO1023n
RMON Rx 512 to 1023 byte packets
0x12BC & 0x21BC
RMON_R_P1024TO2047n
RMON Rx 1024 to 2047 byte packets
0x12C0 & 0x21C0
RMON_R_P_GTE2048n
RMON Rx packets w > 2048 bytes
0x12C4 & 0x21C4
RMON_R_OCTETSn
RMON Rx Octets
0x12C8 & 0x21C8
IEEE_R_DROPn
Count of frames not counted correctly
0x12CC & 0x21CC
IEEE_R_FRAME_OKn
Frames Received OK
0x12D0 & 0x21D0
IEEE_R_CRCn
Frames Received with CRC Error
0x12D4 & 0x21D4
IEEE_R_ALIGNn
Frames Received with Alignment Error
0x12D8 & 0x21D8
IEEE_R_MACERRn
Receive Fifo Overflow count
0x12DC & 0x21DC
IEEE_R_FDXFCn
Flow Control Pause frames received
0x12E0 & 0x21E0
IEEE_R_OCTETS_OKn
Octet count for Frames Rcvd w/o Error
19.2.4 Register Description
The following sections describe each register in detail.
MCF5275 Reference Manual, Rev. 2
19-8
Freescale Semiconductor
Memory Map/Register Definition
19.2.4.1 Ethernet Interrupt Event Register (EIR)
When an event occurs that sets a bit in the EIRn, an interrupt will be generated if the corresponding
bit in the interrupt mask register (EIMR) is also set. The bit in the EIR is cleared if a one is written
to that bit position; writing zero has no effect. This register is cleared upon hardware reset.
These interrupts can be divided into operational interrupts, transceiver/network error interrupts,
and internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB,
RXF, RXB, and MII. Interrupts resulting from errors/problems detected in the network or
transceiver are HBERR, BABR, BABT, LC and RL. Interrupts resulting from internal errors are
HBERR and UN.
Some of the error interrupts are independently counted in the MIB block counters. Software may
choose to mask off these interrupts since these errors will be visible to network management via
the MIB counters.
•
•
•
•
•
•
HBERR - IEEE_T_SQE
BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)
BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)
LATE_COL - IEEE_T_LCOL
COL_RETRY_LIM - IEEE_T_EXCOL
XFIFO_UN - IEEE_T_MACERR
31
R
W
Reset
R
30
29
28
27
HB BABR BABT GRA TXF
ERR
26
TXB
25
24
RXF RXB
23
22
21
20
19
18
17
16
MII
EB
ERR
LC
RL
UN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x1004 (FEC0) & IPSBAR + 0x1804 (FEC1)
Figure 19-2. Ethernet Interrupt Event Register (EIRn)
Table 19-4. EIRn Field Descriptions
Bits
Name
Description
31
HBERR
Heartbeat error. This interrupt indicates that HBC is set in the TCRn register and that the
COL input was not asserted within the Heartbeat window following a transmission.
30
BABR
Babbling receive error. This bit indicates a frame was received with length in excess of
RCRn[MAX_FL] bytes.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-9
Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-4. EIRn Field Descriptions (Continued)
Bits
Name
Description
29
BABT
Babbling transmit error. This bit indicates that the transmitted frame length has exceeded
RCRn[MAX_FL] bytes. This condition is usually caused by a frame that is too long being
placed into the transmit data buffer(s). Truncation does not occur.
28
GRA
Graceful stop complete. This interrupt will be asserted for one of three reasons. Graceful
stop means that the transmitter is put into a pause state after completion of the frame
currently being transmitted.
1) A graceful stop, which was initiated by the setting of the TCRn[GTS] bit is now complete.
2) A graceful stop, which was initiated by the setting of the TCRn[TFC_PAUSE] bit is now
complete.
3) A graceful stop, which was initiated by the reception of a valid full duplex flow control
“pause” frame is now complete. Refer to Section 19.3.10, “ Full Duplex Flow Control.”
27
TXF
Transmit frame interrupt. This bit indicates that a frame has been transmitted and that the
last corresponding buffer descriptor has been updated.
26
TXB
Transmit buffer interrupt. This bit indicates that a transmit buffer descriptor has been
updated.
25
RXF
Receive frame interrupt. This bit indicates that a frame has been received and that the last
corresponding buffer descriptor has been updated.
24
RXB
Receive buffer interrupt. This bit indicates that a receive buffer descriptor has been
updated that was not the last in the frame.
23
MII
22
EBERR
Ethernet bus error. This bit indicates that a system bus error occurred when a DMA
transaction was underway. When the EBERR bit is set, ECRn[ETHER_EN] will be cleared,
halting frame processing by the FEC. When this occurs software will need to insure that
the FIFO controller and DMA are also soft reset.
21
LC
Late collision. This bit indicates that a collision occurred beyond the collision window (slot
time) in half duplex mode. The frame is truncated with a bad CRC and the remainder of the
frame is discarded.
20
RL
Collision retry limit. This bit indicates that a collision occurred on each of 16 successive
attempts to transmit the frame. The frame is discarded without being transmitted and
transmission of the next frame will commence. Can only occur in half duplex mode.
19
UN
Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before
the complete frame was transmitted. A bad CRC is appended to the frame fragment and
the remainder of the frame is discarded.
18–0
—
Reserved, should be cleared.
MII interrupt. This bit indicates that the MII has completed the data transfer requested.
19.2.4.2 Interrupt Mask Registers (EIMR0 & EIMR1)
The EIMRn registers control which interrupt events are allowed to generate actual interrupts. All
implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the
corresponding bits in both the EIRn and EIMRn registers are set, the interrupt will be signalled to
the CPU. The interrupt signal will remain asserted until a 1 is written to the EIRn bit (write 1 to
clear) or a 0 is written to the EIMRn bit.
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Freescale Semiconductor
Memory Map/Register Definition
31
R
W
30
29
28
27
HB BABR BABT GRA TXF
ERR
Reset
R
26
TXB
25
24
RXF RXB
23
22
21
20
19
18
17
16
MII
EB
ERR
LC
RL
UN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x1008 (FEC0) & IPSBAR + 0x1808 (FEC1)
Figure 19-3. Interrupt Mask Register (EIMRn)
Table 19-5. EIMRn Field Descriptions
Bits
31–19
Name
Description
See Figure 19-3 Interrupt mask. Each bit corresponds to an interrupt source defined by the EIRn
and Table 19-4. register. The corresponding EIMRn bit determines whether an interrupt condition
can generate an interrupt. At every processor clock, the EIRn samples the signal
generated by the interrupting source. The corresponding EIRn bit reflects the state
of the interrupt signal even if the corresponding EIMRn bit is set.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is not masked.
18–0
—
Reserved, should be cleared.
19.2.4.3 Receive Descriptor Active Registers (RDAR0 & RDAR1)
RDARn is a command register, written by the user, that indicates that the receive descriptor ring
has been updated (empty receive buffers have been produced by the driver with the empty bit set).
Whenever the register is written, the RDAR bit is set. This is independent of the data actually
written by the user. When set, the FEC will poll the receive descriptor ring and process receive
frames (provided ECRn[ETHER_EN] is also set). Once the FEC polls a receive descriptor whose
empty bit is not set, then the FEC will clear the RDAR bit and cease receive descriptor ring polling
until the user sets the bit again, signifying that additional descriptors have been placed into the
receive descriptor ring.
The RDAR registers are cleared at reset and when ECRn[ETHER_EN] is cleared.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-11
Fast Ethernet Controllers (FEC0 & FEC1)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
RDAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Address
IPSBAR + 0x1010 (FEC0) & IPSBAR + 0x1810 (FEC1)
Figure 19-4. Receive Descriptor Active Register (RDARn)
Table 19-6. RDARn Field Descriptions
Bits
Name
31–25
—
24
RDAR
23–0
—
Description
Reserved, should be cleared.
Set to one when this register is written, regardless of the value written. Cleared by the FEC
device whenever no additional “empty” descriptors remain in the receive ring. Also cleared
when ECRn[ETHER_EN] is cleared.
Reserved, should be cleared.
19.2.4.4 Transmit Descriptor Active Registers (TDAR0 & TDAR1)
The TDARn are command registers which should be written by the user to indicate that the
transmit descriptor ring has been updated (transmit buffers have been produced by the driver with
the ready bit set in the buffer descriptor).
Whenever the register is written, the TDAR bit is set. This value is independent of the data actually
written by the user. When set, the FEC will poll the transmit descriptor ring and process transmit
frames (provided ECRn[ETHER_EN] is also set). Once the FEC polls a transmit descriptor whose
ready bit is not set, then the FEC will clear the TDAR bit and cease transmit descriptor ring polling
until the user sets the bit again, signifying additional descriptors have been placed into the transmit
descriptor ring.
The TDARn register is cleared at reset, when ECRn[ETHER_EN] is cleared, or when
ECRn[RESET] is set.
MCF5275 Reference Manual, Rev. 2
19-12
Freescale Semiconductor
Memory Map/Register Definition
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
TDAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
W
Reset
Address
IPSBAR + 0x1014 (FEC0) & IPSBAR + 0x1814 (FEC1)
Figure 19-5. Transmit Descriptor Active Register (TDARn)
Table 19-7. TDARn Field Descriptions
Bits
Name
31–25
—
24
TDAR
23–0
—
Description
Reserved, should be cleared.
Set to one when this register is written, regardless of the value written. Cleared by the FEC
device whenever no additional “ready” descriptors remain in the transmit ring. Also cleared
when ECRn[ETHER_EN] is cleared.
Reserved, should be cleared.
19.2.4.5 Ethernet Control Registers (ECR0 & ECR1)
ECRn is a read/write user register, though both fields in this register may be altered by hardware
as well. The ECRn is used to enable/disable the FEC.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Address
ETHER RESET
_EN
0
0
IPSBAR + 0x1024
Figure 19-6. Ethernet Control Register (ECRn)
Table 19-8. ECRn Field Descriptions
Bits
Name
31–2
—
Description
Reserved.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-13
Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-8. ECRn Field Descriptions (Continued)
Bits
Name
1
Description
ETHER_EN When this bit is set, the FEC is enabled, and reception and transmission are possible.
When this bit is cleared, reception is immediately stopped and transmission is stopped
after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s)
for an aborted transmit frame are not updated after clearing this bit. When ETHER_EN is
deasserted, the DMA, buffer descriptor, and FIFO control logic are reset, including the
buffer descriptor and FIFO pointers. The ETHER_EN bit is altered by hardware under the
following conditions:
• ECRn[RESET] is set by software, in which case ETHER_EN will be cleared
• An error condition causes the EIRn[EBERR] bit to set, in which case ETHER_EN will be
cleared
0
RESET
When this bit is set, the equivalent of a hardware reset is performed but it is local to the
FEC. ETHER_EN is cleared and all other FEC registers take their reset values. Also, any
transmission/reception currently in progress is abruptly aborted. This bit is automatically
cleared by hardware during the reset sequence. The reset sequence takes approximately
8 system clock cycles after RESET is written with a 1.
19.2.4.6 MII Management Frame Registers (MMFR0 & MMFR1)
The MMFRn is accessed by the user and does not reset to a defined value. The MMFRn registers
are used to communicate with the attached MII compatible PHY device(s), providing read/write
access to their MII registers. Performing a write to the MMFRn will cause a management frame
to be sourced unless the MSCRn has been programmed to 0. In the case of writing to MMFRn
when MSCRn = 0, if the MSCRn register is then written to a non-zero value, an MII frame will be
generated with the data previously written to the MMFRn. This allows MMFRn and MSCRn to
be programmed in either order if MSCRn is currently zero.
31
R
30
29
ST
28
27
26
OP
25
24
23
22
21
PA
20
19
18
17
RA
16
TA
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
R
DATA
W
Reset
Address
—
—
—
—
—
—
—
—
IPSBAR + 0x1040 (FEC0) & IPSBAR + 0x1840 (FEC1)
Figure 19-7. MII Management Frame Register (MMFRn)
MCF5275 Reference Manual, Rev. 2
19-14
Freescale Semiconductor
Memory Map/Register Definition
Table 19-9. MMFRn Field Descriptions
Bit
Name
Description
31–30
ST
Start of frame delimiter. These bits must be programmed to 01 for a valid MII management
frame.
29–28
OP
Operation code. This field must be programmed to 10 (read) or 01 (write) to generate a
valid MII management frame. A value of 11 will produce “read” frame operation while a
value of 00 will produce “write” frame operation, but these frames will not be MII compliant.
27–23
PA
PHY address. This field specifies one of up to 32 attached PHY devices.
22–18
RA
Register address. This field specifies one of up to 32 registers within the specified PHY
device.
17–16
TA
Turn around. This field must be programmed to 10 to generate a valid MII management
frame.
15–0
DATA
Management frame data. This is the field for data to be written to or read from the PHY
register.
To perform a read or write operation on the MII Management Interface, the MMFRn register must
be written by the user. To generate a valid read or write management frame, the ST field must be
written with a 01 pattern, and the TA field must be written with a 10. If other patterns are written
to these fields, a frame will be generated but will not comply with the IEEE 802.3 MII definition.
To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY
register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFRn register. Writing
this pattern will cause the control logic to shift out the data in the MMFRn register following a
preamble generated by the control state machine. During this time the contents of the MMFRn
register will be altered as the contents are serially shifted and will be unpredictable if read by the
user. Once the write management frame operation has completed, the MII interrupt will be
generated. At this time the contents of the MMFRn register will match the original value written.
To generate an MII Management Interface read frame (read a PHY register) the user must write
{01 10 PHYAD REGAD 10 XXXX} to the MMFRn register (the content of the DATA field is a
don’t care). Writing this pattern will cause the control logic to shift out the data in the MMFRn
register following a preamble generated by the control state machine. During this time the contents
of the MMFRn register will be altered as the contents are serially shifted, and will be unpredictable
if read by the user. Once the read management frame operation has completed, the MII interrupt
will be generated. At this time the contents of the MMFRn register will match the original value
written except for the DATA field whose contents have been replaced by the value read from the
PHY register.
If the MMFRn register is written while frame generation is in progress, the frame contents will be
altered. Software should use the MII_STATUSn register and/or the MII interrupt to avoid writing
to the MMFRn register while frame generation is in progress.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-15
Fast Ethernet Controllers (FEC0 & FEC1)
19.2.4.7 MII Speed Control Registers (MSCR0 & MSCR1)
The MSCRn provides control of the MII clock (FECn_EMDC pin) frequency and allows a
preamble drop on the MII management frame.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DIS_
PRE
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Address
MII_SPEED
0
0
0
0
0
0
0
0
IPSBAR + 0x1044 (FEC0) & IPSBAR + 0x1844 (FEC1)
Figure 19-8. MII Speed Control Register (MSCRn)
Table 19-10. MSCR Field Descriptions
Bits
Name
31–8
—
7
DIS_PRE
6–1
0
Description
Reserved, should be cleared.
Asserting this bit will cause preamble (32 1’s) not to be prepended to the MII management
frame. The MII standard allows the preamble to be dropped if the attached PHY device(s)
does not require it.
MII_SPEED MII_SPEED controls the frequency of the MII management interface clock (FECn_EMDC)
relative to the system clock. A value of 0 in this field will “turn off” the FECn_EMDC and
leave it in low voltage state. Any non-zero value will result in the FECn_EMDC frequency
of 1/(MII_SPEED × 2) of the system clock frequency.
—
Reserved, should be cleared.
The MII_SPEED field must be programmed with a value to provide an FECn_EMDC frequency
of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The
MII_SPEED must be set to a non-zero value in order to source a read or write management frame.
After the management frame is complete the MSCRn register may optionally be set to zero to turn
off the FECn_EMDC. The FECn_EMDC generated will have a 50% duty cycle except when
MII_SPEED is changed during operation (change will take effect following either a rising or
falling edge of FECn_EMDC).
If the system clock is 83 MHz, programming MII_SPEED to 0x11 will result in an FECn_EMDC
frequency of 83 MHz / (17 × 2) = 2.44 MHz. A table showing optimum values for MII_SPEED as
a function of system clock frequency is provided below.
MCF5275 Reference Manual, Rev. 2
19-16
Freescale Semiconductor
Memory Map/Register Definition
Table 19-11. Programming Examples for MSCRn
System Clock Frequency
MSCR[MII_SPEED]
FECn_EMDC frequency
25 MHz
0x5
2.5 MHz
33 MHz
0x7
2.36 MHz
40 MHz
0x8
2.5 MHz
50 MHz
0xA
2.5 MHz
66 MHz
0xE
2.36 MHz
75 MHz
0xF
2.5 MHz
83 MHz
0x11
2.44 MHz
19.2.4.8 MIB Control Registers (MIBC0 & MIBC1)
The MIBCn is a read/write register used to provide control of and to observe the state of the MIB
block. This register is accessed by user software if there is a need to disable the MIB block
operation. For example, in order to clear all MIB counters in RAM the user should disable the MIB
block, then clear all the MIB RAM locations, then enable the MIB block. The MIB_DIS bit is reset
to 1. See Table 19-3 for the locations of the MIB counters.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R MIB_ MIB_
DIS IDLE
W
Reset
R
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x1064 (FEC0) & IPSBAR + 0x1864 (FEC1)
Figure 19-9. MIB Control Register (MIBCn)
Table 19-12. MIBCn Field Descriptions
Bits
Name
Description
31
MIB_DIS
A read/write control bit. If set, the MIB logic will halt and not update any MIB counters.
30
MIB_IDLE
A read-only status bit. If set the MIB block is not currently updating any MIB counters.
29–0
—
Reserved.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-17
Fast Ethernet Controllers (FEC0 & FEC1)
19.2.4.9 Receive Control Registers (RCR0 & RCR1)
The RCRn, programmed by the user, controls the operational mode of the receive block and should
be written only when ECRn[ETHER_EN] = 0 (initialization time).
R
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
15
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
20
19
18
17
16
1
0
1
1
1
0
6
5
4
3
2
1
0
0
0
FCE
0
0
0
MAX_FL
W
Reset
R
W
Reset
Address
BC_ PROM MII_ DRT LOOP
REJ
MODE
0
0
0
0
1
IPSBAR + 0x1084 (FEC0) & IPSBAR + 0x1884 (FEC1)
Figure 19-10. Receive Control Register (RCR)
Table 19-13. RCR Field Descriptions
Bits
Name
31–27
—
26–16
MAX_FL
15–6
—
5
FCE
4
BC_REJ
3
PROM
2
Description
Reserved, should be cleared.
Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and
includes the CRC at the end of the frame. Transmit frames longer than MAX_FL will cause
the BABT interrupt to occur. Receive Frames longer than MAX_FL will cause the BABR
interrupt to occur and will set the LG bit in the end of frame receive buffer descriptor. The
recommended default value to be programmed by the user is 1518 or 1522 (if VLAN Tags
are supported).
Reserved, should be cleared.
Flow control enable. If asserted, the receiver will detect PAUSE frames. Upon PAUSE
frame detection, the transmitter will stop transmitting data frames for a given duration.
Broadcast frame reject. If asserted, frames with DA (destination address) =
FF_FF_FF_FF_FF_FF will be rejected unless the PROM bit is set. If both BC_REJ and
PROM = 1, then frames with broadcast DA will be accepted and the M (MISS) bit will be
set in the receive buffer descriptor.
Promiscuous mode. All frames are accepted regardless of address matching.
MII_MODE Media independent interface mode. Selects external interface mode. Setting this bit to one
selects MII mode, setting this bit equal to zero selects 7-wire mode (used only for serial 10
Mbps). This bit controls the interface mode for both transmit and receive blocks.
1
DRT
0
LOOP
Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor
transmit activity in half duplex mode).
1 Disable reception of frames while transmitting (normally used for half duplex mode).
Internal loopback. If set, transmitted frames are looped back internal to the device and the
transmit output signals are not asserted. The system clock is substituted for the
FECn_ETXCLK when LOOP is asserted. DRT must be set to zero when asserting LOOP.
MCF5275 Reference Manual, Rev. 2
19-18
Freescale Semiconductor
Memory Map/Register Definition
19.2.4.10 Transmit Control Registers (TCR0 & TCR1)
The TCRn is read/write and is written by the user to configure the transmit block. This register is
cleared at system reset. Bits 2 and 1 should be modified only when ECRn[ETHER_EN] = 0.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
RFC_ TFC_ FEDN HBC GTS
PAUSE PAUSE
W
Reset
Address
0
0
0
0
0
IPSBAR + 0x10C4 (FEC0) & IPSBAR + 0x18C4 (FEC1)
Figure 19-11. Transmit Control Register (TCRn)
Table 19-14. TCR Field Descriptions
Bits
Name
31–5
—
Description
Reserved, should be cleared.
4
RFC_PAUS Receive frame control pause. This read-only status bit will be asserted when a full duplex
E
flow control pause frame has been received and the transmitter is paused for the duration
defined in this pause frame. This bit will automatically clear when the pause duration is
complete.
3
TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is
set, the MAC will stop transmission of data frames after the current transmission is
complete. At this time, the GRA interrupt in the EIRn register will be asserted. With
transmission of data frames stopped, the MAC will transmit a MAC Control PAUSE frame.
Next, the MAC will clear the TFC_PAUSE bit and resume transmitting data frames. Note
that if the transmitter is paused due to user assertion of GTS or reception of a PAUSE
frame, the MAC may still transmit a MAC Control PAUSE frame.
2
FDEN
Full duplex enable. If set, frames are transmitted independent of carrier sense and
collision inputs. This bit should only be modified when ETHER_EN is deasserted.
1
HBC
Heartbeat control. If set, the heartbeat check is performed following end of transmission
and the HB bit in the status register will be set if the collision input does not assert within
the heartbeat window. This bit should only be modified when ETHER_EN is deasserted.
0
GTS
Graceful transmit stop. When this bit is set, the MAC will stop transmission after any frame
that is currently being transmitted is complete and the GRA interrupt in the EIRn register
will be asserted. If frame transmission is not currently underway, the GRA interrupt will be
asserted immediately. Once transmission has completed, a “restart” can be accomplished
by clearing the GTS bit. The next frame in the transmit FIFO will then be transmitted. If an
early collision occurs during transmission when GTS = 1, transmission will stop after the
collision. The frame will be transmitted again once GTS is cleared. Note that there may be
old frames in the transmit FIFO that will be transmitted when GTS is reasserted. To avoid
this deassert ECRn[ETHER_EN] following the GRA interrupt.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-19
Fast Ethernet Controllers (FEC0 & FEC1)
19.2.4.11 Physical Address Low Registers (PALR0 & PALR1)
The PALRn is written by the user. This register contains the lower 32 bits (bytes 0,1,2,3) of the
48-bit address used in the address recognition process to compare with the DA (Destination
Address) field of receive frames with an individual DA. In addition, this register is used in bytes
0 through 3 of the 6-byte source address field when transmitting PAUSE frames. This register is
not reset and must be initialized by the user.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
PADDR1
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
PADDR1
W
Reset
—
—
Address
—
—
—
—
—
—
—
IPSBAR + 0x10E4 (FEC0) & IPSBAR + 0x18E4 (FEC1)
Figure 19-12. Physical Address Low Register (PALRn)
Table 19-15. PALRn Field Descriptions
Bits
Name
31–0
PADDR1
Description
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual
address to be used for exact match, and the source address field in PAUSE frames.
19.2.4.12 Physical Address High Registers (PAUR0 & PAUR1)
The PAURn is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the
48-bit address used in the address recognition process to compare with the DA (destination
address) field of receive frames with an individual DA. In addition, this register is used in bytes 4
and 5 of the 6-byte Source Address field when transmitting PAUSE frames. Bits 15:0 of PAURn
contain a constant type field (0x8808) used for transmission of PAUSE frames. This register is not
reset and bits 31:16 must be initialized by the user.
MCF5275 Reference Manual, Rev. 2
19-20
Freescale Semiconductor
Memory Map/Register Definition
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
PADDR2
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
R
TYPE
W
Reset
1
0
0
0
Address
1
0
0
0
0
IPSBAR + 0x10E8 (FEC0) & IPSBAR + 0x18E8 (FEC1)
Figure 19-13. Physical Address High Register (PAURn)
Table 19-16. PAURn Field Descriptions
BIts
Name
Description
31–16
PADDR2
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for exact
match, and the Source Address field in PAUSE frames.
15–0
TYPE
Type field in PAUSE frames. These 16-bits are a constant value of 0x8808.
19.2.4.13 Opcode/Pause Duration Registers (OPD0 & OPD1)
The OPDn is read/write accessible. This register contains the 16-bit opcode and 16-bit pause
duration fields used in transmission of a PAUSE frame. The opcode field is a constant value,
0x0001. When another node detects a PAUSE frame, that node will pause transmission for the
duration specified in the pause duration field. This register is not reset and must be initialized by
the user.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
OPCODE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
PAUSE_DUR
W
Reset
—
—
Address
—
—
—
—
—
—
—
IPSBAR + 0x10EC (FEC0) & IPSBAR + 0x18EC (FEC1)
Figure 19-14. Opcode/Pause Duration Register (OPDn)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-21
Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-17. OPDn Field Descriptions
Bits
Name
31–16
OPCODE
15–0
Description
Opcode field used in PAUSE frames.
These bits are a constant, 0x0001.
PAUSE_DUR Pause Duration field used in PAUSE frames.
19.2.4.14 Descriptor Individual Upper Address Registers (IAUR0 & IAUR1)
The IAURn is written by the user. This register contains the upper 32 bits of the 64-bit individual
address hash table used in the address recognition process to check for possible match with the DA
field of receive frames with an individual DA. This register is not reset and must be initialized by
the user.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
IADDR1
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
IADDR1
W
Reset
—
—
Address
—
—
—
—
—
—
—
IPSBAR + 0x1118 (FEC0) & IPSBAR + 0x1918 (FEC1)
Figure 19-15. Descriptor Individual Upper Address Register (IAURn)
Table 19-18. IAURn Field Descriptions
Bits
Name
Descriptions
31–0
IADDR1
The upper 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0
of IADDR1 contains hash index bit 32.
19.2.4.15 Descriptor Individual Lower Address Registers (IALR0 & IALR1)
The IALRn register is written by the user. This register contains the lower 32 bits of the 64-bit
individual address hash table used in the address recognition process to check for possible match
with the DA field of receive frames with an individual DA. This register is not reset and must be
initialized by the user.
MCF5275 Reference Manual, Rev. 2
19-22
Freescale Semiconductor
Memory Map/Register Definition
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
IADDR2
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
IADDR2
W
Reset
—
—
—
—
Address
—
—
—
—
—
IPSBAR + 0x111C (FEC0) & IPSBAR + 0x191C (FEC1)
Figure 19-16. Descriptor Individual Lower Address Register (IALR)
Table 19-19. IALR Field Descriptions
Bits
Name
Description
31–0
IADDR2
The lower 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0
of IADDR2 contains hash index bit 0.
19.2.4.16 Descriptor Group Upper Address Registers (GAUR0 & GAUR1)
The GAURn is written by the user. This register contains the upper 32 bits of the 64-bit hash table
used in the address recognition process for receive frames with a multicast address. This register
must be initialized by the user.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
GADDR1
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
GADDR1
W
Reset
—
—
Address
—
—
—
—
—
—
—
IPSBAR + 0x1120 (FEC0) & IPSBAR + 0x1920 (FEC1)
Figure 19-17. Descriptor Group Upper Address Register (GAURn)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-23
Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-20. GAUR Field Descriptions
Bits
Name
31–0
GADDR1
Description
The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the
address recognition process for receive frames with a multicast address. Bit 31 of
GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
19.2.4.17 Descriptor Group Lower Address Registers (GALR0 & GALR1)
The GALRn register is written by the user. This register contains the lower 32 bits of the 64-bit
hash table used in the address recognition process for receive frames with a multicast address. This
register must be initialized by the user.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
GADDR2
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
GADDR2
W
Reset
—
—
Address
—
—
—
—
—
—
—
IPSBAR + 0x1124 (FEC0) & IPSBAR + 0x1924 (FEC1)
Figure 19-18. Descriptor Group Lower Address Register (GALRn)
Table 19-21. GALRn Field Descriptions
Bits
Name
31–0
GADDR2
Description
The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the
address recognition process for receive frames with a multicast address. Bit 31 of
GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
19.2.4.18 FIFO Transmit FIFO Watermark Registers (TFWR0 & TFWR1)
The TFWRn is a 2-bit read/write register programmed by the user to control the amount of data
required in the transmit FIFO before transmission of a frame can begin. This allows the user to
minimize transmit latency (TFWR = 0x) or allow for larger bus access latency (TFWR = 11) due
to contention for the system bus. Setting the watermark to a high value will minimize the risk of
transmit FIFO underrun due to contention for the system bus. The byte counts associated with the
TFWR field may need to be modified to match a given system requirement (worst case bus access
latency by the transmit data DMA channel).
MCF5275 Reference Manual, Rev. 2
19-24
Freescale Semiconductor
Memory Map/Register Definition
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
TFWR
W
Reset
Address
0
0
IPSBAR + 0x1144 (FEC0) & IPSBAR + 0x1944 (FEC1)
Figure 19-19. FIFO Transmit FIFO Watermark Register (TFWRn)
Table 19-22. TFWRn Field Descriptions
Bits
Name
31–2
—
1–0
TFWR
Descriptions
Reserved, should be cleared.
Number of bytes written to transmit FIFO before transmission of a frame begins
0x 64 bytes written
10 128 bytes written
11 192 bytes written
19.2.4.19 FIFO Receive Bound Registers (FRBR0 & FRBR1)
The FRBRn is an 8-bit register that the user can read to determine the upper address bound of the
FIFO RAM. Drivers can use this value, along with the FRSRn to appropriately divide the available
FIFO RAM between the transmit and receive data paths.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
W
Reset
R
R_BOUND
W
Reset
Address
1
0
0
0
0
0
0
0
IPSBAR + 0x114C (FEC0) & IPSBAR + 0x194C (FEC1)
Figure 19-20. FIFO Receive Bound Register (FRBRn)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-25
Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-23. FRBRn Field Descriptions
Bits
Name
31–10
—
9–2
Descriptions
Reserved, read as 0 (except bit 10, which is read as 1).
R_BOUND Read-only. Highest valid FIFO RAM address.
1–0
—
Reserved, should be cleared.
19.2.4.20 FIFO Receive Start Registers (FRSR0 & FRSR1)
The FRSRn is programmed by the user to indicate the starting address of the receive FIFO. FRSRn
marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses
from the start of the FIFO to the location four bytes before the address programmed into the
FRSRn. The receive FIFO uses addresses from FRSRn to FRBRn inclusive.
The FRSRn register is initialized by hardware at reset. FRSRn only needs to be written to change
the default value.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
W
Reset
R
R_FSTART
W
Reset
Address
0
1
0
0
0
0
0
0
IPSBAR + 0x1150 (FEC0) & IPSBAR + 0x1950 (FEC1)
Figure 19-21. FIFO Receive Start Register (FRSRn)
Table 19-24. FRSRn Field Descriptions
Bits
Name
31–10
—
9–2
1–0
Descriptions
Reserved, read as 0 (except bit 10, which is read as 1).
R_FSTART Address of first receive FIFO location. Acts as delimiter between receive and transmit
FIFOs.
—
Reserved, read as 0.
19.2.4.21 Receive Descriptor Ring Start Registers (ERDSR0 & ERDSR1)
The ERDSRn is written by the user. It provides a pointer to the start of the circular receive buffer
descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is
recommended it be made 128-bit aligned (evenly divisible by 16).
MCF5275 Reference Manual, Rev. 2
19-26
Freescale Semiconductor
Memory Map/Register Definition
This register is not reset and must be initialized by the user prior to operation.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
R_DES_START
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
—
—
R
R_DES_START
W
Reset
—
—
—
—
Address
—
—
—
—
—
—
—
—
—
—
IPSBAR + 0x1180 (FEC0) & IPSBAR + 0x1980 (FEC1)
Figure 19-22. Receive Descriptor Ring Start Register (ERDSRn)
Table 19-25. ERDSRn Field Descriptions
Bits
Name
31–2
R_DES_
START
1–0
—
Descriptions
Pointer to start of receive buffer descriptor queue.
Reserved, should be cleared.
19.2.4.22 Transmit Buffer Descriptor Ring Start Registers (ETSDR0 &
ETSDR1)
The ETSDRn is written by the user. It provides a pointer to the start of the circular transmit buffer
descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is
recommended it be made 128-bit aligned (evenly divisible by 16). Bits 1 and 0 should be written
to 0 by the user. Non-zero values in these two bit positions are ignored by the hardware.
This register is not reset and must be initialized by the user prior to operation.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
X_DES_START
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
—
—
R
X_DES_START
W
Reset
—
—
Address
—
—
—
—
—
—
—
—
—
—
—
—
IPSBAR + 0x1184 (FEC0) & IPSBAR + 0x1984 (FEC1)
Figure 19-23. Transmit Buffer Descriptor Ring Start Register (ETDSRn)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-27
Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-26. ETDSRn Field Descriptions
Bits
Name
31–2
X_DES_
START
1–0
—
Descriptions
Pointer to start of transmit buffer descriptor queue.
Reserved, should be cleared.
19.2.4.23 Receive Buffer Size Registers (EMRBR0 & EMRBR1)
The EMRBRn is a 9-bit register programmed by the user. The EMRBRn register dictates the
maximum size of all receive buffers. Note that because receive frames will be truncated at 2k-1
bytes, only bits 10–4 are used. This value should take into consideration that the receive CRC is
always written into the last receive buffer. To allow one maximum size frame per buffer, EMRBRn
must be set to RCRn[MAX_FL] or larger. The EMRBRn must be evenly divisible by 16. To insure
this, bits 3-0 are forced low. To minimize bus utilization (descriptor fetches) it is recommended
that EMRBRn be greater than or equal to 256 bytes.
The EMRBRn register does not reset, and must be initialized by the user.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
W
Reset
R
R_BUF_SIZE
W
Reset
Address
—
—
—
—
—
—
—
IPSBAR + 0x1188 (FEC0) & IPSBAR + 0x1988 (FEC1)
Figure 19-24. Receive Buffer Size Register (EMRBRn)
Table 19-27. EMRBRn Field Descriptions
Bits
Name
30–11
—
10–4
R_BUF_
SIZE
3–0
—
Descriptions
Reserved, should be written to 0 by the host processor.
Receive buffer size.
Reserved, should be written to 0 by the host processor.
19.2.5 Buffer Descriptors
This section provides a description of the operation of the driver/DMA via the buffer descriptors.
It is followed by a detailed description of the receive and transmit descriptor fields.
MCF5275 Reference Manual, Rev. 2
19-28
Freescale Semiconductor
Memory Map/Register Definition
19.2.5.1 Driver/DMA Operation with Buffer Descriptors
The data for the FEC frames must reside in memory external to the FEC. The data for a frame is
placed in one or more buffers. Associated with each buffer is a buffer descriptor (BD) which
contains a starting address (32-bit aligned pointer), data length, and status/control information
(which contains the current state for the buffer). To permit maximum user flexibility, the BDs are
also located in external memory and are read in by the FEC DMA engine.
Software “produces” buffers by allocating/initializing memory and initializing buffer descriptors.
Setting the RxBDn[E] or TxBDn[R] bit “produces” the buffer. Software writing to either the
TDARn or RDARn tells the FEC that a buffer has been placed in external memory for the transmit
or receive data traffic, respectively. The hardware reads the BDs and “consumes” the buffers after
they have been produced. After the data DMA is complete and the buffer descriptor status bits
have been written by the DMA engine, the RxBDn[E] or TxBDn[R] bit will be cleared by
hardware to signal the buffer has been “consumed.” Software may poll the BDs to detect when the
buffers have been consumed or may rely on the buffer/frame interrupts. These buffers may then
be processed by the driver and returned to the free list.
The ECRn[ETHER_EN] signal operates as a reset to the BD/DMA logic. When
ECRn[ETHER_EN] is deasserted the DMA engine BD pointers are reset to point to the starting
transmit and receive BDs. The buffer descriptors are not initialized by hardware during reset. At
least one transmit and receive buffer descriptor must be initialized by software before the
ECRn[ETHER_EN] bit is set.
The buffer descriptors operate as two separate rings. ERDSRn defines the starting address for
receive BDs and ETDSRn defines the starting address for transmit BDs. The last buffer descriptor
in each ring is defined by the Wrap (W) bit. When set, W indicates that the next descriptor in the
ring is at the location pointed to by ERDSRn and ETDSRn for the receive and transmit rings,
respectively. Buffer descriptor rings must start on a 32-bit boundary; however, it is recommended
they are made 128-bit aligned.
19.2.5.1.1 Driver/DMA Operation with Transmit BDs
Typically a transmit frame will be divided between multiple buffers. An example is to have an
application payload in one buffer, TCP header in a 2nd buffer, IP header in a 3rd buffer,
Ethernet/IEEE 802.3 header in a 4th buffer. The Ethernet MAC does not prepend the Ethernet
header (destination address, source address, length/type field(s)), so this must be provided by the
driver in one of the transmit buffers. The Ethernet MAC can append the Ethernet CRC to the
frame. Whether the CRC is appended by the MAC or by the driver is determined by the TC bit in
the transmit BD which must be set by the driver.
The driver (TxBD software producer) should set up Tx BDs in such a way that a complete transmit
frame is given to the hardware at once. If a transmit frame consists of three buffers, the BDs should
be initialized with pointer, length and control (W, L, TC, ABC) and then the TxBDn[R] bits should
be set = 1 in reverse order (3rd, 2nd, 1st BD) to insure that the complete frame is ready in memory
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-29
Fast Ethernet Controllers (FEC0 & FEC1)
before the DMA begins. If the TxBDs are set up in order, the DMA Controller could DMA the first
BD before the 2nd was made available, potentially causing a transmit FIFO underrun.
In the FEC, the DMA is notified by the driver that new transmit frame(s) are available by writing
to the TDARn register. When this register is written to (data value is not significant) the FEC RISC
will tell the DMA to read the next transmit BD in the ring. Once started, the RISC + DMA will
continue to read and interpret transmit BDs in order and DMA the associated buffers, until a
transmit BD is encountered with the R bit = 0. At this point the FEC will poll this BD one more
time. If the R bit = 0 the second time, then the RISC will stop the transmit descriptor read process
until software sets up another transmit frame and writes to TDARn.
When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the
R bit, indicating that the hardware consumer is finished with the buffer.
19.2.5.1.2 Driver/DMA Operation with Receive BDs
Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore
the driver must set a variable to define the length of all receive buffers. In the FEC, this variable
is written to the EMRBRn register.
The driver (RxBD software producer) should set up some number of “empty” buffers for the
Ethernet by initializing the address field and the E and W bits of the associated receive BDs. The
hardware (receive DMA) will consume these buffers by filling them with data as frames are
received and clearing the E bit and writing to the L (1 indicates last buffer in frame) bit, the frame
status bits (if L = 1) and the length field.
If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the
frame. For non-last buffers, the length field in the receive BD will be written by the DMA (at the
same time the E bit is cleared) with the default receive buffer length value. For end of frame buffers
the receive BD will be written with L = 1 and information written to the status bits (M, BC, MC,
LG, NO, CR, OV, TR). Some of the status bits are error indicators which, if set, indicate the receive
frame should be discarded and not given to higher layers. The frame status/length information is
written into the receive FIFO following the end of the frame (as a single 32-bit word) by the
receive logic. The length field for the end of frame buffer will be written with the length of the
entire frame, not just the length of the last buffer.
For simplicity the driver may assign the default receive buffer length to be large enough to contain
an entire frame, keeping in mind that a malfunction on the network or out of spec implementation
could result in giant frames. Frames of 2k (2048) bytes or larger are truncated by the FEC at 2032
bytes so software is guaranteed never to see a receive frame larger than 2032 bytes.
Similar to transmit, the FEC will poll the receive descriptor ring after the driver sets up receive
BDs and writes to the RDARn register. As frames are received the FEC will fill receive buffers
and update the associated BDs, then read the next BD in the receive descriptor ring. If the FEC
MCF5275 Reference Manual, Rev. 2
19-30
Freescale Semiconductor
Memory Map/Register Definition
reads a receive BD and finds the E bit = 0, it will poll this BD once more. If the BD = 0 a second
time the FEC will stop reading receive BDs until the driver writes to RDARn.
19.2.5.2 Ethernet Receive Buffer Descriptors (RxBD0 & RxBD1)
In the RxBD, the user initializes the E and W bits in the first longword and the pointer in second
longword. When the buffer has been DMA’d, the Ethernet controller will modify the E, L, M, BC,
MC, LG, NO, CR, OV, and TR bits and write the length of the used portion of the buffer in the first
longword. The M, BC, MC, LG, NO, CR, OV and TR bits in the first longword of the buffer
descriptor are only modified by the Ethernet controller when the L bit is set.
Offset + 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
E
RO1
W
RO2
L
—
—
M
BC
MC
LG
NO
—
CR
OV
TR
Offset + 2
Data Length
Offset + 4
Rx Data Buffer Pointer - A[31:16]
Offset + 6
Rx Data Buffer Pointer - A[15:0]
Figure 19-25. Receive Buffer Descriptor (RxBDn)
Table 19-28. Receive Buffer Descriptor Field Definitions
Word
Bits
Field Name
Description
Offset + 0
15
E
Empty. Written by the FEC (=0) and user (=1).
0 The data buffer associated with this BD has been filled with received data,
or data reception has been aborted due to an error condition. The status
and length fields have been updated as required.
1 The data buffer associated with this BD is empty, or reception is currently
in progress.
Offset + 0
14
RO1
Receive software ownership. This field is reserved for use by software. This
read/write bit will not be modified by hardware, nor will its value affect
hardware.
Offset + 0
13
W
Offset + 0
12
RO2
Offset + 0
11
L
Last in frame. Written by the FEC.
0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
Offset + 0
10–9
—
Reserved.
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ERDSR.n
Receive software ownership. This field is reserved for use by software. This
read/write bit will not be modified by hardware, nor will its value affect
hardware.
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Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-28. Receive Buffer Descriptor Field Definitions (Continued)
1
Word
Bits
Field Name
Description
Offset + 0
8
M
Miss. Written by the FEC. This bit is set by the FEC for frames that were
accepted in promiscuous mode, but were flagged as a “miss” by the internal
address recognition. Thus, while in promiscuous mode, the user can use the
M-bit to quickly determine whether the frame was destined to this station.
This bit is valid only if the L-bit is set and the PROM bit is set.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.
Offset + 0
7
BC
Will be set if the DA is broadcast (FF-FF-FF-FF-FF-FF).
Offset + 0
6
MC
Will be set if the DA is multicast and not BC.
Offset + 0
5
LG
Rx frame length violation. Written by the FEC. A frame length greater than
RCRn[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The
receive data is not altered in any way unless the length exceeds 2032 bytes.
Offset + 0
4
NO
Receive non-octet aligned frame. Written by the FEC. A frame that contained
a number of bits not divisible by 8 was received, and the CRC check that
occurred at the preceding byte boundary generated an error. This bit is valid
only if the L-bit is set. If this bit is set the CR bit will not be set.
Offset + 0
3
—
Reserved.
Offset + 0
2
CR
Receive CRC error. Written by the FEC. This frame contains a CRC error
and is an integral number of octets in length. This bit is valid only if the L-bit
is set.
Offset + 0
1
OV
Overrun. Written by the FEC. A receive FIFO overrun occurred during frame
reception. If this bit is set, the other status bits, M, LG, NO, CR, and CL lose
their normal meaning and will be zero. This bit is valid only if the L-bit is set.
Offset + 0
0
TR
Will be set if the receive frame is truncated (frame length > 2032 bytes). If
the TR bit is set the frame should be discarded and the other error bits should
be ignored as they may be incorrect.
Offset + 2
15–0
Data
Length
Data length. Written by the FEC. Data length is the number of octets written
by the FEC into this BD’s data buffer if L = 0 (the value will be equal to
EMRBR), or the length of the frame including CRC if L = 1. It is written by the
FEC once as the BD is closed.
0ffset + 4
15–0
A[31:16]
RX data buffer pointer, bits [31:16]1
Offset + 6
15–0
A[15:0]
RX data buffer pointer, bits [15:0]
The receive buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible
by 16. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
NOTE
Whenever the software driver sets an E bit in one or more receive
descriptors, the driver should follow that with a write to RDAR.n
19.2.5.3 Ethernet Transmit Buffer Descriptors (TxBD0 & TxBD1)
Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s
TxBDs. The Ethernet controller confirms transmission by clearing the ready bit (R bit) when
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Freescale Semiconductor
Memory Map/Register Definition
DMA of the buffer is complete. In the TxBD the user initializes the R, W, L, and TC bits and the
length (in bytes) in the first longword, and the buffer pointer in the second longword.
The FEC will set the R bit = 0 in the first longword of the BD when the buffer has been DMA’d.
Status bits for the buffer/frame are not included in the transmit buffer descriptors. Transmit frame
status is indicated via individual interrupt bits (error conditions) and in statistic counters in the
MIB block. See Section 19.2.3, “MIB Block Counters Memory Map” for more details.
Offset + 0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
TO1
W
TO2
L
TC
ABC
—
—
—
—
—
—
—
—
—
Offset + 2
Data Length
Offset + 4
Tx Data Buffer Pointer - A[31:16]
Offset + 6
Tx Data Buffer Pointer - A[15:0]
Figure 19-26. Transmit Buffer Descriptor (TxBDn)
Table 19-29. Transmit Buffer Descriptor Field Definitions
Word
Bits
Field Name
Description
Offset + 0
15
R
Ready. Written by the FEC and the user.
0 The data buffer associated with this BD is not ready for transmission. The
user is free to manipulate this BD or its associated data buffer. The FEC
clears this bit after the buffer has been transmitted or after an error
condition is encountered.
1 The data buffer, which has been prepared for transmission by the user, has
not been transmitted or is currently being transmitted. No fields of this BD
may be written by the user once this bit is set.
Offset + 0
14
TO1
Transmit software ownership. This field is reserved for software use. This
read/write bit will not be modified by hardware, nor will its value affect
hardware.
Offset + 0
13
W
Wrap. Written by user.
0 The next buffer descriptor is found in the consecutive location
1 The next buffer descriptor is found at the location defined in ETDSR.n
Offset + 0
12
TO2
Offset + 0
11
L
Offset + 0
10
TC
Offset + 0
9
ABC
Offset + 0
8–0
—
Transmit software ownership. This field is reserved for use by software. This
read/write bit will not be modified by hardware, nor will its value affect
hardware.
Last in frame. Written by user.
0 The buffer is not the last in the transmit frame.
1 The buffer is the last in the transmit frame.
Tx CRC. Written by user (only valid if L = 1).
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
Append bad CRC. Written by user (only valid if L = 1).
0 No effect
1 Transmit the CRC sequence inverted after the last data byte (regardless of
TC value).
Reserved.
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Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-29. Transmit Buffer Descriptor Field Definitions (Continued)
1
Word
Bits
Field Name
Description
Offset + 2
15–0
Data
Length
Data Length, written by user.
Data length is the number of octets the FEC should transmit from this BD’s
data buffer. It is never modified by the FEC. Bits [15:5] are used by the DMA
engine, bits[4:0] are ignored.
Offset + 4
15–0
A[31:16]
Tx data buffer pointer, bits [31:16]1
Offset + 6
15–0
A[15:0]
Tx data buffer pointer, bits [15:0].
The transmit buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible
by 4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
NOTE
Once the software driver has set up the buffers for a frame, it should
set up the corresponding BDs. The last step in setting up the BDs for
a transmit frame should be to set the R bit in the first BD for the frame.
The driver should follow that with a write to TDARn which will
trigger the FEC to poll the next BD in the ring.
19.3
Functional Description
This section describes the operation of the FECs, beginning with the hardware and software
initialization sequence, then the software (Ethernet driver) interface for transmitting and receiving
frames.
Following the software initialization and operation sections are sections providing a detailed
description of the functions of the FECs.
19.3.1 Initialization Sequence
This section describes which registers are reset due to hardware reset, which are reset by the FEC
RISC, and what locations the user must initialize prior to enabling the FECs.
19.3.1.1 Hardware Controlled Initialization
In the FEC, registers and control logic that generate interrupts are reset by hardware. A hardware
reset deasserts output signals and resets general configuration bits.
Other registers reset when the ECRn[ETHER_EN] bit is cleared. ECRn[ETHER_EN] is
deasserted by a hard reset or may be deasserted by software to halt operation. By deasserting
ECRn[ETHER_EN], the configuration control registers such as the TCRn and RCRn will not be
reset, but the entire data path will be reset.
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Functional Description
Table 19-30. ECRn[ETHER_EN] De-Assertion Effect on FEC
Register/Machine
Reset Value
XMIT block
Transmission is aborted (bad CRC
appended)
RECV block
Receive activity is aborted
DMA block
All DMA activity is terminated
RDARn
Cleared
TDARn
Cleared
Descriptor Controller block
Halt operation
19.3.2 User Initialization (Prior to Setting ECRn[ETHER_EN])
The user needs to initialize portions the FEC prior to setting the ECRn[ETHER_EN] bit. The exact
values will depend on the particular application. The sequence is not important.
Ethernet MAC registers requiring initialization are defined in Table 19-31.
Table 19-31. User Initialization (Before ECRn[ETHER_EN])
Description
Initialize EIMRn
Clear EIRn (write 0xFFFF_FFFF)
TFWRn (optional)
IALRn / IAURn
GAURn / GALRn
PALRn / PAURn (only needed for full duplex flow control)
OPDn (only needed for full duplex flow control)
RCRn
TCRn
MSCRn (optional)
Clear MIB_RAMn (locations IPSBAR + 0x1200-0x12FC
& IPSBAR + 0x2000-0x20FC)
FEC FIFO/DMA registers that require initialization are defined in Table 19-32.
Table 19-32. FEC User Initialization (Before ECR[ETHER_EN])
Description
Initialize FRSRn (optional)
Initialize EMRBRn
Initialize ERDSRn
Initialize ETDSRn
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Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-32. FEC User Initialization (Before ECR[ETHER_EN]) (Continued)
Description
Initialize (Empty) Transmit Descriptor ring
Initialize (Empty) Receive Descriptor ring
19.3.3 Microcontroller Initialization
In the FEC, the descriptor control RISC initializes some registers after ECRn[ETHER_EN] is
asserted. After the microcontroller initialization sequence is complete, the hardware is ready for
operation.
Table 19-33 shows microcontroller initialization operations.
Table 19-33. Microcontroller Initialization
Description
Initialize BackOff Random Number Seed
Activate Receiver
Activate Transmitter
Clear Transmit FIFO
Clear Receive FIFO
Initialize Transmit Ring Pointer
Initialize Receive Ring Pointer
Initialize FIFO Count Registers
19.3.4 User Initialization (After Asserting ECRn[ETHER_EN])
After asserting ECRn[ETHER_EN], the user can set up the buffer/frame descriptors and write to
the TDARn and RDARn. Refer to Section 19.2.5, “Buffer Descriptors” for more details.
19.3.5 Network Interface Options
The FECs support both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for
10 Mbps Ethernet. The interface mode is selected by the RCRn[MII_MODE] bit. In MII mode
(RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE 802.3 standard and supported
by the EMAC. These signals are shown in Table 19-34 below.
Table 19-34. MII Mode
Signal Description
EMAC pin
Transmit Clock
FECn_ETXCLK
Transmit Enable
FECn_ETXEN
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Functional Description
Table 19-34. MII Mode (Continued)
Signal Description
EMAC pin
Transmit Data
FECn_ETXD[3:0]
Transmit Error
FECn_ETXER
Collision
FECn_ECOL
Carrier Sense
FECn_ECRS
Receive Clock
FECn_ERXCLK
Receive Data Valid
FECn_ERXDV
Receive Data
FECn_ERXD[3:0]
Receive Error
FECn_ERXER
Management Data Clock
FECn_EMDC
Management Data
Input/Output
FECn_EMDIO
The 7-wire serial mode interface (RCRn[MII_MODE] = 0) operates in what is generally referred
to as the “AMD” mode. 7-wire mode connections to the external transceiver are shown in
Table 19-35.
Table 19-35. 7-Wire Mode Configuration
SIGNAL DESCRIPTION
EMAC PIN
Transmit Clock
FECn_ETXCLK
Transmit Enable
FECn_ETXEN
Transmit Data
FECn_ETXD[0]
Collision
FECn_ECOL
Receive Clock
FECn_ERXCLK
Receive Data Valid
FECn_ERXDV
Receive Data
FECn_ERXD[0]
19.3.6 FEC Frame Transmission
The Ethernet transmitter is designed to work with almost no intervention from software. Once
ECRn[ETHER_EN] is asserted and data appears in the transmit FIFO, the Ethernet MAC is able
to transmit onto the network.
When the transmit FIFO fills to the watermark (defined by the TFWRn), the MAC transmit logic
will assert FECn_ETXEN and start transmitting the preamble (PA) sequence, the start frame
delimiter (SFD), and then the frame information from the FIFO. However, the controller defers the
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Fast Ethernet Controllers (FEC0 & FEC1)
transmission if the network is busy (FECn_ECRS asserts). Before transmitting, the controller
waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit
times. If so, the transmission begins after waiting an additional 36 bit times (96 bit times after
carrier sense originally became inactive). See Section 19.3.14.1, “ Transmission Errors” for more
details.
If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller
follows the specified backoff procedures and attempts to retransmit the frame until the retry limit
is reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so that they
do not have to be retrieved from system memory in case of a collision. This improves bus
utilization and latency in case immediate retransmission is necessary.
When all the frame data has been transmitted, the FCS (Frame Check Sequence or 32-bit Cyclic
Redundancy Check, CRC) bytes are appended if the TC bit is set in the transmit frame control
word. If the ABC bit is set in the transmit frame control word, a bad CRC will be appended to the
frame data regardless of the TC bit value. Following the transmission of the CRC, the Ethernet
controller writes the frame status information to the MIB block. Short frames are automatically
padded by the transmit logic (if the TC bit in the transmit buffer descriptor for the end of frame
buffer = 1).
Both buffer (TXB) and frame (TFINT) interrupts may be generated as determined by the settings
in the EIMRn.
The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and
XFIFO_UN. If the transmit frame length exceeds MAX_FL bytes the BABT interrupt will be
asserted, however the entire frame will be transmitted (no truncation).
To pause transmission, set the GTS (graceful transmit stop) bit in the TCRn register. When the
TCRn[GTS] is set, the FEC transmitter stops immediately if transmission is not in progress;
otherwise, it continues transmission until the current frame either finishes or terminates with a
collision. After the transmitter has stopped the GRA (graceful stop complete) interrupt is asserted.
If TCRn[GTS] is cleared, the FEC resumes transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
19.3.7 FEC Frame Reception
The FEC receivers are designed to work with almost no intervention from the host and can perform
address recognition, CRC checking, short frame checking, and maximum frame length checking.
When the driver enables the FEC receiver by setting ECRn[ETHER_EN], it will immediately start
processing receive frames. When FECn_ERXDV is asserted, the receiver will first check for a
valid PA/SFD header. If the PA/SFD is valid, it will be stripped and the frame will be processed
by the receiver. If a valid PA/SFD is not found, the frame will be ignored.
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Functional Description
In serial mode, the first 16 bit times of RX_D0 following assertion of FECn_ERXDV are ignored.
Following the first 16 bit times the data sequence is checked for alternating 1/0s. If a 11 or 00 data
sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time
21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected.
When a 11 is detected, the PA/SFD sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes
may occur, but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on
the frame.
Once a collision window (64 bytes) of data has been received and if address recognition has not
rejected the frame, the receive FIFO is signalled that the frame is “accepted” and may be passed
on to the DMA. If the frame is a runt (due to collision) or is rejected by address recognition, the
receive FIFO is notified to “reject” the frame. Thus, no collision fragments are presented to the
user except late collisions, which indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and once the entire
frame is written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word
contains the M, BC, MC, LG, NO, CR, OV and TR status bits, and the frame length. See
Section 19.3.14.2, “ Reception Errors” for more details.
Receive Buffer (RXB) and Frame Interrupts (RFINT) may be generated if enabled by the EIMRn
register. A receive error interrupt is babbling receiver error (BABR). Receive frames are not
truncated if they exceed the max frame length (MAX_FL); however, the BABR interrupt will
occur and the LG bit in the Receive Buffer Descriptor (RxBDn) will be set. See Section 19.2.5.2,
“Ethernet Receive Buffer Descriptors (RxBD0 & RxBD1)” for more details.
When the receive frame is complete, the FEC sets the L-bit in the RxBDn, writes the other frame
status bits into the RxBDn, and clears the E-bit. The Ethernet controller next generates a maskable
interrupt (RFINT bit in EIRn, maskable by RFIEN bit in EIMRn), indicating that a frame has been
received and is in memory. The Ethernet controller then waits for a new frame.
The Ethernet controller receives serial data lsb first.
19.3.8 Ethernet Address Recognition
The FECs filter the received frames based on destination address (DA) type — individual
(unicast), group (multicast), or broadcast (all-ones group address). The difference between an
individual address and a group address is determined by the I/G bit in the destination address field.
A flowchart for address recognition on received frames is illustrated in the figures below.
Address recognition is accomplished through the use of the receive block and microcode running
on the microcontroller. The flowchart shown in Figure 19-27 illustrates the address recognition
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Fast Ethernet Controllers (FEC0 & FEC1)
decisions made by the receive block, while Figure 19-28 illustrates the decisions made by the
microcontroller.
If the DA is a broadcast address and broadcast reject (RCRn[BC_REJ]) is deasserted, then the
frame will be accepted unconditionally, as shown in Figure 19-27. Otherwise, if the DA is not a
broadcast address, then the microcontroller runs the address recognition subroutine, as shown in
Figure 19-28.
If the DA is a group (multicast) address and flow control is disabled, then the microcontroller will
perform a group hash table lookup using the 64-entry hash table programmed in GAURn and
GALRn. If a hash match occurs, the receiver accepts the frame.
If flow control is enabled, the microcontroller will do an exact address match check between the
DA and the designated PAUSE DA (01:80:C2:00:00:01). If the receive block determines that the
received frame is a valid PAUSE frame, then the frame will be rejected. Note the receiver will
detect a PAUSE frame with the DA field set to either the designated PAUSE DA or the unicast
physical address.
If the DA is the individual (unicast) address, the microcontroller performs an individual exact
match comparison between the DA and 48-bit physical address that the user programs in the
PALRn and PAURn registers. If an exact match occurs, the frame is accepted; otherwise, the
microcontroller does an individual hash table lookup using the 64-entry hash table programmed in
registers, IAURn and IALRn. In the case of an individual hash match, the frame is accepted.
Again, the receiver will accept or reject the frame based on PAUSE frame detection, shown in
Figure 19-27.
If neither a hash match (group or individual), nor an exact match (group or individual) occur, then
if promiscuous mode is enabled (RCRn[PROM] = 1), then the frame will be accepted and the
MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected.
Similarly, if the DA is a broadcast address, broadcast reject (RCRn[BC_REJ]) is asserted, and
promiscuous mode is enabled, then the frame will be accepted and the MISS bit in the receive
buffer descriptor is set; otherwise, the frame will be rejected.
In general, when a frame is rejected, it is flushed from the FIFO.
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Functional Description
Accept/Reject
Frame
True
Broadcast Addr
?
False
Receive
Address
Recognition
False
Receive Frame
Set BC bit in RCV BD
True
Hash Match
?
BC_REJ = 1
?
False
True
Receive Frame
Set MC bit in RCV BD if multicast
Exact Match
?
True
False
Pause Frame True
?
False
PROM = 1
?
Reject Frame
Flush from FIFO
True
Receive Frame
Set M (Miss) bit in Rcv BD
Set MC bit in Rcv BD if multicast
Set BC bit in Rcv BD if broadcast
False
Reject Frame
Flush from FIFO
Receive Frame
NOTES:
BC_REJ - field in RCR register (BroadCast REJect)
PROM - field in RCR register (PROMiscous mode)
Pause Frame - valid PAUSE frame received
Figure 19-27. Ethernet Address Recognition—Receive Block Decisions
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Fast Ethernet Controllers (FEC0 & FEC1)
Receive Address
Recognition
Group
False
False
Pause Address
?
False
Exact Match
?
Hash Search
Individual Table
Receive Frame
True
True
Receive Frame
Reject Frame
Flush from FIFO
True
True
Receive Frame
Hash Search
Group Table
Match
?
Individual
True
FCE
?
False
I/G Address
?
Match
?
False
Receive Frame
Reject Frame
Flush from FIFO
NOTES:
FCE - field in RCR register (Flow Control Enable)
I/G - Individual/Group bit in Destination Address (least significant bit in first byte received in MAC frame)
Figure 19-28. Ethernet Address Recognition—Microcode Decisions
19.3.9 Hash Algorithm
The hash table algorithm used in the group and individual hash filtering operates as follows. The
48-bit destination address is mapped into one of 64 bits, which are represented by 64 bits stored
in GAURn, GALRn (group address hash match) or IAURn, IALRn (individual address hash
match). This mapping is performed by passing the 48-bit address through the on-chip 32-bit CRC
generator and selecting the 6 most significant bits of the CRC-encoded result to generate a number
between 0 and 63. The msb of the CRC result selects GAURn (msb = 1) or GALRn (msb = 0). The
least significant 5 bits of the hash result select the bit within the selected register. If the CRC
generator selects a bit that is set in the hash table, the frame is accepted; otherwise, it is rejected.
For example, if eight group addresses are stored in the hash table and random group addresses are
received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from
reaching memory. Those that do reach memory must be further filtered by the processor to
determine if they truly contain one of the eight desired addresses.
The effectiveness of the hash table declines as the number of addresses increases.
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Functional Description
The hash table registers must be initialized by the user. The CRC32 polynomial to use in
computing the hash is:
X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1
A table of example Destination Addresses and corresponding hash values is included below for
reference.
Table 19-36. Destination Address to 6-Bit Hash
48-bit DA
6-bit Hash (in
hex)
Hash Decimal
Value
65:ff:ff:ff:ff:ff
0x0
0
55:ff:ff:ff:ff:ff
0x1
1
15:ff:ff:ff:ff:ff
0x2
2
35:ff:ff:ff:ff:ff
0x3
3
b5:ff:ff:ff:ff:ff
0x4
4
95:ff:ff:ff:ff:ff
0x5
5
d5:ff:ff:ff:ff:ff
0x6
6
f5:ff:ff:ff:ff:ff
0x7
7
db:ff:ff:ff:ff:ff
0x8
8
fb:ff:ff:ff:ff:ff
0x9
9
bb:ff:ff:ff:ff:ff
0xa
10
8b:ff:ff:ff:ff:ff
0xb
11
0b:ff:ff:ff:ff:ff
0xc
12
3b:ff:ff:ff:ff:ff
0xd
13
7b:ff:ff:ff:ff:ff
0xe
14
5b:ff:ff:ff:ff:ff
0xf
15
27:ff:ff:ff:ff:ff
0x10
16
07:ff:ff:ff:ff:ff
0x11
17
57:ff:ff:ff:ff:ff
0x12
18
77:ff:ff:ff:ff:ff
0x13
19
f7:ff:ff:ff:ff:ff
0x14
20
c7:ff:ff:ff:ff:ff
0x15
21
97:ff:ff:ff:ff:ff
0x16
22
a7:ff:ff:ff:ff:ff
0x17
23
99:ff:ff:ff:ff:ff
0x18
24
b9:ff:ff:ff:ff:ff
0x19
25
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Fast Ethernet Controllers (FEC0 & FEC1)
Table 19-36. Destination Address to 6-Bit Hash (Continued)
48-bit DA
6-bit Hash (in
hex)
Hash Decimal
Value
f9:ff:ff:ff:ff:ff
0x1a
26
c9:ff:ff:ff:ff:ff
0x1b
27
59:ff:ff:ff:ff:ff
0x1c
28
79:ff:ff:ff:ff:ff
0x1d
29
29:ff:ff:ff:ff:ff
0x1e
30
19:ff:ff:ff:ff:ff
0x1f
31
d1:ff:ff:ff:ff:ff
0x20
32
f1:ff:ff:ff:ff:ff
0x21
33
b1:ff:ff:ff:ff:ff
0x22
34
91:ff:ff:ff:ff:ff
0x23
35
11:ff:ff:ff:ff:ff
0x24
36
31:ff:ff:ff:ff:ff
0x25
37
71:ff:ff:ff:ff:ff
0x26
38
51:ff:ff:ff:ff:ff
0x27
39
7f:ff:ff:ff:ff:ff
0x28
40
4f:ff:ff:ff:ff:ff
0x29
41
1f:ff:ff:ff:ff:ff
0x2a
42
3f:ff:ff:ff:ff:ff
0x2b
43
bf:ff:ff:ff:ff:ff
0x2c
44
9f:ff:ff:ff:ff:ff
0x2d
45
df:ff:ff:ff:ff:ff
0x2e
46
ef:ff:ff:ff:ff:ff
0x2f
47
93:ff:ff:ff:ff:ff
0x30
48
b3:ff:ff:ff:ff:ff
0x31
49
f3:ff:ff:ff:ff:ff
0x32
50
d3:ff:ff:ff:ff:ff
0x33
51
53:ff:ff:ff:ff:ff
0x34
52
73:ff:ff:ff:ff:ff
0x35
53
23:ff:ff:ff:ff:ff
0x36
54
13:ff:ff:ff:ff:ff
0x37
55
3d:ff:ff:ff:ff:ff
0x38
56
0d:ff:ff:ff:ff:ff
0x39
57
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Freescale Semiconductor
Functional Description
Table 19-36. Destination Address to 6-Bit Hash (Continued)
48-bit DA
6-bit Hash (in
hex)
Hash Decimal
Value
5d:ff:ff:ff:ff:ff
0x3a
58
7d:ff:ff:ff:ff:ff
0x3b
59
fd:ff:ff:ff:ff:ff
0x3c
60
dd:ff:ff:ff:ff:ff
0x3d
61
9d:ff:ff:ff:ff:ff
0x3e
62
bd:ff:ff:ff:ff:ff
0x3f
63
19.3.10 Full Duplex Flow Control
Full-duplex flow control allows the user to transmit pause frames and to detect received pause
frames. Upon detection of a pause frame, MAC data frame transmission stops for a given pause
duration.
To enable pause frame detection, the FEC must operate in full-duplex mode (TCRn[FDEN]
asserted) and flow control enable (RCRn[FCE]) must be asserted. The FEC detects a pause frame
when the fields of the incoming frame match the pause frame specifications, as shown in the table
below. In addition, the receive status associated with the frame should indicate that the frame is
valid.
Table 19-37. PAUSE Frame Field Specification
48-bit Destination Address
0x0180_c200_0001 or Physical Address
48-bit Source Address
Any
16-bit Type
0x8808
16-bit Opcode
0x0001
16-bit PAUSE Duration
0x0000–0xFFFF
Pause frame detection is performed by the receiver and microcontroller modules. The
microcontroller runs an address recognition subroutine to detect the specified pause frame
destination address, while the receiver detects the type and opcode pause frame fields. On
detection of a pause frame, TCRn[GTS] is set by the FEC internally. When transmission has
paused, the EIRn[GRA] interrupt is asserted and the pause timer begins to increment. Note that
the pause timer makes use of the transmit backoff timer hardware, which is used for tracking the
appropriate collision backoff time in half-duplex mode. The pause timer increments once every
slot time, until OPDn[PAUSE_DUR] slot times have expired. On OPDn[PAUSE_DUR]
expiration, TCRn[GTS] is deasserted allowing MAC data frame transmission to resume. Note that
the receive flow control pause (TCRn[RFC_PAUSE]) status bit is set while the transmitter is
paused due to reception of a pause frame.
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Freescale Semiconductor
19-45
Fast Ethernet Controllers (FEC0 & FEC1)
To transmit a pause frame, the FEC must operate in full-duplex mode and the user must assert flow
control pause (TCRn[TFC_PAUSE]). On assertion of transmit flow control pause
(TCRn[TFC_PAUSE]), the transmitter sets TCRn[GTS] internally. When the transmission of data
frames stops, the EIRn[GRA] (graceful stop complete) interrupt asserts. Following EIRn[GRA]
assertion, the pause frame is transmitted. On completion of pause frame transmission, flow control
pause (TCRn[TFC_PAUSE]) and TCRn[GTS] are cleared internally.
The user must specify the desired pause duration in the OPDn register.
Note that when the transmitter is paused due to receiver/microcontroller pause frame detection,
transmit flow control pause (TCRn[TFC_PAUSE]) still may be asserted and will cause the
transmission of a single pause frame. In this case, the EIRn[GRA] interrupt will not be asserted.
19.3.11 Inter-Packet Gap (IPG) Time
The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After
completing a transmission or after the backoff algorithm completes, the transmitter waits for
carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may
begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. If carrier
sense asserts during the last 36 bit times, it will be ignored and a collision will occur.
The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an
inter-packet gap between receive frames is less than 28 bit times, the following frame may be
discarded by the receiver.
19.3.12 Collision Handling
If a collision occurs during frame transmission, the Ethernet controller will continue the
transmission for at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the
collision occurs during the preamble sequence, the JAM pattern will be sent after the end of the
preamble sequence.
If a collision occurs within 512 bit times, the retry process is initiated. The transmitter waits a
random number of slot times. A slot time is 512 bit times. If a collision occurs after 512 bit times,
then no retransmission is performed and the end of frame buffer is closed with a Late Collision
(LC) error indication.
19.3.13 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback mode,
both of the FIFOs are used and the FEC actually operates in a full-duplex fashion. Both internal
and external loopback are configured using combinations of the LOOP and DRT bits in the RCRn
register and the FDEN bit in the TCRn register.
For both internal and external loopback set FDEN = 1.
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Freescale Semiconductor
Functional Description
For internal loopback set RCRn[LOOP] = 1 and RCRn[DRT] = 0. FECn_ETXEN and
FECn_ETXER will not assert during internal loopback. During internal loopback, the
transmit/receive data rate is higher than in normal operation because the internal system clock is
used by the transmit and receive blocks instead of the clocks from the external transceiver. This
will cause an increase in the required system bus bandwidth for transmit and receive data being
DMA’d to/from external memory. It may be necessary to pace the frames on the transmit side
and/or limit the size of the frames to prevent transmit FIFO underrun and receive FIFO overflow.
For external loopback set RCRn[LOOP] = 0, RCRn[DRT] = 0 and configure the external
transceiver for loopback.
19.3.14 Ethernet Error-Handling Procedure
The Ethernet controller reports frame reception and transmission error conditions using the FEC
RxBDs, the EIRn register, and the MIB block counters.
19.3.14.1 Transmission Errors
19.3.14.1.1 Transmitter Underrun
If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All
remaining buffers for that frame are then flushed and closed. The UN bit is set in the EIRn. The
FEC will then continue to the next transmit buffer descriptor and begin transmitting the next
frame.
The “UN” interrupt will be asserted if enabled in the EIMRn register.
19.3.14.1.2 Retransmission Attempts Limit Expired
When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are
flushed and closed, and the RL bit is set in the EIRn. The FEC will then continue to the next
transmit buffer descriptor and begin transmitting the next frame.
The “RL” interrupt will be asserted if enabled in the EIMRn register.
19.3.14.1.3 Late Collision
When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates
transmission. All remaining buffers for that frame are flushed and closed, and the LC bit is set in
the EIRn register. The FEC will then continue to the next transmit buffer descriptor and begin
transmitting the next frame.
The “LC” interrupt will be asserted if enabled in the EIMRn register.
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Freescale Semiconductor
19-47
Fast Ethernet Controllers (FEC0 & FEC1)
19.3.14.1.4 Heartbeat
Some transceivers have a self-test feature called “heartbeat” or “signal quality error.” To signify a
good self-test, the transceiver indicates a collision to the FEC within 4 microseconds after
completion of a frame transmitted by the Ethernet controller. This indication of a collision does
not imply a real collision error on the network, but is rather an indication that the transceiver still
seems to be functioning properly. This is called the heartbeat condition.
If the HBC bit is set in the TCRn register and the heartbeat condition is not detected by the FEC
after a frame transmission, then a heartbeat error occurs. When this error occurs, the FEC closes
the buffer, sets the HB bit in the EIRn register, and generates the HBERR interrupt if it is enabled.
19.3.14.2 Reception Errors
19.3.14.2.1Overrun Error
If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets
the OV bit in the RxBDn. All subsequent data in the frame will be discarded and subsequent
frames may also be discarded until the receive FIFO is serviced by the DMA and space is made
available. At this point the receive frame/status word is written into the FIFO with the OV bit set.
This frame must be discarded by the driver.
19.3.14.2.2Non-Octet Error (Dribbling Bits)
The Ethernet controller handles up to seven dribbling bits when the receive frame terminates past
an non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a
CRC error, then the frame non-octet aligned (NO) error is reported in the RxBDn. If there is no
CRC error, then no error is reported.
19.3.14.2.3CRC Error
When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in the
RxBDn. CRC checking cannot be disabled, but the CRC error can be ignored if checking is not
required.
19.3.14.2.4Frame Length Violation
When the receive frame length exceeds MAX_FL bytes the BABR interrupt will be generated, and
the LG bit in the end of frame RxBDn will be set. The frame is not truncated unless the frame
length exceeds 2032 bytes).
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Freescale Semiconductor
Functional Description
19.3.14.2.5Truncation
When the receive frame length exceeds 2032 bytes the frame is truncated and the TR bit is set in
the receive BD.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
19-49
Fast Ethernet Controllers (FEC0 & FEC1)
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
Chapter 20
Universal Serial Bus
20.1
Introduction
This chapter provides an overview of the universal serial bus (USB) device controller module of
the MCF5275. The USB Specification, Revision 2.0 is a recommended supplement to this chapter.
Unless otherwise stated, all mention of the USB specification refers to revision 2.0 It can be
downloaded from http://www.usb.org. Chapter 2 of this specification, Terms and Abbreviations,
provides definitions of many of the terms found here.
20.1.1 Block Diagram
A block diagram of the complete USB device is shown in Figure 20-1.
USB Device
FIFO Controller
Internal Bus
Interface
Descriptor RAM
1024 x 8
USB_CLK
FIFO RAM
USB_RN & USB_RP
USB_RXD
Partitioned
for each
USB Control Logic
endpoint
USB_TN & USB_TP
USB_TXEN
USB_SUSP
Figure 20-1. USB Device Block Diagram
20.1.2 Overview
The universal serial bus specification describes three types of devices that can connect to the bus.
The USB host is the bus master, and periodically polls peripherals to initiate data transfers. There
is only one host on the bus. The USB function (or USB device) is a bus slave. It can communicate
only with a USB host. It does not generate bus traffic and only responds to requests from the host.
A USB hub is a special class of USB function that adds additional connection points to the bus for
more USB devices.
The USB device operates under the control of the CPU through the internal peripheral bus. From
the user’s perspective, this device hides all direct interaction with the USB protocol. The registers
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
20-1
Universal Serial Bus
allow the user to enable or disable the device, control characteristics of individual endpoints, and
monitor traffic flow through the device without ever seeing the low-level details of the USB
protocol.
While this device hides all direct interaction with the protocol, some knowledge of the USB is
required in order to properly configure the device for operation on the bus. This document covers
programming requirements. Additional information may be found in the USB specification.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module”) prior to configuring the USB module.
20.1.3 Features
The USB device provides the following USB features to the user:
•
•
•
Supports full speed 12-Mbps and low speed 1.5-Mbps USB operation
Compliant with Universal Serial Bus Specification, Revision 2.0
Supports up to four endpoints. Endpoint 0 is required by the USB specification, but all
others are optional. Endpoint configurations as shown in Table 20-1.
Table 20-1. Endpoint Configurations
Endpoint
Type
FIFO Size
Data Transfer
Comments
0
IN
Variable
Control
Mandatory
OUT
Variable
IN or OUT
Variable
1-3
•
•
•
•
•
Mandatory
Ctrl, Int, Bulk, or Iso
Optional
USB descriptors are stored in a dedicated 1-Kbyte descriptor RAM. The RAM is accessible
from the internal peripheral bus via registers within this device.
One FIFO RAM per USB endpoint. FIFO controllers share a 2-Kbyte RAM made of four
contiguous 512-byte RAM’s. User programmable registers allow on-the-fly configuration
of individual FIFO sizes.
Isochronous communications pipes are supported. A frame match interrupt feature is
supported in order to notify the user when a specific USB frame occurs.
Remote wake-up feature is supported via a register bit.
Self powered
20.1.4 Modes of Operation
This device provides two modes of operation to the user:
MCF5275 Reference Manual, Rev. 2
20-2
Freescale Semiconductor
External Signal Description
•
•
20.2
USB disabled: In this mode, the USB device’s datapath will not accept transactions
received on the USB. The user has read/write access to the descriptor RAM.
USB enabled: In this mode, the USB device’s datapath is enabled to accept transactions
received on the USB. The user does not have read/write access to the descriptor RAM.
External Signal Description
The external interface of the device consists of the signals that connect off-chip. The external
interface is described in Table 20-2.
Table 20-2. USB Signals
Name
Direction
Function
Reset State 1
USB_CLK
I
48 Mhz 2 (or 6 Mhz) clock used to derive
12 MHz (or 1.5 MHz) USB bit clock.
—
USB_SPEED
O
Signals between full or low speed.
Asserted
USB_RN
I
Half of differential received USB signal.
—
USB_RP
I
Half of differential received USB signal.
—
USB_RXD
I
Input data from differential input receiver.
—
USB_TN
O
Half of differential output.
Tri-state
USB_TP
O
Half of differential output.
Tri-state
USB_TXEN
O
Output enable.
Deasserted
USB_SUSP
O
Force transceiver into low power state.
Deasserted
1
The default reset state of these pins is GPIO. See Chapter 12, “General Purpose I/O Module” for
more information.
2 Specific clock requirements are set forth in the Universal Serial Bus Specification, Revision 2.0,
Chapter 7 "Electrical Specification."
20.2.1 USB Clock (USB_CLK)
The 48 Mhz clock is used by the USB device for both clock recovery and generation of a 12 Mhz
internal bit clock.
20.2.2 USB Speed (USB_SPEED)
Applications which make use of low speed USB signalling must be able to switch the USB
transceiver between low speed and full speed operations. Software has control of this function by
driving the state of the USB_SPD bit in the USB_CR register onto the USB_SPEED pin.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
20-3
Universal Serial Bus
20.2.3 USB Negative/Positive Receive Signal Inputs (USB_RN &
USB_RP)
These signals are each one half of the differential USB signal, and is extracted from the USB cable
via a single ended input buffer on the external PHY. This signal is used by the module for detecting
the single ended 0 (SE0) USB bus state.
20.2.4 USB Receive Data (USB_RXD)
Input data from the differential input receiver. USB_RXD is the single-ended data extracted from
the USB_RP and USB_RN signals via a differential input buffer.
20.2.5 USB Suspended (USB_SUSP)
After a long period of inactivity (6.0 ms minimum), the USB will enter suspend mode, indicated
on the interface by an active state on USB_SUSP. During this mode, the device is supposed to enter
a low power state while waiting for a wake-up from the USB Host. When the device enters
suspend mode, it asserts the suspend signal which forces the PHY into a low power state. When
the device leaves suspend mode, USB_SUSP is deasserted, enabling the PHY for normal USB
operations.
20.2.6 USB Negative/Positive Transmit Signal Output (USB_TN &
USB_TP)
These signals are each one half of the differential NRZI formatted output from the USB module.
It is fed to the transmitted D- and D+ input of the external PHY.
20.2.7 USB Transmit Enable (USB_TXEN)
This signal is an active low output enable for the differential drivers on the PHY. When this signal
is active, the differential drivers will drive the USB. When this signal is inactive, the differential
drivers will tristate their outputs.
20.3
Memory Map/Register Definition
This section provides a detailed description of all memory and registers accessible to the end user.
The names, addresses, and brief descriptions are shown in Table 20-3. All registers are 32 bits
wide and 32 bit aligned. The user may access on a byte, word, or longword basis.
MCF5275 Reference Manual, Rev. 2
20-4
Freescale Semiconductor
Memory Map/Register Definition
Table 20-3. Memory Map
1
IPSBAR Offset
Mnemonic
[31:24]
[23:16]
[15:8]
0x1C_0000
USB_FRAME
USB Frame Number and Match
0x1C_0004
USB_SPEC
USB Specification/Release Number
0x1C_0008
USB_SR
USB Status Register
0x1C_000C
USB_CR
USB Control Register
0x1C_0010
USB_DAR
USB Descriptor RAM Address
0x1C_0014
USB_DDR
USB Descriptor RAM/Endpoint Buffer Data
0x1C_0018
USB_ISR
USB Interrupt Status Register
0x1C_001C
USB_IMR
USB Interrupt Mask Register
0x1C_0020
USB_MCR
USB FIFO Memory Control
0x1C_0024–0x1C_002C
—
Reserved
0x1C_0030+(n*0x30) 1
USB_EPnSR
Endpoint n Status/Control
0x1C_0034+(n*0x30)
USB_EPnISR
Endpoint n Interrupt Status
0x1C_0038+(n*0x30)
USB_EPnIMR
Endpoint n Interrupt Mask
0x1C_003C+(n*0x30)
USB_EPnFDR
Endpoint n FIFO Data
0x1C_0040+(n*0x30)
USB_EPnFSR
Endpoint n FIFO Status
0x1C_0044+(n*0x30)
USB_EPnFCR
Endpoint n FIFO Control
0x1C_0048+(n*0x30)
USB_EPnLRFP
Endpoint n FIFO Last Read Frame Pointer
0x1C_004C+(n*0x30)
USB_EPnLWFP
Endpoint n FIFO Last Write Frame Pointer
0x1C_0050+(n*0x30)
USB_EPnFAR
Endpoint n FIFO Alarm
0x1C_0054+(n*0x30)
USB_EPnFRP
Endpoint n FIFO Read Pointer
0x1C_0058+(n*0x30)
USB_EPnFWP
Endpoint n FIFO Write Pointer
0x1C_005C+(n*0x30)
—
Reserved
[7:0]
’n’ refers to the number of endpoints: 0, 1, 2, and 3.
20.3.1 Register Descriptions
This section gives detailed descriptions of both the user accessible registers and the bits within the
USB device.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
20-5
Universal Serial Bus
20.3.1.1
USB Frame Number and Match Register (USB_FRAME)
R
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
5
4
3
2
1
0
0
0
0
0
0
MATCH
W
Reset
R
FRAME
W
Reset
0
Address
0
0
0
0
0
IPSBAR + 0x1C_0000
Figure 20-2. USB Frame Number and Match Register (USB_FRAME)
Table 20-4. USB_FRAME Field Descriptions
Bits
Name
31–27
—
26–16
MATCH
15–11
—
10–0
FRAME
20.3.1.2
R
Description
Reserved, should be cleared.
When the value in FRAME equals the value in MATCH, then an interrupt will be generated
(if not masked).
Reserved, should be cleared.
This is the 11 bit frame number decoded from the SOF packet which leads off each USB
frame.
USB Specification/Release Number Register (USB_SPEC)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
W
Reset
R
RELEASE
SPEC
W
Reset
Address
0
0
0
0
0
0
0
1
0
0
0
IPSBAR + 0x1C_0004
Figure 20-3. USB Specification/Release Number Register (USB_SPEC)
MCF5275 Reference Manual, Rev. 2
20-6
Freescale Semiconductor
Memory Map/Register Definition
Table 20-5. USB_SPEC Field Descriptions
Bits
Name
31-16
—
15–12
Reserved, should be cleared.
RELEASE This is the silicon release number of the USB device.
11–0
20.3.1.3
Description
SPEC
This is the version of USB spec to which the underlying USB core is compliant. 0x100 =
version 1.0, 0x110 = version 1.1, 0x200 = version 2.0
USB Status Register (USB_SR)
The read-only USB status register reports the current state of various features of the USB device.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
RST SUSP
CFG
INTF
ALTSET
W
Reset
Address
0
0
0
0
0
0
0
0
0
IPSBAR + 0x1C_0008
Figure 20-4. USB Status Register (USB_SR)
Table 20-6. USB_SR Field Descriptions
Bits
Name
31–9
—
8
RST
7
SUSP
6–5
CFG
Indicates the currently selected USB configuration.
4–3
INTF
Indicates which USB interface in the current configuration that ALTSET is associated with.
2–0
ALTSET
20.3.1.4
Description
Reserved, should be cleared.
Indictates whether the USB is in reset or normal singalling
0 Normal signalling in progress.
1 Reset signalling in progress.
Suspend status.
0 USB is not suspended.
1 USB is suspended.
Indicates the currently selected USB alternate interface.
USB Control Register (USB_CR)
The USB control register configures features of the USB device.
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Freescale Semiconductor
20-7
Universal Serial Bus
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CO
CE
SPD
EN
RST
0
RES
UME
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
W
Reset
R
W
Reset
Address
IPSBAR + 0x1C_000C
Figure 20-5. USB Status Register (USB_CR)
Table 20-7. USB_CR Field Descriptions
Bits
Name
31–7
—
Reserved, should be cleared.
6
CO
Command Over. Indicates that processing of a device request command has completed.
See table in CE description for usage. Automatically clears after the USB core has
completed the status phase of a control transfer.
5
CE
Command Error. Indicates that an error has been encountered during processing of a
device request. CO and CE combine to create the handshake code for the status phase of
a device request transaction.
4
SPD
Description
CO
CE
Result of Transfer
0
X
Application is busy completing the request
1
0
Application processes device request successfully
1
1
Application encountered an error processing the request
USB Speed. Sets low or full speed operation for the USB module.
0 Low Speed
1 Full Speed
WARNING: The USBSPD bit must be set to match the clock on the USB device (48 Mhz
clock for full speed and 6Mhz clock for low speed). Once set for a particular application, do
not change or unpredictable operation of the USB device will result.
3
EN
Enable. Determines if the USB module will respond to requests from the USB host. The
device exits reset in the disabled state. The user must ensure that the USB endpoint
configuration, descriptor tables, and USB registers are programmed appropriately before
enabling communications. This bit does not affect the underlying USB core, only the PHY’s
ability to communicate with the core.
0 USB module is disabled. All transactions to or from the USB device will be ignored.
1 USB module is enabled and ready to communicate with the host.
2
RST
Reset. Executes a hard reset sequence on the USB device. This bit allows the system
software to force a reset of the USB device’s logic when the system is first connected to the
USB, or for debug purposes.
MCF5275 Reference Manual, Rev. 2
20-8
Freescale Semiconductor
Memory Map/Register Definition
Table 20-7. USB_CR Field Descriptions (Continued)
Bits
Name
1
—
0
RESUME
20.3.1.5
Description
Reserved, should be cleared.
Initiates resume signalling on the USB. If remote wake-up capability is enabled for the
current USB configuration, setting this bit will cause the USB module to initiate resume
signalling on the bus. This bit automatically resets to 0 after a write of 1. Writing a 0 to this
bit has no effect. If remote wake-up capability has been disabled in the USB device via the
CLEAR_FEATURE request, then this bit will have no effect. Any user software should have
a time-out feature which aborts the remote wake-up attempt after some time if the
RESUME interrupt does not occur.
USB Descriptor RAM Address Register (USB_DAR)
31
30
R CFG BSY
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DADR
W
Reset
Address
0
0
0
0
0
0
IPSBAR + 0x1C_0010
Figure 20-6. USB Descriptor RAM Address Register (USB_DAR)
Table 20-8. USB_DAR Field Descriptions
Bits
Name
Description
31
CFG
Read only. Configuration vs. Descriptor access indicator. This bit is set automatically at
power-on or hard reset and clears after the last byte of endpoint buffer configuration data
has been downloaded into the USB device.
0 The USB_DDR register is currently set to access the descriptor storage RAM.
1 The USB_DDR register is currently set to download endpoint buffer configuration data
to the USB device.
30
BSY
Read only. Configuration download interface busy signal. Because the external PHY and
the USB device operate on different clocks, a busy indicator is provided to ensure that
writes from the USB_DDR register have a sufficient amount of time to successfully enter
the USB device’s clock domain.
0 No write is in progress.
1 A write is in progress to the USB device’s endpoint buffer. Attempt no other operations
on the USB device until BSY has cleared.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
20-9
Universal Serial Bus
Table 20-8. USB_DAR Field Descriptions (Continued)
Bits
Name
29-10
–
9–0
DADR
20.3.1.6
R
Description
Reserved, should be cleared.
Descriptor RAM address. Allows user access to the USB descriptor RAM. The user
programs a desired address into the DADR bits, then follows it with a read or write to the
USB_DDR register to complete the access. This 10-bit address is an offset address from
the base of the USB descriptor RAM. Upon read/write access to USB_DDR, the address in
DADR will increment automatically. If the CFG bit is set to 1, then DADR is ignored.
USB Descriptor RAM/Endpoint Buffer Data Register (USB_DDR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
DDAT
W
Reset
Address
0
0
0
0
0
IPSBAR + 0x1C_0014
Figure 20-7. USB Descriptor RAM/Endpoint Buffer Data (USB_DDR)
Table 20-9. USB_DDR Field Descriptions
Bits
Name
31-8
—
7–0
DDAT
20.3.1.7
Description
Reserved, should be cleared.
Endpoint buffer/descriptor RAM data register. Allows user access to the USB descriptor
memory or to the endpoint buffer download facility. For descriptor access, software
programs address into the DADR[10:0] bits and follow with a read or write to the USB_DDR
register to complete the access. Upon the read/write access, the address in USB_DAR will
increment automatically. For endpoint buffer access, writes to this register cause the data
to be loaded into the USB device’s endpoint buffers.
Access to this register is only allowed when the USBENA bit in the USB_CR register is set
to 0. Access at other times is ignored and reads are undefined.
When the CFG bit in USB_DAR is set, writes to USB_DDR register go to the USB device
endpoint/config buffers, and reads are undefined. When the CFG bit in USB_DAR is clear,
writes to USB_DDR go to the descriptor RAM, and reads come from the descriptor RAM.
USB Interrupt Status Register (USB_ISR)
The USB interrupt status register maintains the status of interrupt conditions pertaining to USB
functions. An interrupt, once set, remains set until cleared by writing a 1 to the corresponding bit.
Interrupts do not clear automatically if the event that caused them goes away (for example, if reset
MCF5275 Reference Manual, Rev. 2
20-10
Freescale Semiconductor
Memory Map/Register Definition
signalling comes and goes with no intervention from software, both RESET_START and
RESET_STOP would be set). Writing a 0 has no effect.
If a register write occurs at the same time an interrupt is received, the interrupt takes precedence
over the write.
Refer to Section 20.6.2.1, “USB Global Interrupt” for more information about these interrupt
types.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
FM
CC
0
0
0
0
0
0
0
0
0
0
W
Reset
R
MSOF SOF RSTP RSTR RES SUSP
W
Reset
Address
0
0
0
0
0
0
IPSBAR + 0x1C_0018
Figure 20-8. USB Interrupt Status Register (USB_ISR)
Table 20-10. USB_ISR Field Descriptions
Bits
Name
Description
31–8
—
7
MSOF
6
SOF
USB start of frame interrupt.
0 No start of frame received
1 A start of frame token has been received by the USB device. The USB frame number is
current.
5
RSTP
Indicates the end of reset signalling on the USB device.
0 Reset signalling has not stopped. Does not imply that reset signalling is occurring, just
that no end-of-reset event has occurred.
1 Reset signalling has stopped.
4
RSTR
Indicates start of reset signalling on the USB device.
0 No reset in progress.
1 USB Reset in progress.
3
RES
Reserved, should be cleared.
Missed start of frame interrupt.
0 No missed start of frame.
1 An SOF interrupt was set, but not cleared before the next one was received.
Indicates a state change from suspend to resume in the USB device. This bit only indicates
the change from suspended to active mode. Clearing the interrupt has no effect on the
actual state of the USB.
0 Indicates that USB has not left the suspended state (but does not imply that the bus is,
or ever was suspended).
1 USB has left suspend state.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
20-11
Universal Serial Bus
Table 20-10. USB_ISR Field Descriptions (Continued)
Bits
Name
Description
2
SUSP
Indicates a suspend state in the USB device. This bit only indicates the change from active
to suspended mode. Clearing the interrupt has no effect on the actual state of the USB.
0 USB is not suspended, or the interrupt was cleared.
1 USB is suspended.
1
FM
Indicates a match between the USB frame number and the frame match register.
0 No match.
1 Match occurred.
0
CC
This indicates that a USB configuration (configuration, interface, alternate) change
occurred and the software will need to reread the USB Status Register.
0 No activity.
1 Configuration change occurred.
20.3.1.8
USB Interrupt Mask Register (USB_IMR)
This is the USB interrupt mask register. Setting a bit in this register masks the corresponding
interrupt in the USB_ISR register. Upon reset, all interrupts are masked.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
FM
CC
0
0
0
0
0
0
0
0
1
1
W
Reset
R
MSOF SOF RSTP RSTR RES SUSP
W
Reset
Address
1
1
1
1
1
1
IPSBAR + 0x1C_001C
Figure 20-9. USB Interrupt Mask Register (USB_IMR)
MCF5275 Reference Manual, Rev. 2
20-12
Freescale Semiconductor
Memory Map/Register Definition
20.3.1.9
R
USB FIFO Memory Control Register (USB_MCR)
31
30
29
28
27
26
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
0
0
0
0
0
0
25
24
23
22
21
20
19
18
17
16
MEMC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Address
IPSBAR + 0x1C_0020
Figure 20-10. USB Memory Control Register (USB_MCR)
Table 20-11. USB_MCR Field Descriptions
Bits
Name
31–26
—
25–24
MEMC
23–0
—
Description
Reserved, should be cleared.
Selects a size for the FIFOs in the USB device. The FIFO RAM configurations are shown
below.
MEMC[1:0]
FIFO 0
FIFO 1
FIFO 2
FIFO 3
00
32
2016
0
0
01
32
1024
992
0
10
32
992
512
512
11
32
992
768
256
Reserved, should be cleared.
20.3.1.10 Endpoint n Status/Control Register (USB_EPnSR)
The control register allows the user to configure specific aspects of an individual endpoint.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
20-13
Universal Serial Bus
R
31
30
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
SIP
DIR
21
20
19
18
17
16
0
0
0
0
0
0
5
4
3
2
1
0
BYTE_COUNT
W
Reset
R
MAX
TYP
ZLPS
W
Reset
FS
FL
0
0
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x1C_0030+(n*0x30)
Figure 20-11. USB Endpoint n Status/Control Register (USB_EPnSR)
Table 20-12. USB_EPnSR Field Descriptions
Bits
Name
Description
31–28
—
27–16
BYTE_
COUNT
15–9
—
8
SIP
Setup packet in progress indicator.
0 Setup data is not being transferred from host to device.
1 Setup data currently being transferred from host to device.
7
DIR
Transfer direction, ignored for control endpoints.
0 OUT Endpoint (from host to device).
1 IN Endpoint (from device to host).
6–5
MAX
Maximum packet size for the endpoint, ignored for isochronous endpoints.
00 8 bytes
01 16 bytes
10 32 bytes
11 64 bytes
4–3
TYP
Indicates the endpoint type.
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Reserved, should be cleared
Indicates the number of bytes currently stored in the associated FIFO.
The width of this read-only field is dependent on the size of the FIFO. The low order bit of
this field is always at bit position sixteen. The high order bit is dependent on the size of the
FIFO. Bit positions above the FIFO size are treated as undefined and are unaffected by
read or write operations. The maximum field width is twelve bits.
Reserved, should be cleared
MCF5275 Reference Manual, Rev. 2
20-14
Freescale Semiconductor
Memory Map/Register Definition
Table 20-12. USB_EPnSR Field Descriptions (Continued)
Bits
Name
Description
2
ZLPS
Zero length packet send signal.
0 If the FIFO is empty and the host requests a transaction, the USB device will repond with
a NAK.
1 If the FIFO is empty, and the USB host requests an IN transaction, the USB device will
send a zero length packet in response. This bit automatically clears once the transaction
completes successfully and is used to signal the USB host that the end of data has been
reached in a data transmission when the end of data lands on a packet boundary. In that
case, there is no short packet to signal the end of data. This bit allows the software to
signal that an empty packet should go back to the host.
1
FL
Flushes the associated FIFO. This bit is write-only.
0 Do nothing.
1 Initiate flush operation.
0
FS
When written, causes the endpoint to respond with a STALL to the next poll. This bit
automatically clears when the stall takes effect.
0 Do nothing.
1 Force a stall condition.
Note: There is no endpoint stalled indicator. None is returned from the USB device. The
USB host is expected to communicate with the USB device via device requests to fix the
stall condition. The USB host will then send a CLEAR_FEATURE request to the USB
device to clear the stall and resume normal operations.
20.3.1.11 Endpoint n Interrupt Status Register (USB_EPnISR)
The endpoint interrupt status register monitors the status of a specific endpoint and generates a
CPU interrupt each time a monitored event occurs.
An interrupt, once set, remains set until cleared by writing a 1 to the corresponding bit. Interrupts
do not clear automatically if the event that caused them goes away (for example, if reset signalling
comes and goes with no intervention from software, both RESET_START and RESET_STOP
would be set). Writing a 0 has no effect.
If a register write occurs at the same time an interrupt is received, the interrupt takes precedence
over the write.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
20-15
Universal Serial Bus
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FF
FM
FE
FH
FL
DR
EOF
0
0
0
0
0
0
0
0
0
1
0
0
0
0
W
Reset
R
MDR EOT
W
Reset
Address
0
0
IPSBAR + 0x1C_0034+(n*0x30)
Figure 20-12. USB Endpoint n Interrupt Status Register (USB_EPnISR)
Table 20-13. USB_EPnISR Field Descriptions
Bits
Name
Description
31–9
—
Reserved, should be cleared.
8
FF
FIFO full.
0 FIFO is not full.
1 FIFO is full.
7
FM
FIFO empty.
0 FIFO is not empty.
1 FIFO is empty.
6
FE
Indicates an error condition in the FIFO controller. The error condition can be checked by
reading the FIFO status register (USB_EPnFSR).
0 No Error condition pending.
1 Error condition pending.
5
FH
Indicates that the number of bytes in the FIFO has surpassed the high level alarm value.
4
FL
Indicates that the number of bytes in the FIFO has fallen below the FIFO low level alarm
value.
3
MDR
Asserts when a device request (DR) interrupt is pending and another setup packet is
received. Will only assert for control endpoints.
0 Multiple setup packets are not pending.
1 Multiple setup packets pending.
2
EOT
Indicates that the last packet of a USB data transfer has crossed into, or out of, the USB
device. Any packet shorter than the maximum packet size for the associated endpoint is
considered to be an end of transfer marker. In addition, for control endpoints only, the EOT
interrupt will assert then the number of bytes specified in the wLength field of the setup
packet have been transferred.
1
DR
Indicates a device request on the current endpoint. Will only assert for control endpoints
0 No request pending.
1 Request pending.
0
EOF
Monitors the data flow between the FIFO and the USB device and indicates when the end
of a USB packet is written into the FIFO or the USB device as the end of a frame.
0 End of frame (USB packet) was not sent/received.
1 End of frame (USB packet) sent/received.
MCF5275 Reference Manual, Rev. 2
20-16
Freescale Semiconductor
Memory Map/Register Definition
20.3.1.12 Endpoint n Interrupt Mask Register (USB_EPnIMR)
The endpoint interrupt mask register allows software to mask individual interrupts for each
endpoint. Writing a 1 to a bit in this register masks the corresponding interrupt in the USB_EPnSR
register. Writing a 0 unmasks the interrupt.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
FF
FM
FE
FH
FL
DR
EOF
0
0
0
0
0
0
0
1
1
1
1
1
1
1
W
Reset
R
MDR EOT
W
Reset
Address
1
1
IPSBAR + 0x1C_0038+(n*0x30)
Figure 20-13. USB Endpoint n Interrupt Mask Register (USB_EPnIMR)
20.3.1.13 Endpoint n FIFO Data Register (USB_EPnFDR)
The endpoint FIFO data register is the main interface port for the FIFO. Data which is to be
buffered in the FIFO, or has been buffered in the FIFO, is accessed through this register. This
register can always access data from the FIFO, independent of the FIFO’s transmit or receive
configuration. It can be accessed by byte, word, or longword. It is recommended to align all
accesses to the most significant byte (big endian) of the data port, using the address of
USB_EPnFDR for byte, word, and longword transactions. However, accessing the data port at
USB_EPnFDR+1,2,3 for bytes or USB_EPnFDR+2 for words is also accepable.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
DATA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
DATA
W
Reset
0
0
Address
0
0
0
0
0
0
IPSBAR + 0x1C_003C+(n*0x30)
Figure 20-14. USB Endpoint n FIFO Data Register (USB_EPnFDR)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
20-17
Universal Serial Bus
Table 20-14. USB_EPnFDR Field Descriptions
Bits
Name
31–0
DATA
Description
When read, this is the receive FIFO data. When written, this is the transmit FIFO data.
20.3.1.14 Endpoint n FIFO Status Register (USB_EPnFSR)
The FIFO status register contains bits which provide information about the status of the FIFO
controller. Some of the bits of this register used to generate DMA requests, are provided here for
visibility. The bits marked sticky are cleared by writing a one to their position.
R
31
30
29
28
27
26
25
24
23
22
21
20
19
0
0
0
0
F0
F1
F2
F3
0
RXW
UF
OF
FR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
18
17
16
FULL ALA EMPTY
RM
W
Reset
Address
IPSBAR + 0x1C_0040+(n*0x30)
Figure 20-15. USB Endpoint n FIFO Status Register (USB_EPnFSR)
Table 20-15. USB_EPnFSR Field Descriptions
Bits
Name
Description
31–28
—
Reserved, should be cleared.
27
F0
Read only. Provides frame status indicator.
0 No frame boundary.
1 A frame boundary has occurred on the [31:24] byte of the bus.
26
F1
Read only. Provides frame status indicator.
0 No frame boundary.
1 A frame boundary has occurred on the [23:16] byte of the bus.
25
F2
Read only. Provides frame status indicator.
0 No frame boundary.
1 A frame boundary has occurred on the [15:8] byte of the bus.
24
F3
Read only. Provides frame status indicator.
0 No frame boundary.
1 A frame boundary has occurred on the [7:0] byte of the bus.
23
—
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
20-18
Freescale Semiconductor
Memory Map/Register Definition
Table 20-15. USB_EPnFSR Field Descriptions (Continued)
Bits
Name
Description
22
RXW
Receive wait condition. Indicates that the FIFO receive bus is incurring wait states because
there is not enough room in the FIFO to accept the data without causing overflow. This bit
is sticky.
0 No wait state.
1 One or more wait states occur on the FIFO receive bus.
21
UF
Indicates FIFO underflow, sticky bit.
0 No Underflow.
1 Read pointer has passed the write pointer.
20
OF
Indicates FIFO overflow, sticky bit
0 No overflow.
1 Write pointer has passed the read pointer.
19
FR
Frame ready indicator. Only active when the FIFO is programmed for frame mode. All
complete frames must be read from the FIFO to clear this alarm. Read only.
0 No complete frames exist in the FIFO.
1 One or more complete frames exists in the FIFO.
18
FULL
FIFO full, read only.
0 The FIFO is not full.
1 The FIFO has requested attention because it is full. The FIFO must be read to clear this
alarm.
17
ALARM
FIFO alarm. This read-only bit indicates that the FIFO has determined an alarm condition.
When the FIFO is configured to receive (OUT), the FIFO alarm provides high level
indication. The bit will be set when there are less than alarm bytes free in the FIFO. The
alarm is cleared when the FIFO is read so that fewer than EPnFCR[GR] bytes remain in
the FIFO.
When the FIFO is configured to transmit (IN), the FIFO alarm provides low level indication.
The bit will setwhen there are more than alarm bytes in the FIFO. The alarm is cleared
when the FIFO is written so that less than (4 × EPnFCR[GR]) free bytes in the FIFO.
0 Alarm not set.
1 The FIFO has requested attention because it has determined an alarm condition.
16
EMPTY
15-0
—
FIFO empty indicator, ready only
0 The FIFO is not empty.
1 The FIFO has requested attention because it is empty. The FIFO must be written to clear
this alarm.
Reserved, should be cleared.
20.3.1.15 Endpoint n FIFO Control Register (USB_EPnFCR)
The FIFO control register provides programmability of FIFO behaviors, including last transfer
granularity and frame operation. Last transfer granularity allows the user to control when the FIFO
controller stops requesting data transfers through the FIFO alarm by modifying the deassertion
point of the alarm, ensuring the data stream is stopped at a valid point, or there remains enough
space in the FIFO to unload the input data pipeline.
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20-19
Universal Serial Bus
R
31
30
29
28
27
0
0
WFR
0
FRA
ME
0
0
0
0
0
0
0
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
W
Reset
R
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GR
W
Reset
Address
IPSBAR + 0x1C_0044+(n*0x30)
Figure 20-16. USB Endpoint n FIFO Status Register (USB_EPnFSR)
Table 20-16. USB_EPnFCR Field Descriptions
Bits
Name
Description
31–30
—
29
WFR
28
—
27
FRAME
Frame mode enable. When this bit is set, the FIFO controller monitors frame done
information from the peripheral. Setting this bit also enables the other frame control bits in
this register, as well as other frame functions. This bit must be set to use frame functions.
In FRAME mode, the FIFO uses its internal frame pointer and information from the
peripheral to transfer only full frames of data, as defined by the peripheral. Since the
controller only keeps a pointer to the end of the last complete frame, a read request may
contain more than one frame of data.
0 Frame mode disabled.
1 Frame mode enabled.
26–24
GR
These bits define the deassertion point for the “high” service request, and also define the
deassertion point for the “low” service request. A “high” service request is deasserted when
there are less than GR[2:0] data bytes remaining in the FIFO. A “low” service request is
deasserted when there are less than (4 * GR[2:0]) free bytes remaining in the FIFO. The
direction, type, and packet size are defined in the USB_EPnSR registers.
23-0
—
Reserved, should be cleared.
Reserved, should be cleared
Write Frame. When this bit is set, the FIFO controller assumes the next write to its data port
is the end of a frame, and will tag the incoming data accordingly. This bit is automatically
cleared by a write to the data port.
0 Next write to FIFO data register is not the end of frame.
1 Next write to FIFO data register is the end of frame.
Reserved, should be cleared.
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Memory Map/Register Definition
20.3.1.16 Endpoint n Last Read Frame Pointer (USB_EPnLRFP)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
LRFP
W
Reset
0
0
Address
0
0
0
0
IPSBAR + 0x1C_0048+(n*0x30)
Figure 20-17. USB Endpoint n Last Read Frame Pointer (USB_EPnLRFP)
Table 20-17. USB_EPnLRFP Field Descriptions
Bits
Name
31–12
—
11–0
LRFP
Description
Reserved, should be cleared.
A FIFO-maintained pointer which indicates the location of the start of the most recently
read frame, or the start of the frame currently in transmission. The LRFP updates on
FIFO read data accesses to a frame boundary. The LRFP can be read and written for
debug purposes. When FRAME is not set, then this pointer has no meaning. The last
read frame pointer is reset to zero, and non-functional bits of this pointer are unaffected
by reset.
The width of the LRFP field is dependent on the size of the FIFO. The low order bit of
this field is always at bit position zero. The high order bit is dependent on the size of
the FIFO. Bit positions above the FIFO size are treated as undefined and are
unaffected by read or write operations. The maximum field width is twelve bits (i.e.
FIFO size of 212 with a maximum value of 0xFFF).
20.3.1.17 Endpoint n Last Write Frame Pointer (USB_EPnLWFP)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
LWFP
W
Reset
Address
0
0
0
0
0
0
0
IPSBAR + 0x1C_004C+(n*0x30)
Figure 20-18. USB Endpoint n Last Write Frame Pointer (USB_EPnLWFP)
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Freescale Semiconductor
20-21
Universal Serial Bus
Table 20-18. USB_EPnLWFP Field Descriptions
Bits
Name
31–12
—
11–0
LWFP
Description
Reserved, should be cleared.
A FIFO-maintained pointer which indicates the start of the last frame written into the
FIFO. The LWFP updates on FIFO write data accesses which create a frame
boundary, whether that be by setting the WFR bit in the FIFO Control Register, or
by feeding a frame bit in on the appropriate bus. The LWFP can be read and written
for debug purposes. Data between the LWFP and write pointer is of an incomplete
frame, while data between the read pointer and the LWFP has been received as
whole frames. When FRAME is not set, then this pointer has no meaning. The last
write frame pointer is reset to zero, and non-functional bits of this pointer are
unaffected by reset.
The width of the LWFP field is dependent on the size of the FIFO. The low order bit
of this field is always at bit position zero. The high order bit is dependent on the size
of the FIFO. Bit positions above the FIFO size are treated as undefined and are
unaffected by read or write operations. The maximum field width is twelve bits (i.e.
FIFO size of 212 with a maximum value of 0xFFF).
20.3.1.18 Endpoint n FIFO Alarm Register (USB_EPnFAR)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
ALARM
W
Reset
Address
0
0
0
0
0
0
0
IPSBAR + 0x1C_0050+(n*0x30)
Figure 20-19. USB Endpoint n FIFO Alarm Register (USB_EPnFAR)
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Memory Map/Register Definition
Table 20-19. USB_EPnFAR Field Descriptions
Bits
Name
31–12
—
11–0
ALRM
Description
Reserved, should be cleared.
Provides high/low level alarm information to the user integration logic. A low level alarm
reports lack of data while a high level alarm reports lack of free space. This programmable
alarm warns the system when the FIFO is almost full of data (FIFO High), or when the FIFO
is almost out of data (FIFO Low). This register is programmed to the upper limit for the
number of bytes of data or space in the FIFO before an internal alarm is set. If the amount
of data or space in the FIFO is above the indicated amount, the alarm will be set in
non-frame mode. In frame mode, the alarm will be set if the amount of data or space in the
FIFO is above the amount indicated by the ALRM setting OR if there are end of frame bytes
in the FIFO (see frame mode operation). The alarm is cleared when there is less data or
space than is programmed in the FIFO granularity field of the FIFO Control register. The
number of bits in the alarm pointer register will vary with the address space of the FIFO
memory and the alarm pointer is initialized to 0.
The width of the ALRM field is dependent on the size of the FIFO. The low order bit of this
field is always at bit position zero. The high order bit is dependent on the size of the FIFO.
Bit positions above the FIFO size are treated as undefined and are unaffected by read or
write operations. The maximum field width is twelve bits (i.e. FIFO size of 212 with a
maximum value of 0xfff).
20.3.1.19 Endpoint n FIFO Read Pointer (USB_EPnFRP)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
RP
W
Reset
Address
0
0
0
0
0
0
IPSBAR + 0x1C_0054+(n*0x30)
Figure 20-20. USB Endpoint n FIFO Read Pointer (USB_EPnFRP)
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Universal Serial Bus
Table 20-20. USB_EPnFRP Field Description
Bits
Name
Description
31–12
—
Reserved
11–0
RP
A FIFO-maintained pointer which points to the next FIFO location to be read. The physical
address of this FIFO location is actually the sum of the read pointer and the FIFO base,
which is provided through a port to the FIFO controller. This base address can vary, but if
chosen properly, the FIFO RAM address can be concatenated with the read pointer instead
of requiring hardware for addition. The read pointer can be both read and written. This
ability facilitates the debug of the FIFO controller and peripheral drivers.
The width of the RP field is dependent on the size of the FIFO. The low order bit of this field
is always at bit position zero. The high order bit is dependent on the size of the FIFO. Bit
positions above the FIFO size are treated as undefined and are unaffected by read or write
operations. The maximum field width is twelve bits (i.e. FIFO size of 212 with a maximum
value of 0xFF).
20.3.1.20 Endpoint n FIFO Write Pointer (USB_EPnFWP)
R
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
WP
W
Reset
Address
0
0
0
0
0
0
IPSBAR + 0x1C_0058+(n*0x30)
Figure 20-21. USB Endpoint n FIFO Write Pointer (USB_EPnFWP)
Table 20-21. USB_EPnFWP Field Description
Bits
Name
31–12
—
11–0
WP
Description
Reserved
A FIFO-maintained pointer which points to the next FIFO location to be written. The
physical address of this FIFO location is actually the sum of the read pointer and the FIFO
base, which is provided through a port to the FIFO controller. This base address can vary,
but if chosen properly, the FIFO RAM address can be concatenated with the read pointer
instead of requiring hardware for addition. The read pointer can be both read and written.
This ability facilitates the debug of the FIFO controller and peripheral drivers.
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Functional Description
20.4
Functional Description
This section provides a complete functional description of the USB device module, detailing the
operation of the design from the end user perspective. All operating modes, and each major block
within the design are discussed.
20.4.1 USB Components
Each component shown in the block diagram from Section 20.1.1, “Block Diagram” is discussed
within this section.
20.4.1.1
Descriptor RAM
This 1-Kbyte descriptor RAM allows the programmer to preload the descriptors and modify them
as necessary. Refer to chapter 9 of the USB specification for more information on the descriptor
structures.
20.4.1.2
FIFO Controller
The USB never needs to communicate with more than one data FIFO at a time. Therefore, the
FIFO controller modules in the USB device share a single RAM for FIFO data storage. User
programmable registers allow on-the-fly configuration of individual FIFO sizes.
The USB protocol has some specialized requirements which affect FIFO implementation and
create a need for one FIFO per USB endpoint. The USB host may access any endpoint on the
device in any order, even the same endpoint in back to back transactions. There is also a latency
requirement. The USB device must respond to the USB host within a certain number of USB bit
times or the device loses its time slice on the USB until some point in the future. In order to achieve
maximum USB bandwidth utilization, the USB device must be able to provide full packets of data
to the USB host immediately upon request and receive full packets from the host on request. This
requirement results in one FIFO per USB endpoint. Depending upon the traffic requirements, the
user may need to size the FIFO to support double buffering.
20.5
Reset Strategy
This section describes how to reset the device. Descriptions are limited to sources and
requirements of reset. All sources of reset are shown in Table 20-22.
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Universal Serial Bus
Table 20-22. Reset Summary
Reset Type
Hard Reset
Source
Characteristics
Internal
Resets all storage elements in the USB device.
Peripheral Bus
USB Device
Reset
USB_CR
Register
"Soft" reset of USB device. Control registers and FIFO’s are left intact. Required any
time a connect or disconnect event occurs on the USB that is not accompanied by a
hard reset.
USB Bus
Reset
USB Cable
"Soft" reset of all devices on USB so that the host may re-enumerate them with new
addresses. Does not reset any datapath elements, but may require user to flush
FIFO’s and prepare to configure a change request from USB host.
20.5.1 Description of Reset Operation
This USB device includes three reset modes: hard reset, USB device reset, and USB bus reset. All
three reset modes are described in this section.
20.5.2 Hard Reset
A hard reset is generated from the USB device’s bus interface and resets all storage elements in
both the external PHY and in the USB device. A hard reset also issues a USB device reset.
20.5.2.1
USB Device Reset
The USB device must be reset any time a connect/disconnect occurs on the USB system. Any time
the device is plugged in or unplugged from the USB system, software must initiate a USB device
reset in order to ensure that the device can properly communicate with the USB host. Reset
signalling is discussed in Chapter 7 of the USB specification. A USB device reset may invalidate
data remaining in the data FIFOs. Depending upon the application, software may need to flush the
data FIFOs before proceeding.
20.5.2.2
USB Bus Reset
USB bus reset signalling can occur on the USB for a number of reasons. When the device receives
bus reset signalling, it means that the host is preparing to re-enumerate the bus. All transactions in
progress must be invalidated, and the device software should prepare to receive configuration
changes.
Because the device may have valid, but as yet unread data remaining in the FIFOs when USB bus
reset occurs, the hardware does not flush the FIFOs. When device software receives reset
signalling, it should first finish reading any unread data from the FIFOs, then execute FIFO flush
operations on all of the FIFOs. This guarantees that the datapath is empty and ready for new data
transfer operations when reset signalling and re-enumeration are complete.
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Interrupts
Reset signalling is discussed in Chapter 7 of the USB specification.
20.6
Interrupts
This section describes interrupts originated by the USB device. The available interrupts are briefly
described in Table 20-23.
Table 20-23. Interrupt Summary
Number of
Interrupt
Offset
Vector
Priority
Source
Description
INT43–INT4
6
N/A
N/A
N/A
USB Endpoints
USB_EPnISR
USB Endpoint 0-3 specific interrupts.
Tied to FIFO status and datapath
logic.
INT47
N/A
N/A
N/A
USB Global Interrupt
USB_ISR
USB device global status interrupt.
20.6.1 Description of Interrupt Operation
This USB device supports interrupts from two sources: the USB endpoints and the USB device’s
control logic. Both interrupt sources behave exactly the same way.
Each interrupt source is associated with an interrupt status register and an interrupt mask register.
At reset time, all interrupts are masked. Clearing a bit in the mask register unmasks the
corresponding interrupt, while setting the bit masks the interrupt. When an interrupt event occurs
and the interrupt is unmasked, an interrupt request asserts to the CPU’s interrupt controller.
Re-masking the interrupt without actually clearing the request will turn-off the interrupt request to
the CPU, but will not affect the status of the pending interrupt.
The CPU services an interrupt by reading the appropriate interrupt status register and clearing the
pending interrupts. Interrupts are cleared by writing a 1 to the appropriate bit in the interrupt status
register. Writing zeros to the interrupt status registers has no effect. Once all pending interrupts
have been cleared, the interrupt request to the CPU will also clear.
20.6.2 Detailed Interrupt Descriptions
A number of interrupts are generated by the USB device to indicate situations requiring attention
from the CPU. The types of interrupts are broken into two categories: the USB global interrupt and
endpoint specific interrupts.
20.6.2.1
USB Global Interrupt
The USB global interrupt indicates such things as global configuration and status changes that
pertain to the USB, which are described below. Refer to Section 20.3.1.7, “USB Interrupt Status
Register (USB_ISR)” for more information.
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Universal Serial Bus
20.6.2.1.1 Missed Start of Frame (MSOF)
The MSOF interrupt is used to inform software that it did not service the SOF interrupt before
another SOF was received.
20.6.2.1.2 Start of Frame (SOF)
The SOF interrupt indicates that a start of frame token was received by the device. The current
USB frame number may be read from the USB_FRAME register. The start of frame interrupt is
usually used by isochronous devices to provide a stable timebase.
20.6.2.1.3 End of USB Reset Signalling (RESET_STOP)
The RESET_STOP interrupt indicates that reset signalling from the host on the USB has stopped.
When not asserted, RESET_STOP indicates that no end of reset event has been received.
20.6.2.1.4 Start of USB Reset Signalling (RESET_START)
The RESET_START interrupt indicates that reset signalling on the USB has begun. When reset
signalling is active on the USB, the device should not expect to receive any transactions on the
bus. This interrupt results in a reset of the USB device into the powered state. See the USB
specification for more information on the powered state. The powered state means that the USB
device will not respond to USB transactions.
This interrupt only indicates the start of reset signalling. Status of the USB at any given moment
can be verified by examining the USB_SR register.
The user is cautioned that presence of USB reset signalling invalidates any transaction in progress.
On detection of RESET_START, user software should read any remaining valid data from receive
FIFOs and flush all the others. When reset signalling is detected, user software must clear any
pending interrupts and ensure that the USB device is configured properly after the reset.
20.6.2.1.5 Resume Signalling Detected (RES)
This interrupt asserts when resume signalling is detected on the USB. The device uses this
interrupt to wake up from suspend mode and resume normal operations.
20.6.2.1.6 USB Suspended (SUSP)
This interrupt asserts when the USB goes into suspend mode. Suspend mode occurs when the
device fails to receive any traffic from the USB for a period of 3ms. Once suspend mode is
detected, the device should put itself into a low power standby mode.
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Interrupts
20.6.2.1.7 Match Detected in USB_FRAME (FM)
This interrupt asserts when the frame number programmed into the MATCH field of the
USB_FRAME register is the same as the FRAME field of the USB_FRAME register. Isochronous
pipes may use this interrupt for synchronization between the data source and sink.
20.6.2.1.8 USB Configuration Change (CC)
This interrupt indicates that the USB host selected a different configuration or alternate interface
from the list of descriptors stored in the descriptor RAM module. Software should read the
USB_SR register to determine which configuration and alternate interface are current, then
reconfigure itself accordingly.
20.6.2.2
Endpoint Interrupts
The endpoint interrupts indicate requests for service by specific USB endpoints. All bits are
maskable.
When an event occurs that causes an interrupt condition to occur, and the
corresponding bit in the interrupt mask register is 0, an interrupt signal will assert on the USB
device’s interface. Writing a 1 to the associated bit in the interrupt status register clears the
interrupt.
20.6.2.2.1 FIFO Full & Empty Indicators (FF & FM)
These interrupts assert when the FIFO is either full or empty.
20.6.2.2.2 FIFO Error Indicator (FE)
This interrupt indicates some abnormal condition occurred in the FIFO. The cause of the error can
be verified by reading the USB_EPFSRFSR register associated with the FIFO that had the error.
20.6.2.2.3 FIFO High & Low Level Alarms (FH & FL)
Each FIFO has an alarm register, USB_EPnFAR. If the byte count in the FIFO is above the level
specified by the alarm register, then the FH interrupt will assert. If the byte count in the FIFO is
below the level specified by the alarm register, then the FL interrupt will assert.
20.6.2.2.4 End of Transfer (EOT)
This interrupt asserts after the last data byte of a USB transfer has been received or sent by a USB
device. The end of a USB transfer is indicated by either a zero byte packet, or by a data packet
shorter than the maximum packet size for the endpoint. Listed below are other instances in which
the EOT interrupt will or will not assert:
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Universal Serial Bus
•
•
•
•
The EOT interrupt will generally assert along with an EOF interrupt, although it is possible
to get an EOT interrupt without an EOF interrupt if a transfer is terminated on a USB packet
boundary.
The EOT interrupt never asserts for setup packets.
The EOT interrupt asserts after every interrupt packet transfer, at the completion of bulk
data transfers, and at the end of the data phase of a control transfer.
The EOT interrupt only asserts for isochronous packet transfers if the USB device reports
that the packet data is error free. This can be used along with the EOF interrupt to determine
when a transfer error of some sort occurs on an isochronous endpoint.
20.6.2.2.5 Device Request (DR)
The device request (setup packet) interrupt indicates that the most recently received packet was a
setup or device request packet. Software on the USB device must decode and respond to the packet
in order to complete a vendor, class, or standard request.
20.6.2.2.6 Multiple Device Request (MDR)
The multiple device request interrupt asserts when two or more setup packets have been received
before the DR interrupt was cleared. This interrupt is used to determine when the USB host has
aborted a transfer in progress. In this case, the device will receive a setup packet, followed by a
new setup packet before it has completed processing of the original command.
20.6.2.2.7 End of Frame (EOF)
This interrupt indicates that an end of frame marker was sent or received on the FIFO/USB
interface. This interrupt will assert if a DR is received. This interrupt asserts for bulk, control,
isochronous, and interrupt data. While packet retries are not supported for isochronous endpoints,
the end of frame indicator is still valid and may be used along with the SOF interrupt to control
data flow.
20.6.2.3
Interrupts, Missed Interrupts, and the USB Device
There are a number of cases where improper operation of the device could result if interrupts are
not serviced in a timely manner. For example, if a CC interrupt is received, the device does not
service it, and another CC interrupt is received. This could leave the device in an incorrect
operating mode. The interrupts of concern are SOF, CC, EOT, and DR.
The missed-interrupt behaviors are listed below:
20.6.2.3.1 Start of Frame (SOF)
If the device misses a start of frame interrupt, the MSOF bit asserts in the USB_ISR register.
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Software Interface
20.6.2.3.2 Configuration Change (CC)
When the USB device receives a CC interrupt, the device will acknowledge (NAK) all traffic from
the USB host on all endpoints until software clears the interrupt bit. This prevents the device
configuration from getting out of sync with what the host has requested.
20.6.2.3.3 End of Transfer (EOT)
When an end of transfer is received on a BULK OUT endpoint, the device will not NAK all traffic
on that endpoint until software clears the interrupt bit. This prevents data from two different
transfers from becoming mixed up in a FIFO.
20.6.2.3.4 Device Request (DR)
When a device request is received, the device will NAK all in/out traffic on the affected endpoint
until software clears the interrupt bit. This ensures that the device correctly identifies the setup
packet in the FIFO and can clear the FIFO before the data phase is allowed to begin. If multiple
setup packets are received, the MDR interrupt will assert to warn of that condition. The control
transfer state machine within the USB device will not advance from the setup phase to the data
phase until the DEVREQ bit is cleared.
20.7
Software Interface
This section provides information pertinent to programming the device. It includes information to
configure, program, and debug the device.
20.7.1 Device Initialization
During device initialization, user software downloads critical configuration information to the
USB device’s descriptor RAM datapath for processing. This process is performed at two different
times: hard reset and when the device is first connected to the USB system. The USB connection
event is described in the USB Specification, Revision 2.0, Chapter 7, “Electrical Specification.”
At power-up time, the USB device contains no configuration information. The USB device does
not know how many endpoints it has available or how to find the descriptors. Initialization for the
device consists of downloading this information to the appropriate memories and configuring the
datapath to match the intended application. The following steps are involved in the initialization
process:
1. Perform a hard reset or a USB device reset (USB_CR[RST]). Software must wait for the
USB_DAR[CFG] bit to assert before attempting to communicate with the USB device .
2. Download configuration data (StringBufs, CfgBufs, and EpBufs) to the device
(USB_DDR).
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3. Download USB descriptors to the descriptor RAM via the USB_DAR and USB_DDR
registers.
4. Program the USB Interrupt Mask register (USB_IMR) to enable interrupts not associated
with a particular endpoint.
5. Program each endpoint’s control and interrupt registers (USB_EPnIMR and
USB_EPn_CTRL) to support the intended data transfer modes.
6. Select the FIFO sizes (USB_MCR).
7. Program endpoint type, direction, and maximum packet size in the USB_EPnSR register
for each endpoint.
8. Program the FIFO controller registers. For each enabled endpoint, program frame mode,
granularity, alarm level, frame size, etc. (USB_EPnFCR). Normally, all endpoints should
be programmed with FRAME mode enabled.
9. Enable the USB for processing (USBENA bit in USB_CR).
Note that USB device initialization is a time critical process. The USB host will wait about 100ms
after power-on or a connection event to begin enumerating devices on the bus. This device must
have all of the configuration information available when the host requests it.
Once the device has been enumerated, the USB host will select a specific configuration and set of
interfaces on the device. Software on the device must be aware of USB configuration changes in
order to maintain proper communication with the USB host. The software retains sole
responsibility for knowing which configuration and alternate interface are current at any given
time. The CFG_CHG interrupt in the USB_ISR register reports changes in device configuration
and alternate interface settings to the software. Note that the software is required to respond to the
CFG_CHG interrupt. To prevent the state of the device from becoming out of sync with respect to
the host, the device halts further traffic on the USB while this interrupt is pending.
20.7.1.1
Configuration Download
The configuration download process initializes a number of buffers within the USB device that
define its personality on the USB system. This information includes RAM addresses for the
configuration (CfgBufs), string descriptors (StringBufs), and one 40 bit buffer per endpoint
(EpBufs).
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Table 20-24. Configuration Buffers Format (CfgBufs)
Bits
Type
Description
31–16
Descriptor Size
This is the size of the Descriptor to be returned when the USB host issues a
Get_Descriptor command to the device. For the MCF5275 the minimum descriptor
size that can be set is 46 bytes (with one endpoint) and the maximum can be 60
bytes. This includes the combined length of all descriptors (configuration,
interface, endpoint and class or vendor specific) returned for this configuration.
15–0
Descriptor
Address Pointer
This is the address pointer of where the descriptor is located in the USB descriptor
RAM. The address pointer must be set within 0x0000 and 0x0300.
Table 20-25. String Buffers Format (StringBufs)
Bits
Type
Description
23–16
String Length
This is the length of the string in bytes with which this String Buffer is associated.
This is the USB blength of the String Descriptor for the String.
15–0
String Address
Pointer
This is the address pointer of a location in the USB descriptor RAM at which the
String is located.
The endpoint buffers are 40 bit-per-endpoint data strings that are loaded directly into the USB
device. They associate “logical” endpoint numbers in the USB software stack with hardware
within the USB device. Specifically, they attach each endpoint to a USB configuration, interface,
and alternate interface. Then they specify transfer type, packet size, and data direction among other
characteristics. In addition, each endpoint buffer includes a 16 bit data field that allows the end
user to specify the mapping between USB endpoints and the hardware FIFOs for the USB device.
Table 20-26. Endpoint Buffer Format (EpBufs)
Bits
Type
Description
39–36
EpNum
35–34
Ep_Config
33–32
Ep_Interface
Interface number to which the endpoint belongs.
31–30
Ep_AltSetting
Alternate setting to which the endpoint belongs.
29–28
Ep_Type
27
Ep_Dir
26–17
Ep_MaxPktSize
Logical Endpoint Number
Configuration number to which the endpoint belongs.
Type of endpoint.
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Direction of endpoint. Ignored for control endpoints.
0 Out endpoint
1 In endpoint
Maximum packet size for this endpoint.
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Table 20-26. Endpoint Buffer Format (EpBufs)
Bits
Type
16
Unused
15–0
Ep_BufAdrPtr
Description
Unused bit. Set this bit to zero.
16 bit address that points to one of the four FIFOs of the USB device. See
Section 20.7.1.2, “USB Endpoint to FIFO Mapping,” for more information on the
format for this field.
The USB device has one configuration, one interface with two alternate settings, three strings, and
four logical endpoints that are configured as seven physical endpoints.
Download of the configuration data consists of the following steps:
1. Verify that the CFG bit is set in the USB_DDR register. This ensures that the USB device
has been properly reset and is prepared to take data.
2. Write the configuration buffers, string buffers, and endpoint buffers to the USB_DDR
register. These buffers should be written most significant byte first. After writing each
byte, and before performing any other operation on the peripheral, check that the BSY bit
has cleared in the USB_DAR register.
3. After writing all endpoint buffer configuration bytes, check the CFG bit of USB_DAR to
verify that the configuration load has completed. This bit changes from 1 to 0 after the last
byte has been loaded into the USB device.
20.7.1.1.1 Logical vs. Physical Endpoints
There is a distinction in the USB device between logical and physical endpoints. Logical endpoints
are those seen by the host. Physical endpoints can have the same logical endpoint number but
different characteristics, such as being different direction or existing on a different alternate
interface. Endpoint 0 is always a control endpoint. Endpoints 1, 2, and 3 can be organized on one
or both alternate interfaces. See for information about configuring logical endpoints.
20.7.1.2
USB Endpoint to FIFO Mapping
The MCF5275 USB device recognizes up to four logical endpoints or seven physical endpoints.
Some hardware must be associated with each physical endpoint. Since two physical endpoints
mapped on a logical endpoint cannot be used simultaneously, one hardware FIFO will be sufficient
to support both.
Each logical endpoint consists of a FIFO that can be programmed independently for depth,
direction, transfer type, frame mode, and low/high alarms. In order to fit these hardware endpoints
to the USB’s “logical” endpoints, a mapping is established in the USB device’s endpoint buffer.
Endpoint type, direction, and packet size are defined via the USB_EPnSR register for each
endpoint. FIFO characteristics are programmed via the USB_EPnFCR and USB_EPn_ALRM
registers. Mapping of USB endpoints to specific hardware FIFOs is accomplished at power-up
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time when the USB device endpoint buffers are downloaded to the device from the CPU. Each
endpoint buffer makes 16 bits available to the user for the purpose of identifying a hardware
endpoint.
Table 20-27. Ep_BufAdrPtr Format
Bit
Name
15
14
TRXTYP[1:0]
13
12
11
10
9
8
7
6
5
4
RESERVED
3
2
1
0
EPNUM[3:0]
Table 20-28. Ep_BufAdrPtr Field Descriptions
Bits
Name
Description
15–14
TRXTYP
For this revision of the USB device, these bits must be set to 0b00 for endpoint 0, and 0b11
for all other endpoints.
3–0
EPNUM
This field maps the endpoint to one of the USB device’s hardware FIFOs. Multiple USB
device endpoints may map to a single hardware FIFO. It is up to the software to monitor
and control any data hazards related to operation in this way.
Ep_Buf0 is a special case. The value in Ep_BufAdrPtr indicates the descriptor RAM address
instead of one of the hardware endpoints (FIFOs). Logical and physical endpoint 0 always use
hardware endpoint 0 for transfers not handled by the USB device. Software can map the remaining
logical endpoints to any of the remaining three hardware endpoints.
20.7.1.3
USB Descriptor Download
The USB descriptors are standard data structures which are used by the USB host to allocate
bandwidth and to figure out how many and what kind of endpoints are available on the device.
While this data is stored in the device’s memory space, it is not directly used by either the
USBCORE or the USB devices. The data gets returned to the USB host during a
GET_DESCRIPTOR request. The USB host picks a specific configuration and alternate interface,
and then instructs the device which to enable. The USB descriptor formats are defined in Chapter
9 of the USB specification. Software programs are available from various sources to assist in
creating the descriptor tables.
Any time the USB host changes the USB device configuration or alternate interface, an interrupt
is generated in this device to inform the user that something changed. Software must then read the
USB status register (USB_SR) to determine the new current configuration and alternate setting.
Software is responsible for FIFO management and endpoint re-configuration each time the USB
configuration changes.
Download of the descriptor data consists of the following steps:
1. Verify that the CFG bit is clear in the USB_DDR register. This ensures that the USB device
has been properly reset and configured and is prepared to take data.
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2. Write the starting address of the descriptors into the DADR field of the USB_DAR
register. The address written to this register is the address of the desciptors within the
descriptor RAM attached to the USB device, not the system RAM.
3. Write each byte of the descriptor table to the DDAT field of the USB_DDR register. The
USB_DAR register increments automatically at each register access (read or write).
20.7.1.4
USB Interrupt Register
If the application makes use of the interrupt registers, then the specific interrupts to be used must
be enabled. During a reset, all interrupts revert to the masked state. The USB global interrupt
(affecting the whole USB device) is programmed separately from those affecting a single
endpoint.
20.7.1.5
Endpoint Registers
For each endpoint, the characteristics of the FIFO and a number of interrupt sources may be
programmed. Software must program the following registers:
•
•
•
•
•
•
USB endpoint interrupt mask (USB_EPnIMR)
Separate interrupt registers are provided for each hardware FIFO. Enable the interrupts
pertaining to the application by writing a 0 to the mask bit for that interrupt.
Endpoint FIFO controller configuration(USB_EPnFCR).
Each FIFO is programmed based for the type of data transmission used by the endpoint.
FIFO alarm register (USB_EPn_ALRM).
For bulk traffic (FRAME=1), the alarm level is normally programmed to a multiple of the
USB packet size(i.e. for 8 byte packets and a 16 byte FIFO, the alarm would be
programmed to 8 bytes) to allow the request lines to request full packets. For single
buffered endpoints (packet size =8, FIFO depth=8 bytes), the alarm is normally
programmed to 0. For isochronous traffic, the alarm is programmed to allow streaming
operation to occur on the isochronous endpoint.
20.7.1.6
FIFO Sizes
FIFO sizes must be programmed to match the traffic sent across the USB. The USB_MCR register
allows software to choose which memory configuration is to be used at any given time.
20.7.1.7
Enable the Device
The last step in initializing the USB device is to enable it for processing via the USB_CR register.
Set the USBSPD bit appropriately for full or low speed operation(full speed operation) and set the
USBENA (module enable) bit.
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Note that the USBSPD bit must not be changed after the initial USB device configuration,
otherwise unpredictable operation of the USB may result.
20.7.2 Exception Handling
Exception handling refers to two situations. The first occurs when corrupted frames must be
discarded. The second is when an error situation occurs on the USB.
Corrupted frames are automatically discarded by the hardware. No software intervention is
required to deal with this problem.
If the device cannot respond to the host in the time allotted, hardware automatically handles retries.
No software intervention is required in this case.
The following types of error situations can arise and must be dealt with by the software:
20.7.2.1
Unable to Complete Device Request
In the event that the software receives a device request that it cannot interpret, it asserts the
CMD_ERROR and CMD_OVER bits back to the USB device. This results in a STALL to the
endpoint in question and requires intervention from the USB host to clear. When the CMD_OVER
bit clears, it indicates that the USB host has cleared the stall condition.
20.7.2.2
Aborted Device Request
When the host sends a setup packet to the device, it is possible that the ACK handshake from the
device could be corrupted, and lost on its way back to the host. In this case, the host will retry the
setup packet. In this case, the device can wind up with two or more setup packets in its FIFO. There
are two ways to detect this condition:
•
•
the presence of MDEVREQ interrupt
the SIP bit in the endpoint status register (USB_EPnSR) is active.
In either case, the presence of more than one setup packet causes the device to invalidate all
packets except the last one in the FIFO. Once a packet is acknowledged, no more are sent.
In the case that MDEVREQ is active, software must discard the first packet, and process the
second one. In the case of SIP active, software must discard the first one, clear the device request,
and wait for the device request to reassert.
20.7.2.3
Unable to Fill or Empty FIFO Due to Temporary Problem
If the USB device is unable to fill or empty a FIFO due to a temporary problem (for example the
operating system did not service the FIFO in time and it overflowed), the software should stall the
endpoint via the STALL bit in the endpoint control register. This will abort the transfer in progress
and force intervention from the USB host to clear the stall condition. The STALL register bit
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automatically clears once the stall condition takes effect. It is up to the application software on the
host to deal with the stall condition and notify the device as to how it should proceed.
20.7.2.4
Catastrophic Error
In the case of a catastrophic error, the software should execute a hard reset, reinitialize the USB
device, and wait for the USB host to re-enumerate the bus.
20.7.3 Data Transfer Operations
Three types of data transfer modes exist for this USB device: control transfers, bulk transfers, and
isochronous transfers. In addition to the three data transfer modes listed, the USB specification
also supports an interrupt transfer. From the point of view of the USB device, the interrupt transfer
type is identical to the bulk data transfer mode, and no additional hardware is supplied to support
it. This section covers the transfer modes and how they work from the ground up.
All data is moved across the USB in terms of packets. Groups of packets are combined to form
data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control
transfers. Isochronous data is also moved in the form of packets, but since isochronous pipes are
given a fixed portion of the USB bandwidth at all time, there is no concept of an end of transfer.
20.7.3.1
USB Packets
Data moves across the USB in units called packets. Packets range in size from 0 to 1023 bytes,
and, depending on the transfer mode the packet size, is restricted to a small set of values. For bulk,
control, and interrupt traffic, packet sizes are limited to 8, 16, 32, or 64 bytes. Isochronous data
packets can take any size from 0 to 1023 bytes. The packet size is programmable within the USB
device on an endpoint by endpoint basis.
The terms packet and frame are used interchangeably within this document. While USB traffic
occurs in units called packets, the FIFO mechanism uses the term frames for the same blocks of
data. The only difference between frames and packets from the user’s standpoint is that packets
may be as little as zero bytes in length, while a frame must be at least one byte in length.
20.7.3.1.1 Short Packets
Each endpoint has a maximum packet size associated with it. In most cases, packets transferred
across an endpoint will be sent at the maximum size. Since the USB does not indicate a data
transfer size, or include an end of transfer token, short packets are used to mark the end of data.
Software indicates end of data by writing short packets into the FIFO. Incoming short packets are
indicated by examining the length of a received packet or by looking at the end of transfer and end
of frame interrupts.
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20.7.3.1.2 Sending Packets
To send a packet of data to the USB host using programmed I/O, use these steps:
1. For an N byte packet, write the first N-1 bytes to the FIFO data register (USB_EPnFDR).
Data may be written as bytes, words, or longwords.
2. For the Nth byte, set the WFR bit in the USB_EPnFCR register, then write the last data
byte to the USB_EPnFDR register. Note that data is written in big-endian format. The
most significant byte(byte 0) is held in bits 31 to 24.
20.7.3.1.3 Receiving Packets
To receive a packet of data from the USB host, either DMA or programmed I/O may be used.
For programmed I/O, follow these steps:
1. Monitor EOF interrupt for the endpoint.
2. On receiving EOF interrupt, prepare to read a complete packet of data. Clear the EOF
interrupt so that software will receive notification of the next frame.
3. Read the USB_EPnFDR register to read in the next piece of data.
4. Read the USB_EPnFSR register to get the end of frame status bits. If the end of frame bit
is set for the current transfer, then stop reading data.
5. Go back to step 3.
20.7.3.1.4 Programming the FIFO Controller
The FIFO controller module has two modes of operation, frame and non-frame. For the USB
application, normally only frame mode is used.
In frame mode, the FIFO controller can handle automatic hardware retry of bad packets. This
mode is used for bulk, control, and interrupt endpoints. During device initialization, the user
should configure the FIFOs via the USB_EPnFCR register for FRAME mode. Data flow is
controlled with the end of frame (EOF) and end of transfer (EOT) interrupts, or with the DMA
request lines.
20.7.3.2
USB Transfers
Data transfers on the USB system are composed of one or more packets. Instead of maintaining a
transfer count, the USB host and device send groups of packets to each other in units called
transfers. In a transfer, all packets are the same size, except the last one. The last packet in a
transfer will be a short packet, as small as 0 bytes in the case that the last data byte ends on a packet
boundary.
This section describes how data transfers work from both the device to the host, and from the host
to the device.
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20.7.3.2.1 Data Transfers to the Host
Given an arbitrary sized block of data to be sent to the host, break it into a number of packets sized
at the maximum packet size of the target endpoint.
If number of bytes in the transfer is evenly divisible by the number of bytes in the maximum packet
size, then the transfer ends on a packet boundary. A zero length packet will be required to terminate
the transfer. If the number of bytes in the transfer is not evenly divisible by the maximum packet
size, then the last packet of the transfer will be a short packet and no zero length packet is required.
For each packet in the transfer, write the data to the USB_EPnFDR register. The last byte in each
packet must be tagged with the end of frame marker via the USB_EPnFCR register or comm
service request lines. Monitor the FIFO_LOW interrupt, EOF interrupt, or comm service requests
to determine when the FIFO can accept another packet.
After the last byte of the transfer has been written to the FIFO, if a zero length packet is required
to terminate the transfer, then set the ZLPS bit for the endpoint.
Wait for the EOT interrupt to determine when the transfer has completed.
20.7.3.2.2 Data Transfers to the Device
The length of data transfer from the host is generally not known in advance. The device receives
a continuous stream of packets and uses the EOT interrupt to determine when the transfer ended.
Software on the device monitors the EOF interrupt and/or the comm DMA requests to manage
packet traffic. Each time a packet is received, the device must pull the data from the FIFO. Each
time an end of frame is transferred from the USB device into the data FIFO, the EOF interrupt
asserts. At the end of a complete transfer, the EOT interrupt asserts. Until the CPU has serviced
the EOT interrupt, the device will NAK any further requests from the host. This guarantees that
data from two different transfers will never get intermixed within the FIFO.
20.7.3.3
Control Transfers
The USB host sends commands to the device via control transfers. Control transfers may be
addressed to any control endpoint. Control transfers consist of up to three distinct phases. Each
control transfer begins with a setup phase, followed by an optional data phase, and is completed
with a status phase. Command processing occurs in the following steps:
1. SETUP packet received on control endpoint. DEVREQ, and EOF interrupts assert for that
endpoint.
2. Read 8 bytes of the setup packet from the appropriate FIFO data register and decode the
command.
3. Clear EOF and DEVREQ interrupts.
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4. If a data transfer is implied by the command, set up and perform the data transfer. Be
careful not to send back more bytes to the USB host than were requested in the wLength
field of the SETUP packet. Hardware does not check for incorrect data phase length. The
EOT interrupt will assert on completion of the data phase.
5. Assert CMD_OVER/CMD_ERROR bits to indicate processing or error status. The USB
device will generate appropriate handshakes on the USB to implement the status phase.
CMD_OVER automatically clears at the end of the status phase.
6. Wait for CMD_OVER to clear, indicating that the device request has completed.
The MCF5275 USB device will handle all of the standard requests without software intervention.
User software does not need to be concerned with handling any of the so-called "Chapter 9"
requests listed in the USB specification, except for SYNCH_FRAME.
20.7.3.4
Bulk Traffic
Bulk traffic guarantees the error-free delivery of data in the order that it was sent, but the rate of
transfer is not guaranteed. Bandwidth is allocated to bulk, interrupt, and control packets based on
the bandwidth usage policy of the USB host.
20.7.3.4.1 Bulk OUT
For OUT transfers (from host to device), internal logic marks the start of packet location in the
FIFO. If a transfer does not complete without errors, the logic will force the FIFO to back up to
the start of the current packet and try again. No software intervention is required to handle packet
retries.
User software reads packets from the FIFOs as they appear and stops when an EOT interrupt is
received. To enable further data transfers, software services and clears the pending interrupts (EOF
or EOT), then waits for the next transfer to begin.
20.7.3.4.2 Bulk IN
For IN transfers (from device to host), software tags the last byte in a packet to mark the end of
frame. If a transfer does not complete without errors, hardware will automatically force the FIFO
to back up to the start of the current packet and re-send the data. User software is expected to write
data to the FIFO data register in units of the associated endpoint’s maximum packet size. The end
of frame may be indicated via the WFR bit in the endpoint FIFO control register (USB_EPnFCR).
In the USB protocol, the last packet in a transfer is allowed to be short (smaller than endpoint’s
maximum packet size) or even zero length. In order to indicate a zero length packet, the software
should set the ZLPS bit in the associated endpoint’s control register. The ZLPS bit automatically
clears after the zero length packet has been successfully sent to the host.
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The EOT interrupt asserts to indicate that the last packet of the IN transfer has completed. Software
should clear any pending interrupts (EOT and EOF) to begin the next data transfer.
20.7.3.5
Interrupt Traffic
Interrupt endpoints are a special case of bulk traffic. Interrupt endpoints are serviced on a periodic
basis by the USB host. Interrupt endpoints are guaranteed to transfer one packet per polling
interval. Thus, an endpoint with an 8 byte packet size and serviced every 2 ms would move
32 Kbps across the USB.
The only difference between interrupt transfers and bulk transfers from the device standpoint is
that every time an interrupt packet is transferred, regardless of size, the EOT interrupt asserts. The
device driver software must service this interrupt before the next interrupt servicing interval to
prevent the device from NAK’ing the poll.
Device driver software must be careful that the interrupt endpoint polling interval is longer than
the device’s interrupt service latency.
20.7.3.6
Isochronous Operations
Isochronous operations are a special case of USB traffic. Instead of guaranteeing delivery with
unbounded latency, isochronous traffic flows over the bus at a guaranteed rate with no error
checking.
20.7.3.6.1 Isochronous Transfers in a Nutshell
The USB host guarantees an endpoint exactly one isochronous packet per frame. Isochronous
packets may range from 0 bytes to 1023 bytes. Please refer to the USB specification for more
information on isochronous transfer.
Given that isochronous packets may be as large as 1023 bytes, it may not be practical to implement
large FIFOs for each endpoint. Instead, the software drivers are responsible for keeping the FIFOs
serviced. Each time an IN or OUT request is received on an isochronous endpoint, the software
drivers must ensure that the correct amount of data can be transferred without allowing the FIFO
to go empty. If the FIFO goes empty during an isochronous packet transfer, the host will terminate
the packet immediately and the device loses its time slot until the next USB frame.
In order to allow the driver software to maintain synchronization with the USB host, the
USBCORE maintains a register which holds the current USB frame number. An interrupt is
asserted each time the frame number changes or when a specific USB frame number is received.
The interrupts are maskable.
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Chapter 21
Watchdog Timer Module
21.1
Introduction
The watchdog timer (WDT) is a 16-bit timer used to help software recover from runaway code.
The watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on
underflow. To prevent a reset, software must periodically restart the countdown by servicing the
watchdog.
21.1.1 Low-Power Mode Operation
This subsection describes the operation of the watchdog module in low-power modes and halted
mode of operation (by issuing a HALT instruction). Low-power modes are described in Chapter 8,
“Power Management.” Table 21-1 shows the watchdog module operation in the low-power
modes, and shows how this module may facilitate exit from each mode.
Table 21-1. Watchdog Module Operation in Low-power Modes
Low-power Mode
Watchdog Operation
Mode Exit
Wait
Normal if WCR[WAIT] cleared, stopped otherwise
Upon Watchdog reset
Doze
Normal if WCR[DOZE] cleared, stopped otherwise
Upon Watchdog reset
Stop
Stopped
No
In wait mode with the watchdog control register’s WAIT bit (WCR[WAIT]) set, watchdog timer
operation stops. In wait mode with the WCR[WAIT] bit cleared, the watchdog timer continues to
operate normally. In doze mode with the WCR[DOZE] bit set, the watchdog timer module
operation stops. In doze mode with the WCR[DOZE] bit cleared, the watchdog timer continues to
operate normally. Watchdog timer operation stops in stop mode. When stop mode is exited, the
watchdog timer continues to operate in its pre-stop mode state.
In halted mode (entered by issuing a HALT instruction) with the WCR[HALTED] bit set,
watchdog timer module operation stops. When halted mode is exited, watchdog timer operation
continues from the state it was in before entering halted mode, but any updates made in halted
mode remain. If the WCR[HALTED] bit is cleared, the watchdog timer continues to operate
normally after executing a HALT instruction. This is a debug feature available for the user
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21.1.2 Block Diagram
Internal Bus
16-bit WCNTR
Internal Bus
Clock
16-bit WSR
Count = 0
Divide by
4096
16-bit Watchdog Counter
EN
Reset
Load Counter
WAIT
DOZE
16-bit WMR
HALTED
Internal Bus
Figure 21-1. Watchdog Timer Block Diagram
21.2
Memory Map/Register Definition
This subsection describes the memory map and registers for the watchdog timer. The watchdog
timer has a IPSBAR offset for base address of 0x14_0000. Refer to Table 21-2 for an overview of
the watchdog memory map.
Table 21-2. Watchdog Timer Module Memory Map
IPSBAR Offset
1
[31:24]
[23:16]
[15:8]
Access1
[7:0]
0x14_0000
Watchdog Control Register (WCR)
Watchdog Modulus Register (WMR)
S
0x14_0004
Watchdog Count Register (WCNTR)
Watchdog Service Register (WSR)
S/U
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
21.2.1 Register Description
The watchdog timer programming model consists of these registers:
•
•
•
Watchdog control register (WCR), which configures watchdog timer operation
Watchdog modulus register (WMR), which determines the timer modulus
reload value
Watchdog count register (WCNTR), which provides visibility to the watchdog counter
value
MCF5275 Reference Manual, Rev. 2
21-2
Freescale Semiconductor
Memory Map/Register Definition
•
Watchdog service register (WSR), which requires a service sequence to
prevent reset
21.2.1.1 Watchdog Control Register (WCR)
The 16-bit WCR configures watchdog timer operation.
R
15
14
13
12
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
WAIT DOZE HALTED
0
EN
W
Reset
Address
1
1
1
1
IPSBAR + 0x14_0000
Figure 21-2. Watchdog Control Register (WCR)
Table 21-3. WCR Field Descriptions
Bits
Name
Description
15–4
—
3
WAIT
Wait mode bit. Controls the function of the watchdog timer in wait mode. Once written, the
WAIT bit is not affected by further writes except in halted mode. Reset sets WAIT.
0 Watchdog timer not affected in wait mode
1 Watchdog timer stopped in wait mode
2
DOZE
Doze mode bit. Controls the function of the watchdog timer in doze mode. Once written,
the DOZE bit is not affected by further writes except in halted mode. Reset sets DOZE.
0 Watchdog timer not affected in doze mode
1 Watchdog timer stopped in doze mode
1
HALTED
Halted mode bit. Controls the function of the watchdog timer in halted mode. Once written,
the HALTED bit is not affected by further writes except in halted mode.
During halted mode, watchdog timer registers can be written and read normally. When
halted mode is exited, timer operation continues from the state it was in before entering
halted mode, but any updates made in halted mode remain. If a write-once register is
written for the first time in halted mode, the register is still writable when halted mode is
exited.
0 Watchdog timer not affected in halted mode
1 Watchdog timer stopped in halted mode
Note: Changing the HALTED bit from 1 to 0 during halted mode starts the watchdog timer.
Changing the HALTED bit from 0 to 1 during halted mode stops the watchdog timer.
0
EN
Watchdog enable bit. Enables the watchdog timer. Once written, the EN bit is not affected
by further writes except in halted mode. When the watchdog timer is disabled, the
watchdog counter and prescaler counter are held in a stopped state.
0 Watchdog timer disabled
1 Watchdog timer enabled
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
21-3
Watchdog Timer Module
21.2.1.2 Watchdog Modulus Register (WMR)
15
14
13
12
11
10
9
8
R
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
WM
W
Reset
1
1
1
1
1
1
Address
1
1
IPSBAR + 0x14_0002
Figure 21-3. Watchdog Modulus Register (WMR)
Table 21-4. WMR Field Descriptions
Bits
Name
Description
15–0
WM
Watchdog modulus. Contains the modulus that is reloaded into the watchdog counter by a
service sequence. Once written, the WM[15:0] field is not affected by further writes except
in halted mode. Writing to WMR immediately loads the new modulus value into the
watchdog counter. The new value is also used at the next and all subsequent reloads.
Reading WMR returns the value in the modulus register.
Reset initializes the WM[15:0] field to 0xFFFF.
Note: The prescaler counter is reset anytime a new value is loaded into the watchdog
counter and also during reset.
21.2.1.3 Watchdog Count Register (WCNTR)
15
14
13
12
11
10
9
8
R
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
WC
W
Reset
1
1
Address
1
1
1
1
1
1
IPSBAR + 0x14_0004
Figure 21-4. Watchdog Count Register (WCNTR)
Table 21-5. WCNTR Field Descriptions
Bits
Name
Description
15–0
WC
Watchdog count field. Reflects the current value in the watchdog counter. Reading the
16-bit WCNTR with two 8-bit reads is not guaranteed to return a coherent value. Writing to
WCNTR has no effect, and write cycles are terminated normally.
21.2.1.4 Watchdog Service Register (WSR)
When the watchdog timer is enabled, writing 0x5555 and then 0xAAAA to WSR before the
watchdog counter times out prevents a reset. If WSR is not serviced before the timeout, the
watchdog timer sends a signal to the reset controller module that sets the RSR[WDR] bit and
asserts a system reset.
MCF5275 Reference Manual, Rev. 2
21-4
Freescale Semiconductor
Memory Map/Register Definition
Both writes must occur in the order listed before the timeout, but any number of instructions can
be executed between the two writes. However, writing any value other than 0x5555 or 0xAAAA
to WSR resets the servicing sequence, requiring both values to be written to keep the watchdog
timer from causing a reset.
15
14
13
12
11
10
9
8
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
WS
W
Reset
0
0
Address
0
0
0
0
0
0
IPSBAR + 0x0014_0006
Figure 21-5. Watchdog Service Register (WSR)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
21-5
Watchdog Timer Module
MCF5275 Reference Manual, Rev. 2
21-6
Freescale Semiconductor
Chapter 22
Pulse Width Modulation (PWM) Module
22.1
Introduction
This chapter describes the configuration and operation of the pulse width modulation (PWM)
module for the MCF5275 device. It includes a block diagram, programming model, and functional
description.
22.1.1 Overview
The PWM module shown in Figure 22-1, generates a synchronous series of pulses having
programmable period and duty cycle. With a suitable low-pass filter, the PWM can be used as a
digital-to-analog converter.
Internal Bus Clock
fsys/2
PWM Clocks
PWM Channels
Clock select
Channel 3
Period and Duty
Control
PWMOUT3
Counter
Channel 2
Period and Duty
Enable
PWMOUT2
Counter
Channel 1
Period and Duty
PWMOUT1
Counter
Polarity
Channel 0
Alignment
Period and Duty
PWMOUT0
Counter
Figure 22-1. PWM Block Diagram
Summary of the main features include:
•
•
•
•
•
Double-buffered period and duty cycle
Left or center aligned outputs
Four independent PWM modules
Byte-wide registers provide programmable duty cycle and period control
Four programmable clock sources
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
22-1
Pulse Width Modulation (PWM) Module
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module”) prior to configuring the PWM module.
22.2
Memory Map/Register Definition
This section describes the registers and control bits in the PWM module. There are four
independent PWM modules, each with its own control and counter registers. The memory map for
the PWM is shown in Table 22-1.
Table 22-1. PWM Module Memory Map
IPSBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x1D_0000
PWM Enable Register
(PWME)
PWM Polarity Register
(PWMPOL)
PWM Clock Select
Register (PWMCLK)
PWM Prescale Clock
Select Register
(PWMPRCLK)
0x1D_0004
PWM Center Align
Enable Register
(PWMCAE)
PWM Control Register
(PWMCTL)
Reserved
0x1D_0008
PWM Scale A Register
(PWMSCLA)
PWM Scale B Register
(PWMSCLB)
Reserved
0x1D_000C
PWM 0 Counter
Register (PWMCNT0)
PWM 1 Counter
Register (PWMCNT1)
0x1D_0010
Reserved
0x1D_0014
PWM 2 Period Register
(PWMPER2)
PWM 3 Period Register
(PWMPER3)
0x1D_0018
PWM 0 Duty Register
(PWMDTY0)
PWM 1 Duty Register
(PWMDTY1)
PWM 2 Counter
Register (PWMCNT2)
PWM 3 Counter
Register (PWMCNT3)
PWM 0 Period Register
(PWMPER0)
PWM 1 Period Register
(PWMPER1)
Reserved
PWM 2 Duty Register
(PWMDTY2)
PWM 3 Duty Register
(PWMDTY3)
22.2.1 PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEn) to start its waveform output. While in run mode,
if all four PWM channels are disabled, PWME[3:0] = 0, the prescaler counter shuts off for power
savings. See Section 22.3.2.1, “PWM Enable” for more information.
R
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
PWME3 PWME2 PWME1 PWME0
W
Reset
Address
0
0
0
0
IPSBAR + 0x1D_0000
Figure 22-2. PWM Enable Register (PWME)
MCF5275 Reference Manual, Rev. 2
22-2
Freescale Semiconductor
Memory Map/Register Definition
Table 22-2. PWME Field Descriptions
Bits
Name
7–4
—
3
PWME3
PWM channel 3 output enable. If enabled, the PWM signal becomes available at
PWMOUT3 when its corresponding clock source begins its next cycle.
0 PWM output disabled
1 PWM output enabled
2
PWME2
PWM channel 2 output enable. If enabled, the PWM signal becomes available at
PWMOUT2 when its corresponding clock source begins its next cycle. If PWMCTL[CON23]
is set, then this bit has no effect and PWMOUT2 is disabled.
0 PWM output disabled
1 PWM output enabled, if PWMCTL[CON23]=0
1
PWME1
PWM channel 1 output enable. If enabled, the PWM signal becomes available at
PWMOUT1 when its corresponding clock source begins its next cycle.
0 PWM output disabled
1 PWM output enabled
0
PWME0
PWM channel 0 output enable. If enabled, the PWM signal becomes available at
PWMOUT0 when its corresponding clock source begins its next cycle. If PWMCTL[CON01]
is set, then this bit has no effect and PWMOUT0 is disabled.
0 PWM output disabled
1 PWM output enabled, if PWMCTL[CON01]=0
Description
Reserved, should be cleared.
22.2.2 PWM Polarity Register (PWMPOL)
The starting polarity of each PWM channel waveform is determined by the associated
PWMPOL[PPOLn] bit. If the polarity is changed while a PWM signal is being generated, a
truncated or stretched pulse can occur during the transition.
R
7
6
5
4
3
2
1
0
0
0
0
0
PPOL3
PPOL2
PPOL1
PPOL0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x1D_0001
Figure 22-3. PWM Polarity Register (PWMPOL)
Table 22-3. PWMPOL Field Descriptions
Bits
Name
7–4
—
3–0
PPOLn
Description
Reserved, should be cleared.
PWM channel n polarity.
0 PWM channel n output is low at the beginning of the period, then goes high when the
duty count is reached
1 PWM channel n output is high at the beginning of the period, then goes low when the
duty count is reached
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
22-3
Pulse Width Modulation (PWM) Module
22.2.3 PWM Clock Select Register (PWMCLK)
Each PWM channel has the capability of selecting one of two clocks. For channels 0 and 1 the
clock choices are clock A or SA. For channels 2 and 3 the choices are clock B or SB. The clock
selection is done with the below PWMCLK[PCLKx] control bits. If a clock select is changed
while a PWM signal is being generated, a truncated or stretched pulse can occur during the
transition.
R
7
6
5
4
3
2
1
0
0
0
0
0
PCLK3
PCLK2
PCLK1
PCLK0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x1D_0002
Figure 22-4. PWM Clock Select Register (PWMCLK)
Table 22-4. PWMCLK Field Descriptions
Bits
Name
7–4
—
3–0
PCLKn
Description
Reserved, should be cleared.
PWM channel n clock select. Selects between one of two clock sources for each PWM
channel. See Section 22.2.4, “PWM Prescale Clock Select Register (PWMPRCLK)” and
Section 22.2.7, “PWM Scale A Register (PWMSCLA)” for more information on how the
different clock rates are generated.
PCLK3
(PWM3 Clock
Source)
PCLK2
(PWM2 Clock
Source)
PCLK1
(PWM1 Clock
Source)
PCLK0
(PWM0 Clock
Source)
0
B
B
A
A
1
SB
SB
SA
SA
22.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
The PWMPRCLK register selects the prescale clock source for clocks A and B independently. If
the clock prescale is changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
7
R
6
0
5
4
PCKB
3
2
0
1
0
PCKA
W
Reset
Address
0
0
0
0
0
0
0
0
IPSBAR + 0x1D_0003
Figure 22-5. PWM Prescale Clock Select Register (PWMPRCLK)
MCF5275 Reference Manual, Rev. 2
22-4
Freescale Semiconductor
Memory Map/Register Definition
Table 22-5. PWMPRCLK Field Descriptions
Bits
Name
7
—
6–4
PCKB
Description
Reserved, should be cleared.
3
—
2–0
PCKA
Clock B prescalar select. These three bits control the rate of Clock B which can be used for
PWM channels 2 and 3.
PCKB
Clock B Rate
000
Internal bus clock ÷ 20
001
Internal bus clock ÷ 21
...
...
111
Internal bus clock ÷ 27
Reserved, should be cleared.
Clock A prescalar select. These three bits control the rate of Clock A which can be used for
PWM channels 0 and 1.
PCKA
Clock A Rate
000
Internal bus clock ÷ 20
001
Internal bus clock ÷ 21
...
...
111
Internal bus clock ÷ 27
22.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains four control bits for the selection of center aligned outputs or left
aligned outputs for each PWM channel. Write these bits only when the corresponding channel is
disabled. See Section 22.3.2.5, “Left Aligned Outputs” and Section 22.3.2.6, “Center Aligned
Outputs” for a more detailed description of the PWM output modes.
R
7
6
5
4
3
2
1
0
0
0
0
0
CAE3
CAE2
CAE1
CAE0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x1D_0004
Figure 22-6. PWM Center Align Enable Register (PWMCAE)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
22-5
Pulse Width Modulation (PWM) Module
Table 22-6. PWMCAE Field Descriptions
Bits
Name
7–4
—
3–0
CAEn
Description
Reserved, should be cleared.
Center align enable for channel n.
0 Channel n operates in left aligned output mode
1 Channel n operates in center aligned output mode
22.2.6 PWM Control Register (PWMCTL)
The PWMCTL register provides various control of the PWM module. Change the CONnn bits
only when both corresponding channels are disabled. See Section 22.3.2.7, “PWM 16-Bit
Functions” for a more detailed description of the concatenation function.
R
7
6
5
4
3
2
1
0
0
0
CON23
CON01
PSWAI
PFRZ
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x1D_0005
Figure 22-7. PWM Control Register (PWMCTL)
Table 22-7. PWMCTL Field Descriptions
Bits
Name
7–6
—
5
CON23
Concatenates PWM channels 2 and 3 to form one 16-bit PWM channel.
0 Channels 2 and 3 are separate 8-bit PWMs
1 Concatenate PWM 2 and 3. Channel 2 becomes the high order byte and channel 3 the
low order byte. PWMOUT3 is the output for this 16-bit PWM signal, and PWMOUT2 is
disabled. The channel 3 clock select, polarity, center align enable, and enable bits control
this concatenated output.
4
CON01
Concatenates PWM channels 0 and 1 to form one 16-bit PWM channel.
0 Channels 0 and 1 are separate 8-bit PWMs
1 Concatenate PWM 0 and 1. Channel 0 becomes the high order byte and channel 1 the
low order byte. PWMOUT1 is the output for this 16-bit PWM signal, and PWMOUT0 is
disabled. The channel 1 clock select, polarity, center align enable, and enable bits control
this concatenated output.
3
PSWAI
PWM stops in wait mode. Disables the input clock to the prescaler while in wait mode.
0 Allow the clock to the prescaler while in wait mode
1 Stop the input clock to the prescaler whenever the core is in wait mode
2
PFRZ
PWM counters stop in freeze mode.
0 Allow PWM counters to continue while in freeze mode
1 Disable PWM input clock to the prescaler when the core is in freeze mode. Useful for
emulation as it allows the PWM function to be suspended.
1–0
—
Description
Reserved, should be cleared.
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
22-6
Freescale Semiconductor
Memory Map/Register Definition
22.2.7 PWM Scale A Register (PWMSCLA)
PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock
SA is generated according to the following equation:
Clock A
Clock SA = ----------------------------------------2 × PWMSCLA
Any value written to this register will cause the scale counter to load the new scale value
(PWMSCLA).
7
6
5
R
4
3
2
1
0
0
0
0
0
SCALEA
W
Reset
0
Address
0
0
0
IPSBAR + 0x1D_0008
Figure 22-8. PWM Scale A Register (PWMSCLA)
Table 22-8. PWMSCLA Field Descriptions
Bits
Name
7–0
SCALEA
Description
Part of divisor used to form Clock SA from Clock A.
SCALEA
Value
0x00
256
0x01
1
0x02
2
...
...
0xFF
255
22.2.8 PWM Scale B Register (PWMSCLB)
PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock
SB is generated according to the following equation:
Clock B
Clock SB = ---------------------------------------2 × PWMSCLB
Any value written to this register will cause the scale counter to load the new scale value
(PWMSCLB).
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
22-7
Pulse Width Modulation (PWM) Module
7
6
5
R
4
3
2
1
0
0
0
0
0
SCALEB
W
Reset
0
Address
0
0
0
IPSBAR + 0x1D_0009
Figure 22-9. PWM Scale B Register (PWMSCLB)
Table 22-9. PWMSCLB Field Descriptions
Bits
Name
7–0
SCALEB
Description
Divisor used to form Clock SB from Clock B.
SCALEB
Value
0x00
256
0x01
1
0x02
2
...
...
0xFF
255
22.2.9 PWM Channel Counter Registers (PWMCNTn)
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock
source, PWMCLK[PCLKn]. The user can read the counters at any time without affecting the count
or the operation of the PWM channel. Any value written to the counter causes the counter to reset
to 0x00, the counter direction to be set to up for center-aligned mode, the immediate load of both
duty and period registers with values from the buffers, and the output to change according to the
polarity bit.
The counter is also cleared at the end of the effective period (see Section 22.3.2.5, “Left Aligned
Outputs” and Section 22.3.2.6, “Center Aligned Outputs” for more details). When the channel is
disabled (PWMEn=0), the PWMCNTn register does not count. When a channel is enabled
(PWMEn=1), the associated PWM counter starts at the count in the PWMCNTn register. For more
detailed information on the operation of the counters, refer to Section 22.3.2.4, “PWM Timer
Counters.”
MCF5275 Reference Manual, Rev. 2
22-8
Freescale Semiconductor
Memory Map/Register Definition
7
6
5
4
R
3
2
1
0
0
0
0
0
COUNT
W
Reset
0
Address
0
0
0
IPSBAR + 0x1D_000C (PWM0); IPSBAR + 0x1D_000D (PWM1);
IPSBAR + 0x1D_000E (PWM2); IPSBAR + 0x1D_000F (PWM3)
Figure 22-10. PWM Counter Registers (PWMCNTn)
Table 22-10. PWMCNTn Field Descriptions
Bits
Name
7–0
COUNT
Description
Current value of the PWM up counter. Resest to zero when written.
22.2.10PWM Channel Period Registers (PWMPERn)
The PWM period registers determine the period of the associated PWM channel. Refer to
Section 22.3.2.3, “PWM Period and Duty” for more information.
Calculating the output period depends on the output mode (center aligned has twice the period as
left aligned mode) as well as PWMPERn. See the below equation:
PWM n period = Channel clock period × ( PWMCAE [ CAEn ] + 1 ) × PWMPERn
For Boundary Case programming values (e.g. PWMPERn = 0x00), please refer to
Section 22.3.2.8, “PWM Boundary Cases.”
7
6
5
4
R
3
2
1
0
1
1
1
1
PERIOD
W
Reset
1
Address
1
1
1
IPSBAR + 0x1D_0012 (PWM0); IPSBAR + 0x1D_0013 (PWM1);
IPSBAR + 0x1D_0014 (PWM2); IPSBAR + 0x1D_0015 (PWM3)
Figure 22-11. PWM Period Registers (PWMPERn)
Table 22-11. PWMPERn Field Descriptions
Bits
Name
Description
7–0
PERIOD
Period counter for the output PWM signal.
If PERIOD = 0x00, the PWMn output is always high (PPOLn=1) or always low (PPOLn=0).
See Section 22.3.2.8, “PWM Boundary Cases” for other special cases.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
22-9
Pulse Width Modulation (PWM) Module
22.2.11PWM Channel Duty Registers (PWMDTYn)
The PWM duty registers determine the duty cycle of the associated PWM channel. To calculate
the output duty cycle (high time as a percentage of period) for a particular channel:
PWMDTYn
Duty Cycle = ⎛⎝ 1 – PWMPOL [ PPOLn ] – -------------------------------⎞⎠ × 100%
PWMPERn
For Boundary Case programming values (e.g. PWMDTYn = 0x00 or PWMDTYn > PWMPERn),
please refer to Section Section 22.3.2.8, “PWM Boundary Cases”.
7
6
5
4
R
3
2
1
0
1
1
1
1
DUTY
W
Reset
Address
1
1
1
1
IPSBAR + 0x1D_0018 (PWM0); IPSBAR + 0x1D_0019 (PWM1);
IPSBAR + 0x1D_001A (PWM2); IPSBAR + 0x1D_001B (PWM3)
Figure 22-12. PWM Duty Registers (PWMDTYn)
Table 22-12. PWMDTYn Field Descriptions
22.3
Bits
Name
Description
7–0
DUTY
Contains the duty value used to determine when a transition will occur on the PWM output
signal. When a match occurs with the corresponding PWMCNTn register, the PWM output
will toggle.
If DUTY = 0x00, the PWMn output is always low (PPOLn=1) or always high (PPOLn=0).
See Section 22.3.2.8, “PWM Boundary Cases” for other special cases.
Functional Description
22.3.1 PWM Clock Select
There are four available clocks named Clock A, B, SA (Scaled A), and SB (Scaled B), all of which
are based on the internal bus clock.
Clock A and B can be programmed to run at 1, 1/2, ..., 1/128 times the internal bus clock. Clock
SA and SB use clock A and B respectively as an input and divides it further with a reloadable
counter. The rates available for clock SA and SB are programmable to run at clock A and B
divided by 2, 4, ..., or 512. Each PWM channel has the capability of selecting one of two clocks,
MCF5275 Reference Manual, Rev. 2
22-10
Freescale Semiconductor
Functional Description
either the prescaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram
in Figure 22-13 shows the four different clocks and how the scaled clocks are created.
PCLR3
Clock SB
1
PWMSCLB
÷2
0
PWMPRCLK
[PCKB]
1
0
Clock B
Internal
Bus Clock
(fsys/2)
Clock to
PWM3
Clock to
PWM2
PCLR2
Clock SA
PCLR1
1
PWMSCLA
÷2
0
PWMPRCLK
[PCKA]
1
0
Clock A
Clock to
PWM1
Clock to
PWM0
PCLR0
Figure 22-13. PWM Clock Select Block Diagram
22.3.1.1 Prescaled Clock (A or B)
The internal bus clock is the input clock to the PWM prescaler which can be disabled when the
device is in Freeze mode by setting the PWMCTL[PFRZ] bit. This is useful for reducing power
consumption and for emulation in order to freeze the PWM. The input clock is also be disabled
when all four PWM channels are disabled (PWMEn=0).
Clock A and B are scaled values of the input clock. The value is software selectable for both clock
A and B and has options of 1, 1/2, ..., or 1/128 times the internal bus clock. The value selected for
clock A and B are determined by the PWMPRCLK[PCKAn] and PWMPRCLK[PCKBn] bits.
22.3.1.2 Scaled Clock (SA or SB)
The scaled A (SA) and scaled B (SB) clocks uses clock A and B respectively as inputs and divide
it further with a user programmable value and then divide this by 2. The rates available for clock
SA are programmable to run at clock A divided by 2, 4, ..., or 512. Similar rates are available for
clock SB.
Clock SA equals Clock A divided by two times the value in the PWMSCLA register:
Clock A
Clock SA = ----------------------------------------2 × PWMSCLA
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Pulse Width Modulation (PWM) Module
Similarly, Clock SB is generated according to the following equation:
Clock B
Clock SB = ---------------------------------------2 × PWMSCLB
As an example, consider the case in which the user writes 0xFF into the PWMSCLA register.
Clock A for this case is selected to be internal bus clock divided by 4. A pulse will occur at a rate
of once every 255×4 bus cycles. Passing this through the divide by two circuit produces a clock
signal of the internal bus clock divided by 2040. Similarly, a value of 0x01 in the PWMSCLA
register when Clock A is internal bus clock divided by 4 will produce an internal bus clock divided
by 8 rate.
Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded.
Otherwise, when changing rates the counter would have to count down to 0x01 before counting at
the proper rate. Forcing the associated counter to re-load the scale register value every time
PWMSCLA or PWMSCLB is written prevents this.
Writing to the scale registers while channels are operating can cause irregularities in the PWM
outputs.
22.3.1.3 Clock Select
Each PWM channel has the capability of selecting one of two clocks. For channels 0 and 1 the
clock choices are clock A or SA. For channels 2 and 3 the choices are clock B or SB. The clock
selection is done with the PWMCLK[PCLKx] control bits.
Changing clock control bits while channels are operating can cause irregularities in the PWM
outputs.
22.3.2 PWM Channel Timers
The main part of the PWM module is the actual timers. Each of the timer channels has a counter,
a period register and a duty register (each are 8-bit). The waveform output period is controlled by
a match between the period register and the value in the counter. The duty is controlled by a match
between the duty register and the counter value and causes the state of the output to change during
the period. The starting polarity of the output is also selectable on a per channel basis. Figure 22-14
shows a block diagram for PWM timer.
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Freescale Semiconductor
Functional Description
Clock Source
From Figure 22-13
PWMDTYn
PWMCNTn
0
Up/Down
Reset
1
PWMOUTn
PWMEn
PPOLn
PWMPERn
PWMCAE = 1
PWMCAE = 0
Figure 22-14. PWM Timer Channel Block Diagram
22.3.2.1 PWM Enable
Each PWM channel has an enable bit (PWMEn) to start its waveform output. When any of the
PWMEn bits are set (PWMEn=1), the associated PWM output signal is enabled immediately.
However, the actual PWM waveform is not available on the associated PWM output until its clock
source begins its next cycle due to the synchronization of PWMEn and the clock source. An
exception to this is when channels are concatenated. Refer to Section 22.3.2.7, “PWM 16-Bit
Functions” for more detail.
Note that the first PWM cycle after enabling the channel can be irregular. When the channel is
disabled (PWMEn=0), the counter for the channel does not count.
22.3.2.2 PWM Polarity
Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This
is shown on the block diagram as a mux select. When one of the bits in the PWMPOL register is
set, the associated PWM channel output is high at the beginning of the waveform, then goes low
when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and
then goes high when the duty count is reached.
22.3.2.3 PWM Period and Duty
Dedicated period and duty registers exist for each channel and are double buffered so that if they
change while the channel is enabled, the change will not take effect until one of the following
occurs:
•
•
•
The effective period ends
The PWMCNTn register is written (counter resets to 0x00)
The channel is disabled, PWMEn = 0
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Pulse Width Modulation (PWM) Module
In this way, the output of the PWM will always be either the old waveform or the new waveform,
not some variation in between. If the channel is not enabled, then writes to the period and duty
registers will go directly to the latches as well as the buffer.
A change in duty or period can be forced into effect immediately by writing the new value to the
duty and/or period registers and then writing to the counter. This forces the counter to reset and
the new duty and/or period values to be latched. In addition, since the counter is readable it is
possible to know where the count is with respect to the duty value and software can be used to
make adjustments. When forcing a new period or duty into effect immediately, an irregular PWM
cycle can occur.
Depending on the polarity bit, the duty registers will contain the count of either the high time or
the low time.
22.3.2.4 PWM Timer Counters
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock
source (see Figure 22-13 for the available clock sources and rates). The counter compares to two
registers, a duty register and a period register as shown in Figure 22-14. When the PWM counter
matches the duty register the output flip-flop changes state causing the PWM waveform to also
change state. A match between the PWM counter and the period register behaves differently
depending on what output mode is selected as shown in Figure 22-14 and described in
Section 22.3.2.5, “Left Aligned Outputs” and Section 22.3.2.6, “Center Aligned Outputs”.
Each channel counter can be read at anytime without affecting the count or the operation of the
PWM channel.
Any value written to the counter causes the counter to reset to 0x00, the counter direction to be set
to up, the immediate load of both duty and period registers with values from the buffers, and the
output to change according to the polarity bit. When the channel is disabled (PWMEn = 0), the
counter stops. When a channel becomes enabled (PWMEn = 1), the associated PWM counter
continues from the count in the PWMCNTn register. This allows the waveform to continue where
it left off when the channel is re-enabled. When the channel is disabled, writing “0” to the period
register will cause the counter to reset on the next selected clock.
NOTE
If the user wants to start a new “clean” PWM waveform without any
“history” from the old waveform, the user must write to channel
counter (PWMCNTn) prior to enabling the PWM channel
(PWMEn = 1).
Generally, writes to the counter are done prior to enabling a channel in order to start from a known
state. However, writing a counter can also be done while the PWM channel is enabled (counting).
The effect is similar to writing the counter when the channel is disabled except that the new period
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
Functional Description
is started immediately with the output set according to the polarity bit. Writing to the counter while
the channel is enabled can cause an irregular PWM cycle to occur.
The counter is cleared at the end of the effective period (see Section 22.3.2.5, “Left Aligned
Outputs” and Section 22.3.2.6, “Center Aligned Outputs” for more details).
Table 22-13. PWM Timer Counter Conditions
Counter Clears (0x00)
Counter Counts
Counter Stops
When PWMCNTn register written to
any value
When PWM channel is enabled
(PWMEn = 1). Counts from last value
in PWMCNTn.
When PWM channel is disabled
(PWMEn = 0)
Effective period ends
22.3.2.5 Left Aligned Outputs
The PWM timer provides the choice of two types of outputs, Left Aligned or Center Aligned
outputs. They are selected with the PWMCAE[CAEn] bits. If the CAEn bit is cleared, the
corresponding PWM output will be left aligned.
In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to
two registers, a duty register and a period register as shown in the block diagram in Figure 22-14.
When the PWM counter matches the duty register the output flip-flop changes state causing the
PWM waveform to also change state. A match between the PWM counter and the period register
resets the counter and the output flip-flop as shown in Figure 22-14 as well as performing a load
from the double buffer period and duty register to the associated registers as described in
Figure 22.3.2.3. The counter counts from 0 to the value in the period register minus 1.
NOTE
Changing the PWM output mode from left aligned output to center
aligned output (or vice versa) while channels are operating can cause
irregularities in the PWM output. It is recommended to program the
output mode before enabling the PWM channel.
PPOLn = 0
PPOLn = 1
PWMDTYn
Period = PWMPERn
Figure 22-15. PWM Left Aligned Output Waveform
To calculate the output frequency in left aligned output mode for a particular channel, take the
selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the
period register for that channel.
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Pulse Width Modulation (PWM) Module
Clock (A, B, SA, or SB)
PWMn frequency = ---------------------------------------------------------PWMPERn
The PWMn duty cycle (high time as a percentage of period) is expressed as:
PWMDTYn
Duty Cycle = ⎛ 1 – PWMPOL [ PPOLn ] – -------------------------------⎞ × 100%
⎝
PWMPERn ⎠
22.3.2.5.1 Left Aligned Output Example
As an example of a left aligned output, consider the following case:
Clock Source = internal bus clock, where internal bus clock = 75MHz (13.33ns period)
PPOLn = 0, PWMPERn = 4, PWMDTYn = 1
PWMn Frequency = 75MHz ÷ 4 = 18.75MHz
PWMn Period = 53.33ns
1
PWMn Duty Cycle = ⎛ 1 – ---⎞ × 100% = 75%
⎝
4⎠
Shown below is the output waveform generated:
E = 13.33ns
DUTY CYCLE = 75%
PERIOD = 53.33ns
Figure 22-16. PWM Left Aligned Output Example Waveform
22.3.2.6 Center Aligned Outputs
For center aligned output mode selection, set the PWMCAE[CAEn] bit and the corresponding
PWM output will be center aligned.
The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the
counter is equal to 0x00. The counter compares to two registers, a duty register and a period
register as shown in the block diagram in Figure 22-14. When the PWM counter matches the duty
register the output flip-flop changes state causing the PWM waveform to also change state. A
match between the PWM counter and the period register changes the counter direction from an
up-count to a down-count. When the PWM counter decrements and matches the duty register
again, the output flip-flop changes state causing the PWM output to also change state. When the
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Freescale Semiconductor
Functional Description
PWM counter decrements and reaches zero, the counter direction changes from a down-count
back to an up-count and a load from the double buffer period and duty registers to the associated
registers is performed as described in Figure 22.3.2.3. The counter counts from 0 up to the value
in the period register and then back down to 0. Thus the effective period is PWMPERn × 2.
Changing the PWM output mode from left aligned output to center aligned output (or vice versa)
while channels are operating can cause irregularities in the PWM output. It is recommended to
program the output mode before enabling the PWM channel.
PPOLn = 0
PPOLn = 1
PWMDTYn
PWMDTYn
PWMPERn
PWMPERn
Period = PWMPERn × 2
Figure 22-17. PWM Center Aligned Output Waveform
To calculate the output frequency in center aligned output mode for a particular channel, take the
selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value
in the period register for that channel.
Clock (A, B, SA, or SB)
PWMn frequency = ---------------------------------------------------------2 × P WMPERn
The PWMn duty cycle (high time as a percentage of period) is expressed as:
PWMDTYn
Duty Cycle = ⎛⎝ 1 – PWMPOL [ PPOLn ] – -------------------------------⎞⎠ × 100%
PWMPERn
22.3.2.6.1 Center Aligned Output Example
As an example of a center aligned output, consider the following case:
Clock Source = internal bus clock, where internal bus clock=75MHz (13.3ns period)
PPOLn = 0, PWMPERn = 4, PWMDTYn = 1
PWMn Frequency = 75MHz/(2x4) = 9.38MHz
PWMn Period = 106.67ns
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Freescale Semiconductor
22-17
Pulse Width Modulation (PWM) Module
1
PWMn Duty Cycle = ⎛ 1 – ---⎞ × 100% = 75%
⎝
4⎠
Shown below is the output waveform generated.
E=13.33ns
E=13.33ns
DUTY CYCLE = 75%
PERIOD = 106.67ns
Figure 22-18. PWM Center Aligned Output Example Waveform
22.3.2.7 PWM 16-Bit Functions
The PWM timer also has the option of generating 4-channels of 8-bits or 2-channels of 16-bits for
greater PWM resolution}. This 16-bit channel option is achieved through the concatenation of two
8-bit channels.
The PWMCTL register contains two concatenation control bits, each of which is used to
concatenate a pair of PWM channels into one 16-bit channel. Channels 2 and 3 are concatenated
with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit. Change these bits
only when both corresponding channels are disabled.
As shown in Figure 22-19, when channels 2 and 3 are concatenated, channel 2 registers become
the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel
0 registers become the high order bytes of the double byte channel.
When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit
channel clock select control bits. That is channel 3 when channels 2 and 3 are concatenated, and
channel 1 when channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the
corresponding low order 8-bit channel as also shown in Figure 22-19. The polarity of the resulting
PWM output is controlled by the PPOLn bit of the corresponding low order 8-bit channel as well.
Once concatenated mode is enabled (PWMCTL[CONnn] bits set) then enabling/disabling the
corresponding 16-bit PWM channel is controlled by the low order PWMEn bit. In this case, the
high order bytes PWMEn bits have no effect and their corresponding PWM output is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the
low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must
be made by 16-bit access to maintain data coherency.
MCF5275 Reference Manual, Rev. 2
22-18
Freescale Semiconductor
Functional Description
Clock Source 3
High
Low
PWMCNT2
PWCNT3
Period/Duty Compare
PWMOUT3
Clock Source 1
High
Low
PWMCNT0
PWCNT1
Period/Duty Compare
PWMOUT1
Figure 22-19. PWM 16-Bit Mode
Either left aligned or center aligned output mode can be used in concatenated mode and is
controlled by the low order CAEn bit. The high order CAEn bit has no effect.
The table shown below is used to summarize which channels are used to set the various control
bits when in 16-bit mode.
Table 22-14. 16-bit Concatenation Mode Summary
CONnn
PWMEn
PPOLn
PCLKn
CAEn
PWMn
Output
CON23
PWME3
PPOL3
PCLK3
CAE3
PWMOUT3
CON01
PWME1
PPOL1
PCLK1
CAE1
PWMOUT1
22.3.2.8 PWM Boundary Cases
The following table summarizes the boundary conditions for the PWM regardless of the output
mode (Left Aligned or Center Aligned) and 8-bit (normal) or 16-bit (concatenation):
Table 22-15. PWM Boundary Cases
PWMDTYn
PWMPERn
PPOLn
PWMn Output
0x00
(indicates no duty)
>0x00
1
Always Low
0x00
(indicates no duty)
>0x00
0
Always High
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22-19
Pulse Width Modulation (PWM) Module
Table 22-15. PWM Boundary Cases
PWMDTYn
PWMPERn
PPOLn
PWMn Output
XX
0x00 1
(indicates no period)
1
Always High
XX
0x001
(indicates no period)
0
Always Low
>= PWMPERn
XX
1
Always High
>= PWMPERn
XX
0
Always Low
1Counter=0x00
and does not count.
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Freescale Semiconductor
Chapter 23
Programmable Interrupt Timer Modules
(PIT0–PIT3)
23.1
Introduction
This chapter describes the operation of the four programmable interrupt timer modules,
PIT0–PIT3.
23.1.1 Overview
The PIT is a 16-bit timer that provides precise interrupts at regular intervals with minimal
processor intervention. The timer can either count down from the value written in the modulus
register, or it can be a free-running down-counter.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module”) prior to configuring the PIT modules.
23.1.2 Block Diagram
Internal Bus
16-bit PCNTRn
Internal Bus
Clock (fsys/2)
Prescaler
16-bit PIT Counter
COUNT = 0
PIF
Load
Counter
EN
PRE[3:0]
To Interrupt
Controller
PIE
OVW
RLD
DOZE
DBG
16-bit PMRn
Internal Bus
Figure 23-1. PIT Block Diagram
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Freescale Semiconductor
23-1
Programmable Interrupt Timer Modules (PIT0–PIT3)
23.1.3 Low-Power Mode Operation
This subsection describes the operation of the PIT modules in low-power modes and debug mode
of operation. Low-power modes are described in the Power Management Module. Table 23-1
shows the PIT module operation in low-power modes, and how it can exit from each mode.
NOTE
The low-power interrupt control register (LPICR) in the System
Control Module specifies the interrupt level at or above which the
device can be brought out of a low-power mode.
Table 23-1. PIT Module Operation in Low-power Modes
Low-power Mode
PIT Operation
Wait
Normal
Doze
Mode Exit
N/A
Normal if PCSRn[DOZE] cleared, Any IRQn Interrupt at or above level in LPICR
stopped otherwise
Stop
Stopped
Debug
Normal if PCSRn[DBG] cleared,
stopped otherwise
No
No. Any IRQn Interrupt will be serviced upon
normal exit from debug mode
In wait mode, the PIT module continues to operate as in run mode and can be configured to exit
the low-power mode by generating an interrupt request. In doze mode with the PCSRn[DOZE] bit
set, PIT module operation stops. In doze mode with the PCSRn[DOZE] bit cleared, doze mode
does not affect PIT operation. When doze mode is exited, the PIT continues to operate in the state
it was in prior to doze mode. In stop mode, the system clock is absent, and PIT module operation
stops.
In debug mode with the PCSRn[DBG] bit set, PIT module operation stops. In debug mode with
the PCSRn[DBG] bit cleared, debug mode does not affect PIT operation. When debug mode is
exited, the PIT continues to operate in its pre-debug mode state, but any updates made in debug
mode remain.
23.2
Memory Map/Register Definition
This section contains a memory map, shown in Table 23-2, and describes the register structure for
PIT0–PIT3.
Table 23-2. Programmable Interrupt Timer Modules Memory Map
IPSBAR Offset
[31:24]
[23:16]
[15:8]
[7:0]
Access1
0x15_0000
PIT Control and Status Register
(PCSR0)
PIT Modulus Register (PMR0)
S
0x15_0004
PIT Count Register (PCNTR0)
Reserved2
S/U
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Freescale Semiconductor
Memory Map/Register Definition
Table 23-2. Programmable Interrupt Timer Modules Memory Map (Continued)
IPSBAR Offset
[31:24]
[23:16]
0x15_0008–
0x15_FFFF
[15:8]
Access1
[7:0]
Reserved
—
0x16_0000
PIT Control and Status Register
(PCSR1)
PIT Modulus Register (PMR1)
S
0x16_0004
PIT Count Register (PCNTR1)
Reserved2
S/U
0x16_0008–
0x16_FFFF
Reserved
—
0x17_0000
PIT Control and Status Register
(PCSR2)
PIT Modulus Register (PMR2)
S
0x17_0004
PIT Count Register (PCNTR2)
Reserved2
S/U
0x17_0008–
0x17_FFFF
Reserved
—
0x18_0000
PIT Control and Status Register
(PCSR3)
PIT Modulus Register (PMR3)
S
0x18_0004
PIT Count Register (PCNTR3)
Reserved2
S/U
0x18_0008–
0x18_FFFF
Reserved
—
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
2 Accesses to reserved address locations have no effect and result in a cycle termination transfer error.
23.2.1 Register Description
The PIT programming model consists of these registers:
•
•
•
The PIT control and status register (PCSRn) configures the timer’s operation.
The PIT modulus register (PMRn) determines the timer modulus reload value.
The PIT count register (PCNTRn) provides visibility to the counter value.
23.2.1.1 PIT Control and Status Register (PCSRn)
R
15
14
13
12
0
0
0
0
0
0
0
0
11
10
9
8
PRE
7
0
6
5
4
DOZE DBG OVW
3
2
1
0
PIE
PIF
RLD
EN
0
0
0
0
W
Reset
Address
0
0
0
0
0
0
0
0
IPSBAR + 0x0015_0000 (PIT0); IPSBAR + 0x0016_0000 (PIT1);
IPSBAR + 0x0017_0000 (PIT2); IPSBAR + 0x0018_0000 (PIT3)
Figure 23-2. PIT Control and Status Register (PCSRn)
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Freescale Semiconductor
23-3
Programmable Interrupt Timer Modules (PIT0–PIT3)
Table 23-3. PCSRn Field Descriptions
Bits
Name
15–12
—
11–8
PRE
Description
Reserved, should be cleared.
Prescaler. The read/write prescaler bits select the system clock divisor to generate the PIT
clock. To accurately predict the timing of the next count, change the PRE[3:0] bits only
when the enable bit (EN) is clear. Changing PRE[3:0] resets the prescaler counter. System
reset and the loading of a new value into the counter also reset the prescaler counter.
Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing
the EN bit stops the prescaler counter.
PRE
System Clock Divisor
0000
20
0001
21
0010
22
...
...
1101
213
1110
214
1111
215
7
—
Reserved, should be cleared.
6
DOZE
5
DBG
Debug mode bit. Controls the function of the PIT in debug mode. Reset clears DBG. During
debug mode, register read and write accesses function normally. When debug mode is
exited, timer operation continues from the state it was in before entering debug mode, but
any updates made in debug mode remain.
0 PIT function not affected in debug mode
1 PIT function stopped in debug mode
Note: Changing the DBG bit from 1 to 0 during debug mode starts the PIT timer. Likewise,
changing the DBG bit from 0 to 1 during debug mode stops the PIT timer.
4
OVW
Overwrite. Enables writing to PMRn to immediately overwrite the value in the PIT counter.
0 Value in PMRn replaces value in PIT counter when count reaches 0x0000.
1 Writing PMRn immediately replaces value in PIT counter.
3
PIE
PIT interrupt enable. This read/write bit enables the PIF flag to generate interrupt requests.
0 PIF interrupt requests disabled
1 PIF interrupt requests enabled
2
PIF
PIT interrupt flag. This read/write bit is set when the PIT counter reaches 0x0000. Clear
PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF.
0 PIT count has not reached 0x0000.
1 PIT count has reached 0x0000.
Doze mode bit. The read/write DOZE bit controls the function of the PIT in doze mode.
Reset clears DOZE.
0 PIT function not affected in doze mode
1 PIT function stopped in doze mode
When doze mode is exited, timer operation continues from the state it was in before
entering doze mode.
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Freescale Semiconductor
Memory Map/Register Definition
Table 23-3. PCSRn Field Descriptions (Continued)
Bits
Name
1
RLD
0
EN
Description
Reload bit. The read/write reload bit enables loading the value of PMRn into the PIT
counter when the count reaches 0x0000.
0 Counter rolls over to 0xFFFF on count of 0x0000
1 Counter reloaded from PMRn on count of 0x0000
PIT enable bit. Enables PIT operation. When the PIT is disabled, the counter and prescaler
are held in a stopped state. This bit is read anytime, write anytime.
0 PIT disabled
1 PIT enabled
23.2.1.2 PIT Modulus Register (PMRn)
The 16-bit read/write PMRn contains the timer modulus value that is loaded into the PIT counter
when the count reaches 0x0000 and the PCSRn[RLD] bit is set.
When the PCSRn[OVW] bit is set, PMRn is transparent, and the value written to PMRn is
immediately loaded into the PIT counter. The prescaler counter is reset anytime a new value is
loaded into the PIT counter and also during reset. Reading the PMRn returns the value written in
the modulus latch. Reset initializes PMRn to 0xFFFF.
15
14
13
12
11
10
9
8
R
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
PM
W
Reset
1
1
1
Address
1
1
1
1
1
IPSBAR + 0x0015_0002 (PIT0);IPSBAR + 0x0016_0002 (PIT1);
IPSBAR + 0x0017_0002 (PIT2); IPSBAR + 0x0018_0002 (PIT3)
Figure 23-3. PIT Modulus Register (PMRn)
23.2.1.3 PIT Count Register (PCNTRn)
The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two
8-bit reads is not guaranteed to be coherent. Writing to PCNTRn has no effect, and write cycles
are terminated normally.
15
14
13
12
11
10
9
8
R
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
PC
W
Reset
1
1
Address
1
1
1
1
1
1
IPSBAR + 0x0015_0004 (PIT0), IPSBAR + 0x0016_0004 (PIT1),
IPSBAR + 0x0017_0004 (PIT2), IPSBAR + 0x0018_0004 (PIT3)
Figure 23-4. PIT Count Register (PCNTR)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
23-5
Programmable Interrupt Timer Modules (PIT0–PIT3)
23.3
Functional Description
This section describes the PIT functional operation.
23.3.1 Set-and-Forget Timer Operation
This mode of operation is selected when the RLD bit in the PCSR register is set.
When the PIT counter reaches a count of 0x0000, the PIF flag is set in PCSRn. The value in the
modulus register is loaded into the counter, and the counter begins decrementing toward 0x0000.
If the PCSRn[PIE] bit is set, the PIF flag issues an interrupt request to the CPU.
When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn
without having to wait for the count to reach 0x0000.
PIT CLOCK
COUNTER
0x0002
0x0001
MODULUS
0x0000
0x0005
0x0005
PIF
Figure 23-5. Counter Reloading from the Modulus Latch
23.3.2 Free-Running Timer Operation
This mode of operation is selected when the PCSRn[RLD] bit is clear. In this mode, the counter
rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to
decrement.
When the counter reaches a count of 0x0000, the PCSRn[PIF] flag is set. If the PCSRn[PIE] bit is
set, the PIF flag issues an interrupt request to the CPU.
When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn
without having to wait for the count to reach 0x0000.
PIT CLOCK
COUNTER
MODULUS
0x0002
0x0001
0x0000
0xFFFF
0x0005
PIF
Figure 23-6. Counter in Free-Running Mode
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23-6
Freescale Semiconductor
Functional Description
23.3.3 Timeout Specifications
The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the
internal bus clock period as selected by the PCSRn[PRE] bits. The PMRn[PM] bits select the
timeout period.
PRE[3:0] × (PM[15:0] + 1)Timeout period = -----------------------------------------------------------------------------------f sys ⁄ 2
23.3.4 Interrupt Operation
Table 23-4 shows the interrupt request generated by the PIT.
Table 23-4. PIT Interrupt Requests
Interrupt Request
Flag
Enable Bit
Timeout
PIF
PIE
The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to
generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
23-7
Programmable Interrupt Timer Modules (PIT0–PIT3)
MCF5275 Reference Manual, Rev. 2
23-8
Freescale Semiconductor
Chapter 24
Queued Serial Peripheral Interface (QSPI)
Module
24.1 Introduction
This chapter describes the queued serial peripheral interface (QSPI) module. Following a feature
set overview is a description of operation including details of the QSPI’s internal RAM
organization. The chapter concludes with the programming model and a timing diagram.
24.1.1 Overview
The queued serial peripheral interface module provides a serial peripheral interface with queued
transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU
intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address
and data registers.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module”) prior to configuring the QSPI Module.
24.1.2 Features
•
•
•
•
•
•
•
Programmable queue to support up to 16 transfers without user intervention
Supports transfer sizes of 8 to 16 bits in 1-bit increments
Four peripheral chip-select lines for control of up to 15 devices
Baud rates from 162.7 Kbps to 20.75 Mbps at 83 MHz
Programmable delays before and after transfers
Programmable QSPI clock phase and polarity
Supports wraparound mode for continuous transfers
24.1.3 Module Description
The QSPI module communicates with the integrated ColdFire CPU using internal memory
mapped registers starting at IPSBAR + 0x340. See Section 24.3, “Memory Map/Register
Definition.” A block diagram of the QSPI module is shown in Figure 24-1.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
24-1
Queued Serial Peripheral Interface (QSPI) Module
24.1.3.1 Interface and Signals
The module provides access to as many as 15 devices with a total of seven signals: QSPI_DOUT,
QSPI_DIN, QSPI_CLK, QSPI_CS0, QSPI_CS1, QSPI_CS2, and QSPI_CS3.
Peripheral chip-select signals, QSPI_CS[3:0], are used to select an external device as the source
or destination for serial data transfer. Signals are asserted at a logic level corresponding to the
value of the QSPI_CS[3:0] bits in the command RAM whenever a command in the queue is
executed. More than one chip-select signal can be asserted simultaneously.
Although QSPI_CS[3:0] will function as simple chip selects in most applications, up to 15 devices
can be selected by decoding them with an external 4-to-16 decoder.
Queue Control
Block
4
Queue
Pointer
80-Byte
QSPI
RAM
Done
Comparator
QSPI
Address
Register
End Queue
Pointer
QSPI
Data
Register
4
4
Control Logic
Chip
Select
Status
Regs
lsb
QSPI_DIN
8/16 Bit Shift Reg.
Rx/Tx Data Reg.
Logic
Array
Control
Regs
msb
4
QSPI_DOUT
Command
4
Delay
Counter
QSPI_CS[3:0]
Internal Bus
Internal Bus
Clock (fsys/2)
Baud Rate
Generator
Divide by 2
QSPI_CLK
Figure 24-1. QSPI Block Diagram
Table 24-1. QSPI Input and Output Signals and Functions
Signal Name
Hi-Z or Actively Driven
Function
QSPI Data Output (QSPI_DOUT)
Configurable
Serial data output from QSPI
QSPI Data Input (QSPI_DIN)
N/A
Serial data input to QSPI
MCF5275 Reference Manual, Rev. 2
24-2
Freescale Semiconductor
Operation
Table 24-1. QSPI Input and Output Signals and Functions (Continued)
Signal Name
Hi-Z or Actively Driven
Function
Serial Clock (QSPI_CLK)
Actively driven
Clock output from QSPI
Peripheral Chip Selects (QSPI_CS[3:0])
Actively driven
Peripheral selects
24.1.4 Internal Bus Interface
Because the QSPI module only operates in master mode, the master bit in the QSPI mode register,
QMR[MSTR], must be set for the QSPI to function properly. The QSPI can initiate serial transfers
but cannot respond to transfers initiated by other QSPI masters.
24.2 Operation
The QSPI uses a dedicated 80-Byte block of static RAM accessible both to the module and the
CPU to perform queued operations. The RAM is divided into three segments as follows:
•
•
•
16 command control bytes (command RAM)
16 transmit data words (transfer RAM)
16 receive data words (transfer RAM)
The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word
of receive data comprise 1 of the 16 queue entries (0x0–0xF).
NOTE
Throughout ColdFire documentation, “word” is used consistently and
exclusively to designate a 16-bit data unit. The only exceptions to this
appear in discussions of serial communication modules such as QSPI
that support variable-length data units. To simplify these discussions
the functional unit is referred to as a ‘word’ regardless of length.
The user initiates QSPI operation by loading a queue of commands in command RAM, writing
transmit data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the
queued commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to
signal their completion. As another option, QIR[SPIFE] can be enabled to generate an interrupt.
The QSPI uses four queue pointers. The user can access three of them through fields in QSPI wrap
register (QWR):
•
•
•
•
The new queue pointer, QWR[NEWQP], points to the first command in the queue.
An internal queue pointer points to the command currently being executed.
The completed queue pointer, QWR[CPTQP], points to the last command executed.
The end queue pointer, QWR[ENDQP], points to the final command in the queue.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
24-3
Queued Serial Peripheral Interface (QSPI) Module
The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation,
the following sequence repeats:
1. The command pointed to by the internal pointer is executed.
2. The value in the internal pointer is copied into QWR[CPTQP].
3. The internal pointer is incremented.
Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed.
After each command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a
match occurs, QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting
QWR[WREN] enables wraparound mode.
QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0
unless another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but
is changed to show the last queue entry before the QSPI is enabled. QWR[NEWQP] and
QWR[ENDQP] can be written at any time. When the QWR[NEWQP] value changes, the internal
pointer value also changes unless a transfer is in progress, in which case the transfer completes
normally. Leaving QWR[NEWQP] and QWR[ENDQP] set to 0x0 causes a single transfer to occur
when the QSPI is enabled.
Data is transferred relative to QSPI_CLK which can be generated in any one of four combinations
of phase and polarity using QMR[CPHA,CPOL]. Data is transferred with the most significant bit
(msb) first. The number of bits transferred defaults to 8, but can be set to any value between 8 and
16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]).
24.2.1 QSPI RAM
The QSPI contains an 80-Byte block of static RAM that can be accessed by both the user and the
QSPI. This RAM does not appear in the device memory map because it can only be accessed by
the user indirectly through the QSPI address register (QAR) and the QSPI data register (QDR).
The RAM is divided into three segments with 16 addresses each:
•
•
•
Receive data RAM, the initial destination for all incoming data
Transmit data RAM, a buffer for all out-bound data
Command RAM, where commands are loaded
The transmit and command RAM are user write-only. The receive RAM is user read-only.
Figure 24-2 shows the RAM configuration. The RAM contents are undefined immediately after a
reset.
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48
separate locations that comprise 16 words of transmit data, 16 words of receive data and 16 bytes
of commands.
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Freescale Semiconductor
Operation
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and causes
the value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at
the address specified by QAR[ADDR]. This also causes QAR to increment. A read access requires
a single wait state.
Relative
Address
Register
0x00
QTR0
0x01
QTR1
...
...
0x0F
QTR15
0x10
QRR0
0x11
QRR1
...
...
0x1F
QRR15
0x20
QCR0
0x21
QCR1
...
...
0x2F
QCR15
Function
Transmit RAM
16 bits wide
Receive RAM
16 bits wide
Command RAM
8 bits wide
Figure 24-2. QSPI RAM Model
24.2.1.1 Receive RAM
Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the
QSPI RAM space. The user reads this segment to retrieve data from the QSPI. Data words with
less than 16 bits are stored in the least significant bits of the RAM. Unused bits in a receive queue
entry are set to zero upon completion of the individual queue entry.
QWR[CPTQP] shows which queue entries have been executed. The user can query this field to
determine which locations in receive RAM contain valid data.
24.2.1.2 Transmit RAM
Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses
0x0 to 0xF. The user normally writes 1 word into this segment for each queue command to be
executed. The user cannot read data in the transmit RAM.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
24-5
Queued Serial Peripheral Interface (QSPI) Module
Outbound data must be written to transmit RAM in a right-justified format. The unused bits are
ignored. The QSPI copies the data to its data serializer (shift register) for transmission. The data
is transmitted most significant bit first and remains in transmit RAM until overwritten by the user.
24.2.1.3 Command RAM
The CPU writes one byte of control information to this segment for each QSPI command to be
executed. Command RAM, referred to as QCR0–15, is write-only memory from a user’s
perspective.
Command RAM consists of 16 bytes with each byte divided into two fields. The peripheral chip
select field controls the QSPI_CS signal levels for the transfer. The command control field
provides transfer options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in
QWR[NEWQP] through the address in QWR[ENDQP].
The QSPI executes a queue of commands defined by the control bits in each command RAM entry
which sequence the following actions:
•
•
•
Chip-select pins are activated
Data is transmitted from transmit RAM and received into the receive RAM
The synchronous transfer clock QSPI_CLK is generated
Before any data transfers begin, control data must be written to the command RAM, and any
out-bound data must be written to transmit RAM. Also, the queue pointers must be initialized to
the first and last entries in the command queue.
Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity
are controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which
QSPI_CLK edge is used to drive outgoing data and to latch incoming data.
24.2.2 Baud Rate Selection
The maximum QSPI clock frequency is one-fourth the clock frequency of the internal bus clock.
Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler
to derive the QSPI_CLK rate from the internal bus clock divided by two.
A baud rate value of zero turns off the QSPI_CLK.
The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the
following expression:
QMR[BAUD] = fsys/2 / (2 × [desired QSPI_CLK baud rate]
MCF5275 Reference Manual, Rev. 2
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Freescale Semiconductor
Operation
Table 24-2. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate
Internal Bus Clock
QMR [BAUD]
83 MHz
2
20.75 MHz
4
10.375 MHz
8
5.188 MHz
16
2.594 MHz
32
1.297 MHz
255
129.4 kHz
24.2.3 Transfer Delays
The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer. The
time between QSPI_CS assertion and the leading QSPI_CLK edge, and the time between the end
of one transfer and the beginning of the next, are both independently programmable.
The chip select to clock delay enable bit in command RAM, QCR[DSCK], enables the
programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK.
QDLYR[QCD] determines the period of delay before the leading edge of QSPI_CLK. The
following expression determines the actual delay before the QSPI_CLK leading edge:
QSPI_CS-to-QSPI_CLK delay = QDLYR[QCD]/fsys/2
QDLYR[QCD] has a range of 1–127.
When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the QSPI_CLK
period is used.
The command RAM delay after transmit enable bit, QCR[DT], enables the programmable delay
period from the negation of the QSPI_CS signals until the start of the next transfer. The delay after
transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between
consecutive transfers to allow serial A/D converters to complete conversion. There are two
transfer delay options: the user can choose to delay a standard period after serial transfer is
complete or can specify a delay period. Writing a value to QDLYR[DTL] specifies a delay period.
QCR[DT] determines whether the standard delay period (DT = 0) or the specified delay period
(DT = 1) is used. The following expression is used to calculate the delay:
Delay after transfer = 32 × QDLYR[DTL] /fsys/2
(DT = 1)
where QDLYR[DTL] has a range of 1–255.
A zero value for DTL causes a delay-after-transfer value of 8192/fsys/2.
Standard delay after transfer = 17/fsys/2 (DT = 0)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
24-7
Queued Serial Peripheral Interface (QSPI) Module
Adequate delay between transfers must be specified for long data streams because the QSPI
module requires time to load a transmit RAM entry for transfer. Receiving devices need at least
the standard delay between successive transfers. If the internal bus clock is operating at a slower
rate, the delay between transfers must be increased proportionately.
24.2.4 Transfer Length
There are two transfer length options. The user can choose a default value of 8 bits or a
programmed value of 8 to 16 bits. The programmed value must be written into QMR[BITS]. The
command RAM bits per transfer enable field, QCR[BITSE], determines whether the default value
(BITSE = 0) or the BITS[3–0] value (BITSE = 1) is used. QMR[BITS] gives the required number
of bits to be transferred, with 0b0000 representing 16.
24.2.5 Data Transfer
Operation is initiated by setting QDLYR[SPE]. Shortly after QDLYR[SPE] is set, the QSPI
executes the command at the command RAM address pointed to by QWR[NEWQP]. Data at the
pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is
simultaneously received is stored at the pointer address in receive RAM.
When the proper number of bits has been transferred, the QSPI stores the working queue pointer
value in QWR[CPTQP], increments the working queue pointer, and loads the next data for transfer
from the transmit RAM. The command pointed to by the incremented working queue pointer is
executed next unless a new value has been written to QWR[NEWQP]. If a new queue pointer
value is written while a transfer is in progress, then that transfer is completed normally.
When the CONT bit in the command RAM is set, the QSPI_CS signals are asserted between
transfers. When CONT is cleared, QSPI_CS[3:0] are negated between transfers. The QSPI_CS
signals are not high impedance.
When the QSPI reaches the end of the queue, it asserts the SPIF flag, QIR[SPIF]. If QIR[SPIFE]
is set, an interrupt request is generated when QIR[SPIF] is asserted. Then the QSPI clears
QDLYR[SPE] and stops, unless wraparound mode is enabled.
Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address
0x0, or to the address specified by QWR[NEWQP], depending on the state of QWR[WRTO].
In wraparound mode, the QSPI cycles through the queue continuously, even while requesting
interrupt service. QDLYR[SPE] is not cleared when the last command in the queue is executed.
New receive data overwrites previously received data in the receive RAM. Each time the end of
the queue is reached, QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven
QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request.
Additional interrupt requests during servicing can be prevented by clearing QIR[SPIFE].
MCF5275 Reference Manual, Rev. 2
24-8
Freescale Semiconductor
Memory Map/Register Definition
There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or
setting QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended
because this may abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and
stops the first time it reaches the end of the queue after QWR[WREN] is cleared. After
QWR[HALT] is set, the QSPI finishes the current transfer, then stops executing commands. After
the QSPI stops, QDLYR[SPE] can be cleared.
24.3 Memory Map/Register Definition
Table 24-3 is the QSPI register memory map. Reading reserved locations returns zeros.
Table 24-3. QSPI Registers
IPSBAR
Offset
1
[31:24]
[23:16]
[15:8]
[7:0]
0x00_0340
QSPI Mode Register (QMR)
Reserved1
0x00_0344
QSPI Delay Register (QDLYR)
Reserved1
0x00_0348
QSPI Wrap Register (QWR)
Reserved1
0x00_034C
QSPI Interrupt Register (QIR)
Reserved1
0x00_0350
QSPI Address Register (QAR)
Reserved1
0x00_0354
QSPI Data Register (QDR)
Reserved1
Addresses not assigned to a register and undefined register bits are reserved for expansion.
Write accesses to these reserved address spaces and reserved register bits have no effect.
24.3.1 QSPI Mode Register (QMR)
The QMR, shown in Figure 24-3, determines the basic operating modes of the QSPI module.
Parameters such as QSPI_CLK polarity and phase, baud rate, master mode operation, and transfer
size are determined by this register. The data output high impedance enable, DOHIE, controls the
operation of QSPI_DOUT between data transfers. When DOHIE is cleared, QSPI_DOUT is
actively driven between transfers. When DOHIE is set, QSPI_DOUT assumes a high impedance
state.
NOTE
Because the QSPI does not operate in slave mode, the master mode
enable bit, QMR[MSTR], must be set for the QSPI module to operate
correctly.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
24-9
Queued Serial Peripheral Interface (QSPI) Module
15
14
13
12
R MSTR DOHIE
11
10
BITS
9
8
7
6
5
CPOL CPHA
4
3
2
1
0
1
0
0
BAUD
W
Reset
0
0
Address
0
0
0
0
0
1
0
0
0
0
0
IPSBAR + 0x00_0340
Figure 24-3. QSPI Mode Register (QMR)
Table 24-4. QMR Field Descriptions
Bits
Name
Description
15
MSTR
Master mode enable.
0 Reserved, do not use.
1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.
14
DOHIE
Data output high impedance enable. Selects QSPI_DOUT mode of operation.
0 Default value after reset. QSPI_DOUT is actively driven between transfers.
1 QSPI_DOUT is high impedance between transfers.
13–10
BITS
Transfer size. Determines the number of bits to be transferred for each entry in the queue.
BITS
Bits per Transfer
0000
16
0001–0111
Reserved
1000
8
1001
9
1010
10
1011
11
1100
12
1101
13
1110
14
1111
15
9
CPOL
Clock polarity. Defines the clock polarity of QSPI_CLK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.
8
CPHA
Clock phase. Defines the QSPI_CLK clock-phase.
0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of
QSPI_CLK.
1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of
QSPI_CLK.
7–0
BAUD
Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value
of zero disables the QSPI. A value of 1 is an invalid setting. The desired QSPI_CLK baud
rate is related to the internal bus clock and QMR[BAUD] by the following expression:
QMR[BAUD] = fsys/2 / (2 × [desired QSPI_CLK baud rate])
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Freescale Semiconductor
Memory Map/Register Definition
Figure 24-4 shows an example of a QSPI clocking and data transfer.
QSPI_CLK
QSPI_DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
msb
QSPI_DIN
15
A
B
QSPI_CS
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
Figure 24-4. QSPI Clocking and Data Transfer Example
24.3.2 QSPI Delay Register (QDLYR)
Figure 24-5 shows the QDLYR.
15
14
13
12
R SPE
11
10
9
8
7
6
5
4
QCD
3
2
1
0
0
1
0
0
DTL
W
Reset
0
0
Address
0
0
0
1
0
0
0
0
0
0
IPSBAR + 0x00_0344
Figure 24-5. QSPI Delay Register (QDLYR)
Table 24-5. QDLYR Field Descriptions
Bits
Name
Description
15
SPE
QSPI enable. When set, the QSPI initiates transfers in master mode by executing
commands in the command RAM. Automatically cleared by the QSPI when a transfer
completes. The user can also clear this bit to abort transfer unless QIR[ABRTL] is set. The
recommended method for aborting transfers is to set QWR[HALT].
14–8
QCD
QSPICLK delay. When the DSCK bit in the command RAM is set this field determines the
length of the delay from assertion of the chip selects to valid QSPI_CLK transition.
7–0
DTL
Delay after transfer. When the DT bit in the command RAM is set this field determines the
length of delay after the serial transfer.
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Freescale Semiconductor
24-11
Queued Serial Peripheral Interface (QSPI) Module
24.3.3 QSPI Wrap Register (QWR)
15
14
13
12
11
R HALT WREN WRTO CSIV
10
9
8
7
ENDQP
6
5
4
3
CPTQP
2
1
0
NEWQP
W
Reset
0
0
0
0
Address
0
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0348
Figure 24-6. QSPI Wrap Register (QWR)
Table 24-6. QWR Field Descriptions
Bits
Name
Description
15
HALT
Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once
it has completed execution of the current command.
14
WREN
Wraparound enable. Enables wraparound mode.
0 Execution stops after executing the command pointed to by QWR[ENDQP].
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the
entry pointed to by QWR[NEWQP] and continue execution.
13
WRTO
Wraparound location. Determines where the QSPI wraps to in wraparound mode.
0 Wrap to RAM entry zero.
1 Wrap to RAM entry pointed to by QWR[NEWQP].
12
CSIV
QSPI_CS inactive level.
0 QSPI chip select outputs return to zero when not driven from the value in the current
command RAM entry during a transfer (that is, inactive state is 0, chip selects are active
high).
1 QSPI chip select outputs return to one when not driven from the value in the current
command RAM entry during a transfer (that is, inactive state is 1, chip selects are active
low).
11–8
ENDQP
End of queue pointer. Points to the RAM entry that contains the last transfer description in
the queue.
7–4
CPTQP
Completed queue entry pointer. Points to the RAM entry that contains the last command
to have been completed. This field is read only.
3–0
NEWQP
Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on
initiating a transfer.
24.3.4 QSPI Interrupt Register (QIR)
Figure 24-7 shows the QIR.
MCF5275 Reference Manual, Rev. 2
24-12
Freescale Semiconductor
Memory Map/Register Definition
15
14
13
R WCE ABR
FB
TB
W
Reset
0
0
0
0
Address
12
11
10
ABR WCE ABR
TL
FE
TE
0
0
0
9
8
7
6
5
4
0
SPIFE
0
0
0
0
0
0
0
0
0
0
3
2
WCEF ABRT
0
0
1
0
0
SPIF
0
0
IPSBAR + 0x00_034C
Figure 24-7. QSPI Interrupt Register (QIR)
Table 24-7. QIR Field Descriptions
BIts
Name
Description
15
WCEFB
Write collision access error enable. A write collision occurs during a data transfer when the
RAM entry containing the command currently being executed is written to by the CPU with
the QDR. When this bit is asserted, the write access to QDR results in an access error.
14
ABRTB
Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer.
When set, an attempt to clear QDLYR[SPE] during a transfer results in an access error.
13
—
12
ABRTL
Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR.
QDLYR[SPE] is only cleared by the QSPI when a transfer completes.
11
WCEFE
Write collision interrupt enable. Interrupt enable for WCEF. Setting this bit enables the
interrupt, and clearing it disables the interrupt.
10
ABRTE
Abort interrupt enable. Interrupt enable for ABRT flag. Setting this bit enables the interrupt,
and clearing it disables the interrupt.
9
—
8
SPIFE
7–4
—
3
WCEF
Write collision error flag. Indicates that an attempt has been made to write to the RAM entry
that is currently being executed. Writing a 1 to this bit clears it and writing 0 has no effect.
2
ABRT
Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR
rather than by completion of the command queue by the QSPI. Writing a 1 to this bit clears
it and writing 0 has no effect.
1
—
0
SPIF
Reserved, should be cleared.
Reserved, should be cleared.
QSPI finished interrupt enable. Interrupt enable for SPIF. Setting this bit enables the
interrupt, and clearing it disables the interrupt.
Reserved, should be cleared.
Reserved, should be cleared.
QSPI finished flag. Asserted when the QSPI has completed all the commands in the
queue. Set on completion of the command pointed to by QWR[ENDQP], and on
completion of the current command after assertion of QWR[HALT]. In wraparound mode,
this bit is set every time the command pointed to by QWR[ENDQP] is completed. Writing
a 1 to this bit clears it and writing 0 has no effect.
The command and data RAM in the QSPI are indirectly accessible with QDR and QAR as 48
separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes
of commands.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
24-13
Queued Serial Peripheral Interface (QSPI) Module
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also
causes the value in QAR to increment.
Correspondingly, a read at QDR returns the data in the RAM at the address specified by
QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.
NOTE
The QAR does not wrap after the last queue entry within each section
of the RAM. The application software must handle address range
errors.
24.3.5 QSPI Address Register (QAR)
The QAR, shown in Figure 24-8, is used to specify the location in the QSPI RAM that read and
write operations affect.
R
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
0
0
ADDR
W
Reset
Address
0
0
0
0
IPSBAR + 0x00_0350
Figure 24-8. QSPI Address Register
24.3.6 QSPI Data Register (QDR)
The QDR, shown in Figure 24-9, is used to access QSPI RAM indirectly. The CPU reads and
writes all data from and to the QSPI RAM through this register.
15
14
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DATA
W
Reset
Address
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0354
Figure 24-9. QSPI Data Register (QDR)
24.3.7 Command RAM Registers (QCR0–QCR15)
The command RAM is accessed using the upper byte of QDR. The QSPI cannot modify
information in command RAM.
There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select
field enables external peripherals for transfer. The command field provides transfer operations.
MCF5275 Reference Manual, Rev. 2
24-14
Freescale Semiconductor
Memory Map/Register Definition
NOTE
The command RAM is accessed only using the most significant byte
of QDR and indirect addressing based on QAR[ADDR].
Figure 24-10 shows the command RAM register.
15
14
13
12
DT
DSCK
—
—
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
R
W CONT BITSE
Reset
—
—
Address
QSPI_CS
—
—
—
—
QAR[ADDR]
Figure 24-10. Command RAM Registers (QCR0–QCR15)
Table 24-8. QCR0–QCR15 Field Descriptions
Bits
Name
Description
15
CONT
Continuous.
0 Chip selects return to inactive level defined by QWR[CSIV] when transfer is complete.
1 Chip selects remain asserted after the transfer of 16 words of data (see note below).
14
BITSE
Bits per transfer enable.
0 Eight bits
1 Number of bits set in QMR[BITS]
13
DT
12
DSCK
11–8
QSPI_CS
7–0
—
Delay after transfer enable.
0 Default reset value.
1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing
with peripherals that have a latency requirement. The delay between transfers is
determined by QDLYR[DTL].
Chip select to QSPI_CLK delay enable.
0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period.
1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK.
Peripheral chip selects. Used to select an external device for serial data transfer. More than
one chip select may be active at once, and more than one device can be connected to each
chip select. Bits 11–8 map directly to QSPI_CS[3:0], respectively. If it is desired to use
those bits as a chip select value, then an external demultiplexor must be connected to the
QSPI_CS[3:0] pins.
Reserved, should be cleared.
NOTE
In order to keep the chip selects asserted for all transfers, the
QWR[CSIV] bit must be set to control the level that the chip selects
return to after the first transfer.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
24-15
Queued Serial Peripheral Interface (QSPI) Module
QSPI_CS[3:0]
QS1
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS5
QS4
QSPI_DIN
Min
Max
1T1
QS1: QSPI_CS to QSPI_CLK
20 ns
QS2: QSPI_CLK to QSPI_DOUT VALID
QS3: QSPI_CLK to QSPI_DOUT HOLD
0 ns
QS4: QSPI_DIN to QSPI_CLK SETUP
10 ns
QS5: QSPI_DIN to QSPI_CLK HOLD
10 ns
1 T1 is defined as the clock period in ns.
Figure 24-11. QSPI Timing
24.3.8 Programming Example
The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of
5.188 MHz. The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are
used in this example.
1. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the falling
clock edge, and a QSPI_CLK frequency of 5.188 MHz (assuming a 83-MHz internal bus
clock).
2. Write QDLYR with the desired delays.
3. Write QIR with 0xD00F to enable write collision, abort bus errors, and clear any
interrupts.
4. Write QAR with 0x0020 to select the first command RAM entry.
MCF5275 Reference Manual, Rev. 2
24-16
Freescale Semiconductor
Memory Map/Register Definition
5. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00,
0x7B00, 0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four
transfers for each chip select. The chip selects are active low in this example.
6. Write QAR with 0x0000 to select the first transmit RAM entry.
7. Write QDR with sixteen 12-bit words of data.
8. Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry 15.
9. Set QDLYR[SPE] to enable the transfers.
10. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are complete.
11. Write QAR with 0x0010 to select the first receive RAM entry.
12. Read QDR to get the received data for each transfer.
13. Repeat steps 5 through 13 to do another transfer.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
24-17
Queued Serial Peripheral Interface (QSPI) Module
MCF5275 Reference Manual, Rev. 2
24-18
Freescale Semiconductor
Chapter 25
DMA Timers (DTIM0–DTIM3)
25.1
Introduction
This chapter describes the configuration and operation of the four Direct Memory Access (DMA)
timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture
and reference compare capabilities with optional signaling of events using interrupts or triggers.
Additionally, programming examples are included.
NOTE
The designation “n” is used throughout this section to refer to registers
or signals associated with one of the four identical timer
modules—DTIM0, DTIM1, DTIM2, or DTIM3.
25.1.1 Overview
Each DMA timer module has a separate register set for configuration and control. The timers can
be configured to operate from the system clock or from an external clocking source using the
DTINn signal. If the system clock is selected, it can be divided by 16 or 1. The selected clock
source is routed to an 8-bit programmable prescaler that clocks the actual DMA timer counter
register (DTCNn). Using the DTMRn, DTXMRn, DTCRn, and DTRRn registers, the DMA timer
may be configured to assert an output signal, generate an interrupt, or initiate a DMA transfer on
a particular event.
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module”) prior to configuring the DMA Timers.
Figure 25-1 is a block diagram of one of the four identical timer modules.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
25-1
DMA Timers (DTIM0–DTIM3)
0
15
Internal Bus Clock
(÷1 or ÷16)
DMA Timer
Clock
Generator
DTINn
7
DMA Timer Mode Register (DTMRn)
Prescaler
Mode Bits
0
DMA Timer Extended Mode
Register (DTXMRn)
Divider
clock
31
Capture
0
DMA Timer Counter Register (DTCNn)
(contains incrementing value)
Detection
31
0
DMA Timer Capture Register (DTCRn)
(latches DTCN value when triggered by DTINn)
DTOUTn
To Interrupt
controller
31
0
DMA Timer Reference Register (DTRRn)
(reference value for comparison with DTCN)
0
7
DMA Timer Event Register (DTERn)
(indicates capture or when DTCN = DTRRn)
DREQn
Figure 25-1. DMA Timer Block Diagram
25.1.2 Features
Each DMA timer module has the following features:
•
•
•
•
•
•
•
•
25.2
Maximum timeout period of 211,954 seconds at 83 MHz (~659 hours)
12-ns resolution at 83 MHz
Programmable sources for the clock input, including external clock
Programmable prescaler
Input-capture capability with programmable trigger edge on input pin
Programmable mode for the output pin on reference compare
Free run and restart modes
Programmable interrupt or DMA request on input capture or reference-compare
Memory Map/Register Definition
The following features are programmable through the timer registers, shown in Table 25-1:
25.2.1 Prescaler
The prescaler clock input is selected from system clock (divided by 1 or 16) or from the
corresponding timer input, DTINn. DTINn is synchronized to the system clock. The
MCF5275 Reference Manual, Rev. 2
25-2
Freescale Semiconductor
Memory Map/Register Definition
synchronization delay is between two and three system clocks. The corresponding DTMRn[CLK]
selects the clock input source. A programmable prescaler divides the clock input by values from
1 to 256. The prescaler output is an input to the 32-bit counter, DTCNn.
25.2.2 Capture Mode
Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value when
the corresponding input capture edge detector senses a defined DTINn transition. The capture edge
bits (DTMRn[CE]) select the type of transition that triggers the capture and sets the timer event
register capture event bit, DTERn[CAP]. If DTERn[CAP] is set and DTXMRn[DMAEN] is one,
a DMA request is asserted. If DTERn[CAP] is set and DTXMRn[DMAEN] is zero, an interrupt
is asserted.
25.2.3 Reference Compare
Each DMA timer can be configured to count up to a reference value, at which point DTERn[REF]
is set. If DTMRn[ORRI] is one and DTXMRn[DMAEN] is zero, an interrupt is asserted. If
DTMRn[ORRI] is one and DTXMRn[DMAEN] is one, a DMA request is asserted. If the free
run/restart bit DTMRn[FRR] is set, a new count starts. If it is clear, the timer keeps running.
25.2.4 Output Mode
When a timer reaches the reference value selected by DTRR, it can send an output signal on
DTOUTn. DTOUTn can be an active-low pulse or a toggle of the current output as selected by the
DTMRn[OM] bit.
25.2.5 Memory Map
The timer module registers, shown in Table 25-1, can be modified at any time.
Table 25-1. DMA Timer Module Memory Map
IPSBAR
Offset
0x00_0400
[31:24]
[23:16]
DMA Timer0 Mode Register (DTMR0)
[15:8]
[7:0]
DMA Timer0
Extended Mode
Register (DTXMR0)
DMA Timer0 Event
Register (DTER0)
0x00_0404
DMA Timer0 Reference Register (DTRR0)
0x00_0408
DMA Timer0 Capture Register (DTCR0)
0x00_040C
DMA Timer0 Counter Register (DTCN0)
0x00_0440
DMA Timer1 Mode Register (DTMR1)
DMA Timer1
Extended Mode
Register (DTXMR1)
DMA Timer1 Event
Register (DTER1)
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
25-3
DMA Timers (DTIM0–DTIM3)
Table 25-1. DMA Timer Module Memory Map (Continued)
IPSBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x00_0444
DMA Timer1 Reference Register (DTRR1)
0x00_0448
DMA Timer1 Capture Register (DTCR1)
0x00_044C
DMA Timer1 Counter Register (DTCN1)
0x00_0480
DMA Timer2 Mode Register (DTMR2)
DMA Timer2
Extended Mode
Register (DTXMR2)
0x00_0484
DMA Timer2 Reference Register (DTRR2)
0x00_0488
DMA Timer2 Capture Register (DTCR2)
0x00_048C
DMA Timer2 Counter Register (DTCN2)
0x00_04C0
DMA Timer3 Mode Register (DTMR3)
DMA Timer3
Extended Mode
Register (DTXMR3)
0x00_04C4
DMA Timer3 Reference Register (DTRR3)
0x00_04C8
DMA Timer3 Capture Register (DTCR3)
0x00_04CC
DMA Timer3 Counter Register (DTCN3)
DMA Timer2 Event
Register (DTER2)
DMA Timer3 Event
Register (DTER3)
25.2.6 DMA Timer Mode Registers (DTMRn)
DTMRs, shown in Figure 25-2, program the prescaler and various timer modes.
15
14
13
12
R
11
10
9
8
7
PS
6
CE
5
4
3
2
OM ORRI FRR
1
CLK
0
RST
W
Reset
0
0
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0400 (DTMR0); IPSBAR + 0x00_0440 (DTMR1);
IPSBAR + 0x00_0480 (DTMR2); IPSBAR + 0x00_04C0 (DTMR3)
Figure 25-2. DMA Timer Mode Registers (DTMRn)
Table 25-2. DTMRn Field Descriptions
Bits
Name
Description
15–8
PS
Prescaler value. The prescaler is programmed to divide the clock input (system clock/(16
or 1) or clock on DTINn) by values from 1 (PS = 0x00) to 256 (PS = 0xFF).
7–6
CE
Capture edge.
00 Disable capture event output
01 Capture on rising edge only
10 Capture on falling edge only
11 Capture on any edge
MCF5275 Reference Manual, Rev. 2
25-4
Freescale Semiconductor
Memory Map/Register Definition
Table 25-2. DTMRn Field Descriptions (Continued)
Bits
Name
Description
5
OM
4
ORRI
Output reference request, interrupt enable. If ORRI is set when DTERn[REF] = 1, a DMA
request or an interrupt occurs, depending on the value of DTXMRn[DMAEN] (DMA request
if =1, interrupt if =0).
0 Disable DMA request or interrupt for reference reached (does not affect DMA request
or interrupt on capture function).
1 Enable DMA request or interrupt upon reaching the reference value.
3
FRR
Free run/restart
0 Free run. Timer count continues to increment after reaching the reference value.
1 Restart. Timer count is reset immediately after reaching the reference value.
2–1
CLK
Input clock source for the timer
00 Stop count
01 System clock divided by 1
10 System clock divided by 16. Note that this clock source is not synchronized with the
timer; thus successive time-outs may vary slightly.
11 DTINn pin (falling edge)
0
RST
Reset timer. Performs a software timer reset similar to an external reset, although other
register values can still be written while RST = 0. A transition of RST from 1 to 0 resets
register values. The timer counter is not clocked unless the timer is enabled.
0 Reset timer (software reset)
1 Enable timer
Output mode.
0 Active-low pulse for one system clock cycle (12-ns resolution at 83 MHz).
1 Toggle output.
25.2.7 DMA Timer Extended Mode Registers (DTXMRn)
DTXMRn, shown in Figure 25-3, program DMA request and increment modes for the timers.
7
R DMAEN
6
5
4
3
2
1
0
0
0
0
0
0
0
MODE16
0
0
0
0
0
0
0
W
Reset
Address
0
IPSBAR + 0x00_0402 (DTXMR0); IPSBAR + 0x00_0442 (DTXMR1);
IPSBAR + 0x00_0482 (DTXMR2); IPSBAR + 0x00_04C2 (DTXMR3)
Figure 25-3. DMA Timer Extended Mode Registers (DTXMRn)
Table 25-3. DTXMRn Field Descriptions
Bits
Name
Description
7
DMAEN
DMA request. Enables DMA request output on counter reference match or capture edge
event.
0 DMA request disabled
1 DMA request enabled
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
25-5
DMA Timers (DTIM0–DTIM3)
Table 25-3. DTXMRn Field Descriptions (Continued)
Bits
Name
Description
6–1
—
0
MODE16
Reserved, should be cleared.
Selects the increment mode for the timer. MODE16 = 1 is intended to exercise the upper
bits of the 32-bit timer in diagnostic software without requiring the timer to count through
its entire dynamic range. When set, the counter’s upper 16 bits mirror its lower 16 bits.
All 32 bits of the counter are still compared to the reference value.
0 Increment timer by 1
1 Increment timer by 65,537
25.2.8 DMA Timer Event Registers (DTERn)
DTERn, shown in Figure 25-4, reports capture or reference events by setting DTERn[CAP] or
DTERn[REF]. This reporting is done regardless of the corresponding DMA request or interrupt
enable values, DTXMRn[DMAEN] and DTMRn[ORRI,CE].
Writing a 1 to either DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect bit value);
both bits can be cleared at the same time. If configured to generate an interrupt request, the REF
and CAP bits must be cleared early in the interrupt service routine so the timer module can negate
the interrupt request signal to the interrupt controller. If configured to generate a DMA request, the
processing of the DMA data transfer automatically clears both the REF and CAP flags via the
internal DMA ACK signal.
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
REF
CAP
w1c
w1c
0
0
W
Reset
Address
0
0
0
0
0
0
IPSBAR + 0x00_0403 (DTER0); IPSBAR + 0x00_0443 (DTER1);
IPSBAR + 0x00_0483 (DTER2); IPSBAR + 0x00_04C3 (DTER3)
Figure 25-4. DMA Timer Event Registers (DTERn)
MCF5275 Reference Manual, Rev. 2
25-6
Freescale Semiconductor
Memory Map/Register Definition
Table 25-4. DTERn Field Descriptions
Bits
Name
7–2
—
1
REF
0
CAP
Description
Reserved, should be cleared.
Output reference event. The counter value, DTCNn, equals the reference value, DTRRn.
Writing a one to REF clears the event condition. Writing a zero has no effect.
REF
DTMRn[ORRI]
DTXMRn[DMAEN]
0
X
X
No event
1
0
0
No request asserted
1
0
1
No request asserted
1
1
0
Interrupt request asserted
1
1
1
DMA request asserted
Capture event. The counter value has been latched into DTCRn. Writing a one to CAP
clears the event condition. Writing a zero has no effect.
CAP
DTMRn[CE]
DTXMRn
[DMAEN]
0
X
X
No event
1
00
0
Disable capture event output
1
00
1
Disable capture event output
1
01
0
Capture on rising edge & trigger interrupt
1
01
1
Capture on rising edge & trigger DMA
1
10
0
Capture on falling edge & trigger interrupt
1
10
1
Capture on falling edge & trigger DMA
1
11
0
Capture on any edge & trigger interrupt
1
11
1
Capture on any edge & trigger DMA
25.2.9 DMA Timer Reference Registers (DTRRn)
Each DTRRn, shown in Figure 25-5, contains the reference value compared with the respective
free-running timer counter (DTCNn) as part of the output-compare function. The reference value
is not matched until DTCNn equals DTRRn, and the prescaler indicates that DTCNn should be
incremented again. Thus, the reference register is matched after DTRRn+1 time intervals.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
25-7
DMA Timers (DTIM0–DTIM3)
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
REF
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
R
REF
W
Reset
1
1
1
Address
1
1
1
1
1
IPSBAR + 0x00_0404 (DTRR0); IPSBAR + 0x00_0444 (DTRR1);
IPSBAR + 0x00_0484 (DTRR2); IPSBAR + 0x00_04C4 (DTRR3)
Figure 25-5. DMA Timer Reference Registers (DTRRn)
25.2.10 DMA Timer Capture Registers (DTCRn)
Each DTCRn, shown in Figure 25-6, latches the corresponding DTCNn value during a capture
operation when an edge occurs on DTINn, as programmed in DTMRn. The system clock is
assumed to be the clock source. DTINn cannot simultaneously function as a clocking source and
as an input capture pin. Indeterminate operation will result if DTINn is set as the clock source
when the input capture mode is used.
31
30
29
28
27
R
26
25
24
23
22
21
20
19
18
17
16
CAP (32-bit capture counter value)
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
CAP (32-bit capture counter value)
W
Reset
Address
0
0
0
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0408 (DTCR0); IPSBAR + 0x00_0448 (DTCR1);
IPSBAR + 0x00_0488 (DTCR2); IPSBAR + 0x00_04C8 (DTCR3)
Figure 25-6. DMA Timer Capture Registers (DTCRn)
25.2.11 DMA Timer Counters (DTCNn)
The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Writing
to DTCNn, shown in Figure 25-7, clears it. The timer counter increments on the clock source
rising edge (system clock ÷ 1, system clock ÷ 16, or DTINn).
MCF5275 Reference Manual, Rev. 2
25-8
Freescale Semiconductor
Using the DMA Timer Modules
31
30
29
28
27
R
26
25
24
23
22
21
20
19
18
17
16
CNT (32-bit timer counter value count)
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
CNT (32-bit timer counter value count)
W
Reset
0
0
Address
0
0
0
0
0
0
0
0
0
IPSBAR + 0x00_040C (DTCN0); IPSBAR + 0x00_044C (DTCN1);
IPSBAR + 0x00_048C (DTCN2); IPSBAR + 0x00_04CC (DTCN3)
Figure 25-7. DMA Timer Counters (DTCNn)
25.3
Using the DMA Timer Modules
The general-purpose timer modules are typically used in the following manner, though this is not
necessarily the program order in which these actions must occur:
•
•
The DTMRn and DTXMRn registers are configured for the desired function and behavior.
— Count and compare to a reference value stored in the DTRRn register
— Capture the timer value on an edge detected on DTINn
— Configure DTOUTn output mode
— Increment counter by 1 or by 65,537 (16-bit mode)
— Enable/disable interrupt or DMA request on counter reference match or capture edge
The DTMRn[CLK] register is configured to select the clock source to be routed to the
prescaler.
— System clock (can be divided by 1 or 16)
— DTINn, the maximum value of DTINn is 1/5 of the system clock, as described in the
MCF5275 Electrical Characteristics.
NOTE
DTINn may not be configured as a clock source when the timer
capture mode is selected or indeterminate operation will result.
•
•
•
The 8-bit DTMRn[PS] prescaler value is set
Using DTMRn[RST] the counter is cleared and started
Timer events are either handled with an interrupt service routine, a DMA request, or by a
software polling mechanism
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
25-9
DMA Timers (DTIM0–DTIM3)
25.3.1 Code Example
The following code provides an example of how to initialize DMA Timer0 and how to use the
timer for counting time-out periods.
DTMR0
DTMR1
DTRR0
DTRR1
DTCR0
DTCR1
DTCN0
DTCN1
DTER0
DTER1
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
IPSBARx+0x400;Timer0 mode register
IPSBARx+0x440 ;Timer1 mode register
IPSBARx+0x404 ;Timer0 reference register
IPSBARx+0x444 ;Timer1 reference register
IPSBARx+0x408 ;Timer0 capture register
IPSBARx+0x448 ;Timer1 capture register
IPSBARx+0x40C ;Timer0 counter register
IPSBARx+0x44C ;Timer1 counter register
IPSBARx+0x403 ;Timer0 event register
IPSBARx+0x443 ;Timer1 event register
* TMR0 is defined as: *
*[PS] = 0xFF,
divide clock by 256
*[CE] = 00
disable capture event output
*[OM] = 0
output=active-low pulse
*[ORRI] = 0,
disable ref. match output
*[FRR] = 1,
restart mode enabled
*[CLK] = 10,
system clock/16
*[RST] = 0,
timer0 disabled
move.w #0xFF0C,D0
move.w D0,TMR0
move.l #0x0000,D0;writing to the timer counter with any
move.l DO,TCN0 ;value resets it to zero
move.l #AFAF,DO ;set the timer0 reference to be
move.l #D0,TRR0 ;defined as 0xAFAF
The simple example below uses Timer0 to count time-out loops. A time-out occurs when the
reference value, 0xAFAF, is reached.
timer0_ex
clr.l DO
clr.l D1
clr.l D2
move.l #0x0000,D0
move.l D0,TCN0
;reset the counter to 0x0000
move.b #0x03,D0
move.b D0,TER0
;writing ones to TER0[REF,CAP]
;clears the event flags
move.w TMR0,D0
bset #0,D0
move.w D0,TMR0
TMR0[RST]
;save the contents of TMR0 while setting
;the 0 bit. This enables timer 0 and starts counting
;load the value back into the register, setting
T0_LOOP
move.b TER0,D1
;load TER0 and see if
MCF5275 Reference Manual, Rev. 2
25-10
Freescale Semiconductor
Using the DMA Timer Modules
btst #1,D1
beq T0_LOOP
;TER0[REF] has been set
addi.l #1,D2
cmp.l #5,D2
beq T0_FINISH
;Increment D2
;Did D2 reach 5? (i.e. timer ref has timed)
;If so, end timer0 example. Otherwise jump
move.b #0x02,D0
;writing one to TER0[REF] clears the event
back.
flag
move.b D0,TER0
jmp T0_LOOP
T0_FINISH
HALT
;End processing. Example is finished
25.3.2 Calculating Time-Out Values
The formula below determines time-out periods for various reference values:
Time-out period = (1/clock frequency) x (1 or 16) x (DTMRn[PS] + 1) x (DTRRn[REF] + 1)
When calculating time-out periods, add 1 to the prescaler to simplify calculating, because
DTMRn[PS] = 0x00 yields a prescaler of 1 and DTMRn[PS] = 0xFF yields a prescaler of 256.
For example, if a 83-MHz timer clock is divided by 16, DTMRn[PS] = 0x7F, and the timer is
referenced at 0x13C9E (81,054 decimal), the time-out period is as follows:
Time-out period = [1/(83 x 106)] x (16) x (127 + 1) x (81,054 + 1) = 2.00 s
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
25-11
DMA Timers (DTIM0–DTIM3)
MCF5275 Reference Manual, Rev. 2
25-12
Freescale Semiconductor
Chapter 26
I2C Interface
26.1
Introduction
This chapter describes the MCF5275 I2C module, including I2C protocol, clock synchronization,
and I2C programming model registers. It also provides extensive programming examples.
26.2
Overview
I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
exchange, minimizing the interconnection between devices. This bus is suitable for applications
that require occasional communication between many devices over a short distance. The flexible
I2C bus allows additional devices to be connected to the bus for expansion and system
development.
The interface is designed to operate up to 100 Kbps with maximum bus loading and timing. The
device is capable of operating at higher baud rates, up to a maximum of the internal bus clock
divided by 20, with reduced bus loading. The maximum communication length and the number of
devices that can be connected are limited by a maximum bus capacitance of 400 pF.
The I2C system is a true multiple-master bus; it uses arbitration and collision detection to prevent
data corruption in the event that multiple devices attempt to control the bus simultaneously. This
feature supports complex applications with multiprocessor control and can be used for rapid
testing and alignment of end products through external connections to an assembly-line computer.
NOTE
compatible with the Philips I2C bus
protocol. For information on system configuration, protocol, and
restrictions, see The I2C Bus Specification, Version 2.1.
The I2C module is designed to be
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module”) prior to configuring the I2C module.
26.3
Features
The I2C module has the following key features:
•
•
Compatibility with I2C bus standard version 2.1
Support for 3.3-V tolerant devices
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
26-1
I2C Interface
•
•
•
•
•
•
•
•
•
•
Multiple-master operation
Software-programmable for one of 50 different serial clock frequencies
Software-selectable acknowledge bit
Interrupt-driven, byte-by-byte data transfer
Arbitration-lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
START and STOP signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
Figure 26-1 is a block diagram of the I2C module.
Internal Bus
IRQ
Address
Data
Address Decode
Data MUX
I2C Data
I/O Register
(I2DR)
I2C Address
Register
(IADR)
Registers and ColdFire Interface
I2C Frequency
Divider Register
(IFDR)
I2C Control
Register
(I2CR)
Clock
Control
Start, Stop,
and
Arbitration
Control
Input
Sync
I2C Status
Register
(I2SR)
In/Out
Data
Shift
Register
Address
Compare
I2C_SCL I2C_SDA
Figure 26-1. I2C Module Block Diagram
MCF5275 Reference Manual, Rev. 2
26-2
Freescale Semiconductor
I2C System Configuration
Figure 26-1 shows the relationships of the below I2C registers, which are described in
Section 26.5, “Memory Map/Register Definition":
I2C address register (I2ADR)
I2C frequency divider register (I2FDR)
I2C control register (I2CR)
I2C status register (I2SR)
I2C data I/O register (I2DR)
•
•
•
•
•
I2C System Configuration
26.4
The I2C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL) for data
transfer. For I2C compliance, all devices connected to these two signals must have open drain or
open collector outputs. The logic AND function is exercised on both lines with external pull-up
resistors.
Out of reset, the I2C default state is as a slave receiver. Thus, when not programmed to be a master
or responding to a slave transmit address, the I2C module should return to the default slave receiver
state. See Section 26.6.1, “Initialization Sequence,” for exceptions.
Normally, a standard communication is composed of four parts: START signal, slave address
transmission, data transfer, and STOP signal. These are discussed in the following sections.
26.4.1 START Signal
When no other device is bus master (both I2C_SCL and I2C_SDA lines are at logic high), a device
can initiate communication by sending a START signal (see A in Figure 26-2). A START signal
is defined as a high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the
beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves.
Interrupt bit set
(Byte complete)
msb
I2C_SCL
I2C_SDA
A
1
lsb
2
3
4
5
6
7
8
msb
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
Signal
I2C_SCL held low while
Interrupt is serviced
Calling Address
B
R/W
C
XXX
ACK
Bit
D
lsb
1
2
3
D7
D6 D5
4
5
6
D4
D3
D2 D1
Data Byte
E
7
8
9
D0
No STOP
ACK Signal
Bit
F
Figure 26-2. I2C Standard Communication Protocol
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
26-3
I2C Interface
26.4.2 Slave Address Transmission
The master sends the slave address in the first byte after the START signal (B). After the seven-bit
calling address, it sends the R/W bit (C), which tells the slave data transfer direction (0 = write
transfer, 1 = read transfer).
Each slave must have a unique address. An I2C master must not transmit its own slave address; it
cannot be master and slave at the same time.
The slave whose address matches that sent by the master pulls I2C_SDA low at the ninth serial
clock (D) to return an acknowledge bit.
26.4.3 Data Transfer
When successful slave addressing is achieved, the data transfer can proceed (E) on a byte-by-byte
basis in the direction specified by the R/W bit sent by the calling master.
Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high,
as Figure 26-2 shows. I2C_SCL is pulsed once for each data bit, with the msb being sent first. The
receiving device must acknowledge each byte by pulling I2C_SDA low at the ninth clock;
therefore, a data byte transfer takes nine clock pulses. See Figure 26-3.
I2C_SCL Held Low while
Interrupt is Serviced
I2C_SCL
1
2
3
4
5
6
7
8
9
I2C_SDA
Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W
1
2
3
4
Interrupt Bit Set
(Byte Complete)
6
7
8
9
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Data Byte
Slave Address
START
Signal
5
ACK from
Receiver
No
ACK STOP
Bit Signal
Figure 26-3. Data Transfer
26.4.4 Acknowlege
The transmitter releases the I2C_SDA line high during the acknowledge clock pulse as shown in
Figure 26-4. The receiver pulls down the I2C_SDA line during the acknowledge clock pulse so
that it remains stable low during the high period of the clock pulse.
If it does not acknowledge the master, the slave receiver must leave I2C_SDA high. The master
can then generate a STOP signal to abort the data transfer or generate a START signal (repeated
start, shown in Figure 26-5 and discussed in Section 26.4.6, “Repeated START”) to start a new
calling sequence.
MCF5275 Reference Manual, Rev. 2
26-4
Freescale Semiconductor
I2C System Configuration
I2C_SCL
1
2
3
4
5
6
7
8
9
Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 R/W
I2C_SDA by Transmitter
I2C_SDA by Receiver
START Signal
Figure 26-4. Acknowledgement by Receiver
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it
means end-of-data to the slave. The slave releases I2C_SDA for the master to generate a STOP or
START signal (Figure 26-4).
26.4.5 STOP Signal
The master can terminate communication by generating a STOP signal to free the bus. A STOP
signal is defined as a low-to-high transition of I2C_SDA while I2C_SCL is at logical high (F). The
master can generate a STOP even if the slave has generated an acknowledgment at which point the
slave must release the bus. The master may also generate a START signal following a calling
address, without first generating a STOP signal. Refer to Section 26.4.6, “Repeated START.”
msb
I2C_SCL
I2C_SDA
lsb
1
2
3
4
5
6
7
8
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
START
Signal
Calling Address
lsb
msb
R/W ACK
Bit
1
XX
2
3
4
5
6
7
8
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Repeated
START
Signal A
New Calling Address
Stop
R/W No
ACK
Bit
STOP
Signal
Figure 26-5. Repeated START
26.4.6 Repeated START
A repeated START signal is a START signal generated without first generating a STOP signal to
terminate the communication. The master uses a repeated START to communicate with another
slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.
Various combinations of read/write formats are then possible:
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
26-5
I2C Interface
•
•
•
The first example in Figure 26-6 is the case of master-transmitter transmitting to
slave-receiver. The transfer direction is not changed.
The second example in Figure 26-6 is the master reading the slave immediately after the
first byte. At the moment of the first acknowledge, the master-transmitter becomes a
master-receiver and the slave-receiver becomes slave-transmitter.
In the third example in Figure 26-6 the START condition and slave address are both
repeated using the repeated START signal. This is to communicate with same slave in a
different mode without releasing the bus. The master transmits data to the slave first, and
then the master reads data from slave by reversing the R/W bit.
ST = Start
SP = Stop
A = Acknowledge (I2C_SDA low)
A = Not Acknowledge (I2C_SDA high)
Rept ST = Repeated Start
From Slave to Master
R/W
Example 1:
ST
7bit Slave Address
0
A
Register Address
A
DATA
A
DATA
A
DATA
A/A SP
R/W
Example 2:
ST
7bit Slave Address
Example 3:
ST
From Master to Slave
7-bit Slave
Address
1
R/W
1
A
SP
R/W
A
DATA
A/A
Rept
ST
7-bit Slave 0
Address
A
Master Transmits to Slave
DATA
A DATA A/A SP
Master Reads from Slave
Figure 26-6. Data Transfer, Combined Format
1
Note: No acknowledge on the last byte
26.4.7 Clock Synchronization and Arbitration
I2C is a true multi-master bus that allows more than one master to be connected to it. If two or
more masters devices simultaneously request control of the bus, a clock synchronization
procedure determines the bus clock. Because wire-AND logic is performed on the I2C_SCL line,
a high-to-low transition on the I2C_SCL line affects all the devices connected on the bus. The
devices start counting their low period and once a device’s clock has gone low, it holds the
I2C_SCL line low until the clock high state is reached. However, the change of low to high in this
device clock may not change the state of the I2C_SCL line if another device clock is still within
MCF5275 Reference Manual, Rev. 2
26-6
Freescale Semiconductor
I2C System Configuration
its low period. Therefore, synchronized clock I2C_SCL is held low by the device with the longest
low period.
Devices with shorter low periods enter a high wait state during this time (see Figure 26-8). When
all devices concerned have counted off their low period, the synchronized clock I2C_SCL line is
released and pulled high. There is then no difference between the device clocks and the state of the
I2C_SCL line and all the devices start counting their high periods. The first device to complete its
high period pulls the I2C_SCL line low again.
The relative priority of the contending masters is determined by a data arbitration procedure. A
bus master loses arbitration if it transmits logic "1" while another master transmits logic "0". The
losing masters immediately switch over to slave receive mode and stop driving I2C_SDA output
(see Figure 26-7). In this case the transition from master to slave mode does not generate a STOP
condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration.
I2C_SCL
I2C_SDA by
Master1
I2C_SDA by
Master2
Master 2 Loses Arbitration,
and becomes slave-receiver
I2C_SDA
Figure 26-7. Arbitration Procedure
Wait
Start counting high period
I2C_SCL1
I2C_SCL2
I2C_SCL
Internal Counter Reset
Figure 26-8. Clock Synchronization
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
26-7
I2C Interface
26.4.8 Handshaking and Clock Stretching
The clock synchronization mechanism can be used as a handshake in data transfers. Slave devices
can hold I2C_SCL low after completing one byte transfer. In such a case, the clock mechanism
halts the bus clock and forces the master clock into wait states until the slave releases I2C_SCL.
Slaves may also slow down the transfer bit rate. After the master has driven I2C_SCL low, the
slave can drive I2C_SCL low for the required period and then release it. If the slave I2C_SCL low
period is longer than the master I2C_SCL low period, the resulting I2C_SCL bus signal low period
is stretched.
26.5
Memory Map/Register Definition
Table 26-1 lists the configuration registers used in the I2C interface.
Table 26-1. I2C Interface Memory Map
IPSBAR Offset
Mnemonic
[31:24]
[23:0]
Access
0x0300
I2ADR
I2C Address Register
Reserved
R/W
Reserved
R/W
I2C
0x0304
I2FDR
Frequency Divider Register
0x0308
I2CR
I2C Control Register
Reserved
R/W
0x030C
I2SR
I2C
Reserved
R/W
0x0310
I2DR
Reserved
R/W
Status Register
I2C Data I/O Register
26.5.1 I2C Address Register (I2ADR)
The I2ADR holds the address the I2C responds to when addressed as a slave. Note that it is not the
address sent on the bus during the address transfer.
7
6
5
R
4
3
2
1
ADR
0
0
W
Reset
Address
0
0
0
0
0
0
0
0
IPSBAR + 0x00_0300
Figure 26-9. I2C Address Register (I2ADR)
Table 26-2. I2ADR Field Descriptions
Bits
Name
Description
7–1
ADR
Slave address. Contains the specific slave address to be used by the I2C module. Slave
mode is the default I2C mode for an address match on the bus.
0
—
Reserved, should be cleared.
MCF5275 Reference Manual, Rev. 2
26-8
Freescale Semiconductor
Memory Map/Register Definition
26.5.2 I2C Frequency Divider Register (I2FDR)
The I2FDR, shown in Figure 26-10, provides a programmable prescaler to configure the I2C clock
for bit-rate selection.
R
7
6
0
0
0
0
5
4
3
2
1
0
0
0
0
IC
W
Reset
0
Address
0
0
IPSBAR + 0x00_0304
Figure 26-10. I2C Frequency Divider Register (I2FDR)
Table 26-3. I2FDR Field Descriptions
Bits
Name
Description
7–6
—
Reserved, should be cleared.
5–0
IC
I2C clock rate. Prescales the clock for bit-rate selection. The serial bit clock frequency is
equal to the internal bus clock divided by the divider shown below. Due to potentially slow
I2C_SCL and I2C_SDA rise and fall times, bus signals are sampled at the prescaler
frequency.
IC
Divider
IC
Divider
IC
Divider
IC
Divider
0x00
28
0x10
288
0x20
20
0x30
160
0x01
30
0x11
320
0x21
22
0x31
192
0x02
34
0x12
384
0x22
24
0x32
224
0x03
40
0x13
480
0x23
26
0x33
256
0x04
44
0x14
576
0x24
28
0x34
320
0x05
48
0x15
640
0x25
32
0x35
384
0x06
56
0x16
768
0x26
36
0x36
448
0x07
68
0x17
960
0x27
40
0x37
512
0x08
80
0x18
1152
0x28
48
0x38
640
0x09
88
0x19
1280
0x29
56
0x39
768
0x0A
104
0x1A
1536
0x2A
64
0x3A
896
0x0B
128
0x1B
1920
0x2B
72
0x3B
1024
0x0C
144
0x1C
2304
0x2C
80
0x3C
1280
0x0D
160
0x1D
2560
0x2D
96
0x3D
1536
0x0E
192
0x1E
3072
0x2E
112
0x3E
1792
0x0F
240
0x1F
3840
0x2F
128
0x3F
2048
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
26-9
I2C Interface
26.5.3 I2C Control Register (I2CR)
The I2CR is used to enable the I2C module and the I2C interrupt. It also contains bits that govern
operation as a slave or a master.
R
7
6
5
4
3
2
1
0
IEN
IIEN
MSTA
MTX
TXAK
RSTA
0
0
0
0
0
0
0
0
0
0
W
Reset
Address
IPSBAR + 0x00_0308
Figure 26-11. I2C Control Register (I2CR)
Table 26-4. I2CR Field Descriptions
Bits
Name
Description
7
IEN
I2C enable. Controls the software reset of the entire I2C module. If the module is enabled
in the middle of a byte transfer, slave mode ignores the current bus transfer and starts
operating when the next START condition is detected. Master mode is not aware that the
bus is busy; so initiating a start cycle may corrupt the current bus cycle, ultimately causing
either the current master or the I2C module to lose arbitration, after which bus operation
returns to normal.
0 The I2C module is disabled, but registers can still be accessed.
1 The I2C module is enabled. This bit must be set before any other I2CR bits have any
effect.
6
IIEN
I2C interrupt enable.
0 I2C module interrupts are disabled, but currently pending interrupt condition are not
cleared.
1 I2C module interrupts are enabled. An I2C interrupt occurs if I2SR[IIF] is also set.
5
MSTA
Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without
generating a STOP signal.
0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.
1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects
master mode.
4
MTX
Transmit/receive mode select bit. Selects the direction of master and slave transfers.
0 Receive
1 Transmit. When the device is addressed as a slave, software should set MTX according
to I2SR[SRW]. In master mode, MTX should be set according to the type of transfer
required. Therefore, when the MCU addresses a slave device, MTX is always 1.
3
TXAK
Transmit acknowledge enable. Specifies the value driven onto I2C_SDA during
acknowledge cycles for both master and slave receivers. Note that writing TXAK applies
only when the I2C bus is a receiver.
0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte
of data.
1 No acknowledge signal response is sent (that is, acknowledge bit = 1).
MCF5275 Reference Manual, Rev. 2
26-10
Freescale Semiconductor
Memory Map/Register Definition
Table 26-4. I2CR Field Descriptions (Continued)
Bits
Name
Description
2
RSTA
Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes
loss of arbitration.
0 No repeat start
1 Generates a repeated START condition.
1–0
—
Reserved, should be cleared.
26.5.4 I2C Status Register (I2SR)
This I2SR contains bits that indicate transaction direction and status.
R
7
6
5
4
3
2
1
0
ICF
IAAS
IBB
IAL
0
SRW
IIF
RXAK
1
0
0
0
0
0
0
1
W
Reset
Address
IPSBAR + 0x00_030C
Figure 26-12. I2C Status Register (I2SR)
Table 26-5. I2SR Field Descriptions
Bits
Name
Description
7
ICF
6
IAAS
5
IBB
I2C bus busy bit. Indicates the status of the bus.
0 Bus is idle. If a STOP signal is detected, IBB is cleared.
1 Bus is busy. When START is detected, IBB is set.
4
IAL
Arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by
software by writing zero to it.)
• I2C_SDA sampled low when the master drives high during an address or data-transmit
cycle.
• I2C_SDA sampled low when the master drives high during the acknowledge bit of a
data-receive cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
3
—
Reserved, should be cleared.
Data transferring bit. While one byte of data is transferred, ICF is cleared.
0 Transfer in progress
1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer.
I2C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU
must check SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit.
0 Not addressed.
1 Addressed as a slave. Set when its own address (IADR) matches the calling address.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
26-11
I2C Interface
Table 26-5. I2SR Field Descriptions (Continued)
Bits
Name
Description
2
SRW
Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of
the calling address sent from the master. SRW is valid only when a complete transfer has
occurred, no other transfers have been initiated, and the I2C module is a slave and has an
address match.
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
1
IIF
I2C interrupt. Must be cleared by software by writing a zero in the interrupt routine.
0 No I2C interrupt pending
1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set
when one of the following occurs:
• Complete one byte transfer (set at the falling edge of the ninth clock)
• Reception of a calling address that matches its own specific address in slave-receive
mode
• Arbitration lost
0
RXAK
Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle.
0 An acknowledge signal was received after the completion of 8-bit data transmission on
the bus
1 No acknowledge signal was detected at the ninth clock.
26.5.5 I2C Data I/O Register (I2DR)
In master-receive mode, reading the I2DR allows a read to occur and initiates next the byte data
to be received. In slave mode, the same function is available once the I2C has received its slave
address.
7
6
5
4
R
3
2
1
0
0
0
0
0
Data
W
Reset
Address
0
0
0
0
IPSBAR + 0x00_0310
Figure 26-13. I2C Data I/O Register (I2DR)
MCF5275 Reference Manual, Rev. 2
26-12
Freescale Semiconductor
I2C Programming Examples
Table 26-6. I2DR Field Description
26.6
Bit
Name
Description
7–0
DATA
I2C data. In master transmit mode, when data is written to this register, a data transfer is
initiated. The most significant bit is sent first. In master receive mode, reading this register
initiates the reception of the next byte of data. In slave mode, the same functions are
available after an address match has occurred.
Note: 1. In master transmit mode, the first byte of data written to I2DR following assertion
of I2CR[MSTA] is used for the address transfer and should comprise the calling address
(in position D7–D1) concatenated with the required R/W bit (in position D0). This bit (D0)
is not automatically appended by the hardware, software must provide the appropriate
R/W bit.
Note: 2. I2CR[MSTA] generates a start when a master does not already own the bus.
I2CR[RSTA] generates a start (restart) without the master first issuing a stop (i.e., the
master already owns the bus). In order to start the read of data, a dummy read to this
register starts the read process from the slave. The next read of the I2DR register contains
the actual data.
I2C Programming Examples
The following examples show programming for initialization, signaling START, post-transfer
software response, signalling STOP, and generating a repeated START.
26.6.1 Initialization Sequence
Before the interface can transfer serial data, registers must be initialized, as follows:
1. Set I2FDR[IC] to obtain I2C_SCL frequency from the system bus clock. See
Section 26.5.2, “I2C Frequency Divider Register (I2FDR).”
2. Update the I2ADR to define its slave address.
3. Set I2CR[IEN] to enable the I2C bus interface system.
4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and
interrupt-enable or not.
NOTE
If I2SR[IBB] is set when the I C bus module is enabled, execute the
following pseudocode sequence before proceeding with normal
initialization code. This issues a STOP command to the slave device,
placing it in idle state as if it were just power-cycled on.
2
I2CR = 0x0
I2CR = 0xA0
dummy read of I2DR
I2SR = 0x0
I2CR = 0x0
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
26-13
I2C Interface
26.6.2 Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the
master transmitter mode. On a multiple-master bus system, I2SR[IBB] must be tested to determine
whether the serial bus is free. If the bus is free (IBB = 0), the START signal and the first byte (the
slave address) can be sent. The data written to the data register comprises the address of the desired
slave and the lsb indicates the transfer direction.
The free time between a STOP and the next START condition is built into the hardware that
generates the START cycle. Depending on the relative frequencies of the system clock and the
I2C_SCL period, it may be necessary to wait until the I2C is busy after writing the calling address
to the I2DR before proceeding with the following instructions.
The following example signals START and transmits the first byte of data (slave address):
CHFLAG
MOVE.B I2SR,-(A0)
BTST.B #5, (A0)+
BNE.S CHFLAG
TXSTART MOVE.B I2CR,-(A0)
BSET.B #4,(A0)
MOVE.B (A0)+, I2CR
MOVE.B I2CR, -(A0)
BSET.B #5, (A0)
MOVE.B (A0)+, I2CR
MOVE.B CALLING,-(A0)
MOVE.B (A0)+, I2DR
IFREE
MOVE.B I2SR,-(A0)
;Check I2SR[MBB]
;If I2SR[MBB] = 1, wait until it is clear
;Set transmit mode
;Set master mode
;Generate START condition
;Transmit the calling address, D0=R/W
;Check I2SR[MBB]
;If it is clear, wait until it is set.
BTST.B #5, (A0)+
BEQ.S IFREE;
26.6.3 Post-Transfer Software Response
Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is
finished. I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during
initialization by setting I2CR[IIEN]. Software must first clear I2SR[IIF] in the interrupt routine.
I2SR[ICF] is cleared either by reading from I2DR in receive mode or by writing to I2DR in
transmit mode.
Software can service the I2C I/O in the main program by monitoring IIF if the interrupt function
is disabled. Polling should monitor IIF rather than ICF because that operation is different when
arbitration is lost.
When an interrupt occurs at the end of the address cycle, the master is always in transmit mode;
that is, the address is sent. If master receive mode is required I2CR[MTX] should be toggled.
MCF5275 Reference Manual, Rev. 2
26-14
Freescale Semiconductor
I2C Programming Examples
During slave-mode address cycles (I2SR[IAAS] = 1), I2SR[SRW] is read to determine the
direction of the next transfer. MTX is programmed accordingly. For slave-mode data cycles (IAAS
= 0), SRW is invalid. MTX should be read to determine the current transfer direction.
The following is an example of a software response by a master transmitter in the interrupt routine
(see Figure 26-14).
I2SR
LEA.L I2SR,-(A7)
BCLR.B #1,(A7)+
MOVE.B I2CR,-(A7)
BTST.B #5,(A7)+
BEQ.S SLAVE
MOVE.B I2CR,-(A7)
BTST.B #4,(A7)+
BEQ.S RECEIVE
MOVE.B I2SR,-(A7)
BTST.B #0,(A7)+
BNE.B END
TRANSMITMOVE.B DATABUF,-(A7)
MOVE.B (A7)+, I2DR
;Load effective address
;Clear the IIF flag
;Push the address on stack,
;check the MSTA flag
;Branch if slave mode
;Push the address on stack
;check the mode flag
;Branch if in receive mode
;Push the address on stack,
;check ACK from receiver
;If no ACK, end of transmission
;Stack data byte
;Transmit next byte of data
26.6.4 Generation of STOP
A data transfer ends when the master signals a STOP, which can occur after all data is sent, as in
the following example.
MASTX
END
MOVE.B I2SR, -(A7)
BTST.B #0,(A7)+
BNE.B END
MOVE.B TXCNT,D0
BEQ.S END
MOVE.B DATABUF,-(A7)
MOVE.B (A7)+,I2DR
MOVE.B TXCNT,D0
SUBQ.L #1,D0
MOVE.B D0,TXCNT
BRA.S EMASTX;Exit
LEA.L I2CR,-(A7)
BCLR.B #5,(A7)+
EMASTX RTE
;If no ACK, branch to end
;Get value from the transmitting counter
;If no more data, branch to end
;Transmit next byte of data
;Decrease the TXCNT
;Generate a STOP condition
;Return from interrupt
For a master receiver to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the
next-to-last byte. Before the last byte is read, a STOP signal must be generated, as in the following
example.
MASR
MOVE.B RXCNT,D0
SUBQ.L #1,D0
MOVE.B D0,RXCNT
BEQ.S ENMASR
MOVE.B RXCNT,D1
;Decrease RXCNT
;Last byte to be read
;Check second-to-last byte to be read
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
26-15
I2C Interface
EXTB.L D1
SUBI.L #1,D1;
BNE.S NXMAR
LAMAR BSET.B #3,I2CR
BRA NXMAR
ENMASR
NXMAR
BCLR.B #5,I2CR
MOVE.B I2DR,RXBUF
;Not last one or second last
;Disable ACK
;Last one, generate STOP signal
;Read data and store RTE
26.6.5 Generation of Repeated START
After the data transfer, if the master still wants the bus, it can signal another START followed by
another slave address without signalling a STOP, as in the following example.
RESTART MOVE.B
BSET.B
MOVE.B
MOVE.B
MOVE.B
I2CR,-(A7)
#2, (A7)
(A7)+, I2CR
CALLING,-(A7)
CALLING,-(A7)
;Repeat START (RESTART)
;Transmit the calling address, D0=R/W-
MOVE.B (A7)+, I2DR
26.6.6 Slave Mode
In the slave interrupt service routine, software should poll the I2SR[IAAS] bit to determine if the
controller has received its slave address. If IAAS is set, software should set the transmit/receive
mode select bit (I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears the IAAS
automatically. The only time IAAS is read as set is from the interrupt at the end of the address cycle
where an address match occurred; interrupts resulting from subsequent data transfers will have
IAAS cleared. A data transfer can now be initiated by writing information to I2DR for slave
transmits, or read from I2DR in slave-receive mode. A dummy read of I2DR in slave/receive mode
releases I2C_SCL, allowing the master to send data.
In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data.
Setting RXAK means an end-of-data signal from the master receiver, after which software must
switch it from transmitter to receiver mode. Reading I2DR then releases I2C_SCL so that the
master can generate a STOP signal.
26.6.7 Arbitration Lost
If several devices try to engage the bus at the same time, one becomes master. Hardware
immediately switches devices that lose arbitration to slave receive mode. Data output to I2C_SDA
stops, but I2C_SCL is still generated until the end of the byte during which arbitration is lost. An
interrupt occurs at the falling edge of the ninth clock of this transfer with I2SR[IAL] = 1 and
I2CR[MSTA] = 0.
MCF5275 Reference Manual, Rev. 2
26-16
Freescale Semiconductor
I2C Programming Examples
If a device that is not a master tries to transmit or do a START, hardware inhibits the transmission,
clears MSTA without signalling a STOP, generates an interrupt to the CPU, and sets IAL to
indicate a failed attempt to engage the bus. When considering these cases, the slave service routine
should first test IAL and software should clear it if it is set.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
26-17
I2C Interface
Clear
IIF
Y
TX
TX/Rx
?
Master
Mode?
N
Y
RX
Arbitration
Lost?
N
Last Byte
Transmitted
?
N
RXAK= 0
?
Clear IAL
Y
Last
Byte to be
Read ?
N
Y
Y
N
End of
ADDR Cycle
(Master RX)
?
N
Write Next
Byte to I2DR
N
Y
Y
(Read)Y
N Data
Cycle
SRW=1
?
Generate
STOP Signal
Switch to
Rx Mode
Generate
STOP Signal
Tx/Rx
?
N (WRITE)
N
Y
Set TX
Mode
Write Data
to I2DR
Dummy Read
from I2DR
IAAS=1
?
Address Y
Cycle
2nd Last
Byte to be
Read?
Set TXAK =1
Y
IAAS=1
?
Read Data
from I2DR
And Store
RX
TX
ACK from
Receiver
?
N
Read Data
from I2DR
and Store
Tx Next
Byte
Set RX
Mode
Switch to
Rx Mode
Dummy Read
from I2DR
Dummy Read
from I2DR
RTE
Figure 26-14. Flow-Chart of Typical I2C Interrupt Routine
MCF5275 Reference Manual, Rev. 2
26-18
Freescale Semiconductor
Chapter 27
UART Modules
27.1
Introduction
This chapter describes the use of the universal asynchronous receiver/transmitters (UARTs)
implemented on the MCF5275 and includes programming examples.
NOTE
The designation “n” is used throughout this section to refer to registers
or signals associated with one of the three identical UART modules:
UART0, UART1, or UART2.
27.1.1
Overview
The MCF5275 contains three independent UARTs. Each UART can be clocked by the internal bus
clock, eliminating the need for an external UART clock. As Figure 27-1 shows, each UART
module interfaces directly to the CPU and consists of the following:
•
•
•
•
Serial communication channel
Programmable clock generation
Interrupt control logic and DMA request logic
Internal channel control logic
Internal Channel
Control Logic
UnCTS
Serial
Communications
Channel
Interrupt Request
(to Interrupt Controller)
Transmit DMA Request
Receive DMA Request
UnRXD
UnTXD
Interrupt Control
Logic
DMA Request
Logic
UnRTS
Programmable
Clock
Generation
External Signals
UART
Internal Bus Clock (fsys/2)
or External clock (DTnIN)
(To SCM and DMA Controller)
Figure 27-1. UART Block Diagram
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
27-1
UART Modules
NOTE
UARTn can be clocked by the DTnIN pin. However, if the timers are
used, then input capture mode is not available for that timer.
The serial communication channel provides a full-duplex asynchronous/synchronous receiver and
transmitter deriving an operating frequency from the internal bus clock or an external clock using
the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting
appropriate start, stop, and parity bits. It outputs the resulting stream on the channel transmitter
serial data output (UnTXD). See Section 27.4.2.1, “Transmitter.”
The receiver converts serial data from the channel receiver serial data input (UnRXD) to parallel
format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled
character onto the bus during read operations. The receiver may be polled, interrupt driven, or use
DMA requests for servicing. See Section 27.4.2.2, “Receiver.”
NOTE
The GPIO module must be configured to enable the peripheral
function of the appropriate pins (refer to Chapter 12, “General
Purpose I/O Module”) prior to configuring the UART module.
27.1.2
Features
The MCF5275 contains three independent UART modules with the following features:
•
•
•
•
•
•
•
•
•
•
•
Each can be clocked by an external clock or by the internal bus clock (eliminating a need
for an external UART clock).
Full-duplex asynchronous/synchronous receiver/transmitter channel
Quadruple-buffered receiver
Double-buffered transmitter
Independently programmable receiver and transmitter clock sources
Programmable data format:
— 5–8 data bits plus parity
— Odd, even, no parity, or force parity
— One, one-and-a-half, or two stop bits
Each channel programmable to normal (full-duplex), automatic echo, local loop-back, or
remote loop-back mode
Automatic wake-up mode for multidrop applications
Four maskable interrupt conditions
All three UARTs have DMA request capability
Parity, framing, and overrun error detection
MCF5275 Reference Manual, Rev. 2
27-2
Freescale Semiconductor
External Signal Description
•
•
•
•
False-start bit detection
Line-break detection and generation
Detection of breaks originating in the middle of a character
Start/end break interrupt/status
27.2
External Signal Description
Figure 27-1 shows both the external and internal signal groups.
An internal interrupt request signal is provided to notify the interrupt controller of an interrupt
condition. The output is the logical NOR of unmasked UISRn bits. The interrupt level and priority
are programmed in the interrupt controller—ICR13 for UART0, ICR14 for UART1, and ICR15 for
UART2. See Section 13.2.1.6, “Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)).”
Note that the UARTs can also be configured to automatically transfer data by using the DMA
rather than interrupting the core. When there is data in the receiver FIFO or when the transmit
holding register is empty, a DMA request can be issued. For more information on generating DMA
requests, refer to Section 27.4.6.1.2, “Setting up the UART to Request DMA Service,” and
Section 18.3.1, “DMA Request Control (DMAREQC).”
Table 27-1 briefly describes the UART module signals.
NOTE
The terms ‘assertion’ and ‘negation’ are used to avoid confusion
between active-low and active-high signals. ‘Asserted’ indicates that
a signal is active, independent of the voltage level; ‘negated’ indicates
that a signal is inactive.
Table 27-1. UART Module Signals
Signal
Description
Transmitter Serial
Data Output
(UnTXD)
UnTXD is held high (mark condition) when the transmitter is disabled, idle, or operating in the
local loop-back mode. Data is shifted out on UnTXD on the falling edge of the clock source, with
the least significant bit (lsb) sent first.
Receiver Serial
Data Input
(UnRXD)
Data received on UnRXD is sampled on the rising edge of the clock source, with the lsb
received first.
Clear-to- Send
(UnCTS)
This input can generate an interrupt on a change of state.
Request-to-Send
(UnRTS)
This output can be programmed to be negated or asserted automatically by either the receiver
or the transmitter. When connected to a transmitter’s UnCTS, UnRTS can control serial data
flow.
Figure 27-2 shows a signal configuration for a UART/RS-232 interface.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
27-3
UART Modules
UART
RS-232 Transceiver
UnRTS
DI2
UnCTS
DO2
UnTXD
DI1
UnRXD
DO1
Figure 27-2. UART/RS-232 Interface
27.3
Memory Map/Register Definition
This section contains a detailed description of each register and its specific function. Flowcharts
in Section 27.4.6, “Programming,” describe basic UART module programming. The operation of
the UART module is controlled by writing control bytes into the appropriate registers. Table 27-2
is a memory map for UART module registers.
NOTE
UART registers are accessible only as bytes.
NOTE
Interrupt can mean either an interrupt request asserted to the CPU or a
DMA request.
Table 27-2. UART Module Memory Map
IPSBAR
Offset
UART0
UART1
UART2
[31:24]
[23:16]
[15:8]
[7:0]
0x00_0200
0x00_0240
0x00_0280
UART Mode Registers1 (UMR1n) , (UMR2n)
Reserved
0x00_0204
0x00_0244
0x00_0284
(Read) UART Status Registers (USRn)
Reserved
0x00_0208
0x00_0248
0x00_0288
0x00_020C
0x00_024C
0x00_028C
1(UCSRn)
(Write) UART Clock Select register
Reserved
(Read) Do not access2
Reserved
(Write) UART Command Registers (UCRn)
Reserved
(UART/Read) UART Receive Buffers (URBn)
Reserved
(UART/Write) UART Transmit Buffers (UTBn)
Reserved
MCF5275 Reference Manual, Rev. 2
27-4
Freescale Semiconductor
Memory Map/Register Definition
Table 27-2. UART Module Memory Map (Continued)
IPSBAR
Offset
[31:24]
UART0
UART1
UART2
[23:16]
[15:8]
0x00_0210
0x00_0250
0x00_0290
(Read) UART Input Port Change Register
(UIPCRn)
Reserved
(Write) UART Auxiliary Control Register1 (UACRn)
Reserved
0x00_0214
0x00_0254
0x00_0294
(Read) UART interrupt Status Register (UISRn)
Reserved
(Write) UART Interrupt Mask Register (UIMRn)
Reserved
0x00_0218
0x00_0258
0x00_0298
(Read) Do not access2
Reserved
(Write) UART Divider Upper Register (UBG1n)
Reserved
0x00_021C
0x00_025C
0x00_029C
(Read) Do not access2
Reserved
(Write) UART Divider Lower Register (UBG2n)
Reserved
0x00_0234
0x00_0274
0x00_02B4
(Read) UART Input Port Register (UIPn)
Reserved
(Write) Do not access2
Reserved
0x00_0238
0x00_0278
0x00_02B8
(Read) Do not access2
Reserved
(Write) UART Output Port Bit Set Command
Register (UOP1n)
Reserved
0x00_023C
0x00_027C
0x00_02BC
(Read) Do not access2
Reserved
(Write) UART Output Port Bit Reset Command
Register (UOP0n)
Reserved
[7:0]
1
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset
command. That is, if channel operation is not disabled, undesirable results may occur.
2 This address is for factory testing. Reading this location results in undesired effects and possible incorrect
transmission or reception of characters. Register contents may also be changed.
27.3.1
UART Mode Registers 1 (UMR1n)
The UMR1n registers control configuration. UMR1n can be read or written when the mode
register pointer points to it, at RESET or after a RESET MODE REGISTER POINTER command using
UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
27-5
UART Modules
7
6
5
R RXRTS RXIRQ/
FFULL
W
Reset
Address
0
0
4
ERR
0
3
PM
0
2
1
PT
0
0
0
B/C
0
0
IPSBAR + 0x0200 (UART0); IPSBAR + 0x0240 (UART1);
IPSBAR + 0x0280 (UART2)
After UMR1n is read or written, the pointer points to UMR2n.
Figure 27-3. UART Mode Registers 1 (UMR1n)
Table 27-3. UMR1n Field Descriptions
Bits
Name
Description
7
RxRTS
Receiver request-to-send. Allows the UnRTS output to control the UnCTS input of the
transmitting device to prevent receiver overrun. If both the receiver and transmitter are
incorrectly programmed for UnRTS control, UnRTS control is disabled for both. Transmitter
RTS control is configured in UMR2n[TxRTS].
0 The receiver has no effect on UnRTS.
1 When a valid start bit is received, UnRTS is negated if the UART's FIFO is full. UnRTS is
reasserted when the FIFO has an empty position available.
6
RxIRQ/
FFULL
Receiver interrupt select.
0 RxRDY is the source that generates interrupt or DMA requests.
1 FFULL is the source that generates interrupt or DMA requests.
5
ERR
Error mode. Configures the FIFO status bits, USRn[RB,FE,PE].
0 Character mode. The USRn values reflect the status of the character at the top of the FIFO.
ERR must be 0 for correct A/D flag information when in multidrop mode.
1 Block mode. The USRn values are the logical OR of the status for all characters reaching
the top of the FIFO since the last RESET ERROR STATUS command for the channel was issued.
See Section 27.3.5, “UART Command Registers (UCRn).”
4–3
PM
Parity mode. Selects the parity or multidrop mode for the channel. The parity bit is added to the
transmitted character, and the receiver performs a parity check on incoming data. The value of
PM affects PT, as shown below.
2
PT
Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or
address character is transmitted (PM = 11).
PM
1–0
B/C
Parity Mode
Parity Type (PT= 0)
Parity Type (PT= 1)
00
With parity
Even parity
Odd parity
01
Force parity
Low parity
High parity
10
No parity
11
Multidrop mode
n/a
Data character
Address character
Bits per character. Select the number of data bits per character to be sent. The values shown
do not include start, parity, or stop bits.
00 5 bits
01 6 bits
10 7 bits
11 8 bits
MCF5275 Reference Manual, Rev. 2
27-6
Freescale Semiconductor
Memory Map/Register Definition
27.3.2
UART Mode Register 2 (UMR2n)
The UMR2n registers control UART module configuration. UMR2n can be read or written when
the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses
do not update the pointer.
7
R
6
CM
5
4
3
2
TXRTS TXCTS
1
0
0
0
SB
W
Reset
Address
0
0
0
0
0
0
IPSBAR + 0x0200 (UART0); IPSBAR + 0x0240 (UART1);
IPSBAR + 0x0280 (UART2)
After UMR1n is read or written, the pointer points to UMR2n.
Figure 27-4. UART Mode Register 2 (UMR2n)
Table 27-4. UMR2n Field Descriptions
Bits
Name
Description
7–6
CM
Channel mode. Selects a channel mode. Section 27.4.3, “Looping Modes,” describes individual
modes.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
5
TxRTS
Transmitter ready-to-send. Controls negation of UnRTS to automatically terminate a message
transmission. Attempting to program a receiver and transmitter in the same channel for UnRTS
control is not permitted and disables UnRTS control for both.
0 The transmitter has no effect on UnRTS.
1 In applications where the transmitter is disabled after transmission completes, setting this bit
automatically clears UOP[RTS] one bit time after any characters in the channel transmitter
shift and holding registers are completely sent, including the programmed number of stop bits.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
27-7
UART Modules
Table 27-4. UMR2n Field Descriptions (Continued)
Bits
Name
Description
4
TxCTS
Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation
of the transmitter.
0 UnCTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of UnCTS each time it is
ready to send a character. If UnCTS is asserted, the character is sent; if it is deasseted, the
channel UnTXD remains in the high state and transmission is delayed until UnCTS is
asserted. Changes in UnCTS as a character is being sent do not affect its transmission.
3–0
SB
Stop-bit length control. Selects the length of the stop bit appended to the transmitted character.
Stop-bit lengths of 9/16 to 2 bits are programmable for 6–8 bit characters. Lengths of 1-1/16 to
2 bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high
condition at the center of the first stop-bit position, that is, one bit time after the last data bit or
after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing
bit 3 selects one stop bit and setting bit 3 selects two stop bits for transmission.
27.3.3
SB
5 Bits
6–8 Bits
SB
5–8 Bits
0000
1.063
0.563
1000
1.563
0001
1.125
0.625
1001
1.625
0010
1.188
0.688
1010
1.688
0011
1.250
0.750
1011
1.750
0100
1.313
0.813
1100
1.813
0101
1.375
0.875
1101
1.875
0110
1.438
0.938
1110
1.938
0111
1.500
1.000
1111
2.000
UART Status Registers (USRn)
The USRn registers, shown in Figure 27-5, show the status of the transmitter, the receiver, and the
FIFO.
R
7
6
5
4
RB
FE
PE
OE
0
0
0
0
3
2
1
0
TXEMP TXRDY FFULL RXRDY
W
Reset
Address
0
0
0
0
IPSBAR + 0x0204 (USR0); IPSBAR + 0x0244 (USR1);
IPSBAR + 0x0284 (USR2)
Figure 27-5. UART Status Register (USRn)
MCF5275 Reference Manual, Rev. 2
27-8
Freescale Semiconductor
Memory Map/Register Definition
Table 27-5. USRn Field Descriptions
Bits
Name
Description
7
RB
Received break. The received break circuit detects breaks that originate in the middle of a
received character. However, a break in the middle of a character must persist until the end
of the next detected character time.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. Only a
single FIFO position is occupied when a break is received. Further entries to the FIFO
are inhibited until UnRXD returns to the high state for at least one-half bit time, which is
equal to two successive edges of the UART clock. RB is valid only when RxRDY = 1.
6
FE
Framing error.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was
received. The stop-bit check occurs in the middle of the first stop-bit position. FE is valid
only when RxRDY = 1.
5
PE
Parity error. Valid only if RxRDY = 1.
0 No parity error occurred.
1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO
was received with incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the
received address or data (A/D) bit. PE is valid only when RxRDY = 1.
4
OE
Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon
receipt of a new character when the FIFO is full and a character is already in the shift
register waiting for an empty FIFO position. When this occurs, the character in the
receiver shift register and its break detect, framing error status, and parity error, if any,
are lost. OE is cleared by the RESET ERROR STATUS command in UCRn.
3
TxEMP
Transmitter empty.
0 The transmit buffer is not empty. Either a character is being shifted out, or the transmitter
is disabled. The transmitter is enabled/disabled by programming UCRn[TC].
1 The transmitter has underrun (both the transmitter holding register and transmitter shift
registers are empty). This bit is set after transmission of the last stop bit of a character
if there are no characters in the transmitter holding register awaiting transmission.
2
TxRDY
Transmitter ready.
0 The CPU loaded the transmitter holding register or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TxRDY is set when
a character is sent to the transmitter shift register or when the transmitter is first enabled.
If the transmitter is disabled, characters loaded into the transmitter holding register are
not sent.
1
FFULL
FIFO full.
0 The FIFO is not full but may hold up to two unread characters.
1 A character was received and the receiver FIFO is now full. Any characters received
when the FIFO is full are lost.
0
RxRDY
Receiver ready.
0 The CPU has read the receive buffer and no characters remain in the FIFO after this
read.
1 One or more characters were received and are waiting in the receive buffer FIFO.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
27-9
UART Modules
27.3.4
UART Clock Select Registers (UCSRn)
The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal
bus clock as the clocking source for the transmitter and receiver. See Section 27.4.1,
“Transmitter/Receiver Clock Source.” The transmitter and receiver can use different clock
sources. To use the internal bus clock for both, set UCSRn to 0xDD.
7
6
5
4
3
2
1
0
0
0
R
W
Reset
RCS
0
Address
0
TCS
0
0
0
0
IPSBAR + 0x0204 (UCSR0); IPSBAR + 0x0244 (UCSR1);
IPSBAR + 0x0284 (UCSR2)
Figure 27-6. UART Clock Select Register (UCSRn)
Table 27-6. UCSRn Field Descriptions
Bits
Name
7–4
RCS
Receiver clock select. Selects the clock source for the receiver channel.
1101 Prescaled internal bus clock
1110 DTIN divided by 16
1111 DTIN
3–0
TCS
Transmitter clock select. Selects the clock source for the transmitter channel.
1101 Prescaled internal bus clock
1110 DTIN divided by 16
1111 DTIN
27.3.5
Description
UART Command Registers (UCRn)
The UCRs, shown in Figure 27-7, supply commands to the UART. Only multiple commands that
do not conflict can be specified in a single write to a UCRn. For example, RESET TRANSMITTER
and ENABLE TRANSMITTER cannot be specified in one command.
7
6
5
4
3
2
1
0
R
W
0
Reset
0
Address
MISC
0
0
TC
0
0
RC
0
0
0
IPSBAR + I0x0208 (UCR0); IPSBAR + 0x0248 (UCR1);
IPSBAR + 0x0288 (UCR2)
Figure 27-7. UART Command Register (UCRn)
Table 27-7 describes UCRn fields and commands. Examples in Section 27.4.2, “Transmitter and
Receiver Operating Modes,” show how these commands are used.
MCF5275 Reference Manual, Rev. 2
27-10
Freescale Semiconductor
Memory Map/Register Definition
Table 27-7. UCRn Field Descriptions
Bits
Value
Command
6–4
Description
MISC Field (This field selects a single command.)
000
NO COMMAND
—
001
RESET MODE
Causes the mode register pointer to point to UMR1n.
REGISTER POINTER
010
RESET RECEIVER
Immediately disables the receiver, clears USRn[FFULL,RxRDY], and reinitializes
the receiver FIFO pointer. No other registers are altered. Because it places the
receiver in a known state, use this command instead of RECEIVER DISABLE when
reconfiguring the receiver.
011
RESET TRANSMITTER
Immediately disables the transmitter and clears USRn[TxEMP,TxRDY]. No other
registers are altered. Because it places the transmitter in a known state, use this
command instead of TRANSMITTER DISABLE when reconfiguring the transmitter.
100
RESET ERROR
STATUS
Clears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after
a data block is received.
RESET BREAK–
Clears the delta break bit, UISRn[DB].
101
CHANGE INTERRUPT
110
START BREAK
Forces UnTXD low. If the transmitter is empty, the break may be delayed up to one
bit time. If the transmitter is active, the break starts when character transmission
completes. The break is delayed until any character in the transmitter shift register
is sent. Any character in the transmitter holding register is sent after the break. The
transmitter must be enabled for the command to be accepted. This command
ignores the state of UnCTS.
111
STOP BREAK
Causes UnTXD to go high (mark) within two bit times. Any characters in the
transmit buffer are sent.
3–2
TC Field (This field selects a single command)
00
NO ACTION TAKEN
Causes the transmitter to stay in its current mode: if the transmitter is enabled, it
remains enabled; if the transmitter is disabled, it remains disabled.
01
TRANSMITTER
Enables operation of the channel’s transmitter. USRn[TxEMP,TxRDY] are set. If
the transmitter is already enabled, this command has no effect.
ENABLE
10
TRANSMITTER
DISABLE
11
—
Terminates transmitter operation and clears USRn[TxEMP,TxRDY]. If a character
is being sent when the transmitter is disabled, transmission completes before the
transmitter becomes inactive. If the transmitter is already disabled, the command
has no effect.
Reserved, do not use.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
27-11
UART Modules
Table 27-7. UCRn Field Descriptions (Continued)
Bits
Value
Command
Description
1–0
RC (This field selects a single command)
00
NO ACTION TAKEN
Causes the receiver to stay in its current mode. If the receiver is enabled, it
remains enabled; if disabled, it remains disabled.
01
RECEIVER ENABLE
If the UART module is not in multidrop mode (UMR1n[PM] ≠ 11), RECEIVER ENABLE
enables the channel's receiver and forces it into search-for-start-bit state. If the
receiver is already enabled, this command has no effect.
10
RECEIVER DISABLE
Disables the receiver immediately. Any character being received is lost. The
command does not affect receiver status bits or other control registers. If the
UART module is programmed for local loop-back or multidrop mode, the receiver
operates even though this command is selected. If the receiver is already
disabled, the command has no effect.
11
27.3.6
—
Reserved, do not use.
UART Receive Buffers (URBn)
The receive buffers (shown in Figure 27-8) contain one serial shift register and three receiver
holding registers, which act as a FIFO. UnRXD is connected to the serial shift register. The CPU
reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift
register is full (see Figure 27-18). RB contains the character in the receiver.
7
6
5
4
R
3
2
1
0
1
1
1
1
RB
W
Reset
Address
1
1
1
1
IPSBAR + 0x020C (URB0); IPSBAR + 0x024C (URB1);
IPSBAR + 0x028C (URB2)
Figure 27-8. UART Receive Buffer (URBn)
27.3.7
UART Transmit Buffers (UTBn)
The transmit buffers consist of the transmitter holding register and the transmitter shift register.
The holding register accepts characters from the bus master if channel’s USRn[TxRDY] is set. A
write to the transmit buffer clears USRn[TxRDY], inhibiting any more characters until the shift
register can accept more data. When the shift register is empty, it checks if the holding register has
a valid character to be sent (TxRDY = 0). If there is a valid character, the shift register loads it and
sets USRn[TxRDY] again. Writes to the transmit buffer when the channel’s TxRDY = 0 and when
the transmitter is disabled have no effect on the transmit buffer.
Figure 27-9 shows UTBn. TB contains the character in the transmit buffer.
MCF5275 Reference Manual, Rev. 2
27-12
Freescale Semiconductor
Memory Map/Register Definition
7
6
5
4
3
2
1
0
0
0
0
0
R
W
Reset
TB
0
Address
0
0
0
IPSBAR + 0x020C(UTB0); IPSBAR + 0x024C(UTB1);
IPSBAR + 0x028C(UTB2)
Figure 27-9. UART Transmit Buffer (UTBn)
27.3.8
UART Input Port Change Registers (UIPCRn)
The UIPCRs, shown in Figure 27-10, hold the current state and the change-of-state for UnCTS.
R
7
6
5
4
3
2
1
0
0
0
0
COS
0
0
0
CTS
0
0
0
0
1
1
1
UnCTS
W
Reset
Address IPSBAR + 0x0210 (UIPCR0); IPSBAR + 0x0250 (UIPCR1); IPSBAR +
0x0290 (UIPCR2)
Figure 27-10. UART Input Port Change Register (UIPCRn)
Table 27-8. UIPCRn Field Descriptions
Bits
Name
7–5
—
4
COS
3–1
—
0
CTS
27.3.9
Description
Reserved, should be cleared.
Change of state (high-to-low or low-to-high transition).
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears
UISRn[COS].
1 A change-of-state longer than 25–50 µs occurred on the UnCTS input. UACRn can be
programmed to generate an interrupt to the CPU when a change of state is detected.
Reserved, should be cleared.
Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the
state of UnCTS. If UnCTS is detected asserted at that time, COS is set, which initiates an
interrupt if UACRn[IEC] is enabled.
0 The current state of the UnCTS input is asserted.
1 The current state of the UnCTS input is deasserted.
UART Auxiliary Control Register (UACRn)
The UACRs, shown in Figure 27-8, control the input enable.
MCF5275 Reference Manual, Rev. 2
Freescale Semiconductor
27-13
UART Modules
7
6
5
4
3
2
1
0
W
0
0
0
0
0
0
0
IEC
Reset
0
0
0
0
0
0
0
0
R
Address
IPSBAR + 0x0210 (UACR0); IPSBAR + 0x0250 (UACR1); IPSBAR +
0x0290 (UACR2)
Figure 27-11. UART Auxiliary Control Register (UACRn)
Table 27-9. UACRn Field Descriptions
Bits
Name
7–1
—
0
IEC
Description
Reserved, should be cleared.
Input enable control.
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an
external transition on the UnCTS input (if UIMRn[COS] = 1).
27.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
The UISRs, shown in Figure 27-12, provide status for all potential interrupt sources. UISRn
contents are masked by UIMRn. If corresponding UISRn and UIMRn bits are set, the internal
interrupt output is asserted. If a UIMRn bit is cleared, the state of the corresponding UISRn bit has
no effect on the output.
The UISRn and UIMRn registers share the same space in memory. Reading this register provides">