NXP MPC561 32-bit Microcontrollers Reference Manual

MPC561/MPC563 Reference Manual
Additional Devices Supported:
MPC562
MPC564
MPC561RM
REV 1.2
08/2005
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125
[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 26668334
[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
[email protected]
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property
of their respective owners. The described product is a PowerPC
microprocessor. The PowerPC name is a trademark of IBM Corp. and used
under license
© Freescale Semiconductor, Inc. 2004, 2005. All rights reserved.
MPC561RM
REV 1.2
08/2005
Contents
Paragraph
Number
Title
Page
Number
About This Book lxxvii
Audience ..................................................................................................................... lxxvii
Organization ................................................................................................................ lxxvii
Suggested Reading ........................................................................................................ lxxx
Conventions and Nomenclature .................................................................................... lxxx
Notational Conventions ............................................................................................... lxxxi
Acronyms and Abbreviations ..................................................................................... lxxxii
References .................................................................................................................. lxxxiii
Chapter 1
Overview
1.1
1.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.1.5
1.3.1.6
1.3.1.7
1.3.1.8
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
1.3.3.5
1.3.3.6
1.4
1.5
1.6
1.7
1.8
Introduction ..................................................................................................................... 1-1
Block Diagram ................................................................................................................ 1-2
Key Features ................................................................................................................... 1-3
High-Performance CPU System ................................................................................. 1-3
RISC MCU Central Processing Unit (RCPU) ........................................................ 1-4
Unified System Interface Unit (USIU) ................................................................... 1-4
Burst Buffer Controller (BBC) Module .................................................................. 1-4
Flexible Memory Protection Unit ........................................................................... 1-5
Memory Controller ................................................................................................. 1-5
512-Kbytes of CDR3 Flash EEPROM Memory (UC3F) –
MPC563/MPC564 Only 1-5
32-Kbyte Static RAM (CALRAM) ........................................................................ 1-6
General Purpose I/O Support (GPIO) ..................................................................... 1-6
Nexus Debug Port (Class 3) ........................................................................................ 1-6
Integrated I/O System ................................................................................................. 1-6
Two Time Processor Units (TPU3) ........................................................................ 1-6
22-Channel Modular I/O System (MIOS14) .......................................................... 1-6
Two Enhanced Queued Analog-to-Digital Converter Modules (QADC64E) ........ 1-7
Three CAN 2.0B Controller (TouCAN) Modules .................................................. 1-7
Queued Serial Multi-Channel Module (QSMCM) ................................................. 1-8
Peripheral Pin Multiplexing (PPM) ........................................................................ 1-8
MPC561/MPC563 Optional Features ............................................................................. 1-9
Comparison of MPC561/MPC563 and MPC555 ........................................................... 1-9
Additional MPC561/MPC563 Differences ................................................................... 1-10
SRAM Keep-Alive Power Behavior ............................................................................. 1-11
MPC561/MPC563 Address Map .................................................................................. 1-11
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
iii
Contents
Paragraph
Number
1.9
Title
Page
Number
Supporting Documentation List .................................................................................... 1-14
Chapter 2
Signal Descriptions
2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.4.1
2.6.4.2
2.6.4.3
2.6.4.4
2.6.5
Signal Groupings ............................................................................................................ 2-1
Signal Summary .............................................................................................................. 2-3
MPC561/MPC563 Signal Multiplexing ................................................................... 2-20
READI Port Signal Sharing ...................................................................................... 2-21
Pad Module Configuration Register (PDMCR) ............................................................ 2-22
Pad Module Configuration Register (PDMCR2) .......................................................... 2-23
MPC561/MPC563 Development Support Signal Sharing ............................................ 2-28
JTAG Mode Selection .............................................................................................. 2-29
BDM Mode Selection ............................................................................................... 2-30
Nexus Mode Selection .............................................................................................. 2-30
Reset State ..................................................................................................................... 2-31
Signal Functionality Configuration Out of Reset ..................................................... 2-31
Signal State During Reset ......................................................................................... 2-31
Power-On Reset and Hard Reset .............................................................................. 2-32
Pull-Up/Pull-Down ................................................................................................... 2-32
Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only Signals .. 2-32
Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals .................... 2-32
Special Pull Resistor Disable Control Functionality (SPRDS) ............................ 2-32
Pull Device Select (PULL_SEL) .......................................................................... 2-33
Signal Reset States .................................................................................................... 2-33
Chapter 3
Central Processing Unit
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.6
RCPU Block Diagram .................................................................................................... 3-1
RCPU Key Features ........................................................................................................ 3-3
Instruction Sequencer ..................................................................................................... 3-3
Independent Execution Units .......................................................................................... 3-4
Branch Processing Unit (BPU) ................................................................................... 3-5
Integer Unit (IU) ......................................................................................................... 3-5
Load/Store Unit (LSU) ............................................................................................... 3-6
Floating-Point Unit (FPU) .......................................................................................... 3-6
Levels of the PowerPC ISA Architecture ....................................................................... 3-6
RCPU Programming Model ............................................................................................ 3-7
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
iv
Contents
Paragraph
Number
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.4.1
3.7.4.2
3.7.4.3
3.7.5
3.7.6
3.7.7
3.8
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.9.10
3.9.10.1
3.9.10.2
3.9.10.3
3.10
3.10.1
3.10.2
3.10.3
3.11
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.12
3.13
3.13.1
3.13.2
Title
Page
Number
User Instruction Set Architecture (UISA)
Register Set ............................................................................................................... 3-12
General-Purpose Registers (GPRs) ........................................................................... 3-12
Floating-Point Registers (FPRs) ............................................................................... 3-12
Floating-Point Status and Control Register (FPSCR) .............................................. 3-13
Condition Register (CR) ........................................................................................... 3-16
Condition Register CR0 Field Definition ............................................................. 3-17
Condition Register CR1 Field Definition ............................................................. 3-17
Condition Register CRn Field — Compare Instruction ....................................... 3-17
Integer Exception Register (XER) ............................................................................ 3-18
Link Register (LR) .................................................................................................... 3-19
Count Register (CTR) ............................................................................................... 3-19
VEA Register Set — Time Base (TB) .......................................................................... 3-20
OEA Register Set .......................................................................................................... 3-20
Machine State Register (MSR) ................................................................................. 3-20
DAE/Source Instruction Service Register (DSISR) ................................................. 3-22
Data Address Register (DAR) .................................................................................. 3-23
Time Base Facility (TB) — OEA ............................................................................. 3-23
Decrementer Register (DEC) .................................................................................... 3-23
Machine Status Save/Restore Register 0 (SRR0) ..................................................... 3-23
Machine Status Save/Restore Register 1 (SRR1) ..................................................... 3-23
General SPRs (SPRG0–SPRG3) .............................................................................. 3-24
Processor Version Register (PVR) ........................................................................... 3-25
Implementation-Specific SPRs ................................................................................. 3-25
EIE, EID, and NRI Special-Purpose Registers ..................................................... 3-25
Floating-Point Exception Cause Register (FPECR) ............................................. 3-26
Additional Implementation-Specific Registers ..................................................... 3-27
Instruction Set ............................................................................................................... 3-27
Instruction Set Summary .......................................................................................... 3-28
Recommended Simplified Mnemonics ..................................................................... 3-33
Calculating Effective Addresses ............................................................................... 3-34
Exception Model ........................................................................................................... 3-34
Exception Classes ..................................................................................................... 3-35
Ordered Exceptions ................................................................................................... 3-35
Unordered Exceptions ............................................................................................... 3-35
Precise Exceptions .................................................................................................... 3-36
Exception Vector Table ............................................................................................ 3-36
Instruction Timing ........................................................................................................ 3-37
User Instruction Set Architecture (UISA) .................................................................... 3-39
Computation Modes .................................................................................................. 3-39
Reserved Fields ......................................................................................................... 3-39
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
v
Contents
Paragraph
Number
3.13.3
3.13.4
3.13.5
3.13.6
3.13.7
3.13.7.1
3.13.7.2
3.13.8
3.13.8.1
3.13.9
3.13.9.1
3.13.9.2
3.13.10
3.13.10.1
3.13.10.2
3.13.10.3
3.13.10.4
3.13.10.5
3.13.10.6
3.13.10.7
3.13.10.8
3.14
3.14.1
3.14.2
3.14.3
3.14.4
3.14.5
3.14.6
3.15
3.15.1
3.15.1.1
3.15.1.2
3.15.2
3.15.2.1
3.15.3
3.15.4
3.15.4.1
3.15.4.2
3.15.4.3
3.15.4.4
3.15.4.5
Title
Page
Number
Classes of Instructions .............................................................................................. 3-40
Exceptions ................................................................................................................. 3-40
Branch Processor ...................................................................................................... 3-40
Instruction Fetching .................................................................................................. 3-40
Branch Instructions ................................................................................................... 3-40
Invalid Branch Instruction Forms ......................................................................... 3-40
Branch Prediction ................................................................................................. 3-40
Fixed-Point Processor ............................................................................................... 3-41
Fixed-Point Instructions ........................................................................................ 3-41
Floating-Point Processor ........................................................................................... 3-41
General .................................................................................................................. 3-41
Optional Instructions ............................................................................................ 3-41
Load/Store Processor ................................................................................................ 3-42
Fixed-Point Load with Update and Store with Update Instructions ..................... 3-42
Fixed-Point Load and Store Multiple Instructions ............................................... 3-42
Fixed-Point Load String Instructions .................................................................... 3-42
Storage Synchronization Instructions ................................................................... 3-42
Floating-Point Load and Store With Update Instructions .................................... 3-42
Floating-Point Load Single Instructions ............................................................... 3-42
Floating-Point Store Single Instructions ............................................................... 3-42
Optional Instructions ............................................................................................ 3-43
Virtual Environment Architecture (VEA) .................................................................... 3-43
Atomic Update Primitives ........................................................................................ 3-43
Effect of Operand Placement on Performance ......................................................... 3-43
Storage Control Instructions ..................................................................................... 3-43
Instruction Synchronize (isync) Instruction .............................................................. 3-43
Enforce In-Order Execution of I/O (eieio) Instruction ............................................. 3-44
Time Base ................................................................................................................. 3-44
Operating Environment Architecture (OEA) ................................................................ 3-44
Branch Processor Registers ...................................................................................... 3-44
Machine State Register (MSR) ............................................................................. 3-44
Branch Processors Instructions ............................................................................. 3-44
Fixed-Point Processor ............................................................................................... 3-44
Special Purpose Registers ..................................................................................... 3-44
Storage Control Instructions ..................................................................................... 3-45
Exceptions ................................................................................................................. 3-45
System Reset Exception and NMI (0x0100) ........................................................ 3-45
Machine Check Exception (0x0200) .................................................................... 3-46
Data Storage Exception (0x0300) ......................................................................... 3-48
Instruction Storage Exception (0x0400) ............................................................... 3-48
External Interrupt (0x0500) .................................................................................. 3-48
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
vi
Contents
Paragraph
Number
3.15.4.6
3.15.4.7
3.15.4.8
3.15.4.9
3.15.4.10
3.15.4.11
3.15.4.12
3.15.4.13
3.15.4.14
3.15.4.15
3.15.4.16
3.15.5
3.15.6
3.15.7
Title
Page
Number
Alignment Exception (0x00600) .......................................................................... 3-49
Program Exception (0x0700) ................................................................................ 3-51
Floating-Point Unavailable Exception (0x0800) .................................................. 3-52
Decrementer Exception (0x0900) ......................................................................... 3-53
System Call Exception (0x0C00) ......................................................................... 3-54
Trace Exception (0x0D00) ................................................................................... 3-54
Floating-Point Assist Exception (0x0E00) ........................................................... 3-55
Implementation-Dependent Software Emulation Exception (0x1000) ................ 3-56
Implementation-Dependent Instruction Protection Exception (0x1300) .............. 3-57
Implementation-Specific Data Protection Error Exception (0x1400) .................. 3-58
Implementation-Dependent Debug Exceptions .................................................... 3-59
Partially Executed Instructions ................................................................................. 3-60
Timer Facilities ......................................................................................................... 3-61
Optional Facilities and Instructions .......................................................................... 3-61
Chapter 4
Burst Buffer Controller 2 Module
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.1.1
4.4.1.2
4.5
Key Features ................................................................................................................... 4-2
BIU Key Features ....................................................................................................... 4-2
IMPU Key Features .................................................................................................... 4-3
ICDU Key Features .................................................................................................... 4-3
DECRAM Key Features ............................................................................................. 4-4
Branch Target Buffer Key Features ............................................................................ 4-4
Operation Modes ............................................................................................................. 4-4
Instruction Fetch ......................................................................................................... 4-4
Decompression Off Mode ....................................................................................... 4-4
Decompression On Mode ....................................................................................... 4-5
Burst Operation of the BBC ........................................................................................ 4-5
Access Violation Detection ........................................................................................ 4-5
Slave Operation ........................................................................................................... 4-6
Reset Behavior ............................................................................................................ 4-6
Debug Operation Mode .............................................................................................. 4-7
Exception Table Relocation (ETR) ................................................................................. 4-7
ETR Operation ............................................................................................................ 4-8
Enhanced External Interrupt Relocation (EEIR) ...................................................... 4-10
Decompressor RAM (DECRAM) Functionality .......................................................... 4-12
General-Purpose Memory Operation ........................................................................ 4-13
Memory Protection Violations ............................................................................. 4-14
DECRAM Standby Operation Mode .................................................................... 4-14
Branch Target Buffer .................................................................................................... 4-14
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
vii
Contents
Paragraph
Number
4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.6
4.6.1
4.6.1.1
4.6.1.2
4.6.2
4.6.2.1
4.6.2.2
4.6.2.3
4.6.2.4
4.6.2.5
4.6.3
Title
Page
Number
BTB Operation .......................................................................................................... 4-14
BTB Invalidation .................................................................................................. 4-16
BTB Enabling/Disabling ...................................................................................... 4-16
BTB Inhibit Regions ............................................................................................. 4-16
BBC Programming Model ............................................................................................ 4-17
Address Map ............................................................................................................. 4-17
BBC Special Purpose Registers (SPRs) ............................................................... 4-17
DECRAM and DCCR Block ................................................................................ 4-18
BBC Register Descriptions ....................................................................................... 4-19
BBC Module Configuration Register (BBCMCR) ............................................... 4-19
Region Base Address Registers (MI_RBA[0:3]) ................................................. 4-21
Region Attribute Registers (MI_RA[0:3]) ............................................................ 4-22
Global Region Attribute Register (MI_GRA) ...................................................... 4-23
External Interrupt Relocation Table Base Address Register (EIBADR) .............. 4-25
Decompressor Class Configuration Registers .......................................................... 4-25
Chapter 5
Unified System Interface Unit (USIU) Overview
5.1
5.1.1
Memory Map and Registers ............................................................................................ 5-2
USIU Special-Purpose Registers ................................................................................ 5-6
Chapter 6
System Configuration and Protection
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.2
6.1.2.1
6.1.2.2
6.1.3
6.1.4
6.1.4.1
6.1.4.2
6.1.4.3
6.1.4.4
6.1.4.4.1
6.1.4.4.2
System Configuration and Protection Features .............................................................. 6-3
System Configuration ................................................................................................. 6-3
USIU Pin Multiplexing ........................................................................................... 6-4
Arbitration Support ................................................................................................. 6-4
External Master Modes ............................................................................................... 6-4
Operation in External Master Modes ...................................................................... 6-5
Address Decoding for External Accesses ............................................................... 6-6
USIU General-Purpose I/O ......................................................................................... 6-6
Enhanced Interrupt Controller .................................................................................... 6-8
Key Features ........................................................................................................... 6-8
Interrupt Configuration ........................................................................................... 6-8
Regular Interrupt Controller Operation (MPC555/MPC556-Compatible Mode) 6-10
Enhanced Interrupt Controller Operation ............................................................. 6-11
Lower Priority Request Masking ...................................................................... 6-14
Backward Compatibility with MPC555/MPC556 ............................................ 6-14
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
viii
Contents
Paragraph
Number
6.1.4.5
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.2
6.2.1
6.2.2
6.2.2.1
6.2.2.1.1
6.2.2.1.2
6.2.2.1.3
6.2.2.2
6.2.2.2.1
6.2.2.2.2
6.2.2.2.3
6.2.2.2.4
6.2.2.2.5
6.2.2.2.6
6.2.2.2.7
6.2.2.2.8
6.2.2.2.9
6.2.2.3
6.2.2.3.1
6.2.2.3.2
6.2.2.3.3
6.2.2.4
6.2.2.4.1
6.2.2.4.2
6.2.2.4.3
6.2.2.4.4
6.2.2.4.5
6.2.2.4.6
6.2.2.4.7
6.2.2.4.8
6.2.2.4.9
6.2.2.4.10
Title
Page
Number
Interrupt Overhead Estimation for Enhanced Interrupt Controller Mode ............ 6-16
Hardware Bus Monitor ............................................................................................. 6-17
Decrementer (DEC) .................................................................................................. 6-18
Time Base (TB) ........................................................................................................ 6-19
Real-Time Clock (RTC) ........................................................................................... 6-19
Periodic Interrupt Timer (PIT) .................................................................................. 6-20
Software Watchdog Timer (SWT) ............................................................................ 6-21
Freeze Operation ....................................................................................................... 6-23
Low Power Stop Operation ....................................................................................... 6-23
Memory Map and Register Definitions ........................................................................ 6-23
Memory Map ............................................................................................................ 6-23
System Configuration and Protection Registers ....................................................... 6-24
System Configuration Registers ........................................................................... 6-24
SIU Module Configuration Register (SIUMCR) .............................................. 6-25
Internal Memory Map Register (IMMR) .......................................................... 6-28
External Master Control Register (EMCR) ...................................................... 6-29
SIU Interrupt Controller Registers ........................................................................ 6-31
SIU Interrupt Pending Register (SIPEND) ....................................................... 6-32
SIU Interrupt Pending Register 2 (SIPEND2) .................................................. 6-32
SIU Interrupt Pending Register 3 (SIPEND3) .................................................. 6-33
SIU Interrupt Mask Register (SIMASK) .......................................................... 6-33
SIU Interrupt Mask Register 2 (SIMASK2) .................................................... 6-34
SIU Interrupt Mask Register 3 (SIMASK3) ..................................................... 6-35
SIU Interrupt Edge Level Register (SIEL) ....................................................... 6-35
SIU Interrupt Vector Register (SIVEC) ........................................................... 6-35
Interrupt In-Service Registers (SISR2 and SISR3) .......................................... 6-37
System Protection Registers ................................................................................. 6-37
System Protection Control Register (SYPCR) ................................................. 6-37
Software Service Register (SWSR) .................................................................. 6-38
Transfer Error Status Register (TESR) ............................................................. 6-39
System Timer Registers ........................................................................................ 6-40
Decrementer Register (DEC) ............................................................................ 6-40
Time Base SPRs (TB) ....................................................................................... 6-40
Time Base Reference Registers (TBREF0 and TBREF1) ................................ 6-41
Time Base Control and Status Register (TBSCR) ............................................ 6-42
Real-Time Clock Status and Control Register (RTCSC) ................................. 6-42
Real-Time Clock Register (RTC) ..................................................................... 6-43
Real-Time Clock Alarm Register (RTCAL) .................................................... 6-44
Periodic Interrupt Status and Control Register (PISCR) .................................. 6-44
Periodic Interrupt Timer Count Register (PITC) .............................................. 6-45
Periodic Interrupt Timer Register (PITR) ........................................................ 6-45
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
ix
Contents
Paragraph
Number
6.2.2.5
6.2.2.5.1
6.2.2.5.2
6.2.2.5.3
Title
Page
Number
General-Purpose I/O Registers ............................................................................. 6-46
SGPIO Data Register 1 (SGPIODT1) ............................................................. 6-46
SGPIO Data Register 2 (SGPIODT2) ............................................................. 6-47
SGPIO Control Register (SGPIOCR) .............................................................. 6-48
Chapter 7
Reset
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.5.3
Reset Operation ............................................................................................................... 7-1
Power-On Reset .......................................................................................................... 7-1
Hard Reset ................................................................................................................... 7-2
Soft Reset .................................................................................................................... 7-2
Loss of PLL Lock ....................................................................................................... 7-2
On-Chip Clock Switch ................................................................................................ 7-3
Software Watchdog Reset ........................................................................................... 7-3
Checkstop Reset .......................................................................................................... 7-3
Debug Port Hard Reset ............................................................................................... 7-3
Debug Port Soft Reset ................................................................................................. 7-3
JTAG Reset ................................................................................................................. 7-3
ILBC Illegal Bit Change ............................................................................................. 7-3
Reset Actions Summary .................................................................................................. 7-3
Data Coherency During Reset ........................................................................................ 7-4
Reset Status Register (RSR) ........................................................................................... 7-5
Reset Configuration ........................................................................................................ 7-7
Hard Reset Configuration ........................................................................................... 7-7
Hard Reset Configuration Word (RCW) .................................................................. 7-11
Soft Reset Configuration .......................................................................................... 7-13
Chapter 8
Clocks and Power Control
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.4
System Clock Sources .................................................................................................... 8-3
System PLL ..................................................................................................................... 8-3
Frequency Multiplication ............................................................................................ 8-4
Skew Elimination ........................................................................................................ 8-4
Pre-Divider .................................................................................................................. 8-4
PLL Block Diagram .................................................................................................... 8-4
PLL Pins ..................................................................................................................... 8-5
System Clock During PLL Loss of Lock ........................................................................ 8-6
Low-Power Divider ........................................................................................................ 8-6
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
x
Contents
Paragraph
Number
8.5
8.5.1
8.5.2
8.5.3
8.6
8.7
8.7.1
8.7.2
8.7.3
8.7.3.1
8.7.3.2
8.7.3.3
8.7.3.4
8.7.3.5
8.8
8.8.1
8.8.2
8.8.2.1
8.8.2.2
8.8.2.3
8.8.2.4
8.8.2.5
8.8.2.6
8.8.2.7
8.8.2.8
8.8.2.9
8.8.2.10
8.8.2.11
8.8.3
8.8.3.1
8.8.3.2
8.9
8.10
8.11
8.11.1
8.11.2
8.11.3
8.11.4
Title
Page
Number
Internal Clock Signals ..................................................................................................... 8-7
General System Clocks ............................................................................................. 8-10
Clock Out (CLKOUT) .............................................................................................. 8-13
Engineering Clock (ENGCLK) ................................................................................ 8-14
Clock Source Switching ................................................................................................ 8-14
Low-Power Modes ........................................................................................................ 8-16
Entering a Low-Power Mode .................................................................................... 8-16
Power Mode Descriptions ......................................................................................... 8-17
Exiting from Low-Power Modes .............................................................................. 8-17
Exiting from Normal-Low Mode .......................................................................... 8-18
Exiting from Doze Mode ...................................................................................... 8-19
Exiting from Deep-Sleep Mode ............................................................................ 8-19
Exiting from Power-Down Mode ......................................................................... 8-19
Low-Power Modes Flow ...................................................................................... 8-19
Basic Power Structure ................................................................................................... 8-21
General Power Supply Definitions ........................................................................... 8-21
Chip Power Structure ................................................................................................ 8-22
NVDDL ................................................................................................................ 8-22
QVDDL ................................................................................................................ 8-22
VDD ...................................................................................................................... 8-22
VDDSYN, VSSSYN ............................................................................................ 8-22
KAPWR ................................................................................................................ 8-22
VDDA, VSSA ....................................................................................................... 8-22
VFLASH ............................................................................................................... 8-22
VDDF, VSSF ........................................................................................................ 8-22
VDDH ................................................................................................................... 8-23
IRAMSTBY .......................................................................................................... 8-23
VSS ....................................................................................................................... 8-23
Keep-Alive Power ..................................................................................................... 8-24
Keep-Alive Power Configuration ......................................................................... 8-24
Keep-Alive Power Registers Lock Mechanism .................................................... 8-25
IRAMSTBY Supply Failure Detection ......................................................................... 8-27
Power-Up/Down Sequencing ....................................................................................... 8-27
Clocks Unit Programming Model ................................................................................. 8-29
System Clock Control Register (SCCR) ................................................................... 8-29
PLL, Low-Power, and Reset-Control Register (PLPRCR) ...................................... 8-33
Change of Lock Interrupt Register (COLIR) ............................................................ 8-36
IRAMSTBY Control Register (VSRMCR) .............................................................. 8-37
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xi
Contents
Paragraph
Number
Title
Page
Number
Chapter 9
External Bus Interface
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
9.5.3
9.5.3.1
9.5.3.2
9.5.4
9.5.5
9.5.6
9.5.7
9.5.7.1
9.5.7.2
9.5.7.3
9.5.7.4
9.5.8
9.5.8.1
9.5.8.2
9.5.8.3
9.5.8.4
9.5.8.5
9.5.8.6
9.5.8.7
9.5.9
9.5.9.1
9.5.9.2
9.5.9.3
9.5.9.4
9.5.10
9.5.11
9.5.11.1
9.5.11.2
Features ........................................................................................................................... 9-1
Bus Transfer Signals ....................................................................................................... 9-1
Bus Control Signals ........................................................................................................ 9-2
Bus Interface Signal Descriptions ................................................................................... 9-3
Bus Operations ................................................................................................................ 9-8
Basic Transfer Protocol .............................................................................................. 9-8
Single Beat Transfer ................................................................................................... 9-9
Single Beat Read Flow ........................................................................................... 9-9
Single Beat Write Flow ........................................................................................ 9-11
Single Beat Flow with Small Port Size ................................................................. 9-14
Data Bus Pre-Discharge Mode ................................................................................. 9-15
Operating Conditions ............................................................................................ 9-16
Initialization Sequence .......................................................................................... 9-16
Burst Transfer ........................................................................................................... 9-17
Burst Mechanism ...................................................................................................... 9-18
Alignment and Packaging of Transfers .................................................................... 9-29
Arbitration Phase ...................................................................................................... 9-32
Bus Request .......................................................................................................... 9-33
Bus Grant .............................................................................................................. 9-33
Bus Busy ............................................................................................................... 9-34
Internal Bus Arbiter .............................................................................................. 9-35
Address Transfer Phase Signals ................................................................................ 9-37
Transfer Start ........................................................................................................ 9-37
Address Bus .......................................................................................................... 9-37
Read/Write ............................................................................................................ 9-37
Burst Indicator ...................................................................................................... 9-37
Transfer Size ......................................................................................................... 9-38
Address Types ...................................................................................................... 9-38
Burst Data in Progress .......................................................................................... 9-40
Termination Signals .................................................................................................. 9-40
Transfer Acknowledge .......................................................................................... 9-40
Burst Inhibit .......................................................................................................... 9-40
Transfer Error Acknowledge ................................................................................ 9-40
Termination Signals Protocol ............................................................................... 9-40
Storage Reservation .................................................................................................. 9-42
Bus Exception Control Cycles .................................................................................. 9-45
Retrying a Bus Cycle ............................................................................................ 9-45
Termination Signals Protocol Summary ............................................................... 9-49
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xii
Contents
Paragraph
Number
9.5.12
9.5.13
9.5.14
Title
Page
Number
Bus Operation in External Master Modes ................................................................. 9-49
Contention Resolution on External Bus .................................................................... 9-53
Show Cycle Transactions .......................................................................................... 9-55
Chapter 10
Memory Controller
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.6.1
10.2.6.2
10.2.6.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.4
10.5
10.6
10.7
10.8
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
Overview ....................................................................................................................... 10-1
Memory Controller Architecture .................................................................................. 10-3
Associated Registers ................................................................................................. 10-4
Port Size Configuration ............................................................................................ 10-4
Write-Protect Configuration ..................................................................................... 10-5
Address and Address Space Checking ...................................................................... 10-5
Burst Support ............................................................................................................ 10-5
Reduced Data Setup Time ........................................................................................ 10-6
Case 1: Normal Setup Time .................................................................................. 10-6
Case 2: Short Setup Time ..................................................................................... 10-7
Summary of Short Setup Time ............................................................................. 10-8
Chip-Select Timing ..................................................................................................... 10-10
Memory Devices Interface Example ...................................................................... 10-12
Peripheral Devices Interface Example .................................................................... 10-13
Relaxed Timing Examples ...................................................................................... 10-14
Extended Hold Time on Read Accesses ................................................................. 10-18
Summary of GPCM Timing Options ...................................................................... 10-22
Write and Byte Enable Signals ................................................................................... 10-24
Dual Mapping of the Internal Flash EEPROM Array ................................................ 10-24
Dual Mapping of an External Flash Region ............................................................... 10-26
Global (Boot) Chip-Select Operation ......................................................................... 10-27
Memory Controller External Master Support ............................................................. 10-28
Programming Model ................................................................................................... 10-31
General Memory Controller Programming Notes .................................................. 10-31
Memory Controller Status Registers (MSTAT) ..................................................... 10-32
Memory Controller Base Registers (BR0–BR3) .................................................... 10-32
Memory Controller Option Registers (OR0–OR3) ................................................ 10-34
Dual-Mapping Base Register (DMBR) .................................................................. 10-36
Dual-Mapping Option Register (DMOR) ............................................................... 10-37
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xiii
Contents
Paragraph
Number
Title
Page
Number
Chapter 11
L-Bus to U-Bus Interface (L2U)
11.1
11.2
11.3
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.6
11.6.1
11.6.2
11.6.3
11.7
11.7.1
11.7.2
11.7.3
11.7.4
11.7.5
11.7.6
11.8
11.8.1
11.8.2
11.8.3
11.8.4
11.8.5
11.8.6
General Features ........................................................................................................... 11-1
Data Memory Protection Unit Features ........................................................................ 11-1
L2U Block Diagram ...................................................................................................... 11-2
Modes Of Operation ..................................................................................................... 11-3
Normal Mode ............................................................................................................ 11-3
Reset Operation ......................................................................................................... 11-4
Peripheral Mode ........................................................................................................ 11-4
Factory Test Mode .................................................................................................... 11-4
Data Memory Protection ............................................................................................... 11-4
Functional Description .............................................................................................. 11-5
Associated Registers ................................................................................................. 11-6
L-Bus Memory Access Violations ............................................................................ 11-7
Reservation Support ...................................................................................................... 11-7
Reservation Protocol ................................................................................................. 11-8
L2U Reservation Support ......................................................................................... 11-8
Reserved Location (Bus) and Possible Actions ........................................................ 11-9
L-Bus Show Cycle Support .......................................................................................... 11-9
Programming Show Cycles .................................................................................... 11-10
Performance Impact ................................................................................................ 11-10
Show Cycle Protocol .............................................................................................. 11-10
L-Bus Write Show Cycle Flow ............................................................................... 11-10
L-Bus Read Show Cycle Flow ................................................................................ 11-11
Show Cycle Support Guidelines ............................................................................. 11-11
L2U Programming Model ........................................................................................... 11-12
U-Bus Access .......................................................................................................... 11-13
Transaction Size ...................................................................................................... 11-13
L2U Module Configuration Register (L2U_MCR) ................................................ 11-13
Region Base Address Registers (L2U_RBAx) ....................................................... 11-14
Region Attribute Registers (L2U_RAx) ................................................................. 11-15
Global Region Attribute Register (L2U_GRA) ...................................................... 11-16
Chapter 12
U-Bus to IMB3 Bus Interface (UIMB)
12.1
12.2
12.3
12.4
Features ......................................................................................................................... 12-1
UIMB Block Diagram .................................................................................................. 12-2
Clock Module ............................................................................................................... 12-2
Interrupt Operation ....................................................................................................... 12-3
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xiv
Contents
Paragraph
Number
12.4.1
12.4.2
12.4.3
12.4.4
12.5
12.5.1
12.5.2
12.5.3
Title
Page
Number
Interrupt Sources and Levels on IMB3 ..................................................................... 12-3
IMB3 Interrupt Multiplexing .................................................................................... 12-4
ILBS Sequencing ...................................................................................................... 12-4
Interrupt Synchronizer .............................................................................................. 12-5
Programming Model ..................................................................................................... 12-6
UIMB Module Configuration Register (UMCR) ..................................................... 12-7
Test Control Register (UTSTCREG) ........................................................................ 12-8
Pending Interrupt Request Register (UIPEND) ........................................................ 12-8
Chapter 13
QADC64E Legacy Mode Operation
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.3
13.3.1.4
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10
13.4
13.4.1
13.4.1.1
13.4.1.2
13.4.2
13.4.3
13.4.4
QADC64E Block Diagram ........................................................................................... 13-1
Key Features and Quick Reference Diagrams .............................................................. 13-2
Features of the QADC64E Legacy Mode Operation ................................................ 13-2
Memory Map ............................................................................................................ 13-3
Legacy and Enhanced Modes of Operation .............................................................. 13-4
Using the Queue and Result Word Table ................................................................. 13-5
External Multiplexing ............................................................................................... 13-5
Programming the QADC64E Registers ........................................................................ 13-7
QADC64E Module Configuration Register (QADMCR) ........................................ 13-8
Low Power Stop Mode ......................................................................................... 13-9
Freeze Mode ......................................................................................................... 13-9
Switching Between Legacy and Enhanced Modes of Operation ........................ 13-10
Supervisor/Unrestricted Address Space ............................................................. 13-10
QADC64E Interrupt Register (QADCINT) ............................................................ 13-12
Port Data Register (PORTQA and PORTQB) ........................................................ 13-13
Port Data Direction Register (DDRQA) ................................................................. 13-14
Control Register 0 (QACR0) .................................................................................. 13-14
Control Register 1 (QACR1) .................................................................................. 13-15
Control Register 2 (QACR2) .................................................................................. 13-17
Status Registers (QASR0 and QASR1) .................................................................. 13-20
Conversion Command Word Table ........................................................................ 13-27
Result Word Table .................................................................................................. 13-32
Analog Subsystem ...................................................................................................... 13-34
Analog-to-Digital Converter Operation .................................................................. 13-34
Conversion Cycle Times ..................................................................................... 13-35
Amplifier Bypass Mode Conversion Timing ..................................................... 13-35
Channel Decode and Multiplexer ........................................................................... 13-36
Sample Buffer Amplifier ........................................................................................ 13-36
Digital-to-Analog Converter (DAC) Array ............................................................ 13-36
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xv
Contents
Paragraph
Number
13.4.5
13.4.6
13.4.7
13.4.8
13.5
13.5.1
13.5.2
13.5.3
13.5.4
13.5.4.1
13.5.4.2
13.5.4.3
13.5.4.3.1
13.5.4.3.2
13.5.4.3.3
13.5.4.3.4
13.5.4.4
13.5.4.4.1
13.5.4.4.2
13.5.4.4.3
13.5.4.4.4
13.5.5
13.5.6
13.5.7
13.5.7.1
13.5.7.2
13.6
13.6.1
13.6.2
13.7
13.7.1
13.7.2
13.7.3
13.7.3.1
13.7.4
13.7.5
13.7.5.1
13.7.5.2
13.7.5.3
13.7.5.4
Title
Page
Number
Comparator ............................................................................................................. 13-37
Bias ......................................................................................................................... 13-37
Successive Approximation Register ...................................................................... 13-37
State Machine ......................................................................................................... 13-37
Digital Subsystem ....................................................................................................... 13-37
Queue Priority ......................................................................................................... 13-38
Paused Sub-Queues ................................................................................................. 13-38
Boundary Conditions .............................................................................................. 13-40
Scan Modes ............................................................................................................. 13-41
Disabled Mode .................................................................................................... 13-41
Reserved Mode ................................................................................................... 13-41
Single-Scan Modes ............................................................................................. 13-42
Software Initiated Single-Scan Mode ............................................................. 13-42
External Trigger Single-Scan Mode ............................................................... 13-43
External Gated Single-Scan Mode ................................................................. 13-43
Periodic/Interval Timer Single-Scan Mode .................................................... 13-44
Continuous-Scan Modes ..................................................................................... 13-44
Software Initiated Continuous-Scan Mode ..................................................... 13-45
External Trigger Continuous-Scan Mode ....................................................... 13-46
External Gated Continuous-Scan Mode ......................................................... 13-46
Periodic/Interval Timer Continuous-Scan Mode ............................................ 13-47
QADC64E Clock (QCLK) Generation ................................................................... 13-47
Periodic / Interval Timer ......................................................................................... 13-51
Configuration and Control Using the IMB3 Interface ............................................ 13-51
QADC64E Bus Interface Unit ............................................................................ 13-51
QADC64E Bus Accessing .................................................................................. 13-52
Trigger and Queue Interaction Examples ................................................................... 13-54
Queue Priority Schemes .......................................................................................... 13-54
Conversion Timing Schemes .................................................................................. 13-63
QADC64E Integration Requirements ......................................................................... 13-66
Port Digital Input/Output Signals ........................................................................... 13-66
External Trigger Input Signals ................................................................................ 13-67
Analog Power Signals ............................................................................................. 13-67
Analog Supply Filtering and Grounding ............................................................ 13-69
Analog Reference Signals ....................................................................................... 13-71
Analog Input Signals .............................................................................................. 13-71
Analog Input Considerations .............................................................................. 13-73
Settling Time for the External Circuit ................................................................ 13-75
Error Resulting from Leakage ............................................................................ 13-75
Accommodating Positive/Negative Stress Conditions ....................................... 13-76
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xvi
Contents
Paragraph
Number
Title
Page
Number
Chapter 14
QADC64E Enhanced Mode Operation
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.3
14.3.1
14.3.1.1
14.3.1.2
14.3.1.3
14.3.1.4
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
14.3.9
14.3.10
14.3.10.1
14.3.11
14.3.11.1
14.3.12
14.3.13
14.3.14
14.3.15
14.3.16
14.3.17
14.3.18
14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.4.1
QADC64E Block Diagram ........................................................................................... 14-1
Key Features and Quick Reference Diagrams .............................................................. 14-2
Features of the QADC64E Enhanced Mode Operation ............................................ 14-2
Memory Map ............................................................................................................ 14-3
Legacy and Enhanced Modes of Operation .............................................................. 14-4
Using the Queue and Result Word Table ................................................................. 14-5
External Multiplexing ............................................................................................... 14-5
Programming the QADC64E Registers ........................................................................ 14-7
QADC64E Module Configuration Register ........................................................... 14-8
Low Power Stop Mode ......................................................................................... 14-8
Freeze Mode ......................................................................................................... 14-9
Switching Between Legacy and Enhanced Modes of Operation .......................... 14-9
Supervisor/Unrestricted Address Space ............................................................. 14-10
QADC64E Interrupt Register ................................................................................. 14-11
Port Data Register ................................................................................................... 14-12
Port Data Direction Register ................................................................................... 14-13
Control Register 0 ................................................................................................... 14-14
Control Register 1 ................................................................................................... 14-16
Control Register 2 ................................................................................................... 14-18
Status Registers (QASR0 and QASR1) .................................................................. 14-22
Conversion Command Word Table ........................................................................ 14-28
Result Word Table .................................................................................................. 14-34
Analog Subsystem .............................................................................................. 14-36
Analog-to-Digital Converter Operation .................................................................. 14-36
Conversion Cycle Times ..................................................................................... 14-36
Channel Decode and Multiplexer ........................................................................... 14-37
Sample Buffer Amplifier ........................................................................................ 14-37
Digital to Analog Converter (DAC) Array ............................................................. 14-37
Comparator ............................................................................................................. 14-38
Bias ......................................................................................................................... 14-38
Successive Approximation Register ...................................................................... 14-38
State Machine ......................................................................................................... 14-38
Digital Subsystem ....................................................................................................... 14-38
Queue Priority ......................................................................................................... 14-39
Sub-Queues That are Paused .................................................................................. 14-39
Boundary Conditions .............................................................................................. 14-41
Scan Modes ............................................................................................................. 14-42
Disabled Mode .................................................................................................... 14-42
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xvii
Contents
Paragraph
Number
14.4.4.2
14.4.4.3
14.4.4.3.1
14.4.4.3.2
14.4.4.3.3
14.4.4.3.4
14.4.4.4
14.4.4.4.1
14.4.4.4.2
14.4.4.4.3
14.4.4.4.4
14.4.5
14.4.6
14.4.7
14.4.7.1
14.4.7.2
14.5
14.5.1
14.5.2
14.6
14.6.1
14.6.2
14.6.3
14.6.3.1
14.6.4
14.6.5
14.6.5.1
14.6.5.2
14.6.5.3
14.6.5.4
Title
Page
Number
Reserved Mode ................................................................................................... 14-42
Single-Scan Modes ............................................................................................. 14-43
Software Initiated Single-Scan Mode ............................................................. 14-43
External Trigger Single-Scan Mode ............................................................... 14-44
External Gated Single-Scan Mode ................................................................. 14-44
Periodic/Interval Timer Single-Scan Mode .................................................... 14-45
Continuous-Scan Modes ..................................................................................... 14-45
Software Initiated Continuous-Scan Mode ..................................................... 14-46
External Trigger Continuous-Scan Mode ....................................................... 14-47
External Gated Continuous-Scan Mode ......................................................... 14-47
Periodic/Interval Timer Continuous-Scan Mode ............................................ 14-48
QADC64E Clock (QCLK) Generation ................................................................... 14-48
Periodic/Interval Timer ........................................................................................... 14-50
Configuration and Control Using the IMB3 Interface ............................................ 14-51
QADC64E Bus Interface Unit ............................................................................ 14-51
QADC64E Bus Accessing .................................................................................. 14-51
Trigger and Queue Interaction Examples ................................................................... 14-53
Queue Priority Schemes .......................................................................................... 14-53
Conversion Timing Schemes .................................................................................. 14-62
QADC64E Integration Requirements ......................................................................... 14-65
Port Digital Input/Output Signals ........................................................................... 14-65
External Trigger Input Signals ................................................................................ 14-66
Analog Power Signals ............................................................................................. 14-66
Analog Supply Filtering and Grounding ............................................................ 14-67
Analog Reference Signals ....................................................................................... 14-69
Analog Input Signals .............................................................................................. 14-70
Analog Input Considerations .............................................................................. 14-71
Settling Time for the External Circuit ................................................................ 14-73
Error Resulting from Leakage ............................................................................ 14-73
Accommodating Positive/Negative Stress Conditions ....................................... 14-74
Chapter 15
Queued Serial Multi-Channel Module
15.1
15.2
15.2.1
15.3
15.4
15.4.1
15.4.2
Block Diagram .............................................................................................................. 15-1
Key Features ................................................................................................................. 15-2
MPC561/MPC563 QSMCM Details ........................................................................ 15-3
Memory Maps ............................................................................................................... 15-4
QSMCM Global Registers ............................................................................................ 15-6
Low-Power Stop Operation ...................................................................................... 15-6
Freeze Operation ....................................................................................................... 15-6
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xviii
Contents
Paragraph
Number
15.4.3
15.4.4
15.4.5
15.4.6
15.4.7
15.4.8
15.5
15.5.1
15.5.2
15.5.3
15.6
15.6.1
15.6.1.1
15.6.1.2
15.6.1.3
15.6.1.4
15.6.1.5
15.6.2
15.6.2.1
15.6.2.2
15.6.2.3
15.6.3
15.6.4
15.6.4.1
15.6.4.2
15.6.4.3
15.6.5
15.6.5.1
15.6.5.2
15.6.5.3
15.6.5.4
15.6.5.5
15.6.5.6
15.6.5.7
15.6.5.8
15.6.6
15.6.6.1
15.6.7
15.6.8
15.7
15.7.1
Title
Page
Number
Access Protection ...................................................................................................... 15-6
QSMCM Interrupts ................................................................................................... 15-7
QSPI Interrupt Generation ........................................................................................ 15-8
QSMCM Configuration Register (QSMCMMCR) .................................................. 15-8
QSMCM Test Register (QTEST) ............................................................................. 15-9
QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL) ..................................... 15-9
QSMCM Pin Control Registers .................................................................................. 15-10
Port QS Data Register (PORTQS) .......................................................................... 15-11
PORTQS Pin Assignment Register (PQSPAR) ..................................................... 15-12
PORTQS Data Direction Register (DDRQS) ......................................................... 15-13
Queued Serial Peripheral Interface ............................................................................. 15-14
QSPI Registers ....................................................................................................... 15-16
QSPI Control Register 0 (SPCR0) ...................................................................... 15-17
QSPI Control Register 1 (SPCR1) ...................................................................... 15-19
QSPI Control Register 2 (SPCR2) ...................................................................... 15-20
QSPI Control Register 3 (SPCR3) ...................................................................... 15-20
QSPI Status Register (SPSR) .............................................................................. 15-21
QSPI RAM .............................................................................................................. 15-22
Receive RAM ..................................................................................................... 15-23
Transmit RAM .................................................................................................... 15-23
Command RAM .................................................................................................. 15-23
QSPI Pins ................................................................................................................ 15-24
QSPI Operation ....................................................................................................... 15-25
Enabling, Disabling, and Halting the SPI ........................................................... 15-26
QSPI Interrupts ................................................................................................... 15-26
QSPI Flow .......................................................................................................... 15-27
Master Mode Operation .......................................................................................... 15-34
Clock Phase and Polarity .................................................................................... 15-35
Baud Rate Selection ............................................................................................ 15-35
Delay Before Transfer ........................................................................................ 15-36
Delay After Transfer ........................................................................................... 15-36
Transfer Length .................................................................................................. 15-37
Peripheral Chip Selects ....................................................................................... 15-37
Optional Enhanced Peripheral Chip Selects ....................................................... 15-37
Master Wraparound Mode .................................................................................. 15-38
Slave Mode ............................................................................................................. 15-39
Description of Slave Operation .......................................................................... 15-40
Slave Wraparound Mode ........................................................................................ 15-41
Mode Fault .............................................................................................................. 15-42
Serial Communication Interface ................................................................................. 15-42
SCI Registers .......................................................................................................... 15-45
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xix
Contents
Paragraph
Number
15.7.2
15.7.3
15.7.4
15.7.5
15.7.6
15.7.7
15.7.7.1
15.7.7.2
15.7.7.3
15.7.7.4
15.7.7.5
15.7.7.6
15.7.7.7
15.7.7.8
15.7.7.9
15.7.7.10
15.7.7.11
15.8
15.8.1
15.8.2
15.8.2.1
15.8.2.2
15.8.3
15.8.4
15.8.5
15.8.6
15.8.7
15.8.8
15.8.9
15.8.10
15.8.11
15.8.12
Title
Page
Number
SCI Control Register 0 (SCCxR0) .......................................................................... 15-46
SCI Control Register 1 (SCCxR1) .......................................................................... 15-47
SCI Status Register (SCxSR) .................................................................................. 15-48
SCI Data Register (SCxDR) ................................................................................... 15-50
SCI Pins .................................................................................................................. 15-51
SCI Operation ......................................................................................................... 15-51
Definition of Terms ............................................................................................ 15-51
Serial Formats ..................................................................................................... 15-52
Baud Clock ......................................................................................................... 15-52
Parity Checking .................................................................................................. 15-53
Transmitter Operation ......................................................................................... 15-54
Receiver Operation ............................................................................................. 15-55
Receiver Bit Processor ........................................................................................ 15-55
Receiver Functional Operation ........................................................................... 15-57
Idle-Line Detection ............................................................................................. 15-58
Receiver Wake-Up .............................................................................................. 15-58
Internal Loop Mode ............................................................................................ 15-59
SCI Queue Operation .................................................................................................. 15-59
Queue Operation of SCI1 for Transmit and Receive .............................................. 15-59
Queued SCI1 Status and Control Registers ............................................................ 15-59
QSCI1 Control Register (QSCI1CR) .................................................................. 15-60
QSCI1 Status Register (QSCI1SR) .................................................................... 15-61
QSCI1 Transmitter Block Diagram ........................................................................ 15-62
QSCI1 Additional Transmit Operation Features .................................................... 15-63
QSCI1 Transmit Flow Chart Implementing the Queue .......................................... 15-65
Example QSCI1 Transmit for 17 Data Bytes ......................................................... 15-67
Example SCI Transmit for 25 Data Bytes .............................................................. 15-68
QSCI1 Receiver Block Diagram ............................................................................. 15-70
QSCI1 Additional Receive Operation Features ...................................................... 15-70
QSCI1 Receive Flow Chart Implementing the Queue ............................................ 15-73
QSCI1 Receive Queue Software Flow Chart ......................................................... 15-74
Example QSCI1 Receive Operation of 17 Data Frames ......................................... 15-75
Chapter 16
CAN 2.0B Controller Module
16.1
16.2
16.2.1
16.3
16.3.1
Features ......................................................................................................................... 16-1
External Signals ............................................................................................................ 16-2
TouCAN Signal Sharing ........................................................................................... 16-3
TouCAN Architecture ................................................................................................... 16-3
Tx/Rx Message Buffer Structure .............................................................................. 16-4
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xx
Contents
Paragraph
Number
16.3.1.1
16.3.1.2
16.3.1.3
16.3.1.4
16.3.1.5
16.3.1.6
16.3.2
16.3.3
16.3.3.1
16.3.4
16.3.5
16.4
16.4.1
16.4.2
16.4.3
16.4.3.1
16.4.3.2
16.4.4
16.4.4.1
16.4.4.2
16.4.5
16.4.6
16.5
16.5.1
16.5.2
16.5.3
16.6
16.7
16.7.1
16.7.2
16.7.3
16.7.4
16.7.5
16.7.6
16.7.7
16.7.8
16.7.9
16.7.10
16.7.11
16.7.12
16.7.13
Title
Page
Number
Common Fields for Extended and Standard Format Frames ................................ 16-4
Fields for Extended Format Frames ..................................................................... 16-6
Fields for Standard Format Frames ...................................................................... 16-6
Serial Message Buffers ......................................................................................... 16-6
Message Buffer Activation/Deactivation Mechanism .......................................... 16-7
Message Buffer Lock/Release/Busy Mechanism ................................................. 16-7
Receive Mask Registers ............................................................................................ 16-7
Bit Timing ................................................................................................................. 16-8
Configuring the TouCAN Bit Timing ................................................................ 16-10
Error Counters ......................................................................................................... 16-10
Time Stamp ............................................................................................................. 16-12
TouCAN Operation ..................................................................................................... 16-12
TouCAN Reset ........................................................................................................ 16-12
TouCAN Initialization ............................................................................................ 16-13
Transmit Process ..................................................................................................... 16-13
Transmit Message Buffer Deactivation .............................................................. 16-14
Reception of Transmitted Frames ....................................................................... 16-14
Receive Process ...................................................................................................... 16-14
Receive Message Buffer Deactivation ................................................................ 16-16
Locking and Releasing Message Buffers ........................................................... 16-16
Remote Frames ....................................................................................................... 16-17
Overload Frames ..................................................................................................... 16-17
Special Operating Modes ............................................................................................ 16-17
Debug Mode ........................................................................................................... 16-17
Low-Power Stop Mode ........................................................................................... 16-18
Auto Power Save Mode .......................................................................................... 16-19
Interrupts ..................................................................................................................... 16-20
Programming Model ................................................................................................... 16-21
TouCAN Module Configuration Register (CANMCR) ......................................... 16-25
TouCAN Test Configuration Register .................................................................... 16-27
TouCAN Interrupt Configuration Register (CANICR) .......................................... 16-27
Control Register 0 (CANCTRL0) ........................................................................... 16-27
Control Register 1 (CANCTRL1) ........................................................................... 16-28
Prescaler Divide Register (PRESDIV) ................................................................... 16-29
Control Register 2 (CANCTRL2) ........................................................................... 16-30
Free Running Timer (TIMER) ................................................................................ 16-31
Receive Global Mask Registers (RXGMSKHI, RXGMSKLO) ............................ 16-31
Receive Buffer 14 Mask Registers (RX14MSKHI, RX14MSKLO) ...................... 16-32
Receive Buffer 15 Mask Registers (RX15MSKHI, RX15MSKLO) ...................... 16-33
Error and Status Register (ESTAT) ........................................................................ 16-33
Interrupt Mask Register (IMASK) .......................................................................... 16-35
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxi
Contents
Paragraph
Number
16.7.14
16.7.15
Title
Page
Number
Interrupt Flag Register (IFLAG) ............................................................................. 16-36
Error Counters (RXECTR, TXECTR) .................................................................... 16-36
Chapter 17
Modular Input/Output Subsystem (MIOS14)
17.1
17.2
17.2.1
17.2.2
17.3
17.3.1
17.3.2
17.3.3
17.3.4
17.3.5
17.4
17.4.1
17.4.2
17.5
17.6
17.6.1
17.6.1.1
17.6.1.2
17.6.1.3
17.6.1.4
17.7
17.7.1
17.7.1.1
17.7.1.2
17.7.2
17.7.3
17.7.3.1
17.7.3.2
17.8
17.8.1
17.8.1.1
17.8.2
17.8.3
17.8.4
17.8.5
Block Diagram .............................................................................................................. 17-1
MIOS14 Key Features .................................................................................................. 17-3
Submodule Numbering, Naming, and Addressing ................................................... 17-4
Signal Naming Convention ....................................................................................... 17-5
MIOS14 Configuration ................................................................................................. 17-6
MIOS14 Signals ........................................................................................................ 17-9
MIOS14 Bus System ................................................................................................ 17-9
Read/Write and Control Bus ................................................................................... 17-10
Request Bus ............................................................................................................ 17-10
Counter Bus Set ...................................................................................................... 17-10
MIOS14 Programming Model .................................................................................... 17-10
Bus Error Support ................................................................................................... 17-10
Wait States .............................................................................................................. 17-11
MIOS14 I/O Ports ....................................................................................................... 17-13
MIOS14 Bus Interface Submodule (MBISM) ............................................................ 17-13
MIOS14 Bus Interface (MBISM) Registers ........................................................... 17-13
MIOS14 Test and Signal Control Register (MIOS14TPCR) ............................. 17-13
MIOS14 Vector Register (MIOS14VECT) ........................................................ 17-14
MIOS14 Module and Version Number Register (MIOS14VNR) ...................... 17-14
MIOS14 Module Configuration Register (MIOS14MCR) ................................. 17-15
MIOS14 Counter Prescaler Submodule (MCPSM) .................................................... 17-16
MCPSM Features .................................................................................................... 17-16
MCPSM Signal Functions .................................................................................. 17-17
Modular I/O Bus (MIOB) Interface .................................................................... 17-17
Effect of RESET on MCPSM ................................................................................. 17-17
MCPSM Registers .................................................................................................. 17-17
MCPSM Registers Organization ........................................................................ 17-17
MCPSM Status/Control Register (MCPSMSCR) .............................................. 17-18
MIOS14 Modulus Counter Submodule (MMCSM) ................................................... 17-19
MMCSM Features .................................................................................................. 17-20
MMCSM Signal Functions ................................................................................. 17-21
MMCSM Prescaler ................................................................................................. 17-21
Modular I/O Bus (MIOB) Interface ........................................................................ 17-21
Effect of RESET on MMCSM ................................................................................ 17-22
MMCSM Registers ................................................................................................. 17-22
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxii
Contents
Paragraph
Number
17.8.5.1
17.8.5.2
17.8.5.3
17.8.5.4
17.8.5.5
17.9
17.9.1
17.9.1.1
17.9.2
17.9.3
17.9.3.1
17.9.3.2
17.9.3.3
17.9.3.4
17.9.3.5
17.9.3.5.1
17.9.3.5.2
17.9.3.5.3
17.9.3.6
17.9.4
17.9.5
17.9.6
17.9.6.1
17.9.6.2
17.9.6.3
17.9.6.4
17.9.6.5
17.10
17.10.1
17.10.2
17.10.3
17.10.3.1
17.10.3.2
17.10.3.3
17.10.3.4
17.10.3.5
17.10.3.6
17.10.3.7
17.10.3.8
17.10.3.9
Title
Page
Number
MMCSM Register Organization ......................................................................... 17-22
MMCSM Up-Counter Register (MMCSMCNT) ............................................... 17-23
MMCSM Modulus Latch Register (MMCSMML) ............................................ 17-24
MMCSM Status/Control Register (MMCSMSCRD)
(Duplicated) .................................................................................................... 17-24
MMCSM Status/Control Register (MMCSMSCR) ............................................ 17-24
MIOS14 Double Action Submodule (MDASM) ........................................................ 17-26
MDASM Features ................................................................................................... 17-27
MDASM Signal Functions ................................................................................. 17-28
MDASM Description .............................................................................................. 17-28
MDASM Modes of Operation ................................................................................ 17-29
Disable (DIS) Mode ............................................................................................ 17-29
Input Pulse Width Measurement (IPWM) Mode ................................................ 17-30
Input Period Measurement (IPM) Mode ............................................................. 17-31
Input Capture (IC) Mode .................................................................................... 17-32
Output Compare (OCB and OCAB) Modes ....................................................... 17-33
Single Shot Output Pulse Operation ............................................................... 17-34
Single Output Compare Operation ................................................................. 17-35
Output Port Bit Operation ............................................................................... 17-36
Output Pulse Width Modulation (OPWM) Mode .............................................. 17-36
Modular I/O Bus (MIOB) Interface ........................................................................ 17-39
Effect of RESET on MDASM ................................................................................ 17-39
MDASM Registers ................................................................................................. 17-39
MDASM Registers Organization ....................................................................... 17-39
MDASM Data A (MDASMAR) Register .......................................................... 17-41
MDASM Data B (MDASMBR) Register ........................................................... 17-42
MDASM Status/Control Register (MDASMSCRD) (Duplicated) .................... 17-43
MDASM Status/Control Register (MDASMSCR) ............................................ 17-43
MIOS14 Pulse Width Modulation Submodule (MPWMSM) .................................... 17-46
MPWMSM Terminology ........................................................................................ 17-47
MPWMSM Features ............................................................................................... 17-47
MPWMSM Description .......................................................................................... 17-48
Clock Selection ................................................................................................... 17-49
Counter ............................................................................................................... 17-49
Period Register .................................................................................................... 17-49
Pulse Width Registers ......................................................................................... 17-50
Duty Cycles (0% and 100%) .............................................................................. 17-51
Pulse/Frequency Range Table ............................................................................ 17-52
MPWMSM Status and Control Register (SCR) ................................................. 17-53
MPWMSM Interrupt .......................................................................................... 17-53
MPWMSM Port Functions ................................................................................. 17-54
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxiii
Contents
Paragraph
Number
17.10.3.10
17.10.4
17.10.5
17.10.6
17.10.6.1
17.10.6.2
17.10.6.3
17.10.6.4
17.10.6.5
17.11
17.11.1
17.11.2
17.11.3
17.11.3.1
17.11.3.2
17.11.4
17.11.5
17.11.6
17.11.7
17.11.8
17.11.8.1
17.11.8.2
17.12
17.12.1
17.12.2
17.12.3
17.12.3.1
17.12.3.2
17.12.3.3
17.12.4
17.12.4.1
17.12.4.2
17.12.4.3
17.12.5
17.12.6
17.12.6.1
17.12.6.2
17.13
17.13.1
17.13.2
17.13.3
Title
Page
Number
MPWMSM Data Coherency ............................................................................... 17-54
Modular Input/Output Bus (MIOS14) Interface ..................................................... 17-54
Effect of RESET on MPWMSM ............................................................................ 17-54
MPWMSM Registers .............................................................................................. 17-55
MPWMSM Registers Organization .................................................................... 17-55
MPWMSM Period Register (MPWMPERR) ..................................................... 17-57
MPWMSM Pulse Width Register (MPWMPULR) ........................................... 17-57
MPWMSM Counter Register (MPWMCNTR) .................................................. 17-58
MPWMSM Status/Control Register (MPWMSCR) ........................................... 17-58
MIOS14 16-bit Parallel Port I/O Submodule (MPIOSM) .......................................... 17-60
MPIOSM Features .................................................................................................. 17-61
MPIOSM Signal Functions ..................................................................................... 17-61
MPIOSM Description ............................................................................................. 17-61
MPIOSM Port Function ...................................................................................... 17-61
Non-Bonded MPIOSM Pads .............................................................................. 17-61
Modular I/O Bus (MIOB) Interface ........................................................................ 17-62
Effect of RESET on MPIOSM ............................................................................... 17-62
MPIOSM Testing .................................................................................................... 17-62
MPIOSM Registers ................................................................................................. 17-62
MPIOSM Register Organization ............................................................................ 17-62
MPIOSM Data Register (MPIOSMDR) ............................................................. 17-62
MPIOSM Data Direction Register (MPIOSMDDR) .......................................... 17-63
MIOS14 Interrupts ...................................................................................................... 17-63
MIOS14 Interrupt Structure .................................................................................... 17-63
MIOS14 Interrupt Request Submodule (MIRSM) ................................................. 17-64
MIRSM0 Interrupt Registers .................................................................................. 17-65
Interrupt Status Register (MIOS14SR0) ............................................................. 17-65
Interrupt Enable Register (MIOS14ER0) ........................................................... 17-66
Interrupt Request Pending Register (MIOS14RPR0) ......................................... 17-66
MIRSM1 Interrupt Registers .................................................................................. 17-67
Interrupt Status Register (MIOS14SR1) ............................................................. 17-67
Interrupt Enable Register (MIOS14ER1) ........................................................... 17-68
Interrupt Request Pending Register (MIOS14RPR1) ......................................... 17-68
Interrupt Control Section (ICS) .............................................................................. 17-69
MBISM Interrupt Registers .................................................................................... 17-69
MIOS14 Interrupt Level Register 0 (MIOS14LVL0) ........................................ 17-69
MIOS14 Interrupt Level Register 1 (MIOS14LVL1) ........................................ 17-70
MIOS14 Function Examples ...................................................................................... 17-70
MIOS14 Input Double Edge Pulse Width Measurement ........................................ 17-70
MIOS14 Input Double Edge Period Measurement ................................................. 17-71
MIOS14 Double Edge Single Output Pulse Generation ......................................... 17-72
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxiv
Contents
Paragraph
Number
17.13.4
17.13.5
Title
Page
Number
MIOS14 Output Pulse Width Modulation with MDASM ...................................... 17-73
MIOS14 Input Pulse Accumulation ........................................................................ 17-74
Chapter 18
Peripheral Pin Multiplexing (PPM) Module
18.1
18.2
18.3
18.3.1
18.3.1.1
18.3.1.2
18.3.1.3
18.3.2
18.3.2.1
18.3.2.2
18.3.2.3
18.3.2.4
18.3.3
18.4
18.4.1
18.4.1.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
18.4.7
18.4.8
18.4.9
18.4.10
18.4.11
18.4.12
Key Features ................................................................................................................. 18-1
Programming Model ..................................................................................................... 18-2
Functional Description .................................................................................................. 18-3
PPM Parallel-to-Serial Communication Protocol ..................................................... 18-3
Internal Multiplexing ............................................................................................ 18-4
PPM Clocks .......................................................................................................... 18-5
PPM Control Settings ........................................................................................... 18-7
PPM Signal Short Functionality ............................................................................... 18-9
TouCAN Shorting ................................................................................................. 18-9
TPU Shorting ........................................................................................................ 18-9
ETRIG1 and ETRIG2 ........................................................................................... 18-9
T2CLK ................................................................................................................ 18-10
PPM Module Pad Configuration ............................................................................. 18-10
PPM Registers ............................................................................................................. 18-10
Module Configuration Register (PPMMCR) .......................................................... 18-10
Entering Stop Mode ............................................................................................ 18-11
PPM Control Register (PPMPCR) .......................................................................... 18-12
Transmit Configuration Registers (TX_CONFIG_1 and TX_CONFIG_2) ........... 18-15
Receive Configuration Registers (RX_CONFIG_1 and RX_CONFIG_2) ............ 18-16
Receive Data Register (RX_DATA) ...................................................................... 18-17
Receive Shift Register (RX_SHIFTER) ................................................................. 18-18
Transmit Data Register (TX_DATA) ..................................................................... 18-18
General-Purpose Data Out (GPDO) ....................................................................... 18-18
General-Purpose Data In (GPDI) ............................................................................ 18-19
Short Register (SHORT_REG) .............................................................................. 18-19
Short Channels Register (SHORT_CH_REG) ...................................................... 18-22
Scale Transmit Clock Register (SCALE_TCLK_REG) ........................................ 18-24
Chapter 19
Time Processor Unit 3
19.1
19.2
19.2.1
Overview ....................................................................................................................... 19-2
TPU3 Components ........................................................................................................ 19-2
Time Bases ................................................................................................................ 19-2
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxv
Contents
Paragraph
Number
19.2.2
19.2.3
19.2.4
19.2.5
19.2.6
19.3
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
19.3.9
19.4
19.4.1
19.4.2
19.4.3
19.4.4
19.4.5
19.4.6
19.4.7
19.4.8
19.4.9
19.4.10
19.4.11
19.4.12
19.4.13
19.4.14
19.4.15
19.5
Title
Page
Number
Timer Channels ......................................................................................................... 19-2
Scheduler .................................................................................................................. 19-2
Microengine .............................................................................................................. 19-3
Host Interface ............................................................................................................ 19-3
Parameter RAM ........................................................................................................ 19-3
TPU Operation .............................................................................................................. 19-3
Event Timing ............................................................................................................ 19-3
Channel Orthogonality .............................................................................................. 19-4
Interchannel Communication .................................................................................... 19-4
Programmable Channel Service Priority .................................................................. 19-4
Coherency ................................................................................................................. 19-4
Emulation Support .................................................................................................... 19-4
TPU3 Interrupts ........................................................................................................ 19-5
Prescaler Control for TCR1 ...................................................................................... 19-5
Prescaler Control for TCR2 ...................................................................................... 19-7
Programming Model ..................................................................................................... 19-8
TPU Module Configuration Register (TPUMCR) ................................................. 19-11
Development Support Control Register (DSCR) .................................................... 19-12
Development Support Status Register (DSSR) ...................................................... 19-13
TPU3 Interrupt Configuration Register (TICR) ..................................................... 19-14
Channel Interrupt Enable Register (CIER) ............................................................. 19-15
Channel Function Select Registers (CFSRn) .......................................................... 19-15
Host Sequence Registers (HSQRn) ........................................................................ 19-16
Host Service Request Registers (HSRRn) ............................................................. 19-17
Channel Priority Registers (CPRx) ......................................................................... 19-18
Channel Interrupt Status Register (CISR) .............................................................. 19-19
TPU3 Module Configuration Register 2 (TPUMCR2) ........................................... 19-19
TPU Module Configuration Register 3 (TPUMCR3) ............................................. 19-21
SIU Test Register (SIUTST) ................................................................................... 19-22
Factory Test Registers ............................................................................................ 19-22
TPU3 Parameter RAM ............................................................................................ 19-23
Time Functions ........................................................................................................... 19-23
Chapter 20
Dual-Port TPU3 RAM (DPTRAM)
20.1
20.2
20.3
20.3.1
20.3.2
Features ......................................................................................................................... 20-1
DPTRAM Configuration Block Diagram ..................................................................... 20-2
Programming Model ..................................................................................................... 20-2
DPTRAM Module Configuration Register (DPTMCR) ......................................... 20-3
DPTRAM Test Register (DPTTCR) ......................................................................... 20-4
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxvi
Contents
Paragraph
Number
20.3.3
20.3.4
20.3.5
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.4.6
20.5
Title
Page
Number
RAM Base Address Register (RAMBAR) ............................................................... 20-4
MISR High (MISRH) and MISR Low Registers (MISRL) ...................................... 20-5
MISC Counter (MISCNT) ........................................................................................ 20-6
DPTRAM Operation ..................................................................................................... 20-6
Normal Operation ..................................................................................................... 20-6
Standby Operation .................................................................................................... 20-6
Reset Operation ......................................................................................................... 20-7
Stop Operation .......................................................................................................... 20-7
Freeze Operation ....................................................................................................... 20-7
TPU3 Emulation Mode Operation ............................................................................ 20-7
Multiple Input Signature Calculator (MISC) ................................................................ 20-8
Chapter 21
CDR3 Flash (UC3F) EEPROM
21.0.1
21.1
21.1.1
21.2
21.2.1
21.2.1.1
21.2.1.2
21.2.1.3
21.2.1.4
21.2.2
21.2.3
21.2.3.1
21.2.4
21.3
21.3.1
21.3.2
21.3.3
21.3.3.1
21.3.4
21.3.5
21.3.6
21.3.6.1
21.3.7
21.3.7.1
21.3.7.2
21.3.7.3
Features of the CDR3 Flash EEPROM (UC3F) ....................................................... 21-3
UC3F Interface ............................................................................................................. 21-4
External Interface ...................................................................................................... 21-4
Programming Model ..................................................................................................... 21-5
UC3F EEPROM Control Registers .......................................................................... 21-5
Register Addressing .............................................................................................. 21-5
UC3F EEPROM Configuration Register (UC3FMCR) ....................................... 21-5
UC3F EEPROM Extended Configuration Register (UC3FMCRE) ..................... 21-8
UC3F EEPROM High Voltage Control Register (UC3FCTL) .......................... 21-11
UC3F EEPROM Array Addressing ........................................................................ 21-15
UC3F EEPROM Shadow Row ............................................................................... 21-15
Reset Configuration Word (UC3FCFIG) ........................................................... 21-16
UC3F EEPROM 512-Kbyte Array Configuration .................................................. 21-19
UC3F Operation .......................................................................................................... 21-19
Reset ........................................................................................................................ 21-19
Register Read and Write Operation ........................................................................ 21-20
Array Read Operation ............................................................................................. 21-20
Array On-Page Read Operation .......................................................................... 21-21
Shadow Row Select Read Operation ...................................................................... 21-21
Array Program/Erase Interlock Write Operation .................................................... 21-21
High Voltage Operations ........................................................................................ 21-21
Overview of Program/Erase Operation .............................................................. 21-21
Programming .......................................................................................................... 21-21
Program Sequence .............................................................................................. 21-22
Program Shadow Information ............................................................................. 21-24
Program Suspend ................................................................................................ 21-25
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxvii
Contents
Paragraph
Number
21.3.8
21.3.8.1
21.3.8.2
21.3.8.3
21.3.9
21.3.10
21.3.11
21.3.11.1
21.3.11.2
21.3.11.3
21.3.11.4
21.3.12
Title
Page
Number
Erasing .................................................................................................................... 21-25
Erase Sequence ................................................................................................... 21-26
Erasing Shadow Information Words .................................................................. 21-28
Erase Suspend ..................................................................................................... 21-28
Stop Operation ........................................................................................................ 21-28
Disabled .................................................................................................................. 21-29
Censored Accesses and Non-Censored Accesses ................................................... 21-29
Setting and Clearing Censor ............................................................................... 21-31
Setting Censor ..................................................................................................... 21-32
Clearing Censor .................................................................................................. 21-32
Switching The UC3F EEPROM Censorship ...................................................... 21-33
Background Debug Mode or Freeze Operation ...................................................... 21-34
Chapter 22
CALRAM Operation
22.1
22.2
22.3
22.4
22.4.1
22.4.2
22.4.2.1
22.4.3
22.4.4
22.4.5
22.4.6
22.4.6.1
22.4.6.2
22.4.6.3
22.4.6.4
22.5
22.5.1
22.5.2
22.5.3
22.5.4
Features ......................................................................................................................... 22-1
CALRAM Block Diagram ............................................................................................ 22-2
CALRAM Memory Map .............................................................................................. 22-2
Modes of Operation ...................................................................................................... 22-4
Reset .......................................................................................................................... 22-5
One-Cycle Mode ....................................................................................................... 22-5
CALRAM Access/Privilege Violations ................................................................ 22-5
Two-Cycle Mode ...................................................................................................... 22-5
Standby Operation/Keep-Alive Power .................................................................... 22-5
Stop Operation .......................................................................................................... 22-6
Overlay Mode Operation ......................................................................................... 22-6
Overlay Mode Configuration ................................................................................ 22-6
Priority of Overlay Regions ................................................................................ 22-11
Normal (Non-Overlay) Access to Overlay Regions ........................................... 22-12
Calibration Write Cycle Flow ............................................................................. 22-12
Programming Model ................................................................................................... 22-12
CALRAM Module Configuration Register (CRAMMCR) .................................... 22-13
CALRAM Region Base Address Registers (CRAM_RBAx) ................................ 22-15
CALRAM Overlay Configuration Register (CRAM_OVLCR) ............................. 22-17
CALRAM Ownership Trace Register (CRAM_OTR) ........................................... 22-17
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxviii
Contents
Paragraph
Number
Title
Page
Number
Chapter 23
Development Support
23.1
23.1.1
23.1.1.1
23.1.1.2
23.1.1.3
23.1.2
23.1.3
23.1.4
23.1.4.1
23.1.4.2
23.1.4.3
23.1.4.4
23.1.4.5
23.1.5
23.2
23.2.1
23.2.1.1
23.2.1.2
23.2.1.3
23.2.1.4
23.2.1.5
23.2.1.6
23.2.2
23.2.2.1
23.2.3
23.2.3.1
23.3
23.3.1
23.3.1.1
23.3.1.2
23.3.1.3
23.3.1.4
23.3.1.5
23.3.1.6
23.4
23.4.1
23.4.2
23.4.3
Program Flow Tracking ................................................................................................ 23-1
Program Trace Cycle ................................................................................................ 23-2
Instruction Queue Status Pins — VF [0:2] ........................................................... 23-2
History Buffer Flushes Status Pins— VFLS [0:1] ............................................... 23-3
Queue Flush Information Special Case ................................................................ 23-4
Program Trace when in Debug Mode ....................................................................... 23-4
Sequential Instructions Marked as Indirect Branch .................................................. 23-4
External Hardware .................................................................................................... 23-4
Synchronizing the Trace Window to the CPU Internal Events ............................ 23-5
Detecting the Trace Window Start Address ......................................................... 23-6
Detecting the Assertion/Negation of VSYNC ...................................................... 23-6
Detecting the Trace Window End Address .......................................................... 23-6
Compress .............................................................................................................. 23-7
Instruction Fetch Show Cycle Control ...................................................................... 23-7
Watchpoints and Breakpoints Support ......................................................................... 23-7
Internal Watchpoints and Breakpoints ...................................................................... 23-9
Restrictions ......................................................................................................... 23-11
Byte and Half-Word Working Modes ................................................................ 23-11
Examples ............................................................................................................. 23-12
Context Dependent Filter .................................................................................... 23-13
Ignore First Match .............................................................................................. 23-14
Generating Six Compare Types .......................................................................... 23-14
Instruction Support ................................................................................................. 23-14
Load/Store Support ............................................................................................. 23-16
Watchpoint Counters .............................................................................................. 23-19
Trap Enable Programming .................................................................................. 23-19
Development System Interface ................................................................................... 23-19
Debug Mode Support .............................................................................................. 23-21
Debug Mode Enable vs. Debug Mode Disable .................................................. 23-23
Entering Debug Mode ......................................................................................... 23-24
Check Stop State and Debug Mode .................................................................... 23-26
Saving Machine State upon Entering Debug Mode ........................................... 23-27
Running in Debug Mode .................................................................................... 23-27
Exiting Debug Mode ........................................................................................... 23-28
Development Port ....................................................................................................... 23-28
Development Port Pins ........................................................................................... 23-28
Development Serial Clock ...................................................................................... 23-29
Development Serial Data In .................................................................................... 23-29
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxix
Contents
Paragraph
Number
23.4.4
23.4.5
23.4.5.1
23.4.5.2
23.4.5.3
23.4.6
23.4.6.1
23.4.6.2
23.4.6.3
23.4.6.4
23.4.6.5
23.4.6.6
23.4.6.7
23.4.6.8
23.4.6.9
23.4.6.10
23.4.6.11
23.5
23.5.1
23.6
23.6.1
23.6.2
23.6.3
23.6.4
23.6.5
23.6.6
23.6.7
23.6.8
23.6.9
23.6.10
23.6.11
23.6.12
23.6.13
Title
Page
Number
Development Serial Data Out ................................................................................. 23-29
Freeze Signal ........................................................................................................... 23-29
SGPIO6/FRZ/PTR Signal ................................................................................... 23-30
IWP[0:1]/VFLS[0:1] Signals .............................................................................. 23-30
VFLS[0:1]/MPIO32B[3:4] Signals ................................................................... 23-30
Development Port Registers ................................................................................... 23-30
Development Port Shift Register ........................................................................ 23-30
Trap Enable Control Register ............................................................................. 23-30
Development Port Registers Decode .................................................................. 23-31
Development Port Serial Communications — Clock Mode Selection ............... 23-31
Development Port Serial Communications — Trap Enable Mode .................... 23-33
Serial Data into Development Port — Trap Enable Mode ................................. 23-33
Serial Data Out of Development Port — Trap Enable Mode ............................. 23-34
Development Port Serial Communications — Debug Mode ............................. 23-35
Serial Data Into Development Port ..................................................................... 23-35
Serial Data Out of Development Port ................................................................. 23-36
Fast Download Procedure ................................................................................... 23-37
Software Monitor Debugger Support ......................................................................... 23-38
Freeze Indication ..................................................................................................... 23-38
Development Support Registers ................................................................................. 23-39
Register Protection .................................................................................................. 23-40
Comparator A–D Value Registers (CMPA–CMPD) .............................................. 23-41
Exception Cause Register (ECR) ............................................................................ 23-41
Debug Enable Register (DER) ................................................................................ 23-43
Breakpoint Counter A Value and Control Register ................................................ 23-45
Breakpoint Counter B Value and Control Register ................................................ 23-46
Comparator E–F Value Registers (CMPE–CMPF) ................................................ 23-46
Comparator G–H Value Registers (CMPG–CMPH) .............................................. 23-47
L-Bus Support Control Register 1 .......................................................................... 23-47
L-Bus Support Control Register 2 .......................................................................... 23-48
I-Bus Support Control Register (ICTRL) ............................................................... 23-51
Breakpoint Address Register (BAR) ...................................................................... 23-53
Development Port Data Register (DPDR) .............................................................. 23-53
Chapter 24
READI Module
24.1
24.1.1
24.2
24.2.1
Features Summary ........................................................................................................ 24-1
Functional Block Diagram ........................................................................................ 24-2
Modes of Operation ...................................................................................................... 24-3
Reset Configuration .................................................................................................. 24-3
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxx
Contents
Paragraph
Number
24.2.2
24.2.3
24.2.4
24.3
24.4
24.5
24.6
24.6.1
24.6.1.1
24.6.1.2
24.6.1.3
24.6.1.4
24.6.1.5
24.6.1.6
24.6.1.7
24.6.1.8
24.6.1.9
24.6.2
24.6.3
24.6.4
24.6.5
24.6.5.1
24.6.5.2
24.7
24.7.1
24.7.1.1
24.7.2
24.7.3
24.7.4
24.7.5
24.7.5.1
24.7.5.2
24.7.5.3
24.7.5.3.1
24.7.5.3.2
24.7.5.4
24.7.6
24.7.7
24.7.7.1
24.7.7.2
Title
Page
Number
Security ..................................................................................................................... 24-4
Normal ...................................................................................................................... 24-4
Disabled .................................................................................................................... 24-4
Parametrics .................................................................................................................... 24-4
Messages ....................................................................................................................... 24-4
Terms and Definitions .................................................................................................. 24-6
Programming Model ..................................................................................................... 24-8
Register Map ............................................................................................................. 24-8
User-Mapped Register (OTR) .............................................................................. 24-8
Tool-Mapped Registers ........................................................................................ 24-9
Device ID Register (DID) ..................................................................................... 24-9
Development Control Register (DC) .................................................................. 24-10
Mode Control Register (MC) .............................................................................. 24-11
User Base Address Register (UBA) ................................................................... 24-12
Read/Write Access Register (RWA) .................................................................. 24-13
Upload/Download Information Register (UDI) .................................................. 24-15
Data Trace Attributes 1 and 2 Registers (DTA1 and DTA2) ............................. 24-17
Accessing Memory-Mapped Locations Via
the Auxiliary Port ............................................................................................... 24-18
Accessing READI Tool Mapped Registers Via the Auxiliary Port ........................ 24-19
Partial Register Updates .......................................................................................... 24-19
Programming Considerations ................................................................................. 24-20
Program Trace Guidelines .................................................................................. 24-20
Compressed Code Mode Guidelines .................................................................. 24-20
Signal Interface ........................................................................................................... 24-20
Functional Description ............................................................................................ 24-21
Signals Implemented .......................................................................................... 24-21
Functional Block Diagram ...................................................................................... 24-22
Message Priority ..................................................................................................... 24-22
Signal Protocol ........................................................................................................ 24-23
Messages ................................................................................................................. 24-24
Message Formats ................................................................................................ 24-28
Rules of Messages .............................................................................................. 24-31
Branch Trace Message Examples ....................................................................... 24-32
Example of Indirect Branch Message ............................................................. 24-32
Example of Direct Branch Message ............................................................... 24-33
Non-Temporal Ordering of Transmitted Messages ............................................ 24-33
READI Reset Configuration ................................................................................... 24-34
READI Signals ....................................................................................................... 24-36
Reset Configuration for Debug Mode ................................................................ 24-36
Reset Configuration for Non-Debug Mode ........................................................ 24-37
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxxi
Contents
Paragraph
Number
24.7.7.3
24.7.7.4
24.7.7.5
24.8
24.8.1
24.8.1.1
24.8.2
24.8.2.1
24.8.2.2
24.8.2.3
24.8.2.4
24.8.2.4.1
24.8.2.4.2
24.8.2.4.3
24.8.2.4.4
24.8.2.4.5
24.8.2.5
24.8.2.6
24.8.3
24.8.4
24.8.4.1
24.8.4.2
24.8.4.3
24.8.4.4
24.8.5
24.8.6
24.8.7
24.9
24.9.1
24.9.2
24.9.2.1
24.9.2.2
24.9.2.3
24.9.2.4
24.9.2.5
24.9.2.6
24.9.3
24.9.4
24.9.5
24.9.6
24.9.7
Title
Page
Number
Secure Mode ....................................................................................................... 24-37
Disabled Mode .................................................................................................... 24-37
Guidelines for Transmitting Input Messages ...................................................... 24-37
Program Trace ............................................................................................................ 24-38
Branch Trace Messaging ........................................................................................ 24-38
RCPU Instructions that Cause BTM Messages .................................................. 24-38
BTM Message Formats ........................................................................................... 24-38
Direct Branch Messages ..................................................................................... 24-38
Indirect Branch Messages ................................................................................... 24-39
Correction Messages ........................................................................................... 24-40
Synchronization Messages .................................................................................. 24-42
Direct Branch Synchronization Message ....................................................... 24-44
Indirect Branch Synchronization Message ..................................................... 24-44
Direct Branch Synchronization Message With Compressed Code ................ 24-44
Indirect Branch Synchronization Message with Compressed Code ............... 24-45
Resource Full Message ................................................................................... 24-45
Error Messages ................................................................................................... 24-46
Relative Addressing ............................................................................................ 24-46
Queue Overflow Program Trace Error Message .................................................... 24-47
Branch Trace Message Operation ........................................................................... 24-47
BTM Capture and Encoding Algorithm ............................................................. 24-47
Instruction Fetch Snooping ................................................................................. 24-48
Instruction Execution Tracking .......................................................................... 24-48
Instruction Flush Cases ....................................................................................... 24-48
Branch Trace Message Queueing ........................................................................... 24-48
BTM Timing Diagrams .......................................................................................... 24-49
Program Trace Guidelines ...................................................................................... 24-51
Data Trace .................................................................................................................. 24-52
Data Trace for the Load/Store Bus (L-Bus) ............................................................ 24-52
Data Trace Message Formats .................................................................................. 24-52
Data Write Message ............................................................................................ 24-52
Data Read Message ............................................................................................. 24-53
Data Trace Synchronization Messages ............................................................... 24-53
Data Write Synchronization Message ................................................................ 24-54
Data Read Synchronization Messaging .............................................................. 24-54
Relative Addressing ............................................................................................ 24-54
Queue Overflow Data Trace Error Message ........................................................... 24-54
Data Trace Operation .............................................................................................. 24-54
Data Trace Windowing ........................................................................................... 24-56
Special L-Bus Cases ............................................................................................... 24-56
Data Trace Queuing ................................................................................................ 24-56
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxxii
Contents
Paragraph
Number
24.9.8
24.9.8.1
24.9.8.2
24.9.9
24.10
24.10.1
24.10.2
24.10.2.1
24.10.2.2
24.10.3
24.10.3.1
24.10.3.2
24.10.4
24.10.4.1
24.10.4.2
24.10.5
24.10.5.1
24.10.5.2
24.10.5.3
24.10.6
24.10.7
24.10.8
24.10.8.1
24.10.8.2
24.10.8.3
24.10.9
24.10.10
24.10.10.1
24.11
24.12
24.12.1
24.12.1.1
24.12.2
24.12.3
24.12.4
24.13
24.13.1
24.13.2
24.13.2.1
24.13.2.2
24.13.3
Title
Page
Number
Throughput and Latency ......................................................................................... 24-57
Assumptions for Throughput Analysis ............................................................... 24-57
Throughput Calculations .................................................................................... 24-57
Data Timing Diagrams ............................................................................................ 24-57
Read/Write Access ...................................................................................................... 24-59
Functional Description ............................................................................................ 24-59
Write Operation to Memory-Mapped Locations and SPR Registers ..................... 24-61
Single Write Operation ....................................................................................... 24-61
Block Write Operation ........................................................................................ 24-62
Read Operation to Memory-Mapped Locations and SPR Registers ...................... 24-63
Single Read Operation ........................................................................................ 24-63
Block Read Operation ......................................................................................... 24-64
Read/Write Access to Internal READI Registers ................................................... 24-64
Write Operation .................................................................................................. 24-64
Read Operation ................................................................................................... 24-65
Error Handling ........................................................................................................ 24-65
Access Alignment ............................................................................................... 24-65
L-Bus Address Error ........................................................................................... 24-65
L-Bus Data Error ................................................................................................ 24-65
Exception Sequences .............................................................................................. 24-66
Secure Mode ........................................................................................................... 24-66
Error Messages ....................................................................................................... 24-66
Read/Write Access Error .................................................................................... 24-66
Invalid Message .................................................................................................. 24-67
Invalid Access Opcode ....................................................................................... 24-67
Faster Read/Write Accesses with Default Attributes ............................................. 24-67
Throughput and Latency ......................................................................................... 24-68
Assumptions for Throughput Analysis ............................................................... 24-68
Read/Write Timing Diagrams ..................................................................................... 24-69
Watchpoint Support ................................................................................................... 24-72
Watchpoint Messaging ........................................................................................... 24-72
Watchpoint Source Field .................................................................................... 24-73
Watchpoint Overrun Error Message ....................................................................... 24-73
Synchronization ...................................................................................................... 24-74
Watchpoint Timing Diagrams ................................................................................ 24-74
Ownership Trace ........................................................................................................ 24-74
Ownership Trace Messaging .................................................................................. 24-75
Queue Overflow Ownership Trace Error Message ................................................. 24-75
OTM Flow .......................................................................................................... 24-75
OTM Queueing ................................................................................................... 24-76
OTM Timing Diagrams .......................................................................................... 24-76
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxxiii
Contents
Paragraph
Number
24.14
24.14.1
24.14.1.1
24.14.1.2
24.14.1.3
24.14.1.4
24.14.2
24.14.2.1
24.14.2.2
24.14.2.3
24.14.2.4
24.14.3
24.14.4
24.15
24.15.1
24.15.2
Title
Page
Number
RCPU Development Access ...................................................................................... 24-76
RCPU Development Access Messaging ................................................................. 24-77
DSDI Message .................................................................................................... 24-77
DSDO Message .................................................................................................. 24-78
BDM Status Message ......................................................................................... 24-78
Error Message (Invalid Message) ....................................................................... 24-79
RCPU Development Access Operation .................................................................. 24-79
Enabling RCPU Development Access Via READI Signals ............................... 24-80
Entering Background Debug Mode (BDM) Via READI Signals ...................... 24-80
Non-Debug Mode Access of RCPU Development Access ................................ 24-80
RCPU Development Access Flow Diagram ....................................................... 24-81
Throughput .............................................................................................................. 24-82
Development Access Timing Diagrams ................................................................. 24-82
Power Management ................................................................................................... 24-86
Functional Description ............................................................................................ 24-86
Low Power Modes .................................................................................................. 24-86
Chapter 25
IEEE 1149.1-Compliant Interface (JTAG)
25.1
25.1.1
25.1.2
25.1.2.1
25.1.2.2
25.1.3
25.1.3.1
25.1.3.2
25.1.3.3
25.1.3.4
25.1.4
25.2
25.2.1
25.2.2
IEEE 1149.1 Test Access Port ...................................................................................... 25-1
Overview ................................................................................................................... 25-2
Entering JTAG Mode ................................................................................................ 25-3
TAP Controller ..................................................................................................... 25-4
Boundary Scan Register ....................................................................................... 25-4
Instruction Register ................................................................................................. 25-30
EXTEST ............................................................................................................. 25-31
SAMPLE/PRELOAD ......................................................................................... 25-31
BYPASS ............................................................................................................. 25-31
CLAMP ............................................................................................................... 25-32
HI-Z ........................................................................................................................ 25-32
MPC561/MPC563 Restrictions .................................................................................. 25-32
Non-Scan Chain Operation ..................................................................................... 25-32
BSDL Description ................................................................................................... 25-33
Appendix A
MPC562/MPC564 Compression Features
A.1
A.2
ICDU Key Features ........................................................................................................ A-1
Class-Based Compression Model Main Principles......................................................... A-1
MPC561/MPC563 Reference Manual, Rev. 1.2
xxxiv
Freescale Semiconductor
Contents
Paragraph
Number
A.2.1
A.2.2
A.2.3
A.2.4
A.2.5
A.2.6
A.2.7
A.2.8
A.2.8.1
A.2.8.2
A.2.8.3
A.2.9
A.2.9.1
A.2.9.2
A.2.9.3
A.2.9.4
A.2.9.5
A.2.10
A.2.11
A.2.12
A.2.13
A.2.14
A.2.14.1
A.2.14.2
A.3
A.3.1
A.3.1.1
A.3.1.2
A.3.1.2.1
A.3.2
A.3.3
A.3.3.1
A.4
Title
Page
Number
Compression Model Features ..................................................................................... A-1
Model Limitations....................................................................................................... A-2
Instruction Class-Based Compression Algorithm....................................................... A-2
Compressed Address Generation with Direct Branches............................................. A-4
Compressed Address Generation—Indirect Branches ............................................... A-6
Compressed Address Generation—Exceptions .......................................................... A-6
Class Code Compression Algorithm Rules ................................................................ A-7
Bypass Field Compression Rules ............................................................................... A-7
Branch Right Segment Compression #1................................................................. A-7
Branch Right Segment Compression #2................................................................. A-8
Right Segment Zero Length Compression Bypass................................................. A-8
Instruction Class Structures and Programming .......................................................... A-8
Global Bypass......................................................................................................... A-8
Single Segment Full Compression – CLASS_1 ..................................................... A-9
Twin Segment Full Compression – CLASS_2 ....................................................... A-9
Left Segment Compression and Right Segment Bypass – CLASS_3................. A-10
Left Segment Bypass and Right Segment Compression—CLASS_4..................A-11
Instruction Layout Programming Summary ..............................................................A-11
Compression Process .................................................................................................A-11
Decompression.......................................................................................................... A-12
Compression Environment Initialization .................................................................. A-13
Compression/Non-Compression Mode Switch ........................................................ A-14
Compression Definition for Exception Handlers ................................................. A-14
Running Mixed Code............................................................................................ A-14
Operation Modes........................................................................................................... A-14
Instruction Fetch ....................................................................................................... A-14
Decompression Off Mode..................................................................................... A-15
Decompression On Mode ..................................................................................... A-15
Show Cycles in Decompression On Mode ....................................................... A-15
Vocabulary Table Storage Operation ........................................................................ A-16
READI Compression ................................................................................................ A-16
I-Bus Support Control Register (ICTRL) ............................................................. A-16
Decompressor Class Configuration Registers (DCCR0-15) ........................................ A-18
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxxv
Contents
Paragraph
Number
Title
Page
Number
Appendix B
Internal Memory Map
Appendix C
Clock and Board Guidelines
C.1
C.2
C.2.1
C.2.2
C.2.3
C.3
C.3.1
C.3.2
C.3.3
MPC56x Device Power Distribution ...............................................................................C-2
Crystal Oscillator External Components .........................................................................C-4
KAPWR Filtering ........................................................................................................C-5
PLL External Components...........................................................................................C-5
PLL Off-Chip Capacitor CXFC...................................................................................C-6
PLL and Clock Oscillator External Components Layout Requirements .........................C-7
Traces and Placement ..................................................................................................C-7
Grounding/Guarding....................................................................................................C-7
IRAMSTBY Regulator Circuit....................................................................................C-7
Appendix D
TPU3 ROM Functions
D.1
D.2
D.3
D.4
D.5
D.6
D.7
D.8
D.9
D.10
D.11
D.12
D.13
D.14
D.15
D.16
D.17
D.18
D.19
D.20
D.20.1
Overview......................................................................................................................... D-1
Programmable Time Accumulator (PTA) ....................................................................... D-3
Queued Output Match TPU3 Function (QOM) .............................................................. D-5
Table Stepper Motor (TSM)............................................................................................ D-7
Frequency Measurement (FQM) .................................................................................. D-10
Universal Asynchronous Receiver/Transmitter (UART).............................................. D-12
New Input Capture/Transition Counter (NITC)............................................................ D-15
Multiphase Motor Commutation (COMM) .................................................................. D-17
Hall Effect Decode (HALLD) ...................................................................................... D-20
Multichannel Pulse-Width Modulation (MCPWM) ..................................................... D-22
Multi TPU (MULTI) ..................................................................................................... D-30
Fast Quadrature Decode TPU3 Function (FQD) .......................................................... D-35
Period/Pulse-Width Accumulator (PPWA)................................................................... D-38
ID TPU3 Function (ID)................................................................................................. D-40
Output Compare (OC) .................................................................................................. D-42
Pulse-Width Modulation (PWM).................................................................................. D-44
Discrete Input/Output (DIO)......................................................................................... D-46
Synchronized Pulse-Width Modulation (SPWM)......................................................... D-48
Read/Write Timers and Pin TPU3 Function (RWTPIN) .............................................. D-51
Serial Input/Output Port (SIOP) ................................................................................... D-53
Parameters................................................................................................................. D-53
MPC561/MPC563 Reference Manual, Rev. 1.2
xxxvi
Freescale Semiconductor
Contents
Paragraph
Number
D.20.1.1
D.20.1.2
D.20.1.3
D.20.1.4
D.20.1.5
D.20.1.6
D.20.2
D.20.3
D.20.3.1
D.20.3.2
D.20.3.3
Title
Page
Number
CHAN_CONTROL .............................................................................................. D-56
BIT_D ................................................................................................................... D-56
HALF_PERIOD ................................................................................................... D-56
BIT_COUNT ........................................................................................................ D-56
XFER_SIZE.......................................................................................................... D-56
SIOP_DATA ......................................................................................................... D-57
Host RCPU Initialization of the SIOP Function....................................................... D-57
SIOP Function Performance ..................................................................................... D-57
XFER_SIZE Greater Than 16 .............................................................................. D-58
Data Positioning.................................................................................................... D-58
Data Timing .......................................................................................................... D-58
Appendix E
Memory Access Timing
Appendix F
Electrical Characteristics
F.1
F.2
F.2.1
F.2.2
F.2.3
F.3
F.3.1
F.4
F.5
F.6
F.7
F.8
F.8.1
F.8.2
F.9
F.9.1
F.9.2
F.10
F.10.1
F.11
F.12
F.13
Package ............................................................................................................................ F-2
EMI Characteristics ......................................................................................................... F-2
Reference Documents .................................................................................................. F-2
Definitions and Acronyms ........................................................................................... F-3
EMI Testing Specifications.......................................................................................... F-3
Thermal Characteristics ................................................................................................... F-3
Thermal References ..................................................................................................... F-5
ESD Protection ................................................................................................................ F-6
DC Electrical Characteristics........................................................................................... F-7
Oscillator and PLL Electrical Characteristics................................................................ F-11
Flash Electrical Characteristics...................................................................................... F-12
Power-Up/Down Sequencing......................................................................................... F-13
Power-Up/Down Option A ........................................................................................ F-13
Power-Up/Down Option B ........................................................................................ F-15
Issues Regarding Power Sequence ................................................................................ F-17
Application of PORESET or HRESET ..................................................................... F-17
Keep-Alive RAM....................................................................................................... F-18
AC Timing ..................................................................................................................... F-18
Debug Port Timing .................................................................................................... F-43
READI Electrical Characteristics .................................................................................. F-45
RESET Timing............................................................................................................... F-47
IEEE 1149.1 Electrical Characteristics.......................................................................... F-50
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxxvii
Contents
Paragraph
Number
F.14
F.15
F.16
F.17
F.18
F.19
F.20
F.20.1
F.20.2
F.20.3
F.21
F.22
F.22.1
F.22.1.1
Title
Page
Number
QADC64E Electrical Characteristics............................................................................. F-54
QSMCM Electrical Characteristics ............................................................................... F-56
GPIO Electrical Characteristics ..................................................................................... F-60
TPU3 Electrical Characteristics..................................................................................... F-61
TouCAN Electrical Characteristics................................................................................ F-62
PPM Timing Characteristics .......................................................................................... F-62
MIOS Timing Characteristics ........................................................................................ F-64
MPWMSM Timing Characteristics ........................................................................... F-64
MMCSM Timing Characteristics .............................................................................. F-67
MDASM Timing Characteristics............................................................................... F-69
MPIOSM Timing Characteristics .................................................................................. F-71
Pin Summary ................................................................................................................. F-73
Package Diagrams...................................................................................................... F-83
MPC561/MPC563 Ball Map ................................................................................. F-86
Appendix G
66-MHz Electrical Characteristics
G.1
G.2
G.3
G.3.1
G.3.2
G.3.3
G.4
G.4.1
G.5
G.6
G.7
G.8
G.9
G.9.1
G.9.2
G.10
G.10.1
G.10.2
G.11
G.11.1
G.12
G.13
G.14
66-MHz Feature Limitations .......................................................................................... G-1
Package ........................................................................................................................... G-3
EMI Characteristics ........................................................................................................ G-3
Reference Documents ................................................................................................. G-3
Definitions and Acronyms .......................................................................................... G-3
EMI Testing Specifications......................................................................................... G-3
Thermal Characteristics .................................................................................................. G-3
Thermal References .................................................................................................... G-6
ESD Protection ............................................................................................................... G-6
DC Electrical Characteristics.......................................................................................... G-7
Oscillator and PLL Electrical Characteristics............................................................... G-10
Flash Electrical Characteristics......................................................................................G-11
Power-Up/Down Sequencing........................................................................................ G-12
Power-Up/Down Option A ....................................................................................... G-13
Power-Up/Down Option B ....................................................................................... G-15
Issues Regarding Power Sequence ............................................................................... G-17
Application of PORESET or HRESET .................................................................... G-17
Keep-Alive RAM...................................................................................................... G-18
AC Timing .................................................................................................................... G-18
Debug Port Timing ................................................................................................... G-41
READI Electrical Characteristics ................................................................................. G-43
RESET Timing.............................................................................................................. G-44
IEEE 1149.1 Electrical Characteristics......................................................................... G-47
MPC561/MPC563 Reference Manual, Rev. 1.2
xxxviii
Freescale Semiconductor
Contents
Paragraph
Number
G.15
G.16
G.17
G.18
G.19
G.20
G.21
G.21.1
G.21.2
G.21.3
G.22
G.23
G.23.1
G.23.1.1
Title
Page
Number
QADC64E Electrical Characteristics............................................................................ G-50
QSMCM Electrical Characteristics .............................................................................. G-52
GPIO Electrical Characteristics .................................................................................... G-56
TPU3 Electrical Characteristics.................................................................................... G-57
TouCAN Electrical Characteristics............................................................................... G-58
PPM Timing Characteristics ......................................................................................... G-58
MIOS Timing Characteristics ....................................................................................... G-59
MPWMSM Timing Characteristics .......................................................................... G-60
MMCSM Timing Characteristics ............................................................................. G-62
MDASM Timing Characteristics.............................................................................. G-64
MPIOSM Timing Characteristics ................................................................................. G-67
Pin Summary ................................................................................................................ G-68
Package Diagrams..................................................................................................... G-78
MPC561/MPC563 Ball Map ................................................................................ G-81
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xxxix
Contents
Paragraph
Number
Title
Page
Number
MPC561/MPC563 Reference Manual, Rev. 1.2
xl
Freescale Semiconductor
Figures
Figure
Number
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
2-6
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
Title
Page
Number
MPC561/MPC563 Block Diagram ........................................................................................... 1-3
Recommended Connection Diagram for IRAMSTBY........................................................... 1-11
MPC561/MPC563 Memory Map ........................................................................................... 1-12
MPC561/MPC563 Internal Memory Map .............................................................................. 1-14
MPC561/MPC563 Signal Groupings ....................................................................................... 2-2
Pads Module Configuration Register (PDMCR) .................................................................... 2-22
Pads Module Configuration Register 2 (PDMCR2) ............................................................... 2-23
Debug Mode Selection (JTAG) .............................................................................................. 2-30
Debug Mode Selection (BDM)............................................................................................... 2-30
Debug Mode Selection (Nexus).............................................................................................. 2-31
RCPU Block Diagram .............................................................................................................. 3-2
Sequencer Data Path ................................................................................................................. 3-4
RCPU Programming Model ..................................................................................................... 3-8
General-Purpose Registers (GPRs)......................................................................................... 3-12
Floating-Point Registers (FPRs) ............................................................................................. 3-13
Floating-Point Status and Control Register (FPSCR)............................................................. 3-14
Condition Register (CR) ......................................................................................................... 3-16
Integer Exception Register (XER) .......................................................................................... 3-18
Link Register (LR).................................................................................................................. 3-19
Count Register (CTR) ............................................................................................................. 3-19
Machine State Register (MSR) ............................................................................................... 3-20
DAE/Source Instruction Service Register (DSISR) ............................................................... 3-22
Data Address Register (DAR) ................................................................................................ 3-23
Machine Status Save/Restore Register 0 (SRR0) ................................................................... 3-23
Machine Status Save/Restore Register 1 (SRR1) ................................................................... 3-24
SPRG0–SPRG3 — General Special-Purpose Registers 0–3 .................................................. 3-24
Processor Version Register (PVR) ......................................................................................... 3-25
Floating-Point Exception Cause Register (FPECR) ............................................................... 3-26
Basic Instruction Pipeline ....................................................................................................... 3-38
BBC Module Block Diagram ................................................................................................... 4-2
Exception Table Entries Mapping ............................................................................................ 4-8
External Interrupt Vectors Splitting........................................................................................ 4-12
DECRAM Interfaces Block Diagram ..................................................................................... 4-13
BTB Block Diagram ............................................................................................................... 4-16
MPC561/MPC563 Memory Map ........................................................................................... 4-17
BBC Module Configuration Register (BBCMCR)................................................................. 4-19
Region Base Address Register (MI_RBA[0:3]) ..................................................................... 4-21
Region Attribute Register (MI_RA0[0:3]) ............................................................................. 4-22
Global Region Attribute Register (MI_GRA) ........................................................................ 4-23
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xli
Figures
Figure
Page
Title
Number
Number
4-11
External Interrupt Relocation Table Base Address Register (EIBADR)................................ 4-25
5-1
USIU Block Diagram................................................................................................................ 5-2
6-1
System Configuration and Protection Logic............................................................................. 6-3
6-2
Circuit Paths of Reading and Writing to SGPIO ...................................................................... 6-7
6-3
MPC561/MPC563 Interrupt Structure...................................................................................... 6-9
6-4
Lower Priority Request Masking—One Bit Diagram ............................................................ 6-14
6-5
MPC561/MPC563 Interrupt Controller Block Diagram ........................................................ 6-15
6-6
Typical Interrupt Handler Routine.......................................................................................... 6-17
6-7
RTC Block Diagram ............................................................................................................... 6-20
6-8
PIT Block Diagram ................................................................................................................. 6-21
6-9
SWT State Diagram ................................................................................................................ 6-22
6-10
SWT Block Diagram .............................................................................................................. 6-23
6-11
MPC561/MPC563 Memory Map ........................................................................................... 6-24
6-12
SIU Module Configuration Register (SIUMCR).................................................................... 6-25
6-13
Internal Memory Mapping Register (IMMR)......................................................................... 6-28
6-14
External Master Control Register (EMCR) ............................................................................ 6-30
6-15
SIU Interrupt Pending Register (SIPEND) ............................................................................. 6-32
6-16
SIU Interrupt Pending Register 2 (SIPEND2) ........................................................................ 6-32
6-17
SIU Interrupt Pending Register 3 (SIPEND3) ........................................................................ 6-33
6-18
SIU Interrupt Mask Register (SIMASK) ................................................................................ 6-34
6-19
SIU Interrupt Mask Register 2 (SIMASK2) ........................................................................... 6-34
6-20
SIU Interrupt Mask Register 3 (SIMASK3) ........................................................................... 6-35
6-21
SIU Interrupt Edge Level Register (SIEL) ............................................................................. 6-35
6-22
SIU Interrupt Vector Register (SIVEC).................................................................................. 6-36
6-23
Example of SIVEC Register Usage for Interrupt Table Handling ......................................... 6-36
6-24
Interrupt In-Service Register 2 (SISR2) ................................................................................. 6-37
6-25
Interrupt In-Service Register 3 (SISR3) ................................................................................. 6-37
6-26
System Protection Control Register (SYPCR) ....................................................................... 6-38
6-27
Software Service Register (SWSR) ........................................................................................ 6-39
6-28
Transfer Error Status Register (TESR) ................................................................................... 6-39
6-29
Decrementer Register (DEC).................................................................................................. 6-40
6-30
Time Base (Reading) (TB) ..................................................................................................... 6-41
6-31
Time Base (Writing) (TB) ...................................................................................................... 6-41
6-32
Time Base Reference Register 0 (TBREF0)........................................................................... 6-41
6-33
Time Base Reference Register 1 (TBREF1)........................................................................... 6-41
6-34
Time Base Control and Status Register (TBSCR).................................................................. 6-42
6-35
Real-Time Clock Status and Control Register (RTCSC) ....................................................... 6-43
6-36
Real-Time Clock Register (RTC) ........................................................................................... 6-43
6-37
Real-Time Clock Alarm Register (RTCAL) .......................................................................... 6-44
6-38
Periodic Interrupt Status and Control Register (PISCR) ........................................................ 6-44
MPC561/MPC563 Reference Manual, Rev. 1.2
xlii
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
6-39
Periodic Interrupt Timer Count (PITC) .................................................................................. 6-45
6-40
Periodic Interrupt Timer Register (PITR)............................................................................... 6-45
6-41
SGPIO Data Register 1 (SGPIODT1) .................................................................................... 6-46
6-42
SGPIO Data Register 2 (SGPIODT2) .................................................................................... 6-47
6-43
SGPIO Control Register (SGPIOCR)..................................................................................... 6-48
7-1
Reset Status Register (RSR) ..................................................................................................... 7-5
7-2
Reset Configuration Basic Scheme........................................................................................... 7-8
7-3
Reset Configuration Sampling Scheme for
“Short” PORESET Assertion, Limp Mode Disabled ............................................................... 7-9
7-4
Reset Configuration Timing for “Short” PORESET Assertion, Limp Mode Enabled............. 7-9
7-5
Reset Configuration Timing for “Long” PORESET Assertion, Limp Mode Disabled.......... 7-10
7-6
Reset Configuration Sampling Timing Requirements............................................................ 7-10
7-7
Reset Configuration Word (RCW) ......................................................................................... 7-11
8-1
Clock Unit Block Diagram ....................................................................................................... 8-2
8-2
Main System Oscillator Crystal Configuration ........................................................................ 8-3
8-3
System PLL Block Diagram ..................................................................................................... 8-5
8-4
MPC561/MPC563 Clocks ........................................................................................................ 8-8
8-5
General System Clocks Select ................................................................................................ 8-11
8-6
Divided System Clocks Timing Diagram ............................................................................... 8-12
8-7
Clocks Timing For DFNH = 1 (or DFNL = 0) ....................................................................... 8-13
8-8
Clock Source Switching Flow Chart ...................................................................................... 8-15
8-9
Low-Power Modes Flow Diagram ......................................................................................... 8-20
8-10
IRAMSTBY Regulator Circuit ............................................................................................... 8-23
8-11
Basic Power Supply Configuration......................................................................................... 8-24
8-12
External Power Supply Scheme.............................................................................................. 8-25
8-13
Keep-Alive Register Key State Diagram................................................................................ 8-27
8-14
No Standby, No KAPWR, All System Power-On/Off ........................................................... 8-28
8-15
Standby and KAPWR, Other Power-On/Off .......................................................................... 8-29
8-16
System Clock and Reset Control Register (SCCR) ................................................................ 8-30
8-17
PLL, Low-Power, and Reset-Control Register (PLPRCR) .................................................... 8-34
8-18
Change of Lock Interrupt Register (COLIR).......................................................................... 8-36
8-19
IRAMSTBY Control Register (VSRMCR) ............................................................................ 8-37
9-1
Input Sample Window .............................................................................................................. 9-2
9-2
MPC561/MPC563 Bus Signals ................................................................................................ 9-3
9-3
Basic Transfer Protocol ............................................................................................................ 9-8
9-4
Basic Flow Diagram of a Single Beat Read Cycle ................................................................... 9-9
9-5
Single Beat Read Cycle – Basic Timing – Zero Wait States.................................................. 9-10
9-6
Single Beat Read Cycle – Basic Timing – One Wait State .................................................... 9-11
9-7
Basic Flow Diagram of a Single Beat Write Cycle ................................................................ 9-12
9-8
Single Beat Basic Write Cycle Timing – Zero Wait States .................................................... 9-13
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xliii
Figures
Figure
Page
Title
Number
Number
9-9
Single Beat Basic Write Cycle Timing – One Wait State ...................................................... 9-14
9-10
Single Beat 32-Bit Data Write Cycle Timing — 16-Bit Port Size ......................................... 9-15
9-11
Read Followed by Write when Pre-Discharge Mode is Enabled, and EHTR is Set .............. 9-17
9-12
Basic Flow Diagram Of A Burst-Read Cycle......................................................................... 9-21
9-13
Burst-Read Cycle – 32-Bit Port Size – Zero Wait State......................................................... 9-21
9-14
Burst-Read Cycle – 32-Bit Port Size – One Wait State.......................................................... 9-22
9-15
Burst-Read Cycle – 32-Bit Port Size – Wait States Between Beats ....................................... 9-23
9-16
Burst-Read Cycle – 16-Bit Port Size ...................................................................................... 9-24
9-17
Basic Flow Diagram of a Burst-Write Cycle.......................................................................... 9-26
9-18
Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
(Only for External Master Memory Controller Service Support)........................................... 9-26
9-19
Burst-Inhibit Read Cycle, 32-Bit Port Size (Emulated Burst)................................................ 9-27
9-20
Non-Wrap Burst with Three Beats ......................................................................................... 9-28
9-21
Non-Wrap Burst with One Data Beat ..................................................................................... 9-29
9-22
Internal Operand Representation ............................................................................................ 9-30
9-23
Interface To Different Port Size Devices................................................................................ 9-31
9-24
Bus Arbitration Flowchart ...................................................................................................... 9-33
9-25
Master Signals Basic Connection ........................................................................................... 9-34
9-26
Bus Arbitration Timing Diagram............................................................................................ 9-35
9-27
Internal Bus Arbitration State Machine .................................................................................. 9-36
9-28
Termination Signals Protocol Basic Connection .................................................................... 9-41
9-29
Termination Signals Protocol Timing Diagram...................................................................... 9-41
9-30
Reservation on Local Bus ....................................................................................................... 9-43
9-31
Reservation on Multi-level Bus Hierarchy ............................................................................. 9-44
9-32
Retry Transfer Timing – Internal Arbiter ............................................................................... 9-46
9-33
Retry Transfer Timing – External Arbiter .............................................................................. 9-47
9-34
Retry on Burst Cycle............................................................................................................... 9-48
9-35
Basic Flow of an External Master Read Access ..................................................................... 9-50
9-36
Basic Flow of an External Master Write Access .................................................................... 9-51
9-37
Peripheral Mode: External Master Reads from MPC561/MPC563 (Two Wait States) ......... 9-52
9-38
Peripheral Mode: External Master Writes to MPC561/MPC563 (Two Wait States)............ 9-53
9-39
Flow of Retry of External Master Read Access ..................................................................... 9-54
9-40
Retry of External Master Access (Internal Arbiter)................................................................ 9-55
9-41
Instruction Show Cycle Transaction....................................................................................... 9-57
9-42
Data Show Cycle Transaction................................................................................................. 9-58
10-1
Memory Controller Function within the USIU....................................................................... 10-1
10-2
Memory Controller Block Diagram........................................................................................ 10-2
10-3
MPC561/MPC563 Simple System Configuration .................................................................. 10-3
10-4
Bank Base Address and Match Structure ............................................................................... 10-4
10-5
A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts) ............................................. 10-9
MPC561/MPC563 Reference Manual, Rev. 1.2
xliv
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
10-6
4 Beat Burst Read with Short Setup Time (Zero Wait State) ............................................... 10-10
10-7
GPCM–Memory Devices Interface ...................................................................................... 10-12
10-8
Memory Devices Interface Basic Timing (ACS = 00, TRLX = 0)....................................... 10-13
10-9
Peripheral Devices Interface ................................................................................................. 10-13
10-10 Peripheral Devices Basic Timing (ACS = 11, TRLX = 0) ................................................... 10-14
10-11 Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1).................................... 10-15
10-12 Relaxed Timing — Write Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1) ................ 10-16
10-13 Relaxed Timing — Write Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1) ................ 10-17
10-14 Relaxed Timing — Write Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1.................. 10-18
10-15 Consecutive Accesses (Write After Read, EHTR = 0) ......................................................... 10-19
10-16 Consecutive Accesses (Write After Read, EHTR = 1) ......................................................... 10-20
10-17 Consecutive Accesses
(Read After Read From Different Banks, EHTR = 1) .......................................................... 10-21
10-18 Consecutive Accesses (Read After Read from Same Bank, EHTR = 1).............................. 10-22
10-19 Aliasing Phenomenon Illustration ........................................................................................ 10-26
10-20 Synchronous External Master
Configuration for GPCM-Handled Memory Devices .......................................................... 10-29
10-21 Synchronous External Master Basic Access (GPCM Controlled)........................................ 10-30
10-22 Memory Controller Status Register (MSTAT) ..................................................................... 10-32
10-23 Memory Controller Base Registers 0–3 (BR0–BR3) ........................................................... 10-32
10-24 Memory Controller Option Registers 1–3 (OR0–OR3) ....................................................... 10-34
10-25 Dual-Mapping Base Register (DMBR) ................................................................................ 10-36
10-26 Dual-Mapping Option Register (DMOR)............................................................................. 10-37
11-1
L2U Bus Interface Block Diagram ......................................................................................... 11-3
11-2
DMPU Basic Functional Diagram .......................................................................................... 11-5
11-3
Region Base Address Example............................................................................................... 11-7
11-4
L2U Module Configuration Register (L2U_MCR) .............................................................. 11-14
11-5
L2U Region x Base Address Register (L2U_RBAx) ........................................................... 11-14
11-6
L2U Region X Attribute Register (L2U_RAx) .................................................................... 11-15
11-7
L2U Global Region Attribute Register (L2U_GRA) ........................................................... 11-16
12-1
UIMB Interface Module Block Diagram................................................................................ 12-2
12-2
IMB3 Clock – Full-Speed IMB3 Bus ..................................................................................... 12-3
12-3
IMB3 Clock – Half-Speed IMB3 Bus .................................................................................... 12-3
12-4
Interrupt Synchronizer Signal Flow........................................................................................ 12-4
12-5
Time-Multiplexing Protocol for IRQ Signals ......................................................................... 12-5
12-6
Interrupt Synchronizer Block Diagram................................................................................... 12-6
12-7
UIMB Module Configuration Register (UMCR) ................................................................... 12-7
12-8
Pending Interrupt Request Register (UIPEND)...................................................................... 12-9
13-1
QADC64E Block Diagram ..................................................................................................... 13-1
13-2
QADC64E Conversion Queue Operation............................................................................... 13-5
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xlv
Figures
Figure
Page
Title
Number
Number
13-3
Example of External Multiplexing ......................................................................................... 13-6
13-4
Module Configuration Register (QADCMCR) ...................................................................... 13-8
13-5
QADC Interrupt Register (QADCINT) ................................................................................ 13-12
13-6
Interrupt Levels on IRQ with ILBS ...................................................................................... 13-13
13-7
Port x Data Register (PORTQA and PORTQB).................................................................. 13-13
13-8
Port A Data Direction Register (DDRQA) .......................................................................... 13-14
13-9
Control Register 0 (QACR0) ................................................................................................ 13-15
13-10
Control Register 1 (QACR1) ............................................................................................... 13-16
13-11 Control Register 2 (QACR2) ................................................................................................ 13-18
13-12 Status Register 0 (QASR0) ................................................................................................... 13-21
13-13 QADC64E Queue Status Transition ..................................................................................... 13-26
13-14 Status Register 1 (QASR1) ................................................................................................... 13-27
13-15 QADC64E Conversion Queue Operation............................................................................. 13-28
13-16 Conversion Command Word Table (CCW) ......................................................................... 13-30
13-17 Right Justified, Unsigned Result Format (RJURR).............................................................. 13-33
13-18 Left Justified, Signed Result Format (LJSRR) ..................................................................... 13-33
13-19 Left Justified, Unsigned Result Register (LJURR) .............................................................. 13-33
13-20 QADC64E Analog Subsystem Block Diagram .................................................................... 13-34
13-21 Conversion Timing ............................................................................................................... 13-35
13-22 Bypass Mode Conversion Timing ........................................................................................ 13-36
13-23 QADC64E Queue Operation with Pause.............................................................................. 13-39
13-24 QADC64E Clock Subsystem Functions ............................................................................... 13-48
13-25 QADC64E Clock Programmability Examples ..................................................................... 13-50
13-26 Bus Cycle Accesses .............................................................................................................. 13-53
13-27 CCW Priority Situation 1...................................................................................................... 13-56
13-28 CCW Priority Situation 2...................................................................................................... 13-56
13-29 CCW Priority Situation 3...................................................................................................... 13-57
13-30 CCW Priority Situation 4...................................................................................................... 13-57
13-31 CCW Priority Situation 5...................................................................................................... 13-58
13-32 CCW Priority Situation 6...................................................................................................... 13-58
13-33 CCW Priority Situation 7...................................................................................................... 13-59
13-34 CCW Priority Situation 8...................................................................................................... 13-59
13-35 CCW Priority Situation 9...................................................................................................... 13-60
13-36 CCW Priority Situation 10.................................................................................................... 13-60
13-37 CCW Priority Situation 11.................................................................................................... 13-61
13-38 CCW Freeze Situation 12 ..................................................................................................... 13-61
13-39 CCW Freeze Situation 13 ..................................................................................................... 13-62
13-40 CCW Freeze Situation 14 ..................................................................................................... 13-62
13-41 CCW Freeze Situation 15 ..................................................................................................... 13-62
13-42 CCW Freeze Situation 16 ..................................................................................................... 13-62
MPC561/MPC563 Reference Manual, Rev. 1.2
xlvi
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
13-43 CCW Freeze Situation 17 ..................................................................................................... 13-63
13-44 CCW Freeze Situation 18 ..................................................................................................... 13-63
13-45 CCW Freeze Situation 19 ..................................................................................................... 13-63
13-46 External Trigger Mode (Positive Edge) Timing with Pause................................................. 13-64
13-47 Gated Mode, Single-Scan Timing ........................................................................................ 13-65
13-48 Gated Mode, Continuous Scan Timing................................................................................. 13-66
13-49 Equivalent Analog Input Circuitry ....................................................................................... 13-68
13-50 Errors Resulting from Clipping ............................................................................................ 13-69
13-51 Star-Ground at the Point of Power Supply Origin ................................................................ 13-71
13-52 Electrical Model of an A/D Input Signal .............................................................................. 13-72
13-53 External Multiplexing of Analog Signal Sources ................................................................. 13-74
13-54 Input Signal Subjected to Negative Stress ............................................................................ 13-76
13-55 Input Signal Subjected to Positive Stress ............................................................................. 13-77
14-1
QADC64E Block Diagram ..................................................................................................... 14-1
14-2
CCW Queue and Result Table Block Diagram ...................................................................... 14-5
14-3
Example of External Multiplexing ......................................................................................... 14-6
14-4
Module Configuration Register (QADCMCR) ...................................................................... 14-8
14-5
QADC Interrupt Register (QADCINT) ................................................................................ 14-12
14-6
Interrupt Levels on IRQ with ILBS ...................................................................................... 14-12
14-7
Port A Data Register (PORTQA), Port B Data Register (PORTQB)................................... 14-13
14-8
Portx Data Direction Register (DDRQA and DDRQB) ...................................................... 14-14
14-9
Control Register 0 (QACR0) ................................................................................................ 14-14
14-10
Control Register 1 (QACR1) ............................................................................................... 14-16
14-11 Control Register 2 (QACR2) ................................................................................................ 14-18
14-12 Status Register 0 (QASR0) ................................................................................................... 14-22
14-13 Queue Status Transition........................................................................................................ 14-27
14-14 Status Register 1 (QASR1) ................................................................................................... 14-28
14-15 QADC64E Conversion Queue Operation............................................................................. 14-29
14-16 Conversion Command Word Table (CCW) ......................................................................... 14-31
14-17 Right Justified, Unsigned Result Format (RJURR).............................................................. 14-35
14-18 Left Justified, Signed Result Format (LJSRR) ..................................................................... 14-35
14-19 Left Justified, Unsigned Result Register (LJURR) .............................................................. 14-35
14-20 QADC64E Analog Subsystem Block Diagram .................................................................... 14-36
14-21 Conversion Timing ............................................................................................................... 14-37
14-22 QADC64E Queue Operation With Pause ............................................................................. 14-40
14-23 QADC64E Clock Subsystem Functions ............................................................................... 14-49
14-24 Bus Cycle Accesses .............................................................................................................. 14-52
14-25 CCW Priority Situation 1...................................................................................................... 14-55
14-26 CCW Priority Situation 2...................................................................................................... 14-55
14-27 CCW Priority Situation 3...................................................................................................... 14-56
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xlvii
Figures
Figure
Page
Title
Number
Number
14-28 CCW Priority Situation 4...................................................................................................... 14-56
14-29 CCW Priority Situation 5...................................................................................................... 14-57
14-30 CCW Priority Situation 6...................................................................................................... 14-57
14-31 CCW Priority Situation 7...................................................................................................... 14-58
14-32 CCW Priority Situation 8...................................................................................................... 14-58
14-33 CCW Priority Situation 9...................................................................................................... 14-59
14-34 CCW Priority Situation 10.................................................................................................... 14-59
14-35 CCW Priority Situation 11.................................................................................................... 14-60
14-36 CCW Freeze Situation 12 ..................................................................................................... 14-60
14-37 CCW Freeze Situation 13 ..................................................................................................... 14-61
14-38 CCW Freeze Situation 14 ..................................................................................................... 14-61
14-39 CCW Freeze Situation 15 ..................................................................................................... 14-61
14-40 CCW Freeze Situation 16 ..................................................................................................... 14-61
14-41 CCW Freeze Situation 17 ..................................................................................................... 14-62
14-42 CCW Freeze Situation 18 ..................................................................................................... 14-62
14-43 CCW Freeze Situation 19 ..................................................................................................... 14-62
14-44 External Trigger Mode (Positive Edge) Timing with Pause................................................. 14-63
14-45 Gated Mode, Single-Scan Timing ........................................................................................ 14-64
14-46 Gated Mode, Continuous Scan Timing................................................................................. 14-65
14-47 Equivalent Analog Input Circuitry ....................................................................................... 14-66
14-48 Errors Resulting from Clipping ............................................................................................ 14-67
14-49 Star-Ground at the Point of Power Supply Origin ................................................................ 14-69
14-50 Electrical Model of an A/D Input Signal .............................................................................. 14-71
14-51 External Multiplexing of Analog Signal Sources ................................................................. 14-72
14-52 Input Signal Subjected to Negative Stress ............................................................................ 14-74
14-53 Input Signal Subjected to Positive Stress ............................................................................. 14-75
15-1
QSMCM Block Diagram ........................................................................................................ 15-2
15-2
QSMCM Interrupt Levels ....................................................................................................... 15-7
15-3
Interrupt Hardware Block Diagram ........................................................................................ 15-8
15-4
QSMCM Configuration Register (QSMCMMCR) ................................................................ 15-8
15-5
QSM2 Dual SCI Interrupt Level Register (QDSCI_IL) ......................................................... 15-9
15-6
QSPI_IL — QSPI Interrupt Level Register .......................................................................... 15-10
15-7
PORTQS — Port QS Data Register ..................................................................................... 15-12
15-8
PORTQS Pin Assignment Register (PQSPAR).................................................................... 15-13
15-9
PORTQS Data Direction Register (DDRQS) ....................................................................... 15-14
15-10 QSPI Block Diagram ............................................................................................................ 15-15
15-11 QSPI Control Register 0 (SPCR0)........................................................................................ 15-17
15-12 SPCR1 — QSPI Control Register ........................................................................................ 15-19
15-13 SPCR2 — QSPI Control Register 2 ..................................................................................... 15-20
15-14 SPCR3 — QSPI Control Register 3 ..................................................................................... 15-21
MPC561/MPC563 Reference Manual, Rev. 1.2
xlviii
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
15-15 QSPI Status Register (SPSR)................................................................................................ 15-21
15-16 QSPI RAM............................................................................................................................ 15-23
15-17 CR[0:F] — Command RAM 0x30 51C0, 0x30 51DF.......................................................... 15-24
15-18 Flowchart of QSPI Initialization Operation.......................................................................... 15-28
15-19 Flowchart of QSPI Master Operation (Part 1) ...................................................................... 15-29
15-20 Flowchart of QSPI Master Operation (Part 2) ...................................................................... 15-30
15-21 Flowchart of QSPI Master Operation (Part 3) ...................................................................... 15-31
15-22 Flowchart of QSPI Slave Operation (Part 1) ........................................................................ 15-32
15-23 Flowchart of QSPI Slave Operation (Part 2) ........................................................................ 15-33
15-24 SCI Transmitter Block Diagram ........................................................................................... 15-43
15-25 SCI Receiver Block Diagram ............................................................................................... 15-44
15-26 SCCxR0 — SCI Control Register 0 ..................................................................................... 15-46
15-27 SCI Control Register 1 (SCCxR1)........................................................................................ 15-47
15-28 SCIx Status Register (SCxSR).............................................................................................. 15-49
15-29 SCI Data Register (SCxDR) ................................................................................................. 15-51
15-30 Start Search Example............................................................................................................ 15-57
15-31 QSCI1 Control Register (QSCI1CR).................................................................................... 15-60
15-32 QSCI1 Status Register (QSCI1SR)....................................................................................... 15-61
15-33 Queue Transmitter Block Enhancements ............................................................................. 15-63
15-34 Queue Transmit Flow ........................................................................................................... 15-66
15-35 Queue Transmit Software Flow ............................................................................................ 15-66
15-36 Queue Transmit Example for 17 Data Bytes ........................................................................ 15-67
15-37 Queue Transmit Example for 25 Data Frames ..................................................................... 15-69
15-38 Queue Receiver Block Enhancements .................................................................................. 15-70
15-39 Queue Receive Flow ............................................................................................................. 15-73
15-40 Queue Receive Software Flow ............................................................................................. 15-74
15-41 Queue Receive Example for 17 Data Bytes.......................................................................... 15-75
16-1
TouCAN Block Diagram ........................................................................................................ 16-1
16-2
Typical CAN Network............................................................................................................ 16-3
16-3
Extended ID Message Buffer Structure .................................................................................. 16-4
16-4
Standard ID Message Buffer Structure ................................................................................... 16-4
16-5
Relationship between System Clock and CAN Bit Segments ................................................ 16-9
16-6
CAN Controller State Diagram............................................................................................. 16-12
16-7
Interrupt Levels on IRQ with ILBS ...................................................................................... 16-21
16-8
TouCAN Message Buffer Memory Map .............................................................................. 16-24
16-9
TouCAN Module Configuration Register (CANMCR) ....................................................... 16-25
16-10 TouCAN Interrupt Configuration Register (CANICR) ........................................................ 16-27
16-11 Control Register 0 (CANCTRL0)......................................................................................... 16-27
16-12 Control Register 1 (CANCTRL1)......................................................................................... 16-28
16-13 Prescaler Divide Register...................................................................................................... 16-29
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
xlix
Figures
Figure
Page
Title
Number
Number
16-14 Control Register 2 (CANCTRL2)......................................................................................... 16-30
16-15 Free Running Timer Register (TIMER) ............................................................................... 16-31
16-16 Receive Global Mask Register: High (RXGMSKHI), Low (RXGMSKLO) ....................... 16-31
16-17 Receive Buffer 14 Mask Registers: High (RX14MSKHI), Low (RX14MSKLO)............... 16-32
16-18 Receive Buffer 15 Mask Registers: High (RX15MSKHI), Low (RX15MSKLO)............... 16-33
16-19 Error and Status Register (ESTAT) ...................................................................................... 16-33
16-20 Interrupt Mask Register (IMASK)........................................................................................ 16-35
16-21 Interrupt Flag Register (IFLAG)........................................................................................... 16-36
16-22 Receive Error Counter (RXECTR), Transmit Error Counter (TXECTR)............................ 16-36
17-1
MPC561/MPC563 MIOS14 Block Diagram .......................................................................... 17-2
17-2
MIOS14 Memory Map ......................................................................................................... 17-13
17-3
MBISM Registers ................................................................................................................. 17-13
17-4
Test and Signal Control Register (MIOS14TPCR) .............................................................. 17-14
17-5
Vector Register (MIOS14VECT) ......................................................................................... 17-14
17-6
MIOS14 Module/Version Number Register (MIOS14VNR)............................................... 17-14
17-7
Module Configuration Register (MIOS14MCR).................................................................. 17-15
17-8
MCPSM Block Diagram....................................................................................................... 17-16
17-9
MCPSM Status/Control Register (MCPSMSCR) ................................................................ 17-18
17-10 MMCSM Block Diagram ..................................................................................................... 17-20
17-11 MMCSM Modulus Up-Counter............................................................................................ 17-20
17-12 MMCSM Up-Counter Register (MMCSMCNT) ................................................................. 17-23
17-13 MMCSM Modulus Latch Register (MMCSMML) .............................................................. 17-24
17-14 MMCSM Status/Control Register (MMCSMSCR).............................................................. 17-24
17-15 MDASM Block Diagram...................................................................................................... 17-27
17-16 Input Pulse Width Measurement Example ........................................................................... 17-31
17-17 Input Period Measurement Example..................................................................................... 17-32
17-18 MDASM Input Capture Example ......................................................................................... 17-33
17-19 Single Shot Output Pulse Example ....................................................................................... 17-35
17-20 Single Shot Output Transition Example ............................................................................... 17-36
17-21 MDASM Output Pulse Width Modulation Example............................................................ 17-37
17-22 MDASM Data A Register (MDASMAR) ............................................................................ 17-41
17-23 MDASM DataB Register (MDASMBR).............................................................................. 17-42
17-24 MDASM Status/Control Register (MDASMSCR)............................................................... 17-44
17-25 MPWMSM Block Diagram .................................................................................................. 17-47
17-26 MPWMSM Period Register (MPWMPERR) ....................................................................... 17-57
17-27 MPWMSM Pulse Width Register (MPWMPULR).............................................................. 17-58
17-28 MPWMSM Counter Register (MPWMCNTR) .................................................................... 17-58
17-29 MPWMSM Status/Control Register (MPWMSCR)............................................................. 17-58
17-30 MPIOSM 1-Bit Block Diagram ............................................................................................ 17-60
17-31 MPIOSM — Register Organization ..................................................................................... 17-62
MPC561/MPC563 Reference Manual, Rev. 1.2
l
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
17-32 MPIOSM Data Register (MPIOSMDR)............................................................................... 17-62
17-33 MPIOSM Data Direction Register (MPIOSMDDR)............................................................ 17-63
17-34 MIOS14 Interrupt Structure.................................................................................................. 17-64
17-35 Interrupt Status Register (MIOS14SR0)............................................................................... 17-66
17-36 Interrupt Enable Register (MIOS14ER0) ............................................................................. 17-66
17-37 Interrupt Request Pending Register (MIOS14RPR0) ........................................................... 17-67
17-38 Interrupt Status Register (MIOS14SR1)............................................................................... 17-67
17-39 Interrupt Enable Register (MIOS14ER1) ............................................................................. 17-68
17-40 Interrupt Request Pending Register (MIOS14RPR1) ........................................................... 17-68
17-41 MIOS14 Interrupt Level Register 0 (MIOS14LVL0)........................................................... 17-69
17-42 MIOS14 Interrupt Level Register 1 (MIOS14LVL1)........................................................... 17-70
17-43 MIOS14 Example: Double Capture Pulse Width Measurement .......................................... 17-71
17-44 MIOS14 Example: Double Capture Period Measurement ................................................... 17-72
17-45 MIOS14 Example: Double Edge Output Compare .............................................................. 17-73
17-46 MIOS14 Example: Pulse Width Modulation Output............................................................ 17-74
18-1
N-Signal I/O Compared with PPM I/O................................................................................... 18-2
18-2
Block Diagram of PPM Module ............................................................................................. 18-4
18-3
Internal Multiplexer Mechanism for Transmit Data............................................................... 18-5
18-4
Internal Multiplexer Mechanism for Received Data .............................................................. 18-5
18-5
PPM Clocks and Serial Data Signals ...................................................................................... 18-6
18-6
One Transmit and Receive Cycle in SPI Mode ...................................................................... 18-7
18-7
Examples Of Several TCLK Frequencies and Sample Rates ................................................. 18-8
18-8
Module Configuration Register (PPMMCR)........................................................................ 18-10
18-9
PPM Control Register (PPMPCR)........................................................................................ 18-12
18-10 Set ENRX While ENTX = 1................................................................................................. 18-14
18-11 Set ENTX while ENRX = 1.................................................................................................. 18-14
18-12 SPI Transfer Format with CP = 0 ......................................................................................... 18-15
18-13 SPI Transfer Format with CP = 1 ......................................................................................... 18-15
18-14 Transmit Configuration Register 1 (TX_CONFIG_1) ......................................................... 18-16
18-15 Transmit Configuration Register 2 (TX_CONFIG_2) ......................................................... 18-16
18-16 Receive Configuration Register 1 (RX_CONFIG_1)........................................................... 18-16
18-17 Receive Configuration Register 2 (RX_CONFIG_2)........................................................... 18-17
18-18 Receive Data Register (RX_DATA) .................................................................................... 18-18
18-19 Receive Shifter Register (RX_SHIFTER) ............................................................................ 18-18
18-20 Transmit Data Register (TX_DATA) ................................................................................... 18-18
18-21 General Purpose Data Out Register (GPDO) ....................................................................... 18-19
18-22 General Purpose Data In Register (GPDI)............................................................................ 18-19
18-23 Short Register (SHORT_REG)............................................................................................. 18-19
18-24 Example of TouCAN Internal Short with SH_TCAN = 0b110............................................ 18-21
18-25 Short Between TPU Channels .............................................................................................. 18-22
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
li
Figures
Figure
Page
Title
Number
Number
18-26 Short Channels Register (SHORT_CH_REG) ..................................................................... 18-23
18-27 Scale Transmit Clock Register (SCALE_TCLK_REG)....................................................... 18-24
19-1
TPU3 Block Diagram ............................................................................................................. 19-1
19-2
TPU3 Interrupt Levels ............................................................................................................ 19-5
19-3
TCR1 Prescaler Control.......................................................................................................... 19-7
19-4
TCR2 Prescaler Control.......................................................................................................... 19-8
19-5
TPUMCR — TPU Module Configuration Register ............................................................. 19-11
19-6
DSCR — Development Support Control Register ............................................................... 19-12
19-7
DSSR — Development Support Status Register .................................................................. 19-14
19-8
TICR — TPU3 Interrupt Configuration Register ................................................................. 19-14
19-9
CIER — Channel Interrupt Enable Register......................................................................... 19-15
19-10 CFSR0 — Channel Function Select Register 0 .................................................................... 19-16
19-11 CFSR1 — Channel Function Select Register 1 .................................................................... 19-16
19-12 CFSR2 — Channel Function Select Register 2 .................................................................... 19-16
19-13 CFSR3 — Channel Function Select Register 3 .................................................................... 19-16
19-14 HSQR0 — Host Sequence Register 0................................................................................... 19-17
19-15 HSQR1 — Host Sequence Register 1................................................................................... 19-17
19-16 HSRR0 — Host Service Request Register 0 ........................................................................ 19-17
19-17 HSRR1 — Host Service Request Register 1 ........................................................................ 19-17
19-18 CPR0 — Channel Priority Register 0 ................................................................................... 19-18
19-19 CPR1 — Channel Priority Register 1 ................................................................................... 19-18
19-20 CISR — Channel Interrupt Status Register .......................................................................... 19-19
19-21 TPUMCR2 — TPU Module Configuration Register 2 ........................................................ 19-19
19-22 TPUMCR3 — TPU Module Configuration Register 3 ........................................................ 19-21
19-23 SIUTST — SIU Test Register .............................................................................................. 19-22
20-1
DPTRAM Configuration ........................................................................................................ 20-2
20-2
DPTRAM Memory Map......................................................................................................... 20-3
20-3
DPT Module Configuration Register (DPTMCR).................................................................. 20-3
20-4
RAM Array Base Address Register (RAMBAR)................................................................... 20-5
20-5
Multiple Input Signature Register High (MISRH) ................................................................. 20-5
20-6
Multiple Input Signature Register Low (MISRL) .................................................................. 20-6
20-7
MISC Counter (MISCNT) ...................................................................................................... 20-6
21-1
Block Diagram for a 512 Kbyte UC3F Module Configuration .............................................. 21-2
21-2
UC3F EEPROM Configuration Register (UC3FMCR) ......................................................... 21-5
21-3
UC3FMCRE— UC3F EEPROM Extended Configuration Register ..................................... 21-9
21-4
UC3F EEPROM High Voltage Control Register (UC3FCTL) ............................................ 21-11
21-5
PEGOOD Valid Time ........................................................................................................... 21-14
21-6
Shadow Information ............................................................................................................. 21-16
21-7
Hard Reset Configuration Word (UC3FCFIG) .................................................................... 21-16
21-8
512-Kbyte Array Configuration............................................................................................ 21-19
MPC561/MPC563 Reference Manual, Rev. 1.2
lii
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
21-9
Program State Diagram......................................................................................................... 21-23
21-10 Erase State Diagram.............................................................................................................. 21-27
21-11 Censorship States and Transitions ........................................................................................ 21-33
22-1
System Block Diagram ........................................................................................................... 22-2
22-2
MPC561/MPC563 Memory Map with CALRAM Address Ranges ...................................... 22-3
22-3
Standby Power Supply Configuration for CALRAM Array .................................................. 22-4
22-4
CALRAM Array ..................................................................................................................... 22-7
22-5
CALRAM Module Overlay Map of Flash (CLPS = 0) .......................................................... 22-8
22-6
CALRAM Address Map (CLPS = 0) ..................................................................................... 22-9
22-7
CALRAM Module Overlay Map of Flash (CLPS = 1) ........................................................ 22-10
22-8
CALRAM Address Map (CLPS = 1) ................................................................................... 22-11
22-9
CALRAM Module Configuration Register (CRAMMCR).................................................. 22-13
22-10 CALRAM Region Base Address Register (CRAM_RBAx) ................................................ 22-16
22-11 CALRAM Overlay Configuration Register (CRAM_OVLCR)........................................... 22-17
22-12 CALRAM Ownership Trace Register (CRAM_OTR) ......................................................... 22-18
23-1
Watchpoint and Breakpoint Support in the CPU.................................................................... 23-9
23-2
Partially Supported Watchpoint/Breakpoint Example.......................................................... 23-13
23-3
Instruction Support General Structure .................................................................................. 23-15
23-4
Load/Store Support General Structure.................................................................................. 23-18
23-5
Functional Diagram of MPC561/MPC563 Debug Mode Support ....................................... 23-21
23-6
Debug Mode Logic ............................................................................................................... 23-23
23-7
BDM Mode Selection ........................................................................................................... 23-24
23-8
Debug Mode Reset Configuration ........................................................................................ 23-25
23-9
Asynchronous Clock Serial Communications ...................................................................... 23-32
23-10 Synchronous Self Clock Serial Communication .................................................................. 23-32
23-11 Enabling Clock Mode Following Reset................................................................................ 23-33
23-12 Download Procedure Code Example .................................................................................... 23-37
23-13 Slow Download Procedure Loop .......................................................................................... 23-38
23-14 Fast Download Procedure Loop ........................................................................................... 23-38
23-15 Comparator A–D Value Register (CMPA–CMPD).............................................................. 23-41
23-16 Exception Cause Register (ECR).......................................................................................... 23-42
23-17 Debug Enable Register (DER).............................................................................................. 23-43
23-18
Breakpoint Counter A Value and Control Register (COUNTA)......................................... 23-45
23-19 Breakpoint Counter B Value and Control Register (COUNTB) .......................................... 23-46
23-20 Comparator E–F Value Registers (CMPE–CMPF) .............................................................. 23-46
23-21 Comparator G–H Value Registers (CMPG–CMPH)............................................................ 23-47
23-22 L-Bus Support Control Register 1 (LCTRL) ........................................................................ 23-47
23-23 L-Bus Support Control Register 2 (LCTRL2) ...................................................................... 23-48
23-24 I-Bus Support Control Register (ICTRL) ............................................................................. 23-51
23-25 Breakpoint Address Register (BAR) .................................................................................... 23-53
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
liii
Figures
Figure
Page
Title
Number
Number
23-26 Development Port Data Register (DPDR) ............................................................................ 23-53
24-1
READI Functional Block Diagram......................................................................................... 24-3
24-2
READI Ownership Trace Register (OTR).............................................................................. 24-9
24-3
READI Device ID Register .................................................................................................. 24-10
24-4
READI Development Control (DC) Register ....................................................................... 24-10
24-5
READI Mode Control (MC) Register .................................................................................. 24-12
24-6
READI User Base Address Register .................................................................................... 24-13
24-7
READI Read/Write Access Register .................................................................................... 24-14
24-8
READI Upload/Download Information Register ................................................................. 24-16
24-9
RWD Field Configuration .................................................................................................... 24-17
24-10 READI Data Trace Attributes 1 Register (DTA1)
READI Data Trace Attributes 2 Register (DTA2) ............................................................... 24-17
24-11 Functional Diagram of Signal Interface................................................................................ 24-22
24-12 Auxiliary Signal Packet Structure for Program Trace Indirect
Branch Message .................................................................................................................... 24-23
24-13 MSEI/MSEO Transfers......................................................................................................... 24-24
24-14 Transmission Sequence of Messages.................................................................................... 24-32
24-15 READI Module Enabled....................................................................................................... 24-34
24-16 Enabling Program Trace Out of System Reset ..................................................................... 24-36
24-17 READI Mode Selection ........................................................................................................ 24-36
24-18 READI Module Disabled...................................................................................................... 24-37
24-19 Direct Branch Message Format ............................................................................................ 24-38
24-20 Indirect Branch Message Format .......................................................................................... 24-39
24-21 Indirect Branch Message Format with Compressed Code.................................................... 24-39
24-22 Bit Pointer Format with Compressed Code .......................................................................... 24-39
24-23 Program Trace Correction Message Format ......................................................................... 24-42
24-24 Direct Branch Synchronization Message Format (PTSM = 0)............................................. 24-44
24-25 Direct Branch Synchronization Message Format (PTSM = 1)............................................. 24-44
24-26 Indirect Branch Synchronization Message Format (PTSM = 0) .......................................... 24-44
24-27 Indirect Branch Synchronization Message Format (PTSM = 1) .......................................... 24-44
24-28 Direct Branch Synchronization Message Format with Compressed
Code (PTSM = 0).................................................................................................................. 24-45
24-29 Direct Branch Synchronization Message Format with Compressed
Code (PTSM = 1).................................................................................................................. 24-45
24-30 Indirect Branch Synchronization Message Format with Compressed
Code (PTSM - 0)................................................................................................................... 24-45
24-31 Indirect Branch Synchronization Message Format with Compressed
Code (PTSM = 1).................................................................................................................. 24-45
24-32 Program Trace Full Message Format.................................................................................... 24-46
24-33 Relative Address Generation and Re-Creation ..................................................................... 24-47
MPC561/MPC563 Reference Manual, Rev. 1.2
liv
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
24-34 Error Message (Queue Overflow) Format ............................................................................ 24-47
24-35 Direct Branch Message ......................................................................................................... 24-49
24-36 Indirect Branch Message ...................................................................................................... 24-49
24-37 Indirect Branch Message with Compressed Code ................................................................ 24-49
24-38 Program Trace Correction Message ..................................................................................... 24-50
24-39 Error Message (Program/Data/Ownership Trace Overrun).................................................. 24-50
24-40 Direct Branch Synchronization Message.............................................................................. 24-50
24-41 Indirect Branch Synchronization Message ........................................................................... 24-51
24-42 Direct Branch Synchronization Message
with Compressed Code ......................................................................................................... 24-51
24-43 Indirect Branch Synchronization Message with Compressed Code ..................................... 24-51
24-44 Data Write Message Format ................................................................................................. 24-52
24-45 Data Read Message Format .................................................................................................. 24-53
24-46 Data Write Synchronization Message Format ...................................................................... 24-54
24-47 Data Read Synchronization Message Format ....................................................................... 24-54
24-48 Error Message (Queue Overflow) Format ............................................................................ 24-54
24-49 Data Trace Flow Diagram for Non-Pipelined Access .......................................................... 24-55
24-50 Date Write Message.............................................................................................................. 24-57
24-51 Data Read Message............................................................................................................... 24-58
24-52 Data Write Synchronization Message................................................................................... 24-58
24-53 Data Read Synchronization Message ................................................................................... 24-58
24-54 Error Message (Program/Data/Ownership Trace Overrun).................................................. 24-59
24-55 Target Ready Message.......................................................................................................... 24-59
24-56 Read Register Message ......................................................................................................... 24-59
24-57 Write Register Message ........................................................................................................ 24-60
24-58 Read/Write Response Message............................................................................................. 24-60
24-59 Read/Write Access Flow Diagram ....................................................................................... 24-61
24-60 Error Message (Read/Write Access Error) Format............................................................... 24-67
24-61 Error Message (Invalid Message) Format ............................................................................ 24-67
24-62 Error Message (Invalid Access Opcode) Format.................................................................. 24-67
24-63 Block Write Access .............................................................................................................. 24-69
24-64 Block Read Access ............................................................................................................... 24-70
24-65 Device Ready for Upload/Download Request Message....................................................... 24-70
24-66 Upload Request Message...................................................................................................... 24-71
24-67 Download Request Message ................................................................................................. 24-71
24-68 Upload/Download Information Message.............................................................................. 24-72
24-69 Error Message (Invalid Access Opcode) .............................................................................. 24-72
24-70 Watchpoint Message Format ................................................................................................ 24-73
24-71 Error Message (Watchpoint Overrun) Format...................................................................... 24-73
24-72 Watchpoint Message............................................................................................................. 24-74
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lv
Figures
Figure
Page
Title
Number
Number
24-73 Error Message (Watchpoint Overrun) .................................................................................. 24-74
24-74 Ownership Trace Message Format ....................................................................................... 24-75
24-75 Error Message Format .......................................................................................................... 24-75
24-76 Ownership Trace Message.................................................................................................... 24-76
24-77 Error Message (Program/Data/Ownership Trace Overrun).................................................. 24-76
24-78 RCPU Development Access Multiplexing between READI and BDM Signals .................. 24-77
24-79 DSDI Message Format.......................................................................................................... 24-78
24-80 DSDO Message Format ........................................................................................................ 24-78
24-81 BDM Status Message Format ............................................................................................... 24-79
24-82 Error Message (Invalid Message) Format ............................................................................ 24-79
24-83 RCPU Development Access Flow Diagram ......................................................................... 24-81
24-84 RCPU Development Access Timing Diagram — Debug Mode Entry Out-of-Reset........... 24-83
24-85 Transmission Sequence of DSDx Data Messages ................................................................ 24-83
24-86 Error Message (Invalid Message) ......................................................................................... 24-85
24-87 DSDI Data Message (Assert Non-Maskable Breakpoint) .................................................... 24-85
24-88 DSDI Data Message (CPU Instruction — rfi) ...................................................................... 24-85
24-89 DSDO Data Message (CPU Data Out) ................................................................................. 24-86
25-1
Pin Requirement on JTAG...................................................................................................... 25-1
25-2
Test Logic Block Diagram...................................................................................................... 25-3
25-3
JTAG Mode Selection ............................................................................................................ 25-3
25-4
TAP Controller State Machine ............................................................................................... 25-4
25-5
Bypass Register..................................................................................................................... 25-31
A-1
Instruction Compression Alternatives ..................................................................................... A-3
A-2
Addressing Instructions with Compressed Address ................................................................ A-4
A-3
Compressed Target Address Generation by Direct Branches.................................................. A-5
A-4
Branch Right Segment Compression #1 .................................................................................. A-7
A-5
Branch Right Segment Compression #2 .................................................................................. A-8
A-6
Global Bypass Instruction Layout ........................................................................................... A-8
A-7
CLASS_1 Instruction Layout .................................................................................................. A-9
A-8
CLASS_2 Instruction Layout .................................................................................................. A-9
A-9
CLASS_3 Instruction Layout ................................................................................................ A-10
A-10
CLASS_4 Instruction Layout ................................................................................................ A-11
A-11
Code Compression Process.................................................................................................... A-12
A-12
Code Decompression Process ................................................................................................ A-13
A-13
I-Bus Support Control Register (ICTRL) .............................................................................. A-16
A-14
Decompressor Class Configuration Registers1 (DCCRx) ..................................................... A-19
C-1
MPC561/MPC563 Power Distribution Diagram — 2.6 V .......................................................C-3
C-2
Power Distribution Diagram — 5 V and Analog .....................................................................C-3
C-3
Crystal Oscillator Circuit ..........................................................................................................C-4
C-4
RC Filter Example ....................................................................................................................C-5
MPC561/MPC563 Reference Manual, Rev. 1.2
lvi
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
C-5
Bypass Capacitors Example (Alternative) ................................................................................C-5
C-6
RC Filter Example ....................................................................................................................C-6
C-7
LC Filter Example (Alternative)...............................................................................................C-6
C-8
PLL Off-Chip Capacitor Example ............................................................................................C-7
C-9
IRAMSTBY Regulator Circuit .................................................................................................C-8
D-1
TPU3 Memory Map................................................................................................................. D-1
D-2
PTA Parameters ....................................................................................................................... D-4
D-3
QOM Parameters ..................................................................................................................... D-6
D-4
TSM Parameters — Master Mode ........................................................................................... D-8
D-5
TSM Parameters — Slave Mode ............................................................................................. D-9
D-6
FQM Parameters .................................................................................................................... D-11
D-7
UART Transmitter Parameters .............................................................................................. D-13
D-8
UART Receiver Parameters................................................................................................... D-14
D-9
NITC Parameters ................................................................................................................... D-16
D-10
COMM Parameters ................................................................................................................ D-18
D-10
COMM Parameters (continued)............................................................................................. D-20
D-11
HALLD Parameters ............................................................................................................... D-21
D-12
MCPWM Parameters — Master Mode ................................................................................. D-23
D-13
MCPWM Parameters — Slave Edge-Aligned Mode ............................................................ D-24
D-14
MCPWM Parameters — Slave Ch A Non-Inverted Center-Aligned Mode.......................... D-26
D-15
MCPWM Parameters — Slave Ch B Non-Inverted Center-Aligned Mode .......................... D-27
D-16
MCPWM Parameters — Slave Ch A Inverted Center-Aligned Mode .................................. D-28
D-17
MCPWM Parameters — Slave Ch B Inverted Center-Aligned Mode .................................. D-29
D-18
MULTI Parameters — FRINC .............................................................................................. D-31
D-19
MULTI Parameters — FREDEC........................................................................................... D-32
D-20
MULTI Parameters — SPEED.............................................................................................. D-33
D-21
MULTI Parameters — PWM_IN .......................................................................................... D-34
D-22
FQD Parameters — Primary Channel ................................................................................... D-36
D-23
FQD Parameters — Secondary Channel ............................................................................... D-37
D-24
PPWA Parameters.................................................................................................................. D-39
D-25
ID Parameters ........................................................................................................................ D-41
D-26
OC Parameters ....................................................................................................................... D-43
D-27
PWM Parameters ................................................................................................................... D-45
D-28
DIO Parameters...................................................................................................................... D-47
D-29
SPWM Parameters ................................................................................................................. D-49
D-30
RWTPIN Parameters ............................................................................................................. D-52
D-31
Two Possible SIOP Configurations ....................................................................................... D-53
D-32
SIOP Parameters .................................................................................................................... D-55
D-33
SIOP Function Data Transition Example .............................................................................. D-59
F-1
Option A Power-Up Sequence Without Keep-Alive Supply.................................................. F-14
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lvii
Figures
Figure
Page
Title
Number
Number
F-2
Option A Power-Up Sequence With Keep-Alive Supply....................................................... F-14
F-3
Option A Power-Down Sequence Without Keep-Alive Supply............................................. F-15
F-4
Option A Power-Down Sequence With Keep-Alive Supply.................................................. F-15
F-5
Option B Power-Up Sequence Without Keep-Alive Supply.................................................. F-16
F-6
Option B Power-Up Sequence With Keep-Alive Supply ....................................................... F-16
F-7
Option B Power-Down Sequence Without Keep-Alive Supply ............................................. F-17
F-8
Option B Power-Down Sequence with Keep-Alive Supply ................................................... F-17
F-9
Generic Timing Examples ...................................................................................................... F-19
F-10
CLKOUT Pin Timing ............................................................................................................. F-27
F-11
Synchronous Output Signals Timing ...................................................................................... F-28
F-12
Predischarge Timing ............................................................................................................... F-29
F-13
Synchronous Active Pull-Up And Open Drain
Outputs Signals Timing .......................................................................................................... F-30
F-14
Synchronous Input Signals Timing......................................................................................... F-31
F-15
Input Data Timing In Normal Case ........................................................................................ F-32
F-16
External Bus Read Timing (GPCM Controlled – ACS = ‘00’).............................................. F-33
F-17
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’).......................... F-34
F-18
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’).......................... F-35
F-19
External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’).... F-36
F-20
Address Show Cycle Bus Timing ........................................................................................... F-36
F-21
Address and Data Show Cycle Bus Timing............................................................................ F-37
F-22
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘0’) ....................... F-38
F-23
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘1’) ....................... F-39
F-24
External Bus Write Timing (GPCM Controlled – TRLX = ‘1’, CSNT = ‘1’) ....................... F-40
F-25
External Master Read From Internal Registers Timing.......................................................... F-41
F-26
External Master Write To Internal Registers Timing ............................................................. F-42
F-27
Interrupt Detection Timing for External Edge Sensitive Lines .............................................. F-43
F-28
Debug Port Clock Input Timing ............................................................................................. F-44
F-29
Debug Port Timings................................................................................................................ F-44
F-30
Auxiliary Port Data Input Timing Diagram............................................................................ F-45
F-31
Auxiliary Port Data Output Timing Diagram ......................................................................... F-46
F-32
Enable Auxiliary From RSTI.................................................................................................. F-46
F-33
Disable Auxiliary From RSTI................................................................................................. F-46
F-34
Reset Timing – Configuration from Data Bus........................................................................ F-48
F-35
Reset Timing – Data Bus Weak Drive During Configuration................................................ F-49
F-36
Reset Timing – Debug Port Configuration ............................................................................. F-50
F-37
JTAG Test Clock Input Timing .............................................................................................. F-51
F-38
JTAG Test Access Port Timing Diagram ............................................................................... F-52
F-39
Boundary Scan (JTAG) Timing Diagram............................................................................... F-53
F-40
QSPI Timing – Master, CPHA = 0 ......................................................................................... F-58
MPC561/MPC563 Reference Manual, Rev. 1.2
lviii
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
F-41
QSPI Timing – Master, CPHA = 1 ......................................................................................... F-58
F-42
QSPI Timing – Slave, CPHA = 0 ........................................................................................... F-59
F-43
QSPI Timing – Slave, CPHA = 1 ........................................................................................... F-59
F-44
TPU3 Timing .......................................................................................................................... F-61
F-45
PPM_TCLK Timing ............................................................................................................... F-63
F-46
PPM Data Transfer Timing (SPI Mode)................................................................................. F-63
F-47
MCPSM Enable to VS_PCLK Pulse Timing Diagram .......................................................... F-64
F-48
MPWMSM Minimum Output Pulse Example Timing Diagram............................................ F-65
F-49
MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram .............................. F-66
F-50
MPWMSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ......................... F-66
F-51
MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram.............. F-66
F-52
MMCSM Minimum Input Pin (Either Load Or Clock) Timing Diagram .............................. F-67
F-53
MMCSM Clock Pin To Counter Bus Increment Timing Diagram ........................................ F-68
F-54
MMCSM Load Pin To Counter Bus Reload Timing Diagram............................................... F-68
F-55
MMCSM Counter Bus Reload To Interrupt Flag Setting Timing Diagram........................... F-68
F-56
MMCSM Prescaler Clock Select To Counter Bus Increment Timing Diagram .................... F-69
F-57
MDASM Minimum Input Pin Timing Diagram..................................................................... F-70
F-58
MDASM Input Pin To Counter Bus Capture Timing Diagram.............................................. F-70
F-59
MDASM Input Pin to MDASM Interrupt Flag Timing Diagram .......................................... F-70
F-60
MDASM Minimum Output Pulse Width Timing Diagram.................................................... F-71
F-61
Counter Bus to MDASM Output Pin Change Timing Diagram............................................. F-71
F-62
Counter Bus to MDASM Interrupt Flag Setting Timing Diagram ......................................... F-71
F-63
MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram ............................... F-72
F-64
MPC561/MPC563 Package Footprint (1 of 2) ....................................................................... F-84
F-65
MPC561/MPC563 Package Footprint (2 of 2) ....................................................................... F-85
F-66
MPC561/MPC563 Ball Map .................................................................................................. F-86
F-67
MPC561/MPC563 Ball Map (Black and White, page 1) ....................................................... F-87
F-68
MPC561/MPC563 Ball Map (Black and White, page 2) ....................................................... F-88
F-69
MPC561/MPC563 Ball Map (Black and White, page 3) ....................................................... F-89
F-70
MPC561/MPC563 Ball Map (Black and White, page 4) ....................................................... F-90
G-1
Option A Power-Up Sequence Without Keep-Alive Supply................................................. G-13
G-2
Option A Power-Up Sequence With Keep-Alive Supply...................................................... G-14
G-3
Option A Power-Down Sequence Without Keep-Alive Supply............................................ G-14
G-4
Option A Power-Down Sequence With Keep-Alive Supply................................................. G-15
G-5
Option B Power-Up Sequence Without Keep-Alive Supply................................................. G-16
G-6
Option B Power-Up Sequence With Keep-Alive Supply ...................................................... G-16
G-7
Option B Power-Down Sequence Without Keep-Alive Supply ............................................ G-17
G-8
Option B Power-Down Sequence with Keep-Alive Supply .................................................. G-17
G-9
Generic Timing Examples ..................................................................................................... G-19
G-10
CLKOUT Pin Timing ............................................................................................................ G-25
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lix
Figures
Figure
Page
Title
Number
Number
G-11
Synchronous Output Signals Timing ..................................................................................... G-26
G-12
Synchronous Active Pull-Up And Open Drain Outputs Signals Timing .............................. G-27
G-13
Synchronous Input Signals Timing........................................................................................ G-28
G-14
Input Data Timing In Normal Case ....................................................................................... G-29
G-15
External Bus Read Timing (GPCM Controlled – ACS = ‘00’)............................................. G-30
G-16
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’)......................... G-31
G-17
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’)......................... G-32
G-18
External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’)... G-33
G-19
Address Show Cycle Bus Timing .......................................................................................... G-34
G-20
Address and Data Show Cycle Bus Timing........................................................................... G-35
G-21
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘0’) ...................... G-36
G-22
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘1’) ...................... G-37
G-23
External Bus Write Timing (GPCM Controlled – TRLX = ‘1’, CSNT = ‘1’) ...................... G-38
G-24
External Master Read From Internal Registers Timing......................................................... G-39
G-25
External Master Write To Internal Registers Timing ............................................................ G-40
G-26
Interrupt Detection Timing for External Edge Sensitive Lines ............................................. G-41
G-27
Debug Port Clock Input Timing ............................................................................................ G-42
G-28
Debug Port Timings............................................................................................................... G-42
G-29
Auxiliary Port Data Input Timing Diagram........................................................................... G-43
G-30
Auxiliary Port Data Output Timing Diagram ........................................................................ G-43
G-31
Enable Auxiliary From RSTI................................................................................................. G-44
G-32
Disable Auxiliary From RSTI................................................................................................ G-44
G-33
Reset Timing – Configuration from Data Bus....................................................................... G-45
G-34
Reset Timing – Data Bus Weak Drive During Configuration............................................... G-46
G-35
Reset Timing – Debug Port Configuration ............................................................................ G-47
G-36
JTAG Test Clock Input Timing ............................................................................................. G-48
G-37
JTAG Test Access Port Timing Diagram .............................................................................. G-48
G-38
Boundary Scan (JTAG) Timing Diagram.............................................................................. G-49
G-39
QSPI Timing – Master, CPHA = 0 ........................................................................................ G-54
G-40
QSPI Timing – Master, CPHA = 1 ........................................................................................ G-54
G-41
QSPI Timing – Slave, CPHA = 0 .......................................................................................... G-55
G-42
QSPI Timing – Slave, CPHA = 1 .......................................................................................... G-55
G-43
TPU3 Timing ......................................................................................................................... G-57
G-44
PPM_TCLK Timing .............................................................................................................. G-59
G-45
PPM Data Transfer Timing (SPI Mode)................................................................................ G-59
G-46
MCPSM Enable to VS_PCLK Pulse Timing Diagram ......................................................... G-60
G-47
MPWMSM Minimum Output Pulse Example Timing Diagram........................................... G-61
G-48
MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ............................. G-61
G-49
MPWMSM Enable To MPWMO Output Pin Rising Edge Timing Diagram ....................... G-62
G-50
MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram............. G-62
MPC561/MPC563 Reference Manual, Rev. 1.2
lx
Freescale Semiconductor
Figures
Figure
Page
Title
Number
Number
G-51
MMCSM Minimum Input Pin (Either Load or Clock) Timing Diagram.............................. G-63
G-52
MMCSM Clock Pin to Counter Bus Increment Timing Diagram......................................... G-63
G-53
MMCSM Load Pin to Counter Bus Reload Timing Diagram ............................................... G-64
G-54
MMCSM Counter Bus Reload to Interrupt Flag Setting Timing Diagram ........................... G-64
G-55
MMCSM Prescaler Clock Select to Counter Bus Increment Timing Diagram..................... G-64
G-56
MDASM Minimum Input Pin Timing Diagram.................................................................... G-65
G-57
MDASM Input Pin To Counter Bus Capture Timing Diagram............................................. G-66
G-58
MDASM Input Pin to MDASM Interrupt Flag Timing Diagram ......................................... G-66
G-59
MDASM Minimum Output Pulse Width Timing Diagram................................................... G-66
G-60
Counter Bus to MDASM Output Pin Change Timing Diagram............................................ G-66
G-61
Counter Bus to MDASM Interrupt Flag Setting Timing Diagram ........................................ G-67
G-62
MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram .............................. G-67
G-63
MPC561/MPC563 Package Footprint (1 of 2) ...................................................................... G-79
G-64
MPC561/MPC563 Package Footprint (2 of 2) ...................................................................... G-80
G-65
MPC561/MPC563 Ball Map ................................................................................................. G-81
G-66
MPC561/MPC563 Ball Map (Black and White, page 1) ...................................................... G-82
G-67
MPC561/MPC563 Ball Map (Black and White, page 2) ...................................................... G-83
G-68
MPC561/MPC563 Ball Map (Black and White, page 3) ...................................................... G-84
G-69
MPC561/MPC563 Ball Map (Black and White, page 4) ...................................................... G-85
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxi
Figures
Figure
Number
Title
Page
Number
MPC561/MPC563 Reference Manual, Rev. 1.2
lxii
Freescale Semiconductor
Tables
Table
Number
i
ii
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
Title
Page
Number
Notational Conventions ..................................................................................................... 1-lxxxii
Acronyms and Abbreviated Terms .................................................................................... 1-lxxxii
MPC56x Family Features ......................................................................................................... 1-1
Differences Between MPC555 and MPC561/MPC563............................................................ 1-9
MPC561/MPC563 Signal Descriptions .................................................................................... 2-3
MPC561/MPC563 Signal Sharing.......................................................................................... 2-20
Reduced and Full Port Mode Pads.......................................................................................... 2-21
Full Port Only Mode Pads ...................................................................................................... 2-21
PDMCR Field Descriptions .................................................................................................... 2-22
PDMCR2 Field Description.................................................................................................... 2-24
TCNC Pad Functionalities ...................................................................................................... 2-25
PPMPAD Pad Functionalities................................................................................................. 2-25
Enhanced PCS Functionality ................................................................................................. 2-25
Enhanced PCS 4 & 5 Pad Function ........................................................................................ 2-26
Enhanced PCS 6 & 7 Pad Function ........................................................................................ 2-28
MPC561/MPC563 Development Support Shared Signals ..................................................... 2-28
MPC561/MPC563 Mode Selection Options.......................................................................... 2-29
MPC561/MPC563 Signal Reset State .................................................................................... 2-34
RCPU Execution Units ............................................................................................................. 3-4
Supervisor-Level SPRs ............................................................................................................. 3-9
Development Support SPRs.................................................................................................... 3-11
FPSCR Bit Categories ............................................................................................................ 3-13
FPSCR Bit Descriptions ......................................................................................................... 3-14
Floating-Point Result Flags in FPSCR ................................................................................... 3-16
Bit Settings for CR0 Field of CR............................................................................................ 3-17
Bit Settings for CR1 Field of CR............................................................................................ 3-17
CRn Field Bit Settings for Compare Instructions ................................................................... 3-18
Integer Exception Register Bit Descriptions .......................................................................... 3-18
Machine State Register Bit Descriptions ................................................................................ 3-20
Floating-Point Exception Mode Bits ...................................................................................... 3-22
Uses of SPRG0–SPRG3 ......................................................................................................... 3-24
Processor Version Register Bit Descriptions.......................................................................... 3-25
EIE, EID, AND NRI Registers ............................................................................................... 3-25
FPECR Bit Descriptions ......................................................................................................... 3-26
Instruction Set Summary ........................................................................................................ 3-28
RCPU Exception Classes........................................................................................................ 3-35
Exception Vector Offset Table .............................................................................................. 3-36
Instruction Latency and Blockage .......................................................................................... 3-39
Floating-Point Exception Mode Encoding ............................................................................. 3-44
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxiii
Tables
Table
Number
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
3-37
3-38
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
Title
Page
Number
Settings Caused by Reset ....................................................................................................... 3-45
Register Settings following an NMI ....................................................................................... 3-45
Machine Check Exception Processor Actions ........................................................................ 3-47
Register Settings following a Machine Check Exception ...................................................... 3-47
Register Settings following External Interrupt ...................................................................... 3-49
Register Settings for Alignment Exception ........................................................................... 3-50
Register Settings following Program Exception.................................................................... 3-52
Register Settings following a Floating-Point Unavailable Exception ................................... 3-52
Register Settings Following a Decrementer Exception ......................................................... 3-53
Register Settings following a System Call Exception ........................................................... 3-54
Register Settings following a Trace Exception....................................................................... 3-55
Register Settings following Floating-Point Assist Exceptions ............................................... 3-55
Register Settings following a Software Emulation Exception................................................ 3-56
Register Settings following an Instruction Protection Exception ........................................... 3-57
Register Settings Following a Data Protection Error Exception ............................................ 3-59
Register Settings Following a Debug Exception .................................................................... 3-60
Register Settings for Data Breakpoint Match ......................................................................... 3-60
Exception Addresses Mapping ................................................................................................. 4-9
Exception Relocation Page Offset .......................................................................................... 4-10
BBC SPRs............................................................................................................................... 4-17
BBCMCR Field Descriptions ................................................................................................ 4-19
MI_RBA[0:3] Registers Bit Descriptions.............................................................................. 4-21
MI_RA[0:3] Registers Bit Descriptions ................................................................................ 4-22
Region Size Programming Possible Values............................................................................ 4-23
MI_GRA Field Descriptions.................................................................................................. 4-24
EIBADR External Interrupt Relocation Table Base Address Register Bit Descriptions ...... 4-25
USIU Address Map................................................................................................................... 5-3
USIU Special-Purpose Registers .............................................................................................. 5-7
Hex Address Format for SPR Cycles ....................................................................................... 5-7
USIU Pin Multiplexing Control................................................................................................ 6-4
SGPIO Configuration ............................................................................................................... 6-7
Priority of Interrupt Sources—Regular Operation.................................................................. 6-10
Priority of Interrupt Sources—Enhanced Operation .............................................................. 6-12
Interrupt Latency Estimation for Three Typical Cases........................................................... 6-16
Decrementer Time-Out Periods .............................................................................................. 6-18
SIUMCR Bit Descriptions ..................................................................................................... 6-25
Debug Pins Configuration ...................................................................................................... 6-27
General Pins Configuration .................................................................................................... 6-27
Single-Chip Select Field Pin Configuration ........................................................................... 6-27
MPC561/MPC563 Reference Manual, Rev. 1.2
lxiv
Freescale Semiconductor
Tables
Table
Number
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
7-1
7-2
7-3
7-4
7-5
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
9-1
9-2
9-3
9-4
9-5
Title
Page
Number
Multi-Level Reservation Control Pin Configuration .............................................................. 6-28
IMMR Bit Descriptions ......................................................................................................... 6-29
EMCR Bit Descriptions ......................................................................................................... 6-30
SIU Interrupt Controller – Bit Acronym Definitions.............................................................. 6-31
SYPCR Bit Descriptions........................................................................................................ 6-38
SWSR Bit Descriptions ......................................................................................................... 6-39
TESR Bit Descriptions........................................................................................................... 6-39
TBSCR Bit Descriptions........................................................................................................ 6-42
RTCSC Bit Descriptions........................................................................................................ 6-43
PISCR Bit Descriptions ......................................................................................................... 6-44
PITC Bit Descriptions............................................................................................................ 6-45
PIT Bit Descriptions .............................................................................................................. 6-45
SGPIODT1 Bit Descriptions ................................................................................................. 6-46
SGPIODT2 Bit Descriptions ................................................................................................. 6-47
SGPIOCR Bit Descriptions ................................................................................................... 6-48
Data Direction Control............................................................................................................ 6-48
Reset Action Taken for Each Reset Cause ............................................................................... 7-4
Reset Configuration Word and Data Corruption/Coherency.................................................... 7-4
Reset Status Register Bit Descriptions ..................................................................................... 7-5
Reset Configuration Options .................................................................................................... 7-7
RCW Bit Descriptions ............................................................................................................ 7-11
Reset Clocks Source Configuration .......................................................................................... 8-9
TMBCLK Divisions ............................................................................................................... 8-10
Status of Clock Source............................................................................................................ 8-16
Power Mode Control Bit Settings .......................................................................................... 8-17
Power Mode Descriptions...................................................................................................... 8-17
Power Mode Wake-Up Operation ......................................................................................... 8-18
Power Supplies ....................................................................................................................... 8-21
KAPWR Registers and Key Registers.................................................................................... 8-26
SCCR Bit Descriptions ........................................................................................................... 8-30
COM and CQDS Bits Functionality ....................................................................................... 8-33
PLPRCR Bit Descriptions ..................................................................................................... 8-34
COLIR Bit Descriptions ........................................................................................................ 8-36
VSRMCR Bit Descriptions.................................................................................................... 8-37
MPC561/MPC563 BIU Signals................................................................................................ 9-4
Data Bus Requirements For Read Cycles............................................................................... 9-31
Data Bus Contents for Write Cycles....................................................................................... 9-32
Priority Between Internal and External Masters over External Bus ....................................... 9-36
4 Word Burst Length and Order ............................................................................................. 9-38
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxv
Tables
Table
Number
9-6
9-7
9-8
9-9
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
12-1
12-2
12-3
12-4
12-5
12-6
12-7
13-1
13-2
13-3
13-4
13-5
13-6
Title
Page
Number
BURST/TSIZE Encoding ....................................................................................................... 9-38
Address Type Pins .................................................................................................................. 9-39
Address Types Definition ....................................................................................................... 9-39
Termination Signals Protocol ................................................................................................. 9-49
Timing Requirements for Reduced Setup Time ..................................................................... 10-6
Timing Attributes Summary ................................................................................................. 10-11
Programming Rules for Timing Strobes ............................................................................... 10-22
Write Enable/Byte Enable Signals Function ........................................................................ 10-24
Boot Bank Fields Values After Hard Reset .......................................................................... 10-28
Memory Controller Address Map......................................................................................... 10-31
MSTAT Bit Descriptions..................................................................................................... 10-32
BR0–BR3 Bit Descriptions.................................................................................................. 10-33
BRx[V] Reset Value ............................................................................................................ 10-34
OR0–OR3 Bit Descriptions ................................................................................................. 10-35
DMBR Bit Descriptions........................................................................................................ 10-36
DMOR Bit Descriptions ....................................................................................................... 10-38
DMPU Registers ..................................................................................................................... 11-6
Reservation Snoop Support .................................................................................................... 11-9
L2U_MCR LSHOW Modes ................................................................................................. 11-10
L2U Show Cycle Support Chart ........................................................................................... 11-12
L2U (PPC) Register Decode................................................................................................. 11-12
Hex Address For SPR Cycles ............................................................................................... 11-13
L2U_MCR Bit Descriptions ................................................................................................ 11-14
L2U_RBAx Bit Descriptions............................................................................................... 11-15
L2U_RAx Bit Descriptions ................................................................................................. 11-15
L2U_GRA Bit Descriptions................................................................................................. 11-16
STOP and HSPEED Bit Functionality.................................................................................... 12-2
Bus Cycles and System Clock Cycles .................................................................................... 12-3
ILBS Signal Functionality ...................................................................................................... 12-5
IRQMUX Functionality .......................................................................................................... 12-5
UIMB Interface Register Map ................................................................................................ 12-6
UMCR Bit Descriptions.......................................................................................................... 12-8
UIPEND Bit Descriptions....................................................................................................... 12-9
QADC64E_A Address Map ................................................................................................... 13-3
QADC64E_B Address Map.................................................................................................... 13-4
Multiplexed Analog Input Channels....................................................................................... 13-7
Analog Input Channels ........................................................................................................... 13-7
QADCMCR Bit Descriptions ................................................................................................. 13-8
QADC64E Bus Error Response............................................................................................ 13-11
MPC561/MPC563 Reference Manual, Rev. 1.2
lxvi
Freescale Semiconductor
Tables
Table
Number
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
13-25
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
14-18
14-19
14-20
Title
Page
Number
QADCINT Bit Descriptions ................................................................................................. 13-12
PORTQA, PORTQB Bit Descriptions.................................................................................. 13-14
QACR0 Bit Descriptions ...................................................................................................... 13-15
QACR1 Bit Descriptions ...................................................................................................... 13-16
Queue 1 Operating Modes .................................................................................................... 13-16
QACR2 Bit Descriptions ...................................................................................................... 13-18
Queue 2 Operating Modes .................................................................................................... 13-19
QASR0 Bit Descriptions....................................................................................................... 13-21
Pause Response..................................................................................................................... 13-25
Queue Status ......................................................................................................................... 13-25
QASR1 Bit Descriptions....................................................................................................... 13-27
CCW Bit Descriptions .......................................................................................................... 13-30
Non-Multiplexed Channel Assignments and Signal Designations....................................... 13-31
Multiplexed Channel Assignments and Signal Designations ............................................... 13-32
QADC64E Clock Programmability ...................................................................................... 13-50
Trigger Events....................................................................................................................... 13-54
Status Bits ............................................................................................................................. 13-55
External Circuit Settling Time to 1/2 LSB (10-Bit Conversions) ....................................... 13-75
Error Resulting from Input Leakage (IOFF)......................................................................... 13-76
QADC64E_A Address Map ................................................................................................... 14-3
QADC64E_B Address Map.................................................................................................... 14-4
Multiplexed Analog Input Channels....................................................................................... 14-6
Analog Input Channels ........................................................................................................... 14-7
QADCMCR Bit Descriptions ................................................................................................. 14-8
QADC64E Bus Error Response............................................................................................ 14-11
QADCINT Bit Descriptions ................................................................................................. 14-12
PORTQA, PORTQB Bit Descriptions.................................................................................. 14-13
QACR0 Bit Descriptions ...................................................................................................... 14-15
Prescaler fSYSCLK Divide-by Values.................................................................................... 14-15
QACR1 Bit Descriptions ...................................................................................................... 14-17
Queue 1 Operating Modes .................................................................................................... 14-17
QACR2 Bit Descriptions ...................................................................................................... 14-19
Queue 2 Operating Modes .................................................................................................... 14-20
QASR0 Bit Descriptions....................................................................................................... 14-22
Pause Response..................................................................................................................... 14-26
Queue Status ......................................................................................................................... 14-26
QASR1 Bit Descriptions....................................................................................................... 14-28
CCW Bit Descriptions .......................................................................................................... 14-31
QADC64E_A Multiplexed Channel Assignments and Signal Designations ....................... 14-32
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxvii
Tables
Table
Number
14-21
14-22
14-23
14-24
14-25
14-26
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
15-18
15-19
15-20
15-21
15-22
15-23
15-24
15-25
15-26
15-27
15-28
15-29
15-30
15-31
15-32
15-33
Title
Page
Number
QADC64E_B Multiplexed Channel Assignments and Signal Designations........................ 14-33
QADC64E Clock Programmability ...................................................................................... 14-50
Trigger Events....................................................................................................................... 14-53
Status Bits ............................................................................................................................. 14-54
External Circuit Settling Time to 1/2 LSB (10-Bit Conversions) ........................................ 14-73
Error Resulting From Input Leakage (IOFF)........................................................................ 14-74
QSMCM Register Map ........................................................................................................... 15-4
QSMCM Global Registers...................................................................................................... 15-6
Interrupt Levels....................................................................................................................... 15-7
QSMCMMCR Bit Descriptions.............................................................................................. 15-9
QDSCI_IL Bit Descriptions.................................................................................................... 15-9
QSPI_IL Bit Descriptions ..................................................................................................... 15-10
QSMCM Pin Control Registers ............................................................................................ 15-10
Effect of DDRQS on QSPI Pin Function.............................................................................. 15-11
QSMCM Pin Functions ........................................................................................................ 15-12
PQSPAR Bit Descriptions .................................................................................................... 15-13
DDRQS Bit Descriptions...................................................................................................... 15-14
QSPI Register Map ............................................................................................................... 15-16
SPCR0 Bit Descriptions....................................................................................................... 15-18
Bits Per Transfer ................................................................................................................... 15-18
SPCR1 Bit Descriptions........................................................................................................ 15-19
SPCR2 Bit Descriptions....................................................................................................... 15-20
SPCR3 Bit Descriptions....................................................................................................... 15-21
SPSR Bit Descriptions ......................................................................................................... 15-22
Command RAM Bit Descriptions........................................................................................ 15-24
QSPI Pin Functions............................................................................................................... 15-25
Example SCK Frequencies with a 40-MHz IMB3 Clock..................................................... 15-35
PCS Enhanced Functionality ................................................................................................ 15-37
SCI Registers ........................................................................................................................ 15-45
SCCxR0 Bit Descriptions ..................................................................................................... 15-46
SCCxR1 Bit Descriptions .................................................................................................... 15-47
SCxSR Bit Descriptions....................................................................................................... 15-49
SCxDR Bit Descriptions ...................................................................................................... 15-51
SCI Pin Functions ................................................................................................................. 15-51
Serial Frame Formats............................................................................................................ 15-52
Examples of SCIx Baud Rates.............................................................................................. 15-53
Effect of Parity Checking on Data Size ................................................................................ 15-53
QSCI1CR Bit Descriptions ................................................................................................... 15-60
QSCI1SR Bit Descriptions ................................................................................................... 15-61
MPC561/MPC563 Reference Manual, Rev. 1.2
lxviii
Freescale Semiconductor
Tables
Table
Number
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
16-17
16-18
16-19
16-20
16-21
16-22
16-23
16-24
16-25
16-26
16-27
16-28
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
Title
Page
Number
Common Extended/Standard Format Frames ........................................................................ 16-4
Message Buffer Codes for Receive Buffers............................................................................ 16-5
Message Buffer Codes for Transmit Buffers .......................................................................... 16-5
Extended Format Frames ........................................................................................................ 16-6
Standard Format Frames ......................................................................................................... 16-6
Receive Mask Register Bit Values ......................................................................................... 16-8
Mask Examples for Normal/Extended Messages .................................................................. 16-8
Example System Clock, CAN Bit Rate, and S-Clock Frequencies ........................................ 16-9
Interrupt Levels..................................................................................................................... 16-20
TouCAN Register Map ......................................................................................................... 16-21
CANMCR Bit Descriptions .................................................................................................. 16-25
CANICR Bit Descriptions ................................................................................................... 16-27
CANCTRL0 Bit Descriptions............................................................................................... 16-28
Rx MODE[1:0] Configuration.............................................................................................. 16-28
Transmit Signal Configuration ............................................................................................. 16-28
CANCTRL1 Bit Descriptions............................................................................................... 16-29
PRESDIV Bit Descriptions.................................................................................................. 16-30
CANCTRL2 Bit Descriptions.............................................................................................. 16-30
TIMER Bit Descriptions ....................................................................................................... 16-31
RXGMSKHI, RXGMSKLO Bit Descriptions...................................................................... 16-32
RX14MSKHI, RX14MSKLO Field Descriptions ................................................................ 16-32
RX15MSKHI, RX15MSKLO Field Descriptions ................................................................ 16-33
ESTAT Bit Descriptions ...................................................................................................... 16-34
Transmit Bit Error Status ...................................................................................................... 16-35
Fault Confinement State Encoding ....................................................................................... 16-35
IMASK Bit Descriptions ...................................................................................................... 16-36
IFLAG Bit Descriptions....................................................................................................... 16-36
RXECTR, TXECTR Bit Descriptions ................................................................................. 16-36
MIOS14 Configuration Description ....................................................................................... 17-6
MIOS14 I/O Ports ................................................................................................................. 17-13
MIOS14TPCR Bit Descriptions ........................................................................................... 17-14
MIOS14VNR Bit Descriptions ............................................................................................. 17-15
MIOS14MCR Bit Descriptions ............................................................................................ 17-15
MCPSM Register Address Map ........................................................................................... 17-17
MCPSMSCR Bit Descriptions ............................................................................................ 17-18
Clock Prescaler Setting ......................................................................................................... 17-18
MMCSM Address Map ........................................................................................................ 17-22
MMCSMCNT Bit Descriptions............................................................................................ 17-23
MMCSMML Bit Descriptions.............................................................................................. 17-24
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxix
Tables
Table
Number
17-12
17-13
17-14
17-15
17-16
17-17
17-18
17-19
17-20
17-21
17-22
17-23
17-24
17-25
17-26
17-27
17-28
17-29
17-30
17-31
17-32
17-33
17-34
17-35
17-36
17-37
17-38
17-39
17-40
17-41
17-42
17-43
18-1
18-2
18-3
18-4
18-5
18-6
18-7
Title
Page
Number
MMCSMSCR Bit Descriptions ............................................................................................ 17-25
MMCSMCNT Edge Sensitivity............................................................................................ 17-25
MMCSMCNT Clock Signal ................................................................................................. 17-25
Prescaler Values................................................................................................................... 17-26
MDASM Modes of Operation .............................................................................................. 17-29
MDASM PWM Example Output Frequencies/Resolutions at fSYS = 40 MHz.................... 17-38
MDASM Address Map ......................................................................................................... 17-39
MDASMAR Bit Descriptions............................................................................................... 17-42
MDASMBR Bit Descriptions ............................................................................................... 17-43
MDASMSCR Bit Descriptions............................................................................................. 17-44
MDASM Mode Selects......................................................................................................... 17-45
MDASM Counter Bus Selection .......................................................................................... 17-46
PWM Pulse/Frequency Ranges (in Hz) Using /1 or /256 Option (40 MHz) ........................ 17-52
MPWMSM Address Map ..................................................................................................... 17-55
MPWMPERR Bit Descriptions ............................................................................................ 17-57
MPWMPULR Bit Descriptions ............................................................................................ 17-58
MPWMCNTR Bit Descriptions............................................................................................ 17-58
MPWMSCR Bit Descriptions............................................................................................... 17-59
PWMSM Output Signal Polarity Selection .......................................................................... 17-59
Prescaler Values.................................................................................................................... 17-60
MPIOSM I/O Signal Function .............................................................................................. 17-61
MPIOSMDR Bit Descriptions .............................................................................................. 17-63
MPIOSMDDR Bit Descriptions ........................................................................................... 17-63
MIOS14SR0 Bit Description ................................................................................................ 17-66
MIOS14ER0 Bit Descriptions .............................................................................................. 17-66
MIOS14PR0 Bit Descriptions .............................................................................................. 17-67
MIOS14SR1 Bit Descriptions .............................................................................................. 17-67
MIOS14ER1 Bit Descriptions .............................................................................................. 17-68
MIOS14RPR1 Bit Descriptions............................................................................................ 17-68
MBISM Interrupt Registers Address Map............................................................................ 17-69
MIOS14LVL0 Bit Descriptions............................................................................................ 17-70
MIOS14LVL1 Bit Descriptions............................................................................................ 17-70
PPM Memory Map ................................................................................................................. 18-2
PPMMCR Bit Descriptions .................................................................................................. 18-11
PPMPCR Bit Descriptions.................................................................................................... 18-12
SAMP[0:2] Bit Settings ........................................................................................................ 18-13
PPMPCR[CM] and PPMPCR[STR] Bit Operation.............................................................. 18-15
Configuration Register (TX and RX) Channel Settings ....................................................... 18-17
SHORT_REG Bit Descriptions ............................................................................................ 18-20
MPC561/MPC563 Reference Manual, Rev. 1.2
lxx
Freescale Semiconductor
Tables
Table
Number
18-8
18-9
18-10
18-11
18-12
18-13
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
20-1
20-2
20-3
21-1
21-2
21-3
21-4
21-5
21-6
Title
Page
Number
SHORT_REG[SH_TCAN] Bit Settings ............................................................................... 18-20
SHORT_REG[SH_TPU] Bit Settings .................................................................................. 18-21
SHORT_CH_REG Bit Descriptions..................................................................................... 18-23
Examples of the SHORT_CH Bits ....................................................................................... 18-23
SCALE_TCLK Frequencies ................................................................................................. 18-24
SCALE_TCLK_REG Bit Descriptions ................................................................................ 18-24
TPU Memory Map.................................................................................................................. 19-1
Enhanced TCR1 Prescaler Divide Values .............................................................................. 19-6
TCR1 Prescaler Values ........................................................................................................... 19-6
TCR2 Counter Clock Source .................................................................................................. 19-7
TCR2 Prescaler Control.......................................................................................................... 19-8
TPU3 Register Map ................................................................................................................ 19-8
TPUMCR Bit Description .................................................................................................... 19-11
DSCR Bit Descriptions ......................................................................................................... 19-12
DSSR Bit Descriptions ......................................................................................................... 19-14
TICR Bit Description............................................................................................................ 19-15
CIER Bit Descriptions .......................................................................................................... 19-15
CFSRn Bit Descriptions........................................................................................................ 19-16
HSQRn Bit Descriptions....................................................................................................... 19-17
HSSRn Bit Descriptions ....................................................................................................... 19-18
CPRn Bit Description ........................................................................................................... 19-18
Channel Priorities ................................................................................................................. 19-18
CISR Bit Descriptions .......................................................................................................... 19-19
TPUMCR2 Bit Descriptions ................................................................................................. 19-19
Entry Table Bank Location................................................................................................... 19-20
System Clock Frequency/Minimum Guaranteed Detected Pulse......................................... 19-20
TPUMCR3 Bit Descriptions ................................................................................................. 19-21
SIUTST Bit Descriptions...................................................................................................... 19-22
Registers Used for Factory Test Only .................................................................................. 19-22
Parameter RAM Address Offset Map .................................................................................. 19-23
DPTRAM Register Map ......................................................................................................... 20-3
DPTMCR Bit Settings ............................................................................................................ 20-4
RAMBAR Bit Settings ........................................................................................................... 20-5
UC3F External Interface Signals ............................................................................................ 21-4
UC3F Register Programming Model ...................................................................................... 21-5
UC3FMCR Bit Descriptions................................................................................................... 21-6
UC3FMCRE Bit Descriptions ................................................................................................ 21-9
UC3FCTL Bit Descriptions .................................................................................................. 21-11
RCW Bit Descriptions .......................................................................................................... 21-17
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxi
Tables
Table
Number
21-7
21-8
21-9
21-10
22-1
22-2
22-3
22-4
22-5
22-6
22-7
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
23-22
23-23
23-24
23-25
23-26
23-27
23-28
Title
Page
Number
Program Interlock State Descriptions ................................................................................... 21-23
Erase Interlock State Descriptions ........................................................................................ 21-27
Censorship States .................................................................................................................. 21-30
Censorship Modes and Censorship Status ............................................................................ 21-31
Priorities of Overlay Regions ............................................................................................... 22-12
CALRAM Control Registers ................................................................................................ 22-13
CRAMMCR Bit Descriptions............................................................................................... 22-14
CRAMMCR Privilege Bit Assignment for 8-Kbyte Array Blocks ...................................... 22-15
CRAM_RBAx Bit Descriptions ........................................................................................... 22-16
RGN_SIZE Encoding ........................................................................................................... 22-16
CRAMOVLCR Bit Descriptions .......................................................................................... 22-17
VF Pins Instruction Encodings ............................................................................................... 23-3
VF Pins Queue Flush Encodings ............................................................................................ 23-3
VFLS Pin Encodings .............................................................................................................. 23-4
Detecting the Trace Buffer Start Point ................................................................................... 23-6
Fetch Show Cycles Control .................................................................................................... 23-7
Instruction Watchpoints Programming Options ................................................................... 23-15
Load/Store Data Events ........................................................................................................ 23-16
Load/Store Watchpoints Programming Options................................................................... 23-17
Check Stop State and Debug Mode ...................................................................................... 23-27
Trap Enable Data Shifted into Development Port Shift Register ......................................... 23-34
Debug Port Command Shifted Into Development Port Shift Register ................................. 23-34
Status / Data Shifted Out of Development Port Shift Register............................................. 23-35
Debug Instructions / Data Shifted into Development Port Shift Register ............................ 23-36
Development Support Programming Model......................................................................... 23-39
Development Support Registers Read Access Protection .................................................... 23-40
Development Support Registers Write Access Protection ................................................... 23-41
CMPA-CMPD Bit Descriptions ........................................................................................... 23-41
ECR Bit Descriptions............................................................................................................ 23-42
DER Bit Descriptions ........................................................................................................... 23-43
Breakpoint Counter A Value and Control Register (COUNTA).......................................... 23-45
Breakpoint Counter B Value and Control Register (COUNTB) ......................................... 23-46
CMPE–CMPF Bit Descriptions............................................................................................ 23-46
CMPG-CMPH Bit Descriptions ........................................................................................... 23-47
LCTRL1 Bit Descriptions..................................................................................................... 23-47
LCTRL2 Bit Descriptions..................................................................................................... 23-49
ICTRL Bit Descriptions........................................................................................................ 23-51
ISCT_SER Bit Descriptions ................................................................................................. 23-52
BAR Bit Descriptions ........................................................................................................... 23-53
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxii
Tables
Table
Number
24-1
24-2
24-3
24-4
24-5
24-6
24-7
24-8
24-9
24-10
24-11
24-12
24-13
24-14
24-15
24-16
24-17
24-18
24-19
24-20
24-21
24-22
24-23
24-24
24-25
24-26
24-27
24-28
24-29
24-30
24-31
24-32
24-33
24-34
24-35
25-1
25-2
25-3
A-1
Title
Page
Number
Public Messages...................................................................................................................... 24-5
Vendor-Defined Messages...................................................................................................... 24-5
Terms and Definitions ............................................................................................................ 24-6
OTR Bit Descriptions ............................................................................................................. 24-9
Tool-Mapped Register Space.................................................................................................. 24-9
DID Bit Descriptions ............................................................................................................ 24-10
DC Bit Descriptions.............................................................................................................. 24-11
RCPU Development Access Modes ..................................................................................... 24-11
MC Bit Descriptions ............................................................................................................. 24-12
UBA Bit Descriptions ........................................................................................................... 24-13
RWA Read/Write Access Bit Descriptions .......................................................................... 24-14
UDI Bit Descriptions ............................................................................................................ 24-16
Read Access Status ............................................................................................................... 24-16
Write Access Status .............................................................................................................. 24-16
DTA 1 AND 2 Bit Descriptions ........................................................................................... 24-17
Data Trace Values................................................................................................................. 24-18
Description of READI Signals ............................................................................................. 24-21
MSEI/MSEO Protocol .......................................................................................................... 24-23
Public Messages Supported .................................................................................................. 24-24
Error Message Codes ............................................................................................................ 24-27
Vendor-Defined Messages Supported .................................................................................. 24-27
Message Field Sizes, ............................................................................................................. 24-29
Indirect Branch Message ...................................................................................................... 24-33
Direct Branch Message ......................................................................................................... 24-33
READI Reset Configuration Options ................................................................................... 24-34
Bit Pointer Format ................................................................................................................ 24-39
Program Trace Correction Due to a Mispredicted Branch ................................................... 24-40
Program Trace Correction Due to an Exception................................................................... 24-41
Resource Codes..................................................................................................................... 24-46
Special L-Bus Case Handling ............................................................................................... 24-56
Throughput Comparison for FPM and RPM MDO/MDI Configurations ............................ 24-68
Watchpoint Source................................................................................................................ 24-73
Development Port Access: DSDI Field ................................................................................ 24-84
Development Port Access: DSDO Field............................................................................... 24-84
Power Management Mechanism Overview .......................................................................... 24-86
MPC561 Boundary Scan Bit Definition ................................................................................. 25-5
MPC563 Boundary Scan Bit Definition ............................................................................... 25-17
Instruction Decoding............................................................................................................. 25-30
ICTRL Bit Descriptions......................................................................................................... A-17
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxiii
Tables
Table
Number
A-2
A-3
A-4
B-1
B-2
B-3
B-4
B-5
B-6
B-7
B-8
B-9
B-10
B-11
B-12
B-13
B-14
B-15
B-16
B-17
B-18
C-1
C-2
D-1
D-2
D-3
D-4
E-1
E-2
F-1
F-2
F-3
F-4
F-5
F-6
F-7
F-8
F-9
F-10
Title
Page
Number
ISCT_SER Bit Descriptions .................................................................................................. A-18
DCCR0-DCCR15 Field Descriptions .................................................................................... A-20
Instruction Layout Encoding ................................................................................................. A-21
SPR (Special Purpose Registers) ..............................................................................................B-2
UC3F Flash Array.....................................................................................................................B-4
DECRAM SRAM Array...........................................................................................................B-4
BBC (Burst Buffer Controller Module)....................................................................................B-4
USIU (Unified System Interface Unit) .....................................................................................B-5
CDR3 Flash Control Registers EEPROM (UC3F)...................................................................B-9
DPTRAM Control Registers...................................................................................................B-10
DPTRAM Memory Arrays .....................................................................................................B-10
Time Processor Unit 3 A and B (TPU3 A and B) ..................................................................B-10
QADC64E A and B (Queued Analog-to-Digital Converter)..................................................B-14
QSMCM (Queued Serial Multi-Channel Module) .................................................................B-16
Peripheral Pin Multiplexing (PPM) Module...........................................................................B-17
MIOS14 (Modular Input/Output Subsystem) .........................................................................B-18
TouCAN A, B and C (CAN 2.0B Controller) ........................................................................B-26
UIMB (U-Bus to IMB Bus Interface).....................................................................................B-31
CALRAM Control Registers ..................................................................................................B-31
CALRAM Array .....................................................................................................................B-32
READI Module Registers .......................................................................................................B-32
External Components Value For Different Crystals (Q1) ........................................................C-4
IRAMSTBY Regulator Operating Specifications ....................................................................C-8
Bank 0 and Bank 1 Functions .................................................................................................. D-2
QOM Bit Encoding .................................................................................................................. D-5
SIOP Function Valid CHAN_Control Options ..................................................................... D-56
SIOP State Timing ................................................................................................................. D-58
Memory Access Times Using Different Buses.........................................................................E-1
Instruction Timing Examples for Different Buses....................................................................E-2
Absolute Maximum Ratings (VSS = 0V) ................................................................................. F-1
Thermal Characteristics ............................................................................................................ F-3
ESD Protection ......................................................................................................................... F-6
DC Electrical Characteristics.................................................................................................... F-7
Oscillator and PLL.................................................................................................................. F-11
Array Program and Erase Characteristics ............................................................................... F-12
CENSOR Cell Program and Erase Characteristics................................................................. F-12
Flash Module Life................................................................................................................... F-12
Power Supply Pin Groups....................................................................................................... F-13
Bus Operation Timing ............................................................................................................ F-20
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxiv
Tables
Table
Number
F-12
F-11
F-13
F-14
F-15
F-16
F-17
F-18
F-19
F-20
F-21
F-22
F-23
F-24
F-25
F-26
F-27
F-28
G-1
G-2
G-3
G-4
G-5
G-6
G-7
G-8
G-9
G-10
G-11
G-12
G-13
G-14
G-15
G-16
G-17
G-18
G-19
G-20
G-21
Title
Page
Number
Debug Port Timing ................................................................................................................. F-43
Interrupt Timing...................................................................................................................... F-43
READI AC Electrical Characteristics..................................................................................... F-45
RESET Timing ....................................................................................................................... F-47
JTAG Timing .......................................................................................................................... F-50
QADC64E Conversion Characteristics .................................................................................. F-54
QSPI Timing ........................................................................................................................... F-56
QSCI Timing........................................................................................................................... F-57
GPIO Timing .......................................................................................................................... F-60
TPU3 Timing .......................................................................................................................... F-61
TouCAN Timing..................................................................................................................... F-62
PPM Timing............................................................................................................................ F-62
MCPSM Timing Characteristics............................................................................................. F-64
MPWMSM Timing Characteristics ........................................................................................ F-64
MMCSM Timing Characteristics ........................................................................................... F-67
MDASM Timing Characteristics............................................................................................ F-69
MPIOSM Timing Characteristics ........................................................................................... F-71
MPC561/MPC563 Signal Names and Pin Names .................................................................. F-73
Absolute Maximum Ratings (VSS = 0V) ................................................................................ G-1
Thermal Characteristics ........................................................................................................... G-3
ESD Protection ........................................................................................................................ G-6
DC Electrical Characteristics................................................................................................... G-7
Oscillator and PLL................................................................................................................. G-10
Array Program and Erase Characteristics .............................................................................. G-11
CENSOR Cell Program and Erase Characteristics................................................................ G-11
Flash Module Life.................................................................................................................. G-12
Power Supply Pin Groups...................................................................................................... G-12
Bus Operation Timing ........................................................................................................... G-20
Interrupt Timing..................................................................................................................... G-40
Debug Port Timing ................................................................................................................ G-41
READI AC Electrical Characteristics.................................................................................... G-43
RESET Timing ...................................................................................................................... G-44
JTAG Timing ......................................................................................................................... G-47
QADC64E Conversion Characteristics ................................................................................. G-50
QSPI Timing .......................................................................................................................... G-52
QSCI Timing.......................................................................................................................... G-53
GPIO Timing ......................................................................................................................... G-56
TPU3 Timing ......................................................................................................................... G-57
TouCAN Timing.................................................................................................................... G-58
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxv
Tables
Table
Number
G-22
G-23
G-24
G-25
G-26
G-27
G-28
Title
Page
Number
PPM Timing........................................................................................................................... G-58
MCPSM Timing Characteristics............................................................................................ G-60
MPWMSM Timing Characteristics ....................................................................................... G-60
MMCSM Timing Characteristics .......................................................................................... G-62
MDASM Timing Characteristics........................................................................................... G-64
MPIOSM Timing Characteristics .......................................................................................... G-67
MPC561/MPC563 Signal Names and Pin Names ................................................................. G-68
MPC561/MPC563 Reference Manual, Rev. 1.2
lxxvi
Freescale Semiconductor
About This Book
This manual describes the capabilities, operation, and function of the Freescale MPC561/MPC563
microcontrollers. The documentation follows the modular construction of the devices in the MPC500
family product line. Each microcontroller in the MPC500 family has a comprehensive reference manual
that provides sufficient information for normal operation of the device. The reference manual is
supplemented by module-specific reference manuals that provide detailed information about module
operation and applications. Where information in this manual varies from information in other references,
this manual takes precedence. Refer to Suggested Reading for further information.
Unless otherwise noted, references to the MPC561 and MPC563 also apply to their code compressed
counterparts, the MPC562 and MPC564, respectively. Any functional differences between the
MPC561/MPC563 and MPC562/MPC564 are noted. MPC562/MPC564-specific information is located in
Appendix A, “MPC562/MPC564 Compression Features.”
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products for the MPC561/MPC563. It is assumed that the reader understands operating
systems and microprocessor and microcontroller system design.
Organization
Following is a summary and brief description of the major sections of this manual:
• Chapter 1, “Overview,” provides an overview of the MPC561/MPC563 microcontroller, including
a block diagram showing the major modular components, a features list, and a summary of
differences between the MPC561/MPC563 and the MPC555.
• Chapter 2, “Signal Descriptions,” describes the MPC561/MPC563 microcontroller’s external
signals.
• Chapter 3, “Central Processing Unit,” describes the RISC processor (RCPU) used in the MPC500
family of microcontrollers.
• Chapter 4, “Burst Buffer Controller 2 Module,” describes the three main functional parts: the bus
interface unit (BIU), the instruction memory protection unit (IMPU), and the instruction code
decompressor unit (ICDU).
• Chapter 5, “Unified System Interface Unit (USIU) Overview.” The unified system interface unit
(USIU) of the MPC561/MPC563 consists of several functional modules that control system
start-up, system initialization and operation, system protection, and the external system bus.
• Chapter 6, “System Configuration and Protection.” The MPC561/MPC563 incorporates many
system functions that normally must be provided in external circuits. In addition, it is designed to
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxvii
•
•
•
•
•
•
•
•
•
•
•
•
provide maximum system safeguards against hardware and software faults. This chapter provides
a detailed explanation of this functionality.
Chapter 7, “Reset.” This section describes the MPC561/MPC563 reset sources, operation, control,
and status.
Chapter 8, “Clocks and Power Control,” describes the main timing and power control reference for
the MPC561/MPC563.
Chapter 9, “External Bus Interface,” describes the functionality of the MPC561/MPC563 external
bus.
Chapter 10, “Memory Controller,” generates interface signals to support a glueless interface to
external memory and peripheral devices.
Chapter 11, “L-Bus to U-Bus Interface (L2U),” describes the interface between the load/store bus
(L-bus) and the unified bus (U-bus). The L2U module includes the Data Memory Protection Unit
(DMPU), which provides protection for data memory accesses.
Chapter 12, “U-Bus to IMB3 Bus Interface (UIMB).” The U-bus to IMB3 bus interface (UIMB)
structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3).
It controls bus communication between the U-bus and the IMB3.
Chapter 13, “QADC64E Legacy Mode Operation.” The two queued analog-to-digital converter
(QADC) modules on MPC561/MPC563 devices are 10-bit, unipolar, successive approximation
converters. The modules can be configured to operate in one of two modes, legacy mode (MPC555
compatible) and enhanced mode. This chapter describes how the modules operate in legacy mode,
which is the default mode of operation.
Chapter 14, “QADC64E Enhanced Mode Operation.” The two queued analog-to-digital converter
(QADC) modules on the MPC561/MPC563 devices are 10-bit, unipolar, successive approximation
converters. The modules can be configured to operate in one of two modes, legacy mode (for
MPC555 compatibility) and enhanced mode. This chapter describes how the module operates in
enhanced mode.
Chapter 15, “Queued Serial Multi-Channel Module.” The MPC561/MPC563 contains one queued
serial multi-channel module (QSMCM) which provides three serial communication interfaces: the
queued serial peripheral interface (QSPI) and two serial communications interfaces (SCI/UART).
This chapter describes the functionality of each.
Chapter 16, “CAN 2.0B Controller Module,” describes the three CAN 2.0B controller modules
(TouCAN) implemented on the MPC561/MPC563. Each TouCAN is a communication controller
that implements the Controller Area Network (CAN) protocol, an asynchronous communications
protocol used in automotive and industrial control systems. It is a high speed (one Mbit/sec), short
distance, priority based protocol that can run over a variety of mediums.
Chapter 17, “Modular Input/Output Subsystem (MIOS14).” The modular I/O system (MIOS)
consists of a library of flexible I/O and timer functions including I/O port, counters, input capture,
output compare, pulse and period measurement, and PWM. Because the MIOS14 is composed of
submodules, it is easily configurable for different kinds of applications.
Chapter 18, “Peripheral Pin Multiplexing (PPM) Module.” The PPM functions as a
parallel-to-serial communications module that reduces the number of signals required to connect
MPC561/MPC563 Reference Manual, Rev. 1.2
lxxviii
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
•
•
the MPC561/MPC563 to an external device; and shorts internal signals to increase access to
multiple functions multiplexed on the same external signal.
Chapter 19, “Time Processor Unit 3,” describes an enhanced version of the original TPU, an
intelligent, semi-autonomous microcontroller designed for timing control.
Chapter 20, “Dual-Port TPU3 RAM (DPTRAM).” The dual-port RAM (DPTRAM) module
consists of a control register block and an 8-Kbyte array of static RAM that can be used either as
microcode storage for the TPU3 or as general-purpose memory. The MPC561/MPC563 has one
DPTRAM module that serves two TPU3 modules.
Chapter 21, “CDR3 Flash (UC3F) EEPROM.” The MPC563 U-bus CDR3 (UC3F) EEPROM
module is designed for use in embedded microcontroller applications targeted for high-speed read
performance and high-density byte count requirements.
Chapter 22, “CALRAM Operation.” This module provides the MPC561/MPC563 with a general
purpose memory that may be read from or written to as either bytes, half-words, or words. In
addition to this, a portion of the CALRAM, called the overlay region, can be used for calibration
(i.e., overlaying portions of the U-bus Flash with a portion of the CALRAM array).
Chapter 23, “Development Support,” covers program flow tracking support,
breakpoint/watchpoint support, development system interface support (debug mode) and software
monitor debugger support. These features allow efficiency in debugging systems based on the
MPC561/MPC563.
Chapter 24, “READI Module.” The READI module provides development support capabilities for
MCUs in single chip mode, without requiring address and data signals for internal visibility.
Chapter 25, “IEEE 1149.1-Compliant Interface (JTAG),” describes MPC561/MPC563
compatibility with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture as
well as any potential incompatibility issues.
Appendix A, “MPC562/MPC564 Compression Features,” includes information about code
compression features of the MPC562/MPC564.
Appendix B, “Internal Memory Map,” provides memory maps for the MPC561/MPC563 modules.
Appendix C, “Clock and Board Guidelines.” The MPC561/MPC563 built-in PLL, oscillator, and
other analog and sensitive circuits require that the board design follow special layout guidelines to
ensure proper operation of the chip clocks. This appendix describes how the clock supplies and
external components should be connected in a system.
Appendix D, “TPU3 ROM Functions,” provides a brief description of the pre-programmed
functions in the TPU3.
Appendix E, “Memory Access Timing,” lists memory access timings for internal and external
memory combinations.
Appendix F, “Electrical Characteristics,” contains detailed information on power considerations,
DC/AC electrical characteristics, and AC timing characteristics of the MPC561/MPC563 at the
default 40 MHz and optional 56 MHz operating frequencies.
Appendix G, “66-MHz Electrical Characteristics,” contains detailed information on power
considerations, DC/AC electrical characteristics, and AC timing characteristics of the
MPC561/MPC563 at the optional operating frequency of 66 MHz.
This document also includes a register index and comprehensive index.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxix
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the PowerPCΤΜ architecture. Also listed are documents that further complement
this manual by providing in-depth functional descriptions of certain modules:
• QSM (Queued Serial Module) Reference Manual (QSMRM/AD)
• TPU (Time Processor Unit) documentation (TPULITPAK/D, including the TPURM/AD)
• RCPU (RISC Central Processor Unit) Reference Manual (RCPURM/AD)
• Nexus Standard Specification Rev 1.0 (IEEE-ISTO 5001-1999) available at:
http://www.nexus5001.org/
•
JTAG IEEE 1149.1 Specification
The following general documentation, available through Morgan-Kaufmann Publishers, 340 Pine Street,
Sixth Floor, San Francisco, CA, provides useful information about the PowerPC architecture:
• The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc.
Freescale documentation is available from the sources listed on the back cover of this manual. A brief
summary of available documentation is listed below:
• Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture
(MPCFPE32B/AD)—Describes resources defined by the PowerPC architecture.
• Reference manuals—These books provide details about individual implementations and are
intended for use with the Programming Environments Manual.
• Addenda/errata to reference manuals—Because some processors have follow-on parts, an
addendum is provided that describes the additional features and functionality changes and are
intended for use with the corresponding reference manuals.
• Product Briefs—Each device has a product brief that provides an overview of its features. This
document is roughly the equivalent to the overview chapter (Chapter 1) of an implementation’s
reference manual.
• The Programmer’s Reference Guide for the PowerPC Architecture (MPCPRG/D)—This concise
reference includes the register summary, exception vectors, and the PowerPC ISA instruction set.
• Application notes—These short documents address specific design issues useful to programmers
and engineers working with Freescale processors.
Additional literature is published as new processors become available. For a current list of documentation,
refer to http://www.motorola.com/semiconductors.
Conventions and Nomenclature
This document uses the following notational conventions:
cleared/set
When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
MPC561/MPC563 Reference Manual, Rev. 1.2
lxxx
Freescale Semiconductor
ACTIVE_HIGH
ACTIVE_LOW
0x0
0b0
italics
REG[FIELD]
x
n
¬
&
|
Logic level one
Logic level zero
To set a bit or bits
To clear a bit or bits
LSB
MSB
Asserted
Negated
Names for signals that are active high are shown in uppercase text. Signals that are
active high are referred to as asserted when they are high and negated when they
are low.
Names for signals that are active low are shown in uppercase text with an overbar.
Active-low signals are referred to as asserted (active) when they are low and
negated when they are high.
Prefix to denote hexadecimal number
Prefix to denote binary number
Italics indicate variable command parameters.
Book titles in text are also set in italics.
Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, CRAMMCR[DIS] identifies the array disable bit
(DIS) within the CALRAM module configuration register.
A range of bits or signals is referred to by mnemonic and the numbers that define
the range. For example, DATA[24:31] form the least significant byte of the data
bus.
In some contexts, such as signal encodings, x indicates a don’t care.
Used to express an undefined numerical value
NOT logical operator
AND logical operator
OR logical operator
is the voltage that corresponds to Boolean true (1) state.
is the voltage that corresponds to Boolean false (0) state.
means to establish logic level one on the bit or bits.
means to establish logic level zero on the bit or bits.
means least significant bit or bits.
means most significant bit or bits.
means that a signal is in active logic state. An active low signal changes from logic
level one to logic level zero when asserted, and an active high signal changes from
logic level zero to logic level one.
means that an asserted signal changes logic state. An active low signal changes
from logic level zero to logic level one when negated, and an active high signal
changes from logic level one to logic level zero.
Notational Conventions
Table i contains notational conventions that are used in this document.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxxi
Table i. Notational Conventions
Symbol
Function
+
Addition
–
Subtraction (two’s complement) or negation
*
Multiplication
/
Division
>
Greater
<
Less
=
Equal
≥
Equal or greater
≤
Equal or less
≠
Not equal
•
AND
|
Inclusive OR (OR)
⊕
Exclusive OR (EOR)
NOT
Complementation
:
Concatenation
?
Transferred
⇔
Exchanges
±
Sign bit; also used to show tolerance
«
Sign extension
Acronyms and Abbreviations
Table ii contains acronyms and abbreviations that are used in this document.
Table ii. Acronyms and Abbreviated Terms
Term
Meaning
ALU
Arithmetic logic unit
BIST
Built-in self test
BIU
Bus interface unit
BPU
Branch processing unit
BSDL
Boundary-scan description language
CMOS
Complementary metal-oxide semiconductor
EA
Effective address
EAR
External access register
FIFO
First-in-first-out
FPR
Floating-point register
FPSCR
Floating-point status and control register
MPC561/MPC563 Reference Manual, Rev. 1.2
lxxxii
Freescale Semiconductor
Table ii. Acronyms and Abbreviated Terms (continued)
Term
Meaning
FPU
Floating-point unit
GPR
General-purpose register
IABR
Instruction address breakpoint register
IEEE
Institute for Electrical and Electronics Engineers
IU
Integer unit
JTAG
Joint Test Action Group
LIFO
Last-in-first-out
LR
Link register
LSB
Least-significant bit
LSU
Load/store unit
MSB
Most-significant bit
MSR
Machine state register
NaN
Not a number
No-op
No operation
OEA
Operating environment architecture
PLL
Phase-locked loop
POR
Power-on reset
PVR
Processor version register
RISC
Reduced instruction set computing
SPR
Special-purpose register
SRR0
Machine status save/restore register 0
SRR1
Machine status save/restore register 1
TB
Time base facility
TBL
Time base lower register
TBU
Time base upper register
TLB
Translation lookaside buffer
TTL
Transistor-to-transistor logic
UIMM
Unsigned immediate value
UISA
User instruction set architecture
VEA
Virtual environment architecture
XER
Register used for indicating conditions such as carries and overflows for integer operations
References
The Sematech Official Dictionary and the Reference Guide to Letter Symbols for Semiconductor Devices
by the JEDEC Council/Electronics Industries Association are recommended as references for terminology
and symbology.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
lxxxiii
MPC561/MPC563 Reference Manual, Rev. 1.2
lxxxiv
Freescale Semiconductor
Chapter 1
Overview
This chapter provides an overview of the MPC561/MPC563 microcontrollers, including a block diagram
showing the major modular components and sections that list the major features, and differences between
the MPC561/MPC563 and the MPC555. The MPC561, MPC562, MPC563, and MPC564 devices are
members of the Freescale MPC500 RISC Microcontroller family. The parts herein will be referred to only
as MPC561/MPC563 unless specific parts need to be referenced.
Table 1-1. MPC56x Family Features
1.1
Device
Flash
Code Compression
MPC561
None
Not Supported
MPC562
None
Supported
MPC563
512-Kbytes Flash
Not Supported
MPC564
512-Kbytes Flash
Supported
Introduction
The MPC561/MPC563 devices offer the following features:
• PowerPC ISA-compliant 32-bit single issue RISC processor (RCPU)
• 64-bit floating-point unit (FPU)
• Unified system integration unit (USIU) with a flexible memory controller and enhanced interrupt
controller (EIC)
• 512-Kbytes of Flash EEPROM memory (available on the MPC563 only)
— Typical endurance of 100,000 write/erase cycles @ 25ºC
— Typical data retention of 100 years @ 25ºC
• 32-Kbytes of static RAM in one CALRAM module, configured as
— 28-Kbyte normal access only array
— 4-Kbyte normal access or overlay access array (eight 512-byte regions)
• Two time processing units (TPU3) with one 8-Kbyte dual port TPU RAM (DPTRAM)
• One 22-timer channel modular I/O system (MIOS14)
• Three TouCAN modules (TouCAN)
• Two enhanced queued analog systems (QADC64E)
• One queued serial multi-channel module (QSMCM), which contains one queued serial peripheral
interface (QSPI) and two serial controller interfaces (SCI/UART)
• One peripheral pin multiplexing module (PPM) with a parallel to serial driver
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
1-1
Overview
•
•
•
•
•
1.2
Debug features:
— Nexus debug port (Class 3)
— Background debug mode (BDM)
— IEEE 1194.1-compliant interface (JTAG) for boundary scan
Plastic ball grid array (PBGA) packaging
— 388 ball PBGA
— 27 mm x 27 mm body size
— 1.0 mm ball pitch
Default 40-, and optional 56-, and 66-MHz operation
-40°C–125°C
Independent power supplies
— 5-V I/O (5.0 ± 0.25 V)
— 2.6 ± 0.1-V external bus with a 5-V tolerant I/O system
— 2.6 ± 0.1-V internal logic
— <150µA on-chip voltage shunt regulator for RAM standby operation
Block Diagram
Figure 1-1 is a block diagram of the MPC561/MPC563.
MPC561/MPC563 Reference Manual, Rev. 1.2
1-2
Freescale Semiconductor
Overview
512 Kbytes
Flash
MPC563 only
JTAG
Burst
Buffer
Controller
U-Bus
E-Bus
USIU
READI
RCPU
L2U
L-Bus
32-Kbyte CALRAM
28-Kbyte
SRAM
(No Overlay)
4-Kbyte Overlay
QADC64E
QADC64E
QSMCM
PPM
UIMB
IMB3
TPU3
8-Kbyte
DPTRAM
TPU3
Tou
CAN
Tou
CAN
Tou
CAN
MIOS14
Figure 1-1. MPC561/MPC563 Block Diagram
1.3
Key Features
The MPC561/MPC563 key features are explained in the following sections.
1.3.1
•
•
High-Performance CPU System
Fully static design
Four major power saving modes
— On, doze, sleep, deep-sleep, and power-down
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
1-3
Overview
1.3.1.1
•
•
•
•
•
•
•
•
•
PowerPCΤΜ-compliant 32-bit single issue core
Precise exception model
64-bit floating point unit (FPU)
Code compression supported on MPC562/MPC564
Reduces usage of internal/external Flash memory (up to 50% for code) on the MPC564
Reduces code size up to 50%
Extensive system development support
On-chip watchpoints and breakpoints
Program flow tracking capability
1.3.1.2
•
•
•
•
•
•
•
•
Unified System Interface Unit (USIU)
System configuration and protection features:
— Periodic-interrupt timer
— Bus monitor
— Software watchdog timer
— Real-time clock (RTC)
— PPC decrementer
— Time base
Clock synthesizer
Power management
Reset controller
External bus interface that tolerates 5-V inputs, provides 2.6-V outputs, and supports multi-master
designs
Enhanced interrupt controller that supports up to eight external and 40 internal interrupts,
simplifies the interrupt structure, and decreases interrupt processing time
USIU supports dual mapping to map part of one internal/external memory to another external
memory
External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions per
memory cycle
1.3.1.3
•
•
•
•
RISC MCU Central Processing Unit (RCPU)
Burst Buffer Controller (BBC) Module
Support for enhanced interrupt controller (EIC)
Support for enhanced exception table relocation feature
Branch target buffer
Contains 2 Kbytes of decompression RAM (DECRAM) for code compression. This RAM may
also be used as general-purpose RAM when the code compression feature is not used.
MPC561/MPC563 Reference Manual, Rev. 1.2
1-4
Freescale Semiconductor
Overview
1.3.1.4
•
•
•
•
Flexible memory protection units (MPU) in BBC and L2U
Default attributes available in one global entry
Attribute support for speculative accesses
Up to eight memory regions are supported, four for data and four for instructions
1.3.1.5
•
•
•
•
•
•
•
•
Memory Controller
Four flexible chip selects via memory controller
32-bit address and data buses
4-Kbyte to one 16-Mbyte (data) or 4-Gbyte (instruction) region size support
Supports enhanced external burst
— Up to eight-beat transfer bursts, two-clock minimum bus transactions
Use with SRAM, EPROM, Flash and other peripherals
Byte selects or write enables
32-bit address fully decodes internal address space (4 Gbytes) with bit masks
Four regions
1.3.1.6
•
•
•
•
•
•
•
•
Flexible Memory Protection Unit
512-Kbytes of CDR3 Flash EEPROM Memory (UC3F) –
MPC563/MPC564 Only
One 512-Kbyte module
Page read mode (2/1/1/1 clock read access time)
Byte, half-word or word programmable.
Block (64 Kbytes) erasable
External 4.75- to 5.25-V VFLASH power supply for program, erase, and read operations
Security modes for software protection
Typical endurance of 100,000 write/erase cycles @ 25ºC
Typical data retention of 100 years @ 25ºC
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
1-5
Overview
1.3.1.7
•
•
•
•
•
Composed of one 32-Kbyte CALRAM module
— 28-Kbyte static RAM
— 4-Kbyte calibration (overlay) RAM feature that allows calibration of Flash-based constants
Eight 512-byte overlay regions
One clock fast accesses
Two clock cycle access option for power saving
Standby power supply (IRAMSTBY) for data retention
1.3.1.8
•
•
•
•
•
•
•
•
Nexus Debug Port (Class 3)
Compliant with Class 3 of the IEEE-ISTO 5001-1999
Program trace via branch trace messaging (BTM)
Data trace via data write messaging (DWM) and data read messaging (DRM)
Ownership trace via ownership trace messaging (OTM)
Run-time access to on-chip memory map and special-purpose registers (SPRs) via the READI
read/write access protocol
Watchpoint messaging via the auxiliary port
9 or 16 full-duplex auxiliary pin interface for medium and high visibility throughput
All features configurable and controllable via the auxiliary port
Supports the RCPU debug mode via the auxiliary port
1.3.3
Integrated I/O System
1.3.3.1
•
•
•
•
Two Time Processor Units (TPU3)
True 5 V I/O
Two time processing units (TPU3) with 16 channels each
Each TPU3 is a micro-coded timer subsystem
8 Kbytes of dual port TPU RAM (DPTRAM) shared by two TPU3 modules for TPU micro-code
1.3.3.2
•
•
General Purpose I/O Support (GPIO)
24 address signals and 32 data signals can be used for general-purpose I/O in single-chip mode
16 GPIO in MIOS14
Many peripheral signals can be used as GPIO when not used as primary functions
5-V outputs with slew rate control
1.3.2
•
•
•
•
•
32-Kbyte Static RAM (CALRAM)
22-Channel Modular I/O System (MIOS14)
Six modulus counter sub-modules (MCSM)
10 double-action sub-modules (DASM)
MPC561/MPC563 Reference Manual, Rev. 1.2
1-6
Freescale Semiconductor
Overview
•
•
12 dedicated PWM sub-modules (PWMSM)
One MIOS14 16-bit parallel port I/O sub-modules (MPIOSM)
1.3.3.3
•
•
•
•
•
•
•
•
•
•
•
•
Two queued analog-to-digital converter modules (QADC64E_A, QADC64E_B) providing a total
of 32 analog channels
16 analog input channels on each QADC64E module using internal multiplexing
Directly supports up to four external multiplexers
Up to 41 total input channels on the two QADC64E modules with external multiplexing
Software configurable to operate in enhanced or legacy (MPC555 compatible) mode
Unused analog channels can be used as digital input/output signals
— GPIO on all channels in enhanced mode
10-bit A/D converter with internal sample/hold
Minimum conversion time of 7 µs (with typical QCLK frequency, 2 MHz) and +/- 2 bits accuracy
Two conversion command queues of variable length
Automated queue modes initiated by:
— External edge trigger
— Software command
— Periodic/interval timer within the QADC64E module, that can be assigned to both queue 1 and
2
— External gated trigger (queue 1 only)
64 result registers
— Output data is right- or left-justified, signed or unsigned.
Alternate reference input (ALTREF), with control in the conversion command word (CCW)
1.3.3.4
•
•
Two Enhanced Queued Analog-to-Digital Converter Modules
(QADC64E)
Three CAN 2.0B Controller (TouCAN) Modules
Three TouCAN modules (TouCAN_A, TouCAN_B, TouCAN_C)
Each TouCAN provides the following features:
— 16 message buffers, programmable I/O modes
— Maskable interrupts
— Independent of the transmission medium (external transceiver is assumed)
— Open network architecture, multi-master concept
— High immunity to EMI
— Short latency time for high-priority messages
— Low-power sleep mode, with programmable wake-up on bus activity
— TouCAN_C pins are shared with MIOS14 GPIO or QSMCM
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
1-7
Overview
1.3.3.5
•
•
•
•
One queued serial module with one queued SPI and two SCIs (QSMCM)
QSMCM matches full MPC555 QSMCM functionality
Queued SPI
— Provides full-duplex communication port for peripheral expansion or inter-processor
communication
— Up to 32 preprogrammed transfers, reducing overhead
— Synchronous serial interface with baud rate of up to system clock / 4
— Four programmable peripheral-selects signals:
— Supports up to 16 devices with external decoding
— Supports up to eight devices with internal decoding
— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient
interfacing to serial analog-to-digital (A/D) converters
SCI
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffers and 16 register transmit buffers on one SCI
— Advanced error detection and optional parity generation and detection
— Word-length programmable as eight or nine bits
— Separate transmitter and receiver enable bits, and double buffering of data
— Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected,
or a new address byte is received
1.3.3.6
•
•
•
•
•
•
•
Queued Serial Multi-Channel Module (QSMCM)
Peripheral Pin Multiplexing (PPM)
Synchronous serial interface between the microprocessor and an external device
Four internal parallel data sources can be multiplexed through the PPM
— TPU3_A: 16 channels
— TPU3_B: 16 channels
— MIOS14: 12 PWM channels, four MDA channels
— Internal GPIO: 16 general-purpose inputs, 16 general-purpose outputs
Software configurable stream size
Software configurable clock (TCLK) based on system clock
Software selectable clock modes (SPI mode and TDM mode)
Software selectable operation modes
— Continuous mode
— Start-transmit-receive (STR) mode
Software configurable internal modules interconnect (shorting)
MPC561/MPC563 Reference Manual, Rev. 1.2
1-8
Freescale Semiconductor
Overview
1.4
MPC561/MPC563 Optional Features
The following features of the MPC561/MPC563 are optional features and may not appear in certain
configurations:
• 56- or 66-MHz operation (40 MHz is default)
• Code compression (available on MPC562 and MPC564 only)
• 512 Kbytes Flash (available on MPC563 and MPC564 only)
1.5
Comparison of MPC561/MPC563 and MPC555
In Table 1-2, the MPC555 is used as a baseline to compare the high level differences from an early device
offering in the MPC500 family to the MPC561/MPC563.
Table 1-2. Differences Between MPC555 and MPC561/MPC563
Module
MPC555
MPC561/MPC563
CPU Core
BBC
Identical
Basic
Enhanced Code Compression (classes scheme
with 2 Kbytes DECRAM)
Code Compression is available only on
MPC562/MPC564.
L2U
Identical
SRAM
26 Kbytes
32 Kbytes calibration SRAM with overlay
features
Flash
448-Kbyte CMF
(2 modules, 256-Kbyte and 192-Kbyte)
512-Kbyte UC3F (1 module) on MPC563 only.
No Flash on MPC561
USIU
Basic
Enhanced Interrupt Controller
JTAG
Selectable by RCW
Selectable at PORESET
READI
None
New Module (Class 3 Nexus
IEEE-ISTO 5001-1999)
UIMB
QADC64E
Identical
(2)
QSMCM
MIOS
(2) Enhanced
(1) Identical (1)
MIOS1
MIOS14
4 Extra PWMSM
4 Extra MCSM
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
1-9
Overview
Table 1-2. Differences Between MPC555 and MPC561/MPC563 (continued)
Module
•
•
•
•
•
•
•
•
MPC561/MPC563
TouCAN
(2) Identical (3)
TPU3
(2) Identical (2)
DPTRAM
(6 Kbytes) Identical (8 Kbytes)
PPM
1.6
MPC555
—
New Module
Additional MPC561/MPC563 Differences
The MPC561/MPC563 devices are very similar to the MPC555 with the following differences:
— Up to 66 MHz operating frequency (Refer to the applicable electrical characteristics document
for more information.)
— CDR3 technology
— Two power supplies: 5.0-V I/O, 2.6-V external bus signals, 2.6-V internal logic
— New modules: READI, CALRAM, PPM
— Extra TouCAN module, additional 6 Kbytes of SRAM on L-bus (32 Kbytes total) with
CALRAM overlay features, extra 2 Kbytes of DPTRAM (8 Kbytes total)
QADC64E
— GPO on all channel signals in addition to GPI functions
TouCAN, TPU3, QSMCM, UIMB, Core, L2U
— No changes
BBC2
— Enhanced interrupt controller support
— Enhanced exception relocation table
— Branch target buffer
— 2 Kbytes of decompression RAM for code compression. This may also be used as
general-purpose RAM while not used for code compression.
CALRAM (with overlay features)
— New module
— Overlay features allow calibration of Flash-based constants
UC3F (U-bus CDR3 Flash module) on MPC563/MPC564 only
— 512 Kbytes of non-volatile memory (NVM)
— Designed for use in embedded microcontroller (MCU) applications targeted for high speed
read performance and high density byte count requirements
READI
— New module
USIU
— Enhanced interrupt controller
— ENGCLK default frequency
MPC561/MPC563 Reference Manual, Rev. 1.2
1-10
Freescale Semiconductor
Overview
•
•
•
1.7
— READI support
— Reduced data setup time
— Enhanced external burst support
MIOS14
— Four additional PWM channels
— Four additional MCSM timers
DPTRAM (8 Kbytes)
— No functional changes
PPM (peripheral pin multiplexing)
— New module
— Four-to-one multiplexing
— Parallel-to-serial driver (SPI and TDM)
SRAM Keep-Alive Power Behavior
The IRAMSTBY pin provides keep-alive power to RAM when the main power supply is shut down. The
IRAMSTBY pin can be powered directly from a battery using an internal shunt regulator or via a small
battery for standby use. See Figure 1-2.
To Battery
R
To IRAMSTBY Pad
C
Figure 1-2. Recommended Connection Diagram for IRAMSTBY
While power is off, the IRAMSTBY supply powers the following:
• 32-Kbyte CALRAM
• 8-Kbyte DPTRAM module
• 2-Kbyte BBC DECRAM module
NOTE
IRAMSTBY must always be supplied with at least 50µA for correct
operation.
1.8
MPC561/MPC563 Address Map
The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of
eight locations by programming a register in the USIU (IMMR[ISB]). The eight possible locations are the
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
1-11
Overview
first eight 4-Mbyte memory blocks starting with address 0x0000 0000 (refer to Figure 1-3). The
programmability of the internal memory map location allows the user to implement a multiple-chip
system.
0x0000 0000
Internal 4-Mbyte
Memory Block
0x003F FFFF
0x0040 0000
(Can reside in one of
eight locations)
0x007F FFFF
0x0080 0000
0x00BF FFFF
0x00C0 0000
0x00FF FFFF
0x0100 0000
0x013F FFFF
0x0140 0000
0x017F FFFF
0x0180 0000
0x01BF FFFF
0x01C0 0000
0x01FF FFFF
0xFFFF FFFF
Figure 1-3. MPC561/MPC563 Memory Map
The internal memory space is divided into the following sections. Refer to Figure 1-4.
• Flash memory (512-Kbytes)
• CALRAM static RAM memory (32-Kbytes)
• Control registers and IMB3 modules (64 Kbytes)
— BBC control registers (16-Kbytes)
— USIU and Flash control registers (16-Kbytes)
— UIMB interface and IMB3 modules (32-Kbytes)
— CALRAM/READI control registers (256-bytes)
MPC561/MPC563 Reference Manual, Rev. 1.2
1-12
Freescale Semiconductor
Overview
0x00 0000
UC3F Flash*
512 Kbytes
0x07 FFFF
0x08 0000
Reserved for Flash
2,605 Kbytes
0x2F C000
USIU Control Registers
UC3F Control
Registers*
0x2F C800
0x2FC80B
Reserved
0x2F 7FFF
0x2F 8000
0x2F 8800
0x2F A000
0x2F BFFF
0x2F C000
BBC DECRAM 2 Kbytes
Reserved for BBC
BBC CONTROL
DPTRAM Control (32 bytes)
Reserved (8160 bytes)
USIU & Flash Control
16 Kbytes
0x2F FFFF
0x30 0000
UIMB I/F & IMB
0x30 0000
0x30 0020
0x30 2000
DPTRAM (8 Kbytes)
Modules
32 Kbytes
TPU3_A (1 Kbyte)
0x30 7FFF
0x30 8000
Reserved for IMB
480 Kbytes
0x37 FFFF
0x38 0000
0x38 00FF
0x38 0100
0x38 3FFF
0x38 4000
TPU3_B (1 Kbyte)
QADC64E_A (1 Kbyte)
0x30 4000
0x30 4400
0x30 4800
0x30 4C00
CALRAM/
READI Control
256 bytes
QADC64E_B (1 Kbyte)
Reserved (L-bus Control)
16 Kbytes
Reserved (2 Kbytes)
0x30 5400
PPM (64 bytes)
0x30 5C00
Reserved (960 bytes)
0x30 5C80
MIOS14 (4 Kbytes)
0x30 6000
TouCAN_A (1 Kbyte)
0x30 7000
Reserved (L-bus Mem)
464 Kbytes
QSMCM (1 Kbyte)
0x30 5000
0x3F 7FFF
0x3F 8000
0x3F F000
0x3F FFFF
CALRAM
32 Kbytes
TouCAN_B (1 Kbyte)
4-Kbyte Overlay Section
Note: Flash is available only on the
MPC563/MPC564.
0x30 7400
TouCAN_C (1 Kbyte)
0x30 7800
Reserved (896 bytes)
0x30 7900
UIMB Registers
(128 bytes)
0x30 7F80
0x30 7FFF
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
1-13
Overview
Figure 1-4. MPC561/MPC563 Internal Memory Map
1.9
Supporting Documentation List
This list contains references to currently available and planned documentation.
• MPC555 User’s Manual (MPC555UM/AD)
• RCPU Reference Manual (RCPURM/AD)
• Nexus Standard Specification (non-Freescale document) available at: http://www.nexus5001.org/
• IEEE 1149.1 Specification (non-Freescale document)
MPC561/MPC563 Reference Manual, Rev. 1.2
1-14
Freescale Semiconductor
Chapter 2
Signal Descriptions
This chapter describes the MPC561/MPC563 microcontroller’s external signals. It contains a description
of individual signals, shows their behavior, shows whether the signal is an input or an output, and indicates
signal multiplexing.
NOTE
A bar over a signal name indicates that the signal is active-low—for
example, TA (transfer acknowledge). Active-low signals are referred to as
asserted (active) when they are low and negated when they are high. Signals
that are not active-low, such as ADDR[8:31] (address bus signals) and
DATA[0:31] (data bus signals) are referred to as asserted when they are high
and negated when they are low.
Refer to Appendix F, “Electrical Characteristics,” and Appendix G, “66-MHz Electrical Characteristics,”
for detailed electrical information for each signal.
2.1
Signal Groupings
Figure 2-1 illustrates the external signals of the MPC561/MPC563 grouped by functional module.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-1
Signal Descriptions
SGPIOA[8:31] / ADDR[8:31]
SGPIOD[0:31] / DATA[0:31]
Bus
Interface
67 Pins
TSIZ[0:1]
WR / RD
BURST
BDIP
TA
TEA
OE
TEXP / RSTCONF
STS / BI
TS
MDO4 / SGPIOC0 / IRQ0
RSV / SGPIOC1 / IRQ1
Interrupt
Controller
8 Pins
CR / SGPIOC2 / MTS / IRQ2
KR / RETRY / SGPIOC3 / IRQ3
AT2 / SGPIOC4 / IRQ4
MODCK1 / SPGIOC5 / IRQ5
MODCK[2:3] / IRQ[6:7]
FRZ / PTR / SGPIOC6
Development
and Debug
7 Pins
LWP0 / IRQOUT / SGPIOC7
VF0 / LWP1 / BG
VF1 / IWP2 / BR
VF2 / IWP3 / BB
VFLS[0:1] / IWP[0:1]
24
32
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
QADC64E_A
and
QADC64E_B
39 Pins
QSMCM
11 Pins
B_ANw / B_PQB0 / B_AN0
B_ANx/ B_PQB1 / B_AN1
B_ANy/ B_PQB2 / B_AN2
B_ANz / B_PQB3 / B_AN3
B_PQB[4:7] / B_AN[48:51]
B_MA[0:2] / B_PQA[0:2] / B_AN[52:54]
B_PQA[3:7] / B_AN[55:59]
VRH
VRL
ALTREF
VDDA
VSSA
PCS[6:7] / ETRIG[1:2]
SS / QGPIO0 / PCS0
QGPIO[1:3] / PCS[1:3]
QGPIO4 / MISO
QGPIO5 / MOSI
QGPIO6 / SCK
QGPO1 / TXD1
C_CNTX0 /QGPO2 / TXD2
QGPI1 / RXD1
C_CNRX0 / QGPI2 / RXD2
WE[0:3] / BE[0:3] / AT[0:3]
Write Enable
4 Pins
A_CNTX0
A_CNRX0
B_CNTX0
B_CNRX0
TouCAN
4 Pins (plus 2 Pins
multiplexed with
MIOS and QSMCM)
1
1
1
1
1
1
1
1
1
4
3
5
5
5
1
1
1
1
1
3
1
1
1
1
1
1
4
3
5
1
1
1
1
1
2
1
1
1
1
1
3
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
16
1
16
1
EPEE
B0EPEE
VFLASH
VDDF
VSSF
HRESET
PORESET / TRST
SRESET
TCK / DSCK / MCKI
TDI / DSDI / MDI0
TDO / DSDO / MDO0
TMS / EVTI
QVDDL
Global Power Supply
UC3F Flash
EEPROM1
5 Pins
System
Control
3 Pins
JTAG/BDM/READI
5 Pins
JCOMP / RSTI
MDA[11:15]
MDA[27:31]
MPWM0 / MDI1
MPWM1 / MDO2
MPWM2 / PPM_TX1
MPWM3 / PPM_RX1
MPWM16
MPWM[17:19] / MDO[3, 6:7]
MPIO32B0 / MDO1 / VF0
MPIO32B1 / MCKO / VF1
MPIO32B2 / MSEI / VF2
MPIO32B3 / MSEO / VFLS0
MPIO32B4 / VFLS1
MPIO32B5 / MDO5
MPIO32B6 / MPWM4 / MDO6
MPIO32B[7:9] / MPWM[5,20:21]
MPIO32B10 / PPM_TSYNC
MPIO32B11 / C_CNRX0
MPIO32B12 / C_CNTX0
MPIO32B13 / PPM_TCLK
MPIO32B14 / PPM_RX0
MPIO32B15 / PPM_TX0
A_TPUCH[0:15]
A_T2CLK / PCS5
B_TPUCH[0:15]
B_T2CLK / PCS4
VDD
VSS
KAPWR
IRAMSTBY
NVDDL
4
1
1
1
MPC561/563
A_ANw / A_PQB0 / A_AN0
A_ANx/ A_PQB1 / A_AN1
A_ANy/ A_PQB2 / A_AN2
A_ANz / A_PQB3 / A_AN3
A_PQB[4:7] / A_AN[48:51]
A_MA[0:2] / A_PQA[0:2] / A_AN[52:54]
A_PQA[3:7] / A_AN[55:59]
Chip Selects
4 Pins
1
1
1
1
1
1
Configuration
1 Pin
CS[0:3]
1
1
Clocks and
PLL
8 Pins
4
1
1
1
1
1
XTAL
EXTAL
XFC
CLKOUT
EXTCLK
ENGCLK / BUCLK
VDDSYN
VSSSYN
PULL_SEL
VDDH
MIOS14
34 Pins
TPU3 A and B
34 Pins
Note: In cases where one multiplexed signal
is an input and another is an output, together
they are shown as I/O.
1
The MPC561 has no Flash EEPROM
Figure 2-1. MPC561/MPC563 Signal Groupings
MPC561/MPC563 Reference Manual, Rev. 1.2
2-2
Freescale Semiconductor
Signal Descriptions
2.2
Signal Summary
Table 2-1 describes individual MPC561/MPC563 signals, grouped by functional module.
Table 2-1. MPC561/MPC563 Signal Descriptions
Signal Name
No. of
Type
Signals
Function after
Reset1
Description
Bus Interface
I/O
ADDR[8:31] / SGPIOA[8:31]
24
Address Bus [8:31]. Specifies the physical address of the
Controlled by
bus transaction. The address is driven onto the bus and kept
RCW[SC].
valid until a transfer acknowledge is received from the slave.
See Table 6-10. ADDR8 is the MSB for this bus.
I/O
I/O
DATA[0:31] / SGPIOD[0:31]
32
Port SGPIOA[8:31]. Allows the signals to be used as
general-purpose inputs/outputs.
Data Bus [0:31]. Provides the general-purpose data path
Controlled by
between the MPC561/MPC563 and all other devices.
RCW[SC].
Although the data path is a maximum of 32 bits wide, it can
See Table 6-10. be sized to support 8-, 16-, or 32-bit transfers. DATA0 is the
MSB of the data bus.
I/O
Port SGPIOD[0:31]. Allows the signals to be used as
general-purpose inputs/outputs.
TSIZ[0:1]
2
I/O
TSIZ[0:1]
RD/WR
1
I/O
RD/WR
BURST
1
I/O
BURST
Burst Indicator. Driven by the bus master to indicate that the
currently initiated transaction is a burst.
BDIP
1
I/O
BDIP
Burst Data In Progress. Indicates to the slave that there is a
data beat following the current data beat.
TS
TA
1
1
I/O
I/O
TS
TA
Transfer Size [0:1]. Indicates the size of the requested data
transfer in the current bus cycle.
Read/Write. Indicates the direction of the data transfer for a
transaction. A logic one indicates a read from a slave device;
a logic zero indicates a write to a slave device.
Transfer Start. Indicates the start of a bus cycle that
transfers data to/from a slave device. This signal is driven by
the master only when it has gained ownership of the bus.
Every master should negate this signal before relinquishing
the bus.
This is an active-low signal and needs an external pull-up
resistor to ensure proper operation and meet signal timing
specifications.
Transfer Acknowledge. This line indicates that the slave
device addressed in the current transaction has accepted
the data transferred by the master (write) or has driven the
data bus with valid data (read). The slave device negates the
TA signal after the end of the transaction. The slave device
will then immediately three-state the TA signal to prevent
contention on the line in case a new transfer that addresses
another slave device(s) is initiated.
This signal is an active-low signal and needs an external
pull-up resistor to ensure proper operation and conform to
signal timing specifications.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-3
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
TEA
1
I/O
TEA
OE
1
O
OE
RSTCONF / TEXP
I
1
BI / STS
RSTCONF until
reset negates.
Description
Transfer Error Acknowledge. This signal indicates that a bus
error occurred in the current transaction. The
MPC561/MPC563 asserts this signal when the bus monitor
does not detect a bus cycle termination within 2040 clock
cycles. The assertion of TEA causes the termination of the
current bus cycle, regardless of the state of TA.
An external pull-up device is required to negate TEA quickly,
before a second error is detected. That is, the signal must
be pulled up within one clock cycle of the time it was
three-stated by the MPC561/MPC563.
Output Enable. This output line is asserted when a read
access is initiated by the MPC561/MPC563 to an external
slave controlled by the memory controller’s GPCM.
Reset Configuration. This input line is sampled by the
MPC561/MPC563 during the assertion of the HRESET
signal in order to sample the reset configuration. If the line
is asserted, the configuration mode is sampled from the
external data bus. When this line is negated, the
configuration mode adopted by the MPC561/MPC563 is
either the internal default or read from the internal Flash
(MPC563 only).
O
Timer Expired. This output line reflects the status of
PLPRCR[TEXPS] in the USIU. This bit indicates an expired
timer value.
I/O
Burst Inhibit. This bidirectional, active-low, three-state
signal indicates that the slave device addressed in the
current burst transaction is not able to support burst
transfers. When the MPC561/MPC563 drives out the signal
for a specific transaction, it asserts or negates BI according
to the value specified in the appropriate control registers.
The signal is negated after the end of the transaction and
then is immediately three-stated.
This is an active-low signal and needs an external pull-up
resistor to ensure proper operation and signal timing
specifications.
1
O
Controlled by
RCW[DBGC].
See Table 6-8.
Special Transfer Start. This output signal is driven by the
MPC561/MPC563 to indicate the start of a transaction on
the external bus or signals the beginning of an internal
transaction in show cycle mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-4
Freescale Semiconductor
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
Description
Interrupt Controller
Interrupt Request 0. One of the eight external signals that
can request, by means of the internal interrupt controller, a
service routine from the RCPU. IRQ0 is a non-maskable
interrupt (NMI).
I
1
I/O
IRQ0 / SGPIOC0 / MDO4
O
MDO4 if the
Nexus (READI)
port is enabled,
Port SGPIOC0. Allows the signal to be used as a
IRQ0 otherwise.
general-purpose input/output.
See Section 2.5.
READI Message Data Out. Message data out (MDO4) are
output signals used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
rising edge of MCKO. Eight signals are implemented.
Interrupt Request 1. One of the eight external signals that
can request, by means of the internal interrupt controller, a
service routine from the RCPU.
I
IRQ1 / RSV / SGPIOC1
1
IRQ1
O
I/O
Port SGPIOC1. Allows the signal to be used as a
general-purpose input/output.
Interrupt Request 2. One of the eight external signals that
can request, by means of the internal interrupt controller, a
service routine from the RCPU.
I
I
IRQ2 / CR / SGPIOC2 /
MTS2
1
IRQ2
I/O
Cancel Reservation. Instructs the MPC561/MPC563 to
clear its reservation because some other master has
touched its reserved space. An external bus snooper
asserts this signal.
Port SGPIOC2. Allows the signal to be used as a
general-purpose input/output.
O
Memory Transfer Start. This is the transfer start signal from
the MPC561’s memory controller that allows external
memory access by an external bus master.
I
Interrupt Request 3. One of the eight external signals that
can request, by means of the internal interrupt controller, a
service routine from the RCPU.
I/O
IRQ3 / KR / RETRY /
SGPIOC3
Reservation. This signal is used, together with the address
bus, to indicate that the internal core initiated a transfer as a
result of a STWCX or a LWARX instruction.
1
I/O
I/O
IRQ3
Kill Reservation. In case of a bus cycle initiated by a STWCX
instruction issued by the RCPU core to a non-local bus on
which the storage reservation has been lost, this signal is
used by the non-local bus interface to back-off the cycle.
Retry. Indicates to a master that the cycle is terminated but
should be repeated. As an input, it is driven by the external
slave to retry a cycle.
Port SGPIOC3. Allows the signal to be used as a
general-purpose input/output.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-5
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
IRQ4 / AT2 / SGPIOC4
No. of
Type
Signals
1
Function after
Reset1
I
Interrupt Request 4. One of the eight external signals that
can request, by means of the internal interrupt controller, a
service routine from the RCPU.
O
Address Type 2. A bit from the address type bus which
indicates one of the 16 “address types” to which the address
applies. The address type signals are valid at the rising edge
of the clock in which the special transfer start (STS) is
asserted.
IRQ4
I/O
Port SGPIOC4. Allows the signal to be used as a
general-purpose input/output.
I
IRQ5 / MODCK1 / SPGIOC5
1
I
MODCK1 until
reset negates,
then IRQ5
I/O
I
IRQ[6:7] / MODCK[2:3]
2
I
CS[0:3]
WE[0:3] / BE[0:3] / AT[0:3]
4
4
Description
O
O
O
Interrupt Request 5. One of the eight external signals that
can request, by means of the internal interrupt controller, a
service routine from the RCPU.
Mode Clock 1. Sampled at the negation of PORESET/TRST
in order to configure the phase-locked loop (PLL)/clock
mode of operation.
Port SGPIOC5. Allows the signal to be used as a
general-purpose input/output.
MODCK[2:3]
until reset
negates, then
IRQ[6:7]
CS[0:3]
Controlled by
RCW[ATWC].
See Table 6-8.
Interrupt Request [6:7]. One of the eight external signals
that can request, by means of the internal interrupt
controller, a service routine from the RCPU.
Mode Clock [2:3]. Sampled at the negation of
PORESET/TRST in order to configure the PLL/clock mode
of operation.
Chip Select [0:3]. These output signals enable peripheral or
memory devices at programmed addresses if defined
appropriately in the memory controller. CS0 or CS3 can be
configured to be the global chip select for the boot device.
Write Enable[0:3]/Byte Enable[0:3]. This output signal is
asserted when a write access to an external slave controlled
by the memory controller is initiated by the
MPC561/MPC563. It can be optionally asserted on all read
and write accesses. See WEBS bit definition in Table 10-8.
WEn/BEn are asserted when data lanes shown below
contain valid data to be stored by the slave device.
– WE0/BE0 is asserted if the data lane DATA[0:7] contains
valid data to be stored by the slave device.
• WE1/BE1 is asserted if the data lane DATA[8:15]
contains valid data to be stored by the slave device.
• WE2/BE2 is asserted if the data lane DATA[16:23]
contains valid data to be stored by the slave device.
• WE3/BE3 is asserted if the data lane DATA[24:31]
contains valid data to be stored by the slave device.
Address Type [0:3]. Indicates one of the 16 address types to
which the address applies. The address type signals are
valid at the rising edge of the clock in which the special
transfer start (STS) is asserted.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-6
Freescale Semiconductor
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
Description
System Control
I
PORESET /
TRST
PORESET / TRST
1
I
Power-On Reset. This signal should be activated as a result
of a voltage failure on the keep-alive power supply. The
signal has a glitch detector to ensure that low spikes of less
than 20 ns are rejected. The internal PORESET / TRST
signal is asserted only if PORESET / TRST is asserted for
more than 100 ns. See Chapter 7, “Reset,” for more details
on timing.
Test Reset. This input provides asynchronous reset to the
test logic (JTAG).
Hard Reset. The reset controller can detect an external
assertion of HRESET only if it occurs while the
MPC561/MPC563 is not asserting reset. After negation of
HRESET or SRESET is detected, a 16-cycle period is taken
before testing the presence of an external reset.
HRESET
1
I/O
HRESET
The internal HRESET signal is considered asserted only
when assertion lasts for more than 100 ns. To meet external
timing requirements, an external pull-up device is required
to negate HRESET. See Chapter 7, “Reset,” for more details
on timing.
SRESET
1
I/O
SRESET
Soft Reset. The reset controller can detect an external
assertion of SRESET only if it occurs while the
MPC561/MPC563 is not asserting reset. After negation of
HRESET or SRESET is detected, a 16-cycle period is taken
before testing the presence of an external soft reset. To
meet external timing requirements, an external pull-up
device is required to negate SRESET. See Chapter 7,
“Reset,” for more details on timing.
Development and Debug
I/O
SGPIOC6 / FRZ / PTR
1
SGPIOC7 / IRQOUT/ LWP0
1
O
Port SGPIOC6. Allows the signals to be used as
general-purpose inputs/outputs.
PTR
Freeze. Indicates that the RCPU is in debug stopped mode.
O
Program Trace. Indicates an instruction fetch is taking place
(for program flow tracking).
I/O
Port SGPIOC7. Allows the signal to be used as
general-purpose inputs/outputs.
O
O
LWP0
Interrupt Out. Indicates that an interrupt has been requested
to all external devices.
Load/Store Watchpoint 0. This output signal reports the
detection of a data watchpoint in the program flow executed
by the RCPU. See Chapter 23, “Development Support,” for
more details.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-7
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
Bus Grant. Indicates external bus status. BG is asserted low
when the external bus arbiter grants ownership of the
external bus to a specific master. This is an active-low signal
and needs an external pull-up resistor to ensure proper
operation and meet signal timing specifications.
I/O
BG / VF0 / LWP1
1
O
Controlled by
RCW[DBGC].
See Table 6-8.
Bus Request. Indicates that the external bus has been
requested for external cycle. This is an active-low signal and
needs an external pull-up resistor to ensure proper
operation and meet signal timing specifications.
I/O
1
O
Controlled by
RCW[DBGC].
See Table 6-8.
O
IWP[0:1] / VFLS[0:1]
1
O
Visible Instruction Queue Flush Status 1. This output signal
together with VF0 and VF2 is output by the
MPC561/MPC563 when program instruction flow tracking is
required. VFs report the number of instructions flushed from
the instruction queue in the internal core. See Chapter 23,
“Development Support,” for more details.
Instruction Watchpoint 2. This output signal reports the
detection of an instruction watchpoint in the program flow
executed by the RCPU.
Bus Busy. Indicates that the master is using the external
bus. BB is an active-low signal and needs an external
pull-up resistor to ensure proper operation and signal timing
specifications.
I/O
BB / VF2 / IWP3
Visible Instruction Queue Flush Status 0. This output signal
together with VF1 and VF2 is output by the
MPC561/MPC563 when program instruction flow tracking is
required. VFs report the number of instructions flushed from
the instruction queue in the internal core. See Chapter 23,
“Development Support,” for more details.
Load/Store Watchpoint 1. This output signal reports the
detection of a data watchpoint in the program flow executed
by the RCPU.
O
BR / VF1 / IWP2
Description
Controlled by
RCW[DBGC].
See Table 6-8
Visible Instruction Queue Flush Status 2. This output signal
together with VF0 and VF1 is output by the
MPC561/MPC563 when a program instructions flow
tracking is required. VFs report the number of instructions
flushed from the instruction queue in the internal core.
O
Instruction Watchpoint 3. This output signal reports the
detection of an instruction watchpoint in the program flow
executed by the internal core.
O
Instruction Watchpoint [0:1]. These output signals report the
detection of an instruction watchpoint in the program flow
executed by the RCPU.
2
O
Controlled by
RCW[DBGC].
See Table 6-8.
Visible History Buffer Flush Status [0:1]. These signals are
output by the MPC561/MPC563 to enable program
instruction flow tracking. They report the number of
instructions flushed from the history buffer in the RCPU. See
Chapter 23, “Development Support,” for details.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-8
Freescale Semiconductor
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
Description
JTAG/BDM/READI
I
TMS / EVTI
1
I
TMS unless the
Nexus (READI)
port is enabled,
then EVTI.
See Section 2.5.
I
I
TDI / DSDI / MDI0
1
I
1
I
I
DSDI unless the
Nexus (READI)
port (MDI0) or
JTAG mode
(TDI) is enabled.
See Section 2.5.
DSCK unless
the Nexus
(READI) port
(MCKI) or JTAG
mode (TCK) is
enabled.
See Section 2.5.
O
TDO / DSDO / MDO0
1
O
O
JCOMP / RSTI
1
I
I
EVTI. Event in (EVTI) is level sensitive when configured for
breakpoint generation, otherwise it is edge sensitive.
Test Data In. This input is used for serial test instructions
and test data for on-board test logic (JTAG).
I
TCK / DSCK / MCKI
Test Mode Select. This input controls test mode operations
for on-board test logic (JTAG).
DSDO unless
the Nexus
(READI) port
(MDO0) or JTAG
mode (TDO) is
enabled.
See Section 2.5.
Development Serial Data Input. This input signal is the data
in for the debug port interface. See Chapter 23,
“Development Support,” for details.
Message Data In. MDI0 is a Nexus input signal used for
downloading configuration information, writes to user
resources, and so forth. Internal latching of MDI occurs on
the rising edge of MCKI.
Test Clock. This input provides a clock for on-board test logic
(JTAG).
Development Serial Clock. This input signal is the clock for
the debug port interface. See Chapter 23, “Development
Support,” for details.
Message Clock In. This input line is the input clock to the
READI module for the Nexus message clock input.
Test Data Out. This output is used for serial test instructions
and test data for on-board test logic (JTAG).
Development Serial Data Output. This output signal is the
data-out line of the debug port interface. See Chapter 23,
“Development Support,” for details.
READI Message Data Out. Message data out: MDO0 is an
output signal used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
rising edge of MCKO. Eight MDO signals are implemented.
JTAG Compliancy. This signal enables the IEEE1149.1
JTAG compliant circuitry in the MPC561/MPC563.
See Section 2.5. 0 JTAG disabled
1 JTAG enabled
RSTI. Reset input for the Nexus port.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-9
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
Description
Clocks and PLL
XTAL
1
O
XTAL
XTAL. This output signal is one of the connections to an
external crystal for the internal oscillator circuitry.
EXTAL
1
I
EXTAL
EXTAL. This signal is one of the connections to an external
crystal for the internal oscillator circuitry. If EXTAL is unused,
it must be grounded.
XFC
1
I
XFC
External Filter Capacitance. This input signal is the
connection for an external capacitor filter for the PLL
circuitry.
Clock Out. This output signal is the clock system frequency.
The CLKOUT drive strength can be configured to full
strength, half strength, quarter strength, or disabled. The
drive strength is configured using the COM[0:1] bits and
CQDS bits in the SCCR register in the USIU.
CLKOUT
1
O
CLKOUT
EXTCLK
1
I
EXTCLK
EXTCLK. This is the external frequency source for the
MPC561/MPC563. If EXTCLK is unused, it must be
grounded.
O
ENGCLK / BUCLK
1
ENGCLK (2.6
V)
O
ENGCLK. This is the engineering clock output. Drive voltage
can be configured to 2.6 V, 5 V (with slew-rate control), or
disabled. The drive voltage is configured using the
EECLK[0:1] bits in the SCCR register in the SIU.
BUCLK. When the MPC561/MPC563 is in limp mode, it is
operating from a less precise on-chip ring oscillator to allow
the system to continue minimum functionality until the
system clock is fixed. This backup clock can be seen
externally if selected by the values of the EECLK[0:1] bits in
the SCCR register in the USIU.
VDDSYN
1
I
VDDSYN
VDDSYN. This is the power supply of the PLL circuitry.
VSSSYN
1
I
VSSSYN
VSSSYN. This is the ground reference of the PLL circuitry.
Configuration
PULL_SEL3
1
I
PULL_SEL
Pull Select. PULL_SEL determines whether the pull devices
on the MIOS and TPU signals are pull-ups or pull-downs.
When pull-ups are selected, the pull-ups are to 5.0 V except
the following MIOS signals will be pulled to 2.6V:
VF[0:2]/MPIO32B[0:2], VFLS[0:1]/MPIO32B[3:4], and
MDO[7:4]/MPIO32B[7:10]. When this pin is low, pull-downs
are selected.
TouCAN
A_CNTX0
1
O
A_CNTX0
TouCAN_A Transmit Data. This signal is the serial data
output.
A_CNRX0
1
I
A_CNRX0
TouCAN_A Receive Data. This signal is the serial data
input.
B_CNTX0
1
O
B_CNTX0
TouCAN_B Transmit Data. This signal is the serial data
output.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-10
Freescale Semiconductor
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
B_CNRX0
No. of
Type
Signals
1
I
Function after
Reset1
B_CNRX0
Description
TouCAN_B Receive Data. This signal is the serial data
input.
UC3F Flash4
EPEE. This external program/erase enable control signal
externally controls the program or erase operations. When
held low, program or erase operations on the entire internal
Flash module are disabled. Available in the MPC563 only.
This signal is not connected on the MPC561.
EPEE4
1
I
EPEE
B0EPEE4
1
I
B0EPEE
VFLASH4
1
I
VFLASH
VFLASH. Flash supply voltage (5-V supply) used during all
operations of the UC3F. Available in the MPC563 only. This
signal is not connected on the MPC561.
VDDF4
1
I
VDDF
VDDF. Flash core voltage input (2.6-V supply). Available in
the MPC563 only. This signal should be connected to VDD,
preferably directly to a 2.6V plane on the circuit board. This
signal is not connected on the MPC561.
VSSF4
1
I
VSSF
VSSF. Flash core ground reference. Available in the
MPC563 only. This signal is not connected on the MPC561.
B0EPEE. This control signal externally controls the program
or erase operations on block 0 of the internal Flash. When
held low, program or erase operations on block 0 only are
disabled. Available in the MPC563 only. This signal is not
connected on the MPC561.
QADC64E_A and QADC64E_B
ETRIG[1:2] / PCS[6:7]
A_AN0 / A_ANw / A_PQB0
2
1
I
ETRIG[1:2]
O
PCS[6:7]. This signals provide QSPI peripheral chip select
when the enhanced PCS mode is selected.
I
Analog Channel 0. Internally multiplexed input-only analog
channel. Passed on as a separate signal to the QADC64E.
I
A_AN0
Multiplexed Analog Input (A_ANw). Externally multiplexed
analog input.
Port A_PQB0. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
I/O5
A_AN1 / A_ANx/ A_PQB1
ETRIG[1:2]. These are the external trigger inputs to the
QADC64E_A and QADC64E_B modules. ETRIG1 can be
configured to be used by both QADC64E_A and
QADC64E_B. Likewise, ETRIG2 can be used by both
QADC64E_B and QADC64E_A. The trigger input signals
are associated with the scan queues.
I
Analog Channel 1. Internally multiplexed input-only analog
channel. Passed on as a separate signal to the QADC64E.
I
Multiplexed Analog Input (A_ANx). Externally multiplexed
analog input.
1
A_AN1
I/O5
Port A_PQB1. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-11
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
Analog Channel 2. Internally multiplexed input-only analog
channel. The input is passed on as a separate signal to the
QADC64E.
I
A_AN2 / A_ANy/ A_PQB2
A_AN3 / A_ANz / A_PQB3
1
1
I
A_AN2
Port A_PQB2. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
I
Analog Input 3. Internally multiplexed input-only analog
channel. The input is passed on as a separate signal to the
QADC64E.
I
A_AN3
4
Analog Input [48:51]. Analog input channel. The input is
passed on as a separate signal to the QADC64E.
AN[48:51]
I/O5
I
3
I
A_AN[52:54]
Analog Input [55:59]. Input-only. These inputs are passed on
as separate signals to the QADC64E.
A_AN[55:59]
I/O
I
B_AN0 / B_ANw / B_PQB0
1
I
I/O
Multiplexed Address [0:2] for QADC64E Module A. Provides
a three-bit multiplexed address output to the external
multiplexer chip to allow selection of one of the eight inputs.
Port A_PQA[0:2]. This is a bidirectional general-purpose
I/O.
I
5
Port A_PQB[4:7]. This is a bidirectional general-purpose I/O
if the QADC64E is configured in enhanced mode, otherwise
it is an input only.
Analog Input [52:54]. Input-only. These inputs are passed on
as separate signals to the QADC64E.
I/O
A_AN[55:59] / A_PQA[3:7]
Multiplexed Analog Input (A_ANz). Externally multiplexed
analog input.
Port A_PQB 3. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
I
A_AN[52:54] / A_MA[0:2] /
A_PQA[0:2]
Multiplexed Analog Input (A_ANy). Externally multiplexed
analog input.
I/O5
I/O5
A_AN[48:51] / A_PQB[4:7]
Description
Port A_PQA[3:7]. This is a bidirectional general-purpose
I/O.
Analog Channel 0. Internally multiplexed input-only analog
channel. Passed on as a separate signal to the QADC64E.
B_AN0
Multiplexed Analog Input (B_ANw). Externally multiplexed
analog input.
Port B_PQB0. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-12
Freescale Semiconductor
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
I
B_AN1 / B_ANx/ B_PQB1
B_AN2 / B_ANy/ B_PQB2
B_AN3 / B_ANz / B_PQB3
1
1
1
I
Analog Channel 1. Internally multiplexed input-only analog
channel. Passed on as a separate signal to the QADC64E.
B_AN1
Port B_PQB1. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
I
Analog Channel 2. Internally multiplexed input-only analog
channel. The input is passed on as a separate signal to the
QADC64E.
I
B_AN2
Port B_PQB2. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
I
Analog Input 3. Internally multiplexed input-only analog
channel. The input is passed on as a separate signal to the
QADC64E.
I
4
B_AN3
B_AN[48:51]
Analog Input [52:54]. These inputs are passed on as
separate signals to the QADC64E.
B_AN[52:54]
I/O
5
Multiplexed Address [0:2] for QADC64E Module A. Provides
a three-bit multiplexed address output to the external
multiplexer chip to allow selection of one of the eight inputs.
Port B_PQA[0:2]. This is a bidirectional general-purpose
I/O.
I
B_AN[55:59] / B_PQA[3:7]
Analog Input [48:51]. Analog input channel. The input is
passed on as a separate signal to the QADC64E.
Port B_PQB[4:7]. This is a bidirectional general-purpose I/O
if the QADC64E is configured in enhanced mode, otherwise
it is an input only.
I
I
Multiplexed Analog Input (B_ANz). Externally multiplexed
analog input.
Port B_PQB3. This is a bidirectional general-purpose I/O if
the QADC64E is configured in enhanced mode, otherwise it
is an input only.
I/O
3
Multiplexed Analog Input (B_ANy). Externally multiplexed
analog input.
I/O
I
B_AN[52:54] / B_MA[0:2] /
B_PQA[0:2]
Multiplexed Analog Input (B_ANx). Externally multiplexed
analog input.
I/O
I/O
B_AN[48:51] / B_PQB[4:7]
Description
B_AN[55:59]
I/O
Analog Input [55:59]. These inputs are passed on as
separate signals to the QADC64E.
Port B_PQA[3:7]. This is a bidirectional general-purpose
I/O.
VRH
1
I
VRH
VRH. Input signal for high reference voltage for the
QADC64E_A and QADC64E_B modules.
VRL
1
I
VRL
VRL. Input signal for low reference voltage for the
QADC64E_A and QADC64E_B modules.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-13
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
Description
ALTREF
1
I
ALTREF
ALTREF. Input signal for alternate reference voltage for the
QADC64E_A and QADC64E_B modules.
VDDA
1
I
VDDA
VDDA. Power supply input to analog subsystems of the
QADC64E_A and QADC64E_B modules.
VSSA
1
I
VSSA
VSSA. Ground level for analog subsystems of the
QADC64E_A and QADC64E_B modules.
QSMCM
I/O
PCS0. This signal provides QSPI peripheral chip select 0 for
the QSMCM module.
I/O
PCS0 / SS / QGPIO0
QGPIO0
1
Port QGPIO0. When this signal is not needed for a QSPI
application it can be configured as a general-purpose
input/output.
I/O
I/O
PCS[1:3] / QGPIO[1:3]
MISO / QGPIO4
MOSI / QGPIO5
3
PCS[1:3]. These signals provide QSPI peripheral chip
selects for the QSMCM module.
QGPIO[1:3]
I/O
Port QGPIO[1:3]. When these signals are not needed for
QSPI applications they can be configured as
general-purpose input/outputs.
I/O
Master-In Slave-Out (MISO). This bidirectional signal is the
serial data input to the QSPI in master mode, and serial data
output from the QSPI in slave mode.
QGPIO4
1
I/O
Port QGPIO4. When this signal is not needed for a QSPI
application it can be configured as a general-purpose
input/output.
I/O
Master-Out Slave-In (MOSI). This bidirectional signal is the
serial data output from the QSPI in master mode and serial
data input to the QSPI in slave mode.
QGPIO5
1
I/O
1
I/O
QGPIO6
O
TXD1 / QGPO1
1
O
Port QGPIO5. When this signal is not needed for a QSPI
application it can be configured as a general-purpose
input/output.
SCK. This bidirectional signal is the clock from the QSPI in
master mode or is the clock to the QSPI in slave mode.
I/O
SCK / QGPIO6
SS. Assertion of this bidirectional signal places the QSPI in
slave mode.
Port QGPIO6 for the QSMCM module. When this signal is
not needed for a QSPI application it can be configured as a
general-purpose input/output. When the QSPI is enabled for
serial transmitting, the signal cannot function as a GPIO.
Transmit Data 1. This is the serial data output from the SCI1.
QGPO1
Port QGPO 1. When these signals are not needed for SCI
applications, they can be configured as general-purpose
outputs. When the transmit enable bit in the SCI control
register is set to a logic 1, these signals cannot function as
general-purpose outputs.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-14
Freescale Semiconductor
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
TXD2 / QGPO2 / C_CNTX06
No. of
Type
Signals
1
Function after
Reset1
O
Transmit Data 2. This is the serial data output from the SCI2
O
Port QGPO 2. When this signal is not needed for SCI
applications it can be configured as general-purpose output.
When the transmit enable bit in the SCI control register is set
to a logic 1, this signal cannot function as a general-purpose
output.
QGPO2
O
TouCAN Transmit Data. This signal is the serial data output
for the TouCAN_C module.
I
Receive Data 1. This input signal is the serial data input to
the SCI.
RXD1 / QGPI1
Port QGPI 1. When this signal is not needed for SCI
applications, it can be configured as a general-purpose
input. When the receive enable bit in the SCI control register
is set to a logic 1, this signal cannot function as a
general-purpose input.
QGPI1
1
I
I
RXD2 / QGPI2 / C_CNRX06
1
Description
I
Receive Data 2. This input signal provides serial data input
to the SCI2.
Port QGPI 2. When this signal is not needed for SCI
applications it can be configured as a general-purpose
input. When the receive enable bit in the SCI control register
is set to a logic 1, this signal cannot function as a
general-purpose input.
QGPI2
TouCAN Receive Data. This is the serial data input signal for
the TouCAN_C module.
I
MIOS14
MDA[11:15, 27:31]
MPWM0 / MDI1
10
I/O
MDA[11:15,
27:31]
I/O
MPWM0 unless
the Nexus
(READI) port is
enabled, then
MDI1.
See Section 2.5.
1
I
Double Action. These 10 signals provide paths for two 16-bit
input captures and two 16-bit output compares.
Clock and Load inputs:
• MDA11 can provide clock inputs to the modulus counter
submodule, MMCSM6
• MDA12 can provide load inputs to the modulus counter
submodule, MMCSM6
• MDA13 can provide clock inputs to MMCSM22
• MDA14 can provide load inputs to MMCSM22
• MDA27 can provide clock inputs to MMCSM23
• MDA28 can provide load inputs to MMCSM23
• MDA30 can provide clock inputs to MMCSM7
• MDA31 can provide load inputs to MMCSM7
Pulse Width Modulation 0. This signal provides variable
pulse width outputs at a wide range of frequencies.
Message Data In. MDI1 is a Nexus input signal used for
downloading configuration information, writes to user
resources, etc. Internal latching of MDI will occur on rising
edge of MCKI.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-15
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
I/O
MPWM1 / MDO2
1
MPWM2 / PPM_TX1
1
O
Function after
Reset1
MPWM1 unless
the Nexus
(READI) port is
enabled, then
MDO2.
See Section 2.5.
I/O
MPWM2
O
1
MPWM3
I
MPWM16
MPWM17 / MDO3
1
MPWM16
I/O
MPWM17
unless the
Nexus (READI)
port is enabled.
See Section 2.5.
O
I/O
MPWM[18:19] / MDO[6:7]
2
MPWM[18:19]
O
READI Message Data Out. Message data out (MDO2) is an
output signal used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
the rising edge of MCKO. Eight MDO signals are
implemented.
Pulse Width Modulation 2. This signal provides a variable
pulse width output signal at a wide range of frequencies.
Pulse Width Modulation 3. This signal provides a variable
pulse width output signal at a wide range of frequencies.
PPMRX1. Receive data to the PPM channel number 1.
I/O
1
Pulse Width Modulation 1. This signal provides a variable
pulse width output signal at a wide range of frequencies.
PPMTX1. Transmit data from PPM channel number 1.
I/O
MPWM3 / PPM_RX1
Description
Pulse Width Modulation 16. This signal provides a variable
pulse width output at a wide range of frequencies.
Clock Input: MPWM16 can provide a clock input to modulus
clock submodule, MMCSM8
Pulse Width Modulation 17. This signal provides variable
pulse width outputs at a wide range of frequencies.
Load Input: PWM17 can provide a load input to modulus
clock submodule, MMCSM8
READI Message Data Out. Message data out (MDO3) is an
output signal used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
rising edge of MCKO. Eight MDO signals are implemented.
Pulse Width Modulation [18:19]. These signals provide
variable pulse width output signals at a wide range of
frequencies.
Clock and Load Input:
• MPWM18 can provide clock inputs to modulus counter
submodule MMCSM24
• MPWM19 can provide load inputs to modulus counter
submodule MMCSM24
READI Message Data Out. Message data out (MDO[6:7])
are output signals used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
rising edge of MCKO. Eight MDO signals are implemented.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-16
Freescale Semiconductor
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
I/O
MPIO32B0 / VF0 / MDO1
1
O
MIOS14 GPIO 0. Allows the signals to be used as
general-purpose inputs/outputs.
MPIO32B0
unless the
Nexus (READI)
port is enabled,
then MDO1.
See Section 2.5.
I/O
1
O
MIOS14 GPIO 1. Allows the signals to be used as
general-purpose inputs/outputs.
MPIO32B1
unless the
Nexus (READI)
port is enabled,
then
MCKO.
See Section 2.5.
I/O
MPIO32B2 / VF2 / MSEI
1
I
Visible Instruction Queue Flush Status 1. These signals
output by the MPC561/MPC563 when program instruction
flow tracking is required. VF reports the number of
instructions flushed from the instruction queue in the
internal core. VF signals are also multiplexed with the
development and debug signals VF0 / LWP1 / BG, VF1 /
IWP2 / BR, and VF2 / IWP3 / BB.
MCKO. Message clock-out (MCKO) is a free-running output
clock to development tools for timing of MDO and MSEO
signal functions. MCKO is the same as the
MPC561/MPC563 system clock.
O
O
Visible Instruction Queue Flush Status 0. These signals
output by the MPC561/MPC563 when program instruction
flow tracking is required. VF reports the number of
instructions flushed from the instruction queue in the
internal core. VF signals are also multiplexed with the
development and debug signals VF0 / LWP1 / BG, VF1 /
IWP2 / BR, and VF2 / IWP3 / BB.
READI Message Data Out. Message data out (MDO1) is an
output signal used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
rising edge of MCKO. Eight MDO signals are implemented.
O
MPIO32B1 / VF1 / MCKO
Description
MIOS14 GPIO 2. Allows the signals to be used as
general-purpose inputs/outputs.
MPIO32B2
unless the
Nexus (READI)
port is enabled,
then MSEI.
See Section 2.5.
Visible Instruction Queue Flush Status 2. These signals
output by the MPC561/MPC563 when program instruction
flow tracking is required. VF reports the number of
instructions flushed from the instruction queue in the
internal core. VF signals are also multiplexed with the
development and debug signals VF0 / LWP1 / BG, VF1 /
IWP2 / BR, and VF2 / IWP3 / BB.
MSEI. Message Start/End Input. The MSEI input is a Nexus
input signal that indicates when a message on the MDI
signals has started, when a variable length packet has
ended, and when the message has ended. Internal latching
of MSEI occurs on rising edge of MCKI.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-17
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
I/O
O
MPIO32B3 / VFLS0 / MSEO
2
MIOS14 GPIO 3. Allows the signal to be used as a
general-purpose input/output.
MPIO32B3
unless the
Nexus (READI)
port is enabled.
See Section 2.5.
I/O
1
MIOS14 GPIO 4. Allows the signal to be used as a
general-purpose input/output.
MPIO32B4
O
I/O
MPIO32B5 / MDO5
1
O
I/O
MPIO32B6 / MPWM4 /
MDO6
1
I/O
MIOS14 GPIO 5. Allows the signal to be used as a
general-purpose input/output.
MPIO32B6
unless the
Nexus (READI)
port is enabled,
then MDO6.
See Section 2.5.
MIOS14 GPIO 6. Allows the signal to be used as
general-purpose input/output.
I/O
3
MPIO32B[7:9]
I/O
1
MPIO32B11 / C_CNRX06
1
O
Pulse Width Modulation 4. These signals provide variable
pulse width outputs at a wide range of frequencies.
READI Message Data Out. Message data out (MDO6) is an
output signal used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
rising edge of MCKO. Eight MDO signals are implemented.
Pulse Width Modulation [5, 20:21]. These signals provide
variable pulse width outputs at a wide range of frequencies.
MIOS14 GPIO 10. This function allows the signals to be
used as general-purpose inputs/outputs.
MPIO32B10
I/O
MPIO32B11
I
READI Message Data Out. Message data out (MDO5) is an
output signal used for uploading OTM, BTM, DTM, and
read/write accesses. External latching of MDO occurs on
rising edge of MCKO. Eight MDO signals are implemented.
MIOS14 GPIO[7:9]. Allows these signals to be used as
general-purpose input/outputs.
I/O
MPIO32B10 / PPM_TSYNC
Visible History Buffer Flush Status 1. This signal is output by
the MPC561/MPC563 to allow program instruction flow
tracking. It reports the number of instructions flushed from
the history buffer in the RCPU. See Chapter 23,
“Development Support,” for details.
MPIO32B5
unless the
Nexus (READI)
port is enabled,
then MDO5.
See Section 2.5.
O
MPIO32B[7:9] /
MPWM[5, 20:21]
Visible History Buffer Flush Status 0. This signal is output by
the MPC561/MPC563 to allow program instruction flow
tracking. It reports the number of instructions flushed from
the history buffer in the RCPU. See Chapter 23,
“Development Support,” for details.
MSEO. Message start/end out (MSEO) is an output signal
which indicates when a message on the MDO signals has
started, when a variable length packet has ended, and when
the message has ended. External latching of MSEO occurs
on rising edge of MCKO.
O
MPIO32B4 / VFLS1
Description
PPM_TSYNC. Synchronizes the data between the PPM and
peripheral devices.
MIOS14 GPIO 11. This function allows the signals to be
used as general-purpose inputs/outputs.
TouCAN_C Receive Data. This is the serial data input signal
for the TouCAN_C module.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-18
Freescale Semiconductor
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
I/O
MPIO32B12 / C_CNTX06
1
MIOS14 GPIO 12. This function allows the signals to be
used as general-purpose inputs/outputs.
MPIO32B12
O
TouCAN_C Transmit Data. This is the serial data output
signal for the TouCAN_C module.
I/O
MPIO32B13 / PPM_TCLK
1
MIOS14 GPIO 13. This function allows the signals to be
used as general-purpose inputs/outputs.
MPIO32B13
O
PPM_TCLK. PPM bus clock
I/O
MPIO32B14 / PPM_RX0
1
MIOS14 GPIO 14. This function allows the signals to be
used as general-purpose inputs/outputs.
MPIO32B14
I
PPM_RX0. Receive data to the PPM channel number 0.
I/O
MPIO32B15 / PPM_TX0
1
Description
MIOS14 GPIO 15. This function allows the signals to be
used as general-purpose inputs/outputs.
MPIO32B15
O
PPM_TX0. Transmit data from PPM channel number 0.
TPU
A_TPUCH[0:15]
16
I/O
A_TPUCH[0:15] Provides TPU module A with 16 input/output programmable
timed events.
I/O
A_T2CLK / PCS5
1
A_T2CLK
O
B_TPUCH[0:15]
16
I/O
PCS5. This signal provides QSPI peripheral chip select
when the enhanced PCS mode is selected.
B_TPUCH[0:15] Provides TPU module B with 16 input/output programmable
timed events.
I/O
B_T2CLK / PCS4
1
This signal is used to clock or gate the timer count register
2 (TCR2) within the TPU module A. This signal is an
output-only in special test mode.
B_T2CLK
O
This signal is used to clock or gate the timer count register
2 (TCR2) within the TPU module B. This signal is an
output-only in special test mode.
PCS4. This signal provides QSPI peripheral chip select
when the enhanced PCS mode is selected.
Global Power
NVDDL
1
I
NVDDL
NVDDL. Noisy 2.6-V voltage supply input. This signal
supplies the final output stage of the 2.6-V pad output
drivers. The NVDDL and QVDDL supplies should be
connected to the same power supply in a user's system.
QVDDL
1
I
QVDDL
QVDDL. Quiet 2.6-V voltage supply input. This signal
supplies all pad logic and pre-driver circuitry, except for the
final output stage of the 2.6-V pad output drivers.
The NVDDL and QVDDL supplies should be connected to
the same power supply in a user's system.
VDDH
1
I
VDDH
VDDH. 5-V voltage supply input.
VDD
1
I
VDD
VDD. 2.6-V voltage supply input for internal logic.
KAPWR
1
I
KAPWR
Keep-Alive Power. 2.6-V voltage supply input for the
oscillator and keep-alive registers.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-19
Signal Descriptions
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signal Name
No. of
Type
Signals
Function after
Reset1
Description
VSS
1
I
VSS
VSS. Zero supply/ground level for internal logic/external
bus.
IRAMSTBY
1
I
IRAMSTBY
SRAM Keep-Alive Power. This is an input current source for
an internal regulator that supplies voltage to all SRAM
modules in standby mode. This pad connects through a
voltage regulator and a voltage switch to the following
modules: CALRAM (32-Kbyte SRAM), DPTRAM (8-Kbyte
SRAM), BBC DECRAM (2-Kbyte vocabulary SRAM).
1
2
3
4
5
6
This is the function after PORESET/TRST and HRESET.
This signal also included the MDO5 function on the K27S mask set of the MPC561.
This signal was ECK on K27S mask set of MPC561.
Only the MCP563/MPC564 have Flash memory.
The input only applies in legacy mode.
C_CNTX0 and C_CNRX0 can be shared either with the MIOS14 GPIO pins (MPIO32B12, MPIO32B11) or with the QSMCM
SC12 pins (TXD2 / QGPO2, RXD2 / QGPI2). The selection is made by the TCNC bits in the PDMCR2 register. Refer to
Section 2.4, “Pad Module Configuration Register (PDMCR2).”
2.2.1
MPC561/MPC563 Signal Multiplexing
Table 2-2 describes the signal multiplexing that occurs between different modules of the
MPC561/MPC563. Most of the signal functions are controlled by the PDMCR2 register.
Table 2-2. MPC561/MPC563 Signal Sharing
Signal Name
Module Sharing
C_CNTX0/MPIO32B12,
C_CNRX0/MPIO32B11
TouCAN shared with MIOS14 GPIO
TXD2/QGPO2/C_CNTX0
RXD2/QGPI2/C_CNRX0
TouCAN shared with QSMCM SCI2
MPIO32B5/MDO5
READI submodule shared with MIOS14 GPIO
MPIO32B6/MPWM4,
MPIO32B7/MPWM5,
MPIO32B8/MPWM20,
MPIO32B9/MPWM21
MIOS14 PWM submodule shared with MIOS14 GPIO
VF0/MPIO32B0/MDO1,
VF1/MPIO32B1/MCKO,
VF2/MPIO32B2/MSEI,
VFLS0/MPIO32B3/MSEO
Debug pins shared with MIOS14 GPIO and READI
MPIO32B13/PPM_TCLK
MPIO32B14/PPM_RX0
MPIO32B15/PPM_TX0
PPM submodule shared with MIOS14 GPIO
MPWM2/PPM_TX1
MPWM3/PPM_RX1
PPM submodule shared with MIOS14 PWM submodule
MPC561/MPC563 Reference Manual, Rev. 1.2
2-20
Freescale Semiconductor
Signal Descriptions
Table 2-2. MPC561/MPC563 Signal Sharing (continued)
Signal Name
Module Sharing
MPWM0/MDI1,
MPWM1/MDO2,
MPWM17/MDO3,
MPWM[18:19]/MDO[6:7]
B_T2CLK/PCS4
A_T2CLK/PCS5
TPU3 modules shared with QSMCM module.
ETRIG1/PCS6
ETRIG2/PCS7
2.2.2
READI submodule shared with MIOS14 PWM submodule
QADC64E modules shared with QSMCM module.
READI Port Signal Sharing
Table 2-3 and Table 2-4 show the signal functionality of the READI signals when the Nexus port is in
reduced port mode and full port mode.
.
Table 2-3. Reduced and Full Port Mode Pads
Functionality in Reduced
Port Mode
Pad Name
Functionality When Not in
Reduced Port Mode
TDI/DSDI/MDI01
MDI0
TDI/DSDI
TDO/DSDO/MDO0
MDO0
TDO/DSDO2
VF0/MPIO32B0/MDO1
MDO1
VF0/MPIO32B03
VF1/MPIO32B1/MCKO
MCKO
VF1/MPIO32B13
VF2/MPIO32B2/MSEI
MSEI
VF2/MPIO32B23
VFLS0/MPIO32B3/MSEO
MSEO
VFLS0/MPIO32B34
1
TDI in JTAG mode, DSDI in BDM mode.
TDO in JTAG mode, DSDO in BDM mode.
3 Selected by the VF bit in the MIOS14TPCR.
4
Selected by the VFLS bit in the MIOS14TPCR.
2
Table 2-4. Full Port Only Mode Pads
Functionality in Full Port
Mode
Pad Name
Functionality when not in
Full Port Mode
MPWM0/MDI1
MDI1
MPWM0
MPWM1/MDO2
MDO2
MPWM1
MPWM17/MDO3
MDO3
MPWM17
IRQ0/SGPIOC0/MDO4
MDO4
IRQ0/SGPIOC0
MPIO32B5/MDO5
MDO5
MPIO32B5
MPIO32B6 / MPWM4 / MDO6
MDO61
MPIO32B6/MPWM4
1
MPWM18/MDO6
MDO6
MPWM18
MPWM19/MDO7
MDO7
MPWM19
1
The MDO6 bit in the PDMCR2 register determines where the MDO6 signal is available.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-21
Signal Descriptions
2.3
Pad Module Configuration Register (PDMCR)
Bits in the PDMCR (which resides in the SIU memory map) control the slew rate and weak
pull-up/pull-down characteristics of some signals; refer to Appendix F, “Electrical Characteristics.” The
PORESET/TRST signal resets all the PDMCR bits asynchronously.
MSB
0
1
Field
2
3
4
5
SLRC
6
7
8
9
10
PRDS SPRDS T2CLK_PU
HRESET
11
12
13
14
PULL_DIS
15
—
0000_0000_0000_0000
Addr
0x2F C03C
LSB
16
17
18
19
20
21
22
23
Field
24
25
26
27
28
29
30
31
—
HRESET
0000_0000_0000_0000
Figure 2-2. Pads Module Configuration Register (PDMCR)
Table 2-5 contains bit descriptions for the PDMCR.
Table 2-5. PDMCR Field Descriptions
Bits
Name
Description
SLRC0 controls the slew rate of signals on the following modules: TPU3, QADC64E, SGPIOA,
SGPIOD, SGPIOC. For the slew rate refer to Appendix F, “Electrical Characteristics.”
0 Slew rate controlled
1 Not slew rate controlled
SLRC1 controls the slew rate of signals on the following modules: QSPI, TouCAN_A, TouCAN_B.
For the slew rate refer to Appendix F, “Electrical Characteristics.”
0 Slew rate controlled
1 Not slew rate controlled
0:5
SLRC[0:5]
SLRC2 controls the slew rate of signals on the QSCI in QSMCM . For the slew rate refer to
Appendix F, “Electrical Characteristics.”
0 Slew rate controlled
1 Not slew rate controlled
SLRC3 controls the slew rate of signals on the following modules: MIOS14 except
MPWM2/PPM_TX1 and MPWM3 signal. For the slew rate refer to Appendix F, “Electrical
Characteristics.”
0 Slew rate controlled
1 Not slew rate controlled
SLRC4 controls the slew rate of the MIOS14 MPWM2 signal. For the slew rate refer to Appendix F,
“Electrical Characteristics.”
0 Slew rate controlled
1 Not slew rate controlled
SLRC5 controls the slew rate of the MIOS14 MPWM3 signal. For the slew rate refer to Appendix F,
“Electrical Characteristics.”
0 Slew rate controlled
1 Not slew rate controlled
MPC561/MPC563 Reference Manual, Rev. 1.2
2-22
Freescale Semiconductor
Signal Descriptions
Table 2-5. PDMCR Field Descriptions (continued)
Bits
Name
6
PRDS
7
SPRDS
8
Description
PULL_DIS
15-31
—
2.4
Disables weak pull-up/pull down devices enabled at the assertion of PORESET/TRST or
HRESET.
Signals affected by the SPRDS bit include the following: BDIP, TA, TS, TEA, RD/WR, BR, BG, BB,
TSIZ, BI/STS, BURST, TDI, TMS, JCOMP, TCK.
0 Enable weak pull-up/pull down devices on pads controlled by this signal.
1 Disable weak pull-up/pull down devices on pads controlled by this signal.
Refer to Table 2-14 for more information on SPRDS.
T2CLK_PU Controls the pull-up on the TPU T2CLK signals.
0 Pull-ups are enabled if the T2CLK signals are defined as inputs
1 Pull-ups are disabled on the T2CLK signals
9:14
1
Disables weak pull-up/pull down devices enabled at the assertion of PORESET/TRST or
HRESET.
Signals affected by the PRDS bit include the following:
• all SGPIO signals
• all TPU3 signals
0 Enable weak pull-up/pull down devices on pads controlled by this signal.
1 Disable weak pull-up/pull down devices on pads controlled by this signal.
Refer to Table 2-14 for more information on PRDS.
Disables weak pull up-or-down devices enabled at the assertion of PORESET/TRST or HRESET.
Signals affected by these bits include the following:
• PULL_DIS0 (bit 9): all MIOS14 input signals
• PULL_DIS1 (bit 10): all QSMCM input signals
• PULL_DIS2 (bit 11): all QADC64E input signals, except ETRIG1 and ETRIG2
• PULL_DIS3 (bit 12): all TouCAN input signals
• PULL_DIS4 (bit 13): Reserved
• PULL_DIS5 (bit 14): ETRIG1 and ETRIG21
0 Enable weak pull-up/pull-down devices on pads controlled by this signal.
1 Disable weak pull-up/pull-down devices on pads controlled by this signal.
Reserved
This bit was RESERVED on the K27S mask set of MPC561.
Pad Module Configuration Register (PDMCR2)
The PDMCR2 controls alternate functionality of signals shared between different modules, as well as the
pre-discharge circuitry to allow 5V friendliness on the data bus.
MSB
0
1
Field PREDIS_ EN
2
3
—
4
5
TCNC
HRESET
6
7
8
9
MPI7 MPI8 MPI9
10
11
—
12
13
14
PPMPAD
15
—
0000_0000_0000_0000
Addr
0x2F C038
LSB
16
Field
PPMV
HRESET
17
18
—
19
20
21
MDO6 MPI6
22
23
24
—
25
26
27
28
29
PC PCS PCS PCS PCS
SV 4EN 5EN 6EN 7EN
30
31
—
0000_0000_0000_0000
Figure 2-3. Pads Module Configuration Register 2 (PDMCR2)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-23
Signal Descriptions
Table 2-6. PDMCR2 Field Description
Bits
Name
0
PREDIS_
EN
Description
Enable for the Pre-discharge circuit to allow 5 volt external devices on the external data bus.
0 Bus pre-discharge disabled
1 Bus pre-discharge enabled
Note: This bit is reserved in 66-MHz implementations.
1:3
—
Reserved
4:5
TCNC
Controls the function on the following pads: TXD2/QGPO2/C_CNTX0, RXD2/QGPI2/C_CNRX0,
MPIO32B11/C_CNRX0, MPIO32B12/C_CNTX0. Refer to Table 2-7.
6
MPI7
Controls the pad MPIO32B7/MPWM5.
0 MPIO32B7 function will be selected.
1 MPWM5 function will be selected.
7
MPI8
Controls the pad MPIO32B8/MPWM20.
0 MPIO32B8 function will be selected.
1 MPWM20 function will be selected.
8
MPI9
Controls the pad MPIO32B9/MPWM21.
0 MPIO32B9 function will be selected.
1 MPWM21 function will be selected.
11:13
PPMPAD
14:15
—
16
PPMV
17:19
—
20
MDO6
Selects the functionality of MDO6
0 The pad MPIO32B6/MPWM4/MDO6 will function as MDO6, and the pad MPWM18/MDO6 will
function as MPWM18.
1 The pad MPWM18/MDO6 will function as MDO6, and the pad MPIO32B6/MPWM4/MDO6 will
function according to MPI6 bit.
This selection is enabled only if full port mode is implemented in the READI module, if full port
mode is not selected then MPWM18/MDO6 will function as MPWM18, and
MPIO32B6/MPWM4/MDO6 will function according to MPI6 bit.
NOTE: It is recommended to use MPIO32B6/MPWM4/MDO6 for the Nexus port as MDO6 is
enabled from reset.
21
MPI6
Controls the pad MPIO32B6/MPWM4/MDO6.
0 MPIO32B6 function will be selected.
1 MPWM4 function will be selected.
This bit will be disabled if full port mode is enabled in the READI module, and MDO6 bit is logic ‘0’.
22:24
—
25
PCSV
Control the PPM module pads: MPIO32B14/PPM_RX0, MPIO32B15/PPM_TX0,
MPWM2/PPM_TX1, MPWM3/PPM_RX1, MPIO32B10/PPM_TSYNC, MPIO32B13/PPM_TCLK.
Refer to Table 2-8.
Reserved
Selects the voltage of the PPM pads.
0 The voltage will be 2.6 V.
1 The voltage will be 5 V.
Reserved
Reserved
Selects the polarity of QSMCM module QSPI PCS signals in the PCS expanded mode.
0 Selects Active High.
1 Selects Active Low.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-24
Freescale Semiconductor
Signal Descriptions
Table 2-6. PDMCR2 Field Description (continued)
Bits
Name
26
PCS4EN1
Controls the pad B_T2CLK/PCS4.
0 B_T2CLK function will be selected.
1 PCS4 function will be selected.
27
PCS5EN
Controls the pad A_T2CLK/PCS5.
0 A_T2CLK function will be selected.
1 PCS5 function will be selected.
28
PCS6EN
Controls the pad ETRIG1/PCS6.
0 ETRIG1 function will be selected.
1 PCS6 function will be selected.
29
PCS7EN
Controls the pad ETRIG2/PCS7.
0 ETRIG2 function will be selected.
1 PCS7 function will be selected.
30:31
—
1
Description
Reserved
Refer to Table 2-9 for information regarding enhanced PCS functionality.
Table 2-7. TCNC Pad Functionalities
TCNC
Values
TXD2/QGPO2/
C_CNTX0
RXD2/QGPI2/
C_CNRX0
MPIO32B11/
C_CNRX0
MPIO32B12/
C_CNTX0
00
TXD2/QGPO2
RXD2/QGPI2
MPIO32B11
MPIO32B12
x1
TXD2/QGPO2
RXD2/QGPI2
C_CNRX0
C_CNTX0
10
C_CNTX0
C_CNRX0
MPIO32B11
MPIO32B12
Table 2-8. PPMPAD Pad Functionalities
PPMPAD
Values
MPIO32B14/
PPM_RX0
MPIO32B15/
PPM_TX0
MPWM3/
PPM_RX1
MPWM2/
PPM_TX1
MPIO32B10/
PPM_TSYNC
MPIO32B1/
PPM_TCLK
x00
MPIO32B14
MPIO32B15
MPWM3
MPWM2
MPIO32B10
MPIO32B13
001
MPIO32B14
PPM_TX0
MPWM3
MPWM2
PPM_TSYNC
PPM_TCLK
010
PPM_RX0
MPIO32B15
MPWM3
MPWM2
PPM_TSYNC
PPM_TCLK
011
PPM_RX0
PPM_TX0
MPWM3
MPWM2
PPM_TSYNC
PPM_TCLK
101
MPIO32B14
PPM_TX0
MPWM3
PPM_TX1
PPM_TSYNC
PPM_TCLK
110
PPM_RX0
MPIO32B15
PPM_RX1
MPWM2
PPM_TSYNC
PPM_TCLK
111
PPM_RX0
PPM_TX0
PPM_RX1
PPM_TX1
PPM_TSYNC
PPM_TCLK
Table 2-9. Enhanced PCS Functionality
PCS_IN[3:0]
PCS_OUT[7:0] IF PCSV = 0
PCS_OUT[7:0] IF PCSV = 1
0000
00000001
11111110
0001
00000010
11111101
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-25
Signal Descriptions
Table 2-9. Enhanced PCS Functionality (continued)
PCS_IN[3:0]
PCS_OUT[7:0] IF PCSV = 0
PCS_OUT[7:0] IF PCSV = 1
0010
00000100
11111011
0011
00001000
11110111
0100
00010000
11101111
0101
00100000
11011111
0110
01000000
10111111
0111
10000000
01111111
1000
00000000
11111111
1001
RESERVED
RESERVED
1010
1011
1100
1101
1110
1111
NOTE
PCS_IN[3:0] are driven from the QSMCM module. PCS_OUT[7:0] values
are driven by the corresponding PCS[7:0] pads. If all of the PCS enable bits
PCS4EN, PCS5EN, PCS6EN and PCS7EN bits are zero, PCS[3:0] will be
driven directly by the QSMCM module. If one or more of these enable bits
is set, the enhanced PCS function is selected, and the enabled pads drive
PCS_OUT[7:0] value, as shown in Table 2-9.
Table 2-10 details the functionality of the A_T2CLK/PCS5 and B_T2CLK/PCS4 pads dependent on the
values of PDMCR2[PCS5EN], PDMCR2[PCS4EN] and SHORT_REG [SH_T2CLK]. Also shown in this
table is the internal connection of the TPU signals when the enhanced chip select function is used.
Table 2-10. Enhanced PCS 4 & 5 Pad Function
SHORT_REG A_T2CLK/PCS5 B_T2CLK/PCS4
[SH_T2CLK] PAD Function
PAD Function
A_T2CLK internal B_T2CLK internal
TPU_A
TPU_B
Connection
Connection
PDMCR2
[PCS5EN]
PDMCR2
[PCS4EN]
0
0
0
A_T2CLK
B_T2CLK
A_T2CLK/PCS5
Pad
B_T2CLK/PCS4
Pad
0
0
1
A_T2CLK
B_T2CLK
A_T2CLK/PCS5
Pad
A_T2CLK/PCS5
Pad
0
1
0
A_T2CLK
PCS4
A_T2CLK/PCS5
Pad
B_T2CLK Signal
driven HI internally
MPC561/MPC563 Reference Manual, Rev. 1.2
2-26
Freescale Semiconductor
Signal Descriptions
Table 2-10. Enhanced PCS 4 & 5 Pad Function
SHORT_REG A_T2CLK/PCS5 B_T2CLK/PCS4
[SH_T2CLK] PAD Function
PAD Function
A_T2CLK internal B_T2CLK internal
TPU_A
TPU_B
Connection
Connection
PDMCR2
[PCS5EN]
PDMCR2
[PCS4EN]
0
1
1
A_T2CLK
PCS4
A_T2CLK/PCS5
Pad
A_T2CLK/PCS5
Pad
1
0
0
PCS5
B_T2CLK
A_T2CLK Signal
driven HI internally
B_T2CLK/PCS4
Pad
1
0
1
PCS5
B_T2CLK
A_T2CLK Signal
B_T2CLK Signal
driven HI internally driven HI internally
by connection to
A_T2CLK
1
1
0
PCS5
PCS4
A_T2CLK Signal
B_T2CLK Signal
driven HI internally driven HI internally
1
1
1
PCS5
PCS4
A_T2CLK Signal
B_T2CLK Signal
driven HI internally driven HI internally
by connection to
A_T2CLK
1. If PCS4/5EN = 1 then A/B_T2CLK into the module is pulled up internally (enabling Div/8 clock, in gate mode).
2. If only PCS4EN=1, then A_T2CLK can be driven into B_T2CLK if PPM_SHORT[SH_T2CLK] is set.
3. If only PCS5EN=1 then A_T2CLK will be pulled up, if PPM_SHORT[SH_T2CLK] is set, then, B_T2CLK will be high
regardless of pin state.
All of this is regardless of the Pull up/down state.
Note: The PPM shorting function has higher priority logic. If shorting is selected, then A_T2CLK → B_T2CLK. If A_T2CLK
is selected as PCS then both A_T2CLK and B_T2CLK will be high regardless of B_T2CLK/PCS4 Pad state.
Table 2-11 details the functionality of the ETRIG1/PCS6 and ETRIG2/PCS7 pads dependent on the values
of PDMCR2[PCS6EN], PDMCR2[PCS7EN], SHORT_REG [SH_ET1] and SHORT_REG [SH_ET2].
Also shown in this table is the internal connection of the ETRIG signals when the enhanced chip select
function is used.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-27
Signal Descriptions
2.5
MPC561/MPC563 Development Support Signal Sharing
Table 2-11. Enhanced PCS 6 & 7 Pad Function
PDMCR2 PDMCR2 PULL_
[PCS6EN] [PCS7EN] DIS5
SHORT_ SHORT_
ETRIG1/PCS6 ETRIG2/PCS7
REG
REG
PAD Function PAD Function
[SH_ET1] [SH_ET2]
Pad
Pull-up
ETRIG 1
internal
connection
ETRIG2
internal
connection
ETRIG1
ETRIG2
0
0
0
0
0
ETRIG1
ETRIG2
Enabled
0
0
0
1
1
ETRIG1
ETRIG2
Enabled A_TPUCH15 B_TPUCH15
0
0
1
0
0
ETRIG1
ETRIG2
Disabled
0
0
1
1
1
ETRIG1
ETRIG2
Disabled A_TPUCH15 B_TPUCH15
0
1
0
0
0
ETRIG1
PCS7
Enabled
0
1
0
1
1
ETRIG1
PCS7
Enabled A_TPUCH15 B_TPUCH15
0
1
1
0
0
ETRIG1
PCS7
Disabled
0
1
1
1
1
ETRIG1
PCS7
Disabled A_TPUCH15 B_TPUCH15
1
0
0
0
0
PCS6
ETRIG2
Enabled
1
0
0
1
1
PCS6
ETRIG2
Enabled A_TPUCH15 B_TPUCH15
1
0
1
0
0
PCS6
ETRIG2
Disabled
1
0
1
1
1
PCS6
ETRIG2
Disabled A_TPUCH15 B_TPUCH15
1
1
0
0
0
PCS6
PCS7
Enabled
1
1
0
1
1
PCS6
PCS7
Enabled A_TPUCH15 B_TPUCH15
1
1
1
0
0
PCS6
PCS7
Disabled
1
1
1
1
1
PCS6
PCS7
Disabled A_TPUCH15 B_TPUCH15
ETRIG1
ETRIG1
ETRIG1
PCS6
PCS6
PCS6
PCS6
ETRIG2
PCS7
PCS7
ETRIG2
ETRIG2
PCS7
PCS7
On the MPC561/MPC563, the JTAG, BDM, and READI (Nexus interface) signals are all shared. Only one
set of signals can be active at a time. Table 2-12 shows the shared functions in the different modes.
Table 2-12. MPC561/MPC563 Development Support Shared Signals
Signal1
Direction
JTAG
BDM
READI
JCOMP/RSTI
Input
JCOMP
0
RSTI
TCK/DSCK/MCKI
Input
TCK
DSCK
MCKI
TDI/DSDI/MDI0
Input
TDI
DSDI
MDI0
TDO/DSDO/MDO0
Output
TDO
DSDO
MDO0
TMS/EVTI
Input
TMS
—
EVTI
1
Only one set of signals are enabled at a time.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-28
Freescale Semiconductor
Signal Descriptions
Table 2-13. MPC561/MPC563 Mode Selection Options
Signal
State
When Sampled
Affect
BDM Mode
DSCK
DSDI
High
SRESET negation
BDM mode enabled
Low
SRESET negation
BDM mode disabled
High
8 clocks after SRESET
Synchronous mode
Low
8 clocks after SRESET
Asynchronous mode
Nexus Configuration
EVTI
MDI0
High
RSTI negation
READI module Disabled
Low
RSTI negation
READI module Enabled
High
EVTI negation
Full Port mode
Low
EVTI negation
Reduced port mode
JTAG Selection
JCOMP
2.5.1
Low
PORESET
Nexus or BDM allowed
High
PORESET
JTAG Mode Selected
JTAG Mode Selection
The MPC561/MPC563 has five JTAG signals. The test data input (TDI) and test data output (TDO) scan
ports are used to scan instructions as well as data into the various scan registers for JTAG operations. The
scan operation is controlled by the test access port (TAP) controller, which in turn is controlled by the test
mode select (TMS) input sequence. The scan data is latched at the rising edge of the test clock (TCK).
On the MPC561/MPC563, JTAG is used for boundary scan only. There is no access to internal
MPC561/MPC563 circuitry. When JTAG mode is enabled, the READI module will be held inactive. See
Figure 2-4 for JTAG mode selection.
JTAG is entered by the following sequence of events:
• Assert PORESET/TRST to reset the JTAG TAP controller
• Hold JCOMP/RSTI high prior to PORESET/TRST negation and keep high as long as JTAG mode
is required
(The READI module will be held inactive since only one of the multiplexed functions JCOMP and
RSTI can be asserted at the negation of PORESET/TRST).
JTAG mode is exited by:
• Drive JCOMP/RSTI low.
NOTE
PORESET/TRST and analog signals ANx, EXTAL, XTAL, and
TDI/TDO/TMS/TCK are not in the JTAG scan path.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-29
Signal Descriptions
PORESET/TRST
JCOMP/RSTI
JTAG Config
JTAG On
T
JTAG Disabled
Figure 2-4. Debug Mode Selection (JTAG)
2.5.2
BDM Mode Selection
The MPC561/MPC563 has a 10 pin BDM port. See Figure 2-5 for BDM mode selection.
The BDM mode is entered by the following sequence of events:
• Hold DSCK high at reset negation (SRESET)
• Configure DSDI to select BDM clock mode, within 8 clocks of reset negation
BDM mode is exited by:
• Reset the device by asserting PORESET/TRST or HRESET
SRESET
DSCK
DSDI
JCOMP/RSTI
TMS/EVTI
(low)
(low)
BDM Enable
Configure BDM
Enable Nexus
BDM On
Nexus Off
T
Figure 2-5. Debug Mode Selection (BDM)
2.5.3
Nexus Mode Selection
The READI module signals support the Nexus (IEEE-ISTO 5001-1999) auxiliary port interface for debug.
There are two modes available: full port mode and reduced port mode. Reduced port mode allows for a 1
bit input stream and a 2 bit output stream. Full port mode allows for a 2-bit input stream and an 8-bit output
stream. If MDI0 is held high when Nexus mode is enabled, full port mode will be used during Nexus
debug. If MDI0 is held low when Nexus mode is enabled, reduced port mode will be used. See Figure 2-6
for Nexus mode selection.
The Nexus interface is entered by the following sequence of events:
• Hold JCOMP/RSTI low while negating PORESET/TRST
• Hold TMS/EVTI low to enable Nexus mode and configure TDI/DSDI/MDI0 for full or reduced
port mode. Both of these should be done at least 4 clocks before driving JCOMP/RSTI high
MPC561/MPC563 Reference Manual, Rev. 1.2
2-30
Freescale Semiconductor
Signal Descriptions
•
Drive JCOMP/RSTI high
Nexus mode is exited by:
• Hold JCOMP/RSTI low to reset Nexus port
• Hold TMS/EVTI high to disable Nexus mode at least 4 clocks before driving JCOMP/RSTI high
• Drive JCOMP/RSTI high
PORESET/TRST
JCOMP/RSTI
TMS/EVTI
MDI0
T
Enable and
Configure Nexus
Nexus On
Nexus Off
Figure 2-6. Debug Mode Selection (Nexus)
2.6
Reset State
During reset, a 130-µA (maximum) resistor “weakly pulls” all input signals, with the exception of the
power-supply and clock-related signals, to a value based on conditions described in Appendix F,
“Electrical Characteristics.” In reset state, all I/O signals become inputs, and all outputs (except for
CLKOUT, HRESET, and SRESET) are pulled only by the pull-up/pull-down.
2.6.1
Signal Functionality Configuration Out of Reset
The reset configuration word (RCW) defines the post-reset functionality of some multiplexed signals. For
details on these signals and how they are configured, refer to Section 7.5.2, “Hard Reset Configuration
Word.”
The 2.6-V bus related signals have selectable output buffer drive strengths that are controlled by the COM0
bit in the USIU’s system clock and reset control register (SCCR). The control is as follows:
0 = 2.6-V bus signals full drive (50-pF load)
1 = 2.6-V bus signals reduced drive (25-pF load)
2.6.2
Signal State During Reset
While HRESET is asserted, the reset-configuration value is latched from the data bus into various bits on
the part. The function of many signals depends upon the value latched. If the value on the data bus changes,
then the function of various signals may also change. This is especially true if the reset configuration word
(RCW) comes from the Flash, because the Flash does not drive the RCW until 256 clocks after the start of
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-31
Signal Descriptions
HRESET. However, the signals must not cause any spurious conditions or consume an excessive amount
of power during reset. To prevent these conditions, the signals need to have a defined reset state.
Table 2-14 describes the reset state of the signals based on signal functionality.
All signals are initialized to a “reset state” during reset. This state remains active until reset is negated or
until software disables the pull-up or pull-down device based on the signal functionality. Upon assertion
of the corresponding bits in the signal control registers and negation of reset, the signal acquires the
functionality that was programmed.
2.6.3
Power-On Reset and Hard Reset
Power-on reset and hard reset affect the functionality of the signals out of reset. (During soft reset, the
functionality of the signals is unaltered.)
Upon assertion of the power-on reset signal (PORESET/TRST) the functionality of the signal is not yet
known to the RCPU. The weak pull-up or weak pull-down resistors are enabled. The reset configuration
word configures the system, and towards the end of reset the signal functionality is known. Based upon
the signal functionality, the pull-up or pull-down devices are either disabled immediately at the negation
of reset or remain enabled, as shown in Table 2-14.
Because hard reset can occur when a bus cycle is pending, the PDMCR bits that enable and disable the
pull-up or pull-down resistors are set or reset synchronously to eliminate contention on the signals.
(PORESET/TRST affects these bits asynchronously.)
2.6.4
2.6.4.1
Pull-Up/Pull-Down
Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only
Signals
The pull resistors are enabled and disabled by the corresponding bits in the PDMCR register in the USIU
(see Table 2-14). When those bits are negated (logic 0), the pull resistors are enabled. When asserted (logic
1), the devices are disabled.
2.6.4.2
Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals
The 5-V/2.6-V multiplexed pad does not have a pull-up device. The pull-down will be controlled by the
corresponding bits in the PDMCR register. When this bit is negated, the pull-down is enabled, when
asserted the pull-down will be disabled.
NOTE
All pull-up/pull-down devices are disabled when all the signals are forced
to three state in JTAG mode.
2.6.4.3
Special Pull Resistor Disable Control Functionality (SPRDS)
For the signals that support debug, opcode tracking, and bus control functionality, the pull resistors will be
controlled by the SPRDS bit in the PDMCR register. During reset this signal will be synchronously used
MPC561/MPC563 Reference Manual, Rev. 1.2
2-32
Freescale Semiconductor
Signal Descriptions
to enable the pull resistors in the pads. On negation of reset, based on which functionality is selected for
the signals, this signal is set to disable the pull resistors, or is continued to be held in its reset state to
indicate that the pulls are disabled only when the output driver is enabled.
2.6.4.4
Pull Device Select (PULL_SEL)
The MIOS14 and the TPU signals have selectable pull-up or pull-down devices. The devices are controlled
by the PULL_SEL signal. A high on the PULL_SEL signal enables pull-up devices on the MIOS14 and
TPU signals. A low enables pull-down devices. Note that the pull devices can be disabled by the
PULL_DIS0 (MIOS14) and PRDS (TPU) bits in the PDMCR register. See Section 2.3, “Pad Module
Configuration Register (PDMCR).”
2.6.5
Signal Reset States
Table 2-14 summarizes the reset states of all signals on the MPC561/MPC563. Note that PD refers to a
weak pull-down, PU2.6 refers to a weak pull-up to 2.6 V, and PU5 refers to a weak pull-up to 5 V. All
control of the weak-pull devices is in the pad module configuration register, described in Table 2-5.
NOTE
2.6-V inputs are 5-V tolerant, but 2.6-V outputs are not. Do not connect
2.6-V outputs to a driver or pull-up greater than 3.1 V.
NOTE
Depending on the application, pins may require a pull-down resistor to
avoid getting any command due to noise.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-33
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State
Signal List1
Voltage
Slew Rate
Controlled
Option?
Drive
Load
(pF)2
Reset State
Hysteresi
s
Enabled?
Function After HRESET,
PORESET/TRST
USIU
ADDR[8:31]3/
2.6 V
No
50 ; 25
PD until reset
negates4, 6
No
SGPIOA[8:31]
5V
Yes
50 ; 505
PD until PRDS
is set
No
DATA[0:31]3/
2.6 V
No
50 ; 25
PD until reset
negates6
No
SGPIOD[0:31]
5V
Yes
50:50 5
PD until PRDS
is set
No
IRQ0 /
2.6 V
No
NA
Yes
SGPIOC07 /
2.6 V
No
50 ; 25
PU2.6 until
PRDS is set8
MDO4 7
2.6 V
No
50 ; 25
IRQ1 /
2.6 V
No
NA
PD until reset
negates 6, 8
Yes
RSV /
2.6 V
No
50 ; 25
PD until reset
negates 6
Yes
SGPIOC1 3
5V
Yes
IRQ2 /
2.6 V
No
NA
PD until reset
negates 6, 8
Yes
CR /
2.6 V
No
NA
PD until reset
negates 6, 8
No
SGPIOC2 3 /
5V
Yes
MTS9
2.6 V
No
50 ; 25
PD until reset
negates 6
No
IRQ3 /
2.6 V
No
NA
PD until reset
negates 6, 8
Yes
KR /
2.6 V
No
50 ; 25
PD when driver
not enabled 4
No
RETRY/
2.6 V
No
50 ; 25
PD when driver
not enabled 4
No
SGPIOC3 3
5V
Yes
50 ; 50 5 PD until PRDS
is set
No
Yes
Controlled by SC bit in the
reset config word. See
Table 6-10.
Controlled by SC bit in the
reset config word. See
Table 6-10.
MDO4 if the Nexus (READI)
port is enabled, IRQ0
otherwise. See Section 2.5.
Yes
50 ; 50 5 PD until PRDS
is set
50 ; 50 5 PD until PRDS
is set
IRQ1
Yes
IRQ2
No
IRQ3
MPC561/MPC563 Reference Manual, Rev. 1.2
2-34
Freescale Semiconductor
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
Drive
Load
(pF)2
IRQ4 /
2.6 V
No
NA
PD until reset
negates 6, 8
Yes
AT2 /
2.6 V
No
50 ; 25
PD until reset
negates 6, 8
No
SGPIOC4 3
5V
Yes
IRQ510 /
2.6 V
No
NA
SGPIOC5 7 /
2.6 V
No
50 ; 25
MODCK111
2.6 V
No
IRQ[6:7] 10 /
2.6 V
MODCK[2:3] 11
Reset State
50 ; 50 5 PD until PRDS
is set
Hysteresi
s
Enabled?
Function After HRESET,
PORESET/TRST
IRQ4
Yes
PU2.6 until reset
negates
Yes
MODCK1 until reset negates,
then IRQ5
PU2.6 until
PRDS is set
No
NA
PU2.6V until
reset negates
No
No
NA
PU2.6 until
SPRDS is set
Yes
2.6 V
No
NA
PU2.6 until reset
negates
No
PULL_SEL
5V
No
NA
PU5, external
pull device
required
No
PULL_SEL
TSIZ[0:1] 7
2.6 V
No
50 ; 25
PD when driver
not enabled or
until SPRDS is
set
No
TSIZ[0:1]
RD/WR 7
2.6 V
No
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
No
RD/WR
BURST 7
2.6 V
No
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
No
BURST
BDIP 7
2.6 V
No
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
No
BDIP
TS 7,12
2.6 V
No
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
No
TS
MODCK[2:3] until reset
negates, then IRQ[6:7]
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-35
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
Drive
Load
(pF)2
TA 7, 12
2.6 V
No
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
No
TA
TEA 7, 12
2.6 V
No
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
No
TEA
OE 7
2.6 V
No
50 ; 25
PU2.6 until reset
negates
No
OE
RSTCONF /
2.6 V
No
N/A
No
RSTCONF until reset
negates.
TEXP 7, 11
2.6 V
No
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
BI 7, 12/
2.6 V
No
50 ; 25
STS 7
2.6 V
No
50 ; 25
CS[0:3] 7
2.6 V
No
50 ; 25
WE[0:3] 7/
2.6 V
No
50 ; 25
BE[0:3] 7/
2.6 V
No
50 ; 25
AT[0:3] 7
2.6 V
No
50 ; 25
Reset State
PU2.6 when
driver not
enabled or until
SPRDS is set.
Hysteresi
s
Enabled?
Function After HRESET,
PORESET/TRST
No
No
No
Controlled by DBGC in the
reset configuration word.
See Table 6-8.
PU2.6 until reset
negates
No
CS[0:3]
PU2.6 when
driver not
enabled or until
SPRDS is set
No
Controlled by bit ATWC (bit
12) of the reset configuration
word. See Table 6-8.
No
No
System Control
PORESET/
2.6 V
No
NA
External pull-up
required
Yes
TRST 11
2.6 V
No
NA
HRESET 11, 12
2.6 V13
No
SRESET 11, 12
2.6 V13
No
PORESET/TRST
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
Yes
HRESET
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
External pull-up
required
Yes
SRESET
Yes
Development and Debug
MPC561/MPC563 Reference Manual, Rev. 1.2
2-36
Freescale Semiconductor
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
SGPIOC6 3 /
5V
Yes
FRZ /
2.6 V
No
50 ; 25
PD until reset
negates
No
PTR
2.6 V
No
50 ; 25
PD until reset
negates
No
SGPIOC7 3/
5V
Yes
IRQOUT /
2.6 V
No
50 ; 25
PD until reset
negates 6
No
LWP0
2.6 V
No
50 ; 25
PD until reset
negates 6
No
BG 7/
2.6 V
No
50 ; 25
No
2.6 V
No
50 ; 25
2.6 V
No
50 ; 25
PU2.6 when
driver not
enabled or until
SPRDS is set
BR 7/
2.6 V
No
50 ; 25
7/
2.6 V
No
50 ; 25
IWP2 7
2.6 V
No
50 ; 25
2.6 V
No
50 ; 25
VF2 7/
2.6 V
No
50 ; 25
7
2.6 V
No
50 ; 25
IWP[0:1] 7/
2.6 V
No
50 ; 25
7
2.6 V
No
50 ; 25
VF0 7/
7
LWP1
VF1
BB
7, 12/
IWP3
VFLS[0:1]
Drive
Load
(pF)2
Reset State
50 ; 50 5 PD until PRDS
is set
50 ; 50 5 PD until PRDS
is set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 when
driver not
enabled or until
SPRDS is set
PU2.6 until reset
negates
Hysteresi
s
Enabled?
No
Yes
No
Function After HRESET,
PORESET/TRST
PTR
LWP0
Controlled by DBGC in reset
config word. See Table 6-8.
No
No
No
Controlled by DBGC in reset
config word. See Table 6-8.
No
No
No
Controlled by DBGC in reset
config word. See Table 6-8.
No
No
No
Controlled by DBGC in the
reset config word. See
Table 6-8.
JTAG/BDM/READI
TMS /
2.6 V
No
NA
EVTI
2.6 V
No
NA
TDI /
2.6 V
No
NA
DSDI /
2.6 V
No
NA
MDI0
2.6 V
No
NA
TCK /
2.6 V
No
NA
DSCK /
2.6 V
No
NA
MCKI
2.6 V
No
NA
PU2.6 if in JTAG
mode, otherwise
PD until SPRDS
is set14
No
PU2.6 if in JTAG
mode, otherwise
PD until SPRDS
is set 6
No
PD until reset
negates 6
No
No
No
Yes
Yes
Yes
TMS unless the Nexus
(READI) port is enabled, then
EVTI. See Section 2.5.
DSDI unless the Nexus
(READI) port (MDI0) or JTAG
mode (TDI) is enabled. See
Section 2.5.
DSCK unless the Nexus
(READI) port (MCKI) or JTAG
mode (TCK) is enabled. See
Section 2.5.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-37
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
Drive
Load
(pF)2
TDO 7 /
2.6 V
No
50 ; 25
7
DSDO /
2.6 V
No
50 ; 25
MDO0 7
2.6 V
No
50 ; 25
JCOMP /
2.6 V
No
NA
RSTI
2.6 V
No
NA
Reset State
PU2.6 until reset
negates or the
driver is enabled
PD until SPRDS
is set
Hysteresi
s
Enabled?
No
Function After HRESET,
PORESET/TRST
No
DSDO unless the Nexus
(READI) port (MDO0) or
JTAG mode (TDO) is enabled.
See Section 2.5.
No
See Section 2.5.
No
No
Clocks and PLL
XTAL 11
2.6 V
NA ; NA
NA ; NA
—
NA
XTAL
EXTAL 11
2.6 V
NA ; NA
NA ; NA
—
NA
EXTAL
XFC
2.6 V
NA ; NA
NA ; NA
—
NA
XFC
CLKOUT 7
2.6 V
No
90; 50;
2515
—
No
CLKOUT
EXTCLK 11
2.6 V
NA ; NA
NA ; NA
—
No
EXTCLK
2.6 V / 5 V
NA ; NA
NA ; NA
—
No
ENGCLK (2.6 V)
2.6 V
NA ; NA
NA ; NA
—
No
ENGCLK
3/
BUCLK
QSMCM
PCS0 /
5V
Yes
50 ; 50
SS /
5V
Yes
50 ; 50
QGPIO0
5V
Yes
50 ; 50
PCS[1:3]/
5V
Yes
50 ; 50
QGPIO[1:3]
5V
Yes
50 ; 50
MISO /
5V
Yes
QGPIO4
5V
Yes
MOSI /
5V
Yes
QGPIO5
5V
Yes
SCK /
5V
Yes
QGPIO6
5V
Yes
TXD1 /
5V
Yes
50 ; 50
QGPO1
5V
Yes
50 ; 50
PU5 until
PULL_DIS1 is
set
No
QGPO0
No
No
PU5 until
PULL_DIS1 is
set
No
No
200 ; 50 5 PU5 until
PULL_DIS1 is
200 ; 50 5 set
No
200 ; 50 5 PU5 until
PULL_DIS1 is
200 ; 50 5 set
No
200 ; 50 5 PU5 until
PULL_DIS1 is
200 ; 50 5 set
No
PU5 until
PULL_DIS1 is
set
QGPIO[1:3]
QGPIO4
No
QGPIO5
No
QGPIO6
No
No
QGPO1
No
MPC561/MPC563 Reference Manual, Rev. 1.2
2-38
Freescale Semiconductor
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
Drive
Load
(pF)2
TXD2 /
5V
Yes
50 ; 50
QGPO2 /
5V
Yes
50 ; 50
C_CNTX0
5V
Yes
50 ; 50
RXD1 /
5V
NA
NA
QGPI1
5V
NA
NA
RXD2 /
5V
NA
NA
QGPI2 /
5V
NA
NA
C_CNRX0
5V
NA
NA
Reset State
PU5 until
PULL_DIS1 is
set
Hysteresi
s
Enabled?
No
Function After HRESET,
PORESET/TRST
QGPO2
No
No
Must be driven
or connected to
a pull device
No
Must be driven
or connected to
a pull device
No
QGPI1
No
QGPI2
No
No
MIOS14
MDA[11:15,
27:31]
5V
Yes
50 ; 50
Pull device
enabled until
PULL_DIS0 is
set16
Yes
MDA[11:15,27:31]
MPWM0 /
5V
Yes
50 ; 50
Yes
MDI1
2.6 V
No
NA
Pull device
enabled until
PULL_DIS0 is
set 16
MPWM0 unless the Nexus
(READI) port is enabled, then
MDI1. See Section 2.5.
MPWM1 3 /
5V
Yes
50 ; 50
Yes
MDO2
2.6 V
No
50 ; 25
Pull device
enabled until
PULL_DIS0 is
set 16
No
MPWM1 unless the Nexus
(READI) port is enabled, then
MDO2. See Section 2.5.
MPWM23 /
5V
Yes
50 ; 50
Yes
MPWM2
2.6 V
No
50 ; 25
PPM_TX1
5V
Yes
50 ; 25
Pull device
enabled until
PULL_DIS0 is
set 16
MPWM3/
5V
Yes
50 ; 50
Yes
PPM_RX1
2.6 V
No
NA
Pull device
enabled until
PULL_DIS0 is
set 16
MPWM16
5V
Yes
50 ; 50
Pull device
enabled until
PULL_DIS0 is
set 16
Yes
MPWM16
MPWM173 /
5V
Yes
50 ; 50
Yes
MDO3
2.6 V
No
50 ; 25
Pull device
enabled until
PULL_DIS0 is
set 16
MPWM17 unless the Nexus
(READI) port is enabled. See
Section 2.5.
Yes
No
No
MPWM3
Yes
No
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-39
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
Drive
Load
(pF)2
MPWM[18:19]3
/
5V
Yes
50 ; 50
MDO[6:7]
2.6 V
No
50 ; 25
MPIO32B03 /
5V
Yes
VF0 /
2.6 V
No
2.6 V
No
MDO1
3
Reset State
Pull device
enabled until
PULL_DIS0 is
set 16
Yes
50 ; 50 5 Pull device
enabled until
50 ; 25 PULL_DIS0 is
16
50 ; 25 set.
Yes
50 ; 50
5
MPIO32B1 /
5V
Yes
VF1/
2.6 V
No
50 ; 25
MCKO
2.6 V
No
50 ; 25
MPIO32B23 /
5V
Yes
VF2 /
2.6 V
No
MSEI
2.6 V
No
Yes
Yes
VFLS0 /
2.6 V
No
50 ; 25
MSEO
2.6 V
No
50 ; 25
Yes
VFLS1
2.6 V
No
MPIO32B53 /
5V
Yes
MDO5
2.6 V
No
MPIO32B63 /
5V
Yes
MPWM4 /
5V
Yes
MDO6
2.6 V
Yes
50 ; 50
No
No
Pull device
enabled until
PULL_DIS0 is
set16
Yes
50 ; 50 5 Pull device
enabled until
50 ; 25 PULL_DIS0 is
set 16
Yes
50 ; 50 5 Pull device
enabled until
50 ; 50 PULL_DIS0 is
16
50 ; 25 set.
Yes
50 ; 25
50 ; 50
5
MPIO32B[7:9] /
5V
Yes
MPWM[5,
20:21]
5V
Yes
MPIO32B103 /
5V
Yes
PPM_TSYNC
2.6 V
No
5V
Yes
MPIO32B11 /
5V
Yes
50 ; 50
C_CNRX0
5V
Yes
NA
50 ; 50
Pull device
enabled until
PULL_DIS0 is
set 16
50 ; 50 5 Pull device
enabled until
50 ; 25 PULL_DIS0 is
16
50 ; 50 set
PU5 until
PULL_DIS0 is
set
MPIO32B1 unless the Nexus
(READI) port is enabled, then
MCKO. See Section 2.5.
MPIO32B2 unless the Nexus
(READI) port is enabled, then
MSEI. See Section 2.5.
Yes
Yes
50 ; 50
MPIO32B0 unless the Nexus
(READI) port is enabled, then
MDO1. See Section 2.5.
No
Pull device
enabled until
PULL_DIS0 is
set.16
5
MPWM[18:19]
No
50 ; 50 5 Pull device
enabled until
50 ; 25 PULL_DIS0 is
set.16
N/A
5V
5V
No
Yes
5
Function After HRESET,
PORESET/TRST
No
Pull device
enabled until
PULL_DIS0 is
set.16
MPIO32B33 /
MPIO32B43 /
Hysteresi
s
Enabled?
No
MPIO32B3 unless the Nexus
(READI) port is enabled, then
MSEO. See Section 2.5.
No
MPIO32B4
No
No
Yes
MPIO32B5 unless the Nexus
(READI) port is enabled, then
MDO5. See Section 2.5.
MPIO32B6 unless the Nexus
(READI) port is enabled, then
MDO6. See Section 2.5.
No
Yes
MPIO32B[7:9]
Yes
Yes
MPIO32B10
No
Yes
MPIO32B11
No
MPC561/MPC563 Reference Manual, Rev. 1.2
2-40
Freescale Semiconductor
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
MPIO32B12 /
5V
Yes
C_CNTX0
5V
Yes
MPIO32B133 /
5V
Yes
PPM_TCLK
2.6 V
No
5V
Yes
MPIO32B14 /
5V
Yes
PPM_RX0
2.6 V
No
5V
No
MPIO32B153 /
5V
Yes
PPM_TX0
2.6 V
No
5V
Yes
Drive
Load
(pF)2
Reset State
Hysteresi
s
Enabled?
50 ; 50 5 PU5 until
PULL_DIS0 is
50 ; 50 set
Yes
50 ; 50 5 Pull device
enabled until
50 ; 25 PULL_DIS0 is
16
50 ; 50 set
Yes
50 ; 50 5 Pull device
enabled until
NA
PULL_DIS0 is
set 16
NA
Yes
50 ; 50 5 Pull device
enabled until
50 ; 25 PULL_DIS0 is
16
50 ; 50 set
Function After HRESET,
PORESET/TRST
MPIO32B12
No
MPIO32B13
No
No
MPIO32B14
Yes
Yes
Yes
MPIO32B15
No
No
TPU_A / TPU_B
50 ; 50 5 Pull device
enabled until
PRDS is set 16
A_TPUCH[0:15
]
5V
Yes
A_T2CLK /
5V
Yes
50 ; 50
PCS5
5V
Yes
50 ; 50
B_TPUCH[0:15
]
5V
Yes
B_T2CLK /
5V
Yes
50 ; 50
PCS4
5V
Yes
50 ; 50
PU5 when driver
not enabled or
until T2CLK_PU
is set
50 ; 50 5 Pull device
enabled until
PRDS is set 16
PU5 when driver
not enabled or
until T2CLK_PU
is set
Yes
A_TPUCH[0:15]
Yes
A_T2CLK
No
Yes
B_TPUCH[0:15]
Yes
B_T2CLK
No
QADC64E_A / QADC64E_B
ETRIG[1:2] /
5V
Yes
N/A
PD until
PULL_DIS5 is
set
Yes
PCS[6:7]
5V
Yes
50 ; 50
PU5 until
PULL_DIS1 is
set
Yes
A_AN0 /
5V
Yes
NA
A_ANw /
5V
Yes
A_PQB0
5V
Yes
PU5 when driver
not enabled or
NA
until
5 PULL_DIS2 is
50 ; 50
set
No
ETRIG[1:2]
A_AN0
No
Yes
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-41
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
Drive
Load
(pF)2
A_AN1 /
5V
Yes
NA
A_ANx /
5V
Yes
A_PQB1
5V
Yes
A_AN2 /
5V
Yes
A_ANy /
5V
Yes
A_PQB2
5V
Yes
A_AN3 /
5V
Yes
A_ANz /
5V
Yes
A_PQB3
5V
Yes
A_AN[48:51]/
5V
Yes
A_PQB[4:7]
5V
Yes
A_AN[52:54] /
5V
Yes
A_MA[0:2] /
5V
Yes
A_PQA[0:2]
5V
Yes
A_AN[55:59]/
5V
Yes
A_PQA[3:7]
5V
Yes
B_AN0 /
5V
Yes
B_ANw /
5V
Yes
B_PQB0
5V
Yes
B_AN1 /
5V
Yes
B_ANx /
5V
Yes
B_PQB1
5V
Yes
B_AN2 /
5V
Yes
B_ANy /
5V
Yes
B_PQB2
5V
Yes
Reset State
PU5 when driver
not enabled or
NA
until
5 PULL_DIS2 is
50 ; 50
set
NA
PU5 when driver
not enabled or
NA
until
50 ; 50 5 PULL_DIS2 is
set
NA
PU5 when driver
not enabled or
NA
until
5 PULL_DIS2 is
50 ; 50
set
NA
PU5 when driver
not enabled or
50 ; 50 5 until
PULL_DIS2 is
set
NA
PU5 when driver
not enabled or
NA
until
5
PULL_DIS2 is
50 ; 50
set
NA
PU5 when driver
not enabled or
50 ; 50 5 until
PULL_DIS2 is
set
NA
PU5 when driver
not enabled or
NA
until
5 PULL_DIS2 is
50 ; 50
set
NA
PU5 when driver
not enabled or
NA
until
50 ; 50 5 PULL_DIS2 is
set
NA
PU5 when driver
not enabled or
NA
until
5 PULL_DIS2 is
50 ; 50
set
Hysteresi
s
Enabled?
No
Function After HRESET,
PORESET/TRST
A_AN1
No
Yes
No
A_AN2
No
Yes
No
A_AN3
No
Yes
No
A_AN[48:51]
Yes
No
A_AN[52:54]
Yes
Yes
No
A_AN[55:59]
Yes
No
B_AN0
No
Yes
No
B_AN1
No
Yes
No
B_AN2
No
Yes
MPC561/MPC563 Reference Manual, Rev. 1.2
2-42
Freescale Semiconductor
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
Drive
Load
(pF)2
B_AN3 /
5V
Yes
NA
B_ANz /
5V
Yes
B_PQB3
5V
Yes
B_AN[48:51]/
5V
Yes
B_PQB[4:7]
5V
Yes
B_AN[52:54]/
5V
Yes
B_MA[0:2]/
5V
Yes
B_PQA[0:2]
5V
Yes
B_AN[55:59]/
5V
Yes
B_PQA[3:7]
5V
Yes
Reset State
PU5 when driver
not enabled or
NA
until
5 PULL_DIS2 is
50 ; 50
set
NA
PU5 when driver
not enabled or
50 ; 50 5 until
PULL_DIS2 is
set
NA
PU5 when driver
not enabled or
NA
until
5 PULL_DIS2 is
50 ; 50
set
NA
PU5 when driver
not enabled or
50 ; 50 5 until
PULL_DIS2 is
set
Hysteresi
s
Enabled?
No
Function After HRESET,
PORESET/TRST
B_AN3
No
Yes
No
B_AN[48:51]
Yes
No
B_AN[52:54]
Yes
Yes
No
B_AN[55:59]
Yes
TouCAN_A / TouCAN_B
A_CNTX0
5V
Yes
50 ; 50 17 PU5 until
PULL_DIS3 is
set
No
A_CNTX0
B_CNTX0
5V
Yes
50 ; 50 17 PU5 until
PULL_DIS3 is
set
No
B_CNTX0
A_CNRX0
5V
No
NA
PU5 until
PULL_DIS3 is
set
Yes
A_CNRX0
B_CNRX0
5V
No
NA
PU5 until
PULL_DIS3 is
set
Yes
B_CNRX0
UC3F Flash
EPEE18
2.6 V
No
—
PU2.6
No
EPEE
B0EPEE18
2.6 V
No
—
PU2.6
No
B0EPEE
UC3F Power Supplies
VFLASH 18
5V
—
—
—
—
VFLASH
VDDF 18
2.6 V
—
—
—
—
VDDF
VSSF 18
0V
—
—
—
—
VSSF
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-43
Signal Descriptions
Table 2-14. MPC561/MPC563 Signal Reset State (continued)
Signal List1
Voltage
Slew Rate
Controlled
Option?
Drive
Load
(pF)2
Reset State
Hysteresi
s
Enabled?
Function After HRESET,
PORESET/TRST
Global Power Supplies
NVDDL
2.6 V
—
—
—
—
NVDDL
VDDH
5V
—
—
—
—
VDDH
VDD
2.6 V
—
—
—
—
VDDI
VSS
0V
—
—
—
—
VSS
KAPWR 11
2.6 V
—
—
—
—
KAPWR
IRAMSTBY19
≥2.6 V
—
—
—
—
IRAMSTBY
QVDDL
2.6 V
—
—
—
—
QVDDL
USIU Power Supplies
VDDSYN
2.6 V
—
—
—
—
VDDSYN
VSSSYN
2.6 V
—
—
—
—
VSSSYN
QADC64E Power Supplies
VRH
5V
—
—
—
—
VRH
VRL
0V
—
—
—
—
VRL
ALTREF
5V
—
—
—
—
ALTREF
VDDA
5V
—
—
—
—
VDDA
VSSA
0V
—
—
—
—
VSSA
1
This column contains only the list of signals and should not be confused with the actual pin name. For actual pin
names, see Appendix F, “Electrical Characteristics.”
2 For 5-V outputs, the left hand value represents slew rate control off, and the right hand value represents slew rate
control on. For 2.6-V outputs, the left hand value represents loads that are full drive, and the right hand value
represents loads that are half drive.
3 Care should be taken that neither a pull-up to greater than 3.1 V or an external output that can drive greater than
3.1 V is connected to this pin while the 2.6-V driver is enabled.
4 Pull-up/pull-down is active when pin is defined as an input and/or during reset, therefore, output enable is negated.
This also means that external pull-up/pull-down is NOT required unless specified.
5 For this 5-V output, a drive load of 200 pf is possible but with a rise/fall time of 300 ns.
6
During reset, the output enable to the pad driver is negated and the PD is active. After reset is negated, the PD is
disabled.
7
2.6-V outputs cannot be connected to a pull-up or driver greater than 3.1 V.
8 This pin requires a pull-up to 2.6 V if interrupts are ever enabled for this IRQ input.
9 This signal also includes the MDO5 function on the K27S mask set of the MPC561.
10
The MODCK[1:3] are shared functions with IRQ[5:7]. If IRQ[5:7] are used as interrupts, the interrupt source should
be removed during PORESET/TRST to insure the MODCK pins are in the correct state on the rising edge of
PORESET/TRST.
11 These pins are powered by KAPWR (keep-alive power supply). Any pull-ups on these pins should pull-up to
KAPWR.
MPC561/MPC563 Reference Manual, Rev. 1.2
2-44
Freescale Semiconductor
Signal Descriptions
12
An external pull-up is required in order to negate the signal in the appropriate time.
This pin is 5-V tolerant.
14
This signal was PD only until SPRDS is set on mask set K27S of the MPC561.
15
These values represent full drive, half drive and quarter drive.
16 Whether the Pull device is a pull-up or a pull-down is determined by the state of the PULL_SEL signal.
17
For this 5-V output, a drive load of 200 pf is possible, but will have a rise/fall time of 100ns.
18
MPC563 only, no connection on MPC561.
19
IRAMSTBY is the input to an approximately 1.7V voltage regulator. It should be connected through a resistor to a
standby power supply.
13
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
2-45
Signal Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
2-46
Freescale Semiconductor
Chapter 3
Central Processing Unit
The RISC processor (RCPU) used in the MPC500 family of microcontrollers integrates five independent
execution units: an integer unit (IU), a load/store unit (LSU), a branch processing unit (BPU), a
floating-point unit (FPU) and an integer multiplier divider (IMD). The RISC’s use of simple instructions
with rapid execution times yields high efficiency and throughput for PowerPC ISA-based systems.
Most integer instructions execute in one clock cycle. Instructions can complete out of order for increased
performance; however, the processor makes execution appear sequential.
This section provides an overview of the RCPU. For a detailed description of this processor, refer to the
RCPU Reference Manual. The following sections describe each block and sub-block.
3.1
RCPU Block Diagram
Figure 3-1 provides a block diagram of the RCPU.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-1
Central Processing Unit
RCPU
FPU
FPR
History
L-DATA
FPR
(32 X 64)
Load/Store
Floating Data
Load/
Store
Integer
Data
L-ADDR
Load/
Store
Address
Control Bus
Instruction
Sequencer
Instruction
Pre-fetch
Queue
GPR
History
Branch
Processor
Unit
GPR
(32 X 32)
I-ADDR
Next Address
Generation
(4 slots/clock)
IMUL/
IDIV
Source Buses
I-DATA
ALU/
BFU
Control
Regs
Write Back Bus
2 slots/clock
Figure 3-1. RCPU Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
3-2
Freescale Semiconductor
Central Processing Unit
3.2
RCPU Key Features
Major features of the RCPU include:
• High-performance microprocessor
— Single clock-cycle execution for many instructions
• Five independent execution units and two register files
— Independent LSU for load and store operations
— BPU featuring static branch prediction
— A 32-bit integer unit (IU)
— Fully IEEE 754-compliant FPU for both single- and double-precision operations except as
noted in Section 3.4.4, “Floating-Point Unit (FPU),” or refer to the RCPU Reference Manual.
— 32 general-purpose registers (GPRs) for integer operands
— 32 floating-point registers (FPRs) for single- or double-precision operands
• Facilities for enhanced system performance
— Atomic memory references
• In-system testability and debugging features
• High instruction and data throughput
— Condition register (CR) look-ahead operations performed by BPU
— Branch-folding capability during execution (zero-cycle branch execution time)
— Programmable static branch prediction on unresolved conditional branches
— A pre-fetch queue that can hold up to four instructions, providing look-ahead capability
— Interlocked pipelines with feed-forwarding that control data dependencies in hardware
• Class code compression model support
— Efficient use of internal Flash (MPC564) and external Flash (MPC562/MPC564) by increasing
code density up to 100%
3.3
Instruction Sequencer
The instruction sequencer provides centralized control over data flow between execution units and register
files. It implements the basic instruction pipeline, fetches instructions from the memory system, issues
them to available execution units, and maintains a state history that is used to back up the machine in the
event of an exception.
The instruction sequencer fetches instructions from the burst buffer controller into the instruction pre-fetch
queue. The BPU extracts branch instructions from the pre-fetch queue and, using branch prediction on
unresolved conditional branches, allows the instruction sequencer to fetch instructions from a predicted
target stream while a conditional branch is evaluated. The BPU folds out branch instructions for
unconditional or conditional branches unaffected by instructions in the execution stage.
Instructions issued beyond a predicted branch do not complete execution until the branch is resolved,
preserving the programming model of sequential execution. If branch prediction is incorrect, the
instruction unit flushes all predicted path instructions, and instructions are issued from the correct path.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-3
Central Processing Unit
Instruction Memory System
32
Instruction Buffer
Instruction Address Generator
32
Branch
Condition
Evaluation
Instruction
Pre-fetch
Queue
Read Write Buses
CC unit
32
Execution Units and Registers Files
Figure 3-2. Sequencer Data Path
3.4
Independent Execution Units
The PowerPC ISA architecture provides independent floating-point, integer, load/store, and branch
processing execution units, making it possible to implement advanced features such as look-ahead
operations. For example, since branch instructions do not depend on GPRs, branches can often be resolved
early, eliminating stalls caused by taken branches.
Table 3-1 summarizes the RCPU execution units.
Table 3-1. RCPU Execution Units
Unit
Branch processing unit (BPU)
Load/store unit (LSU)
Description
Includes the implementation of all branch instructions.
Includes implementation of all load and store instructions, whether defined as
part of the integer processor or the floating-point processor.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-4
Freescale Semiconductor
Central Processing Unit
Table 3-1. RCPU Execution Units (continued)
Unit
Description
Integer unit (IU)
Includes implementation of all integer instructions except load/store instructions.
This module includes the GPRs (including GPR history and scoreboard) and the
following subunits: the IMUL-IDIV, which includes the implementation of the
integer multiply and divide instructions and the ALU-BFU, which includes
implementation of all integer logic, add and subtract instructions, and bit field
instructions.
Floating-point unit (FPU)
Includes the FPRs (including FPR history and scoreboard) and the
implementation of all floating-point instructions except load/store floating-point
instructions.
The following sections describe these execution units in greater detail.
3.4.1
Branch Processing Unit (BPU)
The BPU, located within the instruction sequencer, performs condition register look-ahead operations on
conditional branches. The BPU looks through the instruction queue for a conditional branch instruction
and attempts to resolve it early, achieving the effect of a zero-cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch. Therefore,
when it encounters an unresolved conditional branch instruction, the processor pre-fetches instructions
from the predicted target stream until the conditional branch is resolved.
The BPU uses a calculation feature to compute branch target addresses with three special-purpose,
user-accessible registers: the link register (LR), the count register (CTR), and the condition register (CR).
The BPU calculates the return pointer for a subroutine, then calls and saves it into the LR. The LR also
contains the branch target address for the branch conditional to link register (bclrx) instruction. The CTR
contains the branch target address for the branch conditional to count register (bcctrx) instruction. The
contents of the LR and CTR can be copied to or from any GPR. Because the BPU uses dedicated registers
rather than general-purpose or floating-point registers, execution of branch instructions is independent
from execution of integer instructions. The CR bits indicate conditions that may result from the execution
of relevant instructions.
3.4.2
Integer Unit (IU)
The IU executes all integer processor instructions (except the integer storage access instructions)
implemented by the load/store unit. The IU contains the following subunits:
• The IMUL–IDIV unit, which implements the integer multiply and divide instructions
• The Arithmetic Logic Unit (ALU)–BFU unit, which implements all integer logic, add, subtract,
and bit-field instructions
The IU also includes the integer exception register (XER) and the general-purpose register file.
IMUL–IDIV and ALU–BFU are implemented as separate execution units. The ALU–BFU unit can
execute one instruction per clock cycle. IMUL–IDIV instructions require multiple clock cycles to execute.
IMUL–IDIV is pipelined for multiply instructions, so that consecutive multiply instructions can be issued
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-5
Central Processing Unit
on consecutive clock cycles. Divide instructions are not pipelined; an integer divide instruction preceded
or followed by an integer divide or multiply instruction results in a processor-pipeline stall. However, since
IMUL–IDIV and ALU–BFU are implemented as separate execution units, an integer divide instruction
preceded or followed by an ALU–BFU instruction does not cause a delay in the pipeline.
3.4.3
Load/Store Unit (LSU)
The load/store unit handles all data transfer between the general-purpose register file and the internal
load/store bus (L-bus). The load/store unit is implemented as an independent execution unit so that stalls
in the memory pipeline do not stall the master instruction pipeline (unless there is a data dependency). The
unit is fully pipelined so that memory instructions of any size may be issued on back-to-back cycles.
There is a 32-bit wide data path between the load/store unit and the general-purpose register file.
Single-word accesses can be achieved with an internal on-chip data RAM, resulting in a two-clock latency.
Double-word accesses require two clocks, resulting in a three-clock latency. Since the L-bus is 32 bits
wide, double-word transfers require two bus accesses. The load/store unit performs zero-fill for byte and
half-word transfers and sign extension for half-word transfers.
Addresses are formed by adding the source-one register operand specified by the instruction (or zero) to
either a source-two register operand or to a 16-bit, immediate value embedded in the instruction.
3.4.4
Floating-Point Unit (FPU)
The FPU contains a double-precision multiply array, the floating-point status and control register
(FPSCR), and the FPRs. The multiply-add array allows the RCPU to efficiently implement floating-point
operations such as multiply, multiply-add, and divide.
The RCPU depends on a software envelope to fully implement the IEEE floating-point specification.
Overflows, underflows, NaNs (not a number), and denormalized numbers cause floating-point assist
exceptions that invoke a software routine to deliver (with hardware assistance) the correct IEEE result.
To accelerate time-critical operations and make them more deterministic, the RCPU provides a mode of
operation that avoids invoking a software envelope and attempts to deliver results in hardware that are
adequate for most applications, if not in strict compliance with IEEE standards. In this mode, denormalized
numbers, NaNs, and IEEE invalid operations are legitimate, returning default results rather than causing
floating-point assist exceptions.
3.5
Levels of the PowerPC ISA Architecture
The PowerPC ISA architecture consists of three levels:
• User instruction set architecture (UISA) — defines the base user-level instruction set, user-level
registers, data types, floating-point exception model, memory models for a uniprocessor
environment, and programming model for a uniprocessor environment.
• Virtual environment architecture (VEA) — describes the memory model for a multiprocessor
environment, and describes other aspects of virtual environments.
Implementations that conform to the VEA also adhere to the UISA, but may not necessarily adhere
to the OEA.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-6
Freescale Semiconductor
Central Processing Unit
•
Operating environment architecture (OEA) — defines the memory-management model,
supervisor-level registers, synchronization requirements, and the exception model.
Implementations that conform to the OEA also adhere to the UISA and the VEA.
Adherence to the PowerPC ISA architecture can be measured in terms of which of the levels are
implemented.
3.6
RCPU Programming Model
The PowerPC ISA architecture defines register-to-register operations for most computational instructions.
Source operands for these instructions are accessed from the registers or are embedded in the instruction
opcode. The three-register instruction format allows specification of a target register distinct from the two
source operands. Load and store instructions transfer data between memory and on-chip registers.
PowerPC ISA-compliant processors have two levels of privilege: supervisor mode (typically used by the
operating environment) and user mode (used by the application software). The programming model
incorporates 32 GPRs, special-purpose registers (SPRs), and several miscellaneous registers.
Supervisor-level access is provided through the processor’s exception mechanism. That is, when an
exception is taken (whether automatically, because of an error or problem that needs to be serviced, or
deliberately, as in the case of a trap instruction), the processor begins operating in supervisor mode. The
access level is indicated by the privilege-level (PR) bit in the machine state register (MSR).
Figure 3-3 illustrates the user-level and supervisor-level RCPU programming models and the three levels
of the PowerPC ISA architecture. Note that registers such as the general-purpose registers (GPRs) are
accessed through operands that are part of the instructions. Registers can be accessed explicitly through
specific instructions such as move to special-purpose register (mtspr) or move from special-purpose
register (mftspr), or implicitly as part of an instruction’s execution. Some registers are accessed both
explicitly and implicitly.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-7
Central Processing Unit
SUPERVISOR MODEL OEA
USER MODEL UISA
Machine State Register
FPR0
FPR1
MSR
0
31
Supervisor-Level SPRs
FPR31
63
0
GPR0
GPR1
See Table 3-2 for list of
supervisor-level SPRs.
Condition
Register
CR
0
GPR31
0
31
31
0
Development Support SPRs
31 Floating-Point Status
and Control Register
See Table 3-3 for list of
development-support SPRs.
FPSCR
0
31
0
User-Level SPRs
31
Integer Exception Register (XER)
Link Register (LR)
Count Register (CTR)
31
0
USER MODEL VEA
Time Base Facility (for Reading)
Time Base Lower – Read (TBL)
Time Base Upper – Read (TBU)
Figure 3-3. RCPU Programming Model
MPC561/MPC563 Reference Manual, Rev. 1.2
3-8
Freescale Semiconductor
Central Processing Unit
Table 3-2 lists the MPC561/MPC563 supervisor-level registers; refer also to Chapter 6, “System
Configuration and Protection,” Chapter 11, “L-Bus to U-Bus Interface (L2U),” and Chapter 4, “Burst
Buffer Controller 2 Module,” for more information.
Table 3-2. Supervisor-Level SPRs
SPR Number
(Decimal)
Special-Purpose Register
18
DAE/Source Instruction Service Register (DSISR)
See Section 3.9.2, “DAE/Source Instruction Service
Register (DSISR),” for bit descriptions.
19
Data Address Register (DAR)
See Section 3.9.3, “Data Address Register (DAR),” for bit
descriptions.
22
Decrementer Register (DEC)
See Section 6.1.6, “Decrementer (DEC).” for bit
descriptions.
26
Save and Restore Register 0 (SRR0)
See Section 3.9.6, “Machine Status Save/Restore
Register 0 (SRR0),” for bit descriptions.
27
Save and Restore Register 1 (SRR1)
See Section 3.9.7, “Machine Status Save/Restore
Register 1 (SRR1),” for bit descriptions.
80
External Interrupt Enable (EIE)1
See Section 3.9.10.1, “EIE, EID, and NRI
Special-Purpose Registers.”
81
External Interrupt Disable (EID)1
See Section 3.9.10.1, “EIE, EID, and NRI
Special-Purpose Registers.”
82
Non-Recoverable Interrupt (NRI)1
See Section 3.9.10.1, “EIE, EID, and NRI
Special-Purpose Registers.”
272
SPR General 0 (SPRG0)1
See Section 3.9.8, “General SPRs (SPRG0–SPRG3),”
for bit descriptions.
273
SPR General 1 (SPRG1)1
See Section 3.9.8, “General SPRs (SPRG0–SPRG3),”
for bit descriptions.
274
SPR General 2 (SPRG2)
See Section 3.9.8, “General SPRs (SPRG0–SPRG3),”
for bit descriptions.
275
SPR General 3 (SPRG3)
See Section 3.9.8, “General SPRs (SPRG0–SPRG3),”
for bit descriptions.
284
Time Base Lower – Write (TBL)
See Section 6.1.7, “Time Base (TB).”
285
Time Base Upper – Write (TBU)
See Section 6.1.7, “Time Base (TB).”
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-9
Central Processing Unit
Table 3-2. Supervisor-Level SPRs (continued)
SPR Number
(Decimal)
Special-Purpose Register
287
Processor Version Register (PVR)
See Table 3-14 for bit descriptions.
528
IMPU Global Region Attribute (MI_GRA)1
See Table 4-8 for bit descriptions.
536
L2U Region Attribute (L2U_GRA)
See Table 11-10 for bit descriptions.
560
BBC Module Configuration Register (BBC_MCR)1
See Table 4-4 for bit descriptions.
568
L2U Module Configuration Register (L2U_MCR)1
See Table 11-7 for bit descriptions.
784
L2U Region Base Address Register 0 (L2U_RBA0)1
See Table 4-5 for bit descriptions.
785
IMPU Region Base Address Register 1 (MI_RBA1)1
See Table 4-5 for bits descriptions.
786
IMPU Region Base Address Register 2 (MI_RBA2)1
See Table 4-5 for bits descriptions.
787
IMPU Region Base Address Register 3 (MI_RBA3)1
See Table 4-5 for bits descriptions.
816
IMPU Region Attribute Register 0 (MI_RA0)1. See
Table 4-6 for bits descriptions.
817
IMPU Region Attribute Register 1 (MI_RA1)1. See
Table 4-6 for bits descriptions.
818
IMPU Region Attribute Register 2 (MI_RA2)1. See
Table 4-6 for bits descriptions.
819
IMPU Region Attribute Register 3(MI_RA3)1. See
Table 4-6 for bits descriptions.
792
L2U Region Base Address Register 0 (L2U_RBA0)1
See Table 11-8 for bit descriptions.
793
L2U Region Base Address Register 1 (L2U_RBA1)1
See Table 11-8 for bit descriptions.
794
L2U Region Base Address Register 2 (L2U_RBA2)1
See Table 11-8 for bit descriptions.
795
L2U Region Base Address Register 3 (L2U_RBA3)1
See Table 11-8 for bit descriptions.
824
L2U Region Attribute Register 0 (L2U_RA0)1
See Table 11-9 for bit descriptions.
825
L2U Region Attribute Register 1 (L2U_RA1)1
See Table 11-9 for bit descriptions.
826
L2U Region Attribute Register 2 (L2U_RA2)1
See Table 11-9 for bit descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-10
Freescale Semiconductor
Central Processing Unit
Table 3-2. Supervisor-Level SPRs (continued)
SPR Number
(Decimal)
1
Special-Purpose Register
827
L2U Region Attribute Register 3 (L2U_RA3)1
See Table 11-9 for bit descriptions.
1022
Floating-Point Exception Cause Register (FPECR)1
See Section 3.9.10.2, “Floating-Point Exception Cause
Register (FPECR),” for bit descriptions.
Implementation-specific SPR, not defined by the PowerPC ISA
architecture.
Table 3-3 lists the RCPU SPRs used for development support.
Table 3-3. Development Support SPRs1
SPR Number
(Decimal)
Special-Purpose Register
144
Comparator A Value Register (CMPA)
See Table 23-17 for bit descriptions.
145
Comparator B Value Register (CMPB)
See Table 23-17 for bit descriptions.
146
Comparator C Value Register (CMPC)
See Table 23-17 for bit descriptions.
147
Comparator D Value Register (CMPD)
See Table 23-17 for bit descriptions.
148
Exception Cause Register (ECR)
See Table 23-18 for bit descriptions.
149
Debug Enable Register (DER)
See Table 23-19 for bit descriptions.
150
Breakpoint Counter A Value and Control (COUNTA)
See Table 23-20 for bit descriptions.
151
Breakpoint Counter B Value and Control (COUNTB)
See Table 23-21 for bit descriptions.
152
Comparator E Value Register (CMPE)
See Table 23-22 for bit descriptions.
153
Comparator F Value Register (CMPF)
See Table 23-22 for bit descriptions.
154
Comparator G Value Register (CMPG)
See Table 23-23 for bit descriptions.
155
Comparator H Value Register (CMPH)
See Table 23-23 for bit descriptions.
156
L-bus Support Comparators Control 1 (LCTRL1)
See Table 23-24 for bit descriptions.
157
L-bus Support Comparators Control 2 (LCTRL2)
See Table 23-25 for bit descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-11
Central Processing Unit
Table 3-3. Development Support SPRs1 (continued)
SPR Number
(Decimal)
1
Special-Purpose Register
158
I-bus Support Control Register (ICTRL)
See Table 23-26 for bit descriptions.
159
Breakpoint Address Register (BAR)
See Table 23-28 for bit descriptions.
630
Development Port Data Register (DPDR)
See Section 23.6.13, “Development Port Data Register
(DPDR),” for bit descriptions.
All development-support SPRs are implementation-specific.
Unless otherwise noted, reserved fields should be written with a zero when written and return zero when
read. An exception to this rule is XER[16:23]; see Section 3.7.5, “Integer Exception Register (XER).”
These bits are set to the value written to them and return that value when read.
3.7
User Instruction Set Architecture (UISA)
Register Set
The UISA registers can be accessed by either user- or supervisor-level instructions. The general-purpose
registers are accessed through instruction operands.
3.7.1
General-Purpose Registers (GPRs)
Integer data is manipulated in the integer unit’s thirty-two 32-bit GPRs, shown below. These registers are
accessed as source and destination registers through operands in the instruction syntax.
MSB
0
LSB
1
2 3 4 5
6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31
GPR0
GPR1
...
...
GPR31
Reset
Unchanged
Figure 3-4. General-Purpose Registers (GPRs)
3.7.2
Floating-Point Registers (FPRs)
The PowerPC ISA architecture provides 32 64-bit FPRs. These registers are accessed as source and
destination registers through operands in floating-point instructions. Each FPR supports the
double-precision, floating-point format. Every instruction that interprets the contents of an FPR as a
MPC561/MPC563 Reference Manual, Rev. 1.2
3-12
Freescale Semiconductor
Central Processing Unit
floating-point value does so using the double-precision floating-point format. Therefore, all floating-point
numbers are stored in double-precision format.
All floating-point arithmetic instructions operate on data located in FPRs and, with the exception of the
compare instructions (which update the CR), place the result into an FPR. Information about the status of
floating-point operations is placed into the floating-point status and control register (FPSCR) and in some
cases, after the completion of the operation’s writeback stage, into the CR. For information on how the CR
is affected by floating-point operations, see Section 3.7.4, “Condition Register (CR).”
MSB
LSB
0
63
FPR0
FPR1
...
...
FPR31
Reset
Unchanged
Figure 3-5. Floating-Point Registers (FPRs)
3.7.3
Floating-Point Status and Control Register (FPSCR)
The FPSCR controls the handling of floating-point exceptions and records status resulting from the
floating-point operations. FPSCR[0:23] are status bits. FPSCR[24:31] are control bits.
FPSCR[0:12] and FPSCR[21:23] are floating-point exception condition bits. These bits are sticky, except
for the floating-point enabled exception summary (FEX) and floating-point invalid operation exception
summary (VX). Once set, sticky bits remain set until they are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0
instruction.
Table 3-4 summarizes which bits in the FPSCR are sticky status bits, which are normal status bits, and
which are control bits.
Table 3-4. FPSCR Bit Categories
Bits
[0], [3:12], [21:23]
[1:2], [13:20]
[24:31]
Type
Status, sticky
Status, not sticky
Control
FEX and VX are the logical ORs of other FPSCR bits. Therefore these two bits are not listed among the
FPSCR bits directly affected by the various instructions.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-13
Central Processing Unit
MSB
0
1
2
Field FX FEX VX
3
4
5
6
OX
UX
ZX
XX
7
13
14
15
VXSN VXISI VXIDI VXZDZ VXIMZ VXVC FR
AN
FI
FPRF0
Reset
8
9
10
11
12
Unchanged
LSB
16
Field
17
18
FPRF[1:4]
19
20
0
21
22
23
VX
VX VXCVI
SOFT SQRT
Reset
24
25
26
27
28
29
VE
OE
UE
ZE
XE
NI
30
31
RN
Unchanged
Figure 3-6. Floating-Point Status and Control Register (FPSCR)
A listing of FPSCR bit settings is shown in Table 3-5.
Table 3-5. FPSCR Bit Descriptions
Bits
Name
Description
0
FX
Floating-point exception summary. Every floating-point instruction implicitly
sets FPSCR[FX] if that instruction causes any of the floating-point exception
bits in the FPSCR to change from 0 to 1. The mcrfs instruction implicitly clears
FPSCR[FX] if the FPSCR field containing FPSCR[FX] has been copied. The
mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can set or clear FPSCR[FX]
explicitly.
Sticky bit
1
FEX
Floating-point enabled exception summary. This bit signals the occurrence of
any of the enabled exception conditions. It is the logical OR of all the
floating-point exception bits masked with their respective enable bits. The
mcrfs instruction implicitly clears FPSCR[FEX] if the result of the logical OR
described above becomes zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1
instructions cannot set or clear FPSCR[FEX] explicitly.
Not sticky
2
VX
Floating-point invalid operation exception summary. This bit signals the
occurrence of any invalid operation exception. It is the logical OR of all of the
invalid operation exceptions. The mcrfs instruction implicitly clears
FPSCR[VX] if the result of the logical OR described above becomes zero. The
mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear FPSCR[VX]
explicitly.
Not sticky
3
OX
Floating-point overflow exception.
Sticky bit
4
UX
Floating-point underflow exception.
Sticky bit
5
ZX
Floating-point zero divide exception.
Sticky bit
6
XX
Floating-point inexact exception.
Sticky bit
7
VXSNAN
Floating-point invalid operation exception for SNaN.
Sticky bit
8
VXISI
Floating-point invalid operation exception for ∞ - ∞.
Sticky bit
9
VXIDI
Floating-point invalid operation exception for ∞/∞.
Sticky bit
10
VXZDZ
Floating-point invalid operation exception for 0/0.
Sticky bit
11
VXIMZ
Floating-point invalid operation exception for ∞ x 0.
Sticky bit
MPC561/MPC563 Reference Manual, Rev. 1.2
3-14
Freescale Semiconductor
Central Processing Unit
Table 3-5. FPSCR Bit Descriptions (continued)
Bits
Name
12
VXVC
13
Description
Floating-point invalid operation exception for invalid compare.
Sticky bit
FR
Floating-point fraction rounded. The last floating-point instruction that
potentially rounded the intermediate result incremented the fraction.
Not sticky
14
FI
Floating-point fraction inexact. The last floating-point instruction that
potentially rounded the intermediate result produced an inexact fraction or a
disabled exponent overflow.
Not sticky
[15:19]
FPRF
Floating-point result flags. This field is based on the value placed into the
target register even if that value is undefined. Refer to Table 3-6 for specific bit
settings.
15 Floating-point result class descriptor (C). Floating-point instructions other
than the compare instructions may set this bit with the FPCC bits, to
indicate the class of the result.
16-19 Floating-point condition code (FPCC). Floating-point compare
instructions always set one of the FPCC bits to one and the other three
FPCC bits to zero. Other floating-point instructions may set the FPCC bits
with the C bit, to indicate the class of the result. Note that in this case the
high-order three bits of the FPCC retain their relational significance
indicating that the value is less than, greater than, or equal to zero.
16 Floating-point less than or negative (FL or <)
17 Floating-point greater than or positive (FG or >)
18 Floating-point equal or zero (FE or =)
19 Floating-point unordered or NaN (FU or ?)
Not sticky
20
—
21
VXSOFT
Floating-point invalid operation exception for software request. This bit can be
altered only by the mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The
purpose of VXSOFT is to allow software to cause an invalid operation
condition for a condition that is not necessarily associated with the execution
of a floating-point instruction. For example, it might be set by a program that
computes a square root if the source operand is negative.
Sticky bit
22
VXSQRT
Floating-point invalid operation exception for invalid square root. This
guarantees that software can simulate fsqrt and frsqrte, and can provide a
consistent interface to handle exceptions caused by square root operations.
Sticky bit
23
VXCVI
Floating-point invalid operation exception for invalid integer convert.
Sticky bit
24
VE
Floating-point invalid operation exception enable.
—
25
OE
Floating-point overflow exception enable.
—
26
UE
Floating-point underflow exception enable. This bit should not be used to
determine whether denormalization should be performed on floating-point
stores.
—
27
ZE
Floating-point zero divide exception enable.
—
28
XE
Floating-point inexact exception enable.
—
Reserved
—
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-15
Central Processing Unit
Table 3-5. FPSCR Bit Descriptions (continued)
Bits
Name
Description
29
NI
Non-IEEE mode bit.
—
30–31
RN
Floating-point rounding control.
00 Round to nearest
01 Round toward zero
10 Round toward +infinity
11 Round toward -infinity
—
Table 3-6 illustrates the floating-point result flags that correspond to FPSCR[15:19].
Table 3-6. Floating-Point Result Flags in FPSCR
3.7.4
Result Flags
(Bits 15:19)
C<>=?
Result Value Class
10001
Quiet NaN
01001
– Infinity
01000
– Normalized number
11000
– Denormalized number
10010
– Zero
00010
+ Zero
10100
+ Denormalized number
00100
+ Normalized number
00101
+ Infinity
Condition Register (CR)
The condition register (CR) is a 32-bit register that reflects the result of certain operations and provides a
mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit fields: CR0 to CR7.
MSB
0
Field
Reset
LSB
1
CR0
2
3
4
5
6
CR1
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CR2
CR3
CR4
CR5
CR6
31
CR7
Unchanged
Figure 3-7. Condition Register (CR)
The CR fields can be set in the following ways:
• Specified fields of the CR can be set by an instruction (mtcrf) to move to the CR from a GPR.
• Specified fields of the CR can be moved from one CRx field to another with the mcrf instruction.
• A specified field of the CR can be set by an instruction (mcrxr) to move to the CR from the XER.
• Condition register logical instructions can be used to perform logical operations on specified bits
in the condition register.
• CR0 can be the implicit result of an integer operation.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-16
Freescale Semiconductor
Central Processing Unit
•
A specified CR field can be the explicit result of an integer compare instruction.
Instructions are provided to test individual CR bits.
3.7.4.1
Condition Register CR0 Field Definition
In most integer instructions, when the CR is set to reflect the result of the operation (that is, when Rc = 1),
and for addic., andi., and andis., the first three bits of CR0 are set by an algebraic comparison of the result
to zero; the fourth bit of CR0 is copied from XER[SO]. For integer instructions, CR0[0:3] are set to reflect
the result as a signed quantity. The EQ bit reflects the result as an unsigned quantity or bit string.
The CR0 bits are interpreted as shown in Table 3-7. If any portion of the result (the 32-bit value placed
into the destination register) is undefined, the value placed in the first three bits of CR0 is undefined.
Table 3-7. Bit Settings for CR0 Field of CR
CR0 Bit
Description
0
Negative (LT). This bit is set when the result is negative.
1
Positive (GT). This bit is set when the result is positive (and not zero).
2
Zero (EQ). This bit is set when the result is zero.
3
Summary overflow (SO). This is a copy of the final state of XER[SO] at the completion of the instruction.
3.7.4.2
Condition Register CR1 Field Definition
In all floating-point instructions when the CR is set to reflect the result of the operation (that is, when Rc
= 1), the CR1 field (bits 4 to 7 of the CR) is copied from FPSCR[0:3] to indicate the floating-point
exception status. For more information about the FPSCR, see Section 3.7.3, “Floating-Point Status and
Control Register (FPSCR).” The bit settings for the CR1 field are shown in Table 3-8.
Table 3-8. Bit Settings for CR1 Field of CR
CR1 Bit
Description
0
Floating-point exception (FX). This is a copy of the final state of FPSCR[FX] at the completion of the
instruction.
1
Floating-point enabled exception (FEX).This is a copy of the final state of FPSCR[FEX] at the completion of
the instruction.
2
Floating-point invalid exception (VX).This is a copy of the final state of FPSCR[VX] at the completion of the
instruction.
3
Floating-point overflow exception (OX).This is a copy of the final state of FPSCR[OX] at the completion of
the instruction.
3.7.4.3
Condition Register CRn Field — Compare Instruction
When a specified CR field is set by a compare instruction, the bits of the specified field are interpreted as
shown in Table 3-9. A condition register field can also be accessed by the mfcr, mcrf, and mtcrf
instructions.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-17
Central Processing Unit
Table 3-9. CRn Field Bit Settings for Compare Instructions
1
CRn Bit1
Description
0
Less than, floating-point less than (LT, FL).
For integer compare instructions, (rA) < SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison). For floating-point compare instructions, (frA) < (frB).
1
Greater than, floating-point greater than (GT, FG).
For integer compare instructions, (rA) > SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM,
or (rB) (logical comparison). For floating-point compare instructions, (frA) > (frB).
2
Equal, floating-point equal (EQ, FE).
For integer compare instructions, (rA) = SIMM, UIMM, or (rB).
For floating-point compare instructions, (frA) = (frB).
3
Summary overflow, floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of the final state of XER[SO] at the completion of the
instruction. For floating-point compare instructions, one or both of (frA) and (frB) is not a number (NaN).
Here, the bit indicates the bit number in any one of the four-bit subfields, CR0–CR7
3.7.5
Integer Exception Register (XER)
The integer exception register (XER), SPR 1, is a user-level, 32-bit register.
MSB
0
LSB
1
2
3
4
Field SO OV CA
Reset
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
—
Unchanged
Addr
5
31
BYTES
00_0000_0000_0000_0000_0
Unchanged
SPR 1
Figure 3-8. Integer Exception Register (XER)
The bit descriptions for XER, shown in Table 3-10, are based on the operation of an instruction considered
as a whole, not on intermediate results. For example, the result of the subtract from carrying (subfcx)
instruction is specified as the sum of three values. This instruction sets bits in the XER based on the entire
operation, not on an intermediate sum.
In most cases, reserved fields in registers are ignored when written to and return zero when read. However,
XER[16:23] are set to the value written to them and return that value when read.
Table 3-10. Integer Exception Register Bit Descriptions
Bits
Name
Description
0
SO
Summary Overflow (SO). The summary overflow bit is set whenever an instruction sets the
overflow bit (OV) to indicate overflow and remains set until software clears it. It is not altered by
compare instructions or other instructions that cannot overflow.
1
OV
Overflow (OV). The overflow bit is set to indicate that an overflow has occurred during execution
of an instruction. Integer and subtract instructions having OE=1 set OV if the carry out of bit 0 is
not equal to the carry out of bit 1, and clear it otherwise. The OV bit is not altered by compare
instructions or other instructions that cannot overflow.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-18
Freescale Semiconductor
Central Processing Unit
Table 3-10. Integer Exception Register Bit Descriptions
Bits
Name
Description
2
CA
Carry (CA). In general, the carry bit is set to indicate that a carry out of bit 0 occurred during
execution of an instruction. Add carrying, subtract from carrying, add extended, and subtract
from extended instructions set CA if there is a carry out of bit 0, and clear it otherwise. The CA
bit is not altered by compare instructions or other instructions that cannot carry, except that shift
right algebraic instructions set the CA bit to indicate whether any ‘1’ bits have been shifted out
of a negative quantity.
3:24
—
Reserved
25:31
BYTES
3.7.6
This field specifies the number of bytes to be transferred by a Load String Word Indexed (lswx)
or Store String Word Indexed (stswx) instruction.
Link Register (LR)
The link register (LR), SPR 8, supplies the branch target address for the branch conditional to link register
(bclrx) instruction, and can be used to hold the logical address of the instruction that follows a branch and
link instruction.
Note that although the two least-significant bits can accept any values written to them, they are ignored
when the LR is used as an address.
Both conditional and unconditional branch instructions include the option of placing the effective address
of the instruction after the branch instruction in the LR. This is done regardless of whether the branch is
taken.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
Branch Address
Reset
Unchanged
Addr
SPR 8
31
Figure 3-9. Link Register (LR)
3.7.7
Count Register (CTR)
The count register (CTR), SPR 9, is used to hold a loop count that can be decremented during execution
of branch instructions with an appropriately coded BO field. If the value in CTR is 0 before being
decremented, it is –1 afterward. The count register provides the branch target address for the branch
conditional to count register (bcctrx) instructio
MSB
0
LSB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
Loop Count
Reset
Unchanged
Addr
SPR 9
31
Figure 3-10. Count Register (CTR)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-19
Central Processing Unit
3.8
VEA Register Set — Time Base (TB)
The virtual environment architecture (VEA) defines registers in addition to the UISA register set. The
VEA register set can be accessed by all software with either user- or supervisor-level privileges. Refer to
Section 6.1.7, “Time Base (TB),” for more information.
3.9
OEA Register Set
The operating environment architecture (OEA) includes a number of SPRs and other registers that are
accessible only by supervisor-level instructions. Some SPRs are RCPU-specific; some RCPU SPRs may
not be implemented in other PowerPC ISA processors, or may not be implemented in the same way.
3.9.1
Machine State Register (MSR)
The machine state register is a 32-bit register that defines the state of the processor. When an exception
occurs, the contents of the MSR are loaded into SRR1, and the MSR is updated to reflect the
exception-processing machine state. The MSR can also be modified by the mtmsr, sc, and rfi instructions.
It can be read by the mfmsr instruction.
11
MSB
0
1
2
3
4
5
Field
6
7
8
9
10
11
12
—
SRESET
13
14
15
POW
0
ILE
0000_0000_0000_0000
LSB
16
Field EE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PR
FP
ME
FE0
SE
BE
FE1
—
IP
IR
DR
—
DCMPEN
RI
LE
1
SRESET
000
U
0000_0
ID12
000
X3
00
Figure 3-11. Machine State Register (MSR)
1
This bit is available only on code compression-enabled options of the MPC561/MPC563.
The reset value is a reset configuration word value extracted from the internal bus line. Refer to Section 7.5.2, “Hard
Reset Configuration Word (RCW).”
3
The reset value is defined by the equation "BBCMCR[EN_COMP] AND BBCMCR[EXC_COMP]". At HRESET the
BBCMCR[EN_COMP] and BBCMCR[EXC_COMP] bits recieve their values from RCW bits 21 and 22. The BBCMCR
does not change at SRESET. Thus the DCMPEN reset value may be different on SRESET and HRESET, if software
changes these BBCMCR bits from their reset values.
2
Table 3-11 shows the bit definitions for the MSR.
Table 3-11. Machine State Register Bit Descriptions
Bits
Name
0:12
—
13
POW
Description
Reserved
Power management enable.
0 Power management disabled (normal operation mode)
1 Power management enabled (reduced power mode)
MPC561/MPC563 Reference Manual, Rev. 1.2
3-20
Freescale Semiconductor
Central Processing Unit
Table 3-11. Machine State Register Bit Descriptions (continued)
Bits
Name
Description
14
—
Reserved
15
ILE
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to
select the endian mode for the context established by the exception. Little-endian mode is not
supported on the MPC561/MPC563. This bit should be cleared to 0 at all times.
0 The processor runs in big-endian mode during exception processing.
1 The processor runs in little-endian mode during exception processing.
16
EE
External interrupt enable. Interrupts should only be negated while the EE bit is disabled (0).
Software should disable interrupts (EE = 0) in the RCPU before clearing or masking any
interrupt source from the USIU or external pins. For external interrupts, it is recommended that
the edge-triggered interrupt scheme be used. See Section 6.1.4, “Enhanced Interrupt
Controller.”
0 The processor delays recognition of external interrupts and decrementer exception
conditions.
1 The processor is enabled to take an external interrupt or the decrementer exception.
17
PR
Privilege level.
0 The processor can execute both user- and supervisor-level instructions.
1 The processor can only execute user-level instructions.
18
FP
Floating-point available.
0 The processor prevents dispatch of floating-point instructions, including floating-point loads,
stores and moves. Floating-point enabled program exceptions can still occur and the FPRs
can still be accessed.
1 The processor can execute floating-point instructions, and can take floating-point enabled
exception type program exceptions.
19
ME
Machine check enable.
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
20
FE0
Floating-point exception mode 0 (See Table 3-12.)
21
SE
Single-step trace enable.
0 The processor executes instructions normally.
1 The processor generates a single-step trace exception when the next instruction executes
successfully. When this bit is set, the processor dispatches instructions in strict program
order. Successful execution means the instruction caused no other exception.
22
BE
Branch trace enable.
0 No trace exception occurs when a branch instruction is completed.
1 Trace exception occurs when a branch instruction is completed.
23
FE1
Floating-point exception mode 1 (See Table 3-12).
24
—
Reserved
25
IP
Exception prefix. The setting of this bit specifies the location of the exception vector table.
0 Exception vector table starts at the physical address 0x0000 0000.
1 Exception vector table starts at the physical address 0xFFF0 0000.
26
IR
Instruction relocation.
0 Instruction address translation is off; the BBC IMPU does not check for address permission
attributes.
1 Instruction address translation is on; the BBC IMPU checks for address permission
attributes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-21
Central Processing Unit
Table 3-11. Machine State Register Bit Descriptions (continued)
Bits
Name
27
DR
Data relocation.
0 Data address translation is off; the L2U DMPU does not check for address permission
attributes.
1 Data address translation is on; the L2U DMPU checks for addressn permission attributes.
28
—
Reserved
29
Description
DCMPEN Decompression On/Off. The reset value of this bit is (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP]).
Note: This bit should not be set for the MPC561/MPC563.
0 The RCPU runs in normal operation mode.
1 The RCPU runs in compressed mode.
Note: MSR[DCMPEN] should not be changed by software by a direct MSR register write
(MTMSR instruction). It can be changed only by the RFI instruction or by an exception.
30
RI
Recoverable exception (for machine check and non-maskable breakpoint exceptions).
0 Machine state is not recoverable.
1 Machine state is recoverable.
31
LE
Little-endian mode. This mode is not supported on MPC561/MPC563. This bit should be
cleared to 0 at all times.
0 The processor operates in big-endian mode during normal processing.
1 The processor operates in little-endian mode during normal processing.
The floating-point exception mode bits are interpreted as shown in Table 3-12.
Table 3-12. Floating-Point Exception Mode Bits
FE[0:1]
Mode
00
Ignore exceptions mode. Floating-point exceptions do not cause the
floating-point assist error handler to be invoked.
01, 10, 11
3.9.2
Floating-point precise mode. The system floating-point assist error
handler is invoked precisely at the instruction that caused the enabled
exception.
DAE/Source Instruction Service Register (DSISR)
The DSISR, SPR 18, identifies the cause of data access and alignment exceptions.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
DSISR
Reset
Unchanged
Addr
SPR 18
31
Figure 3-12. DAE/Source Instruction Service Register (DSISR)
For more information about bit settings, see Section 3.15.4.2, “Machine Check Exception (0x0200),”
Section 3.15.4.6, “Alignment Exception (0x00600),” and Section 3.15.4.15, “Implementation-Specific
Data Protection Error Exception (0x1400).”
MPC561/MPC563 Reference Manual, Rev. 1.2
3-22
Freescale Semiconductor
Central Processing Unit
3.9.3
Data Address Register (DAR)
After an alignment exception, the DAR, SPR 19, is set to the effective address of a load or store element.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
Data Address
Reset
Unchanged
Addr
SPR 19
31
Figure 3-13. Data Address Register (DAR)
3.9.4
Time Base Facility (TB) — OEA
Refer to Section 6.1.7, “Time Base (TB),” for information.
3.9.5
Decrementer Register (DEC)
Refer to Section 6.1.6, “Decrementer (DEC),” for information.
3.9.6
Machine Status Save/Restore Register 0 (SRR0)
The machine status save/restore register 0 (SRR0), SPR 26, identifies where instruction execution should
resume when an rfi instruction is executed following an exception. It also holds the effective address of
the instruction that follows the system call (sc) instruction.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
SRR0
Reset
Undefined
Addr
SPR 26
31
Figure 3-14. Machine Status Save/Restore Register 0 (SRR0)
When an exception occurs, SRR0 is set to point to an instruction such that all prior instructions have
completed execution and no subsequent instruction has begun execution. The instruction addressed by
SRR0 may not have completed execution, depending on the exception type. SRR0 addresses either the
instruction causing the exception or the instruction immediately following. The instruction addressed can
be determined from the exception type and status bits.
3.9.7
Machine Status Save/Restore Register 1 (SRR1)
The machine status save/restore register 1 (SRR1), SPR 27, saves the machine status on exceptions and
restores the machine status when an rfi instruction is executed.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-23
Central Processing Unit
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
SRR1
Reset
Undefined
Addr
SPR 27
31
Figure 3-15. Machine Status Save/Restore Register 1 (SRR1)
In general, when an exception occurs, SRR1[0:15] are loaded with exception-specific information, and
MSR[16:31] are placed into SRR1[16:31].
3.9.8
General SPRs (SPRG0–SPRG3)
SPRG0–SPRG3, SPRs 272-275, are provided for general operating system use, such as fast-state saves
and multiprocessor-implementation support. SPRG0–SPRG3 are shown below.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31
SPRG0
SPRG1
SPRG2
SPRG3
Reset
Unchanged
Figure 3-16. SPRG0–SPRG3 — General Special-Purpose Registers 0–3
Uses for SPRG0–SPRG3 are shown in Table 3-13.
Table 3-13. Uses of SPRG0–SPRG3
Register
Description
SPRG0
Software may load a unique physical address in this register to identify an area of memory reserved for use
by the exception handler. This area must be unique for each processor in the system.
SPRG1
This register may be used as a scratch register by the exception handler to save the content of a GPR. That
GPR then can be loaded from SPRG0 and used as a base register to save other GPRs to memory.
SPRG2
This register may be used by the operating system as needed.
SPRG3
This register may be used by the operating system as needed.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-24
Freescale Semiconductor
Central Processing Unit
3.9.9
Processor Version Register (PVR)
The PVR is a 32-bit, read-only register that identifies the version and revision level of the processor. The
contents of the PVR can be copied to a GPR by the mfspr instruction. Read access to the PVR is available
in supervisor mode only; write access is not provided.
MSB
0
LSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Field
VERSION
REVISION
Reset
0000_0000_0000_0010
0000_0000_0010_0000
Addr
31
SPR 287
Figure 3-17. Processor Version Register (PVR)
Table 3-14. Processor Version Register Bit Descriptions
Bits
Name
Description
0:15
VERSION
A 16-bit number that identifies the version of the PowerPC ISA processor. The RCPU value
is 0x0002.
16:31
REVISION
A 16-bit number that distinguishes between various releases of a particular version. The
RCPU value is 0x0020.
3.9.10
Implementation-Specific SPRs
The MPC561/MPC563 includes several implementation-specific SPRs that are not defined by the
PowerPC ISA architecture. These registers, listed in Table 3-2 and Table 3-3, can be accessed by
supervisor-level instructions only.
3.9.10.1
EIE, EID, and NRI Special-Purpose Registers
The RCPU includes three implementation-specific SPRs that facilitate the software manipulation of the
MSR[RI] and MSR[EE] bits: External Interrupt Enable (EIE), External Interrupt Disable (EID), and
Non-recoverable Interrupt (NRI). Issuing the mtspr instruction with one of these registers as an operand
causes the RI and EE bits to be set or cleared as shown in Table 3-15.
Table 3-15. EIE, EID, AND NRI Registers
SPR Number
(Decimal)
Mnemonic
MSR[EE]
MSR[RI]
80
EIE
1
1
81
EID
0
1
82
NRI
0
0
A read (mfspr) of any of these locations is treated as an unimplemented instruction, resulting in a software
emulation exception.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-25
Central Processing Unit
3.9.10.2
Floating-Point Exception Cause Register (FPECR)
The FPECR, SPR 1022, is a supervisor-level internal status and control register used by the user’s
floating-point assist software envelope. It contains four status bits that indicate whether the result of the
operation is tiny and whether any of three source operands are denormalized. In addition, it contains one
control bit to enable or disable SIE mode. This register must not be accessed by user code.
MSB
0
1
2
3
4
5
6
7
8
Field SIE
9
10
11
12
13
14
26
27
28
29
30
15
—
SRESET
0000_0000_0000_0000
LSB
16
17
18
Field
19
20
21
22
23
24
25
—
SRESET
DNC DNB DNA
31
TR
0000_0000_0000_0000
Addr
SPR 1022
Figure 3-18. Floating-Point Exception Cause Register (FPECR)
A listing of FPECR bit settings is shown in Table 3-16.
Table 3-16. FPECR Bit Descriptions
Bits
Name
Description
0
SIE
1:27
—
28
DNC
Source operand C denormalized status bit.
0 Source operand C is not denormalized
1 Source operand C is denormalized
29
DNB
Source operand B denormalized status bit.
0 Source operand B is not denormalized
1 Source operand B is denormalized
30
DNA
Source operand A denormalized status bit.
0 Source operand A is not denormalized
1 Source operand A is denormalized
31
TR
Synchronized ignore exception mode control bit.
0 Disable SIE mode
1 Enable SIE mode
Reserved
Floating-point tiny result.
0 Floating-point result is not tiny
1 Floating-point result is tiny
NOTE
Software must insert a sync instruction before reading the FPECR.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-26
Freescale Semiconductor
Central Processing Unit
3.9.10.3
Additional Implementation-Specific Registers
Refer to the following sections for details on additional implementation-specific registers in the
MPC561/MPC563:
• Section 4.6, “BBC Programming Model”
• Section 6.2.2.1.2, “Internal Memory Map Register (IMMR)”
• Section 11.8, “L2U Programming Model”
• Chapter 23, “Development Support”
3.10
Instruction Set
All PowerPC ISA instructions are encoded as single words (32 bits) and are consistent among all
instruction types. The fixed instruction length and consistent format simplify instruction pipelining and
permit efficient decoding to occur in parallel with operand accesses.
The PowerPC ISA instructions are divided into the following categories:
• Integer instructions, which include computational and logical instructions
— Integer arithmetic instructions
— Integer compare instructions
— Integer logical instructions
— Integer rotate and shift instructions
• Floating-point instructions, which include floating-point computational instructions, as well as
instructions that affect the floating-point status and control register (FPSCR)
— Floating-point arithmetic instructions
— Floating-point multiply/add instructions
— Floating-point rounding and conversion instructions
— Floating-point compare instructions
— Floating-point status and control instructions
• Load/store instructions., which include integer and floating-point load and store instructions
— Integer load and store instructions
— Integer load and store multiple instructions
— Floating-point load and store
— Primitives used to construct atomic memory operations (lwarx and stwcx. instructions)
• Flow control instructions, which include branching instructions, condition register logical
instructions, trap instructions, and other instructions that affect the instruction flow
— Branch and trap instructions
— Condition register logical instructions
• Processor control instructions, which are used for synchronizing memory accesses.
— Move to/from SPR instructions
— Move to/from MSR
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-27
Central Processing Unit
— Synchronize
— Instruction synchronize
NOTE
This grouping of the instructions does not indicate which execution unit
executes a particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. The
PowerPC ISA architecture uses instructions that are four bytes long and word-aligned. It provides for byte,
half-word, and word operand loads and stores between memory and a set of 32 GPRs.
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register,
modified, and then written back to the target location with distinct instructions.
PowerPC ISA-compliant processors follow the program flow when they are in the normal execution state.
However, the flow of instructions can be interrupted directly by the execution of an instruction or by an
asynchronous event. Either kind of exception may cause one of several components of the system software
to be invoked.
3.10.1
Instruction Set Summary
Table 3-17 provides a summary of RCPU instructions. Refer to the RCPU Reference Manual for a detailed
description of the instruction set.
Table 3-17. Instruction Set Summary
Mnemonic
Operand Syntax
Name
add (add. addo addo.)
rD,rA,rB
Add
addc (addc. addco addco.)
rD,rA,rB
Add Carrying
adde (adde. addeo addeo.)
rD,rA,rB
Add Extended
addi
rD,rA,SIMM
Add Immediate
addic
rD,rA,SIMM
Add Immediate Carrying
addic.
rD,rA,SIMM
Add Immediate Carrying and Record
addis
rD,rA,SIMM
Add Immediate Shifted
addme (addme. addmeo addmeo.)
rD,rA
Add to Minus One Extended
addze (addze. addzeo addzeo.)
rD,rA
Add to Zero Extended
and (and.)
rA,rS,rB
AND
andc (andc.)
rA,rS,rB
AND with Complement
andi.
rA,rS,UIMM
AND Immediate
andis.
rA,rS,UIMM
AND Immediate Shifted
b (ba bl bla)
target_addr
Branch
MPC561/MPC563 Reference Manual, Rev. 1.2
3-28
Freescale Semiconductor
Central Processing Unit
Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
bc (bca bcl bcla)
BO,BI,target_addr
Branch Conditional
bcctr (bcctrl)
BO,BI
Branch Conditional to Count Register
bclr (bclrl)
BO,BI
Branch Conditional to Link Register
cmp
crfD,L,rA,rB
Compare
cmpi
crfD,L,rA,SIMM
Compare Immediate
cmpl
crfD,L,rA,rB
Compare Logical
cmpli
crfD,L,rA,UIMM
Compare Logical Immediate
cntlzw (cntlzw.)
rA,rS
Count Leading Zeros Word
crand
crbD,crbA,crbB
Condition Register AND
crandc
crbD,crbA, crbB
Condition Register AND with Complement
creqv
crbD,crbA, crbB
Condition Register Equivalent
crnand
crbD,crbA,crbB
Condition Register NAND
crnor
crbD,crbA,crbB
Condition Register NOR
cror
crbD,crbA,crbB
Condition Register OR
crorc
crbD,crbA, crbB
Condition Register OR with Complement
crxor
crbD,crbA,crbB
Condition Register XOR
divw (divw. divwo divwo.)
rD,rA,rB
Divide Word
divwu divwu. divwuo divwuo.
rD,rA,rB
Divide Word Unsigned
eieio
—
Enforce In-Order Execution of I/O
eqv (eqv.)
rA,rS,rB
Equivalent
extsb (extsb.)
rA,rS
Extend Sign Byte
extsh (extsh.)
rA,rS
Extend Sign Half Word
fabs (fabs.)
frD,frB
Floating Absolute Value
fadd (fadd.)
frD,frA,frB
Floating Add (Double-Precision)
fadds (fadds.)
frD,frA,frB
Floating Add Single
fcmpo
crfD,frA,frB
Floating Compare Ordered
fcmpu
crfD,frA,frB
Floating Compare Unordered
fctiw (fctiw.)
frD,frB
Floating Convert to Integer Word
fctiwz (fctiwz.)
frD,frB
Floating Convert to Integer Word with Round
Toward Zero
fdiv (fdiv.)
frD,frA,frB
Floating Divide (Double-Precision)
fdivs (fdivs.)
frD,frA,frB
Floating Divide Single
fmadd (fmadd.)
frD,frA,frC,frB
Floating Multiply-Add (Double-Precision)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-29
Central Processing Unit
Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
fmadds (fmadds.)
frD,frA,frC,frB
Floating Multiply-Add Single
fmr (fmr.)
frD,frB
Floating Move Register
fmsub (fmsub.)
frD,frA,frC,frB
Floating Multiply-Subtract (Double-Precision)
fmsubs (fmsubs.)
frD,frA,frC,frB
Floating Multiply-Subtract Single
fmul (fmul.)
frD,frA,frC
Floating Multiply (Double-Precision)
fmuls (fmuls.)
frD,frA,frC
Floating Multiply Single
fnabs (fnabs.)
frD,frB
Floating Negative Absolute Value
fneg (fneg.)
frD,frB
Floating Negate
fnmadd (fnmadd.)
frD,frA,frC,frB
Floating Negative Multiply-Add (DoublePrecision)
fnmadds (fnmadds.)
frD,frA,frC,frB
Floating Negative Multiply-Add Single
fnmsub (fnmsub.)
frD,frA,frC,frB
Floating Negative Multiply-Subtract
(Double-Precision)
fnmsubs (fnmsubs.)
frD,frA,frC,frB
Floating Negative Multiply-Subtract Single
frsp (frsp.)
frD,frB
Floating Round to Single
fsub (fsub.)
frD,frA,frB
Floating Subtract (Double-Precision)
fsubs (fsubs.)
frD,frA,frB
Floating Subtract Single
isync
—
Instruction Synchronize
lbz
rD,d(rA)
Load Byte and Zero
lbzu
rD,d(rA)
Load Byte and Zero with Update
lbzux
rD,rA,rB
Load Byte and Zero with Update Indexed
lbzx
rD,rA,rB
Load Byte and Zero Indexed
lfd
frD,d(rA)
Load Floating-Point Double
lfdu
frD,d(rA)
Load Floating-Point Double with Update
lfdux
frD,rA,rB
Load Floating-Point Double with Update
Indexed
lfdx
frD,rA,rB
Load Floating-Point Double Indexed
lfs
frD,d(rA)
Load Floating-Point Single
lfsu
frD,d(rA)
Load Floating-Point Single with Update
lfsux
frD,rA,rB
Load Floating-Point Single with Update Indexed
lfsx
frD,rA,rB
Load Floating-Point Single Indexed
lha
rD,d(rA)
Load Half-Word Algebraic
lhau
rD,d(rA)
Load Half-Word Algebraic with Update
lhaux
rD,rA,rB
Load Half-Word Algebraic with Update Indexed
MPC561/MPC563 Reference Manual, Rev. 1.2
3-30
Freescale Semiconductor
Central Processing Unit
Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
lhax
rD,rA,rB
Load Half-Word Algebraic Indexed
lhbrx
rD,rA,rB
Load Half-Word Byte-Reverse Indexed
lhz
rD,d(rA)
Load Half-Word and Zero
lhzu
rD,d(rA)
Load Half-Word and Zero with Update
lhzux
rD,rA,rB
Load Hal-Word and Zero with Update Indexed
lhzx
rD,rA,rB
Load Half-Word and Zero Indexed
lmw
rD,d(rA)
Load Multiple Word
lswi
rD,rA,NB
Load String Word Immediate
lswx
rD,rA,rB
Load String Word Indexed
lwarx
rD,rA,rB
Load Word and Reserve Indexed
lwbrx
rD,rA,rB
Load Word Byte-Reverse Indexed
lwz
rD,d(rA)
Load Word and Zero
lwzu
rD,d(rA)
Load Word and Zero with Update
lwzux
rD,rA,rB
Load Word and Zero with Update Indexed
lwzx
rD,rA,rB
Load Word and Zero Indexed
mcrf
crfD,crfS
Move Condition Register Field
mcrfs
crfD,crfS
Move to Condition Register from FPSCR
mcrxr
crfD
Move to Condition Register from XER
mfcr
rD
Move from Condition Register
mffs (mffs.)
frD
Move from FPSCR
mfmsr
rD
Move from Machine State Register
mfspr
rD,SPR
Move from Special Purpose Register
mftb
rD, TBR
Move from Time Base
mtcrf
CRM,rS
Move to Condition Register Fields
mtfsb0 (mtfsb0.)
crbD
Move to FPSCR Bit 0
mtfsb1 (mtfsb1.)
crbD
Move to FPSCR Bit 1
mtfsf (mtfsf.)
FM,frB
Move to FPSCR Fields
mtfsfi (mtfsfi.)
crfD,IMM
Move to FPSCR Field Immediate
mtmsr
rS
Move to Machine State Register
mtspr
SPR,rS
Move to Special Purpose Register
mulhw (mulhw.)
rD,rA,rB
Multiply High Word
mulhwu (mulhwu.)
rD,rA,rB
Multiply High Word Unsigned
mulli
rD,rA,SIMM
Multiply Low Immediate
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-31
Central Processing Unit
Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
mullw (mullw. mullwo mullwo.)
rD,rA,rB
Multiply Low
nand (nand.)
rA,rS,rB
NAND
neg (neg. nego nego.)
rD,rA
Negate
nor (nor.)
rA,rS,rB
NOR
or (or.)
rA,rS,rB
OR
orc
rA,rS,rB
OR with Complement
ori
rA,rS,UIMM
OR Immediate
oris
rA,rS,UIMM
OR Immediate Shifted
(orc.)
rfi
—
Return from Interrupt
rlwimi (rlwimi.)
rA,rS,SH,MB,ME
Rotate Left Word Immediate then Mask Insert
rlwinm (rlwinm.)
rA,rS,SH,MB,ME
Rotate Left Word Immediate then AND with
Mask
rlwnm (rlwnm.)
rA,rS,rB,MB,ME
Rotate Left Word then AND with Mask
sc
—
System Call
slw (slw.)
rA,rS,rB
Shift Left Word
sraw (sraw.)
rA,rS,rB
Shift Right Algebraic Word
srawi (srawi.)
rA,rS,SH
Shift Right Algebraic Word Immediate
srw (srw.)
rA,rS,rB
Shift Right Word
stb
rS,d(rA)
Store Byte
stbu
rS,d(rA)
Store Byte with Update
stbux
rS,rA,rB
Store Byte with Update Indexed
stbx
rS,rA,rB
Store Byte Indexed
stfd
frS,d(rA)
Store Floating-Point Double
stfdu
frS,d(rA)
Store Floating-Point Double with Update
stfdux
frS,rB
Store Floating-Point Double with Update
Indexed
stfdx
frS,rB
Store Floating-Point Double Indexed
stfiwx
frS,rB
Store Floating-Point as Integer Word Indexed
stfs
frS,d(rA)
Store Floating-Point Single
stfsu
frS,d(rA)
Store Floating-Point Single with Update
stfsux
frS,rB
Store Floating-Point Single with Update Indexed
stfsx
frS,r B
Store Floating-Point Single Indexed
sth
rS,d(rA)
Store Half-Word
MPC561/MPC563 Reference Manual, Rev. 1.2
3-32
Freescale Semiconductor
Central Processing Unit
Table 3-17. Instruction Set Summary (continued)
Mnemonic
Operand Syntax
Name
sthbrx
rS,rA,rB
Store Half-Word Byte-Reverse Indexed
sthu
rS,d(rA)
Store Half-Word with Update
sthux
rS,rA,rB
Store Half-Word with Update Indexed
sthx
rS,rA,rB
Store Half-Word Indexed
stmw
rS,d(rA)
Store Multiple Word
stswi
rS,rA,NB
Store String Word Immediate
stswx
rS,rA,rB
Store String Word Indexed
stw
rS,d(rA)
Store Word
stwbrx
rS,rA,rB
Store Word Byte-Reverse Indexed
stwcx.
rS,rA,rB
Store Word Conditional Indexed
stwu
rS,d(rA)
Store Word with Update
stwux
rS,rA,rB
Store Word with Update Indexed
stwx
rS,rA,rB
Store Word Indexed
subf (subf. subfo subfo.)
rD,rA,rB
Subtract From
subfc (subfc. subfco subfco.)
rD,rA,rB
Subtract from Carrying
subfe (subfe. subfeo subfeo.)
rD,rA,rB
Subtract from Extended
subfic
rD,rA,SIMM
Subtract from Immediate Carrying
subfme (subfme. subfmeo subfmeo.)
rD,rA
Subtract from Minus One Extended
subfze (subfze. subfzeo subfzeo.)
rD,rA
Subtract from Zero Extended
sync
—
Synchronize
tw
TO,rA,rB
Trap Word
twi
TO,rA,SIMM
Trap Word Immediate
xor (xor.)
rA,rS,rB
XOR
xori
rA,rS,UIMM
XOR Immediate
xoris
rA,rS,UIMM
XOR Immediate Shifted
Note: The dot (.) suffix on a mnemonic indicates that the CR register update is enabled. The o suffix on a mnemonic indicates
that the overflow bit update in the XER is enabled.
3.10.2
Recommended Simplified Mnemonics
To simplify assembly language coding, a set of alternative mnemonics is provided for some frequently
used operations (such as no-op, load immediate, load address, move register, and complement register).
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-33
Central Processing Unit
For a complete list of simplified mnemonics, see the RCPU Reference Manual. Programs written to be
portable across the various assemblers for the PowerPC ISA architecture should not assume the existence
of mnemonics not described in that manual.
3.10.3
Calculating Effective Addresses
The effective address (EA) is the 32-bit address computed by the processor when executing a memory
access or branch instruction or when fetching the next sequential instruction.
The PowerPC ISA architecture supports two simple memory addressing modes:
• EA = (rA|0) + 16-bit offset (including offset = 0) (register indirect with immediate index)
• EA = (rA|0) + rB (register indirect with index)
These simple addressing modes allow efficient address generation for memory accesses. Calculation of the
effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address, the storage operand is considered to wrap around from the maximum effective
address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit unsigned binary
arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
3.11
Exception Model
The PowerPC ISA exception mechanism allows the processor to change to supervisor state as a result of
external signals, errors, or unusual conditions that arise in the execution of instructions. When exceptions
occur, information about the state of the processor is saved to certain registers, and the processor begins
execution at an address (exception vector) predetermined for each exception. Processing of exceptions
occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific condition
may be determined by examining a register associated with the exception — for example, the DAE/source
instruction service register (DSISR). Additionally, some exception conditions can be explicitly enabled or
disabled by software.
The PowerPC ISA architecture requires that exceptions be taken in program order; therefore, although a
particular implementation may recognize exception conditions out of order, they are handled strictly in
order with respect to the instruction stream. When an instruction-caused exception is recognized, any
unexecuted instructions that appear earlier in the instruction stream, including any that have not yet entered
the execute state, are required to complete before the exception is taken. For example, if a single
instruction encounters multiple exception conditions, those exceptions are taken and handled sequentially.
Likewise, exceptions that are asynchronous and precise are recognized when they occur, but are not
handled until all instructions currently in the execute stage successfully complete execution and report
their results.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-34
Freescale Semiconductor
Central Processing Unit
Note that exceptions can occur while an exception handler routine is executing, and multiple exceptions
can become nested. It is up to the exception handler to save the appropriate machine state if it is desired
that control be returned to the excepting program.
In many cases, after the exception handler handles an exception, there is an attempt to execute the
instruction that caused the exception. Instruction execution continues until the next exception condition is
encountered. This method of recognizing and handling exception conditions sequentially guarantees that
the machine state is recoverable and processing can resume without losing instruction results.
To prevent the loss of state information, exception handlers must save the information stored in SRR0 and
SRR1 soon after the exception is taken to prevent this information from being lost due to another exception
being taken.
3.11.1
Exception Classes
The RCPU exception classes are shown in Table 3-18.
Table 3-18. RCPU Exception Classes
3.11.2
Class
Exception Type
Asynchronous, unordered
Machine check
System reset
Asynchronous, ordered
External interrupt
Decrementer
Synchronous (ordered, precise)
Instruction-caused exceptions
Ordered Exceptions
In the RCPU, all exceptions except for reset, debug port non-maskable interrupts, and machine check
exceptions are ordered. Ordered exceptions satisfy the following criteria:
• Only one exception is reported at a time. If, for example, a single instruction encounters multiple
exception conditions, those conditions are encountered sequentially. After the exception handler
handles an exception, instruction execution continues until the next exception condition is
encountered.
• When the exception is taken, no program state is lost.
3.11.3
Unordered Exceptions
Unordered exceptions may be reported at any time and are not guaranteed to preserve program state
information. The processor can never recover from a reset exception. It can recover from other unordered
exceptions in most cases. However, if a debug port non-maskable interrupt or machine check exception
occurs during the servicing of a previous exception, the machine state information in SRR0 and SRR1
(and, in some cases, the DAR and DSISR) may not be recoverable; the processor may be in the process of
saving or restoring these registers.
To determine whether the machine state is recoverable, the RI (recoverable exception) bit in SRR1 can be
read. During exception processing, the RI bit in the MSR is copied to SRR1 and then cleared. The
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-35
Central Processing Unit
operating system should set the RI bit in the MSR at the end of each exception handler’s prologue (after
saving the program state) and clear the bit at the start of each exception handler’s epilogue (before
restoring the program state). Then, if an unordered exception occurs during the servicing of an exception
handler, the RI bit in SRR1 will contain the correct value.
3.11.4
Precise Exceptions
In the RCPU, all synchronous (instruction-caused) exceptions are precise. When a precise exception
occurs, the processor backs the machine up to the instruction causing the exception. This ensures that the
machine is in its correct architecturally-defined state. The following conditions exist at the point a precise
exception occurs:
1. Architecturally, no instruction following the faulting instruction in the code stream has begun
execution.
2. All instructions preceding the faulting instruction appear to have completed with respect to the
executing processor.
3. SRR0 addresses either the instruction causing the exception or the immediately following
instruction. Which instruction is addressed can be determined from the exception type and the
status bits.
4. Depending on the type of exception, the instruction causing the exception may not have begun
execution, may have partially completed, or may have completed execution.
3.11.5
Exception Vector Table
The setting of the exception prefix (IP) bit in the MSR determines how exceptions are vectored. If the bit
is cleared, the exception vector table begins at the physical address 0x0000 0000; if IP is set, the exception
vector table begins at the physical address 0xFFF0 0000. Table 3-19 shows the exception vector offset of
the first instruction of the exception handler routine for each exception type.
NOTE
In the MPC561/MPC563, the exception table can additionally be relocated
by the BBC module to internal memory and reduce the total size required by
the exception table (see Section 4.3, “Exception Table Relocation (ETR).”
Table 3-19. Exception Vector Offset Table
Vector Offset
(hex)
Exception Type
Section
00000
Reserved
—
00100
System reset, NMI interrupt
Section 3.15.4.1, “System Reset Exception and NMI (0x0100)”
00200
Machine Check
Section 3.15.4.2, “Machine Check Exception (0x0200)”
00300
Data Storage
Section 3.15.4.3, “Data Storage Exception (0x0300)”
00400
Reserved
Instruction Storage1
00500
External Interrupt
Section 3.15.4.5, “External Interrupt (0x0500)”
MPC561/MPC563 Reference Manual, Rev. 1.2
3-36
Freescale Semiconductor
Central Processing Unit
Table 3-19. Exception Vector Offset Table (continued)
1
Vector Offset
(hex)
Exception Type
Section
00600
Alignment
Section 3.15.4.6, “Alignment Exception (0x00600)”
00700
Program
Section 3.15.4.7, “Program Exception (0x0700)”
00800
Floating-Point Unavailable
Section 3.15.4.8, “Floating-Point Unavailable Exception
(0x0800)”
00900
Decrementer
Section 3.15.4.9, “Decrementer Exception (0x0900)”
00A00
Reserved
—
00B00
Reserved
—
00C00
System call
Section 3.15.4.10, “System Call Exception (0x0C00)”
00D00
Trace.
Section 3.15.4.11, “Trace Exception (0x0D00)”
00E00
Floating-Point Assist
Section 3.15.4.12, “Floating-Point Assist Exception (0x0E00)”
01000
Implementation-Dependent
Software Emulation
Section 3.15.4.13, “Implementation-Dependent Software
Emulation Exception (0x1000)”
01100
Reserved
—
01200
Reserved
—
01300
Implementation-Dependent
Instruction
Protection Exception
Section 3.15.4.14, “Implementation-Dependent Instruction
Protection Exception (0x1300)”
01400
Implementation-Dependent Data
Protection Error
Section 3.15.4.15, “Implementation-Specific Data Protection
Error Exception (0x1400)”
01500–01BFF
Reserved
—
01C00
Implementation-Dependent
Data Breakpoint
Section 3.15.4.16, “Implementation-Dependent Debug
Exceptions”
01D00
Implementation-Dependent
Instruction Breakpoint
Section 3.15.4.16, “Implementation-Dependent Debug
Exceptions”
01E00
Implementation-Dependent
Maskable
External Breakpoint
Section 3.15.4.16, “Implementation-Dependent Debug
Exceptions”
01F00
Implementation-Dependent
Non-Maskable External Breakpoint
Section 3.15.4.16, “Implementation-Dependent Debug
Exceptions”
This exception will not be generated by hardware.
3.12
Instruction Timing
The RCPU processor is pipelined. Because the processing of an instruction is broken into a series of stages,
an instruction does not require the processor’s full resources.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-37
Central Processing Unit
The instruction pipeline in the MPC561/MPC563 has four stages:
1. The dispatch stage is implemented using a distributed mechanism. The central dispatch unit
broadcasts the instruction to all units. In addition, scoreboard information (regarding data
dependencies) is broadcast to each execution unit. Each execution unit decodes the instruction. If
the instruction is not implemented, a program exception is taken. If the instruction is legal and no
data dependency is found, the instruction is accepted by the appropriate execution unit, and the data
found in the destination register is copied to the history buffer. If a data dependency exists, the
machine is stalled until the dependency is resolved.
2. In the execute stage, each execution unit that has an executable instruction executes the instruction.
(For some instructions, this occurs over multiple cycles.)
3. In the writeback stage, the execution unit writes the result to the destination register and reports to
the history buffer that the instruction is completed.
4. In the retirement stage, the history buffer retires instructions in architectural order. An instruction
retires from the machine if it completes execution with no exceptions and if all instructions
preceding it in the instruction stream have finished execution with no exceptions. As many as six
instructions can be retired in one clock.
The history buffer maintains the correct architectural machine state. An exception is taken only when the
instruction is ready to be retired from the machine (i.e., after all previously-issued instructions have
already been retired from the machine). When an exception is taken, all instructions following the
excepting instruction are canceled, (i.e., the values of the affected destination registers are restored using
the values saved in the history buffer during the dispatch stage).
Figure 3-19 shows basic instruction pipeline timing.
FETCH
i1
i2
DECODE
i3
i1
i2
READ AND EXECUTE
i1
i2
i1
WRITE BACK (TO DEST REG)
L ADDRESS DRIVE
i2
i1
store
L DATA
LOAD WRITE BACK
BRANCH DECODE
BRANCH EXECUTE
load
i1
i1
i1
Figure 3-19. Basic Instruction Pipeline
Table 3-20 indicates the latency and blockage for each type of instruction. Latency refers to the interval
from the time an instruction begins execution until it produces a result that is available for use by a
MPC561/MPC563 Reference Manual, Rev. 1.2
3-38
Freescale Semiconductor
Central Processing Unit
subsequent instruction. Blockage refers to the interval from the time an instruction begins execution until
its execution unit is available for a subsequent instruction.
NOTE
When the blockage equals the latency, it is not possible to issue another
instruction to the same unit in the same cycle in which the first instruction
is being written back.
Table 3-20. Instruction Latency and Blockage
1
3.13
3.13.1
Instruction Type
Precision
Latency
Blockage
Floating-point
multiply-add
Double
Single
7
6
7
6
Floating-point
add or subtract
Double
Single
4
4
4
4
Floating-point multiply
Double
Single
5
4
5
4
Floating-point divide
Double
Single
17
10
17
10
Integer multiply
—
2
1 or 21
Integer divide
—
2 to 111
2 to 111
Integer load/store
—
See note1
See note1
Refer to Section 7, “Instruction Timing,” in the RCPU Reference Manual
(RCPURM/AD) for details.
User Instruction Set Architecture (UISA)
Computation Modes
The RCPU is a 32-bit implementation of the PowerPC ISA architecture. Any reference in the PowerPC
ISA architecture books (UISA, VEA, OEA) regarding 64-bit implementations are not supported by the
core. All registers except the floating-point registers are 32 bits wide.
3.13.2
Reserved Fields
Reserved fields in instructions are described under the specific instruction definition sections. Unless
otherwise noted, reserved fields should be written with a zero when written and return a zero when read.
Thus, this type of invalid form instructions yield results of the defined instructions with the appropriate
field zero.
In most cases, the reserved fields in registers are ignored on write and return zeros for them on read on any
control register implemented by the MPC561/MPC563. Exception to this rule are bits [16:23] of the
fixed-point exception cause register (XER) and the reserved bits of the machine state register (MSR),
which are set by the source value on write and return the value last set for it on read.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-39
Central Processing Unit
3.13.3
Classes of Instructions
Non-optional instructions are implemented by the hardware. Optional instructions are executed by
implementation-dependent code and any attempt to execute one of these commands causes the RCPU to
take the implementation-dependent software emulation interrupt (offset 0x01000 of the vector table).
Illegal and reserved instruction class instructions are supported by implementation- dependent code and,
thus, the RCPU hardware generates the implementation-dependent software emulation interrupt. Invalid
and preferred instruction forms treatment by the RCPU is described under the specific processor
compliance sections.
3.13.4
Exceptions
Invocation of the system software for any instruction-caused exception in the RCPU is precise, regardless
of the type and setting.
3.13.5
Branch Processor
The RCPU implements all the instructions defined for the branch processor in the UISA in the hardware.
3.13.6
Instruction Fetching
The core fetches a number of instructions into its internal buffer (the instruction pre-fetch queue) prior to
execution. If a program modifies the instructions it intends to execute, it should call a system library
program to ensure that the modifications have been made visible to the instruction fetching mechanism
prior to execution of the modified instructions.
3.13.7
Branch Instructions
The core implements all the instructions defined for the branch processor by the UISA in the hardware.
For performance of various instructions, refer to Table 3-20 of this manual.
3.13.7.1
Invalid Branch Instruction Forms
Bits marked with z in the BO encoding definition are discarded by the MPC561/MPC563 decoding. Thus,
these types of invalid form instructions yield results of the defined instructions with the z-bit zero. If the
decrement and test CTR option is specified for the bcctr or bcctrl instructions, the target address of the
branch is the new value of the CTR. Condition is evaluated correctly, including the value of the counter
after decrement.
3.13.7.2
Branch Prediction
The core uses the y bit to predict path for pre-fetch. Prediction is only done for not-ready branch
conditions. No prediction is done for branches to the link or count register if the target address is not ready.
Refer to the RCPU Reference Manual (conditional branch control) for more information.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-40
Freescale Semiconductor
Central Processing Unit
3.13.8
3.13.8.1
Fixed-Point Processor
Fixed-Point Instructions
The core implements the following instructions:
• Fixed-point arithmetic instructions
• Fixed-point compare instructions
• Fixed-point trap instructions
• Fixed-point logical instructions
• Fixed-point rotate and shift instructions
• Move to/from system register instructions
All instructions are defined for the fixed-point processor in the UISA in the hardware. For performance of
the various instructions, refer to Table 3-20.
— Move To/From System Register Instructions. Move to/from invalid special registers in which
SPR0 = 1 yields invocation of the privilege instruction error interrupt handler if the processor
is in problem state. For a list of all implemented special registers, refer to Table 3-2, and
Table 3-3.
— Fixed-Point Arithmetic Instructions. If an attempt is made to perform any of the divisions in
the divw[o][.] instruction (0x80000000 ÷ -1, <anything> ÷ 0), then the contents of rD are
0x80000000; if Rc =1, the contents of bits in CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is
set to the correct value. If an attempt is made to perform any of the divisions in the divw[o][.]
instruction, <anything> ÷ 0. In cmpi, cmp, cmpli, and cmpl instructions, the L-bit is applicable
for 64-bit implementations. In 32-bit implementations, if L = 1 the instruction form is invalid.
The core ignores this bit and therefore, the behavior when L = 1 is identical to the valid form
instruction with L = 0
3.13.9
3.13.9.1
Floating-Point Processor
General
The RCPU implements all floating-point features as defined in the UISA, including the non-IEEE working
mode. Some features require software assistance. For more information refer to the RCPU Reference
Manual (Floating-point Load Instructions).
3.13.9.2
Optional Instructions
The only optional instruction implemented by RCPU hardware is store floating-point as integer word
indexed (stfiwx). An attempt to execute any other optional instruction causes an implementation
dependent software emulation exception.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-41
Central Processing Unit
3.13.10 Load/Store Processor
The load/store processor supports all of the 32-bit implementation fixed-point PowerPC ISA load/store
instructions in the hardware.
3.13.10.1 Fixed-Point Load with Update and Store with Update Instructions
For load with update and store with update instructions, when rA = 0, the EA is written into R0. For load
with update instructions, when rA = rD, rA is boundedly undefined.
3.13.10.2 Fixed-Point Load and Store Multiple Instructions
For these types of instructions, EA must be a multiple of four. If it is not, the system alignment error
handler is invoked. For a lmw instruction (if rA is in the range of registers to be loaded), the instruction
completes normally. rA is then loaded from the memory location as follows:
rA ← MEM(EA+(rA-rD)*4, 4)
3.13.10.3 Fixed-Point Load String Instructions
Load string instructions behave the same as load multiple instructions, with respect to invalid format in
which rA is in the range of registers to be loaded. When rA is in range, it is updated from memory.
3.13.10.4 Storage Synchronization Instructions
For these type of instructions, EA must be a multiple of four. If it is not, the system alignment error handler
is invoked.
3.13.10.5 Floating-Point Load and Store With Update Instructions
For Load and Store with update instructions, if rD = 0 then the EA is written into R0.
3.13.10.6 Floating-Point Load Single Instructions
When the operand falls in the range of a single denormalized number, the floating-point assist interrupt
handler is invoked.
Refer to the RCPU Reference Manual (Floating-point Assist For Denormalized Operands) for complete
description of handling denormalized floating-point numbers.
3.13.10.7 Floating-Point Store Single Instructions
When the operand falls in the range of a single denormalized number, the floating-point assist interrupt
handler is invoked.
When the operand is ZERO it is converted to the correct signed ZERO in single-precision format.
When the operand is between the range of single denormalized and double denormalized it is considered
a programming error. The hardware will handle this case as if the operand was single denormalized.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-42
Freescale Semiconductor
Central Processing Unit
When the operand falls in the range of double denormalized numbers it is considered a programming error.
The hardware will handle this case as if the operand was ZERO.
The following check is done on the stored operand in order to determine whether it is a denormalized
single-precision operand and invoke the floating-point assist interrupt handler:
(frS[1:11] ≠ 0) AND (frS[1:11]
≤ 896)
Eqn. 3-1
Refer to the RCPU Reference Manual (Floating-Point Assist for Denormalized Operands) for complete
description of handling denormalized floating-point numbers.
3.13.10.8 Optional Instructions
No optional instructions are supported.
3.14
3.14.1
Virtual Environment Architecture (VEA)
Atomic Update Primitives
Both the lwarx and stwcx instructions are implemented according to the PowerPC ISA architecture
requirements. The MPC561/MPC563 does not provide support for snooping an external bus activity
outside the chip. The provision is made to cancel the reservation inside the MPC561/MPC563 by using the
CR and KR input signals. Internal buses are snooped for RCPU accesses, and the reservation mechanism
can be used for multitask single master applications.
3.14.2
Effect of Operand Placement on Performance
The load/store unit hardware supports all of the PowerPC ISA load/store instructions. An optimal
performance is obtained for naturally aligned operands. These accesses result in optimal performance (one
bus cycle) for up to four bytes in size and good performance (two bus cycles) for double precision
floating-point operands. Unaligned operands are supported in hardware and are broken into a series of
aligned transfers. The effect of operand placement on performance is as stated in the VEA, except for the
case of 8-byte operands. In that case, since the RCPU uses a 32-bit wide data bus, the performance is good
rather than optimal.
3.14.3
Storage Control Instructions
The RCPU does not implement the following cache control instructions: icbi, dcbt, dcbi, dcbf, dcbz, dcbst,
and dcbtst .
3.14.4
Instruction Synchronize (isync) Instruction
The isync instruction causes a reflect which waits for all prior instructions to complete and then executes
the next sequential instruction. Any instruction after an isync will see all effects of prior instructions.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-43
Central Processing Unit
3.14.5
Enforce In-Order Execution of I/O (eieio) Instruction
When executing an eieio instruction, the load/store unit will wait until all previous accesses have
terminated before issuing cycles associated with load/store instructions following the eieio instruction.
3.14.6
Time Base
A description of the time base register may be found in Chapter 6, “System Configuration and Protection,”
and in Chapter 8, “Clocks and Power Control.”
3.15
Operating Environment Architecture (OEA)
The MPC561/MPC563 has an internal memory space that includes memory-mapped control registers and
internal memory used by various modules on the chip. This memory is part of the main memory as seen
by the RCPU and can be accessed by an external system master.
3.15.1
3.15.1.1
Branch Processor Registers
Machine State Register (MSR)
The floating-point exception mode encoding in the RCPU is as shown in Table 3-21.
:
Table 3-21. Floating-Point Exception Mode Encoding
Mode
FE0
FE1
Ignore exceptions
0
0
Precise
0
1
Precise
1
0
Precise
1
1
The SF bit is reserved set to zero. The IP bit initial state after reset is set as programmed by the reset
configuration as specified by the USIU characteristics.
3.15.1.2
Branch Processors Instructions
The RCPU implements all the instructions defined for the branch processor in the UISA in the hardware.
3.15.2
3.15.2.1
•
•
Fixed-Point Processor
Special Purpose Registers
Unsupported Registers — The following registers are not supported by the MPC561/MPC563:
SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U, IBAT2L, IBAT3U, IBAT3L,
DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L, DBAT3U, DBAT3L.
Added Registers — For a list of added special purpose registers, refer to Table 3-2, and Table 3-3.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-44
Freescale Semiconductor
Central Processing Unit
3.15.3
Storage Control Instructions
Storage control instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not implemented
by the MPC561/MPC563.
3.15.4
Exceptions
The following paragraphs define the types of OEA exceptions. The exception table vector defines the
offset value by exception type. Refer to Table 3-19.
3.15.4.1
System Reset Exception and NMI (0x0100)
A system reset exception occurs when:
• Any reset signal is asserted: PORESET, HRESET, or SRESET
• An internal reset is requested, such as from the software watchdog timer
Settings caused by reset as shown in Table 3-22.
Table 3-22. Settings Caused by Reset
Register
Setting
MSR
IP depends on internal data bus configuration word; ME is unchanged.
DCMPEN is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP]). All other bits are cleared
SRR0
Undefined
SRR1
Undefined
FPECR
0x0000 0000
ICTRL
0x0000 0000
LCTRL1
0x0000 0000
LCTRL2
0x0000 0000
COUNTA[16:31]
0x0000 0000
COUNTB[16:31]
0x0000 0000
A non-maskable interrupt (NMI) occurs when the IRQ0 is asserted and the following registers are set.
Table 3-23. Register Settings following an NMI
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the next instruction the
processor executes if no interrupt conditions are present
Save/Restore Register 1 (SRR1)
1:4
Cleared to 0
10:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-45
Central Processing Unit
Table 3-23. Register Settings following an NMI (continued)
Register Name
Bits
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Other
1
Description
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the RCPU is in decompression on mode, SRR0 will contain a compressed address.
Execution begins at physical address 0x0100 if the hard reset configuration word IP bit is cleared to 0.
Execution begins at physical address 0xFFF0 0100 if the hard reset configuration word IP bit is set to 1.
3.15.4.2
Machine Check Exception (0x0200)
A machine-check exception is assumed to be caused by one of the following conditions:
• The accessed address does not exist.
• A data error was detected.
• A storage protection violation was detected by chip-select logic.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-46
Freescale Semiconductor
Central Processing Unit
When a machine-check exception occurs, the processor does one of the following:
• Takes a machine check exception;
• Enters the checkstop state; or
• Enters debug mode.
Which action is taken depends on the value of the MSR[ME] bit, whether or not debug mode was enabled
at reset, and (if debug mode is enabled) the values of the CHSTPE (checkstop enable) and MCIE (machine
check enable) bits in the debug enable register (DER). Table 3-24 summarizes the possibilities. When the
processor is in the checkstop state, instruction processing is suspended and cannot be restarted without
resetting the core.
Table 3-24. Machine Check Exception Processor Actions
MSR[ME]
Debug Mode
Enable
CHSTPE
MCIE
Action Performed when Exception Detected
0
0
X
X
Enter checkstop state
1
0
X
X
Branch to machine-check exception handler
0
1
0
X
Enter checkstop state
0
1
1
X
Enter debug mode
1
1
X
0
Branch to machine-check exception handler
1
1
X
1
Enter debug mode
An indication is sent to the USIU which may generate an automatic reset in this condition. Refer to
Chapter 7, “Reset,” for more details.
The register settings for machine check exceptions are shown in Table 3-25.
Table 3-25. Register Settings following a Machine Check Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
interrupt
Save/Restore Register 1 (SRR1)
02
MSR0
1
Set to 1 for instruction fetch-related errors and 0 for
load/store-related errors
2:4
5:9
2
10:15
16:31 2
Cleared to 0
MSR[5:9]
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-47
Central Processing Unit
Table 3-25. Register Settings following a Machine Check Exception (continued)
Register Name
Bits
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Data/Storage Interrupt Status
Register (DSISR)3
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Other
Cleared to 0
0:14
Cleared to 0
15:16
Set to bits [29:30] of the instruction if X-form and to 0b00 if
D-form
17
Data Address Register (DAR)3
Description
Set to bit 25 of the instruction if X-form and to Bit 5 if D-form
18:21
Set to bits [21:24] of the instruction if X-form and to bits [1:4] if
D-form
22:31
Set to bits [6:15] of the instruction
All
Set to the effective address of the data access that caused the
interrupt
1
If the exception occurs due to a data error caused by a Load/Store instruction and the processor in Decompression
On mode, the SRR0 register will contain the address of the Load/Store instruction in compressed format. If the
exception occurs due to an instruction fetch in Decompression On mode, the SRR0 register will contain an
indeterminate value.
2 This bit is loaded from the corresponding bit in the MSR when an interrupt is taken. The appropriate bit in MSR is
loaded from this bit when an RFI is executed.
3 DSISR and DAR registers are only updated when the machine check exception is caused by a data access violation.
when a machine check exception is taken, instruction execution resumes at offset 0x0200 from the base
address indicated by MSR[IP].
3.15.4.3
Data Storage Exception (0x0300)
A data storage exception is never generated by the RCPU. The software may branch to this location as a
result of implementation-specific data storage protection error exception.
3.15.4.4
Instruction Storage Exception (0x0400)
An instruction storage interrupt is never generated by them RCPU. The software may branch to this
location as a result of an implementation-specific instruction storage protection error exception.
3.15.4.5
External Interrupt (0x0500)
The external interrupt exception is taken on assertion of the internal IRQ line to the RCPU, that is driven
by on-chip interrupt controller. The interrupt may be caused by the assertion of an external IRQ signal, by
a USIU timer, or by an internal chip peripheral. Refer to Section 6.1.4, “Enhanced Interrupt Controller,”
for more information on the interrupt controller.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-48
Freescale Semiconductor
Central Processing Unit
The interrupt may be delayed by other higher priority exceptions or if the MSR[EE] bit is cleared when
the exception occurs. MSR[EE] is automatically cleared by hardware to disable external interrupts when
any exception is taken.
Upon detecting an external interrupt, the processor assigns it to the instruction at the head of the history
buffer (after retiring all instructions that are ready to retire).
The enhanced interrupt controller mode is available for interrupt-driven applications on
MPC561/MPC563. It allows the single external interrupt exception vector 0x500 to be split into up to 48
different vectors corresponding to 48 interrupt sources to speed up interrupt processing. It also supports a
low priority source masking feature in hardware to handle nested interrupts more easily. See Section 6.1.4,
“Enhanced Interrupt Controller,” and Chapter 4, “Burst Buffer Controller 2 Module.”
The register settings for the external interrupt exception are shown in Table 3-26.
Table 3-26. Register Settings following External Interrupt
Register
Bits
Setting Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that the processor would
have attempted to execute next if no interrupt conditions were present.
Save/Restore Register 1 (SRR1)
[0:15]
Cleared to 0
[16:31]
Loaded from bits [16:31] of MSR. In the current implementation, bit 30
of the SRR1 is never cleared, except by loading a zero value from
MSR[RI]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPE This bit is set according to (BBCMCR[EN_COMP] AND
N
BBCMCR[EXC_COMP])
Other
1
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain an
address in compressed format.
When an external interrupt is taken, instruction execution resumes at offset 0x00500 from the physical
base address indicated by MSR[IP].
3.15.4.6
Alignment Exception (0x00600)
The following conditions cause an alignment exception:
• The operand of a floating-point load or store instruction is not word-aligned.
• The operand of a load or store multiple instruction is not word-aligned.
• The operand of lwarx or stwcx. is not word-aligned.
Alignment exceptions use the SRR0 and SRR1 to save the machine state and the DSISR to determine the
source of the exception.
The register settings for alignment exceptions are shown in Table 3-27.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-49
Central Processing Unit
Table 3-27. Register Settings for Alignment Exception
Register
Bits
Save/Restore Register 0 (SRR0)1
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Set to the effective address of the instruction that caused the
exception.
[0:15]
Cleared to 0
[16:31]
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Data/Storage Interrupt Status
Register (DSISR)
1
Setting Description
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Other
Cleared to 0
[0:11]
Cleared to 0
[12:13]
Cleared to 0
14
Cleared to 0
[15:16]
For instructions that use register indirect with index addressing,
set to bits [29:30] of the instruction.
For instructions that use register indirect with immediate index
addressing, cleared.
17
For instructions that use register indirect with index addressing,
set to bit 25 of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bit 5 of the instruction.
[18:21]
For instructions that use register indirect with index addressing,
set to bits [21:24] of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bits [1:4] of the instruction.
[22:26]
Set to bits [6:10] (source or destination) of the instruction.
[27:31]
Set to bits [11:15] of the instruction (rA). Set to either bits
[11:15] of the instruction or to any register number not in the
range of registers loaded by a valid form instruction, for lmw,
lswi, and lswx instructions. Otherwise undefined.
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
MPC561/MPC563 Reference Manual, Rev. 1.2
3-50
Freescale Semiconductor
Central Processing Unit
NOTE
For load or store instructions that use register indirect with index
addressing, the DSISR can be set to the same value that would have resulted
if the corresponding instruction uses register indirect with immediate index
addressing had caused the exception. Similarly, for load or store instructions
that use register indirect with immediate index addressing, DSISR can hold
a value that would have resulted from an instruction that uses register
indirect with index addressing. (If there is no corresponding instruction, no
alternative value can be specified.)
When an alignment exception is taken, instruction execution resumes at offset 0x00600 from the physical
base address indicated by MSR[IP].
3.15.4.7
Program Exception (0x0700)
A program exception occurs when no higher priority exception exists and one or more of the following
exception conditions, which correspond to bit settings in SRR1, occur during execution of an instruction:
• System floating-point enabled exception — A system floating-point enabled exception is
generated when the following condition is met as a result of a move to FPSCR instruction, move
to MSR (mtmsr) instruction, or return from interrupt (rfi) instruction:
• (MSR[FE0] | MSR[FE1]) and- FPSCR[FEX] = 1.
• Notice that in the RCPU implementation of the PowerPC ISA architecture, a program interrupt is
not generated by a floating-point arithmetic instruction that results in the condition shown above;
a floating-point assist exception is generated instead.
• Privileged instruction — A privileged instruction type program exception is generated by any of
the following conditions:
— The execution of a privileged instruction (mfmsr, mtmsr, or rfi) is attempted and the processor
is operating at the user privilege level (MSR[PR] = 1).
— The execution of mtspr or mfspr where SPR0 = 1 in the instruction encoding (indicating a
supervisor-access register) and MSR[PR] = 1 (indicating the processor is operating at the user
privilege level), provided the SPR instruction field encoding represents either:
— a valid internal-to-the-processor special-purpose register; or
— an external-to-the-processor special-purpose register (either valid or invalid).
• Trap — A trap type program exception is generated when any of the conditions specified in a trap
instruction is met.
The register settings for program exceptions are shown in Table 3-28.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-51
Central Processing Unit
Table 3-28. Register Settings following Program Exception
Register
Bits
Save/Restore Register 0 (SRR0)1
All
Save/Restore Register 1 (SRR1)2
[0:10]
Machine State Register (MSR)
Setting Description
Contains the effective address of the excepting instruction
Cleared to 0
11
Set for a floating-point enabled program exception; otherwise
cleared.
12
Cleared to 0.
13
Set for a privileged instruction program exception; otherwise
cleared.
14
Set for a trap program exception; otherwise cleared.
15
Cleared to 0 if SRR0 contains the address of the instruction
causing the exception, and set if SRR0 contains the address of
a subsequent instruction.
[16:31]
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Other
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
2
Only one of bits 11, 13, and 14 can be set.
When a program exception is taken, instruction execution resumes at offset 0x0700 from the physical base
address indicated by MSR[IP].
3.15.4.8
Floating-Point Unavailable Exception (0x0800)
A floating-point unavailable exception occurs when no higher priority exception exists, an attempt is made
to execute a floating-point instruction (including floating-point load, store, and move instructions), and the
floating-point available bit in the MSR is disabled, (MSR[FP] = 0).
Table 3-29. Register Settings following a Floating-Point Unavailable Exception
Register
Bits
Setting Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
exception.
Save/Restore Register 1 (SRR1)
[0:15]
Cleared to 0
[16:31]
Loaded from MSR[16:31]
MPC561/MPC563 Reference Manual, Rev. 1.2
3-52
Freescale Semiconductor
Central Processing Unit
Table 3-29. Register Settings following a Floating-Point Unavailable Exception (continued)
Register
Bits
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Other
1
Setting Description
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
3.15.4.9
Decrementer Exception (0x0900)
A decrementer exception occurs when no higher priority exception exists, the decrementer register has
completed decrementing, and MSR[EE] = 1. The decrementer exception request is canceled when the
exception is handled. The decrementer register counts down, causing an exception (unless masked) when
passing through zero. The decrementer implementation meets the following requirements:
• Loading a GPR from the decrementer does not affect the decrementer.
• Storing a GPR value to the decrementer replaces the value in the decrementer with the value in the
GPR.
• Whenever bit 0 of the decrementer changes from zero to one, an exception request is signaled. If
multiple decrementer exception requests are received before the first can be reported, only one
exception is reported. The occurrence of a decrementer exception cancels the request.
• If the decrementer is altered by software and if bit 0 is changed from zero to one, an interrupt
request is signaled.
The register settings for the decrementer exception are shown in Table 3-30.
Table 3-30. Register Settings Following a Decrementer Exception
Register
Bits
Setting Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that the processor
would have attempted to execute next if no exception
conditions were present.
Save/Restore Register 1 (SRR1)
[0:15]
Cleared to 0
[16:31]
Loaded from MSR[16:31]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Other
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-53
Central Processing Unit
1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
When a decrementer exception is taken, instruction execution resumes at offset 0x0900 from the physical
base address indicated by MSR[IP].
3.15.4.10 System Call Exception (0x0C00)
A system call exception occurs when a system call instruction is executed. The effective address of the
instruction following the sc instruction is placed into SRR0. MSR[16:31] are placed into SRR1[16:31],
and SRR1[0:15] are set to undefined values. Then a system call exception is generated.
The system call instruction is context synchronizing. That is, when a system call exception occurs,
instruction dispatch is halted and the following synchronization is performed:
1. The exception mechanism waits for all instructions in execution to complete to a point where they
report all exceptions they will cause.
2. The processor ensures that all instructions in execution complete in the context in which they began
execution.
3. Instructions dispatched after the exception is processed are fetched and executed in the context
established by the exception mechanism.
Register settings are shown in Table 3-31.
Table 3-31. Register Settings following a System Call Exception
Register
Setting Description
1
Save/Restore Register 0 (SRR0)
All
Save/Restore Register 1 (SRR1)
[0:15]
Undefined
[16:31]
Loaded from MSR[16:31]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
Other
1
Set to the effective address of the instruction following the
System Call instruction
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the exception occurs during a data access in Decompression On mode, the SRR0 register will contain the address
of the Load/Store instruction in compressed format. If the exception occurs during an instruction fetch in
decompression on mode, the SRR0 register will contain an indeterminate value.
When a system call exception is taken, instruction execution resumes at offset 0x00C00 from the physical
base address indicated by MSR[IP].
3.15.4.11 Trace Exception (0x0D00)
A trace interrupt occurs if MSR[SE] = 1 and any instruction except rfi is successfully completed or
MSR[BE]= 1 and a branch is completed. Notice that the trace interrupt does not occur after an instruction
that caused an interrupt (for instance, sc). Monitor/debugger software must change the vectors of other
MPC561/MPC563 Reference Manual, Rev. 1.2
3-54
Freescale Semiconductor
Central Processing Unit
possible interrupt addresses to single-step such instructions. If this is unacceptable, other debug features
can be used. Refer to Chapter 23, “Development Support,” for more information. See Table 3-32 for Trace
Exception register settings.
Table 3-32. Register Settings following a Trace Exception
Register Name
Bits
Save/Restore Register 0 (SRR0)
All
Set to the effective address of the instruction following the
executed instruction
Save/Restore Register 1 (SRR1)
1:4
Cleared to 0
10:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Other
1
Description
1
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Execution resumes at offset 0x0D00 from the base address indicated by MSR[IP].
3.15.4.12 Floating-Point Assist Exception (0x0E00)
A floating point assist exception occurs when the following conditions are true:
• A floating-point enabled exception condition is detected;
• The corresponding floating-point enable bit in the FPSCR (floating point status and control
register) is set (exception enabled); and
• MSR[FE0] | MSR[FE1] = 1
These conditions are summarized in the following equation:
(MSR[FE0] | MSR[FE1]) AND FPSCR[FEX] = 1
Note that when ((MSR[FE0] | MSR[FE1]) AND FPSCR[FEX]) is set as a result of move to FPSCR, move
to MSR or rfi, a program exception is generated, rather than a floating-point assist exception.
A floating point assist exception also occurs when a tiny result is detected and the floating point underflow
exception is disabled (FPSCR[UE] = 0).
The register settings for floating-point assist exceptions are shown in Table 3-33.
Table 3-33. Register Settings following Floating-Point Assist Exceptions
Register Name
1
Save/Restore Register 0 (SRR0)
Bits
Description
All
Set to the effective address of the instruction that caused the
interrupt
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-55
Central Processing Unit
Table 3-33. Register Settings following Floating-Point Assist Exceptions
Register Name
Bits
Description
Save/Restore Register 1 (SRR1)
1:4
10:15
Other
Machine State Register (MSR)
IP
ME
LE
DCMPEN
Cleared to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
Other
1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
When a floating-point exception is taken, instruction execution resumes at offset 0x0E00 from the base
address indicated by MSR[IP].
3.15.4.13 Implementation-Dependent Software Emulation Exception (0x1000)
An implementation-dependent software emulation exception occurs in the following instances:
• When executing any non-implemented instruction. This includes all illegal and unimplemented
optional instructions and all floating-point instructions.
• When executing a mtspr or mfspr instruction that specifies an un-implemented
internal-to-the-processor SPR, regardless of the value of bit 0 of the SPR.
• When executing a mtspr or mfspr that specifies an un-implemented external-to-the-processor
register and SPR0 = 0 or MSR[PR] = 0 (no program interrupt condition).
Table 3-34 shows the register settings set when a software emulation exception occurs.
Table 3-34. Register Settings following a Software Emulation Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
interrupt
Save/Restore Register 1 (SRR1)
1:4
Cleared to 0
10:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
MPC561/MPC563 Reference Manual, Rev. 1.2
3-56
Freescale Semiconductor
Central Processing Unit
Table 3-34. Register Settings following a Software Emulation Exception
Register Name
Bits
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Other
1
Description
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Execution resumes at offset 0x01000 from the base address indicated by MSR[IP].
3.15.4.14 Implementation-Dependent Instruction Protection Exception (0x1300)
The implementation-specific instruction storage protection error interrupt occurs in the following cases:
• The fetch access violates storage protection and MSR[IR] = 1.
• The fetch access is to guarded storage and MSR[IR] = 1.
The register settings for instruction protection exceptions are shown in Table 3-35.
Table 3-35. Register Settings following an Instruction Protection Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
exception
Save/Restore Register 1 (SRR1)
0:2
Cleared to 0
Machine State Register (MSR)
3
Set to 1 if the fetch access was to a guarded storage when
MSR[IR] = 1, otherwise clear to 0
4
Set to 1 if the storage access is not permitted by the protection
mechanism (IMPU in BBC) and MSR[IR] = 1; otherwise clear
to 0
5:15
Cleared to 0
16:31
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[IR]
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Other
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-57
Central Processing Unit
1
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain an
indeterminate value.
Execution resumes at offset 0x1300 from the base address indicated by MSR[IP].
3.15.4.15 Implementation-Specific Data Protection Error Exception (0x1400)
The implementation-specific data protection error exception occurs in the following case:
• The data access violates the storage protection and MSR[DR]=1. See Chapter 11, “L-Bus to U-Bus
Interface (L2U).”
MPC561/MPC563 Reference Manual, Rev. 1.2
3-58
Freescale Semiconductor
Central Processing Unit
See Table 3-36 for data-protection-error exception register settings.
Table 3-36. Register Settings Following a Data Protection Error Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
Set to the effective address of the instruction that caused the
exception
Save/Restore Register 1 (SRR1)
0:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPEN
Data/Storage Interrupt Status
Register (DSISR)
Other
Cleared to 0
0:3
Cleared to 0
4
Set to 1 if the storage access is not permitted by the protection
mechanism. Otherwise cleared to 0
5
Cleared to 0
6
Set to 1 for a store operation and cleared to 0 for a load
operation
7:31
Data Address Register (DAR)
1
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
All
Cleared to 0
Set to the effective address of the data access that caused the
exception
If the exception occurs during a data access in Decompression On mode, the SRR0 register will contain the address
of the Load/Store instruction in compressed format.
When a data protection error exception is taken, instruction execution resumes at offset 0x1400 from the
base address indicated by MSR[IP].
3.15.4.16 Implementation-Dependent Debug Exceptions
Implementation-dependent debug exceptions occur in the following cases:
• When there is an internal breakpoint match (for more details, refer to Chapter 23, “Development
Support.”
• When a peripheral breakpoint request is asserted to the RCPU.
• When the development port request is asserted to the RCPU. Refer to Chapter 23, “Development
Support,” for details on how to generate the development port-interrupt request.
See Table 3-37 for debug-exception register settings.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-59
Central Processing Unit
Table 3-37. Register Settings Following a Debug Exception
Register Name
Bits
Description
Save/Restore Register 0 (SRR0)1
All
For I-breakpoints, set to the effective address of the instruction
that caused the interrupt. For L-breakpoint, set to the effective
address of the instruction following the instruction that caused
the interrupt. For development port maskable request or a
peripheral breakpoint, set to the effective address of the
instruction that the processor would have executed next if no
interrupt conditions were present. If the development port
request is asserted at reset, the value of SRR0 is undefined.
Save/Restore Register 1 (SRR1)
1:4
Cleared to 0
10:15
Cleared to 0
Other
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
If the development port request is asserted at reset, the value
of SRR1 is undefined.
Machine State Register (MSR)
IP
No change
ME
No change
LE
Bit is copied from ILE
DCMPE This bit is set according to (BBCMCR[EN_COMP] AND
N
BBCMCR[EXC_COMP])
Other
1
Cleared to 0
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain
the instruction address in compressed format.
For data breakpoint exceptions, the register shown in Table 3-38 is set.
Table 3-38. Register Settings for Data Breakpoint Match
Register Name
BAR
Bits
Description
Set to the effective address of the data access as computed by
the instruction that caused the interrupt
Execution resumes at offset from the base address indicated by MSR[IP] as follows:
• 0x01C00 – For data breakpoint match
• 0x01D00 – For instruction breakpoint match
• 0x01E00 – For development port maskable request or a peripheral breakpoint
• 0x01F00 – For development port non-maskable request
3.15.5
Partially Executed Instructions
In general, the architecture permits instructions to be partially executed when an alignment or data storage
interrupt occurs. In the core, instructions are not executed at all if an alignment interrupt condition is
MPC561/MPC563 Reference Manual, Rev. 1.2
3-60
Freescale Semiconductor
Central Processing Unit
detected and data storage interrupt is never generated by the hardware. In the RCPU, the instruction can
be partially executed only in the case of the load/store instructions that cause multiple accesses to the
memory subsystem. These instructions are:
• Multiple/string instructions
• Unaligned load/store instructions
In the last case, the store instruction can be partially completed if one of the accesses (except the first one)
causes the data storage protection error. The implementation-specific data storage protection interrupt is
taken in this case. For the update forms, the update register (rA) is not altered.
3.15.6
Timer Facilities
Descriptions of the timebase and decrementer registers can be found in Chapter 6, “System Configuration
and Protection,” and in Chapter 8, “Clocks and Power Control.”
3.15.7
Optional Facilities and Instructions
Any other OEA optional facilities and instructions (except those that are discussed here) are not
implemented by the RCPU hardware. Attempting to execute any of these instructions causes an
implementation dependent software emulation interrupt to be taken.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
3-61
Central Processing Unit
MPC561/MPC563 Reference Manual, Rev. 1.2
3-62
Freescale Semiconductor
Chapter 4
Burst Buffer Controller 2 Module
The burst buffer controller module (BBC) consists of four main functional parts: the bus interface unit
(BIU), the instruction memory protection unit (IMPU), branch target buffer (BTB) and the instruction code
decompressor unit (ICDU). See Figure 4-1. Information about decompression features of the BBC is found
in Appendix A, “MPC562/MPC564 Compression Features.”
The BBC master BIU interfaces between the RCPU instruction port and the internal U-bus and can support
burstable and non-burstable U-bus accesses.
The IMPU allows the instruction memory to be divided into four regions with different protection
attributes. The IMPU compares the attributes of the RCPU memory access request with the attributes of
the appropriate region. If the access is allowed, the proper signals are sent to the BIU. If access to the
memory region is disallowed because the region is protected, an interrupt is sent to the RCPU and the
master BIU cancels U-bus access.
The IMPU is able to relocate the RCPU exception vectors. The IMPU always maps the exception vectors
into the internal memory space of the MPC561/MPC563. This feature is important for a
multi-MPC561/MPC563 system, where, although the internal memories of some controllers are not
shifted to the lower 4 Mbytes, they can still have their own internal exception vector tables with the same
exception addresses issued by their RCPU cores.
The IMPU also supports an MPC561/MPC563-enhanced interrupt controller by extending an exception
vector’s relocation mechanism to translate the RCPU external interrupt exception vector separately and
splitting it into 48 different vectors, corresponding to the code generated by the interrupt controller. See
also Section 6.1.4.4, “Enhanced Interrupt Controller Operation.”
The branch target buffer (BTB) improves the performance of the MPC561/MPC563 by holding and
supplying previously accessed or decompressed instructions to the RCPU core. The BTB can be enabled
in either decompression on or off mode.
The ICDU provides decompressed instructions to RCPU in the decompression ON mode and contains a 2
Kbyte RAM (DECRAM) to hold decompression vocabularies. The DECRAM can serve as a general
purpose RAM memory on the U-bus if code compression is not used.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-1
Burst Buffer Controller 2 Module
BBC
IMPU
Registers
Address
Buffer
To
Addresses
U-bus
Slave
Machine
32
30
BTB
32
IMPU
Compression
Address
Decompressor
Control Logic
RCPU Core (Sequencer)
Compress/
Uncompress
Data
32
32
Data
Buffer
1 x 32
DECRAM
2 Kbytes
ICDU
U-bus Data
32
/
U-bus
Sequencer
Address
Address and Data
Buffers Control
Pipelined and
Burstable
Access Control
U-bus
Master
Machine
BIU
U-bus Controls
L/U Interface
SIU Interface
Figure 4-1. BBC Module Block Diagram
4.1
4.1.1
•
•
Key Features
BIU Key Features
Supports pipelined and burstable and single accesses to internal and external memories
Supports the decoupled interface with the RCPU instruction unit
MPC561/MPC563 Reference Manual, Rev. 1.2
4-2
Freescale Semiconductor
Burst Buffer Controller 2 Module
•
•
•
•
•
4.1.2
•
•
•
•
•
•
•
•
•
•
•
4.1.3
Implements a parked master on the U-bus, resulting in zero clock delays for RCPU fetch accesses
to the U-bus
Fully utilizes the U-bus pipeline for fetch accesses
Avoids undesirable delays through a tight interface with the L2U module (fully utilizing U-bus
bandwidth and back-to-back accesses)
Supports program trace and show cycles
Supports a special attribute for debug port fetch accesses.
IMPU Key Features
There are four regions in which the base address and size can be programmed.
Available region sizes include 2 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes,
256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes....4 Gbytes.
Overlap between regions is allowed.
Each of the four regions supports the following attributes:
— User/supervisor
— Guard attribute (causes an interrupt in case of speculative fetch attempt)
— Compressed/non-compressed (MPC562/MPC564 only)
— Regions are enabled or disabled in software.
Global region entry declares the default access attributes for all memory areas not covered by the
four regions:
The RCPU gets the instruction storage protection exception generated upon
— An access violation of protection attributes
— A fetch from a guarded region.
The RCPU MSR[IR] bit controls IMPU protection.
Programming is performed by using the RCPU mtspr/mfspr instructions to/from implementation
specific special-purpose registers.
The IMPU supplies relocation addresses of all the exceptions within the internal memory space.
The IMPU implements external interrupt vector splitting to reduce the external interrupt latency.
There is a special reset exception vector for decompression on mode (MPC562/MPC564 only).
ICDU Key Features
The following are instruction code decompression unit key features of the MPC562/MPC564. See
Appendix A, “MPC562/MPC564 Compression Features” for more information.
• Instruction code on-line decompression based on “instruction classes” algorithm.
• No need for address translation between compressed and non-compressed address spaces — ICDU
provides “next instruction address” to the RCPU
• In most cases, instruction decompression takes one clock
• Code decompression is pipelined:
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-3
Burst Buffer Controller 2 Module
•
•
— No performance penalty during sequential program flow execution
— Minimal performance penalty due to change of program flow execution
Two operation modes are available: decompression on and decompression off. Switch between
compressed and non-compressed user application software parts is possible.
Adaptive vocabularies scheme is supported; each user application can have its own optimum
vocabularies.
4.1.4
•
•
•
•
•
•
DECRAM Key Features
2 Kbytes RAM for decompression vocabulary tables
2 clock read/write accesses when used as a U-bus general-purpose RAM
4 clock load/store accesses from the L-bus
Byte, half-word (16-bit) or word (32-bit) read/write accesses and fetches
Special access protection functions
Low-power standby operation for data retention
4.1.5
•
•
•
•
Branch Target Buffer Key Features
Consists of eight “branch target entries” (BTE). Each entry contains:
— A 32-bit register that stores the target of historical change of flow (COF) address
— Four RAM entries, 38 bits each, which hold up to four valid instruction OPCODES (32 bits).
The six extra bits are used by ICDU in decompression on mode.
— A 32-bit register that stores the values used to calculate the address following the last valid
instruction.
FIFO removal policy management is implemented for the eight BTEs
Software-controlled BTB enable/disable and invalidate
User transparent (that is, no user management is required)
4.2
4.2.1
Operation Modes
Instruction Fetch
The BBC provides two instruction fetch modes: decompression off and decompression on. The operational
modes are defined by RCPU MSR[DCMPEN] bit. If the bit is set, the mode is decompression on.
Otherwise, it is in decompression off.
4.2.1.1
Decompression Off Mode
In this mode, the BBC bus interface unit (BIU) module transfers fetch accesses from the RCPU to the
U-bus. When a new access is issued by the RCPU, it is transferred in parallel to both the IMPU and the
BIU. The IMPU compares the address of the access to its region programming. The BIU checks if the
access can be immediately transferred to the U-bus, otherwise it requests the U-bus for the next clock.
MPC561/MPC563 Reference Manual, Rev. 1.2
4-4
Freescale Semiconductor
Burst Buffer Controller 2 Module
The BIU may be programmed for burstable or non-burstable access. If the BIU is programmed for
burstable access, the U-bus address phase transaction is accompanied by the burst request attribute. If
burstable access is allowed by the U-bus slave, the BIU continues current access as burstable, otherwise
current access is executed as a single access. If any protection violation is detected by the IMPU, the
current U-bus access is aborted by the BIU and an exception is signaled to the RCPU.
Show cycle, program trace and debug port access attributes accompanying the RCPU access are forwarded
by the BIU along with the U-bus access.
4.2.1.2
Decompression On Mode
See Appendix A, “MPC562/MPC564 Compression Features” for explanation of the decompression on
mode.
4.2.2
Burst Operation of the BBC
The BBC may initiate and handle burst accesses on the U-bus. The BBCMCR[BE] bit determines whether
the BBC operates burst cycles or not. Burst requests are enabled when the BE bit is set. The BBC handles
non-wrap-around bursts with up to 4 data beats on the internal U-bus.
NOTE
The burst operation in the MPC561/MPC563 is useful if a user system
implements burstable memory devices on the external bus. Otherwise the
mode will cause performance degradation when running code from external
memory.
When the RCPU runs in serialized mode it is recommended that bursts be
disabled by the BBC to speed up MPC561/MPC563 operation.
Burst operation for decompression on and in debug mode is disabled
regardless of BBCMCR[BE] bit setting.
The BBC burst should be turned off if the USIU burst feature is enabled.
4.2.3
Access Violation Detection
Instruction memory protection is assigned on a regional basis. Default operation of IMPU is done on a
global region. The IMPU has control registers which contain the following information: region protection
on/off, region base address, size and access permissions.
Protection logic is activated only if the RCPU MSR[IR] bit is set.
During each fetch request from the RCPU core to instruction memory, the address is compared to a value
in the region base address of enabled regions. Any address matching the specific region within its
appropriate size as defined in the region attribute register sets a match indication.
When more than one match indication occurs, the effective region is the region with the highest priority.
Priority is determined by region number. The lowest region number has the highest priority and the global
region has lowest priority.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-5
Burst Buffer Controller 2 Module
When no match happens, the effective region is the global region.
The region attribute registers contain the region protection fields: PP, G, and CMPR. The protection fields
are compared to address attributes issued by the RCPU. If the access is permitted, the address is passed to
the BIU and further to the U-bus.
Whenever the IMPU detects access violation, the following actions are taken:
1. The request forwarded to the BIU is canceled
2. The RCPU is informed that the requested address caused an access violation by exception request.
However, if the required address contains a show cycle attribute, the BIU delivers the access onto the
U-bus to obtain program tracking.
The exception vector (address) that the RCPU issues for this exception has a 0x1300 offset in the RCPU
exception vector table. The access violation status is provided in the RCPU SRR1 special purpose register.
The encoding of the status bits is as follows:
• SRR1 [1] = 0
• SRR1 [3] = Guarded storage
• SRR1 [4] = Protected storage or compression violation
• SRR1 [10] = 0
Only one bit is set at a time.
4.2.4
Slave Operation
The BBC is operating as a U-bus slave when the IMPU registers, decompressor RAM (DECRAM) or
ICDU registers are accessed from the U-bus. The IMPU register programming is done using PowerPC ISA
mtspr/mfspr instructions. The ICDU configuration registers (DCCRs) and DECRAM are mapped into the
chip memory space and accessed by load/store instructions. DCCR and DECRAM accesses may be
disabled by BBCMCR[DCAE]. Refer to Section 4.6.2.1, “BBC Module Configuration Register
(BBCMCR).”
4.2.5
Reset Behavior
Upon soft reset, the BBC switches to an idle state and all pending U-bus accesses are ignored, the ICDU
internal queue is flushed and the IMPU switches to a disabled state where all memory space is accessible
for both user and supervisor.
Hard reset sets some of the fields and bits in the BBC configuration registers to their default reset state.
Some bits in the BBCMCR register get their values from the reset configuration word.
All the registers are reset using HRESET; SRESET alone has no effect on them.
MPC561/MPC563 Reference Manual, Rev. 1.2
4-6
Freescale Semiconductor
Burst Buffer Controller 2 Module
NOTE
Because HRESET resets the EN_COMP bit and the EXC_COMP bit but
SRESET does not, there may be different behavior between HRESET and
SRESET when both EN_COMP and EXC_COMP are set. Special care must
be taken to ensure operation in a known mode whenever reset occurs. The
reset states of these bits are determined by reset configuration words. The
location of the reset vector is dependent on the value of the MSR[IP] bit in
the RCPU. If MSR[IP] is set, the exception table relocation feature can be
used. See Section 4.3.1, “ETR Operation.”
4.2.6
Debug Operation Mode
When the MPC561/MPC563 RCPU core is in debug mode, the BBC initiates non-burstable access to the
debug port and ICDU is bypassed (i.e., instructions transmitted to the debug port must be non-compressed
regardless of RCPU MSR[DCMPEN] bit state).
4.3
Exception Table Relocation (ETR)
The BBC is able to relocate the exception addresses of the RCPU. The relocation feature always maps the
exception addresses into the internal memory space of the MPC561/MPC563. See Figure 4-2. This feature
is important in multi-MPC561/MPC563 systems, where, although the memory map in some was shifted
to not be on the lower 4 Mbytes, their RCPU cores can still access their own exception handlers in their
internal Flash in spite of several RCPUs issuing the same exception addresses.
The relocation also saves wasted space between the exception table entries in the case where each
exception entry contained only a branch instruction to the exception routine, which is located elsewhere.
The exception vector table may be programmed to be located in four places in the MPC561/MPC563
internal memory space.
The exception table relocation is supported in both decompression on and decompression off operation
modes.
The RESET routine vector is relocated differently in decompression on and in decompression off modes.
This feature may be used by a software code compression tool to guarantee that a vocabulary table
initialization routine is always executed before application code is running.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-7
Burst Buffer Controller 2 Module
Exception Pointer by Core
Internal Memory Structure
0
0
Decompression
ON
Y
100
N
branch to...
8
branch to...
10
branch to...
branch to...
branch to...
200
branch to...
branch to...
300
branch to...
branch to...
400
500
branch to...
B8
branch to...
.
.
.
.
600
700
1F00
Exception Table
branch to...
.
.
.
.
branch to...
branch to...
Free Memory Space
1FFC
1FFC
Figure 4-2. Exception Table Entries Mapping
4.3.1
ETR Operation
The exception vectors generated by the RCPU are 0x100 bytes apart from each other, starting at address
0x0000 0100 or 0xFFF0 0100, depending on the value of MSR[IP] bit in the RCPU.
If the exception table relocation is disabled by the ETRE bit in the BBCMCR register, the BBC transfers
the exception fetch address to the U-bus of the MPC561/MPC563 with no interference. In this case, normal
PowerPC ISA exception addressing is implemented.
If the exception table relocation is enabled, the BBC translates the exception vector into the exception
relocation address as shown in Table 4-1. At that location, a branch instruction with absolute addressing
(ba) must be placed. Each ba instruction branches to the required exception routine. These branch
instructions should be successive in that region of memory. That way, a table of branch instructions is
implemented. Executing the branch instruction causes the core to branch twice until it gets to the exception
routine.
Each exception relocation table entry occupies two words to support decompression on mode, where a
branch instruction can be more than 32 bits long. The branch table can be located in four locations in the
internal memory, the location is defined by BBCMCR[OERC] as shown in Table 4-2.
MPC561/MPC563 Reference Manual, Rev. 1.2
4-8
Freescale Semiconductor
Burst Buffer Controller 2 Module
NOTE
The 8 Kbytes allocated for the original PowerPC ISA exception table can be
almost fully utilized. This is possible if the MPC561/MPC563 system
memory is not mapped to the exception address space, (i.e., the addresses
0xFFF0 0000 to 0xFFF0 1FFF are not used).
In such case, these 8 Kbytes can be fully utilized by the compiler, except
for the lower 64 words (256 bytes) which are dedicated for the branch
instructions.
If the RCPU, while executing an exception, issues any address between two
successive exception entries (e.g., 0xFFF0 0104), then the operation of the
MPC561/MPC563 is not guaranteed if the ETR is enabled.
In order to activate the exception table relocation feature, the following steps are required:
1. Set the RCPU MSR[IP] bit
2. Set the BBCMCR[ETRE] bit. See Section 4.6.2.1, “BBC Module Configuration Register
(BBCMCR),” for programming details.
The ETR feature can be activated from reset, by setting corresponding bits in the reset configuration word.
.
Table 4-1. Exception Addresses Mapping
Original Address Issues by
Core
Mapped Address by Exception Table
Relocation Logic
Reserved
0xFFF0 0000
Page_Offset+0x000
System Reset
0xFFF0 0100
Name of Exception
Compression disabled
Compression enabled
Page_Offset1+0x08
Page_Offset1+0x0B8
Machine Check
0xFFF0 0200
Page_Offset+0x010
Reserved
0xFFF0 0300
Page_Offset+0x018
Reserved
0xFFF0 0400
Page_Offset+0x020
External Interrupt2
0xFFF0 0500
Page_Offset+0x028
Alignment
0xFFF0 0600
Page_Offset+0x030
Program
0xFFF0 0700
Page_Offset+0x038
Floating Point unavailable
0xFFF0 0800
Page_Offset+0x040
Decrementer
0xFFF0 0900
Page_Offset+0x048
Reserved
0xFFF0 0A00
Page_Offset+0x050
Reserved
0xFFF0 0B00
Page_Offset+0x058
System Call
0xFFF0 0C00
Page_Offset+0x060
Trace
0xFFF0 0D00
Page_Offset+0x068
Floating Point Assist
0xFFF0 0E00
Page_Offset+0x070
Implementation Dependent
Software Emulation
0xFFF0 1000
Page_Offset+0x080
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-9
Burst Buffer Controller 2 Module
Table 4-1. Exception Addresses Mapping (continued)
Original Address Issues by
Core
Mapped Address by Exception Table
Relocation Logic
Implementation Dependent
Instruction Storage
Protection Error
0xFFF0 1300
Page_Offset+0x098
Implementation Dependent
Data Storage Protection
Error
0xFFF0 1400
Page_Offset+0x0A0
Implementation Dependent
Data Breakpoint
0xFFF0 1C00
Page_Offset+0x0E0
Implementation Dependent
Instruction Breakpoint
0x0FFF 1D00
Page_Offset+0x0E8
Implementation Dependent
Maskable External
Breakpoint
0xFFF0 1E00
Page_Offset+0x0F0
Non-Maskable External
Breakpoint
0xFFF0 1F00
Page_Offset+0x0F8
Name of Exception
1
2
Refer to Table 4-2.
0x500 is remapped if the EEIR feature is enabled. See Section 4.3.2, “Enhanced External Interrupt Relocation
(EEIR).”
Table 4-2. Exception Relocation Page Offset
BBCMCR(OERC[0:1])
1
2
4.3.2
Page Offset
0x0 + ISB
offset1
Comments
0
0
0
0
1
0x1 0000 + ISB offset
64 Kbytes2
1
0
0x8 0000 + ISB offset
512 Kbytes
1
1
0x3F E000 + ISB offset
L-bus (CALRAM)
Address
ISB offset is equal 4M * ISB (0x400000 * ISB), where ISB is value of bit field in USIU IMMR register.
This offset is different from the MPC555.
Enhanced External Interrupt Relocation (EEIR)
The BBC also supports the enhanced external interrupt model of the MPC561/MPC563 which allows the
removal of the interrupt requesting a source detection stage from the interrupt routine. The interrupt
controller provides the interrupt vector to the BBC together with an interrupt request to the RCPU. When
the RCPU acknowledges an interrupt request, it issues an external interrupt vector to the BBC. The BBC
logic detects this address and replaces it with another address corresponding to the interrupt controller
vector, which is defined by the highest priority interrupt request from a peripherial module or external
interrupt request pin. See Figure 4-3.
The external interrupt relocation table should be placed at the physical address defined in the external
interrupt relocation table base address register. See Section 4.6.2.5, “External Interrupt Relocation Table
MPC561/MPC563 Reference Manual, Rev. 1.2
4-10
Freescale Semiconductor
Burst Buffer Controller 2 Module
Base Address Register (EIBADR).” This is the base address of a branch table. See Table 6-4 and
Figure 4-3.
Each table entry must contain a branch absolute (ba) instruction to the first instruction of an interrupt
service routine. Each table entry occupies two words (eight bytes) to support decompression on mode,
where a branch instruction can be more than 32 bits long.
The memory space allocated for the external interrupt relocation table is up to 2 Kbytes. If part of the
external interrupt relocation table entry is not used, it may be utilized for another purpose such as
instruction code space or data space.
In order to activate the external interrupt relocation feature, the following steps are required:
1. Program the EIBADR register to the external interrupt branch table base address. See
Section 4.6.2.5, “External Interrupt Relocation Table Base Address Register (EIBADR).”
2. Set the MSR[IP] bit.
3. Set the BBCMCR[EIR] bit. See Section 4.6.2.1, “BBC Module Configuration Register
(BBCMCR),” for programming details.
NOTE
If both the enhanced external interrupt relocation and exception table
relocation functions are activated simultaneously, the final external interrupt
vector is defined by EEIR mechanism.
When the EEIR function is activated, any branch instruction execution with
the 0xFFF0 0500 target address may cause unpredictable program
execution.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-11
Burst Buffer Controller 2 Module
Internal Memory Structure
EIBADR
Branch absolute to handler
Branch absolute to handler
Branch absolute to handler
External
Interrupt
0x500
Relocation Table
Interrupt
Vector
Offset
000
Base Address
(EIBADR)
External Interrupt Handlers Table
External Interrupt
Vector Relocator
Translated Vectors
Interrupt Pointer by Core
Branch absolute to handler
Interrupt Code
from Interrupt
Controller
Branch absolute to handler
Main code can start here
Figure 4-3. External Interrupt Vectors Splitting
4.4
Decompressor RAM (DECRAM) Functionality
Decompressor RAM (DECRAM) is a part of the ICDU. It occupies a 2-Kbyte physical RAM array block.
It is mapped both in the ICDU internal address space and in the chip memory address space. It is a single
port memory and may not be accessed simultaneously from the ICDU and U-bus.
MPC561/MPC563 Reference Manual, Rev. 1.2
4-12
Freescale Semiconductor
Burst Buffer Controller 2 Module
U-bus Address
U-bus Data
Slave BIU
ICDU
Vocabulary Table (VT1)
Array (1 Kbyte)
Vocabulary Table (VT2)
Array (1 Kbyte)
DECRAM
VT1 Data
VT1 Address
VT2 Data
VT2 Address
ICDU Control Logic
Figure 4-4. DECRAM Interfaces Block Diagram
4.4.1
General-Purpose Memory Operation
In the case of decompression off mode, the DECRAM can serve as a two-clock access general-purpose
RAM for U-bus instruction fetches or four-clock access for read/write data operations. The base address
of the DECRAM is 0x2F 8000. See Figure 4-6. The proper access rights to the DECRAM array may be
defined by programming the R, D, and S bits of the BBCMCR register:
• Read/write or read only
• Instruction/data or data only
• Supervisor/user or supervisor only
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-13
Burst Buffer Controller 2 Module
U-bus access mode of the RAM is activated by the BBCMCR[DCAE] bit setting (see Section 4.6.2.1,
“BBC Module Configuration Register (BBCMCR)”). In this mode the DECRAM can be accessed from
the U-bus and cannot be accessed by the ICDU logic.
In this mode:
• The DECRAM supports word, half-word and byte operations.
• The DECRAM is emulated to be 32 bits wide. For example: a load access from offset 0 in the
DECRAM will deliver the concatenation of the first word in each of the DECRAM banks when
RAM 1 contains the 16 LSB of the word and RAM 2 contains the 16 MSB.
• Load accesses at any width are supplied with 32 bits of valid data.
• The DECRAM communicates with the U-bus pipeline but does not support pipelined accesses to
itself. If a store operation is second in the U-bus pipe, the store is carried out immediately and the
U-bus acknowledgment is performed when the previous transaction in the pipe completes.
• Burst access is not supported.
NOTE
Instructions running from the DECRAM should not also perform store
operations to the DECRAM.
4.4.1.1
Memory Protection Violations
The DECRAM module does not acknowledge U-bus accesses that violate the configuration defined in the
BBCMCR. This causes the machine check exception for the internal RCPU or an error condition for the
MPC561/MPC563 external master.
4.4.1.2
DECRAM Standby Operation Mode
The bus interface and DECRAM control logic are powered by VDD supply. The memory array is supplied
by a separate power pin (IRAMSTBY).
4.5
Branch Target Buffer
The burst buffer controller contains a branch target buffer (BTB) to reduce the impact of branches on
processor performance. Following is a summary of the BTB features:
• Software controlled BTB enable/disable, inhibit, and invalidate
• User transparent — no user management required
The BTB consists of eight branch target entries (BTE). Refer to Figure 4-5. All entries are managed as a
fully associative cache. Each entry contains a tag and several data buffers related to this tag.
4.5.1
BTB Operation
When the RCPU generates a change of flow (COF) address for instruction fetch, the BTB control logic
compares it to the tag values currently stored in the tag register file where the following events can happen:
MPC561/MPC563 Reference Manual, Rev. 1.2
4-14
Freescale Semiconductor
Burst Buffer Controller 2 Module
•
•
BTE Miss — The target address and instruction code data will be stored in one of the BTE entries
defined by its control logic. Up to four instructions and their corresponding addresses subsequent
to the COF target instruction may be saved in each BTE entry. The number of valid instructions
currently stored in the BTE entry is written into the VDC field of the current BTE entry. The valid
flag is set at the end of this process. The entry to be replaced upon miss is chosen based on FIFO
replacement method. Thus the BTB can support up to eight different branch target addresses in a
program loop.
BTE Hit — When the target address of a branch matches one of the valid BTE entries, two
activities take place in parallel:
— The BTB supplies all the valid instructions in the matched entry to the RCPU.
— The BIU starts to prefetch new instructions (and ICDU decompresses them in compressed
mode) from the address following the last instruction that is stored in the matched BTB entry.
The BBC will supply these new instructions to the RCPU after all the stored instructions in the
matched BTB entry were delivered.
In case of a BTB hit, the impact of instruction decompression latency (in compressed mode) is eliminated
as well as a latency of instruction storage memory device.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-15
Burst Buffer Controller 2 Module
BTE TAG Register File
BTE Memory Array
32-bit
Instruction
Address
Tag Register/Comparator
Next Address
VDC
Hit
V
Instruction Buffers
Tag Register/Comparator
Next Address
VDC
Hit
V
Instruction Buffers
Tag Register/Comparator
Next Address
VDC
Hit
V
Instruction Buffers
Tag Register/Comparator
Next Address
VDC
Hit
Tag Register/Comparator
Next Address
VDC
Hit
VDC
Hit
VDC
Hit
VDC
Instruction Buffers
V
Tag Register/Comparator
Next Address
Instruction Buffers
V
Tag Register/Comparator
Next Address
Instruction Buffers
V
Tag Register/Comparator
Next Address
Instruction Buffers
V
Hit
Instruction Buffers
V
BTB Hit
Figure 4-5. BTB Block Diagram
4.5.1.1
BTB Invalidation
Write access to any BBC special purpose register invalidates all BTB entries.
NOTE
To guarantee that the BTB does not contain instructions that may have been
changed, the BTB contents should be invalidated any time instruction
memory is modified.
4.5.1.2
BTB Enabling/Disabling
The BTB operation may be enabled or disabled by programming the BTEE bit in the BBCMCR register.
4.5.1.3
BTB Inhibit Regions
The BTB operation may be inhibited regarding some memory regions. The BTB caching is inhibited for
a region if the BTBINH bit is set in the region attribute register (or global region attribute register). See
MPC561/MPC563 Reference Manual, Rev. 1.2
4-16
Freescale Semiconductor
Burst Buffer Controller 2 Module
Section 4.6.2.3, “Region Attribute Registers (MI_RA[0:3]),” and Section 4.6.2.4, “Global Region
Attribute Register (MI_GRA)” for details.
4.6
BBC Programming Model
4.6.1
Address Map
The BBC consists of three separately addressable sections within the internal chip address space:
1. BBC and IMPU control registers. These are mapped in the SPR registers area and may be
programmed by using the RCPU mtspr/mfspr instructions.
2. Decompressor vocabulary RAM (DECRAM). The DECRAM array occupies the 2-Kbyte physical
memory (8 Kbytes of the MPC561/MPC563 address space is allocated for DECRAM).
3. Decompressor class configuration registers (DCCR) block. It consists of 15 decompression class
configuration registers. These registers are available for word wide read/write accesses through
U-bus. The registers occupy a 64-byte physical block (8-Kbyte chip address space is allocated for
the register block).
0x2F 8000
0x2F 87FF
0x2F 8800
DECRAM
2 Kbytes
Reserved
0x2F 9FFF
0x2F A000
DCCR0 – DCCR15
0x2F A03F
Figure 4-6. MPC561/MPC563 Memory Map
4.6.1.1
BBC Special Purpose Registers (SPRs)
Table 4-3. BBC SPRs
SPR Number
(Decimal)
Address for
External
Master
Access (Hex)
528
0x2100
IMPU Global Region Attribute Register (MI_GRA). See Table 4-8 for bits
descriptions.
529
0x2300
External Interrupt Relocation Table Base Address Register (EIBADR). See
Table 4-9 for bits descriptions.
560
0x2110
BBC Module Configuration Register (BBCMCR). See Table 4-4 for bits descriptions
Register Name
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-17
Burst Buffer Controller 2 Module
Table 4-3. BBC SPRs (continued)
SPR Number
(Decimal)
Address for
External
Master
Access (Hex)
784
0x2180
IMPU Region Base Address Register 0 (MI_RBA0). See Table 4-5 for bits
descriptions.
785
0x2380
IMPU Region Base Address Register 1 (MI_RBA1). See Table 4-5 for bits
descriptions.
786
0x2580
IMPU Region Base Address Register 2 (MI_RBA2). See Table 4-5 for bits
descriptions.
787
0x2780
IMPU Region Base Address Register 3 (MI_RBA3). See Table 4-5 for bits
descriptions.
816
0x2190
IMPU Region Attribute Register 0 (MI_RA0). See Table 4-6 for bits descriptions.
817
0x2390
IMPU Region Attribute Register 1 (MI_RA1). See Table 4-6 for bits descriptions.
818
0x2590
IMPU Region Attribute Register 2 (MI_RA2). See Table 4-6 for bits descriptions.
819
0x2790
IMPU Region Attribute Register 3 (MI_RA3). See Table 4-6 for bits descriptions.
Register Name
All the above registers may be accessed in the supervisor mode only. An exception is internally generated
by the RCPU if there is an attempt to access them in user mode. An external master receives a transfer
error acknowledge when attempting to access a register in user mode.
NOTE
If one of these registers is written within 4 instructions of a branch target,
the user application may crash. To prevent this, ensure that any instruction
writing to these registers is preceded by 4 instructions that are not the target
of any branch, and is followed by an isync instruction.
4.6.1.2
DECRAM and DCCR Block
The DECRAM occupies addresses from 0x2F 8000 to 0x2F 87FF. The DCCR block occupies addresses
from 0x2F A000 to 0x2F A03F.
The address for non-implemented memory blocks is not acknowledged, and causes an error condition.
MPC561/MPC563 Reference Manual, Rev. 1.2
4-18
Freescale Semiconductor
Burst Buffer Controller 2 Module
4.6.2
BBC Register Descriptions
4.6.2.1
BBC Module Configuration Register (BBCMCR)
,
MSB
Field
0
1
2
R
D
S
3
4
5
6
7
8
9
10
TEST
HRESET
11 12 13
14
15
—
0000_0000_0000_0000
LSB
16
Field
HRESET
17
—
18
BE
19
21
ETRE EIR
ID192
000
20
0
22
23
1
EN_ EXC_COMP
COMP1
ID212
ID222
Addr
24
25
26
DECOMP_SC_ OERC[0:1] BTEE
EN1
ID212
ID(24:25)2
27 28 29
—
30
31
DCAE TST
00_0000
SPR 560
Figure 4-7. BBC Module Configuration Register (BBCMCR)
1
MPC562/MPC564 only.
2 The reset value is a reset configuration word value extracted from the internal bus line. Refer to Section 7.5.2, “Hard Reset
Configuration Word (RCW).”
Table 4-4. BBCMCR Field Descriptions
Bits
Name
Description
0
R
Read Only. Any attempt to write to the DECRAM array while R is set is terminated with
an error. This causes a machine check exception for RCPU.
0 DECRAM array is Readable and Writable.
1 DECRAM array is Read only.
1
D
Data Only. The DECRAM array may be used for Instructions and Data or for Data
storage only. Any attempt to load instructions from the DECRAM array, while D is set, is
terminated with an error This causes a machine check exception for the RCPU.
0 DECRAM array holds Data and/or Instruction.
1 DECRAM array holds Data only.
2
S
Supervisor Only.
When the bit is set (S = 1), only a Supervisor program may access the DECRAM. If a
Supervisor program is accessing the array, normal read/write operation will occur. If a
User program is attempting to access the array, the access will be terminated with an
error This causes a machine check exception for the RCPU.
If S = 0, the RAM array is placed in Unrestricted Space and access by both Supervisor
and User programs is allowed.
3:7
TEST
8:17
—
18
BE1
These bits can be set in Factory test mode only. The User should treat these bits as
reserved and always write as zeros.
Reserved
Burst Enable
0 Burst access is disabled.
1 Burst access is enabled.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-19
Burst Buffer Controller 2 Module
Table 4-4. BBCMCR Field Descriptions (continued)
Bits
Name
Description
19
ETRE
Exception Table Relocation Enable
0 Exception Table Relocation is off: BBC does NOT map exception addresses.
1 Exception Table Relocation is on: BBC maps exception addresses to a table holding
branch instructions two memory words apart from each other.
The reset value is taken from the reset configuration word bit 19.
Note: On the MPC562/MPC564, do not put compressed code at addresses 0xFFF0
0000 to 0xFFFF FFFF if ETRE = 1.
20
EIR
Enhanced External Interrupt Relocation Enable— This bit activates the external
interrupt relocation table mechanism. This bit is independent from the value of ETRE
bit, but if EIR and ETRE are enabled, the mapping of external interrupt will be via EIR.
0 EIR function is disabled.
1 EIR function is active.
21
EN_COMP2
Enable Compression. This bit enables the operation of the MPC562/MPC564 in
compression on mode.
NOTE: For Rev A and later versions of the MPC563 and rev B and later of the MPC561,
the default state is defined by bit 21 of the reset configuration word, and is writable. In
earlier versions, the bit can only be set by the reset configuration word.
0 decompression on mode is disabled.
1 decompression on mode is enabled.
The MPC561/MPC563 operates only in decompression off mode. The
MPC562/MPC564 may operate with both decompression on and decompression off
modes.
22
EXC_COMP2
Exception Compression. This bit determines the operation of the MPC562/MPC564
with exceptions. If this bit is set, the MPC562/MPC564 assumes that the all exception
routine codes are compressed; otherwise it is assumed that all exception routine codes
are not compressed. The reset value is determined by reset configuration word bit 22.
0 The RCPU assumes that exception routines are noncompressed.
1 The RCPU assumes that all exception routines are compressed.
This bit has effects only when the EN_COMP bit is set. The MPC561/MPC563 operates
only in decompression off mode. The MPC562/MPC564 may operate with both
decompression on and decompression off modes.
23
DECOMP_SC_EN2 Decompression Show Cycle Enable. This bit determines the way the MPC562/MPC564
executes instruction show cycles.
The reset value is determined by configuration word bit 21. For further details regarding
show cycles execution in “Decompression ON” mode see Section 4.2.1.2,
“Decompression On Mode.”
0 Decompression Show Cycles do not include the bit pointer.
1 Decompression Show Cycles include the bit pointer information on the data bus.
24:25
OERC[0:1]
Other Exceptions Relocation Control. These bits have effect only if ETRE was enabled;
See details in Section 4.3.1, “ETR Operation.”
00: offset 0
01 Offset 64 Kbytes
10 Offset 512 Kbytes
11 Offset to 0x003FE000
The reset value is determined by reset configuration word bits 24 and 25
26
BTEE1
Branch Target Entries Enable. This bit enables Branch Target Entries of BTB operation
0 BTE operation is disabled
1 BTE operation is enabled
MPC561/MPC563 Reference Manual, Rev. 1.2
4-20
Freescale Semiconductor
Burst Buffer Controller 2 Module
Table 4-4. BBCMCR Field Descriptions (continued)
1
2
Bits
Name
27:29
—
30
DCAE
31
TST
Description
Reserved.
NOTE: Bit 27 was BCMEE and should be written as 0.
Decompressor Configuration Access Enable. This bit enables DECRAM and DCCR
registers access from the U-bus master (i.e., RCPU, external master).
0 DECRAM and DCCR registers are locked.
1 DECRAM allows accesses from the U-bus only.
DCAE bit should be set before vocabulary tables are loaded via the U-bus.
Reserved for BBC Test Operations.
BE and BTEE should not both be set at the same time, setting the BE bit disables the BTB.
This bit is available on the MPC562/MPC564 only, software should write "0" to this bit for MPC561/MPC563.
NOTE
When writing to the BBCMCR register, the following instruction after
mtspr BBCMCR, Rx should be ISYNC, to make sure that the programmed
value will come into effect before any further action.
4.6.2.2
Region Base Address Registers (MI_RBA[0:3])
The following registers contain 32 bits and define the starting address of the protected regions. There is
one register for each of four regions.
,
MSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
25
26
27
28
29
30
15
RA
HRESET
Unchanged
LSB
16
17
Field
HRESET
18
19
20
21
22
23
24
RA
—
Undefined
0000_0000_0000
Addr
31
SPR 784 (MI_RBA0), SPR 785 (MI_RBA1), SPR 786 (MI_RBA2), SPR 787 (MI_RBA3)
Figure 4-8. Region Base Address Register (MI_RBA[0:3])
Table 4-5. MI_RBA[0:3] Registers Bit Descriptions
Bits
Name
Description
0:19
RA
Region Base address. The RA field provides the base address of the region. The region base
address should start on the memory block boundary for the corresponding region size, specified
in the region attribute register MI_RA.
20:31
—
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-21
Burst Buffer Controller 2 Module
NOTE
When the MPC562/MPC564 operates in decompression on mode, a
minimum of four unused words MUST be left after the last instruction in
any region.
4.6.2.3
Region Attribute Registers (MI_RA[0:3])
The following registers define protection attributes and size for four memory regions.
,
MSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
25
26
27
28
29
30
15
RS
HRESET
Unchanged
LSB
16
17
Field
18
19
RS
HRESET
21
PP
Undefined
Addr
20
22
23
—
24
G
000
CMPR
BTBINH
Undefined
31
—
000
SPR 816 (MI_RA0), SPR 817 (MI_RA1), SPR 818 (MI_RA2), 819 (MI_RA3)
Figure 4-9. Region Attribute Register (MI_RA0[0:3])
Table 4-6. MI_RA[0:3] Registers Bit Descriptions
Bits
Name
Description
0:19
RS
Region size. For byte size by region, see Table 4-7.
20:21
PP1
Protection bits:
00 Supervisor — No Access, User — No Access.
01 Supervisor — Fetch, User — No Access.
1x Supervisor — Fetch, User — Fetch.
22:24
—
Reserved
25
G1
Guard attribute for region
0 Speculative fetch is not prohibited from region. Region is not guarded.
1 Speculative fetch is prohibited from guarded region. An exception will occur under such attempt.
26:27
CMPR2
Compressed Region.
x0 The region in not restricted
01 Region is considered a non-compressed code region. Access to the region is allowed only in
“Decompression Off” mode
11 Region is considered a compressed code region. Access to the region is allowed only in
“Decompression On” mode
28
BTBINH
BTB Inhibit region
0 BTB operation is not prohibited for current memory region
1 BTB operation is prohibited for current memory region.
29:31
—
Reserved
1
G and PP attributes perform similar protection activities on a region. The more protective attribute will be implied on the
region if the attributes programming oppose each other.
2
This field is available only on the MPC562/MPC564.
MPC561/MPC563 Reference Manual, Rev. 1.2
4-22
Freescale Semiconductor
Burst Buffer Controller 2 Module
Table 4-7. Region Size Programming Possible Values
RS Field Value (Binary)
4.6.2.4
Size
0000_0000_0000_0000_0000
4 Kbytes
0000_0000_0000_0000_0001
8 Kbytes
0000_0000_0000_0000_0011
16 Kbytes
0000_0000_0000_0000_0111
32 Kbytes
0000_0000_0000_0000_1111
64 Kbytes
0000_0000_0000_0001_1111
128 Kbytes
0000_0000_0000_0011_1111
256 Kbytes
0000_0000_0000_0111_1111
512 Kbytes
0000_0000_0000_1111_1111
1 Mbyte
0000_0000_0001_1111_1111
2 Mbytes
0000_0000_0011_1111_1111
4 Mbytes
0000_0000_0111_1111_1111
8 Mbytes
0000_0000_1111_1111_1111
16 Mbytes
0000_0001_1111_1111_1111
32 Mbytes
0000_0011_1111_1111_1111
64 Mbytes
0000_0111_1111_1111_1111
128 Mbytes
0000_1111_1111_1111_1111
256 Mbytes
0001_1111_1111_1111_1111
512 Mbytes
0011_1111_1111_1111_1111
1 Gbyte
0111_1111_1111_1111_1111
2 Gbytes
1111_1111_1111_1111_1111
4 Gbytes
Global Region Attribute Register (MI_GRA)
The MI_GRA register defines protection attributes for memory region, not covered by
MI_RB[0:3]/MI_RBA[0:3] registers. It also contains protection regions 0-3 enable bits.
,
MSB
0
1
2
3
4
5
6
7
8
9
Field ENR 0 ENR1 ENR2 ENR3
10
11
12
13
14
27
28
29
30
15
—
HRESET
0000_0000_0000_0000
LSB
16
17
Field
HRESET
Addr
18
—
19
20
21
PP
22
23
24
—
25
G
26
CMPR
BTBINH
31
—
0000_0000_0000_0000
SPR 528
Figure 4-10. Global Region Attribute Register (MI_GRA)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-23
Burst Buffer Controller 2 Module
Table 4-8. MI_GRA Field Descriptions
1
Bits
Name
Description
0
ENR0
Enable IMPU Region 0
0 Region 0 is off.
1 Region 0 is on.
1
ENR1
Enable IMPU Region 1
0 Region 1 is off.
1 Region 1 is on.
2
ENR2
Enable IMPU Region 2
0 Region 2 is off.
1 Region 2 is on.
3
ENR3
Enable IMPU Region 3
0 Region 3 is off.
1 Region 3 is on.
4:19
—
Reserved
20:21
PP
Protection Bits
00 Supervisor – No Access, User – No Access.
01 Supervisor – Fetch, User – No Access.
1x Supervisor – Fetch, User – Fetch.
22:24
—
Reserved
25
G
Guard attribute for region
0 Fetch is not prohibited from region. Region is not guarded.
1 Fetch is prohibited from guarded region. An exception will occur under such attempt.
26:27
CMPR1
Compressed Region.
x0 The region is not restricted
01 Region is considered a non-compressed code region Access to the region is allowed only in
“Decompression Off” mode
11 Region is considered a compressed code region. Access to the region is allowed only in
“Decompression On” mode
28
BTBINH
BTB Inhibit region
0 BTB operation is not prohibited for current memory region
1 BTB operation is prohibited for current memory region.
29:31
—
Reserved
This field is available only on the MPC562/MPC564.
NOTE
The MI_GRA register should be programmed to enable fetch access (PP and
G bits) before RCPU MSR[IR] is set.
MPC561/MPC563 Reference Manual, Rev. 1.2
4-24
Freescale Semiconductor
Burst Buffer Controller 2 Module
4.6.2.5
External Interrupt Relocation Table Base Address Register (EIBADR)
,
MSB
0
LSB
1
2
Field
HRESET
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
18 19 20 21 22 23 24 25 26 27 28 29 30
BA
—
Unchanged
000_0000_0000
31
Figure 4-11. External Interrupt Relocation Table Base Address Register (EIBADR)
Table 4-9. EIBADR External Interrupt Relocation Table Base Address Register Bit Descriptions
Bits
Name
0:20
BA
External Interrupt Relocation Table Base Address bits [0:20]
21:31
—
Reserved. EIBADR must be set on a 4K page boundary.
4.6.3
Description
Decompressor Class Configuration Registers
See Section A.4, “Decompressor Class Configuration Registers (DCCR0-15)” for the registers of the
ICDU.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-25
Burst Buffer Controller 2 Module
MPC561/MPC563 Reference Manual, Rev. 1.2
4-26
Freescale Semiconductor
Chapter 5
Unified System Interface Unit (USIU) Overview
The unified system interface unit (USIU) of the MPC561/MPC563 consists of several functional modules
that control system start-up, system initialization and operation, system protection, and the external system
bus. The MPC561/MPC563 USIU functions include the following and are discussed in the designated
chapters:
• System configuration and protection with GPIO capability and an enhanced interrupt controller.
Refer to Chapter 6, “System Configuration and Protection.”
• System reset monitoring and generation, refer to Chapter 7, “Reset.”
• Clock synthesis, power management, and debug support. Refer to Chapter 8, “Clocks and Power
Control.”
• External bus interface (EBI), refer to Chapter 9, “External Bus Interface.”
• Memory controller that supports four memory banks. Refer to Chapter 10, “Memory Controller.”
The USIU provides system configuration and protection features that control the overall system
configuration and supply various monitors and timers including the bus monitor, software watchdog timer,
periodic interrupt timer, decrementer, time base, and real-time clock. Freeze support and low power stop
is provided. The interrupt controller supports up to eight external interrupts, eight levels for all internal
USIU interrupt sources and 32 levels for internal peripheral modules on the IMB bus. It has an enhanced
mode of operation, which simplifies the MPC561/MPC563 interrupt structure and speeds up interrupt
processing.
Additionally, the USIU provides several pinout configurations that allow up to 64 general-purpose I/O,
external 32-bit port that supports internal and external masters, and various debug functions.
Reset logic for the MPC561/MPC563 provides soft and hard resets, checkstop and watchdog resets, and
other types of reset. The reset status register (RSR) reflects the most recent source to cause a reset.
The clock synthesizer generates the clock signals used by the USIU as well as the other modules and
external devices. This circuitry can generate a system clock from a range of crystals, typically in the 4 MHz
or 20 MHz range.
The USIU supports various low-power modes. Each one supplies a different range of power consumption,
functionality and wake-up time. Refer to Chapter 8, “Clocks and Power Control,” for details.
The EBI handles the transfer of information between the internal busses and the memory or peripherals in
the external address space. The MPC561/MPC563 is designed to allow external bus masters to request and
obtain mastership of the system bus, and if required access the on-chip memory and registers. Refer to
Chapter 9, “External Bus Interface,” for details.
The memory controller module provides glueless interface to many types of memory devices and
peripherals. It supports up to four memory banks. Refer to Chapter 10, “Memory Controller,” for details.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
5-1
Unified System Interface Unit (USIU) Overview
The USIU supports the internal Flash censorship mechanism on the MPC561/MPC563 to protect the Flash
contents. Refer to Chapter 21, “CDR3 Flash (UC3F) EEPROM.” It is not possible to operate the
MPC561/MPC563 from the external world while the Flash is in censorship mode and in a censorship state.
The internal Flash array will be either locked or accessible only after the entire array contents have been
erased. The MPC561/MPC563 is in censored mode if one of the following events occurs:
• booting from external memory
• operating in peripheral mode or if accessed from an external master
• operating in debug mode (BDM or Nexus)
Figure 5-1 shows the USIU block diagram.
USIU
Memory Control Lines
Memory
Controller
U-Bus
U-bus
Interface
Address
E-bus
Interface
E-Bus
•
•
•
•
•
•
•
•
Configuration Registers
Software Watchdog
Bus Monitor
Periodic Interrupt
Timer and Decrementer
Real-time Clock
Debug
Pin Multiplexing
Interrupt Controller
Sub bus
Data
Slave
Interface
SGPIO
Clocks & Reset
Figure 5-1. USIU Block Diagram
5.1
Memory Map and Registers
Table 5-1 is an address map of the USIU registers and, unless otherwise noted, registers are 32 bits wide.
The address shown for each register is relative to the base address of the MPC561/MPC563 internal
memory map. The internal memory block can reside in one of eight possible 4 Mbyte memory spaces. See
Figure 1-3 for details.
MPC561/MPC563 Reference Manual, Rev. 1.2
5-2
Freescale Semiconductor
Unified System Interface Unit (USIU) Overview
Table 5-1. USIU Address Map
Address
Register
0x2F C000
USIU Module Configuration Register (SIUMCR)
See Table 6-7 for bit descriptions.
0x2F C004
System Protection Control Register (SYPCR)
See Table 6-15 for bit descriptions.
0x2F C008
Reserved
0x2F C00E1
Software Service Register (SWSR)
See Table 6-16 for bit descriptions.
0x2F C010
Interrupt Pending Register (SIPEND).
0x2F C014
Interrupt Mask Register (SIMASK)
See Section 6.2.2.2.4, “SIU Interrupt Mask Register (SIMASK),” for bit descriptions.
0x2F C018
Interrupt Edge Level Mask (SIEL)
See Section 6.2.2.2.7, “SIU Interrupt Edge Level Register (SIEL),” for bit descriptions.
0x2F C01C
Interrupt Vector (SIVEC)
See Section 6.2.2.2.8, “SIU Interrupt Vector Register (SIVEC),” for bit descriptions.
0x2F C020
Transfer Error Status Register (TESR)
See Table 6-17 for bit descriptions.
0x2F C024
USIU General-Purpose I/O Data Register (SGPIODT1)
See Table 6-23 for bit descriptions.
0x2F C028
USIU General-Purpose I/O Data Register 2 (SGPIODT2)
See Table 6-24 for bit descriptions.
0x2F C02C
USIU General-Purpose I/O Control Register (SGPIOCR)
See Table 6-25 for bit descriptions.
0x2F C030
External Master Mode Control Register (EMCR)
See Table 6-13 for bit descriptions.
0x2F C038
Pads Module Configuration Register 2 (PDMCR2)
See Table 2-6 for bit descriptions.
0x2F C03C
Pads Module Configuration Register (PDMCR)
See Table 2-5 for bit descriptions.
0x2F C040
Interrupt Pend2 Register (SIPEND2)
See Section 6.2.2.2.2, “SIU Interrupt Pending Register 2 (SIPEND2),” for bit descriptions.
0x2F C044
Interrupt Pend3 Register (SIPEND3)
See Section 6.2.2.2.3, “SIU Interrupt Pending Register 3 (SIPEND3),” for bit descriptions.
0x2F C048
Interrupt Mask2 Register (SIMASK2)
See Section 6.2.2.2.5, “SIU Interrupt Mask Register 2 (SIMASK2),” for details.
0x2F C04C
Interrupt Mask3 Register (SIMASK3)
See Section 6.2.2.2.6, “SIU Interrupt Mask Register 3 (SIMASK3),” for details.
0x2F C050
Interrupt In-Service2 Register (SISR2)
See Section 6.2.2.2.9, “Interrupt In-Service Registers (SISR2 and SISR3),” for details.
0x2F C054
Interrupt In-Service3 Register (SISR3)
See Section 6.2.2.2.9, “Interrupt In-Service Registers (SISR2 and SISR3),” for details.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
5-3
Unified System Interface Unit (USIU) Overview
Table 5-1. USIU Address Map (continued)
Address
0x2F C0FC–0x2F
C0FF
Register
Reserved
Memory Controller Registers
0x2F C100
Base Register 0 (BR0)
See Table 10-8 for bit descriptions.
0x2F C104
Option Register 0 (OR0)
See Table 10-10 for bit descriptions.
0x2F C108
Base Register 1 (BR1)
See Table 10-8 for bit descriptions.
0x2F C10C
Option Register 1 (OR1)
See Table 10-10 for bit descriptions.
0x2F C110
Base Register 2 (BR2)
See Table 10-8 for bit descriptions.
0x2F C114
Option Register 2 (OR2)
See Table 10-10 for bit descriptions.
0x2F C118
Base Register 3 (BR3)
See Table 10-8 for bit descriptions.
0x2F C11C
Option Register 3 (OR3)
See Table 10-10 for bit descriptions.
0x2F C120–0x2F C13C Reserved
0x2F C140
Dual-Mapping Base Register (DMBR)
See Table 10-11 for bit descriptions.
0x2F C144
Dual-Mapping Option Register (DMOR)
See Table 10-12 for bit descriptions.
0x2F C148–0x2F C174 Reserved
0x2F C1781
0x2F C17A–0x2F
C1FC
Memory Status (MSTAT)
See Table 10-7 for bit descriptions.
Reserved
System Integration Timers
0x2F C200
Time Base Status and Control (TBSCR)
See Table 6-18 for bit descriptions.
0x2F C204
Time Base Reference 0 (TBREF0)
See Section 6.2.2.4.3, “Time Base Reference Registers (TBREF0 and TBREF1),” for bit
descriptions.
0x2F C208
Time Base Reference 1 (TBREF1)
See Section 6.2.2.4.3, “Time Base Reference Registers (TBREF0 and TBREF1),” for bit
descriptions.
0x2F C20C–0x2F
C21C
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
5-4
Freescale Semiconductor
Unified System Interface Unit (USIU) Overview
Table 5-1. USIU Address Map (continued)
Address
Register
0x2F C220
Real-Time Clock Status and Control (RTCSC)
See Table 6-19 for bit descriptions.
0x2F C224
Real-Time Clock (RTC)
See Section 6.2.2.4.6, “Real-Time Clock Register (RTC),” for bit descriptions.
0x2F C228
Real-Time Alarm Seconds (RTSEC) — Reserved
0x2F C22C
Real-Time Alarm (RTCAL)
See Section 6.2.2.4.7, “Real-Time Clock Alarm Register (RTCAL),” for bit descriptions.
0x2F C230–0x2F C23C Reserved
0x2F C240
PIT Status and Control (PISCR)
See Table 6-20 for bit descriptions.
0x2F C244
PIT Count (PITC)
See Table 6-21 for bit descriptions.
0x2F C248
PIT Register (PITR)
See Table 6-22 for bit descriptions.
0x2F C24C–0x2F
C27C
Reserved
Clocks and Reset
0x2F C280
System Clock Control Register (SCCR)
See Table 8-9 for bit descriptions.
0x2F C284
PLL Low-Power and Reset Control Register (PLPRCR)
See Table 8-11 for bit descriptions.
0x2F C2881
Reset Status Register (RSR)
See Table 7-3 for bit descriptions.
0x2F C28C1
Change of Lock Interrupt Register (COLIR)
See Table 8-12 for bit descriptions.
0x2F C2901
IRAMSTBY Control Register (VSRCR)
See Table 8-13 for bit descriptions.
0x2F C294–0x2F C2FC Reserved
System Integration Timer Keys
0x2F C300
Time Base Status and Control Key (TBSCRK)
See Table 8-8 for bit descriptions.
0x2F C304
Time Base Reference 0 Key (TBREF0K)
See Table 8-8 for bit descriptions.
0x2F C308
Time Base Reference 1 Key (TBREF1K)
See Table 8-8 for bit descriptions.
0x2F C30C
Time Base and Decrementor Key (TBK)
See Table 8-8 for bit descriptions.
0x2F C310–0x2F C31C Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
5-5
Unified System Interface Unit (USIU) Overview
Table 5-1. USIU Address Map (continued)
Address
Register
0x2F C320
Real-Time Clock Status and Control Key (RTCSCK)
See Table 8-8 for bit descriptions.
0x2F C324
Real-Time Clock Key (RTCK)
See Table 8-8 for bit descriptions.
0x2F C328
Real-Time Alarm Seconds Key (RTSECK)
See Table 8-8 for bit descriptions.
0x2F C32C
Real-Time Alarm Key (RTCALK)
See Table 8-8 for bit descriptions.
0x2F C330–0x2F C33C Reserved
0x2F C340
PIT Status and Control Key (PISCRIK)
See Table 8-8 for bit descriptions.
0x2F C344
PIT Count Key (PITCK)
See Table 8-8 for bit descriptions.
0x2F C348–0x2F C37C Reserved
Clocks and Reset Keys
0x2F C380
System Clock Control Key (SCCRK)
See Table 8-8 for bit descriptions.
0x2F C384
PLL Low-Power and Reset Control Register Key (PLPRCRK)
See Table 8-8 for bit descriptions.
0x2F C388
Reset Status Register Key (RSRK)
See Table 8-8 for bit descriptions.
0x2F C38C–0x2F
C3FC
1
5.1.1
Reserved
16-bit register.
USIU Special-Purpose Registers
Table 5-2 lists the MPC561/MPC563 special purpose registers (SPR) used by the USIU. These registers
reside in an alternate internal memory space that can only be accessed with the mtspr and mfspr
instructions, or from an external master (refer to Section 6.1.2, “External Master Modes,” for details). All
registers are 32 bits wide.
NOTE
RCPU special purpose registers cannot be accessed by an external master.
Only SPRs in the USIU can be accessed by an external master.
MPC561/MPC563 Reference Manual, Rev. 1.2
5-6
Freescale Semiconductor
Unified System Interface Unit (USIU) Overview
Table 5-2. USIU Special-Purpose Registers
Internal
Address[0:31]
1
Decimal Address
spr[5:9]:spr[0:4]1
Register
0x2C00
Decrementer (DEC).
See Section 3.9.5, “Decrementer Register
(DEC),” for more information.
22
0x1880
Time Base Lower — Read (TBL).
See Section 6.2.2.4.2, “Time Base SPRs (TB),”
for bit descriptions.
268
0x1A80
Time Base Upper — Read (TBU).
See Section 6.2.2.4.2, “Time Base SPRs (TB),”
for bit descriptions.
269
0x3880
Time Base Lower — Write (TBL).
SeeSee Section 6.2.2.4.2, “Time Base SPRs
(TB),” for bit descriptions.
284
0x3A80
Time Base Upper — Write (TBU).
See Section 6.2.2.4.2, “Time Base SPRs (TB),”
for bit descriptions.
285
0x3D30
Internal Memory Mapping Register (IMMR).
See Table 6-12 for bit descriptions.
638
Bits [0:17] and [28:31] are all 0.
Table 5-3 shows the MPC561/MPC563 address format for special purpose register access. For an external
master, accessing an MPC500 SPR, address bits [0:17] and [28:31] are compared to zeros to confirm that
an SPR access is valid. See Section 6.1.2.1, “Operation in External Master Modes,” for more details.
.
Table 5-3. Hex Address Format for SPR Cycles
A[0:17]
A[18:22]
A[23:27]
A[28:31]
0
spr5:9
spr0:4
0
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
5-7
Unified System Interface Unit (USIU) Overview
MPC561/MPC563 Reference Manual, Rev. 1.2
5-8
Freescale Semiconductor
Chapter 6
System Configuration and Protection
The MPC561/MPC563 incorporateDMAes many system functions that normally must be provided in
external circuits. In addition, it is designed to provide maximum system safeguards against hardware and
software faults. The system configuration and protection sub-module provides the following features:
• System Configuration (Section 6.1.1, “System Configuration”)—The USIU allows the
configuration of the system according to the particular requirements. The functions include control
of show cycle operation, pin multiplexing, and internal memory map location. System
configuration also includes a register containing part and mask number constants to identify the
part in software.
• External Master Modes Support (Section 6.1.2, “External Master Modes”)—External master
modes are special modes of operation that allow an alternate master on the external bus to access
the internal modules for debugging and backup purposes.
• General-Purpose I/O (Section 6.1.3, “USIU General-Purpose I/O ”)—The USIU provides 64 pins
for general-purpose I/O. The SGPIO pins are multiplexed with the address and data pins.
• Enhanced Interrupt Controller (Section 6.1.4, “Enhanced Interrupt Controller”)—The interrupt
controller receives interrupt requests from a number of internal and external sources and directs
them on a single interrupt-request line to the RCPU.
• Bus Monitor (Section 6.1.5, “Hardware Bus Monitor”)—The SIU provides a bus monitor to watch
internal to external accesses. It monitors the transfer acknowledge (TA) response time for internal
to external transfers. A transfer error acknowledge (TEA) is asserted if the TA response limit is
exceeded. This function can be disabled.
• Decrementer (Section 6.1.6, “Decrementer (DEC)”)—The DEC is a 32-bit decrementing counter
defined by the MPC500 architecture to provide a decrementer interrupt. This binary counter is
clocked by the same frequency as the time base (also defined by the MPC561/MPC563
architecture). The period for the DEC when driven by a 4-MHz oscillator can be up to 4295
seconds, which is approximately 71.6 minutes. Refer to Table 6-6.
• Time Base Counter (Section 6.1.7, “Time Base (TB)”)—The TB is a 64-bit counter defined by the
MPC500 architecture to provide a time base reference for the operating system or application
software. The TB has four independent reference registers that can generate a maskable interrupt
when the time-base counter reaches the value programmed in one of the four reference registers.
The associated bit in the TB status register will be set for the reference register which generated
the interrupt.
• Real-Time Clock (Section 6.1.8, “Real-Time Clock (RTC)”)—The RTC is used to provide
time-of-day information to the operating system or application software. It is composed of a 45-bit
counter and an alarm register. A maskable interrupt is generated when the counter reaches the value
programmed in the alarm register. The RTC is clocked by the same clock as the PIT.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-1
System Configuration and Protection
•
•
•
•
Periodic Interrupt Timer (Section 6.1.9, “Periodic Interrupt Timer (PIT)”)—The SIU provides a
timer to generate periodic interrupts for use with a real-time operating system or the application
software. The PIT provides a period from 1 µs to 4 seconds with a four-MHz crystal or 200 ns to
0.8 ms with a 20-MHz crystal. The PIT function can be disabled.
Software Watchdog Timer (Section 6.1.10, “Software Watchdog Timer (SWT)”)—The SWT
asserts a reset or non-maskable interrupt, as selected by the system protection control register
(SYPCR), if the software fails to service the SWT for a designated period of time (e.g., because the
software is trapped in a loop or lost). After a system reset, this function is enabled with a maximum
time-out period and asserts a system reset if the time-out is reached. The SWT can be disabled or
its time-out period can be changed in the SYPCR. Once the SYPCR is written, it cannot be written
again until a system reset.
Freeze Support (Section 6.1.11, “Freeze Operation”)—The SIU allows control of whether the
SWT, PIT, TB, DEC, and RTC should continue to run during freeze mode.
Low Power Stop (Section 6.1.12, “Low Power Stop Operation”)—In low power modes, specific
timers are frozen but others are not.
Figure 6-1 shows a block diagram of the system configuration and protection logic.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-2
Freescale Semiconductor
System Configuration and Protection
Module
Configuration
Internal and
External Interrupt Requests
TA
Interrupt
Controller
Bus
Monitor
TS
Clock
TEA
Periodic Interrupt
Timer
Interrupt
Software
Watchdog Timer
Interrupt or
System Reset
Decrementer
Decrementer
Exception
Time Base Counter
Interrupt
Real-Time
Clock
Interrupt
Figure 6-1. System Configuration and Protection Logic
6.1
System Configuration and Protection Features
The system configuration and protection sub-module provides features described in the following sections.
6.1.1
System Configuration
The SIU allows the configuration of the system according to the particular requirements. The functions
include control of show cycle operation, pin multiplexing, and internal memory map location. System
configuration also includes a register containing part and mask number constants to identify the part in
software.
System configuration registers include the SIU module configuration register (SIUMCR), and the internal
memory mapping register (IMMR). Refer to Section 6.2.2, “System Configuration and Protection
Registers,” for register diagrams and bit descriptions.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-3
System Configuration and Protection
6.1.1.1
USIU Pin Multiplexing
Some of the functions defined in the various sections of the USIU (external bus interface, memory
controller, and general-purpose I/O) share pins. Table 6-1 summarizes how the pin functions of these
multiplexed pins are assigned.
.
Table 6-1. USIU Pin Multiplexing Control
Pin Name
Multiplexing Controlled by:
IRQ0 / SGPIOC0 / MDO4
IRQ1 / RSV / SGPIOC1
IRQ2 / CR / SGPIOC2 / MTS
IRQ3 / KR / RETRY / SGPIOC3
IRQ4 / AT2 / SGPIOC4
IRQ5 / SGPIOC5 / MODCK1
IRQ6 / MODCK2
IRQ7 / MODCK3
At Power-On Reset: MODCK[1:3]
Otherwise: Programmed in SIUMCR
Note:MDO4 is controlled by READI enable.
SGPIOC6 / FRZ / PTR
SGPIOC7 / IRQOUT / LWP0
BG / VF0 / LWP1
BR / VF1 / IWP2
BB / VF2 / IWP3
IWP[0:1] / VFLS[0:1]
BI / STS
WE[0:3] / BE[0:3] / AT[0:3]
TDI/DSDI / MDI0
TCK / DSCK / MCKI
TDO / DSDO / MDO0
Programmed in SIUMCR and Hard Reset Configuration
Note:MDIO, MCKI, and MDO0 are controlled by READI enable.
DATA[0:31] / SGPIOD[0:31]
ADDR[8:31] / SGPIOA[8:31]
Programmed in SIUMCR
RSTCONF /TEXP
6.1.1.2
At Power-On Reset: RSTCONF
Otherwise: Programmed in SIUMCR
Arbitration Support
Two bits in the SIUMCR control USIU bus arbitration. The external arbitration (EARB) bit determines
whether arbitration is performed internally or externally. If EARB is cleared (internal arbitration), the
external arbitration request priority (EARP) bit determines the priority of an external master’s arbitration
request. The operation of the internal arbiter is described in Section 9.5.7.4, “Internal Bus Arbiter.”
6.1.2
External Master Modes
External master modes are special modes of operation that allow an alternative master on the external bus
to access the internal modules for debugging and backup purposes. They provide access to the internal
buses (U-bus and L-bus) and to the intermodule bus (IMB3).
There are two external master modes:
•
Peripheral mode (enabled by setting PRPM in the external master control (EMCR) register) uses a
special slave mechanism that shuts down the RCPU and an alternative master on the external bus
can perform accesses to any internal bus slave.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-4
Freescale Semiconductor
System Configuration and Protection
•
Slave mode (enabled by setting EMCR[SLVM] and clearing EMCR[PRPM]) enables an external
master to access any internal bus slave while the RCPU is fully operational.
Both modes can be enabled and disabled by software. In addition, peripheral mode can be selected from
reset.
The internal bus is not capable of providing priority between internal RCPU accesses and external master
accesses. If the bandwidth of external master accesses is large, it is recommended that the system force
gaps between external master accesses in order to avoid suspension of internal RCPU activity.
The MPC561/MPC563 does not support burst accesses from an external master; only single accesses of 8,
16, or 32 bits can be performed. The MPC561/MPC563 asserts burst inhibit (BI) on any attempt to initiate
a burst access to internal memory.
The MPC561/MPC563 provides memory controller services for external master accesses (single and
burst) to external memories. See Chapter 10, “Memory Controller,” for details.
6.1.2.1
Operation in External Master Modes
The external master modes are controlled by the EMCR register, which contains the internal bus attributes.
The default attributes in the EMCR allow an external master to configure the EMCR with the required
attributes and access internal registers. The external master must be granted external bus ownership in
order to initiate the external master access. The SIU compares the address on the external bus to the
allocated internal address space. If the address is within the internal space, the access is performed with
the internal bus. The internal address space is determined according to IMMR[ISB] (see Section 6.2.2.1.2,
“Internal Memory Map Register (IMMR),” for details). The external master access is terminated by the
TA, TEA, or RETRY signal on the external bus.
A deadlock situation might occur if an internal-to-external access is attempted on the internal bus while an
external master access is initiated on the external bus. In this case, the SIU will assert RETRY on the
external bus in order to relinquish and retry the external access until the internal access is completed. The
internal bus will deny other internal accesses for the next eight clocks in order to complete the pending
accesses and prevent additional internal accesses from being initiated on the internal bus. The SIU will
also mask internal accesses to support consecutive external accesses if the delay between the external
accesses is less than four clocks. The external master access and retry timings are described in
Section 9.5.12, “Bus Operation in External Master Modes.”
The external master may access the internal MPC561/MPC563 special registers that are located outside
the RCPU. To access one of these special purpose registers (see Section 5.1.1, “USIU Special-Purpose
Registers”), EMCR[CONT] must be set and EMCR[SUPU] must be cleared. The external master can then
access the special register when it is provided the address according to the MPC561/MPC563 address map.
Only the first external master access that follows EMCR setting will be assigned to the special register
map; any subsequent accesses will be directed to the normal address map. This is done in order to enable
access to the EMCR again after the required MPC561/MPC563 special register access.
Peripheral mode does not require external bus arbitration between the external master and the internal
RCPU, since the internal RCPU is disabled. The BR and BB signals should be connected to ground, and
the internal bus arbitration should be selected in order to prevent the “slave” MPC561/MPC563 from
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-5
System Configuration and Protection
occupying the external bus. Internal bus arbitration is selected by clearing SIUMCR[EARB] (see
Section 6.2.2.1.1, “SIU Module Configuration Register (SIUMCR)”).
6.1.2.2
Address Decoding for External Accesses
During an external master access, the USIU compares the external address with the internal address block
to determine if MPC561/MPC563 operation is required. Since only 24 of the 32 internal address bits are
available on the external bus, the USIU assigns zeros to the most significant address bits (ADDR[0:7]).
The address compare sequence can be summarized as follows:
• Normal external access. If EMCR[CONT] is cleared, the address is compared to the internal
address map. Refer to Section 6.2.2.1.3, “External Master Control Register (EMCR)”.
— MPC561/MPC563 special register external access. If EMCR[CONT] is set by the previous
external master access, the address is compared to the MPC561/MPC563 special address
range. See Section 5.1.1, “USIU Special-Purpose Registers,” for a list of the SPRs in the USIU.
— Memory controller external access. If the first two comparisons do not match, the internal
memory controller determines whether the address matches an address assigned to one of the
regions. If it finds a match, the memory controller generates the appropriate chip select and
attribute accordingly
When trying to fetch an MPC561/MPC563 special register from an external master, the address might be
aliased to one of the external devices on the external bus. If this device is selected by the
MPC561/MPC563 internal memory controller, this aliasing does not occur since the chip select is
disabled. If the device has its own address decoding or is being selected by external logic, this case is
resolved.
NOTE
This section does not address slave accesses to internal resources. For
internal resources, the accesses compare against ADDR[8:9] = ISB[1:2].
ISB0 must be cleared.
6.1.3
USIU General-Purpose I/O
The USIU provides 64 general-purpose I/O (SGPIO) pins (See Table 6-2). The SGPIO pins are
multiplexed with the address and data pins. In single-chip mode, where communicating with external
devices is not required, all 64 SGPIO pins can be used. In multiple-chip mode, only eight SGPIO pins are
available. Another configuration allows the use of the address bus for instruction show cycles while the
data bus is dedicated to SGPIO functionality. The functionality of these pins is assigned by the single-chip
(SC) bit in the SIUMCR. (See Section 6.2.2.1.1, “SIU Module Configuration Register (SIUMCR).”)
SGPIO pins are grouped as follows:
• Six groups of eight pins each, whose direction is set uniformly for the whole group
• 16 single pins whose direction is set separately for each pin
Table 6-2 describes the SGPIO signals, and all available configurations. The SGPIO registers are
described in Section 6.2.2.5, “General-Purpose I/O Registers.”
MPC561/MPC563 Reference Manual, Rev. 1.2
6-6
Freescale Semiconductor
System Configuration and Protection
Table 6-2. SGPIO Configuration
SGPIO
Group Name
1
Individual
Pin Control
Direction
Control
Available
Available
Available
Available
When SC = 10
When SC = 00 When SC = 01
When SC = 11
(Single-Chip
(32-bit Port
(16-bit Port
(Single-Chip
Mode with
Size Mode)
Size Mode)
Mode)
Trace)
SGPIOD[0:7]
GDDR0
X
X
SGPIOD[8:15]
GDDR1
X
X
SGPIOD[16:23]
GDDR2
X
X
X
X
X
X
SGPIOD[24:31]
X
SDDRD[23:31]
SGPIOC[0:7]1
X
SDDRC[0:7]
SGPIOA[8:15]
GDDR3
X
SGPIOA[16:23]
GDDR4
X
SGPIOA[24:31]
GDDR5
X
SGPIOC[0:7] is selected according to GPC and MLRC fields in SIUMCR. See Section 6.2.2.1.1, “SIU Module
Configuration Register (SIUMCR).”
Figure 6-2 illustrates the functionality of the SGPIO.
Read Path
Internal
Bus
Read
GPIO
Read
Register
GPIO
Write
Register
Write
Write Path
OE
Clock
Write
SGPIO
Pad
Read
Path of Write Operation
Path of Read Operation
SGPIO Circuitry
Figure 6-2. Circuit Paths of Reading and Writing to SGPIO
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-7
System Configuration and Protection
6.1.4
Enhanced Interrupt Controller
6.1.4.1
•
•
•
•
•
•
Key Features
Significant interrupt latency reduction from that of the MPC555.
Simplified interrupt structure
Up to 48 different interrupt requests
Splitting of single external interrupt vector into up to 48 vectors, one for each source
Automatic lower priority requests masking
Full backward compatibility with MPC555/MPC556 (enhanced mode is software programmable.)
6.1.4.2
Interrupt Configuration
An overview of the MPC561/MPC563 interrupt structure is shown in Figure 6-3. The interrupt controller
receives interrupts from USIU internal sources, such as PIT, RTC, from the UIMB module (which has its
own interrupt controller) or from the IMB3 bus (directly from IMB modules) and from external pins
IRQ[0:7].
MPC561/MPC563 Reference Manual, Rev. 1.2
6-8
Freescale Semiconductor
System Configuration and Protection
DEC_IRQ to RCPU
SWT
I0
Level 7
U-bus INT Levels [0:7]
Level 4
Level 3
Level 2
Level 1
Level 0
8
I6
I5
I4
I3
I2
I1
I0
NMI to RCPU
Wake up from
low-power mode
16
IRQOUT
MUX
UIMB
Timers,
Change
of Lock
SIUMCR
[EICEN, LPMASKEN]
LPMASKEN
IMB3
Levels[0:7]
ilbs[0:1]
IMBIRQ
Sequencer
Enhanced Interrupt Controller
Internal
Bus
IREQ to RCPU
EICEN
48
SIVEC
Level7
Level5
imb_irq [0:6]
imb_irq [0:6] Level[0:6]
Level 6
I7
NMI
GEN
Regular Interrupt Controller
EDGE
DET
IRQ[0:7]
Selector
DEC
6
Offset in
BBC/IMPU
branch table
USIU
Figure 6-3. MPC561/MPC563 Interrupt Structure
If programmed to generate an interrupt, the SWT and external pin IRQ0 always generate an NMI,
non-maskable interrupt to the RCPU.
NOTE
The RCPU takes the system reset exception when an NMI is asserted, the
external interrupt exception for any other asserted interrupt request, and the
decrementer exception when the decrementer MSB changes from 0 to 1.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-9
System Configuration and Protection
The decrementer interrupt request is not a part of the interrupt controller. Each one of the external pins
IRQ[1:7] has its own dedicated assigned priority level. IRQ0 is also mapped, but it should be used only as
a status bit indicating that IRQ0 was asserted and generated NMI interrupt. There are eight additional
interrupt priority levels. Each one of the SIU internal interrupt sources, or any of the peripheral module
interrupt sources can be assigned by software to any one of the eight interrupt priority levels. Thus, a very
flexible interrupt scheme is implemented. The interrupt request signal generated by the interrupt controller
is driven to the RPCU core and to the IRQOUT pin (optionally). This pin may be used in peripheral mode,
when the RCPU is disabled, and the internal modules are accessed externally. The IMB interrupts are
controlled by the UIMB. The IMB provides 32 interrupt levels, and any interrupt source could be
configured to any IMB interrupt level. The UIMB contains a 32-bit register that holds the IMB interrupt
requests, and maps them to the USIU eight interrupt levels.
NOTE
If one interrupt level was configured to more than one interrupt source, the
software should read the UIPEND register in the UIMB module, and the
particular status bits in order to identify which interrupt was asserted.
The interrupt controller may be programmed to operate in two modes—a regular mode or an enhanced
mode.
6.1.4.3
Regular Interrupt Controller Operation (MPC555/MPC556-Compatible
Mode)
In regular operation mode (default setting) the interrupt controller receives interrupt requests from internal
sources, such as timers, PLL lock detector, IMB modules and from external pins IRQ[0:7]. All the internal
interrupt sources may be programmed to drive one or more of eight U-bus interrupt level lines while the
RCPU, upon receiving an interrupt request, has to read the USIU and UIMB status register in order to
determine the interrupt source.
The SIVEC register contains an 8-bit code representing the unmasked interrupt request which has the
highest priority level. The priority between all interrupt sources for the regular interrupt controller
operation is shown in Table 6-3.
Table 6-3. Priority of Interrupt Sources—Regular Operation
Number
Priority
Level
Interrupt Source
Description
Offset in Branch
Table (Hex)
SIVEC Interrupt Code1
0
Highest
EXT_IRQ0
0x0000
00000000
1
—
Level 0
0x0008
00000100
2
—
EXT_IRQ1
0x0010
00001000
3
—
Level 1
0x0018
00001100
4
—
EXT_IRQ2
0x0020
00010000
5
—
Level 2
0x0028
00010100
6
—
EXT_IRQ3
0x0030
00011000
7
—
Level 3
0x0038
00011100
MPC561/MPC563 Reference Manual, Rev. 1.2
6-10
Freescale Semiconductor
System Configuration and Protection
Table 6-3. Priority of Interrupt Sources—Regular Operation
1
Number
Priority
Level
Interrupt Source
Description
Offset in Branch
Table (Hex)
SIVEC Interrupt Code1
8
—
EXT_IRQ4
0x0040
00100000
9
—
Level 4
0x0048
00100100
10
—
EXT_IRQ5
0x0050
00101000
11
—
Level 5
0x0058
00101100
12
—
EXT_IRQ6
0x0060
00110000
13
—
Level 6
0x0068
00110100
14
—
EXT_IRQ7
0x0070
00111000
15
Lowest
Level 7
0x0078
00111100
This is the value in the 8 most significant bits of the SIVEC register (SIVEC[25:31]).
Each interrupt request from external lines and from USIU internal interrupt sources in the case of its
assertion will set a corresponding bit in SIPEND register. The individual SIPEND bits may be masked by
clearing an appropriate bit in SIMASK register.
6.1.4.4
Enhanced Interrupt Controller Operation
The enhanced interrupt controller operation may be turned on by setting the EICEN control bit in the
SIUMCR register. In this mode the 32 IMB interrupt levels will be latched by USIU using eight IMB
interrupt lines and two lines of ilbs via the time multiplexing scheme defined by the UIMB module. In
addition to the IMB interrupt sources the external interrupts and timer interrupts are available in the same
way as in the regular scheme. In this mode, the UIMB module does not drive U-bus interrupt level lines.
Each interrupt request will set a corresponding bit in SIPEND2 or SIPEND3 registers. SIPEND2 an
SIPEND3 may be masked by clearing an appropriate bit in SIMASK2 or SIMASK3 registers.
The priority logic is provided in order to determine the highest unmasked interrupt request, and interrupt
code is generated in the SIVEC register. See Table 6-4.
NOTE
If the enhanced interrupt controller is enabled, a delay is required prior to
re-enabling interrupts. Before clearing an interrupt related register, clear the
MSR[EE] bit (EE = 0). Expect a vector offset of 0x0 if an interrupt is cleared
or disabled while MSR[EE] = 1. This vector should be handled as if no
interrupt has occured, that is, perform an rfi instruction. After clearing an
interrupt source, sufficient time must elapse before re-enabling the
MSR[EE] bit (EE = 1). This time should take longer than the time needed
for a load of the same register that was just cleared. To guarantee enough
time, include this load instruction before the instruction that sets MSR[EE].
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-11
System Configuration and Protection
Table 6-4. Priority of Interrupt Sources—Enhanced Operation
Number
Priority Level
Interrupt Source
Description
Offset in Branch
,
Table (Hex)1 2
SIVEC Interrupt Code3
0
Highest
(see note above)4
0x0000
00000000
1
—
Level 0
0x0008
00000100
2
—
IMB_IRQ 0
0x0010
00001000
3
—
IMB_IRQ 1
0x0018
00001100
4
—
IMB_IRQ 2
0x0020
00010000
5
—
IMB_IRQ 3
0x0028
00010100
6
—
EXT_IRQ2
0x0030
00011000
7
—
Level 1
0x0038
00011100
8
—
IMB_IRQ 4
0x0040
00100000
9
—
IMB_IRQ 5
0x0048
00100100
10
—
IMB_IRQ 6
0x0050
00101000
11
—
IMB_IRQ 7
0x0058
00101100
12
—
EXT_IRQ2
0x0060
00110000
13
—
Level 2
0x0068
00110100
14
—
IMB_IRQ 8
0x0070
00111000
15
—
IMB_IRQ 9
0x0078
00111100
16
—
IMB_IRQ 10
0x0080
01000000
17
—
IMB_IRQ 11
0x0088
01000100
18
—
EXT_IRQ3
0x0090
01001000
19
—
Level 3
0x0098
01001100
20
—
IMB_IRQ 12
0x00A0
01010000
21
—
IMB_IRQ 13
0x00A8
01010100
22
—
IMB_IRQ 14
0x00B0
01011000
23
—
IMB_IRQ 15
0x00B8
01011100
24
—
EXT_IRQ4
0x00C0
01100000
25
—
Level 4
0x00C8
01100100
26
—
IMB_IRQ 16
0x00D0
01101000
27
—
IMB_IRQ 17
0x00D8
01101100
28
—
IMB_IRQ 18
0x00E0
01110000
29
—
IMB_IRQ 19
0x00E8
01110100
30
—
EXT_IRQ5
0x00F0
01111000
31
—
Level 5
0x00F8
01111100
MPC561/MPC563 Reference Manual, Rev. 1.2
6-12
Freescale Semiconductor
System Configuration and Protection
Table 6-4. Priority of Interrupt Sources—Enhanced Operation (continued)
Number
Priority Level
Interrupt Source
Description
Offset in Branch
,
Table (Hex)1 2
SIVEC Interrupt Code3
32
—
IMB_IRQ 20
0x0100
10000000
33
—
IMB_IRQ 21
0x0108
10000100
34
—
IMB_IRQ 22
0x0110
10001000
35
—
IMB_IRQ 23
0x0118
10001100
36
—
EXT_IRQ6
0x0120
10010000
37
—
Level 6
0x0128
10010100
38
—
IMB_IRQ 24
0x0130
10011000
39
—
IMB_IRQ 25
0x0138
10011100
40
—
IMB_IRQ 26
0x0140
10100000
41
—
IMB_IRQ 27
0x0148
10100100
42
—
EXT_IRQ7
0x0150
10101000
43
—
Level 7
0x0158
10101100
44
—
IMB_IRQ 28
0x0160
10110000
45
—
IMB_IRQ 29
0x0168
10110100
46
—
IMB_IRQ 30
0x0170
10111000
47
Lowest
IMB_IRQ 31
0x0178
10111100
1
The branch table feature can be used only if the BBCMCR[EIR] is set.
This offset is added to the table base address from the EIBDR register.
3 This is the value in the 8 most significant bits of the SIVEC register.
4 This vector is reserved and normally is not generated. It may be generated, if any other interrupt source disappears,
before being acknowleged by the RCPU as a result of any change in the interrupt scheme, module stopping, masking
interrupt sources in a module by application software while interrupts are enabled in the RCPU by setting MSR[EE].
2
The value of the SIVEC register is supplied internally to the BBC module and can be used as an offset to
the branch table start address for the external interrupt relocation feature. Thus a fast way to a specific
interrupt source routine is provided without software overhead. The BBCMCR (see Section 4.6.2.1, “BBC
Module Configuration Register (BBCMCR)”) and EIBADR (see Section 4.6.2.5, “External Interrupt
Relocation Table Base Address Register (EIBADR)”) registers must be programmed to enable this feature
in the BBC. Additionally, the SIPEND2 and SIPEND3 registers contain the information about all the
interrupt requests that are asserted at a given time, so that software can always read them.
NOTE
When the enhanced interrupt controller is enabled the SIPEND and
SIMASK registers are not used.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-13
System Configuration and Protection
6.1.4.4.1
Lower Priority Request Masking
This feature (if enabled) simplifies the masking of lower priority interrupt requests when a request of
certain priority is in service in applications that require interrupt nesting. The highest (pending) request is
also masked by itself. The masking is accomplished in the following way.
Upon asserting an interrupt request the BBC generates an acknowledge signal to notify the interrupt
controller that the request and the branch table offset have been latched. The interrupt controller then sets
a bit in the SISR register (interrupt in-service register), according to the asserted request. All other requests
whose priority is lower than or equal to the one that is currently in-service, become masked. The mask
remains set until the SISR bit is cleared by software (by the interrupt handler routine), writing a ‘1’ value
to the corresponding bit. The lower priority request masking diagram is presented in Figure 6-4.
The lower priority request masking feature is disabled by HRESET and it may be enabled by setting the
LPMASK_EN bit in the SIUMCR register.
NOTE
In the regular mode of the interrupt controller the lower priority request
masking feature is not available.
The feature must be activated only together with exception table relocation in the BBC module.
From bit i - 1
Enable
control bit
(LPMASK_EN)
To SIVEC
generation
SIPEND [i]
To RCPU
External
interrupt
request
generation
(OR between
all the bits)
SIMASK [i]
IMPU
acknowledge
Reset by
software
Set
SISR[i]
Reset
To bit i + 1
Figure 6-4. Lower Priority Request Masking—One Bit Diagram
6.1.4.4.2
Backward Compatibility with MPC555/MPC556
The enhanced interrupt controller is a feature that may be enabled according to a user’s application using
the EICEN control bit in SIUMCR register, which can be set and cleared at any time by software. If the bit
is cleared, the default interrupt controller operation is available, as described in Section 6.1.4.3, “Regular
Interrupt Controller Operation (MPC555/MPC556-Compatible Mode).” The regular operation is fully
compatible with the interrupt controller already implemented in MPC555/MPC556.
Figure 6-5 illustrates the interrupt controller functionality in the MPC561/MPC563.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-14
Freescale Semiconductor
System Configuration and Protection
IRQ
...... ...... ...... ......
8
SIEL
External
SIMASK
8
Synchronizer
U-bus INT
Levels[0:7]
SIPEND
Wake up from
low-power mode
16
......
From IMB:
ilbs[0:1]
5
SISR3
S
I
V
E
C
5
(6 from 48)
(Enables branch
to the highest priority
interrupt routine)
SISR2
48
Encoder
Enhanced Interrupt
Controller Enabled
32
Sequencer
IMB IRQ
8
SIPEND2 SIPEND3
IRQ[0:7]
SIMASK2 SIMASK3
Priority
Interrupt Vector
(offset to branch
table – to BBC)
0
MUX
1
Interrupt Request
(to RCPU and IRQOUT pad)
Figure 6-5. MPC561/MPC563 Interrupt Controller Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-15
System Configuration and Protection
6.1.4.5
Interrupt Overhead Estimation for Enhanced Interrupt Controller Mode
The interrupt overhead consists of two main parts:
• Storage of general and special purpose registers
• Recognition of the interrupt source
The interrupt overhead can increase latency, and decrease the overall system performance. The overhead
of register saving time can be reduced by improving the operating system. The number of registers that
should be saved can be reduced if each interrupt event has its own interrupt vector. This solution solves
the interrupt source recognition overhead. Table 6-5 below illustrates the improvements.
Only registers required for the recognition routine are considered to be saved in the calculations below.
Recognition of module internal events/channels is out of the scope of the calculations. See also the typical
interrupt handler flowchart in Figure 6-6.
Table 6-5. Interrupt Latency Estimation for Three Typical Cases
MPC561/MPC563
Architecture Without Using
SIVEC
MPC561/MPC563
Architecture Using
Enhanced Interrupt
Controller Features
MPC561/MPC563 Architecture
Using SIVEC
Operation
Details
Interrupt propagation from
request module to RCPU —
8 clocks
Store of some GPR and
SPR—10 clocks
Read SIPEND—4 clocks
Read SIMASK—4 clocks
SIPEND data processing —
20 clocks
(find first set, access to LUT in
the Flash, branches)
Read UIPEND—4 clocks
UIPEND data processing—20
clocks
(find first set, access to LUT in
the Flash, branches)
Interrupt propagation from
request module to RCPU —
8 clocks
Store of some GPR and SPR
—10 clocks
Read SIVEC—4 clocks
Branch to routine—10 clocks
Read UIPEND—4 clocks
UIPEND data processing —
20 clocks
(find first set, access to LUT in
the Flash, branches)
Notes:
If there is a need to enable
nesting of interrupts during
source recognition procedure,
at least 30 clocks should be
added to the interrupt latency
estimation
To use this feature in compressed —
mode some undetermined
latency is added to make a
branch to compressed address of
the routine. This latency is
dependant on how the user code
is implemented.
Total:
At Least 70-80 Clocks
At Least 50-60 Clocks
Interrupt propagation from
request module to RCPU —
6 clocks
Store of some GPR and
SPR—10 clocks
Only one branch is executed to
reach the interrupt handler
routine of the device requesting
interrupt servicing—2 clocks
20 Clocks
NOTE
Compiler and bus collision overhead are not included in the calculations.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-16
Freescale Semiconductor
System Configuration and Protection
.
Start
Saving the CPU
context
Masking lower
priority requests
Enabling
Interrupt
Handler body
Clearing interrupt
source
Disabling interrupt
Clearing in-service bit
Clearing mask
Restoring the CPU
context
Flow without lower priority
masking enabled
Flow with lower priority
masking enabled
RFI
Figure 6-6. Typical Interrupt Handler Routine
6.1.5
Hardware Bus Monitor
The bus monitor ensures that each bus cycle is terminated within a reasonable period of time. The USIU
provides a bus monitor option to monitor internal to external bus accesses on the external bus. The monitor
counts from transfer start to transfer acknowledge and from transfer acknowledge to transfer acknowledge
within bursts. If the monitor times out, transfer error acknowledge (TEA) is asserted internally by the
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-17
System Configuration and Protection
MPC561/MPC563, and RCPU access is terminated with a data error, causing a machine check state or
exception.
The bus monitor timing bit in the system protection control register (SYPCR[BMT]) defines the bus
monitor time-out period. The programmability of the time-out allows for variation in system peripheral
response time. The timing mechanism is clocked by the external bus clock divided by eight. The maximum
value is 2040 system clock cycles.
SYPCR[BME] enables or disables the bus monitor. But regardless of the state of this bit the bus monitor
is always enabled when freeze is asserted in debug mode.
6.1.6
Decrementer (DEC)
The decrementer (DEC) is a 32-bit decrementing counter defined by the MPC561/MPC563 architecture
to provide a decrementer interrupt. This binary counter is clocked by the same frequency as the time base
(also defined by the MPC500 architecture). The operation of the time base and decrementer are therefore
coherent. The DEC is clocked by the TMBCLK clock. The decrementer period is computed as follows:
TDEC =
232
FTMBCLK
The state of the DEC is not affected by any resets and should be initialized by software. The DEC runs
continuously after power-up once the time base is enabled by setting the TBE bit of the TBSCR (see
Table 6-18) (unless the clock module is programmed to turn off the clock). The decrementer continues
counting while reset is asserted.
Reading from the decrementer has no effect on the counter value. Writing to the decrementer replaces the
value in the decrementer with the value in the GPR.
Whenever bit 0 (the MSB) of the decrementer changes from zero to one, a decrementer exception occurs.
If software alters the decrementer such that the content of bit 0 is changed to a value of 1, a decrementer
exception occurs.
A decrementer exception causes a decrementer interrupt request to be pending in the RCPU. When the
decrementer exception is taken, the decrementer interrupt request is automatically cleared.
Table 6-6 illustrates some of the periods available for the decrementer, assuming a 4-MHz or 20-MHz
crystal, and TBS = 0 which selects TMBCLK division to 4.
NOTE
Time base must be enabled to use the decrementer. See Section 6.2.2.4.4,
“Time Base Control and Status Register (TBSCR),” for more information.
Table 6-6. Decrementer Time-Out Periods
Count Value
Time-Out @ 4 MHz
Time-Out @ 20 MHz
0
1.0 µs
0.2 µs
9
10 µs
2.0 µs
MPC561/MPC563 Reference Manual, Rev. 1.2
6-18
Freescale Semiconductor
System Configuration and Protection
Table 6-6. Decrementer Time-Out Periods (continued)
Count Value
Time-Out @ 4 MHz
Time-Out @ 20 MHz
99
100 µs
20 µs
999
1.0 ms
200 µs
9999
10.0 ms
2 ms
999999
1.0 s
200 ms
9999999
10.0 s
2.0 s
99999999
100.0 s
20 s
999999999
1000 s
200 s
(hex) FFFFFFFF
4295 s
859 s
Refer to Section 3.9.5, “Decrementer Register (DEC),” for more information.
6.1.7
Time Base (TB)
The time base (TB) is a 64-bit free-running binary counter defined by the MPC500 architecture. The TB
has two independent reference registers which can generate a maskable interrupt when the time base
counter reaches the value programmed in one of the two reference registers. The period of the TB depends
on the driving frequency. The TB is clocked by the TMBCLK clock. The period for the TB is:
64
2
T TB = -----------------------------F TMBCLK
The state of TB is not affected by any resets and should be initialized by software. Reads and writes of the
TB are restricted to special instructions. Separate special-purpose registers are defined in the MPC500
architecture for reading and writing the TB. For the MPC561/MPC563 implementation, it is not possible
to read or write the entire TB in a single instruction. Therefore, the mttb and mftb instructions are used to
move the lower half of the time base (TBL) while the mttbu and mftbu instructions are used to move the
upper half (TBU).
Two reference registers are associated with the time base: TBREF0 and TBREF1. A maskable interrupt is
generated when the TB count reaches to the value programmed in one of the two reference registers. Two
status bits in the time base control and status register (TBSCR) indicate which one of the two reference
registers generated the interrupt.
Refer to Section 6.2.2.4, “System Timer Registers,” for diagrams and bit descriptions of TB registers.
Refer to Section 3.9.4, “Time Base Facility (TB) — OEA,” and to the RCPU Reference Manual for
additional information.
6.1.8
Real-Time Clock (RTC)
The RTC is a 32-bit counter and pre-divider used to provide a time-of-day indication to the operating
system and application software as show in Figure 6-7. It is clocked by the PITRTCLK clock. The counter
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-19
System Configuration and Protection
is not affected by reset and operates in all low-power modes. It is initialized by software. The RTC can be
programmed to generate a maskable interrupt when the time value matches the value programmed in its
associated alarm register. It can also be programmed to generate an interrupt once a second. A control and
status register is used to enable or disable the different functions and to report the interrupt source.
NOTE
PITRTCLK can be divided by 4 or 256. See Table 8-1 for default settings.
FREEZE
RTSEC
PITRTCLK
Clock
Clock
Disable
Sec
Interrupt
Divide
By 15625
MUX
32-bit Counter (RTC)
Divide
By 78125
Alarm
Interrupt
=
4-MHz/20-MHz crystal
32-bit Register (RTCAL)
Figure 6-7. RTC Block Diagram
6.1.9
Periodic Interrupt Timer (PIT)
The periodic interrupt timer consists of a 16-bit counter clocked by the PITRTCLK clock signal supplied
by the clock module as shown in Figure 6-8.
The 16-bit counter counts down to zero when loaded with a value from the PITC register. After the timer
reaches zero, the PS bit is set and an interrupt is generated if the PIE bit is a logic one. The software service
routine should read the PS bit and then write a zero to terminate the interrupt request. At the next input
clock edge, the value in the PITC is loaded into the counter, and the process starts over again.
When a new value is written into the PITC, the periodic timer is updated, the divider is reset, and the
counter begins counting. If the PS bit is not cleared, an interrupt request is generated. The request remains
pending until PS is cleared. If the PS bit is set again prior to being cleared, the interrupt remains pending
until PS is cleared.
Any write to the PITC stops the current countdown, and the count resumes with the new value in PITC. If
the PISCR[PTE] bit is not set, the PIT is unable to count and retains the old count value. Reads of the PIT
have no effect on the counter value.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-20
Freescale Semiconductor
System Configuration and Protection
PTE
PITC
(PISCR)
(PISCR)
16-bit
Modulus
Counter
Clock
Disable
PITRTCLK
Clock
PS (PISCR)
PIT
Interrupt
PIE (PISCR)
PITF (PISCR)
Figure 6-8. PIT Block Diagram
The timeout period is calculated as:
PITC + 1
PITC + 1
PIT PERIOD = ----------------------------------- = ----------------------------------------------F PITRTCLK
ExternalClock
⟨ -----------------------------------------⟩
4 or 256
Solving this equation using a 4-MHz external clock and a pre-divider of 256 gives:
PITC + 1
PIT PERIOD = -----------------------15625
This gives a range from 64 microseconds, with a PITC of 0x0000, to 4.19 seconds, with a PITC of 0xFFFF.
When a 20-MHz crystal is used with a pre-divider of 256, the range is between 12.8 microseconds to 0.84
seconds.
6.1.10
Software Watchdog Timer (SWT)
The software watchdog timer (SWT) prevents system lockout in case the software becomes trapped in
loops with no controlled exit. The SWT is enabled after system reset to cause a system reset if it times out.
The SWT requires a special service sequence to be executed on a periodic basis. If this periodic servicing
action does not occur, the SWT times out and issues a reset or a non-maskable interrupt (NMI), depending
on the value of the SWRI bit in the SYPCR register.
The SWT can be disabled by clearing the SWE bit in the SYPCR. Once the SYPCR is written by software,
the state of the SWE bit cannot be changed.
The SWT service sequence consists of the following two steps:
1. Write 0x556C to the software service register (SWSR)
2. Write 0xAA39 to the SWSR
The service sequence clears the watchdog timer and the timing process begins again. If any value other
than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start over.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-21
System Configuration and Protection
Although the writes must occur in the correct order prior to time-out, any number of instructions may be
executed between the writes. This allows interrupts and exceptions to occur, if necessary, between the two
writes.
Not 0x556C/Don’t Reload
Reset
0x556C/Don’t Reload
State 0
Waiting for 0x556C
State 1
Waiting for 0xAA39
0xAA39/Reload
Not 0x556C/Don’t Reload
Not 0xAA39/Don’t Reload
Figure 6-9. SWT State Diagram
Although most software disciplines support the watchdog concept, different systems require different
time-out periods. For this reason, the software watchdog provides a selectable range for the time-out
period.
In Figure 6-10, the range is determined by the value in the SWTC field. The value held in the SWTC field
is then loaded into a 16-bit decrementer clocked by the system clock. An additional divide by 2048
prescaler is used if necessary. The decrementer begins counting when loaded with a value from the
software watchdog timing count field (SWTC). After the timer reaches 0x0, a software watchdog
expiration request is issued to the reset or NMI control logic.
Upon reset, the value in the SWTC is set to the maximum value and is again loaded into the software
watchdog register (SWR), starting the process over. When a new value is loaded into the SWTC, the
software watchdog timer is not updated until the servicing sequence is written to the SWSR. If the SWE
is loaded with the value zero, the modulus counter does not count (i.e. SWTC is disabled).
MPC561/MPC563 Reference Manual, Rev. 1.2
6-22
Freescale Semiconductor
System Configuration and Protection
SWSR
Service
Logic
SWE
(SYPCR)
System
Clock
Clock
Disable
SWTC
Divide By
2048
Reload
MUX
16-bit
SWR/Decrementer
Rollover = 0
Reset
or NMI
FREEZE
Time-out
SWP
(SYPCR)
Figure 6-10. SWT Block Diagram
6.1.11
Freeze Operation
When the FREEZE line is asserted, the clocks to the software watchdog, the periodic interrupt timer, the
real-time clock, the time base counter, and the decrementer can be disabled. This is controlled by the
associated bits in the control register of each timer. If programmed to stop during FREEZE assertion, the
counters maintain their values while FREEZE is asserted. The bus monitor remains enabled regardless of
this signal.
6.1.12
Low Power Stop Operation
When the processor is set in a low-power mode (doze, sleep, or deep-sleep), the software watchdog timer
is frozen. It remains frozen and maintains its count value until the processor exits this state and resumes
executing instructions.
The periodic interrupt timer, decrementer, and time base are not affected by these low-power modes. They
continue to run at their respective frequencies. These timers are capable of generating an interrupt to bring
the MCU out of these low-power modes.
6.2
Memory Map and Register Definitions
This section provides the MPC561/MPC563 memory map, register diagrams and bit descriptions of the
system configuration and protection registers.
6.2.1
Memory Map
The MPC561/MPC563 internal memory space can be assigned to one of eight locations.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-23
System Configuration and Protection
The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of
eight locations by programming the ISB field in the internal memory mapping register (IMMR). The eight
possible locations are the first eight 4-Mbyte memory blocks starting with address 0x0000 0000. (Refer to
Figure 6-11.)
0x0000 0000
0x003F FFFF
0x0040 0000
0X007F FFFF
0X0080 0000
0x00BF FFFF
0x00C0 0000
Internal 4-Mbyte Memory Block
(Resides in one of eight locations)
0x00FF FFFF
0x0100 0000
0x013F FFFF
0x0140 0000
0x017F FFFF
0x0180 0000
0x01BF FFFF
0x01C0 0000
0x01FF FFFF
0xFFFF FFFF
Figure 6-11. MPC561/MPC563 Memory Map
6.2.2
System Configuration and Protection Registers
This section describes the MPC561/MPC563 registers.
6.2.2.1
System Configuration Registers
System configuration registers include the SIUMCR, the IMMR, and the EMCR registers.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-24
Freescale Semiconductor
System Configuration and Protection
6.2.2.1.1
SIU Module Configuration Register (SIUMCR)
The SIUMCR contains bits which configure various features in the SIU module. The register contents are
shown below.
MSB
0
1
Field EARB
2
3
4
EARP
5
6
7
—
HRESET ID01
8
9
11
12
DBGC
—
ATWC
ID[9:10]1
ID111
ID121
27
28
LPMASK
_EN
BURST
_EN
DSHW
000_0000_0
Addr
10
13
14
GPC
15
DLK
000
0x2F C000
LSB
16
1
17
18
Field
—
SC
HRESET
0
ID[17:18]1
19
20
21
RCTX MLRC
22
23
—
24
25
26
NOS EICEN
MTSC HOW
29
30
31
—
0_0000_0000_0000
The reset value is a reset configuration word value, extracted from the internal data bus line. Refer to Section 7.5.2, “Hard
Reset Configuration Word (RCW).”
Figure 6-12. SIU Module Configuration Register (SIUMCR)
WARNING
All SIUMCR fields which are controlled by the reset configuration word
should not be changed by software while the corresponding functions are
active.
Table 6-7. SIUMCR Bit Descriptions
Bits
Name
Description
0
EARB
External arbitration
0 Internal arbitration is performed
1 External arbitration is assumed
1:3
EARP
External arbitration request priority. This field defines the priority of an external master’s
arbitration request. This field is valid when EARB is cleared. Refer to Section 9.5.7.4, “Internal
Bus Arbiter,” for details.
4:7
—
8
DSHW
Data show cycles. This bit selects the show cycle mode to be applied to U-bus data cycles (data
cycles to IMB modules and Flash EEPROM). This field is locked by the DLK bit. Note that
instruction show cycles are programmed in the ICTRL and L-bus data show cycles are
programmed in the L2UMCR.
0 Disable show cycles for all internal data cycles
1 Show address and data of all internal data cycles
9:10
DBGC
Debug pins configuration. Refer to Table 6-8.
11
DBPC
Reserved.
12
ATWC
Address write type enable configuration. This bit configures the pins to function as byte write
enables or address types for debugging purposes.
0 WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]1
1 WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-25
System Configuration and Protection
Table 6-7. SIUMCR Bit Descriptions (continued)
Bits
Name
13:14
GPC
This bit configures the pins as shown in Table 6-9.
15
DLK
Debug register lock
0 Normal operation
1 SIUMCR is locked and can be written only in test mode or when the internal freeze signal is
asserted.
16
—
Reserved
17:18
SC
Single-chip select. This field configures the functionality of the address and data buses.
Changing the SC field while external accesses are performed is not supported. Refer to
Table 6-10.
19
RCTX
Reset configuration/timer expired. During reset the RSTCONF/TEXP pin functions as
RSTCONF. After reset the pin can be configured to function as TEXP, the timer expired signal
that supports the low-power modes.
0 RSTCONF/TEXP functions as RSTCONF
1 RSTCONF/TEXP functions as TEXP
20:21
MLRC
Multi-level reservation control. This field selects between the functionality of the reservation logic
and IRQ pins, refer to Table 6-11.
22:23
—
24
MTSC
25
NOSHOW
Instruction show cycles disabled. If the NOSHOW bit is set (1), then all instruction show cycles
are NOT transmitted to the external bus.
26
EICEN
Enhanced interrupt controller enable. See Section 6.1.4.4, “Enhanced Interrupt Controller
Operation,” for more information.
0 Enhanced interrupt controller operates in regular mode (compatible with MPC555/MPC556)
1 Enhanced interrupt controller is enabled
27
1
Description
Reserved
Memory transfer start control.
0 IRQ2/CR/SGPIOC2/MTS functions according to the MLRC bits setting
1 IRQ2/CR/SGPIOC2/MTS functions as MTS
LPMASK_EN Low priority request masking enable.
0 Lower priority interrupt request masking is disabled
1 Lower priority interrupt request masking is enabled
28
BURST_EN
29:31
—
Burst enable.
0 Burst operation is enabled by the BBCMCR[BE]. Maximum burst length is fixed at 4 beats.
1 USIU initiated burst accesses on the external bus. Maximim burst length can be 4 or 8 beats
and this may be programmed per memory region. Refer to Section 10.2.5, “Burst Support,”
for more information.
Note: Do not assert TEA on the external bus for instruction fetch while
SIUMCR[BURST_EN] = 1. Do not place code at the last 8 words of a memory controller
region while SIUMCR[BURST_EN] = 1.
Reserved
WE/BE is selected per memory region by WEBS in the appropriate BR register in the memory controller.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-26
Freescale Semiconductor
System Configuration and Protection
Table 6-8. Debug Pins Configuration
Pin Function
DBGC
IWP[0:1]/VFLS[0:1]
BI/STS
BG/VF0/LWP1
BR/VF1/IWP2
BB/VF2/IWP3
00
VFLS[0:1]
BI
BG
BR
BB
01
IWP[0:1]
STS
BG
BR
BB
10
VFLS[0:1]
STS
VF0
VF1
VF2
11
IWP[0:1]
STS
LWP1
IWP2
IWP3
Table 6-9. General Pins Configuration
Pin Function
GPC
FRZ/PTR/SGPIOC6
IRQOUT/LWP0/SGPIOC7
00
PTR
LWP0
01
SGPIOC6
SGPIOC7
10
FRZ
LWP0
11
FRZ
IRQOUT
Table 6-10. Single-Chip Select Field Pin Configuration
Pin Function
SC
DATA[0:15]/
SGPIOD[0:15]
DATA[16:31]
SGPIOD[16:31]
ADDR[8:31]/
SGPIOA[8:31]
00 (multiple chip, 32-bit port size)
DATA[0:15]
DATA[16:31]
ADDR[8:31]
01 (multiple chip, 16-bit port size
DATA[0:15]
SPGIOD[16:31]
ADDR[8:31]
10 (single-chip with address show
cycles for debugging)
SPGIOD[0:15]
SPGIOD[16:31]
ADDR[8:31]
11 (single-chip)
SPGIOD[0:15]
SPGIOD[16:31]
SPGIOA[8:31]
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-27
System Configuration and Protection
Table 6-11. Multi-Level Reservation Control Pin Configuration
Pin Function
MLRC
IRQ0/
SGPIOC0/
MDO4
IRQ1/RSV/
SGPIOC1
IRQ2/CR/
SGPIOC2/MTS
IRQ3/KR/
RETRY /SGPIOC3
IRQ4/AT2/
SGPIOC4
IRQ5/
SGPIOC5/MODCK11
00
IRQ0
IRQ1
IRQ22
IRQ3
IRQ4
IRQ5/MODCK1
KR/RETRY
AT2
IRQ5/ MODCK1
SGPIOC3
SGPIOC4
SGPIOC5/MODCK1
KR/RETRY
AT2
SGPIOC5/MODCK1
01
IRQ0
RSV
CR
10
SGPIOC0
SGPIOC1
SGPIOC22
11
1
2
IRQ0
2
IRQ1
SGPIOC2
Operates as MODCK1 during reset.
This is true if MTSC is reset to 0. Otherwise, IRQ2/CR/SGPIOC2/MTS will function as MTS.
2
6.2.2.1.2
Internal Memory Map Register (IMMR)
The internal memory map register (IMMR) is a register located within the MPC561/MPC563 special
register space. The IMMR contains identification of a specific device as well as the base for the internal
memory map. Based on the value read from this register, software can deduce availability and location of
any on-chip system resources.
This register can be read by the mfspr instruction. The ISB field can be written by the mtspr instruction.
The PARTNUM and MASKNUM fields are mask programmed and cannot be changed.
MSB
0
1
2
Field
HRESET
3
4
5
6
7
8
9
10
PARTNUM
11
12
13
14
15
MASKNUM
0
0
1
1
0
X1
X1
X1
16
17
18
19
20
21
22
23
Read-Only Fixed Value
LSB
Field
HRESET
Addr
—
FLEN
0000
ID201
—
—
00
ID232
24
25
26
27
28
29
30
31
—
ISB
—
0000
ID[28:30]1
0
SPR 638
1 The
reset value is 101 for MPC561 and 110 for MPC563.
reset value is a reset configuration word value extracted from the indicated bits of the internal data bus. Refer to
Section 7.5.2, “Hard Reset Configuration Word (RCW).”
2 The
Figure 6-13. Internal Memory Mapping Register (IMMR)
MPC561/MPC563 Reference Manual, Rev. 1.2
6-28
Freescale Semiconductor
System Configuration and Protection
Table 6-12. IMMR Bit Descriptions
Bits
Name
Description
0:7
PARTNUM
This read-only field is mask programmed with a code corresponding to the part number of
the part on which the SIU is located. It is intended to help factory test and user code which
is sensitive to part changes. This changes when the part number changes. For example, it
would change if any new module is added, if the size of any memory module is changed. It
would not change if the part is changed to fix a bug in an existing module. The MPC561 has
an ID of 0x35. The MPC563 has an ID of 0x36.
8:15
MASKNUM
This read-only field is mask programmed with a code corresponding to the mask number of
the part. It is intended to help factory test and user code which is sensitive to part changes.
16:19
—
20
FLEN
21:22
—
Reserved
23
—
Reserved. This bit should be programmed to 0 at all times.
24:27
—
Reserved
28:30
ISB
31
—
6.2.2.1.3
Reserved
Flash enable is a read-write bit. The default state of FLEN is negated, meaning that the boot
is performed from external memory. This bit can be set at reset by the reset configuration
word.
0 On-chip Flash memory is disabled, and all internal cycles to the allocated Flash address
space are mapped to external memory
1 On-chip Flash memory is enabled
This read-write field defines the base address of the internal memory space. The initial value
of this field can be configured at reset to one of eight addresses, and then can be changed
to any value by software. Internal base addresses are as follows:
000 0x0000 0000
001 0x0040 0000
010 0x0080 0000
011 0x00C0 0000
100 0x0100 0000
101 0x0140 0000
110 0x0180 0000
111 0x01C0 0000
Reserved
External Master Control Register (EMCR)
The external master control register selects the external master modes and determines the internal bus
attributes for external-to-internal accesses.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-29
System Configuration and Protection
MSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
26
27
28
29
30
15
—
0000_0000_0000_0000
HRESET
Addr
0x2F C030
LSB
16
17
Field PRPM SLVM
1
HRESET ID16
1
0
18
19
20
—
SIZE
0
01
21
22
SUPU INST
0
1
23
24
—
00
25
RESV CONT
1
1
—
0
TRAC SIZEN
1
1
31
—
00
The reset value is a reset configuration word value, extracted from the indicated internal data bus line. Refer to Section 7.5.2,
“Hard Reset Configuration Word (RCW).”
Figure 6-14. External Master Control Register (EMCR)
Table 6-13. EMCR Bit Descriptions
Bits
Name
Description
0:15
—
16
PRPM
Peripheral mode. In this mode, the internal RCPU core is shut off and an alternative master on
the external bus can access any internal slave module. The reset value of this bit is determined
by the reset configuration word bit 16. The bit can also be written by software.
0 Normal operation
1 Peripheral mode operation
17
SLVM
Slave mode (valid only if PRPM = 0). In this mode, an alternative master on the external bus can
access any internal slave module while the internal RCPU core is fully operational. If PRPM is
set, the value of SLVM is a “don’t care.”
0 Normal operation
1 Slave mode
18
—
19:20
SIZE
Size attribute. If SIZEN = 1, the SIZE bits controls the internal bus attributes as follows:
00 Double word (8 bytes)
01 Word (4 bytes)
10 Half word (2 bytes)
11 Byte
21
SUPU
Supervisor/user attribute. SUPU controls the supervisor/user attribute as follows:
0 Supervisor mode access permitted to all registers
1 User access permitted to registers designated “user access”
22
INST
Instruction attribute. INST controls the internal bus instruction attribute as follows:
0 Instruction fetch
1 Operand or non-CPU access
23:24
—
25
RESV
Reserved
Reserved
Reserved
Reservation attribute. RESV controls the internal bus reservation attribute as follows:
0 Storage reservation cycle
1 Not a reservation
MPC561/MPC563 Reference Manual, Rev. 1.2
6-30
Freescale Semiconductor
System Configuration and Protection
Table 6-13. EMCR Bit Descriptions (continued)
Bits
Name
26
CONT
27
—
28
TRAC
Trace attribute. TRAC controls the internal bus program trace attribute as follows:
0 Program trace
1 Not program trace
29
SIZEN
External size enable control bit. SIZEN determines how the internal bus size attribute is driven:
0 Drive size from external bus signals TSIZE[0:1]
1 Drive size from SIZE0, SIZE1 in EMCR
30:31
—
6.2.2.2
Description
Control attribute. CONT drives the internal bus control bit attribute as follows:
0 Access to MPC561/MPC563 control register, or control cycle access
1 Access to global address map
Reserved
Reserved
SIU Interrupt Controller Registers
The SIU interrupt controller contains the following registers: SIPEND, SIPEND2 and SIPEND3 (interrupt
pending registers), SIMASK, SIMASK2 and SIMASK3 (interrupt mask registers), SIEL, SIVEC, SISR2
and SISR3.
The SIPEND and SIMASK registers are used when the interrupt controller is configured for regular,
MPC555/MPC556 compatible, operation. SIPEND2, SIPEND3, SIMASK2, SIMASK3, SISR2 and
SISR3 registers are used only when the interrupt controller is operating in enhanced interrupt mode.
SIPEND, SIPEND2 and SIPEND3 are 32-bit registers. Each bit in the register corresponds to an interrupt
request. The bits associated with internal exceptions indicate, if set, that an interrupt service is requested.
These bits reflect the status of the internal requesting device, and will be cleared when the appropriate
actions are initiated by software in the device itself. Writing to these bits has no effect.
The bits associated with the IRQ pins have a different behavior depending on the sensitivity defined for
them in the SIEL register. When the IRQ is defined as a “level” interrupt the corresponding bit behaves in
a manner similar to the bits associated with internal interrupt sources, (i.e., it reflects the status of the IRQ
pin). This bit can not be changed by software, it will be cleared when the external signal is negated. When
the IRQ is defined as an “edge” interrupt, if the corresponding bit is set, it indicates that a falling edge was
detected on the line. The bit must be reset by software by writing a ‘1’ to it.
The following acronym definitions apply to the various bits implemented in the SIU interrupt controller
registers.
Table 6-14. SIU Interrupt Controller – Bit Acronym Definitions
Name
Description
IRQn
Interrupt Signal n Request
LVLn
Interrupt Level n Request
IMBIRQn
Intermodule Bus Interrupt Level n Request
IRMn
Interrupt Signal n Mask
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-31
System Configuration and Protection
Table 6-14. SIU Interrupt Controller – Bit Acronym Definitions
6.2.2.2.1
Name
Description
LVMn
Interrupt Level n Mask
EDn
Falling Edge Detect, Interrupt Signal n
WMn
Wakeup Mask, Interrupt Signal n
SIU Interrupt Pending Register (SIPEND)
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field IRQ0 LVL0 IRQ1 LVL1 IRQ2 LVL2 IRQ3 LVL3 IRQ4 LVL4 IRQ5 LVL5 IRQ6 LVL6 IRQ7 LVL7
SRESET
0000_0000_0000_0000
Addr
0x2F C010
LSB
16
17
18
19
20
21
22
23
Field
24
25
26
27
28
29
30
31
—
SRESET
0000_0000_0000_0000
Figure 6-15. SIU Interrupt Pending Register (SIPEND)
6.2.2.2.2
SIU Interrupt Pending Register 2 (SIPEND2)
MSB
0
Field IRQ0
1
LVL0
2
3
4
IMB IMB
IMB
IRQ0 IRQ1 IRQ2
5
6
7
IMB
IRQ3
IRQ1
LVL1
8
9
10
IMB IMB IMB
IRQ4 IRQ5 IRQ6
11
12
13
IMB
IRQ7
IRQ2
LVL2
27
28
29
14
15
IMB IMB
IRQ8 IRQ9
0000_0000_0000_0000
SRESET
Addr
0x2F C040
LSB
16
Field
SRESET
17
18
19
20
21
22
23
24
25
26
30
31
IMB
IMB IRQ3 LVL3 IMB
IMB
IMB
IMB IRQ4 LVL4 IMB
IMB
IMB
IMB IRQ5 LVL5
IRQ10 IRQ1
IRQ12 IRQ13 IRQ14 IRQ15
IRQ16 IRQ17 IRQ18 IRQ19
1
0000_0000_0000_0000
Figure 6-16. SIU Interrupt Pending Register 2 (SIPEND2)
MPC561/MPC563 Reference Manual, Rev. 1.2
6-32
Freescale Semiconductor
System Configuration and Protection
6.2.2.2.3
SIU Interrupt Pending Register 3 (SIPEND3)
MSB
0
Field
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB
IRQ20 IRQ21 IRQ22 IRQ23 6
6 IRQ24 IRQ25 IRQ26 IRQ27 7
7 IRQ28 IRQ29 IRQ30 IRQ31
SRESET
0000_0000_0000_0000
Addr
0x2F C044
LSB
16
17
Field
18
19
20
21
22
23
24
25
26
27
28
29
30
31
—
SRESET
0000_0000_0000_0000
Figure 6-17. SIU Interrupt Pending Register 3 (SIPEND3)
6.2.2.2.4
SIU Interrupt Mask Register (SIMASK)
SIMASK is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND register.
SIMASK2 is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND2 register.
SIMASK3 is a 32-bit read/write register. Each bit in the register corresponds to an interrupt request bit in
the SIPEND3 register.
When the bit is set, it enables the generation of an interrupt request to the RCPU. SIMASK, SIMASK2,
SIMASK3 are updated by software and cleared upon reset. It is the responsibility of the software to
determine which of the interrupt sources are enabled at a given time.
NOTE
Disable external interrupts in the core prior to changing any interrupt
controller related register (SIMASK, SIPEND, SIEL, or SISR). Refer to
MSR[EE] bit description in Table 3-11 and the note regarding special
handling of the EIC in Section 6.1.4.4, “Enhanced Interrupt Controller
Operation.”
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-33
System Configuration and Protection
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
Field IRM0 LVM0 IRM1 LVM1 IRM2 LVM2 IRM3 LVM3 IRM4 LVM4 IRM5 LVM5 IRM6 LVM6 IRM7 LVM7
0000_0000_0000_0000
SRESET
Addr
0x2F C014
LSB
16
17
18
19
20
21
22
23
Field
25
26
27
28
29
30
31
—
SRESET
1
24
0000_0000_0000_0000
IRQ0 of the SIPEND register is not affected by the setting or clearing of the IRM0 bit of the SIMASK register. IRQ0 is a
non-maskable interrupt.
Figure 6-18. SIU Interrupt Mask Register (SIMASK)
6.2.2.2.5
SIU Interrupt Mask Register 2 (SIMASK2)
MSB
Field
0
1
IRQ01
LVL0
2
3
4
IMB IMB
IMB
IRQ0 IRQ1 IRQ2
5
6
7
IMB
IRQ3
IRQ1
LVL1
8
9
10
IMB IMB IMB
IRQ4 IRQ5 IRQ6
11
12
13
IMB
IRQ7
IRQ2
LVL2
27
28
29
14
15
IMB IMB
IRQ8 IRQ9
0000_0000_0000_0000
SRESET
Addr
0x2F C048
LSB
16
Field
SRESET
1
17
18
19
20
21
22
23
24
25
26
30
31
IMB
IMB IRQ3 LVL3 IMB
IMB
IMB
IMB IRQ4 LVL4 IMB
IMB
IMB
IMB IRQ5 LVL5
IRQ10 IRQ1
IRQ12 IRQ13 IRQ14 IRQ15
IRQ16 IRQ17 IRQ18 IRQ19
1
0000_0000_0000_0000
IRQ0 of the SIPEND2 register is not affected by the setting or clearing of the IRQ0 bit of the SIMASK2 register. IRQ0 is a
non-maskable interrupt
Figure 6-19. SIU Interrupt Mask Register 2 (SIMASK2)
MPC561/MPC563 Reference Manual, Rev. 1.2
6-34
Freescale Semiconductor
System Configuration and Protection
6.2.2.2.6
SIU Interrupt Mask Register 3 (SIMASK3)
MSB
0
Field
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB
IRQ20 IRQ21 IRQ22 IRQ23 6
6 IRQ24 IRQ25 IRQ26 IRQ27 7
7 IRQ28 IRQ29 IRQ30 IRQ31
0000_0000_0000_0000
SRESET
Addr
0x2F C04C
LSB
16
17
18
19
20
21
22
23
Field
24
25
26
27
28
29
30
31
—
SRESET
0000_0000_0000_0000
Figure 6-20. SIU Interrupt Mask Register 3 (SIMASK3)
6.2.2.2.7
SIU Interrupt Edge Level Register (SIEL)
The SIEL is a 32-bit read/write register. Each pair of bits corresponds to an external interrupt request. The
EDx bit, if set, specifies that a falling edge in the corresponding IRQ line will be detected as an interrupt
request. When the EDx bit is 0, a low logical level in the IRQ line will be detected as an interrupt request.
The WMx (wake-up mask) bit, if set, indicates that an interrupt request detection in the corresponding line
causes the MPC561/MPC563 to exit low-power mode.
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7
HRESET
0000_0000_0000_0000
Addr
0x2F C018
LSB
16
17
Field
18
19
20
21
22
23
24
25
26
27
28
29
30
31
—
HRESET
0000_0000_0000_0000
Figure 6-21. SIU Interrupt Edge Level Register (SIEL)
6.2.2.2.8
SIU Interrupt Vector Register (SIVEC)
The SIVEC is a 32-bit read-only register that contains an 8-bit code representing the unmasked interrupt
source of the highest priority level. The SIVEC can be read as either a byte, half word, or word. When read
as a byte, a branch table can be used in which each entry contains one instruction (branch). When read as
a half-word, each entry can contain a full routine of up to 256 instructions. The interrupt code is defined
such that its two least significant bits are 0, thus allowing indexing into the table. The two possible ways
of the code usage are shown on Figure 6-23.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-35
System Configuration and Protection
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
Field
INTERRUPT CODE
—
Reset
0011_1100
0000_0000
Addr
13
14
29
30
15
0x2F C01C
LSB
16
17
18
19
20
21
22
23
24
Field
—
Reset
0000_0000_0000_0000
25
26
27
28
31
Figure 6-22. SIU Interrupt Vector Register (SIVEC)
INTR:...
Save state
R3 ← @SIVEC
R4 ← Base of branch table
...
lbz RX, R3 (0)# load as byte
add RX, RX, R4
mtsprCTR, RX
bctr
BASE
b
Routine1
BASE + 4
b
Routine2
BASE + 8
b
Routine3
BASE + C
b
Routine4
BASE +10
•
BASE + n
•
INTR:...
Save state
R3 ← @SIVEC
R4 ← Base of branch table
...
lhz RX, R3 (0)# load as half
add RX, RX, R4
mtspr CTR, RX
bctr
BASE
BASE + 400
BASE + 800
BASE + C00
BASE +1000
BASE + n
1st Instruction of Routine1
•
•
1st Instruction of Routine2
•
•
1st Instruction of Routine3
•
•
1st Instruction of Routine4
•
•
•
•
•
•
•
•
Figure 6-23. Example of SIVEC Register Usage for Interrupt Table Handling
MPC561/MPC563 Reference Manual, Rev. 1.2
6-36
Freescale Semiconductor
System Configuration and Protection
6.2.2.2.9
Interrupt In-Service Registers (SISR2 and SISR3)
SISR2, SISR3 are 32-bit read/write registers. Each bit in the register corresponds to an interrupt request.
A bit is set if:
• There is a pending interrupt request (SIPEND2/3), that is not masked by (SIMASK2/3), and
• The BBC/IMPU acknowledges interrupt request and latches SIVEC value.
Once a bit is set, all requests with lower or equal priority become masked (i.e. they will not generate any
interrupt request to the RCPU) until the bit is cleared. A bit is cleared by writing a ‘1’ to it. Writing zero
has no effect.
MSB
0
1
Field IRQ0
2
LVL0
3
4
IMB IMB IMB
IRQ0 IRQ1 IRQ2
5
6
7
IMB
IRQ3
IRQ1
LVL1
SRESET
8
9
10
IMB IMB
IMB
IRQ4 IRQ5 IRQ6
11
12
13
IMB
IRQ7
IRQ2
LVL2
27
28
29
14
15
IMB IMB
IRQ8 IRQ9
0000_0000_0000_0000
Addr
0x2F C050
LSB
16
Field
17
18
19
20
21
22
23
24
25
26
30
31
IMB
IMB IRQ3 LVL4 IMB
IMB
IMB
IMB IRQ4 LVL4 IMB
IMB
IMB
IMB IRQ5 LVL5
IRQ10 IRQ11
IRQ12 IRQ13 IRQ14 IRQ15
IRQ16 IRQ17 IRQ18 IRQ19
SRESET
0000_0000_0000_0000
Figure 6-24. Interrupt In-Service Register 2 (SISR2)
MSB
0
Field
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB IRQ LVL IMB
IMB
IMB
IMB
IRQ20 IRQ21 IRQ22 IRQ23 6
6 IRQ24 IRQ25 IRQ26 IRQ27 7
7 IRQ28 IRQ29 IRQ30 IRQ31
SRESET
0000_0000_0000_0000
Addr
0x2F C054
LSB
16
17
18
19
20
21
22
Field
23
24
25
26
27
28
29
30
31
—
SRESET
0000_0000_0000_0000
Figure 6-25. Interrupt In-Service Register 3 (SISR3)
6.2.2.3
6.2.2.3.1
System Protection Registers
System Protection Control Register (SYPCR)
The system protection control register (SYPCR) controls the system monitors, the software watchdog
period, and the bus monitor timing. This register can be read at any time, but can be written only once after
system reset.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-37
System Configuration and Protection
MSB
0
1
2
3
4
5
6
7
Field
8
9
10
11
12
13
14
26
27
28
29
30
15
SWTC
1111_1111_1111_1111
HRESET
Addr
0x2F C004
LSB
16
17
18
19
Field
HRESET
20
21
22
23
24
25
BMT
BME
—
1111_1111
0
000
31
SWF SWE SWRI SWP
0
1
1
1
Figure 6-26. System Protection Control Register (SYPCR)
Table 6-15. SYPCR Bit Descriptions
Bits
Name
0:15
SWTC
16:23
BMT
Bus monitor timing. This field specifies the time-out period, in eight-system-clock resolution, of
the bus monitor. BMT must be set to non zero even if the bus monitor is not enabled.
24
BME
Bus monitor enable
0 Disable bus monitor
1 Enable bus monitor
25:27
—
28
SWF
Software watchdog freeze
0 Software watchdog continues to run while FREEZE is asserted
1 Software watchdog stops while FREEZE is asserted
29
SWE
Software watchdog enable. Software should clear this bit after a system reset to disable the
software watchdog timer.
0 Watchdog is disabled
1 Watchdog is enabled
30
SWRI
Software watchdog reset/interrupt select
0 Software watchdog time-out causes a non-maskable interrupt to the RCPU
1 Software watchdog time-out causes a system reset
31
SWP
Software watchdog prescale
0 Software watchdog timer is not prescaled
1 Software watchdog timer is prescaled by 2048
6.2.2.3.2
Description
Software watchdog timer count. This field contains the count value of the software watchdog
timer.
Reserved
Software Service Register (SWSR)
The SWSR is the location to which the SWT servicing sequence is written. To prevent SWT time-out, a
0x556C followed by 0xAA39 should be written to this register. The SWSR can be written at any time but
returns all zeros when read.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-38
Freescale Semiconductor
System Configuration and Protection
MSB
LSB
0
1
2
3
4
5
6
7
8
9
Field
SWSR
Reset
0000_0000_0000_0000
Addr
0x2F C00E
10
11
12
13
14
15
Figure 6-27. Software Service Register (SWSR)
Table 6-16. SWSR Bit Descriptions
Bits
Name
Description
0:15
SWSR
SWT servicing sequence is written to this register. To prevent SWT time-out, a 0x556C followed
by 0xAA39 should be written to this register. The SWSR can be written at any time but returns
all zeros when read.
6.2.2.3.3
Transfer Error Status Register (TESR)
The transfer error status register contains a bit for each exception source generated by a transfer error. A
bit set to logic 1 indicates what type of transfer error exception occurred since the last time the bits were
cleared by reset or by the normal software status bit-clearing mechanism.
NOTE
These bits may be set due to canceled speculative accesses which do not
cause an interrupt. The register has two identical sets of bit fields; one is
associated with instruction transfers and the other with data transfers.
MSB
0
1
2
3
4
5
6
7
8
9
Field
—
Reset
0000_0000_0000_0000
Addr
0x2F C020
10
11
12
13
14
26
27
28
29
30
15
LSB
16
Field
17
—
18
19
IEXT IBMT
Reset
20
21
22
23
24
25
—
DEXT DBM
31
—
0000_0000_0000_0000
Figure 6-28. Transfer Error Status Register (TESR)
Table 6-17. TESR Bit Descriptions
Bits
Name
Description
0:17
—
18
IEXT
Instruction external transfer error acknowledge. This bit is set if the cycle was terminated by an
externally generated TEA signal when an instruction fetch was initiated.
19
IBMT
Instruction transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor
time-out when an instruction fetch was initiated.
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-39
System Configuration and Protection
Table 6-17. TESR Bit Descriptions (continued)
Bits
Name
20:25
—
26
DEXT
Data external transfer error acknowledge. This bit is set if the cycle was terminated by an
externally generated TEA signal when a data load or store is requested by an internal master.
27
DBM
Data transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor time-out
when a data load or store is requested by an internal master.
28:31
—
6.2.2.4
Description
Reserved
Reserved
System Timer Registers
The following sections describe registers associated with the system timers. These facilities are powered
by the KAPWR and can preserve their value when the main power supply is off. Refer to Section 8.2.3,
“Pre-Divider,” for details on the required actions needed in order to guarantee this data retention.
A list of KAPWR registers affected by the key/lock mechanism is found in Table 8-8.
6.2.2.4.1
Decrementer Register (DEC)
The 32-bit decrementer register is defined by the PowerPC architecture. The values stored in this register
are used by a down counter to cause decrementer exceptions. The decrementer causes an exception
whenever bit zero changes from a logic zero to a logic one. A read of this register always returns the current
count value from the down counter.
Contents of this register can be read or written to by the mfspr or the mtspr instruction. The decrementer
register is reset by PORESET. HRESET and SRESET do not affect this register. The decrementer is
powered by standby power and can continue to count when standby power is applied.
Decrementer counts down the time base clock and the counting is enabled by TBE bit in TBCSR register
Section 6.2.2.4.4, “Time Base Control and Status Register (TBSCR).”
MSB
LSB
0
31
Field
PORESET
DECREMENTING COUNTER
0000_0000_0000_0000_0000_0000_0000_0000
Unaffected
HRESET
SRESET
Addr
SPR 22
Figure 6-29. Decrementer Register (DEC)
Refer to Section 3.9.5, “Decrementer Register (DEC)” for more information on this register.
6.2.2.4.2
Time Base SPRs (TB)
The TB is a 64-bit register containing a 64-bit integer that is incremented periodically. There is no
automatic initialization of the TB; the system software must perform this initialization. The contents of the
MPC561/MPC563 Reference Manual, Rev. 1.2
6-40
Freescale Semiconductor
System Configuration and Protection
register may be written by the mttbl or the mttbu instructions, see Section 3.9.4, “Time Base Facility (TB)
— OEA.”
Refer to Section 3.8, “VEA Register Set — Time Base (TB)’ and Section 3.9.4, “Time Base Facility (TB)
— OEA” for more information on reading and writing the TBU and TBL registers.
MSB
LSB
0
Field
31 32
TBU
PORESET
63
TBL
Unaffected
Addr
SPR 269, SPR 268
Figure 6-30. Time Base (Reading) (TB)
MSB
LSB
0
Field
31 32
TBU
PORESET
63
TBL
Unaffected
Addr
SPR 285, SPR 284
Figure 6-31. Time Base (Writing) (TB)
6.2.2.4.3
Time Base Reference Registers (TBREF0 and TBREF1)
Two reference registers (TBREF0 and TBREF1) are associated with the lower part of the time base (TBL).
Each is a 32-bit read/write register. Upon a match between the contents of TBL and the reference register,
a maskable interrupt is generated.
MSB
LSB
0
31
Field
TBREF0
Reset
Unaffected
Addr
0x2F C204
Figure 6-32. Time Base Reference Register 0 (TBREF0)
MSB
LSB
0
31
Field
TBREF1
Reset
Unaffected
Addr
0x2F C208
Figure 6-33. Time Base Reference Register 1 (TBREF1)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-41
System Configuration and Protection
6.2.2.4.4
Time Base Control and Status Register (TBSCR)
The TBSCR is 16-bit read/write register. It controls the TB, decrementer count enable, and interrupt
generation and is used for reporting the source of the interrupts. The register can be read anytime. A status
bit is cleared by writing a one to it. (Writing a zero has no effect.) More than one bit can be cleared at a time.
MSB
0
Field
LSB
1
2
3
4
TBIRQ
PORESET
5
6
7
8
9
10
REFA REFB
11
—
12
13
14
15
REFAE
REFBE
TBF
TBE
0000_0000_0000_0000
Addr
0x2F C200
Figure 6-34. Time Base Control and Status Register (TBSCR)
Table 6-18. TBSCR Bit Descriptions
Bits
Name
Description
0:7
TBIRQ
Time base interrupt request. These bits determine the interrupt priority level of the time base.
Refer to Section 6.1.4, “Enhanced Interrupt Controller” for interrupt level encoding.
8
REFA
Reference A (TBREF0) interrupt status.
0 No match detected
1 TBREF0 value matches value in TBL
9
REFB
Reference B (TBREF1) interrupt status.
0 No match detected
1 TBREF1 value matches value in TBL
10:11
—
12
REFAE
Reference A (TBREF0) interrupt enable. If this bit is set, the time base generates an interrupt
when the REFA bit is set.
13
REFBE
Reference B (TBREF1) interrupt enable. If this bit is set, the time base generates an interrupt
when the REFB bit is set.
14
TBF
Time base freeze. If this bit is set, the time base and decrementer stop while FREEZE is
asserted.
15
TBE
Time base enable
0 Time base and decrementer are disabled
1 Time base and decrementer are enabled
6.2.2.4.5
Reserved
Real-Time Clock Status and Control Register (RTCSC)
The RTCSC enables the different RTC functions and reports the source of the interrupts. The register can
be read anytime. A status bit is cleared by writing a one to it. (Writing a zero does not affect a status bit’s
value.) More than one status bit can be cleared at a time. This register is locked after reset by default.
Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See Section 8.8.3.2,
“Keep-Alive Power Registers Lock Mechanism.”
MPC561/MPC563 Reference Manual, Rev. 1.2
6-42
Freescale Semiconductor
System Configuration and Protection
MSB
LSB
0
1
Field
2
3
4
5
6
7
RTCIRQ
8
9
10
11
12
13
14
15
SEC
ALR
—
4M
SIE
ALE
RTF
RTE
0000_0000_000
PORESET
U
Addr
000
U
0x2F C220
Figure 6-35. Real-Time Clock Status and Control Register (RTCSC)
Table 6-19. RTCSC Bit Descriptions
Bits
Name
0:7
RTCIRQ
8
SEC
Once per second interrupt. This status bit is set every second. It should be cleared by the
software.
9
ALR
Alarm interrupt. This status bit is set when the value of the RTC equals the value programmed in
the alarm register.
10
—
Reserved
11
4M
Real-time clock source
0 RTC assumes that it is driven by 20 MHz to generate the seconds pulse.
1 RTC assumes that it is driven by 4 MHz
12
SIE
Second interrupt enable. If this bit is set, the RTC generates an interrupt when the SEC bit is set.
13
ALE
Alarm interrupt enable. If this bit is set, the RTC generates an interrupt when the ALR bit is set.
14
RTF
Real-time clock freeze. If this bit is set, the RTC stops while FREEZE is asserted.
15
RTE
Real-time clock enable
0 RTC is disabled
1 RTC is enabled
6.2.2.4.6
Description
Real-time clock interrupt request. Thee bits determine the interrupt priority level of the RTC.
Refer to Section 6.1.4, “Enhanced Interrupt Controller” for interrupt level encoding.
Real-Time Clock Register (RTC)
The real-time clock register is a 32-bit read write register. It contains the current value of the real-time
clock. A write to the RTC resets the seconds timer to zero. This register is locked after reset by default.
Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See Section 8.8.3.2,
“Keep-Alive Power Registers Lock Mechanism.”
MSB
LSB
0
31
Field
RTC
Reset
Unaffected
Addr
0x2F C224
Figure 6-36. Real-Time Clock Register (RTC)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-43
System Configuration and Protection
6.2.2.4.7
Real-Time Clock Alarm Register (RTCAL)
The RTCAL is a 32-bit read/write register. When the value of the RTC is equal to the value programmed
in the alarm register, a maskable interrupt is generated.
The alarm interrupt will be generated as soon as there is a match between the ALARM field and the
corresponding bits in the RTC. The resolution of the alarm is 1 second. This register is locked after reset
by default. Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See
Section 8.8.3.2, “Keep-Alive Power Registers Lock Mechanism.”
MSB
LSB
0
31
Field
ALARM
Reset
Unaffected
Addr
0x2F C22C
Figure 6-37. Real-Time Clock Alarm Register (RTCAL)
6.2.2.4.8
Periodic Interrupt Status and Control Register (PISCR)
The PISCR contains the interrupt request level and the interrupt status bit. It also contains the controls for
the 16-bits to be loaded into a modulus counter. This register can be read or written at any time.
MSB
0
LSB
1
2
Field
3
4
PIRQ
PORESET
5
6
7
8
9
10
PS
11
12
—
13
14
15
PIE
PITF
PTE
0000_0000_0000_0000
Addr
0x2F C240
Figure 6-38. Periodic Interrupt Status and Control Register (PISCR)
Table 6-20. PISCR Bit Descriptions
Bits
Name
Description
0:7
PIRQ
8
PS
Periodic interrupt status. This bit is set if the PIT issues an interrupt. The PIT issues an interrupt
after the modulus counter counts to zero. PS can be negated by writing a one to it. A write of zero
has no affect.
9:12
—
Reserved
13
PIE
14
PITF
PIT freeze. If this bit is set, the PIT stops while FREEZE is asserted.
15
PTE
Periodic timer enable
0 PIT stops counting and maintains current value
1 PIT continues to decrement
Periodic interrupt request. These bits determine the interrupt priority level of the PIT. Refer to
Section 6.1.4, “Enhanced Interrupt Controller” for interrupt level encoding.
Periodic interrupt enable. If this bit is set, the time base generates an interrupt when the PS bit
is set.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-44
Freescale Semiconductor
System Configuration and Protection
6.2.2.4.9
Periodic Interrupt Timer Count Register (PITC)
The PITC register contains the 16-bits to be loaded in a modulus counter. This register is readable and
writable at any time.
MSB
0
1
2
3
4
5
6
7
8
Field
PITC
Reset
Unaffected
Addr
0x2F C244
9
10
11
12
13
14
25
26
27
28
29
30
15
LSB
16
17
18
19
20
21
22
23
24
Field
—
Reset
Unaffected
31
Figure 6-39. Periodic Interrupt Timer Count (PITC)
Table 6-21. PITC Bit Descriptions
Bits
Name
Description
0:15
PITC
Periodic interrupt timing count. This field contains the 16-bit value to be loaded into the modulus
counter that is loaded into the periodic timer. This register is readable and writable at any time.
16:31
—
6.2.2.4.10
Reserved
Periodic Interrupt Timer Register (PITR)
The periodic interrupt register is a read-only register that shows the current value in the periodic interrupt
down counter. Read or writing this register does not affect the register.
MSB
0
1
2
3
4
5
6
7
8
Field
PIT
Reset
Unaffected
Addr
0x2F C248
9
10
11
12
13
14
25
26
27
28
29
30
15
LSB
16
17
18
19
20
21
22
23
24
Field
—
Reset
Unaffected
31
Figure 6-40. Periodic Interrupt Timer Register (PITR)
Table 6-22. PIT Bit Descriptions
Bits
Name
Description
0:15
PIT
Periodic interrupt timing count—This field contains the current count remaining for the periodic
timer. Writes have no effect on this field.
16:31
—
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-45
System Configuration and Protection
6.2.2.5
General-Purpose I/O Registers
6.2.2.5.1
SGPIO Data Register 1 (SGPIODT1)
MSB
0
1
2
Field
3
4
5
6
7
8
9
10
SGPIOD[0:7]
11
12
13
14
29
30
15
SGPIOD[8:15]
Reset
0000_0000_0000_00001
Addr
0x2F C024
LSB
16
17
18
Field
20
21
22
23
24
25
26
SGPIOD[16:23]
27
28
31
SGPIOD[24:31]
0000_0000_0000_00001
Reset
1
19
If the device is configured NOT in full bus mode (i.e., SIUMCR[SC]=0b01, 0x10, or 0b11), the GPIO pins will be in input
mode and this register will reflect the state of the pins.
Figure 6-41. SGPIO Data Register 1 (SGPIODT1)
Table 6-23. SGPIODT1 Bit Descriptions
Bits
Name
Description
0:7
SGPIOD[0:7]
SIU general-purpose I/O Group D[0:7]. This 8-bit register controls the data of
general-purpose I/O pins SGPIOD[0:7]. The direction (input or output) of this group of pins
is controlled by the GDDR0 bit in the SGPIO control register.
8:15
SGPIOD[8:15]
SIU general-purpose I/O Group D[8:15]. This 8-bit register controls the data of
general-purpose I/O pins SGPIOD[8:15]. The direction (input or output) of this group of
pins is controlled by the GDDR1 bit in the SGPIO control register.
16:23
SGPIOD[16:23]
SIU general-purpose I/O Group D[16:23]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOD[16:23]. The direction (input or output) of this group of
pins is controlled by the GDDR2 bit in the SGPIO control register
24:31
SGPIOD[24:31]
SIU general-purpose I/O Group D[24:31]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOD[24:31]. The direction of SGPIOD[24:31] is controlled by
eight dedicated direction control signals SDDRD[24:31]. Each pin in this group can be
configured separately as general-purpose input or output.
MPC561/MPC563 Reference Manual, Rev. 1.2
6-46
Freescale Semiconductor
System Configuration and Protection
6.2.2.5.2
SGPIO Data Register 2 (SGPIODT2)
MSB
0
1
2
Field
3
4
5
6
7
8
9
10
11
SGPIOC[0:7]
12
13
14
29
30
15
SGPIOA[8:15]
1
Reset
0000_0000_0000_0000
Addr
0x2F C028
LSB
16
17
18
Field
20
21
22
23
24
25
26
SGPIOA[16:23]
27
28
31
SGPIOA[24:31]
1
Reset
1
19
0000_0000_0000_0000
If the device is configured NOT in full bus mode (i.e., SIUMCR[SC]=0b01, 0x10, or 0b11), the GPIO pins will be in input
mode and this register will reflect the state of the pins.
Figure 6-42. SGPIO Data Register 2 (SGPIODT2)
Table 6-24. SGPIODT2 Bit Descriptions
Bits
Name
Description
0:7
SGPIOC[0:7]
SIU general-purpose I/O Group C[0:7]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOC[0:7]. The direction of SGPIOC[0:7] is controlled by 8
dedicated direction control signals SDDRC[0:7] in the SGPIO control register. Each pin in
this group can be configured separately as general-purpose input or output.
8:15
SGPIOA[8:15] SIU general-purpose I/O Group A[8:15]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[8:15]. The GDDR3 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
16:23
SGPIOA
[16:23]
SIU general-purpose I/O Group A[16:23]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[16:23]. The GDDR4 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
24:31
SGPIOA
[24:31]
SIU general-purpose I/O Group A[24:31]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[24:31]. The GDDR5 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
6-47
System Configuration and Protection
6.2.2.5.3
SGPIO Control Register (SGPIOCR)
1
MSB
0
1
2
Field
3
4
5
6
7
8
9
10
11
SDDRC[0:7]
HRESET
12
13
14
28
29
30
15
—
0000_0000_0000_0000
Addr
0x2F C02C
LSB
16
17
18
19
20
21
22
23
Field GDDR GDDR GDDR GDDR GDDR GDDR
0
1
2
3
4
5
24
25
26
—
27
31
SDDRD[24:31]
0000_0000_0000_0000
HRESET
Figure 6-43. SGPIO Control Register (SGPIOCR)
Table 6-25. SGPIOCR Bit Descriptions
Bits
Name
Description
0:7
SDDRC[0:7]
SGPIO data direction for SGPIOC[0:7]. Each SDDR bit zero to seven controls the direction
of the corresponding SGPIOC pin zero to seven
8:15
—
16
GDDR0
Group data direction for SGPIOD[0:7]
17
GDDR1
Group data direction for SGPIOD[8:15]
18
GDDR2
Group data direction for SGPIOD[16:23]
19
GDDR3
Group data direction for SGPIOA[8:15]
20
GDDR4
Group data direction for SGPIOA[16:23]
21
GDDR5
Group data direction for SGPIOA[24:31]
22:23
—
24:31
SDDRD
[24:31]
Reserved
Reserved
SGPIO data direction for SGPIOD[24:31]. Each SDDRD bits 24:31 controls the direction
of the corresponding SGPIOD pin [24:31].
Table 6-26 describes the bit values for data direction control.
Table 6-26. Data Direction Control
SDDR/GDDR
Operation
0
SGPIO configured as input
1
SGPIO configured as output
MPC561/MPC563 Reference Manual, Rev. 1.2
6-48
Freescale Semiconductor
Chapter 7
Reset
This section describes the MPC561/MPC563 reset sources, operation, control, and status.
7.1
Reset Operation
The MPC561/MPC563 has several inputs to the reset logic which include the following:
• Power-on reset
• External hard reset pin (HRESET)
• External soft reset pin (SRESET)
• Loss of PLL lock
• On-chip clock switch
• Software watchdog reset
• Checkstop reset
• Debug port hard reset
• Debug port soft reset
• JTAG reset
• Illegal bit change (ILBC)
All of these reset sources are fed into the reset controller. The control logic determines the cause of the
reset, synchronizes it, and resets the appropriate logic modules, depending on the source of the reset. The
memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only
on hard reset. External soft reset initializes internal logic while maintaining system configuration.
The reset status register (RSR) reflects the most recent source to cause a reset.
7.1.1
Power-On Reset
The power-on reset pin, PORESET, is an active low input. In a system with power-down low-power mode,
this pin should be activated only as a result of a voltage failure on the KAPWR pin. After detecting the
assertion of PORESET, the MPC561/MPC563 enters the power-on reset state. During this state the
MODCK[1:3] signals determine the oscillator frequency, PLL multiplication factor, and the PITRTCLK
and TMBCLK clock sources. In addition, the MPC561/MPC563 asserts the SRESET and HRESET pins
at the rising edge of PORESET.
The PORESET pin should be asserted for a minimum time of 100,000 of clock oscillator cycles after a
valid level has been reached on the KAPWR supply. After detecting the assertion of PORESET, the
MPC561/MPC563 remains in the power-on reset state until the last of the following two events occurs:
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-1
Reset
•
•
The Internal PLL enters the lock state and the system clock is active.
The PORESET pin is negated.
If limp mode is enabled, the internal PLL is not required to be locked before the chip exits power-on reset.
The internal MODCK[1:3] values are sampled at the rising edge of PORESET. After exiting the power-on
reset state, the MPC561/MPC563 continues to drive the HRESET and SRESET pins for 512 system clock
cycles. When the timer expires (after 512 cycles), the configuration is sampled from data bus pins, if
required (see Section 7.5.1, “Hard Reset Configuration”) and the MPC561/MPC563 stops driving the
HRESET and SRESET pins.
The PORESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The
internal PORESET signal asserts only if the PORESET pin asserts for more than 100 ns.
7.1.2
Hard Reset
HRESET (hard reset) is an active low, bidirectional I/O pin. The MPC561/MPC563 can detect an external
assertion of HRESET only if it occurs while the MPC561/MPC563 is not asserting HRESET.
When the MPC561/MPC563 detects assertion of the external HRESET pin or a cause to assert the internal
HRESET line is detected, the chip starts to drive the HRESET and SRESET for 512 cycles. When the timer
expires (after 512 cycles) the configuration is sampled from data pins (refer to Section 7.5.1, “Hard Reset
Configuration”) and the chip stops driving the HRESET and SRESET pins. An external pull-up resistor
should drive the HRESET and SRESET pins high. After detecting the negation of HRESET or SRESET,
the MPC561/MPC563 waits 16 clock cycles before testing the presence of an external hard or soft reset.
The HRESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The internal
HRESET will be asserted only if HRESET is asserted for more than 100 ns.
The HRESET is an open collector type pin.
7.1.3
Soft Reset
SRESET (soft reset) is an active low, bidirectional I/O pin. The MPC561/MPC563 can only detect an
external assertion of SRESET if it occurs while the MPC561/MPC563 is not asserting SRESET.
When the MPC561/MPC563 detects the assertion of external SRESET or a cause to assert the internal
SRESET line, the chip starts to drive the SRESET for 512 cycles. When the timer expires (after 512 cycles)
the debug port configuration is sampled from the DSDI and DSCK pins and the chip stops driving the
SRESET pin. An external pull-up resistor should drive the SRESET pin high. After the MPC561/MPC563
detects the negation of SRESET, it waits 16 clock cycles before testing the presence of an external soft
reset.
The SRESET is an open collector type pin.
7.1.4
Loss of PLL Lock
If the PLL detects a loss of lock, erroneous external bus operation will occur if synchronous external
devices use the MPC561/MPC563 input clock. Erroneous operation could also occur if devices with a PLL
MPC561/MPC563 Reference Manual, Rev. 1.2
7-2
Freescale Semiconductor
Reset
use the MPC561/MPC563 CLKOUT signal. This source of reset can be optionally asserted if the LOLRE
bit in the PLL, low-power, and reset control register (PLPRCR) is set. The enabled PLL loss of lock event
generates an internal hard reset sequence. Refer to Chapter 8, “Clocks and Power Control,” for more
information on loss of PLL lock.
7.1.5
On-Chip Clock Switch
If the system clock is switched to the backup clock or switched from backup clock to another clock source
an internal hard reset sequence is generated. Refer to Chapter 8, “Clocks and Power Control.”
7.1.6
Software Watchdog Reset
When the MPC561/MPC563 software watchdog counts to zero, a software watchdog reset is asserted. The
enabled software watchdog event generates an internal hard reset sequence.
7.1.7
Checkstop Reset
When the RCPU enters a checkstop state, and the checkstop reset is enabled (the CSR bit in the PLPRCR
is set), a checkstop reset is asserted. The enabled checkstop event generates an internal hard reset sequence.
Refer to the RCPU Reference Manual for more information.
7.1.8
Debug Port Hard Reset
When the development port receives a hard reset request from the development tool, an internal hard reset
sequence is generated. In this case the development tool must reconfigure the debug port. Refer to
Chapter 23, “Development Support,” for more information.
7.1.9
Debug Port Soft Reset
When the development port receives a soft reset request from the development tool, an internal soft reset
sequence is generated. In this case the development tool must reconfigure the debug port. Refer to
Chapter 23, “Development Support,” for more information.
7.1.10
JTAG Reset
When the JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated. Refer
to Chapter 25, “IEEE 1149.1-Compliant Interface (JTAG),” for more information.
7.1.11
ILBC Illegal Bit Change
When locked bits in the PLPRCR register are changed, an internal hard reset sequence is generated. Refer
to Chapter 8, “Clocks and Power Control.”
7.2
Reset Actions Summary
Table 7-1 summarizes the action taken for each reset.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-3
Reset
Table 7-1. Reset Action Taken for Each Reset Cause
Reset Source
Reset
Logic and
PLL
States
Reset
Other
System
Clock HRESET Debug Port
SRESET
Internal
Configuratio Module
Pin
Configuratio
Pin
Logic
n Reset
Reset
Driven
n
Driven
Reset
Power-On Reset
(PORESET)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Hard Reset (HRESET)
Sources:
• External Hard Reset
• Loss of Lock
• On-Chip Clock Switch
• Illegal Low-Power Mode
• Software Watchdog
• Checkstop
• Debug Port Hard Reset
No
Yes
Yes
Yes
Yes
Yes
Yes
Soft Reset (SRESET)
Sources:
• External Soft Reset
• Debug Port Soft Reset
• JTAG Reset
No
No
No
No
Yes
Yes
Yes
7.3
Data Coherency During Reset
The MPC561/MPC563 supports data coherency and avoids data corruption during reset. If a cycle is
executing when any SRESET or HRESET source is detected, then the cycle will either complete or will
not start before generating the corresponding reset control signal. There are reset sources, however, when
the MPC561/MPC563 generates an internal reset due to special internal situations where this protection is
not supported. See Section 7.4, “Reset Status Register (RSR).”
In the case of large operand size (32 or 16 bits) transactions to a smaller port size, the cycle is split into
two 16-bit or four 8-bit cycles. In this case, data coherency is assured and data will not be corrupted.
In the case where the core executes an unaligned load/store cycle which is broken down into multiple
cycles, data coherency is NOT assured between these cycles (i.e., data could be corrupted).
Contention may occur if a write access is in progress to external memory and SRESET/HRESET is
asserted and the external reset configuration word (RCW) is used. In this case, the external RCW drivers,
usually activated by HRESET/SRESET lines, will drive the data bus together with the MPC561/MPC563.
Thus the data in the RAM may be corrupted regardless of the data coherency mechanism in the
MPC561/MPC563.
Table 7-2. Reset Configuration Word and Data Corruption/Coherency
Reset Driven
HRESET
Reset to Use for Data
Coherency (EXT_RESET)
Comments
SRESET
MPC561/MPC563 Reference Manual, Rev. 1.2
7-4
Freescale Semiconductor
Reset
Table 7-2. Reset Configuration Word and Data Corruption/Coherency (continued)
Reset to Use for Data
Coherency (EXT_RESET)
Reset Driven
SRESET
HRESET
HRESET & SRESET
HRESET || SRESET
7.4
Comments
Provided only one of them is driven into the
MPC561/MPC563 at a time
Reset Status Register (RSR)
All of the reset sources are fed into the reset controller. The 16-bit reset status register (RSR) reflects the
most recent source, or sources, of reset. (Simultaneous reset requests can cause more than one bit to be set
at the same time.) This register contains one bit for each reset source. A bit set to logic one indicates the
type of reset that occurred.
Once set, individual bits in the RSR remain set until software clears them. Bits in the RSR can be cleared
by writing a one to the bit. A write of zero has no effect on the bit. The register can be read at all times.
The reset status register receives its default reset values during power-on reset. The RSR is powered by the
KAPWR pin.
MSB
0
LSB
1
2
3
4
5
6
7
8
9
10
11
12
Field EHRS ESRS LLRS SWRS CSRS DBHRS DBSRS JTRS OCCS ILBC GPOR GHRST GSRST
PORESET
HRESET
0
0000_0000_000
SRESET
0000_0000_0000
Addr
1
01
0000_0000
1
13 14
15
—
1
1
000
1
1
000
1
000
0x2F C288
OCCS will be set (1) if limp mode is enabled (SCCR[LME]=1).
Figure 7-1. Reset Status Register (RSR)
Table 7-3. Reset Status Register Bit Descriptions
Bits
Name
Description
0
EHRS1
External hard reset status
0 No external hard reset has occurred
1 An external hard reset has occurred
1
ESRS1
External soft reset status
0 No external soft reset has occurred
1 An external soft reset has occurred
2
LLRS
Loss of lock reset status
0 No enabled loss-of-lock reset has occurred
1 An enabled loss-of-lock reset has occurred
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-5
Reset
Table 7-3. Reset Status Register Bit Descriptions (continued)
1
Bits
Name
Description
3
SWRS
Software watchdog reset status
0 No software watchdog reset has occurred
1 A software watchdog reset has occurred
4
CSRS
Checkstop reset status
0 No enabled checkstop reset has occurred
1 An enabled checkstop reset has occurred
5
DBHRS
Debug port hard reset status
0 No debug port hard reset request has occurred
1 A debug port hard reset request has occurred
6
DBSRS
Debug port soft reset status
0 No debug port soft reset request has occurred
1 A debug port soft reset request has occurred
7
JTRS
JTAG reset status
0 No JTAG reset has occurred
1 A JTAG reset has occurred
8
OCCS
On-chip clock switch
0 No on-chip clock switch reset has occurred
1 An on-chip clock switch reset has occurred
9
ILBC
Illegal bit change. This bit is set when the MPC561/MPC563 changes any of the following bits
when they are locked:
LPM[0:1], locked by the LPML bit
MF[0:11], locked by the MFPDL bit
DIVF[0:4], locked by the MFPDL bit
10
GPOR
Glitch detected on PORESET pin. This bit is set when the PORESET pin is asserted for more
than 20ns
0 No glitch was detected on the PORESET pin
1 A glitch was detected on the PORESET pin
11
GHRST
Glitch detected on HRESET pin. This bit is set when the HRESET pin is asserted for more than
20ns
0 No glitch was detected on the HRESET pin
1 A glitch was detected on the HRESET pin
12
GSRST
Glitch detected on SRESET pin. If the SRESET pin is asserted for more than 20ns the GHRST
bit will be set. If an internal or external SRESET is generated the SRESET pin is asserted and
the GSRST bit will be set.
0 No glitch was detected on SRESET pin
1 A glitch was detected on SRESET pin.
13:15
—
Reserved
In the USIU RSR, if both EHRS and ESRS are set, the reset source is internal. The EHRS and ESRS bits in RSR
register are set for any internal reset source in addition to external HRESET and external SRESET events. If both
internal and external indicator bits are set, then the reset source is internal.
MPC561/MPC563 Reference Manual, Rev. 1.2
7-6
Freescale Semiconductor
Reset
7.5
7.5.1
Reset Configuration
Hard Reset Configuration
When a hard reset event occurs, the MPC561/MPC563 reconfigures its hardware system as well as the
development port configuration. The logical value of the bits that determine its initial mode of operation,
are sampled from the following:
• The external data bus pins DATA[0:31]
• An internal default constant (0x0000 0000)
• An internal NVM register value (UC3FCFIG). Available on the MPC563/MPC564 only.
If at the sampling time RSTCONF is asserted, then the configuration is sampled from the external data
bus. If RSTCONF is negated and a valid NVM value exists (UC3FCFIG[HC]=0), then the configuration
is sampled from the NVM register in the UC3F module. If RSTCONF is negated and no valid NVM value
exists (UC3FCFIG[HC]=1), then the configuration word is sampled from the internal default (all zeros).
HC will be “1” if the internal Flash is erased. Table 7-4 summarizes the reset configuration options.
Table 7-4. Reset Configuration Options
RSTCONF
Has Configuration (HC)
Internal Configuration Word
0
x
DATA[0:31] pins
1
0
NVM Flash EEPROM register (UC3FCFIG)
1
1
Internal data word default (0x0000 0000)
If the PRDS control bit in the PDMCR register is cleared and HRESET and RSTCONF are asserted, the
MPC561/MPC563 pulls the data bus low with a weak resistor. The user can overwrite this default by
driving the appropriate bit high. See Figure 7-2 for the basic reset configuration scheme.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-7
Reset
Has Configuration (HC)
Reset
Config.
Word
32
Flash
32
MUX
32
OE
Dx (Data line)
INT_RESET
Data
Coherency
EXT_RESET
(See Table 7-2)
HRESET/SRESET
RSTCONF
Figure 7-2. Reset Configuration Basic Scheme
During the assertion of the PORESET input signal, the chip assumes the default reset configuration. This
assumed configuration changes if the input signal RSTCONF is asserted when the PORESET is negated
or the CLKOUT starts to oscillate. To ensure that stable data is sampled, the hardware configuration is
sampled every eight clock cycles on the rising edge of CLKOUT with a double buffer. The setup time
required for the data bus is approximately 15 cycles (defined as Tsup in the following figures) and the
maximum rise time of HRESET should be less than six clock cycles. In systems where an external reset
configuration word and the TEXP output function are both required, RSTCONF should be asserted until
SRESET is negated.
Figure 7-3 to Figure 7-6 provide sample reset configuration timings.
NOTE
Timing diagrams in the following figures are not to scale.
MPC561/MPC563 Reference Manual, Rev. 1.2
7-8
Freescale Semiconductor
Reset
CLKOUT
PORESET
Internal PORESET
HRESET
RSTCONF
Tsup
Internal data[0:31]
Default
RSTCONF Controlled
Figure 7-3. Reset Configuration Sampling Scheme for “Short” PORESET Assertion, Limp Mode Disabled
CLKOUT
(Backup Clock)
PORESET
Internal
PORESET
512 clocks
HRESET
Tsup
RSTCONF
Internal data(0:31)
Default
RSTCONF Controlled
Figure 7-4. Reset Configuration Timing for “Short” PORESET Assertion, Limp Mode Enabled
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-9
Reset
CLKOUT
PORESET
PLL lock
Internal
PORESET
HRESET
Tsup
RSTCONF
Internal data[0:31]
Default
RSTCONF Controlled
Figure 7-5. Reset Configuration Timing for “Long” PORESET Assertion, Limp Mode Disabled
1
2
3
8
8
9
10
8
9
10
11
12
13
14
15
16
CLKOUT
HRESET
Maximum time of reset recognition
(maximum rise time - up to 6 clocks)
RSTCONF
DATA
Internal
reset
Reset Configuration Word
Tsup = Minimum Setup time of reset recognition = 15 clocks
Sample Data Configuration
Sample Data Configuration
Figure 7-6. Reset Configuration Sampling Timing Requirements
MPC561/MPC563 Reference Manual, Rev. 1.2
7-10
Freescale Semiconductor
Reset
7.5.2
Hard Reset Configuration Word (RCW)
Following is the hard reset configuration word that is sampled from the internal data bus,
data_sgpiod(0:31) on the negation of HRESET. If the external reset config word is selected (RSTCONF =
0), the internal data bus will reflect the state of external data bus. If the internal reset config word is selected
and neither of the Flash reset config words are enabled (UC3FCFIG[HC] = 1), the internal data bus is
internally driven with all zeros. The reset configuration word is not a register in the memory map. Most of
the bits in the configuration are located in registers in the SIU. Refer to Table 7-5 for a detailed description
of each control bit.
MSB
0
1
Field EARB
2
3
4
IP BDRV BDIS
5
6
BPS[0:1]
HRESET
7
8
—
9
10
11
DBGC[0:1]
—
12
13
14
ATWC EBDF[0:1]
15
—
0000_0000_0000_0000
LSB
16
17
Field PRPM
HRESET
18
SC
19
20
ETRE FLEN
21
22
EN_
EXC_
COMP1 COMP1
23
—
24
25
26
OERC
27
28
—
29
ISB
30
31
DME
0000_0000_0000_0000
Figure 7-7. Reset Configuration Word (RCW)
1
Available only on the MPC562/MPC564, software should write "0" to this bit for MPC561/MPC563.
Table 7-5. RCW Bit Descriptions
Bits
Name
Description
0
EARB
1
IP
Initial Interrupt Prefix — This bit defines the initial value of MSR[IP] immediately after reset.
MSR[IP] defines the Interrupt Table location. If IP is zero then the initial value of MSR[IP] is zero,
If the IP is one, then the initial value of MSR[IP] is one. Default value is zero. See Table 3-11 for
more information.
0 MSR[IP] = 0 after reset
1 MSR[IP] = 1 after reset
2
BDRV
Bus Pins Drive Strength — This bit determines the bus pins (address, data and control) driving
capability to be either full or reduced drive. The bus default drive strength is full; Upon default, it
also effects the CLKOUT drive strength to be full. See Table 6-7 for more information. BDRV
controls the default state of COM1 in the SIUMCR.
0 Full drive
1 Reduced drive
3
BDIS
Boot Disable — If the BDIS bit is set, then memory controller is not activated after reset. If it is
cleared then the memory controller bank 0 is active immediately after reset such that it matches
any addresses. If a write to the OR0 register occurs after reset this bit definition is ignored. The
default value is that the memory controller is enabled to control the boot with the CS0 pin. See
Section 10.7, “Global (Boot) Chip-Select Operation,” for more information.
0 Memory controller bank 0 is active and matches all addresses immediately after reset
1 Memory controller is not activated after reset.
External Arbitration — Refer to Section 9.5.7, “Arbitration Phase,” for a detailed description of
Bus arbitration. The default value is that internal arbitration hardware is used.
0 Internal arbitration is performed
1 External arbitration is assumed
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-11
Reset
Table 7-5. RCW Bit Descriptions (continued)
Bits
Name
Description
4:5
BPS
Boot Port Size — This field defines the port size of the boot device on reset (BR0[PS]). If a write
to the OR0 register occurs after reset this field definition is ignored. See Table 10-5 and
Table 10-8 for more information.
00 32-bit port (default)
01 8-bit port
10 16-bit port
11 Reserved
6:8
—
9:10
Reserved. These bits must not be high in the reset configuration word.
DBGC[0:1] Debug Pins Configuration — See Section 6.2.2.1.1, “SIU Module Configuration Register
(SIUMCR),” for this field definition. The default value is that these pins function as: VFLS[0:1], BI,
BR, BG and BB. See Table 6-8.
11
—
Reserved.
12
ATWC
Address Type Write Enable Configuration — The default value is that these pins function as WE
pins. See Table 6-7.
0 WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]
1 WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
13:14
EBDF
External Bus Division Factor — This field defines the initial value of the external bus frequency.
The default value is that CLKOUT frequency is equal to that of the internal clock (no division).
See Table 8-9.
151
—
16
PRPM
Peripheral Mode Enable — This bit determines if the chip is in peripheral mode. A detailed
description is in Table 6-13 The default value is no peripheral mode enabled.
17:18
SC
Single Chip Select — This field defines the mode of theMPC562/MPC564. See Table 6-10.
00 Extended chip, 32 bits data
01 Extended chip, 16 bits data
10 Single chip and show cycles (address)
11 Single chip
19
ETRE
Exception Table Relocation Enable — This field defines whether the Exception Table Relocation
feature in the BBC is enabled or disabled; The default state for this field is disabled. For more
details, see Table 4-4.
202,3
FLEN
Flash Enable — This field determines whether the on-chip Flash memory is enabled or disabled
out of reset. The default state is disabled, which means that by default, the boot is from external
memory. Refer to Table 6-12 for more details.
0 Flash disabled — boot is from external memory
1 Flash enabled
21
EN_
COMP4
Enable Compression — This bit enables the operation of the MPC562/MPC564 with compressed
code. The default state is disabled. See Table 4-4 and <XrefBlue>Appendix A,
“MPC562/MPC564 Compression Features."
22
EXC_
COMP4
Exception Compression — This bit determines the operation of the MPC562/MPC564 with
exceptions. If this bit is set, then the MPC562/MPC564 assumes that ALL the exception routines
are in compressed code. The default indicates the exceptions are all non-compressed. See
Table 4-4 and <XrefBlue>Appendix A, “MPC562/MPC564 Compression Features."
23
—
Reserved. This bit must be 0 in the reset configuration word.
Reserved. This bit must not be high in the reset configuration word.
MPC561/MPC563 Reference Manual, Rev. 1.2
7-12
Freescale Semiconductor
Reset
Table 7-5. RCW Bit Descriptions (continued)
Bits
Name
Description
24:25
OERC
26:27
—
28:30
ISB
Internal Space Base Select — This field defines the initial value of the ISB field in the IMMR
register. A detailed description is in Table 6-12. The default state is that the internal memory map
is mapped to start at address 0x0000_0000. This bit must not be high in the reset configuration
word.
31
DME
Dual Mapping Enable — This bit determines whether Dual mapping of the internal Flash is
enabled. For a detailed description refer to Table 10-11. The default state is that dual mapping is
disabled.
0 Dual mapping disabled
1 Dual mapping enabled
Other Exceptions Relocation Control — These bits effect only if ETRE was enabled. See
Table 4-2. Relocation offset:
00 Offset 0
01 Offset 64 Kbytes
10 Offset 512 Kbytes
11 Offset to 0x003F E000
Reserved
1
Bit 15 always comes from the internal Flash Reset Configuration Word (MPC563 only).
This bit should not be set on the MPC561/MPC562.
3 This bit is HC if read from the internal Flash Reset Configuration Word. See Section 21.2.3.1, “Reset Configuration
Word (UC3FCFIG)."
4 Available only on the MPC562/MPC564, software should write "0" to this bit for MPC561/MPC563.
2
7.5.3
Soft Reset Configuration
When a soft reset event occurs, the MPC561/MPC563 reconfigures the development port. Refer to
Chapter 23, “Development Support,” for details.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-13
Reset
MPC561/MPC563 Reference Manual, Rev. 1.2
7-14
Freescale Semiconductor
Chapter 8
Clocks and Power Control
The main timing reference for the MPC561/MPC563 can monitor any of the following:
• An external crystal with a frequency of 4 or 20 MHz
• An external frequency source with a frequency of 4 MHz
• An external frequency source at the system frequency
The system operating frequency is generated through a programmable phase-locked loop, the system PLL
(SPLL). The SPLL runs at twice the system speed. The SPLL is programmable in integer multiples of the
input frequency to generate the internal (VCO/2) operating frequency. A pre-divider before the SPLL
enables the division of the high frequency crystal oscillator. The internal operating SPLL frequency should
be at least 30 MHz. It can be divided by a power-of-two divider to generate the system operating
frequencies.
In addition to the system clock, the clocks submodule provides the following:
• TMBCLK to the time base (TB) and decrementer (DEC)
• PITRTCLK to the periodic interrupt timer (PIT) and real-time clock (RTC)
The oscillator, TB, DEC, RTC, and the PIT are powered from the keep alive power supply (KAPWR) pin.
This allows the counters to continue to increment/decrement at the oscillator frequency even when the
main power to the MCU is off. While the power is off, the PIT may be used to signal the power supply IC
to enable power to the system at specific intervals. This is the power-down wake-up feature. When the chip
is not in power-down low-power mode, the KAPWR is powered to the same voltage value as the voltage
of the I/O buffers and logic.
The MPC561/MPC563 clock module consists of the main crystal oscillator, the SPLL, the low-power
divider, the clock generator, the system low-power control block, and the limp mode control block. The
clock module receives control bits from the system clock control register (SCCR), change of lock interrupt
register (COLIR), the PLL low-power and reset-control register (PLPRCR), and the PLL.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-1
Clocks and Power Control
Figure 8-1 is a functional block diagram of the clock unit.
MODCK[1:3]
XFC VDDSYN VSSSYN
EXTCLK
VCOOUT
2:1
MUX
2:1 MUX
SPLL
Lock
GCLK2
TBCLK
System
Low
Power
Control
3:1 MUX
(/4 or /16)
Low
Power
Dividers
(1/2N)
Clock
Drivers
GCLK1 / GCLK2
System Clock
GCLK1C / GCLK2C
System Clock
to RCPU and BBC
CLKOUT
Drivers
ENGCLK
TMBCLK
Driver
Backup Clock
Oscillator Loss
Detector
3:1
MUX
/4 or
/256
XTAL
EXTAL
TMBCLK
RTC / PIT Clock
and Driver
PITRTCLK
Main Clock
Oscillator
Figure 8-1. Clock Unit Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
8-2
Freescale Semiconductor
Clocks and Power Control
8.1
System Clock Sources
The system clock can be provided by the main system oscillator, an external clock input, or the backup
clock (BUCLK) on-chip ring oscillator, see Figure 8-1.
The main system oscillator uses either a 4-MHz or 20-MHz crystal to generate the PLL reference clock.
When the main system oscillator output is the timing reference to the system PLL, skew elimination
between the XTAL/EXTAL pins and CLKOUT is not guaranteed. There is also an on-chip crystal
feedback resistor on the MPC561/MPC563; however, space should be reserved for an off-chip resistor to
allow for future configurations. Figure 8-2 illustrates the main system oscillator crystal configuration.
The external clock input (EXTCLK pin) can receive a clock signal from an external source. The clock
frequency must be in the range of 3-5 MHz or, for 1:1 mode, at the system frequency of at least 15 MHz.
When the external clock input is the timing reference to the system PLL, the skew between the EXTCLK
pin and the CLKOUT is less than ± 1 ns.
The backup clock on-chip ring oscillator allows the MPC561/MPC563 to function with a less precise
clock. When operating from the backup clock, the MPC561/MPC563 is in limp mode. This enables the
system to continue minimum functionality until the system is fixed. The BUCLK frequency is
approximately 11 MHz for the MPC561/MPC563 (see Appendix F, “Electrical Characteristics” for the
complete frequency range).
For normal operation, at least one clock source (EXTCLK or main system oscillator) must be active. A
configuration with both clock sources active is possible as well. At this configuration EXTCLK provides
the system clock and main system oscillator provides the PITRTCLK. The input of an unused timing
reference (EXTCLK or EXTAL) must be grounded.
XTAL
EXTAL
1 MΩ
CL
1
CL
1. Resistor is not currently required on the board but space should be available for its addition in the future.
Figure 8-2. Main System Oscillator Crystal Configuration
8.2
System PLL
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock
input, a feature which offers two benefits: reduces the overall electromagnetic interference generated by
the system, and the ability to oscillate at different frequencies reduces cost by eliminating the need to add
an additional oscillator to a system.
The PLL can perform the following functions:
• Frequency multiplication
• Skew elimination
• Frequency division
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-3
Clocks and Power Control
8.2.1
Frequency Multiplication
The PLL can multiply the input frequency by any integer between one and 4096. The multiplication factor
depends on the value of the MF[0:11] bits in the PLPRCR register. While any integer value from one to
4096 can be programmed, the resulting VCO output frequency must be at least 15 MHz. The multiplication
factor is set to a predetermined value during power-on reset as defined in Table 8-1.
8.2.2
Skew Elimination
The PLL is capable of eliminating the skew between the external clock entering the chip (EXTCLK) and
both the internal clock phases and the CLKOUT pin, making it useful for tight synchronous timings. Skew
elimination is active only when the PLL is enabled and programmed with a multiplication factor of one or
two (MF = 0 or 1). The timing reference to the system PLL is the external clock input (EXTCLK pin).
8.2.3
Pre-Divider
A pre-divider before the phase comparator enables additional system clock resolution when the crystal
oscillator frequency is 20 MHz. The division factor is determined by the DIVF[0:4] bits in the PLPRCR.
8.2.4
PLL Block Diagram
As shown in Figure 8-3, the reference signal, OSCCLK, goes to the phase comparator. The phase
comparator controls the direction (up or down) that the charge pump drives the voltage across the external
filter capacitor (XFC). The direction depends on whether the feedback signal phase lags or leads the
reference signal. The output of the charge pump drives the VCO. The output frequency of the VCO is
divided down and fed back to the phase comparator for comparison with the reference signal, OSCCLK.
The MF values, zero to 4095, are mapped to multiplication factors of one to 4096. Note that when the PLL
is operating in 1:1 mode (refer to Table 8-1), the multiplication factor is one (MF = 0). The PLL output
frequency is twice the maximum system frequency. This double frequency is needed to generate GCLK1
and GCLK2 clocks. On power-up, with a 4-MHz or 20-MHz crystal and the default MF settings,
VCOOUT will be 40 MHz and the system clock will be 20 MHz.
The equation for VCOOUT is:
VCOOUT =
OSCCLK
x (MF + 1) x 2
DIVF + 1
NOTE
When operating with the backup clock, the system clock (and CLKOUT) is
one-half of the ring oscillator frequency, (i.e., the system clock is
approximately 11 MHz). The time base and PIT clocks will be twice the
system clock frequency.
In the case of initial system power up, or if KAPWR is lost, an external circuit must assert power on reset
(PORESET). Once KAPWR is valid, PORESET must be asserted long enough to allow the external
oscillator to start up and stabilize for the device to come out of reset in normal (non limp) mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-4
Freescale Semiconductor
Clocks and Power Control
If limp mode is enabled (by the MODCK[1:3] pins), and PORESET is negated before the external
oscillator has started up, the backup clock, BUCLK, will be used to clock the device. The device will start
to run in limp mode. Software can then switch the clock mode from BUCLK to PLL. If an application
requires that the device always comes out of reset in normal mode, PORESET should be asserted long
enough for the external oscillator to start up. The maximum start-up time of an external oscillator is given
in Appendix F, “Electrical Characteristics” and PORESET should be asserted for this time and at least an
additional 100, 000 input clock cycles.
If limp mode is disabled at reset, a short reset of at least 3 µs is enough to obtain normal chip operation,
because the BUCLK will not start. The system will wait for the external oscillator to start-up and stabilize.
The PLL will begin to lock once PORESET has been negated, assuming stable KAPWR and VDDSYN
power supplies and internal oscillator (or external clock). The PLL maximum lock time is determined by
the input clock to the phase comparator. The PLL locks within 500 input clock cycles if the PLPRCR[MF]
<= 4. The PLL locks within 1000 input clock cycles if PLPRCR[MF] >4. HRESET will be released 512
system clock cycles after the PLL locks.
Whenever PORESET is asserted, the MF bits are set according to Table 8-1, and the division factor high
frequency (DFNH) and division factor low frequency (DFNL) bits in SCCR are set to the value of 0 (÷1
for DFNH and ÷2 for DFNL).
XFC
VDDSYN
OSCCLK
Division Factor
DIVF[0:4]
Feedback
Phase
Comparator
Up
Down
VSSSYN
Charge
Pump
VCO
VCOOUT
Clock
Delay
Multiplication Factor
MF[0:11]
Figure 8-3. System PLL Block Diagram
8.2.5
PLL Pins
The following pins are dedicated to the PLL operation:
• VDDSYN — Drain voltage. This is the VDD dedicated to the analog PLL circuits. The voltage
should be well-regulated and the pin should be provided with an extremely low impedance path to
the VDD power rail. VDDSYN should be bypassed to VSSSYN by a 0.1 µF capacitor located as
close as possible to the chip package.
• VSSSYN — Source voltage. This is the VSS dedicated to the analog PLL circuits. The pin should
be provided with an extremely low impedance path to ground. VSSSYN should be bypassed to
VDDSYN by a 0.1 µF capacitor located as close as possible to the chip package.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-5
Clocks and Power Control
•
8.3
XFC — External filter capacitor. XFC connects to the off-chip capacitor for the PLL filter. One
terminal of the capacitor is connected to XFC, and the other terminal is connected to VDDSYN.
— The off-chip capacitor must have the following values:
– 0 < MF + 1 < 4 (1130 x (MF + 1) – 80) pF
– MF + 1 ≥ 42100 x (MF + 1) pF
Where MF = the value stored on MF[0:11]. This is one less than the desired
frequency multiplication.
System Clock During PLL Loss of Lock
At reset, until the SPLL is locked, the SPLL output clock is disabled.
During normal operation (once the PLL has locked), either the oscillator or an external clock source is
generating the system clock. In this case, if loss of lock is detected and the LOLRE (loss of lock reset
enable) bit in the PLPRCR is cleared, the system clock source continues to function as the PLL’s output
clock. The USIU timers can operate with the input clock to the PLL, so that these timers are not affected
by the PLL loss of lock. Software can use these timers to measure the loss-of-lock period. If the timer
reaches the user-preset software criterion, the MPC561/MPC563 can switch to the backup clock by setting
the switch to backup clock (STBUC) bit in the SCCR, provided the limp mode enable (LME) bit in the
SCCR is set.
If loss of lock is detected during normal operation, assertion of HRESET (for example, if LOLRE is set)
disables the PLL output clock until the lock condition is met. During hard reset, the STBUC bit is set as
long as the PLL lock condition is not met and clears when the PLL is locked. If STBUC and LME are both
set, the system clock switches to the backup clock (BUCLK), and the chip operates in limp mode until
STBUC is cleared.
Every change in the lock status of the PLL can generate a maskable interrupt.
NOTE
When the VCO is the system clock source, chip operation is unpredictable
while the PLL is unlocked. Note further that a switch to the backup clock is
possible only if the LME bit in the SCCR is set.
8.4
Low-Power Divider
The output of the PLL is sent to a low-power divider block. (In limp mode the BUCLK is sent to a
low-power divider block.) This block generates all other clocks in normal operation, but has the ability to
divide the output frequency of the VCO before it generates the general system clocks sent to the rest of the
MPC561/MPC563. The PLL VCOOUT is always divided by at least two.
The purpose of the low-power divider block is to allow reduction and restoration of the operating
frequencies of different sections of the MPC561/MPC563 without losing the PLL lock. Using the
low-power divider block, full chip operation can still be obtained, but at a lower frequency. This is called
gear mode. The selection and speed of gear mode can be changed at any time, with changes occurring
immediately.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-6
Freescale Semiconductor
Clocks and Power Control
The low-power divider block is controlled in the system clock control register (SCCR). The default state
of the low-power divider is to divide all clocks by one. Thus, for a 40-MHz system, the general system
clocks are each 40 MHz. Whenever power-on reset is asserted, the MF bits are set according to Table 8-1,
and the division factor high frequency (DFNH) and division factor low frequency (DFNL) bits in SCCR
are set to the value of 0 (÷1 for DFNH and ÷2 for DFNL).
8.5
Internal Clock Signals
The internal clocks generated by the clocks module are shown in Figure 8-4. The clocks module also
generates the CLKOUT and ENGCLK external clock signals. The PLL synchronizes these signals to each
other. The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR.
When the backup clock is functioning as the system clock, the backup clock is automatically selected as
the time base clock source and is twice the MPC561/MPC563 system clock.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-7
Clocks and Power Control
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
T1
T2
T3
T4
Figure 8-4. MPC561/MPC563 Clocks
Note that GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than GCLK1 and GCLK2.
This is to enable the external bus operation at lower frequencies (controlled by EBDF in the SCCR).
GCLK2_50 always rises simultaneously with GCLK2. When DFNH = 0, GCLK2_50 has a 50% duty
cycle. With other values of DFNH or DFNL, the duty cycle is less than 50%. Refer to Figure 8-7.
GCLK1_50 rises simultaneously with GCLK1. When the MPC561/MPC563 is not in gear mode, the
falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50. EBDF determines the
division factor between GCLK1/GCLK2 and GCLK1_50/GCLK2_50.
During power-on reset, the MODCK1, MODCK2, and MODCK3 pins determine the clock source for the
PLL and the clock drivers. These pins are latched on the positive edge of PORESET. Their values must be
stable as long as this line is asserted. The configuration modes are shown in Table 8-1. MODCK1 specifies
MPC561/MPC563 Reference Manual, Rev. 1.2
8-8
Freescale Semiconductor
Clocks and Power Control
the input source to the SPLL (main system oscillator or EXTCLK). MODCK1, MODCK2, and MODCK3
together determine the multiplication factor at reset and the functionality of limp mode.
If the configuration of PITRTCLK and TMBCLK and the SPLL multiplication factor is to remain
unchanged in power-down low-power mode, the MODCK signals should not be sampled at wake-up from
this mode. In this case the PORESET pin should remain negated and HRESET should be asserted during
the power supply wake-up stage.
When MODCK1 is cleared, the output of the main oscillator is selected as the input to the SPLL. When
MODCK1 is asserted, the external clock input (EXTCLK pin) is selected as the input to the SPLL. In all
cases, the system clock frequency (freqgclk2) can be reduced by the DFNH[0:2] bits in the SCCR. Note
that freqgclk2(max) occurs when the DFNH bits are cleared.
The TBS bit in the SCCR selects the time base clock to be either the SPLL input clock or GCLK2. When
the backup clock is functioning as the system clock, the backup clock is automatically selected as the time
base clock source.
The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR. When
the backup clock is functioning as the system clock, the backup clock is automatically selected as the time
base clock source.
When the PORESET pin is negated (driven to a high value), the MODCK1, MODCK2, and MODCK3
values are not affected. They remain the same as they were defined during the most recent power-on reset.
Table 8-1 shows the clock configuration modes during power-on reset (PORESET asserted).
NOTE
The MODCK[1:3] are shared functions with IRQ[5:7]. If IRQ[5:7] are used
as interrupts, the interrupt source should be removed during PORESET to
insure the MODCK pins are in the correct state on the rising edge of
PORESET.
Table 8-1. Reset Clocks Source Configuration
Default Values after PORESET
MODCK[1:3]1
000
001
010
011
SPLL Options
LME
RTSEL
RTDIV
MF + 1
PITCLK
Division
TMBCLK
Division
0
0
0
1
4
4
Used for testing purposes.
16
Normal operation, PLL enabled.
Main timing reference is crystal
osc (20 MHz).
Limp mode disabled.
4
Normal operation, PLL enabled.
Main timing reference is crystal
osc (4 MHz).
Limp mode enabled.
16
Normal operation, PLL enabled.
Main timing reference is crystal
osc (20 MHz).
Limp mode enabled.
0
1
1
0
0
0
1
1
1
1
5
1
256
256
256
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-9
Clocks and Power Control
Table 8-1. Reset Clocks Source Configuration (continued)
Default Values after PORESET
MODCK[1:3]1
100
101
110
111
1
LME
RTSEL
RTDIV
PITCLK
Division
MF + 1
SPLL Options
TMBCLK
Division
Normal operation, PLL enabled.
1:1 Mode
0
0
1
1
1
1
1
1
1
1
256
5
16
4
Normal operation, PLL enabled.
Main timing reference is EXTCLK (3-5 MHz).
Limp mode disabled.
16
Normal operation, PLL enabled.
1:1 Mode
Main timing reference is EXTCLK pin (>15MHz)
Limp mode enabled.
256
1
256
Main timing reference is EXTCLK pin (>15MHz)
Limp mode disabled.
indicates MODCK pins value during power-on reset
NOTE
The reset value of the PLL pre-divider is one.
The values of the PITRTCLK clock division and TMBCLK clock division can be changed by software.
The RTDIV bit value in the SCCR register defines the division of PITRTCLK. All possible combinations
of the TMBCLK divisions are listed in Table 8-2.
Table 8-2. TMBCLK Divisions1
1
8.5.1
SCCR[TBS]
MF + 1
TMBCLK
Division
1
—
16
0
1, 2
16
0
>2
4
To ensure correct operation of the time base, keep the system clock to time
base clock ratio above 4 and always set SCCR[TBS] = 1 when running on
the backup clock (limp mode).
General System Clocks
The general system clocks (GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and GCLK2_50) are the
basic clock supplied to all modules and sub-modules on the MPC561/MPC563. GCLK1C and GCLK2C
are supplied to the RCPU and to the BBC. GCLK1C and GCLK2C are stopped when the chip enters the
doze-low power mode. GCLK1 and GCLK2 are supplied to the SIU and the clock module. The external
bus clock GCLK2_50 is the same as CLKOUT. The general system clock defaults to VCO/2 = 20 MHz
(assuming a 20-MHz system frequency) with default power-on reset MF values.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-10
Freescale Semiconductor
Clocks and Power Control
The general system clock frequency can be switched between different values. The highest operational
frequency can be achieved when the system clock frequency is determined by DFNH (CSRC bit in the
PLPRCR is cleared) and DFNH = 0 (division by one). The general system clock can be operated at a low
frequency (gear mode) or a high frequency. The DFNL bits in SCCR define the low frequency. The DFNH
bits in SCCR define the high frequency.
The frequency of the general system clock can be changed dynamically with the system clock control
register (SCCR), as shown in Figure 8-5.
VCO/2 (e.g., 40 MHz)
O
DFNH Divider
DFNH
Normal
O
O
General System Clock
DFNL Divider
DFNL
O
Low Power
Figure 8-5. General System Clocks Select
The frequency of the general system clock can be changed “on the fly” by software. The user may simply
cause the general system clock to switch to its low frequency. However, in some applications, there is a
need for a high frequency during certain periods. Interrupt routines, for example, may require more
performance than the low frequency operation provides, but must consume less power than in maximum
frequency operation. The MPC561/MPC563 provides a method to automatically switch between low and
high frequency operation whenever one of the following conditions exists:
• There is a pending interrupt from the interrupt controller. This option is maskable by the PRQEN
bit in the SCCR.
• The (POW) bit in the MSR is clear in normal operation. This option is maskable by the PRQEN
bit in the SCCR.
When neither of these conditions exists and the CSRC bit in PLPRCR is set, the general system clock
switches automatically back to the low frequency.
Abrupt changes in the divide ratio can cause linear changes in the operating currents of the
MPC561/MPC563.
When the multiplication factor (PLPRCR[MF]) for the PLL is changed, the PLL stops all internal clocks
until the PLL adjusts to the new frequency. This includes stopping the clock to the watchdog timer,
therefore SWT cannot reset the system during this period.
When the clock stops, the current consumed by the device from VDD will fall; it will then rise sharply
when the PLL turns on the PLL output clocks at the new frequency. These abrupt changes in the divide
ratio can cause linear changes in the operating currents of the device. Insure that the proper power supply
filtering is available to handle changes instantaneously. The gear modes (DFNH and DFNL) can be used
to temporarily decrease the system frequency to minimize the demand on the power supply when the MF
or DIVF multiply/divide ratio is changed.
When the general system clock is divided, its duty cycle is changed. One phase remains the same (for
example, 12.5 ns at 40 MHz) while the other becomes longer.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-11
Clocks and Power Control
NOTE
CLKOUT does not have a 50% duty cycle when the general system clock is
divided. The CLKOUT wave form is the same as that of GCLK2_50.
GCLK1 Divide by 1
GCLK2 Divide by 1
GCLK1 Divide by 2
GCLK2 Divide by 2
GCLK1 Divide by 4
GCLK2 Divide by 4
Figure 8-6. Divided System Clocks Timing Diagram
The system clocks GCLK1 and GCLK2 frequency is:
FREQsysmax
FREQ sys = ------------------------------------------------------------------DFNH
DFNL + 1
(2
)or ( 2
)
where FREQsysmax = VCOOUT/2
Therefore, the complete equation for determining the system clock frequency is:
System Frequency=
OSCCLK
DIVF + 1
x
(MF + 1)
(2DNFH) or (2DFNL + 1)
2
x
2
MPC561/MPC563 Reference Manual, Rev. 1.2
8-12
Freescale Semiconductor
Clocks and Power Control
The clocks GCLK1_50 and GCLK2_50 frequency is:
1
FREQsysmax
FREQ 50 = ------------------------------------------------------------------- x -------------------------EBDF
+1
DFNH
DFNL + 1
(2
)or ( 2
)
Figure 8-7 shows the timing of USIU clocks when DFNH = 1 or DFNL = 0.
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
Figure 8-7. Clocks Timing For DFNH = 1 (or DFNL = 0)
8.5.2
Clock Out (CLKOUT)
CLKOUT has the same frequency as the general system clock (GCLK2_50). Unlike the main system clock
GCLK1/GCLK2 however, CLKOUT (and GCLK2_50) represents the external bus clock, and thus will be
one-half of the main system clock if the external bus is running at half speed (EBDF = 0b01). The
CLKOUT frequency (system frequency) defaults to VCO/2. CLKOUT can drive full, half, or quarter
strength; it can also be disabled. The drive strength is controlled in the system clock and reset-control
register (SCCR) by the COM[0:1] and CQDS bits. (See Section 8.11.1, “System Clock Control Register
(SCCR)”). Disabling or decreasing the strength of CLKOUT can reduce power consumption, noise, and
electromagnetic interference on the printed circuit board.
When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low state (provided
that BUCS = 0).
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-13
Clocks and Power Control
8.5.3
Engineering Clock (ENGCLK)
ENGCLK is an output clock with a 50% duty cycle. Its frequency defaults to VCO/128, which is 1/64 of
the main system frequency. ENGCLK frequency can be programmed to the main system frequency
divided by a factor from one to 64, as controlled by the ENGDIV[0:5] bits in the SCCR. ENGCLK can
drive full- or half-strength, or it can also be disabled (remaining in the high state). The drive strength is
controlled by the EECLK[0:1] bits in the SCCR. Disabling ENGCLK can reduce power consumption,
noise, and electromagnetic interference on the printed circuit board.
NOTE
The full strength ENGCLK setting (SCCR[EECLK]=0b01) selects a 5-V
driver while the half-strength selection (SCCR[EECLK]=0b00) is a 2.6-V
driver.
When the PLL is acquiring lock, the ENGCLK signal is disabled and remains in the low state (provided
that BUCS = 0).
NOTE
Skew elimination between CLKOUT and ENGCLK is not guaranteed.
8.6
Clock Source Switching
For limp mode support, clock source switching is supported. If for any reason the clock source for the chip
is not functioning, the option is to switch the system clock to the backup clock ring oscillator, BUCLK.
This circuit consists of a loss-of-clock detector, which sets the LOCS status bit and LOCSS sticky bit in
the PLPRCR. If the LME bit in the SCCR is set, whenever LOCS is asserted, the clock logic switches the
system clock automatically to BUCLK and asserts hard reset to the chip. Switching the system clock to
BUCLK is also possible by software setting the STBUC bit in SCCR. Switching from limp mode to normal
system operation is accomplished by clearing STBUC and LOCSS bits. This operation also asserts hard
reset to the chip.
At HRESET assertion, if the PLL output clock is not valid, the BUCLK will be selected until software
clears LOCSS bit in SCCR. At HRESET assertion, if the PLL output clock is valid, the system will switch
to oscillator/external clock. If during HRESET the PLL loses lock or the clock frequency becomes slower
than the required value, the system will switch to the BUCLK. After HRESET negation the PLL lock
condition does not effect the system clock source selection.
If the LME bit is clear, the switch to the backup clock is disabled and assertion of STBUC bit is ignored.
If the chip is in limp mode, clearing the LME bit switches the system to normal operation and asserts hard
reset to the chip.
Figure 8-8 describes the clock switching control logic. Table 8-3 summarizes the status and control for
each state.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-14
Freescale Semiconductor
Clocks and Power Control
LME = 1
poreset_b = 0
poreset_b = 0
1,BUCLK
poreset_b = 1
LME = 1
else
buclk_enable = 1
& hreset_b = 0
bu
cl
hr k_e
es na
et b
_b le
= =1
1
LME = 0
hreset_b = 0
LOCS=0
buclk_enable = 0
& hreset_b = 0
bu
hreset_b = 1
hresert_b = 0
bu
c
hr lk_e
es n
et ab
_b l e
= =0
1
buclk_enable=0
& hreset_b=0
4, osc
cl
k
as _en
se ab
rt
l
hr e =
es 1
et
_b
3,BUCLK
hreset_b = 1
else
2,BUCLK
6,BULCK
buclk_enable = 1
& hreset_b = 0
5, osc
else
Figure 8-8. Clock Source Switching Flow Chart
NOTE
buclk_enable = (STBUC | LOC) and LME lock indicates loss of lock status
bit (LOCS) for all cases and loss of clock sticky bit (LOCSS) when state 3
is active. When buclk_enable is changed, the chip asserts HRESET to
switch the system clock to BUCLK or PLL.
At PORESET negation, if the PLL is not locked, the loss-of-clock sticky bit
(LOCSS) is asserted, and the chip should operate with BUCLK.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-15
Clocks and Power Control
The switching from state three to state four is accomplished by clearing the
STBUC and LOCSS bits. If the switching is done when the PLL is not
locked, the system clock will not oscillate until lock condition is met.
Table 8-3. Status of Clock Source
STATE
PORESET
HRESET
LME
LOCS
(status)
LOCSS
(sticky)
STBUC
BUCS
Chip
Clock
Source
1
0
0
1
0
0
0
1
BUCLK
2
1
0
1
0/1
0
0
1
BUCLK
1
x2
0/1
0/1
1
BUCLK
0
x2
0
0
Oscillator
2
1
3
4
1
2
1
1
1
0
0/1
5
1
1
0/1
0
x
0
0
Oscillator
6
1
0
1
0/1
1
0/1
1
BUCLK
At least one of the two bits, LOCSS or BUCS, must be asserted (one) in this state.
X = don’t care.
The default value of the LME bit is determined by MODCK[1:3] during assertion of the PORESET line.
The configuration modes are shown in Table 8-1.
8.7
Low-Power Modes
The LPM and other bits in the PLPRCR are encoded to provide one normal operating mode and four
low-power modes. In normal and doze modes the system can be in high state with frequency defined by
the DFNH bits, or in the low state with frequency defined by the DFNL bits. The normal-high operating
mode is the state out of reset. This is also the state of the bits after the low-power mode exit signal arrives.
There are four low-power modes:
• Doze mode
• Sleep mode
• Deep-sleep mode
• Power-down mode
8.7.1
Entering a Low-Power Mode
Low-power modes are enabled by setting the MSR[POW] and clearing the SCCR[LPML]. Once enabled,
a low-power mode is entered by setting the LPM bits to the appropriate value. This can be done only in
one of the normal modes. The user cannot change the PLPRCR[LPM or CSRC] when the MCU is in doze
mode.
NOTE
Higher than desired currents during low-power mode can be avoided by
executing a mullw instruction before entering the low-power mode, i.e.,
anytime after reset and prior to entering the low-power mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-16
Freescale Semiconductor
Clocks and Power Control
Table 8-6 summarizes the control bit settings for the different clock power modes.
Table 8-4. Power Mode Control Bit Settings
8.7.2
Power Mode
LPM[0:1]
CSRC
TEXPS
Normal-high
00
0
X
Normal-low (“gear”)
00
1
X
Doze-high
01
0
X
Doze-low
01
1
X
Sleep
10
X
X
Deep-sleep
11
X
1
Power-down
11
X
0
Power Mode Descriptions
Table 8-5 describes the clock frequency and chip functionality for each power mode.
Table 8-5. Power Mode Descriptions
8.7.3
Power Pins that Need
to be Powered-Up
Operation Mode
SPLL
Clocks
Functionality
Normal-high
Active
Full frequency ÷
2DFNH
Full functions not in use
are shut off
Normal-low (“gear”)
Active
Full frequency ÷
2DFNL+1
Doze-high
Active
Full frequency ÷
2DFNH
Doze-low
Active
Full frequency ÷
2DFNL+1
Sleep
Active
Not active
Deep-sleep
Not active
Not active
KAPWR, IRAMSTBY
Power-down
Not active
Not active
KAPWR, IRAMSTBY
SRAM Standby
Not active
Not active
All On
All On
Enabled: RTC, PIT,
TB and DEC,
controller
Disabled: extended
core
(RCPU, BBC, FPU)
KAPWR, VDDSYN,
VDD, QVDDL, NVDDL,
IRAMSTBY
Enabled: RTC, PIT, TB
and DEC
KAPWR, VDDSYN,
IRAMSTBY
SRAM data
retention
KAPWR, VDDSYN,
VDD, QVDDL, NVDDL,
IRAMSTBY
IRAMSTBY
Exiting from Low-Power Modes
Exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt
generated by the interrupt controller. Any enabled asynchronous interrupt clears the LPM bits but does not
change the PLPRCR[CSRC] bit.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-17
Clocks and Power Control
The return to normal-high mode from normal-low, doze-high, low, and sleep mode is accomplished with
the asynchronous interrupt. The sources of the asynchronous interrupt are:
• Asynchronous wake-up interrupt from the interrupt controller
• RTC, PIT, or time base interrupts (if enabled)
• Decrementer exception
The system responds quickly to asynchronous interrupts. The wake-up time from normal-low, doze-high,
doze-low, and sleep mode caused by an asynchronous interrupt or a decrementer exception is only three
to four clock cycles of maximum system frequency. In 40-MHz systems, this wake-up requires 75 to 100
ns. The asynchronous wake-up interrupt from the interrupt controller is level sensitive one. It will therefore
be negated only after the reset of interrupt cause in the interrupt controller.
The timers’ (RTC, PIT, time base, or decrementer) interrupts indications set status bits in the PLPRCR
(TMIST). The clock module considers this interrupt to be pending asynchronous interrupt as long as the
TMIST is set. The TMIST status bit should be cleared before entering any low-power mode.
Table 8-7 summarizes wake-up operation for each of the low-power modes.
Table 8-6. Power Mode Wake-Up Operation
Wake-up
Method
Return Time from Wake-up
Event to Normal-High
Normal-low (“gear”)
Software
or
Interrupt
Doze-high
Interrupt
Asynchronous interrupts:
3-4 maximum system cycles
Synchronous interrupts:
3-4 actual system cycles
Doze-low
Interrupt
Sleep
Interrupt
3-4 maximum system clocks
Deep-sleep
Interrupt
< 500 Oscillator Cycles
125 µs – 4 MHz
25 µs – 20 MHz
Power-down
Interrupt
< 500 oscillator cycles + power
supply wake-up
IRAMSTBY
External
Power-on sequence
Operation Mode
8.7.3.1
Exiting from Normal-Low Mode
In normal mode (as well as doze mode), if the PLPRCR[CSRC] bit is set, the system toggles between low
frequency (defined by PLPRCR[DFNL]) and high frequency (defined by PLPRCR[DFNH]. The system
switches from normal-low mode to normal-high mode if either of the following conditions is met:
• An interrupt is pending from the interrupt controller; or
• The MSR[POW] bit is cleared (power management is disabled).
When neither of these conditions are met, the PLPRCR[CSRC] bit is set, and the asynchronous interrupt
status bits are reset, the system returns to normal-low mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-18
Freescale Semiconductor
Clocks and Power Control
8.7.3.2
Exiting from Doze Mode
The system changes from doze mode to normal-high mode whenever an interrupt is pending from the
interrupt controller.
8.7.3.3
Exiting from Deep-Sleep Mode
The system switches from deep-sleep mode to normal-high mode if any of the following conditions is met:
• An interrupt is pending from the interrupt controller
• An interrupt is requested by the RTC, PIT, or time base
• A decrementer exception
In deep-sleep mode the PLL is disabled. The wake-up time from this mode is up to 500 PLL input
frequency clocks. In one-to-one mode the wake-up time may be up to 100 PLL input frequency clocks.
For a PLL input frequency of 4 MHz, the wake-up time is less than 125 µs.
8.7.3.4
Exiting from Power-Down Mode
Exit from power-down mode is accomplished through hard reset. External logic should assert HRESET in
response to the TEXPS bit being set and TEXP pin being asserted. The TEXPS bit is set by an enabled
RTC, PIT, time base, or decrementer interrupt. The hard reset should be asserted for no longer than the
time it takes for the power supply to wake-up in addition to the PLL lock time. When the TEXPS bit is
cleared (and the TEXP signal is negated), assertion of hard reset sets the bit, causes the pin to be asserted,
and causes an exit from power-down low-power mode. Refer to Section 8.8.3, “Keep-Alive Power” for
more information.
8.7.3.5
Low-Power Modes Flow
Figure 8-9 shows the flow among the different power modes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-19
Clocks and Power Control
(MSR[POW]+Interrupt)+PLPRCR[CSRC]
Software 1
Normal-Low
LPM = 00, CSRC = 1
Software 1
Doze-Low
LPM = 01, CSRC = 1
((MSR[POW]+Interrupt))*CSRC3
Interrupt
Wake-up: 3 - 4 SysFreq
Clocks
Software 1
Software
1
Software 1
Software 1
Doze-High
LPM = 01, CSRC = 0/1
Asynchronous
Interrupts
Wake-up: 3 - 4 Sys
Freqmax Clocks
LPM = 00
CSRC = 0/1
Sleep Mode
LPM = 10, CSRC = 0
Deep-Sleep Mode
LPM = 11, CSRC = 0,
TEXPS = 1
Power-Down Mode
LPM = 11, CSRC = 0,
TEXPS = 02
Normal
High Mode
Async. Wake-up or
RTC/PIT/TB/DEC Interrupt
Wake-up: 500 Input
Frequency Clocks
RTC/PIT/TB/DEC Interrupt
followed by External Hard Reset
Software 1
Hard Reset
1Software
is active only in normal-high/low modes.
TEXPS receives the zero value by writing one. Writing of zero has no effect on TEXPS.
3The switch from normal-high to normal-low is enable only if the conditions to asynchronous interrupt are cleared.
2
Figure 8-9. Low-Power Modes Flow Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
8-20
Freescale Semiconductor
Clocks and Power Control
8.8
8.8.1
Basic Power Structure
General Power Supply Definitions
KAPWR and VSS power the following clock unit modules: oscillator, PITRTCLK and TMBCLK
generation logic, timebase, decrementer, RTC, PIT, system clock control register (SCCR), low-power and
reset-control register (PLPRCR), and reset status register (RSR). All other circuits are powered by the
normal supply pins: VDD, QVDDL, NVDDL, VDDF, VDDSYN, VFLASH, VDDH and VSS. The power
supply for each block is listed in Table 8-7.
Table 8-7. Power Supplies
Circuit
CLKOUT
SPLL (digital),
System low-power control
Internal logic
Clock drivers
Power Supply
NVDDL/QVDDL
SPLL (analog)
VDDSYN
Main oscillator
Reset machine
Limp mode mechanism
Register control
SCCR, PLLRCR and RSR
PPC RTC, PIT, TB, and DEC
KAPWR
CALRAM, DPTRAM, DECRAM
1
IRAMSTBY/VDD1
Keep-alive power is supplied by IRAMSTBY, but run
current is provided through VDD
The following are the relations between different power supplies:
• VDD = QVDDL = NVDDL = VDDSYN = VDDF = 2.6 V ± 0.1 V
• KAPWR = VDD ± 0.2 V (during normal operation)
• VDDH = VDDA = VFLASH = 5.0 ± 5%
• KAPWR = 2.6 ± 0.1 V (during standby operation)
• IRAMSTBY = current source > 50 µA, < 1.75 mA (average)
NOTE
The power supply inputs VDD, QVDDL, NVDDL, VDDSYN, and VDDF
should all be connected to the same 2.6-V power supply. The KAPWR
power supply can be connected to a 2.6-V standby power supply. If
KAPWR is not connected to a standby power supply, it should be connected
to the same power supply as VDD. IRAMSTBY is the input to an
approximately 1.7 volt regulator. It must be connected through a resistor to
a standby power supply. The power supply inputs VDDH and VFLASH
should be connected to the same 5.0-V supply. VDDA can be isolated from
VDDH, but should be the same approximate voltage.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-21
Clocks and Power Control
8.8.2
Chip Power Structure
The MPC561/MPC563 provides a wide range of possibilities for power supply connections. Figure 8-11
illustrates the different power supply sources for each of the basic units on the chip.
8.8.2.1
NVDDL
This supplies the final output stage of the 2.6-V pad output drivers.
8.8.2.2
QVDDL
This supplies all pad logic and pre-driver circuitry, except for the final output stage of the 2.6-V pad output
drivers.
8.8.2.3
VDD
VDD powers the internal logic of the MPC561/MPC563, nominally 2.6V.
8.8.2.4
VDDSYN, VSSSYN
The charge pump and the VCO of the SPLL are fed by a separate 2.6-V power supply (VDDSYN) in order
to improve noise immunity and achieve a high stability in its output frequency. VSSSYN provides an
isolated ground reference for the PLL.
8.8.2.5
KAPWR
The oscillator, time base counter, decrementer, periodic interrupt timer and the real-time clock are fed by
the KAPWR rail. This allows the external power supply unit to disconnect all other sub-units of the MCU
in low-power deep-sleep mode. The TEXP pin (fed by the same rail) can be used by the external power
supply unit to switch between sources. The IRQ[6:7]/MODCK[2:3], IRQ5/MODCK1, XTAL, EXTAL,
EXTCLK, PORESET, HRESET, SRESET, and RSTCONF/TEXP input pins are powered by KAPWR.
Circuits, including pull-up resisters, driving these inputs should be powered by KAPWR.
8.8.2.6
VDDA, VSSA
VDDA supplies power to the analog subsystems of the QADC64E_A and QADC64E_B modules; it is
nominally 5.0 V. VSSA is the ground reference for the analog subsystems.
8.8.2.7
VFLASH
VFLASH supplies the UC3F normal operating voltage. It is nominally 5.0 V. The MPC561 has no
VFLASH signal.
8.8.2.8
VDDF, VSSF
VDDF provides internal core voltage to the UC3F Flash module; it should be a nominal 2.6V. VSSF
provides an isolated ground for the UC3F Flash module. The MPC561 has no VDDF or VSSF signal.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-22
Freescale Semiconductor
Clocks and Power Control
8.8.2.9
VDDH
VDDH provides power for the 5-V I/O operations. It is a nominal 5.0 V.
8.8.2.10
IRAMSTBY
IRAMSTBY is the data retention power supply for all on-board RAM arrays (CALRAM, DPTRAM,
DECRAM). It has a shunt regulator circuit of approximately 1.7 volts that diverts excess current to ground
in order to regulate voltage on the IRAMSTBY power supply pin. Run current is supplied by normal VDD.
IRAMSTBY must be connected to a positive power supply, via a register, and bypassed by a capacitor to
ground (see Figure 8-10. The resistor should sized according to the following equations:
(VSUPPLYMIN – 1.95 V)
> 50 µA
RSUPPLY
(VSUPPLYMAX – 1.35 V)
<1.75 mA (average)
RSUPPLY
where VSUPPLYMIN is the lowest supply voltage and VSUPPLYMAX is the highest possible supply voltage.
See note in the VSRMCR[ZOREG] bit description.
VSUPPLY
RSUPPLY
IRAMSTBY
CSUPPLY
Figure 8-10. IRAMSTBY Regulator Circuit
8.8.2.11
VSS
VSS provides the ground reference for the MPC561/MPC563.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-23
Clocks and Power Control
VDD
VFLASH VDDF VDDA VSSA
I/O
IRAMSTBY
VDDH
CALRAM
VDD
FLASH*
QADC
Internal Logic
Oscillator,
PIT, RTC, TB,
and DEC
DPTRAM
DECRAM
PLL
Clock Control
TEXP
KAPWR
VDD
NVDDL
QVDDL
Note: Flash is not implemented on the
MPC561.
VDDSYN
Figure 8-11. Basic Power Supply Configuration
8.8.3
8.8.3.1
Keep-Alive Power
Keep-Alive Power Configuration
Figure 8-12 is an example of a switching scheme for an optimized low-power system. SW1 and SW2 can
be unified in only one switch if VDDSYN and VDD/NVDDL/QVDDL are supplied by the same source.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-24
Freescale Semiconductor
Clocks and Power Control
SW1
O
VDDSYN
Main Power
Supply
2.6 V
O
O
VDD
SW2
O
MPC561/MPC563
TEXP
Switch
Logic
IRAMSTBY
Power Supply
IRAMSTBY
KAPWR
2.6-V
Backup
Power
Supply
Figure 8-12. External Power Supply Scheme
The MPC561/MPC563 asserts the TEXP signal, if enabled, when the RTC or TB time value matches the
value programmed in the associated alarm register or when the PIT or DEC value reaches zero. The TEXP
signal is negated when the TEXPS status bit is written to one.
The KAPWR power supply feeds the main crystal oscillator (OSCM). The condition for the main crystal
oscillator stability is that the power supply value changes slowly. The maximum slope must be less than 5
mV per oscillation cycle (τ > 200-300/freqoscm).
8.8.3.2
Keep-Alive Power Registers Lock Mechanism
The USIU timer, clocks, reset, power, decrementer, and time base registers are powered by the KAPWR
supply. When the main power supply is disconnected after power-down mode is entered, the value stored
in any of these registers is preserved. If power-down mode is not entered before power disconnect, there
is a chance of data loss in these registers. To minimize the possibility of data loss, the MPC561/MPC563
includes a key mechanism that ensures data retention as long as a register is locked. While a register is
locked, writes to this register are ignored.
Each of the registers in the KAPWR region have a key that can be in one of two states: open or locked. At
power-on reset the following keys are locked by default: RTC, RTSEC, RTCAL, and RTCSC. All other
registers are unlocked. Each key has an address associated with it in the internal map.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-25
Clocks and Power Control
A write of 0x55CCAA33 to the associated key register changes the key to the open state. A write of any
other data to this location changes the key to the locked state. The key registers are write-only. A read of
the key register has undefined side effects and may be interpreted as a write that locks the associated
register.
Table 8-8 lists the registers powered by KAPWR and the associated key registers.
Table 8-8. KAPWR Registers and Key Registers
KAPWR Register
Address or
SPR Number
Register
Associated Key Register
Address
Register
0x2F C200
Time Base Status and Control (TBSCR)
See Table 6-18 for bit descriptions.
0x2F C300
Time Base Status and Control Key
(TBSCRK)
0x2F C204
Time Base Reference 0 (TBREF0)
See Section 6.2.2.4.3, “Time Base
Reference Registers (TBREF0 and
TBREF1)” for bit descriptions.
0x2F C304
Time Base Reference 0 Key (TBREF0K)
0x2F C208
Time Base Reference 1 (TBREF1)
See Section 6.2.2.4.3, “Time Base
Reference Registers (TBREF0 and
TBREF1) for bit descriptions.
0x2F C308
Time Base Reference 1 Key (TBREF1K)
0x2F C220
Real Time Clock Status and Control
(RTCSC)
See Table 6-19 for bit descriptions. This
register is locked after reset by default.
0x2F C320
Real Time Clock Status and Control Key
(RTCSCK)
0x2F C224
Real Time Clock (RTC)
See Section 6.2.2.4.6, “Real-Time Clock
Register (RTC)” for bit descriptions. This
register is locked after reset by default.
0x2F C324
Real Time Clock Key (RTCK)
0x2F C228
Real Time Alarm Seconds (RTSEC)
Reserved. This register is locked after
reset by default.
0x2F C328
Real Time Alarm Seconds Key (RTSECK)
0x2F C22C
Real Time Alarm (RTCAL)
See Section 6.2.2.4.7, “Real-Time Clock
Alarm Register (RTCAL)” for bit
descriptions. This register is locked after
reset by default.
0x2F C32C
Real Time Alarm Key (RTCALK)
0x2F C240
PIT Status and Control (PISCR)
See Table 6-20 for bit descriptions.
0x2F C340
PIT Status and Control Key (PISCRK)
0x2F C244
PIT Count (PITC)
See Table 6-21 for bit descriptions.
0x2F C344
PIT Count Key (PITCK)
0x2F C280
System Clock Control Register (SCCR)
See Table 8-9 for bit descriptions.
0x2F C380
System Clock Control Key (SCCRK)
0x2F C284
PLL Low-Power and Reset-Control
Register (PLPRCR)
See Table 8-11 for bit descriptions.
0x2F C384
PLL Low-Power and Reset-Control
Register Key (PLPRCRK)
MPC561/MPC563 Reference Manual, Rev. 1.2
8-26
Freescale Semiconductor
Clocks and Power Control
Table 8-8. KAPWR Registers and Key Registers (continued)
KAPWR Register
Address or
SPR Number
0x2F C288
Associated Key Register
Register
Address
Register
Reset Status Register (RSR)
See Table 7-3 for bit descriptions.
0x2F C388
Reset Status Register Key (RSRK)
SPR 22
Decrementer
See Section 3.9.5, “Decrementer Register
(DEC)” for bit descriptions.
0x2F C30C
Time Base and Decrementer Key (TBK)
SPR 268, 269,
284, 285,
Time Base
See Section 6.2.2.4.2, “Time Base SPRs
(TB),” for bit descriptions.
Figure 8-13 illustrates the process of locking or unlocking a register powered by KAPWR.
Power-On Reset
(Valid for other registers)
Open
Write to the Key 0x55CCAA33
Write to the key other value
Locked
Power On Reset
(Valid for RTC, RTSEC,
RTCAL and RTCSC)
Figure 8-13. Keep-Alive Register Key State Diagram
8.9
IRAMSTBY Supply Failure Detection
A special circuit for IRAMSTBY supply failure detection is provided. In the case of supply failure
detection, the dedicated sticky bits LVSRS in the VSRMCR register are asserted. Software can read or
clear these bits. The user should enable the detector and then clear these bits. If any of the LVSR bits are
read as one, then a power failure of IRAMSTBY has occurred. The circuit is capable of detecting supply
failure below a voltage level to be determined. Also, enable/disable control bit for the IRAMSTBY
detector may be used to disconnect the circuit and save the detector power consumption.
8.10
Power-Up/Down Sequencing
Figure 8-14 and Figure 8-15 detail the power-up sequencing for MPC561/MPC563 during normal
operation. Note that for each of the conditions detailing the voltage relationships the absolute bounds of
the minimum and maximum voltage supply cannot be violated; that is, the value of VDDL cannot fall
below 2.5 V or exceed 2.7 V, and the value of VDDH cannot fall below 4.75 V or exceed 5.25 V for normal
operation. Power consumption during power up sequencing will be below the operating power
consumption.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-27
Clocks and Power Control
During the power down sequence PORESET needs to be asserted while VDD, NVDDL, and QVDDL are
at a voltage greater than or equal to 2.5 V. Below this voltage the power supply chip can be turned off.
If the turn-off voltage of the power supply chip is greater than 0.74 V for the 2.6-V supply and greater than
0.8 V for the 5-V supply, then the circuitry inside the MPC561/MPC563 will act as a load to the respective
supply and will discharge the supply line down to these values. Since the 2.6-V logic represents a larger
load to the supply chip, the 2.6-V supply line will decay faster than the 5-V supply line.
Power On
Operating
See Note 1.
Power Off
See Note 2.
VDDH
VDD, NVVL,
QVDDL
KAPWR
IRAMSTBY
VDDA, VRH
VDDSYN
VFLASH (5 V)
PORESET
HRESET
1
2
3
4
5
VDDH ≥ QVDDL - 0.5 V
VDDA can lag VDDH, and VDDSYN can lag QVDDL, but both must be at a valid level before resets are negated.
If keep-alive functions are NOT used, then when system power is on: KAPWR = QVDDL ± 0.1 V; KAPWR ≤ 2.7 V
If keep-alive functions ARE used, then KAPWR = QVDDL = NVDDL = 2.6 V ± 0.1 V when system power is on
KAPWR = 2.6 V ± 0.1 V when system power is off. IRAMSTBY should be powered prior to the other supplies. If
IRAMSTBY is powered at the same time as the other supplies, it should be allowed to stabilize before PORESET
is negated. Normal system power is defined as QVDDL = VDD = VDDF = VDDSYN = KAPWR = 2.6 ± 0.1 V and
VDDA = VDDH = VFLASH = 5.0 ± 0.25 V. Flash programming requirements are the same as normal system
power. VFLASH should always be 5.0 ± 0.25 V. Note: Flash is not implemented on the MPC561.
Do not hold the 2.6-V supplies at ground while VDDH/VDDA is ramping to 5 V.
If 5 V is applied before the 2.6-V supply, all 5-V outputs will be in indeterminate states until the 2.6-V supply
reaches a level that allows reset to be distributed throughout the device If 5 V is applied before the 2.6-V supply,
all 5-V outputs will be in indeterminate states until the 2.6-V supply reaches a level that allows reset to be
distributed throughout the device
Figure 8-14. No Standby, No KAPWR, All System Power-On/Off
MPC561/MPC563 Reference Manual, Rev. 1.2
8-28
Freescale Semiconductor
Clocks and Power Control
No Battery Connect Battery Power On
Operating
Power Off
No Battery
VDDH
VDD, NVVL,
QVDDL
KAPWR
IRAMSTBY
VDDA, VRH
VDDSYN
VFLASH (5 V)
PORESET
HRESET
1
2
3
4
5
VDDH ≥ QVDDL - 0.5 V
VDDA can lag VDDH, and VDDSYN can lag QVDDL, but both must be at a valid level before resets are negated.
If keep-alive functions are NOT used, then when system power is on: KAPWR = QVDDL ± 0.1 V; KAPWR ≤ 2.7 V
If keep-alive functions ARE used, then KAPWR = QVDDL = NVDDL = 2.6 V ± 0.1 V when system power is on
KAPWR = 2.6 V ± 0.1 V when system power is off. IRAMSTBY should be powered prior to the other supplies. If
IRAMSTBY is powered at the same time as the other supplies, it should be allowed to stabilize before PORESET
is negated. Normal system power is defined as QVDDL = VDD = VDDF = VDDSYN = KAPWR = 2.6 ± 0.1 V and
VDDA = VDDH = VFLASH = 5.0 ± 0.25 V. Flash programming requirements are the same as normal system
power. VFLASH should always be 5.0 ± 0.25 V. Note: Flash is not implemented on the MPC561.
Do not hold the 2.6-V supplies at ground while VDDH/VDDA is ramping to 5 V.
If 5 V is applied before the 2.6-V supply, all 5-V outputs will be in indeterminate states until the 2.6-V supply
reaches a level that allows reset to be distributed throughout the device If 5 V is applied before the 2.6-V supply,
all 5-V outputs will be in indeterminate states until the 2.6-V supply reaches a level that allows reset to be
distributed throughout the device
Figure 8-15. Standby and KAPWR, Other Power-On/Off
NOTE
For more detailed information on power sequencing see Section F.8,
“Power-Up/Down Sequencing.”
8.11
8.11.1
Clocks Unit Programming Model
System Clock Control Register (SCCR)
The SPLL has a 32-bit control register, SCCR, which is powered by keep-alive power.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-29
Clocks and Power Control
MSB
0
1
Field DBCT
2
COM
PORESET
1
0
ID21
HRESET
U
0
ID21
3
4
5
6
7
8
4
DCSLR MFPDL LPML TBS RTDIV
0000
1
9
10
12
13
14
15
STBUC CQDS PRQEN RTSEL BUCS EBDF[0:1] LME
1
0
EQ22
1
Unaffected
Addr
11
1
0
Unaffected
ID[13:14]1 EQ33
ID[13:14]1
U
0x2F C280
LSB
16
17
18
19
EECLK[0:1]
PORESET
0
0
20
21
22
23
ENGDIV[0:5]
1
HRESET
1
1
1
24
25
—
1
26
27
28
DFNL[0:2]
1
—
29
30
31
DFNH[0:2]
0000_0000
Unaffected
0000_0000
1 The hard reset value is a reset configuration word value, extracted from the indicated internal data bus lines. Refer to Section
7.5.2,
“Hard Reset Configuration Word (RCW).”
2 EQ2 = MODCK1
3 EQ3 = (MODCK1 AND MODCK2 AND MODCK3) | (MODCK1 AND MODCK2 AND MODCK3) | (MODCK1 AND MODCK2 AND
MODCK3). See Table 8-1.
4 RTDIV will be 0 if MODCK[1:3] = 000.
Figure 8-16. System Clock and Reset Control Register (SCCR)
NOTE
COM[1] bit default value is determined during by BDRV reset
configuration bit; See Section 7.5.2, “Hard Reset Configuration Word
(RCW).”
Table 8-9. SCCR Bit Descriptions
Bits
Name
Description
0
DBCT
Disable backup clock for timers. The DBCT bit controls the timers clock source while the
chip is in limp mode. If DBCT is set, the timers clock (TMBLCK, PITRCLK) source will not
be the backup clock, even if the system clock source is the backup clock ring oscillator. The
real-time clock source will be EXTAL or EXTCLK according to RTSEL bit (see description
in bit 11 below), and the time base clocks source will be determined according to TBS bit
and MODCK1.
0 If the chip is in limp mode, the timer clock source is the backup (limp) clock
1 The timer clock source is either the external clock or the crystal (depending on the current
clock mode selected)
1:2
COM
Clock Output Mode – The COM and CQDS bits control the output buffer strength of the
CLKOUT and external bus pins. When both COM bits are set the CLKOUT pin is held in
the high (1) state and external bus pins are driven at reduced drive. These bits can be
dynamically changed without generating spikes on the CLKOUT and external bus pins. If
CLKOUT pin is not connected to external circuits, set both bits (disabling CLKOUT) to
minimize noise and power dissipation. The default value for COM[1] is determined by the
BDRV bit in the reset configuration word. See Table 7-5. For CLKOUT control see
Table 8-10.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-30
Freescale Semiconductor
Clocks and Power Control
Table 8-9. SCCR Bit Descriptions (continued)
Bits
Name
Description
3
DCSLR
Disable clock switching at loss of lock during reset. When DCSLR is clear and limp mode
is enabled, the chip will switch automatically to the backup clock if the PLL losses lock
during HRESET. When DCSLR is asserted, a PLL loss-of-lock event does not cause clock
switching. If HRESET is asserted and DCSLR is set, the chip will not negate HRESET until
the PLL acquires lock.
0 Enable clock switching if the PLL loses lock during reset
1 Disable clock switching if the PLL loses lock during reset
4
MFPDL
MF and pre-divider lock. Setting this control bit disables writes to the MF and DIVF bits.
This helps prevent runaway software from changing the VCO frequency and causing the
SPLL to lose lock. In addition, to protect against hardware interference, a hardware reset
will be asserted if these fields are changed while LPML is asserted. This bit is writable once
after power-on reset.
0 MF and DIVF fields are writable
1 MF and DIVF fields are locked
5
LPML
LPM lock. Setting this control bit disables writes to the LPM and CSRC control bits. In
addition, for added protection, a hardware reset is asserted if any mode is entered other
than normal-high mode. This protects against runaway software causing the MCU to enter
low-power modes. (The MSR[POW] bit provides additional protection). LPML is writable
once after power-on reset.)
0 LPM and CSRC bits are writable
1 LPM and CSRC bits are locked and hard reset will occur if the MCU is not in normal-high
mode
6
TBS
7
RTDIV
RTC (and PIT) clock divider. At power-on reset this bit is cleared if MODCK[1:3] are all low;
otherwise the bit is set.
0 RTC and PIT clock divided by 4
1 RTC and PIT clock divided by 256
8
STBUC
Switch to backup clock control. When software sets this bit, the system clock is switched
to the on-chip backup clock ring oscillator, and the chip undergoes a hard reset. The
STBUC bit is ignored if LME is cleared.
0 Do not switch to the backup clock ring oscillator
1 Switch to backup clock ring oscillator
9
CQDS
Clock quarter drive strength — The COM and CQDS bits control the output buffer strength
of the CLKOUT, see Table 8-10.
10
PRQEN
Power management request enable
0 Remains in the lower frequency (defined by DFNL) even if the power management bit in
the MSR is reset (normal operational mode) or if there is a pending interrupt from the
interrupt controller
1 Switches to high frequency (defined by DFNH) when the power management bit in the
MSR is reset (normal operational mode) or there is a pending interrupt from the interrupt
controller
Time base source.
0 Source is OSCCLK divided by either 4 or 16
1 Source is system clock divided by 16
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-31
Clocks and Power Control
Table 8-9. SCCR Bit Descriptions (continued)
Bits
Name
Description
11
RTSEL
RTC circuit input source select. At power-on reset RTSEL receives the value of the
MODCK1 signal. Refer to Table 8-1. Note that if the chip is operating in limp mode (BUCS
= 0), the RTSEL bit is ignored, and the backup clock is the clock source for the RT and PIT
clocks
0 OSCM clock is selected as input to RTC and PIT
1 EXTCLK clock is selected as the RTC and PIT clock source
12
BUCS
Backup clock status. This status bit indicates the current system clock source. When loss
of clock is detected and the LME bit is set, the clock source is the backup clock and this bit
is set. When the STBUC bit and LME bit are set, the system switches to the backup clock
and BUCS is set.
0 System clock is not the backup clock
1 System clock is the backup clock
13:14
EBDF[0:1]
External bus division factor. These bits define the frequency division factor between
(GCLK1 and GCLK2) and (GCLK1_50 and GCLK2_50). CLKOUT is similar to GCLK2_50.
The GCLK2_50 and GCKL1_50 are used by the external bus interface and controller in
order to interface to the external system. The EBDF bits are initialized during hard reset
using the hard reset configuration mechanism.
00 CLKOUT is GCKL2 divided by 1
01 CLKOUT is GCKL2 divided by 2
1x Reserved
Note: If EBDF > 0, an external burst access with short setup timing will corrupt any USIU
register load/store. Refer to Section 10.2.6, “Reduced Data Setup Time.”
15
LME
Limp mode enable. When LME is set, the loss-of-clock monitor is enabled and any
detection of loss of clock will switch the system clock automatically to backup clock. It is
also possible to switch to the backup clock by setting the STBUC bit.
If LME is cleared, the option of using limp mode is disabled. The loss of clock detector is
not active, and any write to STBUC is ignored.
The LME bit is writable once, by software, after power-on reset, when the system clock is
not backup clock (BUCS = 0).
During power-on reset, the value of LME is determined by the MODCK[1:3] bits. (Refer to
Table 8-1.)
0 Limp mode disabled
1 Limp mode enabled
16:17
EECLK[0:1]
Enable engineering clock. This field controls the output buffer voltage of the ENGCLK pin.
When both bits are set the ENGCLK pin is held in the high state. These bits can be
dynamically changed without generating spikes on the ENGCLK pin. If ENGCLK is not
connected to external circuits, set both bits (disabling ENGCLK) to minimize noise and
power dissipation. For measurement purposes the backup clock (BUCLK) can be driven
externally on the ENGCLK pin.
00 Engineering clock enabled, 2.6 V output buffer
01 Engineering clock enabled (slew rate controlled), 5 V output buffer
10 BUCLK is the output on the ENGCLK 2.6 V output buffer
11 Engineering clock disabled
18:23
ENGDIV[0:5] Engineering clock division factor. These bits define the frequency division factor between
VCO/2 and ENGCLK. Division factor can be from 1 (ENGDIV = 000000) to 64 (ENGDIV =
111111). These bits can be read and written at any time. They are not affected by hard
reset but are cleared during power-on reset.
NOTE: If the engineering clock division factor is not a power of two, synchronization
between the system and ENGCLK is not guaranteed.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-32
Freescale Semiconductor
Clocks and Power Control
Table 8-9. SCCR Bit Descriptions (continued)
Bits
Name
24
—
25:27
DFNL[0:2]
28
—
29:31
DFNH
Description
Reserved
Division factor low frequency. The user can load these bits with the desired divide value
and the CSRC bit to change the frequency. Changing the value of these bits does not result
in a loss of lock condition. These bits are cleared by power-on or hard reset. Refer to
Section 8.5.1, “General System Clocks” and Figure 8-5 for details on using these bits.
000 Divide by 2
001 Divide by 4
010 Divide by 8
011 Divide by 16
100 Divide by 32
101 Divide by 64
110 Reserved
111 Divide by 256
Reserved
Division factor high frequency. These bits determine the general system clock frequency
during normal mode. Changing the value of these bits does not result in a loss of lock
condition. These bits are cleared by power-on or hard reset. The user can load these bits
at any time to change the general system clock rate. Note that the GCLKs generated by
this division factor are not 50% duty cycle (i.e. CLKOUT).
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Reserved
Table 8-10. COM and CQDS Bits Functionality
8.11.2
COM[0:1]
CQDS
Function
00
x
Clock Output Enabled Full-Strength Output Buffer, Bus pins full
drive
01
0
Clock Output Enabled Half-Strength Output Buffer, Bus pins
reduced drive
01
1
Clock Output Enabled Quarter-Strength Output Buffer, Bus pins
reduced drive
10
x
Clock Output Disabled, Bus pins full drive
11
x
Clock Output Disabled, Bus pins reduced drive
PLL, Low-Power, and Reset-Control Register (PLPRCR)
The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered by the keep-alive
power supply.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-33
Clocks and Power Control
MSB
0
1
2
3
Field
4
5
6
7
8
9
10
11
12
13
14
15
MF
— LOCS LOCSS SPLS
PORESET
0000_0000_0000 or 0000_0000_1000
0000
HRESET
Unaffected
Addr
0x2F C284
LSB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Field SPLSS TEXPS TEXP_INV TMIST — CSRC LPM CSR LOLRE —
PORESET
0
1
HRESET
U
1
30
31
DIVF
00_0000_0000_0000
U
0
U
000
Unaffected
—
Unaffected
Figure 8-17. PLL, Low-Power, and Reset-Control Register (PLPRCR)
Table 8-11. PLPRCR Bit Descriptions
Bits
Name
Description
0:11
MF
Multiplication factor bits. The output of the VCO is divided to generate the feedback signal to
the phase comparator. The MF bits control the value of the divider in the SPLL feedback loop.
The phase comparator determines the phase shift between the feedback signal and the
reference clock. This difference results in either an increase or decrease in the VCO output
frequency.
The MF bits can be read and written at any time. However, this field can be write-protected
by setting the MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the MF bits
causes the SPLL to lose lock. Also, the MF field should not be modified when entering or
exiting from low power mode (LPM change), or when back-up clock is active.
The normal reset value for the DFNH bits is zero (divide by 1). When the PLL is operating in
one-to-one mode, the multiplication factor is set to x1 (MF = 0).
12
—
Reserved
13
LOCS
Loss of clock status. When the oscillator or external clock source is not at the minimum
frequency, the loss-of-clock circuit asserts the LOCS bit. This bit is cleared when the
oscillator or external clock source is functioning normally. This bit is reset only on power-on
reset. Writes to this bit have no effect.
0 No loss of oscillator is currently detected
1 Loss of oscillator is currently detected
14
LOCSS
Loss of clock sticky. If, after negation of PORESET, the loss-of-clock circuit detects that the
oscillator or external clock source is not at a minimum frequency, the LOCSS bit is set.
LOCSS remains set until software clears it by writing a one to it. A write of zero has no effect
on this bit. The reset value is determined during hard reset. The STBUC bit will be set
provided the PLL lock condition is not met when HRESET is asserted, and cleared if the PLL
is locked when HRESET is asserted.
0 No loss of oscillator has been detected
1 Loss of oscillator has been detected
15
SPLS
System PLL lock status bit
0 SPLL is currently not locked
1 SPLL is currently locked
MPC561/MPC563 Reference Manual, Rev. 1.2
8-34
Freescale Semiconductor
Clocks and Power Control
Table 8-11. PLPRCR Bit Descriptions (continued)
Bits
Name
Description
16
SPLSS
SPLL lock status sticky bit. An out-of-lock sets the SPLSS bit. The bit remains set until
software clears it by writing a one to it. A write of zero has no effect on this bit. The bit is
cleared at power-on reset. This bit is not affected due to a software initiated loss-of-lock (MF
change and entering deep-sleep or power-down mode). The SPLSS bit is not affected by
hard reset.
0 SPLL has remained in lock
1 SPLL has gone out of lock at least once (not due to software-initiated loss of lock)
17
TEXPS
Timer expired status bit. This bit controls whether the chip negates the TEXP pin in
deep-sleep mode, thus enabling external circuitry to switch off the VDD (power-down mode).
When LPM = 11, CSRC = 0, and TEXPS is high, the TEXP pin remains asserted. When LPM
= 11, CSRC = 0, and TEXPS is low, the TEXPS pin is negated.
To enable automatic wake-up TEXPS is asserted when one of the following occurs:
• The PIT is expired
• The real-time clock alarm is set
• The time base clock alarm is set
• The decrementer exception occurs
• The bit remains set until software clears it by writing a one to it. A write of zero has no
effect on this bit. TEXPS is set by power-on or hard reset.
0 TEXP is negated in deep-sleep mode
1 TEXP pin remains asserted always
18
TEXP_INVP Timer Expired Pin Inversed Polarity – The TEX_INVP bit controls whether the polarity of the
TEXP pin will be active high (normal default) or active low.
0 The TEXP pin is active high
1 The TEXP pin is active low
19
TMIST
Timers interrupt status.TMIST is set when an interrupt from the RTC, PIT, TB or DEC occurs.
The TMIST bit is cleared by writing a one to it. Writing a zero has no effect on this bit. The
system clock frequency remains at its high frequency value (defined by DFNH) if the TMIST
bit is set, even if the CSRC bit in the PLPRCR is set (DFNL enabled) and conditions to switch
to normal-low mode do not exist. This bit is cleared during power-on or hard reset.
0 No timer expired event was detected
1 A timer expire event was detected
20
—
21
CSRC
22:23
LPM
Low-power mode select. These bits are encoded to provide one normal operating mode and
four low-power modes. In normal and doze modes, the system can be in high state
(frequency determined by the DFNH bits) or low state (frequency defined by the DFNL bits).
The LPM field can be write-protected by setting the LPM and CSRC lock (LPML) bit in the
SCCR Refer to Table 8-4 and Table 8-5.
24
CSR
Checkstop reset enable. If this bit is set, then an automatic reset is generated when the
RCPU signals that it has entered checkstop mode, unless debug mode was enabled at reset.
If the bit is clear and debug mode is not enabled, then the USIU will not do anything upon
receiving the checkstop signal from the RCPU. If debug mode is enabled, then the part
enters debug mode upon entering checkstop mode. In this case, the RCPU will not assert
the checkstop signal to the reset circuitry. This bit is writable once after soft reset.
0 No reset will occur when checkstop is asserted
1 Reset will occur when checkstop is asserted
Reserved
Clock source. This bit is cleared at hard reset.
0 General system clock is determined by the DFNH value
1 General system clock is determined by the DFNL value
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-35
Clocks and Power Control
Table 8-11. PLPRCR Bit Descriptions (continued)
Bits
Name
Description
25
LOLRE
Loss of lock reset enable
0 Loss of lock does not cause HRESET assertion
1 Loss of lock causes HRESET assertion
Note: if limp mode is enabled, use the COLIR feature instead of setting the LOLRE bit. See
Section 8.11.3, “Change of Lock Interrupt Register (COLIR).”
26
—
27:31
DIVF
8.11.3
Reserved
The DIVF bits control the value of the pre-divider in the SPLL circuit. The DIVF bits can be
read and written at any time. However, the DIVF field can be write-protected by setting the
MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the DIVF bits causes the SPLL
to lose lock.
Change of Lock Interrupt Register (COLIR)
The COLIR is 16-bit read/write register. It controls the change of lock interrupt generation, and is used for
reporting a loss of lock interrupt source. It contains the interrupt request level and the interrupt status bit.
This register is readable and writable at any time. A status bit is cleared by writing a one (writing a zero
does not affect a status bit’s value). The COLIR is mapped into the MPC561/MPC563 USIU register map.
MSB
0
LSB
1
Field
2
3
4
5
COLIRQ
SRESET
6
7
8
9
10
COLIS
—
COLIE
11
0000_0000_00
Addr
12
13
14
15
—
Unaffected
0x2F C28C
Figure 8-18. Change of Lock Interrupt Register (COLIR)
Table 8-12. COLIR Bit Descriptions
Bits
Name
Description
0:7
COLIRQ
Change of lock interrupt request level. These bits determine the interrupt priority level of the
change of lock. To specify a certain level, the appropriate one of these bits should be set.
8
COLIS
If set (1), the bit indicates that a change in the PLL lock status was detected. The PLL was
locked and lost lock, or the PLL was unlocked and got locked. The bit should be cleared by
writing a one.
9
—
10
COLIE
11:15
—
Reserved
Change of Lock Interrupt enable. If COLIE bit is asserted, an interrupt will be generated
when the COLIS bit is asserted.
0 Change of lock Interrupt disable
1 Change of lock Interrupt enable
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
8-36
Freescale Semiconductor
Clocks and Power Control
8.11.4
IRAMSTBY Control Register (VSRMCR)
This register contains control bits for enabling or disabling the IRAMSTBY supply detection circuit. There
are also four bits that indicate the failure detection. All four bits have the same function and are required
to improve the detection capability in extreme cases.
MSB
0
Field
LSB
1
—
PORESET
2
3
4
5
LVSRS
VSRDE
Unaffected
0
Addr
6
1
7
8
9
10
LVDRS ZOREG
U
11
12
13
14
15
—
0_0000_0000
0x2F C290
U = Unaffected by reset
Figure 8-19. IRAMSTBY Control Register (VSRMCR)
1
This bit is reserved on mask sets which implement bit 7 (ZOREG)
Table 8-13. VSRMCR Bit Descriptions
Bits
Name
0
—
1:4
LVSRS
5
VSRDE1
6
LVDRS
Description
Reserved
Loss of IRAMSTBY sticky. These status bits indicate whether a IRAMSTBY supply failure
occurred. In addition, when the power is turned on for the first time, IRAMSTBY rises and
these bits are set. The LVSRS bits are cleared by writing them to ones. A write of zero has
no effect on these bits.
0 No IRAMSTBY supply failure was detected
1 IRAMSTBY supply failure was detected
IRAMSTBY detector disable.
0 IRAMSTBY detection circuit is enabled
1 IRAMSTBY detection circuit is disabled
Loss of IRAMSTBY for DECRAM Sticky — The status bit, dedicated especially for the BBC
DECRAM, which indicates if there was IRAMSTBY supply failure. When the power is turned
on for the first time, IRAMSTBY rises also and the bits will be asserted. The LVDECRAM bit
can be cleared by writing ones to LVDECRAM. A write of zero has no effect on this bit. The
bit may be used by application software, to decide if there is need to load decompression
vocabularies during reset routine.
0 IRAMSTBY supply failure was not detected
1 IRAMSTBY supply failure was detected
NOTE: The LVDRS bit is provided as a convenience for indicating that the DECRAM has lost
power. It requires that the IRAMSTBY pins are connected to the same power supply. It
actually only monitors the IRAMSTBY supply.
This bit indicates the status of the internal IRAMSTBY supply. This bit is cleared by writing
a 1 to it.
1
7
ZOREG2
8:15
—
0 Internal IRAMSTBY zener regulator has not gone out of regulation
1 Internal IRAMSTBY zener regulator has gone out of regulation.
Note: ZOREG may get set inadvertently if IRAMSTBY is not supplied with at least 150µA.
Reserved
Removed on all parts that have the ZOREG bit.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-37
Clocks and Power Control
2
ZOREG is not in Rev 0 of the MPC561 but is in all later revisions. It is not in Rev 0 or 0A of the MPC563, but is in Rev
A and later revisions.
MPC561/MPC563 Reference Manual, Rev. 1.2
8-38
Freescale Semiconductor
Chapter 9
External Bus Interface
The MPC561/MPC563 external bus is a synchronous, burstable bus. Signals driven on this bus must
adhere to the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support
multiple masters. The MPC561/MPC563 external bus interface architecture supports byte, half-word, and
word operands allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles
controlled by the size outputs (TSIZ0, TSIZ1). For accesses to 16- and 8-bit ports, the slave must be
controlled by the memory controller. For more information, refer to Appendix F, “Electrical
Characteristics.”
9.1
Features
The external bus interface features are listed below:
• 32-bit address bus with transfer size indication (only 24 available on pins)
• 32-bit data bus
• Bus arbitration logic on-chip with external master support
• Chip-select and wait state generation to support peripheral or static memory devices through the
memory controller
• Supports various memory (SRAM, EEPROM) types: synchronous and asynchronous, burstable
and non-burstable
• Supports non-wrap bursts with up to four data beats
• Flash ROM programming support
• Implements the PowerPC ISAarchitecture
• Easy to interface to slave devices
• Bus is synchronous (all signals are referenced to rising edge of bus clock)
• Bus can operate at the same frequency as the internal RCPU core of MPC561/MPC563 or half the
frequency.
9.2
Bus Transfer Signals
The bus transfers information between the MPC561/MPC563 and external memory of a peripheral device.
External devices can accept or provide 8, 16, and 32 data bits in parallel and must follow the handshake
protocol described in this section. The maximum number of bits accepted or provided during a bus transfer
is defined as the port width.
The MPC561/MPC563 has non-multiplexed address and data buses. Control signals indicate the
beginning and type of the cycle, as well as the address space and size of the transfer. The selected device
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-1
External Bus Interface
then controls the length of the cycle with the signal(s) used to terminate the cycle. A strobe signal for the
address lines indicates the validity of the address.
The MPC561/MPC563 bus is synchronous with a synchronous support. The bus and control input signals
must be timed to setup and hold times relative to the rising edge of the clock. Bus cycles can be completed
in two clock cycles.
For all inputs, the MPC561/MPC563 latches the level of the input during a sample window around the
rising edge of the clock signal. This window is illustrated in Figure 9-1, where tsu and tho are the input
setup and hold times, respectively. To ensure that an input signal is recognized on a specific rising edge of
the clock, that input must be stable during the sample window. If an input makes a transition during the
window time period, the level recognized by the MPC561/MPC563 is not predictable; however, the
MPC561/MPC563 always resolves the latched level to either a logic high or low before using it. In
addition to meeting input setup and hold times for deterministic operation, all input signals must obey the
protocols described in this section.
tho
tsu
Clock
Signal
Sample
Window
Figure 9-1. Input Sample Window
9.3
Bus Control Signals
The MPC561/MPC563 initiates a bus cycle by driving the address, size, address type, cycle type, and
read/write outputs. At the beginning of a bus cycle, TSIZ[0:1] are driven with the address type signals.
TSIZ0 and TSIZ1 indicate the number of bytes remaining to be transferred during an operand cycle
(consisting of one or more bus cycles). These signals are valid at the rising edge of the clock in which the
transfer start (TS) signal is asserted.
The read/write (RD/WR) signal determines the direction of the transfer during a bus cycle. Driven at the
beginning of a bus cycle, RD/WR is valid at the rising edge of the clock in which TS is asserted. The logic
level of RD/WR only changes when a write cycle is preceded by a read cycle or vice versa. The signal may
remain low for consecutive write cycles.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-2
Freescale Semiconductor
External Bus Interface
24
1
1
2
4
Bus
Interface
ADDR[8:31]
RD/WR
BURST
TSIZ[0:1]
AT[0:3]
1
PTR
1
BDIP
1
TS
1
RSV
1
KR
1
CR
32
1
Address
and
Transfer
Attributes
Transfer
Start
Reservation
Protocol
DATA[0:31]
Data
BI / STS
1
TA
1
TEA
1
BR
1
BG
1
BB
1
RETRY
Transfer
Cycle
Termination
Arbitration
Figure 9-2. MPC561/MPC563 Bus Signals
9.4
Bus Interface Signal Descriptions
Table 9-1 describes each signal in the bus interface unit. More detailed descriptions can be found in
subsequent subsections. The buses are described in big endian manner, which means that bit 0 is the most
significant bit in a bus (MSB), and bit 31 is the least significant bit (LSB).
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-3
External Bus Interface
.
Table 9-1. MPC561/MPC563 BIU Signals
Signal Name
Pins
Active
I/O
Description
Address and Transfer Attributes
ADDR[8:31]
Address bus
24
[8:31]
High
O
Specifies the physical address of the bus transaction.
I
Driven by an external bus master when it owns the
external bus. An input for testing purposes only.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Driven high
indicates that a read access is in progress. Driven low
indicates that a write access is in progress.
I
Driven by an external master when it owns the
external bus. Driven high indicates that a read access
is in progress. Driven low indicates that a write access
is in progress.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Driven low
indicates that a burst transfer is in progress. Driven
high indicates that the current transfer is not a burst.
I
Driven by an external master when it owns the
external bus. Driven low indicates that a burst transfer
is in progress. Driven high indicates that the current
transfer is not a burst. The MPC561/MPC563 does
not support burst accesses to internal slaves.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Specifies the
data transfer size for the transaction.
I
Driven by an external master when it owns the
external bus. Specifies the data transfer size for the
transaction.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Indicates
additional type on the current transaction.
I
Only for testing purposes.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Indicates
additional information about the address on the
current transaction.
I
Only for testing purposes.
O
Driven by the MPC561/MPC563 along with the
address when it owns the external bus. Indicates
additional information about the address on the
current transaction.
I
Only for testing purposes.
RD/WR
1
HIgh
Read/write
BURST
1
Low
Burst transfer
TSIZ[0:1]
2
High
Transfer size
AT[0:3]
3
High
Address type
RSV
1
Low
Reservation transfer
PTR
1
High
Program trace
MPC561/MPC563 Reference Manual, Rev. 1.2
9-4
Freescale Semiconductor
External Bus Interface
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Signal Name
Pins
Active
I/O
Description
O
Driven by the MPC561/MPC563 when it owns the
external bus. It is part of the burst protocol. When
BDIP is asserted, the second beat in front of the
current one is requested by the master. This signal is
negated prior to the end of a burst to terminate the
burst data phase early.
I
Driven by an external master when it owns the
external bus. When BDIP is asserted, the second beat
in front of the current one is requested by the master.
This signal is negated prior to the end of a burst to
terminate the burst data phase early. The
MPC561/MPC563 does not support burst accesses to
internal slaves.
BDIP
1
Low
Burst data in progress
Transfer Start
O
Driven by the MPC561/MPC563 when it owns the
external bus. Indicates the start of a transaction on the
external bus.
I
Driven by an external master when it owns the
external bus. It indicates the start of a transaction on
the external bus or (in show cycle mode) signals the
beginning of an internal transaction.
TS
1
Low
Transfer start
Reservation Protocol
CR
1
Low
I
Cancel reservation
KR
1
Kill reservation
Low
I
Each MPC500 CPU has its own CR signal. Assertion
of CR instructs the bus master to clear its reservation;
some other master has touched its reserved space.
This is a pulsed signal.
In case of a bus cycle initiated by a STWCX
instruction issued by the RCPU to a non-local bus on
which the storage reservation has been lost, this
signal is used by the non-local bus interface to
back-off the cycle. Refer to Section 9.5.10, “Storage
Reservation” for details.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-5
External Bus Interface
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Signal Name
Pins
Active
I/O
Description
Data
The data bus has the following byte lane assignments:
Data Byte
Byte Lane
DATA[0:7]
0
DATA[8:15]
1
DATA[16:23]
2
DATA[24:31]
3
O
DATA[0:31]
32
High
Driven by the MPC561/MPC563 when it owns the
external bus and it initiated a write transaction to a
slave device. For single beat transactions, the byte
lanes not selected for the transfer by ADDR[30:31]
and TSIZ[0:1] do not supply valid data.
Data bus
In addition, the MPC561/MPC563 drives the
DATA[0:31] when an external master owns the
external bus and initiated a read transaction to an
internal slave module.
I
Driven by the slave in a read transaction. For single
beat transactions, the MPC561/MPC563 does not
sample byte lanes that are not selected for the transfer
by ADDR[30:31] and TSIZ[0:1].
In addition, an external master that owns the bus and
initiated a write transaction to an internal slave module
drives DATA[0:31].
Transfer Cycle Termination
I
TA
1
Low
Transfer acknowledge
O
TEA
Transfer error
acknowledge
1
Driven by the slave device to which the current
transaction was addressed. Indicates that the slave
has received the data on the write cycle or returned
data on the read cycle. If the transaction is a burst, TA
should be asserted for each one of the transaction
beats.
Driven by the MPC561/MPC563 when the slave
device is controlled by the on-chip memory controller
or when an external master initiated a transaction to
an internal slave module.
I
Driven by the slave device to which the current
transaction was addressed. Indicates that an error
condition has occurred during the bus cycle.
O
Driven by the MPC561/MPC563 when the internal
bus monitor detected an erroneous bus condition, or
when an external master initiated a transaction to an
internal slave module and an internal error was
detected.
Low
MPC561/MPC563 Reference Manual, Rev. 1.2
9-6
Freescale Semiconductor
External Bus Interface
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Signal Name
BI / STS
Pins
1
Active
Low
I/O
Description
I
Burst Inhibit: Driven by the slave device to which the
current transaction was addressed. Indicates that the
current slave does not support burst mode.
O
Burst Inhibit: Driven by the MPC561/MPC563 when
the slave device is controlled by the on-chip Memory
Controller. The MPC561/MPC563 also asserts BI for
any external master burst access to internal
MPC561/MPC563 memory space.
Special Transfer Start: Driven by the
MPC561/MPC563 when it owns the external bus.
Indicates the start of a transaction on the external bus
or signals the beginning of an internal transaction in
show cycle mode.
Burst inhibit/
Special Transfer Start
Arbitration
BR
1
I
When the internal arbiter is enabled, BR assertion
indicates that an external master is requesting the
bus.
O
Driven by the MPC561/MPC563 when the internal
arbiter is disabled and the chip is not parked.
Low
Bus request
O
BG
1
Low
Bus grant
I
O
BB
1
Low
Bus busy
I
When the internal arbiter is enabled, the
MPC561/MPC563 asserts this signal to indicate that
an external master may assume ownership of the bus
and begin a bus transaction. The BG signal should be
qualified by the master requesting the bus in order to
ensure it is the bus owner:
Qualified bus grant = BG & ~ BB
When the internal arbiter is disabled, BG is sampled
and properly qualified by the MPC561/MPC563 when
an external bus transaction is to be executed by the
chip.
When the internal arbiter is enabled, the
MPC561/MPC563 asserts this signal to indicate that it
is the current owner of the bus.
When the internal arbiter is disabled, the
MPC561/MPC563 asserts this signal after the
external arbiter has granted the ownership of the bus
to the chip and it is ready to start the transaction.
When the internal arbiter is enabled, the
MPC561/MPC563 samples this signal to get
indication of when the external master ended its bus
tenure (BB negated).
When the internal arbiter is disabled, the BB is
sampled to properly qualify the BG line when an
external bus transaction is to be executed by the chip.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-7
External Bus Interface
Table 9-1. MPC561/MPC563 BIU Signals (continued)
Signal Name
Pins
Active
I/O
I
RETRY
1
Low
O
Retry
9.5
Description
In the case of regular transaction, this signal is driven
by the slave device to indicate that the
MPC561/MPC563 must relinquish the ownership of
the bus and retry the cycle.
When an external master owns the bus and the
internal MPC561/MPC563 bus initiates access to the
external bus at the same time, this signal is used to
cause the external master to relinquish the bus for one
clock to solve the contention.
Bus Operations
This section provides a functional description of the system bus, the signals that control it, and the bus
cycles provided for data transfer operations. It also describes the error conditions, bus arbitration, and reset
operation.
The MPC561/MPC563 generates a system clock output (CLKOUT). This output sets the frequency of
operation for the bus interface directly. Internally, the MPC561/MPC563 uses a phase-lock loop (PLL)
circuit to generate a master clock for all of the MPC561/MPC563 circuitry (including the bus interface)
which is phase-locked to the CLKOUT output signal.
All signals for the MPC561/MPC563 bus interface are specified with respect to the rising edge of the
external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to that
edge. Since the same clock edge is referenced for driving or sampling the bus signals, the possibility of
clock skew could exist between various modules in a system due to routing or the use of multiple clock
lines. It is the responsibility of the system to handle any such clock skew problems that could occur.
9.5.1
Basic Transfer Protocol
The basic transfer protocol defines the sequence of actions that must occur on the MPC561/MPC563 bus
to perform a complete bus transaction. A simplified scheme of the basic transfer protocol is illustrated in
Figure 9-3.
Arbitration
Address Transfer
Data Transfer
Termination
Figure 9-3. Basic Transfer Protocol
The basic transfer protocol provides for an arbitration phase and an address and data transfer phase. The
address phase specifies the address for the transaction and the transfer attributes that describe the
transaction. The data phase performs the transfer of data (if any is to be transferred). The data phase may
transfer a single beat of data (four bytes or less) for nonburst operations, a 4-beat burst of data (4 x 4 bytes),
an 8-beat burst of data (8 x 2 bytes) or a 16-beat burst of data (16 x 1 bytes).
MPC561/MPC563 Reference Manual, Rev. 1.2
9-8
Freescale Semiconductor
External Bus Interface
9.5.2
Single Beat Transfer
During the data transfer phase, the data is transferred from master to slave (in write cycles) or from slave
to master (on read cycles).
During a write cycle, the master drives the data as soon as it can, but never earlier than the cycle following
the address transfer phase. The master has to take into consideration the “one dead clock cycle” switching
between drivers to avoid electrical contentions. The master can stop driving the data bus as soon as it
samples the TA line asserted on the rising edge of the CLKOUT.
During a read cycle, the master accepts the data bus contents as valid at the rising edge of the CLKOUT
in which the TA signal is sampled/asserted.
9.5.2.1
Single Beat Read Flow
The basic read cycle begins with bus arbitration, followed by the address transfer, then the data transfer.
The handshakes illustrated in the following flow and timing figures (Figure 9-4, Figure 9-5, and
Figure 9-6) are applicable to the fixed transaction protocol.
Master
Slave
1. Request bus (BR)
2. Receive bus grant (BG) from arbiter
3. Assert bus busy (BB) if no other master is driving bus
4. Assert transfer start (TS)
5. Drive address and attributes
1. Receive address
2. Return data
3. Assert transfer acknowledge (TA)
Figure 9-4. Basic Flow Diagram of a Single Beat Read Cycle
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-9
External Bus Interface
CLKOUT
BR
Receive bus grant and bus busy negated
BG
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
O
Data is valid
Figure 9-5. Single Beat Read Cycle – Basic Timing – Zero Wait States
MPC561/MPC563 Reference Manual, Rev. 1.2
9-10
Freescale Semiconductor
External Bus Interface
CLKOUT
BR
Receive bus grant and bus busy negated
BG
O
O
assert BB, drive address and assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
Wait state
Data is valid
Figure 9-6. Single Beat Read Cycle – Basic Timing – One Wait State
9.5.2.2
Single Beat Write Flow
The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer.
The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed
transaction protocol.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-11
External Bus Interface
Master
Slave
1. Request bus (BR)
2. Receive bus grant (BG) from arbiter
3. Assert bus busy (BB) if no other master is driving bus
4. Assert transfer start (TS)
5. Drive address and attributes
1. Drive data
1. Assert transfer acknowledge (TA)
1. Interrupt data driving
Figure 9-7. Basic Flow Diagram of a Single Beat Write Cycle
MPC561/MPC563 Reference Manual, Rev. 1.2
9-12
Freescale Semiconductor
External Bus Interface
CLKOUT
BR
Receive bus grant and bus busy negated
BG
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
O
Data is sampled by slave
Figure 9-8. Single Beat Basic Write Cycle Timing – Zero Wait States
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-13
External Bus Interface
CLKOUT
BR
Receive bus grant and bus busy negated
BG
O
O
Assert BB, drive address and assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
Wait state
O
Data is sampled
Figure 9-9. Single Beat Basic Write Cycle Timing – One Wait State
9.5.2.3
Single Beat Flow with Small Port Size
The general case of single beat transfers assumes that the external memory has a 32-bit port size. The
MPC561/MPC563 provides an effective mechanism for interfacing with 16-bit and 8-bit port size
memories, allowing transfers to these devices when they are controlled by the internal memory controller.
In this case, the MPC561/MPC563 attempts to initiate a transfer as in the normal case. If the bus interface
receives a small port size (16 or 8 bits) indication before the transfer acknowledge to the first beat (through
the internal memory controller), the MCU initiates successive transactions until the completion of the data
transfer. Note that all the transactions initiated to complete the data transfer are considered to be part of an
atomic transaction, so the MCU does not allow other unrelated master accesses or bus arbitration to
intervene between the transfers. If any of the transactions except the first is re-tried during an access to a
small port, then a machine-check exception is generated to the RCPU.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-14
Freescale Semiconductor
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[0:1]
ADDR + 2
ADDR
RD/WR
TSIZ[0:1]
10
00
BURST, BDIP
TS
STS
Data1
ABCDEFGH
EFGHEFGH
TA
1. For an illustration of device connections on the data bus, see Figure 9-23.
Figure 9-10. Single Beat 32-Bit Data Write Cycle Timing — 16-Bit Port Size
9.5.3
Data Bus Pre-Discharge Mode
Pre-discharge mode is provided for applications that use 3.3-V/5-V external memories while the
MPC561/MPC563 data bus pads are optimized to 2.6-V memories, and cannot tolerate more than 3.1 V.
When connecting 3.3-V devices to the E-bus, and performing read and write operations, this mode should
be invoked in order to avoid long term reliability issues of the data pads.
When the PDMCR2[PREDIS_EN] bit is set, the MPC561/MPC563 will discharge the bus during the
address phase of any write cycle prior to the data phase. The data bus will be discharged from up to 5 V to
a level which is suitable to the low voltage drivers. In most cases, the ORx[EHTR] bit of the relevant
memory bank, should be set along with the PREDIS_EN bit in order to reserve sufficient time for the
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-15
External Bus Interface
memory to three-state the bus before the bus discharge is initiated. EHTR has a slight performance
reduction impact since it adds a clock gap between some read and write cycles.
NOTE
EHTR also adds one idle clock for two consecutive read cycles from
different memory banks.
NOTE
The pre-disharge will not occur, when using multiple processors with a
common bus accessing an external device, if the processor that initiates a
read is different from the processor that initiated the previous write. Perform
a write to the external device to discharge the external bus, or read a value
of 0x0 from the external device, prior to accessing another MCU on the
same bus.
9.5.3.1
Operating Conditions
Pre-discharge mode should be enabled in the following cases:
• When external devices can charge the data bus to a higher voltage level than 3.1 volts
• And when one or more of the following occurs:
— The MPC561/MPC563 uses write accesses to any external memory
— Data show cycles are enabled
— Instruction show cycles are enabled in code compression mode (MPC562/MPC564 only)
NOTE
In the case of code compression program tracking (3rd case above), the
PREDIS_EN bit should only be set when program tracking is not required
since pre-discharge mode overwrites the compression show cycles data. The
user should not set PREDIS_EN bit when program tracking is required on
development system, and set PREDIS_EN bit on the production version.
EHTR can always be set to keep the same system performance during
development, and production phases.
9.5.3.2
Initialization Sequence
Systems that require pre-discharge operation should include the following steps:
• Execute boot sequence
• Set EHTR bit in all relevant memory banks during the memory controller initialization phase
(configure ORx, and BRx) if it is required to extend the time between read cycles, and
pre-discharge phase of write cycles.
• Set PREDIS_EN in PDMCR2 register
• Start to write data to external devices
MPC561/MPC563 Reference Manual, Rev. 1.2
9-16
Freescale Semiconductor
External Bus Interface
Refer to Section 2.4, “Pad Module Configuration Register (PDMCR2),” and Section 10.9.4, “Memory
Controller Option Registers (OR0–OR3),” for more information on PREDIS_EN, and EHTR
configuration bits.
CLKOUT
ADDR[8:31]
Read Cycle
Write Cycle
EHTR provides 1 clock
gap to three-state data bus
TS
RD/WR
TA
OE
Pre-discharge
to low voltage
Data
Read Data
Write Data
Figure 9-11. Read Followed by Write when Pre-Discharge Mode is Enabled, and EHTR is Set
9.5.4
Burst Transfer
The MPC561/MPC563 uses non-wrapping burst transfers to access operands of up to 32 bytes (eight
words). A non-wrapping burst access stops accessing the external device when the word address is modulo
four/eight. Burst configuration is determined by the value of BURST_EN in the SIUMCR register. See
Chapter 5, “Unified System Interface Unit (USIU) Overview” for further details. The MPC561/MPC563
begins the access by supplying a starting address that points to one of the words in the array and requires
the memory to sequentially drive or sample each word on the data bus. The selected slave device must
internally increment ADDR28 and ADDR29 (and ADDR30 in the case of a 16-bit port slave device, and
also ADDR31 in the case of an 8-bit port slave device) of the supplied address for each transfer, causing
the address to reach a four/eight word boundary, and then stop. The address and transfer attributes supplied
by the MPC561/MPC563 remain stable during the transfers. The selected device terminates each transfer
by driving or sampling the word on the data bus and asserting TA.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-17
External Bus Interface
The MPC561/MPC563 also supports burst-inhibited transfers for slave devices that are unable to support
bursting. For this type of bus cycle, the selected slave device supplies or samples the first word the
MPC561/MPC563 points to and asserts the burst-inhibit signal with TA for the first transfer of the burst
access. The MPC561/MPC563 responds by terminating the burst and accessing the remainder of the
16-byte block. These remaining accesses use up to three read/write bus cycles (each one for a word) in the
case of a 32-bit port width slave, up to seven read/write bus cycles in the case of a 16-bit port width slave,
or up to fifteen read/write bus cycles in the case of a 8-bit port width slave.
The general case of burst transfers assumes that the external memory has a 32-bit port size. The
MPC561/MPC563 provides an effective mechanism for interfacing with 16-bit and 8-bit port size
memories, allowing bursts transfers to these devices when they are controlled by the internal memory
controller.
In this case, the MPC561/MPC563 attempts to initiate a burst transfer as in the normal case. If the memory
controller signals to the bus interface that the external device has a small port size (8 or 16 bits), and if the
burst is accepted, the bus interface completes a burst of 16 or 8 beats respectively for four words. Eight
words requires 32 or 16 beats. Each beat of the burst transfers only one or two bytes effectively. Note that
this burst of 8 or 16 beats is considered an atomic transaction, so the MPC561/MPC563 does not allow
other unrelated master accesses or bus arbitration to intervene between the transfers.
9.5.5
Burst Mechanism
In addition to the standard bus signals, the MPC561/MPC563 burst mechanism uses the following signals:
• The BURST signal indicates that the cycle is a burst cycle.
• The burst data in progress (BDIP) signal indicates the duration of the burst data.
• The burst inhibit (BI) signal indicates whether the slave is burstable.
At the start of the burst transfer, the master drives the address, the address attributes, and the BURST signal
to indicate that a burst transfer is being initiated, and asserts TS. If the slave is burstable, it negates the
burst-inhibit (BI) signal. If the slave cannot burst, it asserts BI. For additional details, refer to
Section 10.2.5, “Burst Support.”
During the data phase of a burst-write cycle, the master drives the data. It also asserts BDIP if it intends to
drive the data beat following the current data beat. When the slave has received the data, it asserts TA to
indicate to the master that it is ready for the next data transfer. The master again drives the next data and
asserts or negates the BDIP signal. If the master does not intend to drive another data beat following the
current one, it negates BDIP to indicate to the slave that the next data beat transfer is the last data of the
burst-write transfer.
BDIP has two basic timings: normal and late (see Figure 9-14 and Figure 9-15). In the late timing mode,
assertion of BDIP is delayed by the number of wait states in the first data beat. This implies that for
zero-wait-state cycles, BDIP assertion time is identical in normal and late modes. Cycles with late BDIP
generation can occur only during cycles for which the memory controller generates TA internally. Refer
to Chapter 10, “Memory Controller” for more information.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-18
Freescale Semiconductor
External Bus Interface
In the MPC561/MPC563, no internal master initiates write bursts. The MPC561/MPC563 is designed to
perform this kind of transaction in order to support an external master that is using the memory controller
services. Refer to Section 10.8, “Memory Controller External Master Support.”
During the data phase of a burst-read cycle, the master receives data from the addressed slave. If the master
needs more than one data beat, it asserts BDIP. Upon receiving the second-to-last data beat, the master
negates BDIP. The slave stops driving new data after it receives the negation of the BDIP signal at the
rising edge of the clock.
Burst inputs (reads) in the MPC561/MPC563 are used only for instruction cycles. Data load cycles are not
supported.
Figures 9-12 through 9-21 are examples of various burst cycles, including illustrations of burst-read and
burst-write cycles for both the 16- and 32-bit port sizes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-19
External Bus Interface
Master
Slave
1. Request Bus (BR)
2. Receive bus grant (BG) from arbiter
3. Assert Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drive Address and Attributes
6. Drive BURST Asserted
ADDR[28:29] mod 4 =?
Receive Address
=0
Assert BDIP
Return Data
Assert Transfer Acknowledge (TA)
Receive Data
=1
BDIP Asserted
Assert BDIP
Receive Data
Assert BDIP
Drive Last Data
& Assert TA
Return Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
No
Drive Last Data
& Assert TA
Yes
Negate Burst Data in Progress (BDIP)
Return Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Receive Data
=4
No
Yes
Receive Data
=3
Drive Last Data
& Assert TA
Yes
Return Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
=2
No
No
Drive Last Data
& Assert TA
Yes
MPC561/MPC563 Reference Manual, Rev. 1.2
9-20
Freescale Semiconductor
External Bus Interface
Figure 9-12. Basic Flow Diagram Of A Burst-Read Cycle
CLKOUT
BR
BG
BB
ADDR[8:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Last Beat
O
Expects Another Data
BDIP
O
O
O
Data
No Data
Expected
TA
O
O
Data
is Valid
O
Data
is Valid
O
Data
is Valid
Data
is Valid
Figure 9-13. Burst-Read Cycle – 32-Bit Port Size – Zero Wait State
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-21
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[8:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Last Beat
O
Expects Another Data
BDIP
Normal
Late
O
O
No Data
Expected
O
Data
TA
O
Wait State
O
Data
is Valid
O
O
Data
is Valid
Data
is Valid
Data
is Valid
Figure 9-14. Burst-Read Cycle – 32-Bit Port Size – One Wait State
MPC561/MPC563 Reference Manual, Rev. 1.2
9-22
Freescale Semiconductor
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[8:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Normal or Late
BDIP
Last Beat
O
Expects Another Data
O
O
O
O
No Data
Expected
O
Data
TA
Data
is Valid
O
Data
is Valid
O
Data
is Valid
Data
is Valid
Wait State
Figure 9-15. Burst-Read Cycle – 32-Bit Port Size – Wait States Between Beats
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-23
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[8:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
BDIP
Data[0:15]
TA
Figure 9-16. Burst-Read Cycle – 16-Bit Port Size
MPC561/MPC563 Reference Manual, Rev. 1.2
9-24
Freescale Semiconductor
External Bus Interface
External Master
Slave
1. Request Bus (BR)
2. Receive Bus Grant (BG) from Arbiter
3. Assert Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drive Address and Attributes
6. Drive BURST Asserted
7. MTS Asserted (from MPC500 Device)
Drive data
Receive Address
ADDR[28:29] mod 4 =?
=0
Assert BDIP
Drive Data
=1
Assert BDIP
Drive Data
=2
Assert BDIP
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Don’t Sample
Next Data
Yes
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
No
Don’t Sample
Next Data
No
Don’t Sample
Next Data
Yes
Sample Data
Assert Transfer Acknowledge (TA)
Drive Data
BDIP Asserted
=3
No
Yes
Negate Burst Data in Progress (BDIP)
Sample Data
Assert Transfer Acknowledge (TA)
BDIP Asserted
Stop Driving Data
No
Don’t Sample
Next Data
Yes
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-25
External Bus Interface
Figure 9-17. Basic Flow Diagram of a Burst-Write Cycle
CLKOUT
BR1
BG1
BB1
ADDR[8:31]
ADDR[28:29] = 00
RD/WR1
TSIZ[0:1]
00
BURST1
TS1
MTS
BDIP1
Will Drive Another Data
O
O
Last Beat
O
O
No Data
Expected
Data
TA
O
O
O
O
Data
Data
Data
Data
is Sampled is Sampled is Sampledis Sampled
1From
external master
Figure 9-18. Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
(Only for External Master Memory Controller Service Support)
MPC561/MPC563 Reference Manual, Rev. 1.2
9-26
Freescale Semiconductor
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[0:27]
ADDR[28:29]
0
1
2
3
ADDR[30:31]
RD/WR
TSIZ[0:1]
00
BURST1
TS
BDIP1
Data
TA
BI
1
BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst, but the USIU splits it into a sequence of
normal cycles.
Figure 9-19. Burst-Inhibit Read Cycle, 32-Bit Port Size (Emulated Burst)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-27
External Bus Interface
CLKOUT
BR
BG
BB
ADDR(0:29)
n (n modulo 4 = 1)
ADDR[30:31]
RD/WR
TSIZ[0:1]
00
BURST
TS
Expects Another Data
BDIP
O
O
Data
TA
BI
Figure 9-20. Non-Wrap Burst with Three Beats
MPC561/MPC563 Reference Manual, Rev. 1.2
9-28
Freescale Semiconductor
External Bus Interface
CLKOUT
BR
BG
BB
ADDR[0:29]
ADDR[30:31]
n (n modulo 4 = 3)
00
RD/WR
TSIZ[0:1]
00
BURST
TS
Is Never Asserted
BDIP
First and Last Beat
Data
TA
O
DATA
is Sampled
Figure 9-21. Non-Wrap Burst with One Data Beat
9.5.6
Alignment and Packaging of Transfers
The MPC561/MPC563 external bus requires natural address alignment:
• Byte accesses allow any address alignment
• Half-word accesses require address bit 31 to equal zero
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-29
External Bus Interface
•
•
Word accesses require address bits 30 – 31 to equal zero
Burst accesses require address bits 30 – 31 to equal zero
The MPC561/MPC563 performs operand transfers through its 32-bit data port. If the transfer is controlled
by the internal memory controller, the MPC561/MPC563 can support 8- and 16-bit data port sizes.
The bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed.
A 32-bit port resides on DATA[0:31], a 16-bit port must reside on DATA[0:15], and an 8-bit port must
reside on DATA[0:7]. The MPC561/MPC563 always tries to transfer the maximum amount of data on all
bus cycles. For a word operation, it always assumes that the port is 32 bits wide when beginning the bus
cycle.
In Figure 9-22, Figure 9-23, Table 9-2, and Table 9-3, the following conventions are used:
• OP0 is the most-significant byte of a word operand and OP3 is the least-significant byte.
• The two bytes of a half-word operand are either OP0 (most-significant) and OP1 or OP2
(most-significant) and OP3, depending on the address of the access.
• The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of
the access.
0
31
OP0
OP1
OP0
OP1
OP2
OP3
OP2
OP3
Word
Half-word
OP0
OP1
Byte
OP2
OP3
Figure 9-22. Internal Operand Representation
MPC561/MPC563 Reference Manual, Rev. 1.2
9-30
Freescale Semiconductor
External Bus Interface
Figure 9-23 illustrates the device connections on the data bus.
0
31
OP0
OP1
DATA[0:7]
OP2
DATA[8:15]
OP0
OP1
OP0
OP1
OP2
OP3
Interface
Output
Register
OP3
DATA[16:23]
OP2
DATA[24:31]
OP3
32-bit Port Size
16-bit Port Size
OP0
OP1
8-bit Port Size
OP2
OP3
Figure 9-23. Interface To Different Port Size Devices
Table 9-2 lists the bytes required on the data bus for read cycles.
Table 9-2. Data Bus Requirements For Read Cycles
Address
Transfer
Size
Byte
Half-word
Word
32-bit Port Size
16-bit Port Size
8-bit
Port
Size
TSIZE
[0:1]
ADDR
[30:31]
DATA
[0:7]
DATA
[8:15]
DATA
[16:23]
DATA
[24:31]
DATA
[0:7]
DATA
[8:15]
DATA
[0:7]
01
00
OP0
—
—
—
OP0
—
OP0
01
01
—
OP1
—
—
—
OP1
OP1
01
10
—
—
OP2
—
OP2
—
OP2
01
11
—
—
—
OP3
—
OP3
OP3
10
00
OP0
OP1
—
—
OP0
OP1
OP0
10
10
—
—
OP2
OP3
OP2
OP3
OP2
00
00
OP0
OP1
OP2
OP3
OP0
OP1
OP0
Note: “—” denotes a byte not required during that read cycle.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-31
External Bus Interface
Table 9-3 lists the patterns of the data transfer for write cycles when the MPC561/MPC563 initiates an
access.
Table 9-3. Data Bus Contents for Write Cycles
Address
Transfer
Size
TSIZE[0:1]
Byte
Half-word
Word
External Data Bus Pattern
ADDR
[30:31]
DATA
[0:7]
DATA
[8:15]
DATA
[16:23]
DATA
[24:31]
01
00
OP0
—
—
—
01
01
OP1
OP1
—
—
01
10
OP2
—
OP2
—
01
11
OP3
OP3
—
OP3
10
00
OP0
OP1
—
—
10
10
OP2
OP3
OP2
OP3
00
00
OP0
OP1
OP2
OP3
Note: “—” denotes a byte not driven during that write cycle.
9.5.7
Arbitration Phase
The external bus design provides for a single bus master at any one time, either the MPC561/MPC563 or
an external device. One or more of the external devices on the bus can have the capability of becoming bus
master for the external bus. Bus arbitration may be handled either by an external central bus arbiter or by
the internal on-chip arbiter. In the latter case, the system is optimized for one external bus master besides
the MPC561/MPC563. The arbitration configuration (external or internal) is set at system reset.
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. The device that
needs the bus asserts BR. The device then waits for the arbiter to assert BG. In addition, the new master
must look at BB to ensure that no other master is driving the bus before it can assert BB to assume
ownership of the bus. Any time the arbiter has taken the bus grant away from the master and the master
wants to execute a new cycle, the master must re-arbitrate before a new cycle can be executed. The
MPC561/MPC563, however, guarantees data coherency for access to a small port size and for decomposed
bursts. This means that the MPC561/MPC563 will not release the bus before the completion of the
transactions that are considered atomic. Figure 9-24 describes the basic protocol for bus arbitration.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-32
Freescale Semiconductor
External Bus Interface
Requesting Device
Arbiter
Request the Bus
1. Assert BR
Grant Bus arbitration
Acknowledge Bus Mastership
1. Wait for BB to be negated.
2. Assert BB to become next master
3. Negate BR
Operate as Bus Master
1. Assert BG
Terminate Arbitration
1. Negate BG (or keep asserted to park
bus master
1. Perform data transfer
Release Bus Mastership
1. Negate BB
Figure 9-24. Bus Arbitration Flowchart
9.5.7.1
Bus Request
The potential bus master asserts BR to request bus mastership. BR should be negated as soon as the bus is
granted, the bus is not busy, and the new master can drive the bus. If more requests are pending, the master
can keep asserting its bus request as long as needed. When configured for external central arbitration, the
MPC561/MPC563 drives this signal when it requires bus mastership. When the internal on-chip arbiter is
used, this signal is an input to the internal arbiter and should be driven by the external bus master.
9.5.7.2
Bus Grant
The arbiter asserts BG to indicate that the bus is granted to the requesting device. This signal can be
negated following the negation of BR or kept asserted for the current master to park the bus.
When configured for external central arbitration, BG is an input signal to the MPC561/MPC563 from the
external arbiter. When the internal on-chip arbiter is used, this signal is an output from the internal arbiter
to the external bus master.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-33
External Bus Interface
9.5.7.3
Bus Busy
BB assertion indicates that the current bus master is using the bus. New masters should not begin transfer
until this signal is negated. The bus owner should not relinquish or negate this signal until the transfer is
complete. To avoid contention on the BB line, the master should three-state this signal when it gets a
logical one value. This requires the connection of an external pull-up resistor to ensure that a master that
acquires the bus is able to recognize the BB line negated, regardless of how many cycles have passed since
the previous master relinquished the bus. Refer to Figure 9-25.
Master
External Bus
MPC500 Device
(Slave 1)
TS
BB
Slave 2
Figure 9-25. Master Signals Basic Connection
MPC561/MPC563 Reference Manual, Rev. 1.2
9-34
Freescale Semiconductor
External Bus Interface
CLKOUT
BR0
BG0
BR1
BG1
BB
ADDR[8:31]
and Attributes
TS
TA
Master 0
“Turns On” and
Drives Signals
Master 0
Negates BB
and “Turns Off”
(Three-state Controls)
Master 1
“Turns On” and
Drives Signals
Figure 9-26. Bus Arbitration Timing Diagram
9.5.7.4
Internal Bus Arbiter
The MPC561/MPC563 can be configured at system reset to use the internal bus arbiter. In this case, the
MPC561/MPC563 will be parked on the bus. The parking feature allows the MPC561/MPC563 to skip the
bus request phase, and if BB is negated, assert BB and initiate the transaction without waiting for BG from
the arbiter.
The priority of the external device relative to the internal MPC561/MPC563 bus masters is programmed
in the SIU module configuration register. If the external device requests the bus and the MPC561/MPC563
does not require it, or if the external device has higher priority than the current internal bus master, the
MPC561/MPC563 grants the bus to the external device.
Table 9-4 describes the priority mechanism used by the internal arbiter.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-35
External Bus Interface
Table 9-4. Priority Between Internal and External Masters over External Bus1
1
2
Type
Direction
Priority
Parked access2
Internal → external
0
Instruction access
Internal → external
3
Data access
Internal → external
4
External access
external → external/internal
EARP (could be programmed to 0 – 7)
External master will be granted external bus ownership if EARP is greater than the internal access priority.
Parked access is instruction or data access from the RCPU which is initiated on the internal bus without
requesting it first in order to improve performance.
Figure 9-27 illustrates the internal finite-state machine that implements the arbiter protocol.
External
Owner
BG = 0
BB = three
state
BB
=
1,
BR = 1
BR
BR
=1
=
0
External Master
Requests Bus
MPC500 Device
Internal Master With Higher
Priority than the External Device
Requires the Bus
External Master
Release Bus
BB = 0
MPC500
Device
Bus Wait
BG = 1
BB = three
state
IDLE
BG = 1
BB = three
state
MCU Needs
the Bus
BB = 1
MPC500 Device
No Longer
Needs the Bus
MPC500
Device Owner
BR = 0
External Device With Higher
Priority than the Current Internal
Bus Master Requests the Bus
BG = 1
BB = 0
MPC500 Device
Still Needs
the Bus
Figure 9-27. Internal Bus Arbitration State Machine
MPC561/MPC563 Reference Manual, Rev. 1.2
9-36
Freescale Semiconductor
External Bus Interface
9.5.8
Address Transfer Phase Signals
Address transfer phase signals include the following:
• Transfer start
• Address bus
• Transfer attributes
Transfer attributes signals include RD/WR, BURST, TSIZ[0:1], AT[0:3], STS, and BDIP. With the
exception of the BDIP, these signals are available at the same time as the address bus.
9.5.8.1
Transfer Start
This signal (TS) indicates the beginning of a transaction on the bus addressing a slave device. This signal
should be asserted by a master only after the ownership of the bus was granted by the arbitration protocol.
This signal is asserted for the first cycle of the transaction only and is negated in successive clock cycles
until the end of the transaction. The master should three-state this signal when it relinquishes the bus to
avoid contention between two or more masters in this line. This situation indicates that an external pull-up
resistor should be connected to the TS signal to avoid having a slave recognize this signal as asserted when
no master drives it. Refer to Figure 9-25.
9.5.8.2
Address Bus
The address bus consists of 32 bits, with ADDR0 the most significant bit and ADDR31 the least significant
bit. Only 24 bits (ADDR[8:31]) are available external to the MPC561/MPC563. The bus is
byte-addressable, so each address can address one or more bytes. The address and its attributes are driven
on the bus with the transfer start signal and kept valid until the bus master receives the transfer
acknowledge signal from the slave. To distinguish the individual byte, the slave device must observe the
TSIZ signals.
9.5.8.3
Read/Write
A high value on the RD/WR line indicates a read access. A low value indicates a write access.
9.5.8.4
Burst Indicator
BURST is driven by the bus master at the beginning of the bus cycle along with the address to indicate that
the transfer is a burst transfer.
The MPC561/MPC563 supports a non-wrapping, 8-beat maximum (with 32-bit port), critical word first
burst type. The maximum burst size is 32 bytes. For a 16-bit port, the burst includes 16 beats. For an 8-bit
port, the burst includes 32 beats at most.
NOTE
8- and 16-bit ports must be controlled by the memory controller.
The actual size of the burst is determined by the address of the starting word of the burst. Refer to Table 9-5
and Table 9-6.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-37
External Bus Interface
Table 9-5. 4 Word Burst Length and Order
Starting
Address
ADDR[28:29]
Burst Order (Assuming
32-bit Port Size)
Burst Length in
Words (Beats)
Burst Length
in Bytes
00
word 0 → word 1 →
word 2 → word 3
4
16
01
word 1 → word 2 → word 3
3
12
10
word 2 → word 3
2
8
11
word 3
1
4
9.5.8.5
Comments
BDIP never asserted
Transfer Size
The transfer size signals (TSIZ[0:1]) indicate the size of the requested data transfer. During each transfer,
the TSIZ signals indicate how many bytes are remaining to be transferred by the transaction. The TSIZ
signals can be used with BURST and ADDR[30:31] to determine which byte lanes of the data bus are
involved in the transfer. For non-burst transfers, the TSIZ signals specify the number of bytes starting from
the byte location addressed by ADDR[30:31]. In burst transfers, the value of TSIZ is always 00.
Table 9-6. BURST/TSIZE Encoding
9.5.8.6
BURST
TSIZ[0:1]
Transfer Size
Negated
01
Byte
Negated
10
Half-word
Negated
11
x
Negated
00
Word
Asserted
00
Burst (16 or 32 bytes)
Address Types
The address type (AT[0:3]), program trace (PTR), and reservation transfer (RSV) signals are outputs that
indicate one of 16 address types. These types are designated as either a normal or alternate master cycle,
user or supervisor, and instruction or data type. The address type signals are valid at the rising edge of the
clock in which the special transfer start (STS) signal is asserted.
A special use of the PTR and RSV signals is for the reservation protocol described in Section 9.5.10,
“Storage Reservation.” Refer to Section 9.5.14, “Show Cycle Transactions” for information on show
cycles.
Table 9-7 summarizes the pins used to define the address type. Table 9-8 lists all the definitions achieved
by combining these pins.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-38
Freescale Semiconductor
External Bus Interface
Table 9-7. Address Type Pins
Pin
:
Function
STS
0 Special transfer
1 Normal transfer
TS
0 Start of transfer
1 No transfer
AT0
Must equal zero on MPC561/MPC563
AT1
0 Supervisor mode
1 User mode
AT2
0 Instruction
1 Data
AT3
Reservation/Program Trace
PTR
0 Program trace
1 No program trace
RSV
0 Reservation data
1 No reservation
Table 9-8. Address Types Definition
STS
TS
AT0
AT1
AT2
AT3
PTR
RSV
1
x
x
x
x
x
1
1
No transfer
0
01
0
0
0
0
0
1
RCPU, normal instruction, program trace, supervisor mode
1
1
1
RCPU, normal instruction, supervisor mode
0
1
0
RCPU, reservation data, supervisor mode
1
1
1
RCPU, normal data, supervisor mode
0
0
1
RCPU, normal instruction, program trace, user mode
1
1
1
RCPU, normal instruction, user mode
0
1
0
RCPU, reservation data, user mode
1
1
1
RCPU, normal data, user mode
1
1
0
1
1
Address Space Definitions
1
?
?
?
1
1
Reserved
0
0
0
0
0
1
RCPU, show cycle address instruction, program trace,
supervisor mode
1
1
1
RCPU, show cycle address instruction, supervisor mode
0
1
0
RCPU, reservation show cycle data, supervisor mode
1
1
1
RCPU, show cycle data, supervisor mode
0
0
1
RCPU, show cycle address instruction, program trace, user
mode
1
1
1
RCPU, show cycle address instruction, user mode
0
1
0
RCPU, reservation show cycle data, user mode
1
1
1
RCPU, show cycle data, user mode
?
1
1
Reserved
1
1
0
1
1
?
?
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-39
External Bus Interface
1
Cases in which both TS and STS are asserted indicate normal cycles with the show cycle attribute.
9.5.8.7
Burst Data in Progress
This signal is sent from the master to the slave to indicate that there is a data beat following the current
data beat. The master uses this signal to give the slave advance warning of the remaining data in the burst.
BDIP can also be used to terminate the burst cycle early. Refer to Section 9.5.4, “Burst Transfer” and
Section 9.5.5, “Burst Mechanism” for more information. Refer to Section 10.9.3, “Memory Controller
Base Registers (BR0–BR3)” for memory controller BDIP options.
9.5.9
Termination Signals
The EBI uses three termination signals:
• Transfer acknowledge (TA)
• Burst inhibit (BI)
• Transfer error acknowledge (TEA)
9.5.9.1
Transfer Acknowledge
Transfer acknowledge (TA) indicates normal completion of the bus transfer. During a burst cycle, the slave
asserts this signal with every data beat returned or accepted.
9.5.9.2
Burst Inhibit
A slave sends the BI signal to the master to indicate that the addressed device does not have burst
capability. If this signal is asserted, the master must transfer in multiple cycles and increment the address
for the slave to complete the burst transfer. For a system that does not use the burst mode at all, this signal
can be tied low permanently. Refer to Section 10.9.3, “Memory Controller Base Registers (BR0–BR3)”
for BI options.
9.5.9.3
Transfer Error Acknowledge
The TEA signal terminates a bus cycle under one or more bus error conditions. The current bus cycle must
be aborted. This signal overrides any other cycle termination signals, such as transfer acknowledge.
9.5.9.4
Termination Signals Protocol
The transfer protocol was defined to avoid electrical contention on lines that can be driven by various
sources. To this end, a slave must not drive signals associated with the data transfer until the address phase
is completed and it recognizes the address as its own. The slave must disconnect from signals immediately
after it has acknowledged the cycle and no later than the termination of the next address phase cycle. This
means that the termination signals must be connected to power through a pull-up resistor to avoid the
situation in which a master samples an undefined value in any of these signals when no real slave is
addressed.
Refer to Figure 9-28 and Figure 9-29.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-40
Freescale Semiconductor
External Bus Interface
Slave 1
External Bus
MCU
Acknowledge
Signals
TA
TEA
Slave 2
Figure 9-28. Termination Signals Protocol Basic Connection
CLKOUT
ADDR[8:31]
Slave 1
Slave 2
RD/WR
TSIZ[0:1]
TS
Data
TA, BI, TEA
Slave 1
allowed to drive
acknowledge signals
Slave 1
negates acknowledge
signals and turns off
Slave 2
allowed to drive
acknowledge signals
Slave 2
negates acknowledge
signals and turns off
Figure 9-29. Termination Signals Protocol Timing Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-41
External Bus Interface
9.5.10
Storage Reservation
Reservation occurs when a master loads data from memory. The memory location must not be overwritten
until the master finishes processing the data and writing the results back to the reserved location. The
MPC561/MPC563 storage reservation protocol supports a multi-level bus structure. For each local bus,
storage reservation is handled by the local reservation logic.
The protocol tries to optimize reservation cancellation such that an MPC500 processor is notified of
storage reservation loss on a remote bus only when it has issued a conditional storeword (stwcx) cycle to
that address. That is, the reservation loss indication comes as part of the stwcx cycle. This method avoids
the need to have very fast storage reservation loss indication signals routed from every remote bus to every
MPC500 master.
The storage reservation protocol makes the following assumptions:
• Each processor has, at most, one reservation flag
• lwarx sets the reservation flag
• lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and
again sets the reservation flag
• stwcx by the same processor clears the reservation flag
• Store by the same processor does not clear the reservation flag
• Some other processor (or other mechanism) store to the same address as an existing reservation
clears the reservation flag
• In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage
The reservation protocol for a single-level (local) bus is illustrated in Figure 9-30. The protocol assumes
that an external logic on the bus carries out the following functions:
• Snoops accesses to all local bus slaves
• Holds one reservation for each local master capable of storage reservations
• Sets the reservation when that master issues a load and reserve request
• Clears the reservation when some other master issues a store to the reservation address
MPC561/MPC563 Reference Manual, Rev. 1.2
9-42
Freescale Semiconductor
External Bus Interface
MPC500 Device
External Bus
External Bus
Interface
Bus
Master
lwarx
S
Q
R
Enable
external stwcx access
AT[0:3], RSV, R/W, TS
ADDR[0:29]
CR
Reservation
Logic
CR
CLKOUT
Figure 9-30. Reservation on Local Bus
The MPC561/MPC563 samples the CR line at the rising edge of CLKOUT. When this signal is asserted,
the reservation flag is reset (negated).
The external bus interface (EBI) samples the logical value of the reservation flag prior to externally
starting a bus cycle initiated by the RCPU stwcx instruction. If the reservation flag is set, the EBI begins
with the bus cycle. If the reservation flag is reset, no bus cycle is initiated externally, and this situation is
reported to the RCPU.
The reservation protocol for a multi-level (local) bus is illustrated in Figure 9-31. The system describes the
situation in which the reserved location is sited in the remote bus.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-43
External Bus Interface
External Bus (Local Bus)
External Bus
Interface
AT[0:3], RSV, R/W, TS
MPC500 Device
ADDR[0:29]
Local Master Accesses with
lwarx to Remove Bus Address
KR
Q
Bus
Interface
S
R
A Master in the Remote Bus Write
to the Reserved Location
Remote Bus
Figure 9-31. Reservation on Multi-level Bus Hierarchy
In this case, the bus interface block implements a reservation flag for the local bus master. The reservation
flag is set by the bus interface when a load with reservation is issued by the local bus master and the
reservation address is located on the remote bus. The flag is reset (negated) when an alternative master on
the remote bus accesses the same location in a write cycle. If the MPC561/MPC563 begins a memory cycle
to the previously reserved address (located in the remote bus) as a result of an stwcx instruction, the
following two cases can occur:
• If the reservation flag is set, the buses interface acknowledges the cycle in a normal way
• If the reservation flag is reset, the bus interface should assert the KR. However, the bus interface
should not perform the remote bus write-access or abort it if the remote bus supports aborted
cycles. In this case the failure of the stwcx instruction is reported to the RCPU.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-44
Freescale Semiconductor
External Bus Interface
9.5.11
Bus Exception Control Cycles
The MPC561/MPC563 bus architecture requires assertion of TA from an external device to signal that the
bus cycle is complete. TA is not asserted in the following cases:
• The external device does not respond
• Various other application-dependent errors occur
External circuitry can provide TEA when no device responds by asserting TA within an appropriate period
of time after the MPC561/MPC563 initiates the bus cycle (it can be the internal bus monitor). This allows
the cycle to terminate and the processor to enter exception-processing for the error condition (each one of
the internal masters causes an internal interrupt under this situation). To properly control termination of a
bus cycle for a bus error, TEA must be asserted at the same time or before TA is asserted. TEA should be
negated before the second rising edge after it was sampled as asserted to avoid the detection of an error for
the next initiated bus cycle. TEA is an open drain pin that allows the “wired-or” of any different sources
of error generation.
9.5.11.1
Retrying a Bus Cycle
When an external device asserts the RETRY signal during a bus cycle, the MPC561/MPC563 enters a
sequence in which it terminates the current transaction, relinquishes the ownership of the bus, and retries
the cycle using the same address, address attributes, and data (in the case of a write cycle).
Figure 9-32 illustrates the behavior of the MPC561/MPC563 when the RETRY signal is detected as a
termination of a transfer. As seen in this figure, in the case when the internal arbiter is enabled, the
MPC561/MPC563 negates BB and asserts BG in the clock cycle following the retry detection. This allows
any external master to gain bus ownership. In the next clock cycle, a normal arbitration procedure occurs
again. As shown in the figure, the external master did not use the bus, so the MPC561/MPC563 initiates a
new transfer with the same address and attributes as before.
In Figure 9-33, the same situation is shown except that the MPC561/MPC563 is working with an external
arbiter. In this case, in the clock cycle after the RETRY signal is detected asserted, BR is negated together
with BB. One clock cycle later, the normal arbitration procedure occurs again.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-45
External Bus Interface
CLKOUT
BR
BG (output)
BB
ADDR[8:31]
Allow External
Master to Gain the Bus
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (input)
O
Figure 9-32. Retry Transfer Timing – Internal Arbiter
MPC561/MPC563 Reference Manual, Rev. 1.2
9-46
Freescale Semiconductor
External Bus Interface
CLKOUT
BR (output)
BG
Allow External
Master to Gain the Bus
BB
ADDR[8:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (input)
O
Figure 9-33. Retry Transfer Timing – External Arbiter
When the MPC561/MPC563 initiates a burst access, the bus interface recognizes the RETRY assertion as
a retry termination only if it detects it before the first data beat was acknowledged by the slave device.
When the RETRY signal is asserted as a termination signal on any data beat of the access after the first
(being the first data beat acknowledged by a normal TA assertion), the MPC561/MPC563 recognizes
RETRY as a transfer error acknowledge.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-47
External Bus Interface
CLKOUT
BR
BG (output)
Allow External Master
to Gain the Bus
BB
ADDR[8:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
BI
RETRY
O
If Asserted Will
Cause Transfer Error
Figure 9-34. Retry on Burst Cycle
If a burst access is acknowledged on its first beat with a normal TA but with the BI signal asserted, the
following single-beat transfers initiated by the MPC561/MPC563 to complete the 16-byte transfer
recognizes the RETRY signal assertion as a transfer error acknowledge.
In the case in which a small port size causes the MPC561/MPC563 to break a bus transaction into several
small transactions, terminating any transaction with RETRY causes a transfer error acknowledge. See
Section 9.5.2.3, “Single Beat Flow with Small Port Size.”
MPC561/MPC563 Reference Manual, Rev. 1.2
9-48
Freescale Semiconductor
External Bus Interface
9.5.11.2
Termination Signals Protocol Summary
Table 9-9 summarizes how the MPC561/MPC563 recognizes the termination signals provided by the slave
device that is addressed by the initiated transfer.
Table 9-9. Termination Signals Protocol
9.5.12
TEA
TA
RETRY
Action
Asserted
X
X
Transfer error termination
Negated
Asserted
X
Normal transfer termination
Negated
Negated
Asserted
Retry transfer termination
Bus Operation in External Master Modes
When an external master takes ownership of the external bus and the MPC561/MPC563 is programmed
for external master mode operation, the external master can access the internal space of the
MPC561/MPC563 (see Section 6.1.2, “External Master Modes”). In external master mode, the external
master owns the bus, and the direction of most of the bus signals is inverted, relative to its direction when
the MPC561/MPC563 owns the bus.
The external master gets ownership of the bus and asserts TS in order to initiate an external master access.
The access is directed to the internal bus only if the input address matches the internal address space. The
access is terminated with one of the followings outputs: TA, TEA, or RETRY. If the access completes
successfully, the MPC561/MPC563 asserts TA, and the external master can proceed with another external
master access or relinquish the bus. If an address or data error is detected internally, the MPC561/MPC563
asserts TEA for one clock. TEA should be negated before the second rising edge after it is sampled asserted
in order to avoid the detection of an error for the next bus cycle initiated. TEA is an open drain pin, and
the negation timing depends on the attached pull-up. The MPC561/MPC563 asserts the RETRY signal for
one clock in order to retry the external master access.
If the address of the external access does not match the internal memory space, the internal memory
controller can provide the chip-select and control signals for accesses that belong to one of the memory
controller regions. This feature is explained in Chapter 10, “Memory Controller.”
Figure 9-35 and Figure 9-36 illustrate the basic flow of read and write external master accesses.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-49
External Bus Interface
External Master
MPC500 Device
1. Request Bus (BR)
2. Receives Bus Grant (BG) From Arbiter
3. Asserts Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
1. Receives Address
Address in Internal
Memory Map
No
Yes
1. Returns Data
Memory
Controller
Asserts CSx
If In Range
1. Asserts Transfer Acknowledge (TA)
1. Receives Data
Figure 9-35. Basic Flow of an External Master Read Access
MPC561/MPC563 Reference Manual, Rev. 1.2
9-50
Freescale Semiconductor
External Bus Interface
External Master
MPC500 Device
1. Request Bus (BR)
2. Receives Bus Grant (BG) From Arbiter
3. Asserts Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
1. Receives Address
1. Drives Data
Address in Internal
Memory Map
No
Yes
Memory
Controller
Asserts CSx
If In Range
1. Receives Data
1. Asserts Transfer Acknowledge (TA)
Figure 9-36. Basic Flow of an External Master Write Access
Figure 9-37, Figure 9-38, and Figure 9-39 describe read and write cycles from an external master
accessing internal space in the MPC561/MPC563.
NOTE
The minimum number of wait states for such access is two clocks. The
accesses in these figures are valid for both peripheral mode and slave mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-51
External Bus Interface
CLKOUT
BR (input)
Use the Internal Arbiter
Receive Bus Grant and Bus Busy Negated
BG
O
O
Assert BB, Drive Address and Assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
TS (input)
O
Data
TA (output)
Minimum 2 Wait States
O
Data is valid
Figure 9-37. Peripheral Mode: External Master Reads from MPC561/MPC563 (Two Wait States)
MPC561/MPC563 Reference Manual, Rev. 1.2
9-52
Freescale Semiconductor
External Bus Interface
CLKOUT
BR (input)
Use the Internal Arbiter
BG
Receive Bus Grant and Bus Busy Negated
O
O
Assert BB, Drive Address and Assert TS
BB
O
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
TS (input)
O
Data
TA (output)
O
Minimum 2 Wait States
Data is sampled
Figure 9-38. Peripheral Mode: External Master Writes to MPC561/MPC563 (Two Wait States)
9.5.13
Contention Resolution on External Bus
When the MPC561/MPC563 is in slave mode, external master access to the MPC561/MPC563 internal
bus can be terminated with relinquish and retry in order to allow a pending internal-to-external access to
be executed. The RETRY signal functions as an output that signals the external master to release the bus
ownership and retry the access after one clock.
Figure 9-39 describes the flow of an external master retried access. Figure 9-40 shows the timing when an
external access is retried and a pending internal-to-external access follows.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-53
External Bus Interface
External Master
MPC500 Device
1. Request Bus (BR)
2. Receives Bus Grant (BG) from Arbiter
3. Asserts Bus Busy (BB) if No Other Master is Driving
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
1. Assert Retry
1. Release Bus Request (BR) for One Clock and Request Bus (BR) Again
2. Wait Until Bus Busy Negated (No Other Master is Driving)
3. Assert Bus Busy (BB)
4. Assert Transfer Start (TS)
5. Drives Address and Attributes
1. Receives Address
No
Address in Internal
Memory Map
Yes
Memory
Controller
Asserts CSx
If In Range
1. Returns Data
1. Asserts Transfer Acknowledge (TA)
1. Receives Data
Figure 9-39. Flow of Retry of External Master Read Access
MPC561/MPC563 Reference Manual, Rev. 1.2
9-54
Freescale Semiconductor
External Bus Interface
CLKOUT
BR
BG (output)
Allow Internal
Access to Gain the
Bus
BB
ADDR[8:31]
ADDR (external)
ADDR (internal)
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (output)
O
Note: the delay for the internal to external cycle may be one clock or greater.
Figure 9-40. Retry of External Master Access (Internal Arbiter)
9.5.14
Show Cycle Transactions
Show cycles are representations of RCPU accesses to internal devices of the MPC561/MPC563. These
accesses are driven externally for emulation, visibility, and debugging purposes. A show cycle can have
one address phase and one data phase, or just an address phase in the case of instruction show cycles. The
cycle can be a write or a read access. The data for both the read and write accesses should be driven by the
bus master. (This is different from normal bus read and write accesses.) The address and data of the show
cycle must each be valid on the bus for one clock. The data phase must not require a transfer acknowledge
to terminate the bus show cycle.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-55
External Bus Interface
Show cycles are activated by properly setting the SIUMCR register bits. Refer to Section 6.2.2.1.1, “SIU
Module Configuration Register (SIUMCR).” Construction visibility is controlled by the ISCT_SER bits
in the ICTRL register. Refer to Table 23-26. Data visibility is controlled by the LSHOW bits of the
L2U_MCR register. Refer to Table 11-7.
In a burst show cycle only the first data beat is shown externally. Refer to Table 9-8 for show cycle
transaction encodings.
Instruction show cycle bus transactions have the following characteristics (see Figure 9-41):
• One clock cycle
• Address phase only; in decompression on mode part of the compressed address is driven on data
lines together with address lines. The external bus interface adds one clock delay between a read
cycle and such show cycle.
• STS assertion only (no TA assertion)
The compressed address is driven on the external bus in the following manner:
• ADDR[0:29] = the word base address;
• DATA[0] = operating mode:
— 0 = decompression off mode;
— 1 = decompression on mode;
• DATA[1:4] = bit pointer
See Chapter 4, “Burst Buffer Controller 2 Module” and Appendix A, “MPC562/MPC564 Compression
Features” for more details about decompression mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
9-56
Freescale Semiconductor
External Bus Interface
I
CLKOUT
PTR
BB
ADDR[8:31]
ADDR2
ADDR1
RD/WR
TSIZ[0:1]
BURST
TS
STS
Data
(three-state)
TA
“Compressed” address on data lines
“Normal” Non-Show Cycle Bus Transaction
Instruction Show Cycle Bus Transaction
Figure 9-41. Instruction Show Cycle Transaction
Both read and write data show cycles have the following characteristics: (see Figure 9-42)
• Two clock cycle duration
• Address valid for two clock cycles
• Data is valid only in the second clock cycle
• STS signal only is asserted (no TA or TS)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-57
External Bus Interface
CLKOUT
BR (in)
BG (out)
BB
ADDR[8:31]
ADDR1
ADDR2
RD/WR
TSIZ[0:1]
BURST
TS
STS
Data
DATA1
DATA2
TA
Read Data Show Cycle Bus Transaction
Write Data Show Cycle Bus Transaction
Figure 9-42. Data Show Cycle Transaction
MPC561/MPC563 Reference Manual, Rev. 1.2
9-58
Freescale Semiconductor
Chapter 10
Memory Controller
The memory controller generates interface signals to support a glueless interface to external memory and
peripheral devices. It supports four regions, each with its own programmed attributes. The four regions are
controlled by four chip-select signals. Read and write strobes are also provided.
The memory controller operates in parallel with the external bus interface to support external cycles. When
an access to one of the memory regions is initiated, the memory controller takes ownership of the external
signals and controls the access until its termination. Refer to Figure 10-1.
ADDR[0:31]
EBI Bus
External Bus
Interface
DATA[0:31]
Control Bus
Internal Bus
U-bus
Interface
WE[0:3]/BE[0:3]
Memory Controller
Bus
Memory
Controller
OE
CS[0:3]
Figure 10-1. Memory Controller Function within the USIU
10.1
Overview
The memory controller provides a glueless interface to external EPROM, static RAM (SRAM), Flash
(EEPROM), and other peripherals. The general-purpose chip-selects are available on lines CS0 through
CS3. CS0 also functions as the global (boot) chip-select for accessing the boot Flash EEPROM. The chip
select allows zero to 30 wait states.
Figure 10-2 is a block diagram of the MPC561/MPC563 memory controller.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-1
Memory Controller
Internal Addresses [0:16], AT[0:2]
Base
Register
Option
Register
0 (BR0)
1 (BR1)
2 (BR2)
Base Register 3 (BR3)
Dual Mapping
Base Register (DMBR)
0 (OR0)
1 (OR1)
2 (OR2)
Option Register 3 (OR3)
Dual Mapping
Option Register (DMOR)
Region Match Logic
Attributes
CS[0:3]
Expired
Wait State
Counter
Load
General-Purpose WE/BE[0:3]
Chip-Select
Machine
OE
(GPCM)
Figure 10-2. Memory Controller Block Diagram
Most memory controller features are common to all four banks. (For features unique to the CS0 bank, refer
to Section 10.7, “Global (Boot) Chip-Select Operation.”) A full 32-bit address decode for each memory
bank is possible with 17 bits having address masking. The full 32-bit decode is available, even if all 32
address bits are not MPC561/MPC563 signals connected to the external device.
Each memory bank includes a variable block size of 32 Kbytes, 64 Kbytes and up to four Gbytes. Each
memory bank can be selected for read-only or read/write operation. The access to a memory bank can be
restricted to certain address type codes for system protection. The address type comparison occurs with a
mask option as well.
From 0 to 30 wait states can be programmed with TA generation. Four write-enable and byte-enable
signals (WE/BE[0:3]) are available for each byte that is written to memory. An output enable (OE) signal
is provided to eliminate external glue logic. A memory transfer start (MTS) strobe permits one master on
a bus to access external memory through the chip selects on another.
The memory controller functionality allows MPC561/MPC563-based systems to be built with little or no
glue logic. A minimal system using no glue logic is shown in Figure 10-3. In this example CS0 is used for
MPC561/MPC563 Reference Manual, Rev. 1.2
10-2
Freescale Semiconductor
Memory Controller
a 16-bit boot EPROM and CS1 is used for a 32-bit SRAM. The WE/BE[0:3] signals are used both to
program the EPROM and to enable write access to various bytes in the RAM.
Address
Address
CS0
CE
OE
OE
WE/BE[0:1]
Data
[0:15]
DATA[0:15]
EPROM
MPC500
Address
CS1
CE
WE/BE[0:3]
WE/BE[0:3]
[0:31]
Data
OE
SRAM
Figure 10-3. MPC561/MPC563 Simple System Configuration
10.2
Memory Controller Architecture
The memory controller consists of a basic machine that handles the memory access cycle: the
general-purpose chip-select machine (GPCM).
When any of the internal masters request a new access to external memory, the address of the transfer (with
17 bits having a mask) and the address type (with three bits having a mask) are compared to each one of
the valid banks defined in the memory controller. Refer to Figure 10-4.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-3
Memory Controller
.............
Address Mask
RBA15
RBA4
RBA3
RBA2
RBA1
RBA0
Base Address
M0 M1 M2 M3 M4 M5 M6 M7 . . . . M16
M[0:16]
A[0:16]
cmp cmp cmp cmp cmpcmpcmp cmp cmp cmp cmp
Match
Figure 10-4. Bank Base Address and Match Structure
When a match is found on one of the memory banks, its attributes are selected for the functional operation
of the external memory access:
• Read-only or read/write operations
• Number of wait states for a single memory access, and for any beat in a burst access
• Burst-inhibit indication. Internal burst requests are still possible during burst-inhibited cycles; the
memory controller emulates the burst cycles
• Port size of the external device
Note that if more than one region matches the internal address supplied, then the lowest numbered region
is selected to provide the attributes and the chip select. If the dual mapping region is matched, it has the
highest priority (refer to Section 10.5, “Dual Mapping of the Internal Flash EEPROM Array”).
10.2.1
Associated Registers
Status bits for each memory bank are found in the memory control status register (MSTAT). The MSTAT
reports write-protect violations for all the banks.
Each of the four memory banks has a base register (BR) and an option register (OR). The BRx and ORx
registers contain the attributes specific to memory bank x. The base register contains a valid bit (V) that
indicates the register information for that particular chip select is valid.
10.2.2
Port Size Configuration
The memory controller supports dynamic bus sizing. Defined 8-bit ports can be accessed as odd or even
bytes. Defined 16-bit ports, when connected to data bus lines zero to 15, can be accessed as odd bytes, even
bytes, or even half-words. Defined 32-bit ports can be accessed as odd bytes, even bytes, odd half-words,
even half-words, or words on word boundaries. The port size is specified by the PS bits in the base register.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-4
Freescale Semiconductor
Memory Controller
10.2.3
Write-Protect Configuration
The WP bit in each base register can restrict write access to its range of addresses. Any attempt to write
this area results in the associated WPER bit being set in the MSTAT.
If an attempt to access an external device results in a write-protect violation, the memory controller
considers the access to be no match. No chip-select line is asserted externally, and the memory controller
does not terminate the cycle. The external bus interface generates a normal cycle on the external bus. Since
the memory controller does not acknowledge the cycle internally, the cycle may be terminated by external
logic asserting TA or by the on-chip bus monitor asserting TEA.
10.2.4
Address and Address Space Checking
The base address is written to the BRx. The address mask bits for the address are written to the OR. The
address type access value, if desired, is written to the AT bits in the BRx. The ATM bits in the ORx can be
used to mask this value. If address type checking is not desired, program the ATM bits to zero.
Each time an external bus cycle access is requested, the address and address type are compared with each
one of the banks. If a match is found, the attributes defined for this bank in its BRx and ORx are used to
control the memory access. If a match is found in more than one bank, the lowest bank matched handles
the memory access (e.g., bank zero is selected over bank one).
NOTE
When an external master accesses a slave on the bus, the internal AT[0:2]
lines reaching the memory controller are forced to 100.
10.2.5
Burst Support
The memory controller supports burst accesses of external burstable memory. To enable bursts, clear the
burst inhibit (BI) bit in the appropriate base register. Burst support is for read only.
Bursts can be four or eight beats depending on the value of the BURST_EN bit in the SIUMCR register
and the BL bit in the BRx register. That is, the memory controller executes up to eight one-word accesses,
but when a modulo eight limit is reached, the burst is terminated (even if fewer than eight words have been
accessed).
When the SIU initiates a burst access, if no match is found in any of the memory controller’s regions then
a burst access is initiated to the external bus. The termination of each beat for this access is externally
controlled.
To support different types of memory devices, the memory controller supports two types of timing for the
BDIP signal: normal and late.
NOTE
The BDIP signal itself is controlled by the external bus interface logic. Refer
to Figure 9-13 and Figure 9-14 in Chapter 9, “External Bus Interface."
If the memory controller is used to support an external master accessing an external device with bursts, the
BDIP input signal is used to indicate to the memory controller when the burst is terminated.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-5
Memory Controller
For addition details, refer to Section 9.5.4, “Burst Transfer."
10.2.6
Reduced Data Setup Time
In order to meet timing requirements when interfacing to external memories, the data setup time can be
reduced. This mode can be selected by programming the BRx registers. Thus there is flexibility in how
each region can be configured to operate. The operation mode will be determined dynamically according
to a particular access type. This means that for a memory region with the reduced setup time mode enabled,
the mode will automatically switch to disabled when there is no requirement for the reduced setup time,
(e.g., a back-to-back load/store access). For a new access with burst length more than 1, the operation
mode will be automatically switched back to the reduced setup time mode.
Reduced setup time can be selected via the SST bit in BR[0:3]. See Section 10.9.3, “Memory Controller
Base Registers (BR0–BR3)” for more details. If SCCR[EBDF] is greater than 0, however, an external burst
access with reduced data setup time will corrupt a load/store to any USIU register.
The reduced setup time mode may or may not have a performance impact, depending on the properties of
the memory. Namely, there is always an additional empty cycle between two burst sequences. On the other
hand, this additional cycle, under certain conditions, may be compensated for by reducing the number of
cycles in initial data access and sequential burst beats.
Table 10-1. Timing Requirements for Reduced Setup Time
CPU Specification
Memory Device Requirements
Cycle time at 56 MHz = 17.9 ns
Initial access time = 49 ns
Short setup time = 3 ns
Burst access time = 13 ns
Normal setup time = 6 ns
Additional delay arising from on-board wires and clock skew between
internal clock and CLKOUT
10.2.6.1
Case 1: Normal Setup Time
Initial access:
Initial access time of memory + Data setup time of CPU + Delays = 49 + 6 + 1 = 56ns
To derive the number of clocks required, divide by the system clock cycle time:
56
---------- = 3.13
17.9
therefore 4 cycles are required
Burst access:
Burst access time of memory + Data setup time of CPU + Delays = 13 + 6 + 1 = 20ns
The number of clocks required
20
= ---------- = 1.11
17.9
therefore 2 clocks are required.
This case is illustrated in Figure 10-5.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-6
Freescale Semiconductor
Memory Controller
10.2.6.2
Case 2: Short Setup Time
Initial access:
Enabling short setup time requires one clock cycle:
Initial access time of memory + Data setup time of CPU + Delays = 49 + 3 + 1 = 53ns
53
The number of clocks required = ---------- = 2.96 + 1(SST Enable Clock) = 3.96 therefore 4 clocks are
17.9
required.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-7
Memory Controller
Burst access:
Burst access time of memory + Data setup time of CPU + Delays = 13 + 3 + 1 = 17ns
17
17.9
The number of clocks required = ---------- = 0.95 therefore 1 clock is required.
This case is illustrated in Figure 10-6.
10.2.6.3
Summary of Short Setup Time
With normal setup time and a 4-beat burst, a 4-2-2-2 burst cycle is required which is reduced to a 4-1-1-1
burst cycle with a short setup time. Short setup time creates a saving of three clock cycles with a 4-beat
burst and can result in even better performance with an 8-beat burst, saving seven clock cycles.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-8
Freescale Semiconductor
Memory Controller
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0b0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Normal
BDIP
Late
Last Beat
Expects Another Data
No Data
Expected
Data
TA
1
2
3
4
1st Data
Is Valid
5
6
2nd Data
Is Valid
7
8
3rd Data
Is Valid
9
10
4th Data
Is Valid
Figure 10-5. A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-9
Memory Controller
CLKOUT
BR
BG
BB
ADDR
[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
Last Beat
Expects Another Data
NO DATA
EXPECTED
BDIP
Data
TA
1
2
3
4
5
1st Data
is Valid
6
2nd Data
is Valid
7
3rd Data
is Valid
4th Data
is Valid
Figure 10-6. 4 Beat Burst Read with Short Setup Time (Zero Wait State)
NOTE
An extra clock cycle is required to enable short set-up time, resulting in a
4-1-1-1 cycle.
10.3
Chip-Select Timing
The general-purpose chip-select machine (GPCM) allows a glueless and flexible interface between the
MPC561/MPC563 and external SRAM, EPROM, EEPROM, ROM peripherals. When an address and
MPC561/MPC563 Reference Manual, Rev. 1.2
10-10
Freescale Semiconductor
Memory Controller
address type match the values programmed in the BR and OR for one of the memory controller banks, the
attributes for the memory cycle are taken from the OR and BR registers. These attributes include the
following fields: CSNT, ACS, SCY, BSCY, WP, TRLX, BI, PS, and SETA. Table 10-2 summarizes the
chip-select timing options.
Byte write and read-enable signals (WE/BE[0:3]) are available for each byte that is written to or read from
memory. An output enable (OE) signal is provided to eliminate external glue logic for read cycles. Upon
system reset, a global (boot) chip select is available. (Refer to Section 10.7, “Global (Boot) Chip-Select
Operation” for more information on the global chip select.) This provides a boot ROM chip select before
the system is fully configured.
Table 10-2. Timing Attributes Summary
Timing Attribute
Bits/Fields
Description
Access speed
TRLX
The TRLX (timing relaxed) bit determines strobe timing to be fast or
relaxed.
Intercycle space time
EHTR
The EHTR (extended hold time on read accesses) bit is provided for
devices that have long disconnect times from the data bus on read
accesses. EHTR specifies whether the next cycle is delayed one clock
cycle following a read cycle, to avoid data bus contentions. EHTR
applies to all cycles following a read cycle except for another read cycle
to the same region.
Synchronous or
asynchronous device
ACS, CSNT
The ACS (address-to-chip-select setup) and CSNT (chip-select
negation time) bits cause the timing of the strobes to be the same as the
address bus timing, or cause the strobes to have setup and hold times
relative to the address bus.
Wait states
SCY, BSCY,
SETA, TRLX
From zero to 15 wait states can be programmed for any cycle that the
memory controller generates. The transfer is then terminated internally.
In simplest case, the cycle length equals (2 + SCY) clock cycles, where
SCY represents the programmed number of wait states (cycle length in
clocks). The number of wait states is doubled if the TRLX bit is set (2 +
(SCY x 2)).
When the SETA (external transfer acknowledge) bit is set, TA must be
generated externally, so that external hardware determines the number
of wait states.
NOTE
When a bank is configured for TA to be generated externally (SETA bit is
set) and the TRLX is set, the memory controller requires the external device
to provide at least one wait state before asserting TA to complete the
transfer. In this case, the minimum transfer time is three clock cycles.
The internal TA generation mode is enabled if the SETA bit in the OR register is cleared. However, if the
TA signal is asserted externally at least two clock cycles before the wait states counter has expired, this
assertion terminates the memory cycle. When SETA is cleared, it is forbidden to assert external TA less
than two clocks before the wait states counter expires.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-11
Memory Controller
10.3.1
Memory Devices Interface Example
Figure 10-7 describes the basic connection between the MPC561/MPC563 and a static memory device. In
this case CSx is connected directly to the chip enable (CE) of the memory device. The WE/BE[0:3] lines
are connected to the respective WE in the memory device where each WE/BE line corresponds to a
different data byte.
MPC5xx
Memory
Address
Address
CSx
CE
OE
OE
WE/BE
WE
Data
Data
Figure 10-7. GPCM–Memory Devices Interface
In Figure 10-8, the CSx timing is the same as that of the address lines output. The strobes for the
transaction are supplied by the OE and the WE/BE lines (if programmed as WE/BE). When the ACS bits
in the corresponding ORx register = 00, CS is asserted at the same time that the address lines are valid.
NOTE
If CSNT is set, the WE signal is negated a quarter of a clock earlier than
normal.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-12
Freescale Semiconductor
Memory Controller
Clock
Address
TS
CSNT = 1, ACS = 00
TA
CS
WE/BE
OE
Data
Note: In this and subsequent timing diagrams in this section, the data bus refers to a read cycle. In a write cycle, the data
immediately follows TS.
Figure 10-8. Memory Devices Interface Basic Timing (ACS = 00, TRLX = 0)
10.3.2
Peripheral Devices Interface Example
Figure 10-9 illustrates the basic connection between the MPC561/MPC563 and an external peripheral
device. In this case CSx is connected directly to the chip enable (CE) of the memory device and the R/W
line is connected to the R/W in the peripheral device. The CSx line is the strobe output for the memory
access.
Peripheral
MPC5xx
Address
CSx
RD/WR
Data
Address
CE
RD/WR
Data
Figure 10-9. Peripheral Devices Interface
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-13
Memory Controller
The CSx timing is defined by the setup time required between the address lines and the CE line. The
memory controller allows specification of the CS timing to meet the setup time required by the peripheral
device. This is accomplished through the ACS field in the base register. In Figure 10-10, the ACS bits are
set to 0b11, so CSx is asserted half a clock cycle after the address lines are valid.
CLOCK
ACS = 11
Address
CSNT = 1
TS
TA
CS
RD/WR
Data
Figure 10-10. Peripheral Devices Basic Timing (ACS = 11, TRLX = 0)
10.3.3
Relaxed Timing Examples
The TRLX field is provided for memory systems that need a more relaxed timing between signals. When
TRLX is set and ACS = 0b00, the memory controller inserts an additional cycle between address and
strobes (CS line and WE/OE).
When TRLX and CSNT are both set in a write to memory, the strobe lines (WE/BE[0:3] and CS, if ACS
= 0b00) are negated one clock earlier than in the regular case.
NOTE
In the case of a bank selected to work with external transfer acknowledge
(SETA = 1) and TRLX = 1, the memory controller does not support external
devices that provide TA to complete the transfer with zero wait states. The
minimum access duration in this case equals three clock cycles.
Figure 10-11 shows a read access with relaxed timing. Note the following:
• Strobes (OE and CS) assertion time is delayed one clock relative to address (TRLX bit set effect).
• Strobe (CS) is further delayed (half-clock) relative to address due to ACS field being set to 11.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-14
Freescale Semiconductor
Memory Controller
•
Total cycle length = 5, is determined as follows:
— Two clocks for basic cycle
— SCY = 1 determines 1 wait state, which is multiplied by two due to TRLX being set (2 + (SCY
x 2)).
— Extra clock is added due to TRLX effect on the strobes.
CLOCK
Address
TS
ACS = ‘00’ & TRLX = ‘1’
ACS = ‘11’ & TRLX = ‘1’
TA
CS
RD/WR
WEBS = ‘1’,Line Acts as BE
in Read.
WE/BE
OE
Data
Figure 10-11. Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1)
Figure 10-12 through Figure 10-14 are examples of write accesses using relaxed timing. In Figure 10-12,
note the following points:
• Because TRLX is set, assertion of the CS and WE strobes is delayed by one clock cycle.
• CS assertion is delayed an additional one quarter clock cycle because ACS = 10.
• The total cycle length = three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— An extra clock cycle is required due to the effect of TRLX on the strobes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-15
Memory Controller
CLOCK
Address
TS
TA
ACS = 10
ACS = 00
CS
RD/WR
WE/BE
OE
Data
Figure 10-12. Relaxed Timing — Write Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1)
In Figure 10-13, note the following:
• Because the TRLX bit is set, the assertion of the CS and WE strobes is delayed by one clock cycle.
• Because ACS = 11, the assertion of CS is delayed an additional half clock cycle.
• Because CSNT = 1, WE is negated one clock cycle earlier than normal. (Refer to Figure 10-8.) The
total cycle length is four clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— Two extra clock cycles are required due to the effect of TRLX on the assertion and negation of
the CS and WE strobes.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-16
Freescale Semiconductor
Memory Controller
Clock
Address
TS
ACS =11
ACS=00 & CSNT = 1
TA
CS
RD/WR
WE/BE
OE
CSNT = 1
Data
Figure 10-13. Relaxed Timing — Write Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1)
In Figure 10-14, notice the following:
• Because ACS = 0, TRLX being set does not delay the assertion of the CS and WE strobes.
• Because CSNT = 1, WE/BE is negated one clock cycle earlier than normal. (Refer to Figure 10-8).
• CS is not negated one clock cycle earlier, since ACS = 00.
• The total cycle length is three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— One extra clock cycle is required due to the effect of TRLX on the negation of the WE/BE
strobes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-17
Memory Controller
Clock
Address
TS
No Effect, ACS = 00
TA
CS
RD/WR
WE/BE
OE
CSNT = 1
Data
Figure 10-14. Relaxed Timing — Write Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1
10.3.4
Extended Hold Time on Read Accesses
For devices that require a long disconnection time from the data bus on read accesses, the bit EHTR in the
corresponding OR register can be set. In this case any MPC561/MPC563 access to the external bus
following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access
to the same bank. Figure 10-15 through Figure 10-18 show the effect of the EHTR bit on memory
controller timing.
Figure 10-15 shows a write access following a read access. Because EHTR = 0, no extra clock cycle is
inserted between memory cycles.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-18
Freescale Semiconductor
Memory Controller
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Figure 10-15. Consecutive Accesses (Write After Read, EHTR = 0)
Figure 10-16 shows a write access following a read access when EHTR = 1. An extra clock is inserted
between the cycles. For a write cycle following a read, this is true regardless of whether both accesses are
to the same region.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-19
Memory Controller
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Extra Clock Before Next Cycle Starts.
Long Tdt Allowed
Figure 10-16. Consecutive Accesses (Write After Read, EHTR = 1)
Figure 10-17 shows consecutive accesses from different banks. Because EHTR = 1 (and the accesses are
to different banks), an extra clock cycle is inserted.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-20
Freescale Semiconductor
Memory Controller
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Extra Clock Before Next Cycle Starts
Long Tdt Allowed
Figure 10-17. Consecutive Accesses
(Read After Read From Different Banks, EHTR = 1)
Figure 10-18 shows two consecutive read cycles from the same bank. Even though
EHTR = 1, no extra clock cycle is inserted between the memory cycles. (In the case of two consecutive
read cycles to the same region, data contention is not a concern.)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-21
Memory Controller
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Figure 10-18. Consecutive Accesses (Read After Read from Same Bank, EHTR = 1)
10.3.5
Summary of GPCM Timing Options
Table 10-3 summarizes the different combinations of timing options.
Table 10-3. Programming Rules for Timing Strobes
WE/BE
Address to
OE
CS
Negated to WE/BE or Negated to Negated to
Add/Data
Add/Data
Add/Data
OE
Asserted
Invalid
Invalid
Invalid
Total
Number of
Cycles
TRLX
Access
Type
ACS
CSNT
Address
to CS
Asserted
0
read
00
X
0
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
read
10
X
1/4 * clock
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
read
11
X
1/2 * clock
1/4 * clock
3/4 * clock
X
1/4 * clock
2 + SCY
0
write
00
0
0
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
10
0
1/4 * clock
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
11
0
1/2 * clock
1/4 * clock
3/4 * clock
1/4 * clock
X
2 + SCY
0
write
00
1
0
1/4 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
0
write
10
1
1/4 * clock
1/2 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
MPC561/MPC563 Reference Manual, Rev. 1.2
10-22
Freescale Semiconductor
Memory Controller
Table 10-3. Programming Rules for Timing Strobes (continued)
CSNT
Address
to CS
Asserted
Address to
WE/BE
OE
CS
Negated to WE/BE or Negated to Negated to
Add/Data
OE
Add/Data
Add/Data
Invalid
Asserted
Invalid
Invalid
11
1
1/2 * clock
1/2 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
read
00
X
0
1/4 * clock
3/4 clock
X
1/4 * clock
2+
2 * SCY
1
read
10
X
(1 + 1/4) *
clock
1/4 * clock
(1 + 3/4) *
clock
X
1/4 * clock
3+
2 * SCY
1
read
11
X
(1 + 1/2) *
clock
1/4 * clock
(1 + 3/4) *
clock
X
1/4 * clock
3+
2 * SCY
1
write
00
0
0
1/4 * clock
3/4 clock
1/4 * clock
X
2+
2 * SCY
1
write
10
0
(1 + 1/4) *
clock
1/4 * clock
(1 + 3/4) *
clock
1/4 * clock
X
3+
2 * SCY
1
write
11
0
(1 + 1/2) *
clock
1/4 * clock
(1 + 3/4)
clock
1/4 * clock
X
3+
2 * SCY
1
write
00
1
0
1/4 * clock
3/4 clock
(1 + 1/2) *
clock
X
3+
2 * SCY
1
write
10
1
(1 + 1/4) *
clock
(1 + 1/2) *
clock
(1 + 3/4)
clock
(1 + 1/2) *
clock
X
4+
2 * SCY
1
write
11
1
(1 + 1/2) *
clock
(1 + 1/2) *
clock
(1 + 3/4)
clock
(1 + 1/2) *
clock
X
4+
2 * SCY
TRLX
Access
Type
ACS
0
write
1
Total
Number of
Cycles
Note: Timing in this table refers to the typical timing only. Consult the electrical characteristics for exact worst-case timing values.
1/4 clock actually means 0 to 1/4 clock, 1/2 clock means 1/4 to 1/2 clock.
Additional timing rules not covered in Table 10-3 include the following:
• If SETA = 1, an external TA signal is required to terminate the cycle.
• If TRLX = 1 and SETA = 1, the minimum cycle length = 3 clock cycles (even if SCY = 0000)
• If TRLX = 1, the number of wait states = 2 ∗ SCY & 2 ∗ BSCY
• ACS = 01 is not defined (reserved).
• If EHTR = 1, an extra (idle) clock cycle is inserted between a read cycle and a following read cycle
to another region, or between a read cycle and a following write cycle to any region.
• If LBDIP = 1 (late BDIP assertion), the BDIP signal is asserted only after the number of wait states
for the first beat in a burst have elapsed. See Figure 9-13 in Chapter 9, “External Bus Interface,”
as well as Section 9.5.5, “Burst Mechanism.”
NOTE
The LBDIP/TBDIP function can operate only when the cycle termination is
internal, using the number of wait states programmed in one of the ORx
registers. The LBDIP/TBDIP function cannot be activated at the same
time—results are unknown.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-23
Memory Controller
10.4
Write and Byte Enable Signals
The GPCM determines the timing and value of the WE/BE signals if allowed by the port size of the
accessed bank, the transfer size of the transaction and the address accessed.
The functionality of the WE/BE[0:3] signals depends upon the value of the write enable/byte select
(WEBS) bit in the corresponding BR register. Setting WEBS to 1 will enable these signals as BE, while
clearing it to zero will enable them as WE. WE is asserted only during write access, while BE is asserted
for both read and write accesses. The timing of the WE/BE signals remains the same in either case, and is
determined by the TRLX, ACS and CSNT bits.
The upper WE/BE (WE0/BE0) indicates that the upper eight bits of the data bus (D0–D7) contains valid
data during a write/read cycle. The upper-middle write byte enable (WE1/BE1) indicates that the
upper-middle eight bits of the data bus (D8–D15) contains valid data during a write/read cycle. The
lower-middle write byte enable (WE2/BE2) indicates that the lower-middle eight bits of the data bus
(D16–D23) contains valid data during a write/read cycle. The lower write/read enable (WE3/BE3)
indicates that the lower eight bits of the data bus contains valid data during a write cycle.
The write/byte enable lines affected in a transaction for 32-bit port (PS = 00), a 16-bit port (PS = 10) and
a 8-bit port (PS = 01) are shown in Table 10-4.
Table 10-4. Write Enable/Byte Enable Signals Function1
Address
Transfer
Size
TSIZ
A30 A31
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
HalfWord
1
0
0
0
1
0
1
0
Word
0
0
0
0
32-bit Port Size
16-bit Port Size
WE0/ WE1/ WE2 WE3/ WE0/ WE1/ WE2/
BE0 BE1 BE2 BE3 BE0 BE1 BE2
X
X
X
8-bit Port Size
WE3/
BE3
WE0
WE
WE1
WE3/
2
/
/BE1
BE3
BE2
BE0
X
X
X
Byte
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
This table shows which write enables are asserted (indicated with an ‘X’) for different combinations of port size and
transfer size.
10.5
Dual Mapping of the Internal Flash EEPROM Array
The internal Flash EEPROM (UC3F) module can be mapped to an external memory region controlled by
the memory controller. Only one region can be programmed to be dual-mapped. When dual mapping is
enabled (DME bit is set in the DMBR register) and when an internal address matches the dual-mapped
address range (as programmed in the DMBR) with the cycle type matching the AT/ATM field in
DMBR/DMOR registers, the following occurs:
• The internal Flash memory does not respond to that address
• The memory controller takes control of the external access
MPC561/MPC563 Reference Manual, Rev. 1.2
10-24
Freescale Semiconductor
Memory Controller
•
•
The attributes for the access are taken from one of the base and option registers of the appropriate
chip select
The chip-select region selected is determined by the CS line select bit field (Section 10.9.5,
“Dual-Mapping Base Register (DMBR)”).
With dual mapping, aliasing of address spaces may occur. This happens when the region is dual-mapped
into a region which is also mapped into one of the four regions available in the memory controller. If code
or data is written to the dual-mapped region, care must be taken to avoid overwriting this code or data by
normal accesses of the chip-select region.
There is a match if:
bus_address[0:16] == {0000000,ISB[0:2],0,BA[1:6]}
Eqn. 10-1
where BA represents the bit field in the DMBR register.
Eqn. 10-2
Care must also be taken to avoid overwriting “normal” CSx data with dual-mapped code or data.
One way to avoid this situation is by disabling the chip-select region and enabling only the dual-mapped
region (DMBR[DME] = 1, but BRx[V] = 0). Figure 10-19 illustrates the phenomenon.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-25
Memory Controller
MPC5xx Memory Map
Dual Mapping
Physical External Memory
CSx
Dual-Map region
Flash
External CSx
Figure 10-19. Aliasing Phenomenon Illustration
NOTE
The default state is to allow dual-mapping data accesses only; this means
that dual mapping is possible only for data accesses on the internal bus.
Also, the default state takes the lower 2 Mbytes of the MPC563 internal
Flash memory. Hence, caution should be taken to change the dual-mapping
setup before the first data access. Dual mapping is not supported for an
external master when the memory controller serves the access; in such a
case, the MPC561/MPC563 terminates the cycle by asserting TEA.
10.6
Dual Mapping of an External Flash Region
The dual mapping feature also enables mapping of external memory to alternative memory regions
controlled by the memory controller. When dual mapping is enabled and an external address matches a
MPC561/MPC563 Reference Manual, Rev. 1.2
10-26
Freescale Semiconductor
Memory Controller
dual mapped address, and the cycle type matches AT/ATM field in DMBR/DMOR register, then the
following occur:
• The chip-select that is mapped to the access does not respond to that address (it remains negated)
• The chip-select region selected is determined by the DMCS bit field in the DMBR register
• The attributes for the access are taken from the corresponding chip select region
Dual mapping can only be enabled over memory addresses in the range 0x0000 0000 through 0x000F
FFFF.
NOTE
Internal Flash must be disabled to use dual mapping over an external
memory.
10.7
Global (Boot) Chip-Select Operation
Global (boot) chip-select operation allows address decoding for a boot ROM before system initialization.
If the global chip-select feature is enabled then the memory controller is enabled from reset.
The global chip select port size is programmable at system reset using RCW[BPS]. The global chip select
does not provide write protection and responds to all address types, allowing a boot ROM to be located
anywhere in the address space.
The memory controller will operate in this boot mode until the first write to any chip select option register
(ORx).The chip select signal can be programmed to continue decoding a range of addresses after this write,
provided the preferred address range is first loaded into the chip select base register (BRx). After the first
write to ORx, the global chip select can only be restarted with a system reset.
Which chip-select line is used as the global chip select, and how it operates, is determined by the reset
configuration parameters:
• FLEN – Internal Flash enable (bit 20)
• BDIS – Boot disable (bit 3)
• DME – Dual mapping enable (bit 31)
Table 10-6 summarizes global chip select operations for all combinations of values on these reset
configuration word lines.In case 1, where FLEN, BDIS, DME = 0b000 (all cleared) at reset, CS0 is the
global chip-select output. When the RCPU begins accessing memory after system reset, CS0 is asserted
for every address, for accesses to both internal and external instructions and data.
In case 2, where FLEN, BDIS, DME = 0b001 at reset, CS0 is asserted for all external address accesses
(instructions and data) and for internal instruction accesses. However, CS3 is asserted for all internal data
accesses. CS3 is used in this case to allow dual mapping of loads/stores to/from an alternative bank which
is not the memory bank normally used for instructions/data. In this way CS3 can be used to allow
load/store from a different memory bank from reset. DME can then be disabled as required.
The global chip select feature is disabled by driving only the BDIS line of the RCW (FLEN, BDIS,
DME = 0b010). This is shown in case 3 of Table 10-6.
Table 10-5 shows the initial values of the “boot bank” in the memory controller.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-27
Memory Controller
Table 10-5. Boot Bank Fields Values After Hard Reset
10.8
Field
Value (Binary)
PS
RCW[4:5] BPS
SST
0
BL
0
WP
0
SETA
0
BI
0b1
V
CS0 = ID3
CS3 = ID20 & ID31
AM[0:16]
0 0000 0000 0000 0000
ATM[0:2]
000
CSNT
0
ACS[0:1]
00
EHTR
0
SCY[0:3]
0b1111
BSCY[0:2]
0b011
TRLX
0
Memory Controller External Master Support
The memory controller in the MPC561/MPC563 supports accesses initiated by both internal and external
bus masters to external memories. If the address of any master is mapped within the internal
MPC561/MPC563 address space, the access will be directed to the internal device, and will be ignored by
the memory controller. If the address is not mapped internally, but rather mapped to one of the memory
controller regions, the memory controller will provide the appropriate chip select and strobes as
programmed in the corresponding region (see Section 6.2.2.1.3, “External Master Control Register
(EMCR)”).
The MPC561/MPC563 supports only synchronous external bus masters. This means that the external
master works with CLKOUT and implements the MPC561/MPC563 bus protocol to access a slave device.
A synchronous master initiates a transfer by asserting TS. The ADDR[0:31] signals must be stable from
the rising edge of CLKOUT during which TS is sampled, until the last TA acknowledges the transfer. Since
the external master works synchronously with the MPC561/MPC563, only setup and hold times around
the rising edge of CLKOUT are important. Once the TS is detected/asserted, the memory controller
compares the address with each one of its defined valid banks to find a possible match. But, since the
external address space is shorter than the internal space, the actual address that is used for comparing
against the memory controller regions is in the format of: {00000000, bits [8:16] of the external address}.
In the case where a match is found, the controls to the memory devices are generated and the transfer
acknowledge indication (TA) is supplied to the master.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-28
Freescale Semiconductor
Memory Controller
Because it takes two clocks for the external address to be recognized and handled by the memory
controller, the TS which is generated by the external master is ahead of the corresponding CS and strobes
which are asserted by the memory controller. This 2-clock delay might cause problems in some
synchronous memories. To overcome this, the memory controller generates the MTS (memory transfer
start) strobe which can be used in the slave’s memory instead of the external master’s TS signal. As seen
in Figure 10-20, the MTS strobe is synchronized to the assertion of CS by the memory controller so that
the external memory can latch the external master’s address correctly. To activate this feature, the MTSC
bit must be set in the SIUMCR register. Use external logic to control devices that can have burst accesses
from an external master.
On the MPC563, when the external master accesses the internal Flash when it is disabled, the access is
terminated with the transfer error acknowledge (TEA) signal asserted, and the memory controller does not
support this access in any way.
When the memory controller serves an external master, the BDIP signal becomes an input signal. This
signal is watched by the memory controller to detect when the burst is terminated.
Synchronous External Master
TA
TS
BDIP
Data
ADDR
BURST
Memory
MPC5xx
TA
TS
MTS
TS
Address
Address
CSx
CE
OE
OE
WE/BE
W
BDIP
BDIP
Data
Data
BURST
BURST
NOTE: The memory controller’s BDIP line is used as a burst_in_progress signal.
Figure 10-20. Synchronous External Master
Configuration for GPCM-Handled Memory Devices
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-29
Memory Controller
Address
Match
&
Compare
Memory
Device
Access
CLOCK
ADDR[0:31]
RD/WR
BURST
TSIZE
TS
MTS
TA
CS
WE/BE
OE
Data
Figure 10-21. Synchronous External Master Basic Access (GPCM Controlled)
NOTE
Because the MPC561/MPC563 has only 24 address signals, the eight most
significant internal address lines are driven as 0b0000_0000, and so
compared in the memory controller’s regions.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-30
Freescale Semiconductor
Memory Controller
10.9
Programming Model
The registers in Table 10-6 are used to control the memory controller.
Table 10-6. Memory Controller Address Map
10.9.1
Address
Register
0x2F C100
Base Register Bank 0 (BR0)
0x2F C104
Option Register Bank 0 (OR0)
0x2F C108
Base Register Bank 1 (BR1)
0x2F C10C
Option Register Bank 1 (OR1)
0x2F C110
Base Register Bank 2 (BR2)
0x2F C114
Option Register Bank 2 (OR2)
0x2F C118
Base Register Bank 3 (BR3)
0x2F C11C
Option Register Bank 3 (OR3)
0x2F C120 — 0x13F
Reserved
0x2F C140
Dual-Mapping Base Register (DMBR)
0x2F C144
Dual-Mapping Option Register (DMOR)
0x2F C148 — 0x2F C174
Reserved
0x2F C178
Memory Status Register (MSTAT)
General Memory Controller Programming Notes
1. In the case of an external master that accesses an internal MPC561/MPC563 module (in slave or
peripheral mode), if that slave device address also matches one of the memory controller’s regions,
the memory controller will not issue any CS for this access, nor will it terminate the cycle. Thus,
this practice should be avoided. Be aware also that any internal slave access prevents memory
controller operation.
2. If the memory controller serves an external master, then it can support accesses to 32-bit port
devices only. This is because the MPC561/MPC563 external bus interface cannot initiate extra
cycles to complete an access to a smaller port-size device as it does not own the external bus.
3. When the SETA bit in the base register is set, then the timing programming for the various strobes
(CS, OE and WE/BE) may become meaningless.
4. When configuring a chip select for a memory region with the intent to access that region
immediately after configuration, then an ISYNC instruction should be executed in order to ensure
that the configuration takes effect before any accesses are initiated.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-31
Memory Controller
10.9.2
Memory Controller Status Registers (MSTAT)
,
MSB
0
LSB
1
2
3
Field
4
5
6
7
—
8
9
10
11
12
13
WPER0 WPER1 WPER2 WPER3
HRESET
14
15
—
0000_0000_0000_0000
Addr
0x2F C178
Figure 10-22. Memory Controller Status Register (MSTAT)
Table 10-7. MSTAT Bit Descriptions
Bits
Name
0:7
—
8:11
12:15
10.9.3
Description
Reserved
WPER0 – Write protection error for bank x. This bit is asserted when a write-protect error occurs for the
WPER3 associated memory bank. A bus monitor (responding to TEA assertion) will, if enabled, prompt
the read of this register if TA is not asserted during a write cycle. WPERx is cleared by writing
one to the bit or by performing a system reset. Writing a zero has no effect on WPER.
—
Reserved
Memory Controller Base Registers (BR0–BR3)
,
MSB
0
1
2
3
4
5
6
7
8
Field
9
10
11
12
13
14
15
BA
HRESET(BR0)
Unchanged
HRESET(BR[1:3])
Unchanged
Addr
0x2F C100 (BR0); 0x2F C108 (BR1); 0x2F C110 (BR2); 0x2F C118 (BR3)
LSB
16
BA
HRESET(BR0)
HRESET(BR[1:3])
1
2
17
18
19
AT
Unchanged
20
21
22
23
PS
SST WP
ID[4:5]
00
24
25
—
BL
Undefined
26
27
28
29
WEBS TBDIP LBDIP SETA
0
Undefined
30
31
BI
V
1
ID3
X2
Unchanged
The reset value is determined by the value on the internal data bus during reset (reset-configuration word).
See Table 10-9 for reset value.
Figure 10-23. Memory Controller Base Registers 0–3 (BR0–BR3)
MPC561/MPC563 Reference Manual, Rev. 1.2
10-32
Freescale Semiconductor
Memory Controller
Table 10-8. BR0–BR3 Bit Descriptions
Bits
Name
Description
0:16
BA
Base address. These bits are compared to the corresponding unmasked address signals among
ADDR[0:16] to determine if a memory bank controlled by the memory controller is being
accessed by an internal bus master. (The address types are also compared.) These bits are used
in conjunction with the AM[0:16] bits in the OR.
17:19
AT
Address type. This field can be used to require accesses of the memory bank to be limited to a
certain address space type. These bits are used in conjunction with the ATM bits in the OR. Note
that the address type field uses only AT[0:2] and does not need AT3 to define the memory type
space. For a full definition of address types, refer to Section 9.5.8.6, “Address Types.”
20:21
PS
Port size
00 32-bit port
01 8-bit port
10 16-bit port
11 Reserved
22
SST
Short Setup Time – This field specifies the setup time required for this memory region.
0 Normal setup time (like the MPC555)
1 Short Setup Time selected
Note that an external burst access with short setup timing will corrupt any USIU register
load/store if SCCR[EBDF] is not 0b00. Refer to Table 8-9.
23
WP
Write protect. An attempt to write to the range of addresses specified in a base address register
that has this bit set can cause the TEA signal to be asserted by the bus-monitor logic (if enabled),
causing termination of this cycle.
0 Both read and write accesses are allowed
1 Only read accesses are allowed. The CSx signal and TA are not asserted by the memory
controller on write cycles to this memory bank. WPER is set in the MSTAT register if a write to
this memory bank is attempted
24
—
Reserved
25
BL
Burst Length – This field specifies the maximum number of words that may comprise a burst
access for this memory region. This field has an effect only in the case when the burst accesses
are initiated by the USIU (SIUMCR[BURST_EN] =1).
0 Burst access of up to 4 words
1 Burst access of up to 8 words
26
WEBS
Write-enable/byte-select. This bit controls the functionality of the WE/BE pads.
0 The WE/BE pads operate as WE
1 The WE/BE pads operate as BE
27
TBDIP
Toggle-burst data in progress. TBDIP determines how long the BDIP strobe will be asserted for
each data beat in the burst cycles.
28
LBDIP
Late-burst-data-in-progress (LBDIP). This bit determines the timing of the first assertion of the
BDIP signal in burst cycles.
NOTE: Do not set both LBDIP and TBDIP bits in a region’s base registers; behavior in such cases
is unpredictable.
0 Normal timing for BDIP assertion (asserts one clock after negation of TS)
1 Late timing for BDIP assertion (asserts after the programmed number of wait states)
29
SETA
External transfer acknowledge
0 TA generated internally by memory controller
1 TA generated by external logic. Note that programming the timing of CS/WE/OE strobes may
have no meaning when this bit is set
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-33
Memory Controller
Table 10-8. BR0–BR3 Bit Descriptions (continued)
Bits
Name
Description
30
BI
Burst inhibit
0 Memory controller drives BI negated (high). The bank supports burst accesses.
1 Memory controller drives BI asserted (low). The bank does not support burst accesses.
NOTE: Following a system reset, the BI bit is set.
31
V
Valid bit. When set, this bit indicates that the contents of the base-register and option-register
pair are valid. The CS signal does not assert until the V-bit is set.
NOTE: An access to a region that has no V-bit set may cause a bus monitor timeout. See
Table 10-9 for the reset value of this bit in BR0.
Table 10-9. BRx[V] Reset Value
10.9.4
Branch Register
BRx[V] Reset Value
BR0
ID3
BR1
0
BR2
0
BR3
ID20 & ID31
Memory Controller Option Registers (OR0–OR3)
1,
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AM1
Field
HRESET
0000_0000_0000_0000
Addr
0x2F C104 (OR0); 0x2F C10C (OR1); 0x2F C114 (OR2), 0x2F C11C (OR3)
LSB
16
AM
HRESET
1
17
18
ATM
19
20
CSNT
0000_0000
21
22
ACS
23
EHTR
24
25
26
27
28
SCY
1111
It is recommended that this field hold values that are the power of 2 minus 1 (e.g.,
29
30
BSCY
0
23 -
1
31
TRLX
1
0
1 = 7 [0b111]).
Figure 10-24. Memory Controller Option Registers 1–3 (OR0–OR3)
MPC561/MPC563 Reference Manual, Rev. 1.2
10-34
Freescale Semiconductor
Memory Controller
Table 10-10. OR0–OR3 Bit Descriptions
Bits
Name
Description
0:16
AM
Address mask. This field allows masking of any corresponding bits in the associated base
register. Masking the address bits independently allows external devices of different size address
ranges to be used. Any clear bit masks the corresponding address bit. Any set bit causes the
corresponding address bit to be used in comparison with the address signals. Address mask bits
can be set or cleared in any order in the field, allowing a resource to reside in more than one area
of the address map. This field can be read or written at anytime.
Following a system reset, the AM bits are cleared in OR0.
17:19
ATM
Address type mask. This field masks selected address type bits, allowing more than one address
space type to be assigned to a chip-select. Any set bit causes the corresponding address type
code bits to be used as part of the address comparison. Any cleared bit masks the corresponding
address type code bit. Clear the ATM bits to ignore address type codes as part of the address
comparison. Note that the address type field uses only AT[0:2] and does not need AT3 to define
the memory type space.
Following a system reset, the ATM bits are cleared in OR0.
20
CSNT
21:22
ACS
23
EHTR
Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after
a read access from the current bank and any MPC561/MPC563 write accesses or read accesses
to a different bank.
0 Memory controller generates normal timing
1 Memory controller generates extended hold timing
Following a system reset, the EHTR bits are cleared in OR0.
24:27
SCY
Cycle length in clocks. This four-bit value represents the number of wait states inserted in the
single cycle, or in the first beat of a burst, when the GPCM handles the external memory access.
Values range from 0 (0b0000) to 15 (0b1111). This is the main parameter for determining the
length of the cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length is (2 + SCY) x Clocks.
If an external TA response is selected for this memory bank (by setting the SETA bit), then the
SCY field is not used.
Following a system reset, the SCY bits are set to 0b1111 in OR0.
Chip-select negation time. Following a system reset, the CSNT bit is reset in OR0.
0 CS/WE are negated normally.
1 CS/WE are negated a quarter of a clock earlier than normal
Following a system reset, the CSNT bit is cleared in OR0.
Address to chip-select setup. Following a system reset, the ACS bits are reset in OR0.
00 CS is asserted at the same time that the address lines are valid.
01 Reserved
10 CS is asserted a quarter of a clock after the address lines are valid.
11 CS is asserted half a clock after the address lines are valid
Following a system reset, the ACS bits are cleared in OR0.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-35
Memory Controller
Table 10-10. OR0–OR3 Bit Descriptions (continued)
Bits
Name
Description
28:30
BSCY
Burst beats length in clocks. This field determines the number of wait states inserted in all burst
beats except the first, when the GPCM starts handling the external memory access and thus
using SCY[0:3] as the main parameter for determining the length of that cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length for the beat is (1 + BSCY) x Clocks.
If an external TA response has been selected for this memory bank (by setting the SETA bit) then
BSCY[0:3] are not used.
000 0-clock-cycle (1 clock per data beat)
001 1-clock-cycle wait states (2 clocks per data beat)
010 2-clock-cycle wait states (3 clocks per data beat)
011 3-clock-cycle wait states (4 clocks per data beat)
1xx Reserved
Following a system reset, the BSCY bits are set to 0b011 in OR0.
31
TRLX
Timing relaxed. This bit, when set, modifies the timing of the signals that control the memory
devices during a memory access to this memory region. Relaxed timing multiplies by two the
number of wait states determined by the SCY and BSCY fields. Refer to Section 10.3.5,
“Summary of GPCM Timing Options,” for a full list of the effects of this bit on signals timing.
0 Normal timing is generated by the GPCM.
1 Relaxed timing is generated by the GPCM
Following a system reset, the TRLX bit is set in OR0.
10.9.5
Dual-Mapping Base Register (DMBR)
,
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Field
—
BA
—
AT
—
HRESET
0
Undefined
000
001
000
Addr
15
0x2F C140
LSB
16
17
18
19
Field
21
22
23
24
25
26
27
—
HRESET
1
20
28
29
30
DMCS
ID201
0000_0000_0000_0
31
DME
ID311
The reset value is a reset configuration word value extracted from the indicated internal data bus lines. Refer to
Section 7.5.2, “Hard Reset Configuration Word (RCW).”
Figure 10-25. Dual-Mapping Base Register (DMBR)
Table 10-11. DMBR Bit Descriptions
Bits
Name
Description
0
—
Reserved
1:6
BA
Base address. BA field corresponds to address bits [11:16]. The base address field is
compared (along with the address type field) to the address of the address bus to determine
whether an address should be dual-mapped by one of the memory banks controlled by the
memory controller. These bits are used in conjunction with the AM[11:16] bits in the DMOR.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-36
Freescale Semiconductor
Memory Controller
Table 10-11. DMBR Bit Descriptions
Bits
Name
7:9
—
Reserved
10:12
AT
Address type. This field can be used to specify that accesses involving the memory bank are
limited to a certain address space type. These bits are used in conjunction with the ATM bits
in the OR. The default value at reset is to map data only. For a full definition of address types,
refer to Section 9.5.8.6, “Address Types.”
13:27
—
Reserved
28:30
DMCS
Dual-mapping chip select. This field determines which chip-select signal is assigned for dual
mapping.
000 CS0
001 CS1
010 CS2
011 CS3
1xx Reserved
31
DME
Dual mapping enabled. This bit indicates that the contents of the dual-mapping registers and
associated base and option registers are valid and enables the dual-mapping operation. The
default value at reset comes from the internal data bus that reflects the reset configuration
word. See Section 10.5, “Dual Mapping of the Internal Flash EEPROM Array,” for more
information.
0 Dual mapping is not active
1 Dual mapping is active
10.9.6
Description
Dual-Mapping Option Register (DMOR)
,
MSB
0
Field
1
2
3
4
5
6
7
8
AM1
—
HRESET
9
10
—
0000_0000_00
Addr
11
12
13
14
ATM
—
001
000
15
0x2F C144
LSB
16
17
Field
HRESET
1
18
19
20
21
22
23
24
25
26
27
28
29
30
31
—
0000_0000_0000_0000
It is recommended that this field hold values that are the power of 2 minus 1 (e.g., 23 - 1 = 7 [0b111]).
Figure 10-26. Dual-Mapping Option Register (DMOR)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-37
Memory Controller
Table 10-12. DMOR Bit Descriptions
Bits
Name
Description
0
—
Reserved
1:6
AM
Address mask. The address mask field of each option register provides for masking any of the
corresponding bits in the associated base register. By masking the address bits independently,
external devices of different size address ranges can be used. Any clear bit masks the
corresponding address bit. Any set causes the corresponding address bit to be used in the
comparison with the address signals. Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one area of the address map. This field
can be read or written at any time.
7:9
—
Reserved
10:12
ATM
13:31
—
Address type mask. This field can be used to mask certain address type bits, allowing more
than one address space type to be assigned to a chip select. Any set bit causes the
corresponding address type code bits to be used as part of the address comparison. Any
cleared bit masks the corresponding address type code bit.
To instruct the memory controller to ignore address type codes as part of the address
comparison, clear the ATM bits.
NOTE: Following a system reset, the ATM bits are cleared in DMOR, except the ATM2 bit. This
means that only data accesses are dual mapped. Refer to the address types definition in
Table 9-8.
Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
10-38
Freescale Semiconductor
Chapter 11
L-Bus to U-Bus Interface (L2U)
The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the
unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides
protection for data memory accesses.
The L2U is bidirectional. It allows load/store accesses not intended for the L-bus data RAM to go to the
U-bus. It also allows code execution from the L-bus data RAM and read/write accesses from the U-bus to
the L-bus.
The L2U directs bus traffic between the L-bus and the U-bus. When transactions start concurrently on both
buses, the L2U interface arbitrates to select which transaction is handled. The top priority is assigned to
U-bus to L-bus accesses; lower priority is assigned to the load/store accesses by the RCPU.
11.1
•
•
•
•
•
•
11.2
•
•
General Features
Non-pipelined master and slave on U-bus
— Does not start two back-to-back accesses on the U-bus
— Supports U-bus pipelining
— Retries back-to-back accesses from U-bus masters
Non-pipelined master and slave on the L-bus
Generates module selects for L-bus memory-mapped resources within a programmable,
contiguous block of storage
Programmable data memory protection unit (DMPU)
L-bus and U-bus snoop logic for the reservation protocol compatible with the PowerPC ISA
architecture
Show cycles for RCPU accesses to the CALRAM (none, all, writes)
— Protection for CALRAM accesses from the U-bus side (all accesses to the CALRAM from the
U-bus side are blocked once the CALRAM protection bit is set)
Data Memory Protection Unit Features
Supports four memory regions whose base address and size can be programmed
— Available sizes are 4 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes, 256
Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, and 16 Mybtes
— Region must start on the specified region size boundary (modulo addressing)
— Overlap between regions is allowed
Each of the four regions supports the following attributes:
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-1
L-Bus to U-Bus Interface (L2U)
•
•
•
•
•
11.3
– Access protection: user or supervisor
– Guarded attribute: speculative or non-speculative
– Enable/disable option
– Read only option
Supports a default global entry for memory space not covered by other regions:
— Default access protection
— Default guarded attribute
Interrupt generated upon:
— Access violation
— Load from guarded region
— Write to read-only region
The MSR[DR] bit (data relocate) controls DMPU protection on/off operation
Programming is done using the mtspr/mfspr instructions to/from implementation-specific special
purpose registers.
No protection for accesses to the CALRAM module on the L-bus (CALRAM has its own
protection options)
L2U Block Diagram
Figure 11-1 shows a block diagram of the L-bus to U-bus interface as implemented in the overall
MPC561/MPC563 bus architecture.
MPC561/MPC563 Reference Manual, Rev. 1.2
11-2
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
U-Bus
Burst Buffer
Controller
MPC500
DMPU
Core
+
FP
L-Bus
L-Bus
Interface
Reservation
Control
USIU
E-Bus
U-Bus
Interface
Address
Decode
L-Bus to U-Bus Interface
UIMB
Interface
IMB3
Figure 11-1. L2U Bus Interface Block Diagram
11.4
Modes Of Operation
The L2U module can operate in the following modes:
• Normal mode
• Reset operation
• Peripheral mode
• Factory test mode
11.4.1
Normal Mode
In normal mode (master or slave) the L2U module acts as a bidirectional protocol translator.
• In master mode the RCPU is fully operational, and there is no external master access to the U-bus.
• Slave mode enables an external master to access any internal bus slave while the RCPU is fully
operational. The L2U transfers load/store accesses from the RCPU to the U-bus and the read/write
accesses by the U-bus master to the L-bus.
In addition to the bus protocol translation, the L2U supports other functions such as show cycles, data
memory protection, and MPC500 reservation protocol.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-3
L-Bus to U-Bus Interface (L2U)
When a load to or store from the U-bus resource is issued by the RCPU, it is compared against the DMPU
region access (address and attribute) comparators. If none of the access attributes are violated, the access
is directed to the U-bus by the L2U module. If the DMPU detects an access violation, it informs the error
status to the master initiating the cycle.
When show cycles are enabled, accesses to all of the L-bus resources by the RCPU are made visible on
the U-bus side by the L2U.
The L2U is responsible for handling the effects of reservations on the L-bus and the U-bus. For the L-bus
and the U-bus, the L2U detects reservation losses and updates the RCPU core with the reservation status.
11.4.2
Reset Operation
While hard or soft reset is asserted on the U-bus, the L2U asserts the corresponding L-bus reset signals.
Upon soft reset assertion, the L2U goes to an idle state and all pending accesses are ignored. Additionally,
the L2U module control registers are not initialized on soft reset, keeping the system configuration
unchanged.
Upon assertion of hard reset, the L2U control registers are initialized to their reset states. The L2U also
drives the reset configuration word from the U-bus to the L-bus upon hard reset.
11.4.3
Peripheral Mode
In the peripheral mode of operation the RCPU is shut down and an alternative master on the external bus
can perform accesses to any internal bus (U-bus and L-bus) slave.
The external master can also access the internal MPC500 special registers that are located in the L2U
module. In order to access one of these MPC500 registers the EMCR[CONT] bit in the USIU must be
cleared.
11.4.4
Factory Test Mode
Factory test mode is a special mode of operation that allows access to the internal modules for testing. This
mode is not intended for general use and is not supported for normal applications.
11.5
Data Memory Protection
The data memory protection unit (DMPU) in the L2U module provides access protection for the memory
regions on the U-bus side from load/store accesses by the RCPU. (Only U-bus space is protected.) The
DMPU does not protect MPC500 register accesses initiated by the RCPU on the L-bus. The user can assign
up to four regions of access protection attributes and can assign global attributes to any space not included
in the active regions. When it detects an access violation, the L2U generates an exception request to the
CPU. A functional diagram of the DMPU is shown in Figure 11-2.
MPC561/MPC563 Reference Manual, Rev. 1.2
11-4
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
Address
Access Attribute
Region0 Address and size
Region1 Address and size
Region2 Address and size
Region0 protection/attribute
Match
Select
Region1 protection/attribute
Region2 protection/attribute
Region3 protection/attribute
Region3 Address and size
Global protection/attribute
Specific
Error Interrupts
to Core
Region Protection/Attribute
MSR[DR]
Exception
Logic
Access
Granted
Figure 11-2. DMPU Basic Functional Diagram
11.5.1
Functional Description
Data memory protection is assigned on a regional basis. Default manipulation of the DMPU is done on a
global region. The DMPU has control registers that contain the following information: region protection
on/off, region base address, region size, and the region’s access permissions. Each region’s protection
attributes can be turned on or off by configuring the global region attribute register’s enable attribute bit
(L2U_GRA[ENRx]).
During each load or store access from the RCPU to the U-bus, the address is compared to the value in the
region base address register of each enabled region. Any access that matches the specific region within its
appropriate size, as defined by the region attribute register’s region size field (L2U_RAx[RS]), sets a
match indication.
When more than one match indication occurs, the effective region is the region with the highest priority.
Priority is determined by region number; highest priority corresponds to the lowest region number, e.g.
region 0 is highest priority, while region 3 is lowest.
When no match occurs, the effective region is the global region, which has the lowest priority.
The region attribute register also contains the region’s protection fields. The protection field (PP) of the
effective region is compared to the access attributes. If the attributes match, the access is permitted. When
the access is permitted, a U-bus access may be generated according to the specific attribute of the effective
region.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-5
L-Bus to U-Bus Interface (L2U)
When the access by the RCPU is not permitted, the L2U module asserts a data memory storage exception
to the RCPU.
For speculative load/store accesses from the RCPU to a region marked as guarded (G bit of region attribute
register is set), the L2U asks the RCPU to retry the L-bus cycle until either the access is not speculative,
or is canceled by the RCPU.
In the case of attempted accesses to a guarded region together with any other protection violation (no
access), the L2U retries the access. The L2U handles this event as a data storage violation only when the
access becomes non-speculative.
Note that access protection is active only when the MPC500’s MSR[DR] = 1. When MSR[DR] = 0, DMPU
exceptions are disabled, all accesses are considered to be to a guarded memory area, and no speculative
accesses are allowed. In this case, if the L-bus master [RCPU] initiates a non-CALRAM cycle (access
through the L2U) that is marked speculative, the L2U asks the RCPU to retry the L-bus cycle until either
the access is not speculative, or it is canceled by the RCPU Core.
NOTE
The programmer must not overlap the CALRAM memory space with any
enabled region. Overlapping an enabled region with CALRAM memory
space disables the L2U data memory protection for that region.
If an enabled region overlaps with the L-bus space, the DMPU ignores all
accesses to addresses within the L-bus space. If an enabled region overlaps
with MPC500 register addresses, the DMPU ignores any access marked as
an MPC500 access.
11.5.2
Associated Registers
Table 11-1 shows registers that are used to control the DMPU of the L2U module. All the registers are
special purpose registers that are accessed via the MPC500 mtspr/mfspr instructions. The registers are also
accessed by an external master when EMCR[CONT] = 0. See Section 11.8, “L2U Programming Model,”
for register diagrams and bit descriptions.
.
Table 11-1. DMPU Registers
Name
Description
L2U_RBA0
Region Base Address Register 0
L2U_RBA1
Region Base Address Register 1
L2U_RBA2
Region Base Address Register 2
L2U_RBA3
Region Base Address Register 3
L2U_RA0
Region Attribute Register 0
L2U_RA1
Region Attribute Register 1
L2U_RA2
Region Attribute Register 2
L2U_RA3
Region Attribute Register 3
L2U_GRA
Global Region Attribute
MPC561/MPC563 Reference Manual, Rev. 1.2
11-6
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
NOTE
The appropriate DMPU registers must be programmed before the MSR[DR]
bit is set. Otherwise, DMPU operation is not guaranteed.
Program the region base address in the L2U_RBAx registers to the lower boundary of the region specified
by the corresponding L2U_RAx[RS] field. If the region base address does not correspond to the boundary
of the block size programmed in the L2U_RAx, the DMPU snaps the region base to the lower boundary
of that block. For example, if the block size is programmed to 16 Kbytes for region zero (i.e.,
L2U_RA0[RS] = 0x3) and the region base address is programmed to 0x1FFF(i.e., L2U_RBA0[RBA] =
0x1), then the effective base address of region zero is 0x0. See Figure 11-3.
0x0000 0000
Region 0
(16 Kbytes)
Resulting Region
0x0000 1FFF
Actual Programmed Region
0x0000 3FFF
0x0000 5FFF
Figure 11-3. Region Base Address Example
External action is required to program only legal region sizes. The L2U does not check whether the value
is legal. If an illegal region size is programmed, the region calculation may not be successful.
11.5.3
L-Bus Memory Access Violations
All L-bus slaves have their own access protection logic. For consistency, all storage access violations have
the same termination result. Thus access violations for load/store accesses started by the RCPU always
have the same termination from all slaves: assertion of the data storage exception. All other L-bus masters
cause machine check exceptions.
11.6
Reservation Support
In general terms, a reservation activity is the process whereby a load and store instruction pair is
accompanied by a reservation of the data, the goal being to achieve an atomic operation. If a bus master
other than the one holding the reservation accesses the data (or some other specific condition occurs as
described in Section 11.6.1, “Reservation Protocol”) the reservation is lost and is indicated accordingly.
The RCPU storage reservation protocol supports a multi-level bus structure. For each local bus, storage
reservation is handled by the local reservation logic. The protocol tries to optimize reservation cancellation
such that an MPC500 processor (RCPU) is notified of storage reservation loss on a remote bus (U-bus,
IMB or external bus) only when it has issued a stwcx cycle to that address. That is, the reservation loss
indication comes as part of the stwcx cycle.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-7
L-Bus to U-Bus Interface (L2U)
11.6.1
Reservation Protocol
The reservation protocol operates under the following assumptions:
• Each processor has at most 1 reservation flag
• A lwarx instruction sets the reservation flag
• Another lwarx instruction by same processor clears the reservation flag related to a previous lwarx
instruction and sets again the reservation flag
• A stwcx instruction by the same processor clears the reservation flag
• A store instruction by the same processor does not clear the reservation flag
• Some other processor (or other mechanism) store to an address with an existing reservation clears
the reservation flag
• In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage
11.6.2
L2U Reservation Support
The L2U is responsible for handling the effects of reservations on the L-bus and the U-bus. For the L-bus
and the U-bus, the L2U detects reservation losses.
The reservation logic in the L2U performs the following functions:
• Snoops accesses to all L-bus and U-bus slaves
• Holds one reservation (address) for the core
• Sets the reservation flag when the RPCU issues a load-with-reservation request
The unit for reservation is one word. A byte or half-word store request by another master will clear the
reservation flag.
A load-with-reservation request by the RPCU updates the reservation address related to a previous
load-with-reservation request and sets the reservation flag for the new location. A store-with-reservation
request by the RPCU clears the reservation flag. A store request by the RPCU does not clear the flag. A
store request by some other master to the reservation address clears the reservation flag.
If the storage reservation is lost, it is guaranteed that a store-with-reservation request by the RPCU will not
modify the storage.
The L2U does not start a store-with-reservation cycle on the U-bus if the reserved location on the U-bus
has been touched by another master. The L2U drives the reservation status back to the core.
When the reserved location in the CALRAM on the L-bus is touched by an alternate master, on the
following clock the L2U indicates to the RPCU that the reservation has been touched. On assertion of the
cancel-reservation signal, the RCPU clears the internal reservation bit. If an stwcx cycle has been issued
at the same time, the RCPU aborts the cycle. Software must check the CR0[EQ] bit to determine if the
stwcx instruction completed successfully.
Storage reservation is set regardless of the termination status (address or data phase) of the lwarx access.
Storage reservation is cleared regardless of the data phase termination status of the stwcx access if the
address phase is terminated normally.
MPC561/MPC563 Reference Manual, Rev. 1.2
11-8
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
Storage reservation will be cleared regardless of the data phase termination status of the write requests by
another master to the reserved address if the address phase of the write access is terminated normally on
the destination (U-bus/L-bus) bus.
If the programmable memory map of the part is modified between a lwarx and a stwcx instruction, the
reservation is not guaranteed.
11.6.3
Reserved Location (Bus) and Possible Actions
Once the RPCU core reserves a memory location, the L2U module is responsible for snooping the L-bus
and U-bus for possible intrusion of the reserved location. Under certain circumstances, the L2U depends
on the USIU or the UIMB to provide status of reservation on external bus and the IMB3 respectively.
Table 11-2 lists all reservation protocol cases supported by the L2U snooping logic.
Table 11-2. Reservation Snoop Support
Reserved Location On
Intruding Alternate Master
L-bus
L-master
Request to cancel the reservation.1
U-master
Request to cancel the reservation.
L-master
Block stwcx2
U-master
Block stwcx
L-master
Block stwcx
U-master
Block stwcx
U-bus
External Bus
Ext-master
IMB3
Action Taken on stwcx cycle
Transfer Status3
L-master
Block stwcx
U-master
Block stwcx
IMB3-master
Transfer Status
1
If the RCPU tries to modify (stwcx) that location, the L2U does not have enough time to stop the write access
from completing. In this case, the L2U will drive cancel-reservation signal back to the core as soon as it
comes to know that the alternate master on the U-bus has touched the reserved location.
2 If the RCPU tries to modify (stwcx) that location, the L2U does not start the cycle on the U-bus and it
communicates to the core that the current write has been aborted by the slave with no side effects.
3 If the RCPU tries to modify (stwcx) that location, the L2U runs a write-cycle-with-reservation request on the
U-bus. The L2U samples the status of the reservation along with the U-bus cycle termination signals and it
communicates to the core if the current write has been aborted by the slave with no side effects.
11.7
L-Bus Show Cycle Support
The L2U module provides support for L-bus show cycles. L-bus show cycles are external visibility cycles
that reflect activity on the L-bus that would otherwise not be visible to the external bus. L-bus show cycles
are software controlled.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-9
L-Bus to U-Bus Interface (L2U)
11.7.1
Programming Show Cycles
L-bus show cycles are disabled during reset and must be configured by setting the LSHOW[0:1] bits in the
L2U_MCR. Table 11-3 shows the configurations of the LSHOW[0:1] bits.
Table 11-3. L2U_MCR LSHOW Modes
11.7.2
LSHOW
Action
00
Disable L-bus show cycles
01
Show address and data of all L-bus space write cycles
10
Reserved (Disable L-bus show cycles)
11
Show address and data of all L-bus space read and write cycles
Performance Impact
When show cycles are enabled in the L2U module, there is a performance penalty on the L-bus. This
occurs because the L2U module does not support more than one access being processed at any time. To
ensure that only one access at a time is processed, and not lose an L-bus access that would have been show
cycled, the L2U module will arbitrate for the L-bus whenever it is processing any access. This L-bus
arbitration will prevent any other L-bus master from starting a cycle that might turn out to be a qualifiable
L-bus show cycle.
For L-bus show cycles, the minimum performance impact on the L-bus will be three clocks. This minimum
impact assumes that the L-bus slave access is a 1-clock access, and the L2U module acquires immediate
bus grant on the U-bus. The L2U has to wait two clocks before completing the show cycle on the U-Bus,
thus using up five clocks for the complete process.
A retried access on the L-bus (no address acknowledge) that qualifies to be show cycled, will be accepted
when it is actually acknowledged. This will cause a 1-clock delay before an L-bus master can retry the
access on the L-bus, because the L2U module will release L-bus one clock later.
L2U asserts the internal bus request signal on the U-bus for a minimum of two clocks when starting a show
cycle on the U-bus.
11.7.3
Show Cycle Protocol
The L2U module behaves as both a master and a slave on the U-bus during show cycles. The L2U starts
the U-bus transfer as a bus master and then completes the address phase and data phase of the cycle as a
slave. The L2U follows U-bus protocol of in-order termination of the data phase.
The USIU can control the start of show cycles on the U-bus by asserting the no-show cycle indicator. This
will cause the L2U module to release the U-bus for at least one clock before retrying the show cycle.
11.7.4
L-Bus Write Show Cycle Flow
The L2U performs the following sequence of actions for an L-bus-write show cycle.
1. Arbitrates for the L-bus to prevent any other L-bus cycles from starting
MPC561/MPC563 Reference Manual, Rev. 1.2
11-10
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
2. Latches the address and the data of the L-bus access, along with all address attributes
3. Waits for the termination of the L-bus access and latches the termination status (data error)
4. Arbitrate for the U-bus, and when granted, starts the U-bus access, asserting show cycle request on
the U-bus, along with address, attributes and the write data. The L2U module provides address
recognition and acknowledgment for the address phase. If the no-show cycle indicator from the
U-bus is asserted, the L2U does not start the show cycle. The L2U module releases the U-bus until
the no-show cycle indicator is negated and then arbitrates for the U-bus again.
5. When the L2U module has U-bus data bus grant, it drives the data phase termination handshakes
on the U-bus.
6. Releases the L-bus
11.7.5
L-Bus Read Show Cycle Flow
The L2U performs the following sequence of actions for an L-bus read show cycle.
1. Arbitrates for the L-bus to prevent any other L-bus cycle from starting
2. Latches the address of the L-bus access, along with all address attributes
3. Waits for the data phase termination on the L-bus and latches the read data, and the termination
status from the L-bus
4. Arbitrates for the U-bus, and when granted, starts the U-bus access, asserting the show cycle
request on the U-bus, along with address attributes. The L2U module provides address
recognition/acknowledgment for the address phase. If the no-show cycle indicator from the U-bus
is asserted, the L2U does not start the show cycle. The L2U module releases the U-bus until the
no-show cycle indicator is negated and then arbitrates for the U-bus again.
5. When the L2U module has U-bus data bus grant, it drives the read data and the data phase
termination handshakes on the U-bus
6. Release the L-bus.
11.7.6
Show Cycle Support Guidelines
The following are the guidelines for L2U show cycle support:
• The L2U module provides address and data for all qualifying L-bus cycles when the appropriate
mode bits are set in the L2U_MCR.
• The L2U-module-only provides show cycles L-bus activity that is not targeted for the U-bus or the
L2U module internal registers, regardless of the termination status of such activity.
• The L2U module does not provide show cycle access to any MPC500 special purpose register.
• The L2U does not start a show cycle for an L-bus access that is retried. This decision to not start
the show cycle causes a clock delay before the cycle can be retried, since the L2U module will have
arbitrated away the L-bus immediately on detecting the show cycle, before the retry information is
available.
• The L2U module does not show cycle any L-bus activity that is aborted.
• The L2U module does not access the U-bus if the USIU inhibits show cycle activity on the U-bus.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-11
L-Bus to U-Bus Interface (L2U)
•
The L2U does not provide show cycle for any L-bus addresses that fall in the L-bus CALRAM
address space if the CALRAM protection [SP] bit is set in the L2U_MCR.
Table 11-4 summarizes the L2U show cycle support.
Table 11-4. L2U Show Cycle Support Chart
Case
Destination
1
L-bus Slave
2
L2U 4
3
1
U-bus/E-bus
4
L-bus
LB ABORT
2
Comments
No
X
Not show cycled
[Cycle will be retried one clock later]3
X
X
Not show cycled
X
X
Not show cycled
1
Yes
No
Show cycled
slave1
Yes
Yes
Not show cycled
[L-bus will be released next clock]
L-bus slave
5
5
LB AACK
1
L-bus slave includes all address in the L-bus address space.
X indicates don’t care conditions.
3 There will be a 1-clock turnaround because the L-bus retry information is not available in time to
negate the L-bus arbitration.
4
L2U indicates L2U registers.
5 U-bus/E-bus refers to all destinations through the L2U interface.
2
11.8
L2U Programming Model
The L2U control registers control the L2U bus interface and the DMPU. They are accessible via the mtspr
and mfspr instructions. They are also accessible by an external master when EMCR[CONT] bit is cleared.
L2U control registers are accessible from both the L-bus side and the U-bus side in one clock cycle. As
with all SPRs, L2U registers are accessible in supervisor mode only.
Any unimplemented bits in L2U registers return 0’s on a read, and the writes to those register bits are
ignored.
Table 11-5 shows L2U registers along with their SPR numbers and hexadecimal addresses that are used to
access L2U registers during a peripheral mode access.
.
Table 11-5. L2U (PPC) Register Decode
Name
SPR #
SPR[5:9]
SPR[0:4]
Address for
External Master
Access1
Access
Description
L2U_MCR
568
10001
11000
0x0000_3110
SUPR
L2U Module Configuration Register
L2U_RBA0
792
11000
11000
0x0000_3180
SUPR
Region Base Address Register 0
L2U_RBA1
793
11000
11001
0x0000_3380
SUPR
Region Base Address Register 1
L2U_RBA2
794
11000
11010
0x0000_3580
SUPR
Region Base Address Register 2
L2U_RBA3
795
11000
11011
0x0000_3780
SUPR
Region Base Address Register 3
L2U_RA0
824
11001
11000
0x0000_3190
SUPR
Region Attribute Register 0
L2U_RA1
825
11001
11001
0x0000_3390
SUPR
Region Attribute Register 1
MPC561/MPC563 Reference Manual, Rev. 1.2
11-12
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
Table 11-5. L2U (PPC) Register Decode (continued)
1
Name
SPR #
SPR[5:9]
SPR[0:4]
Address for
External Master
Access1
Access
Description
L2U_RA2
826
11001
11010
0x0000_3590
SUPR
Region Attribute Register 2
L2U_RA3
827
11001
11011
0x0000_3790
SUPR
Region Attribute Register 3
L2U_GRA
536
10000
11000
0x0000_3100
SUPR
Global Region Attribute
When EMCR[CONT] = 0, for external master access only.
For these registers a bus cycle will be performed on the L-bus and the U-bus with the address as shown in
Table 11-6.
.
11.8.1
Table 11-6. Hex Address For SPR Cycles
A[0:17]
A[18:22]
A[23:27]
A[28:31]
0
spr[5:9]
spr[0:4]
0
U-Bus Access
The L2U registers are accessible from the U-bus side only if it is a supervisor mode data access and the
register address is correct and it is indicated on the U-bus that it is a PPC register access.
A user mode access, or an access marked as instruction, to L2U registers from the U-bus side will cause a
data error on the U-bus.
11.8.2
Transaction Size
All L2U registers are defined by MPC500 architecture as being 32-bit registers in normal mode. There is
no MPC500 instruction to access either a half word or a byte of the special purpose register.
All L2U registers are only word accessible (read and write) in peripheral mode. A half-word or byte access
in peripheral mode will result in a word transaction.
11.8.3
L2U Module Configuration Register (L2U_MCR)
The L2U module configuration register (L2U_MCR) is used to control the L2U module operation.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-13
L-Bus to U-Bus Interface (L2U)
MSB
0
Field
1
SP
2
3
4
5
6
7
8
9
LSHOW
10
11
12
13
14
26
27
28
29
30
15
—
Reset
0000_0000_0000_0000
LSB
16
17
18
19
20
21
22
23
24
25
Field
—
Reset
0000_0000_0000_0000
Addr
SPR 568
31
Figure 11-4. L2U Module Configuration Register (L2U_MCR)
Table 11-7. L2U_MCR Bit Descriptions
Bits
Name
Description
0
SP
CALRAM Protection (SP) bit is used to protect the CALRAM on the L-bus from U-bus accesses.
Any attempt to set or clear the SP bit from the U-bus side has no affect.
Once this bit is set, the L2U blocks all CALRAM accesses initiated by the U-bus masters and the
access is terminated with a data error on the U-bus.
If L-bus show cycles are enabled, setting this bit will disable L-bus CALRAM show cycles.
1:2
LSHOW
LSHOW bits are used to configure the show cycle mode for cycles accessing the L-bus slave e.g.
CALRAM
00 Disable show cycles
01 Show address and data of all L-bus space write cycles
10 Reserved
11 Show address and data of all L-bus space read and write cycles
3:31
—
11.8.4
Reserved
Region Base Address Registers (L2U_RBAx)
The L2U region base address register (L2U_RBAx) defines the base address of a specific region protected
by the data memory protection unit. There are four registers (x = 0...3), one for each supported region.
MSB
0
1
2
3
4
5
6
7
8
Field
RBA
Reset
Undefined
9
10
11
12
13
14
25
26
27
28
29
30
15
LSB
16
17
18
19
20
21
22
23
24
Field
RBA
—
Reset
Undefined
0000_0000_0000
Addr
31
SPR 792–795
Figure 11-5. L2U Region x Base Address Register (L2U_RBAx)
MPC561/MPC563 Reference Manual, Rev. 1.2
11-14
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
Table 11-8. L2U_RBAx Bit Descriptions
Bits
Name
Description
0:19
RBA
Region base address. The RBA field provides the base address of the region. The region base
address should start on the block boundary for the corresponding block size attribute specified
in the region attribute register (L2U_RAx).
20:31
—
11.8.5
Reserved
Region Attribute Registers (L2U_RAx)
Each L2U region attribute register defines the protection attributes associated with a specific region
protected by the data memory protection unit. There are four registers (x = 0...3), one for each supported
region.
MSB
0
1
2
3
Field
4
5
6
7
8
9
10
11
—
12
13
14
28
29
30
15
RS
Reset
0000_0000_0000_0000
LSB
16
17
Field
18
RS
19
20
21
22
PP
23
24
—
25
26
27
G
Reset
0000_0000_0000_0000
Addr
SPR 824–827
31
—
Figure 11-6. L2U Region X Attribute Register (L2U_RAx)
Table 11-9. L2U_RAx Bit Descriptions
Bits
Name
Description
0:7
—
Reserved
8:19
RS
Region size
0000_0000_0000 = 4 Kbytes
0000_0000_0001 = 8 Kbytes
0000_0000_0011 = 16 Kbytes
0000_0000_0111 = 32 Kbytes
0000_0000_1111 = 64 Kbytes
0000_0001_1111 = 128 Kbytes
0000_0011_1111 = 256 Kbytes
0000_0111_1111 = 512 Kbytes
0000_1111_1111 = 1 Mbyte
0001_1111_1111 = 2 Mbytes
0011_1111_1111 = 4 Mbytes
0111_1111_1111 = 8 Mbytes
1111_1111_1111 = 16 Mbytes
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-15
L-Bus to U-Bus Interface (L2U)
Table 11-9. L2U_RAx Bit Descriptions (continued)
Bits
Name
20:21
PP
Protection bits
00 No supervisor access, no user access
01 Supervisor read/write access, no user access
10 Supervisor read/write access, user read-only access
11 Supervisor read/write access, user read/write access
22:24
—
Reserved
25
G
Guarded attribute
0 Not guarded from speculative accesses
1 Guarded from speculative accesses
26:31
—
Reserved
11.8.6
Description
Global Region Attribute Register (L2U_GRA)
The L2U global region attribute register (L2U_GRA) defines the protection attributes associated with the
memory region which is not protected under the four DMPU regions. This register also provides
enable/disable control for the four DMPU regions.
MSB
0
1
2
3
4
5
6
7
8
9
Field ENR0 ENR1 ENR2 ENR3
10
11
12
13
14
26
27
28
29
30
15
—
Reset
0000_0000_0000_0000
LSB
16
Field
17
18
—
19
20
21
PP
22
23
24
—
25
G
Reset
0000_0000_0000_0000
Addr
SPR 536
31
—
Figure 11-7. L2U Global Region Attribute Register (L2U_GRA)
Table 11-10. L2U_GRA Bit Descriptions
Bits
Name
Description
0
ENR0
Enable attribute for region 0
0 Region attribute is off
1 Region attribute is on
1
ENR1
Enable attribute for region 1
0 Region attribute is off
1 Region attribute is on
2
ENR2
Enable attribute for region 2
0 Region attribute is off
1 Region attribute is on
MPC561/MPC563 Reference Manual, Rev. 1.2
11-16
Freescale Semiconductor
L-Bus to U-Bus Interface (L2U)
Table 11-10. L2U_GRA Bit Descriptions (continued)
Bits
Name
Description
3
ENR3
4:19
—
Reserved
20:21
PP
Protection bits
00 No supervisor access, no user access
01 Supervisor read/write access, no user access
10 Supervisor read/write access, user read-only access
11 Supervisor read/write access, user read/write access
22:24
—
Reserved
25
G
Guarded attribute
0 Not guarded from speculative accesses
1 Guarded from speculative accesses
26:31
—
Reserved
Enable attribute for region 3
0 Region attribute is off
1 Region attribute is on
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
11-17
L-Bus to U-Bus Interface (L2U)
MPC561/MPC563 Reference Manual, Rev. 1.2
11-18
Freescale Semiconductor
Chapter 12
U-Bus to IMB3 Bus Interface (UIMB)
The U-bus to IMB3 bus interface (UIMB) structure is used to connect the CPU internal unified bus (U-bus)
to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3. The
UIMB interface (see Figure 12-1) consists of seven submodules that control bus interface timing, address
decode, data multiplexing, intrasystem communication (interrupts), and clock generation to allow
communication between U-bus and the IMB3. The seven submodules are:
• U-bus interface
• IMB3 interface
• Address decoder
• Data multiplexer
• Interrupt synchronizer
• Clock control
• Scan control
12.1
•
•
•
•
•
Features
Provides complete interfacing between the U-bus and the IMB3:
— 15 bits (32 Kbytes) of address decode on IMB3
— 32-bit data bus
— Read/write access to IMB3 module registers
— Interrupt synchronizer
— Monitoring of accesses to unimplemented addresses within UIMB interface address range
— Burst-inhibited accesses to the modules on IMB3
Support of 32-bit and 16-bit bus interface units (BIUs) for IMB3 modules
Half and full speed operation of IMB3 bus with respect to U-bus
Simple “slave only” U-bus interface implementation
— Transparent mode operation not supported
— Relinquish and retry not supported
Supports scan control for modules on the IMB3 and on the U-bus
NOTE
Modules on the IMB3 bus can only be reset by SRESET. Some modules
may have a module reset, as well.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-1
U-Bus to IMB3 Bus Interface (UIMB)
WARNING
The user should not perform instruction fetches from modules on the IMB3.
12.2
UIMB Block Diagram
U-bus
Interface
U-bus
Address
Decode
IMB3
Interface
IMB3
Data
Mux
Scan Control
Interrupt
Synchronizer
Clock Control
Figure 12-1. UIMB Interface Module Block Diagram
12.3
Clock Module
The clock module within the UIMB interface generates the IMB3 clock. The IMB3 clock is the main
timing reference used within the IMB3 modules.
The IMB3 clock is generated based on the STOP and HSPEED bits in the UIMB module configuration
register (UMCR). If the STOP = 1, the IMB3 clock is not generated. If the STOP = 0 and the HSPEED =
0, the IMB3 clock is generated as the inversion of the internal system clock. This is the same frequency as
the CLKOUT if SCCR[EBDF] = 0b00 – full speed external bus. (See Figure 12-2.) If the HSPEED = 1,
then the IMB3 clock is one-half of the internal system frequency. (See Figure 12-3.)
Table 12-1. STOP and HSPEED Bit Functionality
STOP
HSPEED
Functionality
0
0
IMB3 bus frequency is the same as U-bus frequency.
0
1
IMB3 bus frequency is half that of the U-bus frequency.
1
X
IMB3 clock is not generated.
MPC561/MPC563 Reference Manual, Rev. 1.2
12-2
Freescale Semiconductor
U-Bus to IMB3 Bus Interface (UIMB)
CLKOUT
IMB3 Clock
Figure 12-2. IMB3 Clock – Full-Speed IMB3 Bus
CLKOUT
IMB3 Clock
Figure 12-3. IMB3 Clock – Half-Speed IMB3 Bus
Table 12-2 shows the number of system clock cycles that the UIMB requires to perform each type of bus
cycle. It is assumed that the IMB3 is available to the UIMB at all times (fastest possible case).
Table 12-2. Bus Cycles and System Clock Cycles
Bus Cycle (from U-bus Transfer Start
to U-bus Transfer Acknowledge)
Number of System Clock Cycles
Full Speed
Half Speed
Normal write
4
6
Normal read
4
6
Dynamically-sized write
6
10
Dynamically-sized read
6
10
NOTE
The UIMB interface dynamically interprets the port size of the addressed
module during each bus cycle, allowing bus transfers to and from 16-bit and
32-bit IMB3 modules. During a bus transaction, the slave module on the
IMB3 signals its port size (16- or 32-bit) via an internal port size signal.
12.4
Interrupt Operation
The interrupts from the modules on the IMB3 are propagated to the interrupt controller in the USIU
through the UIMB interface. The UIMB interrupt synchronizer latches the interrupts from the modules on
the IMB3 and drives them onto the U-bus, where they are latched by the USIU interrupt controller.
12.4.1
Interrupt Sources and Levels on IMB3
The IMB3 has eight interrupt lines. There can be a maximum of 32 levels of interrupts from the modules
on IMB3 bus. A single module can be a source for more than one interrupt. For example, the QSMCM can
generate two interrupts (one for QSCI1/QSCI2 and another for QSPI). In this case, the QSMCM has two
interrupt sources. Each of these two sources can assert the interrupt on any of the 32 levels.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-3
U-Bus to IMB3 Bus Interface (UIMB)
It is possible for multiple interrupt sources to assert the same interrupt level. To reduce the latency, it is a
good practice for each interrupt source to assert an interrupt on a level on which no other interrupt source
is mapped.
12.4.2
IMB3 Interrupt Multiplexing
The IMB3 has 10 lines for interrupt support. Eight lines are for interrupts and two are for interrupt level
byte select (ILBS). These lines will transfer the 32 interrupt levels to the interrupt synchronizer. A diagram
of the interrupt flow is shown in Figure 12-4.
UIPEND
Register
IMB3 Interrupt
U-bus Interrupt
Level[0:7]
8
[0:7]
8
[8:15]
Byte Count
Byte-enable
to IMB3
Block
Byte-enables
4
[16:23]
U-bus
Data[0:31]
[24:31]
2
Figure 12-4. Interrupt Synchronizer Signal Flow
Latching 32 interrupt levels using eight IMB3 interrupt lines is accomplished with a 4:1 time-multiplexing
scheme. The UIMB drives two signals (ILBS[0:1]) with a multiplexer select code that tells all interrupting
modules on the IMB3 about which group of signals to drive during the next clock. See Figure 12-5.
12.4.3
ILBS Sequencing
The IMB3 interface drives the ILBS signals continuously, incrementing through a code sequence (0b00,
0b01, 0b10, 0b11) once every clock. The UMCR[IRQMUX] bits in the IMB3 module configuration
register select which type of multiplexing the interrupt synchronizer will perform. The IRQMUX field can
select time-multiplexing protocols for 8, 16, 24 or 32 interrupt sources. These protocols would take one,
two, three or four clocks, respectively.
Table 12-4 shows ILBS sequencing. Programming IRQMUX[0:1] to 0b00 disables time multiplexing. In
this case the ILBS lines remain at 0b00 at all times. In this mode, no interrupts from IMB3 modules which
assert on levels 8 through 31 are ever latched by the interrupt synchronizer. SRESET will not clear the
IRQMUX bits, so time multiplexing will be enabled with the previous setup after SRESET is released.
The timing for the scheme and the values of ILBS and the interrupt levels driven onto the IMB3 IRQ lines
are shown in Figure 12-5. This scheme causes a maximum latency of four clocks and an average latency
of two clocks before the interrupt request can reach the interrupt synchronizer.
MPC561/MPC563 Reference Manual, Rev. 1.2
12-4
Freescale Semiconductor
U-Bus to IMB3 Bus Interface (UIMB)
IMB3 CLOCK
ILBS [0:1]
00
IMB3 LVL[0:7]
01
10
11
00
01
LVL
[0:7]
LVL
[8:15]
LVL
16:23
LVL
24:31
LVL
0:7
10
11
Note: This diagram represents the ILBS behavior when IRQMUX[0:1] = 11
Figure 12-5. Time-Multiplexing Protocol for IRQ Signals
Table 12-3. ILBS Signal Functionality
ILBS[0:1]
Description
00
IMB3 interrupt sources mapped onto 0:7 levels will
drive interrupts onto IMB3 LVL[0:7]
01
IMB3 interrupt sources mapped onto 8:15 levels will
drive interrupts onto IMB3 LVL[0:7]
10
IMB3 interrupt sources mapped onto 16:23 levels will
drive interrupts onto IMB3 LVL[0:7]
11
IMB3 interrupt sources mapped onto 24:31 levels will
drive interrupts onto IMB3 LVL[0:7]
The IRQMUX bits determine how many levels of IMB3 interrupts are sampled. Refer to Table 12-4.
Table 12-4. IRQMUX Functionality
IRQMUX[0:1]
12.4.4
ILBS sequence
Description
00
00, 00, 00.....
Latch 0:7 IMB3 interrupt levels
01
00, 01, 00, 01....
Latch 0:15 IMB3 interrupt levels
10
00, 01, 10, 00, 01, 10,.....
Latch 0:23 IMB3 interrupt levels
11
00, 01, 10, 11, 00, 01, 10, 11,....
Latch 0:31 IMB3 interrupt levels
Interrupt Synchronizer
The interrupt synchronizer latches the 32 levels of interrupts from the IMB3 bus into a register which can
be read by the CPU or other U-bus master. Since there are only eight lines for interrupts on the IMB3 and
32 levels of interrupts are possible, the 32 interrupt levels are multiplexed onto eight IMB3 interrupt lines.
Apart from latching these interrupts in the register (UIPEND), the interrupt synchronizer drives the
interrupts onto the U-bus, where they are latched by the interrupt controller in the USIU.
If IMB3 modules drive interrupts on any of the 24 levels (levels eight through 31), they will be latched in
UIPEND in the UIMB. If any of the register bits 7 to 31 are set, then bit 7 will be set as well.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-5
U-Bus to IMB3 Bus Interface (UIMB)
NOTE
Software must poll this register to find out which of the levels 7 to 31 are
asserted.
The UIPEND register contains a status bit for each of the 32 interrupt levels. Each bit of the register is a
read-only status bit, reflecting the current state of the corresponding interrupt signal. For each of the 32
interrupt levels, a corresponding bit of the UIPEND register is set.
Figure 12-4 shows how the eight interrupt lines are connected to the UIPEND register to represent 32
levels of interrupts. Figure 12-6 shows the implementation of the interrupt synchronizer.
UIPEND
Register
U-bus Interrupt Level[0:7]
LVL[0:7]
8
7
LVL7
IMB3 LVL [0:7]
OR
LVL [8:31]
24
RESET
State
Machine
32
IMBCLOCK
ILBS [0:1]
U-bus
Data[0:31]
4
Figure 12-6. Interrupt Synchronizer Block Diagram
12.5
Programming Model
Table 12-5 lists the registers used for configuring and testing the UIMB module. The address offset shown
in this table is from the start of the block reserved for UIMB registers. As shown in Figure 1-2, this block
begins at offset 0x30 7F80 from the start of the MPC561/MPC563 internal memory map (the last 128-byte
sub-block of the UIMB interface memory map).
Table 12-5. UIMB Interface Register Map
Access1
Base Address
S
0x30 7F80
—
Register
UIMB Module Configuration Register (UMCR)
See Table 12-6 for bit descriptions.
0x30 7F84 — 0x30 7F8F Reserved
MPC561/MPC563 Reference Manual, Rev. 1.2
12-6
Freescale Semiconductor
U-Bus to IMB3 Bus Interface (UIMB)
Table 12-5. UIMB Interface Register Map (continued)
Access1
Base Address
S/T
0x30 7F90
—
UIMB Test Control Register (UTSTCREG)
Reserved
0x30 7F94 — 0x30 7F9F Reserved
S
1
Register
0x30 7FA0
Pending Interrupt Request Register (UIPEND)
See Section 12.5.3, “Pending Interrupt Request Register (UIPEND)” for bit
descriptions.
S = Supervisor mode only; T = Test mode only
Any word, half-word or byte access to a 32-bit location within the UIMB interface register decode block
that is unimplemented (defined as reserved) causes the UIMB interface to assert a data error exception on
the U-bus.The entire 32-bit location must be defined as reserved in order for a data error exception to be
asserted.
Unimplemented bits in a register return zero when read.
12.5.1
UIMB Module Configuration Register (UMCR)
The UIMB module configuration register (UMCR) is accessible in supervisor mode only.
MSB
0
Field STOP
HRESET
1
2
3
4
5
6
7
8
9
10
IRQMUX
HSPEED
—
00
1
0000_0000_0000
0
Addr
11
12
13
14
27
28
29
30
15
0x30 7F80
LSB
16
17
Field
HRESET
18
19
20
21
22
23
24
25
26
31
—
0000_0000_0000_0000
Figure 12-7. UIMB Module Configuration Register (UMCR)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-7
U-Bus to IMB3 Bus Interface (UIMB)
Table 12-6. UMCR Bit Descriptions
Bits
Name
Description
0
STOP
Stop enable.
0 Enable system clock for IMB3 bus
1 Disable IMB3 system clock
To avoid complications at restart and data corruption, system software must stop each slave on
the IMB3 before setting the STOP bit. Software must also ensure that all IMB3 interrupts have
been serviced before setting this bit.
1:2
IRQMUX
Interrupt request multiplexing. These bits control the multiplexing of the 32 possible interrupt
requests onto the eight IMB3 interrupt request lines.
00 Disables the multiplexing scheme on the interrupt controller within this interface. What this
means is that the IMB3 IRQ [0:7] signals are non-multiplexed, only providing 8 [0:7] interrupt
request lines to the interrupt controller
01 Enables the IMB3 IRQ control logic to perform a 2-to-1 multiplexing to allow transferring of 16
[0:15] interrupt sources
10 Enables the IMB3 IRQ control logic to perform a 3-to-1 multiplexing to allow transferring of 24
[0:23]interrupt sources
11 Enables the IMB3 IRQ control logic to perform a 4-to-1 multiplexing to allow transferring of 32
[0:31] interrupt sources
3
HSPEED
Half speed. The HSPEED bit controls the frequency at which the IMB3 runs with respect to the
U-bus. This is a modify-once bit. Software can write the reset value of this bit any number of
times. However, once logic 0 is written to this location, any attempt to rewrite this bit to a logic 1
will have no effect.
0 IMB3 frequency is the same as that of the U-bus
1 IMB3 frequency is one half that of the U-bus
4:31
—
12.5.2
Reserved
Test Control Register (UTSTCREG)
The UTSTCREG register is used for factory testing only.
12.5.3
Pending Interrupt Request Register (UIPEND)
The UIPEND register is a read-only status register which reflects the state of the 32 interrupt levels. The
state of IRQ0 is shown in bit 0, the state of IRQ1 is shown in bit 1 and so on. This register is accessible
only in supervisor mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
12-8
Freescale Semiconductor
U-Bus to IMB3 Bus Interface (UIMB)
MSB
0
1
2
3
4
5
6
7
8
9
Field LVL0 LVL1 LVL2 LVL3 LVL4 LVL5 LVL6 LVL7 LVL8 LVL9
10
11
12
13
14
15
LVL
10
LVL
11
LVL
12
LVL
13
LVL
14
LVL
15
0000_0000_0000_0000
HRESET
Addr
0x30 7FA0
LSB
16
Field LVL
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LVL
17
LVL
18
LVL
19
LVL
20
LVL
21
LVL
22
LVL
23
LVL
24
LVL
25
LVL
26
LVL
27
LVL
28
LVL
29
LVL
30
LVL
31
0000_0000_0000_0000
HRESET
Figure 12-8. Pending Interrupt Request Register (UIPEND)
Table 12-7. UIPEND Bit Descriptions
Bits
Name
Description
0:31
LVLx
Pending interrupt request level. Accessible only in supervisor mode. LVLx identifies the interrupt
source as UIMB LVLx, where x is the interrupt number.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
12-9
U-Bus to IMB3 Bus Interface (UIMB)
MPC561/MPC563 Reference Manual, Rev. 1.2
12-10
Freescale Semiconductor
Chapter 13
QADC64E Legacy Mode Operation
The two queued analog-to-digital converter (QADC) modules on MPC561/MPC563 devices are 10-bit,
unipolar, successive approximation converters. The modules can be configured to operate in one of two
modes, legacy mode (MPC555 compatible) and enhanced mode. This chapter describes how the modules
operate in legacy mode, which is the default mode of operation. Refer to Chapter 14, “QADC64E
Enhanced Mode Operation,” for information regarding the QADC64E functionality in enhanced mode.
For this revision of the QADC, the name QADC64E implies the enhanced version of the QADC module,
not just enhanced mode of operation. For simplicity, the names QADC and QADC64E may be used
interchangeably throughout this document.
13.1
QADC64E Block Diagram
Figure 13-1 displays the major components of the QADC64E modules on the MPC561/MPC563.
EXTERNAL
Triggers
EXTERNAL
MUX Address
Up to 16 ANALOG
Input Signals
REFERENCE ANALOG POWER
Inputs
Inputs
ANALOG Input Multiplexor and
DIGITAL Signal Functions
DIGITAL
CONTROL
10-bit ANALOG to DIGITAL CONVERTER
Queues OF 10-BIT Conversion
Command Words (CCW), 64 Entries
BUS INTERFACE UNIT
(BIU)
10-bit RESULT Table,
64 Entries
10-bit to 16-bit
RESULT Alignment
IMB3
Figure 13-1. QADC64E Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-1
QADC64E Legacy Mode Operation
13.2
Key Features and Quick Reference Diagrams
This section gives an overview of the implementation of the two QADC64E modules on
MPC561/MPC563. It can also be used as a quick reference guide while programming the modules.
13.2.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features of the QADC64E Legacy Mode Operation
Internal sample and hold
Directly supports up to four external multiplexers (for example the MC14051)
Up to 41 analog input channels using QADC64E external multiplexing
Programmable input sample time for various source impedances
Minimum conversion time of 7 µs (with typical QCLK frequency, 2 MHz)
Two conversion command queues with a total of 64 entries
Sub-queues possible using pause mechanism
Queue complete and pause software interrupts available on both queues
Queue pointers indicate current location for each queue
Automated queue modes initiated by
— External edge trigger
— Periodic/Interval timer, within QADC64E module
— Software command
— External gated trigger (Queue 1 only)
Single-scan or continuous-scan of queues
64 result registers in each QADC64E module
Output readable in three formats
— Right-justified unsigned
— Left-justified signed
— Left-justified unsigned
Unused analog channels on Port A can be used as digital input/output signals, unused analog
channels on Port B can be used as digital input signals.
The analog section includes input signals, an analog multiplexer, and the sample and hold circuits. The
analog conversion is performed by the digital-to-analog converter (DAC) resistor-capacitor array and a
high-gain comparator.
The digital control section contains queue control logic to sequence the conversion process and interrupt
generation logic. Also included are the periodic/interval timer, control and status registers, the conversion
command word (CCW) table RAM, and the result table RAM.
The bus interface unit (BIU) allows the QADC64E to operate with the applications software through the
IMB3 environment.
MPC561/MPC563 Reference Manual, Rev. 1.2
13-2
Freescale Semiconductor
QADC64E Legacy Mode Operation
13.2.2
Memory Map
The QADC64E occupies 1 Kbyte, or 512 16-bit entries, of address space. Ten 16-bit registers are control,
port, and status registers, 64 16-bit entries are the CCW table, and 64 16-bit entries are the result table, and
occupy 192 16-bit address locations because the result data is readable in three data alignment formats.
Each QADC64E module on the MPC561/MPC563 has its own memory space. Table 13-1 shows the
memory map for QADC64E module A, it occupies 0x30 4800 to 0x30 4BFF. Table 13-2 displays the
memory map for module B. Module B has the same offset scheme starting at 0x30 4C00. QADC64E B
occupies 0x30 4C00 to 0x30 4FFF.
Z
Address
Table 13-1. QADC64E_A Address Map
MSB
0
0x30 4800
LSB
1
2
3
4
5
STOP FRZ
0x30 4802
TEST MODE
0x30 4804
IRL1
6
7
8
9
LOC
K
FLI
P
SUPV
10
11
12
13
Module
Config.1
Interrupt1
IRL2
PORTQA
0x30 4808
DDRQA
PORTQB
EMU
X
TR
G
0x30 480C
CIE1
PIE
1
SSE
1
MQ1
0x30 480E
CIE2
PIE
2
SSE
2
MQ2
0x30 4810
CF1
PF1
CF2 PF2 TOR
1
TOR
2
0x30 4812
Port Data
Port Direction
0x30 480A
PSH
PSA
RESUM
E
QS
CWPQ1
1
Control 0
BQ2
Control 2
CWP
Status 0
CWPQ2
Status 1
Reserved
0x30
4A000x30 4A7F
0x30 4B80
0x30 4BFF
PSL
Control 1
0x30 48140x30 49FF
0x30
SIGN
4B000x30 4B7F
Register
15
Test1
0x30 4806
0x30
4A800x30 4AFF
14
P
BY
P
0000 00
IST
CHAN
UNSIGNED RIGHT JUSTIFIED
SIGNED LEFT JUSTIFIED
UNSIGNED LEFT JUSTIFIED
CCWs
Results
00 0000
Results
00 0000
Results
Registers are accessible only as supervisor data space
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-3
QADC64E Legacy Mode Operation
Table 13-2. QADC64E_B Address Map
Address
0x30 4C00
MSB
LSB
0
1
STO
P
FRZ
2
3
0x30 4C02
TEST MODE
0x30 4C04
IRL1
4
7
8
9
LOC
K
FLI
P
SUPV
10
11
12
13
0x30 4C08
DDRQA
Interrupt1
TRG
PSH
SSE
1
MQ1
0x30 4C0E CIE2
PIE
2
SSE
2
MQ2
0x30 4C10
PF1
CF2
PF2
TOR
1
PS
A
PSL
Control 0
Control 1
RESUM
E
TOR
2
QS
CWPQ1
0x30 4C12
Port Data
Port Direction
PIE
1
BQ2
Control 2
CWP
Status 0
CWPQ2
Status 1
0x30
4C140x30 4DFF
Reserved
P
0x30
4E000x30 4E7F
0x30
4E800x30 4EFF
BYP
0000 00
0x30 4F00- SIGN
0x30 4F7F
1Registers
Register
15
Module
Config.1
PORTQB
0x30 4C0C CIE1
0x30 4F80
0x30 4FFF
14
IRL2
PORTQA
CF1
6
Test1
0x30 4C06
0x30 4C0A EMU
X
5
IST
CHAN
UNSIGNED RIGHT JUSTIFIED
SIGNED LEFT JUSTIFIED
UNSIGNED LEFT JUSTIFIED
CCWs
Results
00 0000
Results
00 0000
Results
are accessible only as supervisor data space
Accesses to supervisor-only data space is permitted only when the bus master is operating in supervisor
access mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user data space addresses. See Section 13.3.1.4, “Supervisor/Unrestricted Address
Space.”
13.2.3
Legacy and Enhanced Modes of Operation
The QADC64E modules can be configured to operate in legacy or enhanced mode. Legacy mode is the
default state out of reset. Configuring bits in the QADC64E module configuration register enables
MPC561/MPC563 Reference Manual, Rev. 1.2
13-4
Freescale Semiconductor
QADC64E Legacy Mode Operation
enhanced mode. This will be described in Section 13.3.1.3, “Switching Between Legacy and Enhanced
Modes of Operation.”
13.2.4
Using the Queue and Result Word Table
The heart of the QADC is its conversion command word (CCW) queues. This is where the module is
programmed to convert a particular channel according to a particular requirement. The queues are created
by writing CCWs into the CCW table in the register memory. The queues are controlled by the three
control registers, and their status can be read from the two status registers. As conversions are completed
the digital value is written into the result word table. Figure 13-2 shows the CCW queue and the result
word table.
Conversion Command
Word (CCW) Table
00
Result Word Table
A/D Converter
Begin Queue 1
00
Channel Select,
Sample, Hold,
and
Analog to Digital
Conversion
End of Queue 1
Begin Queue 2
BQ2
End of Queue 2
MSB
6
7
8
9 10
P BYP IST
LSB
15
CHAN
P = Pause Until Next Trigger
BYP = Bypass Buffer Amplifier
MSB
0
LSB
15
56
0 0 0 0 0 0
Result
Right Justified, Unsigned Result Format
0 1
9 10
15
IST = Input Sample Time
0 0 0 0 0 0
S
Result
Left Justified, Signed Result Format
CHAN = Channel Number and End_of_Queue Code
0
9 10
15
Result
0 0 0 0 0 0
Left Justified, Unsigned Result Format
10-bit Conversion
Command Word
(CCW) Format
10-bit Result is
Software Readable
in Three Different 16-bit Formats
Figure 13-2. QADC64E Conversion Queue Operation
13.2.5
External Multiplexing
The QADC can use from one to four 8-input external multiplexer chips to expand the number of analog
signals that may be converted. The externally multiplexed channels are automatically selected from the
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-5
QADC64E Legacy Mode Operation
channel field of the conversion command word (CCW) table. External Multiplex mode is software
selectable, by setting the EMUX bit of control register 0, QACR0.
Figure 13-3 shows the maximum configuration of four external multiplexer chips connected to the QADC.
The QADC provides three multiplexer address signals – MA[0], MA[1], MA[2] – to select one of the
multiplexer chips. These outputs are the multiplexer control lines and they are connected to all external
multiplexer chips.
The analog output of each of the four multiplexer chips is connected to four separate QADC inputs – ANw,
ANx, ANy, ANz. These signals are the first four signals of port B and each one can represent eight analog
input channels. The QADC converts the proper input channel (ANw, ANx, ANy, ANz) by interpreting the
channel number in the CCW. Refer to Table 13-3.
AN[1]
AN[3]
AN[5]
AN[7]
AN[9]
AN[11]
AN[13]
AN[15]
MUX
AN[16]
AN[18]
AN[20]
AN[22]
AN[24]
AN[26]
AN[28]
AN[30]
MUX
AN[17]
AN[19]
AN[21]
AN[23]
AN[25]
AN[27]
AN[29]
AN[31]
MUX
V
RH
VRL
AN[0]/ANw/PQB[0]
AN[1]/ANx/PQB[1]
AN[2]/ANy/PQB[2]
AN[3]/ANz/PQB[3]
AN[48]/PQB[4]
AN[49]/PQB[5]
AN[50]/PQB[6]
AN[51]/PQB[7]
AN[52]/MA[0]/PQA[0]
AN[53]/MA[1]/PQA[1]
AN[54]/MA[2]/PQA[2]
AN[55]/PQA[3]
AN[56]/PQA[4]
AN[57]PQA[5]
AN[58]/PQA[6]
AN[59]/PQA[7]
ANALOG POWER
ANALOG REFERENCES
PORT B
MUX
V SSA
V DDA
PORT A
AN[0]
AN[2]
AN[4]
AN[6]
AN[8]
AN[10]
AN[12]
AN[14]
QADC
ANALOG
MULTIPLEXER
AND
PORT LOGIC
ANALOG
CONVERTER
DIGITAL
CONTROL
External Triggers:
ETRIG1
ETRIG2
Figure 13-3. Example of External Multiplexing
In the external multiplexed mode, four of the port B signals are redefined to each represent eight input
channels. Refer to Table 13-3 for more information.
MPC561/MPC563 Reference Manual, Rev. 1.2
13-6
Freescale Semiconductor
QADC64E Legacy Mode Operation
I
Table 13-3. Multiplexed Analog Input Channels
Multiplexed Analog Input
Channels
ANw (AN[0])
0, 2, 4, 6, 8, 10, 12, 14
ANx (AN[1])
1, 3, 5, 7, 9, 11, 13, 15
ANy (AN[2])
16, 18, 20, 22, 24, 26, 28, 30
ANz (AN[3])
17, 19, 21, 23, 25, 27, 29, 31
Table 13-4 shows the total number of analog input channels supported with zero to four external
multiplexer chips using one QADC module.
Table 13-4. Analog Input Channels
Number of Analog Input Channels Available
Directly Connected + External Multiplexed = Total Channels
No External
MUX Chips
One External
MUX Chip
Two External
MUX Chips
Three External
MUX Chips
Four External
MUX Chips
16
20
27
34
41
NOTE: QADC64E External MUX Users
If either QADC64E_A or QADC64E_B is in external multiplexing
(EMUX) mode then the multiplexer address signal channels, AN[52:54]
should not be programmed into queues.
13.3
Programming the QADC64E Registers
The QADC64E has three global registers for configuring module operation:
• Module configuration register (Section 13.3.1, “QADC64E Module Configuration Register
(QADMCR)”)
• Interrupt register (Section 13.3.2, “QADC64E Interrupt Register (QADCINT)”
• Test register (QADCTEST) for factory tests.
The global registers are always defined to be in supervisor-only data space. Refer to Table 13-1 for the
QADC64E_A address map and Table 13-2 for the QADC64E_B address map. See Section 13.3.1.4,
“Supervisor/Unrestricted Address Space” for access modes of these registers.
The remaining five registers in the control register block control the operation of the queuing mechanism,
and provide a means of monitoring the operation of the QADC64E.
• Control register 0 (QACR0) contains hardware configuration information (Section 13.3.5,
“Control Register 0 (QACR0)”)
• Control register 1 (QACR1) is associated with queue 1 (Section 13.3.6, “Control Register 1
(QACR1)”)
• Control register 2 (QACR2) is associated with queue 2 (Section 13.3.7, “Control Register 2
(QACR2)”)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-7
QADC64E Legacy Mode Operation
•
Status registers (QASR0 and QASR1) provide visibility on the status of each queue and the
particular conversion that is in progress (Section 13.3.8, “Status Registers (QASR0 and QASR1)”)
The CCW table follows the register block in the address map. There are 64 table entries to hold the desired
analog conversion sequences. Each CCW table entry is 16-bits, with ten implemented bits in four fields.
The final block of address space belongs to the result word table, which appears in three places in the
memory map. Each result word table location holds one 10-bit conversion value.
13.3.1
QADC64E Module Configuration Register (QADMCR)
The QADCMCR contains five implemented bits that control the operating modes of the QADC64E
module. The configurable modes are freeze, stop and supervisor. The QADCMCR also implements a pair
of bits that together select either legacy or enhanced mode for the QADC module, and lock that operating
mode.
.
MSB
0
LSB
1
2
3
Field STOP FRZ
SRESET
4
—
0000_0000
Addr
5
6
7
8
9
10
11
LOCK FLIP SUPV
1
12
13
14
15
—
000_0000
0x30 4800 (QADCMCR_A); 0x30 4C00 (QADCMCR_B)
Figure 13-4. Module Configuration Register (QADCMCR)
Table 13-5. QADCMCR Bit Descriptions
Bits
Name
0
STOP
1
FRZ
2:5
—
6
LOCK
7
FLIP
Description
Stop Enable. Refer to Section 13.3.1.1, “Low Power Stop Mode,” for more information.
0 = Disable stop mode
1 = Enable stop mode
Freeze Enable. Refer to Section 13.3.1.2, “Freeze Mode,” for more information.
0 = Ignores the IMB3 internal FREEZE signal
1 = Finish any conversion in progress, then freeze
Reserved
Lock/Unlock QADC Mode of operation as defined by FLIP bit. Refer to Section 13.3.1.3,
“Switching Between Legacy and Enhanced Modes of Operation,” for more information.
0 = QADC mode is locked
1 = QADC mode is unlocked and changeable using FLIP bit
QADC Mode of Operation – The FLIP bit allows selection of the mode of operation of the QADC
module, either legacy mode (default) or enhanced mode. This bit can only be written when the
LOCK is set (unlocked). Refer to Section 13.3.1.3, “Switching Between Legacy and Enhanced
Modes of Operation,” for more information.
0 = Legacy mode enabled
1 = Enhanced mode enabled
MPC561/MPC563 Reference Manual, Rev. 1.2
13-8
Freescale Semiconductor
QADC64E Legacy Mode Operation
Table 13-5. QADCMCR Bit Descriptions (continued)
Bits
Name
Description
8
SUPV
Supervisor/Unrestricted Data Space. Refer to Section 13.3.1.4, “Supervisor/Unrestricted
Address Space,” and Table 13-6 for more information.
0 = Only the module configuration register, test register, and interrupt register are designated as
supervisor-only data space. Access to all other locations is unrestricted.
1 = All QADC64E registers and CCW/result tables are designated as supervisor-only data space.
9:15
—
13.3.1.1
Reserved. Write as zeros.
Low Power Stop Mode
When the STOP bit in the QADCMCR is set, the QADC64E clock (QCLK) which clocks the A/D
converter, is disabled and the analog circuitry is powered down. This results in a static, low power
consumption, idle condition. The stop mode aborts any conversion sequence in progress. Because the bias
currents to the analog circuits are turned off in stop mode, the QADC64E requires some recovery time (TSR
in Appendix F, “Electrical Characteristics”) to stabilize the analog circuits after the stop enable bit is
cleared.
In stop mode:
• BIU state machine and logic do not shut down
• The CCW and result is not reset and is not accessible
• The module configuration register (QADCMCR), the interrupt register (QADCINT), and the test
register (QADCTEST) are fully accessible and are not reset
• The data direction register (DDRQA), port data register (PORTQA/PORTQB), and control register
0 (QACR0) are not reset and are read-only accessible
• Control register 1 (QACR1), control register 2 (QACR2), and the status registers (QASR0 and
QASR1) are reset and are read-only accessible
• In addition, the periodic/interval timer is held in reset during stop mode
If the STOP bit is clear, stop mode is disabled.
13.3.1.2
Freeze Mode
Freeze mode occurs when the background debug mode is enabled in the USIU and a breakpoint is
encountered. This is indicated by the assertion of the internal FREEZE line on the IMB3. The FRZ bit in
the QADCMCR determines whether or not the QADC64E responds to an IMB3 internal FREEZE signal
assertion. Freeze is very useful when debugging an application.
When the internal FREEZE signal is asserted and the FRZ bit is set, the QADC64E finishes any conversion
in progress and then freezes.
Depending on when the FREEZE signal is asserted, there are three possible queue "freeze" scenarios:
• When a queue is not executing, the QADC64E freezes immediately
• When a queue is executing, the QADC64E completes the conversion in progress and then freezes
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-9
QADC64E Legacy Mode Operation
•
If, during the execution of the current conversion, the queue operating mode for the active queue
is changed, or a queue 2 abort occurs, the QADC64E freezes immediately
During freeze mode, both the analog clock, QCLK, and periodic/interval timer are held in reset. When the
QADC64E enters the freeze mode while a queue is active, the current CCW location of the queue pointer
is saved.
During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer is held in reset.
External trigger events that occur during the freeze mode are not captured. The BIU remains active to
allow IMB3 access to all QADC64E registers and RAM. Although the QADC64E saves a pointer to the
next CCW in the current queue, the software can force the QADC64E to execute a different CCW by
writing new queue operating modes for normal operation. The QADC64E looks at the queue operating
modes, the current queue pointer, and any pending trigger events to decide which CCW to execute when
exiting freeze.
If the FRZ bit is clear, the internal FREEZE signal is ignored.
13.3.1.3
Switching Between Legacy and Enhanced Modes of Operation
The LOCK and FLIP bits of the QADCMCR register control the operating mode of the QADC64E
modules. Out of reset, the QADC64E modules are in legacy mode (FLIP = 0) and the LOCK bit is clear,
indicating that the module is locked in legacy mode. In order to change the value of the FLIP bit, the
operating mode must first be unlocked, by setting the LOCK bit. Only then can the FLIP bit be changed.
Finally, the LOCK bit must be cleared again to protect the state of the FLIP bit from future writes.
1. Write LOCK = 1 to unlock operating mode bit.
2. Modify the value of FLIP as required.
— FLIP = 0 Legacy mode enabled
— FLIP = 1 Enhanced mode enabled
3. Write LOCK = 0 and new FLIP bit value to preserve the value of FLIP bit
• Example 1 Switching from legacy mode to enhanced mode
— QADCMCR = 0x280; LOCK =1, SUPV = 1
— QADCMCR = 0x380; LOCK =1, write FLIP = 1, SUPV = 1
— QADCMCR = 0x180; LOCK = 0, FLIP = 1, SUPV = 1
Subsequent writes to the FLIP bit will have no effect while LOCK = 0.
• Example 2 Switching from enhanced mode to legacy mode
— QADCMCR = 0x280 or 0x380; LOCK = 1, SUPV =1
(Can write FLIP = x because value will not change)
— QADCMCR = 0x280; LOCK = 1, FLIP = 0, SUPV = 1
— QADCMCR = 0x080; LOCK = 0, FLIP = 0, SUPV =1
13.3.1.4
Supervisor/Unrestricted Address Space
The QADC64E memory map is divided into two segments: supervisor-only data space and assignable data
space. Access to supervisor-only data space is permitted only when the software is operating in supervisor
MPC561/MPC563 Reference Manual, Rev. 1.2
13-10
Freescale Semiconductor
QADC64E Legacy Mode Operation
access mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user data space accesses. The SUPV bit in the QADCMCR designates the assignable
space as supervisor or unrestricted.
The following information applies to accesses to address space located within the module’s 16-bit
boundaries and where the response is a bus error. See Table 13-6 for more information.
• Attempts to read a supervisor-only data space when not in the supervisor access mode and
SUPV = 1, causes the bus master to assert a bus error condition. No data is returned. If SUPV = 0,
the QADC64E asserts a bus error condition and no data is returned.
• Attempts to write to supervisor-only data space when not in the supervisor access mode and
SUPV = 1, causes the bus master to assert a bus error condition. No data is written. If SUPV = 0,
the QADC64E asserts a bus error condition and the register is not written.
• Attempts to read unimplemented data space in the unrestricted access mode and SUPV = 1, causes
the bus master to assert a bus error condition and no data is returned. In all other attempts to read
unimplemented data space, the QADC64E causes a bus error condition and no data is returned.
• Attempts to write unimplemented data space in the unrestricted access mode and SUPV = 1, causes
the bus master to assert a bus error condition and no data is written. In all other attempts to write
unimplemented data space, the QADC64E causes a bus error condition and no data is written.
• Attempts to read assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and no data
is returned.
• Attempts to write assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and the
register is not written.
Table 13-6. QADC64E Bus Error Response
S/U1
Mode
SUPV Bit
Supervisor-Only
Register
Supervisor/
Unrestricted Register
Reserved/
Unimplemented
Register
U
0
QADC64E bus error2
Valid access4
QADC64E bus error2
U
1
Master bus error3
Master bus error3
Master bus error3
S
0
Valid access
Valid access
QADC64E bus error2
S
1
Valid access
Valid access
QADC64E bus error2
1
S/U = Supervisor/Unrestricted
QADC64E bus error = Caused by QADC64E
3 Master bus error = Caused by bus master
4 Access to QADCTEST register will act as a reserved/unimplemented register unless in factory
test mode
2
The bus master indicates the supervisor and user space access with the function code bits (FC[2:0]) on the
IMB3. For privilege violations, refer to the Chapter 9, “External Bus Interface” to determine the
consequence of a bus error cycle termination.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-11
QADC64E Legacy Mode Operation
The supervisor-only data space segment contains the QADC64E global registers, which include the
QADCMCR, the QADCTEST, and the QADCINT. The supervisor/unrestricted space designation for the
CCW table, the result word table, and the remaining QADC64E registers is programmable.
13.3.2
QADC64E Interrupt Register (QADCINT)
QADCINT specifies the priority level of QADC64E interrupt requests. The interrupt level for queue 1 and
queue 2 may be different. The interrupt register is read/write accessible in supervisor data space only. The
implemented interrupt register fields can be read and written, reserved bits read zero and writes have no
effect. They are typically written once when the software initializes the QADC64E, and not changed
afterwards.
MSB
LSB
0
1
Field
2
3
IRL1
4
5
6
7
8
9
10
11
IRL2
SRESET
12
13
14
15
—
0000_0000_0000_0000
Addr
0x30 4804 (QADCINT_A); 0x30 4C04 (QADCINT_B)
Figure 13-5. QADC Interrupt Register (QADCINT)
Table 13-7. QADCINT Bit Descriptions
Bit(s)
Name
Description
0:4
IRL1
Queue 1 Interrupt Request Level. The IRL1 field establishes the queue 1 interrupt request level.
The 00000 state provides a le">